lib/Target/RISCV/RISCVISelDAGToDAG.cpp
bool RISCVDAGToDAGISel::MatchSROIW(SDNode *N) const {
  assert(N->getOpcode() == ISD::OR);
  assert(N->getOperand(0).getOpcode() == ISD::SRL);
  assert(isa<ConstantSDNode>(N->getOperand(1)));
  assert(isa<ConstantSDNode>(N->getOperand(0).getOperand(1)));

  // The IsRV64 predicate is checked after PatFrag predicates so we can get
  // here even on RV32.
  if (!Subtarget->is64Bit())
    return false;

  SDValue Srl = N->getOperand(0);
  uint64_t VC1 = N->getConstantOperandVal(1);
  uint64_t VC2 = Srl.getConstantOperandVal(1);

  // Immediate range should be enforced by uimm5 predicate.
  assert(VC2 < 32 && "Unexpected immediate");
  return VC1 == maskTrailingZeros<uint64_t>(32 - VC2);
}
// Check that it is a SROIW (Shift Right Ones Immediate i32 on RV64). A PatFrag
// has already determined it has the right structure:
//
//  (OR (SRL RS1, VC2), VC1)
//
// and then we check that VC1, the mask used to fill with ones, is compatible
// with VC2, the shamt:
//
//  VC2 < 32
//  VC1 == maskTrailingZeros<uint64_t>(32 - VC2)
//
Check that it is a SROIW (Shift Right Ones Immediate i32 on RV64). A PatFrag
has already determined it has the right structure.



and then we check that VC1, the mask used to fill with ones, is compatible
with VC2, the shamt.


Check that it is a SROIW ( Shift Right Ones Immediate i32 on RV64 ) . A PatFrag has already determined it has the right structure . and then we check that VC1 the mask used to fill with ones is compatible with VC2 the shamt .
bool RISCVDAGToDAGISel::MatchSROIW(SDNode *N) const {
  assert(N->getOpcode() == ISD::OR);
  assert(N->getOperand(0).getOpcode() == ISD::SRL);
  assert(isa<ConstantSDNode>(N->getOperand(1)));
  assert(isa<ConstantSDNode>(N->getOperand(0).getOperand(1)));
  if (!Subtarget->is64Bit())
    return false;
  SDValue Srl = N->getOperand(0);
  uint64_t VC1 = N->getConstantOperandVal(1);
  uint64_t VC2 = Srl.getConstantOperandVal(1);
  assert(VC2 < 32 && "Unexpected immediate");
  return VC1 == maskTrailingZeros<uint64_t>(32 - VC2);
}
bool RISCVDAGToDAGISel :: MatchSROIW ( SDNode * N ) const { assert ( N -> getOpcode ( ) == ISD :: OR ) ; assert ( N -> getOperand ( 0 ) . getOpcode ( ) == ISD :: SRL ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( 1 ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( 0 ) . getOperand ( 1 ) ) ) ; if ( ! Subtarget -> is64Bit ( ) ) return false ; SDValue Srl = N -> getOperand ( 0 ) ; uint64_t VC1 = N -> getConstantOperandVal ( 1 ) ; uint64_t VC2 = Srl . getConstantOperandVal ( 1 ) ; assert ( VC2 < 32 && " " ) ; return VC1 == maskTrailingZeros < uint64_t > ( 32 - VC2 ) ; }
Check that it is a SROIW (Shift Right Ones Immediate i32 on RV64).
Check that it is a SROIW ( Shift Right Ones Immediate i32 on RV64 ) .
// The IsRV64 predicate is checked after PatFrag predicates so we can get // here even on RV32. // Immediate range should be enforced by uimm5 predicate.