lib/Target/RISCV/RISCVISelDAGToDAG.cpp
bool RISCVDAGToDAGISel::MatchSLLIUW(SDNode *N) const {
  assert(N->getOpcode() == ISD::AND);
  assert(N->getOperand(0).getOpcode() == ISD::SHL);
  assert(isa<ConstantSDNode>(N->getOperand(1)));
  assert(isa<ConstantSDNode>(N->getOperand(0).getOperand(1)));

  // The IsRV64 predicate is checked after PatFrag predicates so we can get
  // here even on RV32.
  if (!Subtarget->is64Bit())
    return false;

  SDValue Shl = N->getOperand(0);
  uint64_t VC1 = N->getConstantOperandVal(1);
  uint64_t VC2 = Shl.getConstantOperandVal(1);

  // Immediate range should be enforced by uimm5 predicate.
  assert(VC2 < 32 && "Unexpected immediate");
  return VC1 == ((uint64_t)0xFFFFFFFF << VC2);
}
// Check that it is a SLLIUW (Shift Logical Left Immediate Unsigned i32
// on RV64).
// SLLIUW is the same as SLLI except for the fact that it clears the bits
// XLEN-1:32 of the input RS1 before shifting.
// A PatFrag has already checked that it has the right structure:
//
//  (AND (SHL RS1, VC2), VC1)
//
// We check that VC2, the shamt is less than 32, otherwise the pattern is
// exactly the same as SLLI and we give priority to that.
// Eventually we check that VC1, the mask used to clear the upper 32 bits
// of RS1, is correct:
//
//  VC1 == (0xFFFFFFFF << VC2)
//
Check that it is a SLLIUW (Shift Logical Left Immediate Unsigned i32
on RV64).
SLLIUW is the same as SLLI except for the fact that it clears the bits
XLEN-1:32 of the input RS1 before shifting.
A PatFrag has already checked that it has the right structure.



We check that VC2, the shamt is less than 32, otherwise the pattern is
exactly the same as SLLI and we give priority to that.
Eventually we check that VC1, the mask used to clear the upper 32 bits
of RS1, is correct.


Check that it is a SLLIUW ( Shift Logical Left Immediate Unsigned i32 on RV64 ) . SLLIUW is the same as SLLI except for the fact that it clears the bits XLEN - 1 : 32 of the input RS1 before shifting . A PatFrag has already checked that it has the right structure . We check that VC2 the shamt is less than 32 otherwise the pattern is exactly the same as SLLI and we give priority to that . Eventually we check that VC1 the mask used to clear the upper 32 bits of RS1 is correct .
bool RISCVDAGToDAGISel::MatchSLLIUW(SDNode *N) const {
  assert(N->getOpcode() == ISD::AND);
  assert(N->getOperand(0).getOpcode() == ISD::SHL);
  assert(isa<ConstantSDNode>(N->getOperand(1)));
  assert(isa<ConstantSDNode>(N->getOperand(0).getOperand(1)));
  if (!Subtarget->is64Bit())
    return false;
  SDValue Shl = N->getOperand(0);
  uint64_t VC1 = N->getConstantOperandVal(1);
  uint64_t VC2 = Shl.getConstantOperandVal(1);
  assert(VC2 < 32 && "Unexpected immediate");
  return VC1 == ((uint64_t)0xFFFFFFFF << VC2);
}
bool RISCVDAGToDAGISel :: MatchSLLIUW ( SDNode * N ) const { assert ( N -> getOpcode ( ) == ISD :: AND ) ; assert ( N -> getOperand ( 0 ) . getOpcode ( ) == ISD :: SHL ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( 1 ) ) ) ; assert ( isa < ConstantSDNode > ( N -> getOperand ( 0 ) . getOperand ( 1 ) ) ) ; if ( ! Subtarget -> is64Bit ( ) ) return false ; SDValue Shl = N -> getOperand ( 0 ) ; uint64_t VC1 = N -> getConstantOperandVal ( 1 ) ; uint64_t VC2 = Shl . getConstantOperandVal ( 1 ) ; assert ( VC2 < 32 && " " ) ; return VC1 == ( ( uint64_t ) 0xFFFFFFFF << VC2 ) ; }
Check that it is a SLLIUW (Shift Logical Left Immediate Unsigned i32
on RV64).
Check that it is a SLLIUW ( Shift Logical Left Immediate Unsigned i32 on RV64 ) .
// The IsRV64 predicate is checked after PatFrag predicates so we can get // here even on RV32. // Immediate range should be enforced by uimm5 predicate.