FablightFirmware/PWM.cpp
ISR(TIMER2_OVF_vect) {
    register uint8_t reg;

    timer2A_state.lag += timer2A_state.duty4;   // Accumulate
    reg = timer2A_state.duty12;     // Keep duty cycle in register
    if(timer2A_state.lag & 0x10) {  // Add phase accumulator bit 4 overflow
        reg++;
    }
    timer2A_state.lag &= 0x0F;

    if(reg == 0) {
        TCCR2A &= ~(3<<COM2A0);  // PWM output off
    }
    else {
        OCR2A = reg;          // Apply duty cycle
        TCCR2A |= 3<<COM2A0;  // PWM output on
    }

    // Same for B channel
    timer2B_state.lag += timer2B_state.duty4;
    reg = timer2B_state.duty12;
    if(timer2B_state.lag & 0x10) {
        reg++;
    }
    timer2B_state.lag &= 0x0F;

    if(reg == 0) {
        TCCR2A &= ~(3<<COM2B0);
    }
    else {
        OCR2B = reg;
        TCCR2A |= 3<<COM2B0;
    }
}
//---------------------------------------------------------------------
// Timer 2 overflow interrupt service routine
//   This implements a simple 4 bit sigma-delta modulator for the Timer 2 PWMs to increase the resolution to 12 bit.
//   The 4 bit mismatch is accumulated in timer2x_state.lag, bit 4 overflow of this is added to
//   the next pwm duty cycle value. Therefore, the actual duty cycle is switched between 2 values,
//   giving a 12 bit resolution on average.
Timer 2 overflow interrupt service routine
This implements a simple 4 bit sigma-delta modulator for the Timer 2 PWMs to increase the resolution to 12 bit.
The 4 bit mismatch is accumulated in timer2x_state.lag, bit 4 overflow of this is added to
the next pwm duty cycle value. Therefore, the actual duty cycle is switched between 2 values,
giving a 12 bit resolution on average.
Timer 2 overflow interrupt service routine This implements a simple 4 bit sigma - delta modulator for the Timer 2 PWMs to increase the resolution to 12 bit . The 4 bit mismatch is accumulated in timer2x_state . lag bit 4 overflow of this is added to the next pwm duty cycle value . Therefore the actual duty cycle is switched between 2 values giving a 12 bit resolution on average .
ISR(TIMER2_OVF_vect) {
    register uint8_t reg;
    timer2A_state.lag += timer2A_state.duty4;   
    reg = timer2A_state.duty12;     
    if(timer2A_state.lag & 0x10) {  
        reg++;
    }
    timer2A_state.lag &= 0x0F;
    if(reg == 0) {
        TCCR2A &= ~(3<<COM2A0);  
    }
    else {
        OCR2A = reg;          
        TCCR2A |= 3<<COM2A0;  
    }
    timer2B_state.lag += timer2B_state.duty4;
    reg = timer2B_state.duty12;
    if(timer2B_state.lag & 0x10) {
        reg++;
    }
    timer2B_state.lag &= 0x0F;
    if(reg == 0) {
        TCCR2A &= ~(3<<COM2B0);
    }
    else {
        OCR2B = reg;
        TCCR2A |= 3<<COM2B0;
    }
}
ISR ( TIMER2_OVF_vect ) { register uint8_t reg ; timer2A_state . lag += timer2A_state . duty4 ; reg = timer2A_state . duty12 ; if ( timer2A_state . lag & 0x10 ) { reg ++ ; } timer2A_state . lag &= 0x0F ; if ( reg == 0 ) { TCCR2A &= ~ ( 3 << COM2A0 ) ; } else { OCR2A = reg ; TCCR2A |= 3 << COM2A0 ; } timer2B_state . lag += timer2B_state . duty4 ; reg = timer2B_state . duty12 ; if ( timer2B_state . lag & 0x10 ) { reg ++ ; } timer2B_state . lag &= 0x0F ; if ( reg == 0 ) { TCCR2A &= ~ ( 3 << COM2B0 ) ; } else { OCR2B = reg ; TCCR2A |= 3 << COM2B0 ; } }
Timer 2 overflow interrupt service routine
This implements a simple 4 bit sigma-delta modulator for the Timer 2 PWMs to increase the resolution to 12 bit.
Timer 2 overflow interrupt service routine This implements a simple 4 bit sigma - delta modulator for the Timer 2 PWMs to increase the resolution to 12 bit .
// Accumulate // Keep duty cycle in register // Add phase accumulator bit 4 overflow // PWM output off // Apply duty cycle // PWM output on // Same for B channel