src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp
bool TranslatorVisitor::asimd_VHADD(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
    if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
        return UndefinedInstruction();
    }

    if (sz == 0b11) {
        return UndefinedInstruction();
    }

    const size_t esize = 8 << sz;
    const auto d = ToVector(Q, Vd, D);
    const auto m = ToVector(Q, Vm, M);
    const auto n = ToVector(Q, Vn, N);

    const IR::U128 reg_n = ir.GetVector(n);
    const IR::U128 reg_m = ir.GetVector(m);
    const IR::U128 result = U ? ir.VectorHalvingAddUnsigned(esize, reg_n, reg_m) : ir.VectorHalvingAddSigned(esize, reg_n, reg_m);
    ir.SetVector(d, result);

    return true;
}
// ASIMD Three registers of the same length
ASIMD Three registers of the same length
ASIMD Three registers of the same length
bool TranslatorVisitor::asimd_VHADD(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
    if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
        return UndefinedInstruction();
    }
    if (sz == 0b11) {
        return UndefinedInstruction();
    }
    const size_t esize = 8 << sz;
    const auto d = ToVector(Q, Vd, D);
    const auto m = ToVector(Q, Vm, M);
    const auto n = ToVector(Q, Vn, N);
    const IR::U128 reg_n = ir.GetVector(n);
    const IR::U128 reg_m = ir.GetVector(m);
    const IR::U128 result = U ? ir.VectorHalvingAddUnsigned(esize, reg_n, reg_m) : ir.VectorHalvingAddSigned(esize, reg_n, reg_m);
    ir.SetVector(d, result);
    return true;
}
bool TranslatorVisitor :: asimd_VHADD ( bool U , bool D , size_t sz , size_t Vn , size_t Vd , bool N , bool Q , bool M , size_t Vm ) { if ( Q && ( Common :: Bit < 0 > ( Vd ) || Common :: Bit < 0 > ( Vn ) || Common :: Bit < 0 > ( Vm ) ) ) { return UndefinedInstruction ( ) ; } if ( sz == 0b11 ) { return UndefinedInstruction ( ) ; } const size_t esize = 8 << sz ; const auto d = ToVector ( Q , Vd , D ) ; const auto m = ToVector ( Q , Vm , M ) ; const auto n = ToVector ( Q , Vn , N ) ; const IR :: U128 reg_n = ir . GetVector ( n ) ; const IR :: U128 reg_m = ir . GetVector ( m ) ; const IR :: U128 result = U ? ir . VectorHalvingAddUnsigned ( esize , reg_n , reg_m ) : ir . VectorHalvingAddSigned ( esize , reg_n , reg_m ) ; ir . SetVector ( d , result ) ; return true ; }
ASIMD Three registers of the same length
ASIMD Three registers of the same length