libClearCore/src/EthernetManager.cpp
void EthernetManager::IrqHandlerGmac() {
    // Transmit status reg
    volatile uint32_t tsr;
    // Receive status reg
    volatile uint32_t rsr;

    tsr = GMAC->TSR.reg;    // Transmit status register
    rsr = GMAC->RSR.reg;    // Receive  status register
    // Need to clear the ISR (clear on read)
    GMAC->ISR.reg;

    // Frame transmitted
    if (tsr & GMAC_TSR_TXCOMP) {
        // Clear the TSR reg
        GMAC->TSR.reg = tsr;
    }

    // Frame received, add a packet to packet buffer.
    if (rsr & GMAC_RSR_REC) {
        m_recv = true;
    }
    // Clear the RSR reg
    GMAC->RSR.reg = rsr;
}
/**
    The GMAC interrupt handler.

    This should be called by GMAC Interrupt Vector.
    *Note: the register & bits are cleared on read
**/
The GMAC interrupt handler.
This should be called by GMAC Interrupt Vector.
Note: the register & bits are cleared on read
The GMAC interrupt handler . This should be called by GMAC Interrupt Vector . Note : the register & bits are cleared on read
void EthernetManager::IrqHandlerGmac() {
    volatile uint32_t tsr;
    volatile uint32_t rsr;
    tsr = GMAC->TSR.reg;    ister
    rsr = GMAC->RSR.reg;    
    GMAC->ISR.reg;
    if (tsr & GMAC_TSR_TXCOMP) {
        GMAC->TSR.reg = tsr;
    }
    if (rsr & GMAC_RSR_REC) {
        m_recv = true;
    }
    GMAC->RSR.reg = rsr;
}
void EthernetManager :: IrqHandlerGmac ( ) { volatile uint32_t tsr ; volatile uint32_t rsr ; tsr = GMAC -> TSR . reg ; rsr = GMAC -> RSR . reg ; GMAC -> ISR . reg ; if ( tsr & GMAC_TSR_TXCOMP ) { GMAC -> TSR . reg = tsr ; } if ( rsr & GMAC_RSR_REC ) { m_recv = true ; } GMAC -> RSR . reg = rsr ; }
The GMAC interrupt handler.
The GMAC interrupt handler .
// Transmit status reg // Receive status reg // Transmit status register // Receive  status register // Need to clear the ISR (clear on read) // Frame transmitted // Clear the TSR reg // Frame received, add a packet to packet buffer. // Clear the RSR reg