unit_tests/profiling/profiling_tests.cpp
HWCMDTEST_F(IGFX_GEN8_CORE, ProfilingTests, GIVENCommandQueueWithProfolingWHENWalkerIsDispatchedTHENPipeControlWithTimeStampIsPresentInCS) {
    typedef typename FamilyType::PIPE_CONTROL PIPE_CONTROL;
    typedef typename FamilyType::GPGPU_WALKER GPGPU_WALKER;

    MockKernel kernel(program.get(), kernelInfo, *pDevice);
    ASSERT_EQ(CL_SUCCESS, kernel.initialize());

    size_t globalOffsets[3] = {0, 0, 0};
    size_t workItems[3] = {1, 1, 1};
    uint32_t dimensions = 1;
    cl_event event;
    cl_kernel clKernel = &kernel;

    static_cast<CommandQueueHw<FamilyType> *>(pCmdQ)->enqueueKernel(
        clKernel,
        dimensions,
        globalOffsets,
        workItems,
        nullptr,
        0,
        nullptr,
        &event);

    parseCommands<FamilyType>(*pCmdQ);

    // Find GPGPU_WALKER
    auto itorGPGPUWalkerCmd = find<GPGPU_WALKER *>(cmdList.begin(), cmdList.end());
    GenCmdList::reverse_iterator rItorGPGPUWalkerCmd(itorGPGPUWalkerCmd);
    ASSERT_NE(cmdList.end(), itorGPGPUWalkerCmd);

    // Check PIPE_CONTROLs
    auto itorBeforePC = reverse_find<PIPE_CONTROL *>(rItorGPGPUWalkerCmd, cmdList.rbegin());
    ASSERT_NE(cmdList.rbegin(), itorBeforePC);
    auto pBeforePC = genCmdCast<PIPE_CONTROL *>(*itorBeforePC);
    ASSERT_NE(nullptr, pBeforePC);
    EXPECT_EQ(1u, pBeforePC->getCommandStreamerStallEnable());

    auto itorAfterPC = find<PIPE_CONTROL *>(itorGPGPUWalkerCmd, cmdList.end());
    ASSERT_NE(cmdList.end(), itorAfterPC);
    auto pAfterPC = genCmdCast<PIPE_CONTROL *>(*itorAfterPC);
    ASSERT_NE(nullptr, pAfterPC);
    EXPECT_EQ(1u, pAfterPC->getCommandStreamerStallEnable());

    EXPECT_EQ(PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, pBeforePC->getPostSyncOperation());

    EXPECT_TRUE(static_cast<MockEvent<Event> *>(event)->calcProfilingData());

    clReleaseEvent(event);
}
/*
#   Two additional PIPE_CONTROLs are expected before first MI_STORE_REGISTER_MEM (which is before GPGPU_WALKER)
#   and after second MI_STORE_REGISTER_MEM (which is after GPGPU_WALKER).
*/
Two additional PIPE_CONTROLs are expected before first MI_STORE_REGISTER_MEM (which is before GPGPU_WALKER)
and after second MI_STORE_REGISTER_MEM (which is after GPGPU_WALKER).
Two additional PIPE_CONTROLs are expected before first MI_STORE_REGISTER_MEM ( which is before GPGPU_WALKER ) and after second MI_STORE_REGISTER_MEM ( which is after GPGPU_WALKER ) .
HWCMDTEST_F(IGFX_GEN8_CORE, ProfilingTests, GIVENCommandQueueWithProfolingWHENWalkerIsDispatchedTHENPipeControlWithTimeStampIsPresentInCS) {
    typedef typename FamilyType::PIPE_CONTROL PIPE_CONTROL;
    typedef typename FamilyType::GPGPU_WALKER GPGPU_WALKER;
    MockKernel kernel(program.get(), kernelInfo, *pDevice);
    ASSERT_EQ(CL_SUCCESS, kernel.initialize());
    size_t globalOffsets[3] = {0, 0, 0};
    size_t workItems[3] = {1, 1, 1};
    uint32_t dimensions = 1;
    cl_event event;
    cl_kernel clKernel = &kernel;
    static_cast<CommandQueueHw<FamilyType> *>(pCmdQ)->enqueueKernel(
        clKernel,
        dimensions,
        globalOffsets,
        workItems,
        nullptr,
        0,
        nullptr,
        &event);
    parseCommands<FamilyType>(*pCmdQ);
    auto itorGPGPUWalkerCmd = find<GPGPU_WALKER *>(cmdList.begin(), cmdList.end());
    GenCmdList::reverse_iterator rItorGPGPUWalkerCmd(itorGPGPUWalkerCmd);
    ASSERT_NE(cmdList.end(), itorGPGPUWalkerCmd);
    auto itorBeforePC = reverse_find<PIPE_CONTROL *>(rItorGPGPUWalkerCmd, cmdList.rbegin());
    ASSERT_NE(cmdList.rbegin(), itorBeforePC);
    auto pBeforePC = genCmdCast<PIPE_CONTROL *>(*itorBeforePC);
    ASSERT_NE(nullptr, pBeforePC);
    EXPECT_EQ(1u, pBeforePC->getCommandStreamerStallEnable());
    auto itorAfterPC = find<PIPE_CONTROL *>(itorGPGPUWalkerCmd, cmdList.end());
    ASSERT_NE(cmdList.end(), itorAfterPC);
    auto pAfterPC = genCmdCast<PIPE_CONTROL *>(*itorAfterPC);
    ASSERT_NE(nullptr, pAfterPC);
    EXPECT_EQ(1u, pAfterPC->getCommandStreamerStallEnable());
    EXPECT_EQ(PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, pBeforePC->getPostSyncOperation());
    EXPECT_TRUE(static_cast<MockEvent<Event> *>(event)->calcProfilingData());
    clReleaseEvent(event);
}
HWCMDTEST_F ( IGFX_GEN8_CORE , ProfilingTests , GIVENCommandQueueWithProfolingWHENWalkerIsDispatchedTHENPipeControlWithTimeStampIsPresentInCS ) { typedef typename FamilyType :: PIPE_CONTROL PIPE_CONTROL ; typedef typename FamilyType :: GPGPU_WALKER GPGPU_WALKER ; MockKernel kernel ( program . get ( ) , kernelInfo , * pDevice ) ; ASSERT_EQ ( CL_SUCCESS , kernel . initialize ( ) ) ; size_t globalOffsets [ 3 ] = { 0 , 0 , 0 } ; size_t workItems [ 3 ] = { 1 , 1 , 1 } ; uint32_t dimensions = 1 ; cl_event event ; cl_kernel clKernel = & kernel ; static_cast < CommandQueueHw < FamilyType > * > ( pCmdQ ) -> enqueueKernel ( clKernel , dimensions , globalOffsets , workItems , nullptr , 0 , nullptr , & event ) ; parseCommands < FamilyType > ( * pCmdQ ) ; auto itorGPGPUWalkerCmd = find < GPGPU_WALKER * > ( cmdList . begin ( ) , cmdList . end ( ) ) ; GenCmdList :: reverse_iterator rItorGPGPUWalkerCmd ( itorGPGPUWalkerCmd ) ; ASSERT_NE ( cmdList . end ( ) , itorGPGPUWalkerCmd ) ; auto itorBeforePC = reverse_find < PIPE_CONTROL * > ( rItorGPGPUWalkerCmd , cmdList . rbegin ( ) ) ; ASSERT_NE ( cmdList . rbegin ( ) , itorBeforePC ) ; auto pBeforePC = genCmdCast < PIPE_CONTROL * > ( * itorBeforePC ) ; ASSERT_NE ( nullptr , pBeforePC ) ; EXPECT_EQ ( 1u , pBeforePC -> getCommandStreamerStallEnable ( ) ) ; auto itorAfterPC = find < PIPE_CONTROL * > ( itorGPGPUWalkerCmd , cmdList . end ( ) ) ; ASSERT_NE ( cmdList . end ( ) , itorAfterPC ) ; auto pAfterPC = genCmdCast < PIPE_CONTROL * > ( * itorAfterPC ) ; ASSERT_NE ( nullptr , pAfterPC ) ; EXPECT_EQ ( 1u , pAfterPC -> getCommandStreamerStallEnable ( ) ) ; EXPECT_EQ ( PIPE_CONTROL :: POST_SYNC_OPERATION_WRITE_TIMESTAMP , pBeforePC -> getPostSyncOperation ( ) ) ; EXPECT_TRUE ( static_cast < MockEvent < Event > * > ( event ) -> calcProfilingData ( ) ) ; clReleaseEvent ( event ) ; }
Two additional PIPE_CONTROLs are expected before first MI_STORE_REGISTER_MEM (which is before GPGPU_WALKER)
and after second MI_STORE_REGISTER_MEM (which is after GPGPU_WALKER).
Two additional PIPE_CONTROLs are expected before first MI_STORE_REGISTER_MEM ( which is before GPGPU_WALKER ) and after second MI_STORE_REGISTER_MEM ( which is after GPGPU_WALKER ) .
// Find GPGPU_WALKER // Check PIPE_CONTROLs