XilinxProcessorIPLib/drivers/sysmonpsu/src/xsysmonpsu_intr.c
void XSysMonPsu_IntrEnable(XSysMonPsu *InstancePtr, u64 Mask)
{
	u64 RegValue;

	/* Assert the arguments. */
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/* Enable the specified interrupts in the AMS Interrupt Enable Register. */
	RegValue = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
					XSYSMONPSU_IER_0_OFFSET);
	RegValue |= (Mask & XSYSMONPSU_IXR_0_MASK);
	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IER_0_OFFSET,
			  (u32)RegValue);

	RegValue = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
					XSYSMONPSU_IER_1_OFFSET);
	RegValue |= ((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IER_1_OFFSET,
			  (u32)RegValue);
}
/****************************************************************************/
/**
*
* This function enables the specified interrupts in the device.
*
* @param	InstancePtr is a pointer to the XSysMonPsu instance.
* @param	Mask is the 64 bit-mask of the interrupts to be enabled.
*		Bit positions of 1 will be enabled. Bit positions of 0 will
*		keep the previous setting. This mask is formed by OR'ing
*		XSYSMONPSU_IER_0_* and XSYSMONPSU_IER_1_* bits defined in
*		xsysmonpsu_hw.h.
*
* @return	None.
*
* @note		None.
*
*****************************************************************************/
This function enables the specified interrupts in the device.
This function enables the specified interrupts in the device .
void XSysMonPsu_IntrEnable(XSysMonPsu *InstancePtr, u64 Mask)
{
	u64 RegValue;
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	RegValue = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
					XSYSMONPSU_IER_0_OFFSET);
	RegValue |= (Mask & XSYSMONPSU_IXR_0_MASK);
	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IER_0_OFFSET,
			  (u32)RegValue);
	RegValue = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
					XSYSMONPSU_IER_1_OFFSET);
	RegValue |= ((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IER_1_OFFSET,
			  (u32)RegValue);
}
void XSysMonPsu_IntrEnable ( XSysMonPsu * InstancePtr , u64 Mask ) { u64 RegValue ; Xil_AssertVoid ( InstancePtr != NULL ) ; Xil_AssertVoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; RegValue = ( u64 ) XSysmonPsu_ReadReg ( InstancePtr -> Config . BaseAddress + XSYSMONPSU_IER_0_OFFSET ) ; RegValue |= ( Mask & XSYSMONPSU_IXR_0_MASK ) ; XSysmonPsu_WriteReg ( InstancePtr -> Config . BaseAddress + XSYSMONPSU_IER_0_OFFSET , ( u32 ) RegValue ) ; RegValue = ( u64 ) XSysmonPsu_ReadReg ( InstancePtr -> Config . BaseAddress + XSYSMONPSU_IER_1_OFFSET ) ; RegValue |= ( ( Mask >> XSYSMONPSU_IXR_1_SHIFT ) & XSYSMONPSU_IXR_1_MASK ) ; XSysmonPsu_WriteReg ( InstancePtr -> Config . BaseAddress + XSYSMONPSU_IER_1_OFFSET , ( u32 ) RegValue ) ; }
This function enables the specified interrupts in the device.
This function enables the specified interrupts in the device .
/* Assert the arguments. */ /* Enable the specified interrupts in the AMS Interrupt Enable Register. */