XilinxProcessorIPLib/drivers/dp14txss/examples/src/pt_only/tx.c
u32 config_phy(int LineRate_init_tx){
	u32 Status=0;
	u8 linerate;
	u32 dptx_sts = 0;

#if TX_BUFFER_BYPASS
    switch(LineRate_init_tx){
            case XDP_TX_LINK_BW_SET_162GBPS:
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1, 0x3E,
						DIVIDER_162);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2, 0x3E,
						DIVIDER_162);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3, 0x3E,
						DIVIDER_162);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4, 0x3E,
						DIVIDER_162);

				break;

            case XDP_TX_LINK_BW_SET_270GBPS:
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1, 0x3E,
						DIVIDER_270);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2, 0x3E,
						DIVIDER_270);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3, 0x3E,
						DIVIDER_270);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4, 0x3E,
						DIVIDER_270);

				break;

            case XDP_TX_LINK_BW_SET_540GBPS:
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1, 0x3E,
						DIVIDER_540);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2, 0x3E,
						DIVIDER_540);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3, 0x3E,
						DIVIDER_540);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4, 0x3E,
						DIVIDER_540);

				break;

            case XDP_TX_LINK_BW_SET_810GBPS:
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1, 0x3E,
						DIVIDER_810); //57440);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2, 0x3E,
						DIVIDER_810); //57440);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3, 0x3E,
						DIVIDER_810); //57440);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4, 0x3E,
						DIVIDER_810); //57440);

				break;
    }
#endif

	switch(LineRate_init_tx){
	case XDP_TX_LINK_BW_SET_162GBPS:
#ifndef versal
		Status = PHY_Configuration_Tx(&VPhyInst,
				PHY_User_Config_Table[(is_TX_CPLL) ? 0 : 3]);
#else
		linerate = VERSAL_162G;
#endif
		break;

	case XDP_TX_LINK_BW_SET_270GBPS:
#ifndef versal
		Status = PHY_Configuration_Tx(&VPhyInst,
				PHY_User_Config_Table[(is_TX_CPLL) ? 1 : 4]);
#else
			linerate = VERSAL_270G;
#endif
		break;

	case XDP_TX_LINK_BW_SET_540GBPS:
#ifndef versal
		Status = PHY_Configuration_Tx(&VPhyInst,
				PHY_User_Config_Table[(is_TX_CPLL) ? 2 : 5]);
#else
			linerate = VERSAL_540G;
#endif
		break;

	case XDP_TX_LINK_BW_SET_810GBPS:
#ifndef versal
		Status = PHY_Configuration_Tx(&VPhyInst,
				PHY_User_Config_Table[(is_TX_CPLL) ? 9 : 10]);
#else
			linerate = VERSAL_810G;
#endif
		break;
	}

#ifdef versal

	GtCtrl(GT_RATE_MASK,(linerate << 1),1);
    u8 retry=0;
    while ((dptx_sts != ALL_LANE) && retry < 255) {
         dptx_sts = XDp_ReadReg(DpTxSsInst.DpPtr->Config.BaseAddr, 0x280);
         dptx_sts &= ALL_LANE;
         DpPt_CustomWaitUs(DpTxSsInst.DpPtr, 100);
         retry++;
      }
    if(retry==255)
    {
		Status = XST_FAILURE;
    }


#endif

	if (Status != XST_SUCCESS) {
		xil_printf (
				"+++\r\n");
//			"+++++++ TX GT configuration encountered a failure +++++++\r\n");
	}

	return Status;
}
/*****************************************************************************/
/**
*
* This function sets VPHY based on the linerate
*
* @param	user_config_struct.
*
* @return	Status.
*
* @note		None.
*
******************************************************************************/
This function sets VPHY based on the linerate
This function sets VPHY based on the linerate
u32 config_phy(int LineRate_init_tx){
	u32 Status=0;
	u8 linerate;
	u32 dptx_sts = 0;
#if TX_BUFFER_BYPASS
    switch(LineRate_init_tx){
            case XDP_TX_LINK_BW_SET_162GBPS:
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1, 0x3E,
						DIVIDER_162);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2, 0x3E,
						DIVIDER_162);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3, 0x3E,
						DIVIDER_162);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4, 0x3E,
						DIVIDER_162);
				break;
            case XDP_TX_LINK_BW_SET_270GBPS:
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1, 0x3E,
						DIVIDER_270);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2, 0x3E,
						DIVIDER_270);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3, 0x3E,
						DIVIDER_270);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4, 0x3E,
						DIVIDER_270);
				break;
            case XDP_TX_LINK_BW_SET_540GBPS:
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1, 0x3E,
						DIVIDER_540);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2, 0x3E,
						DIVIDER_540);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3, 0x3E,
						DIVIDER_540);
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4, 0x3E,
						DIVIDER_540);
				break;
            case XDP_TX_LINK_BW_SET_810GBPS:
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1, 0x3E,
						DIVIDER_810); 
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2, 0x3E,
						DIVIDER_810); 
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3, 0x3E,
						DIVIDER_810); 
				XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4, 0x3E,
						DIVIDER_810); 
				break;
    }
#endif
	switch(LineRate_init_tx){
	case XDP_TX_LINK_BW_SET_162GBPS:
#ifndef versal
		Status = PHY_Configuration_Tx(&VPhyInst,
				PHY_User_Config_Table[(is_TX_CPLL) ? 0 : 3]);
#else
		linerate = VERSAL_162G;
#endif
		break;
	case XDP_TX_LINK_BW_SET_270GBPS:
#ifndef versal
		Status = PHY_Configuration_Tx(&VPhyInst,
				PHY_User_Config_Table[(is_TX_CPLL) ? 1 : 4]);
#else
			linerate = VERSAL_270G;
#endif
		break;
	case XDP_TX_LINK_BW_SET_540GBPS:
#ifndef versal
		Status = PHY_Configuration_Tx(&VPhyInst,
				PHY_User_Config_Table[(is_TX_CPLL) ? 2 : 5]);
#else
			linerate = VERSAL_540G;
#endif
		break;
	case XDP_TX_LINK_BW_SET_810GBPS:
#ifndef versal
		Status = PHY_Configuration_Tx(&VPhyInst,
				PHY_User_Config_Table[(is_TX_CPLL) ? 9 : 10]);
#else
			linerate = VERSAL_810G;
#endif
		break;
	}
#ifdef versal
	GtCtrl(GT_RATE_MASK,(linerate << 1),1);
    u8 retry=0;
    while ((dptx_sts != ALL_LANE) && retry < 255) {
         dptx_sts = XDp_ReadReg(DpTxSsInst.DpPtr->Config.BaseAddr, 0x280);
         dptx_sts &= ALL_LANE;
         DpPt_CustomWaitUs(DpTxSsInst.DpPtr, 100);
         retry++;
      }
    if(retry==255)
    {
		Status = XST_FAILURE;
    }
#endif
	if (Status != XST_SUCCESS) {
		xil_printf (
				"+++\r\n");
	}
	return Status;
}
u32 config_phy ( int LineRate_init_tx ) { u32 Status = 0 ; u8 linerate ; u32 dptx_sts = 0 ; #if TX_BUFFER_BYPASS switch ( LineRate_init_tx ) { case XDP_TX_LINK_BW_SET_162GBPS : XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH1 , 0x3E , DIVIDER_162 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH2 , 0x3E , DIVIDER_162 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH3 , 0x3E , DIVIDER_162 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH4 , 0x3E , DIVIDER_162 ) ; break ; case XDP_TX_LINK_BW_SET_270GBPS : XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH1 , 0x3E , DIVIDER_270 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH2 , 0x3E , DIVIDER_270 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH3 , 0x3E , DIVIDER_270 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH4 , 0x3E , DIVIDER_270 ) ; break ; case XDP_TX_LINK_BW_SET_540GBPS : XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH1 , 0x3E , DIVIDER_540 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH2 , 0x3E , DIVIDER_540 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH3 , 0x3E , DIVIDER_540 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH4 , 0x3E , DIVIDER_540 ) ; break ; case XDP_TX_LINK_BW_SET_810GBPS : XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH1 , 0x3E , DIVIDER_810 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH2 , 0x3E , DIVIDER_810 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH3 , 0x3E , DIVIDER_810 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH4 , 0x3E , DIVIDER_810 ) ; break ; } #endif switch ( LineRate_init_tx ) { case XDP_TX_LINK_BW_SET_162GBPS : #ifndef versal Status = PHY_Configuration_Tx ( & VPhyInst , PHY_User_Config_Table [ ( is_TX_CPLL ) ? 0 : 3 ] ) ; #else linerate = VERSAL_162G ; #endif break ; case XDP_TX_LINK_BW_SET_270GBPS : #ifndef versal Status = PHY_Configuration_Tx ( & VPhyInst , PHY_User_Config_Table [ ( is_TX_CPLL ) ? 1 : 4 ] ) ; #else linerate = VERSAL_270G ; #endif break ; case XDP_TX_LINK_BW_SET_540GBPS : #ifndef versal Status = PHY_Configuration_Tx ( & VPhyInst , PHY_User_Config_Table [ ( is_TX_CPLL ) ? 2 : 5 ] ) ; #else linerate = VERSAL_540G ; #endif break ; case XDP_TX_LINK_BW_SET_810GBPS : #ifndef versal Status = PHY_Configuration_Tx ( & VPhyInst , PHY_User_Config_Table [ ( is_TX_CPLL ) ? 9 : 10 ] ) ; #else linerate = VERSAL_810G ; #endif break ; } #ifdef versal GtCtrl ( GT_RATE_MASK , ( linerate << 1 ) , 1 ) ; u8 retry = 0 ; while ( ( dptx_sts != ALL_LANE ) && retry < 255 ) { dptx_sts = XDp_ReadReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , 0x280 ) ; dptx_sts &= ALL_LANE ; DpPt_CustomWaitUs ( DpTxSsInst . DpPtr , 100 ) ; retry ++ ; } if ( retry == 255 ) { Status = XST_FAILURE ; } #endif if ( Status != XST_SUCCESS ) { xil_printf ( " \r \n " ) ; } return Status ; }
This function sets VPHY based on the linerate
This function sets VPHY based on the linerate
//57440); //57440); //57440); //57440); //			"+++++++ TX GT configuration encountered a failure +++++++\r\n");