XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c
u64 XSysMon_GetSeqAvgEnables(XSysMon *InstancePtr)
{
	u32 RegValAvg;
	u32 RegValAvg1;
	u64 RetVal = 0x0;

	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Read the averaging enable status for all the channels from the
	 * ADC Channel Averaging Enables Sequencer Registers.
	 */
	RegValAvg = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
				    XSM_SEQ02_OFFSET) & XSM_SEQ02_CH_VALID_MASK;
	RegValAvg |= (XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
			XSM_SEQ03_OFFSET) & XSM_SEQ03_CH_VALID_MASK) <<
			XSM_SEQ_CH_AUX_SHIFT;

	RegValAvg1 = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
				XSM_SEQ09_OFFSET) & XSM_SEQ09_CH_VALID_MASK;

	RetVal = RegValAvg1;
	RetVal = (RetVal << XSM_SEQ_CH_VUSR_SHIFT);
	RetVal = RetVal | RegValAvg;

	return RetVal;
}
/****************************************************************************/
/**
*
* This function returns the channels for which the averaging has been enabled
* in the ADC Channel Averaging Enables Sequencer Registers.
*
* @param	InstancePtr is a pointer to the XSysMon instance.
*
* @returns 	The status of averaging (enabled/disabled) for all the channels.
*		Use XSM_SEQ_CH__* defined in xsysmon_hw.h to interpret the
*		Channel numbers. Bit masks of 1 are the channels for which
*		averaging is enabled and bit mask of 0 are the channels for
*		averaging is disabled.
*
* @note		None.
*
*****************************************************************************/
This function returns the channels for which the averaging has been enabled
in the ADC Channel Averaging Enables Sequencer Registers.
This function returns the channels for which the averaging has been enabled in the ADC Channel Averaging Enables Sequencer Registers .
u64 XSysMon_GetSeqAvgEnables(XSysMon *InstancePtr)
{
	u32 RegValAvg;
	u32 RegValAvg1;
	u64 RetVal = 0x0;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	RegValAvg = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
				    XSM_SEQ02_OFFSET) & XSM_SEQ02_CH_VALID_MASK;
	RegValAvg |= (XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
			XSM_SEQ03_OFFSET) & XSM_SEQ03_CH_VALID_MASK) <<
			XSM_SEQ_CH_AUX_SHIFT;
	RegValAvg1 = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
				XSM_SEQ09_OFFSET) & XSM_SEQ09_CH_VALID_MASK;
	RetVal = RegValAvg1;
	RetVal = (RetVal << XSM_SEQ_CH_VUSR_SHIFT);
	RetVal = RetVal | RegValAvg;
	return RetVal;
}
u64 XSysMon_GetSeqAvgEnables ( XSysMon * InstancePtr ) { u32 RegValAvg ; u32 RegValAvg1 ; u64 RetVal = 0x0 ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; RegValAvg = XSysMon_ReadReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ02_OFFSET ) & XSM_SEQ02_CH_VALID_MASK ; RegValAvg |= ( XSysMon_ReadReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ03_OFFSET ) & XSM_SEQ03_CH_VALID_MASK ) << XSM_SEQ_CH_AUX_SHIFT ; RegValAvg1 = XSysMon_ReadReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ09_OFFSET ) & XSM_SEQ09_CH_VALID_MASK ; RetVal = RegValAvg1 ; RetVal = ( RetVal << XSM_SEQ_CH_VUSR_SHIFT ) ; RetVal = RetVal | RegValAvg ; return RetVal ; }
This function returns the channels for which the averaging has been enabled
in the ADC Channel Averaging Enables Sequencer Registers.
This function returns the channels for which the averaging has been enabled in the ADC Channel Averaging Enables Sequencer Registers .
/*
	 * Assert the arguments.
	 */ /*
	 * Read the averaging enable status for all the channels from the
	 * ADC Channel Averaging Enables Sequencer Registers.
	 */