os_dep/linux/pci_intf.c
void rtw_pci_enable_aspm(_adapter *padapter)
{
	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(pdvobjpriv);
	struct pci_dev	*pdev = pdvobjpriv->ppcidev;
	struct pci_dev	*bridge_pdev = pdev->bus->self;
	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
	u16	aspmlevel = 0;
	u8	u_pcibridge_aspmsetting = 0;
	u8	u_device_aspmsetting = 0;
	u32	u_device_aspmsupportsetting = 0;


	/* We shall check RF Off Level for ASPM function instead of registry settings, revised by Roger, 2013.03.29. */
	if (!(pwrpriv->reg_rfps_level & (RT_RF_LPS_LEVEL_ASPM | RT_RF_PS_LEVEL_ALWAYS_ASPM)))
		return;

	/* When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, */
	/* we do not execute any action and return. Added by tynli. */
	if ((pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) ||
	    (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff)) {
		RTW_INFO("rtw_pci_enable_aspm(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n");
		return;
	}

	/* Get Bridge ASPM Support
	 * not to enable bridge aspm if bridge does not support
	 * Added by sherry 20100803
	*/
	{
		/* Get the Link Capability, it ls located at offset 0x0c from the PCIE Capability */
		pci_read_config_dword(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x0C), &u_device_aspmsupportsetting);

		RTW_INFO("rtw_pci_enable_aspm(): Bridge ASPM support %x\n", u_device_aspmsupportsetting);
		if (((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) || ((u_device_aspmsupportsetting & BIT(10)) != BIT(10))) {
			if (pdvobjpriv->const_devicepci_aspm_setting == 3) {
				RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L0S or L1\n");
				return;
			} else if (pdvobjpriv->const_devicepci_aspm_setting == 2) {
				if ((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) {
					RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L1\n");
					return;
				}
			} else if (pdvobjpriv->const_devicepci_aspm_setting == 1) {
				if ((u_device_aspmsupportsetting & BIT(10)) != BIT(10)) {
					RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L0s\n");
					return;
				}

			}
		} else
			RTW_INFO("rtw_pci_enable_aspm(): Bridge support L0s and L1\n");
	}

	/*
	* Skip following settings if ASPM has already enabled, added by Roger, 2013.03.15.
	*/
	if ((pcipriv->pcibridge_linkctrlreg & (BIT0 | BIT1)) &&
	    (pcipriv->linkctrl_reg & (BIT0 | BIT1))) {
		/* BIT0: L0S, BIT1:L1 */

		RTW_INFO("PlatformEnableASPM(): ASPM is already enabled, skip incoming settings!!\n");
		return;
	}

	/* 4 Enable Pci Bridge ASPM */
	/* Write PCI bridge PCIE-capability Link Control Register */
	/* Justin: Can we change the ASPM Control register ? */
	/* The system BIOS should set this register with a correct value */
	/* If we change the force enable the ASPM L1/L0s, this may cause the system hang */
	u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg;
	u_pcibridge_aspmsetting |= pdvobjpriv->const_hostpci_aspm_setting;

	if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL ||
	    pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS)
		u_pcibridge_aspmsetting &= ~BIT(0); /* for intel host 42 device 43 */

	pci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x10), u_pcibridge_aspmsetting);
	RTW_INFO("PlatformEnableASPM():PciBridge Write reg[%x] = %x\n",
		 (pcipriv->pcibridge_pciehdr_offset + 0x10),
		 u_pcibridge_aspmsetting);

	rtw_udelay_os(50);

	/*Get ASPM level (with/without Clock Req)*/
	aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting;
	u_device_aspmsetting = pcipriv->linkctrl_reg;
	u_device_aspmsetting |= aspmlevel; /* device 43 */

	rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting);

	if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
		rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
		RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
	}

	rtw_udelay_os(50);
}
/*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
 * power saving We should follow the sequence to enable
 * RTL8192SE first then enable Pci Bridge ASPM
 * or the system will show bluescreen.
*/
Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
power saving We should follow the sequence to enable
RTL8192SE first then enable Pci Bridge ASPM
or the system will show bluescreen.
Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for power saving We should follow the sequence to enable RTL8192SE first then enable Pci Bridge ASPM or the system will show bluescreen .
void rtw_pci_enable_aspm(_adapter *padapter)
{
	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(pdvobjpriv);
	struct pci_dev	*pdev = pdvobjpriv->ppcidev;
	struct pci_dev	*bridge_pdev = pdev->bus->self;
	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
	u16	aspmlevel = 0;
	u8	u_pcibridge_aspmsetting = 0;
	u8	u_device_aspmsetting = 0;
	u32	u_device_aspmsupportsetting = 0;
	if (!(pwrpriv->reg_rfps_level & (RT_RF_LPS_LEVEL_ASPM | RT_RF_PS_LEVEL_ALWAYS_ASPM)))
		return;
	if ((pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) ||
	    (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff)) {
		RTW_INFO("rtw_pci_enable_aspm(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n");
		return;
	}
	{
		pci_read_config_dword(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x0C), &u_device_aspmsupportsetting);
		RTW_INFO("rtw_pci_enable_aspm(): Bridge ASPM support %x\n", u_device_aspmsupportsetting);
		if (((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) || ((u_device_aspmsupportsetting & BIT(10)) != BIT(10))) {
			if (pdvobjpriv->const_devicepci_aspm_setting == 3) {
				RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L0S or L1\n");
				return;
			} else if (pdvobjpriv->const_devicepci_aspm_setting == 2) {
				if ((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) {
					RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L1\n");
					return;
				}
			} else if (pdvobjpriv->const_devicepci_aspm_setting == 1) {
				if ((u_device_aspmsupportsetting & BIT(10)) != BIT(10)) {
					RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L0s\n");
					return;
				}
			}
		} else
			RTW_INFO("rtw_pci_enable_aspm(): Bridge support L0s and L1\n");
	}
	if ((pcipriv->pcibridge_linkctrlreg & (BIT0 | BIT1)) &&
	    (pcipriv->linkctrl_reg & (BIT0 | BIT1))) {
		RTW_INFO("PlatformEnableASPM(): ASPM is already enabled, skip incoming settings!!\n");
		return;
	}
	u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg;
	u_pcibridge_aspmsetting |= pdvobjpriv->const_hostpci_aspm_setting;
	if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL ||
	    pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS)
		u_pcibridge_aspmsetting &= ~BIT(0); 
	pci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x10), u_pcibridge_aspmsetting);
	RTW_INFO("PlatformEnableASPM():PciBridge Write reg[%x] = %x\n",
		 (pcipriv->pcibridge_pciehdr_offset + 0x10),
		 u_pcibridge_aspmsetting);
	rtw_udelay_os(50);
	aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting;
	u_device_aspmsetting = pcipriv->linkctrl_reg;
	u_device_aspmsetting |= aspmlevel; 
	rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting);
	if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
		rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
		RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
	}
	rtw_udelay_os(50);
}
void rtw_pci_enable_aspm ( _adapter * padapter ) { struct dvobj_priv * pdvobjpriv = adapter_to_dvobj ( padapter ) ; struct pwrctrl_priv * pwrpriv = dvobj_to_pwrctl ( pdvobjpriv ) ; struct pci_dev * pdev = pdvobjpriv -> ppcidev ; struct pci_dev * bridge_pdev = pdev -> bus -> self ; struct pci_priv * pcipriv = & ( pdvobjpriv -> pcipriv ) ; u16 aspmlevel = 0 ; u8 u_pcibridge_aspmsetting = 0 ; u8 u_device_aspmsetting = 0 ; u32 u_device_aspmsupportsetting = 0 ; if ( ! ( pwrpriv -> reg_rfps_level & ( RT_RF_LPS_LEVEL_ASPM | RT_RF_PS_LEVEL_ALWAYS_ASPM ) ) ) return ; if ( ( pcipriv -> busnumber == 0xff && pcipriv -> devnumber == 0xff && pcipriv -> funcnumber == 0xff ) || ( pcipriv -> pcibridge_busnum == 0xff && pcipriv -> pcibridge_devnum == 0xff && pcipriv -> pcibridge_funcnum == 0xff ) ) { RTW_INFO ( " \n " ) ; return ; } { pci_read_config_dword ( bridge_pdev , ( pcipriv -> pcibridge_pciehdr_offset + 0x0C ) , & u_device_aspmsupportsetting ) ; RTW_INFO ( " \n " , u_device_aspmsupportsetting ) ; if ( ( ( u_device_aspmsupportsetting & BIT ( 11 ) ) != BIT ( 11 ) ) || ( ( u_device_aspmsupportsetting & BIT ( 10 ) ) != BIT ( 10 ) ) ) { if ( pdvobjpriv -> const_devicepci_aspm_setting == 3 ) { RTW_INFO ( " \n " ) ; return ; } else if ( pdvobjpriv -> const_devicepci_aspm_setting == 2 ) { if ( ( u_device_aspmsupportsetting & BIT ( 11 ) ) != BIT ( 11 ) ) { RTW_INFO ( " \n " ) ; return ; } } else if ( pdvobjpriv -> const_devicepci_aspm_setting == 1 ) { if ( ( u_device_aspmsupportsetting & BIT ( 10 ) ) != BIT ( 10 ) ) { RTW_INFO ( " \n " ) ; return ; } } } else RTW_INFO ( " \n " ) ; } if ( ( pcipriv -> pcibridge_linkctrlreg & ( BIT0 | BIT1 ) ) && ( pcipriv -> linkctrl_reg & ( BIT0 | BIT1 ) ) ) { RTW_INFO ( " \n " ) ; return ; } u_pcibridge_aspmsetting = pcipriv -> pcibridge_linkctrlreg ; u_pcibridge_aspmsetting |= pdvobjpriv -> const_hostpci_aspm_setting ; if ( pcipriv -> pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL || pcipriv -> pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS ) u_pcibridge_aspmsetting &= ~ BIT ( 0 ) ; pci_write_config_byte ( bridge_pdev , ( pcipriv -> pcibridge_pciehdr_offset + 0x10 ) , u_pcibridge_aspmsetting ) ; RTW_INFO ( " \n " , ( pcipriv -> pcibridge_pciehdr_offset + 0x10 ) , u_pcibridge_aspmsetting ) ; rtw_udelay_os ( 50 ) ; aspmlevel |= pdvobjpriv -> const_devicepci_aspm_setting ; u_device_aspmsetting = pcipriv -> linkctrl_reg ; u_device_aspmsetting |= aspmlevel ; rtw_pci_platform_switch_device_pci_aspm ( padapter , u_device_aspmsetting ) ; if ( pwrpriv -> reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ ) { rtw_pci_switch_clk_req ( padapter , ( pwrpriv -> reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ ) ? 1 : 0 ) ; RT_SET_PS_LEVEL ( pwrpriv , RT_RF_OFF_LEVL_CLK_REQ ) ; } rtw_udelay_os ( 50 ) ; }
Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
 power saving We should follow the sequence to enable
 RTL8192SE first then enable Pci Bridge ASPM
 or the system will show bluescreen.
Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for power saving We should follow the sequence to enable RTL8192SE first then enable Pci Bridge ASPM or the system will show bluescreen .
/* We shall check RF Off Level for ASPM function instead of registry settings, revised by Roger, 2013.03.29. */ /* When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, */ /* we do not execute any action and return. Added by tynli. */ /* Get Bridge ASPM Support
	 * not to enable bridge aspm if bridge does not support
	 * Added by sherry 20100803
	*/ /* Get the Link Capability, it ls located at offset 0x0c from the PCIE Capability */ /*
	* Skip following settings if ASPM has already enabled, added by Roger, 2013.03.15.
	*/ /* BIT0: L0S, BIT1:L1 */ /* 4 Enable Pci Bridge ASPM */ /* Write PCI bridge PCIE-capability Link Control Register */ /* Justin: Can we change the ASPM Control register ? */ /* The system BIOS should set this register with a correct value */ /* If we change the force enable the ASPM L1/L0s, this may cause the system hang */ /* for intel host 42 device 43 */ /*Get ASPM level (with/without Clock Req)*/ /* device 43 */