XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_gtye4.c
u32 XHdmiphy1_Gtye4ClkChReconfig(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId)
{
    u16 DrpVal;
    u16 WriteVal;
    u16 CPLL_CFG0, CPLL_CFG1, CPLL_CFG2;
    u32 PllxVcoRateMHz;
    XHdmiphy1_ChannelId ChIdPll;
    XHdmiphy1_PllType PllType;
    u32 PllxClkOutMHz;
    u32 PllxClkOutDiv;
    u32 QPllxClkOutMHz;
    u32 Status = XST_SUCCESS;

    /* Obtain current DRP register value for PLL dividers. */
    Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0028, &DrpVal);
    /* Mask out clock divider bits. */
    DrpVal &= ~(XDRP_GTYE4_CHN_REG_0028_CPLL_FBDIV_MASK);
    /* Set CPLL_FBDIV. */
    WriteVal = (XHdmiphy1_NToDrpEncoding(InstancePtr, QuadId, ChId, 2) & XDRP_GTYE4_CHN_REG_0028_FLD_CPLL_FBDIV_MASK);
    DrpVal |= (WriteVal << 8);
    /* Set CPLL_FBDIV_45. */
    WriteVal = (XHdmiphy1_NToDrpEncoding(InstancePtr, QuadId, ChId, 1) & XDRP_GTYE4_CHN_REG_0028_FLD_CPLL_FBDIV_45_MASK);
    DrpVal |= (WriteVal << 7);
    /* Write new DRP register value for PLL dividers. */
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0028, DrpVal);

    /* Write CPLL Ref Clk Div. */
    Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_002A, &DrpVal);
    /* Mask out clock divider bits. */
    DrpVal &= ~(XDRP_GTYE4_CHN_REG_002A_CPLL_REFCLK_DIV_MASK);
    /* Set CPLL_REFCLK_DIV. */
    WriteVal = (XHdmiphy1_MToDrpEncoding(InstancePtr, QuadId, ChId) & XDRP_GTYE4_CHN_REG_002A_FLD_A_TXDIFFCTRL_MASK);
    DrpVal |= (WriteVal << 11);
    /* Write new DRP register value for PLL dividers. */
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_002A, DrpVal);

    /* Configure CPLL Calibration Registers */
    XHdmiphy1_CfgCpllCalPeriodandTol(InstancePtr, QuadId, ChId,
            (XHdmiphy1_IsTxUsingCpll(InstancePtr, QuadId, ChId) ?
                XHDMIPHY1_DIR_TX : XHDMIPHY1_DIR_RX),
            InstancePtr->Config.DrpClkFreq);

    PllxVcoRateMHz = XHdmiphy1_GetPllVcoFreqHz(InstancePtr, QuadId, ChId,
					XHdmiphy1_IsTxUsingCpll(InstancePtr, QuadId, ChId) ?
							XHDMIPHY1_DIR_TX : XHDMIPHY1_DIR_RX) / 1000000;
    /* CPLL VCO = Pll ClkOut */
    PllxClkOutMHz = PllxVcoRateMHz;

    /* CPLL_CFGx */
    if (PllxVcoRateMHz <= XHDMIPHY1_DRP_PLLx_VCO_RANGE1) {
	CPLL_CFG0 = XHDMIPHY1_DRP_CPLL_CFG0_VAL1;
	CPLL_CFG1 = XHDMIPHY1_DRP_CPLL_CFG1_VAL1;
	CPLL_CFG2 = XHDMIPHY1_DRP_CPLL_CFG2_VAL1;
    }
    else if (PllxVcoRateMHz <= XHDMIPHY1_DRP_PLLx_VCO_RANGE2) {
	CPLL_CFG0 = XHDMIPHY1_DRP_CPLL_CFG0_VAL2;
	CPLL_CFG1 = XHDMIPHY1_DRP_CPLL_CFG1_VAL2;
	CPLL_CFG2 = XHDMIPHY1_DRP_CPLL_CFG2_VAL2;
    }
    else {
	CPLL_CFG0 = XHDMIPHY1_DRP_CPLL_CFG0_VAL3;
	CPLL_CFG1 = XHDMIPHY1_DRP_CPLL_CFG1_VAL3;
	CPLL_CFG2 = XHDMIPHY1_DRP_CPLL_CFG2_VAL3;
    }

    /* Write new DRP register value for CPLL_CFGx. */
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_009F, CPLL_CFG0);
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00A0, CPLL_CFG1);
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00B5, CPLL_CFG2);

    /* RTX_BUF_CML_CTRL */
    /* Determine which QPLL (0/1) is active and calculate the PllClkOut */
	/* Determine PLL type. */
    PllType = XHdmiphy1_GetPllType(InstancePtr, QuadId,
			(XHdmiphy1_IsTxUsingQpll(InstancePtr, QuadId, ChId) ?
					XHDMIPHY1_DIR_TX : XHDMIPHY1_DIR_RX), ChId);

    /* Determine which channel(s) to operate on. */
    switch (PllType) {
        case XHDMIPHY1_PLL_TYPE_QPLL:
        case XHDMIPHY1_PLL_TYPE_QPLL0:
            ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN0;
            PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL1;
            break;
        case XHDMIPHY1_PLL_TYPE_QPLL1:
            ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN1;
            PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL1;
            break;
        default:
            ChIdPll = ChId;
            PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL2;
            break;
    }

    /* Get QPLLx VCO rate */
    PllxVcoRateMHz = XHdmiphy1_GetPllVcoFreqHz(InstancePtr, QuadId, ChIdPll,
						(XHdmiphy1_IsTxUsingQpll(InstancePtr, QuadId, ChId) ?
						 XHDMIPHY1_DIR_TX : XHDMIPHY1_DIR_RX)) / 1000000;
    QPllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv;

	/* Update PllxClkOutMHz value */
	PllxClkOutMHz = (PllxClkOutMHz > QPllxClkOutMHz) ?
						PllxClkOutMHz : QPllxClkOutMHz;
	/* Get RTX_BUF_CML_CTRL DRP Reg Value */
    Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00DD, &DrpVal);
    /* Mask out RTX_BUF_CML_CTRL bits */
    DrpVal &= ~XDRP_GTYE4_CHN_REG_00DD_RTX_BUF_MASK;

    if (PllxClkOutMHz < XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE1) {
	DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL1;
    }
    else if (PllxClkOutMHz < XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE2) {
	DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL2;
    }
    else if (PllxClkOutMHz < XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE3) {
	DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL3;
    }
    else if (PllxClkOutMHz < XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4) {
	DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL4;
    }
    else {
	DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL5;
    }
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00DD, DrpVal);


    return Status;
}
/*****************************************************************************/
/**
* This function will configure the channel clock settings.
*
* @param    InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param    QuadId is the GT quad ID to operate on.
* @param    ChId is the channel ID to operate on.
*
* @return
*       - XST_SUCCESS if the configuration was successful.
*       - XST_FAILURE otherwise.
*
* @note     None.
*
******************************************************************************/
This function will configure the channel clock settings.
This function will configure the channel clock settings .
u32 XHdmiphy1_Gtye4ClkChReconfig(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId)
{
    u16 DrpVal;
    u16 WriteVal;
    u16 CPLL_CFG0, CPLL_CFG1, CPLL_CFG2;
    u32 PllxVcoRateMHz;
    XHdmiphy1_ChannelId ChIdPll;
    XHdmiphy1_PllType PllType;
    u32 PllxClkOutMHz;
    u32 PllxClkOutDiv;
    u32 QPllxClkOutMHz;
    u32 Status = XST_SUCCESS;
    Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0028, &DrpVal);
    DrpVal &= ~(XDRP_GTYE4_CHN_REG_0028_CPLL_FBDIV_MASK);
    WriteVal = (XHdmiphy1_NToDrpEncoding(InstancePtr, QuadId, ChId, 2) & XDRP_GTYE4_CHN_REG_0028_FLD_CPLL_FBDIV_MASK);
    DrpVal |= (WriteVal << 8);
    WriteVal = (XHdmiphy1_NToDrpEncoding(InstancePtr, QuadId, ChId, 1) & XDRP_GTYE4_CHN_REG_0028_FLD_CPLL_FBDIV_45_MASK);
    DrpVal |= (WriteVal << 7);
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0028, DrpVal);
    Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_002A, &DrpVal);
    DrpVal &= ~(XDRP_GTYE4_CHN_REG_002A_CPLL_REFCLK_DIV_MASK);
    WriteVal = (XHdmiphy1_MToDrpEncoding(InstancePtr, QuadId, ChId) & XDRP_GTYE4_CHN_REG_002A_FLD_A_TXDIFFCTRL_MASK);
    DrpVal |= (WriteVal << 11);
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_002A, DrpVal);
    XHdmiphy1_CfgCpllCalPeriodandTol(InstancePtr, QuadId, ChId,
            (XHdmiphy1_IsTxUsingCpll(InstancePtr, QuadId, ChId) ?
                XHDMIPHY1_DIR_TX : XHDMIPHY1_DIR_RX),
            InstancePtr->Config.DrpClkFreq);
    PllxVcoRateMHz = XHdmiphy1_GetPllVcoFreqHz(InstancePtr, QuadId, ChId,
					XHdmiphy1_IsTxUsingCpll(InstancePtr, QuadId, ChId) ?
							XHDMIPHY1_DIR_TX : XHDMIPHY1_DIR_RX) / 1000000;
    PllxClkOutMHz = PllxVcoRateMHz;
    if (PllxVcoRateMHz <= XHDMIPHY1_DRP_PLLx_VCO_RANGE1) {
	CPLL_CFG0 = XHDMIPHY1_DRP_CPLL_CFG0_VAL1;
	CPLL_CFG1 = XHDMIPHY1_DRP_CPLL_CFG1_VAL1;
	CPLL_CFG2 = XHDMIPHY1_DRP_CPLL_CFG2_VAL1;
    }
    else if (PllxVcoRateMHz <= XHDMIPHY1_DRP_PLLx_VCO_RANGE2) {
	CPLL_CFG0 = XHDMIPHY1_DRP_CPLL_CFG0_VAL2;
	CPLL_CFG1 = XHDMIPHY1_DRP_CPLL_CFG1_VAL2;
	CPLL_CFG2 = XHDMIPHY1_DRP_CPLL_CFG2_VAL2;
    }
    else {
	CPLL_CFG0 = XHDMIPHY1_DRP_CPLL_CFG0_VAL3;
	CPLL_CFG1 = XHDMIPHY1_DRP_CPLL_CFG1_VAL3;
	CPLL_CFG2 = XHDMIPHY1_DRP_CPLL_CFG2_VAL3;
    }
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_009F, CPLL_CFG0);
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00A0, CPLL_CFG1);
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00B5, CPLL_CFG2);
    PllType = XHdmiphy1_GetPllType(InstancePtr, QuadId,
			(XHdmiphy1_IsTxUsingQpll(InstancePtr, QuadId, ChId) ?
					XHDMIPHY1_DIR_TX : XHDMIPHY1_DIR_RX), ChId);
    switch (PllType) {
        case XHDMIPHY1_PLL_TYPE_QPLL:
        case XHDMIPHY1_PLL_TYPE_QPLL0:
            ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN0;
            PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL1;
            break;
        case XHDMIPHY1_PLL_TYPE_QPLL1:
            ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN1;
            PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL1;
            break;
        default:
            ChIdPll = ChId;
            PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL2;
            break;
    }
    PllxVcoRateMHz = XHdmiphy1_GetPllVcoFreqHz(InstancePtr, QuadId, ChIdPll,
						(XHdmiphy1_IsTxUsingQpll(InstancePtr, QuadId, ChId) ?
						 XHDMIPHY1_DIR_TX : XHDMIPHY1_DIR_RX)) / 1000000;
    QPllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv;
	PllxClkOutMHz = (PllxClkOutMHz > QPllxClkOutMHz) ?
						PllxClkOutMHz : QPllxClkOutMHz;
    Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00DD, &DrpVal);
    DrpVal &= ~XDRP_GTYE4_CHN_REG_00DD_RTX_BUF_MASK;
    if (PllxClkOutMHz < XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE1) {
	DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL1;
    }
    else if (PllxClkOutMHz < XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE2) {
	DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL2;
    }
    else if (PllxClkOutMHz < XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE3) {
	DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL3;
    }
    else if (PllxClkOutMHz < XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4) {
	DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL4;
    }
    else {
	DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL5;
    }
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00DD, DrpVal);
    return Status;
}
u32 XHdmiphy1_Gtye4ClkChReconfig ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId ) { u16 DrpVal ; u16 WriteVal ; u16 CPLL_CFG0 , CPLL_CFG1 , CPLL_CFG2 ; u32 PllxVcoRateMHz ; XHdmiphy1_ChannelId ChIdPll ; XHdmiphy1_PllType PllType ; u32 PllxClkOutMHz ; u32 PllxClkOutDiv ; u32 QPllxClkOutMHz ; u32 Status = XST_SUCCESS ; Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0028 , & DrpVal ) ; DrpVal &= ~ ( XDRP_GTYE4_CHN_REG_0028_CPLL_FBDIV_MASK ) ; WriteVal = ( XHdmiphy1_NToDrpEncoding ( InstancePtr , QuadId , ChId , 2 ) & XDRP_GTYE4_CHN_REG_0028_FLD_CPLL_FBDIV_MASK ) ; DrpVal |= ( WriteVal << 8 ) ; WriteVal = ( XHdmiphy1_NToDrpEncoding ( InstancePtr , QuadId , ChId , 1 ) & XDRP_GTYE4_CHN_REG_0028_FLD_CPLL_FBDIV_45_MASK ) ; DrpVal |= ( WriteVal << 7 ) ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0028 , DrpVal ) ; Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_002A , & DrpVal ) ; DrpVal &= ~ ( XDRP_GTYE4_CHN_REG_002A_CPLL_REFCLK_DIV_MASK ) ; WriteVal = ( XHdmiphy1_MToDrpEncoding ( InstancePtr , QuadId , ChId ) & XDRP_GTYE4_CHN_REG_002A_FLD_A_TXDIFFCTRL_MASK ) ; DrpVal |= ( WriteVal << 11 ) ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_002A , DrpVal ) ; XHdmiphy1_CfgCpllCalPeriodandTol ( InstancePtr , QuadId , ChId , ( XHdmiphy1_IsTxUsingCpll ( InstancePtr , QuadId , ChId ) ? XHDMIPHY1_DIR_TX : XHDMIPHY1_DIR_RX ) , InstancePtr -> Config . DrpClkFreq ) ; PllxVcoRateMHz = XHdmiphy1_GetPllVcoFreqHz ( InstancePtr , QuadId , ChId , XHdmiphy1_IsTxUsingCpll ( InstancePtr , QuadId , ChId ) ? XHDMIPHY1_DIR_TX : XHDMIPHY1_DIR_RX ) / 1000000 ; PllxClkOutMHz = PllxVcoRateMHz ; if ( PllxVcoRateMHz <= XHDMIPHY1_DRP_PLLx_VCO_RANGE1 ) { CPLL_CFG0 = XHDMIPHY1_DRP_CPLL_CFG0_VAL1 ; CPLL_CFG1 = XHDMIPHY1_DRP_CPLL_CFG1_VAL1 ; CPLL_CFG2 = XHDMIPHY1_DRP_CPLL_CFG2_VAL1 ; } else if ( PllxVcoRateMHz <= XHDMIPHY1_DRP_PLLx_VCO_RANGE2 ) { CPLL_CFG0 = XHDMIPHY1_DRP_CPLL_CFG0_VAL2 ; CPLL_CFG1 = XHDMIPHY1_DRP_CPLL_CFG1_VAL2 ; CPLL_CFG2 = XHDMIPHY1_DRP_CPLL_CFG2_VAL2 ; } else { CPLL_CFG0 = XHDMIPHY1_DRP_CPLL_CFG0_VAL3 ; CPLL_CFG1 = XHDMIPHY1_DRP_CPLL_CFG1_VAL3 ; CPLL_CFG2 = XHDMIPHY1_DRP_CPLL_CFG2_VAL3 ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_009F , CPLL_CFG0 ) ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00A0 , CPLL_CFG1 ) ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00B5 , CPLL_CFG2 ) ; PllType = XHdmiphy1_GetPllType ( InstancePtr , QuadId , ( XHdmiphy1_IsTxUsingQpll ( InstancePtr , QuadId , ChId ) ? XHDMIPHY1_DIR_TX : XHDMIPHY1_DIR_RX ) , ChId ) ; switch ( PllType ) { case XHDMIPHY1_PLL_TYPE_QPLL : case XHDMIPHY1_PLL_TYPE_QPLL0 : ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN0 ; PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL1 ; break ; case XHDMIPHY1_PLL_TYPE_QPLL1 : ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN1 ; PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL1 ; break ; default : ChIdPll = ChId ; PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL2 ; break ; } PllxVcoRateMHz = XHdmiphy1_GetPllVcoFreqHz ( InstancePtr , QuadId , ChIdPll , ( XHdmiphy1_IsTxUsingQpll ( InstancePtr , QuadId , ChId ) ? XHDMIPHY1_DIR_TX : XHDMIPHY1_DIR_RX ) ) / 1000000 ; QPllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv ; PllxClkOutMHz = ( PllxClkOutMHz > QPllxClkOutMHz ) ? PllxClkOutMHz : QPllxClkOutMHz ; Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00DD , & DrpVal ) ; DrpVal &= ~ XDRP_GTYE4_CHN_REG_00DD_RTX_BUF_MASK ; if ( PllxClkOutMHz < XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE1 ) { DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL1 ; } else if ( PllxClkOutMHz < XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE2 ) { DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL2 ; } else if ( PllxClkOutMHz < XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE3 ) { DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL3 ; } else if ( PllxClkOutMHz < XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4 ) { DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL4 ; } else { DrpVal |= XHDMIPHY1_DRP_PLLx_CLKOUT_VAL5 ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00DD , DrpVal ) ; return Status ; }
This function will configure the channel clock settings.
This function will configure the channel clock settings .
/* Obtain current DRP register value for PLL dividers. */ /* Mask out clock divider bits. */ /* Set CPLL_FBDIV. */ /* Set CPLL_FBDIV_45. */ /* Write new DRP register value for PLL dividers. */ /* Write CPLL Ref Clk Div. */ /* Mask out clock divider bits. */ /* Set CPLL_REFCLK_DIV. */ /* Write new DRP register value for PLL dividers. */ /* Configure CPLL Calibration Registers */ /* CPLL VCO = Pll ClkOut */ /* CPLL_CFGx */ /* Write new DRP register value for CPLL_CFGx. */ /* RTX_BUF_CML_CTRL */ /* Determine which QPLL (0/1) is active and calculate the PllClkOut */ /* Determine PLL type. */ /* Determine which channel(s) to operate on. */ /* Get QPLLx VCO rate */ /* Update PllxClkOutMHz value */ /* Get RTX_BUF_CML_CTRL DRP Reg Value */ /* Mask out RTX_BUF_CML_CTRL bits */