XilinxProcessorIPLib/drivers/vprocss/src/xvprocss.c
int XVprocSs_CfgInitialize(XVprocSs *InstancePtr, XVprocSs_Config *CfgPtr,
		                   UINTPTR EffectiveAddr)
{
  /* Verify arguments */
  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(CfgPtr != NULL);
  Xil_AssertNonvoid(EffectiveAddr != (UINTPTR)NULL);

  /* Log the start of initialization */
  XVprocSs_LogWrite(InstancePtr, XVPROCSS_EVT_INIT, XVPROCSS_EDAT_BEGIN);

  /* Setup the instance */
  InstancePtr->Config = *CfgPtr;
  InstancePtr->Config.BaseAddress = EffectiveAddr;

  if(XVprocSs_GetSubsystemTopology(InstancePtr) >= XVPROCSS_TOPOLOGY_NUM_SUPPORTED) {
      XVprocSs_LogWrite(InstancePtr, XVPROCSS_EVT_CHK_TOPO, XVPROCSS_EDAT_FAILURE);
      return(XST_FAILURE);
  }
  XVprocSs_LogWrite(InstancePtr, XVPROCSS_EVT_CHK_TOPO, XVprocSs_GetSubsystemTopology(InstancePtr));

  /* Determine sub-cores included in the provided instance of subsystem */
  GetIncludedSubcores(InstancePtr);

  /* Initialize all included sub_cores */
  if(InstancePtr->RstAxisPtr) {
	if(XVprocSs_SubcoreInitResetAxis(InstancePtr) != XST_SUCCESS) {
      return(XST_FAILURE);
    }
  }

  if(InstancePtr->RstAximmPtr) {
	if(XVprocSs_SubcoreInitResetAximm(InstancePtr) != XST_SUCCESS) {
      return(XST_FAILURE);
    }
  }

  if(InstancePtr->RouterPtr) {
	if(XVprocSs_SubcoreInitRouter(InstancePtr) != XST_SUCCESS) {
      return(XST_FAILURE);
    }
  }

  if(InstancePtr->CscPtr) {
	if(XVprocSs_SubcoreInitCsc(InstancePtr) != XST_SUCCESS) {
      return(XST_FAILURE);
    }
  }

  if(InstancePtr->HscalerPtr) {
	if(XVprocSs_SubcoreInitHScaler(InstancePtr) != XST_SUCCESS) {
      return(XST_FAILURE);
    }
  }

  if(InstancePtr->VscalerPtr) {
	if(XVprocSs_SubcoreInitVScaler(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
  }

  if(InstancePtr->HcrsmplrPtr) {
	if(XVprocSs_SubcoreInitHCrsmplr(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
  }

  if(InstancePtr->VcrsmplrInPtr) {
	if(XVprocSs_SubcoreInitVCrsmpleIn(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
  }

  if(InstancePtr->VcrsmplrOutPtr) {
	if(XVprocSs_SubcoreInitVCrsmpleOut(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
  }

  if(InstancePtr->LboxPtr) {
	if(XVprocSs_SubcoreInitLetterbox(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
  }

  if(InstancePtr->VdmaPtr) {
	if(XVprocSs_SubcoreInitVdma(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
	/* If VDMA is included, Buffer address must be set */
    if(InstancePtr->FrameBufBaseaddr == 0) {
      XVprocSs_LogWrite(InstancePtr, XVPROCSS_EVT_CHK_BASEADDR, XVPROCSS_EDAT_FAILURE);
	  return(XST_FAILURE);
	}
  }

  if(InstancePtr->DeintPtr) {
      u32 vdmaBufReq, bufsize;

	if(XVprocSs_SubcoreInitDeinterlacer(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}

    /* Set Deinterlacer buffer offset in allocated DDR Frame Buffer memory */
    if(InstancePtr->VdmaPtr) {
      u32 Bpc; //bytes per component

      Bpc = (InstancePtr->Config.ColorDepth + 7)/8;

      //compute buffer size based on subsystem configuration
      //For 1 4K2K buffer (YUV444 16-bit) size is ~48MB
      bufsize = InstancePtr->Config.MaxWidth *
		        InstancePtr->Config.MaxHeight *
		        InstancePtr->Config.NumVidComponents *
		        Bpc;

      //VDMA requires 4 buffers for total size of ~190MB
      vdmaBufReq = InstancePtr->VdmaPtr->MaxNumFrames * bufsize;
    } else {
      vdmaBufReq = 0;
      bufsize    = 0;
    }

	/* If MADI is included, Buffer address must be set */
    if((InstancePtr->Config.HasMADI) && (InstancePtr->FrameBufBaseaddr == 0)) {
      XVprocSs_LogWrite(InstancePtr, XVPROCSS_EVT_CHK_BASEADDR, XVPROCSS_EDAT_FAILURE);
	  return(XST_FAILURE);
	}

    /* Set Deint Buffer Address Offset
     *   - Located after vdma buffers, if included
     *   - 1 4k2k buffer added as a pad between vdma and deint
     */
    InstancePtr->CtxtData.DeintBufAddr = InstancePtr->FrameBufBaseaddr +
		                                 vdmaBufReq +
										 bufsize;
  }

  /* Reset the hardware */
  XVprocSs_Reset(InstancePtr);

  /* Set subsystem to power on default state */
  SetPowerOnDefaultState(InstancePtr);

  /* Set the flag to indicate the subsystem is ready */
  InstancePtr->IsReady = XIL_COMPONENT_IS_READY;

  /* Log the end of initialization */
  XVprocSs_LogWrite(InstancePtr, XVPROCSS_EVT_INIT, XVPROCSS_EDAT_END);

  return(XST_SUCCESS);
}
/*****************************************************************************/
/**
* This function initializes the video subsystem and included sub-cores.
* This function must be called prior to using the subsystem. Initialization
* includes setting up the instance data for top level as well as all included
* sub-core therein, and ensuring the hardware is in a known stable state.
*
* @param  InstancePtr is a pointer to the Subsystem instance to be worked on.
* @param  CfgPtr points to the configuration structure associated with the
*         subsystem instance.
* @param  EffectiveAddr is the base address of the device. If address
*         translation is being used, then this parameter must reflect the
*         virtual base address. Otherwise, the physical address should be
*         used.
*
* @return XST_SUCCESS if initialization is successful else XST_FAILURE
*
******************************************************************************/
This function initializes the video subsystem and included sub-cores.
This function must be called prior to using the subsystem. Initialization
includes setting up the instance data for top level as well as all included
sub-core therein, and ensuring the hardware is in a known stable state.
This function initializes the video subsystem and included sub - cores . This function must be called prior to using the subsystem . Initialization includes setting up the instance data for top level as well as all included sub - core therein and ensuring the hardware is in a known stable state .
int XVprocSs_CfgInitialize(XVprocSs *InstancePtr, XVprocSs_Config *CfgPtr,
		                   UINTPTR EffectiveAddr)
{
  Xil_AssertNonvoid(InstancePtr != NULL);
  Xil_AssertNonvoid(CfgPtr != NULL);
  Xil_AssertNonvoid(EffectiveAddr != (UINTPTR)NULL);
  XVprocSs_LogWrite(InstancePtr, XVPROCSS_EVT_INIT, XVPROCSS_EDAT_BEGIN);
  InstancePtr->Config = *CfgPtr;
  InstancePtr->Config.BaseAddress = EffectiveAddr;
  if(XVprocSs_GetSubsystemTopology(InstancePtr) >= XVPROCSS_TOPOLOGY_NUM_SUPPORTED) {
      XVprocSs_LogWrite(InstancePtr, XVPROCSS_EVT_CHK_TOPO, XVPROCSS_EDAT_FAILURE);
      return(XST_FAILURE);
  }
  XVprocSs_LogWrite(InstancePtr, XVPROCSS_EVT_CHK_TOPO, XVprocSs_GetSubsystemTopology(InstancePtr));
  GetIncludedSubcores(InstancePtr);
  if(InstancePtr->RstAxisPtr) {
	if(XVprocSs_SubcoreInitResetAxis(InstancePtr) != XST_SUCCESS) {
      return(XST_FAILURE);
    }
  }
  if(InstancePtr->RstAximmPtr) {
	if(XVprocSs_SubcoreInitResetAximm(InstancePtr) != XST_SUCCESS) {
      return(XST_FAILURE);
    }
  }
  if(InstancePtr->RouterPtr) {
	if(XVprocSs_SubcoreInitRouter(InstancePtr) != XST_SUCCESS) {
      return(XST_FAILURE);
    }
  }
  if(InstancePtr->CscPtr) {
	if(XVprocSs_SubcoreInitCsc(InstancePtr) != XST_SUCCESS) {
      return(XST_FAILURE);
    }
  }
  if(InstancePtr->HscalerPtr) {
	if(XVprocSs_SubcoreInitHScaler(InstancePtr) != XST_SUCCESS) {
      return(XST_FAILURE);
    }
  }
  if(InstancePtr->VscalerPtr) {
	if(XVprocSs_SubcoreInitVScaler(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
  }
  if(InstancePtr->HcrsmplrPtr) {
	if(XVprocSs_SubcoreInitHCrsmplr(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
  }
  if(InstancePtr->VcrsmplrInPtr) {
	if(XVprocSs_SubcoreInitVCrsmpleIn(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
  }
  if(InstancePtr->VcrsmplrOutPtr) {
	if(XVprocSs_SubcoreInitVCrsmpleOut(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
  }
  if(InstancePtr->LboxPtr) {
	if(XVprocSs_SubcoreInitLetterbox(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
  }
  if(InstancePtr->VdmaPtr) {
	if(XVprocSs_SubcoreInitVdma(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
    if(InstancePtr->FrameBufBaseaddr == 0) {
      XVprocSs_LogWrite(InstancePtr, XVPROCSS_EVT_CHK_BASEADDR, XVPROCSS_EDAT_FAILURE);
	  return(XST_FAILURE);
	}
  }
  if(InstancePtr->DeintPtr) {
      u32 vdmaBufReq, bufsize;
	if(XVprocSs_SubcoreInitDeinterlacer(InstancePtr) != XST_SUCCESS) {
	  return(XST_FAILURE);
	}
    if(InstancePtr->VdmaPtr) {
      u32 Bpc; 
      Bpc = (InstancePtr->Config.ColorDepth + 7)/8;
      bufsize = InstancePtr->Config.MaxWidth *
		        InstancePtr->Config.MaxHeight *
		        InstancePtr->Config.NumVidComponents *
		        Bpc;
      vdmaBufReq = InstancePtr->VdmaPtr->MaxNumFrames * bufsize;
    } else {
      vdmaBufReq = 0;
      bufsize    = 0;
    }
    if((InstancePtr->Config.HasMADI) && (InstancePtr->FrameBufBaseaddr == 0)) {
      XVprocSs_LogWrite(InstancePtr, XVPROCSS_EVT_CHK_BASEADDR, XVPROCSS_EDAT_FAILURE);
	  return(XST_FAILURE);
	}
    InstancePtr->CtxtData.DeintBufAddr = InstancePtr->FrameBufBaseaddr +
		                                 vdmaBufReq +
										 bufsize;
  }
  XVprocSs_Reset(InstancePtr);
  SetPowerOnDefaultState(InstancePtr);
  InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
  XVprocSs_LogWrite(InstancePtr, XVPROCSS_EVT_INIT, XVPROCSS_EDAT_END);
  return(XST_SUCCESS);
}
int XVprocSs_CfgInitialize ( XVprocSs * InstancePtr , XVprocSs_Config * CfgPtr , UINTPTR EffectiveAddr ) { Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( CfgPtr != NULL ) ; Xil_AssertNonvoid ( EffectiveAddr != ( UINTPTR ) NULL ) ; XVprocSs_LogWrite ( InstancePtr , XVPROCSS_EVT_INIT , XVPROCSS_EDAT_BEGIN ) ; InstancePtr -> Config = * CfgPtr ; InstancePtr -> Config . BaseAddress = EffectiveAddr ; if ( XVprocSs_GetSubsystemTopology ( InstancePtr ) >= XVPROCSS_TOPOLOGY_NUM_SUPPORTED ) { XVprocSs_LogWrite ( InstancePtr , XVPROCSS_EVT_CHK_TOPO , XVPROCSS_EDAT_FAILURE ) ; return ( XST_FAILURE ) ; } XVprocSs_LogWrite ( InstancePtr , XVPROCSS_EVT_CHK_TOPO , XVprocSs_GetSubsystemTopology ( InstancePtr ) ) ; GetIncludedSubcores ( InstancePtr ) ; if ( InstancePtr -> RstAxisPtr ) { if ( XVprocSs_SubcoreInitResetAxis ( InstancePtr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } if ( InstancePtr -> RstAximmPtr ) { if ( XVprocSs_SubcoreInitResetAximm ( InstancePtr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } if ( InstancePtr -> RouterPtr ) { if ( XVprocSs_SubcoreInitRouter ( InstancePtr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } if ( InstancePtr -> CscPtr ) { if ( XVprocSs_SubcoreInitCsc ( InstancePtr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } if ( InstancePtr -> HscalerPtr ) { if ( XVprocSs_SubcoreInitHScaler ( InstancePtr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } if ( InstancePtr -> VscalerPtr ) { if ( XVprocSs_SubcoreInitVScaler ( InstancePtr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } if ( InstancePtr -> HcrsmplrPtr ) { if ( XVprocSs_SubcoreInitHCrsmplr ( InstancePtr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } if ( InstancePtr -> VcrsmplrInPtr ) { if ( XVprocSs_SubcoreInitVCrsmpleIn ( InstancePtr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } if ( InstancePtr -> VcrsmplrOutPtr ) { if ( XVprocSs_SubcoreInitVCrsmpleOut ( InstancePtr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } if ( InstancePtr -> LboxPtr ) { if ( XVprocSs_SubcoreInitLetterbox ( InstancePtr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } if ( InstancePtr -> VdmaPtr ) { if ( XVprocSs_SubcoreInitVdma ( InstancePtr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } if ( InstancePtr -> FrameBufBaseaddr == 0 ) { XVprocSs_LogWrite ( InstancePtr , XVPROCSS_EVT_CHK_BASEADDR , XVPROCSS_EDAT_FAILURE ) ; return ( XST_FAILURE ) ; } } if ( InstancePtr -> DeintPtr ) { u32 vdmaBufReq , bufsize ; if ( XVprocSs_SubcoreInitDeinterlacer ( InstancePtr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } if ( InstancePtr -> VdmaPtr ) { u32 Bpc ; Bpc = ( InstancePtr -> Config . ColorDepth + 7 ) / 8 ; bufsize = InstancePtr -> Config . MaxWidth * InstancePtr -> Config . MaxHeight * InstancePtr -> Config . NumVidComponents * Bpc ; vdmaBufReq = InstancePtr -> VdmaPtr -> MaxNumFrames * bufsize ; } else { vdmaBufReq = 0 ; bufsize = 0 ; } if ( ( InstancePtr -> Config . HasMADI ) && ( InstancePtr -> FrameBufBaseaddr == 0 ) ) { XVprocSs_LogWrite ( InstancePtr , XVPROCSS_EVT_CHK_BASEADDR , XVPROCSS_EDAT_FAILURE ) ; return ( XST_FAILURE ) ; } InstancePtr -> CtxtData . DeintBufAddr = InstancePtr -> FrameBufBaseaddr + vdmaBufReq + bufsize ; } XVprocSs_Reset ( InstancePtr ) ; SetPowerOnDefaultState ( InstancePtr ) ; InstancePtr -> IsReady = XIL_COMPONENT_IS_READY ; XVprocSs_LogWrite ( InstancePtr , XVPROCSS_EVT_INIT , XVPROCSS_EDAT_END ) ; return ( XST_SUCCESS ) ; }
This function initializes the video subsystem and included sub-cores.
This function initializes the video subsystem and included sub - cores .
/* Verify arguments */ /* Log the start of initialization */ /* Setup the instance */ /* Determine sub-cores included in the provided instance of subsystem */ /* Initialize all included sub_cores */ /* If VDMA is included, Buffer address must be set */ /* Set Deinterlacer buffer offset in allocated DDR Frame Buffer memory */ //bytes per component //compute buffer size based on subsystem configuration //For 1 4K2K buffer (YUV444 16-bit) size is ~48MB //VDMA requires 4 buffers for total size of ~190MB /* If MADI is included, Buffer address must be set */ /* Set Deint Buffer Address Offset
     *   - Located after vdma buffers, if included
     *   - 1 4k2k buffer added as a pad between vdma and deint
     */ /* Reset the hardware */ /* Set subsystem to power on default state */ /* Set the flag to indicate the subsystem is ready */ /* Log the end of initialization */