lib/sw_apps/zynqmp_fsbl/src/xfsbl_ddr_init.c
static u32 XFsbl_IicReadSpdEeprom(u8 *SpdData)
{
	XIicPs IicInstance;		/* The instance of the IIC device. */
	XIicPs_Config *ConfigIic;
	u8 TxArray;
	s32 Status;
	u32 UStatus;
	u32 Regval = 0U;

	/* Lookup for I2C-1U device */
	ConfigIic = XIicPs_LookupConfig(XPAR_PSU_I2C_1_DEVICE_ID);
	if (!ConfigIic) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}

	/* Initialize the I2C device */
	Status = XIicPs_CfgInitialize(&IicInstance, ConfigIic,
			ConfigIic->BaseAddress);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}

	/* Set the Serial Clock for I2C */
	Status = XIicPs_SetSClk(&IicInstance, XFSBL_IIC_SCLK_RATE);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}

	/*
	 * Configure I2C Mux to select DDR4 SODIMM Slave
	 * 0x08U - Enable DDR4 SODIMM module
	 */
	TxArray = 0x08U;
	XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U, XFSBL_MUX_ADDR);

	/*
	 * Wait until bus is idle to start another transfer.
	 */
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval & XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}

	/*
	 * Get Configuration to confirm the selection of the slave
	 * device.
	 */
	Status = XIicPs_MasterRecvPolled(&IicInstance, SpdData, 1U,
			XFSBL_MUX_ADDR);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	/*
	 * Wait until bus is idle to start another transfer.
	 */
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}

	/*
	 * Set SODIMM control address to enable access to lower
	 * EEPROM page (0U to 255U Bytes).
	 * 0x00U - Enable Read of Lower Page from EEPROM
	 */
	TxArray = 0x00U;
	XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U,
			XFSBL_SODIMM_CONTROL_ADDR_LOW);
	/*
	 * Wait until bus is idle to start another transfer.
	 */
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}

	/*
	 * Configure SODIMM Slave address to select starting address of the
	 * read bytes.
	 * 0x00U - Set starting byte address of read Lowe Page from EEPROM
	 * This will result in to starting address of 0x149U (0x100U + 0x49U) in
	 * the EEPROM.
	 */
	TxArray = 0x00U;
	XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U,
			XFSBL_SODIMM_SLAVE_ADDR);
	/*
	 * Wait until bus is idle to start another transfer.
	 */
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}

	/*
	 * Receive the Data of 256U Bytes from SPD EEPROM via I2C.
	 */
	Status = XIicPs_MasterRecvPolled(&IicInstance, SpdData, 256U,
			XFSBL_SODIMM_SLAVE_ADDR);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}

	/*
	 * Wait until bus is idle.
	 */
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}


	/*
	 * Set SODIMM control address to enable access to upper
	 * EEPROM page (256U to 511U Bytes).
	 * 0x01U - Enable Read of Upper Page from EEPROM
	 */
	TxArray = 0x01U;
	XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U,
			XFSBL_SODIMM_CONTROL_ADDR_HIGH);
	/*
	 * Wait until bus is idle to start another transfer.
	 */
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}

	/*
	 * Configure SODIMM Slave address to select starting address of the
	 * read bytes.
	 * 0x00U - Set starting byte address of read Upper Page from EEPROM
	 * This will result in to starting address of 0x149U (0x100U + 0x49U) in
	 * the EEPROM.
	 */
	TxArray = 0x00U;
	XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U,
			XFSBL_SODIMM_SLAVE_ADDR);
	/*
	 * Wait until bus is idle to start another transfer.
	 */
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}

	/*
	 * Receive the Data of 256U Bytes from SPD EEPROM via I2C.
	 */
	Status = XIicPs_MasterRecvPolled(&IicInstance, &SpdData[256U], 256U,
			XFSBL_SODIMM_SLAVE_ADDR);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}

	/*
	 * Wait until bus is idle.
	 */
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}

	UStatus = XFSBL_SUCCESS;

END:
	return UStatus;
}
/*****************************************************************************/
/**
 * This function Reads the DDR4 SPD from EEPROM via I2C
 *
 * @param	DdrDataPtr is pointer to DDR Initialization Data Structure
 *
 * @return	returns the error codes described in xfsbl_error.h on any error
 *			returns XFSBL_SUCCESS on success
 *
 *****************************************************************************/
This function Reads the DDR4 SPD from EEPROM via I2C
@param       DdrDataPtr is pointer to DDR Initialization Data Structure

@return      returns the error codes described in xfsbl_error.h on any error
returns XFSBL_SUCCESS on success
This function Reads the DDR4 SPD from EEPROM via I2C @param DdrDataPtr is pointer to DDR Initialization Data Structure @return returns the error codes described in xfsbl_error . h on any error returns XFSBL_SUCCESS on success
static u32 XFsbl_IicReadSpdEeprom(u8 *SpdData)
{
	XIicPs IicInstance;		
	XIicPs_Config *ConfigIic;
	u8 TxArray;
	s32 Status;
	u32 UStatus;
	u32 Regval = 0U;
	ConfigIic = XIicPs_LookupConfig(XPAR_PSU_I2C_1_DEVICE_ID);
	if (!ConfigIic) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	Status = XIicPs_CfgInitialize(&IicInstance, ConfigIic,
			ConfigIic->BaseAddress);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	Status = XIicPs_SetSClk(&IicInstance, XFSBL_IIC_SCLK_RATE);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	TxArray = 0x08U;
	XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U, XFSBL_MUX_ADDR);
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval & XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	Status = XIicPs_MasterRecvPolled(&IicInstance, SpdData, 1U,
			XFSBL_MUX_ADDR);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	TxArray = 0x00U;
	XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U,
			XFSBL_SODIMM_CONTROL_ADDR_LOW);
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	TxArray = 0x00U;
	XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U,
			XFSBL_SODIMM_SLAVE_ADDR);
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	Status = XIicPs_MasterRecvPolled(&IicInstance, SpdData, 256U,
			XFSBL_SODIMM_SLAVE_ADDR);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	TxArray = 0x01U;
	XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U,
			XFSBL_SODIMM_CONTROL_ADDR_HIGH);
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	TxArray = 0x00U;
	XIicPs_MasterSendPolled(&IicInstance, &TxArray, 1U,
			XFSBL_SODIMM_SLAVE_ADDR);
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	Status = XIicPs_MasterRecvPolled(&IicInstance, &SpdData[256U], 256U,
			XFSBL_SODIMM_SLAVE_ADDR);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	Status = XFsbl_PollTimeout(IicInstance.Config.BaseAddress +
			XIICPS_SR_OFFSET, Regval, (Regval &
				XIICPS_SR_BA_MASK) == 0x0U,
			XFSBL_IIC_BUS_TIMEOUT);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_FAILURE;
		goto END;
	}
	UStatus = XFSBL_SUCCESS;
END:
	return UStatus;
}
static u32 XFsbl_IicReadSpdEeprom ( u8 * SpdData ) { XIicPs IicInstance ; XIicPs_Config * ConfigIic ; u8 TxArray ; s32 Status ; u32 UStatus ; u32 Regval = 0U ; ConfigIic = XIicPs_LookupConfig ( XPAR_PSU_I2C_1_DEVICE_ID ) ; if ( ! ConfigIic ) { UStatus = XFSBL_FAILURE ; goto END ; } Status = XIicPs_CfgInitialize ( & IicInstance , ConfigIic , ConfigIic -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } Status = XIicPs_SetSClk ( & IicInstance , XFSBL_IIC_SCLK_RATE ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } TxArray = 0x08U ; XIicPs_MasterSendPolled ( & IicInstance , & TxArray , 1U , XFSBL_MUX_ADDR ) ; Status = XFsbl_PollTimeout ( IicInstance . Config . BaseAddress + XIICPS_SR_OFFSET , Regval , ( Regval & XIICPS_SR_BA_MASK ) == 0x0U , XFSBL_IIC_BUS_TIMEOUT ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } Status = XIicPs_MasterRecvPolled ( & IicInstance , SpdData , 1U , XFSBL_MUX_ADDR ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } Status = XFsbl_PollTimeout ( IicInstance . Config . BaseAddress + XIICPS_SR_OFFSET , Regval , ( Regval & XIICPS_SR_BA_MASK ) == 0x0U , XFSBL_IIC_BUS_TIMEOUT ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } TxArray = 0x00U ; XIicPs_MasterSendPolled ( & IicInstance , & TxArray , 1U , XFSBL_SODIMM_CONTROL_ADDR_LOW ) ; Status = XFsbl_PollTimeout ( IicInstance . Config . BaseAddress + XIICPS_SR_OFFSET , Regval , ( Regval & XIICPS_SR_BA_MASK ) == 0x0U , XFSBL_IIC_BUS_TIMEOUT ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } TxArray = 0x00U ; XIicPs_MasterSendPolled ( & IicInstance , & TxArray , 1U , XFSBL_SODIMM_SLAVE_ADDR ) ; Status = XFsbl_PollTimeout ( IicInstance . Config . BaseAddress + XIICPS_SR_OFFSET , Regval , ( Regval & XIICPS_SR_BA_MASK ) == 0x0U , XFSBL_IIC_BUS_TIMEOUT ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } Status = XIicPs_MasterRecvPolled ( & IicInstance , SpdData , 256U , XFSBL_SODIMM_SLAVE_ADDR ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } Status = XFsbl_PollTimeout ( IicInstance . Config . BaseAddress + XIICPS_SR_OFFSET , Regval , ( Regval & XIICPS_SR_BA_MASK ) == 0x0U , XFSBL_IIC_BUS_TIMEOUT ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } TxArray = 0x01U ; XIicPs_MasterSendPolled ( & IicInstance , & TxArray , 1U , XFSBL_SODIMM_CONTROL_ADDR_HIGH ) ; Status = XFsbl_PollTimeout ( IicInstance . Config . BaseAddress + XIICPS_SR_OFFSET , Regval , ( Regval & XIICPS_SR_BA_MASK ) == 0x0U , XFSBL_IIC_BUS_TIMEOUT ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } TxArray = 0x00U ; XIicPs_MasterSendPolled ( & IicInstance , & TxArray , 1U , XFSBL_SODIMM_SLAVE_ADDR ) ; Status = XFsbl_PollTimeout ( IicInstance . Config . BaseAddress + XIICPS_SR_OFFSET , Regval , ( Regval & XIICPS_SR_BA_MASK ) == 0x0U , XFSBL_IIC_BUS_TIMEOUT ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } Status = XIicPs_MasterRecvPolled ( & IicInstance , & SpdData [ 256U ] , 256U , XFSBL_SODIMM_SLAVE_ADDR ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } Status = XFsbl_PollTimeout ( IicInstance . Config . BaseAddress + XIICPS_SR_OFFSET , Regval , ( Regval & XIICPS_SR_BA_MASK ) == 0x0U , XFSBL_IIC_BUS_TIMEOUT ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_FAILURE ; goto END ; } UStatus = XFSBL_SUCCESS ; END : return UStatus ; }
This function Reads the DDR4 SPD from EEPROM via I2C
 @param       DdrDataPtr is pointer to DDR Initialization Data Structure
This function Reads the DDR4 SPD from EEPROM via I2C @param DdrDataPtr is pointer to DDR Initialization Data Structure
/* The instance of the IIC device. */ /* Lookup for I2C-1U device */ /* Initialize the I2C device */ /* Set the Serial Clock for I2C */ /*
	 * Configure I2C Mux to select DDR4 SODIMM Slave
	 * 0x08U - Enable DDR4 SODIMM module
	 */ /*
	 * Wait until bus is idle to start another transfer.
	 */ /*
	 * Get Configuration to confirm the selection of the slave
	 * device.
	 */ /*
	 * Wait until bus is idle to start another transfer.
	 */ /*
	 * Set SODIMM control address to enable access to lower
	 * EEPROM page (0U to 255U Bytes).
	 * 0x00U - Enable Read of Lower Page from EEPROM
	 */ /*
	 * Wait until bus is idle to start another transfer.
	 */ /*
	 * Configure SODIMM Slave address to select starting address of the
	 * read bytes.
	 * 0x00U - Set starting byte address of read Lowe Page from EEPROM
	 * This will result in to starting address of 0x149U (0x100U + 0x49U) in
	 * the EEPROM.
	 */ /*
	 * Wait until bus is idle to start another transfer.
	 */ /*
	 * Receive the Data of 256U Bytes from SPD EEPROM via I2C.
	 */ /*
	 * Wait until bus is idle.
	 */ /*
	 * Set SODIMM control address to enable access to upper
	 * EEPROM page (256U to 511U Bytes).
	 * 0x01U - Enable Read of Upper Page from EEPROM
	 */ /*
	 * Wait until bus is idle to start another transfer.
	 */ /*
	 * Configure SODIMM Slave address to select starting address of the
	 * read bytes.
	 * 0x00U - Set starting byte address of read Upper Page from EEPROM
	 * This will result in to starting address of 0x149U (0x100U + 0x49U) in
	 * the EEPROM.
	 */ /*
	 * Wait until bus is idle to start another transfer.
	 */ /*
	 * Receive the Data of 256U Bytes from SPD EEPROM via I2C.
	 */ /*
	 * Wait until bus is idle.
	 */