src/arch/socs/stm32f429/C/soc-rcc.c
void soc_rcc_reset(void)
{
    /* Reset the RCC clock configuration to the default reset state */
    /* Set HSION bit */
    set_reg_bits(r_CORTEX_M_RCC_CR, RCC_CR_HSION);

    /* Reset CFGR register */
    write_reg_value(r_CORTEX_M_RCC_CFGR, 0x00000000);

    /* Reset HSEON, CSSON and PLLON bits */
    clear_reg_bits(r_CORTEX_M_RCC_CR,
                   RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);

    /* Reset PLLCFGR register */
    write_reg_value(r_CORTEX_M_RCC_PLLCFGR, 0x24003010);

    /* Reset HSEBYP bit */
    clear_reg_bits(r_CORTEX_M_RCC_CR, RCC_CR_HSEBYP);

    /* Reset all interrupts */
    write_reg_value(r_CORTEX_M_RCC_CIR, 0x00000000);

    full_memory_barrier();
}
/*
 * TODO: some of the bellowing code should be M4 generic. Yet, check if all
 * these registers are M4 generic or STM32F4 core specific
 */
some of the bellowing code should be M4 generic. Yet, check if all
these registers are M4 generic or STM32F4 core specific
some of the bellowing code should be M4 generic . Yet check if all these registers are M4 generic or STM32F4 core specific
void soc_rcc_reset(void)
{
    set_reg_bits(r_CORTEX_M_RCC_CR, RCC_CR_HSION);
    write_reg_value(r_CORTEX_M_RCC_CFGR, 0x00000000);
    clear_reg_bits(r_CORTEX_M_RCC_CR,
                   RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
    write_reg_value(r_CORTEX_M_RCC_PLLCFGR, 0x24003010);
    clear_reg_bits(r_CORTEX_M_RCC_CR, RCC_CR_HSEBYP);
    write_reg_value(r_CORTEX_M_RCC_CIR, 0x00000000);
    full_memory_barrier();
}
void soc_rcc_reset ( void ) { set_reg_bits ( r_CORTEX_M_RCC_CR , RCC_CR_HSION ) ; write_reg_value ( r_CORTEX_M_RCC_CFGR , 0x00000000 ) ; clear_reg_bits ( r_CORTEX_M_RCC_CR , RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON ) ; write_reg_value ( r_CORTEX_M_RCC_PLLCFGR , 0x24003010 ) ; clear_reg_bits ( r_CORTEX_M_RCC_CR , RCC_CR_HSEBYP ) ; write_reg_value ( r_CORTEX_M_RCC_CIR , 0x00000000 ) ; full_memory_barrier ( ) ; }
TODO: some of the bellowing code should be M4 generic.
TODO : some of the bellowing code should be M4 generic .
/* Reset the RCC clock configuration to the default reset state */ /* Set HSION bit */ /* Reset CFGR register */ /* Reset HSEON, CSSON and PLLON bits */ /* Reset PLLCFGR register */ /* Reset HSEBYP bit */ /* Reset all interrupts */