XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bdring.c
int XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr)
{
	UINTPTR RegBase;
	int RingIndex = RingPtr->RingIndex;

	if (!XAxiDma_BdRingHwIsStarted(RingPtr)) {
		/* Start the hardware
		*/
		RegBase = RingPtr->ChanBase;
		XAxiDma_WriteReg(RegBase, XAXIDMA_CR_OFFSET,
			XAxiDma_ReadReg(RegBase, XAXIDMA_CR_OFFSET)
			| XAXIDMA_CR_RUNSTOP_MASK);
	}

	if (XAxiDma_BdRingHwIsStarted(RingPtr)) {
		/* Note as started */
		RingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED;

		/* If there are unprocessed BDs then we want the channel to begin
		 * processing right away
		 */
		if (RingPtr->HwCnt > 0) {

			XAXIDMA_CACHE_INVALIDATE(RingPtr->HwTail);
			if (RingPtr->Cyclic) {
				XAxiDma_WriteReg(RingPtr->ChanBase,
						 XAXIDMA_TDESC_OFFSET,
						 (u32)XAXIDMA_VIRT_TO_PHYS(RingPtr->CyclicBd));
				if (RingPtr->Addr_ext)
					XAxiDma_WriteReg(RingPtr->ChanBase,
							 XAXIDMA_TDESC_MSB_OFFSET,
							 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->CyclicBd)));
				return XST_SUCCESS;
			}

			if ((XAxiDma_BdRead(RingPtr->HwTail,
				    XAXIDMA_BD_STS_OFFSET) &
				XAXIDMA_BD_STS_COMPLETE_MASK) == 0) {
				if (RingPtr->IsRxChannel) {
					if (!RingIndex) {
						XAxiDma_WriteReg(RingPtr->ChanBase,
							XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK));
						if (RingPtr->Addr_ext)
							XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET,
								 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)));
					}
					else {
						XAxiDma_WriteReg(RingPtr->ChanBase,
							(XAXIDMA_RX_TDESC0_OFFSET +
							(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
							(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK ));
						if (RingPtr->Addr_ext)
							XAxiDma_WriteReg(RingPtr->ChanBase,
								(XAXIDMA_RX_TDESC0_MSB_OFFSET +
								(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
								UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)));
					}
				}
				else {
					XAxiDma_WriteReg(RingPtr->ChanBase,
							XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK));
					if (RingPtr->Addr_ext)
						XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET,
								 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)));
				}
			}
		}

		return XST_SUCCESS;
	}

	return XST_DMA_ERROR;
}
/*****************************************************************************/
/**
 * Start a DMA channel and
 * Allow DMA transactions to commence on a given channel if descriptors are
 * ready to be processed.
 *
 * After a DMA channel is started, it is not halted, and it is idle (no active
 * DMA transfers).
 *
 * @param	RingPtr is the Channel instance to be worked on
 *
 * @return
 *		- XST_SUCCESS upon success
 *		- XST_DMA_ERROR if no valid BD available to put into current
 *		BD register
 *
 * @note	This function can be used only when DMA is in SG mode
 *
 *****************************************************************************/
Start a DMA channel and
Allow DMA transactions to commence on a given channel if descriptors are
ready to be processed.

After a DMA channel is started, it is not halted, and it is idle (no active
DMA transfers).

@param       RingPtr is the Channel instance to be worked on

@return
- XST_SUCCESS upon success
- XST_DMA_ERROR if no valid BD available to put into current
BD register

@note        This function can be used only when DMA is in SG mode
Start a DMA channel and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed . After a DMA channel is started it is not halted and it is idle ( no active DMA transfers ) . @param RingPtr is the Channel instance to be worked on @return - XST_SUCCESS upon success - XST_DMA_ERROR if no valid BD available to put into current BD register @note This function can be used only when DMA is in SG mode
int XAxiDma_StartBdRingHw(XAxiDma_BdRing * RingPtr)
{
	UINTPTR RegBase;
	int RingIndex = RingPtr->RingIndex;
	if (!XAxiDma_BdRingHwIsStarted(RingPtr)) {
		RegBase = RingPtr->ChanBase;
		XAxiDma_WriteReg(RegBase, XAXIDMA_CR_OFFSET,
			XAxiDma_ReadReg(RegBase, XAXIDMA_CR_OFFSET)
			| XAXIDMA_CR_RUNSTOP_MASK);
	}
	if (XAxiDma_BdRingHwIsStarted(RingPtr)) {
		RingPtr->RunState = AXIDMA_CHANNEL_NOT_HALTED;
		if (RingPtr->HwCnt > 0) {
			XAXIDMA_CACHE_INVALIDATE(RingPtr->HwTail);
			if (RingPtr->Cyclic) {
				XAxiDma_WriteReg(RingPtr->ChanBase,
						 XAXIDMA_TDESC_OFFSET,
						 (u32)XAXIDMA_VIRT_TO_PHYS(RingPtr->CyclicBd));
				if (RingPtr->Addr_ext)
					XAxiDma_WriteReg(RingPtr->ChanBase,
							 XAXIDMA_TDESC_MSB_OFFSET,
							 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->CyclicBd)));
				return XST_SUCCESS;
			}
			if ((XAxiDma_BdRead(RingPtr->HwTail,
				    XAXIDMA_BD_STS_OFFSET) &
				XAXIDMA_BD_STS_COMPLETE_MASK) == 0) {
				if (RingPtr->IsRxChannel) {
					if (!RingIndex) {
						XAxiDma_WriteReg(RingPtr->ChanBase,
							XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK));
						if (RingPtr->Addr_ext)
							XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET,
								 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)));
					}
					else {
						XAxiDma_WriteReg(RingPtr->ChanBase,
							(XAXIDMA_RX_TDESC0_OFFSET +
							(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
							(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK ));
						if (RingPtr->Addr_ext)
							XAxiDma_WriteReg(RingPtr->ChanBase,
								(XAXIDMA_RX_TDESC0_MSB_OFFSET +
								(RingIndex - 1) * XAXIDMA_RX_NDESC_OFFSET),
								UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)));
					}
				}
				else {
					XAxiDma_WriteReg(RingPtr->ChanBase,
							XAXIDMA_TDESC_OFFSET, (XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail) & XAXIDMA_DESC_LSB_MASK));
					if (RingPtr->Addr_ext)
						XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_TDESC_MSB_OFFSET,
								 UPPER_32_BITS(XAXIDMA_VIRT_TO_PHYS(RingPtr->HwTail)));
				}
			}
		}
		return XST_SUCCESS;
	}
	return XST_DMA_ERROR;
}
int XAxiDma_StartBdRingHw ( XAxiDma_BdRing * RingPtr ) { UINTPTR RegBase ; int RingIndex = RingPtr -> RingIndex ; if ( ! XAxiDma_BdRingHwIsStarted ( RingPtr ) ) { RegBase = RingPtr -> ChanBase ; XAxiDma_WriteReg ( RegBase , XAXIDMA_CR_OFFSET , XAxiDma_ReadReg ( RegBase , XAXIDMA_CR_OFFSET ) | XAXIDMA_CR_RUNSTOP_MASK ) ; } if ( XAxiDma_BdRingHwIsStarted ( RingPtr ) ) { RingPtr -> RunState = AXIDMA_CHANNEL_NOT_HALTED ; if ( RingPtr -> HwCnt > 0 ) { XAXIDMA_CACHE_INVALIDATE ( RingPtr -> HwTail ) ; if ( RingPtr -> Cyclic ) { XAxiDma_WriteReg ( RingPtr -> ChanBase , XAXIDMA_TDESC_OFFSET , ( u32 ) XAXIDMA_VIRT_TO_PHYS ( RingPtr -> CyclicBd ) ) ; if ( RingPtr -> Addr_ext ) XAxiDma_WriteReg ( RingPtr -> ChanBase , XAXIDMA_TDESC_MSB_OFFSET , UPPER_32_BITS ( XAXIDMA_VIRT_TO_PHYS ( RingPtr -> CyclicBd ) ) ) ; return XST_SUCCESS ; } if ( ( XAxiDma_BdRead ( RingPtr -> HwTail , XAXIDMA_BD_STS_OFFSET ) & XAXIDMA_BD_STS_COMPLETE_MASK ) == 0 ) { if ( RingPtr -> IsRxChannel ) { if ( ! RingIndex ) { XAxiDma_WriteReg ( RingPtr -> ChanBase , XAXIDMA_TDESC_OFFSET , ( XAXIDMA_VIRT_TO_PHYS ( RingPtr -> HwTail ) & XAXIDMA_DESC_LSB_MASK ) ) ; if ( RingPtr -> Addr_ext ) XAxiDma_WriteReg ( RingPtr -> ChanBase , XAXIDMA_TDESC_MSB_OFFSET , UPPER_32_BITS ( XAXIDMA_VIRT_TO_PHYS ( RingPtr -> HwTail ) ) ) ; } else { XAxiDma_WriteReg ( RingPtr -> ChanBase , ( XAXIDMA_RX_TDESC0_OFFSET + ( RingIndex - 1 ) * XAXIDMA_RX_NDESC_OFFSET ) , ( XAXIDMA_VIRT_TO_PHYS ( RingPtr -> HwTail ) & XAXIDMA_DESC_LSB_MASK ) ) ; if ( RingPtr -> Addr_ext ) XAxiDma_WriteReg ( RingPtr -> ChanBase , ( XAXIDMA_RX_TDESC0_MSB_OFFSET + ( RingIndex - 1 ) * XAXIDMA_RX_NDESC_OFFSET ) , UPPER_32_BITS ( XAXIDMA_VIRT_TO_PHYS ( RingPtr -> HwTail ) ) ) ; } } else { XAxiDma_WriteReg ( RingPtr -> ChanBase , XAXIDMA_TDESC_OFFSET , ( XAXIDMA_VIRT_TO_PHYS ( RingPtr -> HwTail ) & XAXIDMA_DESC_LSB_MASK ) ) ; if ( RingPtr -> Addr_ext ) XAxiDma_WriteReg ( RingPtr -> ChanBase , XAXIDMA_TDESC_MSB_OFFSET , UPPER_32_BITS ( XAXIDMA_VIRT_TO_PHYS ( RingPtr -> HwTail ) ) ) ; } } } return XST_SUCCESS ; } return XST_DMA_ERROR ; }
Start a DMA channel and
 Allow DMA transactions to commence on a given channel if descriptors are
 ready to be processed.
Start a DMA channel and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed .
/* Start the hardware
		*/ /* Note as started */ /* If there are unprocessed BDs then we want the channel to begin
		 * processing right away
		 */