src/dpdk/drivers/net/qede/base/ecore_cxt.c
enum _ecore_status_t
ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
			    enum ecore_cxt_elem_type elem_type,
			    u32 iid)
{
	u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
	struct ecore_ilt_client_cfg *p_cli;
	struct ecore_ilt_cli_blk *p_blk;
	struct ecore_ptt *p_ptt;
	dma_addr_t p_phys;
	u64 ilt_hw_entry;
	void *p_virt;
	enum _ecore_status_t rc = ECORE_SUCCESS;

	switch (elem_type) {
	case ECORE_ELEM_CXT:
		p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
		elem_size = CONN_CXT_SIZE(p_hwfn);
		p_blk = &p_cli->pf_blks[CDUC_BLK];
		break;
	case ECORE_ELEM_SRQ:
		p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
		elem_size = SRQ_CXT_SIZE;
		p_blk = &p_cli->pf_blks[SRQ_BLK];
		break;
	case ECORE_ELEM_TASK:
		p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
		elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
		p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
		break;
	default:
		DP_NOTICE(p_hwfn, false,
			  "ECORE_INVALID elem type = %d", elem_type);
		return ECORE_INVAL;
	}

	/* Calculate line in ilt */
	hw_p_size = p_cli->p_size.val;
	elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
	line = p_blk->start_line + (iid / elems_per_p);
	shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;

	/* If line is already allocated, do nothing, otherwise allocate it and
	 * write it to the PSWRQ2 registers.
	 * This section can be run in parallel from different contexts and thus
	 * a mutex protection is needed.
	 */

	OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);

	if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr)
		goto out0;

	p_ptt = ecore_ptt_acquire(p_hwfn);
	if (!p_ptt) {
		DP_NOTICE(p_hwfn, false,
			  "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
		rc = ECORE_TIMEOUT;
		goto out0;
	}

	p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
					 &p_phys,
					 p_blk->real_size_in_page);
	if (!p_virt) {
		rc = ECORE_NOMEM;
		goto out1;
	}
	OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);

	p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr = p_virt;
	p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr = p_phys;
	p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
		p_blk->real_size_in_page;

	/* compute absolute offset */
	reg_offset = PSWRQ2_REG_ILT_MEMORY +
		     (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);

	ilt_hw_entry = 0;
	SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
	SET_FIELD(ilt_hw_entry,
		  ILT_ENTRY_PHY_ADDR,
		 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr >> 12));

/* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */

	ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
			    reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
			    OSAL_NULL /* default parameters */);

out1:
	ecore_ptt_release(p_hwfn, p_ptt);
out0:
	OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);

	return rc;
}
/* This function is very RoCE oriented, if another protocol in the future
 * will want this feature we'll need to modify the function to be more generic
 */
This function is very RoCE oriented, if another protocol in the future
will want this feature we'll need to modify the function to be more generic
This function is very RoCE oriented if another protocol in the future will want this feature we ' ll need to modify the function to be more generic
enum _ecore_status_t
ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
			    enum ecore_cxt_elem_type elem_type,
			    u32 iid)
{
	u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
	struct ecore_ilt_client_cfg *p_cli;
	struct ecore_ilt_cli_blk *p_blk;
	struct ecore_ptt *p_ptt;
	dma_addr_t p_phys;
	u64 ilt_hw_entry;
	void *p_virt;
	enum _ecore_status_t rc = ECORE_SUCCESS;
	switch (elem_type) {
	case ECORE_ELEM_CXT:
		p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
		elem_size = CONN_CXT_SIZE(p_hwfn);
		p_blk = &p_cli->pf_blks[CDUC_BLK];
		break;
	case ECORE_ELEM_SRQ:
		p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
		elem_size = SRQ_CXT_SIZE;
		p_blk = &p_cli->pf_blks[SRQ_BLK];
		break;
	case ECORE_ELEM_TASK:
		p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
		elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
		p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
		break;
	default:
		DP_NOTICE(p_hwfn, false,
			  "ECORE_INVALID elem type = %d", elem_type);
		return ECORE_INVAL;
	}
	hw_p_size = p_cli->p_size.val;
	elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
	line = p_blk->start_line + (iid / elems_per_p);
	shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
	OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
	if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr)
		goto out0;
	p_ptt = ecore_ptt_acquire(p_hwfn);
	if (!p_ptt) {
		DP_NOTICE(p_hwfn, false,
			  "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
		rc = ECORE_TIMEOUT;
		goto out0;
	}
	p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
					 &p_phys,
					 p_blk->real_size_in_page);
	if (!p_virt) {
		rc = ECORE_NOMEM;
		goto out1;
	}
	OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
	p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr = p_virt;
	p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr = p_phys;
	p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
		p_blk->real_size_in_page;
	reg_offset = PSWRQ2_REG_ILT_MEMORY +
		     (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
	ilt_hw_entry = 0;
	SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
	SET_FIELD(ilt_hw_entry,
		  ILT_ENTRY_PHY_ADDR,
		 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr >> 12));
	ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
			    reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
			    OSAL_NULL );
out1:
	ecore_ptt_release(p_hwfn, p_ptt);
out0:
	OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
	return rc;
}
enum _ecore_status_t ecore_cxt_dynamic_ilt_alloc ( struct ecore_hwfn * p_hwfn , enum ecore_cxt_elem_type elem_type , u32 iid ) { u32 reg_offset , shadow_line , elem_size , hw_p_size , elems_per_p , line ; struct ecore_ilt_client_cfg * p_cli ; struct ecore_ilt_cli_blk * p_blk ; struct ecore_ptt * p_ptt ; dma_addr_t p_phys ; u64 ilt_hw_entry ; void * p_virt ; enum _ecore_status_t rc = ECORE_SUCCESS ; switch ( elem_type ) { case ECORE_ELEM_CXT : p_cli = & p_hwfn -> p_cxt_mngr -> clients [ ILT_CLI_CDUC ] ; elem_size = CONN_CXT_SIZE ( p_hwfn ) ; p_blk = & p_cli -> pf_blks [ CDUC_BLK ] ; break ; case ECORE_ELEM_SRQ : p_cli = & p_hwfn -> p_cxt_mngr -> clients [ ILT_CLI_TSDM ] ; elem_size = SRQ_CXT_SIZE ; p_blk = & p_cli -> pf_blks [ SRQ_BLK ] ; break ; case ECORE_ELEM_TASK : p_cli = & p_hwfn -> p_cxt_mngr -> clients [ ILT_CLI_CDUT ] ; elem_size = TYPE1_TASK_CXT_SIZE ( p_hwfn ) ; p_blk = & p_cli -> pf_blks [ CDUT_SEG_BLK ( ECORE_CXT_ROCE_TID_SEG ) ] ; break ; default : DP_NOTICE ( p_hwfn , false , " " , elem_type ) ; return ECORE_INVAL ; } hw_p_size = p_cli -> p_size . val ; elems_per_p = ILT_PAGE_IN_BYTES ( hw_p_size ) / elem_size ; line = p_blk -> start_line + ( iid / elems_per_p ) ; shadow_line = line - p_hwfn -> p_cxt_mngr -> pf_start_line ; OSAL_MUTEX_ACQUIRE ( & p_hwfn -> p_cxt_mngr -> mutex ) ; if ( p_hwfn -> p_cxt_mngr -> ilt_shadow [ shadow_line ] . virt_addr ) goto out0 ; p_ptt = ecore_ptt_acquire ( p_hwfn ) ; if ( ! p_ptt ) { DP_NOTICE ( p_hwfn , false , " " ) ; rc = ECORE_TIMEOUT ; goto out0 ; } p_virt = OSAL_DMA_ALLOC_COHERENT ( p_hwfn -> p_dev , & p_phys , p_blk -> real_size_in_page ) ; if ( ! p_virt ) { rc = ECORE_NOMEM ; goto out1 ; } OSAL_MEM_ZERO ( p_virt , p_blk -> real_size_in_page ) ; p_hwfn -> p_cxt_mngr -> ilt_shadow [ shadow_line ] . virt_addr = p_virt ; p_hwfn -> p_cxt_mngr -> ilt_shadow [ shadow_line ] . phys_addr = p_phys ; p_hwfn -> p_cxt_mngr -> ilt_shadow [ shadow_line ] . size = p_blk -> real_size_in_page ; reg_offset = PSWRQ2_REG_ILT_MEMORY + ( line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS ) ; ilt_hw_entry = 0 ; SET_FIELD ( ilt_hw_entry , ILT_ENTRY_VALID , 1ULL ) ; SET_FIELD ( ilt_hw_entry , ILT_ENTRY_PHY_ADDR , ( p_hwfn -> p_cxt_mngr -> ilt_shadow [ shadow_line ] . phys_addr >> 12 ) ) ; ecore_dmae_host2grc ( p_hwfn , p_ptt , ( u64 ) ( osal_uintptr_t ) & ilt_hw_entry , reg_offset , sizeof ( ilt_hw_entry ) / sizeof ( u32 ) , OSAL_NULL ) ; out1 : ecore_ptt_release ( p_hwfn , p_ptt ) ; out0 : OSAL_MUTEX_RELEASE ( & p_hwfn -> p_cxt_mngr -> mutex ) ; return rc ; }
This function is very RoCE oriented, if another protocol in the future
 will want this feature we'll need to modify the function to be more generic
This function is very RoCE oriented if another protocol in the future will want this feature we ' ll need to modify the function to be more generic
/* Calculate line in ilt */ /* If line is already allocated, do nothing, otherwise allocate it and
	 * write it to the PSWRQ2 registers.
	 * This section can be run in parallel from different contexts and thus
	 * a mutex protection is needed.
	 */ /* compute absolute offset */ /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */ /* default parameters */