XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_gtye4.c
u32 XHdmiphy1_Gtye4TxChReconfig(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId)
{
    XHdmiphy1_Channel *ChPtr;
    u32 ReturnVal;
    u16 DrpVal;
    u16 WriteVal;
    XHdmiphy1_ChannelId ChIdPll;
    XHdmiphy1_PllType PllType;
    u32 PllxVcoRateMHz;
    u32 PllxClkOutMHz;
    u32 PllxClkOutDiv;
    u32 Status = XST_SUCCESS;

    ReturnVal = XHdmiphy1_Gtye4TxPllRefClkDiv1Reconfig(InstancePtr, QuadId,
                    ChId);
    if (!XHdmiphy1_IsHDMI(InstancePtr, XHDMIPHY1_DIR_TX)) {
        return ReturnVal;
    }

    /* Determine PLL type. */
    PllType = XHdmiphy1_GetPllType(InstancePtr, QuadId, XHDMIPHY1_DIR_TX,
                ChId);
    /* Determine which channel(s) to operate on. */
    switch (PllType) {
        case XHDMIPHY1_PLL_TYPE_QPLL:
        case XHDMIPHY1_PLL_TYPE_QPLL0:
            ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN0;
            PllxClkOutDiv = 2;
            break;
        case XHDMIPHY1_PLL_TYPE_QPLL1:
            ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN1;
            PllxClkOutDiv = 2;
            break;
        default:
            ChIdPll = ChId;
            PllxClkOutDiv = 1;
            break;
    }

    if (XHdmiphy1_IsHDMI(InstancePtr, XHDMIPHY1_DIR_TX)) {

        ChPtr = &InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(ChId)];
        /* Set TX_PROGDIV_CFG to 20 */
        if ((PllType == XHDMIPHY1_PLL_TYPE_QPLL) ||
            (PllType == XHDMIPHY1_PLL_TYPE_QPLL0) ||
            (PllType == XHDMIPHY1_PLL_TYPE_QPLL1)) {
            if (InstancePtr->Quads[QuadId].
                    Plls[XHDMIPHY1_CH2IDX(ChId)].TxOutDiv != 16) {
                /* TX_PROGDIV_CFG = 20 */
                XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0057, 57442);
            } else {
                /* TX_PROGDIV_CFG = 40 */
                XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0057, 57415);
            }
        }

        /* TX_INT_DATAWIDTH */
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0085, &DrpVal);
        DrpVal &= ~(0x3 << 10);
        WriteVal = ((XHdmiphy1_DrpEncodeIntDataWidth(ChPtr->
                        TxIntDataWidth) & 0x3) << 10);
        DrpVal |= WriteVal;
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0085, DrpVal);

        /* TX_DATA_WIDTH */
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_007A, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_007A_TX_DATA_WIDTH_MASK);
        WriteVal = (XHdmiphy1_DrpEncodeDataWidth(ChPtr->TxDataWidth) & XDRP_GTYE4_CHN_REG_007A_TX_DATA_WIDTH_MASK);
        DrpVal |= WriteVal;
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_007A, DrpVal);

        PllxVcoRateMHz = XHdmiphy1_GetPllVcoFreqHz(InstancePtr, QuadId,
                            ChIdPll, XHDMIPHY1_DIR_TX) / 1000000;
        PllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv;

        /* TXPH_CFG */
        if ((ChPtr->TxIntDataWidth <= 40 &&
                ChPtr->OutDiv[XHDMIPHY1_DIR_TX] == 1) ||
            (ChPtr->TxIntDataWidth <= 20 &&
                ChPtr->OutDiv[XHDMIPHY1_DIR_TX] == 2)) {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG_VAL2;
        }
        else {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG_VAL1;
        }
        /* Write new DRP register value for TXPH_CFG. */
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_008F, DrpVal);

        /* TXPI_CFG0 */
        if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE8) {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL1;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE9) {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL2;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL3;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE10) {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL4;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7) {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL5;
        }
        else {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL6;
        }
        /* Write new DRP register value for TXPI_CFG0. */
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00A7, DrpVal);

        /* TXPI_CFG1 */
        if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE9) {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL1;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL2;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE10) {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL3;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE12) {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL4;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE11) {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL5;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE13) {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL6;
        }
        else {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL7;
        }

        /* Write new DRP register value for TXPI_CFG1. */
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00A8, DrpVal);

        /* TX_PI_BIASSET */
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00FB, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_00FB_TXPI_BIASSET_MASK);
        if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4) {
            DrpVal |= 3 << 1;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
            DrpVal |= 2 << 1;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7) {
            DrpVal |= 1 << 1;
        }
        /* Write new DRP register value for TX_PI_BIASSET. */
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00FB, DrpVal);

        /* CH_HSPMUX_TX */
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0116, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_0116_CH_TX_HSPMUX_MASK);
        if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE5) {
            DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL1;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4) {
            DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL2;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
            DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL3;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7) {
            DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL4;
        }
        else {
            DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL5;
        }

        /* Write new DRP register value for CH_HSPMUX_TX. */
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0116, DrpVal);
    }
    return Status;
}
/*****************************************************************************/
/**
* This function will configure the channel's TX settings.
*
* @param    InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param    QuadId is the GT quad ID to operate on.
* @param    ChId is the channel ID to operate on.
*
* @return
*       - XST_SUCCESS if the configuration was successful.
*       - XST_FAILURE otherwise.
*
* @note     None.
*
******************************************************************************/
This function will configure the channel's TX settings.
This function will configure the channel ' s TX settings .
u32 XHdmiphy1_Gtye4TxChReconfig(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId)
{
    XHdmiphy1_Channel *ChPtr;
    u32 ReturnVal;
    u16 DrpVal;
    u16 WriteVal;
    XHdmiphy1_ChannelId ChIdPll;
    XHdmiphy1_PllType PllType;
    u32 PllxVcoRateMHz;
    u32 PllxClkOutMHz;
    u32 PllxClkOutDiv;
    u32 Status = XST_SUCCESS;
    ReturnVal = XHdmiphy1_Gtye4TxPllRefClkDiv1Reconfig(InstancePtr, QuadId,
                    ChId);
    if (!XHdmiphy1_IsHDMI(InstancePtr, XHDMIPHY1_DIR_TX)) {
        return ReturnVal;
    }
    PllType = XHdmiphy1_GetPllType(InstancePtr, QuadId, XHDMIPHY1_DIR_TX,
                ChId);
    switch (PllType) {
        case XHDMIPHY1_PLL_TYPE_QPLL:
        case XHDMIPHY1_PLL_TYPE_QPLL0:
            ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN0;
            PllxClkOutDiv = 2;
            break;
        case XHDMIPHY1_PLL_TYPE_QPLL1:
            ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN1;
            PllxClkOutDiv = 2;
            break;
        default:
            ChIdPll = ChId;
            PllxClkOutDiv = 1;
            break;
    }
    if (XHdmiphy1_IsHDMI(InstancePtr, XHDMIPHY1_DIR_TX)) {
        ChPtr = &InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(ChId)];
        if ((PllType == XHDMIPHY1_PLL_TYPE_QPLL) ||
            (PllType == XHDMIPHY1_PLL_TYPE_QPLL0) ||
            (PllType == XHDMIPHY1_PLL_TYPE_QPLL1)) {
            if (InstancePtr->Quads[QuadId].
                    Plls[XHDMIPHY1_CH2IDX(ChId)].TxOutDiv != 16) {
                XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0057, 57442);
            } else {
                XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0057, 57415);
            }
        }
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0085, &DrpVal);
        DrpVal &= ~(0x3 << 10);
        WriteVal = ((XHdmiphy1_DrpEncodeIntDataWidth(ChPtr->
                        TxIntDataWidth) & 0x3) << 10);
        DrpVal |= WriteVal;
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0085, DrpVal);
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_007A, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_007A_TX_DATA_WIDTH_MASK);
        WriteVal = (XHdmiphy1_DrpEncodeDataWidth(ChPtr->TxDataWidth) & XDRP_GTYE4_CHN_REG_007A_TX_DATA_WIDTH_MASK);
        DrpVal |= WriteVal;
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_007A, DrpVal);
        PllxVcoRateMHz = XHdmiphy1_GetPllVcoFreqHz(InstancePtr, QuadId,
                            ChIdPll, XHDMIPHY1_DIR_TX) / 1000000;
        PllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv;
        if ((ChPtr->TxIntDataWidth <= 40 &&
                ChPtr->OutDiv[XHDMIPHY1_DIR_TX] == 1) ||
            (ChPtr->TxIntDataWidth <= 20 &&
                ChPtr->OutDiv[XHDMIPHY1_DIR_TX] == 2)) {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG_VAL2;
        }
        else {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG_VAL1;
        }
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_008F, DrpVal);
        if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE8) {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL1;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE9) {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL2;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL3;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE10) {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL4;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7) {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL5;
        }
        else {
            DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL6;
        }
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00A7, DrpVal);
        if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE9) {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL1;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL2;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE10) {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL3;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE12) {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL4;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE11) {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL5;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE13) {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL6;
        }
        else {
            DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL7;
        }
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00A8, DrpVal);
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00FB, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_00FB_TXPI_BIASSET_MASK);
        if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4) {
            DrpVal |= 3 << 1;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
            DrpVal |= 2 << 1;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7) {
            DrpVal |= 1 << 1;
        }
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00FB, DrpVal);
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0116, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_0116_CH_TX_HSPMUX_MASK);
        if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE5) {
            DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL1;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4) {
            DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL2;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
            DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL3;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7) {
            DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL4;
        }
        else {
            DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL5;
        }
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0116, DrpVal);
    }
    return Status;
}
u32 XHdmiphy1_Gtye4TxChReconfig ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId ) { XHdmiphy1_Channel * ChPtr ; u32 ReturnVal ; u16 DrpVal ; u16 WriteVal ; XHdmiphy1_ChannelId ChIdPll ; XHdmiphy1_PllType PllType ; u32 PllxVcoRateMHz ; u32 PllxClkOutMHz ; u32 PllxClkOutDiv ; u32 Status = XST_SUCCESS ; ReturnVal = XHdmiphy1_Gtye4TxPllRefClkDiv1Reconfig ( InstancePtr , QuadId , ChId ) ; if ( ! XHdmiphy1_IsHDMI ( InstancePtr , XHDMIPHY1_DIR_TX ) ) { return ReturnVal ; } PllType = XHdmiphy1_GetPllType ( InstancePtr , QuadId , XHDMIPHY1_DIR_TX , ChId ) ; switch ( PllType ) { case XHDMIPHY1_PLL_TYPE_QPLL : case XHDMIPHY1_PLL_TYPE_QPLL0 : ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN0 ; PllxClkOutDiv = 2 ; break ; case XHDMIPHY1_PLL_TYPE_QPLL1 : ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN1 ; PllxClkOutDiv = 2 ; break ; default : ChIdPll = ChId ; PllxClkOutDiv = 1 ; break ; } if ( XHdmiphy1_IsHDMI ( InstancePtr , XHDMIPHY1_DIR_TX ) ) { ChPtr = & InstancePtr -> Quads [ QuadId ] . Plls [ XHDMIPHY1_CH2IDX ( ChId ) ] ; if ( ( PllType == XHDMIPHY1_PLL_TYPE_QPLL ) || ( PllType == XHDMIPHY1_PLL_TYPE_QPLL0 ) || ( PllType == XHDMIPHY1_PLL_TYPE_QPLL1 ) ) { if ( InstancePtr -> Quads [ QuadId ] . Plls [ XHDMIPHY1_CH2IDX ( ChId ) ] . TxOutDiv != 16 ) { XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0057 , 57442 ) ; } else { XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0057 , 57415 ) ; } } Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0085 , & DrpVal ) ; DrpVal &= ~ ( 0x3 << 10 ) ; WriteVal = ( ( XHdmiphy1_DrpEncodeIntDataWidth ( ChPtr -> TxIntDataWidth ) & 0x3 ) << 10 ) ; DrpVal |= WriteVal ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0085 , DrpVal ) ; Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_007A , & DrpVal ) ; DrpVal &= ~ ( XDRP_GTYE4_CHN_REG_007A_TX_DATA_WIDTH_MASK ) ; WriteVal = ( XHdmiphy1_DrpEncodeDataWidth ( ChPtr -> TxDataWidth ) & XDRP_GTYE4_CHN_REG_007A_TX_DATA_WIDTH_MASK ) ; DrpVal |= WriteVal ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_007A , DrpVal ) ; PllxVcoRateMHz = XHdmiphy1_GetPllVcoFreqHz ( InstancePtr , QuadId , ChIdPll , XHDMIPHY1_DIR_TX ) / 1000000 ; PllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv ; if ( ( ChPtr -> TxIntDataWidth <= 40 && ChPtr -> OutDiv [ XHDMIPHY1_DIR_TX ] == 1 ) || ( ChPtr -> TxIntDataWidth <= 20 && ChPtr -> OutDiv [ XHDMIPHY1_DIR_TX ] == 2 ) ) { DrpVal = XHDMIPHY1_DRP_TXPH_CFG_VAL2 ; } else { DrpVal = XHDMIPHY1_DRP_TXPH_CFG_VAL1 ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_008F , DrpVal ) ; if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE8 ) { DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL1 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE9 ) { DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL2 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6 ) { DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL3 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE10 ) { DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL4 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7 ) { DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL5 ; } else { DrpVal = XHDMIPHY1_DRP_TXPH_CFG0_VAL6 ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00A7 , DrpVal ) ; if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE9 ) { DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL1 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6 ) { DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL2 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE10 ) { DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL3 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE12 ) { DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL4 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE11 ) { DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL5 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE13 ) { DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL6 ; } else { DrpVal = XHDMIPHY1_DRP_TXPI_CFG1_VAL7 ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00A8 , DrpVal ) ; Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00FB , & DrpVal ) ; DrpVal &= ~ ( XDRP_GTYE4_CHN_REG_00FB_TXPI_BIASSET_MASK ) ; if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4 ) { DrpVal |= 3 << 1 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6 ) { DrpVal |= 2 << 1 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7 ) { DrpVal |= 1 << 1 ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00FB , DrpVal ) ; Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0116 , & DrpVal ) ; DrpVal &= ~ ( XDRP_GTYE4_CHN_REG_0116_CH_TX_HSPMUX_MASK ) ; if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE5 ) { DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL1 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4 ) { DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL2 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6 ) { DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL3 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7 ) { DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL4 ; } else { DrpVal |= XHDMIPHY1_DRP_CH_TX_HSPMUX_VAL5 ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0116 , DrpVal ) ; } return Status ; }
This function will configure the channel's TX settings.
This function will configure the channel ' s TX settings .
/* Determine PLL type. */ /* Determine which channel(s) to operate on. */ /* Set TX_PROGDIV_CFG to 20 */ /* TX_PROGDIV_CFG = 20 */ /* TX_PROGDIV_CFG = 40 */ /* TX_INT_DATAWIDTH */ /* TX_DATA_WIDTH */ /* TXPH_CFG */ /* Write new DRP register value for TXPH_CFG. */ /* TXPI_CFG0 */ /* Write new DRP register value for TXPI_CFG0. */ /* TXPI_CFG1 */ /* Write new DRP register value for TXPI_CFG1. */ /* TX_PI_BIASSET */ /* Write new DRP register value for TX_PI_BIASSET. */ /* CH_HSPMUX_TX */ /* Write new DRP register value for CH_HSPMUX_TX. */