lib/sw_apps/zynqmp_dram_test/src/xmt_main.c
void XMt_RunEyeMemtest(XMt_CfgData *XMtPtr, u64 StartAddr, u32 Len)
{
	u32 DataPtr;
	u32 RegVal;
	u64 Index;
	u64 Addr;
	u64 ReadVal;
	u64 ExpectedVal;
	u8 Lane;
	u8 Offset;

	/* For 64Bit increment offset by 8, for 32Bit increment offset by 4 */
	if (XMtPtr->DdrConfigLanes == XMT_DDR_CONFIG_8_LANE) {
		Offset = 8U;
	} else if (XMtPtr->DdrConfigLanes == XMT_DDR_CONFIG_4_LANE) {
		Offset = 4U;
	} else {
		Offset = 2U;
	}

	DataPtr = 0U;

	StartAddr = XMT_DDR_BASEADDR + StartAddr;

	/* Do the Write operation on memory size specified in argument */
	for (Index = StartAddr; Index < (StartAddr+(Len*XMT_KB2BYTE)); Index += Offset) {
		if (Index < (XMT_DDR_0_HIGHADDR + 1U)) {
			Addr = Index;
		} else {
			Addr = XMT_DDR_1_BASEADDR + (Index - (XMT_DDR_0_HIGHADDR + 1U));
		}

		if (Offset == 8U) {
			Xil_Out64(Addr, AggressorPattern64Bit[DataPtr]);
			DataPtr++;
			DataPtr = (DataPtr) % (sizeof(AggressorPattern64Bit)/sizeof(u64));
		} else if (Offset == 4U) {
			Xil_Out32(Addr, AggressorPattern32Bit[DataPtr]);
			DataPtr++;
			DataPtr = (DataPtr) % (sizeof(AggressorPattern32Bit)/sizeof(u32));
		} else {
			Xil_Out16(Addr, AggressorPattern16Bit[DataPtr]);
			DataPtr++;
			DataPtr = (DataPtr) % (sizeof(AggressorPattern16Bit)/sizeof(u16));
		}
	}

	if (XMtPtr->DCacheEnable != 0U) {
#if (defined(XPAR_PSU_DDR_0_S_AXI_BASEADDR))
		if ((StartAddr + (Len * XMT_KB2BYTE)) < (XMT_DDR_0_HIGHADDR + 1U)) {
			Xil_DCacheInvalidateRange(StartAddr, Len * XMT_KB2BYTE);
		} else {
			Xil_DCacheInvalidateRange(StartAddr, XMT_DDR_0_HIGHADDR + 1U - StartAddr);
			Xil_DCacheInvalidateRange(XMT_DDR_1_BASEADDR, StartAddr + (Len * XMT_KB2BYTE) - XMT_DDR_1_BASEADDR);
		}
#elif (defined(XPAR_PSU_DDR_1_S_AXI_BASEADDR))
		Xil_DCacheInvalidateRange(StartAddr, Len * XMT_KB2BYTE);
#endif
	}

	DataPtr = 0U;

	/* Do the Read operation on memory size specified in argument */
	for (Index = StartAddr; Index < (StartAddr+(Len*XMT_KB2BYTE)); Index += Offset) {
		if (Index < (XMT_DDR_0_HIGHADDR + 1U)) {
			Addr = Index;
		} else {
			Addr = XMT_DDR_1_BASEADDR + (Index - (XMT_DDR_0_HIGHADDR + 1U));
		}

		if (Offset == 8U) {
			ReadVal = Xil_In64(Addr);
			ExpectedVal = AggressorPattern64Bit[DataPtr];
			DataPtr++;
			DataPtr = (DataPtr) % (sizeof(AggressorPattern64Bit)/sizeof(u64));
		} else if (Offset == 4U) {
			ReadVal = Xil_In32(Addr);
			ExpectedVal = AggressorPattern32Bit[DataPtr];
			DataPtr++;
			DataPtr = (DataPtr) % (sizeof(AggressorPattern32Bit)/sizeof(u32));
		} else {
			ReadVal = Xil_In16(Addr);
			ExpectedVal = AggressorPattern16Bit[DataPtr];
			DataPtr++;
			DataPtr = (DataPtr) % (sizeof(AggressorPattern16Bit)/sizeof(u16));
		}

		/* Compare the Read Value and the Expected Value */
		if (ReadVal != ExpectedVal) {
			for (Lane = 0U; Lane < XMtPtr->DdrConfigLanes; Lane++) {
				if ((((ReadVal ^ ExpectedVal) >>
						(Lane * 8)) & 0xFF) != 0U) {
					RegVal = Xil_In32(XMT_RESULTS_BASE +
							  (Lane*4));
					Xil_Out32(XMT_RESULTS_BASE + (Lane*4),
						  RegVal + 1);
				}
			}
		}
	}
}
/*****************************************************************************/
/**
 * This function does Read/Write Eye tests and Updated RESULTS registers
 * accordingly. This function is used by Read Eye and Write Eye Tests.
 *
 * @param XMtPtr is the pointer to the Memtest Data Structure
 * @param StartAddr is the starting Address
 * @param Len is the Size of the memory to be Tested
 *
 * @return none
 *
 * @note none
 *****************************************************************************/
This function does Read/Write Eye tests and Updated RESULTS registers
accordingly. This function is used by Read Eye and Write Eye Tests.

@param XMtPtr is the pointer to the Memtest Data Structure
@param StartAddr is the starting Address
@param Len is the Size of the memory to be Tested

@return none

@note none
This function does Read / Write Eye tests and Updated RESULTS registers accordingly . This function is used by Read Eye and Write Eye Tests . @param XMtPtr is the pointer to the Memtest Data Structure @param StartAddr is the starting Address @param Len is the Size of the memory to be Tested @return none @note none
void XMt_RunEyeMemtest(XMt_CfgData *XMtPtr, u64 StartAddr, u32 Len)
{
	u32 DataPtr;
	u32 RegVal;
	u64 Index;
	u64 Addr;
	u64 ReadVal;
	u64 ExpectedVal;
	u8 Lane;
	u8 Offset;
	if (XMtPtr->DdrConfigLanes == XMT_DDR_CONFIG_8_LANE) {
		Offset = 8U;
	} else if (XMtPtr->DdrConfigLanes == XMT_DDR_CONFIG_4_LANE) {
		Offset = 4U;
	} else {
		Offset = 2U;
	}
	DataPtr = 0U;
	StartAddr = XMT_DDR_BASEADDR + StartAddr;
	for (Index = StartAddr; Index < (StartAddr+(Len*XMT_KB2BYTE)); Index += Offset) {
		if (Index < (XMT_DDR_0_HIGHADDR + 1U)) {
			Addr = Index;
		} else {
			Addr = XMT_DDR_1_BASEADDR + (Index - (XMT_DDR_0_HIGHADDR + 1U));
		}
		if (Offset == 8U) {
			Xil_Out64(Addr, AggressorPattern64Bit[DataPtr]);
			DataPtr++;
			DataPtr = (DataPtr) % (sizeof(AggressorPattern64Bit)/sizeof(u64));
		} else if (Offset == 4U) {
			Xil_Out32(Addr, AggressorPattern32Bit[DataPtr]);
			DataPtr++;
			DataPtr = (DataPtr) % (sizeof(AggressorPattern32Bit)/sizeof(u32));
		} else {
			Xil_Out16(Addr, AggressorPattern16Bit[DataPtr]);
			DataPtr++;
			DataPtr = (DataPtr) % (sizeof(AggressorPattern16Bit)/sizeof(u16));
		}
	}
	if (XMtPtr->DCacheEnable != 0U) {
#if (defined(XPAR_PSU_DDR_0_S_AXI_BASEADDR))
		if ((StartAddr + (Len * XMT_KB2BYTE)) < (XMT_DDR_0_HIGHADDR + 1U)) {
			Xil_DCacheInvalidateRange(StartAddr, Len * XMT_KB2BYTE);
		} else {
			Xil_DCacheInvalidateRange(StartAddr, XMT_DDR_0_HIGHADDR + 1U - StartAddr);
			Xil_DCacheInvalidateRange(XMT_DDR_1_BASEADDR, StartAddr + (Len * XMT_KB2BYTE) - XMT_DDR_1_BASEADDR);
		}
#elif (defined(XPAR_PSU_DDR_1_S_AXI_BASEADDR))
		Xil_DCacheInvalidateRange(StartAddr, Len * XMT_KB2BYTE);
#endif
	}
	DataPtr = 0U;
	for (Index = StartAddr; Index < (StartAddr+(Len*XMT_KB2BYTE)); Index += Offset) {
		if (Index < (XMT_DDR_0_HIGHADDR + 1U)) {
			Addr = Index;
		} else {
			Addr = XMT_DDR_1_BASEADDR + (Index - (XMT_DDR_0_HIGHADDR + 1U));
		}
		if (Offset == 8U) {
			ReadVal = Xil_In64(Addr);
			ExpectedVal = AggressorPattern64Bit[DataPtr];
			DataPtr++;
			DataPtr = (DataPtr) % (sizeof(AggressorPattern64Bit)/sizeof(u64));
		} else if (Offset == 4U) {
			ReadVal = Xil_In32(Addr);
			ExpectedVal = AggressorPattern32Bit[DataPtr];
			DataPtr++;
			DataPtr = (DataPtr) % (sizeof(AggressorPattern32Bit)/sizeof(u32));
		} else {
			ReadVal = Xil_In16(Addr);
			ExpectedVal = AggressorPattern16Bit[DataPtr];
			DataPtr++;
			DataPtr = (DataPtr) % (sizeof(AggressorPattern16Bit)/sizeof(u16));
		}
		if (ReadVal != ExpectedVal) {
			for (Lane = 0U; Lane < XMtPtr->DdrConfigLanes; Lane++) {
				if ((((ReadVal ^ ExpectedVal) >>
						(Lane * 8)) & 0xFF) != 0U) {
					RegVal = Xil_In32(XMT_RESULTS_BASE +
							  (Lane*4));
					Xil_Out32(XMT_RESULTS_BASE + (Lane*4),
						  RegVal + 1);
				}
			}
		}
	}
}
void XMt_RunEyeMemtest ( XMt_CfgData * XMtPtr , u64 StartAddr , u32 Len ) { u32 DataPtr ; u32 RegVal ; u64 Index ; u64 Addr ; u64 ReadVal ; u64 ExpectedVal ; u8 Lane ; u8 Offset ; if ( XMtPtr -> DdrConfigLanes == XMT_DDR_CONFIG_8_LANE ) { Offset = 8U ; } else if ( XMtPtr -> DdrConfigLanes == XMT_DDR_CONFIG_4_LANE ) { Offset = 4U ; } else { Offset = 2U ; } DataPtr = 0U ; StartAddr = XMT_DDR_BASEADDR + StartAddr ; for ( Index = StartAddr ; Index < ( StartAddr + ( Len * XMT_KB2BYTE ) ) ; Index += Offset ) { if ( Index < ( XMT_DDR_0_HIGHADDR + 1U ) ) { Addr = Index ; } else { Addr = XMT_DDR_1_BASEADDR + ( Index - ( XMT_DDR_0_HIGHADDR + 1U ) ) ; } if ( Offset == 8U ) { Xil_Out64 ( Addr , AggressorPattern64Bit [ DataPtr ] ) ; DataPtr ++ ; DataPtr = ( DataPtr ) % ( sizeof ( AggressorPattern64Bit ) / sizeof ( u64 ) ) ; } else if ( Offset == 4U ) { Xil_Out32 ( Addr , AggressorPattern32Bit [ DataPtr ] ) ; DataPtr ++ ; DataPtr = ( DataPtr ) % ( sizeof ( AggressorPattern32Bit ) / sizeof ( u32 ) ) ; } else { Xil_Out16 ( Addr , AggressorPattern16Bit [ DataPtr ] ) ; DataPtr ++ ; DataPtr = ( DataPtr ) % ( sizeof ( AggressorPattern16Bit ) / sizeof ( u16 ) ) ; } } if ( XMtPtr -> DCacheEnable != 0U ) { #if ( defined ( XPAR_PSU_DDR_0_S_AXI_BASEADDR ) ) if ( ( StartAddr + ( Len * XMT_KB2BYTE ) ) < ( XMT_DDR_0_HIGHADDR + 1U ) ) { Xil_DCacheInvalidateRange ( StartAddr , Len * XMT_KB2BYTE ) ; } else { Xil_DCacheInvalidateRange ( StartAddr , XMT_DDR_0_HIGHADDR + 1U - StartAddr ) ; Xil_DCacheInvalidateRange ( XMT_DDR_1_BASEADDR , StartAddr + ( Len * XMT_KB2BYTE ) - XMT_DDR_1_BASEADDR ) ; } #elif ( defined ( XPAR_PSU_DDR_1_S_AXI_BASEADDR ) ) Xil_DCacheInvalidateRange ( StartAddr , Len * XMT_KB2BYTE ) ; #endif } DataPtr = 0U ; for ( Index = StartAddr ; Index < ( StartAddr + ( Len * XMT_KB2BYTE ) ) ; Index += Offset ) { if ( Index < ( XMT_DDR_0_HIGHADDR + 1U ) ) { Addr = Index ; } else { Addr = XMT_DDR_1_BASEADDR + ( Index - ( XMT_DDR_0_HIGHADDR + 1U ) ) ; } if ( Offset == 8U ) { ReadVal = Xil_In64 ( Addr ) ; ExpectedVal = AggressorPattern64Bit [ DataPtr ] ; DataPtr ++ ; DataPtr = ( DataPtr ) % ( sizeof ( AggressorPattern64Bit ) / sizeof ( u64 ) ) ; } else if ( Offset == 4U ) { ReadVal = Xil_In32 ( Addr ) ; ExpectedVal = AggressorPattern32Bit [ DataPtr ] ; DataPtr ++ ; DataPtr = ( DataPtr ) % ( sizeof ( AggressorPattern32Bit ) / sizeof ( u32 ) ) ; } else { ReadVal = Xil_In16 ( Addr ) ; ExpectedVal = AggressorPattern16Bit [ DataPtr ] ; DataPtr ++ ; DataPtr = ( DataPtr ) % ( sizeof ( AggressorPattern16Bit ) / sizeof ( u16 ) ) ; } if ( ReadVal != ExpectedVal ) { for ( Lane = 0U ; Lane < XMtPtr -> DdrConfigLanes ; Lane ++ ) { if ( ( ( ( ReadVal ^ ExpectedVal ) >> ( Lane * 8 ) ) & 0xFF ) != 0U ) { RegVal = Xil_In32 ( XMT_RESULTS_BASE + ( Lane * 4 ) ) ; Xil_Out32 ( XMT_RESULTS_BASE + ( Lane * 4 ) , RegVal + 1 ) ; } } } } }
This function does Read/Write Eye tests and Updated RESULTS registers
 accordingly.
This function does Read / Write Eye tests and Updated RESULTS registers accordingly .
/* For 64Bit increment offset by 8, for 32Bit increment offset by 4 */ /* Do the Write operation on memory size specified in argument */ /* Do the Read operation on memory size specified in argument */ /* Compare the Read Value and the Expected Value */