src/dpdk/drivers/net/ixgbe/base/ixgbe_82599.c
s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
{
	ixgbe_link_speed link_speed;
	s32 status;
	u32 ctrl = 0;
	u32 i, autoc, autoc2;
	u32 curr_lms;
	bool link_up = false;

	DEBUGFUNC("ixgbe_reset_hw_82599");

	/* Call adapter stop to disable tx/rx and clear interrupts */
	status = hw->mac.ops.stop_adapter(hw);
	if (status != IXGBE_SUCCESS)
		goto reset_hw_out;

	/* flush pending Tx transactions */
	ixgbe_clear_tx_pending(hw);

	/* PHY ops must be identified and initialized prior to reset */

	/* Identify PHY and related function pointers */
	status = hw->phy.ops.init(hw);

	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
		goto reset_hw_out;

	/* Setup SFP module if there is one present. */
	if (hw->phy.sfp_setup_needed) {
		status = hw->mac.ops.setup_sfp(hw);
		hw->phy.sfp_setup_needed = false;
	}

	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
		goto reset_hw_out;

	/* Reset PHY */
	if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
		hw->phy.ops.reset(hw);

	/* remember AUTOC from before we reset */
	curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;

mac_reset_top:
	/*
	 * Issue global reset to the MAC.  Needs to be SW reset if link is up.
	 * If link reset is used when link is up, it might reset the PHY when
	 * mng is using it.  If link is down or the flag to force full link
	 * reset is set, then perform link reset.
	 */
	ctrl = IXGBE_CTRL_LNK_RST;
	if (!hw->force_full_reset) {
		hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
		if (link_up)
			ctrl = IXGBE_CTRL_RST;
	}

	ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
	IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
	IXGBE_WRITE_FLUSH(hw);

	/* Poll for reset bit to self-clear meaning reset is complete */
	for (i = 0; i < 10; i++) {
		usec_delay(1);
		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
		if (!(ctrl & IXGBE_CTRL_RST_MASK))
			break;
	}

	if (ctrl & IXGBE_CTRL_RST_MASK) {
		status = IXGBE_ERR_RESET_FAILED;
		DEBUGOUT("Reset polling failed to complete.\n");
	}

	msec_delay(50);

	/*
	 * Double resets are required for recovery from certain error
	 * conditions.  Between resets, it is necessary to stall to
	 * allow time for any pending HW events to complete.
	 */
	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
		goto mac_reset_top;
	}

	/*
	 * Store the original AUTOC/AUTOC2 values if they have not been
	 * stored off yet.  Otherwise restore the stored original
	 * values since the reset operation sets back to defaults.
	 */
	autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
	autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);

	/* Enable link if disabled in NVM */
	if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
		autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
		IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
		IXGBE_WRITE_FLUSH(hw);
	}

	if (hw->mac.orig_link_settings_stored == false) {
		hw->mac.orig_autoc = autoc;
		hw->mac.orig_autoc2 = autoc2;
		hw->mac.orig_link_settings_stored = true;
	} else {

		/* If MNG FW is running on a multi-speed device that
		 * doesn't autoneg with out driver support we need to
		 * leave LMS in the state it was before we MAC reset.
		 * Likewise if we support WoL we don't want change the
		 * LMS state.
		 */
		if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
		    hw->wol_enabled)
			hw->mac.orig_autoc =
				(hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
				curr_lms;

		if (autoc != hw->mac.orig_autoc) {
			status = hw->mac.ops.prot_autoc_write(hw,
							hw->mac.orig_autoc,
							false);
			if (status != IXGBE_SUCCESS)
				goto reset_hw_out;
		}

		if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
		    (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
			autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
			autoc2 |= (hw->mac.orig_autoc2 &
				   IXGBE_AUTOC2_UPPER_MASK);
			IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
		}
	}

	/* Store the permanent mac address */
	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);

	/*
	 * Store MAC address from RAR0, clear receive address registers, and
	 * clear the multicast table.  Also reset num_rar_entries to 128,
	 * since we modify this value when programming the SAN MAC address.
	 */
	hw->mac.num_rar_entries = 128;
	hw->mac.ops.init_rx_addrs(hw);

	/* Store the permanent SAN mac address */
	hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);

	/* Add the SAN MAC address to the RAR only if it's a valid address */
	if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
		/* Save the SAN MAC RAR index */
		hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;

		hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
				    hw->mac.san_addr, 0, IXGBE_RAH_AV);

		/* clear VMDq pool/queue selection for this RAR */
		hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
				       IXGBE_CLEAR_VMDQ_ALL);

		/* Reserve the last RAR for the SAN MAC address */
		hw->mac.num_rar_entries--;
	}

	/* Store the alternative WWNN/WWPN prefix */
	hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
				   &hw->mac.wwpn_prefix);

reset_hw_out:
	return status;
}
/**
 * ixgbe_reset_hw_82599 - Perform hardware reset
 * @hw: pointer to hardware structure
 *
 * Resets the hardware by resetting the transmit and receive units, masks
 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 * reset.
 **/
Perform hardware reset
@hw: pointer to hardware structure

Resets the hardware by resetting the transmit and receive units, masks
and clears all interrupts, perform a PHY reset, and perform a link (MAC)
reset.
Perform hardware reset @hw : pointer to hardware structure Resets the hardware by resetting the transmit and receive units masks and clears all interrupts perform a PHY reset and perform a link ( MAC ) reset .
s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
{
	ixgbe_link_speed link_speed;
	s32 status;
	u32 ctrl = 0;
	u32 i, autoc, autoc2;
	u32 curr_lms;
	bool link_up = false;
	DEBUGFUNC("ixgbe_reset_hw_82599");
	status = hw->mac.ops.stop_adapter(hw);
	if (status != IXGBE_SUCCESS)
		goto reset_hw_out;
	ixgbe_clear_tx_pending(hw);
	status = hw->phy.ops.init(hw);
	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
		goto reset_hw_out;
	if (hw->phy.sfp_setup_needed) {
		status = hw->mac.ops.setup_sfp(hw);
		hw->phy.sfp_setup_needed = false;
	}
	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
		goto reset_hw_out;
	if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
		hw->phy.ops.reset(hw);
	curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
mac_reset_top:
	ctrl = IXGBE_CTRL_LNK_RST;
	if (!hw->force_full_reset) {
		hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
		if (link_up)
			ctrl = IXGBE_CTRL_RST;
	}
	ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
	IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
	IXGBE_WRITE_FLUSH(hw);
	for (i = 0; i < 10; i++) {
		usec_delay(1);
		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
		if (!(ctrl & IXGBE_CTRL_RST_MASK))
			break;
	}
	if (ctrl & IXGBE_CTRL_RST_MASK) {
		status = IXGBE_ERR_RESET_FAILED;
		DEBUGOUT("Reset polling failed to complete.\n");
	}
	msec_delay(50);
	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
		goto mac_reset_top;
	}
	autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
	autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
	if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
		autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
		IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
		IXGBE_WRITE_FLUSH(hw);
	}
	if (hw->mac.orig_link_settings_stored == false) {
		hw->mac.orig_autoc = autoc;
		hw->mac.orig_autoc2 = autoc2;
		hw->mac.orig_link_settings_stored = true;
	} else {
		if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
		    hw->wol_enabled)
			hw->mac.orig_autoc =
				(hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
				curr_lms;
		if (autoc != hw->mac.orig_autoc) {
			status = hw->mac.ops.prot_autoc_write(hw,
							hw->mac.orig_autoc,
							false);
			if (status != IXGBE_SUCCESS)
				goto reset_hw_out;
		}
		if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
		    (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
			autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
			autoc2 |= (hw->mac.orig_autoc2 &
				   IXGBE_AUTOC2_UPPER_MASK);
			IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
		}
	}
	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
	hw->mac.num_rar_entries = 128;
	hw->mac.ops.init_rx_addrs(hw);
	hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
	if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
		hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
		hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
				    hw->mac.san_addr, 0, IXGBE_RAH_AV);
		hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
				       IXGBE_CLEAR_VMDQ_ALL);
		hw->mac.num_rar_entries--;
	}
	hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
				   &hw->mac.wwpn_prefix);
reset_hw_out:
	return status;
}
s32 ixgbe_reset_hw_82599 ( struct ixgbe_hw * hw ) { ixgbe_link_speed link_speed ; s32 status ; u32 ctrl = 0 ; u32 i , autoc , autoc2 ; u32 curr_lms ; bool link_up = false ; DEBUGFUNC ( " " ) ; status = hw -> mac . ops . stop_adapter ( hw ) ; if ( status != IXGBE_SUCCESS ) goto reset_hw_out ; ixgbe_clear_tx_pending ( hw ) ; status = hw -> phy . ops . init ( hw ) ; if ( status == IXGBE_ERR_SFP_NOT_SUPPORTED ) goto reset_hw_out ; if ( hw -> phy . sfp_setup_needed ) { status = hw -> mac . ops . setup_sfp ( hw ) ; hw -> phy . sfp_setup_needed = false ; } if ( status == IXGBE_ERR_SFP_NOT_SUPPORTED ) goto reset_hw_out ; if ( hw -> phy . reset_disable == false && hw -> phy . ops . reset != NULL ) hw -> phy . ops . reset ( hw ) ; curr_lms = IXGBE_READ_REG ( hw , IXGBE_AUTOC ) & IXGBE_AUTOC_LMS_MASK ; mac_reset_top : ctrl = IXGBE_CTRL_LNK_RST ; if ( ! hw -> force_full_reset ) { hw -> mac . ops . check_link ( hw , & link_speed , & link_up , false ) ; if ( link_up ) ctrl = IXGBE_CTRL_RST ; } ctrl |= IXGBE_READ_REG ( hw , IXGBE_CTRL ) ; IXGBE_WRITE_REG ( hw , IXGBE_CTRL , ctrl ) ; IXGBE_WRITE_FLUSH ( hw ) ; for ( i = 0 ; i < 10 ; i ++ ) { usec_delay ( 1 ) ; ctrl = IXGBE_READ_REG ( hw , IXGBE_CTRL ) ; if ( ! ( ctrl & IXGBE_CTRL_RST_MASK ) ) break ; } if ( ctrl & IXGBE_CTRL_RST_MASK ) { status = IXGBE_ERR_RESET_FAILED ; DEBUGOUT ( " \n " ) ; } msec_delay ( 50 ) ; if ( hw -> mac . flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED ) { hw -> mac . flags &= ~ IXGBE_FLAGS_DOUBLE_RESET_REQUIRED ; goto mac_reset_top ; } autoc = IXGBE_READ_REG ( hw , IXGBE_AUTOC ) ; autoc2 = IXGBE_READ_REG ( hw , IXGBE_AUTOC2 ) ; if ( autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK ) { autoc2 &= ~ IXGBE_AUTOC2_LINK_DISABLE_MASK ; IXGBE_WRITE_REG ( hw , IXGBE_AUTOC2 , autoc2 ) ; IXGBE_WRITE_FLUSH ( hw ) ; } if ( hw -> mac . orig_link_settings_stored == false ) { hw -> mac . orig_autoc = autoc ; hw -> mac . orig_autoc2 = autoc2 ; hw -> mac . orig_link_settings_stored = true ; } else { if ( ( hw -> phy . multispeed_fiber && ixgbe_mng_enabled ( hw ) ) || hw -> wol_enabled ) hw -> mac . orig_autoc = ( hw -> mac . orig_autoc & ~ IXGBE_AUTOC_LMS_MASK ) | curr_lms ; if ( autoc != hw -> mac . orig_autoc ) { status = hw -> mac . ops . prot_autoc_write ( hw , hw -> mac . orig_autoc , false ) ; if ( status != IXGBE_SUCCESS ) goto reset_hw_out ; } if ( ( autoc2 & IXGBE_AUTOC2_UPPER_MASK ) != ( hw -> mac . orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK ) ) { autoc2 &= ~ IXGBE_AUTOC2_UPPER_MASK ; autoc2 |= ( hw -> mac . orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK ) ; IXGBE_WRITE_REG ( hw , IXGBE_AUTOC2 , autoc2 ) ; } } hw -> mac . ops . get_mac_addr ( hw , hw -> mac . perm_addr ) ; hw -> mac . num_rar_entries = 128 ; hw -> mac . ops . init_rx_addrs ( hw ) ; hw -> mac . ops . get_san_mac_addr ( hw , hw -> mac . san_addr ) ; if ( ixgbe_validate_mac_addr ( hw -> mac . san_addr ) == 0 ) { hw -> mac . san_mac_rar_index = hw -> mac . num_rar_entries - 1 ; hw -> mac . ops . set_rar ( hw , hw -> mac . san_mac_rar_index , hw -> mac . san_addr , 0 , IXGBE_RAH_AV ) ; hw -> mac . ops . clear_vmdq ( hw , hw -> mac . san_mac_rar_index , IXGBE_CLEAR_VMDQ_ALL ) ; hw -> mac . num_rar_entries -- ; } hw -> mac . ops . get_wwn_prefix ( hw , & hw -> mac . wwnn_prefix , & hw -> mac . wwpn_prefix ) ; reset_hw_out : return status ; }
ixgbe_reset_hw_82599 - Perform hardware reset
 @hw: pointer to hardware structure
ixgbe_reset_hw_82599 - Perform hardware reset @hw : pointer to hardware structure
/* Call adapter stop to disable tx/rx and clear interrupts */ /* flush pending Tx transactions */ /* PHY ops must be identified and initialized prior to reset */ /* Identify PHY and related function pointers */ /* Setup SFP module if there is one present. */ /* Reset PHY */ /* remember AUTOC from before we reset */ /*
	 * Issue global reset to the MAC.  Needs to be SW reset if link is up.
	 * If link reset is used when link is up, it might reset the PHY when
	 * mng is using it.  If link is down or the flag to force full link
	 * reset is set, then perform link reset.
	 */ /* Poll for reset bit to self-clear meaning reset is complete */ /*
	 * Double resets are required for recovery from certain error
	 * conditions.  Between resets, it is necessary to stall to
	 * allow time for any pending HW events to complete.
	 */ /*
	 * Store the original AUTOC/AUTOC2 values if they have not been
	 * stored off yet.  Otherwise restore the stored original
	 * values since the reset operation sets back to defaults.
	 */ /* Enable link if disabled in NVM */ /* If MNG FW is running on a multi-speed device that
		 * doesn't autoneg with out driver support we need to
		 * leave LMS in the state it was before we MAC reset.
		 * Likewise if we support WoL we don't want change the
		 * LMS state.
		 */ /* Store the permanent mac address */ /*
	 * Store MAC address from RAR0, clear receive address registers, and
	 * clear the multicast table.  Also reset num_rar_entries to 128,
	 * since we modify this value when programming the SAN MAC address.
	 */ /* Store the permanent SAN mac address */ /* Add the SAN MAC address to the RAR only if it's a valid address */ /* Save the SAN MAC RAR index */ /* clear VMDq pool/queue selection for this RAR */ /* Reserve the last RAR for the SAN MAC address */ /* Store the alternative WWNN/WWPN prefix */