platform/msm_shared/mmc.c
static unsigned int
mmc_boot_fifo_read(unsigned int *mmc_ptr, unsigned int data_len)
{
	unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
	unsigned int mmc_status = 0;
	unsigned int mmc_count = 0;
	unsigned int read_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL |
	    MMC_BOOT_MCI_STAT_DATA_TIMEOUT | MMC_BOOT_MCI_STAT_RX_OVRRUN;

	/* Read the data from the MCI_FIFO register as long as RXDATA_AVLBL
	   bit of MCI_STATUS register is set to 1 and bits DATA_CRC_FAIL,
	   DATA_TIMEOUT, RX_OVERRUN of MCI_STATUS register are cleared to 0.
	   Continue the reads until the whole transfer data is received */

	do {
		mmc_ret = MMC_BOOT_E_SUCCESS;
		mmc_status = readl(MMC_BOOT_MCI_STATUS);

		if (mmc_status & read_error) {
			mmc_ret = mmc_boot_status_error(mmc_status);
			break;
		}

		if (mmc_status & MMC_BOOT_MCI_STAT_RX_DATA_AVLBL) {
			unsigned read_count = 1;
			if (mmc_status & MMC_BOOT_MCI_STAT_RX_FIFO_HFULL) {
				read_count = MMC_BOOT_MCI_HFIFO_COUNT;
			}

			for (unsigned int i = 0; i < read_count; i++) {
				/* FIFO contains 16 32-bit data buffer on 16 sequential addresses */
				*mmc_ptr = readl(MMC_BOOT_MCI_FIFO +
						 (mmc_count %
						  MMC_BOOT_MCI_FIFO_SIZE));
				mmc_ptr++;
				/* increase mmc_count by word size */
				mmc_count += sizeof(unsigned int);
			}
			/* quit if we have read enough of data */
			if (mmc_count == data_len)
				break;
		} else if (mmc_status & MMC_BOOT_MCI_STAT_DATA_END) {
			break;
		}
	}
	while (1);

	return mmc_ret;
}
/*
 * Read data to SDC FIFO.
 */
Read data to SDC FIFO.
Read data to SDC FIFO .
static unsigned int
mmc_boot_fifo_read(unsigned int *mmc_ptr, unsigned int data_len)
{
	unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
	unsigned int mmc_status = 0;
	unsigned int mmc_count = 0;
	unsigned int read_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL |
	    MMC_BOOT_MCI_STAT_DATA_TIMEOUT | MMC_BOOT_MCI_STAT_RX_OVRRUN;
	do {
		mmc_ret = MMC_BOOT_E_SUCCESS;
		mmc_status = readl(MMC_BOOT_MCI_STATUS);
		if (mmc_status & read_error) {
			mmc_ret = mmc_boot_status_error(mmc_status);
			break;
		}
		if (mmc_status & MMC_BOOT_MCI_STAT_RX_DATA_AVLBL) {
			unsigned read_count = 1;
			if (mmc_status & MMC_BOOT_MCI_STAT_RX_FIFO_HFULL) {
				read_count = MMC_BOOT_MCI_HFIFO_COUNT;
			}
			for (unsigned int i = 0; i < read_count; i++) {
				*mmc_ptr = readl(MMC_BOOT_MCI_FIFO +
						 (mmc_count %
						  MMC_BOOT_MCI_FIFO_SIZE));
				mmc_ptr++;
				mmc_count += sizeof(unsigned int);
			}
			if (mmc_count == data_len)
				break;
		} else if (mmc_status & MMC_BOOT_MCI_STAT_DATA_END) {
			break;
		}
	}
	while (1);
	return mmc_ret;
}
static unsigned int mmc_boot_fifo_read ( unsigned int * mmc_ptr , unsigned int data_len ) { unsigned int mmc_ret = MMC_BOOT_E_SUCCESS ; unsigned int mmc_status = 0 ; unsigned int mmc_count = 0 ; unsigned int read_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL | MMC_BOOT_MCI_STAT_DATA_TIMEOUT | MMC_BOOT_MCI_STAT_RX_OVRRUN ; do { mmc_ret = MMC_BOOT_E_SUCCESS ; mmc_status = readl ( MMC_BOOT_MCI_STATUS ) ; if ( mmc_status & read_error ) { mmc_ret = mmc_boot_status_error ( mmc_status ) ; break ; } if ( mmc_status & MMC_BOOT_MCI_STAT_RX_DATA_AVLBL ) { unsigned read_count = 1 ; if ( mmc_status & MMC_BOOT_MCI_STAT_RX_FIFO_HFULL ) { read_count = MMC_BOOT_MCI_HFIFO_COUNT ; } for ( unsigned int i = 0 ; i < read_count ; i ++ ) { * mmc_ptr = readl ( MMC_BOOT_MCI_FIFO + ( mmc_count % MMC_BOOT_MCI_FIFO_SIZE ) ) ; mmc_ptr ++ ; mmc_count += sizeof ( unsigned int ) ; } if ( mmc_count == data_len ) break ; } else if ( mmc_status & MMC_BOOT_MCI_STAT_DATA_END ) { break ; } } while ( 1 ) ; return mmc_ret ; }
Read data to SDC FIFO.
Read data to SDC FIFO .
/* Read the data from the MCI_FIFO register as long as RXDATA_AVLBL
	   bit of MCI_STATUS register is set to 1 and bits DATA_CRC_FAIL,
	   DATA_TIMEOUT, RX_OVERRUN of MCI_STATUS register are cleared to 0.
	   Continue the reads until the whole transfer data is received */ /* FIFO contains 16 32-bit data buffer on 16 sequential addresses */ /* increase mmc_count by word size */ /* quit if we have read enough of data */