XilinxProcessorIPLib/drivers/sysmonpsu/src/xsysmonpsu.c
s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u64 AcqCyclesChMask,
		u32 SysmonBlk)
{
	s32 Status;
	UINTPTR EffectiveBaseAddress;

	/* Assert the arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));

	/*
	 * The sequencer must be in the Safe Mode before writing
	 * to these registers. Return XST_FAILURE if the channel
	 * sequencer is enabled.
	 */
	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
	                                     != XSM_SEQ_MODE_SAFE)) {
		Status = (s32)XST_FAILURE;
		goto End;
	}

	/* Calculate the effective baseaddress based on the Sysmon instance. */
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);

	/*
	 * Set the Acquisition time for the specified channels in the
	 * ADC Channel Acquisition Time Sequencer Registers.
	 */
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ0_OFFSET,
			 (u32)(AcqCyclesChMask & XSYSMONPSU_SEQ_ACQ0_MASK));

	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ1_OFFSET,
			 (u32)(AcqCyclesChMask >> XSM_SEQ_CH_SHIFT) &
					XSYSMONPSU_SEQ_ACQ1_MASK);

	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ2_OFFSET,
			(u32)(AcqCyclesChMask >> XSM_SEQ_CH2_SHIFT) &
					XSYSMONPSU_SEQ_ACQ2_MASK);

	Status = (s32)XST_SUCCESS;

End:
	return Status;
}
/****************************************************************************/
/**
*
* This function sets the number of Acquisition cycles in the ADC Channel
* Acquisition Time Sequencer Registers. The sequencer must be in the Safe Mode
* before writing to these registers.
*
* @param	InstancePtr is a pointer to the XSysMonPsu instance.
* @param	AcqCyclesChMask is the bit mask of all the channels for which
*		the number of acquisition cycles is to be extended.
*		Use XSYSMONPSU_SEQ_ACQ* defined in xsysmonpsu_hw.h to specify the Channel
*		numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
*		for bit masks of 1 and will be the default 4 ADCCLK cycles for
*		bit masks of 0.
*		The AcqCyclesChMask is a 64 bit mask that is written to the three
*		16 bit ADC Channel Acquisition Time Sequencer Registers.
* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
*       block or PL Sysmon block register region.
*
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the Channel Sequencer Registers.
*		- XST_FAILURE if the channel sequencer is enabled.
*
* @note		None.
*
*****************************************************************************/
This function sets the number of Acquisition cycles in the ADC Channel
Acquisition Time Sequencer Registers. The sequencer must be in the Safe Mode
before writing to these registers.
This function sets the number of Acquisition cycles in the ADC Channel Acquisition Time Sequencer Registers . The sequencer must be in the Safe Mode before writing to these registers .
s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u64 AcqCyclesChMask,
		u32 SysmonBlk)
{
	s32 Status;
	UINTPTR EffectiveBaseAddress;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
	                                     != XSM_SEQ_MODE_SAFE)) {
		Status = (s32)XST_FAILURE;
		goto End;
	}
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ0_OFFSET,
			 (u32)(AcqCyclesChMask & XSYSMONPSU_SEQ_ACQ0_MASK));
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ1_OFFSET,
			 (u32)(AcqCyclesChMask >> XSM_SEQ_CH_SHIFT) &
					XSYSMONPSU_SEQ_ACQ1_MASK);
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ2_OFFSET,
			(u32)(AcqCyclesChMask >> XSM_SEQ_CH2_SHIFT) &
					XSYSMONPSU_SEQ_ACQ2_MASK);
	Status = (s32)XST_SUCCESS;
End:
	return Status;
}
s32 XSysMonPsu_SetSeqAcqTime ( XSysMonPsu * InstancePtr , u64 AcqCyclesChMask , u32 SysmonBlk ) { s32 Status ; UINTPTR EffectiveBaseAddress ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Xil_AssertNonvoid ( ( SysmonBlk == XSYSMON_PS ) || ( SysmonBlk == XSYSMON_PL ) ) ; if ( ( XSysMonPsu_GetSequencerMode ( InstancePtr , SysmonBlk ) != XSM_SEQ_MODE_SAFE ) ) { Status = ( s32 ) XST_FAILURE ; goto End ; } EffectiveBaseAddress = XSysMonPsu_GetEffBaseAddress ( InstancePtr -> Config . BaseAddress , SysmonBlk ) ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ0_OFFSET , ( u32 ) ( AcqCyclesChMask & XSYSMONPSU_SEQ_ACQ0_MASK ) ) ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ1_OFFSET , ( u32 ) ( AcqCyclesChMask >> XSM_SEQ_CH_SHIFT ) & XSYSMONPSU_SEQ_ACQ1_MASK ) ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ2_OFFSET , ( u32 ) ( AcqCyclesChMask >> XSM_SEQ_CH2_SHIFT ) & XSYSMONPSU_SEQ_ACQ2_MASK ) ; Status = ( s32 ) XST_SUCCESS ; End : return Status ; }
This function sets the number of Acquisition cycles in the ADC Channel
Acquisition Time Sequencer Registers.
This function sets the number of Acquisition cycles in the ADC Channel Acquisition Time Sequencer Registers .
/* Assert the arguments. */ /*
	 * The sequencer must be in the Safe Mode before writing
	 * to these registers. Return XST_FAILURE if the channel
	 * sequencer is enabled.
	 */ /* Calculate the effective baseaddress based on the Sysmon instance. */ /*
	 * Set the Acquisition time for the specified channels in the
	 * ADC Channel Acquisition Time Sequencer Registers.
	 */