AllJoyn/Samples/BACnetAdapter/bacnet-stack-0.8.2/ports/xplained/ASF/xmega/drivers/adc/adc.h
static inline void adc_set_clock_rate (struct adc_config *conf,
					 uint32_t clk_adc)
  {
    uint32_t clk_per;
    uint16_t ratio;
    uint8_t psc;

    Assert (clk_adc);
#if XMEGA_A || XMEGA_AU
    Assert (clk_adc <= 2000000UL);
#elif XMEGA_D
    Assert (clk_adc <= 1400000UL);
#elif XMEGA_B || XMEGA_C || XMEGA_E
    Assert (clk_adc <= 1800000UL);
#endif

    clk_per = sysclk_get_per_hz ();
    ratio = clk_per / clk_adc;

    /* Round ratio up to the nearest prescaling factor. */
    if (ratio <= 4)
      {
	psc = ADC_PRESCALER_DIV4_gc;
      }
    else if (ratio <= 8)
      {
	psc = ADC_PRESCALER_DIV8_gc;
      }
    else if (ratio <= 16)
      {
	psc = ADC_PRESCALER_DIV16_gc;
      }
    else if (ratio <= 32)
      {
	psc = ADC_PRESCALER_DIV32_gc;
      }
    else if (ratio <= 64)
      {
	psc = ADC_PRESCALER_DIV64_gc;
      }
    else if (ratio <= 128)
      {
	psc = ADC_PRESCALER_DIV128_gc;
      }
    else if (ratio <= 256)
      {
	psc = ADC_PRESCALER_DIV256_gc;
      }
    else
      {
	psc = ADC_PRESCALER_DIV512_gc;
      }

    conf->prescaler = psc;
  }
/**
 * \brief Set ADC prescaler to get desired clock rate
 *
 * Sets the ADC prescaling so that its clock rate becomes _at most_
 * \a clk_adc_hz. This is done by computing the ratio of the peripheral clock
 * rate to the desired ADC clock rate, and rounding it upward to the nearest
 * prescaling factor.
 *
 * \param conf Pointer to ADC module configuration.
 * \param clk_adc Desired ADC clock rate.
 *
 * \note The sample rate is not determined solely by the ADC clock rate for all
 * devices. Setting the current limit mode on some devices will also affect the
 * maximum ADC sampling rate. Refer to the device manual for detailed
 * information on conversion timing and/or the current limitation mode.
 */
\brief Set ADC prescaler to get desired clock rate
Sets the ADC prescaling so that its clock rate becomes _at most_
\a clk_adc_hz. This is done by computing the ratio of the peripheral clock
rate to the desired ADC clock rate, and rounding it upward to the nearest
prescaling factor.

\param conf Pointer to ADC module configuration.
\param clk_adc Desired ADC clock rate.

\note The sample rate is not determined solely by the ADC clock rate for all
devices. Setting the current limit mode on some devices will also affect the
maximum ADC sampling rate. Refer to the device manual for detailed
information on conversion timing and/or the current limitation mode.
\ brief Set ADC prescaler to get desired clock rate Sets the ADC prescaling so that its clock rate becomes _at most_ \ a clk_adc_hz . This is done by computing the ratio of the peripheral clock rate to the desired ADC clock rate and rounding it upward to the nearest prescaling factor . \ param conf Pointer to ADC module configuration . \ param clk_adc Desired ADC clock rate . \ note The sample rate is not determined solely by the ADC clock rate for all devices . Setting the current limit mode on some devices will also affect the maximum ADC sampling rate . Refer to the device manual for detailed information on conversion timing and / or the current limitation mode .
static inline void adc_set_clock_rate (struct adc_config *conf,
					 uint32_t clk_adc)
  {
    uint32_t clk_per;
    uint16_t ratio;
    uint8_t psc;
    Assert (clk_adc);
#if XMEGA_A || XMEGA_AU
    Assert (clk_adc <= 2000000UL);
#elif XMEGA_D
    Assert (clk_adc <= 1400000UL);
#elif XMEGA_B || XMEGA_C || XMEGA_E
    Assert (clk_adc <= 1800000UL);
#endif
    clk_per = sysclk_get_per_hz ();
    ratio = clk_per / clk_adc;
    if (ratio <= 4)
      {
	psc = ADC_PRESCALER_DIV4_gc;
      }
    else if (ratio <= 8)
      {
	psc = ADC_PRESCALER_DIV8_gc;
      }
    else if (ratio <= 16)
      {
	psc = ADC_PRESCALER_DIV16_gc;
      }
    else if (ratio <= 32)
      {
	psc = ADC_PRESCALER_DIV32_gc;
      }
    else if (ratio <= 64)
      {
	psc = ADC_PRESCALER_DIV64_gc;
      }
    else if (ratio <= 128)
      {
	psc = ADC_PRESCALER_DIV128_gc;
      }
    else if (ratio <= 256)
      {
	psc = ADC_PRESCALER_DIV256_gc;
      }
    else
      {
	psc = ADC_PRESCALER_DIV512_gc;
      }
    conf->prescaler = psc;
  }
static inline void adc_set_clock_rate ( struct adc_config * conf , uint32_t clk_adc ) { uint32_t clk_per ; uint16_t ratio ; uint8_t psc ; Assert ( clk_adc ) ; #if XMEGA_A || XMEGA_AU Assert ( clk_adc <= 2000000UL ) ; #elif XMEGA_D Assert ( clk_adc <= 1400000UL ) ; #elif XMEGA_B || XMEGA_C || XMEGA_E Assert ( clk_adc <= 1800000UL ) ; #endif clk_per = sysclk_get_per_hz ( ) ; ratio = clk_per / clk_adc ; if ( ratio <= 4 ) { psc = ADC_PRESCALER_DIV4_gc ; } else if ( ratio <= 8 ) { psc = ADC_PRESCALER_DIV8_gc ; } else if ( ratio <= 16 ) { psc = ADC_PRESCALER_DIV16_gc ; } else if ( ratio <= 32 ) { psc = ADC_PRESCALER_DIV32_gc ; } else if ( ratio <= 64 ) { psc = ADC_PRESCALER_DIV64_gc ; } else if ( ratio <= 128 ) { psc = ADC_PRESCALER_DIV128_gc ; } else if ( ratio <= 256 ) { psc = ADC_PRESCALER_DIV256_gc ; } else { psc = ADC_PRESCALER_DIV512_gc ; } conf -> prescaler = psc ; }
\brief Set ADC prescaler to get desired clock rate
 Sets the ADC prescaling so that its clock rate becomes _at most_
 \a clk_adc_hz.
\ brief Set ADC prescaler to get desired clock rate Sets the ADC prescaling so that its clock rate becomes _at most_ \ a clk_adc_hz .
/* Round ratio up to the nearest prescaling factor. */