product/n1sdp/module/n1sdp_dmc620/src/dimm_spd.c
int dimm_spd_init_check(
    struct mod_cdns_i2c_master_api_polled *i2c_api,
    struct dimm_info *ddr)
{
    int status;

    spd_read(i2c_api, DIMM0_SPD_SLAVE, (uint8_t *)&ddr4_dimm0);
    spd_read(i2c_api, DIMM1_SPD_SLAVE, (uint8_t *)&ddr4_dimm1);

    status = chk_ddr4_dimms(ddr->speed, &ddr4_dimm0, &ddr4_dimm1);
    if (status != FWK_SUCCESS) {
        return status;
    }

    dmc_clk_freq = ddr->speed * UINT32_C(1000000);
    dmc_clk_period = 1.0f / dmc_clk_freq;
    dmc_clk_period_ps = dmc_clk_period * 1000000000000.0f;

    return FWK_SUCCESS;
}
/*
 * APIs invoked by DMC-620 core functions
 */
APIs invoked by DMC-620 core functions
APIs invoked by DMC - 620 core functions
int dimm_spd_init_check(
    struct mod_cdns_i2c_master_api_polled *i2c_api,
    struct dimm_info *ddr)
{
    int status;
    spd_read(i2c_api, DIMM0_SPD_SLAVE, (uint8_t *)&ddr4_dimm0);
    spd_read(i2c_api, DIMM1_SPD_SLAVE, (uint8_t *)&ddr4_dimm1);
    status = chk_ddr4_dimms(ddr->speed, &ddr4_dimm0, &ddr4_dimm1);
    if (status != FWK_SUCCESS) {
        return status;
    }
    dmc_clk_freq = ddr->speed * UINT32_C(1000000);
    dmc_clk_period = 1.0f / dmc_clk_freq;
    dmc_clk_period_ps = dmc_clk_period * 1000000000000.0f;
    return FWK_SUCCESS;
}
int dimm_spd_init_check ( struct mod_cdns_i2c_master_api_polled * i2c_api , struct dimm_info * ddr ) { int status ; spd_read ( i2c_api , DIMM0_SPD_SLAVE , ( uint8_t * ) & ddr4_dimm0 ) ; spd_read ( i2c_api , DIMM1_SPD_SLAVE , ( uint8_t * ) & ddr4_dimm1 ) ; status = chk_ddr4_dimms ( ddr -> speed , & ddr4_dimm0 , & ddr4_dimm1 ) ; if ( status != FWK_SUCCESS ) { return status ; } dmc_clk_freq = ddr -> speed * UINT32_C ( 1000000 ) ; dmc_clk_period = 1.0f / dmc_clk_freq ; dmc_clk_period_ps = dmc_clk_period * 1000000000000.0f ; return FWK_SUCCESS ; }
APIs invoked by DMC-620 core functions
APIs invoked by DMC - 620 core functions