XilinxProcessorIPLib/drivers/v_sdirx/src/xv_sdirx.c
u32 XV_SdiRx_WaitforPayLoad(XV_SdiRx *InstancePtr)
{
	u32 Data0, Data1, Data3;
	int StreamId;
	XSdiVid_TransMode TMode;

	Xil_AssertNonvoid(InstancePtr != NULL);

	Data0 = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
			(XV_SDIRX_MODE_DET_STS_OFFSET));
	Data1 = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
			(XV_SDIRX_TS_DET_STS_OFFSET));

	/* Check if mode and transport are locked */
	if (!(((Data0 & XV_SDIRX_MODE_DET_STS_MODE_LOCKED_MASK)
		== XV_SDIRX_MODE_DET_STS_MODE_LOCKED_MASK)
		&& ((Data1 & XV_SDIRX_TS_DET_STS_T_LOCKED_MASK)
		== XV_SDIRX_TS_DET_STS_T_LOCKED_MASK)))
		return XST_FAILURE;

	TMode = Data0 & XV_SDIRX_MODE_DET_STS_MODE_MASK;

	/* Based on TMode, calculate the expected values to be present in
	 * the st352 valid register
	 */
	switch (TMode) {
		case XSDIVID_MODE_HD:
		case XSDIVID_MODE_SD:
			Data3 = 0x1;
			break;
		case XSDIVID_MODE_3GA:
			Data3 = 0x3;
			break;
		case XSDIVID_MODE_6G:
		case XSDIVID_MODE_12G:
		case XSDIVID_MODE_12GF:
			Data3 = 0xF;
			break;
		default:
			return XST_FAILURE;
	}

	/*
	 * Wait for 50 ms, the maximum frame time for any SDI supported
	 * resolution. The highest frametime is 1/23.98 ~ 41 ms. With some
	 * buffer we consider 50 ms wait time affter which we can ensure that
	 * a frame has been passed.
	 */
	usleep(50000);

	/* Payload are expected for 3GA and above modes */
	if ((XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
				(XV_SDIRX_RX_ST352_VLD_OFFSET)) != Data3) &&
		(TMode >= XSDIVID_MODE_3GA)) {
		return XST_FAILURE;
	}

	for (StreamId = 0; StreamId < XV_SDIRX_MAX_DATASTREAM; StreamId++) {
		InstancePtr->Stream[StreamId].PayloadId
			= XV_SdiRx_GetPayloadId(InstancePtr, StreamId);
	}

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function is used to wait for the payload valid bit to be set.
* This has to be called from application based on the callback indication of
* the video lock interrupt handler. Without this function being called, it may
* be guaranteed that payload bits are valid after video lock interrupt occured.
*
* @param	InstancePtr is a pointer to the XV_SdiRx core instance.
*
* @return
*		- XST_FAILURE if the payload valid bits are not set.
*		- XST_SUCCESS if ST352 registers are read and loaded to
*		  Rx structures
*
* @note         None.
*
******************************************************************************/
This function is used to wait for the payload valid bit to be set.
This has to be called from application based on the callback indication of
the video lock interrupt handler. Without this function being called, it may
be guaranteed that payload bits are valid after video lock interrupt occured.
This function is used to wait for the payload valid bit to be set . This has to be called from application based on the callback indication of the video lock interrupt handler . Without this function being called it may be guaranteed that payload bits are valid after video lock interrupt occured .
u32 XV_SdiRx_WaitforPayLoad(XV_SdiRx *InstancePtr)
{
	u32 Data0, Data1, Data3;
	int StreamId;
	XSdiVid_TransMode TMode;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Data0 = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
			(XV_SDIRX_MODE_DET_STS_OFFSET));
	Data1 = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
			(XV_SDIRX_TS_DET_STS_OFFSET));
	if (!(((Data0 & XV_SDIRX_MODE_DET_STS_MODE_LOCKED_MASK)
		== XV_SDIRX_MODE_DET_STS_MODE_LOCKED_MASK)
		&& ((Data1 & XV_SDIRX_TS_DET_STS_T_LOCKED_MASK)
		== XV_SDIRX_TS_DET_STS_T_LOCKED_MASK)))
		return XST_FAILURE;
	TMode = Data0 & XV_SDIRX_MODE_DET_STS_MODE_MASK;
	switch (TMode) {
		case XSDIVID_MODE_HD:
		case XSDIVID_MODE_SD:
			Data3 = 0x1;
			break;
		case XSDIVID_MODE_3GA:
			Data3 = 0x3;
			break;
		case XSDIVID_MODE_6G:
		case XSDIVID_MODE_12G:
		case XSDIVID_MODE_12GF:
			Data3 = 0xF;
			break;
		default:
			return XST_FAILURE;
	}
	usleep(50000);
	if ((XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
				(XV_SDIRX_RX_ST352_VLD_OFFSET)) != Data3) &&
		(TMode >= XSDIVID_MODE_3GA)) {
		return XST_FAILURE;
	}
	for (StreamId = 0; StreamId < XV_SDIRX_MAX_DATASTREAM; StreamId++) {
		InstancePtr->Stream[StreamId].PayloadId
			= XV_SdiRx_GetPayloadId(InstancePtr, StreamId);
	}
	return XST_SUCCESS;
}
u32 XV_SdiRx_WaitforPayLoad ( XV_SdiRx * InstancePtr ) { u32 Data0 , Data1 , Data3 ; int StreamId ; XSdiVid_TransMode TMode ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Data0 = XV_SdiRx_ReadReg ( InstancePtr -> Config . BaseAddress , ( XV_SDIRX_MODE_DET_STS_OFFSET ) ) ; Data1 = XV_SdiRx_ReadReg ( InstancePtr -> Config . BaseAddress , ( XV_SDIRX_TS_DET_STS_OFFSET ) ) ; if ( ! ( ( ( Data0 & XV_SDIRX_MODE_DET_STS_MODE_LOCKED_MASK ) == XV_SDIRX_MODE_DET_STS_MODE_LOCKED_MASK ) && ( ( Data1 & XV_SDIRX_TS_DET_STS_T_LOCKED_MASK ) == XV_SDIRX_TS_DET_STS_T_LOCKED_MASK ) ) ) return XST_FAILURE ; TMode = Data0 & XV_SDIRX_MODE_DET_STS_MODE_MASK ; switch ( TMode ) { case XSDIVID_MODE_HD : case XSDIVID_MODE_SD : Data3 = 0x1 ; break ; case XSDIVID_MODE_3GA : Data3 = 0x3 ; break ; case XSDIVID_MODE_6G : case XSDIVID_MODE_12G : case XSDIVID_MODE_12GF : Data3 = 0xF ; break ; default : return XST_FAILURE ; } usleep ( 50000 ) ; if ( ( XV_SdiRx_ReadReg ( InstancePtr -> Config . BaseAddress , ( XV_SDIRX_RX_ST352_VLD_OFFSET ) ) != Data3 ) && ( TMode >= XSDIVID_MODE_3GA ) ) { return XST_FAILURE ; } for ( StreamId = 0 ; StreamId < XV_SDIRX_MAX_DATASTREAM ; StreamId ++ ) { InstancePtr -> Stream [ StreamId ] . PayloadId = XV_SdiRx_GetPayloadId ( InstancePtr , StreamId ) ; } return XST_SUCCESS ; }
This function is used to wait for the payload valid bit to be set.
This function is used to wait for the payload valid bit to be set .
/* Check if mode and transport are locked */ /* Based on TMode, calculate the expected values to be present in
	 * the st352 valid register
	 */ /*
	 * Wait for 50 ms, the maximum frame time for any SDI supported
	 * resolution. The highest frametime is 1/23.98 ~ 41 ms. With some
	 * buffer we consider 50 ms wait time affter which we can ensure that
	 * a frame has been passed.
	 */ /* Payload are expected for 3GA and above modes */