src/dpdk/drivers/net/txgbe/base/txgbe_eeprom.c
s32 txgbe_init_eeprom_params(struct txgbe_hw *hw)
{
	struct txgbe_rom_info *eeprom = &hw->rom;
	u32 eec;
	u16 eeprom_size;
	int err = 0;

	DEBUGFUNC("txgbe_init_eeprom_params");

	if (eeprom->type != txgbe_eeprom_unknown)
		return 0;

	eeprom->type = txgbe_eeprom_none;
	/* Set default semaphore delay to 10ms which is a well
	 * tested value
	 */
	eeprom->semaphore_delay = 10; /*ms*/
	/* Clear EEPROM page size, it will be initialized as needed */
	eeprom->word_page_size = 0;

	/*
	 * Check for EEPROM present first.
	 * If not present leave as none
	 */
	eec = rd32(hw, TXGBE_SPISTAT);
	if (!(eec & TXGBE_SPISTAT_BPFLASH)) {
		eeprom->type = txgbe_eeprom_flash;

		/*
		 * SPI EEPROM is assumed here.  This code would need to
		 * change if a future EEPROM is not SPI.
		 */
		eeprom_size = 4096;
		eeprom->word_size = eeprom_size >> 1;
	}

	eeprom->address_bits = 16;

	err = eeprom->read32(hw, TXGBE_SW_REGION_PTR << 1, &eeprom->sw_addr);
	if (err) {
		DEBUGOUT("EEPROM read failed.\n");
		return err;
	}

	DEBUGOUT("eeprom params: type = %d, size = %d, address bits: "
		  "%d %d\n", eeprom->type, eeprom->word_size,
		  eeprom->address_bits, eeprom->sw_addr);

	return 0;
}
/**
 *  txgbe_init_eeprom_params - Initialize EEPROM params
 *  @hw: pointer to hardware structure
 *
 *  Initializes the EEPROM parameters txgbe_rom_info within the
 *  txgbe_hw struct in order to set up EEPROM access.
 **/
Initialize EEPROM params
@hw: pointer to hardware structure

Initializes the EEPROM parameters txgbe_rom_info within the
txgbe_hw struct in order to set up EEPROM access.
Initialize EEPROM params @hw : pointer to hardware structure Initializes the EEPROM parameters txgbe_rom_info within the txgbe_hw struct in order to set up EEPROM access .
s32 txgbe_init_eeprom_params(struct txgbe_hw *hw)
{
	struct txgbe_rom_info *eeprom = &hw->rom;
	u32 eec;
	u16 eeprom_size;
	int err = 0;
	DEBUGFUNC("txgbe_init_eeprom_params");
	if (eeprom->type != txgbe_eeprom_unknown)
		return 0;
	eeprom->type = txgbe_eeprom_none;
	eeprom->semaphore_delay = 10; 
	eeprom->word_page_size = 0;
	eec = rd32(hw, TXGBE_SPISTAT);
	if (!(eec & TXGBE_SPISTAT_BPFLASH)) {
		eeprom->type = txgbe_eeprom_flash;
		eeprom_size = 4096;
		eeprom->word_size = eeprom_size >> 1;
	}
	eeprom->address_bits = 16;
	err = eeprom->read32(hw, TXGBE_SW_REGION_PTR << 1, &eeprom->sw_addr);
	if (err) {
		DEBUGOUT("EEPROM read failed.\n");
		return err;
	}
	DEBUGOUT("eeprom params: type = %d, size = %d, address bits: "
		  "%d %d\n", eeprom->type, eeprom->word_size,
		  eeprom->address_bits, eeprom->sw_addr);
	return 0;
}
s32 txgbe_init_eeprom_params ( struct txgbe_hw * hw ) { struct txgbe_rom_info * eeprom = & hw -> rom ; u32 eec ; u16 eeprom_size ; int err = 0 ; DEBUGFUNC ( " " ) ; if ( eeprom -> type != txgbe_eeprom_unknown ) return 0 ; eeprom -> type = txgbe_eeprom_none ; eeprom -> semaphore_delay = 10 ; eeprom -> word_page_size = 0 ; eec = rd32 ( hw , TXGBE_SPISTAT ) ; if ( ! ( eec & TXGBE_SPISTAT_BPFLASH ) ) { eeprom -> type = txgbe_eeprom_flash ; eeprom_size = 4096 ; eeprom -> word_size = eeprom_size >> 1 ; } eeprom -> address_bits = 16 ; err = eeprom -> read32 ( hw , TXGBE_SW_REGION_PTR << 1 , & eeprom -> sw_addr ) ; if ( err ) { DEBUGOUT ( " \n " ) ; return err ; } DEBUGOUT ( " " " \n " , eeprom -> type , eeprom -> word_size , eeprom -> address_bits , eeprom -> sw_addr ) ; return 0 ; }
txgbe_init_eeprom_params - Initialize EEPROM params
  @hw: pointer to hardware structure
txgbe_init_eeprom_params - Initialize EEPROM params @hw : pointer to hardware structure
/* Set default semaphore delay to 10ms which is a well
	 * tested value
	 */ /*ms*/ /* Clear EEPROM page size, it will be initialized as needed */ /*
	 * Check for EEPROM present first.
	 * If not present leave as none
	 */ /*
		 * SPI EEPROM is assumed here.  This code would need to
		 * change if a future EEPROM is not SPI.
		 */