src/dpdk/drivers/event/dlb/dlb.c
static int
dlb_eventdev_configure(const struct rte_eventdev *dev)
{
	struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
	struct dlb_hw_dev *handle = &dlb->qm_instance;
	struct dlb_hw_rsrcs *rsrcs = &handle->info.hw_rsrc_max;
	const struct rte_eventdev_data *data = dev->data;
	const struct rte_event_dev_config *config = &data->dev_conf;
	int ret;

	/* If this eventdev is already configured, we must release the current
	 * scheduling domain before attempting to configure a new one.
	 */
	if (dlb->configured) {
		dlb_hw_reset_sched_domain(dev, true);

		ret = dlb_hw_query_resources(dlb);
		if (ret) {
			DLB_LOG_ERR("get resources err=%d, devid=%d\n",
				    ret, data->dev_id);
			return ret;
		}
	}

	if (config->nb_event_queues > rsrcs->num_queues) {
		DLB_LOG_ERR("nb_event_queues parameter (%d) exceeds the QM device's capabilities (%d).\n",
			    config->nb_event_queues,
			    rsrcs->num_queues);
		return -EINVAL;
	}
	if (config->nb_event_ports > (rsrcs->num_ldb_ports
			+ rsrcs->num_dir_ports)) {
		DLB_LOG_ERR("nb_event_ports parameter (%d) exceeds the QM device's capabilities (%d).\n",
			    config->nb_event_ports,
			    (rsrcs->num_ldb_ports + rsrcs->num_dir_ports));
		return -EINVAL;
	}
	if (config->nb_events_limit > rsrcs->nb_events_limit) {
		DLB_LOG_ERR("nb_events_limit parameter (%d) exceeds the QM device's capabilities (%d).\n",
			    config->nb_events_limit,
			    rsrcs->nb_events_limit);
		return -EINVAL;
	}

	if (config->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
		dlb->global_dequeue_wait = false;
	else {
		uint32_t timeout32;

		dlb->global_dequeue_wait = true;

		timeout32 = config->dequeue_timeout_ns;

		dlb->global_dequeue_wait_ticks =
			timeout32 * (rte_get_timer_hz() / 1E9);
	}

	/* Does this platform support umonitor/umwait? */
	if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_WAITPKG)) {
		if (RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE != 0 &&
		    RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE != 1) {
			DLB_LOG_ERR("invalid value (%d) for RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE must be 0 or 1.\n",
				    RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE);
			return -EINVAL;
		}
		dlb->umwait_allowed = true;
	}

	rsrcs->num_dir_ports = config->nb_single_link_event_port_queues;
	rsrcs->num_ldb_ports = config->nb_event_ports - rsrcs->num_dir_ports;
	/* 1 dir queue per dir port */
	rsrcs->num_ldb_queues = config->nb_event_queues - rsrcs->num_dir_ports;

	/* Scale down nb_events_limit by 4 for directed credits, since there
	 * are 4x as many load-balanced credits.
	 */
	rsrcs->num_ldb_credits = 0;
	rsrcs->num_dir_credits = 0;

	if (rsrcs->num_ldb_queues)
		rsrcs->num_ldb_credits = config->nb_events_limit;
	if (rsrcs->num_dir_ports)
		rsrcs->num_dir_credits = config->nb_events_limit / 4;
	if (dlb->num_dir_credits_override != -1)
		rsrcs->num_dir_credits = dlb->num_dir_credits_override;

	if (dlb_hw_create_sched_domain(handle, dlb, rsrcs) < 0) {
		DLB_LOG_ERR("dlb_hw_create_sched_domain failed\n");
		return -ENODEV;
	}

	dlb->new_event_limit = config->nb_events_limit;
	__atomic_store_n(&dlb->inflights, 0, __ATOMIC_SEQ_CST);

	/* Save number of ports/queues for this event dev */
	dlb->num_ports = config->nb_event_ports;
	dlb->num_queues = config->nb_event_queues;
	dlb->num_dir_ports = rsrcs->num_dir_ports;
	dlb->num_ldb_ports = dlb->num_ports - dlb->num_dir_ports;
	dlb->num_ldb_queues = dlb->num_queues - dlb->num_dir_ports;
	dlb->num_dir_queues = dlb->num_dir_ports;
	dlb->num_ldb_credits = rsrcs->num_ldb_credits;
	dlb->num_dir_credits = rsrcs->num_dir_credits;

	dlb->configured = true;

	return 0;
}
/* Note: 1 QM instance per QM device, QM instance/device == event device */
1 QM instance per QM device, QM instance/device == event device
1 QM instance per QM device QM instance / device == event device
static int
dlb_eventdev_configure(const struct rte_eventdev *dev)
{
	struct dlb_eventdev *dlb = dlb_pmd_priv(dev);
	struct dlb_hw_dev *handle = &dlb->qm_instance;
	struct dlb_hw_rsrcs *rsrcs = &handle->info.hw_rsrc_max;
	const struct rte_eventdev_data *data = dev->data;
	const struct rte_event_dev_config *config = &data->dev_conf;
	int ret;
	if (dlb->configured) {
		dlb_hw_reset_sched_domain(dev, true);
		ret = dlb_hw_query_resources(dlb);
		if (ret) {
			DLB_LOG_ERR("get resources err=%d, devid=%d\n",
				    ret, data->dev_id);
			return ret;
		}
	}
	if (config->nb_event_queues > rsrcs->num_queues) {
		DLB_LOG_ERR("nb_event_queues parameter (%d) exceeds the QM device's capabilities (%d).\n",
			    config->nb_event_queues,
			    rsrcs->num_queues);
		return -EINVAL;
	}
	if (config->nb_event_ports > (rsrcs->num_ldb_ports
			+ rsrcs->num_dir_ports)) {
		DLB_LOG_ERR("nb_event_ports parameter (%d) exceeds the QM device's capabilities (%d).\n",
			    config->nb_event_ports,
			    (rsrcs->num_ldb_ports + rsrcs->num_dir_ports));
		return -EINVAL;
	}
	if (config->nb_events_limit > rsrcs->nb_events_limit) {
		DLB_LOG_ERR("nb_events_limit parameter (%d) exceeds the QM device's capabilities (%d).\n",
			    config->nb_events_limit,
			    rsrcs->nb_events_limit);
		return -EINVAL;
	}
	if (config->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
		dlb->global_dequeue_wait = false;
	else {
		uint32_t timeout32;
		dlb->global_dequeue_wait = true;
		timeout32 = config->dequeue_timeout_ns;
		dlb->global_dequeue_wait_ticks =
			timeout32 * (rte_get_timer_hz() / 1E9);
	}
	if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_WAITPKG)) {
		if (RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE != 0 &&
		    RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE != 1) {
			DLB_LOG_ERR("invalid value (%d) for RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE must be 0 or 1.\n",
				    RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE);
			return -EINVAL;
		}
		dlb->umwait_allowed = true;
	}
	rsrcs->num_dir_ports = config->nb_single_link_event_port_queues;
	rsrcs->num_ldb_ports = config->nb_event_ports - rsrcs->num_dir_ports;
	rsrcs->num_ldb_queues = config->nb_event_queues - rsrcs->num_dir_ports;
	rsrcs->num_ldb_credits = 0;
	rsrcs->num_dir_credits = 0;
	if (rsrcs->num_ldb_queues)
		rsrcs->num_ldb_credits = config->nb_events_limit;
	if (rsrcs->num_dir_ports)
		rsrcs->num_dir_credits = config->nb_events_limit / 4;
	if (dlb->num_dir_credits_override != -1)
		rsrcs->num_dir_credits = dlb->num_dir_credits_override;
	if (dlb_hw_create_sched_domain(handle, dlb, rsrcs) < 0) {
		DLB_LOG_ERR("dlb_hw_create_sched_domain failed\n");
		return -ENODEV;
	}
	dlb->new_event_limit = config->nb_events_limit;
	__atomic_store_n(&dlb->inflights, 0, __ATOMIC_SEQ_CST);
	dlb->num_ports = config->nb_event_ports;
	dlb->num_queues = config->nb_event_queues;
	dlb->num_dir_ports = rsrcs->num_dir_ports;
	dlb->num_ldb_ports = dlb->num_ports - dlb->num_dir_ports;
	dlb->num_ldb_queues = dlb->num_queues - dlb->num_dir_ports;
	dlb->num_dir_queues = dlb->num_dir_ports;
	dlb->num_ldb_credits = rsrcs->num_ldb_credits;
	dlb->num_dir_credits = rsrcs->num_dir_credits;
	dlb->configured = true;
	return 0;
}
static int dlb_eventdev_configure ( const struct rte_eventdev * dev ) { struct dlb_eventdev * dlb = dlb_pmd_priv ( dev ) ; struct dlb_hw_dev * handle = & dlb -> qm_instance ; struct dlb_hw_rsrcs * rsrcs = & handle -> info . hw_rsrc_max ; const struct rte_eventdev_data * data = dev -> data ; const struct rte_event_dev_config * config = & data -> dev_conf ; int ret ; if ( dlb -> configured ) { dlb_hw_reset_sched_domain ( dev , true ) ; ret = dlb_hw_query_resources ( dlb ) ; if ( ret ) { DLB_LOG_ERR ( " \n " , ret , data -> dev_id ) ; return ret ; } } if ( config -> nb_event_queues > rsrcs -> num_queues ) { DLB_LOG_ERR ( " \n " , config -> nb_event_queues , rsrcs -> num_queues ) ; return - EINVAL ; } if ( config -> nb_event_ports > ( rsrcs -> num_ldb_ports + rsrcs -> num_dir_ports ) ) { DLB_LOG_ERR ( " \n " , config -> nb_event_ports , ( rsrcs -> num_ldb_ports + rsrcs -> num_dir_ports ) ) ; return - EINVAL ; } if ( config -> nb_events_limit > rsrcs -> nb_events_limit ) { DLB_LOG_ERR ( " \n " , config -> nb_events_limit , rsrcs -> nb_events_limit ) ; return - EINVAL ; } if ( config -> event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT ) dlb -> global_dequeue_wait = false ; else { uint32_t timeout32 ; dlb -> global_dequeue_wait = true ; timeout32 = config -> dequeue_timeout_ns ; dlb -> global_dequeue_wait_ticks = timeout32 * ( rte_get_timer_hz ( ) / 1E9 ) ; } if ( rte_cpu_get_flag_enabled ( RTE_CPUFLAG_WAITPKG ) ) { if ( RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE != 0 && RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE != 1 ) { DLB_LOG_ERR ( " \n " , RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE ) ; return - EINVAL ; } dlb -> umwait_allowed = true ; } rsrcs -> num_dir_ports = config -> nb_single_link_event_port_queues ; rsrcs -> num_ldb_ports = config -> nb_event_ports - rsrcs -> num_dir_ports ; rsrcs -> num_ldb_queues = config -> nb_event_queues - rsrcs -> num_dir_ports ; rsrcs -> num_ldb_credits = 0 ; rsrcs -> num_dir_credits = 0 ; if ( rsrcs -> num_ldb_queues ) rsrcs -> num_ldb_credits = config -> nb_events_limit ; if ( rsrcs -> num_dir_ports ) rsrcs -> num_dir_credits = config -> nb_events_limit / 4 ; if ( dlb -> num_dir_credits_override != -1 ) rsrcs -> num_dir_credits = dlb -> num_dir_credits_override ; if ( dlb_hw_create_sched_domain ( handle , dlb , rsrcs ) < 0 ) { DLB_LOG_ERR ( " \n " ) ; return - ENODEV ; } dlb -> new_event_limit = config -> nb_events_limit ; __atomic_store_n ( & dlb -> inflights , 0 , __ATOMIC_SEQ_CST ) ; dlb -> num_ports = config -> nb_event_ports ; dlb -> num_queues = config -> nb_event_queues ; dlb -> num_dir_ports = rsrcs -> num_dir_ports ; dlb -> num_ldb_ports = dlb -> num_ports - dlb -> num_dir_ports ; dlb -> num_ldb_queues = dlb -> num_queues - dlb -> num_dir_ports ; dlb -> num_dir_queues = dlb -> num_dir_ports ; dlb -> num_ldb_credits = rsrcs -> num_ldb_credits ; dlb -> num_dir_credits = rsrcs -> num_dir_credits ; dlb -> configured = true ; return 0 ; }
Note: 1 QM instance per QM device, QM instance/device == event device
Note : 1 QM instance per QM device QM instance / device == event device
/* If this eventdev is already configured, we must release the current
	 * scheduling domain before attempting to configure a new one.
	 */ /* Does this platform support umonitor/umwait? */ /* 1 dir queue per dir port */ /* Scale down nb_events_limit by 4 for directed credits, since there
	 * are 4x as many load-balanced credits.
	 */ /* Save number of ports/queues for this event dev */