bluepill/libopencm3/lib/stm32/f4/rcc.c
void rcc_pllsai_config(uint16_t n, uint16_t p, uint16_t q, uint16_t r)
{
	RCC_PLLSAICFGR = (
	  ((n & RCC_PLLSAICFGR_PLLSAIN_MASK) << RCC_PLLSAICFGR_PLLSAIN_SHIFT) |
	  ((p & RCC_PLLSAICFGR_PLLSAIP_MASK) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) |
	  ((q & RCC_PLLSAICFGR_PLLSAIQ_MASK) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT) |
	  ((r & RCC_PLLSAICFGR_PLLSAIR_MASK) << RCC_PLLSAICFGR_PLLSAIR_SHIFT));
}
/**
 * Set the dividers for the PLLSAI clock outputs
 * divider p is only available on F4x9 parts, pass 0 for other parts.
 * @param n valid range is 49..432
 * @param p 0 if unused, @ref rcc_pllsaicfgr_pllsaip
 * @param q valid range is 2..15
 * @param r valid range is 2..7
 * @sa rcc_pllsai_postscalers
 */
Set the dividers for the PLLSAI clock outputs
divider p is only available on F4x9 parts, pass 0 for other parts.
Set the dividers for the PLLSAI clock outputs divider p is only available on F4x9 parts pass 0 for other parts .
void rcc_pllsai_config(uint16_t n, uint16_t p, uint16_t q, uint16_t r)
{
	RCC_PLLSAICFGR = (
	  ((n & RCC_PLLSAICFGR_PLLSAIN_MASK) << RCC_PLLSAICFGR_PLLSAIN_SHIFT) |
	  ((p & RCC_PLLSAICFGR_PLLSAIP_MASK) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) |
	  ((q & RCC_PLLSAICFGR_PLLSAIQ_MASK) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT) |
	  ((r & RCC_PLLSAICFGR_PLLSAIR_MASK) << RCC_PLLSAICFGR_PLLSAIR_SHIFT));
}
void rcc_pllsai_config ( uint16_t n , uint16_t p , uint16_t q , uint16_t r ) { RCC_PLLSAICFGR = ( ( ( n & RCC_PLLSAICFGR_PLLSAIN_MASK ) << RCC_PLLSAICFGR_PLLSAIN_SHIFT ) | ( ( p & RCC_PLLSAICFGR_PLLSAIP_MASK ) << RCC_PLLSAICFGR_PLLSAIP_SHIFT ) | ( ( q & RCC_PLLSAICFGR_PLLSAIQ_MASK ) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT ) | ( ( r & RCC_PLLSAICFGR_PLLSAIR_MASK ) << RCC_PLLSAICFGR_PLLSAIR_SHIFT ) ) ; }
Set the dividers for the PLLSAI clock outputs
 divider p is only available on F4x9 parts, pass 0 for other parts.
Set the dividers for the PLLSAI clock outputs divider p is only available on F4x9 parts pass 0 for other parts .