XilinxProcessorIPLib/drivers/sysmonpsu/src/xsysmonpsu_intr.c
u64 XSysMonPsu_IntrGetEnabled(XSysMonPsu *InstancePtr)
{
	u64 MaskedInterrupts;

	/* Assert the arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/* Return the value read from the AMS Interrupt Mask Register. */
	MaskedInterrupts = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
                         XSYSMONPSU_IMR_0_OFFSET) & (u64)XSYSMONPSU_IXR_0_MASK;
	MaskedInterrupts |= ((u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
                         XSYSMONPSU_IMR_1_OFFSET) & (u64)XSYSMONPSU_IXR_1_MASK)
                          << XSYSMONPSU_IXR_1_SHIFT;

	return (~MaskedInterrupts);
}
/****************************************************************************/
/**
*
* This function returns the enabled interrupts read from the Interrupt Enable
* Register (IER). Use the XSYSMONPSU_IER_0_* and XSYSMONPSU_IER_1_* constants
* defined in xsysmonpsu_hw.h to interpret the returned value.
*
* @param	InstancePtr is a pointer to the XSysMonPsu instance.
*
* @return	A 64-bit value representing the contents of the Interrupt Mask
* 			Registers (IMR1 IMR0).
*
* @note		None.
*
*****************************************************************************/
This function returns the enabled interrupts read from the Interrupt Enable
Register . Use the XSYSMONPSU_IER_0_* and XSYSMONPSU_IER_1_* constants
defined in xsysmonpsu_hw.h to interpret the returned value.
This function returns the enabled interrupts read from the Interrupt Enable Register . Use the XSYSMONPSU_IER_0_ * and XSYSMONPSU_IER_1_ * constants defined in xsysmonpsu_hw . h to interpret the returned value .
u64 XSysMonPsu_IntrGetEnabled(XSysMonPsu *InstancePtr)
{
	u64 MaskedInterrupts;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	MaskedInterrupts = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
                         XSYSMONPSU_IMR_0_OFFSET) & (u64)XSYSMONPSU_IXR_0_MASK;
	MaskedInterrupts |= ((u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
                         XSYSMONPSU_IMR_1_OFFSET) & (u64)XSYSMONPSU_IXR_1_MASK)
                          << XSYSMONPSU_IXR_1_SHIFT;
	return (~MaskedInterrupts);
}
u64 XSysMonPsu_IntrGetEnabled ( XSysMonPsu * InstancePtr ) { u64 MaskedInterrupts ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; MaskedInterrupts = ( u64 ) XSysmonPsu_ReadReg ( InstancePtr -> Config . BaseAddress + XSYSMONPSU_IMR_0_OFFSET ) & ( u64 ) XSYSMONPSU_IXR_0_MASK ; MaskedInterrupts |= ( ( u64 ) XSysmonPsu_ReadReg ( InstancePtr -> Config . BaseAddress + XSYSMONPSU_IMR_1_OFFSET ) & ( u64 ) XSYSMONPSU_IXR_1_MASK ) << XSYSMONPSU_IXR_1_SHIFT ; return ( ~ MaskedInterrupts ) ; }
This function returns the enabled interrupts read from the Interrupt Enable
Register (IER).
This function returns the enabled interrupts read from the Interrupt Enable Register ( IER ) .
/* Assert the arguments. */ /* Return the value read from the AMS Interrupt Mask Register. */