XilinxProcessorIPLib/drivers/iic/src/xiic_master.c
int XIic_MasterSend(XIic *InstancePtr, u8 *TxMsgPtr, int ByteCount)
{
	u32 CntlReg;

	XIic_IntrGlobalDisable(InstancePtr->BaseAddress);

	/*
	 * Ensure that the master processing has been included such that events
	 * will be properly handled.
	 */
	XIIC_MASTER_INCLUDE;
	InstancePtr->IsDynamic = FALSE;

	/*
	 * If the busy is busy, then exit the critical region and wait for the
	 * bus to not be busy, the function enables the bus not busy interrupt.
	 */
	if (IsBusBusy(InstancePtr)) {
		XIic_IntrGlobalEnable(InstancePtr->BaseAddress);

		return XST_IIC_BUS_BUSY;
	}

	/*
	 * If it is already a master on the bus (repeated start), the direction
	 * was set to Tx which is throttling bus. The control register needs to
	 * be set before putting data into the FIFO.
	 */
	CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
	if (CntlReg & XIIC_CR_MSMS_MASK) {
		CntlReg &= ~XIIC_CR_NO_ACK_MASK;
		CntlReg |= (XIIC_CR_DIR_IS_TX_MASK |
				XIIC_CR_REPEATED_START_MASK);

		XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
				CntlReg);
		InstancePtr->Stats.RepeatedStarts++;
	}

	/*
	 * Save message state.
	 */
	InstancePtr->SendByteCount = ByteCount;
	InstancePtr->SendBufferPtr = TxMsgPtr;
	InstancePtr->RecvBufferPtr = NULL;

	/*
	 * Put the address into the FIFO to be sent and indicate that the
	 * operation to be performed on the bus is a write operation,
	 * a general call address is handled the same as a 7 bit address even
	 * if 10 bit address is selected.
	 * Set the transmit address state to indicate the address has been sent.
	 */
	if ((InstancePtr->Options & XII_SEND_10_BIT_OPTION) &&
		(InstancePtr->AddrOfSlave != 0)) {
		XIic_Send10BitAddrByte1(InstancePtr->AddrOfSlave,
					 XIIC_WRITE_OPERATION);
		XIic_Send10BitAddrByte2(InstancePtr->AddrOfSlave);
	} else {
		XIic_Send7BitAddr(InstancePtr->AddrOfSlave,
				   XIIC_WRITE_OPERATION);
	}
	/*
	 * Set the transmit address state to indicate the address has been sent
	 * for communication with event driven processing.
	 */
	InstancePtr->TxAddrMode = XIIC_TX_ADDR_SENT;

	/*
	 * Fill remaining available FIFO with message data.
	 */
	if (InstancePtr->SendByteCount > 1) {
		XIic_TransmitFifoFill(InstancePtr, XIIC_MASTER_ROLE);
	}

	/*
	 * After filling fifo, if data yet to send > 1, enable Tx � empty
	 * interrupt.
	 */
	if (InstancePtr->SendByteCount > 1) {
		XIic_ClearEnableIntr(InstancePtr->BaseAddress,
					XIIC_INTR_TX_HALF_MASK);
	}

	/*
	 * Clear any pending Tx empty, Tx Error and then enable them.
	 */
	XIic_ClearEnableIntr(InstancePtr->BaseAddress,
				XIIC_INTR_TX_ERROR_MASK |
				XIIC_INTR_TX_EMPTY_MASK);

	/*
	 * When repeated start not used, MSMS must be set after putting data
	 * into transmit FIFO, start the transmitter.
	 */
	CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
	if ((CntlReg & XIIC_CR_MSMS_MASK) == 0) {
		CntlReg &= ~XIIC_CR_NO_ACK_MASK;
		CntlReg |= XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK;
		XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
			 CntlReg);
	}

	XIic_IntrGlobalEnable(InstancePtr->BaseAddress);

	return XST_SUCCESS;
}
/****************************************************************************/
/**
* This function sends data as a master on the IIC bus. If the bus is busy, it
* will indicate so and then enable an interrupt such that the status handler
* will be called when the bus is no longer busy.  The slave address which has
* been set with the XIic_SetAddress() function is the address to which the
* specific data is sent.  Sending data on the bus performs a write operation.
*
* @param	InstancePtr points to the Iic instance to be worked on.
* @param	TxMsgPtr points to the data to be transmitted.
* @param	ByteCount is the number of message bytes to be sent.
*
* @return
*		- XST_SUCCESS indicates the message transmission has been
*		initiated.
*		- XST_IIC_BUS_BUSY indicates the bus was in use and that
*		the BusNotBusy interrupt is enabled which will update the
*		EventStatus when the bus is no longer busy.
*
* @note		None.
*
******************************************************************************/
This function sends data as a master on the IIC bus. If the bus is busy, it
will indicate so and then enable an interrupt such that the status handler
will be called when the bus is no longer busy.  The slave address which has
been set with the XIic_SetAddress() function is the address to which the
specific data is sent.  Sending data on the bus performs a write operation.
This function sends data as a master on the IIC bus . If the bus is busy it will indicate so and then enable an interrupt such that the status handler will be called when the bus is no longer busy . The slave address which has been set with the XIic_SetAddress () function is the address to which the specific data is sent . Sending data on the bus performs a write operation .
int XIic_MasterSend(XIic *InstancePtr, u8 *TxMsgPtr, int ByteCount)
{
	u32 CntlReg;
	XIic_IntrGlobalDisable(InstancePtr->BaseAddress);
	XIIC_MASTER_INCLUDE;
	InstancePtr->IsDynamic = FALSE;
	if (IsBusBusy(InstancePtr)) {
		XIic_IntrGlobalEnable(InstancePtr->BaseAddress);
		return XST_IIC_BUS_BUSY;
	}
	CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
	if (CntlReg & XIIC_CR_MSMS_MASK) {
		CntlReg &= ~XIIC_CR_NO_ACK_MASK;
		CntlReg |= (XIIC_CR_DIR_IS_TX_MASK |
				XIIC_CR_REPEATED_START_MASK);
		XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
				CntlReg);
		InstancePtr->Stats.RepeatedStarts++;
	}
	InstancePtr->SendByteCount = ByteCount;
	InstancePtr->SendBufferPtr = TxMsgPtr;
	InstancePtr->RecvBufferPtr = NULL;
	if ((InstancePtr->Options & XII_SEND_10_BIT_OPTION) &&
		(InstancePtr->AddrOfSlave != 0)) {
		XIic_Send10BitAddrByte1(InstancePtr->AddrOfSlave,
					 XIIC_WRITE_OPERATION);
		XIic_Send10BitAddrByte2(InstancePtr->AddrOfSlave);
	} else {
		XIic_Send7BitAddr(InstancePtr->AddrOfSlave,
				   XIIC_WRITE_OPERATION);
	}
	InstancePtr->TxAddrMode = XIIC_TX_ADDR_SENT;
	if (InstancePtr->SendByteCount > 1) {
		XIic_TransmitFifoFill(InstancePtr, XIIC_MASTER_ROLE);
	}
	if (InstancePtr->SendByteCount > 1) {
		XIic_ClearEnableIntr(InstancePtr->BaseAddress,
					XIIC_INTR_TX_HALF_MASK);
	}
	XIic_ClearEnableIntr(InstancePtr->BaseAddress,
				XIIC_INTR_TX_ERROR_MASK |
				XIIC_INTR_TX_EMPTY_MASK);
	CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
	if ((CntlReg & XIIC_CR_MSMS_MASK) == 0) {
		CntlReg &= ~XIIC_CR_NO_ACK_MASK;
		CntlReg |= XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK;
		XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
			 CntlReg);
	}
	XIic_IntrGlobalEnable(InstancePtr->BaseAddress);
	return XST_SUCCESS;
}
int XIic_MasterSend ( XIic * InstancePtr , u8 * TxMsgPtr , int ByteCount ) { u32 CntlReg ; XIic_IntrGlobalDisable ( InstancePtr -> BaseAddress ) ; XIIC_MASTER_INCLUDE ; InstancePtr -> IsDynamic = FALSE ; if ( IsBusBusy ( InstancePtr ) ) { XIic_IntrGlobalEnable ( InstancePtr -> BaseAddress ) ; return XST_IIC_BUS_BUSY ; } CntlReg = XIic_ReadReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET ) ; if ( CntlReg & XIIC_CR_MSMS_MASK ) { CntlReg &= ~ XIIC_CR_NO_ACK_MASK ; CntlReg |= ( XIIC_CR_DIR_IS_TX_MASK | XIIC_CR_REPEATED_START_MASK ) ; XIic_WriteReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET , CntlReg ) ; InstancePtr -> Stats . RepeatedStarts ++ ; } InstancePtr -> SendByteCount = ByteCount ; InstancePtr -> SendBufferPtr = TxMsgPtr ; InstancePtr -> RecvBufferPtr = NULL ; if ( ( InstancePtr -> Options & XII_SEND_10_BIT_OPTION ) && ( InstancePtr -> AddrOfSlave != 0 ) ) { XIic_Send10BitAddrByte1 ( InstancePtr -> AddrOfSlave , XIIC_WRITE_OPERATION ) ; XIic_Send10BitAddrByte2 ( InstancePtr -> AddrOfSlave ) ; } else { XIic_Send7BitAddr ( InstancePtr -> AddrOfSlave , XIIC_WRITE_OPERATION ) ; } InstancePtr -> TxAddrMode = XIIC_TX_ADDR_SENT ; if ( InstancePtr -> SendByteCount > 1 ) { XIic_TransmitFifoFill ( InstancePtr , XIIC_MASTER_ROLE ) ; } if ( InstancePtr -> SendByteCount > 1 ) { XIic_ClearEnableIntr ( InstancePtr -> BaseAddress , XIIC_INTR_TX_HALF_MASK ) ; } XIic_ClearEnableIntr ( InstancePtr -> BaseAddress , XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK ) ; CntlReg = XIic_ReadReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET ) ; if ( ( CntlReg & XIIC_CR_MSMS_MASK ) == 0 ) { CntlReg &= ~ XIIC_CR_NO_ACK_MASK ; CntlReg |= XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK ; XIic_WriteReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET , CntlReg ) ; } XIic_IntrGlobalEnable ( InstancePtr -> BaseAddress ) ; return XST_SUCCESS ; }
This function sends data as a master on the IIC bus.
This function sends data as a master on the IIC bus .
/*
	 * Ensure that the master processing has been included such that events
	 * will be properly handled.
	 */ /*
	 * If the busy is busy, then exit the critical region and wait for the
	 * bus to not be busy, the function enables the bus not busy interrupt.
	 */ /*
	 * If it is already a master on the bus (repeated start), the direction
	 * was set to Tx which is throttling bus. The control register needs to
	 * be set before putting data into the FIFO.
	 */ /*
	 * Save message state.
	 */ /*
	 * Put the address into the FIFO to be sent and indicate that the
	 * operation to be performed on the bus is a write operation,
	 * a general call address is handled the same as a 7 bit address even
	 * if 10 bit address is selected.
	 * Set the transmit address state to indicate the address has been sent.
	 */ /*
	 * Set the transmit address state to indicate the address has been sent
	 * for communication with event driven processing.
	 */ /*
	 * Fill remaining available FIFO with message data.
	 */ /*
	 * After filling fifo, if data yet to send > 1, enable Tx � empty
	 * interrupt.
	 */ /*
	 * Clear any pending Tx empty, Tx Error and then enable them.
	 */ /*
	 * When repeated start not used, MSMS must be set after putting data
	 * into transmit FIFO, start the transmitter.
	 */