XilinxProcessorIPLib/drivers/aienginev2/src/core/xaie_core.c
static AieRC _XAie_CoreDebugCtrlHalt(XAie_DevInst *DevInst, XAie_LocType Loc,
		u8 Enable)
{
	u64 RegAddr;
	const XAie_CoreMod *CoreMod;
	u8 TileType;

	if((DevInst == XAIE_NULL) ||
			(DevInst->IsReady != XAIE_COMPONENT_IS_READY)) {
		XAIE_ERROR("Invalid Device Instance\n");
		return XAIE_INVALID_ARGS;
	}

	TileType = DevInst->DevOps->GetTTypefromLoc(DevInst, Loc);
	if(TileType != XAIEGBL_TILE_TYPE_AIETILE) {
		XAIE_ERROR("Invalid Tile Type\n");
		return XAIE_INVALID_TILE;
	}

	CoreMod = DevInst->DevProp.DevMod[TileType].CoreMod;

	RegAddr = CoreMod->CoreDebug->RegOff +
		_XAie_GetTileAddr(DevInst, Loc.Row, Loc.Col);

	return XAie_MaskWrite32(DevInst, RegAddr,
			CoreMod->CoreDebug->DebugHalt.Mask, Enable);
}
/*****************************************************************************/
/*
*
* This API writes to the Core debug control register to control the debug halt
* bit.
*
* @param	DevInst: Device Instance
* @param	Loc: Location of the AIE tile.
* @param	Enable: Enable/Disable the debug halt bit(1- Enable, 0-Disable).
* @return	XAIE_OK on success, Error code on failure.
*
* @note		Internal only.
*
******************************************************************************/
This API writes to the Core debug control register to control the debug halt
bit.
This API writes to the Core debug control register to control the debug halt bit .
static AieRC _XAie_CoreDebugCtrlHalt(XAie_DevInst *DevInst, XAie_LocType Loc,
		u8 Enable)
{
	u64 RegAddr;
	const XAie_CoreMod *CoreMod;
	u8 TileType;
	if((DevInst == XAIE_NULL) ||
			(DevInst->IsReady != XAIE_COMPONENT_IS_READY)) {
		XAIE_ERROR("Invalid Device Instance\n");
		return XAIE_INVALID_ARGS;
	}
	TileType = DevInst->DevOps->GetTTypefromLoc(DevInst, Loc);
	if(TileType != XAIEGBL_TILE_TYPE_AIETILE) {
		XAIE_ERROR("Invalid Tile Type\n");
		return XAIE_INVALID_TILE;
	}
	CoreMod = DevInst->DevProp.DevMod[TileType].CoreMod;
	RegAddr = CoreMod->CoreDebug->RegOff +
		_XAie_GetTileAddr(DevInst, Loc.Row, Loc.Col);
	return XAie_MaskWrite32(DevInst, RegAddr,
			CoreMod->CoreDebug->DebugHalt.Mask, Enable);
}
static AieRC _XAie_CoreDebugCtrlHalt ( XAie_DevInst * DevInst , XAie_LocType Loc , u8 Enable ) { u64 RegAddr ; const XAie_CoreMod * CoreMod ; u8 TileType ; if ( ( DevInst == XAIE_NULL ) || ( DevInst -> IsReady != XAIE_COMPONENT_IS_READY ) ) { XAIE_ERROR ( " \n " ) ; return XAIE_INVALID_ARGS ; } TileType = DevInst -> DevOps -> GetTTypefromLoc ( DevInst , Loc ) ; if ( TileType != XAIEGBL_TILE_TYPE_AIETILE ) { XAIE_ERROR ( " \n " ) ; return XAIE_INVALID_TILE ; } CoreMod = DevInst -> DevProp . DevMod [ TileType ] . CoreMod ; RegAddr = CoreMod -> CoreDebug -> RegOff + _XAie_GetTileAddr ( DevInst , Loc . Row , Loc . Col ) ; return XAie_MaskWrite32 ( DevInst , RegAddr , CoreMod -> CoreDebug -> DebugHalt . Mask , Enable ) ; }
This API writes to the Core debug control register to control the debug halt
bit.
This API writes to the Core debug control register to control the debug halt bit .