XilinxProcessorIPLib/drivers/axiethernet/examples/xaxiethernet_example_intr_mcdma.c
int AxiEthernetSgDmaIntrSingleFrameExample(XAxiEthernet *AxiEthernetInstancePtr,
					   XMcdma *DmaInstancePtr, u8 ChanId)
{
	int Status;
	u32 TxFrameLength;
	int PayloadSize = PAYLOAD_SIZE;
	XMcdma_ChanCtrl *Rx_Chan, *Tx_Chan;
	XMcdma_Bd *BdCurPtr;
	u32 CrBits, len, i;
	UINTPTR TxBufPtr;

	/*
	 * Clear variables shared with callbacks
	 */
	FramesRx = 0;
	FramesTx = 0;
	DeviceErrors = 0;
	memset(RxFrame,0,sizeof(RxFrame));
	memset(TxFrame,0,sizeof(TxFrame));

	Rx_Chan = XMcdma_GetMcdmaRxChan(DmaInstancePtr, ChanId);
	Tx_Chan = XMcdma_GetMcdmaTxChan(DmaInstancePtr, ChanId);

	AxiEnthernetSetMAC(AxiEthernetMAC, ChanId - 1);

	/*
	 * Set the MAC address
	 */
	Status = XAxiEthernet_SetMacAddress(AxiEthernetInstancePtr,
	                                    AxiEthernetMAC);
	if (Status != XST_SUCCESS) {
	      AxiEthernetUtilErrorTrap("Error setting MAC address");
	      return XST_FAILURE;
	}

	/*
	 * Calculate the frame length (not including FCS)
	 */
	if (Padding)
		TxFrameLength = XAE_HDR_SIZE + PayloadSize + Padding;
	else
		TxFrameLength = XAE_HDR_SIZE + PayloadSize;


	/*
	 * Setup packet to be transmitted
	 */
	AxiEthernetUtilFrameHdrFormatMAC(&TxFrame, AxiEthernetMAC);
	AxiEthernetUtilFrameHdrFormatType(&TxFrame, PayloadSize);
	AxiEthernetUtilFrameSetPayloadData(&TxFrame, PayloadSize);

	/*
	 * Flush the TX frame before giving it to DMA TX channel to transmit.
	 */
	Xil_DCacheFlushRange((UINTPTR)&TxFrame, TxFrameLength);

	/*
	 * Clear out receive packet memory area
	 */
	AxiEthernetUtilFrameMemClear(&RxFrame);

	/*
	 * Invalidate the RX frame before giving it to DMA RX channel to
	 * receive data.
	 */
	Xil_DCacheInvalidateRange((UINTPTR)&RxFrame, TxFrameLength);

	/*
	 * Make sure Tx and Rx are enabled
	 */
	Status = XAxiEthernet_SetOptions(AxiEthernetInstancePtr,
				     XAE_RECEIVER_ENABLE_OPTION |
				     XAE_TRANSMITTER_ENABLE_OPTION);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting options");
		return XST_FAILURE;
	}

	/*
	 * Start the Axi Ethernet and enable its ERROR interrupts
	 */
	XAxiEthernet_Start(AxiEthernetInstancePtr);

	/*
	 * Enable DMA RX interrupt.
	 *
	 * Interrupt coalescing parameters are left at their default settings
	 * which is to interrupt the processor after every frame has been
	 * processed by the DMA engine.
	 */
	XMcdma_IntrEnable(Rx_Chan, XMCDMA_IRQ_ALL_MASK);


	Status = XMcDma_ChanSubmit(Rx_Chan, (UINTPTR)&RxFrame,
				   TxFrameLength);
	if (Status != XST_SUCCESS) {
		xil_printf("ChanSubmit failed\n\r");
		return XST_FAILURE;
	}

	Status = XMcDma_ChanToHw(Rx_Chan);
	if (Status != XST_SUCCESS) {
			xil_printf("XMcDma_ChanToHw failed\n\r");
			return XST_FAILURE;
	}

	/*
	 * Enable DMA transmit interrupts
	 */
	XMcdma_IntrEnable(Tx_Chan, XMCDMA_IRQ_ALL_MASK);

	BdCurPtr = (XMcdma_Bd *)XMcdma_GetChanCurBd(Tx_Chan);
	TxBufPtr = (UINTPTR)&TxFrame;
	for (i = 0 ; i < 2 ; i++) {
		CrBits = 0;

		if (i == 0)
			len = 64;
		if (i == 1)
			len = TxFrameLength - 64;

		Status = XMcDma_ChanSubmit(Tx_Chan, TxBufPtr,
								   len);
		if (Status != XST_SUCCESS) {
			xil_printf("ChanSubmit failed\n\r");
			return XST_FAILURE;
		}
		if (i == 0) {
			CrBits |= XMCDMA_BD_CTRL_SOF_MASK;
		}
		if (i == 1) {
			CrBits |= XMCDMA_BD_CTRL_EOF_MASK;
		}

		XMcDma_BdSetCtrl(BdCurPtr, CrBits);
		XMCDMA_CACHE_FLUSH((UINTPTR)(BdCurPtr));
		TxBufPtr += 64;
		BdCurPtr = (XMcdma_Bd *)XMcdma_BdChainNextBd(Tx_Chan, BdCurPtr);
	}

	Status = XMcDma_ChanToHw(Tx_Chan);
	if (Status != XST_SUCCESS) {
		xil_printf("XMcDma_ChanToHw failed for Tx\n\r");
		return XST_FAILURE;
	}

	/*
	 * Wait for transmission to complete
	 */
	while (!FramesTx);


	/*
	 * Wait for Rx indication
	 */
	while (!FramesRx);

	/*
	 * Finished this example. If everything worked correctly, all TxBDs and
	 * RxBDs should be free for allocation. Stop the device.
	 */
	XAxiEthernet_Stop(AxiEthernetInstancePtr);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function demonstrates the usage of the Axi Ethernet by sending and
* receiving a single frame in SGDMA interrupt mode.
* The source packet will be described by two descriptors. It will be received
* into a buffer described by a single descriptor.
*
* @param	AxiEthernetInstancePtr is a pointer to the instance of the
*		Axi Ethernet component.
* @param	DmaInstancePtr is a pointer to the instance of the Dma
*		component.
* @param	ChanId is the MCDMA Channel number to be operate on.
*
* @return	-XST_SUCCESS to indicate success
*		-XST_FAILURE to indicate failure
*
* @note		None.
*
******************************************************************************/
This function demonstrates the usage of the Axi Ethernet by sending and
receiving a single frame in SGDMA interrupt mode.
The source packet will be described by two descriptors. It will be received
into a buffer described by a single descriptor.
This function demonstrates the usage of the Axi Ethernet by sending and receiving a single frame in SGDMA interrupt mode . The source packet will be described by two descriptors . It will be received into a buffer described by a single descriptor .
int AxiEthernetSgDmaIntrSingleFrameExample(XAxiEthernet *AxiEthernetInstancePtr,
					   XMcdma *DmaInstancePtr, u8 ChanId)
{
	int Status;
	u32 TxFrameLength;
	int PayloadSize = PAYLOAD_SIZE;
	XMcdma_ChanCtrl *Rx_Chan, *Tx_Chan;
	XMcdma_Bd *BdCurPtr;
	u32 CrBits, len, i;
	UINTPTR TxBufPtr;
	FramesRx = 0;
	FramesTx = 0;
	DeviceErrors = 0;
	memset(RxFrame,0,sizeof(RxFrame));
	memset(TxFrame,0,sizeof(TxFrame));
	Rx_Chan = XMcdma_GetMcdmaRxChan(DmaInstancePtr, ChanId);
	Tx_Chan = XMcdma_GetMcdmaTxChan(DmaInstancePtr, ChanId);
	AxiEnthernetSetMAC(AxiEthernetMAC, ChanId - 1);
	Status = XAxiEthernet_SetMacAddress(AxiEthernetInstancePtr,
	                                    AxiEthernetMAC);
	if (Status != XST_SUCCESS) {
	      AxiEthernetUtilErrorTrap("Error setting MAC address");
	      return XST_FAILURE;
	}
	if (Padding)
		TxFrameLength = XAE_HDR_SIZE + PayloadSize + Padding;
	else
		TxFrameLength = XAE_HDR_SIZE + PayloadSize;
	AxiEthernetUtilFrameHdrFormatMAC(&TxFrame, AxiEthernetMAC);
	AxiEthernetUtilFrameHdrFormatType(&TxFrame, PayloadSize);
	AxiEthernetUtilFrameSetPayloadData(&TxFrame, PayloadSize);
	Xil_DCacheFlushRange((UINTPTR)&TxFrame, TxFrameLength);
	AxiEthernetUtilFrameMemClear(&RxFrame);
	Xil_DCacheInvalidateRange((UINTPTR)&RxFrame, TxFrameLength);
	Status = XAxiEthernet_SetOptions(AxiEthernetInstancePtr,
				     XAE_RECEIVER_ENABLE_OPTION |
				     XAE_TRANSMITTER_ENABLE_OPTION);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting options");
		return XST_FAILURE;
	}
	XAxiEthernet_Start(AxiEthernetInstancePtr);
	XMcdma_IntrEnable(Rx_Chan, XMCDMA_IRQ_ALL_MASK);
	Status = XMcDma_ChanSubmit(Rx_Chan, (UINTPTR)&RxFrame,
				   TxFrameLength);
	if (Status != XST_SUCCESS) {
		xil_printf("ChanSubmit failed\n\r");
		return XST_FAILURE;
	}
	Status = XMcDma_ChanToHw(Rx_Chan);
	if (Status != XST_SUCCESS) {
			xil_printf("XMcDma_ChanToHw failed\n\r");
			return XST_FAILURE;
	}
	XMcdma_IntrEnable(Tx_Chan, XMCDMA_IRQ_ALL_MASK);
	BdCurPtr = (XMcdma_Bd *)XMcdma_GetChanCurBd(Tx_Chan);
	TxBufPtr = (UINTPTR)&TxFrame;
	for (i = 0 ; i < 2 ; i++) {
		CrBits = 0;
		if (i == 0)
			len = 64;
		if (i == 1)
			len = TxFrameLength - 64;
		Status = XMcDma_ChanSubmit(Tx_Chan, TxBufPtr,
								   len);
		if (Status != XST_SUCCESS) {
			xil_printf("ChanSubmit failed\n\r");
			return XST_FAILURE;
		}
		if (i == 0) {
			CrBits |= XMCDMA_BD_CTRL_SOF_MASK;
		}
		if (i == 1) {
			CrBits |= XMCDMA_BD_CTRL_EOF_MASK;
		}
		XMcDma_BdSetCtrl(BdCurPtr, CrBits);
		XMCDMA_CACHE_FLUSH((UINTPTR)(BdCurPtr));
		TxBufPtr += 64;
		BdCurPtr = (XMcdma_Bd *)XMcdma_BdChainNextBd(Tx_Chan, BdCurPtr);
	}
	Status = XMcDma_ChanToHw(Tx_Chan);
	if (Status != XST_SUCCESS) {
		xil_printf("XMcDma_ChanToHw failed for Tx\n\r");
		return XST_FAILURE;
	}
	while (!FramesTx);
	while (!FramesRx);
	XAxiEthernet_Stop(AxiEthernetInstancePtr);
	return XST_SUCCESS;
}
int AxiEthernetSgDmaIntrSingleFrameExample ( XAxiEthernet * AxiEthernetInstancePtr , XMcdma * DmaInstancePtr , u8 ChanId ) { int Status ; u32 TxFrameLength ; int PayloadSize = PAYLOAD_SIZE ; XMcdma_ChanCtrl * Rx_Chan , * Tx_Chan ; XMcdma_Bd * BdCurPtr ; u32 CrBits , len , i ; UINTPTR TxBufPtr ; FramesRx = 0 ; FramesTx = 0 ; DeviceErrors = 0 ; memset ( RxFrame , 0 , sizeof ( RxFrame ) ) ; memset ( TxFrame , 0 , sizeof ( TxFrame ) ) ; Rx_Chan = XMcdma_GetMcdmaRxChan ( DmaInstancePtr , ChanId ) ; Tx_Chan = XMcdma_GetMcdmaTxChan ( DmaInstancePtr , ChanId ) ; AxiEnthernetSetMAC ( AxiEthernetMAC , ChanId - 1 ) ; Status = XAxiEthernet_SetMacAddress ( AxiEthernetInstancePtr , AxiEthernetMAC ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } if ( Padding ) TxFrameLength = XAE_HDR_SIZE + PayloadSize + Padding ; else TxFrameLength = XAE_HDR_SIZE + PayloadSize ; AxiEthernetUtilFrameHdrFormatMAC ( & TxFrame , AxiEthernetMAC ) ; AxiEthernetUtilFrameHdrFormatType ( & TxFrame , PayloadSize ) ; AxiEthernetUtilFrameSetPayloadData ( & TxFrame , PayloadSize ) ; Xil_DCacheFlushRange ( ( UINTPTR ) & TxFrame , TxFrameLength ) ; AxiEthernetUtilFrameMemClear ( & RxFrame ) ; Xil_DCacheInvalidateRange ( ( UINTPTR ) & RxFrame , TxFrameLength ) ; Status = XAxiEthernet_SetOptions ( AxiEthernetInstancePtr , XAE_RECEIVER_ENABLE_OPTION | XAE_TRANSMITTER_ENABLE_OPTION ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } XAxiEthernet_Start ( AxiEthernetInstancePtr ) ; XMcdma_IntrEnable ( Rx_Chan , XMCDMA_IRQ_ALL_MASK ) ; Status = XMcDma_ChanSubmit ( Rx_Chan , ( UINTPTR ) & RxFrame , TxFrameLength ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } Status = XMcDma_ChanToHw ( Rx_Chan ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } XMcdma_IntrEnable ( Tx_Chan , XMCDMA_IRQ_ALL_MASK ) ; BdCurPtr = ( XMcdma_Bd * ) XMcdma_GetChanCurBd ( Tx_Chan ) ; TxBufPtr = ( UINTPTR ) & TxFrame ; for ( i = 0 ; i < 2 ; i ++ ) { CrBits = 0 ; if ( i == 0 ) len = 64 ; if ( i == 1 ) len = TxFrameLength - 64 ; Status = XMcDma_ChanSubmit ( Tx_Chan , TxBufPtr , len ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } if ( i == 0 ) { CrBits |= XMCDMA_BD_CTRL_SOF_MASK ; } if ( i == 1 ) { CrBits |= XMCDMA_BD_CTRL_EOF_MASK ; } XMcDma_BdSetCtrl ( BdCurPtr , CrBits ) ; XMCDMA_CACHE_FLUSH ( ( UINTPTR ) ( BdCurPtr ) ) ; TxBufPtr += 64 ; BdCurPtr = ( XMcdma_Bd * ) XMcdma_BdChainNextBd ( Tx_Chan , BdCurPtr ) ; } Status = XMcDma_ChanToHw ( Tx_Chan ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } while ( ! FramesTx ) ; while ( ! FramesRx ) ; XAxiEthernet_Stop ( AxiEthernetInstancePtr ) ; return XST_SUCCESS ; }
This function demonstrates the usage of the Axi Ethernet by sending and
receiving a single frame in SGDMA interrupt mode.
This function demonstrates the usage of the Axi Ethernet by sending and receiving a single frame in SGDMA interrupt mode .
/*
	 * Clear variables shared with callbacks
	 */ /*
	 * Set the MAC address
	 */ /*
	 * Calculate the frame length (not including FCS)
	 */ /*
	 * Setup packet to be transmitted
	 */ /*
	 * Flush the TX frame before giving it to DMA TX channel to transmit.
	 */ /*
	 * Clear out receive packet memory area
	 */ /*
	 * Invalidate the RX frame before giving it to DMA RX channel to
	 * receive data.
	 */ /*
	 * Make sure Tx and Rx are enabled
	 */ /*
	 * Start the Axi Ethernet and enable its ERROR interrupts
	 */ /*
	 * Enable DMA RX interrupt.
	 *
	 * Interrupt coalescing parameters are left at their default settings
	 * which is to interrupt the processor after every frame has been
	 * processed by the DMA engine.
	 */ /*
	 * Enable DMA transmit interrupts
	 */ /*
	 * Wait for transmission to complete
	 */ /*
	 * Wait for Rx indication
	 */ /*
	 * Finished this example. If everything worked correctly, all TxBDs and
	 * RxBDs should be free for allocation. Stop the device.
	 */