src/arch/socs/stm32f439/C/soc-exti.c
uint8_t soc_exti_enable(gpioref_t kref)
{
    /*
     * First, unable the Interrupt Mask Register for this line
     */
    set_reg_bits(EXTI_IMR, 0x1 << kref.pin);

    /*
     * Then enable the corresponding EXTI NVIC line
     */
    switch (kref.pin) {
        case 0:
            NVIC_EnableIRQ(EXTI0_IRQ - 0x10);
            break;
        case 1:
            NVIC_EnableIRQ(EXTI1_IRQ - 0x10);
            break;
        case 2:
            NVIC_EnableIRQ(EXTI2_IRQ - 0x10);
            break;
        case 3:
            NVIC_EnableIRQ(EXTI3_IRQ - 0x10);
            break;
        case 4:
            NVIC_EnableIRQ(EXTI4_IRQ - 0x10);
            break;
        case 5:
        case 6:
        case 7:
        case 8:
        case 9:
            NVIC_EnableIRQ(EXTI9_5_IRQ - 0x10);
            break;
        case 10:
        case 11:
        case 12:
        case 13:
        case 14:
        case 15:
            NVIC_EnableIRQ(EXTI15_10_IRQ - 0x10);
            break;
        default:
            break; /* Should never happend with 0xf mask */
    }
    return 0;
}
/*
 * Enable the EXTI line. This means:
 * 1) Activate the EXTI_IMR bit of the corresponding pin
 * 2) Enable the corresponding IRQ line in the NVIC(may be already done for
 * multiplexed EXTI IRQs)
 */
Enable the EXTI line. This means:
1) Activate the EXTI_IMR bit of the corresponding pin
2) Enable the corresponding IRQ line in the NVIC(may be already done for
multiplexed EXTI IRQs)
Enable the EXTI line . This means : 1 ) Activate the EXTI_IMR bit of the corresponding pin 2 ) Enable the corresponding IRQ line in the NVIC ( may be already done for multiplexed EXTI IRQs )
uint8_t soc_exti_enable(gpioref_t kref)
{
    set_reg_bits(EXTI_IMR, 0x1 << kref.pin);
    switch (kref.pin) {
        case 0:
            NVIC_EnableIRQ(EXTI0_IRQ - 0x10);
            break;
        case 1:
            NVIC_EnableIRQ(EXTI1_IRQ - 0x10);
            break;
        case 2:
            NVIC_EnableIRQ(EXTI2_IRQ - 0x10);
            break;
        case 3:
            NVIC_EnableIRQ(EXTI3_IRQ - 0x10);
            break;
        case 4:
            NVIC_EnableIRQ(EXTI4_IRQ - 0x10);
            break;
        case 5:
        case 6:
        case 7:
        case 8:
        case 9:
            NVIC_EnableIRQ(EXTI9_5_IRQ - 0x10);
            break;
        case 10:
        case 11:
        case 12:
        case 13:
        case 14:
        case 15:
            NVIC_EnableIRQ(EXTI15_10_IRQ - 0x10);
            break;
        default:
            break; 
    }
    return 0;
}
uint8_t soc_exti_enable ( gpioref_t kref ) { set_reg_bits ( EXTI_IMR , 0x1 << kref . pin ) ; switch ( kref . pin ) { case 0 : NVIC_EnableIRQ ( EXTI0_IRQ - 0x10 ) ; break ; case 1 : NVIC_EnableIRQ ( EXTI1_IRQ - 0x10 ) ; break ; case 2 : NVIC_EnableIRQ ( EXTI2_IRQ - 0x10 ) ; break ; case 3 : NVIC_EnableIRQ ( EXTI3_IRQ - 0x10 ) ; break ; case 4 : NVIC_EnableIRQ ( EXTI4_IRQ - 0x10 ) ; break ; case 5 : case 6 : case 7 : case 8 : case 9 : NVIC_EnableIRQ ( EXTI9_5_IRQ - 0x10 ) ; break ; case 10 : case 11 : case 12 : case 13 : case 14 : case 15 : NVIC_EnableIRQ ( EXTI15_10_IRQ - 0x10 ) ; break ; default : break ; } return 0 ; }
Enable the EXTI line.
Enable the EXTI line .
/*
     * First, unable the Interrupt Mask Register for this line
     */ /*
     * Then enable the corresponding EXTI NVIC line
     */ /* Should never happend with 0xf mask */