XilinxProcessorIPLib/drivers/v_hdmirx/src/xv_hdmirx_intr.c
static void HdmiRx_DdcIntrHandler(XV_HdmiRx *InstancePtr)
{
    u32 Status;

    /* Read Status register */
    Status = XV_HdmiRx_ReadReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET));

    /* Check for HDCP write event */
    if ((Status) & (XV_HDMIRX_DDC_STA_HDCP_WMSG_NEW_EVT_MASK)) {

        // Clear event flag
        XV_HdmiRx_WriteReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET), (XV_HDMIRX_DDC_STA_HDCP_WMSG_NEW_EVT_MASK));

        /* Callback */
        if (InstancePtr->IsHdcpCallbackSet) {
            InstancePtr->HdcpCallback(InstancePtr->HdcpRef, XV_HDMIRX_DDC_STA_HDCP_WMSG_NEW_EVT_MASK);
        }
    }

    /* Check for HDCP read event */
    if ((Status) & (XV_HDMIRX_DDC_STA_HDCP_RMSG_END_EVT_MASK)) {

        // Clear event flag
        XV_HdmiRx_WriteReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET), (XV_HDMIRX_DDC_STA_HDCP_RMSG_END_EVT_MASK));

        /* Callback */
        if (InstancePtr->IsHdcpCallbackSet) {
            InstancePtr->HdcpCallback(InstancePtr->HdcpRef, XV_HDMIRX_DDC_STA_HDCP_RMSG_END_EVT_MASK);
        }
    }

    /* Check for HDCP read not complete event */
    if ((Status) & (XV_HDMIRX_DDC_STA_HDCP_RMSG_NC_EVT_MASK)) {

        // Clear event flag
        XV_HdmiRx_WriteReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET), (XV_HDMIRX_DDC_STA_HDCP_RMSG_NC_EVT_MASK));

        /* Callback */
        if (InstancePtr->IsHdcpCallbackSet) {
            InstancePtr->HdcpCallback(InstancePtr->HdcpRef, XV_HDMIRX_DDC_STA_HDCP_RMSG_NC_EVT_MASK);
        }
    }

    /* Check for HDCP 1.4 Aksv event */
    if ((Status) & (XV_HDMIRX_DDC_STA_HDCP_AKSV_EVT_MASK)) {

        // Clear event flag
        XV_HdmiRx_WriteReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET), (XV_HDMIRX_DDC_STA_HDCP_AKSV_EVT_MASK));

        /* Callback */
        if (InstancePtr->IsHdcpCallbackSet) {
            InstancePtr->HdcpCallback(InstancePtr->HdcpRef, XV_HDMIRX_DDC_STA_HDCP_AKSV_EVT_MASK);
        }
    }

    /* Check for HDCP 1.4 protocol event */
    if ((Status) & (XV_HDMIRX_DDC_STA_HDCP_1_PROT_EVT_MASK)) {

        // Clear event flag
        XV_HdmiRx_WriteReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET), (XV_HDMIRX_DDC_STA_HDCP_1_PROT_EVT_MASK));

        /* Callback */
        if (InstancePtr->IsHdcp14ProtEvtCallbackSet) {
            InstancePtr->Hdcp14ProtEvtCallback(InstancePtr->Hdcp14ProtEvtRef);
        }
    }

    /* Check for HDCP 2.2 protocol event */
    if ((Status) & (XV_HDMIRX_DDC_STA_HDCP_2_PROT_EVT_MASK)) {

        // Clear event flag
        XV_HdmiRx_WriteReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET), (XV_HDMIRX_DDC_STA_HDCP_2_PROT_EVT_MASK));

        /* Callback */
        if (InstancePtr->IsHdcp22ProtEvtCallbackSet) {
            InstancePtr->Hdcp22ProtEvtCallback(InstancePtr->Hdcp22ProtEvtRef);
        }
    }

}
/*****************************************************************************/
/**
*
* This function is the interrupt handler for the HDMI RX DDC peripheral.
*
* @param    InstancePtr is a pointer to the XV_HdmiRx core instance.
*
* @return   None.
*
* @note     None.
*
******************************************************************************/
This function is the interrupt handler for the HDMI RX DDC peripheral.
This function is the interrupt handler for the HDMI RX DDC peripheral .
static void HdmiRx_DdcIntrHandler(XV_HdmiRx *InstancePtr)
{
    u32 Status;
    Status = XV_HdmiRx_ReadReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET));
    if ((Status) & (XV_HDMIRX_DDC_STA_HDCP_WMSG_NEW_EVT_MASK)) {
        XV_HdmiRx_WriteReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET), (XV_HDMIRX_DDC_STA_HDCP_WMSG_NEW_EVT_MASK));
        if (InstancePtr->IsHdcpCallbackSet) {
            InstancePtr->HdcpCallback(InstancePtr->HdcpRef, XV_HDMIRX_DDC_STA_HDCP_WMSG_NEW_EVT_MASK);
        }
    }
    if ((Status) & (XV_HDMIRX_DDC_STA_HDCP_RMSG_END_EVT_MASK)) {
        XV_HdmiRx_WriteReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET), (XV_HDMIRX_DDC_STA_HDCP_RMSG_END_EVT_MASK));
        if (InstancePtr->IsHdcpCallbackSet) {
            InstancePtr->HdcpCallback(InstancePtr->HdcpRef, XV_HDMIRX_DDC_STA_HDCP_RMSG_END_EVT_MASK);
        }
    }
    if ((Status) & (XV_HDMIRX_DDC_STA_HDCP_RMSG_NC_EVT_MASK)) {
        XV_HdmiRx_WriteReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET), (XV_HDMIRX_DDC_STA_HDCP_RMSG_NC_EVT_MASK));
        if (InstancePtr->IsHdcpCallbackSet) {
            InstancePtr->HdcpCallback(InstancePtr->HdcpRef, XV_HDMIRX_DDC_STA_HDCP_RMSG_NC_EVT_MASK);
        }
    }
    if ((Status) & (XV_HDMIRX_DDC_STA_HDCP_AKSV_EVT_MASK)) {
        XV_HdmiRx_WriteReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET), (XV_HDMIRX_DDC_STA_HDCP_AKSV_EVT_MASK));
        if (InstancePtr->IsHdcpCallbackSet) {
            InstancePtr->HdcpCallback(InstancePtr->HdcpRef, XV_HDMIRX_DDC_STA_HDCP_AKSV_EVT_MASK);
        }
    }
    if ((Status) & (XV_HDMIRX_DDC_STA_HDCP_1_PROT_EVT_MASK)) {
        XV_HdmiRx_WriteReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET), (XV_HDMIRX_DDC_STA_HDCP_1_PROT_EVT_MASK));
        if (InstancePtr->IsHdcp14ProtEvtCallbackSet) {
            InstancePtr->Hdcp14ProtEvtCallback(InstancePtr->Hdcp14ProtEvtRef);
        }
    }
    if ((Status) & (XV_HDMIRX_DDC_STA_HDCP_2_PROT_EVT_MASK)) {
        XV_HdmiRx_WriteReg(InstancePtr->Config.BaseAddress, (XV_HDMIRX_DDC_STA_OFFSET), (XV_HDMIRX_DDC_STA_HDCP_2_PROT_EVT_MASK));
        if (InstancePtr->IsHdcp22ProtEvtCallbackSet) {
            InstancePtr->Hdcp22ProtEvtCallback(InstancePtr->Hdcp22ProtEvtRef);
        }
    }
}
static void HdmiRx_DdcIntrHandler ( XV_HdmiRx * InstancePtr ) { u32 Status ; Status = XV_HdmiRx_ReadReg ( InstancePtr -> Config . BaseAddress , ( XV_HDMIRX_DDC_STA_OFFSET ) ) ; if ( ( Status ) & ( XV_HDMIRX_DDC_STA_HDCP_WMSG_NEW_EVT_MASK ) ) { XV_HdmiRx_WriteReg ( InstancePtr -> Config . BaseAddress , ( XV_HDMIRX_DDC_STA_OFFSET ) , ( XV_HDMIRX_DDC_STA_HDCP_WMSG_NEW_EVT_MASK ) ) ; if ( InstancePtr -> IsHdcpCallbackSet ) { InstancePtr -> HdcpCallback ( InstancePtr -> HdcpRef , XV_HDMIRX_DDC_STA_HDCP_WMSG_NEW_EVT_MASK ) ; } } if ( ( Status ) & ( XV_HDMIRX_DDC_STA_HDCP_RMSG_END_EVT_MASK ) ) { XV_HdmiRx_WriteReg ( InstancePtr -> Config . BaseAddress , ( XV_HDMIRX_DDC_STA_OFFSET ) , ( XV_HDMIRX_DDC_STA_HDCP_RMSG_END_EVT_MASK ) ) ; if ( InstancePtr -> IsHdcpCallbackSet ) { InstancePtr -> HdcpCallback ( InstancePtr -> HdcpRef , XV_HDMIRX_DDC_STA_HDCP_RMSG_END_EVT_MASK ) ; } } if ( ( Status ) & ( XV_HDMIRX_DDC_STA_HDCP_RMSG_NC_EVT_MASK ) ) { XV_HdmiRx_WriteReg ( InstancePtr -> Config . BaseAddress , ( XV_HDMIRX_DDC_STA_OFFSET ) , ( XV_HDMIRX_DDC_STA_HDCP_RMSG_NC_EVT_MASK ) ) ; if ( InstancePtr -> IsHdcpCallbackSet ) { InstancePtr -> HdcpCallback ( InstancePtr -> HdcpRef , XV_HDMIRX_DDC_STA_HDCP_RMSG_NC_EVT_MASK ) ; } } if ( ( Status ) & ( XV_HDMIRX_DDC_STA_HDCP_AKSV_EVT_MASK ) ) { XV_HdmiRx_WriteReg ( InstancePtr -> Config . BaseAddress , ( XV_HDMIRX_DDC_STA_OFFSET ) , ( XV_HDMIRX_DDC_STA_HDCP_AKSV_EVT_MASK ) ) ; if ( InstancePtr -> IsHdcpCallbackSet ) { InstancePtr -> HdcpCallback ( InstancePtr -> HdcpRef , XV_HDMIRX_DDC_STA_HDCP_AKSV_EVT_MASK ) ; } } if ( ( Status ) & ( XV_HDMIRX_DDC_STA_HDCP_1_PROT_EVT_MASK ) ) { XV_HdmiRx_WriteReg ( InstancePtr -> Config . BaseAddress , ( XV_HDMIRX_DDC_STA_OFFSET ) , ( XV_HDMIRX_DDC_STA_HDCP_1_PROT_EVT_MASK ) ) ; if ( InstancePtr -> IsHdcp14ProtEvtCallbackSet ) { InstancePtr -> Hdcp14ProtEvtCallback ( InstancePtr -> Hdcp14ProtEvtRef ) ; } } if ( ( Status ) & ( XV_HDMIRX_DDC_STA_HDCP_2_PROT_EVT_MASK ) ) { XV_HdmiRx_WriteReg ( InstancePtr -> Config . BaseAddress , ( XV_HDMIRX_DDC_STA_OFFSET ) , ( XV_HDMIRX_DDC_STA_HDCP_2_PROT_EVT_MASK ) ) ; if ( InstancePtr -> IsHdcp22ProtEvtCallbackSet ) { InstancePtr -> Hdcp22ProtEvtCallback ( InstancePtr -> Hdcp22ProtEvtRef ) ; } } }
This function is the interrupt handler for the HDMI RX DDC peripheral.
This function is the interrupt handler for the HDMI RX DDC peripheral .
/* Read Status register */ /* Check for HDCP write event */ // Clear event flag /* Callback */ /* Check for HDCP read event */ // Clear event flag /* Callback */ /* Check for HDCP read not complete event */ // Clear event flag /* Callback */ /* Check for HDCP 1.4 Aksv event */ // Clear event flag /* Callback */ /* Check for HDCP 1.4 protocol event */ // Clear event flag /* Callback */ /* Check for HDCP 2.2 protocol event */ // Clear event flag /* Callback */