src/optimize.c
static bool is_no_mem_access(gbz80_inst *inst, int opt_level)
{
    switch (inst->opcode) {
    case NOP:
    case ADD16:
    case SWAP:
    case DAA:
    case CP:
    case BIT:
    case RST:
    case JR:
    case JP:
    case RET:
    case CALL:
    case JP_BWD:
    case JP_TARGET:
    case LD16:
    case RR:
    case RL:
    case RRC:
    case RLC:
        return true;
    case LD:
        if (inst->op2 == MEM_C || inst->op2 == MEM_8)
            return false;

        /* mostly in connection with a memcpy */
        if (opt_level == 3 && inst->op1 == MEM_INC_DE)
            return true;

        /* Writing access and reading from HL is usually fine */
        if (opt_level < 3 &&
            (inst->op1 == MEM_HL || inst->op2 == MEM_HL ||
             inst->op1 == MEM_INC_HL || inst->op2 == MEM_INC_HL ||
             inst->op1 == MEM_DEC_HL || inst->op2 == MEM_DEC_HL ||
             inst->op1 == MEM_C || inst->op1 == MEM_8))
            return false;

        return true;
    case AND:
    case OR:
    case XOR:
        return inst->op2 == MEM_HL ? false : true;
    case ADD:
    case SUB:
        return true;
    case PUSH:
    case POP:
        return true;
    case INC:
    case DEC:
    case INC16:
    case DEC16:
        return (opt_level == 3) ? true : ((inst->op1 == MEM_HL) ? false : true);
    default:
        return false;
    }
}
/* Instruction without memory access (read / write) or other side effects
 * that can be influenced by an interrupt.
 */
Instruction without memory access (read / write) or other side effects
that can be influenced by an interrupt.
Instruction without memory access ( read / write ) or other side effects that can be influenced by an interrupt .
static bool is_no_mem_access(gbz80_inst *inst, int opt_level)
{
    switch (inst->opcode) {
    case NOP:
    case ADD16:
    case SWAP:
    case DAA:
    case CP:
    case BIT:
    case RST:
    case JR:
    case JP:
    case RET:
    case CALL:
    case JP_BWD:
    case JP_TARGET:
    case LD16:
    case RR:
    case RL:
    case RRC:
    case RLC:
        return true;
    case LD:
        if (inst->op2 == MEM_C || inst->op2 == MEM_8)
            return false;
        if (opt_level == 3 && inst->op1 == MEM_INC_DE)
            return true;
        if (opt_level < 3 &&
            (inst->op1 == MEM_HL || inst->op2 == MEM_HL ||
             inst->op1 == MEM_INC_HL || inst->op2 == MEM_INC_HL ||
             inst->op1 == MEM_DEC_HL || inst->op2 == MEM_DEC_HL ||
             inst->op1 == MEM_C || inst->op1 == MEM_8))
            return false;
        return true;
    case AND:
    case OR:
    case XOR:
        return inst->op2 == MEM_HL ? false : true;
    case ADD:
    case SUB:
        return true;
    case PUSH:
    case POP:
        return true;
    case INC:
    case DEC:
    case INC16:
    case DEC16:
        return (opt_level == 3) ? true : ((inst->op1 == MEM_HL) ? false : true);
    default:
        return false;
    }
}
static bool is_no_mem_access ( gbz80_inst * inst , int opt_level ) { switch ( inst -> opcode ) { case NOP : case ADD16 : case SWAP : case DAA : case CP : case BIT : case RST : case JR : case JP : case RET : case CALL : case JP_BWD : case JP_TARGET : case LD16 : case RR : case RL : case RRC : case RLC : return true ; case LD : if ( inst -> op2 == MEM_C || inst -> op2 == MEM_8 ) return false ; if ( opt_level == 3 && inst -> op1 == MEM_INC_DE ) return true ; if ( opt_level < 3 && ( inst -> op1 == MEM_HL || inst -> op2 == MEM_HL || inst -> op1 == MEM_INC_HL || inst -> op2 == MEM_INC_HL || inst -> op1 == MEM_DEC_HL || inst -> op2 == MEM_DEC_HL || inst -> op1 == MEM_C || inst -> op1 == MEM_8 ) ) return false ; return true ; case AND : case OR : case XOR : return inst -> op2 == MEM_HL ? false : true ; case ADD : case SUB : return true ; case PUSH : case POP : return true ; case INC : case DEC : case INC16 : case DEC16 : return ( opt_level == 3 ) ? true : ( ( inst -> op1 == MEM_HL ) ? false : true ) ; default : return false ; } }
Instruction without memory access (read / write) or other side effects
 that can be influenced by an interrupt.
Instruction without memory access ( read / write ) or other side effects that can be influenced by an interrupt .
/* mostly in connection with a memcpy */ /* Writing access and reading from HL is usually fine */