XilinxProcessorIPLib/drivers/intc/src/xintc.c
void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id)
{
	u32 Imr;
	u32 CurrentIER;
	u32 Mask;
	XIntc_Config *CfgPtr;

	/*
	 * Assert the arguments
	 */
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertVoid(InstancePtr->CfgPtr->FastIntr == TRUE);

	if (Id > 31) {
		/* Enable user required Id in Slave controller */
		CfgPtr = XIntc_LookupConfig(Id/32);
		if (CfgPtr == NULL) {
			return;
		}

		/* Get the Enabled Interrupts */
		CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);

		/* Convert from integer id to bit mask */
		Mask = XIntc_BitPosMask[(Id%32)];

		/* Disable the Interrupt if it was enabled before calling
		 * this function
		 */
		if (CurrentIER & Mask) {
			XIntc_Disable(InstancePtr, Id);
		}

		/* Slave controllers in Cascade Mode should have all as Fast
		 * interrupts or Normal interrupts, mixed interrupts are not
		 * supported
		 */
		XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0x0);

#ifdef XPAR_MICROBLAZE_BASE_VECTORS
		if (CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out64(CfgPtr->BaseAddress + XIN_IVEAR_OFFSET
					+ (Id * 8), XPAR_MICROBLAZE_BASE_VECTORS
					+ 0x10);
			}
		} else {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET
					+ (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS
					+ 0x10);
			}
		}
#else
		if (CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out64(CfgPtr->BaseAddress + XIN_IVEAR_OFFSET
							+ (Id * 8), 0x10);
			}
		} else {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET
							+ (Id * 4), 0x10);
			}
		}
#endif

		/* Enable the Interrupt if it was enabled before calling this
		 * function
		 */
		if (CurrentIER & Mask) {
			XIntc_Enable(InstancePtr, Id);
		}

	}
	else {

		/* Get the Enabled Interrupts */
		CurrentIER = XIntc_In32(InstancePtr->BaseAddress + XIN_IER_OFFSET);
		Mask = XIntc_BitPosMask[Id];/* Convert from integer id to bit mask */


		/* Disable the Interrupt if it was enabled before
		 * calling this function
		 */
		if (CurrentIER & Mask) {
			XIntc_Disable(InstancePtr, Id);
		}

		/*
		 * Disable the selected interrupt as Fast Interrupt by reading the
		 * interrupt mode register and then modifying only the
		 * specified interrupt id
		 */
		Imr = XIntc_In32(InstancePtr->BaseAddress + XIN_IMR_OFFSET);
		XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET,
						    Imr & ~Mask);

#ifdef XPAR_MICROBLAZE_BASE_VECTORS
		if (InstancePtr->CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out64(InstancePtr->BaseAddress + XIN_IVEAR_OFFSET
					+ (Id * 8), XPAR_MICROBLAZE_BASE_VECTORS
					+ 0x10);
			}
		} else {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
					+ (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS
					+ 0x10);
			}
		}
#else
		if (InstancePtr->CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out64(InstancePtr->BaseAddress + XIN_IVEAR_OFFSET
								+ (Id * 8), 0x10);
			}
		} else {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
								+ (Id * 4), 0x10);
			}
		}
#endif
		/* Enable the Interrupt if it was enabled before
		 * calling this function
		 */
		if (CurrentIER & Mask) {
			XIntc_Enable(InstancePtr, Id);
		}
	}
}
/*****************************************************************************/
/**
*
* Sets the normal interrupt mode for the specified interrupt in the Interrupt
* Mode Register. In Cascade mode disconnects handler from corresponding Slave
* controller IVAR/IVEAR register depending on the Id and sets all interrupt
* sources of the Slave controller as normal interrupts.
*
* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
* @param	Id contains the ID of the interrupt source and should be in the
*		range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being the
*		highest priority interrupt.
*
* @return	None.
*
* @note
*		Slave controllers in Cascade Mode should have all as Fast
* 		interrupts or Normal interrupts, mixed interrupts are not
*		supported
*
****************************************************************************/
Sets the normal interrupt mode for the specified interrupt in the Interrupt
Mode Register. In Cascade mode disconnects handler from corresponding Slave
controller IVAR/IVEAR register depending on the Id and sets all interrupt
sources of the Slave controller as normal interrupts.
Sets the normal interrupt mode for the specified interrupt in the Interrupt Mode Register . In Cascade mode disconnects handler from corresponding Slave controller IVAR / IVEAR register depending on the Id and sets all interrupt sources of the Slave controller as normal interrupts .
void XIntc_SetNormalIntrMode(XIntc *InstancePtr, u8 Id)
{
	u32 Imr;
	u32 CurrentIER;
	u32 Mask;
	XIntc_Config *CfgPtr;
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertVoid(InstancePtr->CfgPtr->FastIntr == TRUE);
	if (Id > 31) {
		CfgPtr = XIntc_LookupConfig(Id/32);
		if (CfgPtr == NULL) {
			return;
		}
		CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
		Mask = XIntc_BitPosMask[(Id%32)];
		if (CurrentIER & Mask) {
			XIntc_Disable(InstancePtr, Id);
		}
		XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0x0);
#ifdef XPAR_MICROBLAZE_BASE_VECTORS
		if (CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out64(CfgPtr->BaseAddress + XIN_IVEAR_OFFSET
					+ (Id * 8), XPAR_MICROBLAZE_BASE_VECTORS
					+ 0x10);
			}
		} else {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET
					+ (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS
					+ 0x10);
			}
		}
#else
		if (CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out64(CfgPtr->BaseAddress + XIN_IVEAR_OFFSET
							+ (Id * 8), 0x10);
			}
		} else {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET
							+ (Id * 4), 0x10);
			}
		}
#endif
		if (CurrentIER & Mask) {
			XIntc_Enable(InstancePtr, Id);
		}
	}
	else {
		CurrentIER = XIntc_In32(InstancePtr->BaseAddress + XIN_IER_OFFSET);
		Mask = XIntc_BitPosMask[Id];
		if (CurrentIER & Mask) {
			XIntc_Disable(InstancePtr, Id);
		}
		Imr = XIntc_In32(InstancePtr->BaseAddress + XIN_IMR_OFFSET);
		XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET,
						    Imr & ~Mask);
#ifdef XPAR_MICROBLAZE_BASE_VECTORS
		if (InstancePtr->CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out64(InstancePtr->BaseAddress + XIN_IVEAR_OFFSET
					+ (Id * 8), XPAR_MICROBLAZE_BASE_VECTORS
					+ 0x10);
			}
		} else {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
					+ (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS
					+ 0x10);
			}
		}
#else
		if (InstancePtr->CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out64(InstancePtr->BaseAddress + XIN_IVEAR_OFFSET
								+ (Id * 8), 0x10);
			}
		} else {
			for (Id = 0; Id < 32 ; Id++)
			{
				XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
								+ (Id * 4), 0x10);
			}
		}
#endif
		if (CurrentIER & Mask) {
			XIntc_Enable(InstancePtr, Id);
		}
	}
}
void XIntc_SetNormalIntrMode ( XIntc * InstancePtr , u8 Id ) { u32 Imr ; u32 CurrentIER ; u32 Mask ; XIntc_Config * CfgPtr ; Xil_AssertVoid ( InstancePtr != NULL ) ; Xil_AssertVoid ( Id < XPAR_INTC_MAX_NUM_INTR_INPUTS ) ; Xil_AssertVoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Xil_AssertVoid ( InstancePtr -> CfgPtr -> FastIntr == TRUE ) ; if ( Id > 31 ) { CfgPtr = XIntc_LookupConfig ( Id / 32 ) ; if ( CfgPtr == NULL ) { return ; } CurrentIER = XIntc_In32 ( CfgPtr -> BaseAddress + XIN_IER_OFFSET ) ; Mask = XIntc_BitPosMask [ ( Id % 32 ) ] ; if ( CurrentIER & Mask ) { XIntc_Disable ( InstancePtr , Id ) ; } XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_IMR_OFFSET , 0x0 ) ; #ifdef XPAR_MICROBLAZE_BASE_VECTORS if ( CfgPtr -> VectorAddrWidth > XINTC_STANDARD_VECTOR_ADDRESS_WIDTH ) { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out64 ( CfgPtr -> BaseAddress + XIN_IVEAR_OFFSET + ( Id * 8 ) , XPAR_MICROBLAZE_BASE_VECTORS + 0x10 ) ; } } else { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_IVAR_OFFSET + ( Id * 4 ) , XPAR_MICROBLAZE_BASE_VECTORS + 0x10 ) ; } } #else if ( CfgPtr -> VectorAddrWidth > XINTC_STANDARD_VECTOR_ADDRESS_WIDTH ) { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out64 ( CfgPtr -> BaseAddress + XIN_IVEAR_OFFSET + ( Id * 8 ) , 0x10 ) ; } } else { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_IVAR_OFFSET + ( Id * 4 ) , 0x10 ) ; } } #endif if ( CurrentIER & Mask ) { XIntc_Enable ( InstancePtr , Id ) ; } } else { CurrentIER = XIntc_In32 ( InstancePtr -> BaseAddress + XIN_IER_OFFSET ) ; Mask = XIntc_BitPosMask [ Id ] ; if ( CurrentIER & Mask ) { XIntc_Disable ( InstancePtr , Id ) ; } Imr = XIntc_In32 ( InstancePtr -> BaseAddress + XIN_IMR_OFFSET ) ; XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_IMR_OFFSET , Imr & ~ Mask ) ; #ifdef XPAR_MICROBLAZE_BASE_VECTORS if ( InstancePtr -> CfgPtr -> VectorAddrWidth > XINTC_STANDARD_VECTOR_ADDRESS_WIDTH ) { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out64 ( InstancePtr -> BaseAddress + XIN_IVEAR_OFFSET + ( Id * 8 ) , XPAR_MICROBLAZE_BASE_VECTORS + 0x10 ) ; } } else { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_IVAR_OFFSET + ( Id * 4 ) , XPAR_MICROBLAZE_BASE_VECTORS + 0x10 ) ; } } #else if ( InstancePtr -> CfgPtr -> VectorAddrWidth > XINTC_STANDARD_VECTOR_ADDRESS_WIDTH ) { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out64 ( InstancePtr -> BaseAddress + XIN_IVEAR_OFFSET + ( Id * 8 ) , 0x10 ) ; } } else { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_IVAR_OFFSET + ( Id * 4 ) , 0x10 ) ; } } #endif if ( CurrentIER & Mask ) { XIntc_Enable ( InstancePtr , Id ) ; } } }
Sets the normal interrupt mode for the specified interrupt in the Interrupt
Mode Register.
Sets the normal interrupt mode for the specified interrupt in the Interrupt Mode Register .
/*
	 * Assert the arguments
	 */ /* Enable user required Id in Slave controller */ /* Get the Enabled Interrupts */ /* Convert from integer id to bit mask */ /* Disable the Interrupt if it was enabled before calling
		 * this function
		 */ /* Slave controllers in Cascade Mode should have all as Fast
		 * interrupts or Normal interrupts, mixed interrupts are not
		 * supported
		 */ /* Enable the Interrupt if it was enabled before calling this
		 * function
		 */ /* Get the Enabled Interrupts */ /* Convert from integer id to bit mask */ /* Disable the Interrupt if it was enabled before
		 * calling this function
		 */ /*
		 * Disable the selected interrupt as Fast Interrupt by reading the
		 * interrupt mode register and then modifying only the
		 * specified interrupt id
		 */ /* Enable the Interrupt if it was enabled before
		 * calling this function
		 */