src/dpdk/drivers/net/mlx5/mlx5_txq.c
static int
txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)
{
	struct mlx5_priv *priv = txq_ctrl->priv;
	struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
	struct mlx5_txq_data *txq = &txq_ctrl->txq;
	void *addr;
	uintptr_t uar_va;
	uintptr_t offset;
	const size_t page_size = rte_mem_page_size();
	if (page_size == (size_t)-1) {
		DRV_LOG(ERR, "Failed to get mem page size");
		rte_errno = ENOMEM;
		return -rte_errno;
	}

	if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
		return 0;
	MLX5_ASSERT(ppriv);
	/*
	 * As rdma-core, UARs are mapped in size of OS page
	 * size. Ref to libmlx5 function: mlx5_init_context()
	 */
	uar_va = (uintptr_t)txq_ctrl->bf_reg;
	offset = uar_va & (page_size - 1); /* Offset in page. */
	addr = rte_mem_map(NULL, page_size, RTE_PROT_WRITE, RTE_MAP_SHARED,
			    fd, txq_ctrl->uar_mmap_offset);
	if (!addr) {
		DRV_LOG(ERR,
			"port %u mmap failed for BF reg of txq %u",
			txq->port_id, txq->idx);
		rte_errno = ENXIO;
		return -rte_errno;
	}
	addr = RTE_PTR_ADD(addr, offset);
	ppriv->uar_table[txq->idx] = addr;
	txq_uar_ncattr_init(txq_ctrl, page_size);
	return 0;
}
/**
 * Remap UAR register of a Tx queue for secondary process.
 *
 * Remapped address is stored at the table in the process private structure of
 * the device, indexed by queue index.
 *
 * @param txq_ctrl
 *   Pointer to Tx queue control structure.
 * @param fd
 *   Verbs file descriptor to map UAR pages.
 *
 * @return
 *   0 on success, a negative errno value otherwise and rte_errno is set.
 */
Remap UAR register of a Tx queue for secondary process.
Remapped address is stored at the table in the process private structure of
the device, indexed by queue index.

@param txq_ctrl
Pointer to Tx queue control structure.
@param fd
Verbs file descriptor to map UAR pages.

@return
0 on success, a negative errno value otherwise and rte_errno is set.
Remap UAR register of a Tx queue for secondary process . Remapped address is stored at the table in the process private structure of the device indexed by queue index . @param txq_ctrl Pointer to Tx queue control structure . @param fd Verbs file descriptor to map UAR pages . @return 0 on success a negative errno value otherwise and rte_errno is set .
static int
txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)
{
	struct mlx5_priv *priv = txq_ctrl->priv;
	struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
	struct mlx5_txq_data *txq = &txq_ctrl->txq;
	void *addr;
	uintptr_t uar_va;
	uintptr_t offset;
	const size_t page_size = rte_mem_page_size();
	if (page_size == (size_t)-1) {
		DRV_LOG(ERR, "Failed to get mem page size");
		rte_errno = ENOMEM;
		return -rte_errno;
	}
	if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
		return 0;
	MLX5_ASSERT(ppriv);
	uar_va = (uintptr_t)txq_ctrl->bf_reg;
	offset = uar_va & (page_size - 1); 
	addr = rte_mem_map(NULL, page_size, RTE_PROT_WRITE, RTE_MAP_SHARED,
			    fd, txq_ctrl->uar_mmap_offset);
	if (!addr) {
		DRV_LOG(ERR,
			"port %u mmap failed for BF reg of txq %u",
			txq->port_id, txq->idx);
		rte_errno = ENXIO;
		return -rte_errno;
	}
	addr = RTE_PTR_ADD(addr, offset);
	ppriv->uar_table[txq->idx] = addr;
	txq_uar_ncattr_init(txq_ctrl, page_size);
	return 0;
}
static int txq_uar_init_secondary ( struct mlx5_txq_ctrl * txq_ctrl , int fd ) { struct mlx5_priv * priv = txq_ctrl -> priv ; struct mlx5_proc_priv * ppriv = MLX5_PROC_PRIV ( PORT_ID ( priv ) ) ; struct mlx5_txq_data * txq = & txq_ctrl -> txq ; void * addr ; uintptr_t uar_va ; uintptr_t offset ; const size_t page_size = rte_mem_page_size ( ) ; if ( page_size == ( size_t ) -1 ) { DRV_LOG ( ERR , " " ) ; rte_errno = ENOMEM ; return - rte_errno ; } if ( txq_ctrl -> type != MLX5_TXQ_TYPE_STANDARD ) return 0 ; MLX5_ASSERT ( ppriv ) ; uar_va = ( uintptr_t ) txq_ctrl -> bf_reg ; offset = uar_va & ( page_size - 1 ) ; addr = rte_mem_map ( NULL , page_size , RTE_PROT_WRITE , RTE_MAP_SHARED , fd , txq_ctrl -> uar_mmap_offset ) ; if ( ! addr ) { DRV_LOG ( ERR , " " , txq -> port_id , txq -> idx ) ; rte_errno = ENXIO ; return - rte_errno ; } addr = RTE_PTR_ADD ( addr , offset ) ; ppriv -> uar_table [ txq -> idx ] = addr ; txq_uar_ncattr_init ( txq_ctrl , page_size ) ; return 0 ; }
Remap UAR register of a Tx queue for secondary process.
Remap UAR register of a Tx queue for secondary process .
/*
	 * As rdma-core, UARs are mapped in size of OS page
	 * size. Ref to libmlx5 function: mlx5_init_context()
	 */ /* Offset in page. */