XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss.c
static void StubAccessLaneSetCallback(void *InstancePtr)
{
	/* Verify argument.*/
	Xil_AssertVoid(InstancePtr != NULL);

	XDpRxSs *DpRxSsPtr = (XDpRxSs *)InstancePtr;
	u32 read_val;

	u8 training = XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
				      XDP_RX_DPCD_TRAINING_PATTERN_SET);

	if (DpRxSsPtr->ltState == 2 && training != 1) {

		read_val = XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
					   XDP_RX_DPCD_LANE01_STATUS);
		read_val &= 0x0000FF00;

		if (MCDP6000_IC_Rev==0x2100) {
			if (DpRxSsPtr->ceRequestValue != read_val) {
				XDpRxSs_MCDP6000_AccessLaneSet(DpRxSsPtr,
					       XDPRXSS_MCDP6000_IIC_SLAVE);
			}
		}

		/* Update the value to be used in next round */
		DpRxSsPtr->ceRequestValue =
			(XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
					 XDP_RX_DPCD_LANE01_STATUS) &
			 0x0000FF00);
	}
}
/*****************************************************************************/
/**
*
* This routine is a stub for the asynchronous access lane set
* interrupt callback. On initialization, access lane set interrupt handler
* is set to this callback.
*
* @param	InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This routine is a stub for the asynchronous access lane set
interrupt callback. On initialization, access lane set interrupt handler
is set to this callback.
This routine is a stub for the asynchronous access lane set interrupt callback . On initialization access lane set interrupt handler is set to this callback .
static void StubAccessLaneSetCallback(void *InstancePtr)
{
	Xil_AssertVoid(InstancePtr != NULL);
	XDpRxSs *DpRxSsPtr = (XDpRxSs *)InstancePtr;
	u32 read_val;
	u8 training = XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
				      XDP_RX_DPCD_TRAINING_PATTERN_SET);
	if (DpRxSsPtr->ltState == 2 && training != 1) {
		read_val = XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
					   XDP_RX_DPCD_LANE01_STATUS);
		read_val &= 0x0000FF00;
		if (MCDP6000_IC_Rev==0x2100) {
			if (DpRxSsPtr->ceRequestValue != read_val) {
				XDpRxSs_MCDP6000_AccessLaneSet(DpRxSsPtr,
					       XDPRXSS_MCDP6000_IIC_SLAVE);
			}
		}
		DpRxSsPtr->ceRequestValue =
			(XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
					 XDP_RX_DPCD_LANE01_STATUS) &
			 0x0000FF00);
	}
}
static void StubAccessLaneSetCallback ( void * InstancePtr ) { Xil_AssertVoid ( InstancePtr != NULL ) ; XDpRxSs * DpRxSsPtr = ( XDpRxSs * ) InstancePtr ; u32 read_val ; u8 training = XDpRxSs_ReadReg ( DpRxSsPtr -> DpPtr -> Config . BaseAddr , XDP_RX_DPCD_TRAINING_PATTERN_SET ) ; if ( DpRxSsPtr -> ltState == 2 && training != 1 ) { read_val = XDpRxSs_ReadReg ( DpRxSsPtr -> DpPtr -> Config . BaseAddr , XDP_RX_DPCD_LANE01_STATUS ) ; read_val &= 0x0000FF00 ; if ( MCDP6000_IC_Rev == 0x2100 ) { if ( DpRxSsPtr -> ceRequestValue != read_val ) { XDpRxSs_MCDP6000_AccessLaneSet ( DpRxSsPtr , XDPRXSS_MCDP6000_IIC_SLAVE ) ; } } DpRxSsPtr -> ceRequestValue = ( XDpRxSs_ReadReg ( DpRxSsPtr -> DpPtr -> Config . BaseAddr , XDP_RX_DPCD_LANE01_STATUS ) & 0x0000FF00 ) ; } }
This routine is a stub for the asynchronous access lane set
interrupt callback.
This routine is a stub for the asynchronous access lane set interrupt callback .
/* Verify argument.*/ /* Update the value to be used in next round */