XilinxProcessorIPLib/drivers/rfdc/src/xrfdc_clock.c
static u32 XRFdc_CheckClkDistValid(XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr)
{
	u32 Status;
	u32 Type;
	u32 Tile;
	u32 PkgTileId;
	u32 PkgADCEdgeTile;
	u8 IsPLL;
	u16 EFuse;
	u8 TileLayout;

	if (DistributionSettingsPtr->DistributedClock > XRFDC_DIST_OUT_OUTDIV) {
		metal_log(METAL_LOG_ERROR, "\n Invalid Parameter Value for Distribution Out (%u) for %s %u in %s\r\n",
			  DistributionSettingsPtr->DistributedClock,
			  (DistributionSettingsPtr->SourceType == XRFDC_ADC_TILE) ? "ADC" : "DAC",
			  DistributionSettingsPtr->SourceTileId, __func__);
		Status = XRFDC_FAILURE;
		goto RETURN_PATH;
	}

	if ((DistributionSettingsPtr->Info.Source < DistributionSettingsPtr->Info.LowerBound) ||
	    (DistributionSettingsPtr->Info.Source > DistributionSettingsPtr->Info.UpperBound)) {
		metal_log(METAL_LOG_ERROR, "\n %s %u does not reside between %s %u and %s %u in %s\r\n",
			  ((DistributionSettingsPtr->SourceType == XRFDC_ADC_TILE) ? "ADC" : "DAC"),
			  DistributionSettingsPtr->SourceTileId,
			  ((DistributionSettingsPtr->EdgeTypes[0] == XRFDC_ADC_TILE) ? "ADC" : "DAC"),
			  DistributionSettingsPtr->EdgeTileIds[0],
			  ((DistributionSettingsPtr->EdgeTypes[1] == XRFDC_ADC_TILE) ? "ADC" : "DAC"),
			  DistributionSettingsPtr->EdgeTileIds[1], __func__);
		Status = XRFDC_FAILURE;
		goto RETURN_PATH;
	}

	if (DistributionSettingsPtr->Info.UpperBound == DistributionSettingsPtr->Info.LowerBound) {
		if (DistributionSettingsPtr->DistributedClock != XRFDC_DIST_OUT_NONE) {
			metal_log(
				METAL_LOG_ERROR,
				"\n Invalid Parameter Value for Distribution Out (%u) for Single Tile Distribution in %s\r\n",
				DistributionSettingsPtr->DistributedClock, __func__);
			Status = XRFDC_FAILURE;
			goto RETURN_PATH;
		}
	} else {
		if (DistributionSettingsPtr->DistributedClock == XRFDC_DIST_OUT_NONE) {
			metal_log(
				METAL_LOG_ERROR,
				"\n Invalid Parameter Value for Distribution Out (%u) for Multi Tile Distribution in %s\r\n",
				DistributionSettingsPtr->DistributedClock, __func__);
			Status = XRFDC_FAILURE;
			goto RETURN_PATH;
		}
	}

	for (PkgTileId = DistributionSettingsPtr->Info.LowerBound;
	     PkgTileId <= DistributionSettingsPtr->Info.UpperBound; PkgTileId++) {
		XRFdc_DistTile2TypeTile(InstancePtr, PkgTileId, &Type, &Tile);
		Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile);
		if (Status != XRFDC_SUCCESS) {
			metal_log(METAL_LOG_ERROR, "\n %s %u not enabled in %s\r\n",
				  ((Type == XRFDC_ADC_TILE) ? "ADC" : "DAC"), Tile, __func__);
			goto RETURN_PATH;
		}
	}

	TileLayout = XRFdc_GetTileLayout(InstancePtr);
	if (TileLayout == XRFDC_4ADC_4DAC_TILES) {
		IsPLL = (DistributionSettingsPtr->SampleRates[DistributionSettingsPtr->SourceType]
							     [DistributionSettingsPtr->SourceTileId] >
			 DistributionSettingsPtr->DistRefClkFreq);
		if ((DistributionSettingsPtr->SourceTileId == XRFDC_TILE_ID0) ||
		    (DistributionSettingsPtr->SourceTileId == XRFDC_TILE_ID3)) {
			if ((DistributionSettingsPtr->DistributedClock == XRFDC_DIST_OUT_OUTDIV) ||
			    ((DistributionSettingsPtr->DistributedClock == XRFDC_DIST_OUT_RX) &&
			     (IsPLL == XRFDC_DISABLED))) {
				Status = XRFDC_FAILURE;
				metal_log(METAL_LOG_ERROR,
					  "\n Distribution of full rate clock from edge tiles not supported in %s\r\n",
					  __func__);
				goto RETURN_PATH;
			}
		}

		if ((DistributionSettingsPtr->SourceType == XRFDC_DAC_TILE) &&
		    (DistributionSettingsPtr->Info.UpperBound > XRFDC_CLK_DST_TILE_226)) {
			if ((DistributionSettingsPtr->DistributedClock == XRFDC_DIST_OUT_OUTDIV) ||
			    (IsPLL == XRFDC_DISABLED)) {
				EFuse = XRFdc_ReadReg16(
					InstancePtr, XRFDC_DRP_BASE(XRFDC_ADC_TILE, XRFDC_BLK_ID1) + XRFDC_HSCOM_ADDR,
					XRFDC_HSCOM_EFUSE_2_OFFSET);
				if (EFuse & XRFDC_PREMIUMCTRL_CLKDIST) {
					Status = XRFDC_FAILURE;
					metal_log(METAL_LOG_ERROR, "\n Invalid Configuration in %s\r\n", __func__);
					goto RETURN_PATH;
				}
			}
		}

		PkgADCEdgeTile = XRFDC_CLK_DST_TILE_227;
	} else {
		PkgADCEdgeTile = XRFDC_CLK_DST_TILE_226;
	}

	if ((DistributionSettingsPtr->SourceType == XRFDC_ADC_TILE) &&
	    (DistributionSettingsPtr->Info.LowerBound < PkgADCEdgeTile)) {
		metal_log(METAL_LOG_ERROR, "\n DAC Cannot Source from ADC in %s\r\n", __func__);
		Status = XRFDC_FAILURE;
		goto RETURN_PATH;
	}

	Status = XRFDC_SUCCESS;
RETURN_PATH:
	return Status;
}
/*****************************************************************************/
/**
*
* This function is used to check the distribution chosen is valid
*
* @param        InstancePtr is a pointer to the XRfdc instance.
* @param        DistributionSettingsPtr pointer to the distribution settings struct
*
* @return
*           - XRFDC_SUCCESS if valid.
*           - XRFDC_FAILURE if not valid.
*
******************************************************************************/
This function is used to check the distribution chosen is valid
This function is used to check the distribution chosen is valid
static u32 XRFdc_CheckClkDistValid(XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr)
{
	u32 Status;
	u32 Type;
	u32 Tile;
	u32 PkgTileId;
	u32 PkgADCEdgeTile;
	u8 IsPLL;
	u16 EFuse;
	u8 TileLayout;
	if (DistributionSettingsPtr->DistributedClock > XRFDC_DIST_OUT_OUTDIV) {
		metal_log(METAL_LOG_ERROR, "\n Invalid Parameter Value for Distribution Out (%u) for %s %u in %s\r\n",
			  DistributionSettingsPtr->DistributedClock,
			  (DistributionSettingsPtr->SourceType == XRFDC_ADC_TILE) ? "ADC" : "DAC",
			  DistributionSettingsPtr->SourceTileId, __func__);
		Status = XRFDC_FAILURE;
		goto RETURN_PATH;
	}
	if ((DistributionSettingsPtr->Info.Source < DistributionSettingsPtr->Info.LowerBound) ||
	    (DistributionSettingsPtr->Info.Source > DistributionSettingsPtr->Info.UpperBound)) {
		metal_log(METAL_LOG_ERROR, "\n %s %u does not reside between %s %u and %s %u in %s\r\n",
			  ((DistributionSettingsPtr->SourceType == XRFDC_ADC_TILE) ? "ADC" : "DAC"),
			  DistributionSettingsPtr->SourceTileId,
			  ((DistributionSettingsPtr->EdgeTypes[0] == XRFDC_ADC_TILE) ? "ADC" : "DAC"),
			  DistributionSettingsPtr->EdgeTileIds[0],
			  ((DistributionSettingsPtr->EdgeTypes[1] == XRFDC_ADC_TILE) ? "ADC" : "DAC"),
			  DistributionSettingsPtr->EdgeTileIds[1], __func__);
		Status = XRFDC_FAILURE;
		goto RETURN_PATH;
	}
	if (DistributionSettingsPtr->Info.UpperBound == DistributionSettingsPtr->Info.LowerBound) {
		if (DistributionSettingsPtr->DistributedClock != XRFDC_DIST_OUT_NONE) {
			metal_log(
				METAL_LOG_ERROR,
				"\n Invalid Parameter Value for Distribution Out (%u) for Single Tile Distribution in %s\r\n",
				DistributionSettingsPtr->DistributedClock, __func__);
			Status = XRFDC_FAILURE;
			goto RETURN_PATH;
		}
	} else {
		if (DistributionSettingsPtr->DistributedClock == XRFDC_DIST_OUT_NONE) {
			metal_log(
				METAL_LOG_ERROR,
				"\n Invalid Parameter Value for Distribution Out (%u) for Multi Tile Distribution in %s\r\n",
				DistributionSettingsPtr->DistributedClock, __func__);
			Status = XRFDC_FAILURE;
			goto RETURN_PATH;
		}
	}
	for (PkgTileId = DistributionSettingsPtr->Info.LowerBound;
	     PkgTileId <= DistributionSettingsPtr->Info.UpperBound; PkgTileId++) {
		XRFdc_DistTile2TypeTile(InstancePtr, PkgTileId, &Type, &Tile);
		Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile);
		if (Status != XRFDC_SUCCESS) {
			metal_log(METAL_LOG_ERROR, "\n %s %u not enabled in %s\r\n",
				  ((Type == XRFDC_ADC_TILE) ? "ADC" : "DAC"), Tile, __func__);
			goto RETURN_PATH;
		}
	}
	TileLayout = XRFdc_GetTileLayout(InstancePtr);
	if (TileLayout == XRFDC_4ADC_4DAC_TILES) {
		IsPLL = (DistributionSettingsPtr->SampleRates[DistributionSettingsPtr->SourceType]
							     [DistributionSettingsPtr->SourceTileId] >
			 DistributionSettingsPtr->DistRefClkFreq);
		if ((DistributionSettingsPtr->SourceTileId == XRFDC_TILE_ID0) ||
		    (DistributionSettingsPtr->SourceTileId == XRFDC_TILE_ID3)) {
			if ((DistributionSettingsPtr->DistributedClock == XRFDC_DIST_OUT_OUTDIV) ||
			    ((DistributionSettingsPtr->DistributedClock == XRFDC_DIST_OUT_RX) &&
			     (IsPLL == XRFDC_DISABLED))) {
				Status = XRFDC_FAILURE;
				metal_log(METAL_LOG_ERROR,
					  "\n Distribution of full rate clock from edge tiles not supported in %s\r\n",
					  __func__);
				goto RETURN_PATH;
			}
		}
		if ((DistributionSettingsPtr->SourceType == XRFDC_DAC_TILE) &&
		    (DistributionSettingsPtr->Info.UpperBound > XRFDC_CLK_DST_TILE_226)) {
			if ((DistributionSettingsPtr->DistributedClock == XRFDC_DIST_OUT_OUTDIV) ||
			    (IsPLL == XRFDC_DISABLED)) {
				EFuse = XRFdc_ReadReg16(
					InstancePtr, XRFDC_DRP_BASE(XRFDC_ADC_TILE, XRFDC_BLK_ID1) + XRFDC_HSCOM_ADDR,
					XRFDC_HSCOM_EFUSE_2_OFFSET);
				if (EFuse & XRFDC_PREMIUMCTRL_CLKDIST) {
					Status = XRFDC_FAILURE;
					metal_log(METAL_LOG_ERROR, "\n Invalid Configuration in %s\r\n", __func__);
					goto RETURN_PATH;
				}
			}
		}
		PkgADCEdgeTile = XRFDC_CLK_DST_TILE_227;
	} else {
		PkgADCEdgeTile = XRFDC_CLK_DST_TILE_226;
	}
	if ((DistributionSettingsPtr->SourceType == XRFDC_ADC_TILE) &&
	    (DistributionSettingsPtr->Info.LowerBound < PkgADCEdgeTile)) {
		metal_log(METAL_LOG_ERROR, "\n DAC Cannot Source from ADC in %s\r\n", __func__);
		Status = XRFDC_FAILURE;
		goto RETURN_PATH;
	}
	Status = XRFDC_SUCCESS;
RETURN_PATH:
	return Status;
}
static u32 XRFdc_CheckClkDistValid ( XRFdc * InstancePtr , XRFdc_Distribution_Settings * DistributionSettingsPtr ) { u32 Status ; u32 Type ; u32 Tile ; u32 PkgTileId ; u32 PkgADCEdgeTile ; u8 IsPLL ; u16 EFuse ; u8 TileLayout ; if ( DistributionSettingsPtr -> DistributedClock > XRFDC_DIST_OUT_OUTDIV ) { metal_log ( METAL_LOG_ERROR , " \n \r \n " , DistributionSettingsPtr -> DistributedClock , ( DistributionSettingsPtr -> SourceType == XRFDC_ADC_TILE ) ? " " : " " , DistributionSettingsPtr -> SourceTileId , __func__ ) ; Status = XRFDC_FAILURE ; goto RETURN_PATH ; } if ( ( DistributionSettingsPtr -> Info . Source < DistributionSettingsPtr -> Info . LowerBound ) || ( DistributionSettingsPtr -> Info . Source > DistributionSettingsPtr -> Info . UpperBound ) ) { metal_log ( METAL_LOG_ERROR , " \n \r \n " , ( ( DistributionSettingsPtr -> SourceType == XRFDC_ADC_TILE ) ? " " : " " ) , DistributionSettingsPtr -> SourceTileId , ( ( DistributionSettingsPtr -> EdgeTypes [ 0 ] == XRFDC_ADC_TILE ) ? " " : " " ) , DistributionSettingsPtr -> EdgeTileIds [ 0 ] , ( ( DistributionSettingsPtr -> EdgeTypes [ 1 ] == XRFDC_ADC_TILE ) ? " " : " " ) , DistributionSettingsPtr -> EdgeTileIds [ 1 ] , __func__ ) ; Status = XRFDC_FAILURE ; goto RETURN_PATH ; } if ( DistributionSettingsPtr -> Info . UpperBound == DistributionSettingsPtr -> Info . LowerBound ) { if ( DistributionSettingsPtr -> DistributedClock != XRFDC_DIST_OUT_NONE ) { metal_log ( METAL_LOG_ERROR , " \n \r \n " , DistributionSettingsPtr -> DistributedClock , __func__ ) ; Status = XRFDC_FAILURE ; goto RETURN_PATH ; } } else { if ( DistributionSettingsPtr -> DistributedClock == XRFDC_DIST_OUT_NONE ) { metal_log ( METAL_LOG_ERROR , " \n \r \n " , DistributionSettingsPtr -> DistributedClock , __func__ ) ; Status = XRFDC_FAILURE ; goto RETURN_PATH ; } } for ( PkgTileId = DistributionSettingsPtr -> Info . LowerBound ; PkgTileId <= DistributionSettingsPtr -> Info . UpperBound ; PkgTileId ++ ) { XRFdc_DistTile2TypeTile ( InstancePtr , PkgTileId , & Type , & Tile ) ; Status = XRFdc_CheckTileEnabled ( InstancePtr , Type , Tile ) ; if ( Status != XRFDC_SUCCESS ) { metal_log ( METAL_LOG_ERROR , " \n \r \n " , ( ( Type == XRFDC_ADC_TILE ) ? " " : " " ) , Tile , __func__ ) ; goto RETURN_PATH ; } } TileLayout = XRFdc_GetTileLayout ( InstancePtr ) ; if ( TileLayout == XRFDC_4ADC_4DAC_TILES ) { IsPLL = ( DistributionSettingsPtr -> SampleRates [ DistributionSettingsPtr -> SourceType ] [ DistributionSettingsPtr -> SourceTileId ] > DistributionSettingsPtr -> DistRefClkFreq ) ; if ( ( DistributionSettingsPtr -> SourceTileId == XRFDC_TILE_ID0 ) || ( DistributionSettingsPtr -> SourceTileId == XRFDC_TILE_ID3 ) ) { if ( ( DistributionSettingsPtr -> DistributedClock == XRFDC_DIST_OUT_OUTDIV ) || ( ( DistributionSettingsPtr -> DistributedClock == XRFDC_DIST_OUT_RX ) && ( IsPLL == XRFDC_DISABLED ) ) ) { Status = XRFDC_FAILURE ; metal_log ( METAL_LOG_ERROR , " \n \r \n " , __func__ ) ; goto RETURN_PATH ; } } if ( ( DistributionSettingsPtr -> SourceType == XRFDC_DAC_TILE ) && ( DistributionSettingsPtr -> Info . UpperBound > XRFDC_CLK_DST_TILE_226 ) ) { if ( ( DistributionSettingsPtr -> DistributedClock == XRFDC_DIST_OUT_OUTDIV ) || ( IsPLL == XRFDC_DISABLED ) ) { EFuse = XRFdc_ReadReg16 ( InstancePtr , XRFDC_DRP_BASE ( XRFDC_ADC_TILE , XRFDC_BLK_ID1 ) + XRFDC_HSCOM_ADDR , XRFDC_HSCOM_EFUSE_2_OFFSET ) ; if ( EFuse & XRFDC_PREMIUMCTRL_CLKDIST ) { Status = XRFDC_FAILURE ; metal_log ( METAL_LOG_ERROR , " \n \r \n " , __func__ ) ; goto RETURN_PATH ; } } } PkgADCEdgeTile = XRFDC_CLK_DST_TILE_227 ; } else { PkgADCEdgeTile = XRFDC_CLK_DST_TILE_226 ; } if ( ( DistributionSettingsPtr -> SourceType == XRFDC_ADC_TILE ) && ( DistributionSettingsPtr -> Info . LowerBound < PkgADCEdgeTile ) ) { metal_log ( METAL_LOG_ERROR , " \n \r \n " , __func__ ) ; Status = XRFDC_FAILURE ; goto RETURN_PATH ; } Status = XRFDC_SUCCESS ; RETURN_PATH : return Status ; }
This function is used to check the distribution chosen is valid
This function is used to check the distribution chosen is valid