XilinxProcessorIPLib/drivers/v_hdmirxss1/src/xv_hdmirxss1.c
int XV_HdmiRxSs1_CfgInitialize(XV_HdmiRxSs1 *InstancePtr,
    XV_HdmiRxSs1_Config *CfgPtr,
    UINTPTR EffectiveAddr)
{
  XV_HdmiRxSs1 *HdmiRxSs1Ptr = InstancePtr;
  XHdmiC_DRMInfoFrame *DrmInfoFramePtr;

  /* Verify arguments */
  Xil_AssertNonvoid(HdmiRxSs1Ptr != NULL);
  Xil_AssertNonvoid(CfgPtr != NULL);
  Xil_AssertNonvoid(EffectiveAddr != (UINTPTR)NULL);

  /* Setup the instance */
  memcpy((void *)&(HdmiRxSs1Ptr->Config), (const void *)CfgPtr,
    sizeof(XV_HdmiRxSs1_Config));
  HdmiRxSs1Ptr->Config.BaseAddress = EffectiveAddr;

  /* Determine sub-cores included in the provided instance of subsystem */
  XV_HdmiRxSs1_GetIncludedSubcores(HdmiRxSs1Ptr, CfgPtr->DeviceId);

  /* Initialize all included sub_cores */
  if (HdmiRxSs1Ptr->HdmiRx1Ptr)
  {
    if (XV_HdmiRxSs1_SubcoreInitHdmiRx1(HdmiRxSs1Ptr) != XST_SUCCESS)
    {
      return(XST_FAILURE);
    }
    XV_HdmiRx1_SetAxiClkFreq(HdmiRxSs1Ptr->HdmiRx1Ptr,
                            HdmiRxSs1Ptr->Config.AxiLiteClkFreq);
  }

#ifdef XPAR_XHDCP_NUM_INSTANCES
  /* HDCP 1.4*/
  if (HdmiRxSs1Ptr->Hdcp14Ptr)
  {
    if (XV_HdmiRxSs1_SubcoreInitHdcp14(HdmiRxSs1Ptr) != XST_SUCCESS)
    {
      return(XST_FAILURE);
    }
  }

  if (HdmiRxSs1Ptr->HdcpTimerPtr)
  {
    if (XV_HdmiRxSs1_SubcoreInitHdcpTimer(HdmiRxSs1Ptr) != XST_SUCCESS)
    {
      return(XST_FAILURE);
    }
  }
#endif

#ifdef XPAR_XHDCP22_RX_NUM_INSTANCES
  /* HDCP 2.2*/
  if (HdmiRxSs1Ptr->Hdcp22Ptr)
  {
    if (XV_HdmiRxSs1_SubcoreInitHdcp22(HdmiRxSs1Ptr) != XST_SUCCESS)
    {
      return(XST_FAILURE);
    }
  }
#endif

  /* Register Callbacks */
  XV_HdmiRxSs1_RegisterSubsysCallbacks(HdmiRxSs1Ptr);

#ifdef USE_HDCP_RX
  /* Default value */
  HdmiRxSs1Ptr->HdcpIsReady = (FALSE);
  XV_HdmiRxSs1_HdcpSetCapability(HdmiRxSs1Ptr, XV_HDMIRXSS1_HDCP_BOTH);
#endif

#if defined(XPAR_XHDCP_NUM_INSTANCES) && defined(XPAR_XHDCP22_RX_NUM_INSTANCES)
  /* HDCP is ready when both HDCP cores are instantiated and all keys are
     loaded */
  if (HdmiRxSs1Ptr->Hdcp14Ptr && HdmiRxSs1Ptr->Hdcp22Ptr &&
      HdmiRxSs1Ptr->Hdcp22Lc128Ptr && HdmiRxSs1Ptr->Hdcp14KeyPtr &&
      HdmiRxSs1Ptr->Hdcp22PrivateKeyPtr) {
    HdmiRxSs1Ptr->HdcpIsReady = (TRUE);

    /* Set default HDCP content protection scheme */
    XV_HdmiRxSs1_HdcpSetProtocol(HdmiRxSs1Ptr, XV_HDMIRXSS1_HDCP_14);
  }
#endif

#if defined(XPAR_XHDCP_NUM_INSTANCES)
  /* HDCP is ready when only the HDCP 1.4 core is instantiated and the key is
     loaded */
  if (!HdmiRxSs1Ptr->HdcpIsReady && HdmiRxSs1Ptr->Hdcp14Ptr &&
       HdmiRxSs1Ptr->Hdcp14KeyPtr) {
    HdmiRxSs1Ptr->HdcpIsReady = (TRUE);

    /* Set default HDCP content protection scheme */
    XV_HdmiRxSs1_HdcpSetProtocol(HdmiRxSs1Ptr, XV_HDMIRXSS1_HDCP_14);
  }
#endif

#if defined(XPAR_XHDCP22_RX_NUM_INSTANCES)
  /* HDCP is ready when only the HDCP 2.2 core is instantiated and the keys are
     loaded */
  if (!HdmiRxSs1Ptr->HdcpIsReady && HdmiRxSs1Ptr->Hdcp22Ptr &&
       HdmiRxSs1Ptr->Hdcp22Lc128Ptr && HdmiRxSs1Ptr->Hdcp22PrivateKeyPtr) {
    HdmiRxSs1Ptr->HdcpIsReady = (TRUE);

    /* Set default HDCP content protection scheme */
    XV_HdmiRxSs1_HdcpSetProtocol(HdmiRxSs1Ptr, XV_HDMIRXSS1_HDCP_22);
  }
#endif

  /* Reset the hardware and set the flag to indicate the
     subsystem is ready
   */
  XV_HdmiRxSs1_Reset(HdmiRxSs1Ptr);
  HdmiRxSs1Ptr->IsReady = XIL_COMPONENT_IS_READY;

  /* Initialize the application version with 0 <default value>.
   * Application need to set the this variable properly to let driver know
   * what version of application is being used.
   */
  HdmiRxSs1Ptr->AppMajVer = 0;
  HdmiRxSs1Ptr->AppMinVer = 0;

  /* Disable the Logging */
  HdmiRxSs1Ptr->EnableHDCPLogging = (FALSE);
  HdmiRxSs1Ptr->EnableHDMILogging = (FALSE);

  /* Initialise the static HDR struct */
  DrmInfoFramePtr = XV_HdmiRxSs1_GetDrmInfoframe(HdmiRxSs1Ptr);
  DrmInfoFramePtr->Static_Metadata_Descriptor_ID = 0xFF;
  DrmInfoFramePtr->EOTF = 0xFF;

  return(XST_SUCCESS);
}
/*****************************************************************************/
/**
* This function initializes the video subsystem and included sub-cores.
* This function must be called prior to using the subsystem. Initialization
* includes setting up the instance data for top level as well as all included
* sub-core therein, and ensuring the hardware is in a known stable state.
*
* @param  InstancePtr is a pointer to the Subsystem instance to be worked on.
* @param  CfgPtr points to the configuration structure associated with the
*         subsystem instance.
* @param  EffectiveAddr is the base address of the device. If address
*         translation is being used, then this parameter must reflect the
*         virtual base address. Otherwise, the physical address should be
*         used.
*
* @return XST_SUCCESS if initialization is successful else XST_FAILURE
*
******************************************************************************/
This function initializes the video subsystem and included sub-cores.
This function must be called prior to using the subsystem. Initialization
includes setting up the instance data for top level as well as all included
sub-core therein, and ensuring the hardware is in a known stable state.
This function initializes the video subsystem and included sub - cores . This function must be called prior to using the subsystem . Initialization includes setting up the instance data for top level as well as all included sub - core therein and ensuring the hardware is in a known stable state .
int XV_HdmiRxSs1_CfgInitialize(XV_HdmiRxSs1 *InstancePtr,
    XV_HdmiRxSs1_Config *CfgPtr,
    UINTPTR EffectiveAddr)
{
  XV_HdmiRxSs1 *HdmiRxSs1Ptr = InstancePtr;
  XHdmiC_DRMInfoFrame *DrmInfoFramePtr;
  Xil_AssertNonvoid(HdmiRxSs1Ptr != NULL);
  Xil_AssertNonvoid(CfgPtr != NULL);
  Xil_AssertNonvoid(EffectiveAddr != (UINTPTR)NULL);
  memcpy((void *)&(HdmiRxSs1Ptr->Config), (const void *)CfgPtr,
    sizeof(XV_HdmiRxSs1_Config));
  HdmiRxSs1Ptr->Config.BaseAddress = EffectiveAddr;
  XV_HdmiRxSs1_GetIncludedSubcores(HdmiRxSs1Ptr, CfgPtr->DeviceId);
  if (HdmiRxSs1Ptr->HdmiRx1Ptr)
  {
    if (XV_HdmiRxSs1_SubcoreInitHdmiRx1(HdmiRxSs1Ptr) != XST_SUCCESS)
    {
      return(XST_FAILURE);
    }
    XV_HdmiRx1_SetAxiClkFreq(HdmiRxSs1Ptr->HdmiRx1Ptr,
                            HdmiRxSs1Ptr->Config.AxiLiteClkFreq);
  }
#ifdef XPAR_XHDCP_NUM_INSTANCES
  if (HdmiRxSs1Ptr->Hdcp14Ptr)
  {
    if (XV_HdmiRxSs1_SubcoreInitHdcp14(HdmiRxSs1Ptr) != XST_SUCCESS)
    {
      return(XST_FAILURE);
    }
  }
  if (HdmiRxSs1Ptr->HdcpTimerPtr)
  {
    if (XV_HdmiRxSs1_SubcoreInitHdcpTimer(HdmiRxSs1Ptr) != XST_SUCCESS)
    {
      return(XST_FAILURE);
    }
  }
#endif
#ifdef XPAR_XHDCP22_RX_NUM_INSTANCES
  if (HdmiRxSs1Ptr->Hdcp22Ptr)
  {
    if (XV_HdmiRxSs1_SubcoreInitHdcp22(HdmiRxSs1Ptr) != XST_SUCCESS)
    {
      return(XST_FAILURE);
    }
  }
#endif
  XV_HdmiRxSs1_RegisterSubsysCallbacks(HdmiRxSs1Ptr);
#ifdef USE_HDCP_RX
  HdmiRxSs1Ptr->HdcpIsReady = (FALSE);
  XV_HdmiRxSs1_HdcpSetCapability(HdmiRxSs1Ptr, XV_HDMIRXSS1_HDCP_BOTH);
#endif
#if defined(XPAR_XHDCP_NUM_INSTANCES) && defined(XPAR_XHDCP22_RX_NUM_INSTANCES)
  if (HdmiRxSs1Ptr->Hdcp14Ptr && HdmiRxSs1Ptr->Hdcp22Ptr &&
      HdmiRxSs1Ptr->Hdcp22Lc128Ptr && HdmiRxSs1Ptr->Hdcp14KeyPtr &&
      HdmiRxSs1Ptr->Hdcp22PrivateKeyPtr) {
    HdmiRxSs1Ptr->HdcpIsReady = (TRUE);
    XV_HdmiRxSs1_HdcpSetProtocol(HdmiRxSs1Ptr, XV_HDMIRXSS1_HDCP_14);
  }
#endif
#if defined(XPAR_XHDCP_NUM_INSTANCES)
  if (!HdmiRxSs1Ptr->HdcpIsReady && HdmiRxSs1Ptr->Hdcp14Ptr &&
       HdmiRxSs1Ptr->Hdcp14KeyPtr) {
    HdmiRxSs1Ptr->HdcpIsReady = (TRUE);
    XV_HdmiRxSs1_HdcpSetProtocol(HdmiRxSs1Ptr, XV_HDMIRXSS1_HDCP_14);
  }
#endif
#if defined(XPAR_XHDCP22_RX_NUM_INSTANCES)
  if (!HdmiRxSs1Ptr->HdcpIsReady && HdmiRxSs1Ptr->Hdcp22Ptr &&
       HdmiRxSs1Ptr->Hdcp22Lc128Ptr && HdmiRxSs1Ptr->Hdcp22PrivateKeyPtr) {
    HdmiRxSs1Ptr->HdcpIsReady = (TRUE);
    XV_HdmiRxSs1_HdcpSetProtocol(HdmiRxSs1Ptr, XV_HDMIRXSS1_HDCP_22);
  }
#endif
  XV_HdmiRxSs1_Reset(HdmiRxSs1Ptr);
  HdmiRxSs1Ptr->IsReady = XIL_COMPONENT_IS_READY;
  HdmiRxSs1Ptr->AppMajVer = 0;
  HdmiRxSs1Ptr->AppMinVer = 0;
  HdmiRxSs1Ptr->EnableHDCPLogging = (FALSE);
  HdmiRxSs1Ptr->EnableHDMILogging = (FALSE);
  DrmInfoFramePtr = XV_HdmiRxSs1_GetDrmInfoframe(HdmiRxSs1Ptr);
  DrmInfoFramePtr->Static_Metadata_Descriptor_ID = 0xFF;
  DrmInfoFramePtr->EOTF = 0xFF;
  return(XST_SUCCESS);
}
int XV_HdmiRxSs1_CfgInitialize ( XV_HdmiRxSs1 * InstancePtr , XV_HdmiRxSs1_Config * CfgPtr , UINTPTR EffectiveAddr ) { XV_HdmiRxSs1 * HdmiRxSs1Ptr = InstancePtr ; XHdmiC_DRMInfoFrame * DrmInfoFramePtr ; Xil_AssertNonvoid ( HdmiRxSs1Ptr != NULL ) ; Xil_AssertNonvoid ( CfgPtr != NULL ) ; Xil_AssertNonvoid ( EffectiveAddr != ( UINTPTR ) NULL ) ; memcpy ( ( void * ) & ( HdmiRxSs1Ptr -> Config ) , ( const void * ) CfgPtr , sizeof ( XV_HdmiRxSs1_Config ) ) ; HdmiRxSs1Ptr -> Config . BaseAddress = EffectiveAddr ; XV_HdmiRxSs1_GetIncludedSubcores ( HdmiRxSs1Ptr , CfgPtr -> DeviceId ) ; if ( HdmiRxSs1Ptr -> HdmiRx1Ptr ) { if ( XV_HdmiRxSs1_SubcoreInitHdmiRx1 ( HdmiRxSs1Ptr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } XV_HdmiRx1_SetAxiClkFreq ( HdmiRxSs1Ptr -> HdmiRx1Ptr , HdmiRxSs1Ptr -> Config . AxiLiteClkFreq ) ; } #ifdef XPAR_XHDCP_NUM_INSTANCES if ( HdmiRxSs1Ptr -> Hdcp14Ptr ) { if ( XV_HdmiRxSs1_SubcoreInitHdcp14 ( HdmiRxSs1Ptr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } if ( HdmiRxSs1Ptr -> HdcpTimerPtr ) { if ( XV_HdmiRxSs1_SubcoreInitHdcpTimer ( HdmiRxSs1Ptr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } #endif #ifdef XPAR_XHDCP22_RX_NUM_INSTANCES if ( HdmiRxSs1Ptr -> Hdcp22Ptr ) { if ( XV_HdmiRxSs1_SubcoreInitHdcp22 ( HdmiRxSs1Ptr ) != XST_SUCCESS ) { return ( XST_FAILURE ) ; } } #endif XV_HdmiRxSs1_RegisterSubsysCallbacks ( HdmiRxSs1Ptr ) ; #ifdef USE_HDCP_RX HdmiRxSs1Ptr -> HdcpIsReady = ( FALSE ) ; XV_HdmiRxSs1_HdcpSetCapability ( HdmiRxSs1Ptr , XV_HDMIRXSS1_HDCP_BOTH ) ; #endif #if defined ( XPAR_XHDCP_NUM_INSTANCES ) && defined ( XPAR_XHDCP22_RX_NUM_INSTANCES ) if ( HdmiRxSs1Ptr -> Hdcp14Ptr && HdmiRxSs1Ptr -> Hdcp22Ptr && HdmiRxSs1Ptr -> Hdcp22Lc128Ptr && HdmiRxSs1Ptr -> Hdcp14KeyPtr && HdmiRxSs1Ptr -> Hdcp22PrivateKeyPtr ) { HdmiRxSs1Ptr -> HdcpIsReady = ( TRUE ) ; XV_HdmiRxSs1_HdcpSetProtocol ( HdmiRxSs1Ptr , XV_HDMIRXSS1_HDCP_14 ) ; } #endif #if defined ( XPAR_XHDCP_NUM_INSTANCES ) if ( ! HdmiRxSs1Ptr -> HdcpIsReady && HdmiRxSs1Ptr -> Hdcp14Ptr && HdmiRxSs1Ptr -> Hdcp14KeyPtr ) { HdmiRxSs1Ptr -> HdcpIsReady = ( TRUE ) ; XV_HdmiRxSs1_HdcpSetProtocol ( HdmiRxSs1Ptr , XV_HDMIRXSS1_HDCP_14 ) ; } #endif #if defined ( XPAR_XHDCP22_RX_NUM_INSTANCES ) if ( ! HdmiRxSs1Ptr -> HdcpIsReady && HdmiRxSs1Ptr -> Hdcp22Ptr && HdmiRxSs1Ptr -> Hdcp22Lc128Ptr && HdmiRxSs1Ptr -> Hdcp22PrivateKeyPtr ) { HdmiRxSs1Ptr -> HdcpIsReady = ( TRUE ) ; XV_HdmiRxSs1_HdcpSetProtocol ( HdmiRxSs1Ptr , XV_HDMIRXSS1_HDCP_22 ) ; } #endif XV_HdmiRxSs1_Reset ( HdmiRxSs1Ptr ) ; HdmiRxSs1Ptr -> IsReady = XIL_COMPONENT_IS_READY ; HdmiRxSs1Ptr -> AppMajVer = 0 ; HdmiRxSs1Ptr -> AppMinVer = 0 ; HdmiRxSs1Ptr -> EnableHDCPLogging = ( FALSE ) ; HdmiRxSs1Ptr -> EnableHDMILogging = ( FALSE ) ; DrmInfoFramePtr = XV_HdmiRxSs1_GetDrmInfoframe ( HdmiRxSs1Ptr ) ; DrmInfoFramePtr -> Static_Metadata_Descriptor_ID = 0xFF ; DrmInfoFramePtr -> EOTF = 0xFF ; return ( XST_SUCCESS ) ; }
This function initializes the video subsystem and included sub-cores.
This function initializes the video subsystem and included sub - cores .
/* Verify arguments */ /* Setup the instance */ /* Determine sub-cores included in the provided instance of subsystem */ /* Initialize all included sub_cores */ /* HDCP 1.4*/ /* HDCP 2.2*/ /* Register Callbacks */ /* Default value */ /* HDCP is ready when both HDCP cores are instantiated and all keys are
     loaded */ /* Set default HDCP content protection scheme */ /* HDCP is ready when only the HDCP 1.4 core is instantiated and the key is
     loaded */ /* Set default HDCP content protection scheme */ /* HDCP is ready when only the HDCP 2.2 core is instantiated and the keys are
     loaded */ /* Set default HDCP content protection scheme */ /* Reset the hardware and set the flag to indicate the
     subsystem is ready
   */ /* Initialize the application version with 0 <default value>.
   * Application need to set the this variable properly to let driver know
   * what version of application is being used.
   */ /* Disable the Logging */ /* Initialise the static HDR struct */