src/dpdk/drivers/net/e1000/base/e1000_ich8lan.c
u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
{
	s32 ret_val;

	DEBUGFUNC("e1000_resume_workarounds_pchlan");
	if (hw->mac.type < e1000_pch2lan)
		return E1000_SUCCESS;

	ret_val = e1000_init_phy_workarounds_pchlan(hw);
	if (ret_val) {
		DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
		return ret_val;
	}

	/* For i217 Intel Rapid Start Technology support when the system
	 * is transitioning from Sx and no manageability engine is present
	 * configure SMBus to restore on reset, disable proxy, and enable
	 * the reset on MTA (Multicast table array).
	 */
	if (hw->phy.type == e1000_phy_i217) {
		u16 phy_reg;

		ret_val = hw->phy.ops.acquire(hw);
		if (ret_val) {
			DEBUGOUT("Failed to setup iRST\n");
			return ret_val;
		}

		/* Clear Auto Enable LPI after link up */
		hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
		phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
		hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);

		if (!(E1000_READ_REG(hw, E1000_FWSM) &
		    E1000_ICH_FWSM_FW_VALID)) {
			/* Restore clear on SMB if no manageability engine
			 * is present
			 */
			ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
							      &phy_reg);
			if (ret_val)
				goto release;
			phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
			hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);

			/* Disable Proxy */
			hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
		}
		/* Enable reset on MTA */
		ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
						      &phy_reg);
		if (ret_val)
			goto release;
		phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
		hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
release:
		if (ret_val)
			DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
		hw->phy.ops.release(hw);
		return ret_val;
	}
	return E1000_SUCCESS;
}
/**
 *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
 *  @hw: pointer to the HW structure
 *
 *  During Sx to S0 transitions on non-managed devices or managed devices
 *  on which PHY resets are not blocked, if the PHY registers cannot be
 *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
 *  the PHY.
 *  On i217, setup Intel Rapid Start Technology.
 **/
workarounds needed during Sx->S0
@hw: pointer to the HW structure

During Sx to S0 transitions on non-managed devices or managed devices
on which PHY resets are not blocked, if the PHY registers cannot be
accessed properly by the s/w toggle the LANPHYPC value to power cycle
the PHY.
On i217, setup Intel Rapid Start Technology.
workarounds needed during Sx - > S0 @hw : pointer to the HW structure During Sx to S0 transitions on non - managed devices or managed devices on which PHY resets are not blocked if the PHY registers cannot be accessed properly by the s / w toggle the LANPHYPC value to power cycle the PHY . On i217 setup Intel Rapid Start Technology .
u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
{
	s32 ret_val;
	DEBUGFUNC("e1000_resume_workarounds_pchlan");
	if (hw->mac.type < e1000_pch2lan)
		return E1000_SUCCESS;
	ret_val = e1000_init_phy_workarounds_pchlan(hw);
	if (ret_val) {
		DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
		return ret_val;
	}
	if (hw->phy.type == e1000_phy_i217) {
		u16 phy_reg;
		ret_val = hw->phy.ops.acquire(hw);
		if (ret_val) {
			DEBUGOUT("Failed to setup iRST\n");
			return ret_val;
		}
		hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
		phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
		hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
		if (!(E1000_READ_REG(hw, E1000_FWSM) &
		    E1000_ICH_FWSM_FW_VALID)) {
			ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
							      &phy_reg);
			if (ret_val)
				goto release;
			phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
			hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
			hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
		}
		ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
						      &phy_reg);
		if (ret_val)
			goto release;
		phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
		hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
release:
		if (ret_val)
			DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
		hw->phy.ops.release(hw);
		return ret_val;
	}
	return E1000_SUCCESS;
}
u32 e1000_resume_workarounds_pchlan ( struct e1000_hw * hw ) { s32 ret_val ; DEBUGFUNC ( " " ) ; if ( hw -> mac . type < e1000_pch2lan ) return E1000_SUCCESS ; ret_val = e1000_init_phy_workarounds_pchlan ( hw ) ; if ( ret_val ) { DEBUGOUT1 ( " \n " , ret_val ) ; return ret_val ; } if ( hw -> phy . type == e1000_phy_i217 ) { u16 phy_reg ; ret_val = hw -> phy . ops . acquire ( hw ) ; if ( ret_val ) { DEBUGOUT ( " \n " ) ; return ret_val ; } hw -> phy . ops . read_reg_locked ( hw , I217_LPI_GPIO_CTRL , & phy_reg ) ; phy_reg &= ~ I217_LPI_GPIO_CTRL_AUTO_EN_LPI ; hw -> phy . ops . write_reg_locked ( hw , I217_LPI_GPIO_CTRL , phy_reg ) ; if ( ! ( E1000_READ_REG ( hw , E1000_FWSM ) & E1000_ICH_FWSM_FW_VALID ) ) { ret_val = hw -> phy . ops . read_reg_locked ( hw , I217_MEMPWR , & phy_reg ) ; if ( ret_val ) goto release ; phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE ; hw -> phy . ops . write_reg_locked ( hw , I217_MEMPWR , phy_reg ) ; hw -> phy . ops . write_reg_locked ( hw , I217_PROXY_CTRL , 0 ) ; } ret_val = hw -> phy . ops . read_reg_locked ( hw , I217_CGFREG , & phy_reg ) ; if ( ret_val ) goto release ; phy_reg &= ~ I217_CGFREG_ENABLE_MTA_RESET ; hw -> phy . ops . write_reg_locked ( hw , I217_CGFREG , phy_reg ) ; release : if ( ret_val ) DEBUGOUT1 ( " \n " , ret_val ) ; hw -> phy . ops . release ( hw ) ; return ret_val ; } return E1000_SUCCESS ; }
e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
  @hw: pointer to the HW structure
e1000_resume_workarounds_pchlan - workarounds needed during Sx - > S0 @hw : pointer to the HW structure
/* For i217 Intel Rapid Start Technology support when the system
	 * is transitioning from Sx and no manageability engine is present
	 * configure SMBus to restore on reset, disable proxy, and enable
	 * the reset on MTA (Multicast table array).
	 */ /* Clear Auto Enable LPI after link up */ /* Restore clear on SMB if no manageability engine
			 * is present
			 */ /* Disable Proxy */ /* Enable reset on MTA */