XilinxProcessorIPLib/drivers/vphy/src/xvphy.c
XVphy_PllType XVphy_GetPllType(XVphy *InstancePtr, u8 QuadId,
		XVphy_DirectionType Dir, XVphy_ChannelId ChId)
{
	XVphy_SysClkDataSelType SysClkDataSel;
	XVphy_SysClkOutSelType SysClkOutSel;
	XVphy_PllType PllType;

	SysClkDataSel = XVphy_GetSysClkDataSel(InstancePtr, QuadId, Dir, ChId);
	SysClkOutSel = XVphy_GetSysClkOutSel(InstancePtr, QuadId, Dir, ChId);

	/* The sysclk data and output reference clocks should match. */

	if ((SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_CPLL_OUTCLK) &&
	(SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_CPLL_REFCLK)) {
		PllType = XVPHY_PLL_TYPE_CPLL;
	}
	else if ((SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_QPLL_OUTCLK) &&
	(SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_QPLL_REFCLK)) {
		PllType = XVPHY_PLL_TYPE_QPLL;
	}
	else if ((SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_QPLL0_OUTCLK) &&
	(SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_QPLL0_REFCLK)) {
		PllType = XVPHY_PLL_TYPE_QPLL0;
	}
	else if ((SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_QPLL1_OUTCLK) &&
	(SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_QPLL1_REFCLK)) {
		PllType = XVPHY_PLL_TYPE_QPLL1;
	}
	else {
		PllType = XVPHY_PLL_TYPE_UNKNOWN;
	}
	/* For GTHE2, GTHE3, GTHE4, GTYE4, and GTXE2. */
	if (InstancePtr->Config.XcvrType != XVPHY_GT_TYPE_GTPE2) {
		return PllType;
	}

	if ((SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_PLL0_OUTCLK) &&
	(SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_PLL0_REFCLK)) {
		PllType = XVPHY_PLL_TYPE_PLL0;
	}
	else if ((SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_PLL1_OUTCLK) &&
	(SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_PLL1_REFCLK)) {
		PllType = XVPHY_PLL_TYPE_PLL1;
	}
	else {
		PllType = XVPHY_PLL_TYPE_UNKNOWN;
	}
	/* For GTPE2. */
	return PllType;
}
/*****************************************************************************/
/**
* Obtain the channel's PLL reference clock selection.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	Dir is an indicator for TX or RX.
* @param	ChId is the channel ID which to operate on.
*
* @return	The PLL type being used by the channel.
*
* @note		None.
*
******************************************************************************/
Obtain the channel's PLL reference clock selection.
Obtain the channel ' s PLL reference clock selection .
XVphy_PllType XVphy_GetPllType(XVphy *InstancePtr, u8 QuadId,
		XVphy_DirectionType Dir, XVphy_ChannelId ChId)
{
	XVphy_SysClkDataSelType SysClkDataSel;
	XVphy_SysClkOutSelType SysClkOutSel;
	XVphy_PllType PllType;
	SysClkDataSel = XVphy_GetSysClkDataSel(InstancePtr, QuadId, Dir, ChId);
	SysClkOutSel = XVphy_GetSysClkOutSel(InstancePtr, QuadId, Dir, ChId);
	if ((SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_CPLL_OUTCLK) &&
	(SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_CPLL_REFCLK)) {
		PllType = XVPHY_PLL_TYPE_CPLL;
	}
	else if ((SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_QPLL_OUTCLK) &&
	(SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_QPLL_REFCLK)) {
		PllType = XVPHY_PLL_TYPE_QPLL;
	}
	else if ((SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_QPLL0_OUTCLK) &&
	(SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_QPLL0_REFCLK)) {
		PllType = XVPHY_PLL_TYPE_QPLL0;
	}
	else if ((SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_QPLL1_OUTCLK) &&
	(SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_QPLL1_REFCLK)) {
		PllType = XVPHY_PLL_TYPE_QPLL1;
	}
	else {
		PllType = XVPHY_PLL_TYPE_UNKNOWN;
	}
	if (InstancePtr->Config.XcvrType != XVPHY_GT_TYPE_GTPE2) {
		return PllType;
	}
	if ((SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_PLL0_OUTCLK) &&
	(SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_PLL0_REFCLK)) {
		PllType = XVPHY_PLL_TYPE_PLL0;
	}
	else if ((SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_PLL1_OUTCLK) &&
	(SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_PLL1_REFCLK)) {
		PllType = XVPHY_PLL_TYPE_PLL1;
	}
	else {
		PllType = XVPHY_PLL_TYPE_UNKNOWN;
	}
	return PllType;
}
XVphy_PllType XVphy_GetPllType ( XVphy * InstancePtr , u8 QuadId , XVphy_DirectionType Dir , XVphy_ChannelId ChId ) { XVphy_SysClkDataSelType SysClkDataSel ; XVphy_SysClkOutSelType SysClkOutSel ; XVphy_PllType PllType ; SysClkDataSel = XVphy_GetSysClkDataSel ( InstancePtr , QuadId , Dir , ChId ) ; SysClkOutSel = XVphy_GetSysClkOutSel ( InstancePtr , QuadId , Dir , ChId ) ; if ( ( SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_CPLL_OUTCLK ) && ( SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_CPLL_REFCLK ) ) { PllType = XVPHY_PLL_TYPE_CPLL ; } else if ( ( SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_QPLL_OUTCLK ) && ( SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_QPLL_REFCLK ) ) { PllType = XVPHY_PLL_TYPE_QPLL ; } else if ( ( SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_QPLL0_OUTCLK ) && ( SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_QPLL0_REFCLK ) ) { PllType = XVPHY_PLL_TYPE_QPLL0 ; } else if ( ( SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_QPLL1_OUTCLK ) && ( SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_QPLL1_REFCLK ) ) { PllType = XVPHY_PLL_TYPE_QPLL1 ; } else { PllType = XVPHY_PLL_TYPE_UNKNOWN ; } if ( InstancePtr -> Config . XcvrType != XVPHY_GT_TYPE_GTPE2 ) { return PllType ; } if ( ( SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_PLL0_OUTCLK ) && ( SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_PLL0_REFCLK ) ) { PllType = XVPHY_PLL_TYPE_PLL0 ; } else if ( ( SysClkDataSel == XVPHY_SYSCLKSELDATA_TYPE_PLL1_OUTCLK ) && ( SysClkOutSel == XVPHY_SYSCLKSELOUT_TYPE_PLL1_REFCLK ) ) { PllType = XVPHY_PLL_TYPE_PLL1 ; } else { PllType = XVPHY_PLL_TYPE_UNKNOWN ; } return PllType ; }
Obtain the channel's PLL reference clock selection.
Obtain the channel ' s PLL reference clock selection .
/* The sysclk data and output reference clocks should match. */ /* For GTHE2, GTHE3, GTHE4, GTYE4, and GTXE2. */ /* For GTPE2. */