AzureMXChip/MXCHIPAZ3166/core/lib/threadx/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c
void enableSecureFIQs(void)
{
  unsigned int tmp;

  tmp = gic_cpu->GICC_CTLR;
  tmp = tmp | 0x8;           // Set bit 3
  gic_cpu->GICC_CTLR = tmp;
}
// Enables the sending of secure interrupts as FIQs
Enables the sending of secure interrupts as FIQs
Enables the sending of secure interrupts as FIQs
void enableSecureFIQs(void)
{
  unsigned int tmp;
  tmp = gic_cpu->GICC_CTLR;
  tmp = tmp | 0x8;           
  gic_cpu->GICC_CTLR = tmp;
}
void enableSecureFIQs ( void ) { unsigned int tmp ; tmp = gic_cpu -> GICC_CTLR ; tmp = tmp | 0x8 ; gic_cpu -> GICC_CTLR = tmp ; }
Enables the sending of secure interrupts as FIQs
Enables the sending of secure interrupts as FIQs
// Set bit 3