target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl931x.c
int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
{
	int err = 0;
	u32 v;
	int type = (regnum & MII_ADDR_C45)?2:1;
	u64 pm;

	mutex_lock(&smi_lock);

	// Set PHY to access via port-mask
	pm = (u64)1 << port;
	sw_w32((u32)pm, RTL931X_SMI_INDRT_ACCESS_CTRL_2);
	sw_w32((u32)(pm >> 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4);

	// Set data to write
	sw_w32_mask(0xffff, val, RTL931X_SMI_INDRT_ACCESS_CTRL_3);

	// Set MMD device number and register to write to
	sw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);

	v = BIT(4) | type << 2 | BIT(0); // WRITE | MMD-access-type | EXEC
	sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);

	do {
		v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
	} while (v & BIT(0));

	pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__,
		 port, devnum, mdiobus_c45_regad(regnum), val, err);
	mutex_unlock(&smi_lock);
	return err;
}
/*
 * Write to an mmd register of the PHY
 */
Write to an mmd register of the PHY
Write to an mmd register of the PHY
int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
{
	int err = 0;
	u32 v;
	int type = (regnum & MII_ADDR_C45)?2:1;
	u64 pm;
	mutex_lock(&smi_lock);
	pm = (u64)1 << port;
	sw_w32((u32)pm, RTL931X_SMI_INDRT_ACCESS_CTRL_2);
	sw_w32((u32)(pm >> 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4);
	sw_w32_mask(0xffff, val, RTL931X_SMI_INDRT_ACCESS_CTRL_3);
	sw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);
	v = BIT(4) | type << 2 | BIT(0); 
	sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
	do {
		v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
	} while (v & BIT(0));
	pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__,
		 port, devnum, mdiobus_c45_regad(regnum), val, err);
	mutex_unlock(&smi_lock);
	return err;
}
int rtl931x_write_mmd_phy ( u32 port , u32 devnum , u32 regnum , u32 val ) { int err = 0 ; u32 v ; int type = ( regnum & MII_ADDR_C45 ) ? 2 : 1 ; u64 pm ; mutex_lock ( & smi_lock ) ; pm = ( u64 ) 1 << port ; sw_w32 ( ( u32 ) pm , RTL931X_SMI_INDRT_ACCESS_CTRL_2 ) ; sw_w32 ( ( u32 ) ( pm >> 32 ) , RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4 ) ; sw_w32_mask ( 0xffff , val , RTL931X_SMI_INDRT_ACCESS_CTRL_3 ) ; sw_w32 ( devnum << 16 | mdiobus_c45_regad ( regnum ) , RTL931X_SMI_INDRT_ACCESS_MMD_CTRL ) ; v = BIT ( 4 ) | type << 2 | BIT ( 0 ) ; sw_w32 ( v , RTL931X_SMI_INDRT_ACCESS_CTRL_0 ) ; do { v = sw_r32 ( RTL931X_SMI_INDRT_ACCESS_CTRL_0 ) ; } while ( v & BIT ( 0 ) ) ; pr_debug ( " \n " , __func__ , port , devnum , mdiobus_c45_regad ( regnum ) , val , err ) ; mutex_unlock ( & smi_lock ) ; return err ; }
Write to an mmd register of the PHY
Write to an mmd register of the PHY
// Set PHY to access via port-mask // Set data to write // Set MMD device number and register to write to // WRITE | MMD-access-type | EXEC