XilinxProcessorIPLib/drivers/dp14txss/examples/src/zcu_pt_dp14_mst/xvid_pat_gen.c
static void VidgenWriteConfig(XDp *InstancePtr,
				Vpg_VidgenConfig *VidgenConfig, u8 Stream)
{
#if !NEW_PAT_GEN
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VsyncPolarity,
				VidgenConfig->Timing.VSyncPolarity | 1);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HsyncPolarity,
				VidgenConfig->Timing.HSyncPolarity | 1);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VsyncWidth,
				VidgenConfig->Timing.F0PVSyncWidth);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VerticalBackPorch,
				VidgenConfig->Timing.F0PVBackPorch);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VerticalFrontPorch,
				VidgenConfig->Timing.F0PVFrontPorch);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VerticalResolution,
				VidgenConfig->Timing.VActive);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HsyncWidth,
				VidgenConfig->Timing.HSyncWidth);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HorizontalBackPorch,
				VidgenConfig->Timing.HBackPorch);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HorizontalFrontPorch,
				VidgenConfig->Timing.HFrontPorch);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HorizontalResolution,
				VidgenConfig->Timing.HActive);
	usleep(MicrosecToWait);


	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], DataEnablePolarity,
				VidgenConfig->DePolarity);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], Framelock_Enable_Delay,
				VidgenConfig->FrameLock0);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], FrameLock_AlignHsync_LineFrac,
				VidgenConfig->FrameLock1);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HdColorBarCfg,
				VidgenConfig->HdColorBarMode);

	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HSBLANK,
				VidgenConfig->TcHsBlnk);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HSSYNC,
				VidgenConfig->TcHsSync);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HESYNC,
				VidgenConfig->TcHeSync);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HEBLNK,
				VidgenConfig->TcHeBlnk);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VSBLNK,
				VidgenConfig->TcVsBlnk);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VSSYNC,
				VidgenConfig->TcVsSync);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VESYNC,
				VidgenConfig->TcVeSync);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VEBLNK,
				VidgenConfig->Timing.F0PVTotal);
	usleep(MicrosecToWait);
#else
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VerticalResolution,
				VidgenConfig->Timing.VActive);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HorizontalResolution,
				VidgenConfig->Timing.HActive);
	usleep(MicrosecToWait);
#endif

	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], MISC0,
				InstancePtr->TxInstance.MsaConfig[Stream - 1].Misc0);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], MISC1,
				InstancePtr->TxInstance.MsaConfig[Stream - 1].Misc1);
}
/*****************************************************************************/
/**
*
* This function writes timing parameters to Video Pattern Generator core.
*
* @param	InstancePtr is a pointer to the XDp instance.
* @param	VidgenConfig is a pointer to Vpg_VidgenConfig that will be
*		used to write parameter values into Video Pattern Generator
*		core registers.
* @param	Stream is the stream number used to identify the steam for
*		which parameters to be written.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function writes timing parameters to Video Pattern Generator core.
This function writes timing parameters to Video Pattern Generator core .
static void VidgenWriteConfig(XDp *InstancePtr,
				Vpg_VidgenConfig *VidgenConfig, u8 Stream)
{
#if !NEW_PAT_GEN
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VsyncPolarity,
				VidgenConfig->Timing.VSyncPolarity | 1);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HsyncPolarity,
				VidgenConfig->Timing.HSyncPolarity | 1);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VsyncWidth,
				VidgenConfig->Timing.F0PVSyncWidth);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VerticalBackPorch,
				VidgenConfig->Timing.F0PVBackPorch);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VerticalFrontPorch,
				VidgenConfig->Timing.F0PVFrontPorch);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VerticalResolution,
				VidgenConfig->Timing.VActive);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HsyncWidth,
				VidgenConfig->Timing.HSyncWidth);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HorizontalBackPorch,
				VidgenConfig->Timing.HBackPorch);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HorizontalFrontPorch,
				VidgenConfig->Timing.HFrontPorch);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HorizontalResolution,
				VidgenConfig->Timing.HActive);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], DataEnablePolarity,
				VidgenConfig->DePolarity);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], Framelock_Enable_Delay,
				VidgenConfig->FrameLock0);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], FrameLock_AlignHsync_LineFrac,
				VidgenConfig->FrameLock1);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HdColorBarCfg,
				VidgenConfig->HdColorBarMode);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HSBLANK,
				VidgenConfig->TcHsBlnk);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HSSYNC,
				VidgenConfig->TcHsSync);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HESYNC,
				VidgenConfig->TcHeSync);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HEBLNK,
				VidgenConfig->TcHeBlnk);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VSBLNK,
				VidgenConfig->TcVsBlnk);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VSSYNC,
				VidgenConfig->TcVsSync);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VESYNC,
				VidgenConfig->TcVeSync);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VEBLNK,
				VidgenConfig->Timing.F0PVTotal);
	usleep(MicrosecToWait);
#else
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], VerticalResolution,
				VidgenConfig->Timing.VActive);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], HorizontalResolution,
				VidgenConfig->Timing.HActive);
	usleep(MicrosecToWait);
#endif
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], MISC0,
				InstancePtr->TxInstance.MsaConfig[Stream - 1].Misc0);
	usleep(MicrosecToWait);
	XDp_WriteReg((XILINX_DISPLAYPORT_VID_BASE_ADDRESS) +
			StreamOffset[Stream - 1], MISC1,
				InstancePtr->TxInstance.MsaConfig[Stream - 1].Misc1);
}
static void VidgenWriteConfig ( XDp * InstancePtr , Vpg_VidgenConfig * VidgenConfig , u8 Stream ) { #if ! NEW_PAT_GEN XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , VsyncPolarity , VidgenConfig -> Timing . VSyncPolarity | 1 ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , HsyncPolarity , VidgenConfig -> Timing . HSyncPolarity | 1 ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , VsyncWidth , VidgenConfig -> Timing . F0PVSyncWidth ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , VerticalBackPorch , VidgenConfig -> Timing . F0PVBackPorch ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , VerticalFrontPorch , VidgenConfig -> Timing . F0PVFrontPorch ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , VerticalResolution , VidgenConfig -> Timing . VActive ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , HsyncWidth , VidgenConfig -> Timing . HSyncWidth ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , HorizontalBackPorch , VidgenConfig -> Timing . HBackPorch ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , HorizontalFrontPorch , VidgenConfig -> Timing . HFrontPorch ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , HorizontalResolution , VidgenConfig -> Timing . HActive ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , DataEnablePolarity , VidgenConfig -> DePolarity ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , Framelock_Enable_Delay , VidgenConfig -> FrameLock0 ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , FrameLock_AlignHsync_LineFrac , VidgenConfig -> FrameLock1 ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , HdColorBarCfg , VidgenConfig -> HdColorBarMode ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , HSBLANK , VidgenConfig -> TcHsBlnk ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , HSSYNC , VidgenConfig -> TcHsSync ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , HESYNC , VidgenConfig -> TcHeSync ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , HEBLNK , VidgenConfig -> TcHeBlnk ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , VSBLNK , VidgenConfig -> TcVsBlnk ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , VSSYNC , VidgenConfig -> TcVsSync ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , VESYNC , VidgenConfig -> TcVeSync ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , VEBLNK , VidgenConfig -> Timing . F0PVTotal ) ; usleep ( MicrosecToWait ) ; #else usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , VerticalResolution , VidgenConfig -> Timing . VActive ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , HorizontalResolution , VidgenConfig -> Timing . HActive ) ; usleep ( MicrosecToWait ) ; #endif XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , MISC0 , InstancePtr -> TxInstance . MsaConfig [ Stream - 1 ] . Misc0 ) ; usleep ( MicrosecToWait ) ; XDp_WriteReg ( ( XILINX_DISPLAYPORT_VID_BASE_ADDRESS ) + StreamOffset [ Stream - 1 ] , MISC1 , InstancePtr -> TxInstance . MsaConfig [ Stream - 1 ] . Misc1 ) ; }
This function writes timing parameters to Video Pattern Generator core.
This function writes timing parameters to Video Pattern Generator core .