XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_hdmi.c
void XHdmiphy1_ClkDetTimerLoad(XHdmiphy1 *InstancePtr, u8 QuadId,
		XHdmiphy1_DirectionType Dir, u32 TimeoutVal)
{
	u32 RegOffset;

	/* Suppress Warning Messages */
	QuadId = QuadId;

	if (Dir == XHDMIPHY1_DIR_TX) {
		RegOffset = XHDMIPHY1_CLKDET_TMR_TX_REG;
	}
	else {
		RegOffset = XHDMIPHY1_CLKDET_TMR_RX_REG;
	}

	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, TimeoutVal);
}
/*****************************************************************************/
/**
* This function loads the timer to TX/RX in the clock detector.
*
* @param	InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	Dir is an indicator for RX or TX.
* @param	TimeoutVal is the timeout value to store in the clock detector.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function loads the timer to TX/RX in the clock detector.
This function loads the timer to TX / RX in the clock detector .
void XHdmiphy1_ClkDetTimerLoad(XHdmiphy1 *InstancePtr, u8 QuadId,
		XHdmiphy1_DirectionType Dir, u32 TimeoutVal)
{
	u32 RegOffset;
	QuadId = QuadId;
	if (Dir == XHDMIPHY1_DIR_TX) {
		RegOffset = XHDMIPHY1_CLKDET_TMR_TX_REG;
	}
	else {
		RegOffset = XHDMIPHY1_CLKDET_TMR_RX_REG;
	}
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, TimeoutVal);
}
void XHdmiphy1_ClkDetTimerLoad ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_DirectionType Dir , u32 TimeoutVal ) { u32 RegOffset ; QuadId = QuadId ; if ( Dir == XHDMIPHY1_DIR_TX ) { RegOffset = XHDMIPHY1_CLKDET_TMR_TX_REG ; } else { RegOffset = XHDMIPHY1_CLKDET_TMR_RX_REG ; } XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffset , TimeoutVal ) ; }
This function loads the timer to TX/RX in the clock detector.
This function loads the timer to TX / RX in the clock detector .
/* Suppress Warning Messages */