src/dpdk/drivers/net/ixgbe/base/ixgbe_dcb_82598.c
s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
					   u16 *refill, u16 *max, u8 *bwg_id,
					   u8 *tsa)
{
	u32 reg, max_credits;
	u8 i;

	reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);

	/* Enable arbiter */
	reg &= ~IXGBE_DPMCS_ARBDIS;
	reg |= IXGBE_DPMCS_TSOEF;

	/* Configure Max TSO packet size 34KB including payload and headers */
	reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);

	IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);

	/* Configure traffic class credits and priority */
	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
		max_credits = max[i];
		reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
		reg |= (u32)(refill[i]);
		reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;

		if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
			reg |= IXGBE_TDTQ2TCCR_GSP;

		if (tsa[i] == ixgbe_dcb_tsa_strict)
			reg |= IXGBE_TDTQ2TCCR_LSP;

		IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
	}

	return IXGBE_SUCCESS;
}
/**
 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
 * @hw: pointer to hardware structure
 * @refill: refill credits index by traffic class
 * @max: max credits index by traffic class
 * @bwg_id: bandwidth grouping indexed by traffic class
 * @tsa: transmission selection algorithm indexed by traffic class
 *
 * Configure Tx Descriptor Arbiter and credits for each traffic class.
 */
Config Tx Desc.

Configure Tx Descriptor Arbiter and credits for each traffic class.
Config Tx Desc . Configure Tx Descriptor Arbiter and credits for each traffic class .
s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
					   u16 *refill, u16 *max, u8 *bwg_id,
					   u8 *tsa)
{
	u32 reg, max_credits;
	u8 i;
	reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
	reg &= ~IXGBE_DPMCS_ARBDIS;
	reg |= IXGBE_DPMCS_TSOEF;
	reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
	IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
		max_credits = max[i];
		reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
		reg |= (u32)(refill[i]);
		reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
		if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
			reg |= IXGBE_TDTQ2TCCR_GSP;
		if (tsa[i] == ixgbe_dcb_tsa_strict)
			reg |= IXGBE_TDTQ2TCCR_LSP;
		IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
	}
	return IXGBE_SUCCESS;
}
s32 ixgbe_dcb_config_tx_desc_arbiter_82598 ( struct ixgbe_hw * hw , u16 * refill , u16 * max , u8 * bwg_id , u8 * tsa ) { u32 reg , max_credits ; u8 i ; reg = IXGBE_READ_REG ( hw , IXGBE_DPMCS ) ; reg &= ~ IXGBE_DPMCS_ARBDIS ; reg |= IXGBE_DPMCS_TSOEF ; reg |= ( 0x4 << IXGBE_DPMCS_MTSOS_SHIFT ) ; IXGBE_WRITE_REG ( hw , IXGBE_DPMCS , reg ) ; for ( i = 0 ; i < IXGBE_DCB_MAX_TRAFFIC_CLASS ; i ++ ) { max_credits = max [ i ] ; reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT ; reg |= ( u32 ) ( refill [ i ] ) ; reg |= ( u32 ) ( bwg_id [ i ] ) << IXGBE_TDTQ2TCCR_BWG_SHIFT ; if ( tsa [ i ] == ixgbe_dcb_tsa_group_strict_cee ) reg |= IXGBE_TDTQ2TCCR_GSP ; if ( tsa [ i ] == ixgbe_dcb_tsa_strict ) reg |= IXGBE_TDTQ2TCCR_LSP ; IXGBE_WRITE_REG ( hw , IXGBE_TDTQ2TCCR ( i ) , reg ) ; } return IXGBE_SUCCESS ; }
ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc.
ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc .
/* Enable arbiter */ /* Configure Max TSO packet size 34KB including payload and headers */ /* Configure traffic class credits and priority */