XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_hdmi.c
void XHdmiphy1_ClkDetEnable(XHdmiphy1 *InstancePtr, u8 Enable)
{
	u32 RegVal;

	/* Read clkdet ctrl register. */
	RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
			XHDMIPHY1_CLKDET_CTRL_REG);

	/* Write new value to clkdet ctrl register. */
	if (Enable) {
		RegVal |= XHDMIPHY1_CLKDET_CTRL_RUN_MASK;
	}
	else {
		RegVal &= ~XHDMIPHY1_CLKDET_CTRL_RUN_MASK;
	}
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, XHDMIPHY1_CLKDET_CTRL_REG,
			RegVal);
}
/*****************************************************************************/
/**
* This function enables the HDMIPHY's detector peripheral.
*
* @param	InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param	Enable specifies TRUE/FALSE value to either enable or disable
*		the clock detector respectively.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function enables the HDMIPHY's detector peripheral.
This function enables the HDMIPHY ' s detector peripheral .
void XHdmiphy1_ClkDetEnable(XHdmiphy1 *InstancePtr, u8 Enable)
{
	u32 RegVal;
	RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
			XHDMIPHY1_CLKDET_CTRL_REG);
	if (Enable) {
		RegVal |= XHDMIPHY1_CLKDET_CTRL_RUN_MASK;
	}
	else {
		RegVal &= ~XHDMIPHY1_CLKDET_CTRL_RUN_MASK;
	}
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, XHDMIPHY1_CLKDET_CTRL_REG,
			RegVal);
}
void XHdmiphy1_ClkDetEnable ( XHdmiphy1 * InstancePtr , u8 Enable ) { u32 RegVal ; RegVal = XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_CLKDET_CTRL_REG ) ; if ( Enable ) { RegVal |= XHDMIPHY1_CLKDET_CTRL_RUN_MASK ; } else { RegVal &= ~ XHDMIPHY1_CLKDET_CTRL_RUN_MASK ; } XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_CLKDET_CTRL_REG , RegVal ) ; }
This function enables the HDMIPHY's detector peripheral.
This function enables the HDMIPHY ' s detector peripheral .
/* Read clkdet ctrl register. */ /* Write new value to clkdet ctrl register. */