XilinxProcessorIPLib/drivers/iic/src/xiic_master.c
static void RecvMasterData(XIic *InstancePtr)
{
	u8 LoopCnt;
	int BytesInFifo;
	int BytesToRead;
	u32 CntlReg;

	/*
	 * Device is a master receiving, get the contents of the control
	 * register and determine the number of bytes in fifo to be read out.
	 */
	CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
	BytesInFifo = XIic_ReadReg(InstancePtr->BaseAddress,
				XIIC_RFO_REG_OFFSET) + 1;

	/*
	 * If data in FIFO holds all data to be retrieved - 1, set NOACK and
	 * disable the Tx error.
	 */
	if ((InstancePtr->RecvByteCount - BytesInFifo) == 1) {
		/*
		 * Disable Tx error interrupt to prevent interrupt
		 * as this device will cause it when it set NO ACK next.
		 */
		XIic_DisableIntr(InstancePtr->BaseAddress,
				  XIIC_INTR_TX_ERROR_MASK);
		XIic_ClearIntr(InstancePtr->BaseAddress,
				XIIC_INTR_TX_ERROR_MASK);

		/*
		 * Write control reg with NO ACK allowing last byte to
		 * have the No ack set to indicate to slave last byte read.
		 */
		XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
			 (CntlReg | XIIC_CR_NO_ACK_MASK));

		/*
		 * Read one byte to clear a place for the last byte to be read
		 * which will set the NO ACK.
		 */
		XIic_ReadRecvByte(InstancePtr);
	}

	/*
	 * If data in FIFO is all the data to be received then get the data
	 * and also leave the device in a good state for the next transaction.
	 */
	else if ((InstancePtr->RecvByteCount - BytesInFifo) == 0) {
		/*
		 * If repeated start option is off then the master should stop
		 * using the bus, otherwise hold the bus, setting repeated start
		 * stops the slave from transmitting data when the FIFO is read.
		 */
		if ((InstancePtr->Options & XII_REPEATED_START_OPTION) == 0) {
			CntlReg &= ~XIIC_CR_MSMS_MASK;
		} else {
			CntlReg |= XIIC_CR_REPEATED_START_MASK;
		}
		XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
			 CntlReg);

		/*
		 * Read data from the FIFO then set zero based FIFO read depth
		 * for a byte.
		 */
		for (LoopCnt = 0; LoopCnt < BytesInFifo; LoopCnt++) {
			XIic_ReadRecvByte(InstancePtr);
		}
		XIic_WriteReg(InstancePtr->BaseAddress,
				XIIC_RFD_REG_OFFSET, 0);

		/*
		 * Disable Rx full interrupt and write the control reg with ACK
		 * allowing next byte sent to be acknowledged automatically.
		 */
		XIic_DisableIntr(InstancePtr->BaseAddress,
				  XIIC_INTR_RX_FULL_MASK);

		XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
			 (CntlReg & ~XIIC_CR_NO_ACK_MASK));

		/*
		 * Send notification of msg Rx complete in RecvHandler callback.
		 */
		InstancePtr->RecvHandler(InstancePtr->RecvCallBackRef, 0);
	} else {
		/*
		 * Fifo data not at n-1, read all but the last byte of data
		 * from the slave, if more than a FIFO full yet to receive
		 * read a FIFO full.
		 */
		BytesToRead = InstancePtr->RecvByteCount - BytesInFifo - 1;
		if (BytesToRead > IIC_RX_FIFO_DEPTH) {
			BytesToRead = IIC_RX_FIFO_DEPTH;
		}

		/*
		 * Read in data from the FIFO.
		 */
		for (LoopCnt = 0; LoopCnt < BytesToRead; LoopCnt++) {
			XIic_ReadRecvByte(InstancePtr);
		}
	}
}
/*****************************************************************************/
/**
*
* This function is called when the receive register is full. The number
* of bytes received to cause the interrupt is adjustable using the Receive FIFO
* Depth register. The number of bytes in the register is read in the Receive
* FIFO occupancy register. Both these registers are zero based values (0-15)
* such that a value of zero indicates 1 byte.
*
* For a Master Receiver to properly signal the end of a message, the data must
* be read in up to the message length - 1, where control register bits will be
* set for bus controls to occur on reading of the last byte.
*
* @param	InstancePtr is a pointer to the XIic instance to be worked on.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function is called when the receive register is full. The number
of bytes received to cause the interrupt is adjustable using the Receive FIFO
Depth register. The number of bytes in the register is read in the Receive
FIFO occupancy register. Both these registers are zero based values (0-15)
such that a value of zero indicates 1 byte.

For a Master Receiver to properly signal the end of a message, the data must
be read in up to the message length - 1, where control register bits will be
set for bus controls to occur on reading of the last byte.
This function is called when the receive register is full . The number of bytes received to cause the interrupt is adjustable using the Receive FIFO Depth register . The number of bytes in the register is read in the Receive FIFO occupancy register . Both these registers are zero based values ( 0 - 15 ) such that a value of zero indicates 1 byte . For a Master Receiver to properly signal the end of a message the data must be read in up to the message length - 1 where control register bits will be set for bus controls to occur on reading of the last byte .
static void RecvMasterData(XIic *InstancePtr)
{
	u8 LoopCnt;
	int BytesInFifo;
	int BytesToRead;
	u32 CntlReg;
	CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
	BytesInFifo = XIic_ReadReg(InstancePtr->BaseAddress,
				XIIC_RFO_REG_OFFSET) + 1;
	if ((InstancePtr->RecvByteCount - BytesInFifo) == 1) {
		XIic_DisableIntr(InstancePtr->BaseAddress,
				  XIIC_INTR_TX_ERROR_MASK);
		XIic_ClearIntr(InstancePtr->BaseAddress,
				XIIC_INTR_TX_ERROR_MASK);
		XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
			 (CntlReg | XIIC_CR_NO_ACK_MASK));
		XIic_ReadRecvByte(InstancePtr);
	}
	else if ((InstancePtr->RecvByteCount - BytesInFifo) == 0) {
		if ((InstancePtr->Options & XII_REPEATED_START_OPTION) == 0) {
			CntlReg &= ~XIIC_CR_MSMS_MASK;
		} else {
			CntlReg |= XIIC_CR_REPEATED_START_MASK;
		}
		XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
			 CntlReg);
		for (LoopCnt = 0; LoopCnt < BytesInFifo; LoopCnt++) {
			XIic_ReadRecvByte(InstancePtr);
		}
		XIic_WriteReg(InstancePtr->BaseAddress,
				XIIC_RFD_REG_OFFSET, 0);
		XIic_DisableIntr(InstancePtr->BaseAddress,
				  XIIC_INTR_RX_FULL_MASK);
		XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
			 (CntlReg & ~XIIC_CR_NO_ACK_MASK));
		InstancePtr->RecvHandler(InstancePtr->RecvCallBackRef, 0);
	} else {
		BytesToRead = InstancePtr->RecvByteCount - BytesInFifo - 1;
		if (BytesToRead > IIC_RX_FIFO_DEPTH) {
			BytesToRead = IIC_RX_FIFO_DEPTH;
		}
		for (LoopCnt = 0; LoopCnt < BytesToRead; LoopCnt++) {
			XIic_ReadRecvByte(InstancePtr);
		}
	}
}
static void RecvMasterData ( XIic * InstancePtr ) { u8 LoopCnt ; int BytesInFifo ; int BytesToRead ; u32 CntlReg ; CntlReg = XIic_ReadReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET ) ; BytesInFifo = XIic_ReadReg ( InstancePtr -> BaseAddress , XIIC_RFO_REG_OFFSET ) + 1 ; if ( ( InstancePtr -> RecvByteCount - BytesInFifo ) == 1 ) { XIic_DisableIntr ( InstancePtr -> BaseAddress , XIIC_INTR_TX_ERROR_MASK ) ; XIic_ClearIntr ( InstancePtr -> BaseAddress , XIIC_INTR_TX_ERROR_MASK ) ; XIic_WriteReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET , ( CntlReg | XIIC_CR_NO_ACK_MASK ) ) ; XIic_ReadRecvByte ( InstancePtr ) ; } else if ( ( InstancePtr -> RecvByteCount - BytesInFifo ) == 0 ) { if ( ( InstancePtr -> Options & XII_REPEATED_START_OPTION ) == 0 ) { CntlReg &= ~ XIIC_CR_MSMS_MASK ; } else { CntlReg |= XIIC_CR_REPEATED_START_MASK ; } XIic_WriteReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET , CntlReg ) ; for ( LoopCnt = 0 ; LoopCnt < BytesInFifo ; LoopCnt ++ ) { XIic_ReadRecvByte ( InstancePtr ) ; } XIic_WriteReg ( InstancePtr -> BaseAddress , XIIC_RFD_REG_OFFSET , 0 ) ; XIic_DisableIntr ( InstancePtr -> BaseAddress , XIIC_INTR_RX_FULL_MASK ) ; XIic_WriteReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET , ( CntlReg & ~ XIIC_CR_NO_ACK_MASK ) ) ; InstancePtr -> RecvHandler ( InstancePtr -> RecvCallBackRef , 0 ) ; } else { BytesToRead = InstancePtr -> RecvByteCount - BytesInFifo - 1 ; if ( BytesToRead > IIC_RX_FIFO_DEPTH ) { BytesToRead = IIC_RX_FIFO_DEPTH ; } for ( LoopCnt = 0 ; LoopCnt < BytesToRead ; LoopCnt ++ ) { XIic_ReadRecvByte ( InstancePtr ) ; } } }
This function is called when the receive register is full.
This function is called when the receive register is full .
/*
	 * Device is a master receiving, get the contents of the control
	 * register and determine the number of bytes in fifo to be read out.
	 */ /*
	 * If data in FIFO holds all data to be retrieved - 1, set NOACK and
	 * disable the Tx error.
	 */ /*
		 * Disable Tx error interrupt to prevent interrupt
		 * as this device will cause it when it set NO ACK next.
		 */ /*
		 * Write control reg with NO ACK allowing last byte to
		 * have the No ack set to indicate to slave last byte read.
		 */ /*
		 * Read one byte to clear a place for the last byte to be read
		 * which will set the NO ACK.
		 */ /*
	 * If data in FIFO is all the data to be received then get the data
	 * and also leave the device in a good state for the next transaction.
	 */ /*
		 * If repeated start option is off then the master should stop
		 * using the bus, otherwise hold the bus, setting repeated start
		 * stops the slave from transmitting data when the FIFO is read.
		 */ /*
		 * Read data from the FIFO then set zero based FIFO read depth
		 * for a byte.
		 */ /*
		 * Disable Rx full interrupt and write the control reg with ACK
		 * allowing next byte sent to be acknowledged automatically.
		 */ /*
		 * Send notification of msg Rx complete in RecvHandler callback.
		 */ /*
		 * Fifo data not at n-1, read all but the last byte of data
		 * from the slave, if more than a FIFO full yet to receive
		 * read a FIFO full.
		 */ /*
		 * Read in data from the FIFO.
		 */