src/dpdk/drivers/net/qede/qede_debug.c
static u32 qed_grc_dump_regs_entries(struct ecore_hwfn *p_hwfn,
				     struct ecore_ptt *p_ptt,
				     struct virt_mem_desc input_regs_arr,
				     u32 *dump_buf,
				     bool dump,
				     enum init_split_types split_type,
				     u8 split_id,
				     bool block_enable[MAX_BLOCK_ID],
				     u32 *num_dumped_reg_entries)
{
	u32 i, offset = 0, input_offset = 0;
	bool mode_match = true;

	*num_dumped_reg_entries = 0;

	while (input_offset < BYTES_TO_DWORDS(input_regs_arr.size)) {
		const struct dbg_dump_cond_hdr *cond_hdr =
		    (const struct dbg_dump_cond_hdr *)
		    input_regs_arr.ptr + input_offset++;
		u16 modes_buf_offset;
		bool eval_mode;

		/* Check mode/block */
		eval_mode = GET_FIELD(cond_hdr->mode.data,
				      DBG_MODE_HDR_EVAL_MODE) > 0;
		if (eval_mode) {
			modes_buf_offset =
				GET_FIELD(cond_hdr->mode.data,
					  DBG_MODE_HDR_MODES_BUF_OFFSET);
			mode_match = qed_is_mode_match(p_hwfn,
						       &modes_buf_offset);
		}

		if (!mode_match || !block_enable[cond_hdr->block_id]) {
			input_offset += cond_hdr->data_size;
			continue;
		}

		for (i = 0; i < cond_hdr->data_size; i++, input_offset++) {
			const struct dbg_dump_reg *reg =
			    (const struct dbg_dump_reg *)
			    input_regs_arr.ptr + input_offset;
			u32 addr, len;
			bool wide_bus;

			addr = GET_FIELD(reg->data, DBG_DUMP_REG_ADDRESS);
			len = GET_FIELD(reg->data, DBG_DUMP_REG_LENGTH);
			wide_bus = GET_FIELD(reg->data, DBG_DUMP_REG_WIDE_BUS);
			offset += qed_grc_dump_reg_entry(p_hwfn,
							 p_ptt,
							 dump_buf + offset,
							 dump,
							 addr,
							 len,
							 wide_bus,
							 split_type, split_id);
			(*num_dumped_reg_entries)++;
		}
	}

	return offset;
}
/* Dumps GRC registers entries. Returns the dumped size in dwords. */
Dumps GRC registers entries. Returns the dumped size in dwords.
Dumps GRC registers entries . Returns the dumped size in dwords .
static u32 qed_grc_dump_regs_entries(struct ecore_hwfn *p_hwfn,
				     struct ecore_ptt *p_ptt,
				     struct virt_mem_desc input_regs_arr,
				     u32 *dump_buf,
				     bool dump,
				     enum init_split_types split_type,
				     u8 split_id,
				     bool block_enable[MAX_BLOCK_ID],
				     u32 *num_dumped_reg_entries)
{
	u32 i, offset = 0, input_offset = 0;
	bool mode_match = true;
	*num_dumped_reg_entries = 0;
	while (input_offset < BYTES_TO_DWORDS(input_regs_arr.size)) {
		const struct dbg_dump_cond_hdr *cond_hdr =
		    (const struct dbg_dump_cond_hdr *)
		    input_regs_arr.ptr + input_offset++;
		u16 modes_buf_offset;
		bool eval_mode;
		eval_mode = GET_FIELD(cond_hdr->mode.data,
				      DBG_MODE_HDR_EVAL_MODE) > 0;
		if (eval_mode) {
			modes_buf_offset =
				GET_FIELD(cond_hdr->mode.data,
					  DBG_MODE_HDR_MODES_BUF_OFFSET);
			mode_match = qed_is_mode_match(p_hwfn,
						       &modes_buf_offset);
		}
		if (!mode_match || !block_enable[cond_hdr->block_id]) {
			input_offset += cond_hdr->data_size;
			continue;
		}
		for (i = 0; i < cond_hdr->data_size; i++, input_offset++) {
			const struct dbg_dump_reg *reg =
			    (const struct dbg_dump_reg *)
			    input_regs_arr.ptr + input_offset;
			u32 addr, len;
			bool wide_bus;
			addr = GET_FIELD(reg->data, DBG_DUMP_REG_ADDRESS);
			len = GET_FIELD(reg->data, DBG_DUMP_REG_LENGTH);
			wide_bus = GET_FIELD(reg->data, DBG_DUMP_REG_WIDE_BUS);
			offset += qed_grc_dump_reg_entry(p_hwfn,
							 p_ptt,
							 dump_buf + offset,
							 dump,
							 addr,
							 len,
							 wide_bus,
							 split_type, split_id);
			(*num_dumped_reg_entries)++;
		}
	}
	return offset;
}
static u32 qed_grc_dump_regs_entries ( struct ecore_hwfn * p_hwfn , struct ecore_ptt * p_ptt , struct virt_mem_desc input_regs_arr , u32 * dump_buf , bool dump , enum init_split_types split_type , u8 split_id , bool block_enable [ MAX_BLOCK_ID ] , u32 * num_dumped_reg_entries ) { u32 i , offset = 0 , input_offset = 0 ; bool mode_match = true ; * num_dumped_reg_entries = 0 ; while ( input_offset < BYTES_TO_DWORDS ( input_regs_arr . size ) ) { const struct dbg_dump_cond_hdr * cond_hdr = ( const struct dbg_dump_cond_hdr * ) input_regs_arr . ptr + input_offset ++ ; u16 modes_buf_offset ; bool eval_mode ; eval_mode = GET_FIELD ( cond_hdr -> mode . data , DBG_MODE_HDR_EVAL_MODE ) > 0 ; if ( eval_mode ) { modes_buf_offset = GET_FIELD ( cond_hdr -> mode . data , DBG_MODE_HDR_MODES_BUF_OFFSET ) ; mode_match = qed_is_mode_match ( p_hwfn , & modes_buf_offset ) ; } if ( ! mode_match || ! block_enable [ cond_hdr -> block_id ] ) { input_offset += cond_hdr -> data_size ; continue ; } for ( i = 0 ; i < cond_hdr -> data_size ; i ++ , input_offset ++ ) { const struct dbg_dump_reg * reg = ( const struct dbg_dump_reg * ) input_regs_arr . ptr + input_offset ; u32 addr , len ; bool wide_bus ; addr = GET_FIELD ( reg -> data , DBG_DUMP_REG_ADDRESS ) ; len = GET_FIELD ( reg -> data , DBG_DUMP_REG_LENGTH ) ; wide_bus = GET_FIELD ( reg -> data , DBG_DUMP_REG_WIDE_BUS ) ; offset += qed_grc_dump_reg_entry ( p_hwfn , p_ptt , dump_buf + offset , dump , addr , len , wide_bus , split_type , split_id ) ; ( * num_dumped_reg_entries ) ++ ; } } return offset ; }
Dumps GRC registers entries.
Dumps GRC registers entries .
/* Check mode/block */