bluepill/libopencm3/lib/stm32/f4/rcc.c
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
{
	/* Enable internal high-speed oscillator (HSI). */
	rcc_osc_on(RCC_HSI);
	rcc_wait_for_osc_ready(RCC_HSI);

	/* Select HSI as SYSCLK source. */
	rcc_set_sysclk_source(RCC_CFGR_SW_HSI);

	/* Enable external high-speed oscillator (HSE). */
	if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
		rcc_osc_on(RCC_HSE);
		rcc_wait_for_osc_ready(RCC_HSE);
	}

	/* Set the VOS scale mode */
	rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_PWR);
	pwr_set_vos_scale(clock->voltage_scale);

	/*
	 * Set prescalers for AHB, ADC, ABP1, ABP2.
	 * Do this before touching the PLL (TODO: why?).
	 */
	rcc_set_hpre(clock->hpre);
	rcc_set_ppre1(clock->ppre1);
	rcc_set_ppre2(clock->ppre2);

	/* Disable PLL oscillator before changing its configuration. */
	rcc_osc_off(RCC_PLL);

	/* Configure the PLL oscillator. */
	if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
		rcc_set_main_pll_hse(clock->pllm, clock->plln,
				clock->pllp, clock->pllq, clock->pllr);
	} else {
		rcc_set_main_pll_hsi(clock->pllm, clock->plln,
				clock->pllp, clock->pllq, clock->pllr);
	}

	/* Enable PLL oscillator and wait for it to stabilize. */
	rcc_osc_on(RCC_PLL);
	rcc_wait_for_osc_ready(RCC_PLL);

	/* Configure flash settings. */
	if (clock->flash_config & FLASH_ACR_DCEN) {
		flash_dcache_enable();
	} else {
		flash_dcache_disable();
	}
	if (clock->flash_config & FLASH_ACR_ICEN) {
		flash_icache_enable();
	} else {
		flash_icache_disable();
	}
	flash_set_ws(clock->flash_config);

	/* Select PLL as SYSCLK source. */
	rcc_set_sysclk_source(RCC_CFGR_SW_PLL);

	/* Wait for PLL clock to be selected. */
	rcc_wait_for_sysclk_status(RCC_PLL);

	/* Set the peripheral clock frequencies used. */
	rcc_ahb_frequency  = clock->ahb_frequency;
	rcc_apb1_frequency = clock->apb1_frequency;
	rcc_apb2_frequency = clock->apb2_frequency;

	/* Disable internal high-speed oscillator. */
	if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
		rcc_osc_off(RCC_HSI);
	}
}
/**
 * Setup clocks to run from PLL.
 *
 * The arguments provide the pll source, multipliers, dividers, all that's
 * needed to establish a system clock.
 *
 * @param clock clock information structure.
 */
Setup clocks to run from PLL.
The arguments provide the pll source, multipliers, dividers, all that's
needed to establish a system clock.

@param clock clock information structure.
Setup clocks to run from PLL . The arguments provide the pll source multipliers dividers all that ' s needed to establish a system clock . @param clock clock information structure .
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
{
	rcc_osc_on(RCC_HSI);
	rcc_wait_for_osc_ready(RCC_HSI);
	rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
	if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
		rcc_osc_on(RCC_HSE);
		rcc_wait_for_osc_ready(RCC_HSE);
	}
	rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_PWR);
	pwr_set_vos_scale(clock->voltage_scale);
	rcc_set_hpre(clock->hpre);
	rcc_set_ppre1(clock->ppre1);
	rcc_set_ppre2(clock->ppre2);
	rcc_osc_off(RCC_PLL);
	if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
		rcc_set_main_pll_hse(clock->pllm, clock->plln,
				clock->pllp, clock->pllq, clock->pllr);
	} else {
		rcc_set_main_pll_hsi(clock->pllm, clock->plln,
				clock->pllp, clock->pllq, clock->pllr);
	}
	rcc_osc_on(RCC_PLL);
	rcc_wait_for_osc_ready(RCC_PLL);
	if (clock->flash_config & FLASH_ACR_DCEN) {
		flash_dcache_enable();
	} else {
		flash_dcache_disable();
	}
	if (clock->flash_config & FLASH_ACR_ICEN) {
		flash_icache_enable();
	} else {
		flash_icache_disable();
	}
	flash_set_ws(clock->flash_config);
	rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
	rcc_wait_for_sysclk_status(RCC_PLL);
	rcc_ahb_frequency  = clock->ahb_frequency;
	rcc_apb1_frequency = clock->apb1_frequency;
	rcc_apb2_frequency = clock->apb2_frequency;
	if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
		rcc_osc_off(RCC_HSI);
	}
}
void rcc_clock_setup_pll ( const struct rcc_clock_scale * clock ) { rcc_osc_on ( RCC_HSI ) ; rcc_wait_for_osc_ready ( RCC_HSI ) ; rcc_set_sysclk_source ( RCC_CFGR_SW_HSI ) ; if ( clock -> pll_source == RCC_CFGR_PLLSRC_HSE_CLK ) { rcc_osc_on ( RCC_HSE ) ; rcc_wait_for_osc_ready ( RCC_HSE ) ; } rcc_peripheral_enable_clock ( & RCC_APB1ENR , RCC_PWR ) ; pwr_set_vos_scale ( clock -> voltage_scale ) ; rcc_set_hpre ( clock -> hpre ) ; rcc_set_ppre1 ( clock -> ppre1 ) ; rcc_set_ppre2 ( clock -> ppre2 ) ; rcc_osc_off ( RCC_PLL ) ; if ( clock -> pll_source == RCC_CFGR_PLLSRC_HSE_CLK ) { rcc_set_main_pll_hse ( clock -> pllm , clock -> plln , clock -> pllp , clock -> pllq , clock -> pllr ) ; } else { rcc_set_main_pll_hsi ( clock -> pllm , clock -> plln , clock -> pllp , clock -> pllq , clock -> pllr ) ; } rcc_osc_on ( RCC_PLL ) ; rcc_wait_for_osc_ready ( RCC_PLL ) ; if ( clock -> flash_config & FLASH_ACR_DCEN ) { flash_dcache_enable ( ) ; } else { flash_dcache_disable ( ) ; } if ( clock -> flash_config & FLASH_ACR_ICEN ) { flash_icache_enable ( ) ; } else { flash_icache_disable ( ) ; } flash_set_ws ( clock -> flash_config ) ; rcc_set_sysclk_source ( RCC_CFGR_SW_PLL ) ; rcc_wait_for_sysclk_status ( RCC_PLL ) ; rcc_ahb_frequency = clock -> ahb_frequency ; rcc_apb1_frequency = clock -> apb1_frequency ; rcc_apb2_frequency = clock -> apb2_frequency ; if ( clock -> pll_source == RCC_CFGR_PLLSRC_HSE_CLK ) { rcc_osc_off ( RCC_HSI ) ; } }
Setup clocks to run from PLL.
Setup clocks to run from PLL .
/* Enable internal high-speed oscillator (HSI). */ /* Select HSI as SYSCLK source. */ /* Enable external high-speed oscillator (HSE). */ /* Set the VOS scale mode */ /*
	 * Set prescalers for AHB, ADC, ABP1, ABP2.
	 * Do this before touching the PLL (TODO: why?).
	 */ /* Disable PLL oscillator before changing its configuration. */ /* Configure the PLL oscillator. */ /* Enable PLL oscillator and wait for it to stabilize. */ /* Configure flash settings. */ /* Select PLL as SYSCLK source. */ /* Wait for PLL clock to be selected. */ /* Set the peripheral clock frequencies used. */ /* Disable internal high-speed oscillator. */