XilinxProcessorIPLib/drivers/canps/src/xcanps_intr.c
void XCanPs_IntrHandler(void *InstancePtr)
{
	u32 PendingIntr;
	u32 EventIntr;
	u32 ErrorStatus;
	XCanPs *CanPtr = (XCanPs *) InstancePtr;

	Xil_AssertVoid(CanPtr != NULL);
	Xil_AssertVoid(CanPtr->IsReady == XIL_COMPONENT_IS_READY);

	PendingIntr = XCanPs_IntrGetStatus(CanPtr);
	PendingIntr &= XCanPs_IntrGetEnabled(CanPtr);

	/*
	 * Clear all pending interrupts.
	 * Rising Edge interrupt
	 */
	XCanPs_IntrClear(CanPtr, PendingIntr);

	/*
	 * An error interrupt is occurring.
	 */
	if (((PendingIntr & XCANPS_IXR_ERROR_MASK) != (u32)0) &&
		(CanPtr->ErrorHandler != NULL)) {
			ErrorStatus = XCanPs_GetBusErrorStatus(CanPtr);
			CanPtr->ErrorHandler(CanPtr->ErrorRef,ErrorStatus);
		/*
		 * Clear Error Status Register.
		 */
		XCanPs_ClearBusErrorStatus(CanPtr,ErrorStatus);
	}

	/*
	 * Check if any following event interrupt is pending:
	 *	  - RX FIFO Overflow
	 *	  - RX FIFO Underflow
	 *	  - TX High Priority Buffer full
	 *	  - TX FIFO Full
	 *	  - Wake up from sleep mode
	 *	  - Enter sleep mode
	 *	  - Enter Bus off status
	 *	  - Arbitration is lost
	 *
	 * If so, call event callback provided by upper level.
	 */
	EventIntr = PendingIntr & ((u32)XCANPS_IXR_RXOFLW_MASK |
				(u32)XCANPS_IXR_RXUFLW_MASK |
				(u32)XCANPS_IXR_TXBFLL_MASK |
				(u32)XCANPS_IXR_TXFLL_MASK |
				(u32)XCANPS_IXR_WKUP_MASK |
				(u32)XCANPS_IXR_SLP_MASK |
				(u32)XCANPS_IXR_BSOFF_MASK |
				(u32)XCANPS_IXR_ARBLST_MASK);
	if ((EventIntr != (u32)0) && (CanPtr->EventHandler != NULL)) {
		CanPtr->EventHandler(CanPtr->EventRef, EventIntr);

		if ((EventIntr & XCANPS_IXR_BSOFF_MASK) != (u32)0) {
			/*
			 * Event callback should reset whole device if "Enter
			 * Bus Off Status" interrupt occurred. All pending
			 * interrupts are cleared and no further checking and
			 * handling of other interrupts is needed any more.
			 */
			return;
		}
	}


	if (((PendingIntr & (XCANPS_IXR_RXFWMFLL_MASK |
			XCANPS_IXR_RXNEMP_MASK)) != (u32)0) &&
		(CanPtr->RecvHandler != NULL)) {

		/*
		 * This case happens when
		 * A number of frames depending on the Rx FIFO Watermark
		 * threshold are received.
		 * And  also when frame was received and is sitting in RX FIFO.
		 *
		 * XCANPS_IXR_RXOK_MASK is not used because the bit is set
		 * just once even if there are multiple frames sitting
		 * in the RX FIFO.
		 *
		 * XCANPS_IXR_RXNEMP_MASK is used because the bit can be
		 * set again and again automatically as long as there is
		 * at least one frame in RX FIFO.
		 */
		CanPtr->RecvHandler(CanPtr->RecvRef);
	}

	/*
	 * A frame was transmitted successfully.
	 */
	if (((PendingIntr & (XCANPS_IXR_TXOK_MASK | XCANPS_IXR_TXFWMEMP_MASK)) != (u32)0) &&
		(CanPtr->SendHandler != NULL)) {
		CanPtr->SendHandler(CanPtr->SendRef);
	}
}
/*****************************************************************************/
/**
*
* This routine is the interrupt handler for the CAN driver.
*
* This handler reads the interrupt status from the ISR, determines the source of
* the interrupts, calls according callbacks, and finally clears the interrupts.
*
* Application beyond this driver is responsible for providing callbacks to
* handle interrupts and installing the callbacks using XCanPs_SetHandler()
* during initialization phase. An example delivered with this driver
* demonstrates how this could be done.
*
* @param	InstancePtr is a pointer to the XCanPs instance that just
*		interrupted.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This routine is the interrupt handler for the CAN driver.
This handler reads the interrupt status from the ISR, determines the source of
the interrupts, calls according callbacks, and finally clears the interrupts.

Application beyond this driver is responsible for providing callbacks to
handle interrupts and installing the callbacks using XCanPs_SetHandler()
during initialization phase. An example delivered with this driver
demonstrates how this could be done.
This routine is the interrupt handler for the CAN driver . This handler reads the interrupt status from the ISR determines the source of the interrupts calls according callbacks and finally clears the interrupts . Application beyond this driver is responsible for providing callbacks to handle interrupts and installing the callbacks using XCanPs_SetHandler () during initialization phase . An example delivered with this driver demonstrates how this could be done .
void XCanPs_IntrHandler(void *InstancePtr)
{
	u32 PendingIntr;
	u32 EventIntr;
	u32 ErrorStatus;
	XCanPs *CanPtr = (XCanPs *) InstancePtr;
	Xil_AssertVoid(CanPtr != NULL);
	Xil_AssertVoid(CanPtr->IsReady == XIL_COMPONENT_IS_READY);
	PendingIntr = XCanPs_IntrGetStatus(CanPtr);
	PendingIntr &= XCanPs_IntrGetEnabled(CanPtr);
	XCanPs_IntrClear(CanPtr, PendingIntr);
	if (((PendingIntr & XCANPS_IXR_ERROR_MASK) != (u32)0) &&
		(CanPtr->ErrorHandler != NULL)) {
			ErrorStatus = XCanPs_GetBusErrorStatus(CanPtr);
			CanPtr->ErrorHandler(CanPtr->ErrorRef,ErrorStatus);
		XCanPs_ClearBusErrorStatus(CanPtr,ErrorStatus);
	}
	EventIntr = PendingIntr & ((u32)XCANPS_IXR_RXOFLW_MASK |
				(u32)XCANPS_IXR_RXUFLW_MASK |
				(u32)XCANPS_IXR_TXBFLL_MASK |
				(u32)XCANPS_IXR_TXFLL_MASK |
				(u32)XCANPS_IXR_WKUP_MASK |
				(u32)XCANPS_IXR_SLP_MASK |
				(u32)XCANPS_IXR_BSOFF_MASK |
				(u32)XCANPS_IXR_ARBLST_MASK);
	if ((EventIntr != (u32)0) && (CanPtr->EventHandler != NULL)) {
		CanPtr->EventHandler(CanPtr->EventRef, EventIntr);
		if ((EventIntr & XCANPS_IXR_BSOFF_MASK) != (u32)0) {
			return;
		}
	}
	if (((PendingIntr & (XCANPS_IXR_RXFWMFLL_MASK |
			XCANPS_IXR_RXNEMP_MASK)) != (u32)0) &&
		(CanPtr->RecvHandler != NULL)) {
		CanPtr->RecvHandler(CanPtr->RecvRef);
	}
	if (((PendingIntr & (XCANPS_IXR_TXOK_MASK | XCANPS_IXR_TXFWMEMP_MASK)) != (u32)0) &&
		(CanPtr->SendHandler != NULL)) {
		CanPtr->SendHandler(CanPtr->SendRef);
	}
}
void XCanPs_IntrHandler ( void * InstancePtr ) { u32 PendingIntr ; u32 EventIntr ; u32 ErrorStatus ; XCanPs * CanPtr = ( XCanPs * ) InstancePtr ; Xil_AssertVoid ( CanPtr != NULL ) ; Xil_AssertVoid ( CanPtr -> IsReady == XIL_COMPONENT_IS_READY ) ; PendingIntr = XCanPs_IntrGetStatus ( CanPtr ) ; PendingIntr &= XCanPs_IntrGetEnabled ( CanPtr ) ; XCanPs_IntrClear ( CanPtr , PendingIntr ) ; if ( ( ( PendingIntr & XCANPS_IXR_ERROR_MASK ) != ( u32 ) 0 ) && ( CanPtr -> ErrorHandler != NULL ) ) { ErrorStatus = XCanPs_GetBusErrorStatus ( CanPtr ) ; CanPtr -> ErrorHandler ( CanPtr -> ErrorRef , ErrorStatus ) ; XCanPs_ClearBusErrorStatus ( CanPtr , ErrorStatus ) ; } EventIntr = PendingIntr & ( ( u32 ) XCANPS_IXR_RXOFLW_MASK | ( u32 ) XCANPS_IXR_RXUFLW_MASK | ( u32 ) XCANPS_IXR_TXBFLL_MASK | ( u32 ) XCANPS_IXR_TXFLL_MASK | ( u32 ) XCANPS_IXR_WKUP_MASK | ( u32 ) XCANPS_IXR_SLP_MASK | ( u32 ) XCANPS_IXR_BSOFF_MASK | ( u32 ) XCANPS_IXR_ARBLST_MASK ) ; if ( ( EventIntr != ( u32 ) 0 ) && ( CanPtr -> EventHandler != NULL ) ) { CanPtr -> EventHandler ( CanPtr -> EventRef , EventIntr ) ; if ( ( EventIntr & XCANPS_IXR_BSOFF_MASK ) != ( u32 ) 0 ) { return ; } } if ( ( ( PendingIntr & ( XCANPS_IXR_RXFWMFLL_MASK | XCANPS_IXR_RXNEMP_MASK ) ) != ( u32 ) 0 ) && ( CanPtr -> RecvHandler != NULL ) ) { CanPtr -> RecvHandler ( CanPtr -> RecvRef ) ; } if ( ( ( PendingIntr & ( XCANPS_IXR_TXOK_MASK | XCANPS_IXR_TXFWMEMP_MASK ) ) != ( u32 ) 0 ) && ( CanPtr -> SendHandler != NULL ) ) { CanPtr -> SendHandler ( CanPtr -> SendRef ) ; } }
This routine is the interrupt handler for the CAN driver.
This routine is the interrupt handler for the CAN driver .
/*
	 * Clear all pending interrupts.
	 * Rising Edge interrupt
	 */ /*
	 * An error interrupt is occurring.
	 */ /*
		 * Clear Error Status Register.
		 */ /*
	 * Check if any following event interrupt is pending:
	 *	  - RX FIFO Overflow
	 *	  - RX FIFO Underflow
	 *	  - TX High Priority Buffer full
	 *	  - TX FIFO Full
	 *	  - Wake up from sleep mode
	 *	  - Enter sleep mode
	 *	  - Enter Bus off status
	 *	  - Arbitration is lost
	 *
	 * If so, call event callback provided by upper level.
	 */ /*
			 * Event callback should reset whole device if "Enter
			 * Bus Off Status" interrupt occurred. All pending
			 * interrupts are cleared and no further checking and
			 * handling of other interrupts is needed any more.
			 */ /*
		 * This case happens when
		 * A number of frames depending on the Rx FIFO Watermark
		 * threshold are received.
		 * And  also when frame was received and is sitting in RX FIFO.
		 *
		 * XCANPS_IXR_RXOK_MASK is not used because the bit is set
		 * just once even if there are multiple frames sitting
		 * in the RX FIFO.
		 *
		 * XCANPS_IXR_RXNEMP_MASK is used because the bit can be
		 * set again and again automatically as long as there is
		 * at least one frame in RX FIFO.
		 */ /*
	 * A frame was transmitted successfully.
	 */