src/dpdk/drivers/net/txgbe/txgbe_rxtx.c
static void
txgbe_dcb_rx_hw_config(struct rte_eth_dev *dev,
		       struct txgbe_dcb_config *dcb_config)
{
	uint32_t reg;
	uint32_t vlanctrl;
	uint8_t i;
	uint32_t q;
	struct txgbe_hw *hw = TXGBE_DEV_HW(dev);

	PMD_INIT_FUNC_TRACE();
	/*
	 * Disable the arbiter before changing parameters
	 * (always enable recycle mode; WSP)
	 */
	reg = TXGBE_ARBRXCTL_RRM | TXGBE_ARBRXCTL_WSP | TXGBE_ARBRXCTL_DIA;
	wr32(hw, TXGBE_ARBRXCTL, reg);

	reg = rd32(hw, TXGBE_PORTCTL);
	reg &= ~(TXGBE_PORTCTL_NUMTC_MASK | TXGBE_PORTCTL_NUMVT_MASK);
	if (dcb_config->num_tcs.pg_tcs == 4) {
		reg |= TXGBE_PORTCTL_NUMTC_4;
		if (dcb_config->vt_mode)
			reg |= TXGBE_PORTCTL_NUMVT_32;
		else
			wr32(hw, TXGBE_POOLCTL, 0);
	}

	if (dcb_config->num_tcs.pg_tcs == 8) {
		reg |= TXGBE_PORTCTL_NUMTC_8;
		if (dcb_config->vt_mode)
			reg |= TXGBE_PORTCTL_NUMVT_16;
		else
			wr32(hw, TXGBE_POOLCTL, 0);
	}

	wr32(hw, TXGBE_PORTCTL, reg);

	if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
		/* Disable drop for all queues in VMDQ mode*/
		for (q = 0; q < TXGBE_MAX_RX_QUEUE_NUM; q++) {
			u32 val = 1 << (q % 32);
			wr32m(hw, TXGBE_QPRXDROP(q / 32), val, val);
		}
	} else {
		/* Enable drop for all queues in SRIOV mode */
		for (q = 0; q < TXGBE_MAX_RX_QUEUE_NUM; q++) {
			u32 val = 1 << (q % 32);
			wr32m(hw, TXGBE_QPRXDROP(q / 32), val, val);
		}
	}

	/* VLNCTL: enable vlan filtering and allow all vlan tags through */
	vlanctrl = rd32(hw, TXGBE_VLANCTL);
	vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
	wr32(hw, TXGBE_VLANCTL, vlanctrl);

	/* VLANTBL - enable all vlan filters */
	for (i = 0; i < NUM_VFTA_REGISTERS; i++)
		wr32(hw, TXGBE_VLANTBL(i), 0xFFFFFFFF);

	/*
	 * Configure Rx packet plane (recycle mode; WSP) and
	 * enable arbiter
	 */
	reg = TXGBE_ARBRXCTL_RRM | TXGBE_ARBRXCTL_WSP;
	wr32(hw, TXGBE_ARBRXCTL, reg);
}
/**
 * txgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
 * @dev: pointer to eth_dev structure
 * @dcb_config: pointer to txgbe_dcb_config structure
 */
Configure general DCB RX HW parameters
@dev: pointer to eth_dev structure
@dcb_config: pointer to txgbe_dcb_config structure
Configure general DCB RX HW parameters @dev : pointer to eth_dev structure @dcb_config : pointer to txgbe_dcb_config structure
static void
txgbe_dcb_rx_hw_config(struct rte_eth_dev *dev,
		       struct txgbe_dcb_config *dcb_config)
{
	uint32_t reg;
	uint32_t vlanctrl;
	uint8_t i;
	uint32_t q;
	struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
	PMD_INIT_FUNC_TRACE();
	reg = TXGBE_ARBRXCTL_RRM | TXGBE_ARBRXCTL_WSP | TXGBE_ARBRXCTL_DIA;
	wr32(hw, TXGBE_ARBRXCTL, reg);
	reg = rd32(hw, TXGBE_PORTCTL);
	reg &= ~(TXGBE_PORTCTL_NUMTC_MASK | TXGBE_PORTCTL_NUMVT_MASK);
	if (dcb_config->num_tcs.pg_tcs == 4) {
		reg |= TXGBE_PORTCTL_NUMTC_4;
		if (dcb_config->vt_mode)
			reg |= TXGBE_PORTCTL_NUMVT_32;
		else
			wr32(hw, TXGBE_POOLCTL, 0);
	}
	if (dcb_config->num_tcs.pg_tcs == 8) {
		reg |= TXGBE_PORTCTL_NUMTC_8;
		if (dcb_config->vt_mode)
			reg |= TXGBE_PORTCTL_NUMVT_16;
		else
			wr32(hw, TXGBE_POOLCTL, 0);
	}
	wr32(hw, TXGBE_PORTCTL, reg);
	if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
		for (q = 0; q < TXGBE_MAX_RX_QUEUE_NUM; q++) {
			u32 val = 1 << (q % 32);
			wr32m(hw, TXGBE_QPRXDROP(q / 32), val, val);
		}
	} else {
		for (q = 0; q < TXGBE_MAX_RX_QUEUE_NUM; q++) {
			u32 val = 1 << (q % 32);
			wr32m(hw, TXGBE_QPRXDROP(q / 32), val, val);
		}
	}
	vlanctrl = rd32(hw, TXGBE_VLANCTL);
	vlanctrl |= TXGBE_VLANCTL_VFE; 
	wr32(hw, TXGBE_VLANCTL, vlanctrl);
	for (i = 0; i < NUM_VFTA_REGISTERS; i++)
		wr32(hw, TXGBE_VLANTBL(i), 0xFFFFFFFF);
	reg = TXGBE_ARBRXCTL_RRM | TXGBE_ARBRXCTL_WSP;
	wr32(hw, TXGBE_ARBRXCTL, reg);
}
static void txgbe_dcb_rx_hw_config ( struct rte_eth_dev * dev , struct txgbe_dcb_config * dcb_config ) { uint32_t reg ; uint32_t vlanctrl ; uint8_t i ; uint32_t q ; struct txgbe_hw * hw = TXGBE_DEV_HW ( dev ) ; PMD_INIT_FUNC_TRACE ( ) ; reg = TXGBE_ARBRXCTL_RRM | TXGBE_ARBRXCTL_WSP | TXGBE_ARBRXCTL_DIA ; wr32 ( hw , TXGBE_ARBRXCTL , reg ) ; reg = rd32 ( hw , TXGBE_PORTCTL ) ; reg &= ~ ( TXGBE_PORTCTL_NUMTC_MASK | TXGBE_PORTCTL_NUMVT_MASK ) ; if ( dcb_config -> num_tcs . pg_tcs == 4 ) { reg |= TXGBE_PORTCTL_NUMTC_4 ; if ( dcb_config -> vt_mode ) reg |= TXGBE_PORTCTL_NUMVT_32 ; else wr32 ( hw , TXGBE_POOLCTL , 0 ) ; } if ( dcb_config -> num_tcs . pg_tcs == 8 ) { reg |= TXGBE_PORTCTL_NUMTC_8 ; if ( dcb_config -> vt_mode ) reg |= TXGBE_PORTCTL_NUMVT_16 ; else wr32 ( hw , TXGBE_POOLCTL , 0 ) ; } wr32 ( hw , TXGBE_PORTCTL , reg ) ; if ( RTE_ETH_DEV_SRIOV ( dev ) . active == 0 ) { for ( q = 0 ; q < TXGBE_MAX_RX_QUEUE_NUM ; q ++ ) { u32 val = 1 << ( q % 32 ) ; wr32m ( hw , TXGBE_QPRXDROP ( q / 32 ) , val , val ) ; } } else { for ( q = 0 ; q < TXGBE_MAX_RX_QUEUE_NUM ; q ++ ) { u32 val = 1 << ( q % 32 ) ; wr32m ( hw , TXGBE_QPRXDROP ( q / 32 ) , val , val ) ; } } vlanctrl = rd32 ( hw , TXGBE_VLANCTL ) ; vlanctrl |= TXGBE_VLANCTL_VFE ; wr32 ( hw , TXGBE_VLANCTL , vlanctrl ) ; for ( i = 0 ; i < NUM_VFTA_REGISTERS ; i ++ ) wr32 ( hw , TXGBE_VLANTBL ( i ) , 0xFFFFFFFF ) ; reg = TXGBE_ARBRXCTL_RRM | TXGBE_ARBRXCTL_WSP ; wr32 ( hw , TXGBE_ARBRXCTL , reg ) ; }
txgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
 @dev: pointer to eth_dev structure
 @dcb_config: pointer to txgbe_dcb_config structure
txgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters @dev : pointer to eth_dev structure @dcb_config : pointer to txgbe_dcb_config structure
/*
	 * Disable the arbiter before changing parameters
	 * (always enable recycle mode; WSP)
	 */ /* Disable drop for all queues in VMDQ mode*/ /* Enable drop for all queues in SRIOV mode */ /* VLNCTL: enable vlan filtering and allow all vlan tags through */ /* enable vlan filters */ /* VLANTBL - enable all vlan filters */ /*
	 * Configure Rx packet plane (recycle mode; WSP) and
	 * enable arbiter
	 */