src/dpdk/drivers/net/vmxnet3/vmxnet3_ethdev.c
static int
eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
{
	struct rte_pci_device *pci_dev;
	struct vmxnet3_hw *hw = eth_dev->data->dev_private;
	uint32_t mac_hi, mac_lo, ver;
	struct rte_eth_link link;
	static const struct rte_mbuf_dynfield vmxnet3_segs_dynfield_desc = {
		.name = VMXNET3_SEGS_DYNFIELD_NAME,
		.size = sizeof(vmxnet3_segs_dynfield_t),
		.align = __alignof__(vmxnet3_segs_dynfield_t),
	};

	PMD_INIT_FUNC_TRACE();

	eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
	eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
	eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
	eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
	pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);

	/* extra mbuf field is required to guess MSS */
	vmxnet3_segs_dynfield_offset =
		rte_mbuf_dynfield_register(&vmxnet3_segs_dynfield_desc);
	if (vmxnet3_segs_dynfield_offset < 0) {
		PMD_INIT_LOG(ERR, "Cannot register mbuf field.");
		return -rte_errno;
	}

	/*
	 * for secondary processes, we don't initialize any further as primary
	 * has already done this work.
	 */
	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
		return 0;

	rte_eth_copy_pci_info(eth_dev, pci_dev);
	eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;

	/* Vendor and Device ID need to be set before init of shared code */
	hw->device_id = pci_dev->id.device_id;
	hw->vendor_id = pci_dev->id.vendor_id;
	hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
	hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;

	hw->num_rx_queues = 1;
	hw->num_tx_queues = 1;
	hw->bufs_per_pkt = 1;

	/* Check h/w version compatibility with driver. */
	ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
	PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);

	if (ver & (1 << VMXNET3_REV_4)) {
		VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
				       1 << VMXNET3_REV_4);
		hw->version = VMXNET3_REV_4 + 1;
	} else if (ver & (1 << VMXNET3_REV_3)) {
		VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
				       1 << VMXNET3_REV_3);
		hw->version = VMXNET3_REV_3 + 1;
	} else if (ver & (1 << VMXNET3_REV_2)) {
		VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
				       1 << VMXNET3_REV_2);
		hw->version = VMXNET3_REV_2 + 1;
	} else if (ver & (1 << VMXNET3_REV_1)) {
		VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
				       1 << VMXNET3_REV_1);
		hw->version = VMXNET3_REV_1 + 1;
	} else {
		PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver);
		return -EIO;
	}

	PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version);

	/* Check UPT version compatibility with driver. */
	ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
	PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
	if (ver & 0x1)
		VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
	else {
		PMD_INIT_LOG(ERR, "Incompatible UPT version.");
		return -EIO;
	}

	/* Getting MAC Address */
	mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
	mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
	memcpy(hw->perm_addr, &mac_lo, 4);
	memcpy(hw->perm_addr + 4, &mac_hi, 2);

	/* Allocate memory for storing MAC addresses */
	eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN *
					       VMXNET3_MAX_MAC_ADDRS, 0);
	if (eth_dev->data->mac_addrs == NULL) {
		PMD_INIT_LOG(ERR,
			     "Failed to allocate %d bytes needed to store MAC addresses",
			     RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
		return -ENOMEM;
	}
	/* Copy the permanent MAC address */
	rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr,
			&eth_dev->data->mac_addrs[0]);

	PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
		     hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
		     hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);

	/* Put device in Quiesce Mode */
	VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);

	/* allow untagged pkts */
	VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);

	hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
		eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc);

	hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
		VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
	RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) ==
		   hw->rxdata_desc_size);

	/* clear shadow stats */
	memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats));
	memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats));

	/* clear snapshot stats */
	memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats));
	memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats));

	/* set the initial link status */
	memset(&link, 0, sizeof(link));
	link.link_duplex = ETH_LINK_FULL_DUPLEX;
	link.link_speed = ETH_SPEED_NUM_10G;
	link.link_autoneg = ETH_LINK_FIXED;
	rte_eth_linkstatus_set(eth_dev, &link);

	return 0;
}
/*
 * It returns 0 on success.
 */
It returns 0 on success.
It returns 0 on success .
static int
eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
{
	struct rte_pci_device *pci_dev;
	struct vmxnet3_hw *hw = eth_dev->data->dev_private;
	uint32_t mac_hi, mac_lo, ver;
	struct rte_eth_link link;
	static const struct rte_mbuf_dynfield vmxnet3_segs_dynfield_desc = {
		.name = VMXNET3_SEGS_DYNFIELD_NAME,
		.size = sizeof(vmxnet3_segs_dynfield_t),
		.align = __alignof__(vmxnet3_segs_dynfield_t),
	};
	PMD_INIT_FUNC_TRACE();
	eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
	eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
	eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
	eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
	pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
	vmxnet3_segs_dynfield_offset =
		rte_mbuf_dynfield_register(&vmxnet3_segs_dynfield_desc);
	if (vmxnet3_segs_dynfield_offset < 0) {
		PMD_INIT_LOG(ERR, "Cannot register mbuf field.");
		return -rte_errno;
	}
	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
		return 0;
	rte_eth_copy_pci_info(eth_dev, pci_dev);
	eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
	hw->device_id = pci_dev->id.device_id;
	hw->vendor_id = pci_dev->id.vendor_id;
	hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
	hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
	hw->num_rx_queues = 1;
	hw->num_tx_queues = 1;
	hw->bufs_per_pkt = 1;
	ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
	PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
	if (ver & (1 << VMXNET3_REV_4)) {
		VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
				       1 << VMXNET3_REV_4);
		hw->version = VMXNET3_REV_4 + 1;
	} else if (ver & (1 << VMXNET3_REV_3)) {
		VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
				       1 << VMXNET3_REV_3);
		hw->version = VMXNET3_REV_3 + 1;
	} else if (ver & (1 << VMXNET3_REV_2)) {
		VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
				       1 << VMXNET3_REV_2);
		hw->version = VMXNET3_REV_2 + 1;
	} else if (ver & (1 << VMXNET3_REV_1)) {
		VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
				       1 << VMXNET3_REV_1);
		hw->version = VMXNET3_REV_1 + 1;
	} else {
		PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver);
		return -EIO;
	}
	PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version);
	ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
	PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
	if (ver & 0x1)
		VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
	else {
		PMD_INIT_LOG(ERR, "Incompatible UPT version.");
		return -EIO;
	}
	mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
	mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
	memcpy(hw->perm_addr, &mac_lo, 4);
	memcpy(hw->perm_addr + 4, &mac_hi, 2);
	eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN *
					       VMXNET3_MAX_MAC_ADDRS, 0);
	if (eth_dev->data->mac_addrs == NULL) {
		PMD_INIT_LOG(ERR,
			     "Failed to allocate %d bytes needed to store MAC addresses",
			     RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
		return -ENOMEM;
	}
	rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr,
			&eth_dev->data->mac_addrs[0]);
	PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
		     hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
		     hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
	VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
	VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
	hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
		eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc);
	hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
		VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
	RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) ==
		   hw->rxdata_desc_size);
	memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats));
	memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats));
	memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats));
	memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats));
	memset(&link, 0, sizeof(link));
	link.link_duplex = ETH_LINK_FULL_DUPLEX;
	link.link_speed = ETH_SPEED_NUM_10G;
	link.link_autoneg = ETH_LINK_FIXED;
	rte_eth_linkstatus_set(eth_dev, &link);
	return 0;
}
static int eth_vmxnet3_dev_init ( struct rte_eth_dev * eth_dev ) { struct rte_pci_device * pci_dev ; struct vmxnet3_hw * hw = eth_dev -> data -> dev_private ; uint32_t mac_hi , mac_lo , ver ; struct rte_eth_link link ; static const struct rte_mbuf_dynfield vmxnet3_segs_dynfield_desc = { . name = VMXNET3_SEGS_DYNFIELD_NAME , . size = sizeof ( vmxnet3_segs_dynfield_t ) , . align = __alignof__ ( vmxnet3_segs_dynfield_t ) , } ; PMD_INIT_FUNC_TRACE ( ) ; eth_dev -> dev_ops = & vmxnet3_eth_dev_ops ; eth_dev -> rx_pkt_burst = & vmxnet3_recv_pkts ; eth_dev -> tx_pkt_burst = & vmxnet3_xmit_pkts ; eth_dev -> tx_pkt_prepare = vmxnet3_prep_pkts ; pci_dev = RTE_ETH_DEV_TO_PCI ( eth_dev ) ; vmxnet3_segs_dynfield_offset = rte_mbuf_dynfield_register ( & vmxnet3_segs_dynfield_desc ) ; if ( vmxnet3_segs_dynfield_offset < 0 ) { PMD_INIT_LOG ( ERR , " " ) ; return - rte_errno ; } if ( rte_eal_process_type ( ) != RTE_PROC_PRIMARY ) return 0 ; rte_eth_copy_pci_info ( eth_dev , pci_dev ) ; eth_dev -> data -> dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS ; hw -> device_id = pci_dev -> id . device_id ; hw -> vendor_id = pci_dev -> id . vendor_id ; hw -> hw_addr0 = ( void * ) pci_dev -> mem_resource [ 0 ] . addr ; hw -> hw_addr1 = ( void * ) pci_dev -> mem_resource [ 1 ] . addr ; hw -> num_rx_queues = 1 ; hw -> num_tx_queues = 1 ; hw -> bufs_per_pkt = 1 ; ver = VMXNET3_READ_BAR1_REG ( hw , VMXNET3_REG_VRRS ) ; PMD_INIT_LOG ( DEBUG , " " , ver ) ; if ( ver & ( 1 << VMXNET3_REV_4 ) ) { VMXNET3_WRITE_BAR1_REG ( hw , VMXNET3_REG_VRRS , 1 << VMXNET3_REV_4 ) ; hw -> version = VMXNET3_REV_4 + 1 ; } else if ( ver & ( 1 << VMXNET3_REV_3 ) ) { VMXNET3_WRITE_BAR1_REG ( hw , VMXNET3_REG_VRRS , 1 << VMXNET3_REV_3 ) ; hw -> version = VMXNET3_REV_3 + 1 ; } else if ( ver & ( 1 << VMXNET3_REV_2 ) ) { VMXNET3_WRITE_BAR1_REG ( hw , VMXNET3_REG_VRRS , 1 << VMXNET3_REV_2 ) ; hw -> version = VMXNET3_REV_2 + 1 ; } else if ( ver & ( 1 << VMXNET3_REV_1 ) ) { VMXNET3_WRITE_BAR1_REG ( hw , VMXNET3_REG_VRRS , 1 << VMXNET3_REV_1 ) ; hw -> version = VMXNET3_REV_1 + 1 ; } else { PMD_INIT_LOG ( ERR , " " , ver ) ; return - EIO ; } PMD_INIT_LOG ( DEBUG , " \n " , hw -> version ) ; ver = VMXNET3_READ_BAR1_REG ( hw , VMXNET3_REG_UVRS ) ; PMD_INIT_LOG ( DEBUG , " " , ver ) ; if ( ver & 0x1 ) VMXNET3_WRITE_BAR1_REG ( hw , VMXNET3_REG_UVRS , 1 ) ; else { PMD_INIT_LOG ( ERR , " " ) ; return - EIO ; } mac_lo = VMXNET3_READ_BAR1_REG ( hw , VMXNET3_REG_MACL ) ; mac_hi = VMXNET3_READ_BAR1_REG ( hw , VMXNET3_REG_MACH ) ; memcpy ( hw -> perm_addr , & mac_lo , 4 ) ; memcpy ( hw -> perm_addr + 4 , & mac_hi , 2 ) ; eth_dev -> data -> mac_addrs = rte_zmalloc ( " " , RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS , 0 ) ; if ( eth_dev -> data -> mac_addrs == NULL ) { PMD_INIT_LOG ( ERR , " " , RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS ) ; return - ENOMEM ; } rte_ether_addr_copy ( ( struct rte_ether_addr * ) hw -> perm_addr , & eth_dev -> data -> mac_addrs [ 0 ] ) ; PMD_INIT_LOG ( DEBUG , " " , hw -> perm_addr [ 0 ] , hw -> perm_addr [ 1 ] , hw -> perm_addr [ 2 ] , hw -> perm_addr [ 3 ] , hw -> perm_addr [ 4 ] , hw -> perm_addr [ 5 ] ) ; VMXNET3_WRITE_BAR1_REG ( hw , VMXNET3_REG_CMD , VMXNET3_CMD_QUIESCE_DEV ) ; VMXNET3_SET_VFTABLE_ENTRY ( hw -> shadow_vfta , 0 ) ; hw -> txdata_desc_size = VMXNET3_VERSION_GE_3 ( hw ) ? eth_vmxnet3_txdata_get ( hw ) : sizeof ( struct Vmxnet3_TxDataDesc ) ; hw -> rxdata_desc_size = VMXNET3_VERSION_GE_3 ( hw ) ? VMXNET3_DEF_RXDATA_DESC_SIZE : 0 ; RTE_ASSERT ( ( hw -> rxdata_desc_size & ~ VMXNET3_RXDATA_DESC_SIZE_MASK ) == hw -> rxdata_desc_size ) ; memset ( hw -> saved_tx_stats , 0 , sizeof ( hw -> saved_tx_stats ) ) ; memset ( hw -> saved_rx_stats , 0 , sizeof ( hw -> saved_rx_stats ) ) ; memset ( hw -> snapshot_tx_stats , 0 , sizeof ( hw -> snapshot_tx_stats ) ) ; memset ( hw -> snapshot_rx_stats , 0 , sizeof ( hw -> snapshot_rx_stats ) ) ; memset ( & link , 0 , sizeof ( link ) ) ; link . link_duplex = ETH_LINK_FULL_DUPLEX ; link . link_speed = ETH_SPEED_NUM_10G ; link . link_autoneg = ETH_LINK_FIXED ; rte_eth_linkstatus_set ( eth_dev , & link ) ; return 0 ; }
It returns 0 on success.
It returns 0 on success .
/* extra mbuf field is required to guess MSS */ /*
	 * for secondary processes, we don't initialize any further as primary
	 * has already done this work.
	 */ /* Vendor and Device ID need to be set before init of shared code */ /* Check h/w version compatibility with driver. */ /* Check UPT version compatibility with driver. */ /* Getting MAC Address */ /* Allocate memory for storing MAC addresses */ /* Copy the permanent MAC address */ /* Put device in Quiesce Mode */ /* allow untagged pkts */ /* clear shadow stats */ /* clear snapshot stats */ /* set the initial link status */