AzureMXChip/MXCHIPAZ3166/core/lib/threadx/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c
void enableCPUInterface(void)
{
  unsigned int tmp;

  tmp = gic_cpu->GICC_CTLR;
  tmp = tmp | 0x1;          // Set bit 0
  gic_cpu->GICC_CTLR = tmp;
}
// Enables the CPU interface
// Must been done one each core seperately
Enables the CPU interface
Must been done one each core seperately
Enables the CPU interface Must been done one each core seperately
void enableCPUInterface(void)
{
  unsigned int tmp;
  tmp = gic_cpu->GICC_CTLR;
  tmp = tmp | 0x1;          
  gic_cpu->GICC_CTLR = tmp;
}
void enableCPUInterface ( void ) { unsigned int tmp ; tmp = gic_cpu -> GICC_CTLR ; tmp = tmp | 0x1 ; gic_cpu -> GICC_CTLR = tmp ; }
Enables the CPU interface
Must been done one each core seperately
Enables the CPU interface Must been done one each core seperately
// Set bit 0