lib/sw_apps/zynqmp_fsbl/src/xfsbl_partition_load.c
static u32 XFsbl_PartitionCopy(XFsblPs * FsblInstancePtr, u32 PartitionNum)
{
	u32 Status;
	u32 DestinationCpu;
	u32 CpuNo;
	u32 DestinationDevice;
	u32 ExecState;
	XFsblPs_PartitionHeader * PartitionHeader;
	u32 SrcAddress;
	PTRSIZE LoadAddress;
	u32 Length;
	u32 RunningCpu;
	u32 RegVal;

#ifdef ARMR5
	u32 Index;
#endif

	/**
	 * Assign the partition header to local variable
	 */
	PartitionHeader =
		&FsblInstancePtr->ImageHeader.PartitionHeader[PartitionNum];

	RunningCpu = FsblInstancePtr->ProcessorID;

	/**
	 * Check for XIP image
	 * No need to copy for XIP image
	 */
	DestinationCpu = XFsbl_GetDestinationCpu(PartitionHeader);

	/**
	 * if destination cpu is not present, it means it is for same cpu
	 */
	if (DestinationCpu == XIH_PH_ATTRB_DEST_CPU_NONE)
	{
		DestinationCpu = FsblInstancePtr->ProcessorID;
	}

	if (PartitionHeader->UnEncryptedDataWordLength == 0U)
	{
		/**
		 * Update the Handoff address only for the first application
		 * of that cpu
		 * This is for XIP image. For other partitions it handoff
		 * address is updated after partition validation
		 */
		CpuNo = FsblInstancePtr->HandoffCpuNo;
		if (XFsbl_CheckHandoffCpu(FsblInstancePtr,
				DestinationCpu) == XFSBL_SUCCESS)
		{
			/* Get the execution state */
			ExecState = XFsbl_GetA53ExecState(PartitionHeader);
			FsblInstancePtr->HandoffValues[CpuNo].CpuSettings =
			        DestinationCpu | ExecState;
			FsblInstancePtr->HandoffValues[CpuNo].HandoffAddress =
				PartitionHeader->DestinationExecutionAddress;
			FsblInstancePtr->HandoffCpuNo += 1U;
		} else {
			/**
			 *
			 * if two partitions has same destination cpu, error can
			 * be triggered here
			 */
		}
		Status = XFSBL_SUCCESS;
		goto END;
	}

	/**
	 * Get the source(flash offset) address where it needs to copy
	 */
	SrcAddress = FsblInstancePtr->ImageOffsetAddress +
				((PartitionHeader->DataWordOffset) *
					XIH_PARTITION_WORD_LENGTH);

	/**
	 * Length of the partition to be copied
	 */
	Length  = (PartitionHeader->TotalDataWordLength) *
					XIH_PARTITION_WORD_LENGTH;
	DestinationDevice = XFsbl_GetDestinationDevice(PartitionHeader);

	/**
	 * Copy the authentication certificate to auth. buffer
	 * Update Partition length to be copied.
	 * For bitstream it will be taken care saperately
	 */
#ifdef XFSBL_SECURE
	if ((XFsbl_IsRsaSignaturePresent(PartitionHeader) ==
			XIH_PH_ATTRB_RSA_SIGNATURE) &&
		(DestinationDevice != XIH_PH_ATTRB_DEST_DEVICE_PL)) {

		Length = Length - XFSBL_AUTH_CERT_MIN_SIZE;

		Status = FsblInstancePtr->DeviceOps.DeviceCopy((SrcAddress + Length),
					(INTPTR)AuthBuffer, XFSBL_AUTH_CERT_MIN_SIZE);
		if (XFSBL_SUCCESS != Status)
		{
			goto END;
		}
	}
#endif

	LoadAddress = (PTRSIZE)PartitionHeader->DestinationLoadAddress;
	/**
	 * Copy the PL to temporary DDR Address
	 * Copy the PS to Load Address
	 * Copy the PMU firmware to PMU RAM
	 */

	if (DestinationDevice == XIH_PH_ATTRB_DEST_DEVICE_PL)
	{
#ifdef XFSBL_BS
		/**
		 * In case of PS Only Reset, skip copying
		 * the PL bitstream
		 */
		if (FsblInstancePtr->ResetReason == XFSBL_PS_ONLY_RESET)
		{
			Status = XFSBL_SUCCESS;
			goto END;
		}

		if (LoadAddress == XFSBL_DUMMY_PL_ADDR)
		{
			LoadAddress = XFSBL_DDR_TEMP_ADDRESS;

#ifdef XFSBL_PL_LOAD_FROM_OCM
			/* In case of PL load from OCM, skip copying */
			Status = XFSBL_SUCCESS;
			goto END;
#endif
		}

#else
		XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_PL_NOT_ENABLED \r\n");
		Status = XFSBL_ERROR_PL_NOT_ENABLED;
		goto END;
#endif
	}

	/**
	 * When destination device is R5-0/R5-1/R5-L and load address is in TCM
	 * copy to high address of TCM address map
	 * Update the LoadAddress
	 */
	Status = XFsbl_GetLoadAddress(DestinationCpu, &LoadAddress, Length);
	if (XFSBL_SUCCESS != Status)
	{
		goto END;
	}

	/**
	 * Configure the memory
	 */
	Status = XFsbl_ConfigureMemory(FsblInstancePtr, RunningCpu, DestinationCpu,
						LoadAddress);
	if (XFSBL_SUCCESS != Status)
	{
		goto END;
	}


#ifdef ARMR5

	/*Disable IsR5IvtBackup */
	IsR5IvtBackup = FALSE;

	/**
	 *
	 * Enable IsR5IvtBackup,if FSBL is running in R5-0/R5-L at 0x0 TCM
	 * Store HIVEC 32 byte data to R5HivecBuffer,
	 * Update the High Vector locations for R5,
	 * set Exception Vector to HIVEC,based on above condition.
	 */
	if (((FsblInstancePtr->ProcessorID ==
			XIH_PH_ATTRB_DEST_CPU_R5_0) ||
		(FsblInstancePtr->ProcessorID ==
				XIH_PH_ATTRB_DEST_CPU_R5_L))  &&
		((LoadAddress >= XFSBL_R50_HIGH_ATCM_START_ADDRESS) &&
		(LoadAddress <
			(XFSBL_R50_HIGH_ATCM_START_ADDRESS + XFSBL_IVT_LENGTH))))
	{


		/**
		 * Enable IsR5IvtBackup,this will used in
		 * XFsbl_PartitionLoad for restoring R5 vectors
		 */
		IsR5IvtBackup = TRUE;

		/**
		 * Get the length of the IVT area to be
		 * skipped from Load Address
		 */
		TcmSkipAddress = LoadAddress%XFSBL_IVT_LENGTH;
		TcmSkipLength = XFSBL_IVT_LENGTH - TcmSkipAddress;
		XFsbl_Printf(DEBUG_DETAILED,"XFsbl_PartitionCopy:Going for LOVEC HIGHVEC Mechanism for R5.\n\r");

		/**
		 * Check if Length is less than SkipLength
		 */
		if (TcmSkipLength > Length) {
			TcmSkipLength = Length;
		}

		/*Store HIVEC 32 bytes data to R5HivecBuffer*/
		(void)XFsbl_MemCpy((u8*)R5HivecBuffer,(u8*)XFSBL_R5_HIVEC,XFSBL_IVT_LENGTH);


		 /* Update the High Vector locations for R5.*/

		Index = XFSBL_R5_HIVEC;
		while (Index < (XFSBL_R5_HIVEC + 32U)) {
			XFsbl_Out32(Index, XFSBL_R5_HIVEC_VALUE);
			Index += 4U;
		}

		/**
		 * Make sure that Low Vector locations are written Properly
		 * Flush the cache
		 */
		Xil_DCacheFlush();

		/*set exception vector to HIVEC */
		XFsbl_SetR5ExcepVectorHiVec();
	}
#endif

	if (DestinationCpu == XIH_PH_ATTRB_DEST_CPU_PMU)
	{
		/* Trigger IPI only for first PMUFW partition */
		if(PartitionHeader->DestinationExecutionAddress != 0U) {
			/* Enable PMU_0 IPI */
			XFsbl_Out32(IPI_PMU_0_IER, IPI_PMU_0_IER_PMU_0_MASK);

			/* Trigger PMU0 IPI in PMU IPI TRIG Reg */
			XFsbl_Out32(IPI_PMU_0_TRIG, IPI_PMU_0_TRIG_PMU_0_MASK);
		}

		/**
		 * Wait until PMU Microblaze goes to sleep state,
		 * before starting firmware download to PMU RAM
		 */
		do {
				RegVal = XFsbl_In32(PMU_GLOBAL_GLOBAL_CNTRL);
				if ((RegVal & PMU_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_MASK)
					== PMU_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_MASK) {
					break;
				}
		} while (1);
	}

#ifdef XFSBL_PERF
	XTime tCur = 0;
	XTime_GetTime(&tCur);
#endif
	/**
	 * Copy the partition to PS_DDR/PL_DDR/TCM
	 */
	Status = FsblInstancePtr->DeviceOps.DeviceCopy(SrcAddress,
					LoadAddress, Length);

#ifdef XFSBL_PERF
	XFsbl_MeasurePerfTime(tCur);
	XFsbl_Printf(DEBUG_PRINT_ALWAYS, ": P%u Copy time, Size: %0u \r\n",
				PartitionNum, Length);
#endif


END:
	return Status;
}
/*****************************************************************************/
/**
 * This function copies the partition to specified destination
 *
 * @param	FsblInstancePtr is pointer to the XFsbl Instance
 *
 * @param	PartitionNum is the partition number in the image to be loaded
 *
 * @return	returns the error codes described in xfsbl_error.h on any error
 * 			returns XFSBL_SUCCESS on success
 *****************************************************************************/
This function copies the partition to specified destination
@param       FsblInstancePtr is pointer to the XFsbl Instance

@param       PartitionNum is the partition number in the image to be loaded

@return      returns the error codes described in xfsbl_error.h on any error
returns XFSBL_SUCCESS on success
This function copies the partition to specified destination @param FsblInstancePtr is pointer to the XFsbl Instance @param PartitionNum is the partition number in the image to be loaded @return returns the error codes described in xfsbl_error . h on any error returns XFSBL_SUCCESS on success
static u32 XFsbl_PartitionCopy(XFsblPs * FsblInstancePtr, u32 PartitionNum)
{
	u32 Status;
	u32 DestinationCpu;
	u32 CpuNo;
	u32 DestinationDevice;
	u32 ExecState;
	XFsblPs_PartitionHeader * PartitionHeader;
	u32 SrcAddress;
	PTRSIZE LoadAddress;
	u32 Length;
	u32 RunningCpu;
	u32 RegVal;
#ifdef ARMR5
	u32 Index;
#endif
	PartitionHeader =
		&FsblInstancePtr->ImageHeader.PartitionHeader[PartitionNum];
	RunningCpu = FsblInstancePtr->ProcessorID;
	DestinationCpu = XFsbl_GetDestinationCpu(PartitionHeader);
	if (DestinationCpu == XIH_PH_ATTRB_DEST_CPU_NONE)
	{
		DestinationCpu = FsblInstancePtr->ProcessorID;
	}
	if (PartitionHeader->UnEncryptedDataWordLength == 0U)
	{
		CpuNo = FsblInstancePtr->HandoffCpuNo;
		if (XFsbl_CheckHandoffCpu(FsblInstancePtr,
				DestinationCpu) == XFSBL_SUCCESS)
		{
			ExecState = XFsbl_GetA53ExecState(PartitionHeader);
			FsblInstancePtr->HandoffValues[CpuNo].CpuSettings =
			        DestinationCpu | ExecState;
			FsblInstancePtr->HandoffValues[CpuNo].HandoffAddress =
				PartitionHeader->DestinationExecutionAddress;
			FsblInstancePtr->HandoffCpuNo += 1U;
		} else {
		}
		Status = XFSBL_SUCCESS;
		goto END;
	}
	SrcAddress = FsblInstancePtr->ImageOffsetAddress +
				((PartitionHeader->DataWordOffset) *
					XIH_PARTITION_WORD_LENGTH);
	Length  = (PartitionHeader->TotalDataWordLength) *
					XIH_PARTITION_WORD_LENGTH;
	DestinationDevice = XFsbl_GetDestinationDevice(PartitionHeader);
#ifdef XFSBL_SECURE
	if ((XFsbl_IsRsaSignaturePresent(PartitionHeader) ==
			XIH_PH_ATTRB_RSA_SIGNATURE) &&
		(DestinationDevice != XIH_PH_ATTRB_DEST_DEVICE_PL)) {
		Length = Length - XFSBL_AUTH_CERT_MIN_SIZE;
		Status = FsblInstancePtr->DeviceOps.DeviceCopy((SrcAddress + Length),
					(INTPTR)AuthBuffer, XFSBL_AUTH_CERT_MIN_SIZE);
		if (XFSBL_SUCCESS != Status)
		{
			goto END;
		}
	}
#endif
	LoadAddress = (PTRSIZE)PartitionHeader->DestinationLoadAddress;
	if (DestinationDevice == XIH_PH_ATTRB_DEST_DEVICE_PL)
	{
#ifdef XFSBL_BS
		if (FsblInstancePtr->ResetReason == XFSBL_PS_ONLY_RESET)
		{
			Status = XFSBL_SUCCESS;
			goto END;
		}
		if (LoadAddress == XFSBL_DUMMY_PL_ADDR)
		{
			LoadAddress = XFSBL_DDR_TEMP_ADDRESS;
#ifdef XFSBL_PL_LOAD_FROM_OCM
			Status = XFSBL_SUCCESS;
			goto END;
#endif
		}
#else
		XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_PL_NOT_ENABLED \r\n");
		Status = XFSBL_ERROR_PL_NOT_ENABLED;
		goto END;
#endif
	}
	Status = XFsbl_GetLoadAddress(DestinationCpu, &LoadAddress, Length);
	if (XFSBL_SUCCESS != Status)
	{
		goto END;
	}
	Status = XFsbl_ConfigureMemory(FsblInstancePtr, RunningCpu, DestinationCpu,
						LoadAddress);
	if (XFSBL_SUCCESS != Status)
	{
		goto END;
	}
#ifdef ARMR5
	IsR5IvtBackup = FALSE;
	if (((FsblInstancePtr->ProcessorID ==
			XIH_PH_ATTRB_DEST_CPU_R5_0) ||
		(FsblInstancePtr->ProcessorID ==
				XIH_PH_ATTRB_DEST_CPU_R5_L))  &&
		((LoadAddress >= XFSBL_R50_HIGH_ATCM_START_ADDRESS) &&
		(LoadAddress <
			(XFSBL_R50_HIGH_ATCM_START_ADDRESS + XFSBL_IVT_LENGTH))))
	{
		IsR5IvtBackup = TRUE;
		TcmSkipAddress = LoadAddress%XFSBL_IVT_LENGTH;
		TcmSkipLength = XFSBL_IVT_LENGTH - TcmSkipAddress;
		XFsbl_Printf(DEBUG_DETAILED,"XFsbl_PartitionCopy:Going for LOVEC HIGHVEC Mechanism for R5.\n\r");
		if (TcmSkipLength > Length) {
			TcmSkipLength = Length;
		}
		(void)XFsbl_MemCpy((u8*)R5HivecBuffer,(u8*)XFSBL_R5_HIVEC,XFSBL_IVT_LENGTH);
		Index = XFSBL_R5_HIVEC;
		while (Index < (XFSBL_R5_HIVEC + 32U)) {
			XFsbl_Out32(Index, XFSBL_R5_HIVEC_VALUE);
			Index += 4U;
		}
		Xil_DCacheFlush();
		XFsbl_SetR5ExcepVectorHiVec();
	}
#endif
	if (DestinationCpu == XIH_PH_ATTRB_DEST_CPU_PMU)
	{
		if(PartitionHeader->DestinationExecutionAddress != 0U) {
			XFsbl_Out32(IPI_PMU_0_IER, IPI_PMU_0_IER_PMU_0_MASK);
			XFsbl_Out32(IPI_PMU_0_TRIG, IPI_PMU_0_TRIG_PMU_0_MASK);
		}
		do {
				RegVal = XFsbl_In32(PMU_GLOBAL_GLOBAL_CNTRL);
				if ((RegVal & PMU_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_MASK)
					== PMU_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_MASK) {
					break;
				}
		} while (1);
	}
#ifdef XFSBL_PERF
	XTime tCur = 0;
	XTime_GetTime(&tCur);
#endif
	Status = FsblInstancePtr->DeviceOps.DeviceCopy(SrcAddress,
					LoadAddress, Length);
#ifdef XFSBL_PERF
	XFsbl_MeasurePerfTime(tCur);
	XFsbl_Printf(DEBUG_PRINT_ALWAYS, ": P%u Copy time, Size: %0u \r\n",
				PartitionNum, Length);
#endif
END:
	return Status;
}
static u32 XFsbl_PartitionCopy ( XFsblPs * FsblInstancePtr , u32 PartitionNum ) { u32 Status ; u32 DestinationCpu ; u32 CpuNo ; u32 DestinationDevice ; u32 ExecState ; XFsblPs_PartitionHeader * PartitionHeader ; u32 SrcAddress ; PTRSIZE LoadAddress ; u32 Length ; u32 RunningCpu ; u32 RegVal ; #ifdef ARMR5 u32 Index ; #endif PartitionHeader = & FsblInstancePtr -> ImageHeader . PartitionHeader [ PartitionNum ] ; RunningCpu = FsblInstancePtr -> ProcessorID ; DestinationCpu = XFsbl_GetDestinationCpu ( PartitionHeader ) ; if ( DestinationCpu == XIH_PH_ATTRB_DEST_CPU_NONE ) { DestinationCpu = FsblInstancePtr -> ProcessorID ; } if ( PartitionHeader -> UnEncryptedDataWordLength == 0U ) { CpuNo = FsblInstancePtr -> HandoffCpuNo ; if ( XFsbl_CheckHandoffCpu ( FsblInstancePtr , DestinationCpu ) == XFSBL_SUCCESS ) { ExecState = XFsbl_GetA53ExecState ( PartitionHeader ) ; FsblInstancePtr -> HandoffValues [ CpuNo ] . CpuSettings = DestinationCpu | ExecState ; FsblInstancePtr -> HandoffValues [ CpuNo ] . HandoffAddress = PartitionHeader -> DestinationExecutionAddress ; FsblInstancePtr -> HandoffCpuNo += 1U ; } else { } Status = XFSBL_SUCCESS ; goto END ; } SrcAddress = FsblInstancePtr -> ImageOffsetAddress + ( ( PartitionHeader -> DataWordOffset ) * XIH_PARTITION_WORD_LENGTH ) ; Length = ( PartitionHeader -> TotalDataWordLength ) * XIH_PARTITION_WORD_LENGTH ; DestinationDevice = XFsbl_GetDestinationDevice ( PartitionHeader ) ; #ifdef XFSBL_SECURE if ( ( XFsbl_IsRsaSignaturePresent ( PartitionHeader ) == XIH_PH_ATTRB_RSA_SIGNATURE ) && ( DestinationDevice != XIH_PH_ATTRB_DEST_DEVICE_PL ) ) { Length = Length - XFSBL_AUTH_CERT_MIN_SIZE ; Status = FsblInstancePtr -> DeviceOps . DeviceCopy ( ( SrcAddress + Length ) , ( INTPTR ) AuthBuffer , XFSBL_AUTH_CERT_MIN_SIZE ) ; if ( XFSBL_SUCCESS != Status ) { goto END ; } } #endif LoadAddress = ( PTRSIZE ) PartitionHeader -> DestinationLoadAddress ; if ( DestinationDevice == XIH_PH_ATTRB_DEST_DEVICE_PL ) { #ifdef XFSBL_BS if ( FsblInstancePtr -> ResetReason == XFSBL_PS_ONLY_RESET ) { Status = XFSBL_SUCCESS ; goto END ; } if ( LoadAddress == XFSBL_DUMMY_PL_ADDR ) { LoadAddress = XFSBL_DDR_TEMP_ADDRESS ; #ifdef XFSBL_PL_LOAD_FROM_OCM Status = XFSBL_SUCCESS ; goto END ; #endif } #else XFsbl_Printf ( DEBUG_GENERAL , " \r \n " ) ; Status = XFSBL_ERROR_PL_NOT_ENABLED ; goto END ; #endif } Status = XFsbl_GetLoadAddress ( DestinationCpu , & LoadAddress , Length ) ; if ( XFSBL_SUCCESS != Status ) { goto END ; } Status = XFsbl_ConfigureMemory ( FsblInstancePtr , RunningCpu , DestinationCpu , LoadAddress ) ; if ( XFSBL_SUCCESS != Status ) { goto END ; } #ifdef ARMR5 IsR5IvtBackup = FALSE ; if ( ( ( FsblInstancePtr -> ProcessorID == XIH_PH_ATTRB_DEST_CPU_R5_0 ) || ( FsblInstancePtr -> ProcessorID == XIH_PH_ATTRB_DEST_CPU_R5_L ) ) && ( ( LoadAddress >= XFSBL_R50_HIGH_ATCM_START_ADDRESS ) && ( LoadAddress < ( XFSBL_R50_HIGH_ATCM_START_ADDRESS + XFSBL_IVT_LENGTH ) ) ) ) { IsR5IvtBackup = TRUE ; TcmSkipAddress = LoadAddress % XFSBL_IVT_LENGTH ; TcmSkipLength = XFSBL_IVT_LENGTH - TcmSkipAddress ; XFsbl_Printf ( DEBUG_DETAILED , " \n \r " ) ; if ( TcmSkipLength > Length ) { TcmSkipLength = Length ; } ( void ) XFsbl_MemCpy ( ( u8 * ) R5HivecBuffer , ( u8 * ) XFSBL_R5_HIVEC , XFSBL_IVT_LENGTH ) ; Index = XFSBL_R5_HIVEC ; while ( Index < ( XFSBL_R5_HIVEC + 32U ) ) { XFsbl_Out32 ( Index , XFSBL_R5_HIVEC_VALUE ) ; Index += 4U ; } Xil_DCacheFlush ( ) ; XFsbl_SetR5ExcepVectorHiVec ( ) ; } #endif if ( DestinationCpu == XIH_PH_ATTRB_DEST_CPU_PMU ) { if ( PartitionHeader -> DestinationExecutionAddress != 0U ) { XFsbl_Out32 ( IPI_PMU_0_IER , IPI_PMU_0_IER_PMU_0_MASK ) ; XFsbl_Out32 ( IPI_PMU_0_TRIG , IPI_PMU_0_TRIG_PMU_0_MASK ) ; } do { RegVal = XFsbl_In32 ( PMU_GLOBAL_GLOBAL_CNTRL ) ; if ( ( RegVal & PMU_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_MASK ) == PMU_GLOBAL_GLOBAL_CNTRL_MB_SLEEP_MASK ) { break ; } } while ( 1 ) ; } #ifdef XFSBL_PERF XTime tCur = 0 ; XTime_GetTime ( & tCur ) ; #endif Status = FsblInstancePtr -> DeviceOps . DeviceCopy ( SrcAddress , LoadAddress , Length ) ; #ifdef XFSBL_PERF XFsbl_MeasurePerfTime ( tCur ) ; XFsbl_Printf ( DEBUG_PRINT_ALWAYS , " \r \n " , PartitionNum , Length ) ; #endif END : return Status ; }
This function copies the partition to specified destination
 @param       FsblInstancePtr is pointer to the XFsbl Instance
This function copies the partition to specified destination @param FsblInstancePtr is pointer to the XFsbl Instance
/**
	 * Assign the partition header to local variable
	 */ /**
	 * Check for XIP image
	 * No need to copy for XIP image
	 */ /**
	 * if destination cpu is not present, it means it is for same cpu
	 */ /**
		 * Update the Handoff address only for the first application
		 * of that cpu
		 * This is for XIP image. For other partitions it handoff
		 * address is updated after partition validation
		 */ /* Get the execution state */ /**
			 *
			 * if two partitions has same destination cpu, error can
			 * be triggered here
			 */ /**
	 * Get the source(flash offset) address where it needs to copy
	 */ /**
	 * Length of the partition to be copied
	 */ /**
	 * Copy the authentication certificate to auth. buffer
	 * Update Partition length to be copied.
	 * For bitstream it will be taken care saperately
	 */ /**
	 * Copy the PL to temporary DDR Address
	 * Copy the PS to Load Address
	 * Copy the PMU firmware to PMU RAM
	 */ /**
		 * In case of PS Only Reset, skip copying
		 * the PL bitstream
		 */ /* In case of PL load from OCM, skip copying */ /**
	 * When destination device is R5-0/R5-1/R5-L and load address is in TCM
	 * copy to high address of TCM address map
	 * Update the LoadAddress
	 */ /**
	 * Configure the memory
	 */ /*Disable IsR5IvtBackup */ /**
	 *
	 * Enable IsR5IvtBackup,if FSBL is running in R5-0/R5-L at 0x0 TCM
	 * Store HIVEC 32 byte data to R5HivecBuffer,
	 * Update the High Vector locations for R5,
	 * set Exception Vector to HIVEC,based on above condition.
	 */ /**
		 * Enable IsR5IvtBackup,this will used in
		 * XFsbl_PartitionLoad for restoring R5 vectors
		 */ /**
		 * Get the length of the IVT area to be
		 * skipped from Load Address
		 */ /**
		 * Check if Length is less than SkipLength
		 */ /*Store HIVEC 32 bytes data to R5HivecBuffer*/ /* Update the High Vector locations for R5.*/ /**
		 * Make sure that Low Vector locations are written Properly
		 * Flush the cache
		 */ /*set exception vector to HIVEC */ /* Trigger IPI only for first PMUFW partition */ /* Enable PMU_0 IPI */ /* Trigger PMU0 IPI in PMU IPI TRIG Reg */ /**
		 * Wait until PMU Microblaze goes to sleep state,
		 * before starting firmware download to PMU RAM
		 */ /**
	 * Copy the partition to PS_DDR/PL_DDR/TCM
	 */