AzureMXChip/MXCHIPAZ3166/core/lib/threadx/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c
void enableNonSecureCPUInterface(void)
{
  unsigned int tmp;

  tmp = gic_cpu->GICC_CTLR;
  tmp = tmp | 0x2;          // Set bit 1
  gic_cpu->GICC_CTLR = tmp;
}
// Enables the group 1 (non-secure) CPU interface
// This function can only be called from the Secure world
// Must been done one each core seperately
Enables the group 1 (non-secure) CPU interface
This function can only be called from the Secure world
Must been done one each core seperately
Enables the group 1 ( non - secure ) CPU interface This function can only be called from the Secure world Must been done one each core seperately
void enableNonSecureCPUInterface(void)
{
  unsigned int tmp;
  tmp = gic_cpu->GICC_CTLR;
  tmp = tmp | 0x2;          
  gic_cpu->GICC_CTLR = tmp;
}
void enableNonSecureCPUInterface ( void ) { unsigned int tmp ; tmp = gic_cpu -> GICC_CTLR ; tmp = tmp | 0x2 ; gic_cpu -> GICC_CTLR = tmp ; }
Enables the group 1 (non-secure) CPU interface
This function can only be called from the Secure world
Must been done one each core seperately
Enables the group 1 ( non - secure ) CPU interface This function can only be called from the Secure world Must been done one each core seperately
// Set bit 1