XilinxProcessorIPLib/drivers/axiethernet/examples/xaxiethernet_example_intr_mcdma.c
int AxiEthernetSgDmaIntrExample(INTC *IntcInstancePtr,
				XAxiEthernet *AxiEthernetInstancePtr,
				XMcdma *DmaInstancePtr,
				u16 AxiEthernetDeviceId,
				u16 AxiMcDmaDeviceId,
				u16 AxiEthernetIntrId)
{
	int Status;
	int LoopbackSpeed;
	XAxiEthernet_Config *MacCfgPtr;
	XMcdma_Config* DmaConfig;
	u8 ChanId;

	/*************************************/
	/* Setup device for first-time usage */
	/*************************************/

	/*
	 *  Get the configuration of AxiEthernet hardware.
	 */
	MacCfgPtr = XAxiEthernet_LookupConfig(AxiEthernetDeviceId);

	/*
	 * Check whether MCDMA is present or not
	 */
	if(MacCfgPtr->AxiDevType != XPAR_AXI_MCDMA) {
		AxiEthernetUtilErrorTrap
			("Device HW not configured for MCDMA mode\r\n");
		return XST_FAILURE;
	}

	DmaConfig = XMcdma_LookupConfig(AxiMcDmaDeviceId);

	/*
	 * Initialize AXIMCDMA engine. AXIMCDMA engine must be initialized before
	 * AxiEthernet. During AXIMCDMA engine initialization, AXIMCDMA hardware is
	 * reset, and since AXIMCDMA reset line is connected to AxiEthernet, this
	 * would ensure a reset of AxiEthernet.
	 */
	Status = XMcDma_CfgInitialize(DmaInstancePtr, DmaConfig);
	if(Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error initializing DMA\r\n");
		return XST_FAILURE;
	}

	xil_printf("DMA init success\n\r");

	/*
	 * Initialize AxiEthernet hardware.
	 */
	Status = XAxiEthernet_CfgInitialize(AxiEthernetInstancePtr, MacCfgPtr,
					MacCfgPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error in initialize");
		return XST_FAILURE;
	}

	xil_printf("Cfg init success\n\r");
	if (MacCfgPtr->Enable_1588)
		Padding = 8;

#if defined(__aarch64__)
	Xil_SetTlbAttributes((UINTPTR)TxBdSpace, NORM_NONCACHE | INNER_SHAREABLE);
	Xil_SetTlbAttributes((UINTPTR)TxBdSpace + BLOCK_SIZE_2MB, NORM_NONCACHE | INNER_SHAREABLE);
	Xil_SetTlbAttributes((UINTPTR)RxBdSpace, NORM_NONCACHE | INNER_SHAREABLE);
	Xil_SetTlbAttributes((UINTPTR)RxBdSpace + BLOCK_SIZE_2MB, NORM_NONCACHE | INNER_SHAREABLE);
#endif

	RxBdSetup(DmaInstancePtr, AxiEthernetInstancePtr, MacCfgPtr, AxiEthernetIntrId);
	TxBdSetup(DmaInstancePtr, AxiEthernetInstancePtr, MacCfgPtr, AxiEthernetIntrId);

	/*
	 * Set PHY to loopback, speed depends on phy type.
	 * MII is 100 and all others are 1000.
	 */
	if (XAxiEthernet_GetPhysicalInterface(AxiEthernetInstancePtr) ==
	                                      XAE_PHY_TYPE_MII) {
	        LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED;
	} else if (MacCfgPtr->Speed == 2500){
	        LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED_2p5G;
	} else {
	        LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED_1G;
	}
	/*
	 * Uncomment Below line of code if user would like to test
	 * External loopback
	 */
	/* ExternalLoopback = 1; */
	AxiEthernetUtilEnterLoopback(AxiEthernetInstancePtr, LoopbackSpeed);
	/*
	 * Set PHY<-->MAC data clock
	 */
	Status =  XAxiEthernet_SetOperatingSpeed(AxiEthernetInstancePtr,
	               (u16)LoopbackSpeed);
	if (Status != XST_SUCCESS) {
	        return XST_FAILURE;
	}

	/*
	 * Setting the operating speed of the MAC needs a delay.  There
	 * doesn't seem to be register to poll, so please consider this
	 * during your application design.
	 */
	 AxiEthernetUtilPhyDelay(2);


	/****************************/
	/* Run through the examples */
	/****************************/

	 for (ChanId = 1 ; ChanId <= AxiEthernetInstancePtr->Config.AxiMcDmaChan_Cnt; ChanId++) {
		/*
		 * Run the AxiEthernet DMA Single Frame Interrupt example
		 */
		Status = AxiEthernetSgDmaIntrSingleFrameExample(AxiEthernetInstancePtr,
							  DmaInstancePtr, ChanId);
		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}


		/*
		 * Tx/Rx Partial checksum offload will be disabled when any of
		 * Tx/Rx VLAN features are built in hardware.
		 */
		if (XAxiEthernet_IsRxPartialCsum(AxiEthernetInstancePtr) &&
			XAxiEthernet_IsTxPartialCsum(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsTxVlanTran(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsTxVlanStrp(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsTxVlanTag(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsRxVlanTran(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsRxVlanStrp(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsRxVlanTag(AxiEthernetInstancePtr))  {
			Hascsum = 1;
			Status = AxiEthernetSgDmaPartialChecksumOffloadExample(AxiEthernetInstancePtr,
									DmaInstancePtr, ChanId);

			if (Status != XST_SUCCESS) {
				return XST_FAILURE;
			}
			Hascsum = 0;
		}


		/*
		 * Tx/Rx Full checksum offload will be disabled when any of
		 * Tx/Rx VLAN features are built in hardware.
		 */
		if (XAxiEthernet_IsRxFullCsum(AxiEthernetInstancePtr) &&
			XAxiEthernet_IsTxFullCsum(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsTxVlanTran(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsTxVlanStrp(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsTxVlanTag(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsRxVlanTran(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsRxVlanStrp(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsRxVlanTag(AxiEthernetInstancePtr))  {
			Hascsum = 1;
			Status = AxiEthernetSgDmaFullChecksumOffloadExample
			(AxiEthernetInstancePtr,DmaInstancePtr, ChanId);

			if (Status != XST_SUCCESS) {
				return XST_FAILURE;
			}
			Hascsum = 0;
		}

		/*
		 * Run the AxiEthernet DMA Multi Frame/Random length Interrupt example
		 */
		Status = AxiEthernetSgDmaIntrMultiFrameExample(AxiEthernetInstancePtr,
								DmaInstancePtr, ChanId);
		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}

		xil_printf("Channel id %d tests passed\n\r", ChanId);
	}

	/*
	 * Stop the device
	 */
	XAxiEthernet_Stop(AxiEthernetInstancePtr);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function demonstrates the usage usage of the Axi Ethernet by sending
* and receiving frames in interrupt driven MCDMA mode.
*
*
* @param	IntcInstancePtr is a pointer to the instance of the Intc
*		component.
* @param	AxiEthernetInstancePtr is a pointer to the instance of the
*		AxiEthernet component.
* @param	DmaInstancePtr is a pointer to the instance of the AXI MCDMA
*		component.
* @param	AxiEthernetDeviceId is Device ID of the Axi Ethernet Device ,
*		typically XPAR_<AXIETHERNET_instance>_DEVICE_ID value from
*		xparameters.h.
* @param	AxiMcDmaDeviceId is Device ID of the Axi DMAA Device ,
*		typically XPAR_<AXIMCDMA_instance>_DEVICE_ID value from
*		xparameters.h.
* @param	AxiEthernetIntrId is the Interrupt ID and is typically
*		XPAR_<INTC_instance>_<AXIETHERNET_instance>_VEC_ID
*		value from xparameters.h.
*
* @return	-XST_SUCCESS to indicate success
*		-XST_FAILURE to indicate failure
*
* @note		AxiMcdma hardware must be initialized before initializing
*		AxiEthernet. Since AxiMcdma reset line is connected to the
*		AxiEthernet reset line, a reset of AxiMcdma hardware during its
*		initialization would reset AxiEthernet.
*
******************************************************************************/
This function demonstrates the usage usage of the Axi Ethernet by sending
and receiving frames in interrupt driven MCDMA mode.
This function demonstrates the usage usage of the Axi Ethernet by sending and receiving frames in interrupt driven MCDMA mode .
int AxiEthernetSgDmaIntrExample(INTC *IntcInstancePtr,
				XAxiEthernet *AxiEthernetInstancePtr,
				XMcdma *DmaInstancePtr,
				u16 AxiEthernetDeviceId,
				u16 AxiMcDmaDeviceId,
				u16 AxiEthernetIntrId)
{
	int Status;
	int LoopbackSpeed;
	XAxiEthernet_Config *MacCfgPtr;
	XMcdma_Config* DmaConfig;
	u8 ChanId;
	MacCfgPtr = XAxiEthernet_LookupConfig(AxiEthernetDeviceId);
	if(MacCfgPtr->AxiDevType != XPAR_AXI_MCDMA) {
		AxiEthernetUtilErrorTrap
			("Device HW not configured for MCDMA mode\r\n");
		return XST_FAILURE;
	}
	DmaConfig = XMcdma_LookupConfig(AxiMcDmaDeviceId);
	Status = XMcDma_CfgInitialize(DmaInstancePtr, DmaConfig);
	if(Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error initializing DMA\r\n");
		return XST_FAILURE;
	}
	xil_printf("DMA init success\n\r");
	Status = XAxiEthernet_CfgInitialize(AxiEthernetInstancePtr, MacCfgPtr,
					MacCfgPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error in initialize");
		return XST_FAILURE;
	}
	xil_printf("Cfg init success\n\r");
	if (MacCfgPtr->Enable_1588)
		Padding = 8;
#if defined(__aarch64__)
	Xil_SetTlbAttributes((UINTPTR)TxBdSpace, NORM_NONCACHE | INNER_SHAREABLE);
	Xil_SetTlbAttributes((UINTPTR)TxBdSpace + BLOCK_SIZE_2MB, NORM_NONCACHE | INNER_SHAREABLE);
	Xil_SetTlbAttributes((UINTPTR)RxBdSpace, NORM_NONCACHE | INNER_SHAREABLE);
	Xil_SetTlbAttributes((UINTPTR)RxBdSpace + BLOCK_SIZE_2MB, NORM_NONCACHE | INNER_SHAREABLE);
#endif
	RxBdSetup(DmaInstancePtr, AxiEthernetInstancePtr, MacCfgPtr, AxiEthernetIntrId);
	TxBdSetup(DmaInstancePtr, AxiEthernetInstancePtr, MacCfgPtr, AxiEthernetIntrId);
	if (XAxiEthernet_GetPhysicalInterface(AxiEthernetInstancePtr) ==
	                                      XAE_PHY_TYPE_MII) {
	        LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED;
	} else if (MacCfgPtr->Speed == 2500){
	        LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED_2p5G;
	} else {
	        LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED_1G;
	}
	AxiEthernetUtilEnterLoopback(AxiEthernetInstancePtr, LoopbackSpeed);
	Status =  XAxiEthernet_SetOperatingSpeed(AxiEthernetInstancePtr,
	               (u16)LoopbackSpeed);
	if (Status != XST_SUCCESS) {
	        return XST_FAILURE;
	}
	 AxiEthernetUtilPhyDelay(2);
	 for (ChanId = 1 ; ChanId <= AxiEthernetInstancePtr->Config.AxiMcDmaChan_Cnt; ChanId++) {
		Status = AxiEthernetSgDmaIntrSingleFrameExample(AxiEthernetInstancePtr,
							  DmaInstancePtr, ChanId);
		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}
		if (XAxiEthernet_IsRxPartialCsum(AxiEthernetInstancePtr) &&
			XAxiEthernet_IsTxPartialCsum(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsTxVlanTran(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsTxVlanStrp(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsTxVlanTag(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsRxVlanTran(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsRxVlanStrp(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsRxVlanTag(AxiEthernetInstancePtr))  {
			Hascsum = 1;
			Status = AxiEthernetSgDmaPartialChecksumOffloadExample(AxiEthernetInstancePtr,
									DmaInstancePtr, ChanId);
			if (Status != XST_SUCCESS) {
				return XST_FAILURE;
			}
			Hascsum = 0;
		}
		if (XAxiEthernet_IsRxFullCsum(AxiEthernetInstancePtr) &&
			XAxiEthernet_IsTxFullCsum(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsTxVlanTran(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsTxVlanStrp(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsTxVlanTag(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsRxVlanTran(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsRxVlanStrp(AxiEthernetInstancePtr) &&
			!XAxiEthernet_IsRxVlanTag(AxiEthernetInstancePtr))  {
			Hascsum = 1;
			Status = AxiEthernetSgDmaFullChecksumOffloadExample
			(AxiEthernetInstancePtr,DmaInstancePtr, ChanId);
			if (Status != XST_SUCCESS) {
				return XST_FAILURE;
			}
			Hascsum = 0;
		}
		Status = AxiEthernetSgDmaIntrMultiFrameExample(AxiEthernetInstancePtr,
								DmaInstancePtr, ChanId);
		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}
		xil_printf("Channel id %d tests passed\n\r", ChanId);
	}
	XAxiEthernet_Stop(AxiEthernetInstancePtr);
	return XST_SUCCESS;
}
int AxiEthernetSgDmaIntrExample ( INTC * IntcInstancePtr , XAxiEthernet * AxiEthernetInstancePtr , XMcdma * DmaInstancePtr , u16 AxiEthernetDeviceId , u16 AxiMcDmaDeviceId , u16 AxiEthernetIntrId ) { int Status ; int LoopbackSpeed ; XAxiEthernet_Config * MacCfgPtr ; XMcdma_Config * DmaConfig ; u8 ChanId ; MacCfgPtr = XAxiEthernet_LookupConfig ( AxiEthernetDeviceId ) ; if ( MacCfgPtr -> AxiDevType != XPAR_AXI_MCDMA ) { AxiEthernetUtilErrorTrap ( " \r \n " ) ; return XST_FAILURE ; } DmaConfig = XMcdma_LookupConfig ( AxiMcDmaDeviceId ) ; Status = XMcDma_CfgInitialize ( DmaInstancePtr , DmaConfig ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " \r \n " ) ; return XST_FAILURE ; } xil_printf ( " \n \r " ) ; Status = XAxiEthernet_CfgInitialize ( AxiEthernetInstancePtr , MacCfgPtr , MacCfgPtr -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } xil_printf ( " \n \r " ) ; if ( MacCfgPtr -> Enable_1588 ) Padding = 8 ; #if defined ( __aarch64__ ) Xil_SetTlbAttributes ( ( UINTPTR ) TxBdSpace , NORM_NONCACHE | INNER_SHAREABLE ) ; Xil_SetTlbAttributes ( ( UINTPTR ) TxBdSpace + BLOCK_SIZE_2MB , NORM_NONCACHE | INNER_SHAREABLE ) ; Xil_SetTlbAttributes ( ( UINTPTR ) RxBdSpace , NORM_NONCACHE | INNER_SHAREABLE ) ; Xil_SetTlbAttributes ( ( UINTPTR ) RxBdSpace + BLOCK_SIZE_2MB , NORM_NONCACHE | INNER_SHAREABLE ) ; #endif RxBdSetup ( DmaInstancePtr , AxiEthernetInstancePtr , MacCfgPtr , AxiEthernetIntrId ) ; TxBdSetup ( DmaInstancePtr , AxiEthernetInstancePtr , MacCfgPtr , AxiEthernetIntrId ) ; if ( XAxiEthernet_GetPhysicalInterface ( AxiEthernetInstancePtr ) == XAE_PHY_TYPE_MII ) { LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED ; } else if ( MacCfgPtr -> Speed == 2500 ) { LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED_2p5G ; } else { LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED_1G ; } AxiEthernetUtilEnterLoopback ( AxiEthernetInstancePtr , LoopbackSpeed ) ; Status = XAxiEthernet_SetOperatingSpeed ( AxiEthernetInstancePtr , ( u16 ) LoopbackSpeed ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } AxiEthernetUtilPhyDelay ( 2 ) ; for ( ChanId = 1 ; ChanId <= AxiEthernetInstancePtr -> Config . AxiMcDmaChan_Cnt ; ChanId ++ ) { Status = AxiEthernetSgDmaIntrSingleFrameExample ( AxiEthernetInstancePtr , DmaInstancePtr , ChanId ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } if ( XAxiEthernet_IsRxPartialCsum ( AxiEthernetInstancePtr ) && XAxiEthernet_IsTxPartialCsum ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsTxVlanTran ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsTxVlanStrp ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsTxVlanTag ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsRxVlanTran ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsRxVlanStrp ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsRxVlanTag ( AxiEthernetInstancePtr ) ) { Hascsum = 1 ; Status = AxiEthernetSgDmaPartialChecksumOffloadExample ( AxiEthernetInstancePtr , DmaInstancePtr , ChanId ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } Hascsum = 0 ; } if ( XAxiEthernet_IsRxFullCsum ( AxiEthernetInstancePtr ) && XAxiEthernet_IsTxFullCsum ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsTxVlanTran ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsTxVlanStrp ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsTxVlanTag ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsRxVlanTran ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsRxVlanStrp ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsRxVlanTag ( AxiEthernetInstancePtr ) ) { Hascsum = 1 ; Status = AxiEthernetSgDmaFullChecksumOffloadExample ( AxiEthernetInstancePtr , DmaInstancePtr , ChanId ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } Hascsum = 0 ; } Status = AxiEthernetSgDmaIntrMultiFrameExample ( AxiEthernetInstancePtr , DmaInstancePtr , ChanId ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } xil_printf ( " \n \r " , ChanId ) ; } XAxiEthernet_Stop ( AxiEthernetInstancePtr ) ; return XST_SUCCESS ; }
This function demonstrates the usage usage of the Axi Ethernet by sending
and receiving frames in interrupt driven MCDMA mode.
This function demonstrates the usage usage of the Axi Ethernet by sending and receiving frames in interrupt driven MCDMA mode .
/*************************************/ /* Setup device for first-time usage */ /*************************************/ /*
	 *  Get the configuration of AxiEthernet hardware.
	 */ /*
	 * Check whether MCDMA is present or not
	 */ /*
	 * Initialize AXIMCDMA engine. AXIMCDMA engine must be initialized before
	 * AxiEthernet. During AXIMCDMA engine initialization, AXIMCDMA hardware is
	 * reset, and since AXIMCDMA reset line is connected to AxiEthernet, this
	 * would ensure a reset of AxiEthernet.
	 */ /*
	 * Initialize AxiEthernet hardware.
	 */ /*
	 * Set PHY to loopback, speed depends on phy type.
	 * MII is 100 and all others are 1000.
	 */ /*
	 * Uncomment Below line of code if user would like to test
	 * External loopback
	 */ /* ExternalLoopback = 1; */ /*
	 * Set PHY<-->MAC data clock
	 */ /*
	 * Setting the operating speed of the MAC needs a delay.  There
	 * doesn't seem to be register to poll, so please consider this
	 * during your application design.
	 */ /****************************/ /* Run through the examples */ /****************************/ /*
		 * Run the AxiEthernet DMA Single Frame Interrupt example
		 */ /*
		 * Tx/Rx Partial checksum offload will be disabled when any of
		 * Tx/Rx VLAN features are built in hardware.
		 */ /*
		 * Tx/Rx Full checksum offload will be disabled when any of
		 * Tx/Rx VLAN features are built in hardware.
		 */ /*
		 * Run the AxiEthernet DMA Multi Frame/Random length Interrupt example
		 */ /*
	 * Stop the device
	 */