XilinxProcessorIPLib/drivers/iic/src/xiic_multi_master.c
static void BusNotBusyHandler(XIic *InstancePtr)
{
	u32 Status;
	u32 CntlReg;

	/*
	 * Should the slave receive have disabled acknowledgement,
	 * enable to allow acknowledgment of the sending of our address to
	 * again be addressed as slave.
	 */
	CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
	XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
		 (CntlReg & ~XIIC_CR_NO_ACK_MASK));

	/*
	 * Flush Tx FIFO by toggling TxFIFOResetBit. FIFO runs normally at 0
	 * Do this in case needed to Tx FIFO with more than expected if what
	 * was set to Tx was less than what the Master expected - read more
	 * from this slave so FIFO had junk in it.
	 */
	XIic_FlushTxFifo(InstancePtr);

	/*
	 * Flush Rx FIFO should slave Rx had a problem, sent No ack but
	 * still received a few bytes. Should the slave receive have disabled
	 * acknowledgement, clear Rx FIFO.
	 */
	XIic_FlushRxFifo(InstancePtr);

	/*
	 * Send Application messaging status via callbacks. Disable either Tx or
	 * Receive interrupt. Which callback depends on messaging direction.
	 */
	Status = XIic_ReadIier(InstancePtr->BaseAddress);
	if (InstancePtr->RecvBufferPtr == NULL) {
		/*
		 * Slave was sending data (master was reading), disable
		 * all the transmit interrupts.
		 */
		XIic_WriteIier(InstancePtr->BaseAddress,
				(Status & ~XIIC_TX_INTERRUPTS));
	}
	else {
		/*
		 * Slave was receiving data (master was writing) disable receive
		 * interrupts.
		 */
		XIic_WriteIier(InstancePtr->BaseAddress,
				(Status & ~XIIC_INTR_RX_FULL_MASK));
	}

	/*
	 * Send Status in StatusHandler callback.
	 */
	InstancePtr->StatusHandler(InstancePtr->StatusCallBackRef,
				   XII_BUS_NOT_BUSY_EVENT);
}
/*****************************************************************************/
/**
*
* The IIC bus busy signals when a master has control of the bus. Until the bus
* is released, i.e. not busy, other devices must wait to use it.
*
* When this interrupt occurs, it signals that the previous master has released
* the bus for another user.
*
* This interrupt is only enabled when the master Tx is waiting for the bus.
*
* This interrupt causes the following tasks:
* - Disable Bus not busy interrupt
* - Enable bus Ack
*	 Should the slave receive have disabled acknowledgement, enable to allow
*	 acknowledgment of the sending of our address to again be addressed as
*	 slave
* - Flush Rx FIFO
*	 Should the slave receive have disabled acknowledgement, a few bytes may
*	 be in FIFO if Rx full did not occur because of not enough byte in FIFO
*	 to have caused an interrupt.
* - Send status to user via status callback with the value:
*	XII_BUS_NOT_BUSY_EVENT
*
* @param	InstancePtr is a pointer to the XIic instance to be worked on.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
The IIC bus busy signals when a master has control of the bus. Until the bus
is released, i.e. not busy, other devices must wait to use it.

When this interrupt occurs, it signals that the previous master has released
the bus for another user.

This interrupt is only enabled when the master Tx is waiting for the bus.

This interrupt causes the following tasks:
Disable Bus not busy interrupt
Enable bus Ack
Should the slave receive have disabled acknowledgement, enable to allow
acknowledgment of the sending of our address to again be addressed as
slave
Flush Rx FIFO
Should the slave receive have disabled acknowledgement, a few bytes may
be in FIFO if Rx full did not occur because of not enough byte in FIFO
to have caused an interrupt.
Send status to user via status callback with the value:
XII_BUS_NOT_BUSY_EVENT
The IIC bus busy signals when a master has control of the bus . Until the bus is released i . e . not busy other devices must wait to use it . When this interrupt occurs it signals that the previous master has released the bus for another user . This interrupt is only enabled when the master Tx is waiting for the bus . This interrupt causes the following tasks : Disable Bus not busy interrupt Enable bus Ack Should the slave receive have disabled acknowledgement enable to allow acknowledgment of the sending of our address to again be addressed as slave Flush Rx FIFO Should the slave receive have disabled acknowledgement a few bytes may be in FIFO if Rx full did not occur because of not enough byte in FIFO to have caused an interrupt . Send status to user via status callback with the value : XII_BUS_NOT_BUSY_EVENT
static void BusNotBusyHandler(XIic *InstancePtr)
{
	u32 Status;
	u32 CntlReg;
	CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
	XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET,
		 (CntlReg & ~XIIC_CR_NO_ACK_MASK));
	XIic_FlushTxFifo(InstancePtr);
	XIic_FlushRxFifo(InstancePtr);
	Status = XIic_ReadIier(InstancePtr->BaseAddress);
	if (InstancePtr->RecvBufferPtr == NULL) {
		XIic_WriteIier(InstancePtr->BaseAddress,
				(Status & ~XIIC_TX_INTERRUPTS));
	}
	else {
		XIic_WriteIier(InstancePtr->BaseAddress,
				(Status & ~XIIC_INTR_RX_FULL_MASK));
	}
	InstancePtr->StatusHandler(InstancePtr->StatusCallBackRef,
				   XII_BUS_NOT_BUSY_EVENT);
}
static void BusNotBusyHandler ( XIic * InstancePtr ) { u32 Status ; u32 CntlReg ; CntlReg = XIic_ReadReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET ) ; XIic_WriteReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET , ( CntlReg & ~ XIIC_CR_NO_ACK_MASK ) ) ; XIic_FlushTxFifo ( InstancePtr ) ; XIic_FlushRxFifo ( InstancePtr ) ; Status = XIic_ReadIier ( InstancePtr -> BaseAddress ) ; if ( InstancePtr -> RecvBufferPtr == NULL ) { XIic_WriteIier ( InstancePtr -> BaseAddress , ( Status & ~ XIIC_TX_INTERRUPTS ) ) ; } else { XIic_WriteIier ( InstancePtr -> BaseAddress , ( Status & ~ XIIC_INTR_RX_FULL_MASK ) ) ; } InstancePtr -> StatusHandler ( InstancePtr -> StatusCallBackRef , XII_BUS_NOT_BUSY_EVENT ) ; }
The IIC bus busy signals when a master has control of the bus.
The IIC bus busy signals when a master has control of the bus .
/*
	 * Should the slave receive have disabled acknowledgement,
	 * enable to allow acknowledgment of the sending of our address to
	 * again be addressed as slave.
	 */ /*
	 * Flush Tx FIFO by toggling TxFIFOResetBit. FIFO runs normally at 0
	 * Do this in case needed to Tx FIFO with more than expected if what
	 * was set to Tx was less than what the Master expected - read more
	 * from this slave so FIFO had junk in it.
	 */ /*
	 * Flush Rx FIFO should slave Rx had a problem, sent No ack but
	 * still received a few bytes. Should the slave receive have disabled
	 * acknowledgement, clear Rx FIFO.
	 */ /*
	 * Send Application messaging status via callbacks. Disable either Tx or
	 * Receive interrupt. Which callback depends on messaging direction.
	 */ /*
		 * Slave was sending data (master was reading), disable
		 * all the transmit interrupts.
		 */ /*
		 * Slave was receiving data (master was writing) disable receive
		 * interrupts.
		 */ /*
	 * Send Status in StatusHandler callback.
	 */