src/dpdk/drivers/net/txgbe/base/txgbe_hw.c
s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
			  u32 enable_addr)
{
	u32 rar_low, rar_high;
	u32 rar_entries = hw->mac.num_rar_entries;

	DEBUGFUNC("txgbe_set_rar");

	/* Make sure we are using a valid rar index range */
	if (index >= rar_entries) {
		DEBUGOUT("RAR index %d is out of range.\n", index);
		return TXGBE_ERR_INVALID_ARGUMENT;
	}

	/* setup VMDq pool selection before this RAR gets enabled */
	hw->mac.set_vmdq(hw, index, vmdq);

	/*
	 * HW expects these in little endian so we reverse the byte
	 * order from network order (big endian) to little endian
	 */
	rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
		  TXGBE_ETHADDRL_AD1(addr[4]) |
		  TXGBE_ETHADDRL_AD2(addr[3]) |
		  TXGBE_ETHADDRL_AD3(addr[2]);
	/*
	 * Some parts put the VMDq setting in the extra RAH bits,
	 * so save everything except the lower 16 bits that hold part
	 * of the address and the address valid bit.
	 */
	rar_high = rd32(hw, TXGBE_ETHADDRH);
	rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
	rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
		     TXGBE_ETHADDRH_AD5(addr[0]));

	rar_high &= ~TXGBE_ETHADDRH_VLD;
	if (enable_addr != 0)
		rar_high |= TXGBE_ETHADDRH_VLD;

	wr32(hw, TXGBE_ETHADDRIDX, index);
	wr32(hw, TXGBE_ETHADDRL, rar_low);
	wr32(hw, TXGBE_ETHADDRH, rar_high);

	return 0;
}
/**
 *  txgbe_set_rar - Set Rx address register
 *  @hw: pointer to hardware structure
 *  @index: Receive address register to write
 *  @addr: Address to put into receive address register
 *  @vmdq: VMDq "set" or "pool" index
 *  @enable_addr: set flag that address is active
 *
 *  Puts an ethernet address into a receive address register.
 **/


Puts an ethernet address into a receive address register.
Puts an ethernet address into a receive address register .
s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
			  u32 enable_addr)
{
	u32 rar_low, rar_high;
	u32 rar_entries = hw->mac.num_rar_entries;
	DEBUGFUNC("txgbe_set_rar");
	if (index >= rar_entries) {
		DEBUGOUT("RAR index %d is out of range.\n", index);
		return TXGBE_ERR_INVALID_ARGUMENT;
	}
	hw->mac.set_vmdq(hw, index, vmdq);
	rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
		  TXGBE_ETHADDRL_AD1(addr[4]) |
		  TXGBE_ETHADDRL_AD2(addr[3]) |
		  TXGBE_ETHADDRL_AD3(addr[2]);
	rar_high = rd32(hw, TXGBE_ETHADDRH);
	rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
	rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
		     TXGBE_ETHADDRH_AD5(addr[0]));
	rar_high &= ~TXGBE_ETHADDRH_VLD;
	if (enable_addr != 0)
		rar_high |= TXGBE_ETHADDRH_VLD;
	wr32(hw, TXGBE_ETHADDRIDX, index);
	wr32(hw, TXGBE_ETHADDRL, rar_low);
	wr32(hw, TXGBE_ETHADDRH, rar_high);
	return 0;
}
s32 txgbe_set_rar ( struct txgbe_hw * hw , u32 index , u8 * addr , u32 vmdq , u32 enable_addr ) { u32 rar_low , rar_high ; u32 rar_entries = hw -> mac . num_rar_entries ; DEBUGFUNC ( " " ) ; if ( index >= rar_entries ) { DEBUGOUT ( " \n " , index ) ; return TXGBE_ERR_INVALID_ARGUMENT ; } hw -> mac . set_vmdq ( hw , index , vmdq ) ; rar_low = TXGBE_ETHADDRL_AD0 ( addr [ 5 ] ) | TXGBE_ETHADDRL_AD1 ( addr [ 4 ] ) | TXGBE_ETHADDRL_AD2 ( addr [ 3 ] ) | TXGBE_ETHADDRL_AD3 ( addr [ 2 ] ) ; rar_high = rd32 ( hw , TXGBE_ETHADDRH ) ; rar_high &= ~ TXGBE_ETHADDRH_AD_MASK ; rar_high |= ( TXGBE_ETHADDRH_AD4 ( addr [ 1 ] ) | TXGBE_ETHADDRH_AD5 ( addr [ 0 ] ) ) ; rar_high &= ~ TXGBE_ETHADDRH_VLD ; if ( enable_addr != 0 ) rar_high |= TXGBE_ETHADDRH_VLD ; wr32 ( hw , TXGBE_ETHADDRIDX , index ) ; wr32 ( hw , TXGBE_ETHADDRL , rar_low ) ; wr32 ( hw , TXGBE_ETHADDRH , rar_high ) ; return 0 ; }
txgbe_set_rar - Set Rx address register
  @hw: pointer to hardware structure
  @index: Receive address register to write
  @addr: Address to put into receive address register
  @vmdq: VMDq "set" or "pool" index
  @enable_addr: set flag that address is active
txgbe_set_rar - Set Rx address register @hw : pointer to hardware structure @index : Receive address register to write @addr : Address to put into receive address register @vmdq : VMDq " set " or " pool " index @enable_addr : set flag that address is active
/* Make sure we are using a valid rar index range */ /* setup VMDq pool selection before this RAR gets enabled */ /*
	 * HW expects these in little endian so we reverse the byte
	 * order from network order (big endian) to little endian
	 */ /*
	 * Some parts put the VMDq setting in the extra RAH bits,
	 * so save everything except the lower 16 bits that hold part
	 * of the address and the address valid bit.
	 */