XilinxProcessorIPLib/drivers/v_hdmitxss1/examples/xhdmi_example/si5324drv.c
int Si5324_SetClock(void *IicPtr, u8 IICAddress, u8 ClkSrc,
                    u32 ClkInFreq, u32 ClkOutFreq) {
    u32 NCn_ls, N2_ls, N3n;
    u8  N1_hs, N2_hs, BwSel;
    int result;
    u8  buf[14*2]; // Need to set 14 registers
    int i;

    // Sanity check
    if ((ClkSrc < SI5324_CLKSRC_CLK1) || (ClkSrc > SI5324_CLKSRC_XTAL)) {
        if (SI5324_DEBUG) {
            xil_printf("Si5324: ERROR: Incorrect input clock selected!\r\n");
        }
        return SI5324_ERR_PARM;
    }
    if (ClkSrc == SI5324_CLKSRC_CLK2) {
        if (SI5324_DEBUG) {
            xil_printf("Si5324: ERROR: Clock input 2 not supported!\r\n");
        }
        return SI5324_ERR_PARM;
    }
    if ((ClkInFreq < SI5324_FIN_MIN) || (ClkInFreq > SI5324_FIN_MAX)) {
        if (SI5324_DEBUG) {
            xil_printf("Si5324: ERROR: Input frequency out of range!\r\n");
        }
        return SI5324_ERR_PARM;
    }
    if ((ClkOutFreq < SI5324_FOUT_MIN) || (ClkOutFreq > SI5324_FOUT_MAX)) {
        if (SI5324_DEBUG) {
            xil_printf("Si5324: ERROR: Output frequency out of range!\r\n");
        }
        return SI5324_ERR_PARM;
    }

    // Calculate the frequency settings for the Si5324
    result = Si5324_CalcFreqSettings(ClkInFreq, ClkOutFreq,
                                     &N1_hs, &NCn_ls, &N2_hs, &N2_ls, &N3n,
                                     &BwSel);
    if (result != SI5324_SUCCESS) {
        if (SI5324_DEBUG) {
            xil_printf("Si5324: ERROR: Could not determine settings for requested frequency!\r\n");
        }
        return result;
    }

    /*
     * Set the clock settings
     */
    if (SI5324_DEBUG) {
        xil_printf("Si5324: Programming frequency settings.\r\n");
    }
    i = 0;

    // Free running mode or use a reference clock
    buf[i] = 0;
    if (ClkSrc == SI5324_CLKSRC_XTAL) {
        // Enable free running mode
        buf[i+1] = 0x54;
    } else {
        // Disable free running mode
        buf[i+1] = 0x14;
    }
    i += 2;

    // Loop bandwidth
    buf[i]   = 2;
    buf[i+1] = (BwSel << 4) | 0x02;
    i += 2;

    // Enable/Disable CLKIN1/2 based on Free Run Mode
    buf[i] = 11;
    if (ClkSrc == SI5324_CLKSRC_CLK1) {
        // Enable CKIN1 & Disable CKIN2
        buf[i+1] = 0x42;
    } else {
        // Disable CKIN1 & Enable CKIN2
        buf[i+1] = 0x41;
    }
    i += 2;

    // N1_HS
    buf[i]   = 25;
    buf[i+1] = N1_hs << 5;
    i += 2;

    // NC1_LS
    buf[i]   = 31;
    buf[i+1] = (u8)((NCn_ls & 0x000F0000) >> 16);
    buf[i+2] = 32;
    buf[i+3] = (u8)((NCn_ls & 0x0000FF00) >>  8);
    buf[i+4] = 33;
    buf[i+5] = (u8)( NCn_ls & 0x000000FF       );
    i += 6;

//    // NC2_LS
//    buf[i]   = 34;
//    buf[i+1] = (u8)((NCn_ls & 0x000F0000) >> 16);
//    buf[i+2] = 35;
//    buf[i+3] = (u8)((NCn_ls & 0x0000FF00) >>  8);
//    buf[i+4] = 36;
//    buf[i+5] = (u8)( NCn_ls & 0x000000FF       );
//    i += 6;

    // N2_HS and N2_LS
    buf[i]    = 40;
    buf[i+1]  = (N2_hs << 5);
    // N2_LS upper bits (same register as N2_HS)
    buf[i+1] |= (u8)((N2_ls & 0x000F0000) >> 16);
    buf[i+2]  = 41;
    buf[i+3]  = (u8)((N2_ls & 0x0000FF00) >>  8);
    buf[i+4]  = 42;
    buf[i+5]  = (u8)( N2_ls & 0x000000FF       );
    i += 6;

    // N3n
    if (ClkSrc == SI5324_CLKSRC_CLK1) {
        // N31
        buf[i]   = 43;
        buf[i+2] = 44;
        buf[i+4] = 45;
    } else {
        // N32
        buf[i]   = 46;
        buf[i+2] = 47;
        buf[i+4] = 48;
    }
    buf[i+1] = (u8)((N3n & 0x00070000) >> 16);
    buf[i+3] = (u8)((N3n & 0x0000FF00) >>  8);
    buf[i+5] = (u8)( N3n & 0x000000FF       );
    i += 6;

    // Start calibration
    buf[i]   = 136;
    buf[i+1] = 0x40;
    i += 2;

    // Sanity check
    if (i != sizeof(buf)) {
        if (SI5324_DEBUG) {
            xil_printf("Si5324: FATAL ERROR: Incorrect buffer size while programming frequency settings!\r\n");
        }
        exit(-1);
    }

    // Send all register settings to the Si5324
    result = Si5324_DoSettings(IicPtr, IICAddress,
                               buf, i / 2);
    return result;
}
/*****************************************************************************/
/**
 * Set the output frequency of the Si5324 clock generator.
 *
 * @param    IICBaseAddress contains the base address of the IIC master
 *           device.
 * @param    IICAddress contains the 7 bit IIC address of the Si5324 device.
 * @param    ClkSrc selects the clock input to use.
 * @param    ClkInFreq contains the frequency of the input clock (2kHz-710MHz).
 * @param    ClkOutFreq contains the desired output clock frequency
 *           (2kHz-945MHz).
 *
 * @return   SI5324_SUCCESS for success, SI5324_ERR_IIC for IIC access failure,
 *           SI5324_ERR_FREQ when the requested frequency cannot be generated,
 *           SI5324_ERR_PARM when the ClkSrc or ClkDest parameters are invalid
 *           or the ClkInFreq or ClkOutFreq are out of range.
 *****************************************************************************/
Set the output frequency of the Si5324 clock generator.
@param    IICBaseAddress contains the base address of the IIC master
device.
@param    IICAddress contains the 7 bit IIC address of the Si5324 device.
@param    ClkSrc selects the clock input to use.
@param    ClkInFreq contains the frequency of the input clock (2kHz-710MHz).
@param    ClkOutFreq contains the desired output clock frequency
(2kHz-945MHz).

@return   SI5324_SUCCESS for success, SI5324_ERR_IIC for IIC access failure,
SI5324_ERR_FREQ when the requested frequency cannot be generated,
SI5324_ERR_PARM when the ClkSrc or ClkDest parameters are invalid
or the ClkInFreq or ClkOutFreq are out of range.
Set the output frequency of the Si5324 clock generator . @param IICBaseAddress contains the base address of the IIC master device . @param IICAddress contains the 7 bit IIC address of the Si5324 device . @param ClkSrc selects the clock input to use . @param ClkInFreq contains the frequency of the input clock ( 2kHz - 710MHz ) . @param ClkOutFreq contains the desired output clock frequency ( 2kHz - 945MHz ) . @return SI5324_SUCCESS for success SI5324_ERR_IIC for IIC access failure SI5324_ERR_FREQ when the requested frequency cannot be generated SI5324_ERR_PARM when the ClkSrc or ClkDest parameters are invalid or the ClkInFreq or ClkOutFreq are out of range .
int Si5324_SetClock(void *IicPtr, u8 IICAddress, u8 ClkSrc,
                    u32 ClkInFreq, u32 ClkOutFreq) {
    u32 NCn_ls, N2_ls, N3n;
    u8  N1_hs, N2_hs, BwSel;
    int result;
    u8  buf[14*2]; 
    int i;
    if ((ClkSrc < SI5324_CLKSRC_CLK1) || (ClkSrc > SI5324_CLKSRC_XTAL)) {
        if (SI5324_DEBUG) {
            xil_printf("Si5324: ERROR: Incorrect input clock selected!\r\n");
        }
        return SI5324_ERR_PARM;
    }
    if (ClkSrc == SI5324_CLKSRC_CLK2) {
        if (SI5324_DEBUG) {
            xil_printf("Si5324: ERROR: Clock input 2 not supported!\r\n");
        }
        return SI5324_ERR_PARM;
    }
    if ((ClkInFreq < SI5324_FIN_MIN) || (ClkInFreq > SI5324_FIN_MAX)) {
        if (SI5324_DEBUG) {
            xil_printf("Si5324: ERROR: Input frequency out of range!\r\n");
        }
        return SI5324_ERR_PARM;
    }
    if ((ClkOutFreq < SI5324_FOUT_MIN) || (ClkOutFreq > SI5324_FOUT_MAX)) {
        if (SI5324_DEBUG) {
            xil_printf("Si5324: ERROR: Output frequency out of range!\r\n");
        }
        return SI5324_ERR_PARM;
    }
    result = Si5324_CalcFreqSettings(ClkInFreq, ClkOutFreq,
                                     &N1_hs, &NCn_ls, &N2_hs, &N2_ls, &N3n,
                                     &BwSel);
    if (result != SI5324_SUCCESS) {
        if (SI5324_DEBUG) {
            xil_printf("Si5324: ERROR: Could not determine settings for requested frequency!\r\n");
        }
        return result;
    }
    if (SI5324_DEBUG) {
        xil_printf("Si5324: Programming frequency settings.\r\n");
    }
    i = 0;
    buf[i] = 0;
    if (ClkSrc == SI5324_CLKSRC_XTAL) {
        buf[i+1] = 0x54;
    } else {
        buf[i+1] = 0x14;
    }
    i += 2;
    buf[i]   = 2;
    buf[i+1] = (BwSel << 4) | 0x02;
    i += 2;
    buf[i] = 11;
    if (ClkSrc == SI5324_CLKSRC_CLK1) {
        buf[i+1] = 0x42;
    } else {
        buf[i+1] = 0x41;
    }
    i += 2;
    buf[i]   = 25;
    buf[i+1] = N1_hs << 5;
    i += 2;
    buf[i]   = 31;
    buf[i+1] = (u8)((NCn_ls & 0x000F0000) >> 16);
    buf[i+2] = 32;
    buf[i+3] = (u8)((NCn_ls & 0x0000FF00) >>  8);
    buf[i+4] = 33;
    buf[i+5] = (u8)( NCn_ls & 0x000000FF       );
    i += 6;
    buf[i]    = 40;
    buf[i+1]  = (N2_hs << 5);
    buf[i+1] |= (u8)((N2_ls & 0x000F0000) >> 16);
    buf[i+2]  = 41;
    buf[i+3]  = (u8)((N2_ls & 0x0000FF00) >>  8);
    buf[i+4]  = 42;
    buf[i+5]  = (u8)( N2_ls & 0x000000FF       );
    i += 6;
    if (ClkSrc == SI5324_CLKSRC_CLK1) {
        buf[i]   = 43;
        buf[i+2] = 44;
        buf[i+4] = 45;
    } else {
        buf[i]   = 46;
        buf[i+2] = 47;
        buf[i+4] = 48;
    }
    buf[i+1] = (u8)((N3n & 0x00070000) >> 16);
    buf[i+3] = (u8)((N3n & 0x0000FF00) >>  8);
    buf[i+5] = (u8)( N3n & 0x000000FF       );
    i += 6;
    buf[i]   = 136;
    buf[i+1] = 0x40;
    i += 2;
    if (i != sizeof(buf)) {
        if (SI5324_DEBUG) {
            xil_printf("Si5324: FATAL ERROR: Incorrect buffer size while programming frequency settings!\r\n");
        }
        exit(-1);
    }
    result = Si5324_DoSettings(IicPtr, IICAddress,
                               buf, i / 2);
    return result;
}
int Si5324_SetClock ( void * IicPtr , u8 IICAddress , u8 ClkSrc , u32 ClkInFreq , u32 ClkOutFreq ) { u32 NCn_ls , N2_ls , N3n ; u8 N1_hs , N2_hs , BwSel ; int result ; u8 buf [ 14 * 2 ] ; int i ; if ( ( ClkSrc < SI5324_CLKSRC_CLK1 ) || ( ClkSrc > SI5324_CLKSRC_XTAL ) ) { if ( SI5324_DEBUG ) { xil_printf ( " \r \n " ) ; } return SI5324_ERR_PARM ; } if ( ClkSrc == SI5324_CLKSRC_CLK2 ) { if ( SI5324_DEBUG ) { xil_printf ( " \r \n " ) ; } return SI5324_ERR_PARM ; } if ( ( ClkInFreq < SI5324_FIN_MIN ) || ( ClkInFreq > SI5324_FIN_MAX ) ) { if ( SI5324_DEBUG ) { xil_printf ( " \r \n " ) ; } return SI5324_ERR_PARM ; } if ( ( ClkOutFreq < SI5324_FOUT_MIN ) || ( ClkOutFreq > SI5324_FOUT_MAX ) ) { if ( SI5324_DEBUG ) { xil_printf ( " \r \n " ) ; } return SI5324_ERR_PARM ; } result = Si5324_CalcFreqSettings ( ClkInFreq , ClkOutFreq , & N1_hs , & NCn_ls , & N2_hs , & N2_ls , & N3n , & BwSel ) ; if ( result != SI5324_SUCCESS ) { if ( SI5324_DEBUG ) { xil_printf ( " \r \n " ) ; } return result ; } if ( SI5324_DEBUG ) { xil_printf ( " \r \n " ) ; } i = 0 ; buf [ i ] = 0 ; if ( ClkSrc == SI5324_CLKSRC_XTAL ) { buf [ i + 1 ] = 0x54 ; } else { buf [ i + 1 ] = 0x14 ; } i += 2 ; buf [ i ] = 2 ; buf [ i + 1 ] = ( BwSel << 4 ) | 0x02 ; i += 2 ; buf [ i ] = 11 ; if ( ClkSrc == SI5324_CLKSRC_CLK1 ) { buf [ i + 1 ] = 0x42 ; } else { buf [ i + 1 ] = 0x41 ; } i += 2 ; buf [ i ] = 25 ; buf [ i + 1 ] = N1_hs << 5 ; i += 2 ; buf [ i ] = 31 ; buf [ i + 1 ] = ( u8 ) ( ( NCn_ls & 0x000F0000 ) >> 16 ) ; buf [ i + 2 ] = 32 ; buf [ i + 3 ] = ( u8 ) ( ( NCn_ls & 0x0000FF00 ) >> 8 ) ; buf [ i + 4 ] = 33 ; buf [ i + 5 ] = ( u8 ) ( NCn_ls & 0x000000FF ) ; i += 6 ; buf [ i ] = 40 ; buf [ i + 1 ] = ( N2_hs << 5 ) ; buf [ i + 1 ] |= ( u8 ) ( ( N2_ls & 0x000F0000 ) >> 16 ) ; buf [ i + 2 ] = 41 ; buf [ i + 3 ] = ( u8 ) ( ( N2_ls & 0x0000FF00 ) >> 8 ) ; buf [ i + 4 ] = 42 ; buf [ i + 5 ] = ( u8 ) ( N2_ls & 0x000000FF ) ; i += 6 ; if ( ClkSrc == SI5324_CLKSRC_CLK1 ) { buf [ i ] = 43 ; buf [ i + 2 ] = 44 ; buf [ i + 4 ] = 45 ; } else { buf [ i ] = 46 ; buf [ i + 2 ] = 47 ; buf [ i + 4 ] = 48 ; } buf [ i + 1 ] = ( u8 ) ( ( N3n & 0x00070000 ) >> 16 ) ; buf [ i + 3 ] = ( u8 ) ( ( N3n & 0x0000FF00 ) >> 8 ) ; buf [ i + 5 ] = ( u8 ) ( N3n & 0x000000FF ) ; i += 6 ; buf [ i ] = 136 ; buf [ i + 1 ] = 0x40 ; i += 2 ; if ( i != sizeof ( buf ) ) { if ( SI5324_DEBUG ) { xil_printf ( " \r \n " ) ; } exit ( -1 ) ; } result = Si5324_DoSettings ( IicPtr , IICAddress , buf , i / 2 ) ; return result ; }
Set the output frequency of the Si5324 clock generator.
Set the output frequency of the Si5324 clock generator .
// Need to set 14 registers // Sanity check // Calculate the frequency settings for the Si5324 /*
     * Set the clock settings
     */ // Free running mode or use a reference clock // Enable free running mode // Disable free running mode // Loop bandwidth // Enable/Disable CLKIN1/2 based on Free Run Mode // Enable CKIN1 & Disable CKIN2 // Disable CKIN1 & Enable CKIN2 // N1_HS // NC1_LS //    // NC2_LS //    buf[i]   = 34; //    buf[i+1] = (u8)((NCn_ls & 0x000F0000) >> 16); //    buf[i+2] = 35; //    buf[i+3] = (u8)((NCn_ls & 0x0000FF00) >>  8); //    buf[i+4] = 36; //    buf[i+5] = (u8)( NCn_ls & 0x000000FF       ); //    i += 6; // N2_HS and N2_LS // N2_LS upper bits (same register as N2_HS) // N3n // N31 // N32 // Start calibration // Sanity check // Send all register settings to the Si5324