emlib/src/em_cmu.c
void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq)
{
  uint32_t freqCal;
  uint32_t sysFreq;
  uint32_t prevFreq;

  /* Get DEVINFO index, set CMSIS frequency SystemHfrcoFreq */
  freqCal = CMU_HFRCODevinfoGet(setFreq);
  EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
  prevFreq = SystemHfrcoFreq;
  SystemHfrcoFreq = (uint32_t)setFreq;

  /* Set max wait-states while changing core clock */
  if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) {
    flashWaitStateMax();
  }

  /* Wait for any previous sync to complete, and then set calibration data
     for the selected frequency.  */
  while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT)) ;

  /* Check for valid calibration data */
  EFM_ASSERT(freqCal != UINT_MAX);

  /* Set divider in HFRCOCTRL for 1, 2 and 4MHz */
  switch (setFreq) {
    case cmuHFRCOFreq_1M0Hz:
      freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
                | CMU_HFRCOCTRL_CLKDIV_DIV4;
      break;

    case cmuHFRCOFreq_2M0Hz:
      freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
                | CMU_HFRCOCTRL_CLKDIV_DIV2;
      break;

    case cmuHFRCOFreq_4M0Hz:
      freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
                | CMU_HFRCOCTRL_CLKDIV_DIV1;
      break;

    default:
      break;
  }

  /* Update HFLE configuration before updating HFRCO.
     Use the new set frequency. */
  if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) {
    /* setFreq is worst-case as dividers may reduce the HFLE frequency. */
    setHfLeConfig(setFreq);
  }

  if (setFreq > prevFreq) {
#if defined(_EMU_CMD_EM01VSCALE0_MASK)
    /* When increasing frequency we need to voltage scale before the change */
    EMU_VScaleEM01ByClock(setFreq, true);
#endif
  }

  CMU->HFRCOCTRL = freqCal;

  /* If HFRCO is selected as HF clock, optimize flash access wait-state configuration
     for this frequency and update CMSIS core clock variable. */
  if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) {
    /* Call SystemCoreClockGet() to update CMSIS core clock variable. */
    sysFreq = SystemCoreClockGet();
    EFM_ASSERT(sysFreq <= (uint32_t)setFreq);
    EFM_ASSERT(sysFreq <= SystemHfrcoFreq);
    EFM_ASSERT(setFreq == SystemHfrcoFreq);
    CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT);
  }

  /* Reduce HFLE frequency if possible. */
  setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));

  if (setFreq <= prevFreq) {
#if defined(_EMU_CMD_EM01VSCALE0_MASK)
    /* When decreasing frequency we need to voltage scale after the change */
    EMU_VScaleEM01ByClock(0, true);
#endif
  }
}
/***************************************************************************/
/**
 * @brief
 *   Set HFRCO calibration for the selected target frequency.
 *
 * @param[in] setFreq
 *   HFRCO frequency to set
 ******************************************************************************/
@brief
Set HFRCO calibration for the selected target frequency.

@param[in] setFreq
HFRCO frequency to set
@brief Set HFRCO calibration for the selected target frequency . @param [ in ] setFreq HFRCO frequency to set
void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq)
{
  uint32_t freqCal;
  uint32_t sysFreq;
  uint32_t prevFreq;
  freqCal = CMU_HFRCODevinfoGet(setFreq);
  EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
  prevFreq = SystemHfrcoFreq;
  SystemHfrcoFreq = (uint32_t)setFreq;
  if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) {
    flashWaitStateMax();
  }
  while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT)) ;
  EFM_ASSERT(freqCal != UINT_MAX);
  switch (setFreq) {
    case cmuHFRCOFreq_1M0Hz:
      freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
                | CMU_HFRCOCTRL_CLKDIV_DIV4;
      break;
    case cmuHFRCOFreq_2M0Hz:
      freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
                | CMU_HFRCOCTRL_CLKDIV_DIV2;
      break;
    case cmuHFRCOFreq_4M0Hz:
      freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
                | CMU_HFRCOCTRL_CLKDIV_DIV1;
      break;
    default:
      break;
  }
  if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) {
    setHfLeConfig(setFreq);
  }
  if (setFreq > prevFreq) {
#if defined(_EMU_CMD_EM01VSCALE0_MASK)
    EMU_VScaleEM01ByClock(setFreq, true);
#endif
  }
  CMU->HFRCOCTRL = freqCal;
  if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) {
    sysFreq = SystemCoreClockGet();
    EFM_ASSERT(sysFreq <= (uint32_t)setFreq);
    EFM_ASSERT(sysFreq <= SystemHfrcoFreq);
    EFM_ASSERT(setFreq == SystemHfrcoFreq);
    CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT);
  }
  setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));
  if (setFreq <= prevFreq) {
#if defined(_EMU_CMD_EM01VSCALE0_MASK)
    EMU_VScaleEM01ByClock(0, true);
#endif
  }
}
void CMU_HFRCOBandSet ( CMU_HFRCOFreq_TypeDef setFreq ) { uint32_t freqCal ; uint32_t sysFreq ; uint32_t prevFreq ; freqCal = CMU_HFRCODevinfoGet ( setFreq ) ; EFM_ASSERT ( ( freqCal != 0 ) && ( freqCal != UINT_MAX ) ) ; prevFreq = SystemHfrcoFreq ; SystemHfrcoFreq = ( uint32_t ) setFreq ; if ( CMU_ClockSelectGet ( cmuClock_HF ) == cmuSelect_HFRCO ) { flashWaitStateMax ( ) ; } while ( BUS_RegBitRead ( & CMU -> SYNCBUSY , _CMU_SYNCBUSY_HFRCOBSY_SHIFT ) ) ; EFM_ASSERT ( freqCal != UINT_MAX ) ; switch ( setFreq ) { case cmuHFRCOFreq_1M0Hz : freqCal = ( freqCal & ~ _CMU_HFRCOCTRL_CLKDIV_MASK ) | CMU_HFRCOCTRL_CLKDIV_DIV4 ; break ; case cmuHFRCOFreq_2M0Hz : freqCal = ( freqCal & ~ _CMU_HFRCOCTRL_CLKDIV_MASK ) | CMU_HFRCOCTRL_CLKDIV_DIV2 ; break ; case cmuHFRCOFreq_4M0Hz : freqCal = ( freqCal & ~ _CMU_HFRCOCTRL_CLKDIV_MASK ) | CMU_HFRCOCTRL_CLKDIV_DIV1 ; break ; default : break ; } if ( CMU_ClockSelectGet ( cmuClock_HF ) == cmuSelect_HFRCO ) { setHfLeConfig ( setFreq ) ; } if ( setFreq > prevFreq ) { #if defined ( _EMU_CMD_EM01VSCALE0_MASK ) EMU_VScaleEM01ByClock ( setFreq , true ) ; #endif } CMU -> HFRCOCTRL = freqCal ; if ( CMU_ClockSelectGet ( cmuClock_HF ) == cmuSelect_HFRCO ) { sysFreq = SystemCoreClockGet ( ) ; EFM_ASSERT ( sysFreq <= ( uint32_t ) setFreq ) ; EFM_ASSERT ( sysFreq <= SystemHfrcoFreq ) ; EFM_ASSERT ( setFreq == SystemHfrcoFreq ) ; CMU_UpdateWaitStates ( sysFreq , VSCALE_DEFAULT ) ; } setHfLeConfig ( CMU_ClockFreqGet ( cmuClock_HFLE ) ) ; if ( setFreq <= prevFreq ) { #if defined ( _EMU_CMD_EM01VSCALE0_MASK ) EMU_VScaleEM01ByClock ( 0 , true ) ; #endif } }
@brief
   Set HFRCO calibration for the selected target frequency.
@brief Set HFRCO calibration for the selected target frequency .
/* Get DEVINFO index, set CMSIS frequency SystemHfrcoFreq */ /* Set max wait-states while changing core clock */ /* Wait for any previous sync to complete, and then set calibration data
     for the selected frequency.  */ /* Check for valid calibration data */ /* Set divider in HFRCOCTRL for 1, 2 and 4MHz */ /* Update HFLE configuration before updating HFRCO.
     Use the new set frequency. */ /* setFreq is worst-case as dividers may reduce the HFLE frequency. */ /* When increasing frequency we need to voltage scale before the change */ /* If HFRCO is selected as HF clock, optimize flash access wait-state configuration
     for this frequency and update CMSIS core clock variable. */ /* Call SystemCoreClockGet() to update CMSIS core clock variable. */ /* Reduce HFLE frequency if possible. */ /* When decreasing frequency we need to voltage scale after the change */