XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_gtye4.c
u32 XHdmiphy1_Gtye4TxPllRefClkDiv1Reconfig(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId)
{
    u16 DrpVal;
    u32 TxRefClkHz;
    u32 Status = XST_SUCCESS;
    XHdmiphy1_Channel *PllPtr = &InstancePtr->Quads[QuadId].
                    Plls[XHDMIPHY1_CH2IDX(ChId)];

    if (XHdmiphy1_IsHDMI(InstancePtr, XHDMIPHY1_DIR_TX)) {
        TxRefClkHz = InstancePtr->HdmiTxRefClkHz;
    }
    else {
        TxRefClkHz = XHdmiphy1_GetQuadRefClkFreq(InstancePtr, QuadId,
                                PllPtr->PllRefClkSel);
    }

    Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_007A,
                    &DrpVal);
    DrpVal &= ~(XDRP_GTYE4_CHN_REG_007A_TXCLK25_MASK);
    DrpVal |= XHdmiphy1_DrpEncodeClk25(TxRefClkHz) << 11;
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_007A,
                DrpVal);

    return Status;
}
/*****************************************************************************/
/**
* This function will configure the channel's TX CLKDIV1 settings.
*
* @param    InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param    QuadId is the GT quad ID to operate on.
* @param    ChId is the channel ID to operate on.
*
* @return
*       - XST_SUCCESS if the configuration was successful.
*       - XST_FAILURE otherwise.
*
* @note     None.
*
******************************************************************************/
This function will configure the channel's TX CLKDIV1 settings.
This function will configure the channel ' s TX CLKDIV1 settings .
u32 XHdmiphy1_Gtye4TxPllRefClkDiv1Reconfig(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId)
{
    u16 DrpVal;
    u32 TxRefClkHz;
    u32 Status = XST_SUCCESS;
    XHdmiphy1_Channel *PllPtr = &InstancePtr->Quads[QuadId].
                    Plls[XHDMIPHY1_CH2IDX(ChId)];
    if (XHdmiphy1_IsHDMI(InstancePtr, XHDMIPHY1_DIR_TX)) {
        TxRefClkHz = InstancePtr->HdmiTxRefClkHz;
    }
    else {
        TxRefClkHz = XHdmiphy1_GetQuadRefClkFreq(InstancePtr, QuadId,
                                PllPtr->PllRefClkSel);
    }
    Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_007A,
                    &DrpVal);
    DrpVal &= ~(XDRP_GTYE4_CHN_REG_007A_TXCLK25_MASK);
    DrpVal |= XHdmiphy1_DrpEncodeClk25(TxRefClkHz) << 11;
    Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_007A,
                DrpVal);
    return Status;
}
u32 XHdmiphy1_Gtye4TxPllRefClkDiv1Reconfig ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId ) { u16 DrpVal ; u32 TxRefClkHz ; u32 Status = XST_SUCCESS ; XHdmiphy1_Channel * PllPtr = & InstancePtr -> Quads [ QuadId ] . Plls [ XHDMIPHY1_CH2IDX ( ChId ) ] ; if ( XHdmiphy1_IsHDMI ( InstancePtr , XHDMIPHY1_DIR_TX ) ) { TxRefClkHz = InstancePtr -> HdmiTxRefClkHz ; } else { TxRefClkHz = XHdmiphy1_GetQuadRefClkFreq ( InstancePtr , QuadId , PllPtr -> PllRefClkSel ) ; } Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_007A , & DrpVal ) ; DrpVal &= ~ ( XDRP_GTYE4_CHN_REG_007A_TXCLK25_MASK ) ; DrpVal |= XHdmiphy1_DrpEncodeClk25 ( TxRefClkHz ) << 11 ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_007A , DrpVal ) ; return Status ; }
This function will configure the channel's TX CLKDIV1 settings.
This function will configure the channel ' s TX CLKDIV1 settings .