src/dpdk/drivers/net/bnx2x/bnx2x.c
int bnx2x_attach(struct bnx2x_softc *sc)
{
	int rc;

	PMD_DRV_LOG(DEBUG, sc, "Starting attach...");

	rc = bnx2x_pci_get_caps(sc);
	if (rc) {
		PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
		return rc;
	}

	sc->state = BNX2X_STATE_CLOSED;

	pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);

	sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;

	/* get PCI capabilites */
	bnx2x_probe_pci_caps(sc);

	if (sc->devinfo.pcie_msix_cap_reg != 0) {
		uint32_t val;
		pci_read(sc,
			 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
			 2);
		sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
	} else {
		sc->igu_sb_cnt = 1;
	}

	/* Init RTE stuff */
	bnx2x_init_rte(sc);

	if (IS_PF(sc)) {
		/* Enable internal target-read (in case we are probed after PF
		 * FLR). Must be done prior to any BAR read access. Only for
		 * 57712 and up
		 */
		if (!CHIP_IS_E1x(sc)) {
			REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
			       1);
			DELAY(200000);
		}

		/* get device info and set params */
		if (bnx2x_get_device_info(sc) != 0) {
			PMD_DRV_LOG(NOTICE, sc, "getting device info");
			return -ENXIO;
		}

/* get phy settings from shmem and 'and' against admin settings */
		bnx2x_get_phy_info(sc);
	} else {
		/* Left mac of VF unfilled, PF should set it for VF */
		memset(sc->link_params.mac_addr, 0, RTE_ETHER_ADDR_LEN);
	}

	sc->wol = 0;

	/* set the default MTU (changed via ifconfig) */
	sc->mtu = RTE_ETHER_MTU;

	bnx2x_set_modes_bitmap(sc);

	/* need to reset chip if UNDI was active */
	if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
/* init fw_seq */
		sc->fw_seq =
		    (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
		     DRV_MSG_SEQ_NUMBER_MASK);
		PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
			    sc->fw_seq);
		bnx2x_prev_unload(sc);
	}

	bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);

	/* calculate qm_cid_count */
	sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);

	sc->max_cos = 1;
	bnx2x_init_multi_cos(sc);

	return 0;
}
/*
* Device attach function.
*
* Allocates device resources, performs secondary chip identification, and
* initializes driver instance variables. This function is called from driver
* load after a successful probe.
*
* Returns:
*   0 = Success, >0 = Failure
*/
Device attach function.
Allocates device resources, performs secondary chip identification, and
initializes driver instance variables. This function is called from driver
load after a successful probe.

0 = Success, >0 = Failure
Device attach function . Allocates device resources performs secondary chip identification and initializes driver instance variables . This function is called from driver load after a successful probe . 0 = Success > 0 = Failure
int bnx2x_attach(struct bnx2x_softc *sc)
{
	int rc;
	PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
	rc = bnx2x_pci_get_caps(sc);
	if (rc) {
		PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
		return rc;
	}
	sc->state = BNX2X_STATE_CLOSED;
	pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
	sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
	bnx2x_probe_pci_caps(sc);
	if (sc->devinfo.pcie_msix_cap_reg != 0) {
		uint32_t val;
		pci_read(sc,
			 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
			 2);
		sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
	} else {
		sc->igu_sb_cnt = 1;
	}
	bnx2x_init_rte(sc);
	if (IS_PF(sc)) {
		if (!CHIP_IS_E1x(sc)) {
			REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
			       1);
			DELAY(200000);
		}
		if (bnx2x_get_device_info(sc) != 0) {
			PMD_DRV_LOG(NOTICE, sc, "getting device info");
			return -ENXIO;
		}
		bnx2x_get_phy_info(sc);
	} else {
		memset(sc->link_params.mac_addr, 0, RTE_ETHER_ADDR_LEN);
	}
	sc->wol = 0;
	sc->mtu = RTE_ETHER_MTU;
	bnx2x_set_modes_bitmap(sc);
	if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
		sc->fw_seq =
		    (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
		     DRV_MSG_SEQ_NUMBER_MASK);
		PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
			    sc->fw_seq);
		bnx2x_prev_unload(sc);
	}
	bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
	sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
	sc->max_cos = 1;
	bnx2x_init_multi_cos(sc);
	return 0;
}
int bnx2x_attach ( struct bnx2x_softc * sc ) { int rc ; PMD_DRV_LOG ( DEBUG , sc , " " ) ; rc = bnx2x_pci_get_caps ( sc ) ; if ( rc ) { PMD_DRV_LOG ( NOTICE , sc , " " ) ; return rc ; } sc -> state = BNX2X_STATE_CLOSED ; pci_write_long ( sc , PCICFG_GRC_ADDRESS , PCICFG_VENDOR_ID_OFFSET ) ; sc -> igu_base_addr = IS_VF ( sc ) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM ; bnx2x_probe_pci_caps ( sc ) ; if ( sc -> devinfo . pcie_msix_cap_reg != 0 ) { uint32_t val ; pci_read ( sc , ( sc -> devinfo . pcie_msix_cap_reg + PCIR_MSIX_CTRL ) , & val , 2 ) ; sc -> igu_sb_cnt = ( val & PCIM_MSIXCTRL_TABLE_SIZE ) + 1 ; } else { sc -> igu_sb_cnt = 1 ; } bnx2x_init_rte ( sc ) ; if ( IS_PF ( sc ) ) { if ( ! CHIP_IS_E1x ( sc ) ) { REG_WR ( sc , PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ , 1 ) ; DELAY ( 200000 ) ; } if ( bnx2x_get_device_info ( sc ) != 0 ) { PMD_DRV_LOG ( NOTICE , sc , " " ) ; return - ENXIO ; } bnx2x_get_phy_info ( sc ) ; } else { memset ( sc -> link_params . mac_addr , 0 , RTE_ETHER_ADDR_LEN ) ; } sc -> wol = 0 ; sc -> mtu = RTE_ETHER_MTU ; bnx2x_set_modes_bitmap ( sc ) ; if ( IS_PF ( sc ) && ! BNX2X_NOMCP ( sc ) ) { sc -> fw_seq = ( SHMEM_RD ( sc , func_mb [ SC_FW_MB_IDX ( sc ) ] . drv_mb_header ) & DRV_MSG_SEQ_NUMBER_MASK ) ; PMD_DRV_LOG ( DEBUG , sc , " " , sc -> fw_seq ) ; bnx2x_prev_unload ( sc ) ; } bnx2x_dcbx_set_state ( sc , FALSE , BNX2X_DCBX_ENABLED_OFF ) ; sc -> qm_cid_count = bnx2x_set_qm_cid_count ( sc ) ; sc -> max_cos = 1 ; bnx2x_init_multi_cos ( sc ) ; return 0 ; }
Device attach function.
Device attach function .
/* get PCI capabilites */ /* Init RTE stuff */ /* Enable internal target-read (in case we are probed after PF
		 * FLR). Must be done prior to any BAR read access. Only for
		 * 57712 and up
		 */ /* get device info and set params */ /* get phy settings from shmem and 'and' against admin settings */ /* Left mac of VF unfilled, PF should set it for VF */ /* set the default MTU (changed via ifconfig) */ /* need to reset chip if UNDI was active */ /* init fw_seq */ /* calculate qm_cid_count */