XilinxProcessorIPLib/drivers/vphy/src/xvphy_gtpe2.c
u32 XVphy_Gtpe2OutDivChReconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId ChId, XVphy_DirectionType Dir)
{
	u16 DrpVal;
	u16 WriteVal;
    u32 Status = XST_SUCCESS;

	/* Obtain current DRP register value for TX/RX dividers. */
	Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x88, &DrpVal);

	if (Dir == XVPHY_DIR_RX) {
		/* Mask out RX_OUT_DIV. */
		DrpVal &= ~0x07;
		/* Set RX_OUT_DIV. */
		WriteVal = (XVphy_DToDrpEncoding(InstancePtr, QuadId, ChId,
				XVPHY_DIR_RX) & 0x7);
		DrpVal |= WriteVal;
	}
	else {
		/* Mask out TX_OUT_DIV. */
		DrpVal &= ~0x70;
		/* Set TX_OUT_DIV. */
		WriteVal = (XVphy_DToDrpEncoding(InstancePtr, QuadId, ChId,
				XVPHY_DIR_TX) & 0x7);
		DrpVal |= (WriteVal << 4);
	}
	/* Write new DRP register value for TX/RX dividers. */
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x88, DrpVal);

	return Status;
}
/*****************************************************************************/
/**
* This function will set the output divider logic for a given channel.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
* @param	Dir is an indicator for RX or TX.
*
* @return
*		- XST_SUCCESS if the configuration was successful.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function will set the output divider logic for a given channel.
This function will set the output divider logic for a given channel .
u32 XVphy_Gtpe2OutDivChReconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId ChId, XVphy_DirectionType Dir)
{
	u16 DrpVal;
	u16 WriteVal;
    u32 Status = XST_SUCCESS;
	Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x88, &DrpVal);
	if (Dir == XVPHY_DIR_RX) {
		DrpVal &= ~0x07;
		WriteVal = (XVphy_DToDrpEncoding(InstancePtr, QuadId, ChId,
				XVPHY_DIR_RX) & 0x7);
		DrpVal |= WriteVal;
	}
	else {
		DrpVal &= ~0x70;
		WriteVal = (XVphy_DToDrpEncoding(InstancePtr, QuadId, ChId,
				XVPHY_DIR_TX) & 0x7);
		DrpVal |= (WriteVal << 4);
	}
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x88, DrpVal);
	return Status;
}
u32 XVphy_Gtpe2OutDivChReconfig ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId ChId , XVphy_DirectionType Dir ) { u16 DrpVal ; u16 WriteVal ; u32 Status = XST_SUCCESS ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0x88 , & DrpVal ) ; if ( Dir == XVPHY_DIR_RX ) { DrpVal &= ~ 0x07 ; WriteVal = ( XVphy_DToDrpEncoding ( InstancePtr , QuadId , ChId , XVPHY_DIR_RX ) & 0x7 ) ; DrpVal |= WriteVal ; } else { DrpVal &= ~ 0x70 ; WriteVal = ( XVphy_DToDrpEncoding ( InstancePtr , QuadId , ChId , XVPHY_DIR_TX ) & 0x7 ) ; DrpVal |= ( WriteVal << 4 ) ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x88 , DrpVal ) ; return Status ; }
This function will set the output divider logic for a given channel.
This function will set the output divider logic for a given channel .
/* Obtain current DRP register value for TX/RX dividers. */ /* Mask out RX_OUT_DIV. */ /* Set RX_OUT_DIV. */ /* Mask out TX_OUT_DIV. */ /* Set TX_OUT_DIV. */ /* Write new DRP register value for TX/RX dividers. */