XilinxProcessorIPLib/drivers/sysmonpsu/src/xsysmonpsu.c
s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u64 AvgEnableChMask,
		u32 SysmonBlk)
{
	s32 Status;
	UINTPTR EffectiveBaseAddress;

	/* Assert the arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));

	/*
	 * The sequencer must be disabled for writing any of these registers.
	 * Return XST_FAILURE if the channel sequencer is enabled.
	 */
	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
	                                     != XSM_SEQ_MODE_SAFE)) {
		Status = (s32)XST_FAILURE;
	} else {
		/* Calculate the effective baseaddress based on the Sysmon instance. */
		EffectiveBaseAddress =
				XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
						SysmonBlk);
		/*
		 * Enable/disable the averaging for the specified channels in the
		 * ADC Channel Averaging Enables Sequencer Registers.
		 */
		XSysmonPsu_WriteReg(EffectiveBaseAddress +
				XSYSMONPSU_SEQ_AVERAGE0_OFFSET,
				(u32)(AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK));

		XSysmonPsu_WriteReg(EffectiveBaseAddress +
				XSYSMONPSU_SEQ_AVERAGE1_OFFSET,
				 (u32)(AvgEnableChMask >> XSM_SEQ_CH_SHIFT) &
				 XSYSMONPSU_SEQ_AVERAGE1_MASK);

		XSysmonPsu_WriteReg(EffectiveBaseAddress +
				XSYSMONPSU_SEQ_AVERAGE2_OFFSET,
				 (u32)(AvgEnableChMask >> XSM_SEQ_CH2_SHIFT) &
				 XSYSMONPSU_SEQ_AVERAGE2_MASK);

		Status = (s32)XST_SUCCESS;
	}

	return Status;
}
/****************************************************************************/
/**
*
* This function enables the averaging for the specified channels in the ADC
* Channel Averaging Enable Sequencer Registers. The sequencer must be in
* the Safe Mode before writing to these registers.
*
* @param	InstancePtr is a pointer to the XSysMonPsu instance.
* @param	AvgEnableChMask is the bit mask of all the channels for which
*		averaging is to be enabled. Use XSYSMONPSU_SEQ_AVERAGE* defined in
*		xsysmonpsu_hw.h to specify the Channel numbers. Averaging will be
*		enabled for bit masks of 1 and disabled for bit mask of 0.
*		The AvgEnableChMask is a 64 bit mask that is written to the
*		three 16 bit ADC Channel Averaging Enable Sequencer Registers.
* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
*       block or PL Sysmon block register region.
*
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the ADC Channel Averaging Enables Sequencer Registers.
*		- XST_FAILURE if the channel sequencer is enabled.
*
* @note		None.
*
*****************************************************************************/
This function enables the averaging for the specified channels in the ADC
Channel Averaging Enable Sequencer Registers. The sequencer must be in
the Safe Mode before writing to these registers.
This function enables the averaging for the specified channels in the ADC Channel Averaging Enable Sequencer Registers . The sequencer must be in the Safe Mode before writing to these registers .
s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u64 AvgEnableChMask,
		u32 SysmonBlk)
{
	s32 Status;
	UINTPTR EffectiveBaseAddress;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
	                                     != XSM_SEQ_MODE_SAFE)) {
		Status = (s32)XST_FAILURE;
	} else {
		EffectiveBaseAddress =
				XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
						SysmonBlk);
		XSysmonPsu_WriteReg(EffectiveBaseAddress +
				XSYSMONPSU_SEQ_AVERAGE0_OFFSET,
				(u32)(AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK));
		XSysmonPsu_WriteReg(EffectiveBaseAddress +
				XSYSMONPSU_SEQ_AVERAGE1_OFFSET,
				 (u32)(AvgEnableChMask >> XSM_SEQ_CH_SHIFT) &
				 XSYSMONPSU_SEQ_AVERAGE1_MASK);
		XSysmonPsu_WriteReg(EffectiveBaseAddress +
				XSYSMONPSU_SEQ_AVERAGE2_OFFSET,
				 (u32)(AvgEnableChMask >> XSM_SEQ_CH2_SHIFT) &
				 XSYSMONPSU_SEQ_AVERAGE2_MASK);
		Status = (s32)XST_SUCCESS;
	}
	return Status;
}
s32 XSysMonPsu_SetSeqAvgEnables ( XSysMonPsu * InstancePtr , u64 AvgEnableChMask , u32 SysmonBlk ) { s32 Status ; UINTPTR EffectiveBaseAddress ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Xil_AssertNonvoid ( ( SysmonBlk == XSYSMON_PS ) || ( SysmonBlk == XSYSMON_PL ) ) ; if ( ( XSysMonPsu_GetSequencerMode ( InstancePtr , SysmonBlk ) != XSM_SEQ_MODE_SAFE ) ) { Status = ( s32 ) XST_FAILURE ; } else { EffectiveBaseAddress = XSysMonPsu_GetEffBaseAddress ( InstancePtr -> Config . BaseAddress , SysmonBlk ) ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_SEQ_AVERAGE0_OFFSET , ( u32 ) ( AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK ) ) ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_SEQ_AVERAGE1_OFFSET , ( u32 ) ( AvgEnableChMask >> XSM_SEQ_CH_SHIFT ) & XSYSMONPSU_SEQ_AVERAGE1_MASK ) ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_SEQ_AVERAGE2_OFFSET , ( u32 ) ( AvgEnableChMask >> XSM_SEQ_CH2_SHIFT ) & XSYSMONPSU_SEQ_AVERAGE2_MASK ) ; Status = ( s32 ) XST_SUCCESS ; } return Status ; }
This function enables the averaging for the specified channels in the ADC
Channel Averaging Enable Sequencer Registers.
This function enables the averaging for the specified channels in the ADC Channel Averaging Enable Sequencer Registers .
/* Assert the arguments. */ /*
	 * The sequencer must be disabled for writing any of these registers.
	 * Return XST_FAILURE if the channel sequencer is enabled.
	 */ /* Calculate the effective baseaddress based on the Sysmon instance. */ /*
		 * Enable/disable the averaging for the specified channels in the
		 * ADC Channel Averaging Enables Sequencer Registers.
		 */