XilinxProcessorIPLib/drivers/axiethernet/examples/xaxiethernet_example_intr_sgdma.c
int AxiEthernetSgDmaIntrSingleFrameExample(XAxiEthernet
			*AxiEthernetInstancePtr, XAxiDma *DmaInstancePtr)
{
	int Status;
	u32 TxFrameLength;
	u32 RxFrameLength;
	int PayloadSize = PAYLOAD_SIZE;
	XAxiDma_BdRing *RxRingPtr = XAxiDma_GetRxRing(DmaInstancePtr);
	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(DmaInstancePtr);
	XAxiDma_Bd *Bd1Ptr;
	XAxiDma_Bd *Bd2Ptr;
	XAxiDma_Bd *BdCurPtr;
	u32 BdSts;

	/*
	 * Clear variables shared with callbacks
	 */
	FramesRx = 0;
	FramesTx = 0;
	DeviceErrors = 0;
	memset(RxFrame,0,sizeof(RxFrame));
	memset(TxFrame,0,sizeof(TxFrame));

	/*
	 * Calculate the frame length (not including FCS)
	 */
	TxFrameLength = XAE_HDR_SIZE + PayloadSize;

	/*
	 * Setup packet to be transmitted
	 */
	AxiEthernetUtilFrameHdrFormatMAC(&TxFrame, AxiEthernetMAC);
	AxiEthernetUtilFrameHdrFormatType(&TxFrame, PayloadSize);
	AxiEthernetUtilFrameSetPayloadData(&TxFrame, PayloadSize);

	/*
	 * Flush the TX frame before giving it to DMA TX channel to transmit.
	 */
	Xil_DCacheFlushRange((UINTPTR)&TxFrame, TxFrameLength);

	/*
	 * Clear out receive packet memory area
	 */
	AxiEthernetUtilFrameMemClear(&RxFrame);

	/*
	 * Invalidate the RX frame before giving it to DMA RX channel to
	 * receive data.
	 */
	Xil_DCacheInvalidateRange((UINTPTR)&RxFrame, TxFrameLength);

	/*
	 * Make sure Tx and Rx are enabled
	 */
	Status = XAxiEthernet_SetOptions(AxiEthernetInstancePtr,
				     XAE_RECEIVER_ENABLE_OPTION |
				     XAE_TRANSMITTER_ENABLE_OPTION);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting options");
		return XST_FAILURE;
	}

	/*
	 * Start the Axi Ethernet device and enable the ERROR interrupt
	 */
	XAxiEthernet_Start(AxiEthernetInstancePtr);
	XAxiEthernet_IntEnable(AxiEthernetInstancePtr,
					XAE_INT_RECV_ERROR_MASK);

	/*
	 * Enable DMA RX interrupt.
	 *
	 * Interrupt coalescing parameters are left at their default settings
	 * which is to interrupt the processor after every frame has been
	 * processed by the DMA engine.
	 */
	XAxiDma_BdRingIntEnable(RxRingPtr, XAXIDMA_IRQ_ALL_MASK);

	/*
	 * Allocate 1 RxBD.
	 */
	Status = XAxiDma_BdRingAlloc(RxRingPtr, 1, &Bd1Ptr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error allocating RxBD");
		return XST_FAILURE;
	}

	/*
	 * Setup the BD.
	 */
	XAxiDma_BdSetBufAddr(Bd1Ptr, (UINTPTR)&RxFrame);
#ifndef XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL
	XAxiDma_BdSetLength(Bd1Ptr, XAE_MAX_JUMBO_FRAME_SIZE);
#else
	XAxiDma_BdSetLength(Bd1Ptr, XAE_MAX_JUMBO_FRAME_SIZE,
				RxRingPtr->MaxTransferLen);
#endif
	XAxiDma_BdSetCtrl(Bd1Ptr, 0);

	/*
	 * Enqueue to HW
	 */
	Status = XAxiDma_BdRingToHw(RxRingPtr, 1, Bd1Ptr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error committing RxBD to HW");
		return XST_FAILURE;
	}

	/*
	 * Start DMA RX channel. Now it's ready to receive data.
	 */
	Status = XAxiDma_BdRingStart(RxRingPtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Enable DMA transmit interrupts
	 */
	XAxiDma_BdRingIntEnable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);

	/*
	 * Allocate, setup, and enqueue 2 TxBDs. The first BD will describe
	 * the first 32 bytes of TxFrame and the second BD will describe the
	 * rest of the frame.
	 *
	 * The function below will allocate two adjacent BDs with Bd1Ptr being
	 * set as the lead BD.
	 */
	Status = XAxiDma_BdRingAlloc(TxRingPtr, 2, &Bd1Ptr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error allocating TxBD");
		return XST_FAILURE;
	}

	/*
	 * Setup TxBD #1
	 */
	XAxiDma_BdSetBufAddr(Bd1Ptr, (UINTPTR)&TxFrame);

#ifndef XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL
	XAxiDma_BdSetLength(Bd1Ptr, 32);
#else
	XAxiDma_BdSetLength(Bd1Ptr, 32,
			TxRingPtr->MaxTransferLen);
#endif

	XAxiDma_BdSetCtrl(Bd1Ptr, XAXIDMA_BD_CTRL_TXSOF_MASK);

	/*
	 * Setup TxBD #2
	 */
	Bd2Ptr = (XAxiDma_Bd *)XAxiDma_BdRingNext(TxRingPtr, Bd1Ptr);
	XAxiDma_BdSetBufAddr(Bd2Ptr, (UINTPTR) (&TxFrame) + 32);
#ifndef XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL
	XAxiDma_BdSetLength(Bd2Ptr, TxFrameLength - 32);
#else
	XAxiDma_BdSetLength(Bd2Ptr, TxFrameLength - 32,
				TxRingPtr->MaxTransferLen);
#endif

	XAxiDma_BdSetCtrl(Bd2Ptr, XAXIDMA_BD_CTRL_TXEOF_MASK);

	/*
	 * Enqueue to HW
	 */
	Status = XAxiDma_BdRingToHw(TxRingPtr, 2, Bd1Ptr);
	if (Status != XST_SUCCESS) {
		/*
		 * Undo BD allocation and exit
		 */
		XAxiDma_BdRingUnAlloc(TxRingPtr, 2, Bd1Ptr);
		AxiEthernetUtilErrorTrap("Error committing TxBD to HW");
		return XST_FAILURE;
	}

	/*
	 * Start DMA TX channel. Transmission starts at once.
	 */
	Status = XAxiDma_BdRingStart(TxRingPtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Wait for transmission to complete
	 */
	while (!FramesTx);
	/*
	 * Now that the frame has been sent, post process our TxBDs.
	 * Since we have only submitted 2 to HW, then there should be only 2 ready
	 * for post processing.
	 */
	if (XAxiDma_BdRingFromHw(TxRingPtr, 2, &Bd1Ptr) == 0) {
		AxiEthernetUtilErrorTrap("TxBDs were not ready for post processing");
		return XST_FAILURE;
	}

	/*
	 * Examine the TxBDs.
	 *
	 * There isn't much to do. The only thing to check would be DMA exception
	 * bits. But this would also be caught in the error handler. So we just
	 * return these BDs to the free list
	 */
	Status = XAxiDma_BdRingFree(TxRingPtr, 2, Bd1Ptr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error freeing up TxBDs");
		return XST_FAILURE;
	}

	/*
	 * Wait for Rx indication
	 */
	while (!FramesRx);

	/*
	 * Now that the frame has been received, post process our RxBD.
	 * Since we have only submitted 1 to HW, then there should be only 1
	 * ready for post processing.
	 */
	if (XAxiDma_BdRingFromHw(RxRingPtr, 1, &Bd1Ptr) == 0) {
		AxiEthernetUtilErrorTrap("RxBD was not ready for post processing");
		return XST_FAILURE;
	}
	BdCurPtr = Bd1Ptr;
	BdSts = XAxiDma_BdGetSts(BdCurPtr);
	if ((BdSts & XAXIDMA_BD_STS_ALL_ERR_MASK) ||
		(!(BdSts & XAXIDMA_BD_STS_COMPLETE_MASK))) {
			AxiEthernetUtilErrorTrap("Rx Error");
			return XST_FAILURE;
	}
	else {
		RxFrameLength =
		(XAxiDma_BdRead(BdCurPtr,XAXIDMA_BD_USR4_OFFSET)) & 0x0000FFFF;
	}

	if (RxFrameLength != TxFrameLength) {
		AxiEthernetUtilErrorTrap("Length mismatch");
		return XST_FAILURE;
	}


	if (AxiEthernetUtilFrameVerify(&TxFrame, &RxFrame) != 0) {
		AxiEthernetUtilErrorTrap("Data mismatch");
		return XST_FAILURE;
	}

	/*
	 * Return the RxBD back to the channel for later allocation. Free the
	 * exact number we just post processed.
	 */
	Status = XAxiDma_BdRingFree(RxRingPtr, 1, Bd1Ptr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error freeing up TxBDs");
		return XST_FAILURE;
	}

	/*
	 * Finished this example. If everything worked correctly, all TxBDs and
	 * RxBDs should be free for allocation. Stop the device.
	 */
	XAxiEthernet_Stop(AxiEthernetInstancePtr);
	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function demonstrates the usage of the Axi Ethernet by sending and
* receiving a single frame in SGDMA interrupt mode.
* The source packet will be described by two descriptors. It will be received
* into a buffer described by a single descriptor.
*
* @param	AxiEthernetInstancePtr is a pointer to the instance of the
*		Axi Ethernet component.
* @param	DmaInstancePtr   is a pointer to the instance of the Dma
*		component.
*
* @return	-XST_SUCCESS to indicate success
*		-XST_FAILURE to indicate failure
*
* @note		None.
*
******************************************************************************/
This function demonstrates the usage of the Axi Ethernet by sending and
receiving a single frame in SGDMA interrupt mode.
The source packet will be described by two descriptors. It will be received
into a buffer described by a single descriptor.
This function demonstrates the usage of the Axi Ethernet by sending and receiving a single frame in SGDMA interrupt mode . The source packet will be described by two descriptors . It will be received into a buffer described by a single descriptor .
int AxiEthernetSgDmaIntrSingleFrameExample(XAxiEthernet
			*AxiEthernetInstancePtr, XAxiDma *DmaInstancePtr)
{
	int Status;
	u32 TxFrameLength;
	u32 RxFrameLength;
	int PayloadSize = PAYLOAD_SIZE;
	XAxiDma_BdRing *RxRingPtr = XAxiDma_GetRxRing(DmaInstancePtr);
	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(DmaInstancePtr);
	XAxiDma_Bd *Bd1Ptr;
	XAxiDma_Bd *Bd2Ptr;
	XAxiDma_Bd *BdCurPtr;
	u32 BdSts;
	FramesRx = 0;
	FramesTx = 0;
	DeviceErrors = 0;
	memset(RxFrame,0,sizeof(RxFrame));
	memset(TxFrame,0,sizeof(TxFrame));
	TxFrameLength = XAE_HDR_SIZE + PayloadSize;
	AxiEthernetUtilFrameHdrFormatMAC(&TxFrame, AxiEthernetMAC);
	AxiEthernetUtilFrameHdrFormatType(&TxFrame, PayloadSize);
	AxiEthernetUtilFrameSetPayloadData(&TxFrame, PayloadSize);
	Xil_DCacheFlushRange((UINTPTR)&TxFrame, TxFrameLength);
	AxiEthernetUtilFrameMemClear(&RxFrame);
	Xil_DCacheInvalidateRange((UINTPTR)&RxFrame, TxFrameLength);
	Status = XAxiEthernet_SetOptions(AxiEthernetInstancePtr,
				     XAE_RECEIVER_ENABLE_OPTION |
				     XAE_TRANSMITTER_ENABLE_OPTION);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting options");
		return XST_FAILURE;
	}
	XAxiEthernet_Start(AxiEthernetInstancePtr);
	XAxiEthernet_IntEnable(AxiEthernetInstancePtr,
					XAE_INT_RECV_ERROR_MASK);
	XAxiDma_BdRingIntEnable(RxRingPtr, XAXIDMA_IRQ_ALL_MASK);
	Status = XAxiDma_BdRingAlloc(RxRingPtr, 1, &Bd1Ptr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error allocating RxBD");
		return XST_FAILURE;
	}
	XAxiDma_BdSetBufAddr(Bd1Ptr, (UINTPTR)&RxFrame);
#ifndef XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL
	XAxiDma_BdSetLength(Bd1Ptr, XAE_MAX_JUMBO_FRAME_SIZE);
#else
	XAxiDma_BdSetLength(Bd1Ptr, XAE_MAX_JUMBO_FRAME_SIZE,
				RxRingPtr->MaxTransferLen);
#endif
	XAxiDma_BdSetCtrl(Bd1Ptr, 0);
	Status = XAxiDma_BdRingToHw(RxRingPtr, 1, Bd1Ptr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error committing RxBD to HW");
		return XST_FAILURE;
	}
	Status = XAxiDma_BdRingStart(RxRingPtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	XAxiDma_BdRingIntEnable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);
	Status = XAxiDma_BdRingAlloc(TxRingPtr, 2, &Bd1Ptr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error allocating TxBD");
		return XST_FAILURE;
	}
	XAxiDma_BdSetBufAddr(Bd1Ptr, (UINTPTR)&TxFrame);
#ifndef XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL
	XAxiDma_BdSetLength(Bd1Ptr, 32);
#else
	XAxiDma_BdSetLength(Bd1Ptr, 32,
			TxRingPtr->MaxTransferLen);
#endif
	XAxiDma_BdSetCtrl(Bd1Ptr, XAXIDMA_BD_CTRL_TXSOF_MASK);
	Bd2Ptr = (XAxiDma_Bd *)XAxiDma_BdRingNext(TxRingPtr, Bd1Ptr);
	XAxiDma_BdSetBufAddr(Bd2Ptr, (UINTPTR) (&TxFrame) + 32);
#ifndef XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL
	XAxiDma_BdSetLength(Bd2Ptr, TxFrameLength - 32);
#else
	XAxiDma_BdSetLength(Bd2Ptr, TxFrameLength - 32,
				TxRingPtr->MaxTransferLen);
#endif
	XAxiDma_BdSetCtrl(Bd2Ptr, XAXIDMA_BD_CTRL_TXEOF_MASK);
	Status = XAxiDma_BdRingToHw(TxRingPtr, 2, Bd1Ptr);
	if (Status != XST_SUCCESS) {
		XAxiDma_BdRingUnAlloc(TxRingPtr, 2, Bd1Ptr);
		AxiEthernetUtilErrorTrap("Error committing TxBD to HW");
		return XST_FAILURE;
	}
	Status = XAxiDma_BdRingStart(TxRingPtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	while (!FramesTx);
	if (XAxiDma_BdRingFromHw(TxRingPtr, 2, &Bd1Ptr) == 0) {
		AxiEthernetUtilErrorTrap("TxBDs were not ready for post processing");
		return XST_FAILURE;
	}
	Status = XAxiDma_BdRingFree(TxRingPtr, 2, Bd1Ptr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error freeing up TxBDs");
		return XST_FAILURE;
	}
	while (!FramesRx);
	if (XAxiDma_BdRingFromHw(RxRingPtr, 1, &Bd1Ptr) == 0) {
		AxiEthernetUtilErrorTrap("RxBD was not ready for post processing");
		return XST_FAILURE;
	}
	BdCurPtr = Bd1Ptr;
	BdSts = XAxiDma_BdGetSts(BdCurPtr);
	if ((BdSts & XAXIDMA_BD_STS_ALL_ERR_MASK) ||
		(!(BdSts & XAXIDMA_BD_STS_COMPLETE_MASK))) {
			AxiEthernetUtilErrorTrap("Rx Error");
			return XST_FAILURE;
	}
	else {
		RxFrameLength =
		(XAxiDma_BdRead(BdCurPtr,XAXIDMA_BD_USR4_OFFSET)) & 0x0000FFFF;
	}
	if (RxFrameLength != TxFrameLength) {
		AxiEthernetUtilErrorTrap("Length mismatch");
		return XST_FAILURE;
	}
	if (AxiEthernetUtilFrameVerify(&TxFrame, &RxFrame) != 0) {
		AxiEthernetUtilErrorTrap("Data mismatch");
		return XST_FAILURE;
	}
	Status = XAxiDma_BdRingFree(RxRingPtr, 1, Bd1Ptr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error freeing up TxBDs");
		return XST_FAILURE;
	}
	XAxiEthernet_Stop(AxiEthernetInstancePtr);
	return XST_SUCCESS;
}
int AxiEthernetSgDmaIntrSingleFrameExample ( XAxiEthernet * AxiEthernetInstancePtr , XAxiDma * DmaInstancePtr ) { int Status ; u32 TxFrameLength ; u32 RxFrameLength ; int PayloadSize = PAYLOAD_SIZE ; XAxiDma_BdRing * RxRingPtr = XAxiDma_GetRxRing ( DmaInstancePtr ) ; XAxiDma_BdRing * TxRingPtr = XAxiDma_GetTxRing ( DmaInstancePtr ) ; XAxiDma_Bd * Bd1Ptr ; XAxiDma_Bd * Bd2Ptr ; XAxiDma_Bd * BdCurPtr ; u32 BdSts ; FramesRx = 0 ; FramesTx = 0 ; DeviceErrors = 0 ; memset ( RxFrame , 0 , sizeof ( RxFrame ) ) ; memset ( TxFrame , 0 , sizeof ( TxFrame ) ) ; TxFrameLength = XAE_HDR_SIZE + PayloadSize ; AxiEthernetUtilFrameHdrFormatMAC ( & TxFrame , AxiEthernetMAC ) ; AxiEthernetUtilFrameHdrFormatType ( & TxFrame , PayloadSize ) ; AxiEthernetUtilFrameSetPayloadData ( & TxFrame , PayloadSize ) ; Xil_DCacheFlushRange ( ( UINTPTR ) & TxFrame , TxFrameLength ) ; AxiEthernetUtilFrameMemClear ( & RxFrame ) ; Xil_DCacheInvalidateRange ( ( UINTPTR ) & RxFrame , TxFrameLength ) ; Status = XAxiEthernet_SetOptions ( AxiEthernetInstancePtr , XAE_RECEIVER_ENABLE_OPTION | XAE_TRANSMITTER_ENABLE_OPTION ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } XAxiEthernet_Start ( AxiEthernetInstancePtr ) ; XAxiEthernet_IntEnable ( AxiEthernetInstancePtr , XAE_INT_RECV_ERROR_MASK ) ; XAxiDma_BdRingIntEnable ( RxRingPtr , XAXIDMA_IRQ_ALL_MASK ) ; Status = XAxiDma_BdRingAlloc ( RxRingPtr , 1 , & Bd1Ptr ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } XAxiDma_BdSetBufAddr ( Bd1Ptr , ( UINTPTR ) & RxFrame ) ; #ifndef XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL XAxiDma_BdSetLength ( Bd1Ptr , XAE_MAX_JUMBO_FRAME_SIZE ) ; #else XAxiDma_BdSetLength ( Bd1Ptr , XAE_MAX_JUMBO_FRAME_SIZE , RxRingPtr -> MaxTransferLen ) ; #endif XAxiDma_BdSetCtrl ( Bd1Ptr , 0 ) ; Status = XAxiDma_BdRingToHw ( RxRingPtr , 1 , Bd1Ptr ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } Status = XAxiDma_BdRingStart ( RxRingPtr ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } XAxiDma_BdRingIntEnable ( TxRingPtr , XAXIDMA_IRQ_ALL_MASK ) ; Status = XAxiDma_BdRingAlloc ( TxRingPtr , 2 , & Bd1Ptr ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } XAxiDma_BdSetBufAddr ( Bd1Ptr , ( UINTPTR ) & TxFrame ) ; #ifndef XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL XAxiDma_BdSetLength ( Bd1Ptr , 32 ) ; #else XAxiDma_BdSetLength ( Bd1Ptr , 32 , TxRingPtr -> MaxTransferLen ) ; #endif XAxiDma_BdSetCtrl ( Bd1Ptr , XAXIDMA_BD_CTRL_TXSOF_MASK ) ; Bd2Ptr = ( XAxiDma_Bd * ) XAxiDma_BdRingNext ( TxRingPtr , Bd1Ptr ) ; XAxiDma_BdSetBufAddr ( Bd2Ptr , ( UINTPTR ) ( & TxFrame ) + 32 ) ; #ifndef XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL XAxiDma_BdSetLength ( Bd2Ptr , TxFrameLength - 32 ) ; #else XAxiDma_BdSetLength ( Bd2Ptr , TxFrameLength - 32 , TxRingPtr -> MaxTransferLen ) ; #endif XAxiDma_BdSetCtrl ( Bd2Ptr , XAXIDMA_BD_CTRL_TXEOF_MASK ) ; Status = XAxiDma_BdRingToHw ( TxRingPtr , 2 , Bd1Ptr ) ; if ( Status != XST_SUCCESS ) { XAxiDma_BdRingUnAlloc ( TxRingPtr , 2 , Bd1Ptr ) ; AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } Status = XAxiDma_BdRingStart ( TxRingPtr ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } while ( ! FramesTx ) ; if ( XAxiDma_BdRingFromHw ( TxRingPtr , 2 , & Bd1Ptr ) == 0 ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } Status = XAxiDma_BdRingFree ( TxRingPtr , 2 , Bd1Ptr ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } while ( ! FramesRx ) ; if ( XAxiDma_BdRingFromHw ( RxRingPtr , 1 , & Bd1Ptr ) == 0 ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } BdCurPtr = Bd1Ptr ; BdSts = XAxiDma_BdGetSts ( BdCurPtr ) ; if ( ( BdSts & XAXIDMA_BD_STS_ALL_ERR_MASK ) || ( ! ( BdSts & XAXIDMA_BD_STS_COMPLETE_MASK ) ) ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } else { RxFrameLength = ( XAxiDma_BdRead ( BdCurPtr , XAXIDMA_BD_USR4_OFFSET ) ) & 0x0000FFFF ; } if ( RxFrameLength != TxFrameLength ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } if ( AxiEthernetUtilFrameVerify ( & TxFrame , & RxFrame ) != 0 ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } Status = XAxiDma_BdRingFree ( RxRingPtr , 1 , Bd1Ptr ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } XAxiEthernet_Stop ( AxiEthernetInstancePtr ) ; return XST_SUCCESS ; }
This function demonstrates the usage of the Axi Ethernet by sending and
receiving a single frame in SGDMA interrupt mode.
This function demonstrates the usage of the Axi Ethernet by sending and receiving a single frame in SGDMA interrupt mode .
/*
	 * Clear variables shared with callbacks
	 */ /*
	 * Calculate the frame length (not including FCS)
	 */ /*
	 * Setup packet to be transmitted
	 */ /*
	 * Flush the TX frame before giving it to DMA TX channel to transmit.
	 */ /*
	 * Clear out receive packet memory area
	 */ /*
	 * Invalidate the RX frame before giving it to DMA RX channel to
	 * receive data.
	 */ /*
	 * Make sure Tx and Rx are enabled
	 */ /*
	 * Start the Axi Ethernet device and enable the ERROR interrupt
	 */ /*
	 * Enable DMA RX interrupt.
	 *
	 * Interrupt coalescing parameters are left at their default settings
	 * which is to interrupt the processor after every frame has been
	 * processed by the DMA engine.
	 */ /*
	 * Allocate 1 RxBD.
	 */ /*
	 * Setup the BD.
	 */ /*
	 * Enqueue to HW
	 */ /*
	 * Start DMA RX channel. Now it's ready to receive data.
	 */ /*
	 * Enable DMA transmit interrupts
	 */ /*
	 * Allocate, setup, and enqueue 2 TxBDs. The first BD will describe
	 * the first 32 bytes of TxFrame and the second BD will describe the
	 * rest of the frame.
	 *
	 * The function below will allocate two adjacent BDs with Bd1Ptr being
	 * set as the lead BD.
	 */ /*
	 * Setup TxBD #1
	 */ /*
	 * Setup TxBD #2
	 */ /*
	 * Enqueue to HW
	 */ /*
		 * Undo BD allocation and exit
		 */ /*
	 * Start DMA TX channel. Transmission starts at once.
	 */ /*
	 * Wait for transmission to complete
	 */ /*
	 * Now that the frame has been sent, post process our TxBDs.
	 * Since we have only submitted 2 to HW, then there should be only 2 ready
	 * for post processing.
	 */ /*
	 * Examine the TxBDs.
	 *
	 * There isn't much to do. The only thing to check would be DMA exception
	 * bits. But this would also be caught in the error handler. So we just
	 * return these BDs to the free list
	 */ /*
	 * Wait for Rx indication
	 */ /*
	 * Now that the frame has been received, post process our RxBD.
	 * Since we have only submitted 1 to HW, then there should be only 1
	 * ready for post processing.
	 */ /*
	 * Return the RxBD back to the channel for later allocation. Free the
	 * exact number we just post processed.
	 */ /*
	 * Finished this example. If everything worked correctly, all TxBDs and
	 * RxBDs should be free for allocation. Stop the device.
	 */