XilinxProcessorIPLib/drivers/vphy/src/xvphy_hdmi_intr.c
void XVphy_HdmiGtHandler(XVphy *InstancePtr)
{
	u32 Event;
	u32 EventMask;
	u32 EventAck;
	XVphy_GtState *TxStatePtr;
	XVphy_GtState *RxStatePtr;

	EventMask = XVPHY_INTR_QPLL0_LOCK_MASK | XVPHY_INTR_CPLL_LOCK_MASK |
		XVPHY_INTR_QPLL1_LOCK_MASK | XVPHY_INTR_TXRESETDONE_MASK |
		XVPHY_INTR_TXALIGNDONE_MASK | XVPHY_INTR_RXRESETDONE_MASK |
		XVPHY_INTR_TXMMCMUSRCLK_LOCK_MASK | XVPHY_INTR_RXMMCMUSRCLK_LOCK_MASK;

	u8 QuadId = 0;

	/* Read Interrupt Status register */
	Event = XVphy_ReadReg(InstancePtr->Config.BaseAddr, XVPHY_INTR_STS_REG);

	EventAck = EventMask & Event;

	/* Read States for Quad=0 Ch1 */
	TxStatePtr = &InstancePtr->Quads[QuadId].Ch1.TxState;
	RxStatePtr = &InstancePtr->Quads[QuadId].Ch1.RxState;

	if (Event & XVPHY_INTR_TXMMCMUSRCLK_LOCK_MASK) {
		XVphy_HdmiTxMmcmLockHandler(InstancePtr);
	}
	if (Event & XVPHY_INTR_RXMMCMUSRCLK_LOCK_MASK) {
		XVphy_HdmiRxMmcmLockHandler(InstancePtr);
	}
	if ((Event & XVPHY_INTR_QPLL0_LOCK_MASK) ||
	    (Event & XVPHY_INTR_QPLL1_LOCK_MASK)) {
#if (XPAR_VPHY_0_TRANSCEIVER == XVPHY_GTPE2)
		if (Event & XVPHY_INTR_QPLL0_LOCK_MASK) { /* PLL0. */
			XVphy_HdmiGtpPllLockHandler(InstancePtr, 0);
		}
		if (Event & XVPHY_INTR_QPLL1_LOCK_MASK) { /* PLL1. */
			XVphy_HdmiGtpPllLockHandler(InstancePtr, 1);
		}
#else
		XVphy_HdmiQpllLockHandler(InstancePtr);
#endif
	}
#if (XPAR_VPHY_0_TRANSCEIVER != XVPHY_GTPE2)
	if (Event & XVPHY_INTR_CPLL_LOCK_MASK) {
		XVphy_HdmiCpllLockHandler(InstancePtr);
	}
#endif
	if ((Event & XVPHY_INTR_TXRESETDONE_MASK)
			&& (*TxStatePtr == XVPHY_GT_STATE_RESET)) {
		XVphy_HdmiGtTxResetDoneLockHandler(InstancePtr);
	}
	if ((Event & XVPHY_INTR_TXALIGNDONE_MASK)
			&& (*TxStatePtr == XVPHY_GT_STATE_ALIGN)) {
		XVphy_HdmiGtTxAlignDoneLockHandler(InstancePtr);
	}
	if ((Event & XVPHY_INTR_RXRESETDONE_MASK)
			&& (*RxStatePtr == XVPHY_GT_STATE_RESET)) {
		XVphy_HdmiGtRxResetDoneLockHandler(InstancePtr);
	}

	/* Clear event flags by writing to Interrupt Status register */
	XVphy_WriteReg(InstancePtr->Config.BaseAddr, XVPHY_INTR_STS_REG,
			EventAck);
}
/*****************************************************************************/
/**
* This function is the interrupt handler for the GT events.
*
* @param	InstancePtr is a pointer to the VPHY instance.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function is the interrupt handler for the GT events.
This function is the interrupt handler for the GT events .
void XVphy_HdmiGtHandler(XVphy *InstancePtr)
{
	u32 Event;
	u32 EventMask;
	u32 EventAck;
	XVphy_GtState *TxStatePtr;
	XVphy_GtState *RxStatePtr;
	EventMask = XVPHY_INTR_QPLL0_LOCK_MASK | XVPHY_INTR_CPLL_LOCK_MASK |
		XVPHY_INTR_QPLL1_LOCK_MASK | XVPHY_INTR_TXRESETDONE_MASK |
		XVPHY_INTR_TXALIGNDONE_MASK | XVPHY_INTR_RXRESETDONE_MASK |
		XVPHY_INTR_TXMMCMUSRCLK_LOCK_MASK | XVPHY_INTR_RXMMCMUSRCLK_LOCK_MASK;
	u8 QuadId = 0;
	Event = XVphy_ReadReg(InstancePtr->Config.BaseAddr, XVPHY_INTR_STS_REG);
	EventAck = EventMask & Event;
	TxStatePtr = &InstancePtr->Quads[QuadId].Ch1.TxState;
	RxStatePtr = &InstancePtr->Quads[QuadId].Ch1.RxState;
	if (Event & XVPHY_INTR_TXMMCMUSRCLK_LOCK_MASK) {
		XVphy_HdmiTxMmcmLockHandler(InstancePtr);
	}
	if (Event & XVPHY_INTR_RXMMCMUSRCLK_LOCK_MASK) {
		XVphy_HdmiRxMmcmLockHandler(InstancePtr);
	}
	if ((Event & XVPHY_INTR_QPLL0_LOCK_MASK) ||
	    (Event & XVPHY_INTR_QPLL1_LOCK_MASK)) {
#if (XPAR_VPHY_0_TRANSCEIVER == XVPHY_GTPE2)
		if (Event & XVPHY_INTR_QPLL0_LOCK_MASK) { 
			XVphy_HdmiGtpPllLockHandler(InstancePtr, 0);
		}
		if (Event & XVPHY_INTR_QPLL1_LOCK_MASK) { 
			XVphy_HdmiGtpPllLockHandler(InstancePtr, 1);
		}
#else
		XVphy_HdmiQpllLockHandler(InstancePtr);
#endif
	}
#if (XPAR_VPHY_0_TRANSCEIVER != XVPHY_GTPE2)
	if (Event & XVPHY_INTR_CPLL_LOCK_MASK) {
		XVphy_HdmiCpllLockHandler(InstancePtr);
	}
#endif
	if ((Event & XVPHY_INTR_TXRESETDONE_MASK)
			&& (*TxStatePtr == XVPHY_GT_STATE_RESET)) {
		XVphy_HdmiGtTxResetDoneLockHandler(InstancePtr);
	}
	if ((Event & XVPHY_INTR_TXALIGNDONE_MASK)
			&& (*TxStatePtr == XVPHY_GT_STATE_ALIGN)) {
		XVphy_HdmiGtTxAlignDoneLockHandler(InstancePtr);
	}
	if ((Event & XVPHY_INTR_RXRESETDONE_MASK)
			&& (*RxStatePtr == XVPHY_GT_STATE_RESET)) {
		XVphy_HdmiGtRxResetDoneLockHandler(InstancePtr);
	}
	XVphy_WriteReg(InstancePtr->Config.BaseAddr, XVPHY_INTR_STS_REG,
			EventAck);
}
void XVphy_HdmiGtHandler ( XVphy * InstancePtr ) { u32 Event ; u32 EventMask ; u32 EventAck ; XVphy_GtState * TxStatePtr ; XVphy_GtState * RxStatePtr ; EventMask = XVPHY_INTR_QPLL0_LOCK_MASK | XVPHY_INTR_CPLL_LOCK_MASK | XVPHY_INTR_QPLL1_LOCK_MASK | XVPHY_INTR_TXRESETDONE_MASK | XVPHY_INTR_TXALIGNDONE_MASK | XVPHY_INTR_RXRESETDONE_MASK | XVPHY_INTR_TXMMCMUSRCLK_LOCK_MASK | XVPHY_INTR_RXMMCMUSRCLK_LOCK_MASK ; u8 QuadId = 0 ; Event = XVphy_ReadReg ( InstancePtr -> Config . BaseAddr , XVPHY_INTR_STS_REG ) ; EventAck = EventMask & Event ; TxStatePtr = & InstancePtr -> Quads [ QuadId ] . Ch1 . TxState ; RxStatePtr = & InstancePtr -> Quads [ QuadId ] . Ch1 . RxState ; if ( Event & XVPHY_INTR_TXMMCMUSRCLK_LOCK_MASK ) { XVphy_HdmiTxMmcmLockHandler ( InstancePtr ) ; } if ( Event & XVPHY_INTR_RXMMCMUSRCLK_LOCK_MASK ) { XVphy_HdmiRxMmcmLockHandler ( InstancePtr ) ; } if ( ( Event & XVPHY_INTR_QPLL0_LOCK_MASK ) || ( Event & XVPHY_INTR_QPLL1_LOCK_MASK ) ) { #if ( XPAR_VPHY_0_TRANSCEIVER == XVPHY_GTPE2 ) if ( Event & XVPHY_INTR_QPLL0_LOCK_MASK ) { XVphy_HdmiGtpPllLockHandler ( InstancePtr , 0 ) ; } if ( Event & XVPHY_INTR_QPLL1_LOCK_MASK ) { XVphy_HdmiGtpPllLockHandler ( InstancePtr , 1 ) ; } #else XVphy_HdmiQpllLockHandler ( InstancePtr ) ; #endif } #if ( XPAR_VPHY_0_TRANSCEIVER != XVPHY_GTPE2 ) if ( Event & XVPHY_INTR_CPLL_LOCK_MASK ) { XVphy_HdmiCpllLockHandler ( InstancePtr ) ; } #endif if ( ( Event & XVPHY_INTR_TXRESETDONE_MASK ) && ( * TxStatePtr == XVPHY_GT_STATE_RESET ) ) { XVphy_HdmiGtTxResetDoneLockHandler ( InstancePtr ) ; } if ( ( Event & XVPHY_INTR_TXALIGNDONE_MASK ) && ( * TxStatePtr == XVPHY_GT_STATE_ALIGN ) ) { XVphy_HdmiGtTxAlignDoneLockHandler ( InstancePtr ) ; } if ( ( Event & XVPHY_INTR_RXRESETDONE_MASK ) && ( * RxStatePtr == XVPHY_GT_STATE_RESET ) ) { XVphy_HdmiGtRxResetDoneLockHandler ( InstancePtr ) ; } XVphy_WriteReg ( InstancePtr -> Config . BaseAddr , XVPHY_INTR_STS_REG , EventAck ) ; }
This function is the interrupt handler for the GT events.
This function is the interrupt handler for the GT events .
/* Read Interrupt Status register */ /* Read States for Quad=0 Ch1 */ /* PLL0. */ /* PLL1. */ /* Clear event flags by writing to Interrupt Status register */