XilinxProcessorIPLib/drivers/axidma/src/xaxidma_bdring.c
int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing *RingPtr, u32 Counter, u32 Timer)
{
	u32 Cr;

	Cr = XAxiDma_ReadReg(RingPtr->ChanBase, XAXIDMA_CR_OFFSET);

	if (Counter != XAXIDMA_NO_CHANGE) {
		if ((Counter == 0) || (Counter > 0xFF)) {

			xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetCoalesce: "
			"invalid  coalescing threshold %d", (int)Counter);
			return XST_FAILURE;
		}

		Cr = (Cr & ~XAXIDMA_COALESCE_MASK) |
			(Counter << XAXIDMA_COALESCE_SHIFT);
	}

	if (Timer != XAXIDMA_NO_CHANGE) {
		if (Timer > 0xFF) {

			xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetCoalesce: "
			"invalid  delay counter %d", (int)Timer);

			return XST_FAILURE;
		}

		Cr = (Cr & ~XAXIDMA_DELAY_MASK) |
			(Timer << XAXIDMA_DELAY_SHIFT);
	}

	XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_CR_OFFSET, Cr);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
 * Set interrupt coalescing parameters for the given descriptor ring channel.
 *
 * @param	RingPtr is a pointer to the descriptor ring instance to be
 *		worked on.
 * @param	Counter sets the packet counter on the channel. Valid range is
 *		- 1..255.
 *		- XAXIDMA_NO_CHANGE to leave this setting unchanged.
 * @param	Timer sets the waitbound timer on the channel. Valid range is
 * 		- 0..255.
 *		- XAXIDMA_NO_CHANGE to leave this setting unchanged.
 *		Each unit depend on hardware building parameter
 *		C_DLYTMR_RESOLUTION,which is in the range from 0 to 100,000
 *		clock cycles. A value of 0 disables the delay interrupt.
 *
 * @return
 *		- XST_SUCCESS if interrupt coalescing settings updated
 *		- XST_FAILURE if Counter or Timer parameters are out of range
 *
 * @note	This function can be used only when DMA is in SG mode
 *
 *****************************************************************************/
Set interrupt coalescing parameters for the given descriptor ring channel.
@param       RingPtr is a pointer to the descriptor ring instance to be
worked on.
@param       Counter sets the packet counter on the channel.

@return
- XST_SUCCESS if interrupt coalescing settings updated
- XST_FAILURE if Counter or Timer parameters are out of range

@note        This function can be used only when DMA is in SG mode
Set interrupt coalescing parameters for the given descriptor ring channel . @param RingPtr is a pointer to the descriptor ring instance to be worked on . @param Counter sets the packet counter on the channel . @return - XST_SUCCESS if interrupt coalescing settings updated - XST_FAILURE if Counter or Timer parameters are out of range @note This function can be used only when DMA is in SG mode
int XAxiDma_BdRingSetCoalesce(XAxiDma_BdRing *RingPtr, u32 Counter, u32 Timer)
{
	u32 Cr;
	Cr = XAxiDma_ReadReg(RingPtr->ChanBase, XAXIDMA_CR_OFFSET);
	if (Counter != XAXIDMA_NO_CHANGE) {
		if ((Counter == 0) || (Counter > 0xFF)) {
			xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetCoalesce: "
			"invalid  coalescing threshold %d", (int)Counter);
			return XST_FAILURE;
		}
		Cr = (Cr & ~XAXIDMA_COALESCE_MASK) |
			(Counter << XAXIDMA_COALESCE_SHIFT);
	}
	if (Timer != XAXIDMA_NO_CHANGE) {
		if (Timer > 0xFF) {
			xdbg_printf(XDBG_DEBUG_ERROR, "BdRingSetCoalesce: "
			"invalid  delay counter %d", (int)Timer);
			return XST_FAILURE;
		}
		Cr = (Cr & ~XAXIDMA_DELAY_MASK) |
			(Timer << XAXIDMA_DELAY_SHIFT);
	}
	XAxiDma_WriteReg(RingPtr->ChanBase, XAXIDMA_CR_OFFSET, Cr);
	return XST_SUCCESS;
}
int XAxiDma_BdRingSetCoalesce ( XAxiDma_BdRing * RingPtr , u32 Counter , u32 Timer ) { u32 Cr ; Cr = XAxiDma_ReadReg ( RingPtr -> ChanBase , XAXIDMA_CR_OFFSET ) ; if ( Counter != XAXIDMA_NO_CHANGE ) { if ( ( Counter == 0 ) || ( Counter > 0xFF ) ) { xdbg_printf ( XDBG_DEBUG_ERROR , " " " " , ( int ) Counter ) ; return XST_FAILURE ; } Cr = ( Cr & ~ XAXIDMA_COALESCE_MASK ) | ( Counter << XAXIDMA_COALESCE_SHIFT ) ; } if ( Timer != XAXIDMA_NO_CHANGE ) { if ( Timer > 0xFF ) { xdbg_printf ( XDBG_DEBUG_ERROR , " " " " , ( int ) Timer ) ; return XST_FAILURE ; } Cr = ( Cr & ~ XAXIDMA_DELAY_MASK ) | ( Timer << XAXIDMA_DELAY_SHIFT ) ; } XAxiDma_WriteReg ( RingPtr -> ChanBase , XAXIDMA_CR_OFFSET , Cr ) ; return XST_SUCCESS ; }
Set interrupt coalescing parameters for the given descriptor ring channel.
Set interrupt coalescing parameters for the given descriptor ring channel .