src/dpdk/drivers/net/igc/base/igc_mac.c
s32 igc_write_8bit_ctrl_reg_generic(struct igc_hw *hw, u32 reg,
				      u32 offset, u8 data)
{
	u32 i, regvalue = 0;

	DEBUGFUNC("igc_write_8bit_ctrl_reg_generic");

	/* Set up the address and data */
	regvalue = ((u32)data) | (offset << IGC_GEN_CTL_ADDRESS_SHIFT);
	IGC_WRITE_REG(hw, reg, regvalue);

	/* Poll the ready bit to see if the MDI read completed */
	for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) {
		usec_delay(5);
		regvalue = IGC_READ_REG(hw, reg);
		if (regvalue & IGC_GEN_CTL_READY)
			break;
	}
	if (!(regvalue & IGC_GEN_CTL_READY)) {
		DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
		return -IGC_ERR_PHY;
	}

	return IGC_SUCCESS;
}
/**
 *  igc_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
 *  @hw: pointer to the HW structure
 *  @reg: 32bit register offset such as IGC_SCTL
 *  @offset: register offset to write to
 *  @data: data to write at register offset
 *
 *  Writes an address/data control type register.  There are several of these
 *  and they all have the format address << 8 | data and bit 31 is polled for
 *  completion.
 **/
Write a 8bit CTRL register
@hw: pointer to the HW structure
@reg: 32bit register offset such as IGC_SCTL
@offset: register offset to write to
@data: data to write at register offset

Writes an address/data control type register.  There are several of these
and they all have the format address << 8 | data and bit 31 is polled for
completion.
Write a 8bit CTRL register @hw : pointer to the HW structure @reg : 32bit register offset such as IGC_SCTL @offset : register offset to write to @data : data to write at register offset Writes an address / data control type register . There are several of these and they all have the format address << 8 | data and bit 31 is polled for completion .
s32 igc_write_8bit_ctrl_reg_generic(struct igc_hw *hw, u32 reg,
				      u32 offset, u8 data)
{
	u32 i, regvalue = 0;
	DEBUGFUNC("igc_write_8bit_ctrl_reg_generic");
	regvalue = ((u32)data) | (offset << IGC_GEN_CTL_ADDRESS_SHIFT);
	IGC_WRITE_REG(hw, reg, regvalue);
	for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) {
		usec_delay(5);
		regvalue = IGC_READ_REG(hw, reg);
		if (regvalue & IGC_GEN_CTL_READY)
			break;
	}
	if (!(regvalue & IGC_GEN_CTL_READY)) {
		DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
		return -IGC_ERR_PHY;
	}
	return IGC_SUCCESS;
}
s32 igc_write_8bit_ctrl_reg_generic ( struct igc_hw * hw , u32 reg , u32 offset , u8 data ) { u32 i , regvalue = 0 ; DEBUGFUNC ( " " ) ; regvalue = ( ( u32 ) data ) | ( offset << IGC_GEN_CTL_ADDRESS_SHIFT ) ; IGC_WRITE_REG ( hw , reg , regvalue ) ; for ( i = 0 ; i < IGC_GEN_POLL_TIMEOUT ; i ++ ) { usec_delay ( 5 ) ; regvalue = IGC_READ_REG ( hw , reg ) ; if ( regvalue & IGC_GEN_CTL_READY ) break ; } if ( ! ( regvalue & IGC_GEN_CTL_READY ) ) { DEBUGOUT1 ( " \n " , reg ) ; return - IGC_ERR_PHY ; } return IGC_SUCCESS ; }
igc_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
  @hw: pointer to the HW structure
  @reg: 32bit register offset such as IGC_SCTL
  @offset: register offset to write to
  @data: data to write at register offset
igc_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register @hw : pointer to the HW structure @reg : 32bit register offset such as IGC_SCTL @offset : register offset to write to @data : data to write at register offset
/* Set up the address and data */ /* Poll the ready bit to see if the MDI read completed */