XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.c
static void XV_HScalerSetPhase(XV_Hscaler_l2 *HscPtr)
{
  u32 loopWidth;
  UINTPTR baseAddr;
  //program phases
  baseAddr = XV_hscaler_Get_HwReg_phasesH_V_BaseAddress(&HscPtr->Hsc);
  loopWidth = HscPtr->Hsc.Config.MaxWidth/HscPtr->Hsc.Config.PixPerClk;
  switch(HscPtr->Hsc.Config.PixPerClk)
  {
    case XVIDC_PPC_1:
            {
              u32 val, lsb, msb, index, i;

              /* PhaseH is 64bits but only lower 16b of each entry is valid
               * Form 32b word with 16bit LSB from 2 consecutive entries
               * Need 1 32b write to get 2 entries into IP registers
               * (i is array loc and index is address offset)
               */
              index = 0;
              for(i=0; i < loopWidth; i+=2)
              {
                lsb = (u32)(HscPtr->phasesH[i]   & (u64)XHSC_MASK_LOW_16BITS);
                msb = (u32)(HscPtr->phasesH[i+1] & (u64)XHSC_MASK_LOW_16BITS);
                val = (msb<<16 | lsb);
                Xil_Out32(baseAddr+(index*4), val);
                ++index;
              }
            }
            break;

    case XVIDC_PPC_2:
            {
              u32 val, i;

              /* PhaseH is 64bits but only lower 32b of each entry is valid
               * Need 1 32b write to get each entry into IP registers
               */
              for(i=0; i < loopWidth; ++i)
              {
                val = (u32)(HscPtr->phasesH[i] & XHSC_MASK_LOW_32BITS);
                Xil_Out32(baseAddr+(i*4), val);
              }
            }
            break;

    case XVIDC_PPC_4:
            {
              u32 lsb, msb, index, offset, i;
              u64 phaseHData;

              /* PhaseH is 64bits and each entry has valid 32b MSB & LSB
               * Need 2 32b writes to get each entry into IP registers
               * (index is array loc and offset is address offset)
               */
              index = 0;
              offset = 0;
              for(i=0; i < loopWidth; ++i)
              {
                phaseHData = HscPtr->phasesH[index];
                lsb = (u32)(phaseHData & XHSC_MASK_LOW_32BITS);
                msb = (u32)((phaseHData>>32) & XHSC_MASK_LOW_32BITS);
                Xil_Out32(baseAddr+(offset*4), lsb);
                Xil_Out32(baseAddr+((offset+1)*4), msb);
                ++index;
                offset += 2;
              }
            }
            break;
    case XVIDC_PPC_8:
	    {
		u32 bits_0_31, bits_32_63, bits_64_95;
		u32 index, offset, i;
		u64 phaseHData, phaseHData_H;
		/*
		 * PhaseH and PhaseH_H are 64bits and each entry has valid 44
		 * bits. PhaseH has lower 44 bits and PhaseH_H has higer 44 bits
		 * Need to form 3 32b writes form the total 88 bits, and
		 * write each 32bits into IP registers.
		 * (index is array loc and offset is address offset)
		 */
		index = 0;
		offset = 0;
		for(i=0; i < loopWidth; i++) {
			bits_0_31 = 0;
			bits_32_63 = 0;
			bits_64_95 = 0;
			phaseHData = HscPtr->phasesH[index];
			phaseHData_H = HscPtr->phasesH_H[index];

			bits_0_31 = (u32)(phaseHData & XHSC_MASK_LOW_32BITS);
			bits_32_63 = (u32)((phaseHData>>32) & XHSC_MASK_LOW_32BITS);
			bits_32_63 |= ((u32)((phaseHData_H & XHSC_MASK_LOW_20BITS)) << 12);
			bits_64_95 = (((u32)(phaseHData_H & XHSC_MASK_LOW_32BITS)) >> 20);
			bits_64_95 |= (((u32)(phaseHData_H>>32) & XHSC_MASK_LOW_12BITS) << 12);
			Xil_Out32(baseAddr+(offset*4), bits_0_31);
			Xil_Out32(baseAddr+((offset+1)*4), bits_32_63);
			Xil_Out32(baseAddr+((offset+2)*4), bits_64_95);
			/*(offset+3)*4 register is reserved,so increment offset by 4*/
			offset += 4;
			index++;
		}
	    }
	    break;


    default:
           break;
  }
}
/*****************************************************************************/
/**
* This function programs the phase data into core registers
*
* @param  HscPtr is a pointer to the core instance to be worked on.
*
* @return None
*
* @Note  This version of driver does not make use of computed coefficients.
*        User must load the coefficients, using the provided API, before
*        scaler can be used
******************************************************************************/
This function programs the phase data into core registers
This function programs the phase data into core registers
static void XV_HScalerSetPhase(XV_Hscaler_l2 *HscPtr)
{
  u32 loopWidth;
  UINTPTR baseAddr;
  baseAddr = XV_hscaler_Get_HwReg_phasesH_V_BaseAddress(&HscPtr->Hsc);
  loopWidth = HscPtr->Hsc.Config.MaxWidth/HscPtr->Hsc.Config.PixPerClk;
  switch(HscPtr->Hsc.Config.PixPerClk)
  {
    case XVIDC_PPC_1:
            {
              u32 val, lsb, msb, index, i;
              index = 0;
              for(i=0; i < loopWidth; i+=2)
              {
                lsb = (u32)(HscPtr->phasesH[i]   & (u64)XHSC_MASK_LOW_16BITS);
                msb = (u32)(HscPtr->phasesH[i+1] & (u64)XHSC_MASK_LOW_16BITS);
                val = (msb<<16 | lsb);
                Xil_Out32(baseAddr+(index*4), val);
                ++index;
              }
            }
            break;
    case XVIDC_PPC_2:
            {
              u32 val, i;
              for(i=0; i < loopWidth; ++i)
              {
                val = (u32)(HscPtr->phasesH[i] & XHSC_MASK_LOW_32BITS);
                Xil_Out32(baseAddr+(i*4), val);
              }
            }
            break;
    case XVIDC_PPC_4:
            {
              u32 lsb, msb, index, offset, i;
              u64 phaseHData;
              index = 0;
              offset = 0;
              for(i=0; i < loopWidth; ++i)
              {
                phaseHData = HscPtr->phasesH[index];
                lsb = (u32)(phaseHData & XHSC_MASK_LOW_32BITS);
                msb = (u32)((phaseHData>>32) & XHSC_MASK_LOW_32BITS);
                Xil_Out32(baseAddr+(offset*4), lsb);
                Xil_Out32(baseAddr+((offset+1)*4), msb);
                ++index;
                offset += 2;
              }
            }
            break;
    case XVIDC_PPC_8:
	    {
		u32 bits_0_31, bits_32_63, bits_64_95;
		u32 index, offset, i;
		u64 phaseHData, phaseHData_H;
		index = 0;
		offset = 0;
		for(i=0; i < loopWidth; i++) {
			bits_0_31 = 0;
			bits_32_63 = 0;
			bits_64_95 = 0;
			phaseHData = HscPtr->phasesH[index];
			phaseHData_H = HscPtr->phasesH_H[index];
			bits_0_31 = (u32)(phaseHData & XHSC_MASK_LOW_32BITS);
			bits_32_63 = (u32)((phaseHData>>32) & XHSC_MASK_LOW_32BITS);
			bits_32_63 |= ((u32)((phaseHData_H & XHSC_MASK_LOW_20BITS)) << 12);
			bits_64_95 = (((u32)(phaseHData_H & XHSC_MASK_LOW_32BITS)) >> 20);
			bits_64_95 |= (((u32)(phaseHData_H>>32) & XHSC_MASK_LOW_12BITS) << 12);
			Xil_Out32(baseAddr+(offset*4), bits_0_31);
			Xil_Out32(baseAddr+((offset+1)*4), bits_32_63);
			Xil_Out32(baseAddr+((offset+2)*4), bits_64_95);
			offset += 4;
			index++;
		}
	    }
	    break;
    default:
           break;
  }
}
static void XV_HScalerSetPhase ( XV_Hscaler_l2 * HscPtr ) { u32 loopWidth ; UINTPTR baseAddr ; baseAddr = XV_hscaler_Get_HwReg_phasesH_V_BaseAddress ( & HscPtr -> Hsc ) ; loopWidth = HscPtr -> Hsc . Config . MaxWidth / HscPtr -> Hsc . Config . PixPerClk ; switch ( HscPtr -> Hsc . Config . PixPerClk ) { case XVIDC_PPC_1 : { u32 val , lsb , msb , index , i ; index = 0 ; for ( i = 0 ; i < loopWidth ; i += 2 ) { lsb = ( u32 ) ( HscPtr -> phasesH [ i ] & ( u64 ) XHSC_MASK_LOW_16BITS ) ; msb = ( u32 ) ( HscPtr -> phasesH [ i + 1 ] & ( u64 ) XHSC_MASK_LOW_16BITS ) ; val = ( msb << 16 | lsb ) ; Xil_Out32 ( baseAddr + ( index * 4 ) , val ) ; ++ index ; } } break ; case XVIDC_PPC_2 : { u32 val , i ; for ( i = 0 ; i < loopWidth ; ++ i ) { val = ( u32 ) ( HscPtr -> phasesH [ i ] & XHSC_MASK_LOW_32BITS ) ; Xil_Out32 ( baseAddr + ( i * 4 ) , val ) ; } } break ; case XVIDC_PPC_4 : { u32 lsb , msb , index , offset , i ; u64 phaseHData ; index = 0 ; offset = 0 ; for ( i = 0 ; i < loopWidth ; ++ i ) { phaseHData = HscPtr -> phasesH [ index ] ; lsb = ( u32 ) ( phaseHData & XHSC_MASK_LOW_32BITS ) ; msb = ( u32 ) ( ( phaseHData >> 32 ) & XHSC_MASK_LOW_32BITS ) ; Xil_Out32 ( baseAddr + ( offset * 4 ) , lsb ) ; Xil_Out32 ( baseAddr + ( ( offset + 1 ) * 4 ) , msb ) ; ++ index ; offset += 2 ; } } break ; case XVIDC_PPC_8 : { u32 bits_0_31 , bits_32_63 , bits_64_95 ; u32 index , offset , i ; u64 phaseHData , phaseHData_H ; index = 0 ; offset = 0 ; for ( i = 0 ; i < loopWidth ; i ++ ) { bits_0_31 = 0 ; bits_32_63 = 0 ; bits_64_95 = 0 ; phaseHData = HscPtr -> phasesH [ index ] ; phaseHData_H = HscPtr -> phasesH_H [ index ] ; bits_0_31 = ( u32 ) ( phaseHData & XHSC_MASK_LOW_32BITS ) ; bits_32_63 = ( u32 ) ( ( phaseHData >> 32 ) & XHSC_MASK_LOW_32BITS ) ; bits_32_63 |= ( ( u32 ) ( ( phaseHData_H & XHSC_MASK_LOW_20BITS ) ) << 12 ) ; bits_64_95 = ( ( ( u32 ) ( phaseHData_H & XHSC_MASK_LOW_32BITS ) ) >> 20 ) ; bits_64_95 |= ( ( ( u32 ) ( phaseHData_H >> 32 ) & XHSC_MASK_LOW_12BITS ) << 12 ) ; Xil_Out32 ( baseAddr + ( offset * 4 ) , bits_0_31 ) ; Xil_Out32 ( baseAddr + ( ( offset + 1 ) * 4 ) , bits_32_63 ) ; Xil_Out32 ( baseAddr + ( ( offset + 2 ) * 4 ) , bits_64_95 ) ; offset += 4 ; index ++ ; } } break ; default : break ; } }
This function programs the phase data into core registers
This function programs the phase data into core registers
//program phases /* PhaseH is 64bits but only lower 16b of each entry is valid
               * Form 32b word with 16bit LSB from 2 consecutive entries
               * Need 1 32b write to get 2 entries into IP registers
               * (i is array loc and index is address offset)
               */ /* PhaseH is 64bits but only lower 32b of each entry is valid
               * Need 1 32b write to get each entry into IP registers
               */ /* PhaseH is 64bits and each entry has valid 32b MSB & LSB
               * Need 2 32b writes to get each entry into IP registers
               * (index is array loc and offset is address offset)
               */ /*
		 * PhaseH and PhaseH_H are 64bits and each entry has valid 44
		 * bits. PhaseH has lower 44 bits and PhaseH_H has higer 44 bits
		 * Need to form 3 32b writes form the total 88 bits, and
		 * write each 32bits into IP registers.
		 * (index is array loc and offset is address offset)
		 */ /*(offset+3)*4 register is reserved,so increment offset by 4*/