src/dpdk/drivers/net/mlx5/mlx5_txq.c
static void
txq_sync_cq(struct mlx5_txq_data *txq)
{
	volatile struct mlx5_cqe *cqe;
	int ret, i;

	i = txq->cqe_s;
	do {
		cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
		ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
		if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
			if (likely(ret != MLX5_CQE_STATUS_ERR)) {
				/* No new CQEs in completion queue. */
				MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
				break;
			}
		}
		++txq->cq_ci;
	} while (--i);
	/* Move all CQEs to HW ownership. */
	for (i = 0; i < txq->cqe_s; i++) {
		cqe = &txq->cqes[i];
		cqe->op_own = MLX5_CQE_INVALIDATE;
	}
	/* Resync CQE and WQE (WQ in reset state). */
	rte_io_wmb();
	*txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
	txq->cq_pi = txq->cq_ci;
	rte_io_wmb();
}
/* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */
Fetches and drops all SW-owned and error CQEs to synchronize CQ.
Fetches and drops all SW - owned and error CQEs to synchronize CQ .
static void
txq_sync_cq(struct mlx5_txq_data *txq)
{
	volatile struct mlx5_cqe *cqe;
	int ret, i;
	i = txq->cqe_s;
	do {
		cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
		ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
		if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
			if (likely(ret != MLX5_CQE_STATUS_ERR)) {
				MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
				break;
			}
		}
		++txq->cq_ci;
	} while (--i);
	for (i = 0; i < txq->cqe_s; i++) {
		cqe = &txq->cqes[i];
		cqe->op_own = MLX5_CQE_INVALIDATE;
	}
	rte_io_wmb();
	*txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
	txq->cq_pi = txq->cq_ci;
	rte_io_wmb();
}
static void txq_sync_cq ( struct mlx5_txq_data * txq ) { volatile struct mlx5_cqe * cqe ; int ret , i ; i = txq -> cqe_s ; do { cqe = & txq -> cqes [ txq -> cq_ci & txq -> cqe_m ] ; ret = check_cqe ( cqe , txq -> cqe_s , txq -> cq_ci ) ; if ( unlikely ( ret != MLX5_CQE_STATUS_SW_OWN ) ) { if ( likely ( ret != MLX5_CQE_STATUS_ERR ) ) { MLX5_ASSERT ( ret == MLX5_CQE_STATUS_HW_OWN ) ; break ; } } ++ txq -> cq_ci ; } while ( -- i ) ; for ( i = 0 ; i < txq -> cqe_s ; i ++ ) { cqe = & txq -> cqes [ i ] ; cqe -> op_own = MLX5_CQE_INVALIDATE ; } rte_io_wmb ( ) ; * txq -> cq_db = rte_cpu_to_be_32 ( txq -> cq_ci ) ; txq -> cq_pi = txq -> cq_ci ; rte_io_wmb ( ) ; }
Fetches and drops all SW-owned and error CQEs to synchronize CQ.
Fetches and drops all SW - owned and error CQEs to synchronize CQ .
/* No new CQEs in completion queue. */ /* Move all CQEs to HW ownership. */ /* Resync CQE and WQE (WQ in reset state). */