lib/sw_apps/zynqmp_fsbl/src/xfsbl_ddr_init.c
static u32 XFsbl_PhyCalcLpddr3RegVal(XFsbl_DimmParams *PDimmPtr, u32 *PhyCfg)
{
	u32 Val;

	Val = (u32)(((PDimmPtr->TRefi / 1000.0) / PDimmPtr->ClockPeriod));
	if (PDimmPtr->PerBankRefresh == 0U) {
		if (PDimmPtr->Capacity != 1024U) {
			Val /= 2U;
		}
	} else {
		if (PDimmPtr->Capacity >= 2048U) {
			Val = (u32)((487.5 / PDimmPtr->ClockPeriod));
		} else if (PDimmPtr->Capacity == 1024U) {
			Val = (u32)((975.0 / PDimmPtr->ClockPeriod));
		}
	}
	if (PDimmPtr->TRefRange) {
		Val /= 4U;
	}
	PhyCfg[PHY_TREFPRD] = (8U * Val) - 1000U;

	PhyCfg[PHY_NOSRA] = 0x1U;

	PhyCfg[PHY_DDRMD] = 0x1U;

	PhyCfg[PHY_TRRD] = (u32)XFSBL_MAX(XFsbl_Ceil(10.0 / PDimmPtr->ClockPeriod), 2U) + (1.875 * PDimmPtr->TRefRange);

	PhyCfg[PHY_TRTP] =  PDimmPtr->BurstLength / 2U + XFSBL_MAX((u32)XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod), 4U) - 4U;

	PhyCfg[PHY_TMRD] = XFSBL_MIN(((u32)XFsbl_Ceil((XFSBL_MAX(10U, 15U / PDimmPtr->ClockPeriod)) / 2.0)) * 2U, 32U);

	PhyCfg[PHY_TXS] = (u32)XFsbl_Ceil(XFSBL_MAX(2.0, ((PDimmPtr->TRfcPs / 1000.0) + 10U) / PDimmPtr->ClockPeriod));

	PhyCfg[PHY_TDQSCKMAX] = 0x5U;

	PhyCfg[PHY_TDQSCK] = (u32)(1.5 / PDimmPtr->ClockPeriod);

	PhyCfg[PHY_TXP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp), 31U);

	PhyCfg[PHY_TRCD] = (PDimmPtr->TRcdPs / 1000.0) - PDimmPtr->AdditiveLatency + 2U;

	PhyCfg[PHY_R061] = PDimmPtr->Mr;

	PhyCfg[PHY_R062] = PDimmPtr->Emr;

	PhyCfg[PHY_R063] = PDimmPtr->Emr2;

	PhyCfg[PHY_DQODT] = (PDimmPtr->DramOdt == 240U) ? 3U : 2U;

	if ((PDimmPtr->AddrMirror == 1U) && (PDimmPtr->DramWidth == 16U)) {
		PhyCfg[PHY_CA1BYTE1] = 3U;
	}

	if ((PDimmPtr->AddrMirror == 1U) && (PDimmPtr->DramWidth == 16U)) {
		PhyCfg[PHY_CA1BYTE0] = 2U;
	}

	if (PDimmPtr->En2ndClk) {
		PhyCfg[PHY_CKOEMODE] = 0x5U;

		PhyCfg[PHY_CKNCLKGATE0] = 0x0U;

		PhyCfg[PHY_CKCLKGATE0] = 0x0U;

		PhyCfg[PHY_CKNCLKGATE1] = 0x0U;

		PhyCfg[PHY_CKCLKGATE1] = 0x0U;
	} else {
		PhyCfg[PHY_CKOEMODE] = ((1U - PDimmPtr->NumRankAddr) * 4U) + 5U;

		PhyCfg[PHY_CKNCLKGATE0] = (1U - PDimmPtr->NumRankAddr) * 0x2U;

		PhyCfg[PHY_CKCLKGATE0] = PhyCfg[PHY_CKNCLKGATE0];

		PhyCfg[PHY_CKNCLKGATE1] = PhyCfg[PHY_CKNCLKGATE0];

		PhyCfg[PHY_CKCLKGATE1] = PhyCfg[PHY_CKNCLKGATE0];
	}

	PhyCfg[PHY_ACREFSSEL] = 0x30U;

	PhyCfg[PHY_ACVREFISEL] = 0x30U;

	PhyCfg[PHY_PDAEN] = 0x0U;

	if (PDimmPtr->Zc1656 || PDimmPtr->HasEccComp) {
		PhyCfg[PHY_DVINIT] = 0x2EU;
	} else {
		if (PDimmPtr->Lp4NoOdt) {
			PhyCfg[PHY_DVINIT] = 0x2FU;
		} else {
			PhyCfg[PHY_DVINIT] = 0x19U;
		}
	}

	PhyCfg[PHY_ACTBD] = 4U;

	PhyCfg[PHY_BG1BD] = 4U;

	PhyCfg[PHY_BG0BD] = 4U;

	PhyCfg[PHY_BA1BD] = 4U;

	PhyCfg[PHY_BA0BD] = 4U;

	PhyCfg[PHY_A03BD] = 4U;

	PhyCfg[PHY_A02BD] = 4U;

	PhyCfg[PHY_A01BD] = 4U;

	PhyCfg[PHY_A00BD] = 4U;

	PhyCfg[PHY_A07BD] = 4U;

	PhyCfg[PHY_A06BD] = 4U;

	PhyCfg[PHY_A05BD] = 4U;

	PhyCfg[PHY_A04BD] = 4U;

	PhyCfg[PHY_A11BD] = 4U;

	PhyCfg[PHY_A10BD] = 4U;

	PhyCfg[PHY_A09BD] = 4U;

	PhyCfg[PHY_A08BD] = 4U;

	PhyCfg[PHY_A15BD] = 4U;

	PhyCfg[PHY_A14BD] = 4U;

	PhyCfg[PHY_A13BD] = 4U;

	PhyCfg[PHY_A12BD] = 4U;

	PhyCfg[PHY_ODT_MODE] = 0x1U;

	PhyCfg[PHY_ZPROG_DRAM_ODT] = 0x7U;

	PhyCfg[PHY_ZPROG_HOST_ODT] = 7U;

	PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xBU;

	PhyCfg[PHY_ZPROG_ASYM_DRV_PU] = 0xBU;

	PhyCfg[PHY_DXREFSSEL] = 0x30U;

	PhyCfg[PHY_DXREFIEN] = 0x3U;

	PhyCfg[PHY_DXREFISELR1] = 0x3FU;

	PhyCfg[PHY_DXREFISELR0] = 0x3FU;

	return XFSBL_SUCCESS;
}
/*****************************************************************************/
/**
 * This function calculates the PHY register values for LPDDR3
 *
 * @param	PDimmPtr is pointer to DIMM parameters Data Structure
 * @param	PhyCfg is the array to store register field values
 *
 * @return	XFSBL_SUCCESS or XFSBL_FAILURE
 *
 *****************************************************************************/
This function calculates the PHY register values for LPDDR3
@param       PDimmPtr is pointer to DIMM parameters Data Structure
@param       PhyCfg is the array to store register field values


This function calculates the PHY register values for LPDDR3 @param PDimmPtr is pointer to DIMM parameters Data Structure @param PhyCfg is the array to store register field values
static u32 XFsbl_PhyCalcLpddr3RegVal(XFsbl_DimmParams *PDimmPtr, u32 *PhyCfg)
{
	u32 Val;
	Val = (u32)(((PDimmPtr->TRefi / 1000.0) / PDimmPtr->ClockPeriod));
	if (PDimmPtr->PerBankRefresh == 0U) {
		if (PDimmPtr->Capacity != 1024U) {
			Val /= 2U;
		}
	} else {
		if (PDimmPtr->Capacity >= 2048U) {
			Val = (u32)((487.5 / PDimmPtr->ClockPeriod));
		} else if (PDimmPtr->Capacity == 1024U) {
			Val = (u32)((975.0 / PDimmPtr->ClockPeriod));
		}
	}
	if (PDimmPtr->TRefRange) {
		Val /= 4U;
	}
	PhyCfg[PHY_TREFPRD] = (8U * Val) - 1000U;
	PhyCfg[PHY_NOSRA] = 0x1U;
	PhyCfg[PHY_DDRMD] = 0x1U;
	PhyCfg[PHY_TRRD] = (u32)XFSBL_MAX(XFsbl_Ceil(10.0 / PDimmPtr->ClockPeriod), 2U) + (1.875 * PDimmPtr->TRefRange);
	PhyCfg[PHY_TRTP] =  PDimmPtr->BurstLength / 2U + XFSBL_MAX((u32)XFsbl_Ceil(7.5 / PDimmPtr->ClockPeriod), 4U) - 4U;
	PhyCfg[PHY_TMRD] = XFSBL_MIN(((u32)XFsbl_Ceil((XFSBL_MAX(10U, 15U / PDimmPtr->ClockPeriod)) / 2.0)) * 2U, 32U);
	PhyCfg[PHY_TXS] = (u32)XFsbl_Ceil(XFSBL_MAX(2.0, ((PDimmPtr->TRfcPs / 1000.0) + 10U) / PDimmPtr->ClockPeriod));
	PhyCfg[PHY_TDQSCKMAX] = 0x5U;
	PhyCfg[PHY_TDQSCK] = (u32)(1.5 / PDimmPtr->ClockPeriod);
	PhyCfg[PHY_TXP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp), 31U);
	PhyCfg[PHY_TRCD] = (PDimmPtr->TRcdPs / 1000.0) - PDimmPtr->AdditiveLatency + 2U;
	PhyCfg[PHY_R061] = PDimmPtr->Mr;
	PhyCfg[PHY_R062] = PDimmPtr->Emr;
	PhyCfg[PHY_R063] = PDimmPtr->Emr2;
	PhyCfg[PHY_DQODT] = (PDimmPtr->DramOdt == 240U) ? 3U : 2U;
	if ((PDimmPtr->AddrMirror == 1U) && (PDimmPtr->DramWidth == 16U)) {
		PhyCfg[PHY_CA1BYTE1] = 3U;
	}
	if ((PDimmPtr->AddrMirror == 1U) && (PDimmPtr->DramWidth == 16U)) {
		PhyCfg[PHY_CA1BYTE0] = 2U;
	}
	if (PDimmPtr->En2ndClk) {
		PhyCfg[PHY_CKOEMODE] = 0x5U;
		PhyCfg[PHY_CKNCLKGATE0] = 0x0U;
		PhyCfg[PHY_CKCLKGATE0] = 0x0U;
		PhyCfg[PHY_CKNCLKGATE1] = 0x0U;
		PhyCfg[PHY_CKCLKGATE1] = 0x0U;
	} else {
		PhyCfg[PHY_CKOEMODE] = ((1U - PDimmPtr->NumRankAddr) * 4U) + 5U;
		PhyCfg[PHY_CKNCLKGATE0] = (1U - PDimmPtr->NumRankAddr) * 0x2U;
		PhyCfg[PHY_CKCLKGATE0] = PhyCfg[PHY_CKNCLKGATE0];
		PhyCfg[PHY_CKNCLKGATE1] = PhyCfg[PHY_CKNCLKGATE0];
		PhyCfg[PHY_CKCLKGATE1] = PhyCfg[PHY_CKNCLKGATE0];
	}
	PhyCfg[PHY_ACREFSSEL] = 0x30U;
	PhyCfg[PHY_ACVREFISEL] = 0x30U;
	PhyCfg[PHY_PDAEN] = 0x0U;
	if (PDimmPtr->Zc1656 || PDimmPtr->HasEccComp) {
		PhyCfg[PHY_DVINIT] = 0x2EU;
	} else {
		if (PDimmPtr->Lp4NoOdt) {
			PhyCfg[PHY_DVINIT] = 0x2FU;
		} else {
			PhyCfg[PHY_DVINIT] = 0x19U;
		}
	}
	PhyCfg[PHY_ACTBD] = 4U;
	PhyCfg[PHY_BG1BD] = 4U;
	PhyCfg[PHY_BG0BD] = 4U;
	PhyCfg[PHY_BA1BD] = 4U;
	PhyCfg[PHY_BA0BD] = 4U;
	PhyCfg[PHY_A03BD] = 4U;
	PhyCfg[PHY_A02BD] = 4U;
	PhyCfg[PHY_A01BD] = 4U;
	PhyCfg[PHY_A00BD] = 4U;
	PhyCfg[PHY_A07BD] = 4U;
	PhyCfg[PHY_A06BD] = 4U;
	PhyCfg[PHY_A05BD] = 4U;
	PhyCfg[PHY_A04BD] = 4U;
	PhyCfg[PHY_A11BD] = 4U;
	PhyCfg[PHY_A10BD] = 4U;
	PhyCfg[PHY_A09BD] = 4U;
	PhyCfg[PHY_A08BD] = 4U;
	PhyCfg[PHY_A15BD] = 4U;
	PhyCfg[PHY_A14BD] = 4U;
	PhyCfg[PHY_A13BD] = 4U;
	PhyCfg[PHY_A12BD] = 4U;
	PhyCfg[PHY_ODT_MODE] = 0x1U;
	PhyCfg[PHY_ZPROG_DRAM_ODT] = 0x7U;
	PhyCfg[PHY_ZPROG_HOST_ODT] = 7U;
	PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xBU;
	PhyCfg[PHY_ZPROG_ASYM_DRV_PU] = 0xBU;
	PhyCfg[PHY_DXREFSSEL] = 0x30U;
	PhyCfg[PHY_DXREFIEN] = 0x3U;
	PhyCfg[PHY_DXREFISELR1] = 0x3FU;
	PhyCfg[PHY_DXREFISELR0] = 0x3FU;
	return XFSBL_SUCCESS;
}
static u32 XFsbl_PhyCalcLpddr3RegVal ( XFsbl_DimmParams * PDimmPtr , u32 * PhyCfg ) { u32 Val ; Val = ( u32 ) ( ( ( PDimmPtr -> TRefi / 1000.0 ) / PDimmPtr -> ClockPeriod ) ) ; if ( PDimmPtr -> PerBankRefresh == 0U ) { if ( PDimmPtr -> Capacity != 1024U ) { Val /= 2U ; } } else { if ( PDimmPtr -> Capacity >= 2048U ) { Val = ( u32 ) ( ( 487.5 / PDimmPtr -> ClockPeriod ) ) ; } else if ( PDimmPtr -> Capacity == 1024U ) { Val = ( u32 ) ( ( 975.0 / PDimmPtr -> ClockPeriod ) ) ; } } if ( PDimmPtr -> TRefRange ) { Val /= 4U ; } PhyCfg [ PHY_TREFPRD ] = ( 8U * Val ) - 1000U ; PhyCfg [ PHY_NOSRA ] = 0x1U ; PhyCfg [ PHY_DDRMD ] = 0x1U ; PhyCfg [ PHY_TRRD ] = ( u32 ) XFSBL_MAX ( XFsbl_Ceil ( 10.0 / PDimmPtr -> ClockPeriod ) , 2U ) + ( 1.875 * PDimmPtr -> TRefRange ) ; PhyCfg [ PHY_TRTP ] = PDimmPtr -> BurstLength / 2U + XFSBL_MAX ( ( u32 ) XFsbl_Ceil ( 7.5 / PDimmPtr -> ClockPeriod ) , 4U ) - 4U ; PhyCfg [ PHY_TMRD ] = XFSBL_MIN ( ( ( u32 ) XFsbl_Ceil ( ( XFSBL_MAX ( 10U , 15U / PDimmPtr -> ClockPeriod ) ) / 2.0 ) ) * 2U , 32U ) ; PhyCfg [ PHY_TXS ] = ( u32 ) XFsbl_Ceil ( XFSBL_MAX ( 2.0 , ( ( PDimmPtr -> TRfcPs / 1000.0 ) + 10U ) / PDimmPtr -> ClockPeriod ) ) ; PhyCfg [ PHY_TDQSCKMAX ] = 0x5U ; PhyCfg [ PHY_TDQSCK ] = ( u32 ) ( 1.5 / PDimmPtr -> ClockPeriod ) ; PhyCfg [ PHY_TXP ] = ( u32 ) XFSBL_MIN ( XFsbl_Ceil ( PDimmPtr -> TXp ) , 31U ) ; PhyCfg [ PHY_TRCD ] = ( PDimmPtr -> TRcdPs / 1000.0 ) - PDimmPtr -> AdditiveLatency + 2U ; PhyCfg [ PHY_R061 ] = PDimmPtr -> Mr ; PhyCfg [ PHY_R062 ] = PDimmPtr -> Emr ; PhyCfg [ PHY_R063 ] = PDimmPtr -> Emr2 ; PhyCfg [ PHY_DQODT ] = ( PDimmPtr -> DramOdt == 240U ) ? 3U : 2U ; if ( ( PDimmPtr -> AddrMirror == 1U ) && ( PDimmPtr -> DramWidth == 16U ) ) { PhyCfg [ PHY_CA1BYTE1 ] = 3U ; } if ( ( PDimmPtr -> AddrMirror == 1U ) && ( PDimmPtr -> DramWidth == 16U ) ) { PhyCfg [ PHY_CA1BYTE0 ] = 2U ; } if ( PDimmPtr -> En2ndClk ) { PhyCfg [ PHY_CKOEMODE ] = 0x5U ; PhyCfg [ PHY_CKNCLKGATE0 ] = 0x0U ; PhyCfg [ PHY_CKCLKGATE0 ] = 0x0U ; PhyCfg [ PHY_CKNCLKGATE1 ] = 0x0U ; PhyCfg [ PHY_CKCLKGATE1 ] = 0x0U ; } else { PhyCfg [ PHY_CKOEMODE ] = ( ( 1U - PDimmPtr -> NumRankAddr ) * 4U ) + 5U ; PhyCfg [ PHY_CKNCLKGATE0 ] = ( 1U - PDimmPtr -> NumRankAddr ) * 0x2U ; PhyCfg [ PHY_CKCLKGATE0 ] = PhyCfg [ PHY_CKNCLKGATE0 ] ; PhyCfg [ PHY_CKNCLKGATE1 ] = PhyCfg [ PHY_CKNCLKGATE0 ] ; PhyCfg [ PHY_CKCLKGATE1 ] = PhyCfg [ PHY_CKNCLKGATE0 ] ; } PhyCfg [ PHY_ACREFSSEL ] = 0x30U ; PhyCfg [ PHY_ACVREFISEL ] = 0x30U ; PhyCfg [ PHY_PDAEN ] = 0x0U ; if ( PDimmPtr -> Zc1656 || PDimmPtr -> HasEccComp ) { PhyCfg [ PHY_DVINIT ] = 0x2EU ; } else { if ( PDimmPtr -> Lp4NoOdt ) { PhyCfg [ PHY_DVINIT ] = 0x2FU ; } else { PhyCfg [ PHY_DVINIT ] = 0x19U ; } } PhyCfg [ PHY_ACTBD ] = 4U ; PhyCfg [ PHY_BG1BD ] = 4U ; PhyCfg [ PHY_BG0BD ] = 4U ; PhyCfg [ PHY_BA1BD ] = 4U ; PhyCfg [ PHY_BA0BD ] = 4U ; PhyCfg [ PHY_A03BD ] = 4U ; PhyCfg [ PHY_A02BD ] = 4U ; PhyCfg [ PHY_A01BD ] = 4U ; PhyCfg [ PHY_A00BD ] = 4U ; PhyCfg [ PHY_A07BD ] = 4U ; PhyCfg [ PHY_A06BD ] = 4U ; PhyCfg [ PHY_A05BD ] = 4U ; PhyCfg [ PHY_A04BD ] = 4U ; PhyCfg [ PHY_A11BD ] = 4U ; PhyCfg [ PHY_A10BD ] = 4U ; PhyCfg [ PHY_A09BD ] = 4U ; PhyCfg [ PHY_A08BD ] = 4U ; PhyCfg [ PHY_A15BD ] = 4U ; PhyCfg [ PHY_A14BD ] = 4U ; PhyCfg [ PHY_A13BD ] = 4U ; PhyCfg [ PHY_A12BD ] = 4U ; PhyCfg [ PHY_ODT_MODE ] = 0x1U ; PhyCfg [ PHY_ZPROG_DRAM_ODT ] = 0x7U ; PhyCfg [ PHY_ZPROG_HOST_ODT ] = 7U ; PhyCfg [ PHY_ZPROG_ASYM_DRV_PD ] = 0xBU ; PhyCfg [ PHY_ZPROG_ASYM_DRV_PU ] = 0xBU ; PhyCfg [ PHY_DXREFSSEL ] = 0x30U ; PhyCfg [ PHY_DXREFIEN ] = 0x3U ; PhyCfg [ PHY_DXREFISELR1 ] = 0x3FU ; PhyCfg [ PHY_DXREFISELR0 ] = 0x3FU ; return XFSBL_SUCCESS ; }
This function calculates the PHY register values for LPDDR3
 @param       PDimmPtr is pointer to DIMM parameters Data Structure
 @param       PhyCfg is the array to store register field values
This function calculates the PHY register values for LPDDR3 @param PDimmPtr is pointer to DIMM parameters Data Structure @param PhyCfg is the array to store register field values