XilinxProcessorIPLib/drivers/sysmonpsu/src/xsysmonpsu_intr.c
void XSysMonPsu_IntrClear(XSysMonPsu *InstancePtr, u64 Mask)
{
	u64 RegValue;

	/* Assert the arguments. */
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/* Clear the specified interrupts in the Interrupt Status register. */
	RegValue = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
					XSYSMONPSU_ISR_0_OFFSET);
	RegValue &= (Mask & (u64)XSYSMONPSU_IXR_0_MASK);
	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_ISR_0_OFFSET,
			  (u32)RegValue);

	RegValue = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
					XSYSMONPSU_ISR_1_OFFSET);
	RegValue &= ((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_ISR_1_OFFSET,
			  (u32)RegValue);
}
/****************************************************************************/
/**
*
* This function clears the specified interrupts in the Interrupt Status
* Register (ISR).
*
* @param	InstancePtr is a pointer to the XSysMonPsu instance.
* @param	Mask is the 64 bit-mask of the interrupts to be cleared.
*		Bit positions of 1 will be cleared. Bit positions of 0 will not
* 		change the previous interrupt status. This mask is formed by
* 		OR'ing the XSYSMONPSU_ISR_0_* and XSYSMONPSU_ISR_1_* bits
* 		which are defined in xsysmonpsu_hw.h.
*
* @return	None.
*
* @note		None.
*
*****************************************************************************/
This function clears the specified interrupts in the Interrupt Status
Register (ISR).
This function clears the specified interrupts in the Interrupt Status Register ( ISR ) .
void XSysMonPsu_IntrClear(XSysMonPsu *InstancePtr, u64 Mask)
{
	u64 RegValue;
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	RegValue = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
					XSYSMONPSU_ISR_0_OFFSET);
	RegValue &= (Mask & (u64)XSYSMONPSU_IXR_0_MASK);
	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_ISR_0_OFFSET,
			  (u32)RegValue);
	RegValue = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
					XSYSMONPSU_ISR_1_OFFSET);
	RegValue &= ((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_ISR_1_OFFSET,
			  (u32)RegValue);
}
void XSysMonPsu_IntrClear ( XSysMonPsu * InstancePtr , u64 Mask ) { u64 RegValue ; Xil_AssertVoid ( InstancePtr != NULL ) ; Xil_AssertVoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; RegValue = ( u64 ) XSysmonPsu_ReadReg ( InstancePtr -> Config . BaseAddress + XSYSMONPSU_ISR_0_OFFSET ) ; RegValue &= ( Mask & ( u64 ) XSYSMONPSU_IXR_0_MASK ) ; XSysmonPsu_WriteReg ( InstancePtr -> Config . BaseAddress + XSYSMONPSU_ISR_0_OFFSET , ( u32 ) RegValue ) ; RegValue = ( u64 ) XSysmonPsu_ReadReg ( InstancePtr -> Config . BaseAddress + XSYSMONPSU_ISR_1_OFFSET ) ; RegValue &= ( ( Mask >> XSYSMONPSU_IXR_1_SHIFT ) & XSYSMONPSU_IXR_1_MASK ) ; XSysmonPsu_WriteReg ( InstancePtr -> Config . BaseAddress + XSYSMONPSU_ISR_1_OFFSET , ( u32 ) RegValue ) ; }
This function clears the specified interrupts in the Interrupt Status
Register (ISR).
This function clears the specified interrupts in the Interrupt Status Register ( ISR ) .
/* Assert the arguments. */ /* Clear the specified interrupts in the Interrupt Status register. */