base/serial.c
void Synchronous_Init()
{
#if defined (PIN_RESET)
   // Go int RESET
   SYSTEM_RST_SEL &= ~SYSTEM_RST_BIT;           // Set as output
   SYSTEM_RST_DIR |= SYSTEM_RST_BIT;            // Set as output
   SYSTEM_RST_OUT &= ~SYSTEM_RST_BIT;           // Set low to reset module 
#endif

   // Set configuration pins
   SERIAL_IOSEL_SEL &= ~SERIAL_IOSEL_BIT;       // Set as output
   SERIAL_IOSEL_DIR |= SERIAL_IOSEL_BIT;        // Set as output
   SERIAL_IOSEL_OUT |= SERIAL_IOSEL_BIT;        // Serial, not SensRcore   

   SERIAL_PORTSEL_SEL &= ~SERIAL_PORTSEL_BIT;   // Set as output
   SERIAL_PORTSEL_DIR |= SERIAL_PORTSEL_BIT;    // Set as output
   SERIAL_PORTSEL_OUT |= SERIAL_PORTSEL_BIT;    // Port select HI for SYNC serial

   SERIAL_SFLOW_SEL &= ~SERIAL_SFLOW_BIT;       // Set as output
   SERIAL_SFLOW_DIR |= SERIAL_SFLOW_BIT;        // Set as output

#if defined(SERIAL_BIT_SYNCHRONOUS)
   SERIAL_SFLOW_OUT |= SERIAL_SFLOW_BIT;        // Select bit flow control
#else // SERIAL_BIT_SYNCHRONOUS
   SERIAL_SFLOW_OUT &= ~SERIAL_SFLOW_BIT;       // Select byte flow control
#endif // SERIAL_BYTE_SYNCHRONOUS      

   //
   // Set up serial pins
   //

#if defined(SERIAL_BIT_SYNCHRONOUS)
   SYNC_SIN_SEL &= ~SYNC_SIN_BIT;               // Enable SIN as GPIO
   SYNC_SOUT_SEL &= ~SYNC_SOUT_BIT;             // Enable SOUT as GPIO
   SYNC_SCLK_SEL &= ~SYNC_SCLK_BIT;             // Enable SCLK as GPIO
   SYNC_SCLK_IES &= ~SYNC_SCLK_BIT;             // interrupt on the low-to-high transition
   SYNC_SCLK_IFG &= ~SYNC_SCLK_BIT;             // clear the interrupt flag		
   SYNC_SCLK_IE |= SYNC_SCLK_BIT;               // Enable SCLK intterupt

#elif defined (SERIAL_BYTE_SYNCHRONOUS)
   // UCI Register Init
   BYTE_SYNC_UCI_CTL0 = UCCKPL | UCSYNC;        // Set UCI to synchronous with clock normally high           
   SYNC_SIN_SEL |= SYNC_SIN_BIT;                // Enable SIN to use UCI B0 SIMO pin
   SYNC_SOUT_SEL |= SYNC_SOUT_BIT;              // Enable SOUT to use UCI B0 SOMI pin
   SYNC_SCLK_SEL |= SYNC_SCLK_BIT;              // Enable the UCSCLK functionality

#endif 
   //   // SEN
   SYNC_SEN_DIR &= ~SYNC_SEN_BIT;               // set the direction to be an input

   // SMSGRDY
   SYNC_SMSGRDY_DIR |= SYNC_SMSGRDY_BIT;        // set SMSGRDY as an output
   SYNC_SMSGRDY_DEASSERT();                     // make sure it is deasserted so that it doesn't misguide ANT

   // SIN
   SYNC_SIN_DIR &= ~SYNC_SIN_BIT;               // set SIN as an input

   // SCLK
   SYNC_SCLK_DIR &= ~SYNC_SCLK_BIT;             // set SCLK as an input

   // SOUT
   SYNC_SOUT_DIR |= SYNC_SOUT_BIT;              // Set SOUT as an output

   // SRDY
   SYNC_SRDY_DIR |= SYNC_SRDY_BIT;              // set SRDY as an output
   SYNC_SRDY_DEASSERT();                        // put SRDY in a known state

#if defined (PIN_RESET)
   SYSTEM_RST_OUT |= SYSTEM_RST_BIT;            // ** Take ANT out of RESET **
   Timer_DelayTime(50000);                      // Delay for 500ms
#endif

#if defined (SYNCH_RESET)
   while(!Serial_SyncReset());                  // Do a synchronous reset
   SYNC_SMSGRDY_DEASSERT();                     // make sure it is deasserted so that it doesn't misguide ANT
#endif

#if defined(SERIAL_BYTE_SYNCHRONOUS) 
   BYTE_SYNC_UCI_CTL1 &= ~UCSWRST;              // Enable SPI
#endif     

   // Enable SEN interrupt
   SYNC_SEN_IES |= SYNC_SEN_BIT;                // interrupt on high-to-low transition
   SYNC_SEN_IFG &= ~SYNC_SEN_BIT;               // reset the interrupt flag
   SYNC_SEN_IE  |= SYNC_SEN_BIT;                // enable the SEN interrupt to allow wake up from sleep                                       

#if defined(SERIAL_BYTE_SYNCHRONOUS)   
   // Enable RECV interrupt
   BYTE_SYNC_UCI_IFR &= ~BYTE_SYNC_RX_INT;      // Enable RX interrupt only
   BYTE_SYNC_UCI_IER |= BYTE_SYNC_RX_INT;       // Enable RX interrupt only

   bTheGotByte = FALSE;
#endif

}
////////////////////////////////////////////////////////////////////////////
// Synchronous_Init
//
// Initialize the synchronous serial interface.
// - put ANT module into synch serial mode
// - reset module (RST pin if > AT3)
// - configure SPI and required gpio's
// - do synchronous reset
// 
////////////////////////////////////////////////////////////////////////////
Synchronous_Init
Initialize the synchronous serial interface.
put ANT module into synch serial mode
reset module (RST pin if > AT3)
configure SPI and required gpio's
do synchronous reset
Synchronous_Init Initialize the synchronous serial interface . put ANT module into synch serial mode reset module ( RST pin if > AT3 ) configure SPI and required gpio ' s do synchronous reset
void Synchronous_Init()
{
#if defined (PIN_RESET)
   SYSTEM_RST_SEL &= ~SYSTEM_RST_BIT;           
   SYSTEM_RST_DIR |= SYSTEM_RST_BIT;            
   SYSTEM_RST_OUT &= ~SYSTEM_RST_BIT;           
#endif
   SERIAL_IOSEL_SEL &= ~SERIAL_IOSEL_BIT;       
   SERIAL_IOSEL_DIR |= SERIAL_IOSEL_BIT;        
   SERIAL_IOSEL_OUT |= SERIAL_IOSEL_BIT;        
   SERIAL_PORTSEL_SEL &= ~SERIAL_PORTSEL_BIT;   
   SERIAL_PORTSEL_DIR |= SERIAL_PORTSEL_BIT;    
   SERIAL_PORTSEL_OUT |= SERIAL_PORTSEL_BIT;    
   SERIAL_SFLOW_SEL &= ~SERIAL_SFLOW_BIT;       
   SERIAL_SFLOW_DIR |= SERIAL_SFLOW_BIT;        
#if defined(SERIAL_BIT_SYNCHRONOUS)
   SERIAL_SFLOW_OUT |= SERIAL_SFLOW_BIT;        
#else 
   SERIAL_SFLOW_OUT &= ~SERIAL_SFLOW_BIT;       
#endif 
    Set up serial pins
#if defined(SERIAL_BIT_SYNCHRONOUS)
   SYNC_SIN_SEL &= ~SYNC_SIN_BIT;                Enable SIN as GPIO
   SYNC_SOUT_SEL &= ~SYNC_SOUT_BIT;              Enable SOUT as GPIO
   SYNC_SCLK_SEL &= ~SYNC_SCLK_BIT;              Enable SCLK as GPIO
   SYNC_SCLK_IES &= ~SYNC_SCLK_BIT;              interrupt on the low-to-high transition
   SYNC_SCLK_IFG &= ~SYNC_SCLK_BIT;              clear the interrupt flag		
   SYNC_SCLK_IE |= SYNC_SCLK_BIT;                Enable SCLK intterupt
#elif defined (SERIAL_BYTE_SYNCHRONOUS)
    UCI Register Init
   BYTE_SYNC_UCI_CTL0 = UCCKPL | UCSYNC;         Set UCI to synchronous with clock normally high           
   SYNC_SIN_SEL |= SYNC_SIN_BIT;                 Enable SIN to use UCI B0 SIMO pin
   SYNC_SOUT_SEL |= SYNC_SOUT_BIT;               Enable SOUT to use UCI B0 SOMI pin
   SYNC_SCLK_SEL |= SYNC_SCLK_BIT;               Enable the UCSCLK functionality
#endif 
       SEN
   SYNC_SEN_DIR &= ~SYNC_SEN_BIT;                set the direction to be an input
    SMSGRDY
   SYNC_SMSGRDY_DIR |= SYNC_SMSGRDY_BIT;         set SMSGRDY as an output
   SYNC_SMSGRDY_DEASSERT();                      make sure it is deasserted so that it doesn't misguide ANT
    SIN
   SYNC_SIN_DIR &= ~SYNC_SIN_BIT;                set SIN as an input
    SCLK
   SYNC_SCLK_DIR &= ~SYNC_SCLK_BIT;              set SCLK as an input
    SOUT
   SYNC_SOUT_DIR |= SYNC_SOUT_BIT;               Set SOUT as an output
    SRDY
   SYNC_SRDY_DIR |= SYNC_SRDY_BIT;               set SRDY as an output
   SYNC_SRDY_DEASSERT();                         put SRDY in a known state
#if defined (PIN_RESET)
   SYSTEM_RST_OUT |= SYSTEM_RST_BIT;             ** Take ANT out of RESET **
   Timer_DelayTime(50000);                       Delay for 500ms
#endif
#if defined (SYNCH_RESET)
   while(!Serial_SyncReset());                   Do a synchronous reset
   SYNC_SMSGRDY_DEASSERT();                      make sure it is deasserted so that it doesn't misguide ANT
#endif
#if defined(SERIAL_BYTE_SYNCHRONOUS) 
   BYTE_SYNC_UCI_CTL1 &= ~UCSWRST;               Enable SPI
#endif     
    Enable SEN interrupt
   SYNC_SEN_IES |= SYNC_SEN_BIT;                 interrupt on high-to-low transition
   SYNC_SEN_IFG &= ~SYNC_SEN_BIT;                reset the interrupt flag
   SYNC_SEN_IE  |= SYNC_SEN_BIT;                 enable the SEN interrupt to allow wake up from sleep                                       
#if defined(SERIAL_BYTE_SYNCHRONOUS)   
    Enable RECV interrupt
   BYTE_SYNC_UCI_IFR &= ~BYTE_SYNC_RX_INT;       Enable RX interrupt only
   BYTE_SYNC_UCI_IER |= BYTE_SYNC_RX_INT;        Enable RX interrupt only
   bTheGotByte = FALSE;
#endif
}
void Synchronous_Init ( ) { #if defined ( PIN_RESET ) SYSTEM_RST_SEL &= ~ SYSTEM_RST_BIT ; SYSTEM_RST_DIR |= SYSTEM_RST_BIT ; SYSTEM_RST_OUT &= ~ SYSTEM_RST_BIT ; #endif SERIAL_IOSEL_SEL &= ~ SERIAL_IOSEL_BIT ; SERIAL_IOSEL_DIR |= SERIAL_IOSEL_BIT ; SERIAL_IOSEL_OUT |= SERIAL_IOSEL_BIT ; SERIAL_PORTSEL_SEL &= ~ SERIAL_PORTSEL_BIT ; SERIAL_PORTSEL_DIR |= SERIAL_PORTSEL_BIT ; SERIAL_PORTSEL_OUT |= SERIAL_PORTSEL_BIT ; SERIAL_SFLOW_SEL &= ~ SERIAL_SFLOW_BIT ; SERIAL_SFLOW_DIR |= SERIAL_SFLOW_BIT ; #if defined ( SERIAL_BIT_SYNCHRONOUS ) SERIAL_SFLOW_OUT |= SERIAL_SFLOW_BIT ; #else SERIAL_SFLOW_OUT &= ~ SERIAL_SFLOW_BIT ; #endif #if defined ( SERIAL_BIT_SYNCHRONOUS ) SYNC_SIN_SEL &= ~ SYNC_SIN_BIT ; SYNC_SOUT_SEL &= ~ SYNC_SOUT_BIT ; SYNC_SCLK_SEL &= ~ SYNC_SCLK_BIT ; SYNC_SCLK_IES &= ~ SYNC_SCLK_BIT ; SYNC_SCLK_IFG &= ~ SYNC_SCLK_BIT ; SYNC_SCLK_IE |= SYNC_SCLK_BIT ; #elif defined ( SERIAL_BYTE_SYNCHRONOUS ) BYTE_SYNC_UCI_CTL0 = UCCKPL | UCSYNC ; SYNC_SIN_SEL |= SYNC_SIN_BIT ; SYNC_SOUT_SEL |= SYNC_SOUT_BIT ; SYNC_SCLK_SEL |= SYNC_SCLK_BIT ; #endif SYNC_SEN_DIR &= ~ SYNC_SEN_BIT ; SYNC_SMSGRDY_DIR |= SYNC_SMSGRDY_BIT ; SYNC_SMSGRDY_DEASSERT ( ) ; SYNC_SIN_DIR &= ~ SYNC_SIN_BIT ; SYNC_SCLK_DIR &= ~ SYNC_SCLK_BIT ; SYNC_SOUT_DIR |= SYNC_SOUT_BIT ; SYNC_SRDY_DIR |= SYNC_SRDY_BIT ; SYNC_SRDY_DEASSERT ( ) ; #if defined ( PIN_RESET ) SYSTEM_RST_OUT |= SYSTEM_RST_BIT ; Timer_DelayTime ( 50000 ) ; #endif #if defined ( SYNCH_RESET ) while ( ! Serial_SyncReset ( ) ) ; SYNC_SMSGRDY_DEASSERT ( ) ; #endif #if defined ( SERIAL_BYTE_SYNCHRONOUS ) BYTE_SYNC_UCI_CTL1 &= ~ UCSWRST ; #endif SYNC_SEN_IES |= SYNC_SEN_BIT ; SYNC_SEN_IFG &= ~ SYNC_SEN_BIT ; SYNC_SEN_IE |= SYNC_SEN_BIT ; #if defined ( SERIAL_BYTE_SYNCHRONOUS ) BYTE_SYNC_UCI_IFR &= ~ BYTE_SYNC_RX_INT ; BYTE_SYNC_UCI_IER |= BYTE_SYNC_RX_INT ; bTheGotByte = FALSE ; #endif }
Synchronous_Init
Initialize the synchronous serial interface.
Synchronous_Init Initialize the synchronous serial interface .
// Go int RESET // Set as output // Set as output // Set low to reset module  // Set configuration pins // Set as output // Set as output // Serial, not SensRcore    // Set as output // Set as output // Port select HI for SYNC serial // Set as output // Set as output // Select bit flow control // SERIAL_BIT_SYNCHRONOUS // Select byte flow control // SERIAL_BYTE_SYNCHRONOUS       // // Set up serial pins // // Enable SIN as GPIO // Enable SOUT as GPIO // Enable SCLK as GPIO // interrupt on the low-to-high transition // clear the interrupt flag		 // Enable SCLK intterupt // UCI Register Init // Set UCI to synchronous with clock normally high            // Enable SIN to use UCI B0 SIMO pin // Enable SOUT to use UCI B0 SOMI pin // Enable the UCSCLK functionality //   // SEN // set the direction to be an input // SMSGRDY // set SMSGRDY as an output // make sure it is deasserted so that it doesn't misguide ANT // SIN // set SIN as an input // SCLK // set SCLK as an input // SOUT // Set SOUT as an output // SRDY // set SRDY as an output // put SRDY in a known state // ** Take ANT out of RESET ** // Delay for 500ms // Do a synchronous reset // make sure it is deasserted so that it doesn't misguide ANT // Enable SPI // Enable SEN interrupt // interrupt on high-to-low transition // reset the interrupt flag // enable the SEN interrupt to allow wake up from sleep                                        // Enable RECV interrupt // Enable RX interrupt only // Enable RX interrupt only