XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c
int XSysMon_SetSingleChParams(XSysMon *InstancePtr, u8 Channel,
				int IncreaseAcqCycles, int IsEventMode,
				int IsDifferentialMode)
{
	u32 RegValue;

	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((Channel <= XSM_CH_VREFN) ||
			  (Channel == XSM_CH_CALIBRATION) ||
			  ((Channel >= XSM_CH_AUX_MIN) &&
			  (Channel <= XSM_CH_AUX_MAX)) ||
			  ((Channel >= XSM_CH_VUSR0) &&
			  (Channel <= XSM_CH_VUSR3)));
	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
			  (IncreaseAcqCycles == FALSE));
	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
	Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
			  (IsDifferentialMode == FALSE));

	/*
	 * Check if the device is in single channel mode else return failure
	 */
	if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SINGCHAN)) {
		return XST_FAILURE;
	}

	/*
	 * Read the Configuration Register 0.
	 */
	RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
				   XSM_CFR0_OFFSET) & XSM_CFR0_AVG_VALID_MASK;

	/*
	 * Select the number of acquisition cycles. The acquisition cycles is
	 * only valid for the external channels.
	 */
	if (IncreaseAcqCycles == TRUE) {
		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
		    || (Channel == XSM_CH_VPVN)) {
			RegValue |= XSM_CFR0_ACQ_MASK;
		} else {
			return XST_FAILURE;
		}
	}

	/*
	 * Select the input mode. The input mode is only valid for the
	 * external channels.
	 */
	if (IsDifferentialMode == TRUE) {

		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
		    || (Channel == XSM_CH_VPVN)) {
			RegValue |= XSM_CFR0_DU_MASK;
		} else {
			return XST_FAILURE;
		}
	}

	/*
	 * Select the ADC mode.
	 */
	if (IsEventMode == TRUE) {
		RegValue |= XSM_CFR0_EC_MASK;
	}

	/*
	 * Write the given values into the Configuration Register 0.
	 */
	RegValue |= (Channel & XSM_CFR0_CHANNEL_MASK);
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR0_OFFSET,
			 RegValue);

	return XST_SUCCESS;
}
/****************************************************************************/
/**
*
* The function sets the given parameters in the Configuration Register 0 in
* the single channel mode.
*
* @param	InstancePtr is a pointer to the XSysMon instance.
* @param	Channel is the channel number for conversion. The valid
*		channels are 0 to 5, 8, and 16 to 31. Channel 6 is
*		valid for 7 series and Zynq XADC. Channel 32 to 35 are valid
*		for Ultrascale.
* @param	IncreaseAcqCycles is a boolean parameter which specifies whether
*		the Acquisition time for the external channels has to be
*		increased to 10 ADCCLK cycles (specify TRUE) or remain at the
*		default 4 ADCCLK cycles (specify FALSE). This parameter is
*		only valid for the external channels.
* @param	IsEventMode is a boolean parameter that specifies continuous
*		sampling (specify FALSE) or event driven sampling mode (specify
*		TRUE) for the given channel.
* @param	IsDifferentialMode is a boolean parameter which specifies
*		unipolar(specify FALSE) or differential mode (specify TRUE) for
*		the analog inputs. The 	input mode is only valid for the
*		external channels.
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the Configuration Register 0.
*		- XST_FAILURE if the channel sequencer is enabled or the input
*		parameters are not valid for the selected channel.
*
* @note
*		- The number of samples for the averaging for all the channels
*		is set by using the function XSysMon_SetAvg.
*		- The calibration of the device is done by doing a ADC
*		conversion on the calibration channel(channel 8). The input
*		parameters IncreaseAcqCycles, IsDifferentialMode and
*		IsEventMode are not valid for this channel.
*
*****************************************************************************/
The function sets the given parameters in the Configuration Register 0 in
the single channel mode.
The function sets the given parameters in the Configuration Register 0 in the single channel mode .
int XSysMon_SetSingleChParams(XSysMon *InstancePtr, u8 Channel,
				int IncreaseAcqCycles, int IsEventMode,
				int IsDifferentialMode)
{
	u32 RegValue;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((Channel <= XSM_CH_VREFN) ||
			  (Channel == XSM_CH_CALIBRATION) ||
			  ((Channel >= XSM_CH_AUX_MIN) &&
			  (Channel <= XSM_CH_AUX_MAX)) ||
			  ((Channel >= XSM_CH_VUSR0) &&
			  (Channel <= XSM_CH_VUSR3)));
	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
			  (IncreaseAcqCycles == FALSE));
	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
	Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
			  (IsDifferentialMode == FALSE));
	if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SINGCHAN)) {
		return XST_FAILURE;
	}
	RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
				   XSM_CFR0_OFFSET) & XSM_CFR0_AVG_VALID_MASK;
	if (IncreaseAcqCycles == TRUE) {
		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
		    || (Channel == XSM_CH_VPVN)) {
			RegValue |= XSM_CFR0_ACQ_MASK;
		} else {
			return XST_FAILURE;
		}
	}
	if (IsDifferentialMode == TRUE) {
		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
		    || (Channel == XSM_CH_VPVN)) {
			RegValue |= XSM_CFR0_DU_MASK;
		} else {
			return XST_FAILURE;
		}
	}
	if (IsEventMode == TRUE) {
		RegValue |= XSM_CFR0_EC_MASK;
	}
	RegValue |= (Channel & XSM_CFR0_CHANNEL_MASK);
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR0_OFFSET,
			 RegValue);
	return XST_SUCCESS;
}
int XSysMon_SetSingleChParams ( XSysMon * InstancePtr , u8 Channel , int IncreaseAcqCycles , int IsEventMode , int IsDifferentialMode ) { u32 RegValue ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Xil_AssertNonvoid ( ( Channel <= XSM_CH_VREFN ) || ( Channel == XSM_CH_CALIBRATION ) || ( ( Channel >= XSM_CH_AUX_MIN ) && ( Channel <= XSM_CH_AUX_MAX ) ) || ( ( Channel >= XSM_CH_VUSR0 ) && ( Channel <= XSM_CH_VUSR3 ) ) ) ; Xil_AssertNonvoid ( ( IncreaseAcqCycles == TRUE ) || ( IncreaseAcqCycles == FALSE ) ) ; Xil_AssertNonvoid ( ( IsEventMode == TRUE ) || ( IsEventMode == FALSE ) ) ; Xil_AssertNonvoid ( ( IsDifferentialMode == TRUE ) || ( IsDifferentialMode == FALSE ) ) ; if ( ( XSysMon_GetSequencerMode ( InstancePtr ) != XSM_SEQ_MODE_SINGCHAN ) ) { return XST_FAILURE ; } RegValue = XSysMon_ReadReg ( InstancePtr -> Config . BaseAddress , XSM_CFR0_OFFSET ) & XSM_CFR0_AVG_VALID_MASK ; if ( IncreaseAcqCycles == TRUE ) { if ( ( ( Channel >= XSM_CH_AUX_MIN ) && ( Channel <= XSM_CH_AUX_MAX ) ) || ( Channel == XSM_CH_VPVN ) ) { RegValue |= XSM_CFR0_ACQ_MASK ; } else { return XST_FAILURE ; } } if ( IsDifferentialMode == TRUE ) { if ( ( ( Channel >= XSM_CH_AUX_MIN ) && ( Channel <= XSM_CH_AUX_MAX ) ) || ( Channel == XSM_CH_VPVN ) ) { RegValue |= XSM_CFR0_DU_MASK ; } else { return XST_FAILURE ; } } if ( IsEventMode == TRUE ) { RegValue |= XSM_CFR0_EC_MASK ; } RegValue |= ( Channel & XSM_CFR0_CHANNEL_MASK ) ; XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_CFR0_OFFSET , RegValue ) ; return XST_SUCCESS ; }
The function sets the given parameters in the Configuration Register 0 in
the single channel mode.
The function sets the given parameters in the Configuration Register 0 in the single channel mode .
/*
	 * Assert the arguments.
	 */ /*
	 * Check if the device is in single channel mode else return failure
	 */ /*
	 * Read the Configuration Register 0.
	 */ /*
	 * Select the number of acquisition cycles. The acquisition cycles is
	 * only valid for the external channels.
	 */ /*
	 * Select the input mode. The input mode is only valid for the
	 * external channels.
	 */ /*
	 * Select the ADC mode.
	 */ /*
	 * Write the given values into the Configuration Register 0.
	 */