XilinxProcessorIPLib/drivers/hdcp1x/src/xhdcp1x_cipher.c
u64 XHdcp1x_CipherGetMi(const XHdcp1x *InstancePtr)
{
	u64 Mi = 0;

	/* Verify arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);

	/* Check that it is not disabled */
	if (!XHdcp1x_CipherIsEnabled(InstancePtr)) {
		return (XST_NOT_ENABLED);
	}

	/* Update Mi */
	Mi = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_Mi_H);
	Mi <<= 32;
	Mi |= XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_Mi_L);

	return (Mi);
}
/*****************************************************************************/
/**
* This function reads the contents of the Mi/An register of BM0.
*
* @param	InstancePtr is the device to query.
*
* @return	The contents of the register.
*
* @note		None.
*
******************************************************************************/
This function reads the contents of the Mi/An register of BM0.
This function reads the contents of the Mi / An register of BM0 .
u64 XHdcp1x_CipherGetMi(const XHdcp1x *InstancePtr)
{
	u64 Mi = 0;
	Xil_AssertNonvoid(InstancePtr != NULL);
	if (!XHdcp1x_CipherIsEnabled(InstancePtr)) {
		return (XST_NOT_ENABLED);
	}
	Mi = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_Mi_H);
	Mi <<= 32;
	Mi |= XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_Mi_L);
	return (Mi);
}
u64 XHdcp1x_CipherGetMi ( const XHdcp1x * InstancePtr ) { u64 Mi = 0 ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; if ( ! XHdcp1x_CipherIsEnabled ( InstancePtr ) ) { return ( XST_NOT_ENABLED ) ; } Mi = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CIPHER_Mi_H ) ; Mi <<= 32 ; Mi |= XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CIPHER_Mi_L ) ; return ( Mi ) ; }
This function reads the contents of the Mi/An register of BM0.
This function reads the contents of the Mi / An register of BM0 .
/* Verify arguments. */ /* Check that it is not disabled */ /* Update Mi */