emlib/src/em_emu.c
static void dcdcValidatedConfigSet(void)
{
/* Disable LP mode hysterysis in the state machine control */
#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1)
/* Comparator threshold on the high side */
#define EMU_DCDCMISCCTRL_LPCMPHYSHI  (0x1UL << 2)
#define EMU_DCDCSMCTRL  (*(volatile uint32_t *)(EMU_BASE + 0x44))

  uint32_t lnForceCcm;

#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
  uint32_t dcdcTiming;
  SYSTEM_ChipRevision_TypeDef rev;
#endif

  /* Enable duty cycling of the bias */
  EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN;

  /* Set low-noise RCO for LNFORCECCM configuration
   * LNFORCECCM is default 1 for EFR32
   * LNFORCECCM is default 0 for EFM32
   */
  lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT);
  if (lnForceCcm) {
    /* 7MHz is recommended for LNFORCECCM = 1 */
    EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz);
  } else {
    /* 3MHz is recommended for LNFORCECCM = 0 */
    EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz);
  }

#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
  EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK;
  EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS
                       | EMU_DCDCMISCCTRL_LPCMPHYSHI;

  SYSTEM_ChipRevisionGet(&rev);
  if ((rev.major == 1)
      && (rev.minor < 3)
      && (errataFixDcdcHsState == errataFixDcdcHsInit)) {
    /* LPCMPWAITDIS = 1 */
    EMU_DCDCSMCTRL |= 1;

    dcdcTiming = EMU->DCDCTIMING;
    dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK
                    | _EMU_DCDCTIMING_LNWAIT_MASK
                    | _EMU_DCDCTIMING_BYPWAIT_MASK);

    dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT)
                   | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT)
                   | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT));
    EMU->DCDCTIMING = dcdcTiming;

    errataFixDcdcHsState = errataFixDcdcHsTrimSet;
  }
#endif
}
/***************************************************************************/
/**
 * @brief
 *   Set recommended and validated current optimization and timing settings
 *
 ******************************************************************************/
@brief
Set recommended and validated current optimization and timing settings
@brief Set recommended and validated current optimization and timing settings
static void dcdcValidatedConfigSet(void)
{
#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1)
#define EMU_DCDCMISCCTRL_LPCMPHYSHI  (0x1UL << 2)
#define EMU_DCDCSMCTRL  (*(volatile uint32_t *)(EMU_BASE + 0x44))
  uint32_t lnForceCcm;
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
  uint32_t dcdcTiming;
  SYSTEM_ChipRevision_TypeDef rev;
#endif
  EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN;
  lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT);
  if (lnForceCcm) {
    EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz);
  } else {
    EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz);
  }
#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
  EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK;
  EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS
                       | EMU_DCDCMISCCTRL_LPCMPHYSHI;
  SYSTEM_ChipRevisionGet(&rev);
  if ((rev.major == 1)
      && (rev.minor < 3)
      && (errataFixDcdcHsState == errataFixDcdcHsInit)) {
    EMU_DCDCSMCTRL |= 1;
    dcdcTiming = EMU->DCDCTIMING;
    dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK
                    | _EMU_DCDCTIMING_LNWAIT_MASK
                    | _EMU_DCDCTIMING_BYPWAIT_MASK);
    dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT)
                   | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT)
                   | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT));
    EMU->DCDCTIMING = dcdcTiming;
    errataFixDcdcHsState = errataFixDcdcHsTrimSet;
  }
#endif
}
static void dcdcValidatedConfigSet ( void ) { #define EMU_DCDCMISCCTRL_LPCMPHYSDIS  (0x1UL << 1)
 #define EMU_DCDCMISCCTRL_LPCMPHYSHI   (0x1UL << 2)
 #define EMU_DCDCSMCTRL   (*(volatile uint32_t *)(EMU_BASE + 0x44))
 uint32_t lnForceCcm ; #if defined ( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) uint32_t dcdcTiming ; SYSTEM_ChipRevision_TypeDef rev ; #endif EMU -> DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN ; lnForceCcm = BUS_RegBitRead ( & EMU -> DCDCMISCCTRL , _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT ) ; if ( lnForceCcm ) { EMU_DCDCLnRcoBandSet ( emuDcdcLnRcoBand_7MHz ) ; } else { EMU_DCDCLnRcoBandSet ( emuDcdcLnRcoBand_3MHz ) ; } #if defined ( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) EMU -> DCDCTIMING &= ~ _EMU_DCDCTIMING_DUTYSCALE_MASK ; EMU -> DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS | EMU_DCDCMISCCTRL_LPCMPHYSHI ; SYSTEM_ChipRevisionGet ( & rev ) ; if ( ( rev . major == 1 ) && ( rev . minor < 3 ) && ( errataFixDcdcHsState == errataFixDcdcHsInit ) ) { EMU_DCDCSMCTRL |= 1 ; dcdcTiming = EMU -> DCDCTIMING ; dcdcTiming &= ~ ( _EMU_DCDCTIMING_LPINITWAIT_MASK | _EMU_DCDCTIMING_LNWAIT_MASK | _EMU_DCDCTIMING_BYPWAIT_MASK ) ; dcdcTiming |= ( ( 180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT ) | ( 12 << _EMU_DCDCTIMING_LNWAIT_SHIFT ) | ( 180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT ) ) ; EMU -> DCDCTIMING = dcdcTiming ; errataFixDcdcHsState = errataFixDcdcHsTrimSet ; } #endif }
@brief
   Set recommended and validated current optimization and timing settings
@brief Set recommended and validated current optimization and timing settings
/* Disable LP mode hysterysis in the state machine control */ /* Comparator threshold on the high side */ /* Enable duty cycling of the bias */ /* Set low-noise RCO for LNFORCECCM configuration
   * LNFORCECCM is default 1 for EFR32
   * LNFORCECCM is default 0 for EFM32
   */ /* 7MHz is recommended for LNFORCECCM = 1 */ /* 3MHz is recommended for LNFORCECCM = 0 */ /* LPCMPWAITDIS = 1 */