src/dpdk/drivers/net/ice/base/ice_common.c
enum ice_status ice_init_hw(struct ice_hw *hw)
{
	struct ice_aqc_get_phy_caps_data *pcaps;
	enum ice_status status;
	u16 mac_buf_len;
	void *mac_buf;

	ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);

	/* Set MAC type based on DeviceID */
	status = ice_set_mac_type(hw);
	if (status)
		return status;

	hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
			 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
		PF_FUNC_RID_FUNCTION_NUMBER_S;

	status = ice_reset(hw, ICE_RESET_PFR);
	if (status)
		return status;

	ice_get_itr_intrl_gran(hw);

	status = ice_create_all_ctrlq(hw);
	if (status)
		goto err_unroll_cqinit;

	status = ice_init_nvm(hw);
	if (status)
		goto err_unroll_cqinit;

	if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
		ice_print_rollback_msg(hw);

	status = ice_clear_pf_cfg(hw);
	if (status)
		goto err_unroll_cqinit;

	/* Set bit to enable Flow Director filters */
	wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
	INIT_LIST_HEAD(&hw->fdir_list_head);

	ice_clear_pxe_mode(hw);

	status = ice_get_caps(hw);
	if (status)
		goto err_unroll_cqinit;

	hw->port_info = (struct ice_port_info *)
			ice_malloc(hw, sizeof(*hw->port_info));
	if (!hw->port_info) {
		status = ICE_ERR_NO_MEMORY;
		goto err_unroll_cqinit;
	}

	/* set the back pointer to HW */
	hw->port_info->hw = hw;

	/* Initialize port_info struct with switch configuration data */
	status = ice_get_initial_sw_cfg(hw);
	if (status)
		goto err_unroll_alloc;

	hw->evb_veb = true;
	/* Query the allocated resources for Tx scheduler */
	status = ice_sched_query_res_alloc(hw);
	if (status) {
		ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
		goto err_unroll_alloc;
	}
	ice_sched_get_psm_clk_freq(hw);

	/* Initialize port_info struct with scheduler data */
	status = ice_sched_init_port(hw->port_info);
	if (status)
		goto err_unroll_sched;
	pcaps = (struct ice_aqc_get_phy_caps_data *)
		ice_malloc(hw, sizeof(*pcaps));
	if (!pcaps) {
		status = ICE_ERR_NO_MEMORY;
		goto err_unroll_sched;
	}

	/* Initialize port_info struct with PHY capabilities */
	status = ice_aq_get_phy_caps(hw->port_info, false,
				     ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL);
	ice_free(hw, pcaps);
	if (status)
		ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n",
			 status);

	/* Initialize port_info struct with link information */
	status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
	if (status)
		goto err_unroll_sched;
	/* need a valid SW entry point to build a Tx tree */
	if (!hw->sw_entry_point_layer) {
		ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
		status = ICE_ERR_CFG;
		goto err_unroll_sched;
	}
	INIT_LIST_HEAD(&hw->agg_list);
	/* Initialize max burst size */
	if (!hw->max_burst_size)
		ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
	status = ice_init_fltr_mgmt_struct(hw);
	if (status)
		goto err_unroll_sched;

	/* Get MAC information */
	/* A single port can report up to two (LAN and WoL) addresses */
	mac_buf = ice_calloc(hw, 2,
			     sizeof(struct ice_aqc_manage_mac_read_resp));
	mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);

	if (!mac_buf) {
		status = ICE_ERR_NO_MEMORY;
		goto err_unroll_fltr_mgmt_struct;
	}

	status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
	ice_free(hw, mac_buf);

	if (status)
		goto err_unroll_fltr_mgmt_struct;
	/* enable jumbo frame support at MAC level */
	status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
	if (status)
		goto err_unroll_fltr_mgmt_struct;
	/* Obtain counter base index which would be used by flow director */
	status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
	if (status)
		goto err_unroll_fltr_mgmt_struct;
	status = ice_init_hw_tbls(hw);
	if (status)
		goto err_unroll_fltr_mgmt_struct;
	ice_init_lock(&hw->tnl_lock);

	return ICE_SUCCESS;

err_unroll_fltr_mgmt_struct:
	ice_cleanup_fltr_mgmt_struct(hw);
err_unroll_sched:
	ice_sched_cleanup_all(hw);
err_unroll_alloc:
	ice_free(hw, hw->port_info);
	hw->port_info = NULL;
err_unroll_cqinit:
	ice_destroy_all_ctrlq(hw);
	return status;
}
/**
 * ice_init_hw - main hardware initialization routine
 * @hw: pointer to the hardware structure
 */
main hardware initialization routine
@hw: pointer to the hardware structure
main hardware initialization routine @hw : pointer to the hardware structure
enum ice_status ice_init_hw(struct ice_hw *hw)
{
	struct ice_aqc_get_phy_caps_data *pcaps;
	enum ice_status status;
	u16 mac_buf_len;
	void *mac_buf;
	ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
	status = ice_set_mac_type(hw);
	if (status)
		return status;
	hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
			 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
		PF_FUNC_RID_FUNCTION_NUMBER_S;
	status = ice_reset(hw, ICE_RESET_PFR);
	if (status)
		return status;
	ice_get_itr_intrl_gran(hw);
	status = ice_create_all_ctrlq(hw);
	if (status)
		goto err_unroll_cqinit;
	status = ice_init_nvm(hw);
	if (status)
		goto err_unroll_cqinit;
	if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
		ice_print_rollback_msg(hw);
	status = ice_clear_pf_cfg(hw);
	if (status)
		goto err_unroll_cqinit;
	wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
	INIT_LIST_HEAD(&hw->fdir_list_head);
	ice_clear_pxe_mode(hw);
	status = ice_get_caps(hw);
	if (status)
		goto err_unroll_cqinit;
	hw->port_info = (struct ice_port_info *)
			ice_malloc(hw, sizeof(*hw->port_info));
	if (!hw->port_info) {
		status = ICE_ERR_NO_MEMORY;
		goto err_unroll_cqinit;
	}
	hw->port_info->hw = hw;
	status = ice_get_initial_sw_cfg(hw);
	if (status)
		goto err_unroll_alloc;
	hw->evb_veb = true;
	status = ice_sched_query_res_alloc(hw);
	if (status) {
		ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
		goto err_unroll_alloc;
	}
	ice_sched_get_psm_clk_freq(hw);
	status = ice_sched_init_port(hw->port_info);
	if (status)
		goto err_unroll_sched;
	pcaps = (struct ice_aqc_get_phy_caps_data *)
		ice_malloc(hw, sizeof(*pcaps));
	if (!pcaps) {
		status = ICE_ERR_NO_MEMORY;
		goto err_unroll_sched;
	}
	status = ice_aq_get_phy_caps(hw->port_info, false,
				     ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL);
	ice_free(hw, pcaps);
	if (status)
		ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n",
			 status);
	status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
	if (status)
		goto err_unroll_sched;
	if (!hw->sw_entry_point_layer) {
		ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
		status = ICE_ERR_CFG;
		goto err_unroll_sched;
	}
	INIT_LIST_HEAD(&hw->agg_list);
	if (!hw->max_burst_size)
		ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
	status = ice_init_fltr_mgmt_struct(hw);
	if (status)
		goto err_unroll_sched;
	mac_buf = ice_calloc(hw, 2,
			     sizeof(struct ice_aqc_manage_mac_read_resp));
	mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
	if (!mac_buf) {
		status = ICE_ERR_NO_MEMORY;
		goto err_unroll_fltr_mgmt_struct;
	}
	status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
	ice_free(hw, mac_buf);
	if (status)
		goto err_unroll_fltr_mgmt_struct;
	status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
	if (status)
		goto err_unroll_fltr_mgmt_struct;
	status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
	if (status)
		goto err_unroll_fltr_mgmt_struct;
	status = ice_init_hw_tbls(hw);
	if (status)
		goto err_unroll_fltr_mgmt_struct;
	ice_init_lock(&hw->tnl_lock);
	return ICE_SUCCESS;
err_unroll_fltr_mgmt_struct:
	ice_cleanup_fltr_mgmt_struct(hw);
err_unroll_sched:
	ice_sched_cleanup_all(hw);
err_unroll_alloc:
	ice_free(hw, hw->port_info);
	hw->port_info = NULL;
err_unroll_cqinit:
	ice_destroy_all_ctrlq(hw);
	return status;
}
enum ice_status ice_init_hw ( struct ice_hw * hw ) { struct ice_aqc_get_phy_caps_data * pcaps ; enum ice_status status ; u16 mac_buf_len ; void * mac_buf ; ice_debug ( hw , ICE_DBG_TRACE , " \n " , __func__ ) ; status = ice_set_mac_type ( hw ) ; if ( status ) return status ; hw -> pf_id = ( u8 ) ( rd32 ( hw , PF_FUNC_RID ) & PF_FUNC_RID_FUNCTION_NUMBER_M ) >> PF_FUNC_RID_FUNCTION_NUMBER_S ; status = ice_reset ( hw , ICE_RESET_PFR ) ; if ( status ) return status ; ice_get_itr_intrl_gran ( hw ) ; status = ice_create_all_ctrlq ( hw ) ; if ( status ) goto err_unroll_cqinit ; status = ice_init_nvm ( hw ) ; if ( status ) goto err_unroll_cqinit ; if ( ice_get_fw_mode ( hw ) == ICE_FW_MODE_ROLLBACK ) ice_print_rollback_msg ( hw ) ; status = ice_clear_pf_cfg ( hw ) ; if ( status ) goto err_unroll_cqinit ; wr32 ( hw , PFQF_FD_ENA , PFQF_FD_ENA_FD_ENA_M ) ; INIT_LIST_HEAD ( & hw -> fdir_list_head ) ; ice_clear_pxe_mode ( hw ) ; status = ice_get_caps ( hw ) ; if ( status ) goto err_unroll_cqinit ; hw -> port_info = ( struct ice_port_info * ) ice_malloc ( hw , sizeof ( * hw -> port_info ) ) ; if ( ! hw -> port_info ) { status = ICE_ERR_NO_MEMORY ; goto err_unroll_cqinit ; } hw -> port_info -> hw = hw ; status = ice_get_initial_sw_cfg ( hw ) ; if ( status ) goto err_unroll_alloc ; hw -> evb_veb = true ; status = ice_sched_query_res_alloc ( hw ) ; if ( status ) { ice_debug ( hw , ICE_DBG_SCHED , " \n " ) ; goto err_unroll_alloc ; } ice_sched_get_psm_clk_freq ( hw ) ; status = ice_sched_init_port ( hw -> port_info ) ; if ( status ) goto err_unroll_sched ; pcaps = ( struct ice_aqc_get_phy_caps_data * ) ice_malloc ( hw , sizeof ( * pcaps ) ) ; if ( ! pcaps ) { status = ICE_ERR_NO_MEMORY ; goto err_unroll_sched ; } status = ice_aq_get_phy_caps ( hw -> port_info , false , ICE_AQC_REPORT_TOPO_CAP_MEDIA , pcaps , NULL ) ; ice_free ( hw , pcaps ) ; if ( status ) ice_warn ( hw , " \n " , status ) ; status = ice_aq_get_link_info ( hw -> port_info , false , NULL , NULL ) ; if ( status ) goto err_unroll_sched ; if ( ! hw -> sw_entry_point_layer ) { ice_debug ( hw , ICE_DBG_SCHED , " \n " ) ; status = ICE_ERR_CFG ; goto err_unroll_sched ; } INIT_LIST_HEAD ( & hw -> agg_list ) ; if ( ! hw -> max_burst_size ) ice_cfg_rl_burst_size ( hw , ICE_SCHED_DFLT_BURST_SIZE ) ; status = ice_init_fltr_mgmt_struct ( hw ) ; if ( status ) goto err_unroll_sched ; mac_buf = ice_calloc ( hw , 2 , sizeof ( struct ice_aqc_manage_mac_read_resp ) ) ; mac_buf_len = 2 * sizeof ( struct ice_aqc_manage_mac_read_resp ) ; if ( ! mac_buf ) { status = ICE_ERR_NO_MEMORY ; goto err_unroll_fltr_mgmt_struct ; } status = ice_aq_manage_mac_read ( hw , mac_buf , mac_buf_len , NULL ) ; ice_free ( hw , mac_buf ) ; if ( status ) goto err_unroll_fltr_mgmt_struct ; status = ice_aq_set_mac_cfg ( hw , ICE_AQ_SET_MAC_FRAME_SIZE_MAX , NULL ) ; if ( status ) goto err_unroll_fltr_mgmt_struct ; status = ice_alloc_fd_res_cntr ( hw , & hw -> fd_ctr_base ) ; if ( status ) goto err_unroll_fltr_mgmt_struct ; status = ice_init_hw_tbls ( hw ) ; if ( status ) goto err_unroll_fltr_mgmt_struct ; ice_init_lock ( & hw -> tnl_lock ) ; return ICE_SUCCESS ; err_unroll_fltr_mgmt_struct : ice_cleanup_fltr_mgmt_struct ( hw ) ; err_unroll_sched : ice_sched_cleanup_all ( hw ) ; err_unroll_alloc : ice_free ( hw , hw -> port_info ) ; hw -> port_info = NULL ; err_unroll_cqinit : ice_destroy_all_ctrlq ( hw ) ; return status ; }
ice_init_hw - main hardware initialization routine
 @hw: pointer to the hardware structure
ice_init_hw - main hardware initialization routine @hw : pointer to the hardware structure
/* Set MAC type based on DeviceID */ /* Set bit to enable Flow Director filters */ /* set the back pointer to HW */ /* Initialize port_info struct with switch configuration data */ /* Query the allocated resources for Tx scheduler */ /* Initialize port_info struct with scheduler data */ /* Initialize port_info struct with PHY capabilities */ /* Initialize port_info struct with link information */ /* need a valid SW entry point to build a Tx tree */ /* Initialize max burst size */ /* Get MAC information */ /* A single port can report up to two (LAN and WoL) addresses */ /* enable jumbo frame support at MAC level */ /* Obtain counter base index which would be used by flow director */