XilinxProcessorIPLib/drivers/i2stx/src/xi2stx.c
u32 XI2s_Tx_SetSclkOutDiv(XI2s_Tx *InstancePtr, u32 MClk, u32 Fs)
{
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid((MClk > 0) && (MClk > Fs));
	Xil_AssertNonvoid((Fs > 0) && (Fs < MClk));
	u32 SClk;
	u8 SClkOut_Div;

	/* Sclk should be multiplied by 32, when 32BitLR parameter is enabled */
	if (InstancePtr->Config.Is32BitLR)
	{
		SClk = (2 * Fs * 32);
	} else {
		SClk = (2 * Fs * InstancePtr->Config.DWidth);
	}

	SClkOut_Div = (MClk/SClk);
	SClkOut_Div /= 2;

	XI2s_Tx_WriteReg(InstancePtr->Config.BaseAddress,
		XI2S_TX_TMR_CTRL_OFFSET, SClkOut_Div & XI2S_TX_CLK_MASK);
	return XST_SUCCESS;
}
/*****************************************************************************/
/**
 * This function calculates the SCLK Output divider value of the
 * I2S timing generator.
 *
 * @param  InstancePtr is a pointer to the I2s Transmitter instance.
 * @param  MClk is the frequency of the MClk.
 * @param  Fs is the sampling frequency of the system.
 * Divider value for the SCLK generation, MCLK/SCLK = SCLKOUT_DIV x 2
 * i.e. MCLK = 384xFs, SCLK = 48xFs
 * (2x24bits) ->
 * SCLKOUT_DIV = MCLK/SCLK/2 = 4
 * Valid values are 1 through 15.
 *
 * @return - XST_FAILURE if SCLK Output divider is not calculated to be a
 *           positive integer.
 *         - XST_SUCCESS, otherwise.
 *
 *****************************************************************************/
This function calculates the SCLK Output divider value of the
I2S timing generator.

@param  InstancePtr is a pointer to the I2s Transmitter instance.
@param  MClk is the frequency of the MClk.
@param  Fs is the sampling frequency of the system.
Divider value for the SCLK generation, MCLK/SCLK = SCLKOUT_DIV x 2
i.e. MCLK = 384xFs, SCLK = 48xFs
(2x24bits) ->
SCLKOUT_DIV = MCLK/SCLK/2 = 4
Valid values are 1 through 15.

@return - XST_FAILURE if SCLK Output divider is not calculated to be a
positive integer.
This function calculates the SCLK Output divider value of the I2S timing generator . @param InstancePtr is a pointer to the I2s Transmitter instance . @param MClk is the frequency of the MClk . @param Fs is the sampling frequency of the system . Divider value for the SCLK generation MCLK / SCLK = SCLKOUT_DIV x 2 i . e . MCLK = 384xFs SCLK = 48xFs ( 2x24bits ) - > SCLKOUT_DIV = MCLK / SCLK / 2 = 4 Valid values are 1 through 15 . @return - XST_FAILURE if SCLK Output divider is not calculated to be a positive integer .
u32 XI2s_Tx_SetSclkOutDiv(XI2s_Tx *InstancePtr, u32 MClk, u32 Fs)
{
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid((MClk > 0) && (MClk > Fs));
	Xil_AssertNonvoid((Fs > 0) && (Fs < MClk));
	u32 SClk;
	u8 SClkOut_Div;
	if (InstancePtr->Config.Is32BitLR)
	{
		SClk = (2 * Fs * 32);
	} else {
		SClk = (2 * Fs * InstancePtr->Config.DWidth);
	}
	SClkOut_Div = (MClk/SClk);
	SClkOut_Div /= 2;
	XI2s_Tx_WriteReg(InstancePtr->Config.BaseAddress,
		XI2S_TX_TMR_CTRL_OFFSET, SClkOut_Div & XI2S_TX_CLK_MASK);
	return XST_SUCCESS;
}
u32 XI2s_Tx_SetSclkOutDiv ( XI2s_Tx * InstancePtr , u32 MClk , u32 Fs ) { Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( ( MClk > 0 ) && ( MClk > Fs ) ) ; Xil_AssertNonvoid ( ( Fs > 0 ) && ( Fs < MClk ) ) ; u32 SClk ; u8 SClkOut_Div ; if ( InstancePtr -> Config . Is32BitLR ) { SClk = ( 2 * Fs * 32 ) ; } else { SClk = ( 2 * Fs * InstancePtr -> Config . DWidth ) ; } SClkOut_Div = ( MClk / SClk ) ; SClkOut_Div /= 2 ; XI2s_Tx_WriteReg ( InstancePtr -> Config . BaseAddress , XI2S_TX_TMR_CTRL_OFFSET , SClkOut_Div & XI2S_TX_CLK_MASK ) ; return XST_SUCCESS ; }
This function calculates the SCLK Output divider value of the
 I2S timing generator.
This function calculates the SCLK Output divider value of the I2S timing generator .
/* Sclk should be multiplied by 32, when 32BitLR parameter is enabled */