src/dpdk/drivers/net/ice/base/ice_common.c
enum ice_status
ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
		   struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
{
	struct ice_aq_desc desc;
	enum ice_status status;

	if (!cfg)
		return ICE_ERR_PARAM;

	/* Ensure that only valid bits of cfg->caps can be turned on. */
	if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
		ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
			  cfg->caps);

		cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
	}

	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
	desc.params.set_phy.lport_num = pi->lport;
	desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);

	ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
	ice_debug(hw, ICE_DBG_LINK, "	phy_type_low = 0x%llx\n",
		  (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
	ice_debug(hw, ICE_DBG_LINK, "	phy_type_high = 0x%llx\n",
		  (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
	ice_debug(hw, ICE_DBG_LINK, "	caps = 0x%x\n", cfg->caps);
	ice_debug(hw, ICE_DBG_LINK, "	low_power_ctrl_an = 0x%x\n",
		  cfg->low_power_ctrl_an);
	ice_debug(hw, ICE_DBG_LINK, "	eee_cap = 0x%x\n", cfg->eee_cap);
	ice_debug(hw, ICE_DBG_LINK, "	eeer_value = 0x%x\n", cfg->eeer_value);
	ice_debug(hw, ICE_DBG_LINK, "	link_fec_opt = 0x%x\n",
		  cfg->link_fec_opt);

	status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);

	if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
		status = ICE_SUCCESS;

	if (!status)
		pi->phy.curr_user_phy_cfg = *cfg;

	return status;
}
/**
 * ice_aq_set_phy_cfg
 * @hw: pointer to the HW struct
 * @pi: port info structure of the interested logical port
 * @cfg: structure with PHY configuration data to be set
 * @cd: pointer to command details structure or NULL
 *
 * Set the various PHY configuration parameters supported on the Port.
 * One or more of the Set PHY config parameters may be ignored in an MFP
 * mode as the PF may not have the privilege to set some of the PHY Config
 * parameters. This status will be indicated by the command response (0x0601).
 */
ice_aq_set_phy_cfg
@hw: pointer to the HW struct
@pi: port info structure of the interested logical port
@cfg: structure with PHY configuration data to be set
@cd: pointer to command details structure or NULL

Set the various PHY configuration parameters supported on the Port.
One or more of the Set PHY config parameters may be ignored in an MFP
mode as the PF may not have the privilege to set some of the PHY Config
parameters. This status will be indicated by the command response (0x0601).
ice_aq_set_phy_cfg @hw : pointer to the HW struct @pi : port info structure of the interested logical port @cfg : structure with PHY configuration data to be set @cd : pointer to command details structure or NULL Set the various PHY configuration parameters supported on the Port . One or more of the Set PHY config parameters may be ignored in an MFP mode as the PF may not have the privilege to set some of the PHY Config parameters . This status will be indicated by the command response ( 0x0601 ) .
enum ice_status
ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
		   struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
{
	struct ice_aq_desc desc;
	enum ice_status status;
	if (!cfg)
		return ICE_ERR_PARAM;
	if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
		ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
			  cfg->caps);
		cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
	}
	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
	desc.params.set_phy.lport_num = pi->lport;
	desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
	ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
	ice_debug(hw, ICE_DBG_LINK, "	phy_type_low = 0x%llx\n",
		  (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
	ice_debug(hw, ICE_DBG_LINK, "	phy_type_high = 0x%llx\n",
		  (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
	ice_debug(hw, ICE_DBG_LINK, "	caps = 0x%x\n", cfg->caps);
	ice_debug(hw, ICE_DBG_LINK, "	low_power_ctrl_an = 0x%x\n",
		  cfg->low_power_ctrl_an);
	ice_debug(hw, ICE_DBG_LINK, "	eee_cap = 0x%x\n", cfg->eee_cap);
	ice_debug(hw, ICE_DBG_LINK, "	eeer_value = 0x%x\n", cfg->eeer_value);
	ice_debug(hw, ICE_DBG_LINK, "	link_fec_opt = 0x%x\n",
		  cfg->link_fec_opt);
	status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
	if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
		status = ICE_SUCCESS;
	if (!status)
		pi->phy.curr_user_phy_cfg = *cfg;
	return status;
}
enum ice_status ice_aq_set_phy_cfg ( struct ice_hw * hw , struct ice_port_info * pi , struct ice_aqc_set_phy_cfg_data * cfg , struct ice_sq_cd * cd ) { struct ice_aq_desc desc ; enum ice_status status ; if ( ! cfg ) return ICE_ERR_PARAM ; if ( cfg -> caps & ~ ICE_AQ_PHY_ENA_VALID_MASK ) { ice_debug ( hw , ICE_DBG_PHY , " \n " , cfg -> caps ) ; cfg -> caps &= ICE_AQ_PHY_ENA_VALID_MASK ; } ice_fill_dflt_direct_cmd_desc ( & desc , ice_aqc_opc_set_phy_cfg ) ; desc . params . set_phy . lport_num = pi -> lport ; desc . flags |= CPU_TO_LE16 ( ICE_AQ_FLAG_RD ) ; ice_debug ( hw , ICE_DBG_LINK , " \n " ) ; ice_debug ( hw , ICE_DBG_LINK , " \n " , ( unsigned long long ) LE64_TO_CPU ( cfg -> phy_type_low ) ) ; ice_debug ( hw , ICE_DBG_LINK , " \n " , ( unsigned long long ) LE64_TO_CPU ( cfg -> phy_type_high ) ) ; ice_debug ( hw , ICE_DBG_LINK , " \n " , cfg -> caps ) ; ice_debug ( hw , ICE_DBG_LINK , " \n " , cfg -> low_power_ctrl_an ) ; ice_debug ( hw , ICE_DBG_LINK , " \n " , cfg -> eee_cap ) ; ice_debug ( hw , ICE_DBG_LINK , " \n " , cfg -> eeer_value ) ; ice_debug ( hw , ICE_DBG_LINK , " \n " , cfg -> link_fec_opt ) ; status = ice_aq_send_cmd ( hw , & desc , cfg , sizeof ( * cfg ) , cd ) ; if ( hw -> adminq . sq_last_status == ICE_AQ_RC_EMODE ) status = ICE_SUCCESS ; if ( ! status ) pi -> phy . curr_user_phy_cfg = * cfg ; return status ; }
ice_aq_set_phy_cfg
 @hw: pointer to the HW struct
 @pi: port info structure of the interested logical port
 @cfg: structure with PHY configuration data to be set
 @cd: pointer to command details structure or NULL
ice_aq_set_phy_cfg @hw : pointer to the HW struct @pi : port info structure of the interested logical port @cfg : structure with PHY configuration data to be set @cd : pointer to command details structure or NULL
/* Ensure that only valid bits of cfg->caps can be turned on. */