XilinxProcessorIPLib/drivers/sysmonpsu/src/xsysmonpsu.c
s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
				u32 IncreaseAcqCycles, u32 IsEventMode,
				u32 IsDifferentialMode, u32 SysmonBlk)
{
	u32 RegValue;
	UINTPTR EffectiveBaseAddress;
	s32 Status;

	/* Assert the arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((Channel <= XSM_CH_SUPPLY3) ||
			  ((Channel >= XSM_CH_SUPPLY_CALIB) &&
			  (Channel <= XSM_CH_GAINERR_CALIB)) ||
			  ((Channel >= XSM_CH_SUPPLY4) &&
			  (Channel <= XSM_CH_TEMP_REMTE)) ||
			  ((Channel >= XSM_CH_VCC_PSLL0) &&
			  (Channel <= XSM_CH_RESERVE1)));
	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
			  (IncreaseAcqCycles == FALSE));
	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
	Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
			  (IsDifferentialMode == FALSE));
	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));

	/* Check if the device is in single channel mode else return failure */
	if ((XSysMonPsu_GetSequencerMode(InstancePtr, SysmonBlk)
				!= XSM_SEQ_MODE_SINGCHAN)) {
		Status = (s32)XST_FAILURE;
		goto End;
	}

	/* Calculate the effective baseaddress based on the Sysmon instance. */
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);

	/* Read the Configuration Register 0 and extract out Averaging value. */
	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
			XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;

	/*
	 * Select the number of acquisition cycles. The acquisition cycles is
	 * only valid for the external channels.
	 */
	if (IncreaseAcqCycles == 1U) {
		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
		    || (Channel == XSM_CH_VPVN)) {
			RegValue |= XSYSMONPSU_CFG_REG0_ACQ_MASK;
		} else {
			Status = (s32)XST_FAILURE;
			goto End;
		}
	}

	/*
	 * Select the input mode. The input mode is only valid for the
	 * external channels.
	 */
	if (IsDifferentialMode == 1U) {

		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
		    || (Channel == XSM_CH_VPVN)) {
			RegValue |= XSYSMONPSU_CFG_REG0_BU_MASK;
		} else {
			Status = (s32)XST_FAILURE;
			goto End;
		}
	}

	/* Select the ADC mode. */
	if (IsEventMode == 1U) {
		RegValue |= XSYSMONPSU_CFG_REG0_EC_MASK;
	}

	/* Write the given values into the Configuration Register 0. */
	RegValue |= ((u32)Channel & XSYSMONPSU_CFG_REG0_MUX_CH_MASK);
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
			 RegValue);

	Status = (s32)XST_SUCCESS;

End:
	return Status;
}
/****************************************************************************/
/**
*
* The function sets the given parameters in the Configuration Register 0 in
* the single channel mode.
*
* @param	InstancePtr is a pointer to the XSysMonPsu instance.
* @param	Channel is the channel number for conversion. The valid
*		channels are 0 - 6, 8 - 10, 13 - 37.
* @param	IncreaseAcqCycles is a boolean parameter which specifies whether
*		the Acquisition time for the external channels has to be
*		increased to 10 ADCCLK cycles (specify TRUE) or remain at the
*		default 4 ADCCLK cycles (specify FALSE). This parameter is
*		only valid for the external channels.
* @param	IsEventMode is a boolean parameter that specifies continuous
*		sampling (specify FALSE) or event driven sampling mode (specify
*		TRUE) for the given channel.
* @param	IsDifferentialMode is a boolean parameter which specifies
*		unipolar(specify FALSE) or differential mode (specify TRUE) for
*		the analog inputs. The 	input mode is only valid for the
*		external channels.
* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
*       block or PL Sysmon block register region.
*
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the Configuration Register 0.
*		- XST_FAILURE if the channel sequencer is enabled or the input
*		parameters are not valid for the selected channel.
*
* @note
*		- The number of samples for the averaging for all the channels
*		is set by using the function XSysMonPsu_SetAvg.
*		- The calibration of the device is done by doing a ADC
*		conversion on the calibration channel(channel 8). The input
*		parameters IncreaseAcqCycles, IsDifferentialMode and
*		IsEventMode are not valid for this channel.
*
*****************************************************************************/
The function sets the given parameters in the Configuration Register 0 in
the single channel mode.
The function sets the given parameters in the Configuration Register 0 in the single channel mode .
s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
				u32 IncreaseAcqCycles, u32 IsEventMode,
				u32 IsDifferentialMode, u32 SysmonBlk)
{
	u32 RegValue;
	UINTPTR EffectiveBaseAddress;
	s32 Status;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((Channel <= XSM_CH_SUPPLY3) ||
			  ((Channel >= XSM_CH_SUPPLY_CALIB) &&
			  (Channel <= XSM_CH_GAINERR_CALIB)) ||
			  ((Channel >= XSM_CH_SUPPLY4) &&
			  (Channel <= XSM_CH_TEMP_REMTE)) ||
			  ((Channel >= XSM_CH_VCC_PSLL0) &&
			  (Channel <= XSM_CH_RESERVE1)));
	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
			  (IncreaseAcqCycles == FALSE));
	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
	Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
			  (IsDifferentialMode == FALSE));
	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
	if ((XSysMonPsu_GetSequencerMode(InstancePtr, SysmonBlk)
				!= XSM_SEQ_MODE_SINGCHAN)) {
		Status = (s32)XST_FAILURE;
		goto End;
	}
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);
	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
			XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;
	if (IncreaseAcqCycles == 1U) {
		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
		    || (Channel == XSM_CH_VPVN)) {
			RegValue |= XSYSMONPSU_CFG_REG0_ACQ_MASK;
		} else {
			Status = (s32)XST_FAILURE;
			goto End;
		}
	}
	if (IsDifferentialMode == 1U) {
		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
		    || (Channel == XSM_CH_VPVN)) {
			RegValue |= XSYSMONPSU_CFG_REG0_BU_MASK;
		} else {
			Status = (s32)XST_FAILURE;
			goto End;
		}
	}
	if (IsEventMode == 1U) {
		RegValue |= XSYSMONPSU_CFG_REG0_EC_MASK;
	}
	RegValue |= ((u32)Channel & XSYSMONPSU_CFG_REG0_MUX_CH_MASK);
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
			 RegValue);
	Status = (s32)XST_SUCCESS;
End:
	return Status;
}
s32 XSysMonPsu_SetSingleChParams ( XSysMonPsu * InstancePtr , u8 Channel , u32 IncreaseAcqCycles , u32 IsEventMode , u32 IsDifferentialMode , u32 SysmonBlk ) { u32 RegValue ; UINTPTR EffectiveBaseAddress ; s32 Status ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Xil_AssertNonvoid ( ( Channel <= XSM_CH_SUPPLY3 ) || ( ( Channel >= XSM_CH_SUPPLY_CALIB ) && ( Channel <= XSM_CH_GAINERR_CALIB ) ) || ( ( Channel >= XSM_CH_SUPPLY4 ) && ( Channel <= XSM_CH_TEMP_REMTE ) ) || ( ( Channel >= XSM_CH_VCC_PSLL0 ) && ( Channel <= XSM_CH_RESERVE1 ) ) ) ; Xil_AssertNonvoid ( ( IncreaseAcqCycles == TRUE ) || ( IncreaseAcqCycles == FALSE ) ) ; Xil_AssertNonvoid ( ( IsEventMode == TRUE ) || ( IsEventMode == FALSE ) ) ; Xil_AssertNonvoid ( ( IsDifferentialMode == TRUE ) || ( IsDifferentialMode == FALSE ) ) ; Xil_AssertNonvoid ( ( SysmonBlk == XSYSMON_PS ) || ( SysmonBlk == XSYSMON_PL ) ) ; if ( ( XSysMonPsu_GetSequencerMode ( InstancePtr , SysmonBlk ) != XSM_SEQ_MODE_SINGCHAN ) ) { Status = ( s32 ) XST_FAILURE ; goto End ; } EffectiveBaseAddress = XSysMonPsu_GetEffBaseAddress ( InstancePtr -> Config . BaseAddress , SysmonBlk ) ; RegValue = XSysmonPsu_ReadReg ( EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET ) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK ; if ( IncreaseAcqCycles == 1U ) { if ( ( ( Channel >= XSM_CH_AUX_MIN ) && ( Channel <= XSM_CH_AUX_MAX ) ) || ( Channel == XSM_CH_VPVN ) ) { RegValue |= XSYSMONPSU_CFG_REG0_ACQ_MASK ; } else { Status = ( s32 ) XST_FAILURE ; goto End ; } } if ( IsDifferentialMode == 1U ) { if ( ( ( Channel >= XSM_CH_AUX_MIN ) && ( Channel <= XSM_CH_AUX_MAX ) ) || ( Channel == XSM_CH_VPVN ) ) { RegValue |= XSYSMONPSU_CFG_REG0_BU_MASK ; } else { Status = ( s32 ) XST_FAILURE ; goto End ; } } if ( IsEventMode == 1U ) { RegValue |= XSYSMONPSU_CFG_REG0_EC_MASK ; } RegValue |= ( ( u32 ) Channel & XSYSMONPSU_CFG_REG0_MUX_CH_MASK ) ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET , RegValue ) ; Status = ( s32 ) XST_SUCCESS ; End : return Status ; }
The function sets the given parameters in the Configuration Register 0 in
the single channel mode.
The function sets the given parameters in the Configuration Register 0 in the single channel mode .
/* Assert the arguments. */ /* Check if the device is in single channel mode else return failure */ /* Calculate the effective baseaddress based on the Sysmon instance. */ /* Read the Configuration Register 0 and extract out Averaging value. */ /*
	 * Select the number of acquisition cycles. The acquisition cycles is
	 * only valid for the external channels.
	 */ /*
	 * Select the input mode. The input mode is only valid for the
	 * external channels.
	 */ /* Select the ADC mode. */ /* Write the given values into the Configuration Register 0. */