lib/sw_apps/mba_fs_boot/src/fs-boot.c
static void flash_readarray_mode(unsigned long flash_addr)
{

	/*
	 * We assume it is all CFI FLASH
	 * Write 32-bit to take care off all flash
	 * configurations.
	 */
	/*
	 * The axi_emc_v1_01_a core is not able to response/react to the
	 * subsequent read operation immediately while it is busy
	 * performing write operation ( e.g. four 8-bit flash write or
	 * 2 16-bit flash write ).
	 *
	 * The temporary workaround is issue four 8bit bus write instead
	 * of a single 32bit bus write. This is temporary solution until
	 * axi_emc is fixed.
	 */
	*((volatile unsigned char *)(flash_addr)) = 0xFF;
	*((volatile unsigned char *)((flash_addr)+1)) = 0xFF;
	*((volatile unsigned char *)((flash_addr)+2)) = 0xFF;
	*((volatile unsigned char *)((flash_addr)+3)) = 0xFF;
}
/*!
 * This routine send a command to the CUI
 * to put the FLASH into Read Array mode.
 *
 * @param  addr - Memory address of FLASH device
 *
 * @return  none
 */
This routine send a command to the CUI
to put the FLASH into Read Array mode.

@param  addr - Memory address of FLASH device

@return  none
This routine send a command to the CUI to put the FLASH into Read Array mode . @param addr - Memory address of FLASH device @return none
static void flash_readarray_mode(unsigned long flash_addr)
{
	*((volatile unsigned char *)(flash_addr)) = 0xFF;
	*((volatile unsigned char *)((flash_addr)+1)) = 0xFF;
	*((volatile unsigned char *)((flash_addr)+2)) = 0xFF;
	*((volatile unsigned char *)((flash_addr)+3)) = 0xFF;
}
static void flash_readarray_mode ( unsigned long flash_addr ) { * ( ( volatile unsigned char * ) ( flash_addr ) ) = 0xFF ; * ( ( volatile unsigned char * ) ( ( flash_addr ) + 1 ) ) = 0xFF ; * ( ( volatile unsigned char * ) ( ( flash_addr ) + 2 ) ) = 0xFF ; * ( ( volatile unsigned char * ) ( ( flash_addr ) + 3 ) ) = 0xFF ; }
This routine send a command to the CUI
 to put the FLASH into Read Array mode.
This routine send a command to the CUI to put the FLASH into Read Array mode .
/*
	 * We assume it is all CFI FLASH
	 * Write 32-bit to take care off all flash
	 * configurations.
	 */ /*
	 * The axi_emc_v1_01_a core is not able to response/react to the
	 * subsequent read operation immediately while it is busy
	 * performing write operation ( e.g. four 8-bit flash write or
	 * 2 16-bit flash write ).
	 *
	 * The temporary workaround is issue four 8bit bus write instead
	 * of a single 32bit bus write. This is temporary solution until
	 * axi_emc is fixed.
	 */