src/dpdk/drivers/net/ice/base/ice_common.c
enum ice_status
ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
		enum ice_fec_mode fec)
{
	struct ice_aqc_get_phy_caps_data *pcaps;
	enum ice_status status = ICE_SUCCESS;
	struct ice_hw *hw;

	if (!pi || !cfg)
		return ICE_ERR_BAD_PTR;

	hw = pi->hw;

	pcaps = (struct ice_aqc_get_phy_caps_data *)
		ice_malloc(hw, sizeof(*pcaps));
	if (!pcaps)
		return ICE_ERR_NO_MEMORY;

	status = ice_aq_get_phy_caps(pi, false,
				     (ice_fw_supports_report_dflt_cfg(hw) ?
				      ICE_AQC_REPORT_DFLT_CFG :
				      ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL);

	if (status)
		goto out;

	cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
	cfg->link_fec_opt = pcaps->link_fec_options;

	switch (fec) {
	case ICE_FEC_BASER:
		/* Clear RS bits, and AND BASE-R ability
		 * bits and OR request bits.
		 */
		cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
			ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
		cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
			ICE_AQC_PHY_FEC_25G_KR_REQ;
		break;
	case ICE_FEC_RS:
		/* Clear BASE-R bits, and AND RS ability
		 * bits and OR request bits.
		 */
		cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
		cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
			ICE_AQC_PHY_FEC_25G_RS_544_REQ;
		break;
	case ICE_FEC_NONE:
		/* Clear all FEC option bits. */
		cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
		break;
	case ICE_FEC_AUTO:
		/* AND auto FEC bit, and all caps bits. */
		cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
		cfg->link_fec_opt |= pcaps->link_fec_options;
		break;
	default:
		status = ICE_ERR_PARAM;
		break;
	}

	if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) &&
	    !ice_fw_supports_report_dflt_cfg(pi->hw)) {
		struct ice_link_default_override_tlv tlv;

		if (ice_get_link_default_override(&tlv, pi))
			goto out;

		if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
		    (tlv.options & ICE_LINK_OVERRIDE_EN))
			cfg->link_fec_opt = tlv.fec_options;
	}

out:
	ice_free(hw, pcaps);

	return status;
}
/**
 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
 * @pi: port information structure
 * @cfg: PHY configuration data to set FEC mode
 * @fec: FEC mode to configure
 */
Configure PHY FEC data based on FEC mode
@pi: port information structure
@cfg: PHY configuration data to set FEC mode
@fec: FEC mode to configure
Configure PHY FEC data based on FEC mode @pi : port information structure @cfg : PHY configuration data to set FEC mode @fec : FEC mode to configure
enum ice_status
ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
		enum ice_fec_mode fec)
{
	struct ice_aqc_get_phy_caps_data *pcaps;
	enum ice_status status = ICE_SUCCESS;
	struct ice_hw *hw;
	if (!pi || !cfg)
		return ICE_ERR_BAD_PTR;
	hw = pi->hw;
	pcaps = (struct ice_aqc_get_phy_caps_data *)
		ice_malloc(hw, sizeof(*pcaps));
	if (!pcaps)
		return ICE_ERR_NO_MEMORY;
	status = ice_aq_get_phy_caps(pi, false,
				     (ice_fw_supports_report_dflt_cfg(hw) ?
				      ICE_AQC_REPORT_DFLT_CFG :
				      ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL);
	if (status)
		goto out;
	cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
	cfg->link_fec_opt = pcaps->link_fec_options;
	switch (fec) {
	case ICE_FEC_BASER:
		cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
			ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
		cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
			ICE_AQC_PHY_FEC_25G_KR_REQ;
		break;
	case ICE_FEC_RS:
		cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
		cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
			ICE_AQC_PHY_FEC_25G_RS_544_REQ;
		break;
	case ICE_FEC_NONE:
		cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
		break;
	case ICE_FEC_AUTO:
		cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
		cfg->link_fec_opt |= pcaps->link_fec_options;
		break;
	default:
		status = ICE_ERR_PARAM;
		break;
	}
	if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) &&
	    !ice_fw_supports_report_dflt_cfg(pi->hw)) {
		struct ice_link_default_override_tlv tlv;
		if (ice_get_link_default_override(&tlv, pi))
			goto out;
		if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
		    (tlv.options & ICE_LINK_OVERRIDE_EN))
			cfg->link_fec_opt = tlv.fec_options;
	}
out:
	ice_free(hw, pcaps);
	return status;
}
enum ice_status ice_cfg_phy_fec ( struct ice_port_info * pi , struct ice_aqc_set_phy_cfg_data * cfg , enum ice_fec_mode fec ) { struct ice_aqc_get_phy_caps_data * pcaps ; enum ice_status status = ICE_SUCCESS ; struct ice_hw * hw ; if ( ! pi || ! cfg ) return ICE_ERR_BAD_PTR ; hw = pi -> hw ; pcaps = ( struct ice_aqc_get_phy_caps_data * ) ice_malloc ( hw , sizeof ( * pcaps ) ) ; if ( ! pcaps ) return ICE_ERR_NO_MEMORY ; status = ice_aq_get_phy_caps ( pi , false , ( ice_fw_supports_report_dflt_cfg ( hw ) ? ICE_AQC_REPORT_DFLT_CFG : ICE_AQC_REPORT_TOPO_CAP_MEDIA ) , pcaps , NULL ) ; if ( status ) goto out ; cfg -> caps |= ( pcaps -> caps & ICE_AQC_PHY_EN_AUTO_FEC ) ; cfg -> link_fec_opt = pcaps -> link_fec_options ; switch ( fec ) { case ICE_FEC_BASER : cfg -> link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN ; cfg -> link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | ICE_AQC_PHY_FEC_25G_KR_REQ ; break ; case ICE_FEC_RS : cfg -> link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN ; cfg -> link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | ICE_AQC_PHY_FEC_25G_RS_544_REQ ; break ; case ICE_FEC_NONE : cfg -> link_fec_opt &= ~ ICE_AQC_PHY_FEC_MASK ; break ; case ICE_FEC_AUTO : cfg -> caps &= ICE_AQC_PHY_CAPS_MASK ; cfg -> link_fec_opt |= pcaps -> link_fec_options ; break ; default : status = ICE_ERR_PARAM ; break ; } if ( fec == ICE_FEC_AUTO && ice_fw_supports_link_override ( pi -> hw ) && ! ice_fw_supports_report_dflt_cfg ( pi -> hw ) ) { struct ice_link_default_override_tlv tlv ; if ( ice_get_link_default_override ( & tlv , pi ) ) goto out ; if ( ! ( tlv . options & ICE_LINK_OVERRIDE_STRICT_MODE ) && ( tlv . options & ICE_LINK_OVERRIDE_EN ) ) cfg -> link_fec_opt = tlv . fec_options ; } out : ice_free ( hw , pcaps ) ; return status ; }
ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
 @pi: port information structure
 @cfg: PHY configuration data to set FEC mode
 @fec: FEC mode to configure
ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode @pi : port information structure @cfg : PHY configuration data to set FEC mode @fec : FEC mode to configure
/* Clear RS bits, and AND BASE-R ability
		 * bits and OR request bits.
		 */ /* Clear BASE-R bits, and AND RS ability
		 * bits and OR request bits.
		 */ /* Clear all FEC option bits. */ /* AND auto FEC bit, and all caps bits. */