lib/bsp/standalone/src/arm/ARMv8/32bit/xil_cache.c
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
{
	const u32 cacheline = 64U;
	u32 end;
	u32 tempadr = adr;
	u32 tempend;
	u32 currmask;

	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);
	if (len != 0U) {
		end = tempadr + len;
		tempend = end;

		if ((tempadr & (cacheline-1U)) != 0U) {
			tempadr &= (~(cacheline - 1U));
			Xil_DCacheFlushLine(tempadr);
			tempadr += cacheline;
		}
		if ((tempend & (cacheline-1U)) != 0U) {
			tempend &= (~(cacheline - 1U));
			Xil_DCacheFlushLine(tempend);
		}

		while (tempadr < tempend) {
			/* Select cache level 0 and D cache in CSSR */
			mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
			/* Invalidate Data cache line */
			mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC,
				(tempadr & (~0x3F)));
			/* Wait for invalidate to complete */
			dsb();
			/* Select cache level 0 and D cache in CSSR */
			mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
			/* Invalidate Data cache line */
			mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC,
				(tempadr & (~0x3F)));
			/* Wait for invalidate to complete */
			dsb();
			tempadr += cacheline;
		}
	}
	mtcpsr(currmask);
}
/****************************************************************************/
/**
 * @brief	Invalidate the Data cache for the given address range.
 *		The cachelines present in the adderss range are cleaned and
 *		invalidated
 *
 * @param	adr: 32bit start address of the range to be invalidated.
 * @param	len: Length of the range to be invalidated in bytes.
 *
 * @return	None.
 *
 * @note	In Cortex-A53, functionality to simply invalid the cachelines
 *		is not present. Such operations are a problem for an
 *		environment that supports virtualisation. It would allow
 *		one OS to invalidate a line belonging to another OS.
 *		This could lead to the other OS crashing because of the
 *		loss of essential data. Hence, such operations are promoted
 *		to clean and invalidate to avoid such corruption.
 *
 ****************************************************************************/
@brief       Invalidate the Data cache for the given address range.
The cachelines present in the adderss range are cleaned and
invalidated

@param       adr: 32bit start address of the range to be invalidated.
@param       len: Length of the range to be invalidated in bytes.

@return      None.

@note        In Cortex-A53, functionality to simply invalid the cachelines
is not present. Such operations are a problem for an
environment that supports virtualisation. It would allow
one OS to invalidate a line belonging to another OS.
This could lead to the other OS crashing because of the
loss of essential data. Hence, such operations are promoted
to clean and invalidate to avoid such corruption.
@brief Invalidate the Data cache for the given address range . The cachelines present in the adderss range are cleaned and invalidated @param adr : 32bit start address of the range to be invalidated . @param len : Length of the range to be invalidated in bytes . @return None . @note In Cortex - A53 functionality to simply invalid the cachelines is not present . Such operations are a problem for an environment that supports virtualisation . It would allow one OS to invalidate a line belonging to another OS . This could lead to the other OS crashing because of the loss of essential data . Hence such operations are promoted to clean and invalidate to avoid such corruption .
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
{
	const u32 cacheline = 64U;
	u32 end;
	u32 tempadr = adr;
	u32 tempend;
	u32 currmask;
	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);
	if (len != 0U) {
		end = tempadr + len;
		tempend = end;
		if ((tempadr & (cacheline-1U)) != 0U) {
			tempadr &= (~(cacheline - 1U));
			Xil_DCacheFlushLine(tempadr);
			tempadr += cacheline;
		}
		if ((tempend & (cacheline-1U)) != 0U) {
			tempend &= (~(cacheline - 1U));
			Xil_DCacheFlushLine(tempend);
		}
		while (tempadr < tempend) {
			mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
			mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC,
				(tempadr & (~0x3F)));
			dsb();
			mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
			mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC,
				(tempadr & (~0x3F)));
			dsb();
			tempadr += cacheline;
		}
	}
	mtcpsr(currmask);
}
void Xil_DCacheInvalidateRange ( INTPTR adr , u32 len ) { const u32 cacheline = 64U ; u32 end ; u32 tempadr = adr ; u32 tempend ; u32 currmask ; currmask = mfcpsr ( ) ; mtcpsr ( currmask | IRQ_FIQ_MASK ) ; if ( len != 0U ) { end = tempadr + len ; tempend = end ; if ( ( tempadr & ( cacheline - 1U ) ) != 0U ) { tempadr &= ( ~ ( cacheline - 1U ) ) ; Xil_DCacheFlushLine ( tempadr ) ; tempadr += cacheline ; } if ( ( tempend & ( cacheline - 1U ) ) != 0U ) { tempend &= ( ~ ( cacheline - 1U ) ) ; Xil_DCacheFlushLine ( tempend ) ; } while ( tempadr < tempend ) { mtcp ( XREG_CP15_CACHE_SIZE_SEL , 0x0 ) ; mtcp ( XREG_CP15_INVAL_DC_LINE_MVA_POC , ( tempadr & ( ~ 0x3F ) ) ) ; dsb ( ) ; mtcp ( XREG_CP15_CACHE_SIZE_SEL , 0x2 ) ; mtcp ( XREG_CP15_INVAL_DC_LINE_MVA_POC , ( tempadr & ( ~ 0x3F ) ) ) ; dsb ( ) ; tempadr += cacheline ; } } mtcpsr ( currmask ) ; }
@brief       Invalidate the Data cache for the given address range.
@brief Invalidate the Data cache for the given address range .
/* Select cache level 0 and D cache in CSSR */ /* Invalidate Data cache line */ /* Wait for invalidate to complete */ /* Select cache level 0 and D cache in CSSR */ /* Invalidate Data cache line */ /* Wait for invalidate to complete */