XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_hdmi_intr.c
void XHdmiphy1_HdmiRxClkDetFreqChangeHandler(XHdmiphy1 *InstancePtr)
{
    XHdmiphy1_PllType PllType;
    u32 RxRefClkHz;
    u8 Id, Id0, Id1;

    if (InstancePtr->RxHdmi21Cfg.IsEnabled) {
        if (InstancePtr->Config.RxRefClkSel !=
                InstancePtr->Config.RxFrlRefClkSel) {
            return;
        }
    }

    XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_RX_FREQ, 0);

    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].RxState =
            XHDMIPHY1_GT_STATE_IDLE;
    }

    if (!InstancePtr->RxHdmi21Cfg.IsEnabled) {
        /* Mask the MMCM Lock */
        XHdmiphy1_MmcmLockedMaskEnable(InstancePtr, 0, XHDMIPHY1_DIR_RX, TRUE);
    }

    /* Determine PLL type and RX reference clock selection. */
    PllType = XHdmiphy1_GetPllType(InstancePtr, 0, XHDMIPHY1_DIR_RX,
            XHDMIPHY1_CHANNEL_ID_CH1);

    /* Fetch New RX Reference Clock Frequency */
    RxRefClkHz = XHdmiphy1_ClkDetGetRefClkFreqHz(InstancePtr,
                    XHDMIPHY1_DIR_RX);

    /* Round input frequency to 10 kHz. */
    RxRefClkHz = (RxRefClkHz+5000) / 10000;
    RxRefClkHz = RxRefClkHz * 10000;

    /* Store RX reference clock. */
    if (InstancePtr->RxHdmi21Cfg.IsEnabled) {
        InstancePtr->HdmiRxRefClkHz = XHDMIPHY1_HDMI21_FRL_REFCLK;
    }
    else {
        InstancePtr->HdmiRxRefClkHz = RxRefClkHz;
    }

    /* If the RX frequency has changed, the PLL is always disabled. */
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    XHdmiphy1_PowerDownGtPll(InstancePtr, 0,
        (PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
        XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA, TRUE);

    XHdmiphy1_ResetGtPll(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
        XHDMIPHY1_DIR_RX, TRUE);
#else
	/* Suppress Warning Messages */
    PllType = PllType;

    /* Mask RESET DONE */
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, XHDMIPHY1_RX_INIT_REG,
			(XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
					XHDMIPHY1_RX_INIT_REG) | 0x10101010));

#endif

    /* If DRU is present, disable it and assert reset. */
    if (InstancePtr->Config.DruIsPresent) {
        XHdmiphy1_DruReset(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, TRUE);
        XHdmiphy1_DruEnable(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, FALSE);
    }

    /* Clear RX timer. */
    XHdmiphy1_ClkDetTimerClear(InstancePtr, 0, XHDMIPHY1_DIR_RX);

    /* If there is reference clock, load RX timer in usec.
     * The reference clock should be larger than 25Mhz. We are using a 20Mhz
     * instead to keep some margin for errors. */
    if (RxRefClkHz > 20000000) {
        XHdmiphy1_ClkDetTimerLoad(InstancePtr, 0, XHDMIPHY1_DIR_RX,
                        InstancePtr->Config.AxiLiteClkFreq/1000);

        /* Callback to re-initialize. */
        if (InstancePtr->HdmiRxInitCallback) {
            InstancePtr->HdmiRxInitCallback(InstancePtr->HdmiRxInitRef);
        }
    }
}
/*****************************************************************************/
/**
* This function is the handler for events triggered by a change in RX frequency
* as detected by the HDMI clock detector logic.
*
* @param    InstancePtr is a pointer to the HDMIPHY instance.
*
* @return   None.
*
* @note     None.
*
******************************************************************************/
This function is the handler for events triggered by a change in RX frequency
as detected by the HDMI clock detector logic.
This function is the handler for events triggered by a change in RX frequency as detected by the HDMI clock detector logic .
void XHdmiphy1_HdmiRxClkDetFreqChangeHandler(XHdmiphy1 *InstancePtr)
{
    XHdmiphy1_PllType PllType;
    u32 RxRefClkHz;
    u8 Id, Id0, Id1;
    if (InstancePtr->RxHdmi21Cfg.IsEnabled) {
        if (InstancePtr->Config.RxRefClkSel !=
                InstancePtr->Config.RxFrlRefClkSel) {
            return;
        }
    }
    XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_RX_FREQ, 0);
    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].RxState =
            XHDMIPHY1_GT_STATE_IDLE;
    }
    if (!InstancePtr->RxHdmi21Cfg.IsEnabled) {
        XHdmiphy1_MmcmLockedMaskEnable(InstancePtr, 0, XHDMIPHY1_DIR_RX, TRUE);
    }
    PllType = XHdmiphy1_GetPllType(InstancePtr, 0, XHDMIPHY1_DIR_RX,
            XHDMIPHY1_CHANNEL_ID_CH1);
    RxRefClkHz = XHdmiphy1_ClkDetGetRefClkFreqHz(InstancePtr,
                    XHDMIPHY1_DIR_RX);
    RxRefClkHz = (RxRefClkHz+5000) / 10000;
    RxRefClkHz = RxRefClkHz * 10000;
    if (InstancePtr->RxHdmi21Cfg.IsEnabled) {
        InstancePtr->HdmiRxRefClkHz = XHDMIPHY1_HDMI21_FRL_REFCLK;
    }
    else {
        InstancePtr->HdmiRxRefClkHz = RxRefClkHz;
    }
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    XHdmiphy1_PowerDownGtPll(InstancePtr, 0,
        (PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
        XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA, TRUE);
    XHdmiphy1_ResetGtPll(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
        XHDMIPHY1_DIR_RX, TRUE);
#else
    PllType = PllType;
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, XHDMIPHY1_RX_INIT_REG,
			(XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
					XHDMIPHY1_RX_INIT_REG) | 0x10101010));
#endif
    if (InstancePtr->Config.DruIsPresent) {
        XHdmiphy1_DruReset(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, TRUE);
        XHdmiphy1_DruEnable(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, FALSE);
    }
    XHdmiphy1_ClkDetTimerClear(InstancePtr, 0, XHDMIPHY1_DIR_RX);
    if (RxRefClkHz > 20000000) {
        XHdmiphy1_ClkDetTimerLoad(InstancePtr, 0, XHDMIPHY1_DIR_RX,
                        InstancePtr->Config.AxiLiteClkFreq/1000);
        if (InstancePtr->HdmiRxInitCallback) {
            InstancePtr->HdmiRxInitCallback(InstancePtr->HdmiRxInitRef);
        }
    }
}
void XHdmiphy1_HdmiRxClkDetFreqChangeHandler ( XHdmiphy1 * InstancePtr ) { XHdmiphy1_PllType PllType ; u32 RxRefClkHz ; u8 Id , Id0 , Id1 ; if ( InstancePtr -> RxHdmi21Cfg . IsEnabled ) { if ( InstancePtr -> Config . RxRefClkSel != InstancePtr -> Config . RxFrlRefClkSel ) { return ; } } XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_RX_FREQ , 0 ) ; XHdmiphy1_Ch2Ids ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . RxState = XHDMIPHY1_GT_STATE_IDLE ; } if ( ! InstancePtr -> RxHdmi21Cfg . IsEnabled ) { XHdmiphy1_MmcmLockedMaskEnable ( InstancePtr , 0 , XHDMIPHY1_DIR_RX , TRUE ) ; } PllType = XHdmiphy1_GetPllType ( InstancePtr , 0 , XHDMIPHY1_DIR_RX , XHDMIPHY1_CHANNEL_ID_CH1 ) ; RxRefClkHz = XHdmiphy1_ClkDetGetRefClkFreqHz ( InstancePtr , XHDMIPHY1_DIR_RX ) ; RxRefClkHz = ( RxRefClkHz + 5000 ) / 10000 ; RxRefClkHz = RxRefClkHz * 10000 ; if ( InstancePtr -> RxHdmi21Cfg . IsEnabled ) { InstancePtr -> HdmiRxRefClkHz = XHDMIPHY1_HDMI21_FRL_REFCLK ; } else { InstancePtr -> HdmiRxRefClkHz = RxRefClkHz ; } #if ( XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5 ) XHdmiphy1_PowerDownGtPll ( InstancePtr , 0 , ( PllType == XHDMIPHY1_PLL_TYPE_CPLL ) ? XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA , TRUE ) ; XHdmiphy1_ResetGtPll ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_RX , TRUE ) ; #else PllType = PllType ; XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_RX_INIT_REG , ( XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_RX_INIT_REG ) | 0x10101010 ) ) ; #endif if ( InstancePtr -> Config . DruIsPresent ) { XHdmiphy1_DruReset ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , TRUE ) ; XHdmiphy1_DruEnable ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , FALSE ) ; } XHdmiphy1_ClkDetTimerClear ( InstancePtr , 0 , XHDMIPHY1_DIR_RX ) ; if ( RxRefClkHz > 20000000 ) { XHdmiphy1_ClkDetTimerLoad ( InstancePtr , 0 , XHDMIPHY1_DIR_RX , InstancePtr -> Config . AxiLiteClkFreq / 1000 ) ; if ( InstancePtr -> HdmiRxInitCallback ) { InstancePtr -> HdmiRxInitCallback ( InstancePtr -> HdmiRxInitRef ) ; } } }
This function is the handler for events triggered by a change in RX frequency
as detected by the HDMI clock detector logic.
This function is the handler for events triggered by a change in RX frequency as detected by the HDMI clock detector logic .
/* Mask the MMCM Lock */ /* Determine PLL type and RX reference clock selection. */ /* Fetch New RX Reference Clock Frequency */ /* Round input frequency to 10 kHz. */ /* Store RX reference clock. */ /* If the RX frequency has changed, the PLL is always disabled. */ /* Suppress Warning Messages */ /* Mask RESET DONE */ /* If DRU is present, disable it and assert reset. */ /* Clear RX timer. */ /* If there is reference clock, load RX timer in usec.
     * The reference clock should be larger than 25Mhz. We are using a 20Mhz
     * instead to keep some margin for errors. */ /* Callback to re-initialize. */