XilinxProcessorIPLib/drivers/devcfg/src/xdevcfg.c
u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
{

	u32 RegData;

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/* Read the PCAP status register for DMA status */
	RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
					XDCFG_STATUS_OFFSET);

	if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
				XDCFG_STATUS_DMA_CMD_Q_F_MASK){
		return XST_SUCCESS;
	}

	return XST_FAILURE;
}
/******************************************************************************/
/**
*
* This function checks if DMA command queue is full.
*
* @param	InstancePtr is a pointer to the XDcfg instance.
*
* @return	XST_SUCCESS is the DMA is busy
*		XST_FAILURE if the DMA is idle
*
* @note		The DMA queue has a depth of two.
*
****************************************************************************/
This function checks if DMA command queue is full.
This function checks if DMA command queue is full .
u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
{
	u32 RegData;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
					XDCFG_STATUS_OFFSET);
	if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
				XDCFG_STATUS_DMA_CMD_Q_F_MASK){
		return XST_SUCCESS;
	}
	return XST_FAILURE;
}
u32 XDcfg_IsDmaBusy ( XDcfg * InstancePtr ) { u32 RegData ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; RegData = XDcfg_ReadReg ( InstancePtr -> Config . BaseAddr , XDCFG_STATUS_OFFSET ) ; if ( ( RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK ) == XDCFG_STATUS_DMA_CMD_Q_F_MASK ) { return XST_SUCCESS ; } return XST_FAILURE ; }
This function checks if DMA command queue is full.
This function checks if DMA command queue is full .
/* Read the PCAP status register for DMA status */