src/dpdk/drivers/net/ice/base/ice_common.c
static enum ice_status ice_pf_reset(struct ice_hw *hw)
{
	u32 cnt, reg;

	/* If at function entry a global reset was already in progress, i.e.
	 * state is not 'device active' or any of the reset done bits are not
	 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
	 * global reset is done.
	 */
	if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
	    (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
		/* poll on global reset currently in progress until done */
		if (ice_check_reset(hw))
			return ICE_ERR_RESET_FAILED;

		return ICE_SUCCESS;
	}

	/* Reset the PF */
	reg = rd32(hw, PFGEN_CTRL);

	wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));

	/* Wait for the PFR to complete. The wait time is the global config lock
	 * timeout plus the PFR timeout which will account for a possible reset
	 * that is occurring during a download package operation.
	 */
	for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
	     ICE_PF_RESET_WAIT_COUNT; cnt++) {
		reg = rd32(hw, PFGEN_CTRL);
		if (!(reg & PFGEN_CTRL_PFSWR_M))
			break;

		ice_msec_delay(1, true);
	}

	if (cnt == ICE_PF_RESET_WAIT_COUNT) {
		ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
		return ICE_ERR_RESET_FAILED;
	}

	return ICE_SUCCESS;
}
/**
 * ice_pf_reset - Reset the PF
 * @hw: pointer to the hardware structure
 *
 * If a global reset has been triggered, this function checks
 * for its completion and then issues the PF reset
 */
Reset the PF
@hw: pointer to the hardware structure

If a global reset has been triggered, this function checks
for its completion and then issues the PF reset
Reset the PF @hw : pointer to the hardware structure If a global reset has been triggered this function checks for its completion and then issues the PF reset
static enum ice_status ice_pf_reset(struct ice_hw *hw)
{
	u32 cnt, reg;
	if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
	    (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
		if (ice_check_reset(hw))
			return ICE_ERR_RESET_FAILED;
		return ICE_SUCCESS;
	}
	reg = rd32(hw, PFGEN_CTRL);
	wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
	for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
	     ICE_PF_RESET_WAIT_COUNT; cnt++) {
		reg = rd32(hw, PFGEN_CTRL);
		if (!(reg & PFGEN_CTRL_PFSWR_M))
			break;
		ice_msec_delay(1, true);
	}
	if (cnt == ICE_PF_RESET_WAIT_COUNT) {
		ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
		return ICE_ERR_RESET_FAILED;
	}
	return ICE_SUCCESS;
}
static enum ice_status ice_pf_reset ( struct ice_hw * hw ) { u32 cnt , reg ; if ( ( rd32 ( hw , GLGEN_RSTAT ) & GLGEN_RSTAT_DEVSTATE_M ) || ( rd32 ( hw , GLNVM_ULD ) & ICE_RESET_DONE_MASK ) ^ ICE_RESET_DONE_MASK ) { if ( ice_check_reset ( hw ) ) return ICE_ERR_RESET_FAILED ; return ICE_SUCCESS ; } reg = rd32 ( hw , PFGEN_CTRL ) ; wr32 ( hw , PFGEN_CTRL , ( reg | PFGEN_CTRL_PFSWR_M ) ) ; for ( cnt = 0 ; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + ICE_PF_RESET_WAIT_COUNT ; cnt ++ ) { reg = rd32 ( hw , PFGEN_CTRL ) ; if ( ! ( reg & PFGEN_CTRL_PFSWR_M ) ) break ; ice_msec_delay ( 1 , true ) ; } if ( cnt == ICE_PF_RESET_WAIT_COUNT ) { ice_debug ( hw , ICE_DBG_INIT , " \n " ) ; return ICE_ERR_RESET_FAILED ; } return ICE_SUCCESS ; }
ice_pf_reset - Reset the PF
 @hw: pointer to the hardware structure
ice_pf_reset - Reset the PF @hw : pointer to the hardware structure
/* If at function entry a global reset was already in progress, i.e.
	 * state is not 'device active' or any of the reset done bits are not
	 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
	 * global reset is done.
	 */ /* poll on global reset currently in progress until done */ /* Reset the PF */ /* Wait for the PFR to complete. The wait time is the global config lock
	 * timeout plus the PFR timeout which will account for a possible reset
	 * that is occurring during a download package operation.
	 */