lib/sw_apps/zynqmp_fsbl/src/xfsbl_ddr_init.c
static u32 XFsbl_DdrcRegsInit(struct DdrcInitData *DdrDataPtr)
{
	XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
	u32 DdrCfg[300U] = XFSBL_DDRC_REG_DEFVAL;
	u32 Status;

	Status = XFsbl_DdrcCalcCommonRegVal(DdrDataPtr, PDimmPtr, DdrCfg);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}

	if (PDimmPtr->MemType == SPD_MEMTYPE_DDR3) {
		Status = XFsbl_DdrcCalcDdr3RegVal(PDimmPtr, DdrCfg);
		if (Status != XFSBL_SUCCESS) {
			Status = XFSBL_FAILURE;
			goto END;
		}
	}

	if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
		Status = XFsbl_DdrcCalcDdr4RegVal(PDimmPtr, DdrCfg);
		if (Status != XFSBL_SUCCESS) {
			Status = XFSBL_FAILURE;
			goto END;
		}
	}

	if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) {
		Status = XFsbl_DdrcCalcLpddr3RegVal(PDimmPtr, DdrCfg);
		if (Status != XFSBL_SUCCESS) {
			Status = XFSBL_FAILURE;
			goto END;
		}
	}

	if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
		Status = XFsbl_DdrcCalcLpddr4RegVal(PDimmPtr, DdrCfg);
		if (Status != XFSBL_SUCCESS) {
			Status = XFSBL_FAILURE;
			goto END;
		}
	}

	DdrCfg[DDR_DFI_TPHY_RDCSLAT] = DdrCfg[DDR_DFI_T_RDDATA_EN] - 2U;

	if (!PDimmPtr->RDimm) {
		DdrCfg[DDR_DFI_TPHY_WRCSLAT] = DdrCfg[DDR_DFI_TPHY_WRLAT] - 2U;
	}

	/* Store the MR values which will be used for PHY Registers */
	PDimmPtr->Mr = DdrCfg[DDR_MR];
	PDimmPtr->Emr = DdrCfg[DDR_EMR];
	PDimmPtr->Emr2 = DdrCfg[DDR_EMR2];
	PDimmPtr->Emr3 = DdrCfg[DDR_EMR3];
	PDimmPtr->Mr4 = DdrCfg[DDR_MR4];
	PDimmPtr->Mr5 = DdrCfg[DDR_MR5];
	PDimmPtr->Mr6 = DdrCfg[DDR_MR6];

	XFsbl_DdrcRegsWrite(PDimmPtr, DdrCfg);


END:
	return Status;
}
/*****************************************************************************/
/**
 * This function calculates and writes DDR controller registers
 *
 * @param	DdrDataPtr is pointer to DDR Initialization Data Structure
 *
 * @return	None
 *
 *****************************************************************************/
This function calculates and writes DDR controller registers
@param       DdrDataPtr is pointer to DDR Initialization Data Structure

@return      None
This function calculates and writes DDR controller registers @param DdrDataPtr is pointer to DDR Initialization Data Structure @return None
static u32 XFsbl_DdrcRegsInit(struct DdrcInitData *DdrDataPtr)
{
	XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
	u32 DdrCfg[300U] = XFSBL_DDRC_REG_DEFVAL;
	u32 Status;
	Status = XFsbl_DdrcCalcCommonRegVal(DdrDataPtr, PDimmPtr, DdrCfg);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}
	if (PDimmPtr->MemType == SPD_MEMTYPE_DDR3) {
		Status = XFsbl_DdrcCalcDdr3RegVal(PDimmPtr, DdrCfg);
		if (Status != XFSBL_SUCCESS) {
			Status = XFSBL_FAILURE;
			goto END;
		}
	}
	if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
		Status = XFsbl_DdrcCalcDdr4RegVal(PDimmPtr, DdrCfg);
		if (Status != XFSBL_SUCCESS) {
			Status = XFSBL_FAILURE;
			goto END;
		}
	}
	if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) {
		Status = XFsbl_DdrcCalcLpddr3RegVal(PDimmPtr, DdrCfg);
		if (Status != XFSBL_SUCCESS) {
			Status = XFSBL_FAILURE;
			goto END;
		}
	}
	if (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) {
		Status = XFsbl_DdrcCalcLpddr4RegVal(PDimmPtr, DdrCfg);
		if (Status != XFSBL_SUCCESS) {
			Status = XFSBL_FAILURE;
			goto END;
		}
	}
	DdrCfg[DDR_DFI_TPHY_RDCSLAT] = DdrCfg[DDR_DFI_T_RDDATA_EN] - 2U;
	if (!PDimmPtr->RDimm) {
		DdrCfg[DDR_DFI_TPHY_WRCSLAT] = DdrCfg[DDR_DFI_TPHY_WRLAT] - 2U;
	}
	PDimmPtr->Mr = DdrCfg[DDR_MR];
	PDimmPtr->Emr = DdrCfg[DDR_EMR];
	PDimmPtr->Emr2 = DdrCfg[DDR_EMR2];
	PDimmPtr->Emr3 = DdrCfg[DDR_EMR3];
	PDimmPtr->Mr4 = DdrCfg[DDR_MR4];
	PDimmPtr->Mr5 = DdrCfg[DDR_MR5];
	PDimmPtr->Mr6 = DdrCfg[DDR_MR6];
	XFsbl_DdrcRegsWrite(PDimmPtr, DdrCfg);
END:
	return Status;
}
static u32 XFsbl_DdrcRegsInit ( struct DdrcInitData * DdrDataPtr ) { XFsbl_DimmParams * PDimmPtr = & DdrDataPtr -> PDimm ; u32 DdrCfg [ 300U ] = XFSBL_DDRC_REG_DEFVAL ; u32 Status ; Status = XFsbl_DdrcCalcCommonRegVal ( DdrDataPtr , PDimmPtr , DdrCfg ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } if ( PDimmPtr -> MemType == SPD_MEMTYPE_DDR3 ) { Status = XFsbl_DdrcCalcDdr3RegVal ( PDimmPtr , DdrCfg ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } } if ( PDimmPtr -> MemType == SPD_MEMTYPE_DDR4 ) { Status = XFsbl_DdrcCalcDdr4RegVal ( PDimmPtr , DdrCfg ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } } if ( PDimmPtr -> MemType == SPD_MEMTYPE_LPDDR3 ) { Status = XFsbl_DdrcCalcLpddr3RegVal ( PDimmPtr , DdrCfg ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } } if ( PDimmPtr -> MemType == SPD_MEMTYPE_LPDDR4 ) { Status = XFsbl_DdrcCalcLpddr4RegVal ( PDimmPtr , DdrCfg ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } } DdrCfg [ DDR_DFI_TPHY_RDCSLAT ] = DdrCfg [ DDR_DFI_T_RDDATA_EN ] - 2U ; if ( ! PDimmPtr -> RDimm ) { DdrCfg [ DDR_DFI_TPHY_WRCSLAT ] = DdrCfg [ DDR_DFI_TPHY_WRLAT ] - 2U ; } PDimmPtr -> Mr = DdrCfg [ DDR_MR ] ; PDimmPtr -> Emr = DdrCfg [ DDR_EMR ] ; PDimmPtr -> Emr2 = DdrCfg [ DDR_EMR2 ] ; PDimmPtr -> Emr3 = DdrCfg [ DDR_EMR3 ] ; PDimmPtr -> Mr4 = DdrCfg [ DDR_MR4 ] ; PDimmPtr -> Mr5 = DdrCfg [ DDR_MR5 ] ; PDimmPtr -> Mr6 = DdrCfg [ DDR_MR6 ] ; XFsbl_DdrcRegsWrite ( PDimmPtr , DdrCfg ) ; END : return Status ; }
This function calculates and writes DDR controller registers
 @param       DdrDataPtr is pointer to DDR Initialization Data Structure
This function calculates and writes DDR controller registers @param DdrDataPtr is pointer to DDR Initialization Data Structure
/* Store the MR values which will be used for PHY Registers */