src/dpdk/drivers/net/i40e/i40e_rxtx.c
int
i40e_rx_queue_init(struct i40e_rx_queue *rxq)
{
	int err = I40E_SUCCESS;
	struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
	struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
	uint16_t pf_q = rxq->reg_idx;
	uint16_t buf_size;
	struct i40e_hmc_obj_rxq rx_ctx;

	err = i40e_rx_queue_config(rxq);
	if (err < 0) {
		PMD_DRV_LOG(ERR, "Failed to config RX queue");
		return err;
	}

	/* Clear the context structure first */
	memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
	rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
	rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;

	rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
	rx_ctx.qlen = rxq->nb_rx_desc;
#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
	rx_ctx.dsize = 1;
#endif
	rx_ctx.dtype = rxq->hs_mode;
	if (rxq->hs_mode)
		rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
	else
		rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
	rx_ctx.rxmax = rxq->max_pkt_len;
	rx_ctx.tphrdesc_ena = 1;
	rx_ctx.tphwdesc_ena = 1;
	rx_ctx.tphdata_ena = 1;
	rx_ctx.tphhead_ena = 1;
	rx_ctx.lrxqthresh = 2;
	rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
	rx_ctx.l2tsel = 1;
	/* showiv indicates if inner VLAN is stripped inside of tunnel
	 * packet. When set it to 1, vlan information is stripped from
	 * the inner header, but the hardware does not put it in the
	 * descriptor. So set it zero by default.
	 */
	rx_ctx.showiv = 0;
	rx_ctx.prefena = 1;

	err = i40e_clear_lan_rx_queue_context(hw, pf_q);
	if (err != I40E_SUCCESS) {
		PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
		return err;
	}
	err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
	if (err != I40E_SUCCESS) {
		PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
		return err;
	}

	rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);

	buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
		RTE_PKTMBUF_HEADROOM);

	/* Check if scattered RX needs to be used. */
	if (rxq->max_pkt_len > buf_size)
		dev_data->scattered_rx = 1;

	/* Init the RX tail regieter. */
	I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);

	return 0;
}
/* Init the RX queue in hardware */
Init the RX queue in hardware
Init the RX queue in hardware
int
i40e_rx_queue_init(struct i40e_rx_queue *rxq)
{
	int err = I40E_SUCCESS;
	struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
	struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
	uint16_t pf_q = rxq->reg_idx;
	uint16_t buf_size;
	struct i40e_hmc_obj_rxq rx_ctx;
	err = i40e_rx_queue_config(rxq);
	if (err < 0) {
		PMD_DRV_LOG(ERR, "Failed to config RX queue");
		return err;
	}
	memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
	rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
	rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
	rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
	rx_ctx.qlen = rxq->nb_rx_desc;
#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
	rx_ctx.dsize = 1;
#endif
	rx_ctx.dtype = rxq->hs_mode;
	if (rxq->hs_mode)
		rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
	else
		rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
	rx_ctx.rxmax = rxq->max_pkt_len;
	rx_ctx.tphrdesc_ena = 1;
	rx_ctx.tphwdesc_ena = 1;
	rx_ctx.tphdata_ena = 1;
	rx_ctx.tphhead_ena = 1;
	rx_ctx.lrxqthresh = 2;
	rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
	rx_ctx.l2tsel = 1;
	rx_ctx.showiv = 0;
	rx_ctx.prefena = 1;
	err = i40e_clear_lan_rx_queue_context(hw, pf_q);
	if (err != I40E_SUCCESS) {
		PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
		return err;
	}
	err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
	if (err != I40E_SUCCESS) {
		PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
		return err;
	}
	rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
	buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
		RTE_PKTMBUF_HEADROOM);
	if (rxq->max_pkt_len > buf_size)
		dev_data->scattered_rx = 1;
	I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
	return 0;
}
int i40e_rx_queue_init ( struct i40e_rx_queue * rxq ) { int err = I40E_SUCCESS ; struct i40e_hw * hw = I40E_VSI_TO_HW ( rxq -> vsi ) ; struct rte_eth_dev_data * dev_data = I40E_VSI_TO_DEV_DATA ( rxq -> vsi ) ; uint16_t pf_q = rxq -> reg_idx ; uint16_t buf_size ; struct i40e_hmc_obj_rxq rx_ctx ; err = i40e_rx_queue_config ( rxq ) ; if ( err < 0 ) { PMD_DRV_LOG ( ERR , " " ) ; return err ; } memset ( & rx_ctx , 0 , sizeof ( struct i40e_hmc_obj_rxq ) ) ; rx_ctx . dbuff = rxq -> rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT ; rx_ctx . hbuff = rxq -> rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT ; rx_ctx . base = rxq -> rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT ; rx_ctx . qlen = rxq -> nb_rx_desc ; #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC rx_ctx . dsize = 1 ; #endif rx_ctx . dtype = rxq -> hs_mode ; if ( rxq -> hs_mode ) rx_ctx . hsplit_0 = I40E_HEADER_SPLIT_ALL ; else rx_ctx . hsplit_0 = I40E_HEADER_SPLIT_NONE ; rx_ctx . rxmax = rxq -> max_pkt_len ; rx_ctx . tphrdesc_ena = 1 ; rx_ctx . tphwdesc_ena = 1 ; rx_ctx . tphdata_ena = 1 ; rx_ctx . tphhead_ena = 1 ; rx_ctx . lrxqthresh = 2 ; rx_ctx . crcstrip = ( rxq -> crc_len == 0 ) ? 1 : 0 ; rx_ctx . l2tsel = 1 ; rx_ctx . showiv = 0 ; rx_ctx . prefena = 1 ; err = i40e_clear_lan_rx_queue_context ( hw , pf_q ) ; if ( err != I40E_SUCCESS ) { PMD_DRV_LOG ( ERR , " " ) ; return err ; } err = i40e_set_lan_rx_queue_context ( hw , pf_q , & rx_ctx ) ; if ( err != I40E_SUCCESS ) { PMD_DRV_LOG ( ERR , " " ) ; return err ; } rxq -> qrx_tail = hw -> hw_addr + I40E_QRX_TAIL ( pf_q ) ; buf_size = ( uint16_t ) ( rte_pktmbuf_data_room_size ( rxq -> mp ) - RTE_PKTMBUF_HEADROOM ) ; if ( rxq -> max_pkt_len > buf_size ) dev_data -> scattered_rx = 1 ; I40E_PCI_REG_WRITE ( rxq -> qrx_tail , rxq -> nb_rx_desc - 1 ) ; return 0 ; }
Init the RX queue in hardware
Init the RX queue in hardware
/* Clear the context structure first */ /* showiv indicates if inner VLAN is stripped inside of tunnel
	 * packet. When set it to 1, vlan information is stripped from
	 * the inner header, but the hardware does not put it in the
	 * descriptor. So set it zero by default.
	 */ /* Check if scattered RX needs to be used. */ /* Init the RX tail regieter. */