os_dep/linux/pci_intf.c
static void rtw_pci_update_default_setting(_adapter *padapter)
{
	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(pdvobjpriv);
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);

	/* reset pPSC->reg_rfps_level & priv->b_support_aspm */
	pwrpriv->reg_rfps_level = 0;

	/* Update PCI ASPM setting */
	/* pwrpriv->const_amdpci_aspm = pdvobjpriv->const_amdpci_aspm; */
	switch (pdvobjpriv->const_pci_aspm) {
	case 0:		/* No ASPM */
		break;

	case 1:		/* ASPM dynamically enabled/disable. */
		pwrpriv->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
		break;

	case 2:		/* ASPM with Clock Req dynamically enabled/disable. */
		pwrpriv->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
		break;

	case 3:		/* Always enable ASPM and Clock Req from initialization to halt. */
		pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
		pwrpriv->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
		break;

	case 4:		/* Always enable ASPM without Clock Req from initialization to halt. */
		pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
		pwrpriv->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
		break;

	case 5: /* Linux do not support ASPM OSC, added by Roger, 2013.03.27.	 */
		break;
	}

	pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;

	/* Update Radio OFF setting */
	switch (pdvobjpriv->const_hwsw_rfoff_d3) {
	case 1:
		if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
			pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
		break;

	case 2:
		if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
			pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
		pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
		break;

	case 3:
		pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
		break;
	}

	/* Update Rx 2R setting */
	/* pPSC->reg_rfps_level |= ((pDevice->RegLPS2RDisable) ? RT_RF_LPS_DISALBE_2R : 0); */

	/*  */
	/* Set HW definition to determine if it supports ASPM. */
	/*  */
	switch (pdvobjpriv->const_support_pciaspm) {
	case 1: {	/* Support ASPM. */
		u8	b_support_backdoor = _TRUE;
		u8	b_support_l1_on_amd = _FALSE;

		rtw_hal_get_def_var(padapter, HAL_DEF_PCI_AMD_L1_SUPPORT, &b_support_l1_on_amd);

		if (pHalData->CustomerID == RT_CID_TOSHIBA &&
		    pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD &&
		    !pcipriv->amd_l1_patch && !b_support_l1_on_amd) {
			RTW_INFO("%s(): Disable L1 Backdoor!!\n", __func__);
			b_support_backdoor = _FALSE;
		}
		rtw_hal_set_def_var(padapter, HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, &b_support_backdoor);
	}
	break;

	default:
		/* Do nothing. Set when finding the chipset. */
		break;
	}
}
/*
 * Update PCI dependent default settings.
 *
 */
Update PCI dependent default settings.
Update PCI dependent default settings .
static void rtw_pci_update_default_setting(_adapter *padapter)
{
	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(pdvobjpriv);
	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
	pwrpriv->reg_rfps_level = 0;
	switch (pdvobjpriv->const_pci_aspm) {
	case 0:		
		break;
	case 1:		
		pwrpriv->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
		break;
	case 2:		
		pwrpriv->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
		break;
	case 3:		
		pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
		pwrpriv->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
		break;
	case 4:		
		pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
		pwrpriv->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
		break;
	case 5: 
		break;
	}
	pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
	switch (pdvobjpriv->const_hwsw_rfoff_d3) {
	case 1:
		if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
			pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
		break;
	case 2:
		if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
			pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
		pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
		break;
	case 3:
		pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
		break;
	}
	switch (pdvobjpriv->const_support_pciaspm) {
	case 1: {	
		u8	b_support_backdoor = _TRUE;
		u8	b_support_l1_on_amd = _FALSE;
		rtw_hal_get_def_var(padapter, HAL_DEF_PCI_AMD_L1_SUPPORT, &b_support_l1_on_amd);
		if (pHalData->CustomerID == RT_CID_TOSHIBA &&
		    pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD &&
		    !pcipriv->amd_l1_patch && !b_support_l1_on_amd) {
			RTW_INFO("%s(): Disable L1 Backdoor!!\n", __func__);
			b_support_backdoor = _FALSE;
		}
		rtw_hal_set_def_var(padapter, HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, &b_support_backdoor);
	}
	break;
	default:
		break;
	}
}
static void rtw_pci_update_default_setting ( _adapter * padapter ) { struct dvobj_priv * pdvobjpriv = adapter_to_dvobj ( padapter ) ; struct pci_priv * pcipriv = & ( pdvobjpriv -> pcipriv ) ; struct pwrctrl_priv * pwrpriv = dvobj_to_pwrctl ( pdvobjpriv ) ; HAL_DATA_TYPE * pHalData = GET_HAL_DATA ( padapter ) ; pwrpriv -> reg_rfps_level = 0 ; switch ( pdvobjpriv -> const_pci_aspm ) { case 0 : break ; case 1 : pwrpriv -> reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM ; break ; case 2 : pwrpriv -> reg_rfps_level |= ( RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ ) ; break ; case 3 : pwrpriv -> reg_rfps_level &= ~ ( RT_RF_LPS_LEVEL_ASPM ) ; pwrpriv -> reg_rfps_level |= ( RT_RF_PS_LEVEL_ALWAYS_ASPM | RT_RF_OFF_LEVL_CLK_REQ ) ; break ; case 4 : pwrpriv -> reg_rfps_level &= ~ ( RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ ) ; pwrpriv -> reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM ; break ; case 5 : break ; } pwrpriv -> reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC ; switch ( pdvobjpriv -> const_hwsw_rfoff_d3 ) { case 1 : if ( pwrpriv -> reg_rfps_level & RT_RF_LPS_LEVEL_ASPM ) pwrpriv -> reg_rfps_level |= RT_RF_OFF_LEVL_ASPM ; break ; case 2 : if ( pwrpriv -> reg_rfps_level & RT_RF_LPS_LEVEL_ASPM ) pwrpriv -> reg_rfps_level |= RT_RF_OFF_LEVL_ASPM ; pwrpriv -> reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC ; break ; case 3 : pwrpriv -> reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3 ; break ; } switch ( pdvobjpriv -> const_support_pciaspm ) { case 1 : { u8 b_support_backdoor = _TRUE ; u8 b_support_l1_on_amd = _FALSE ; rtw_hal_get_def_var ( padapter , HAL_DEF_PCI_AMD_L1_SUPPORT , & b_support_l1_on_amd ) ; if ( pHalData -> CustomerID == RT_CID_TOSHIBA && pcipriv -> pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD && ! pcipriv -> amd_l1_patch && ! b_support_l1_on_amd ) { RTW_INFO ( " \n " , __func__ ) ; b_support_backdoor = _FALSE ; } rtw_hal_set_def_var ( padapter , HAL_DEF_PCI_SUUPORT_L1_BACKDOOR , & b_support_backdoor ) ; } break ; default : break ; } }
Update PCI dependent default settings.
Update PCI dependent default settings .
/* reset pPSC->reg_rfps_level & priv->b_support_aspm */ /* Update PCI ASPM setting */ /* pwrpriv->const_amdpci_aspm = pdvobjpriv->const_amdpci_aspm; */ /* No ASPM */ /* ASPM dynamically enabled/disable. */ /* ASPM with Clock Req dynamically enabled/disable. */ /* Always enable ASPM and Clock Req from initialization to halt. */ /* Always enable ASPM without Clock Req from initialization to halt. */ /* Linux do not support ASPM OSC, added by Roger, 2013.03.27.	 */ /* Update Radio OFF setting */ /* Update Rx 2R setting */ /* pPSC->reg_rfps_level |= ((pDevice->RegLPS2RDisable) ? RT_RF_LPS_DISALBE_2R : 0); */ /*  */ /* Set HW definition to determine if it supports ASPM. */ /*  */ /* Support ASPM. */ /* Do nothing. Set when finding the chipset. */