example_projects/EVE_Test_XMEGA128A1_GEN4-FT813-50CTP/Display_Test1/Clockconfig.c
void clk_init(void)
{	
	// This function also enables the 2 MHz internal RC oscillator and its DFLL, even it isn't used.
	// Thats because of a BUG in the H revision of the XMEGA:
	/*	20. Both DFLLs and both oscillators have to be enabled for one to work
	 *	In order to use the automatic runtime calibration for the 2 MHz or the 32 MHz internal oscillators, the DFLL for both
	 *	oscillators and both oscillators have to be enabled for one to work.
	 *	Problem fix/Workaround
	 *	Enable both DFLLs and both oscillators when using automatic runtime calibration for either of the internal
	 *	oscillators
	 */
	
	OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm | OSC_RC2MEN_bm;	/* Enable all internal oscillators */
	while(!(OSC.STATUS & OSC_RC32KRDY_bm));							/* Wait for 32Khz oscillator to stabilize */
	while(!(OSC.STATUS & OSC_RC32MRDY_bm));							/* Wait for 32MHz oscillator to stabilize */
	while(!(OSC.STATUS & OSC_RC2MRDY_bm));							/* Wait for 2MHz oscillator to stabilize */
	DFLLRC2M.CTRL = DFLL_ENABLE_bm ;								/* Enable DFLL also for 2 MHz Oscillator */
	DFLLRC32M.CTRL = DFLL_ENABLE_bm ;								/* Enable DFLL  */
	CCP = CCP_IOREG_gc;												/* Disable register security for clock update */
	CLK.CTRL = CLK_SCLKSEL_RC32M_gc;								/* Switch to 32MHz clock */
}
// This function set the system clock to 32 MHz with automatic calibration.
This function set the system clock to 32 MHz with automatic calibration.
This function set the system clock to 32 MHz with automatic calibration .
void clk_init(void)
{	
	OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm | OSC_RC2MEN_bm;	
	while(!(OSC.STATUS & OSC_RC32KRDY_bm));							
	while(!(OSC.STATUS & OSC_RC32MRDY_bm));							
	while(!(OSC.STATUS & OSC_RC2MRDY_bm));							
	DFLLRC2M.CTRL = DFLL_ENABLE_bm ;								
	DFLLRC32M.CTRL = DFLL_ENABLE_bm ;								
	CCP = CCP_IOREG_gc;												
	CLK.CTRL = CLK_SCLKSEL_RC32M_gc;								
}
void clk_init ( void ) { OSC . CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm | OSC_RC2MEN_bm ; while ( ! ( OSC . STATUS & OSC_RC32KRDY_bm ) ) ; while ( ! ( OSC . STATUS & OSC_RC32MRDY_bm ) ) ; while ( ! ( OSC . STATUS & OSC_RC2MRDY_bm ) ) ; DFLLRC2M . CTRL = DFLL_ENABLE_bm ; DFLLRC32M . CTRL = DFLL_ENABLE_bm ; CCP = CCP_IOREG_gc ; CLK . CTRL = CLK_SCLKSEL_RC32M_gc ; }
This function set the system clock to 32 MHz with automatic calibration.
This function set the system clock to 32 MHz with automatic calibration .
// This function also enables the 2 MHz internal RC oscillator and its DFLL, even it isn't used. // Thats because of a BUG in the H revision of the XMEGA: /*	20. Both DFLLs and both oscillators have to be enabled for one to work
	 *	In order to use the automatic runtime calibration for the 2 MHz or the 32 MHz internal oscillators, the DFLL for both
	 *	oscillators and both oscillators have to be enabled for one to work.
	 *	Problem fix/Workaround
	 *	Enable both DFLLs and both oscillators when using automatic runtime calibration for either of the internal
	 *	oscillators
	 */ /* Enable all internal oscillators */ /* Wait for 32Khz oscillator to stabilize */ /* Wait for 32MHz oscillator to stabilize */ /* Wait for 2MHz oscillator to stabilize */ /* Enable DFLL also for 2 MHz Oscillator */ /* Enable DFLL  */ /* Disable register security for clock update */ /* Switch to 32MHz clock */