lib/sw_apps/zynqmp_pmufw/src/pm_hooks.c
void PmHookPowerOffSuspendDdrReady(void)
{
	u32 reg;

	/* Configure MIO 26 to be controlled by the PMU */
	XPfw_RMW32(IOU_SCLR_MIO_PIN_26, 0x000000FEU ,0x00000008U);

	/* Configure MIO26 tri-state enables */
	XPfw_RMW32(IOU_SCLR_MIO_MST_TRI0, 0x04000000U ,0x00000000U);

	/* Get MIO26 state */
	reg = XPfw_Read32(PMU_IOMODULE_GPI1);
	reg &= PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK;

	if (reg > 0U) {
		/* Drive MIO37 low to signal that PMU is ready to restore DDR */
		reg = XPfw_Read32(PMU_LOCAL_GPO1_READ);
		reg &= ~PMU_IOMODULE_GPO1_MIO_5_MASK;
		XPfw_Write32(PMU_IOMODULE_GPO1, reg);

		/* Configure MIO 37 to be controlled by the PMU */
		XPfw_RMW32(IOU_SCLR_MIO_PIN_37, 0x000000FEU ,0x00000008U);

		/* Configure MIO37 tri-state enables */
		XPfw_RMW32(IOU_SCLR_MIO_MST_TRI1, 0x00000020U ,0x00000000U);

		/* Wait for MIO26 to go down before continuing with resume */
		do {
			reg = XPfw_Read32(PMU_IOMODULE_GPI1);
			reg &= PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK;
		} while (reg != 0U);
	}
}
/**
 * PmHookPowerOffSuspendDdrReady() - User hook for signaling that PMUFW is ready
 * 				     to take DDR out of self refresh
 */
User hook for signaling that PMUFW is ready
to take DDR out of self refresh
User hook for signaling that PMUFW is ready to take DDR out of self refresh
void PmHookPowerOffSuspendDdrReady(void)
{
	u32 reg;
	XPfw_RMW32(IOU_SCLR_MIO_PIN_26, 0x000000FEU ,0x00000008U);
	XPfw_RMW32(IOU_SCLR_MIO_MST_TRI0, 0x04000000U ,0x00000000U);
	reg = XPfw_Read32(PMU_IOMODULE_GPI1);
	reg &= PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK;
	if (reg > 0U) {
		reg = XPfw_Read32(PMU_LOCAL_GPO1_READ);
		reg &= ~PMU_IOMODULE_GPO1_MIO_5_MASK;
		XPfw_Write32(PMU_IOMODULE_GPO1, reg);
		XPfw_RMW32(IOU_SCLR_MIO_PIN_37, 0x000000FEU ,0x00000008U);
		XPfw_RMW32(IOU_SCLR_MIO_MST_TRI1, 0x00000020U ,0x00000000U);
		do {
			reg = XPfw_Read32(PMU_IOMODULE_GPI1);
			reg &= PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK;
		} while (reg != 0U);
	}
}
void PmHookPowerOffSuspendDdrReady ( void ) { u32 reg ; XPfw_RMW32 ( IOU_SCLR_MIO_PIN_26 , 0x000000FEU , 0x00000008U ) ; XPfw_RMW32 ( IOU_SCLR_MIO_MST_TRI0 , 0x04000000U , 0x00000000U ) ; reg = XPfw_Read32 ( PMU_IOMODULE_GPI1 ) ; reg &= PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK ; if ( reg > 0U ) { reg = XPfw_Read32 ( PMU_LOCAL_GPO1_READ ) ; reg &= ~ PMU_IOMODULE_GPO1_MIO_5_MASK ; XPfw_Write32 ( PMU_IOMODULE_GPO1 , reg ) ; XPfw_RMW32 ( IOU_SCLR_MIO_PIN_37 , 0x000000FEU , 0x00000008U ) ; XPfw_RMW32 ( IOU_SCLR_MIO_MST_TRI1 , 0x00000020U , 0x00000000U ) ; do { reg = XPfw_Read32 ( PMU_IOMODULE_GPI1 ) ; reg &= PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK ; } while ( reg != 0U ) ; } }
PmHookPowerOffSuspendDdrReady() - User hook for signaling that PMUFW is ready
                                   to take DDR out of self refresh
PmHookPowerOffSuspendDdrReady () - User hook for signaling that PMUFW is ready to take DDR out of self refresh
/* Configure MIO 26 to be controlled by the PMU */ /* Configure MIO26 tri-state enables */ /* Get MIO26 state */ /* Drive MIO37 low to signal that PMU is ready to restore DDR */ /* Configure MIO 37 to be controlled by the PMU */ /* Configure MIO37 tri-state enables */ /* Wait for MIO26 to go down before continuing with resume */