src/system_mt7687.c
void cmnPLL1ON_PLL2ON(uint8_t fg960M)
{
    volatile uint32_t reg;
    volatile uint32_t *pTopCfgCM4PWRCtl = (volatile uint32_t *)TOP_CFG_CM4_PWR_CTL_CR;

    reg = cmnReadRegister32(pTopCfgCM4PWRCtl);
    reg = (reg >>  CM4_MPLL_EN_SHIFT) & CM4_MPLL_EN_MASK;

    if (reg != CM4_MPLL_EN_PLL1_ON_PLL2_ON) {
        reg = cmnReadRegister32(pTopCfgCM4PWRCtl);
        reg = reg & ~(CM4_MCU_960_EN_MASK << CM4_MCU_960_EN_SHIFT);
        reg = reg & ~(CM4_NEED_RESTORE_MASK <<  CM4_NEED_RESTORE_SHIFT);    // avoid W1C
        reg = reg | (CM4_MCU_960_EN_DISABLE << CM4_MCU_960_EN_SHIFT);
        cmnWriteRegister32(pTopCfgCM4PWRCtl, reg);

        reg = cmnReadRegister32(pTopCfgCM4PWRCtl);
        reg = reg & ~(CM4_MPLL_EN_MASK << CM4_MPLL_EN_SHIFT);
        reg = reg & ~(CM4_NEED_RESTORE_MASK <<  CM4_NEED_RESTORE_SHIFT);    // avoid W1C
        reg = reg | (CM4_MPLL_EN_PLL1_ON_PLL2_ON << CM4_MPLL_EN_SHIFT);
        cmnWriteRegister32(pTopCfgCM4PWRCtl, reg);

        do {
            reg = cmnReadRegister32(pTopCfgCM4PWRCtl);
            reg = reg & (CM4_WF_PLL_RDY_MASK << CM4_WF_PLL_RDY_SHIFT);
        } while (!reg);

        reg = cmnReadRegister32(pTopCfgCM4PWRCtl);
        reg = reg & ~(CM4_MCU_960_EN_MASK << CM4_MCU_960_EN_SHIFT);
        reg = reg & ~(CM4_NEED_RESTORE_MASK <<  CM4_NEED_RESTORE_SHIFT);    // avoid W1C
    }

    if (fg960M) {
        reg = reg | (CM4_MCU_960_EN_ENABLE << CM4_MCU_960_EN_SHIFT);
    } else {
        reg = reg | (CM4_MCU_960_EN_DISABLE << CM4_MCU_960_EN_SHIFT);
    }
    cmnWriteRegister32(pTopCfgCM4PWRCtl, reg);
    return;
}
/**
  * @brief  This function is to enable both PPL1 and PLL2.
  * @param  MCU 960M enable selector
  * @retval None
  */
@brief  This function is to enable both PPL1 and PLL2.
@param  MCU 960M enable selector
@retval None
@brief This function is to enable both PPL1 and PLL2 . @param MCU 960M enable selector @retval None
void cmnPLL1ON_PLL2ON(uint8_t fg960M)
{
    volatile uint32_t reg;
    volatile uint32_t *pTopCfgCM4PWRCtl = (volatile uint32_t *)TOP_CFG_CM4_PWR_CTL_CR;
    reg = cmnReadRegister32(pTopCfgCM4PWRCtl);
    reg = (reg >>  CM4_MPLL_EN_SHIFT) & CM4_MPLL_EN_MASK;
    if (reg != CM4_MPLL_EN_PLL1_ON_PLL2_ON) {
        reg = cmnReadRegister32(pTopCfgCM4PWRCtl);
        reg = reg & ~(CM4_MCU_960_EN_MASK << CM4_MCU_960_EN_SHIFT);
        reg = reg & ~(CM4_NEED_RESTORE_MASK <<  CM4_NEED_RESTORE_SHIFT);    
        reg = reg | (CM4_MCU_960_EN_DISABLE << CM4_MCU_960_EN_SHIFT);
        cmnWriteRegister32(pTopCfgCM4PWRCtl, reg);
        reg = cmnReadRegister32(pTopCfgCM4PWRCtl);
        reg = reg & ~(CM4_MPLL_EN_MASK << CM4_MPLL_EN_SHIFT);
        reg = reg & ~(CM4_NEED_RESTORE_MASK <<  CM4_NEED_RESTORE_SHIFT);    
        reg = reg | (CM4_MPLL_EN_PLL1_ON_PLL2_ON << CM4_MPLL_EN_SHIFT);
        cmnWriteRegister32(pTopCfgCM4PWRCtl, reg);
        do {
            reg = cmnReadRegister32(pTopCfgCM4PWRCtl);
            reg = reg & (CM4_WF_PLL_RDY_MASK << CM4_WF_PLL_RDY_SHIFT);
        } while (!reg);
        reg = cmnReadRegister32(pTopCfgCM4PWRCtl);
        reg = reg & ~(CM4_MCU_960_EN_MASK << CM4_MCU_960_EN_SHIFT);
        reg = reg & ~(CM4_NEED_RESTORE_MASK <<  CM4_NEED_RESTORE_SHIFT);    
    }
    if (fg960M) {
        reg = reg | (CM4_MCU_960_EN_ENABLE << CM4_MCU_960_EN_SHIFT);
    } else {
        reg = reg | (CM4_MCU_960_EN_DISABLE << CM4_MCU_960_EN_SHIFT);
    }
    cmnWriteRegister32(pTopCfgCM4PWRCtl, reg);
    return;
}
void cmnPLL1ON_PLL2ON ( uint8_t fg960M ) { volatile uint32_t reg ; volatile uint32_t * pTopCfgCM4PWRCtl = ( volatile uint32_t * ) TOP_CFG_CM4_PWR_CTL_CR ; reg = cmnReadRegister32 ( pTopCfgCM4PWRCtl ) ; reg = ( reg >> CM4_MPLL_EN_SHIFT ) & CM4_MPLL_EN_MASK ; if ( reg != CM4_MPLL_EN_PLL1_ON_PLL2_ON ) { reg = cmnReadRegister32 ( pTopCfgCM4PWRCtl ) ; reg = reg & ~ ( CM4_MCU_960_EN_MASK << CM4_MCU_960_EN_SHIFT ) ; reg = reg & ~ ( CM4_NEED_RESTORE_MASK << CM4_NEED_RESTORE_SHIFT ) ; reg = reg | ( CM4_MCU_960_EN_DISABLE << CM4_MCU_960_EN_SHIFT ) ; cmnWriteRegister32 ( pTopCfgCM4PWRCtl , reg ) ; reg = cmnReadRegister32 ( pTopCfgCM4PWRCtl ) ; reg = reg & ~ ( CM4_MPLL_EN_MASK << CM4_MPLL_EN_SHIFT ) ; reg = reg & ~ ( CM4_NEED_RESTORE_MASK << CM4_NEED_RESTORE_SHIFT ) ; reg = reg | ( CM4_MPLL_EN_PLL1_ON_PLL2_ON << CM4_MPLL_EN_SHIFT ) ; cmnWriteRegister32 ( pTopCfgCM4PWRCtl , reg ) ; do { reg = cmnReadRegister32 ( pTopCfgCM4PWRCtl ) ; reg = reg & ( CM4_WF_PLL_RDY_MASK << CM4_WF_PLL_RDY_SHIFT ) ; } while ( ! reg ) ; reg = cmnReadRegister32 ( pTopCfgCM4PWRCtl ) ; reg = reg & ~ ( CM4_MCU_960_EN_MASK << CM4_MCU_960_EN_SHIFT ) ; reg = reg & ~ ( CM4_NEED_RESTORE_MASK << CM4_NEED_RESTORE_SHIFT ) ; } if ( fg960M ) { reg = reg | ( CM4_MCU_960_EN_ENABLE << CM4_MCU_960_EN_SHIFT ) ; } else { reg = reg | ( CM4_MCU_960_EN_DISABLE << CM4_MCU_960_EN_SHIFT ) ; } cmnWriteRegister32 ( pTopCfgCM4PWRCtl , reg ) ; return ; }
@brief  This function is to enable both PPL1 and PLL2.
@brief This function is to enable both PPL1 and PLL2 .
// avoid W1C // avoid W1C // avoid W1C