XilinxProcessorIPLib/drivers/aiengine/src/tile/xaietile_strm.c
void XAieTile_StrmConfigSlvSlot(XAieGbl_Tile *TileInstPtr, u8 Slave, u8 Slot,
							u8 Enable, u32 RegVal)
{
	u64 RegAddr;
        XAieGbl_RegStrmSlot *RegPtr;

	XAie_AssertNonvoid(TileInstPtr != XAIE_NULL);

       	if(TileInstPtr->TileType == XAIEGBL_TILE_TYPE_AIETILE) {
                RegPtr = &(TileStrmSlot[(XAIETILE_STRSW_SPORT_NUMSLOTS * Slave) +
                                                                 Slot]);
        } else {
                RegPtr = &(ShimStrmSlot[(XAIETILE_STRSW_SPORT_NUMSLOTS * Slave) +
                                                                 Slot]);
        }

	/* Get the address of Slave slot config reg */
	RegAddr = TileInstPtr->TileAddr + RegPtr->RegOff;

	if(Enable == XAIE_ENABLE) {
		RegVal|=(XAie_SetField(Enable, RegPtr->En.Lsb, RegPtr->En.Mask));
	} else {
		RegVal = 0U;
	}

	XAieGbl_Write32(RegAddr, RegVal);
}
/*****************************************************************************/
/**
*
* This API is used to configure the selected slot of the slave port in the
* stream switch of the corresponding tile.
*
* @param	TileInstPtr - Pointer to the Tile instance.
* @param	Slave - Slave port ID value.
* @param	Slot - Slave slot ID value, ranging from 0-3.
* @param	Enable - Enable/Disable the slave slot (1-Enable,0-Disable).

* @param	RegVal - Config value to be used for the slot. Applicable only
*		when Enable==1, else set to 0.
*		Bit encoding : 31:21-Rsvd, 28:24-Slot ID, 23:21-Rsvd,
*			20:16-ID mask, 15:6-Rsvd, 5:4-Master select/msel,
*			3-Rsvd, 2:0-Arbiter to use.
*		Use the macro "xaietile_strm.c::XAIETILE_STRSW_SLVSLOT_CFG()" to
*		frame the 32-bit RegVal.
*
* @return	None.
*
* @note		None.
*
*******************************************************************************/
This API is used to configure the selected slot of the slave port in the
stream switch of the corresponding tile.
This API is used to configure the selected slot of the slave port in the stream switch of the corresponding tile .
void XAieTile_StrmConfigSlvSlot(XAieGbl_Tile *TileInstPtr, u8 Slave, u8 Slot,
							u8 Enable, u32 RegVal)
{
	u64 RegAddr;
        XAieGbl_RegStrmSlot *RegPtr;
	XAie_AssertNonvoid(TileInstPtr != XAIE_NULL);
       	if(TileInstPtr->TileType == XAIEGBL_TILE_TYPE_AIETILE) {
                RegPtr = &(TileStrmSlot[(XAIETILE_STRSW_SPORT_NUMSLOTS * Slave) +
                                                                 Slot]);
        } else {
                RegPtr = &(ShimStrmSlot[(XAIETILE_STRSW_SPORT_NUMSLOTS * Slave) +
                                                                 Slot]);
        }
	RegAddr = TileInstPtr->TileAddr + RegPtr->RegOff;
	if(Enable == XAIE_ENABLE) {
		RegVal|=(XAie_SetField(Enable, RegPtr->En.Lsb, RegPtr->En.Mask));
	} else {
		RegVal = 0U;
	}
	XAieGbl_Write32(RegAddr, RegVal);
}
void XAieTile_StrmConfigSlvSlot ( XAieGbl_Tile * TileInstPtr , u8 Slave , u8 Slot , u8 Enable , u32 RegVal ) { u64 RegAddr ; XAieGbl_RegStrmSlot * RegPtr ; XAie_AssertNonvoid ( TileInstPtr != XAIE_NULL ) ; if ( TileInstPtr -> TileType == XAIEGBL_TILE_TYPE_AIETILE ) { RegPtr = & ( TileStrmSlot [ ( XAIETILE_STRSW_SPORT_NUMSLOTS * Slave ) + Slot ] ) ; } else { RegPtr = & ( ShimStrmSlot [ ( XAIETILE_STRSW_SPORT_NUMSLOTS * Slave ) + Slot ] ) ; } RegAddr = TileInstPtr -> TileAddr + RegPtr -> RegOff ; if ( Enable == XAIE_ENABLE ) { RegVal |= ( XAie_SetField ( Enable , RegPtr -> En . Lsb , RegPtr -> En . Mask ) ) ; } else { RegVal = 0U ; } XAieGbl_Write32 ( RegAddr , RegVal ) ; }
This API is used to configure the selected slot of the slave port in the
stream switch of the corresponding tile.
This API is used to configure the selected slot of the slave port in the stream switch of the corresponding tile .
/* Get the address of Slave slot config reg */