src/dpdk/drivers/net/qede/qede_debug.c
static enum dbg_status qed_dbg_dev_init(struct ecore_hwfn *p_hwfn)
{
	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	u8 num_pfs = 0, max_pfs_per_port = 0;

	if (dev_data->initialized)
		return DBG_STATUS_OK;

	/* Set chip */
	if (ECORE_IS_K2(p_hwfn->p_dev)) {
		dev_data->chip_id = CHIP_K2;
		dev_data->mode_enable[MODE_K2] = 1;
		dev_data->num_vfs = MAX_NUM_VFS_K2;
		num_pfs = MAX_NUM_PFS_K2;
		max_pfs_per_port = MAX_NUM_PFS_K2 / 2;
	} else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
		dev_data->chip_id = CHIP_BB;
		dev_data->mode_enable[MODE_BB] = 1;
		dev_data->num_vfs = MAX_NUM_VFS_BB;
		num_pfs = MAX_NUM_PFS_BB;
		max_pfs_per_port = MAX_NUM_PFS_BB;
	} else {
		return DBG_STATUS_UNKNOWN_CHIP;
	}

	/* Set HW type */
	dev_data->hw_type = HW_TYPE_ASIC;
	dev_data->mode_enable[MODE_ASIC] = 1;

	/* Set port mode */
	switch (p_hwfn->p_dev->num_ports_in_engine) {
	case 1:
		dev_data->mode_enable[MODE_PORTS_PER_ENG_1] = 1;
		break;
	case 2:
		dev_data->mode_enable[MODE_PORTS_PER_ENG_2] = 1;
		break;
	case 4:
		dev_data->mode_enable[MODE_PORTS_PER_ENG_4] = 1;
		break;
	}

	/* Set 100G mode */
	if (ECORE_IS_CMT(p_hwfn->p_dev))
		dev_data->mode_enable[MODE_100G] = 1;

	/* Set number of ports */
	if (dev_data->mode_enable[MODE_PORTS_PER_ENG_1] ||
	    dev_data->mode_enable[MODE_100G])
		dev_data->num_ports = 1;
	else if (dev_data->mode_enable[MODE_PORTS_PER_ENG_2])
		dev_data->num_ports = 2;
	else if (dev_data->mode_enable[MODE_PORTS_PER_ENG_4])
		dev_data->num_ports = 4;

	/* Set number of PFs per port */
	dev_data->num_pfs_per_port = OSAL_MIN_T(u32,
						num_pfs / dev_data->num_ports,
						max_pfs_per_port);

	/* Initializes the GRC parameters */
	qed_dbg_grc_init_params(p_hwfn);

	dev_data->use_dmae = true;
	dev_data->initialized = 1;

	return DBG_STATUS_OK;
}
/* Initializes debug data for the specified device */
Initializes debug data for the specified device
Initializes debug data for the specified device
static enum dbg_status qed_dbg_dev_init(struct ecore_hwfn *p_hwfn)
{
	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	u8 num_pfs = 0, max_pfs_per_port = 0;
	if (dev_data->initialized)
		return DBG_STATUS_OK;
	if (ECORE_IS_K2(p_hwfn->p_dev)) {
		dev_data->chip_id = CHIP_K2;
		dev_data->mode_enable[MODE_K2] = 1;
		dev_data->num_vfs = MAX_NUM_VFS_K2;
		num_pfs = MAX_NUM_PFS_K2;
		max_pfs_per_port = MAX_NUM_PFS_K2 / 2;
	} else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
		dev_data->chip_id = CHIP_BB;
		dev_data->mode_enable[MODE_BB] = 1;
		dev_data->num_vfs = MAX_NUM_VFS_BB;
		num_pfs = MAX_NUM_PFS_BB;
		max_pfs_per_port = MAX_NUM_PFS_BB;
	} else {
		return DBG_STATUS_UNKNOWN_CHIP;
	}
	dev_data->hw_type = HW_TYPE_ASIC;
	dev_data->mode_enable[MODE_ASIC] = 1;
	switch (p_hwfn->p_dev->num_ports_in_engine) {
	case 1:
		dev_data->mode_enable[MODE_PORTS_PER_ENG_1] = 1;
		break;
	case 2:
		dev_data->mode_enable[MODE_PORTS_PER_ENG_2] = 1;
		break;
	case 4:
		dev_data->mode_enable[MODE_PORTS_PER_ENG_4] = 1;
		break;
	}
	if (ECORE_IS_CMT(p_hwfn->p_dev))
		dev_data->mode_enable[MODE_100G] = 1;
	if (dev_data->mode_enable[MODE_PORTS_PER_ENG_1] ||
	    dev_data->mode_enable[MODE_100G])
		dev_data->num_ports = 1;
	else if (dev_data->mode_enable[MODE_PORTS_PER_ENG_2])
		dev_data->num_ports = 2;
	else if (dev_data->mode_enable[MODE_PORTS_PER_ENG_4])
		dev_data->num_ports = 4;
	dev_data->num_pfs_per_port = OSAL_MIN_T(u32,
						num_pfs / dev_data->num_ports,
						max_pfs_per_port);
	qed_dbg_grc_init_params(p_hwfn);
	dev_data->use_dmae = true;
	dev_data->initialized = 1;
	return DBG_STATUS_OK;
}
static enum dbg_status qed_dbg_dev_init ( struct ecore_hwfn * p_hwfn ) { struct dbg_tools_data * dev_data = & p_hwfn -> dbg_info ; u8 num_pfs = 0 , max_pfs_per_port = 0 ; if ( dev_data -> initialized ) return DBG_STATUS_OK ; if ( ECORE_IS_K2 ( p_hwfn -> p_dev ) ) { dev_data -> chip_id = CHIP_K2 ; dev_data -> mode_enable [ MODE_K2 ] = 1 ; dev_data -> num_vfs = MAX_NUM_VFS_K2 ; num_pfs = MAX_NUM_PFS_K2 ; max_pfs_per_port = MAX_NUM_PFS_K2 / 2 ; } else if ( ECORE_IS_BB_B0 ( p_hwfn -> p_dev ) ) { dev_data -> chip_id = CHIP_BB ; dev_data -> mode_enable [ MODE_BB ] = 1 ; dev_data -> num_vfs = MAX_NUM_VFS_BB ; num_pfs = MAX_NUM_PFS_BB ; max_pfs_per_port = MAX_NUM_PFS_BB ; } else { return DBG_STATUS_UNKNOWN_CHIP ; } dev_data -> hw_type = HW_TYPE_ASIC ; dev_data -> mode_enable [ MODE_ASIC ] = 1 ; switch ( p_hwfn -> p_dev -> num_ports_in_engine ) { case 1 : dev_data -> mode_enable [ MODE_PORTS_PER_ENG_1 ] = 1 ; break ; case 2 : dev_data -> mode_enable [ MODE_PORTS_PER_ENG_2 ] = 1 ; break ; case 4 : dev_data -> mode_enable [ MODE_PORTS_PER_ENG_4 ] = 1 ; break ; } if ( ECORE_IS_CMT ( p_hwfn -> p_dev ) ) dev_data -> mode_enable [ MODE_100G ] = 1 ; if ( dev_data -> mode_enable [ MODE_PORTS_PER_ENG_1 ] || dev_data -> mode_enable [ MODE_100G ] ) dev_data -> num_ports = 1 ; else if ( dev_data -> mode_enable [ MODE_PORTS_PER_ENG_2 ] ) dev_data -> num_ports = 2 ; else if ( dev_data -> mode_enable [ MODE_PORTS_PER_ENG_4 ] ) dev_data -> num_ports = 4 ; dev_data -> num_pfs_per_port = OSAL_MIN_T ( u32 , num_pfs / dev_data -> num_ports , max_pfs_per_port ) ; qed_dbg_grc_init_params ( p_hwfn ) ; dev_data -> use_dmae = true ; dev_data -> initialized = 1 ; return DBG_STATUS_OK ; }
Initializes debug data for the specified device
Initializes debug data for the specified device
/* Set chip */ /* Set HW type */ /* Set port mode */ /* Set 100G mode */ /* Set number of ports */ /* Set number of PFs per port */ /* Initializes the GRC parameters */