AzureMXChip/MXCHIPAZ3166/core/lib/threadx/ports_module/cortex_a35/gnu/example_build/sample_threadx_module_manager/timer_interrupts.c
void init_timer(void)
{
    // Enable interrupts
    __asm("MSR DAIFClr, #0xF");
    setICC_IGRPEN1_EL1(igrpEnable);

    // Configure the SP804 timer to generate an interrupt
    setTimerBaseAddress(0x1C110000);
    initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ);
    startTimer();

    // The SP804 timer generates SPI INTID 34.  Enable
    // this ID, and route it to core 0.0.0.0 (this one!)
    SetSPIRoute(34, 0, gicdirouter_ModeSpecific);    // Route INTID 34 to 0.0.0.0 (this core)
    SetSPIPriority(34, 0);                           // Set INTID 34 to priority to 0
    ConfigureSPI(34, gicdicfgr_Level);               // Set INTID 34 as level-sensitive
    EnableSPI(34);                                   // Enable INTID 34
}
// Initialize Timer 0 and Interrupt Controller
Initialize Timer 0 and Interrupt Controller
Initialize Timer 0 and Interrupt Controller
void init_timer(void)
{
    __asm("MSR DAIFClr, #0xF");
    setICC_IGRPEN1_EL1(igrpEnable);
    setTimerBaseAddress(0x1C110000);
    initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ);
    startTimer();
    SetSPIRoute(34, 0, gicdirouter_ModeSpecific);    
    SetSPIPriority(34, 0);                           
    ConfigureSPI(34, gicdicfgr_Level);               
    EnableSPI(34);                                   
}
void init_timer ( void ) { __asm ( " " ) ; setICC_IGRPEN1_EL1 ( igrpEnable ) ; setTimerBaseAddress ( 0x1C110000 ) ; initTimer ( 0x200 , SP804_AUTORELOAD , SP804_GENERATE_IRQ ) ; startTimer ( ) ; SetSPIRoute ( 34 , 0 , gicdirouter_ModeSpecific ) ; SetSPIPriority ( 34 , 0 ) ; ConfigureSPI ( 34 , gicdicfgr_Level ) ; EnableSPI ( 34 ) ; }
Initialize Timer 0 and Interrupt Controller
Initialize Timer 0 and Interrupt Controller
// Enable interrupts // Configure the SP804 timer to generate an interrupt // The SP804 timer generates SPI INTID 34.  Enable // this ID, and route it to core 0.0.0.0 (this one!) // Route INTID 34 to 0.0.0.0 (this core) // Set INTID 34 to priority to 0 // Set INTID 34 as level-sensitive // Enable INTID 34