AzureMXChip/MXCHIPAZ3166/core/lib/threadx/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c
void disableSecureFIQs(void)
{
  unsigned int tmp;

  tmp = gic_cpu->GICC_CTLR;
  tmp = tmp | 0xFFFFFFFF7;  // Clear bit 3
  gic_cpu->GICC_CTLR = tmp;
}
// Disables the sending of secure interrupts as FIQs
Disables the sending of secure interrupts as FIQs
Disables the sending of secure interrupts as FIQs
void disableSecureFIQs(void)
{
  unsigned int tmp;
  tmp = gic_cpu->GICC_CTLR;
  tmp = tmp | 0xFFFFFFFF7;  
  gic_cpu->GICC_CTLR = tmp;
}
void disableSecureFIQs ( void ) { unsigned int tmp ; tmp = gic_cpu -> GICC_CTLR ; tmp = tmp | 0xFFFFFFFF7 ; gic_cpu -> GICC_CTLR = tmp ; }
Disables the sending of secure interrupts as FIQs
Disables the sending of secure interrupts as FIQs
// Clear bit 3