src/dpdk/drivers/net/mlx5/mlx5_txq.c
static void
txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl)
{
	struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(txq_ctrl->priv));
	void *addr;
	const size_t page_size = rte_mem_page_size();
	if (page_size == (size_t)-1) {
		DRV_LOG(ERR, "Failed to get mem page size");
		rte_errno = ENOMEM;
	}

	if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
		return;
	addr = ppriv->uar_table[txq_ctrl->txq.idx];
	rte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
}
/**
 * Unmap UAR register of a Tx queue for secondary process.
 *
 * @param txq_ctrl
 *   Pointer to Tx queue control structure.
 */
Unmap UAR register of a Tx queue for secondary process.
@param txq_ctrl
Pointer to Tx queue control structure.
Unmap UAR register of a Tx queue for secondary process . @param txq_ctrl Pointer to Tx queue control structure .
static void
txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl)
{
	struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(txq_ctrl->priv));
	void *addr;
	const size_t page_size = rte_mem_page_size();
	if (page_size == (size_t)-1) {
		DRV_LOG(ERR, "Failed to get mem page size");
		rte_errno = ENOMEM;
	}
	if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
		return;
	addr = ppriv->uar_table[txq_ctrl->txq.idx];
	rte_mem_unmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
}
static void txq_uar_uninit_secondary ( struct mlx5_txq_ctrl * txq_ctrl ) { struct mlx5_proc_priv * ppriv = MLX5_PROC_PRIV ( PORT_ID ( txq_ctrl -> priv ) ) ; void * addr ; const size_t page_size = rte_mem_page_size ( ) ; if ( page_size == ( size_t ) -1 ) { DRV_LOG ( ERR , " " ) ; rte_errno = ENOMEM ; } if ( txq_ctrl -> type != MLX5_TXQ_TYPE_STANDARD ) return ; addr = ppriv -> uar_table [ txq_ctrl -> txq . idx ] ; rte_mem_unmap ( RTE_PTR_ALIGN_FLOOR ( addr , page_size ) , page_size ) ; }
Unmap UAR register of a Tx queue for secondary process.
Unmap UAR register of a Tx queue for secondary process .