XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c
int XSysMon_SetSeqChEnables(XSysMon *InstancePtr, u64 ChEnableMask)
{
	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * The sequencer must be in the Safe Mode before writing
	 * to these registers. Return XST_FAILURE if the channel sequencer
	 * is enabled.
	 */
	if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SAFE)) {
		return XST_FAILURE;
	}

	/*
	 * Enable the specified channels in the ADC Channel Selection Sequencer
	 * Registers.
	 */
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ00_OFFSET,
			 (ChEnableMask & XSM_SEQ00_CH_VALID_MASK));

	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ01_OFFSET,
			 (ChEnableMask >> XSM_SEQ_CH_AUX_SHIFT) &
			 XSM_SEQ01_CH_VALID_MASK);

	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			XSM_SEQ08_OFFSET,
			(ChEnableMask >> XSM_SEQ_CH_VUSR_SHIFT) &
			 XSM_SEQ08_CH_VALID_MASK);

	return XST_SUCCESS;
}
/****************************************************************************/
/**
*
* This function enables the specified channels in the ADC Channel Selection
* Sequencer Registers. The sequencer must be in the Safe Mode before writing
* to these registers.
*
* @param	InstancePtr is a pointer to the XSysMon instance.
* @param	ChEnableMask is the bit mask of all the channels to be enabled.
*		Use XSM_SEQ_CH_* defined in xsysmon_hw.h to specify the Channel
*		numbers. Bit masks of 1 will be enabled and bit mask of 0 will
*		be disabled.
*		The ChEnableMask is a 64 bit mask that is written to the three
*		16 bit ADC Channel Selection Sequencer Registers.
*
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the ADC Channel Selection Sequencer Registers.
*		- XST_FAILURE if the channel sequencer is enabled.
*
* @note		None.
*
*****************************************************************************/
This function enables the specified channels in the ADC Channel Selection
Sequencer Registers. The sequencer must be in the Safe Mode before writing
to these registers.
This function enables the specified channels in the ADC Channel Selection Sequencer Registers . The sequencer must be in the Safe Mode before writing to these registers .
int XSysMon_SetSeqChEnables(XSysMon *InstancePtr, u64 ChEnableMask)
{
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SAFE)) {
		return XST_FAILURE;
	}
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ00_OFFSET,
			 (ChEnableMask & XSM_SEQ00_CH_VALID_MASK));
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ01_OFFSET,
			 (ChEnableMask >> XSM_SEQ_CH_AUX_SHIFT) &
			 XSM_SEQ01_CH_VALID_MASK);
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			XSM_SEQ08_OFFSET,
			(ChEnableMask >> XSM_SEQ_CH_VUSR_SHIFT) &
			 XSM_SEQ08_CH_VALID_MASK);
	return XST_SUCCESS;
}
int XSysMon_SetSeqChEnables ( XSysMon * InstancePtr , u64 ChEnableMask ) { Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; if ( ( XSysMon_GetSequencerMode ( InstancePtr ) != XSM_SEQ_MODE_SAFE ) ) { return XST_FAILURE ; } XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ00_OFFSET , ( ChEnableMask & XSM_SEQ00_CH_VALID_MASK ) ) ; XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ01_OFFSET , ( ChEnableMask >> XSM_SEQ_CH_AUX_SHIFT ) & XSM_SEQ01_CH_VALID_MASK ) ; XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ08_OFFSET , ( ChEnableMask >> XSM_SEQ_CH_VUSR_SHIFT ) & XSM_SEQ08_CH_VALID_MASK ) ; return XST_SUCCESS ; }
This function enables the specified channels in the ADC Channel Selection
Sequencer Registers.
This function enables the specified channels in the ADC Channel Selection Sequencer Registers .
/*
	 * Assert the arguments.
	 */ /*
	 * The sequencer must be in the Safe Mode before writing
	 * to these registers. Return XST_FAILURE if the channel sequencer
	 * is enabled.
	 */ /*
	 * Enable the specified channels in the ADC Channel Selection Sequencer
	 * Registers.
	 */