XilinxProcessorIPLib/drivers/srio/examples/xsrio_dma_loopback_example.c
int XSrioDmaLoopbackExample(XSrio *InstancePtr, u16 DeviceId)
{
	XSrio_Config *SrioConfig;
	XAxiDma_Config *DmaConfig;
	int Status = XST_SUCCESS;
	int Count = 0;
	
	/* Initialize the SRIO Device Configuration Interface driver */
	SrioConfig = XSrio_LookupConfig(DeviceId);
	if (!SrioConfig) {
		xil_printf("No SRIO config found for %d\r\n", DeviceId);
		return XST_FAILURE;
	}

	/**< This is where the virtual address would be used, this example
	 * uses physical address.
	 */
	Status = XSrio_CfgInitialize(InstancePtr, SrioConfig,
				SrioConfig->BaseAddress);
	if (Status != XST_SUCCESS) {
		xil_printf("Initialization failed for SRIO\n\r");
		return Status;
	}
	 
	 /* Check for PE Configuration */
	Status = XSrio_GetPEType(InstancePtr); 
	if (Status != XSRIO_IS_MEMORY) {
		xil_printf("SRIO is not configured as the Memory \n\r");
		return XST_FAILURE;
	}
		
	/* Clearing the Memory */
	for(Count=0; Count<(128*1024); Count += 4) {
		*(u32 *)(MEM_ADDR + Count) = 0;
	}
	
	/**< Check whether Streaming Write Operation is Supported by the 
	 * Core or not Since it is a loopback Example Checking at the both 
	 * Target and source Operations.
	 */
	Status = XSrio_IsOperationSupported(InstancePtr, XSRIO_OP_MODE_SWRITE,
						XSRIO_DIR_TX);
	if (Status != XST_SUCCESS) {
                return XST_FAILURE;
        }
	
	Status = XSrio_IsOperationSupported(InstancePtr, XSRIO_OP_MODE_SWRITE,
						XSRIO_DIR_RX);
	if (Status != XST_SUCCESS) {
                return XST_FAILURE;
        }
	
	/**< Frame the SRIO Write-Stream Packet in the Memory 
	 * The Packet-format used here is HELLO Packet format
	 * More details look into pg 3.1 version:73 page(HELLO PACKET FORMAT).
	 */
	*(u32 *)(MEM_ADDR + 0x00) = 0x50000600;
		/* Lower word of the HELLO Packet */
	*(u32 *)(MEM_ADDR + 0x04) = 0x08602F74;
		/* Upper word of the HELLO packet */
	Count = 8;

	while(Count<(DATA_SIZE * 2)) {
		*(u32 *)(MEM_ADDR + Count) = Count;
		 Count += 4;
	}
	
	/* SRIO Configuration */
	/* Set the Local Configuration Space Base Address */
	XSrio_SetLCSBA(InstancePtr, 0xFFF);
        /* Set the Water Mark Level to transfer priority 0,1,2 packet */
	XSrio_SetWaterMark(InstancePtr, 0x5, 0x4, 0x3);
        /* Set the Port Response timeout value */
	XSrio_SetPortRespTimeOutValue(InstancePtr, 0x010203);
	
	/* DMA Configuration */
	DmaConfig = XAxiDma_LookupConfig(DMA_DEV_ID);
    	if (!DmaConfig) {
           xil_printf("No DMA config found for %d\r\n", DMA_DEV_ID);
           return XST_FAILURE;
    	}

	/* Initialize DMA engine */
    	Status = XAxiDma_CfgInitialize(&AxiDma, DmaConfig);
	if (Status != XST_SUCCESS) {
           xil_printf("Initialization failed %d\r\n", Status);
           return XST_FAILURE;
     	}
	
	/**< Configure the DMA Tx Side 
         * MEM_ADDR is the address where Tx packet is formed
	 */
	XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_CR_OFFSET,
				XAXIDMA_CR_RUNSTOP_MASK);
	XAxiDma_IntrEnable(&AxiDma,XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
	XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_SRCADDR_OFFSET, MEM_ADDR);

	/*
	 * Configure the DMA Rx Side
     * MEM_ADDR+0x5000 is the address where Rx packet is formed
	 */
	XAxiDma_WriteReg(DmaConfig->BaseAddr,
		XAXIDMA_RX_OFFSET+XAXIDMA_CR_OFFSET, XAXIDMA_CR_RUNSTOP_MASK);
	XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
	XAxiDma_WriteReg(DmaConfig->BaseAddr,
		XAXIDMA_RX_OFFSET + XAXIDMA_DESTADDR_OFFSET, MEM_ADDR+0x5000);
	
	
	for(Count=8; Count<DATA_SIZE; Count += 4) {
		*(u32 *)(MEM_ADDR + Count) = Count;
	}
	
	XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_BUFFLEN_OFFSET, 256);
	/* Wait till DMA MM2S Transfer Complete */
	while(!(XAxiDma_ReadReg(DmaConfig->BaseAddr, XAXIDMA_SR_OFFSET)
			& 0x1000));
	XAxiDma_WriteReg(DmaConfig->BaseAddr,
			XAXIDMA_RX_OFFSET+XAXIDMA_BUFFLEN_OFFSET, 256);
	 /* Wait till S2MM Transfer Complete */
	  while(!( XAxiDma_ReadReg(DmaConfig->BaseAddr,
			XAXIDMA_RX_OFFSET+XAXIDMA_SR_OFFSET) & 0x1000));
	  	
	/* Verifying the Data */
	for(Count=8; Count<DATA_SIZE; Count += 4) {
		if(*(u32 *)(MEM_ADDR + 0x5000 + Count) 
				!= *(u32 *)(MEM_ADDR + Count)) {
			xil_printf("\n ERROR in Transfer\n\r");
			return XST_FAILURE;
		}
	}	

	/* Clearing the Memory */
	for(Count=0x5000; Count<(0x6000); Count += 4) {
		*(u32 *)(MEM_ADDR + Count) = 0;
	}

	for(Count=0; Count<DATA_SIZE; Count += 4) {
		if(*(u32 *)(MEM_ADDR + 0x5000+ Count) != 0x00) {
			xil_printf("\n ERROR in Clearing Memory\n\r");
			return XST_FAILURE;
		}
	}	

	return Status;
}
/*****************************************************************************/
/**
* XSrioDmaLoopbackExample This function does a minimal test on the XSrio device
* and driver as a design example. The purpose of this function is to illustrate
* how to use the XSrio Component.
* 
* This function does the following:
*	- Initialize the SRIO device
* 	- Initialize the DMA engine
*	- Clearing the Memory
* 	- Framing the SRIO Packet in the Memory
*	- Configuring the SRIO
* 	- Configuring the DMA
*	- Verifying the Data
*
* @param	InstancePtr is a pointer to the instance of the
*		XSrio driver.
* @param	DeviceId is Device ID of the SRIO Gen2 Device.
*
* @return
*		-XST_SUCCESS to indicate success
*		-XST_FAILURE to indicate failure
*
******************************************************************************/
XSrioDmaLoopbackExample This function does a minimal test on the XSrio device
and driver as a design example. The purpose of this function is to illustrate
how to use the XSrio Component.

This function does the following:
Initialize the SRIO device
Initialize the DMA engine
Clearing the Memory
Framing the SRIO Packet in the Memory
Configuring the SRIO
Configuring the DMA
Verifying the Data
XSrioDmaLoopbackExample This function does a minimal test on the XSrio device and driver as a design example . The purpose of this function is to illustrate how to use the XSrio Component . This function does the following : Initialize the SRIO device Initialize the DMA engine Clearing the Memory Framing the SRIO Packet in the Memory Configuring the SRIO Configuring the DMA Verifying the Data
int XSrioDmaLoopbackExample(XSrio *InstancePtr, u16 DeviceId)
{
	XSrio_Config *SrioConfig;
	XAxiDma_Config *DmaConfig;
	int Status = XST_SUCCESS;
	int Count = 0;
	SrioConfig = XSrio_LookupConfig(DeviceId);
	if (!SrioConfig) {
		xil_printf("No SRIO config found for %d\r\n", DeviceId);
		return XST_FAILURE;
	}
	Status = XSrio_CfgInitialize(InstancePtr, SrioConfig,
				SrioConfig->BaseAddress);
	if (Status != XST_SUCCESS) {
		xil_printf("Initialization failed for SRIO\n\r");
		return Status;
	}
	Status = XSrio_GetPEType(InstancePtr); 
	if (Status != XSRIO_IS_MEMORY) {
		xil_printf("SRIO is not configured as the Memory \n\r");
		return XST_FAILURE;
	}
	for(Count=0; Count<(128*1024); Count += 4) {
		*(u32 *)(MEM_ADDR + Count) = 0;
	}
	Status = XSrio_IsOperationSupported(InstancePtr, XSRIO_OP_MODE_SWRITE,
						XSRIO_DIR_TX);
	if (Status != XST_SUCCESS) {
                return XST_FAILURE;
        }
	Status = XSrio_IsOperationSupported(InstancePtr, XSRIO_OP_MODE_SWRITE,
						XSRIO_DIR_RX);
	if (Status != XST_SUCCESS) {
                return XST_FAILURE;
        }
	*(u32 *)(MEM_ADDR + 0x00) = 0x50000600;
	*(u32 *)(MEM_ADDR + 0x04) = 0x08602F74;
	Count = 8;
	while(Count<(DATA_SIZE * 2)) {
		*(u32 *)(MEM_ADDR + Count) = Count;
		 Count += 4;
	}
	XSrio_SetLCSBA(InstancePtr, 0xFFF);
	XSrio_SetWaterMark(InstancePtr, 0x5, 0x4, 0x3);
	XSrio_SetPortRespTimeOutValue(InstancePtr, 0x010203);
	DmaConfig = XAxiDma_LookupConfig(DMA_DEV_ID);
    	if (!DmaConfig) {
           xil_printf("No DMA config found for %d\r\n", DMA_DEV_ID);
           return XST_FAILURE;
    	}
    	Status = XAxiDma_CfgInitialize(&AxiDma, DmaConfig);
	if (Status != XST_SUCCESS) {
           xil_printf("Initialization failed %d\r\n", Status);
           return XST_FAILURE;
     	}
	XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_CR_OFFSET,
				XAXIDMA_CR_RUNSTOP_MASK);
	XAxiDma_IntrEnable(&AxiDma,XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DMA_TO_DEVICE);
	XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_SRCADDR_OFFSET, MEM_ADDR);
	XAxiDma_WriteReg(DmaConfig->BaseAddr,
		XAXIDMA_RX_OFFSET+XAXIDMA_CR_OFFSET, XAXIDMA_CR_RUNSTOP_MASK);
	XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_IOC_MASK, XAXIDMA_DEVICE_TO_DMA);
	XAxiDma_WriteReg(DmaConfig->BaseAddr,
		XAXIDMA_RX_OFFSET + XAXIDMA_DESTADDR_OFFSET, MEM_ADDR+0x5000);
	for(Count=8; Count<DATA_SIZE; Count += 4) {
		*(u32 *)(MEM_ADDR + Count) = Count;
	}
	XAxiDma_WriteReg(DmaConfig->BaseAddr, XAXIDMA_BUFFLEN_OFFSET, 256);
	while(!(XAxiDma_ReadReg(DmaConfig->BaseAddr, XAXIDMA_SR_OFFSET)
			& 0x1000));
	XAxiDma_WriteReg(DmaConfig->BaseAddr,
			XAXIDMA_RX_OFFSET+XAXIDMA_BUFFLEN_OFFSET, 256);
	  while(!( XAxiDma_ReadReg(DmaConfig->BaseAddr,
			XAXIDMA_RX_OFFSET+XAXIDMA_SR_OFFSET) & 0x1000));
	for(Count=8; Count<DATA_SIZE; Count += 4) {
		if(*(u32 *)(MEM_ADDR + 0x5000 + Count) 
				!= *(u32 *)(MEM_ADDR + Count)) {
			xil_printf("\n ERROR in Transfer\n\r");
			return XST_FAILURE;
		}
	}	
	for(Count=0x5000; Count<(0x6000); Count += 4) {
		*(u32 *)(MEM_ADDR + Count) = 0;
	}
	for(Count=0; Count<DATA_SIZE; Count += 4) {
		if(*(u32 *)(MEM_ADDR + 0x5000+ Count) != 0x00) {
			xil_printf("\n ERROR in Clearing Memory\n\r");
			return XST_FAILURE;
		}
	}	
	return Status;
}
int XSrioDmaLoopbackExample ( XSrio * InstancePtr , u16 DeviceId ) { XSrio_Config * SrioConfig ; XAxiDma_Config * DmaConfig ; int Status = XST_SUCCESS ; int Count = 0 ; SrioConfig = XSrio_LookupConfig ( DeviceId ) ; if ( ! SrioConfig ) { xil_printf ( " \r \n " , DeviceId ) ; return XST_FAILURE ; } Status = XSrio_CfgInitialize ( InstancePtr , SrioConfig , SrioConfig -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return Status ; } Status = XSrio_GetPEType ( InstancePtr ) ; if ( Status != XSRIO_IS_MEMORY ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } for ( Count = 0 ; Count < ( 128 * 1024 ) ; Count += 4 ) { * ( u32 * ) ( MEM_ADDR + Count ) = 0 ; } Status = XSrio_IsOperationSupported ( InstancePtr , XSRIO_OP_MODE_SWRITE , XSRIO_DIR_TX ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } Status = XSrio_IsOperationSupported ( InstancePtr , XSRIO_OP_MODE_SWRITE , XSRIO_DIR_RX ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } * ( u32 * ) ( MEM_ADDR + 0x00 ) = 0x50000600 ; * ( u32 * ) ( MEM_ADDR + 0x04 ) = 0x08602F74 ; Count = 8 ; while ( Count < ( DATA_SIZE * 2 ) ) { * ( u32 * ) ( MEM_ADDR + Count ) = Count ; Count += 4 ; } XSrio_SetLCSBA ( InstancePtr , 0xFFF ) ; XSrio_SetWaterMark ( InstancePtr , 0x5 , 0x4 , 0x3 ) ; XSrio_SetPortRespTimeOutValue ( InstancePtr , 0x010203 ) ; DmaConfig = XAxiDma_LookupConfig ( DMA_DEV_ID ) ; if ( ! DmaConfig ) { xil_printf ( " \r \n " , DMA_DEV_ID ) ; return XST_FAILURE ; } Status = XAxiDma_CfgInitialize ( & AxiDma , DmaConfig ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \r \n " , Status ) ; return XST_FAILURE ; } XAxiDma_WriteReg ( DmaConfig -> BaseAddr , XAXIDMA_CR_OFFSET , XAXIDMA_CR_RUNSTOP_MASK ) ; XAxiDma_IntrEnable ( & AxiDma , XAXIDMA_IRQ_IOC_MASK , XAXIDMA_DMA_TO_DEVICE ) ; XAxiDma_WriteReg ( DmaConfig -> BaseAddr , XAXIDMA_SRCADDR_OFFSET , MEM_ADDR ) ; XAxiDma_WriteReg ( DmaConfig -> BaseAddr , XAXIDMA_RX_OFFSET + XAXIDMA_CR_OFFSET , XAXIDMA_CR_RUNSTOP_MASK ) ; XAxiDma_IntrEnable ( & AxiDma , XAXIDMA_IRQ_IOC_MASK , XAXIDMA_DEVICE_TO_DMA ) ; XAxiDma_WriteReg ( DmaConfig -> BaseAddr , XAXIDMA_RX_OFFSET + XAXIDMA_DESTADDR_OFFSET , MEM_ADDR + 0x5000 ) ; for ( Count = 8 ; Count < DATA_SIZE ; Count += 4 ) { * ( u32 * ) ( MEM_ADDR + Count ) = Count ; } XAxiDma_WriteReg ( DmaConfig -> BaseAddr , XAXIDMA_BUFFLEN_OFFSET , 256 ) ; while ( ! ( XAxiDma_ReadReg ( DmaConfig -> BaseAddr , XAXIDMA_SR_OFFSET ) & 0x1000 ) ) ; XAxiDma_WriteReg ( DmaConfig -> BaseAddr , XAXIDMA_RX_OFFSET + XAXIDMA_BUFFLEN_OFFSET , 256 ) ; while ( ! ( XAxiDma_ReadReg ( DmaConfig -> BaseAddr , XAXIDMA_RX_OFFSET + XAXIDMA_SR_OFFSET ) & 0x1000 ) ) ; for ( Count = 8 ; Count < DATA_SIZE ; Count += 4 ) { if ( * ( u32 * ) ( MEM_ADDR + 0x5000 + Count ) != * ( u32 * ) ( MEM_ADDR + Count ) ) { xil_printf ( " \n \n \r " ) ; return XST_FAILURE ; } } for ( Count = 0x5000 ; Count < ( 0x6000 ) ; Count += 4 ) { * ( u32 * ) ( MEM_ADDR + Count ) = 0 ; } for ( Count = 0 ; Count < DATA_SIZE ; Count += 4 ) { if ( * ( u32 * ) ( MEM_ADDR + 0x5000 + Count ) != 0x00 ) { xil_printf ( " \n \n \r " ) ; return XST_FAILURE ; } } return Status ; }
XSrioDmaLoopbackExample This function does a minimal test on the XSrio device
and driver as a design example.
XSrioDmaLoopbackExample This function does a minimal test on the XSrio device and driver as a design example .
/* Initialize the SRIO Device Configuration Interface driver */ /**< This is where the virtual address would be used, this example
	 * uses physical address.
	 */ /* Check for PE Configuration */ /* Clearing the Memory */ /**< Check whether Streaming Write Operation is Supported by the 
	 * Core or not Since it is a loopback Example Checking at the both 
	 * Target and source Operations.
	 */ /**< Frame the SRIO Write-Stream Packet in the Memory 
	 * The Packet-format used here is HELLO Packet format
	 * More details look into pg 3.1 version:73 page(HELLO PACKET FORMAT).
	 */ /* Lower word of the HELLO Packet */ /* Upper word of the HELLO packet */ /* SRIO Configuration */ /* Set the Local Configuration Space Base Address */ /* Set the Water Mark Level to transfer priority 0,1,2 packet */ /* Set the Port Response timeout value */ /* DMA Configuration */ /* Initialize DMA engine */ /**< Configure the DMA Tx Side 
         * MEM_ADDR is the address where Tx packet is formed
	 */ /*
	 * Configure the DMA Rx Side
     * MEM_ADDR+0x5000 is the address where Rx packet is formed
	 */ /* Wait till DMA MM2S Transfer Complete */ /* Wait till S2MM Transfer Complete */ /* Verifying the Data */ /* Clearing the Memory */