src/dpdk/drivers/net/igc/base/igc_base.c
void igc_rx_fifo_flush_base(struct igc_hw *hw)
{
	u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
	int i, ms_wait;

	DEBUGFUNC("igc_rx_fifo_flush_base");

	/* disable IPv6 options as per hardware errata */
	rfctl = IGC_READ_REG(hw, IGC_RFCTL);
	rfctl |= IGC_RFCTL_IPV6_EX_DIS;
	IGC_WRITE_REG(hw, IGC_RFCTL, rfctl);

	if (!(IGC_READ_REG(hw, IGC_MANC) & IGC_MANC_RCV_TCO_EN))
		return;

	/* Disable all Rx queues */
	for (i = 0; i < 4; i++) {
		rxdctl[i] = IGC_READ_REG(hw, IGC_RXDCTL(i));
		IGC_WRITE_REG(hw, IGC_RXDCTL(i),
				rxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE);
	}
	/* Poll all queues to verify they have shut down */
	for (ms_wait = 0; ms_wait < 10; ms_wait++) {
		msec_delay(1);
		rx_enabled = 0;
		for (i = 0; i < 4; i++)
			rx_enabled |= IGC_READ_REG(hw, IGC_RXDCTL(i));
		if (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE))
			break;
	}

	if (ms_wait == 10)
		DEBUGOUT("Queue disable timed out after 10ms\n");

	/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
	 * incoming packets are rejected.  Set enable and wait 2ms so that
	 * any packet that was coming in as RCTL.EN was set is flushed
	 */
	IGC_WRITE_REG(hw, IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF);

	rlpml = IGC_READ_REG(hw, IGC_RLPML);
	IGC_WRITE_REG(hw, IGC_RLPML, 0);

	rctl = IGC_READ_REG(hw, IGC_RCTL);
	temp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP);
	temp_rctl |= IGC_RCTL_LPE;

	IGC_WRITE_REG(hw, IGC_RCTL, temp_rctl);
	IGC_WRITE_REG(hw, IGC_RCTL, temp_rctl | IGC_RCTL_EN);
	IGC_WRITE_FLUSH(hw);
	msec_delay(2);

	/* Enable Rx queues that were previously enabled and restore our
	 * previous state
	 */
	for (i = 0; i < 4; i++)
		IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl[i]);
	IGC_WRITE_REG(hw, IGC_RCTL, rctl);
	IGC_WRITE_FLUSH(hw);

	IGC_WRITE_REG(hw, IGC_RLPML, rlpml);
	IGC_WRITE_REG(hw, IGC_RFCTL, rfctl);

	/* Flush receive errors generated by workaround */
	IGC_READ_REG(hw, IGC_ROC);
	IGC_READ_REG(hw, IGC_RNBC);
	IGC_READ_REG(hw, IGC_MPC);
}
/**
 *  igc_rx_fifo_flush_base - Clean Rx FIFO after Rx enable
 *  @hw: pointer to the HW structure
 *
 *  After Rx enable, if manageability is enabled then there is likely some
 *  bad data at the start of the FIFO and possibly in the DMA FIFO.  This
 *  function clears the FIFOs and flushes any packets that came in as Rx was
 *  being enabled.
 **/
Clean Rx FIFO after Rx enable
@hw: pointer to the HW structure

After Rx enable, if manageability is enabled then there is likely some
bad data at the start of the FIFO and possibly in the DMA FIFO.  This
function clears the FIFOs and flushes any packets that came in as Rx was
being enabled.
Clean Rx FIFO after Rx enable @hw : pointer to the HW structure After Rx enable if manageability is enabled then there is likely some bad data at the start of the FIFO and possibly in the DMA FIFO . This function clears the FIFOs and flushes any packets that came in as Rx was being enabled .
void igc_rx_fifo_flush_base(struct igc_hw *hw)
{
	u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
	int i, ms_wait;
	DEBUGFUNC("igc_rx_fifo_flush_base");
	rfctl = IGC_READ_REG(hw, IGC_RFCTL);
	rfctl |= IGC_RFCTL_IPV6_EX_DIS;
	IGC_WRITE_REG(hw, IGC_RFCTL, rfctl);
	if (!(IGC_READ_REG(hw, IGC_MANC) & IGC_MANC_RCV_TCO_EN))
		return;
	for (i = 0; i < 4; i++) {
		rxdctl[i] = IGC_READ_REG(hw, IGC_RXDCTL(i));
		IGC_WRITE_REG(hw, IGC_RXDCTL(i),
				rxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE);
	}
	for (ms_wait = 0; ms_wait < 10; ms_wait++) {
		msec_delay(1);
		rx_enabled = 0;
		for (i = 0; i < 4; i++)
			rx_enabled |= IGC_READ_REG(hw, IGC_RXDCTL(i));
		if (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE))
			break;
	}
	if (ms_wait == 10)
		DEBUGOUT("Queue disable timed out after 10ms\n");
	IGC_WRITE_REG(hw, IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF);
	rlpml = IGC_READ_REG(hw, IGC_RLPML);
	IGC_WRITE_REG(hw, IGC_RLPML, 0);
	rctl = IGC_READ_REG(hw, IGC_RCTL);
	temp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP);
	temp_rctl |= IGC_RCTL_LPE;
	IGC_WRITE_REG(hw, IGC_RCTL, temp_rctl);
	IGC_WRITE_REG(hw, IGC_RCTL, temp_rctl | IGC_RCTL_EN);
	IGC_WRITE_FLUSH(hw);
	msec_delay(2);
	for (i = 0; i < 4; i++)
		IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl[i]);
	IGC_WRITE_REG(hw, IGC_RCTL, rctl);
	IGC_WRITE_FLUSH(hw);
	IGC_WRITE_REG(hw, IGC_RLPML, rlpml);
	IGC_WRITE_REG(hw, IGC_RFCTL, rfctl);
	IGC_READ_REG(hw, IGC_ROC);
	IGC_READ_REG(hw, IGC_RNBC);
	IGC_READ_REG(hw, IGC_MPC);
}
void igc_rx_fifo_flush_base ( struct igc_hw * hw ) { u32 rctl , rlpml , rxdctl [ 4 ] , rfctl , temp_rctl , rx_enabled ; int i , ms_wait ; DEBUGFUNC ( " " ) ; rfctl = IGC_READ_REG ( hw , IGC_RFCTL ) ; rfctl |= IGC_RFCTL_IPV6_EX_DIS ; IGC_WRITE_REG ( hw , IGC_RFCTL , rfctl ) ; if ( ! ( IGC_READ_REG ( hw , IGC_MANC ) & IGC_MANC_RCV_TCO_EN ) ) return ; for ( i = 0 ; i < 4 ; i ++ ) { rxdctl [ i ] = IGC_READ_REG ( hw , IGC_RXDCTL ( i ) ) ; IGC_WRITE_REG ( hw , IGC_RXDCTL ( i ) , rxdctl [ i ] & ~ IGC_RXDCTL_QUEUE_ENABLE ) ; } for ( ms_wait = 0 ; ms_wait < 10 ; ms_wait ++ ) { msec_delay ( 1 ) ; rx_enabled = 0 ; for ( i = 0 ; i < 4 ; i ++ ) rx_enabled |= IGC_READ_REG ( hw , IGC_RXDCTL ( i ) ) ; if ( ! ( rx_enabled & IGC_RXDCTL_QUEUE_ENABLE ) ) break ; } if ( ms_wait == 10 ) DEBUGOUT ( " \n " ) ; IGC_WRITE_REG ( hw , IGC_RFCTL , rfctl & ~ IGC_RFCTL_LEF ) ; rlpml = IGC_READ_REG ( hw , IGC_RLPML ) ; IGC_WRITE_REG ( hw , IGC_RLPML , 0 ) ; rctl = IGC_READ_REG ( hw , IGC_RCTL ) ; temp_rctl = rctl & ~ ( IGC_RCTL_EN | IGC_RCTL_SBP ) ; temp_rctl |= IGC_RCTL_LPE ; IGC_WRITE_REG ( hw , IGC_RCTL , temp_rctl ) ; IGC_WRITE_REG ( hw , IGC_RCTL , temp_rctl | IGC_RCTL_EN ) ; IGC_WRITE_FLUSH ( hw ) ; msec_delay ( 2 ) ; for ( i = 0 ; i < 4 ; i ++ ) IGC_WRITE_REG ( hw , IGC_RXDCTL ( i ) , rxdctl [ i ] ) ; IGC_WRITE_REG ( hw , IGC_RCTL , rctl ) ; IGC_WRITE_FLUSH ( hw ) ; IGC_WRITE_REG ( hw , IGC_RLPML , rlpml ) ; IGC_WRITE_REG ( hw , IGC_RFCTL , rfctl ) ; IGC_READ_REG ( hw , IGC_ROC ) ; IGC_READ_REG ( hw , IGC_RNBC ) ; IGC_READ_REG ( hw , IGC_MPC ) ; }
igc_rx_fifo_flush_base - Clean Rx FIFO after Rx enable
  @hw: pointer to the HW structure
igc_rx_fifo_flush_base - Clean Rx FIFO after Rx enable @hw : pointer to the HW structure
/* disable IPv6 options as per hardware errata */ /* Disable all Rx queues */ /* Poll all queues to verify they have shut down */ /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
	 * incoming packets are rejected.  Set enable and wait 2ms so that
	 * any packet that was coming in as RCTL.EN was set is flushed
	 */ /* Enable Rx queues that were previously enabled and restore our
	 * previous state
	 */ /* Flush receive errors generated by workaround */