XilinxProcessorIPLib/drivers/dp14txss/examples/src/pt_only/tx.c
void sendAudioInfoFrame(XDp_TxAudioInfoFrame *xilInfoFrame)
{
	u8 db1, db2, db3, db4;
	u32 temp;
	u8 RSVD=0;

	//Fixed paramaters
	u8  dp_version   = xilInfoFrame->version;

	//Write #1
	db1 = 0x00; //sec packet ID fixed to 0 - SST Mode
	db2 = xilInfoFrame->type;
	db3 = xilInfoFrame->info_length&0xFF;
	db4 = (dp_version<<2)|(xilInfoFrame->info_length>>8);
	temp = db4<<24|db3<<16|db2<<8|db1;
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
		     XDP_TX_AUDIO_INFO_DATA(1), temp);

	//Write #2
	db1 = xilInfoFrame->audio_channel_count
					| (xilInfoFrame->audio_coding_type<<4) | (RSVD<<3);
	db2 = (RSVD<<5)| (xilInfoFrame->sampling_frequency<<2)
					| xilInfoFrame->sample_size;
	db3 = RSVD;
	db4 = xilInfoFrame->channel_allocation;
	temp = db4 << 24 | db3 << 16 | db2 << 8 | db1;
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);

	//Write #3
	db1 = (xilInfoFrame->level_shift<<3) | RSVD
								| (xilInfoFrame->downmix_inhibit <<7);
	db2 = RSVD;
	db3 = RSVD;
	db4 = RSVD;
	temp = db4 << 24 | db3 << 16 | db2 << 8 | db1;
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);

	//Write #4
	db1 = RSVD;
	db2 = RSVD;
	db3 = RSVD;
	db4 = RSVD;
	temp = 0x00000000;
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);
	//Write #5
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);

	//Write #6
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);
	//Write #7
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);
	//Write #8
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);
}
// This functionality moved to driver wef 2019.2
This functionality moved to driver wef 2019.2
This functionality moved to driver wef 2019 . 2
void sendAudioInfoFrame(XDp_TxAudioInfoFrame *xilInfoFrame)
{
	u8 db1, db2, db3, db4;
	u32 temp;
	u8 RSVD=0;
	u8  dp_version   = xilInfoFrame->version;
	db1 = 0x00; 
	db2 = xilInfoFrame->type;
	db3 = xilInfoFrame->info_length&0xFF;
	db4 = (dp_version<<2)|(xilInfoFrame->info_length>>8);
	temp = db4<<24|db3<<16|db2<<8|db1;
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
		     XDP_TX_AUDIO_INFO_DATA(1), temp);
	db1 = xilInfoFrame->audio_channel_count
					| (xilInfoFrame->audio_coding_type<<4) | (RSVD<<3);
	db2 = (RSVD<<5)| (xilInfoFrame->sampling_frequency<<2)
					| xilInfoFrame->sample_size;
	db3 = RSVD;
	db4 = xilInfoFrame->channel_allocation;
	temp = db4 << 24 | db3 << 16 | db2 << 8 | db1;
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);
	db1 = (xilInfoFrame->level_shift<<3) | RSVD
								| (xilInfoFrame->downmix_inhibit <<7);
	db2 = RSVD;
	db3 = RSVD;
	db4 = RSVD;
	temp = db4 << 24 | db3 << 16 | db2 << 8 | db1;
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);
	db1 = RSVD;
	db2 = RSVD;
	db3 = RSVD;
	db4 = RSVD;
	temp = 0x00000000;
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_AUDIO_INFO_DATA(1), temp);
}
void sendAudioInfoFrame ( XDp_TxAudioInfoFrame * xilInfoFrame ) { u8 db1 , db2 , db3 , db4 ; u32 temp ; u8 RSVD = 0 ; u8 dp_version = xilInfoFrame -> version ; db1 = 0x00 ; db2 = xilInfoFrame -> type ; db3 = xilInfoFrame -> info_length & 0xFF ; db4 = ( dp_version << 2 ) | ( xilInfoFrame -> info_length >> 8 ) ; temp = db4 << 24 | db3 << 16 | db2 << 8 | db1 ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_AUDIO_INFO_DATA ( 1 ) , temp ) ; db1 = xilInfoFrame -> audio_channel_count | ( xilInfoFrame -> audio_coding_type << 4 ) | ( RSVD << 3 ) ; db2 = ( RSVD << 5 ) | ( xilInfoFrame -> sampling_frequency << 2 ) | xilInfoFrame -> sample_size ; db3 = RSVD ; db4 = xilInfoFrame -> channel_allocation ; temp = db4 << 24 | db3 << 16 | db2 << 8 | db1 ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_AUDIO_INFO_DATA ( 1 ) , temp ) ; db1 = ( xilInfoFrame -> level_shift << 3 ) | RSVD | ( xilInfoFrame -> downmix_inhibit << 7 ) ; db2 = RSVD ; db3 = RSVD ; db4 = RSVD ; temp = db4 << 24 | db3 << 16 | db2 << 8 | db1 ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_AUDIO_INFO_DATA ( 1 ) , temp ) ; db1 = RSVD ; db2 = RSVD ; db3 = RSVD ; db4 = RSVD ; temp = 0x00000000 ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_AUDIO_INFO_DATA ( 1 ) , temp ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_AUDIO_INFO_DATA ( 1 ) , temp ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_AUDIO_INFO_DATA ( 1 ) , temp ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_AUDIO_INFO_DATA ( 1 ) , temp ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_AUDIO_INFO_DATA ( 1 ) , temp ) ; }
This functionality moved to driver wef 2019.2
This functionality moved to driver wef 2019 . 2
//Fixed paramaters //Write #1 //sec packet ID fixed to 0 - SST Mode //Write #2 //Write #3 //Write #4 //Write #5 //Write #6 //Write #7 //Write #8