XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1.c
u32 XHdmiphy1_CfgLineRate(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, u64 LineRateHz)
{
	u8 Id;
	u8 Id0;
	u8 Id1;

	XHdmiphy1_Ch2Ids(InstancePtr, ChId, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(Id)].LineRateHz =
								LineRateHz;
	}

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
* Configure the channel's line rate. This is a software only configuration and
* this value is used in the PLL calculator.
*
* @param	InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
* @param	LineRate is the line rate to configure software.
*
* @return
*		- XST_SUCCESS if the reference clock type is valid.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
Configure the channel's line rate. This is a software only configuration and
this value is used in the PLL calculator.
Configure the channel ' s line rate . This is a software only configuration and this value is used in the PLL calculator .
u32 XHdmiphy1_CfgLineRate(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, u64 LineRateHz)
{
	u8 Id;
	u8 Id0;
	u8 Id1;
	XHdmiphy1_Ch2Ids(InstancePtr, ChId, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(Id)].LineRateHz =
								LineRateHz;
	}
	return XST_SUCCESS;
}
u32 XHdmiphy1_CfgLineRate ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId , u64 LineRateHz ) { u8 Id ; u8 Id0 ; u8 Id1 ; XHdmiphy1_Ch2Ids ( InstancePtr , ChId , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ QuadId ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . LineRateHz = LineRateHz ; } return XST_SUCCESS ; }
Configure the channel's line rate.
Configure the channel ' s line rate .