XilinxProcessorIPLib/drivers/avbuf/src/xavbuf_clk.c
static int  XAVBuf_ConfigurePll(XAVBuf_Pll *PllInstancePtr)
{
	u32 BaseAddress = PllInstancePtr->BaseAddress;
	u64 timer = 0;
	u32 RegPll = 0;
	u8 Pll = PllInstancePtr->Pll;

	RegPll |= XAVBUF_ENABLE_BIT << XAVBUF_PLL_CTRL_BYPASS_SHIFT;
	RegPll |= PllInstancePtr->FracIntegerFBDIV <<
		XAVBUF_PLL_CTRL_FBDIV_SHIFT;
	RegPll |= PllInstancePtr->Divider << XAVBUF_PLL_CTRL_DIV2_SHIFT;
	RegPll |= PllInstancePtr->InputRefClk << XAVBUF_PLL_CTRL_PRE_SRC_SHIFT;
	XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) *
		PllInstancePtr->Offset), RegPll);
	RegPll = 0;
	/* Set the values for lock dly, lock counter, capacitor and resistor. */
	RegPll |=
		PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV - 25].cp
		<< XAVBUF_PLL_CFG_CP_SHIFT;
	RegPll |=
		PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV - 25].res
		<< XAVBUF_PLL_CFG_RES_SHIFT;
	RegPll |=
		PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV - 25].lfhf
		<< XAVBUF_PLL_CFG_LFHF_SHIFT;
	RegPll |=
		PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -
		25].lock_dly << XAVBUF_PLL_CFG_LOCK_DLY_SHIFT;
	RegPll |=
		PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -
		25].lock_cnt << XAVBUF_PLL_CFG_LOCK_CNT_SHIFT;
	XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_CFG + (MOD_3(Pll) *
		PllInstancePtr->Offset), RegPll);
	/* Enable and set Fractional Data. */
	XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_FRAC_CFG + (MOD_3(Pll) *
		PllInstancePtr->Offset),
		(1U << XAVBUF_PLL_FRAC_CFG_ENABLED_SHIFT) |
		(PllInstancePtr->Fractional <<
		XAVBUF_PLL_FRAC_CFG_DATA_SHIFT));
	/* Assert reset to the PLL. */
	XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) *
		PllInstancePtr->Offset),
		XAVBUF_PLL_CTRL_RESET_MASK, XAVBUF_PLL_CTRL_RESET_SHIFT,
		XAVBUF_ENABLE_BIT);

	/* Deassert reset to the PLL. */
	XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) *
		PllInstancePtr->Offset),
		XAVBUF_PLL_CTRL_RESET_MASK, XAVBUF_PLL_CTRL_RESET_SHIFT,
		XAVBUF_DISABLE_BIT);

	while (!(XAVBuf_ReadReg(BaseAddress, XAVBUF_PLL_STATUS -
		((1 - PllInstancePtr->Fpd) * XAVBUF_REG_OFFSET)) &
		(1 << MOD_3(Pll))))
		if (++timer > 1000)
			return XST_FAILURE;

	/* Deassert Bypass. */
	XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) *
		PllInstancePtr->Offset),
		XAVBUF_PLL_CTRL_BYPASS_MASK, XAVBUF_PLL_CTRL_BYPASS_SHIFT,
		XAVBUF_DISABLE_BIT);

	if (PllInstancePtr->DomainSwitchDiv != 1)
		XAVBuf_ReadModifyWriteReg(BaseAddress,
		(XAVBUF_DOMAIN_SWITCH_CTRL
		+ (MOD_3(Pll) * XAVBUF_REG_OFFSET) - ((1 - PllInstancePtr->Fpd)
		* XAVBUF_REG_OFFSET)),
		XAVBUF_DOMAIN_SWITCH_DIVISOR0_MASK,
		XAVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT,
		PllInstancePtr->DomainSwitchDiv);
	usleep(1);

	return XST_SUCCESS;

}
/******************************************************************************/
/**
 * This function configures PLL.
 *
 * @param	PllInstancePtr is pointer to the XAVBuf_Pll instance.
 *
 * @return	XST_SUCCESS if PLL is configured without an error.
 *		XST_FAILURE otherwise.
 *
 * @note	None.
 *
*******************************************************************************/
This function configures PLL.
@param       PllInstancePtr is pointer to the XAVBuf_Pll instance.

@return      XST_SUCCESS if PLL is configured without an error.

@note        None.
This function configures PLL . @param PllInstancePtr is pointer to the XAVBuf_Pll instance . @return XST_SUCCESS if PLL is configured without an error . @note None .
static int  XAVBuf_ConfigurePll(XAVBuf_Pll *PllInstancePtr)
{
	u32 BaseAddress = PllInstancePtr->BaseAddress;
	u64 timer = 0;
	u32 RegPll = 0;
	u8 Pll = PllInstancePtr->Pll;
	RegPll |= XAVBUF_ENABLE_BIT << XAVBUF_PLL_CTRL_BYPASS_SHIFT;
	RegPll |= PllInstancePtr->FracIntegerFBDIV <<
		XAVBUF_PLL_CTRL_FBDIV_SHIFT;
	RegPll |= PllInstancePtr->Divider << XAVBUF_PLL_CTRL_DIV2_SHIFT;
	RegPll |= PllInstancePtr->InputRefClk << XAVBUF_PLL_CTRL_PRE_SRC_SHIFT;
	XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) *
		PllInstancePtr->Offset), RegPll);
	RegPll = 0;
	RegPll |=
		PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV - 25].cp
		<< XAVBUF_PLL_CFG_CP_SHIFT;
	RegPll |=
		PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV - 25].res
		<< XAVBUF_PLL_CFG_RES_SHIFT;
	RegPll |=
		PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV - 25].lfhf
		<< XAVBUF_PLL_CFG_LFHF_SHIFT;
	RegPll |=
		PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -
		25].lock_dly << XAVBUF_PLL_CFG_LOCK_DLY_SHIFT;
	RegPll |=
		PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -
		25].lock_cnt << XAVBUF_PLL_CFG_LOCK_CNT_SHIFT;
	XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_CFG + (MOD_3(Pll) *
		PllInstancePtr->Offset), RegPll);
	XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_FRAC_CFG + (MOD_3(Pll) *
		PllInstancePtr->Offset),
		(1U << XAVBUF_PLL_FRAC_CFG_ENABLED_SHIFT) |
		(PllInstancePtr->Fractional <<
		XAVBUF_PLL_FRAC_CFG_DATA_SHIFT));
	XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) *
		PllInstancePtr->Offset),
		XAVBUF_PLL_CTRL_RESET_MASK, XAVBUF_PLL_CTRL_RESET_SHIFT,
		XAVBUF_ENABLE_BIT);
	XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) *
		PllInstancePtr->Offset),
		XAVBUF_PLL_CTRL_RESET_MASK, XAVBUF_PLL_CTRL_RESET_SHIFT,
		XAVBUF_DISABLE_BIT);
	while (!(XAVBuf_ReadReg(BaseAddress, XAVBUF_PLL_STATUS -
		((1 - PllInstancePtr->Fpd) * XAVBUF_REG_OFFSET)) &
		(1 << MOD_3(Pll))))
		if (++timer > 1000)
			return XST_FAILURE;
	XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) *
		PllInstancePtr->Offset),
		XAVBUF_PLL_CTRL_BYPASS_MASK, XAVBUF_PLL_CTRL_BYPASS_SHIFT,
		XAVBUF_DISABLE_BIT);
	if (PllInstancePtr->DomainSwitchDiv != 1)
		XAVBuf_ReadModifyWriteReg(BaseAddress,
		(XAVBUF_DOMAIN_SWITCH_CTRL
		+ (MOD_3(Pll) * XAVBUF_REG_OFFSET) - ((1 - PllInstancePtr->Fpd)
		* XAVBUF_REG_OFFSET)),
		XAVBUF_DOMAIN_SWITCH_DIVISOR0_MASK,
		XAVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT,
		PllInstancePtr->DomainSwitchDiv);
	usleep(1);
	return XST_SUCCESS;
}
static int XAVBuf_ConfigurePll ( XAVBuf_Pll * PllInstancePtr ) { u32 BaseAddress = PllInstancePtr -> BaseAddress ; u64 timer = 0 ; u32 RegPll = 0 ; u8 Pll = PllInstancePtr -> Pll ; RegPll |= XAVBUF_ENABLE_BIT << XAVBUF_PLL_CTRL_BYPASS_SHIFT ; RegPll |= PllInstancePtr -> FracIntegerFBDIV << XAVBUF_PLL_CTRL_FBDIV_SHIFT ; RegPll |= PllInstancePtr -> Divider << XAVBUF_PLL_CTRL_DIV2_SHIFT ; RegPll |= PllInstancePtr -> InputRefClk << XAVBUF_PLL_CTRL_PRE_SRC_SHIFT ; XAVBuf_WriteReg ( BaseAddress , XAVBUF_PLL_CTRL + ( MOD_3 ( Pll ) * PllInstancePtr -> Offset ) , RegPll ) ; RegPll = 0 ; RegPll |= PllFracDivideTable [ PllInstancePtr -> FracIntegerFBDIV - 25 ] . cp << XAVBUF_PLL_CFG_CP_SHIFT ; RegPll |= PllFracDivideTable [ PllInstancePtr -> FracIntegerFBDIV - 25 ] . res << XAVBUF_PLL_CFG_RES_SHIFT ; RegPll |= PllFracDivideTable [ PllInstancePtr -> FracIntegerFBDIV - 25 ] . lfhf << XAVBUF_PLL_CFG_LFHF_SHIFT ; RegPll |= PllFracDivideTable [ PllInstancePtr -> FracIntegerFBDIV - 25 ] . lock_dly << XAVBUF_PLL_CFG_LOCK_DLY_SHIFT ; RegPll |= PllFracDivideTable [ PllInstancePtr -> FracIntegerFBDIV - 25 ] . lock_cnt << XAVBUF_PLL_CFG_LOCK_CNT_SHIFT ; XAVBuf_WriteReg ( BaseAddress , XAVBUF_PLL_CFG + ( MOD_3 ( Pll ) * PllInstancePtr -> Offset ) , RegPll ) ; XAVBuf_WriteReg ( BaseAddress , XAVBUF_PLL_FRAC_CFG + ( MOD_3 ( Pll ) * PllInstancePtr -> Offset ) , ( 1U << XAVBUF_PLL_FRAC_CFG_ENABLED_SHIFT ) | ( PllInstancePtr -> Fractional << XAVBUF_PLL_FRAC_CFG_DATA_SHIFT ) ) ; XAVBuf_ReadModifyWriteReg ( BaseAddress , XAVBUF_PLL_CTRL + ( MOD_3 ( Pll ) * PllInstancePtr -> Offset ) , XAVBUF_PLL_CTRL_RESET_MASK , XAVBUF_PLL_CTRL_RESET_SHIFT , XAVBUF_ENABLE_BIT ) ; XAVBuf_ReadModifyWriteReg ( BaseAddress , XAVBUF_PLL_CTRL + ( MOD_3 ( Pll ) * PllInstancePtr -> Offset ) , XAVBUF_PLL_CTRL_RESET_MASK , XAVBUF_PLL_CTRL_RESET_SHIFT , XAVBUF_DISABLE_BIT ) ; while ( ! ( XAVBuf_ReadReg ( BaseAddress , XAVBUF_PLL_STATUS - ( ( 1 - PllInstancePtr -> Fpd ) * XAVBUF_REG_OFFSET ) ) & ( 1 << MOD_3 ( Pll ) ) ) ) if ( ++ timer > 1000 ) return XST_FAILURE ; XAVBuf_ReadModifyWriteReg ( BaseAddress , XAVBUF_PLL_CTRL + ( MOD_3 ( Pll ) * PllInstancePtr -> Offset ) , XAVBUF_PLL_CTRL_BYPASS_MASK , XAVBUF_PLL_CTRL_BYPASS_SHIFT , XAVBUF_DISABLE_BIT ) ; if ( PllInstancePtr -> DomainSwitchDiv != 1 ) XAVBuf_ReadModifyWriteReg ( BaseAddress , ( XAVBUF_DOMAIN_SWITCH_CTRL + ( MOD_3 ( Pll ) * XAVBUF_REG_OFFSET ) - ( ( 1 - PllInstancePtr -> Fpd ) * XAVBUF_REG_OFFSET ) ) , XAVBUF_DOMAIN_SWITCH_DIVISOR0_MASK , XAVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT , PllInstancePtr -> DomainSwitchDiv ) ; usleep ( 1 ) ; return XST_SUCCESS ; }
This function configures PLL.
This function configures PLL .
/* Set the values for lock dly, lock counter, capacitor and resistor. */ /* Enable and set Fractional Data. */ /* Assert reset to the PLL. */ /* Deassert reset to the PLL. */ /* Deassert Bypass. */