XilinxProcessorIPLib/drivers/v_sditx/src/xv_sditx.c
void XV_SdiTx_StartSdi(XV_SdiTx *InstancePtr, XSdiVid_TransMode SdiMode,
			XSdiVid_BitRate IsFractional,
			XV_SdiTx_MuxPattern MuxPattern)
{
	u32 Data;

	/* Following assertions make sure the IP is configured with in the
	 * subcore GUI paramter limit
	 */
	Xil_AssertVoid(((InstancePtr->Config.MaxRateSupported == XSDITX_LINE_RATE_3G) &&
			(SdiMode <= XSDIVID_MODE_3GB)) ||
			((InstancePtr->Config.MaxRateSupported == XSDITX_LINE_RATE_6G) &&
			(SdiMode <= XSDIVID_MODE_6G)) ||
			((InstancePtr->Config.MaxRateSupported == XSDITX_LINE_RATE_12G8DS) &&
			(SdiMode <= XSDIVID_MODE_12G)));

	InstancePtr->IsStreamUp = TRUE;

	Data = XV_SdiTx_ReadReg(InstancePtr->Config.BaseAddress,
				(XV_SDITX_MDL_CTRL_OFFSET));
	Data &= ~(XV_SDITX_MDL_CTRL_MODE_MASK
		| XV_SDITX_MDL_CTRL_M_MASK
		| XV_SDITX_MDL_CTRL_MUX_PATTERN_MASK);



	/* Enable HFR, if frame rate is above 96 */
	if (InstancePtr->Stream[0].Video.FrameRate >= XVIDC_FR_96HZ &&
			InstancePtr->Stream[0].Video.FrameRate <= XVIDC_FR_240HZ) {
		Data |= XV_SDITX_MDL_CTRL_ENABLE_HFR;
		if (SdiMode == XSDIVID_MODE_6G)
			MuxPattern = 0x3;
	}

	Data |= (((SdiMode & 0x7) << XV_SDITX_MDL_CTRL_MODE_SHIFT) |
		((IsFractional & 0x1) << XV_SDITX_MDL_CTRL_M_SHIFT) |
		((MuxPattern & 0x7) << XV_SDITX_MDL_CTRL_MUX_PATTERN_SHIFT));

	XV_SdiTx_WriteReg((InstancePtr)->Config.BaseAddress,
				(XV_SDITX_MDL_CTRL_OFFSET), (Data));

	Data = XV_SdiTx_ReadReg(InstancePtr->Config.BaseAddress,
				(XV_SDITX_RST_CTRL_OFFSET));

	Data |= XV_SDITX_RST_CTRL_SDITX_SS_EN_MASK;

	XV_SdiTx_WriteReg((InstancePtr)->Config.BaseAddress,
				(XV_SDITX_RST_CTRL_OFFSET), (Data));

	/* Clear detected error */
	XV_SdiTx_ClearDetectedError(InstancePtr);
}
/*****************************************************************************/
/**
*
* This function starts the SDI TX core.
*
* @param    InstancePtr is a pointer to the XV_SdiTx core instance.
* @param    SdiMode specifies the SDI mode of the SDI TX.
* @param    IsFractional specifies the bitrate of the SDI TX.
* @param    MuxPattern specifies the data stream interleaving pattern to be
*			used.
*
* @return   None.
*
* @note     None.
*
******************************************************************************/
This function starts the SDI TX core.
This function starts the SDI TX core .
void XV_SdiTx_StartSdi(XV_SdiTx *InstancePtr, XSdiVid_TransMode SdiMode,
			XSdiVid_BitRate IsFractional,
			XV_SdiTx_MuxPattern MuxPattern)
{
	u32 Data;
	Xil_AssertVoid(((InstancePtr->Config.MaxRateSupported == XSDITX_LINE_RATE_3G) &&
			(SdiMode <= XSDIVID_MODE_3GB)) ||
			((InstancePtr->Config.MaxRateSupported == XSDITX_LINE_RATE_6G) &&
			(SdiMode <= XSDIVID_MODE_6G)) ||
			((InstancePtr->Config.MaxRateSupported == XSDITX_LINE_RATE_12G8DS) &&
			(SdiMode <= XSDIVID_MODE_12G)));
	InstancePtr->IsStreamUp = TRUE;
	Data = XV_SdiTx_ReadReg(InstancePtr->Config.BaseAddress,
				(XV_SDITX_MDL_CTRL_OFFSET));
	Data &= ~(XV_SDITX_MDL_CTRL_MODE_MASK
		| XV_SDITX_MDL_CTRL_M_MASK
		| XV_SDITX_MDL_CTRL_MUX_PATTERN_MASK);
	if (InstancePtr->Stream[0].Video.FrameRate >= XVIDC_FR_96HZ &&
			InstancePtr->Stream[0].Video.FrameRate <= XVIDC_FR_240HZ) {
		Data |= XV_SDITX_MDL_CTRL_ENABLE_HFR;
		if (SdiMode == XSDIVID_MODE_6G)
			MuxPattern = 0x3;
	}
	Data |= (((SdiMode & 0x7) << XV_SDITX_MDL_CTRL_MODE_SHIFT) |
		((IsFractional & 0x1) << XV_SDITX_MDL_CTRL_M_SHIFT) |
		((MuxPattern & 0x7) << XV_SDITX_MDL_CTRL_MUX_PATTERN_SHIFT));
	XV_SdiTx_WriteReg((InstancePtr)->Config.BaseAddress,
				(XV_SDITX_MDL_CTRL_OFFSET), (Data));
	Data = XV_SdiTx_ReadReg(InstancePtr->Config.BaseAddress,
				(XV_SDITX_RST_CTRL_OFFSET));
	Data |= XV_SDITX_RST_CTRL_SDITX_SS_EN_MASK;
	XV_SdiTx_WriteReg((InstancePtr)->Config.BaseAddress,
				(XV_SDITX_RST_CTRL_OFFSET), (Data));
	XV_SdiTx_ClearDetectedError(InstancePtr);
}
void XV_SdiTx_StartSdi ( XV_SdiTx * InstancePtr , XSdiVid_TransMode SdiMode , XSdiVid_BitRate IsFractional , XV_SdiTx_MuxPattern MuxPattern ) { u32 Data ; Xil_AssertVoid ( ( ( InstancePtr -> Config . MaxRateSupported == XSDITX_LINE_RATE_3G ) && ( SdiMode <= XSDIVID_MODE_3GB ) ) || ( ( InstancePtr -> Config . MaxRateSupported == XSDITX_LINE_RATE_6G ) && ( SdiMode <= XSDIVID_MODE_6G ) ) || ( ( InstancePtr -> Config . MaxRateSupported == XSDITX_LINE_RATE_12G8DS ) && ( SdiMode <= XSDIVID_MODE_12G ) ) ) ; InstancePtr -> IsStreamUp = TRUE ; Data = XV_SdiTx_ReadReg ( InstancePtr -> Config . BaseAddress , ( XV_SDITX_MDL_CTRL_OFFSET ) ) ; Data &= ~ ( XV_SDITX_MDL_CTRL_MODE_MASK | XV_SDITX_MDL_CTRL_M_MASK | XV_SDITX_MDL_CTRL_MUX_PATTERN_MASK ) ; if ( InstancePtr -> Stream [ 0 ] . Video . FrameRate >= XVIDC_FR_96HZ && InstancePtr -> Stream [ 0 ] . Video . FrameRate <= XVIDC_FR_240HZ ) { Data |= XV_SDITX_MDL_CTRL_ENABLE_HFR ; if ( SdiMode == XSDIVID_MODE_6G ) MuxPattern = 0x3 ; } Data |= ( ( ( SdiMode & 0x7 ) << XV_SDITX_MDL_CTRL_MODE_SHIFT ) | ( ( IsFractional & 0x1 ) << XV_SDITX_MDL_CTRL_M_SHIFT ) | ( ( MuxPattern & 0x7 ) << XV_SDITX_MDL_CTRL_MUX_PATTERN_SHIFT ) ) ; XV_SdiTx_WriteReg ( ( InstancePtr ) -> Config . BaseAddress , ( XV_SDITX_MDL_CTRL_OFFSET ) , ( Data ) ) ; Data = XV_SdiTx_ReadReg ( InstancePtr -> Config . BaseAddress , ( XV_SDITX_RST_CTRL_OFFSET ) ) ; Data |= XV_SDITX_RST_CTRL_SDITX_SS_EN_MASK ; XV_SdiTx_WriteReg ( ( InstancePtr ) -> Config . BaseAddress , ( XV_SDITX_RST_CTRL_OFFSET ) , ( Data ) ) ; XV_SdiTx_ClearDetectedError ( InstancePtr ) ; }
This function starts the SDI TX core.
This function starts the SDI TX core .
/* Following assertions make sure the IP is configured with in the
	 * subcore GUI paramter limit
	 */ /* Enable HFR, if frame rate is above 96 */ /* Clear detected error */