src/dpdk/drivers/net/ixgbe/ixgbe_ethdev.c
static void
ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
		   uint8_t queue, uint8_t msix_vector)
{
	uint32_t tmp, idx;

	msix_vector |= IXGBE_IVAR_ALLOC_VAL;
	if (hw->mac.type == ixgbe_mac_82598EB) {
		if (direction == -1)
			direction = 0;
		idx = (((direction * 64) + queue) >> 2) & 0x1F;
		tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
		tmp &= ~(0xFF << (8 * (queue & 0x3)));
		tmp |= (msix_vector << (8 * (queue & 0x3)));
		IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
	} else if ((hw->mac.type == ixgbe_mac_82599EB) ||
			(hw->mac.type == ixgbe_mac_X540) ||
			(hw->mac.type == ixgbe_mac_X550) ||
			(hw->mac.type == ixgbe_mac_X550EM_x)) {
		if (direction == -1) {
			/* other causes */
			idx = ((queue & 1) * 8);
			tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
			tmp &= ~(0xFF << idx);
			tmp |= (msix_vector << idx);
			IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
		} else {
			/* rx or tx causes */
			idx = ((16 * (queue & 1)) + (8 * direction));
			tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
			tmp &= ~(0xFF << idx);
			tmp |= (msix_vector << idx);
			IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
		}
	}
}
/**
 * set the IVAR registers, mapping interrupt causes to vectors
 * @param hw
 *  pointer to ixgbe_hw struct
 * @direction
 *  0 for Rx, 1 for Tx, -1 for other causes
 * @queue
 *  queue to map the corresponding interrupt to
 * @msix_vector
 *  the vector to map to the corresponding queue
 */
set the IVAR registers, mapping interrupt causes to vectors
@param hw
pointer to ixgbe_hw struct
@direction
0 for Rx, 1 for Tx, -1 for other causes
@queue
queue to map the corresponding interrupt to
@msix_vector
the vector to map to the corresponding queue
set the IVAR registers mapping interrupt causes to vectors @param hw pointer to ixgbe_hw struct @direction 0 for Rx 1 for Tx - 1 for other causes @queue queue to map the corresponding interrupt to @msix_vector the vector to map to the corresponding queue
static void
ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
		   uint8_t queue, uint8_t msix_vector)
{
	uint32_t tmp, idx;
	msix_vector |= IXGBE_IVAR_ALLOC_VAL;
	if (hw->mac.type == ixgbe_mac_82598EB) {
		if (direction == -1)
			direction = 0;
		idx = (((direction * 64) + queue) >> 2) & 0x1F;
		tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
		tmp &= ~(0xFF << (8 * (queue & 0x3)));
		tmp |= (msix_vector << (8 * (queue & 0x3)));
		IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
	} else if ((hw->mac.type == ixgbe_mac_82599EB) ||
			(hw->mac.type == ixgbe_mac_X540) ||
			(hw->mac.type == ixgbe_mac_X550) ||
			(hw->mac.type == ixgbe_mac_X550EM_x)) {
		if (direction == -1) {
			idx = ((queue & 1) * 8);
			tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
			tmp &= ~(0xFF << idx);
			tmp |= (msix_vector << idx);
			IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
		} else {
			idx = ((16 * (queue & 1)) + (8 * direction));
			tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
			tmp &= ~(0xFF << idx);
			tmp |= (msix_vector << idx);
			IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
		}
	}
}
static void ixgbe_set_ivar_map ( struct ixgbe_hw * hw , int8_t direction , uint8_t queue , uint8_t msix_vector ) { uint32_t tmp , idx ; msix_vector |= IXGBE_IVAR_ALLOC_VAL ; if ( hw -> mac . type == ixgbe_mac_82598EB ) { if ( direction == -1 ) direction = 0 ; idx = ( ( ( direction * 64 ) + queue ) >> 2 ) & 0x1F ; tmp = IXGBE_READ_REG ( hw , IXGBE_IVAR ( idx ) ) ; tmp &= ~ ( 0xFF << ( 8 * ( queue & 0x3 ) ) ) ; tmp |= ( msix_vector << ( 8 * ( queue & 0x3 ) ) ) ; IXGBE_WRITE_REG ( hw , IXGBE_IVAR ( idx ) , tmp ) ; } else if ( ( hw -> mac . type == ixgbe_mac_82599EB ) || ( hw -> mac . type == ixgbe_mac_X540 ) || ( hw -> mac . type == ixgbe_mac_X550 ) || ( hw -> mac . type == ixgbe_mac_X550EM_x ) ) { if ( direction == -1 ) { idx = ( ( queue & 1 ) * 8 ) ; tmp = IXGBE_READ_REG ( hw , IXGBE_IVAR_MISC ) ; tmp &= ~ ( 0xFF << idx ) ; tmp |= ( msix_vector << idx ) ; IXGBE_WRITE_REG ( hw , IXGBE_IVAR_MISC , tmp ) ; } else { idx = ( ( 16 * ( queue & 1 ) ) + ( 8 * direction ) ) ; tmp = IXGBE_READ_REG ( hw , IXGBE_IVAR ( queue >> 1 ) ) ; tmp &= ~ ( 0xFF << idx ) ; tmp |= ( msix_vector << idx ) ; IXGBE_WRITE_REG ( hw , IXGBE_IVAR ( queue >> 1 ) , tmp ) ; } } }
set the IVAR registers, mapping interrupt causes to vectors
 @param hw
  pointer to ixgbe_hw struct
 @direction
  0 for Rx, 1 for Tx, -1 for other causes
 @queue
  queue to map the corresponding interrupt to
 @msix_vector
  the vector to map to the corresponding queue
set the IVAR registers mapping interrupt causes to vectors @param hw pointer to ixgbe_hw struct @direction 0 for Rx 1 for Tx - 1 for other causes @queue queue to map the corresponding interrupt to @msix_vector the vector to map to the corresponding queue
/* other causes */ /* rx or tx causes */