XilinxProcessorIPLib/drivers/dp14rxss/examples/src/rx_only/xdprxss_dp14_rx.c
void PLLRefClkSel (XVphy *InstancePtr, u8 link_rate) {
	switch (link_rate) {
	case 0x6:
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, ONBOARD_REF_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, DP159_FORWARDED_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				  XVPHY_DP_LINK_RATE_HZ_162GBPS);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CMN1,
				  XVPHY_DP_LINK_RATE_HZ_162GBPS);
		break;
	case 0x14:
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, ONBOARD_REF_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, DP159_FORWARDED_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				  XVPHY_DP_LINK_RATE_HZ_540GBPS);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CMN1,
				  XVPHY_DP_LINK_RATE_HZ_540GBPS);
		break;
	case 0x1E:
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, ONBOARD_REF_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, DP159_FORWARDED_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				  XVPHY_DP_LINK_RATE_HZ_810GBPS);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CMN1,
				  XVPHY_DP_LINK_RATE_HZ_810GBPS);
		break;
	default:
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, ONBOARD_REF_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0,
//					DP159_FORWARDED_CLK, XVPHY_DP_REF_CLK_FREQ_HZ_135);
					DP159_FORWARDED_CLK, XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				  XVPHY_DP_LINK_RATE_HZ_270GBPS);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CMN1,
				  XVPHY_DP_LINK_RATE_HZ_270GBPS);
		break;
	}
}
/*****************************************************************************/
/**
*
* This function sets proper ref clk frequency and line rate
*
* @param    InstancePtr is a pointer to the Video PHY instance.
*
* @return    None.
*
* @note        None.
*
******************************************************************************/
This function sets proper ref clk frequency and line rate
This function sets proper ref clk frequency and line rate
void PLLRefClkSel (XVphy *InstancePtr, u8 link_rate) {
	switch (link_rate) {
	case 0x6:
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, ONBOARD_REF_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, DP159_FORWARDED_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				  XVPHY_DP_LINK_RATE_HZ_162GBPS);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CMN1,
				  XVPHY_DP_LINK_RATE_HZ_162GBPS);
		break;
	case 0x14:
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, ONBOARD_REF_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, DP159_FORWARDED_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				  XVPHY_DP_LINK_RATE_HZ_540GBPS);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CMN1,
				  XVPHY_DP_LINK_RATE_HZ_540GBPS);
		break;
	case 0x1E:
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, ONBOARD_REF_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, DP159_FORWARDED_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				  XVPHY_DP_LINK_RATE_HZ_810GBPS);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CMN1,
				  XVPHY_DP_LINK_RATE_HZ_810GBPS);
		break;
	default:
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0, ONBOARD_REF_CLK,
					XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgQuadRefClkFreq(InstancePtr, 0,
					DP159_FORWARDED_CLK, XVPHY_DP_REF_CLK_FREQ_HZ_270);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				  XVPHY_DP_LINK_RATE_HZ_270GBPS);
		XVphy_CfgLineRate(InstancePtr, 0, XVPHY_CHANNEL_ID_CMN1,
				  XVPHY_DP_LINK_RATE_HZ_270GBPS);
		break;
	}
}
void PLLRefClkSel ( XVphy * InstancePtr , u8 link_rate ) { switch ( link_rate ) { case 0x6 : XVphy_CfgQuadRefClkFreq ( InstancePtr , 0 , ONBOARD_REF_CLK , XVPHY_DP_REF_CLK_FREQ_HZ_270 ) ; XVphy_CfgQuadRefClkFreq ( InstancePtr , 0 , DP159_FORWARDED_CLK , XVPHY_DP_REF_CLK_FREQ_HZ_270 ) ; XVphy_CfgLineRate ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DP_LINK_RATE_HZ_162GBPS ) ; XVphy_CfgLineRate ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CMN1 , XVPHY_DP_LINK_RATE_HZ_162GBPS ) ; break ; case 0x14 : XVphy_CfgQuadRefClkFreq ( InstancePtr , 0 , ONBOARD_REF_CLK , XVPHY_DP_REF_CLK_FREQ_HZ_270 ) ; XVphy_CfgQuadRefClkFreq ( InstancePtr , 0 , DP159_FORWARDED_CLK , XVPHY_DP_REF_CLK_FREQ_HZ_270 ) ; XVphy_CfgLineRate ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DP_LINK_RATE_HZ_540GBPS ) ; XVphy_CfgLineRate ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CMN1 , XVPHY_DP_LINK_RATE_HZ_540GBPS ) ; break ; case 0x1E : XVphy_CfgQuadRefClkFreq ( InstancePtr , 0 , ONBOARD_REF_CLK , XVPHY_DP_REF_CLK_FREQ_HZ_270 ) ; XVphy_CfgQuadRefClkFreq ( InstancePtr , 0 , DP159_FORWARDED_CLK , XVPHY_DP_REF_CLK_FREQ_HZ_270 ) ; XVphy_CfgLineRate ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DP_LINK_RATE_HZ_810GBPS ) ; XVphy_CfgLineRate ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CMN1 , XVPHY_DP_LINK_RATE_HZ_810GBPS ) ; break ; default : XVphy_CfgQuadRefClkFreq ( InstancePtr , 0 , ONBOARD_REF_CLK , XVPHY_DP_REF_CLK_FREQ_HZ_270 ) ; XVphy_CfgQuadRefClkFreq ( InstancePtr , 0 , DP159_FORWARDED_CLK , XVPHY_DP_REF_CLK_FREQ_HZ_270 ) ; XVphy_CfgLineRate ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DP_LINK_RATE_HZ_270GBPS ) ; XVphy_CfgLineRate ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CMN1 , XVPHY_DP_LINK_RATE_HZ_270GBPS ) ; break ; } }
This function sets proper ref clk frequency and line rate
This function sets proper ref clk frequency and line rate
//					DP159_FORWARDED_CLK, XVPHY_DP_REF_CLK_FREQ_HZ_135);