AllJoyn/Samples/BACnetAdapter/bacnet-stack-0.8.2/ports/xplained/ASF/xmega/drivers/twi/twim.c
status_code_t twi_master_transfer(TWI_t * twi,
    const twi_package_t * package,
    bool read)
{
    /* Do a sanity check on the arguments. */

    if ((twi == NULL) || (package == NULL)) {
        return ERR_INVALID_ARG;
    }

    /* Initiate a transaction when the bus is ready. */

    status_code_t status = twim_acquire(package->no_wait);

    if (STATUS_OK == status) {
        transfer.bus = (TWI_t *) twi;
        transfer.pkg = (twi_package_t *) package;
        transfer.addr_count = 0;
        transfer.data_count = 0;
        transfer.read = read;

        uint8_t const chip = (package->chip) << 1;

        if (package->addr_length || (false == read)) {
            transfer.bus->MASTER.ADDR = chip;
        } else if (read) {
            transfer.bus->MASTER.ADDR = chip | 0x01;
        }

        status = twim_release();
    }

    return status;
}
/**
 * \brief Perform a TWI master write or read transfer.
 *
 * This function is a TWI Master write or read transaction.
 *
 * \param twi       Base address of the TWI (i.e. &TWI_t).
 * \param package   Package information and data
 *                  (see \ref twi_package_t)
 * \param read      Selects the transfer direction
 *
 * \return  status_code_t
 *      - STATUS_OK if the transfer completes
 *      - ERR_BUSY to indicate an unavailable bus
 *      - ERR_IO_ERROR to indicate a bus transaction error
 *      - ERR_NO_MEMORY to indicate buffer errors
 *      - ERR_PROTOCOL to indicate an unexpected bus state
 *      - ERR_INVALID_ARG to indicate invalid arguments.
 */
\brief Perform a TWI master write or read transfer.
This function is a TWI Master write or read transaction.

\param twi       Base address of the TWI .
\param package   Package information and data

\param read      Selects the transfer direction


\ brief Perform a TWI master write or read transfer . This function is a TWI Master write or read transaction . \ param twi Base address of the TWI . \ param package Package information and data \ param read Selects the transfer direction
status_code_t twi_master_transfer(TWI_t * twi,
    const twi_package_t * package,
    bool read)
{
    if ((twi == NULL) || (package == NULL)) {
        return ERR_INVALID_ARG;
    }
    status_code_t status = twim_acquire(package->no_wait);
    if (STATUS_OK == status) {
        transfer.bus = (TWI_t *) twi;
        transfer.pkg = (twi_package_t *) package;
        transfer.addr_count = 0;
        transfer.data_count = 0;
        transfer.read = read;
        uint8_t const chip = (package->chip) << 1;
        if (package->addr_length || (false == read)) {
            transfer.bus->MASTER.ADDR = chip;
        } else if (read) {
            transfer.bus->MASTER.ADDR = chip | 0x01;
        }
        status = twim_release();
    }
    return status;
}
status_code_t twi_master_transfer ( TWI_t * twi , const twi_package_t * package , bool read ) { if ( ( twi == NULL ) || ( package == NULL ) ) { return ERR_INVALID_ARG ; } status_code_t status = twim_acquire ( package -> no_wait ) ; if ( STATUS_OK == status ) { transfer . bus = ( TWI_t * ) twi ; transfer . pkg = ( twi_package_t * ) package ; transfer . addr_count = 0 ; transfer . data_count = 0 ; transfer . read = read ; uint8_t const chip = ( package -> chip ) << 1 ; if ( package -> addr_length || ( false == read ) ) { transfer . bus -> MASTER . ADDR = chip ; } else if ( read ) { transfer . bus -> MASTER . ADDR = chip | 0x01 ; } status = twim_release ( ) ; } return status ; }
\brief Perform a TWI master write or read transfer.
\ brief Perform a TWI master write or read transfer .
/* Do a sanity check on the arguments. */ /* Initiate a transaction when the bus is ready. */