src/dpdk/drivers/net/mlx5/mlx5_txq.c
static int
txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)
{
	struct mlx5_priv *priv = txq_ctrl->priv;
	struct mlx5_dev_config *config = &priv->config;
	unsigned int max_inline;

	max_inline = txq_calc_inline_max(txq_ctrl);
	if (!txq_ctrl->txq.inlen_send) {
		/*
		 * Inline data feature is not engaged at all.
		 * There is nothing to adjust.
		 */
		return 0;
	}
	if (txq_ctrl->max_inline_data <= max_inline) {
		/*
		 * The requested inline data length does not
		 * exceed queue capabilities.
		 */
		return 0;
	}
	if (txq_ctrl->txq.inlen_mode > max_inline) {
		DRV_LOG(ERR,
			"minimal data inline requirements (%u) are not"
			" satisfied (%u) on port %u, try the smaller"
			" Tx queue size (%d)",
			txq_ctrl->txq.inlen_mode, max_inline,
			priv->dev_data->port_id,
			priv->sh->device_attr.max_qp_wr);
		goto error;
	}
	if (txq_ctrl->txq.inlen_send > max_inline &&
	    config->txq_inline_max != MLX5_ARG_UNSET &&
	    config->txq_inline_max > (int)max_inline) {
		DRV_LOG(ERR,
			"txq_inline_max requirements (%u) are not"
			" satisfied (%u) on port %u, try the smaller"
			" Tx queue size (%d)",
			txq_ctrl->txq.inlen_send, max_inline,
			priv->dev_data->port_id,
			priv->sh->device_attr.max_qp_wr);
		goto error;
	}
	if (txq_ctrl->txq.inlen_empw > max_inline &&
	    config->txq_inline_mpw != MLX5_ARG_UNSET &&
	    config->txq_inline_mpw > (int)max_inline) {
		DRV_LOG(ERR,
			"txq_inline_mpw requirements (%u) are not"
			" satisfied (%u) on port %u, try the smaller"
			" Tx queue size (%d)",
			txq_ctrl->txq.inlen_empw, max_inline,
			priv->dev_data->port_id,
			priv->sh->device_attr.max_qp_wr);
		goto error;
	}
	if (txq_ctrl->txq.tso_en && max_inline < MLX5_MAX_TSO_HEADER) {
		DRV_LOG(ERR,
			"tso header inline requirements (%u) are not"
			" satisfied (%u) on port %u, try the smaller"
			" Tx queue size (%d)",
			MLX5_MAX_TSO_HEADER, max_inline,
			priv->dev_data->port_id,
			priv->sh->device_attr.max_qp_wr);
		goto error;
	}
	if (txq_ctrl->txq.inlen_send > max_inline) {
		DRV_LOG(WARNING,
			"adjust txq_inline_max (%u->%u)"
			" due to large Tx queue on port %u",
			txq_ctrl->txq.inlen_send, max_inline,
			priv->dev_data->port_id);
		txq_ctrl->txq.inlen_send = max_inline;
	}
	if (txq_ctrl->txq.inlen_empw > max_inline) {
		DRV_LOG(WARNING,
			"adjust txq_inline_mpw (%u->%u)"
			"due to large Tx queue on port %u",
			txq_ctrl->txq.inlen_empw, max_inline,
			priv->dev_data->port_id);
		txq_ctrl->txq.inlen_empw = max_inline;
	}
	txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->txq.inlen_send,
					    txq_ctrl->txq.inlen_empw);
	MLX5_ASSERT(txq_ctrl->max_inline_data <= max_inline);
	MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= max_inline);
	MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send);
	MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw ||
		    !txq_ctrl->txq.inlen_empw);
	return 0;
error:
	rte_errno = ENOMEM;
	return -ENOMEM;
}
/**
 * Adjust Tx queue data inline parameters for large queue sizes.
 * The data inline feature requires multiple WQEs to fit the packets,
 * and if the large amount of Tx descriptors is requested by application
 * the total WQE amount may exceed the hardware capabilities. If the
 * default inline setting are used we can try to adjust these ones and
 * meet the hardware requirements and not exceed the queue size.
 *
 * @param txq_ctrl
 *   Pointer to Tx queue control structure.
 *
 * @return
 *   Zero on success, otherwise the parameters can not be adjusted.
 */
Adjust Tx queue data inline parameters for large queue sizes.
The data inline feature requires multiple WQEs to fit the packets,
and if the large amount of Tx descriptors is requested by application
the total WQE amount may exceed the hardware capabilities. If the
default inline setting are used we can try to adjust these ones and
meet the hardware requirements and not exceed the queue size.

@param txq_ctrl
Pointer to Tx queue control structure.

@return
Zero on success, otherwise the parameters can not be adjusted.
Adjust Tx queue data inline parameters for large queue sizes . The data inline feature requires multiple WQEs to fit the packets and if the large amount of Tx descriptors is requested by application the total WQE amount may exceed the hardware capabilities . If the default inline setting are used we can try to adjust these ones and meet the hardware requirements and not exceed the queue size . @param txq_ctrl Pointer to Tx queue control structure . @return Zero on success otherwise the parameters can not be adjusted .
static int
txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)
{
	struct mlx5_priv *priv = txq_ctrl->priv;
	struct mlx5_dev_config *config = &priv->config;
	unsigned int max_inline;
	max_inline = txq_calc_inline_max(txq_ctrl);
	if (!txq_ctrl->txq.inlen_send) {
		return 0;
	}
	if (txq_ctrl->max_inline_data <= max_inline) {
		return 0;
	}
	if (txq_ctrl->txq.inlen_mode > max_inline) {
		DRV_LOG(ERR,
			"minimal data inline requirements (%u) are not"
			" satisfied (%u) on port %u, try the smaller"
			" Tx queue size (%d)",
			txq_ctrl->txq.inlen_mode, max_inline,
			priv->dev_data->port_id,
			priv->sh->device_attr.max_qp_wr);
		goto error;
	}
	if (txq_ctrl->txq.inlen_send > max_inline &&
	    config->txq_inline_max != MLX5_ARG_UNSET &&
	    config->txq_inline_max > (int)max_inline) {
		DRV_LOG(ERR,
			"txq_inline_max requirements (%u) are not"
			" satisfied (%u) on port %u, try the smaller"
			" Tx queue size (%d)",
			txq_ctrl->txq.inlen_send, max_inline,
			priv->dev_data->port_id,
			priv->sh->device_attr.max_qp_wr);
		goto error;
	}
	if (txq_ctrl->txq.inlen_empw > max_inline &&
	    config->txq_inline_mpw != MLX5_ARG_UNSET &&
	    config->txq_inline_mpw > (int)max_inline) {
		DRV_LOG(ERR,
			"txq_inline_mpw requirements (%u) are not"
			" satisfied (%u) on port %u, try the smaller"
			" Tx queue size (%d)",
			txq_ctrl->txq.inlen_empw, max_inline,
			priv->dev_data->port_id,
			priv->sh->device_attr.max_qp_wr);
		goto error;
	}
	if (txq_ctrl->txq.tso_en && max_inline < MLX5_MAX_TSO_HEADER) {
		DRV_LOG(ERR,
			"tso header inline requirements (%u) are not"
			" satisfied (%u) on port %u, try the smaller"
			" Tx queue size (%d)",
			MLX5_MAX_TSO_HEADER, max_inline,
			priv->dev_data->port_id,
			priv->sh->device_attr.max_qp_wr);
		goto error;
	}
	if (txq_ctrl->txq.inlen_send > max_inline) {
		DRV_LOG(WARNING,
			"adjust txq_inline_max (%u->%u)"
			" due to large Tx queue on port %u",
			txq_ctrl->txq.inlen_send, max_inline,
			priv->dev_data->port_id);
		txq_ctrl->txq.inlen_send = max_inline;
	}
	if (txq_ctrl->txq.inlen_empw > max_inline) {
		DRV_LOG(WARNING,
			"adjust txq_inline_mpw (%u->%u)"
			"due to large Tx queue on port %u",
			txq_ctrl->txq.inlen_empw, max_inline,
			priv->dev_data->port_id);
		txq_ctrl->txq.inlen_empw = max_inline;
	}
	txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->txq.inlen_send,
					    txq_ctrl->txq.inlen_empw);
	MLX5_ASSERT(txq_ctrl->max_inline_data <= max_inline);
	MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= max_inline);
	MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send);
	MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw ||
		    !txq_ctrl->txq.inlen_empw);
	return 0;
error:
	rte_errno = ENOMEM;
	return -ENOMEM;
}
static int txq_adjust_params ( struct mlx5_txq_ctrl * txq_ctrl ) { struct mlx5_priv * priv = txq_ctrl -> priv ; struct mlx5_dev_config * config = & priv -> config ; unsigned int max_inline ; max_inline = txq_calc_inline_max ( txq_ctrl ) ; if ( ! txq_ctrl -> txq . inlen_send ) { return 0 ; } if ( txq_ctrl -> max_inline_data <= max_inline ) { return 0 ; } if ( txq_ctrl -> txq . inlen_mode > max_inline ) { DRV_LOG ( ERR , " " " " " " , txq_ctrl -> txq . inlen_mode , max_inline , priv -> dev_data -> port_id , priv -> sh -> device_attr . max_qp_wr ) ; goto error ; } if ( txq_ctrl -> txq . inlen_send > max_inline && config -> txq_inline_max != MLX5_ARG_UNSET && config -> txq_inline_max > ( int ) max_inline ) { DRV_LOG ( ERR , " " " " " " , txq_ctrl -> txq . inlen_send , max_inline , priv -> dev_data -> port_id , priv -> sh -> device_attr . max_qp_wr ) ; goto error ; } if ( txq_ctrl -> txq . inlen_empw > max_inline && config -> txq_inline_mpw != MLX5_ARG_UNSET && config -> txq_inline_mpw > ( int ) max_inline ) { DRV_LOG ( ERR , " " " " " " , txq_ctrl -> txq . inlen_empw , max_inline , priv -> dev_data -> port_id , priv -> sh -> device_attr . max_qp_wr ) ; goto error ; } if ( txq_ctrl -> txq . tso_en && max_inline < MLX5_MAX_TSO_HEADER ) { DRV_LOG ( ERR , " " " " " " , MLX5_MAX_TSO_HEADER , max_inline , priv -> dev_data -> port_id , priv -> sh -> device_attr . max_qp_wr ) ; goto error ; } if ( txq_ctrl -> txq . inlen_send > max_inline ) { DRV_LOG ( WARNING , " " " " , txq_ctrl -> txq . inlen_send , max_inline , priv -> dev_data -> port_id ) ; txq_ctrl -> txq . inlen_send = max_inline ; } if ( txq_ctrl -> txq . inlen_empw > max_inline ) { DRV_LOG ( WARNING , " " " " , txq_ctrl -> txq . inlen_empw , max_inline , priv -> dev_data -> port_id ) ; txq_ctrl -> txq . inlen_empw = max_inline ; } txq_ctrl -> max_inline_data = RTE_MAX ( txq_ctrl -> txq . inlen_send , txq_ctrl -> txq . inlen_empw ) ; MLX5_ASSERT ( txq_ctrl -> max_inline_data <= max_inline ) ; MLX5_ASSERT ( txq_ctrl -> txq . inlen_mode <= max_inline ) ; MLX5_ASSERT ( txq_ctrl -> txq . inlen_mode <= txq_ctrl -> txq . inlen_send ) ; MLX5_ASSERT ( txq_ctrl -> txq . inlen_mode <= txq_ctrl -> txq . inlen_empw || ! txq_ctrl -> txq . inlen_empw ) ; return 0 ; error : rte_errno = ENOMEM ; return - ENOMEM ; }
Adjust Tx queue data inline parameters for large queue sizes.
Adjust Tx queue data inline parameters for large queue sizes .
/*
		 * Inline data feature is not engaged at all.
		 * There is nothing to adjust.
		 */ /*
		 * The requested inline data length does not
		 * exceed queue capabilities.
		 */