target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl931x.c
int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
{
	int err = 0;
	u32 v;
	/* Select PHY register type
	 * If select 1G/10G MMD register type, registers EXT_PAGE, MAIN_PAGE and REG settings are don’t care.
	 * 0x0  Normal register (Clause 22)
	 * 0x1: 1G MMD register (MMD via Clause 22 registers 13 and 14)
	 * 0x2: 10G MMD register (MMD via Clause 45)
	 */
	int type = (regnum & MII_ADDR_C45)?2:1;

	mutex_lock(&smi_lock);

	// Set PHY to access via port-number
	sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL);

	// Set MMD device number and register to write to
	sw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);

	v = type << 2 | BIT(0); // MMD-access-type | EXEC
	sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);

	do {
		v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
	} while (v & BIT(0));

	// Check for error condition
	if (v & BIT(1))
		err = -EIO;

	*val = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3) >> 16;

	pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__,
		 port, devnum, mdiobus_c45_regad(regnum), *val, err);

	mutex_unlock(&smi_lock);

	return err;
}
/*
 * Read an mmd register of the PHY
 */
Read an mmd register of the PHY
Read an mmd register of the PHY
int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
{
	int err = 0;
	u32 v;
	int type = (regnum & MII_ADDR_C45)?2:1;
	mutex_lock(&smi_lock);
	sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL);
	sw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);
	v = type << 2 | BIT(0); 
	sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
	do {
		v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
	} while (v & BIT(0));
	if (v & BIT(1))
		err = -EIO;
	*val = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3) >> 16;
	pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__,
		 port, devnum, mdiobus_c45_regad(regnum), *val, err);
	mutex_unlock(&smi_lock);
	return err;
}
int rtl931x_read_mmd_phy ( u32 port , u32 devnum , u32 regnum , u32 * val ) { int err = 0 ; u32 v ; int type = ( regnum & MII_ADDR_C45 ) ? 2 : 1 ; mutex_lock ( & smi_lock ) ; sw_w32 ( port << 5 , RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL ) ; sw_w32 ( devnum << 16 | mdiobus_c45_regad ( regnum ) , RTL931X_SMI_INDRT_ACCESS_MMD_CTRL ) ; v = type << 2 | BIT ( 0 ) ; sw_w32 ( v , RTL931X_SMI_INDRT_ACCESS_CTRL_0 ) ; do { v = sw_r32 ( RTL931X_SMI_INDRT_ACCESS_CTRL_0 ) ; } while ( v & BIT ( 0 ) ) ; if ( v & BIT ( 1 ) ) err = - EIO ; * val = sw_r32 ( RTL931X_SMI_INDRT_ACCESS_CTRL_3 ) >> 16 ; pr_debug ( " \n " , __func__ , port , devnum , mdiobus_c45_regad ( regnum ) , * val , err ) ; mutex_unlock ( & smi_lock ) ; return err ; }
Read an mmd register of the PHY
Read an mmd register of the PHY
/* Select PHY register type
	 * If select 1G/10G MMD register type, registers EXT_PAGE, MAIN_PAGE and REG settings are don’t care.
	 * 0x0  Normal register (Clause 22)
	 * 0x1: 1G MMD register (MMD via Clause 22 registers 13 and 14)
	 * 0x2: 10G MMD register (MMD via Clause 45)
	 */ // Set PHY to access via port-number // Set MMD device number and register to write to // MMD-access-type | EXEC // Check for error condition