XilinxProcessorIPLib/drivers/clk_wiz/examples/xclk_wiz_setrate_example.c
u32 ClkWiz_Example(XClk_Wiz *IntcInstancePtr, u32 DeviceId)
{
	XClk_Wiz_Config *CfgPtr_Dynamic;
	u32 Status = XST_FAILURE;
	u32 Reg;

	/*
	 * Get the CLK_WIZ Dynamic reconfiguration driver instance
	 */
	CfgPtr_Dynamic = XClk_Wiz_LookupConfig(DeviceId);
	if (!CfgPtr_Dynamic) {
		return XST_FAILURE;
	}

	/*
	 * Initialize the CLK_WIZ Dynamic reconfiguration driver
	 */
	Status = XClk_Wiz_CfgInitialize(&ClkWiz_Dynamic, CfgPtr_Dynamic,
		 CfgPtr_Dynamic->BaseAddr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/* Calling Clock wizard dynamic reconfig */

	XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
	XClk_Wiz_SetRate(&ClkWiz_Dynamic, 200);

	XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_US_WIZ_RECONFIG_OFFSET, (XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
	Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
	if (Status != XST_SUCCESS) {
		Reg = XClk_Wiz_ReadReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_STATUS_OFFSET) & CLK_LOCK;
		xil_printf("\n ERROR: Clock is not locked : 0x%x \t Expected "\
		": 0x1\n\r", Reg);
	}

	return Status;
}
/*****************************************************************************/
/**
*
* This function is the main entry point for the example using the
* XClk_Wiz driver.
*
* @param	DeviceId is the unique device ID of the CLK_WIZ
*		Subsystem core.
*
* @return
*		- XST_FAILURE if the system setup failed.
*		- XST_SUCCESS if successful.
*
******************************************************************************/
This function is the main entry point for the example using the
XClk_Wiz driver.
This function is the main entry point for the example using the XClk_Wiz driver .
u32 ClkWiz_Example(XClk_Wiz *IntcInstancePtr, u32 DeviceId)
{
	XClk_Wiz_Config *CfgPtr_Dynamic;
	u32 Status = XST_FAILURE;
	u32 Reg;
	CfgPtr_Dynamic = XClk_Wiz_LookupConfig(DeviceId);
	if (!CfgPtr_Dynamic) {
		return XST_FAILURE;
	}
	Status = XClk_Wiz_CfgInitialize(&ClkWiz_Dynamic, CfgPtr_Dynamic,
		 CfgPtr_Dynamic->BaseAddr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_REG25_OFFSET, 0);
	XClk_Wiz_SetRate(&ClkWiz_Dynamic, 200);
	XClk_Wiz_WriteReg(CfgPtr_Dynamic->BaseAddr, XCLK_US_WIZ_RECONFIG_OFFSET, (XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR));
	Status = XClk_Wiz_WaitForLock(&ClkWiz_Dynamic);
	if (Status != XST_SUCCESS) {
		Reg = XClk_Wiz_ReadReg(CfgPtr_Dynamic->BaseAddr, XCLK_WIZ_STATUS_OFFSET) & CLK_LOCK;
		xil_printf("\n ERROR: Clock is not locked : 0x%x \t Expected "\
		": 0x1\n\r", Reg);
	}
	return Status;
}
u32 ClkWiz_Example ( XClk_Wiz * IntcInstancePtr , u32 DeviceId ) { XClk_Wiz_Config * CfgPtr_Dynamic ; u32 Status = XST_FAILURE ; u32 Reg ; CfgPtr_Dynamic = XClk_Wiz_LookupConfig ( DeviceId ) ; if ( ! CfgPtr_Dynamic ) { return XST_FAILURE ; } Status = XClk_Wiz_CfgInitialize ( & ClkWiz_Dynamic , CfgPtr_Dynamic , CfgPtr_Dynamic -> BaseAddr ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } XClk_Wiz_WriteReg ( CfgPtr_Dynamic -> BaseAddr , XCLK_WIZ_REG25_OFFSET , 0 ) ; XClk_Wiz_SetRate ( & ClkWiz_Dynamic , 200 ) ; XClk_Wiz_WriteReg ( CfgPtr_Dynamic -> BaseAddr , XCLK_US_WIZ_RECONFIG_OFFSET , ( XCLK_WIZ_RECONFIG_LOAD | XCLK_WIZ_RECONFIG_SADDR ) ) ; Status = XClk_Wiz_WaitForLock ( & ClkWiz_Dynamic ) ; if ( Status != XST_SUCCESS ) { Reg = XClk_Wiz_ReadReg ( CfgPtr_Dynamic -> BaseAddr , XCLK_WIZ_STATUS_OFFSET ) & CLK_LOCK ; xil_printf ( " \n \t " " \n \r " , Reg ) ; } return Status ; }
This function is the main entry point for the example using the
XClk_Wiz driver.
This function is the main entry point for the example using the XClk_Wiz driver .
/*
	 * Get the CLK_WIZ Dynamic reconfiguration driver instance
	 */ /*
	 * Initialize the CLK_WIZ Dynamic reconfiguration driver
	 */ /* Calling Clock wizard dynamic reconfig */