XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_hdmi.c
u32 XHdmiphy1_Hdmi21Config(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_DirectionType Dir, u64 LineRate, u8 NChannels)
{
	XHdmiphy1_PllType PllType;
	u32 Status = XST_SUCCESS;

#if (XPAR_HDMIPHY1_0_TRANSCEIVER == XHDMIPHY1_GTHE4) || \
	(XPAR_HDMIPHY1_0_TRANSCEIVER == XHDMIPHY1_GTYE4)
	char SpeedGrade[5] = XPAR_HDMIPHY1_0_SPEEDGRADE_STR;
	char CompVal[5] = "-1";
	char *SpeedGradePtr = &SpeedGrade[0];
	char *CompValPtr = &CompVal[0];

	/* Look for -1 Parts. Max Line rate is 8Gbps */
	if (strncmp(SpeedGradePtr, CompValPtr, 2) == 0) {
		if (LineRate > 8e9) {
			XHdmiphy1_LogWrite(InstancePtr,
                XHDMIPHY1_LOG_EVT_SPDGRDE_ERR, Dir);
			XHdmiphy1_ErrorHandler(InstancePtr);
			return XST_FAILURE;
		}
	}
#endif

	XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_FRL_RECONFIG, Dir);

	/* Determine PLL type. */
	PllType = XHdmiphy1_GetPllType(InstancePtr, 0, Dir,
                XHDMIPHY1_CHANNEL_ID_CH1);

	/* Disable Clock Detector Interrupts */
	if (Dir == XHDMIPHY1_DIR_TX) {
		if (InstancePtr->Config.TxRefClkSel !=
				InstancePtr->Config.TxFrlRefClkSel) {
			XHdmiphy1_IntrDisable(InstancePtr,
					XHDMIPHY1_INTR_HANDLER_TYPE_TX_CLKDET_FREQ_CHANGE);
		}
		/* Enable 4th Channel output */
		XHdmiphy1_Clkout1OBufTdsEnable(InstancePtr, XHDMIPHY1_DIR_TX, (TRUE));
	} else {
		if (InstancePtr->Config.RxRefClkSel !=
						InstancePtr->Config.RxFrlRefClkSel) {
			XHdmiphy1_IntrDisable(InstancePtr,
					XHDMIPHY1_INTR_HANDLER_TYPE_RX_CLKDET_FREQ_CHANGE);
		}
	}

#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
	/* Update reference clock election. */
	XHdmiphy1_CfgPllRefClkSel(InstancePtr, 0,
		((PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
			XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA),
		((Dir == XHDMIPHY1_DIR_TX) ?
			InstancePtr->Config.TxFrlRefClkSel :
			InstancePtr->Config.RxFrlRefClkSel));

	/* Update RefClk selection. */
	XHdmiphy1_WriteCfgRefClkSelReg(InstancePtr, 0);
#endif

	/* Update HDMI Configurations */
	if (Dir == XHDMIPHY1_DIR_TX) {
		InstancePtr->HdmiTxRefClkHz = XHDMIPHY1_HDMI21_FRL_REFCLK;
		InstancePtr->TxHdmi21Cfg.LineRate = LineRate;
		InstancePtr->TxHdmi21Cfg.NChannels = NChannels;
		InstancePtr->TxHdmi21Cfg.IsEnabled = TRUE;

		Status = XHdmiphy1_SetHdmiTxParam(InstancePtr, 0,
				((PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
				XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA),
				InstancePtr->Config.Ppc,
				XVIDC_BPC_8,
				XVIDC_CSF_RGB);

		/* Mask the MMCM Lock */
		XHdmiphy1_MmcmLockedMaskEnable(InstancePtr, 0, Dir, TRUE);

		if (InstancePtr->Config.TxRefClkSel ==
				InstancePtr->Config.TxFrlRefClkSel) {
			XHdmiphy1_MmcmSetClkinsel(InstancePtr, QuadId, Dir,
					XHDMIPHY1_MMCM_CLKINSEL_CLKIN1);
		} else {
			XHdmiphy1_MmcmSetClkinsel(InstancePtr, QuadId, Dir,
					XHDMIPHY1_MMCM_CLKINSEL_CLKIN2);
		}
		if (InstancePtr->Config.TxRefClkSel !=
				InstancePtr->Config.TxFrlRefClkSel) {
			XHdmiphy1_HdmiTxTimerTimeoutHandler(InstancePtr);
		}
	} else {
		InstancePtr->HdmiRxRefClkHz = XHDMIPHY1_HDMI21_FRL_REFCLK;
		InstancePtr->RxHdmi21Cfg.LineRate = LineRate;
		InstancePtr->RxHdmi21Cfg.NChannels = NChannels;
		InstancePtr->RxHdmi21Cfg.IsEnabled = TRUE;

		/* Set MMCM dividers for FRL mode */
		XHdmiphy1_MmcmParam(InstancePtr, QuadId, XHDMIPHY1_DIR_RX);

		/* Mask the MMCM Lock */
		XHdmiphy1_MmcmLockedMaskEnable(InstancePtr, 0, Dir, TRUE);

		if (InstancePtr->Config.RxRefClkSel !=
				InstancePtr->Config.RxFrlRefClkSel) {
			/* Set MMCM CLKINSEL to CLK2 */
			XHdmiphy1_MmcmSetClkinsel(InstancePtr, QuadId, Dir,
					XHDMIPHY1_MMCM_CLKINSEL_CLKIN2);

			/* Start RX MMCM. */
			XHdmiphy1_MmcmStart(InstancePtr, 0, XHDMIPHY1_DIR_RX);

			XHdmiphy1_HdmiRxTimerTimeoutHandler(InstancePtr);
		}
	}

	return Status;
}
/*****************************************************************************/
/**
* This function will configure the GT for HDMI 2.1 operation
*
* @param	InstancePtr is a pointer to the Hdmiphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
* @param	Dir is an indicator for RX or TX.
*
* @return
*		- XST_SUCCESS if TX parameters set/updated.
*		- XST_FAILURE if low resolution video not supported.
*
* @note		None.
*
******************************************************************************/
This function will configure the GT for HDMI 2.1 operation
This function will configure the GT for HDMI 2 . 1 operation
u32 XHdmiphy1_Hdmi21Config(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_DirectionType Dir, u64 LineRate, u8 NChannels)
{
	XHdmiphy1_PllType PllType;
	u32 Status = XST_SUCCESS;
#if (XPAR_HDMIPHY1_0_TRANSCEIVER == XHDMIPHY1_GTHE4) || \
	(XPAR_HDMIPHY1_0_TRANSCEIVER == XHDMIPHY1_GTYE4)
	char SpeedGrade[5] = XPAR_HDMIPHY1_0_SPEEDGRADE_STR;
	char CompVal[5] = "-1";
	char *SpeedGradePtr = &SpeedGrade[0];
	char *CompValPtr = &CompVal[0];
	if (strncmp(SpeedGradePtr, CompValPtr, 2) == 0) {
		if (LineRate > 8e9) {
			XHdmiphy1_LogWrite(InstancePtr,
                XHDMIPHY1_LOG_EVT_SPDGRDE_ERR, Dir);
			XHdmiphy1_ErrorHandler(InstancePtr);
			return XST_FAILURE;
		}
	}
#endif
	XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_FRL_RECONFIG, Dir);
	PllType = XHdmiphy1_GetPllType(InstancePtr, 0, Dir,
                XHDMIPHY1_CHANNEL_ID_CH1);
	if (Dir == XHDMIPHY1_DIR_TX) {
		if (InstancePtr->Config.TxRefClkSel !=
				InstancePtr->Config.TxFrlRefClkSel) {
			XHdmiphy1_IntrDisable(InstancePtr,
					XHDMIPHY1_INTR_HANDLER_TYPE_TX_CLKDET_FREQ_CHANGE);
		}
		XHdmiphy1_Clkout1OBufTdsEnable(InstancePtr, XHDMIPHY1_DIR_TX, (TRUE));
	} else {
		if (InstancePtr->Config.RxRefClkSel !=
						InstancePtr->Config.RxFrlRefClkSel) {
			XHdmiphy1_IntrDisable(InstancePtr,
					XHDMIPHY1_INTR_HANDLER_TYPE_RX_CLKDET_FREQ_CHANGE);
		}
	}
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
	XHdmiphy1_CfgPllRefClkSel(InstancePtr, 0,
		((PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
			XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA),
		((Dir == XHDMIPHY1_DIR_TX) ?
			InstancePtr->Config.TxFrlRefClkSel :
			InstancePtr->Config.RxFrlRefClkSel));
	XHdmiphy1_WriteCfgRefClkSelReg(InstancePtr, 0);
#endif
	if (Dir == XHDMIPHY1_DIR_TX) {
		InstancePtr->HdmiTxRefClkHz = XHDMIPHY1_HDMI21_FRL_REFCLK;
		InstancePtr->TxHdmi21Cfg.LineRate = LineRate;
		InstancePtr->TxHdmi21Cfg.NChannels = NChannels;
		InstancePtr->TxHdmi21Cfg.IsEnabled = TRUE;
		Status = XHdmiphy1_SetHdmiTxParam(InstancePtr, 0,
				((PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
				XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA),
				InstancePtr->Config.Ppc,
				XVIDC_BPC_8,
				XVIDC_CSF_RGB);
		XHdmiphy1_MmcmLockedMaskEnable(InstancePtr, 0, Dir, TRUE);
		if (InstancePtr->Config.TxRefClkSel ==
				InstancePtr->Config.TxFrlRefClkSel) {
			XHdmiphy1_MmcmSetClkinsel(InstancePtr, QuadId, Dir,
					XHDMIPHY1_MMCM_CLKINSEL_CLKIN1);
		} else {
			XHdmiphy1_MmcmSetClkinsel(InstancePtr, QuadId, Dir,
					XHDMIPHY1_MMCM_CLKINSEL_CLKIN2);
		}
		if (InstancePtr->Config.TxRefClkSel !=
				InstancePtr->Config.TxFrlRefClkSel) {
			XHdmiphy1_HdmiTxTimerTimeoutHandler(InstancePtr);
		}
	} else {
		InstancePtr->HdmiRxRefClkHz = XHDMIPHY1_HDMI21_FRL_REFCLK;
		InstancePtr->RxHdmi21Cfg.LineRate = LineRate;
		InstancePtr->RxHdmi21Cfg.NChannels = NChannels;
		InstancePtr->RxHdmi21Cfg.IsEnabled = TRUE;
		XHdmiphy1_MmcmParam(InstancePtr, QuadId, XHDMIPHY1_DIR_RX);
		XHdmiphy1_MmcmLockedMaskEnable(InstancePtr, 0, Dir, TRUE);
		if (InstancePtr->Config.RxRefClkSel !=
				InstancePtr->Config.RxFrlRefClkSel) {
			XHdmiphy1_MmcmSetClkinsel(InstancePtr, QuadId, Dir,
					XHDMIPHY1_MMCM_CLKINSEL_CLKIN2);
			XHdmiphy1_MmcmStart(InstancePtr, 0, XHDMIPHY1_DIR_RX);
			XHdmiphy1_HdmiRxTimerTimeoutHandler(InstancePtr);
		}
	}
	return Status;
}
u32 XHdmiphy1_Hdmi21Config ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_DirectionType Dir , u64 LineRate , u8 NChannels ) { XHdmiphy1_PllType PllType ; u32 Status = XST_SUCCESS ; #if ( XPAR_HDMIPHY1_0_TRANSCEIVER == XHDMIPHY1_GTHE4 ) || ( XPAR_HDMIPHY1_0_TRANSCEIVER == XHDMIPHY1_GTYE4 ) char SpeedGrade [ 5 ] = XPAR_HDMIPHY1_0_SPEEDGRADE_STR ; char CompVal [ 5 ] = " " ; char * SpeedGradePtr = & SpeedGrade [ 0 ] ; char * CompValPtr = & CompVal [ 0 ] ; if ( strncmp ( SpeedGradePtr , CompValPtr , 2 ) == 0 ) { if ( LineRate > 8e9 ) { XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_SPDGRDE_ERR , Dir ) ; XHdmiphy1_ErrorHandler ( InstancePtr ) ; return XST_FAILURE ; } } #endif XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_FRL_RECONFIG , Dir ) ; PllType = XHdmiphy1_GetPllType ( InstancePtr , 0 , Dir , XHDMIPHY1_CHANNEL_ID_CH1 ) ; if ( Dir == XHDMIPHY1_DIR_TX ) { if ( InstancePtr -> Config . TxRefClkSel != InstancePtr -> Config . TxFrlRefClkSel ) { XHdmiphy1_IntrDisable ( InstancePtr , XHDMIPHY1_INTR_HANDLER_TYPE_TX_CLKDET_FREQ_CHANGE ) ; } XHdmiphy1_Clkout1OBufTdsEnable ( InstancePtr , XHDMIPHY1_DIR_TX , ( TRUE ) ) ; } else { if ( InstancePtr -> Config . RxRefClkSel != InstancePtr -> Config . RxFrlRefClkSel ) { XHdmiphy1_IntrDisable ( InstancePtr , XHDMIPHY1_INTR_HANDLER_TYPE_RX_CLKDET_FREQ_CHANGE ) ; } } #if ( XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5 ) XHdmiphy1_CfgPllRefClkSel ( InstancePtr , 0 , ( ( PllType == XHDMIPHY1_PLL_TYPE_CPLL ) ? XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA ) , ( ( Dir == XHDMIPHY1_DIR_TX ) ? InstancePtr -> Config . TxFrlRefClkSel : InstancePtr -> Config . RxFrlRefClkSel ) ) ; XHdmiphy1_WriteCfgRefClkSelReg ( InstancePtr , 0 ) ; #endif if ( Dir == XHDMIPHY1_DIR_TX ) { InstancePtr -> HdmiTxRefClkHz = XHDMIPHY1_HDMI21_FRL_REFCLK ; InstancePtr -> TxHdmi21Cfg . LineRate = LineRate ; InstancePtr -> TxHdmi21Cfg . NChannels = NChannels ; InstancePtr -> TxHdmi21Cfg . IsEnabled = TRUE ; Status = XHdmiphy1_SetHdmiTxParam ( InstancePtr , 0 , ( ( PllType == XHDMIPHY1_PLL_TYPE_CPLL ) ? XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA ) , InstancePtr -> Config . Ppc , XVIDC_BPC_8 , XVIDC_CSF_RGB ) ; XHdmiphy1_MmcmLockedMaskEnable ( InstancePtr , 0 , Dir , TRUE ) ; if ( InstancePtr -> Config . TxRefClkSel == InstancePtr -> Config . TxFrlRefClkSel ) { XHdmiphy1_MmcmSetClkinsel ( InstancePtr , QuadId , Dir , XHDMIPHY1_MMCM_CLKINSEL_CLKIN1 ) ; } else { XHdmiphy1_MmcmSetClkinsel ( InstancePtr , QuadId , Dir , XHDMIPHY1_MMCM_CLKINSEL_CLKIN2 ) ; } if ( InstancePtr -> Config . TxRefClkSel != InstancePtr -> Config . TxFrlRefClkSel ) { XHdmiphy1_HdmiTxTimerTimeoutHandler ( InstancePtr ) ; } } else { InstancePtr -> HdmiRxRefClkHz = XHDMIPHY1_HDMI21_FRL_REFCLK ; InstancePtr -> RxHdmi21Cfg . LineRate = LineRate ; InstancePtr -> RxHdmi21Cfg . NChannels = NChannels ; InstancePtr -> RxHdmi21Cfg . IsEnabled = TRUE ; XHdmiphy1_MmcmParam ( InstancePtr , QuadId , XHDMIPHY1_DIR_RX ) ; XHdmiphy1_MmcmLockedMaskEnable ( InstancePtr , 0 , Dir , TRUE ) ; if ( InstancePtr -> Config . RxRefClkSel != InstancePtr -> Config . RxFrlRefClkSel ) { XHdmiphy1_MmcmSetClkinsel ( InstancePtr , QuadId , Dir , XHDMIPHY1_MMCM_CLKINSEL_CLKIN2 ) ; XHdmiphy1_MmcmStart ( InstancePtr , 0 , XHDMIPHY1_DIR_RX ) ; XHdmiphy1_HdmiRxTimerTimeoutHandler ( InstancePtr ) ; } } return Status ; }
This function will configure the GT for HDMI 2.1 operation
This function will configure the GT for HDMI 2 . 1 operation
/* Look for -1 Parts. Max Line rate is 8Gbps */ /* Determine PLL type. */ /* Disable Clock Detector Interrupts */ /* Enable 4th Channel output */ /* Update reference clock election. */ /* Update RefClk selection. */ /* Update HDMI Configurations */ /* Mask the MMCM Lock */ /* Set MMCM dividers for FRL mode */ /* Mask the MMCM Lock */ /* Set MMCM CLKINSEL to CLK2 */ /* Start RX MMCM. */