XilinxProcessorIPLib/drivers/axiethernet/examples/xaxiethernet_example_util.c
int AxiEthernetUtilConfigureInternalPhy(XAxiEthernet *AxiEthernetInstancePtr,
					int Speed)
{
	u16 PhyReg0;
	signed int PhyAddr;

	PhyAddr = XPAR_AXIETHERNET_0_PHYADDR;

	/* Clear the PHY of any existing bits by zeroing this out */
	PhyReg0 = 0;
	XAxiEthernet_PhyRead(AxiEthernetInstancePtr, PhyAddr,
				 PHY_R0_CTRL_REG, &PhyReg0);

	PhyReg0 &= (~PHY_R0_ANEG_ENABLE);
	PhyReg0 &= (~PHY_R0_ISOLATE);

	switch (Speed) {
		case XAE_SPEED_10_MBPS:
			PhyReg0 |= PHY_R0_DFT_SPD_10;
			break;
		case XAE_SPEED_100_MBPS:
			PhyReg0 |= PHY_R0_DFT_SPD_100;
			break;
		case XAE_SPEED_1000_MBPS:
			PhyReg0 |= PHY_R0_DFT_SPD_1000;
			break;
		case XAE_SPEED_2500_MBPS:
			PhyReg0 |= PHY_R0_DFT_SPD_2500;
			break;
		default:
			AxiEthernetUtilErrorTrap(
				"Intg_LinkSpeed not 10, 100, or 1000 mbps\n\r");
				return XST_FAILURE;
	}

	AxiEthernetUtilPhyDelay(1);
	XAxiEthernet_PhyWrite(AxiEthernetInstancePtr, PhyAddr,
				PHY_R0_CTRL_REG, PhyReg0);
	return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function configures the internal phy for SGMII and 1000baseX modes.
* *
* @param	AxiEthernetInstancePtr is a pointer to the instance of the
*		AxiEthernet component.
* @param	Speed is the loopback speed 10, 100, or 1000 Mbit.
*
* @return
*		- XST_SUCCESS if successful.
*		- XST_FAILURE, in case of failure..
*
* @note		None.
*
******************************************************************************/
This function configures the internal phy for SGMII and 1000baseX modes.
This function configures the internal phy for SGMII and 1000baseX modes .
int AxiEthernetUtilConfigureInternalPhy(XAxiEthernet *AxiEthernetInstancePtr,
					int Speed)
{
	u16 PhyReg0;
	signed int PhyAddr;
	PhyAddr = XPAR_AXIETHERNET_0_PHYADDR;
	PhyReg0 = 0;
	XAxiEthernet_PhyRead(AxiEthernetInstancePtr, PhyAddr,
				 PHY_R0_CTRL_REG, &PhyReg0);
	PhyReg0 &= (~PHY_R0_ANEG_ENABLE);
	PhyReg0 &= (~PHY_R0_ISOLATE);
	switch (Speed) {
		case XAE_SPEED_10_MBPS:
			PhyReg0 |= PHY_R0_DFT_SPD_10;
			break;
		case XAE_SPEED_100_MBPS:
			PhyReg0 |= PHY_R0_DFT_SPD_100;
			break;
		case XAE_SPEED_1000_MBPS:
			PhyReg0 |= PHY_R0_DFT_SPD_1000;
			break;
		case XAE_SPEED_2500_MBPS:
			PhyReg0 |= PHY_R0_DFT_SPD_2500;
			break;
		default:
			AxiEthernetUtilErrorTrap(
				"Intg_LinkSpeed not 10, 100, or 1000 mbps\n\r");
				return XST_FAILURE;
	}
	AxiEthernetUtilPhyDelay(1);
	XAxiEthernet_PhyWrite(AxiEthernetInstancePtr, PhyAddr,
				PHY_R0_CTRL_REG, PhyReg0);
	return XST_SUCCESS;
}
int AxiEthernetUtilConfigureInternalPhy ( XAxiEthernet * AxiEthernetInstancePtr , int Speed ) { u16 PhyReg0 ; signed int PhyAddr ; PhyAddr = XPAR_AXIETHERNET_0_PHYADDR ; PhyReg0 = 0 ; XAxiEthernet_PhyRead ( AxiEthernetInstancePtr , PhyAddr , PHY_R0_CTRL_REG , & PhyReg0 ) ; PhyReg0 &= ( ~ PHY_R0_ANEG_ENABLE ) ; PhyReg0 &= ( ~ PHY_R0_ISOLATE ) ; switch ( Speed ) { case XAE_SPEED_10_MBPS : PhyReg0 |= PHY_R0_DFT_SPD_10 ; break ; case XAE_SPEED_100_MBPS : PhyReg0 |= PHY_R0_DFT_SPD_100 ; break ; case XAE_SPEED_1000_MBPS : PhyReg0 |= PHY_R0_DFT_SPD_1000 ; break ; case XAE_SPEED_2500_MBPS : PhyReg0 |= PHY_R0_DFT_SPD_2500 ; break ; default : AxiEthernetUtilErrorTrap ( " \n \r " ) ; return XST_FAILURE ; } AxiEthernetUtilPhyDelay ( 1 ) ; XAxiEthernet_PhyWrite ( AxiEthernetInstancePtr , PhyAddr , PHY_R0_CTRL_REG , PhyReg0 ) ; return XST_SUCCESS ; }
This function configures the internal phy for SGMII and 1000baseX modes.
This function configures the internal phy for SGMII and 1000baseX modes .
/* Clear the PHY of any existing bits by zeroing this out */