XilinxProcessorIPLib/drivers/dp12txss/examples/src/kcu/xdptxss_kcu105.c
static void Dprx_DetectResolution(void *InstancePtr)
{
	u32 DpHres = 0;
	u32 DpVres = 0;
	u32 GetResCount = 0;
	int i =0;
	do {
		DpHres = (XDp_ReadReg(DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr,
						XDP_RX_MSA_HRES));
		DpVres = (XDp_ReadReg(DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr,
						XDP_RX_MSA_VHEIGHT));
		GetResCount++;
	} while ( (((DpHres == 0) || (DpVres == 0)) && (GetResCount < 10000))
						&& training_done == 1);
	dp_msa_hres = DpHres;
	dp_msa_vres = DpVres;

	Msa[0].Vtm.Timing.HActive = dp_msa_hres;
	Msa[0].Vtm.Timing.VActive = dp_msa_vres;

	GetResCount = 0;
	DpHres_total = (XDp_ReadReg(DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr,
						XDP_RX_MSA_HTOTAL));
	DpVres_total = (XDp_ReadReg(DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr,
						XDP_RX_MSA_VTOTAL));
	while ( ((DpHres_total ==0 || DpVres_total == 0) && GetResCount < 10000)
						&& training_done == 1) {
		DpHres_total = (XDp_ReadReg(
			DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr, XDP_RX_MSA_HTOTAL));
		DpVres_total = (XDp_ReadReg(
			DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr, XDP_RX_MSA_VTOTAL));
		GetResCount++;
	}

	Msa[0].Vtm.Timing.HTotal = DpHres_total;
	Msa[0].Vtm.Timing.F0PVTotal = DpVres_total;
	GetResCount = 0;
	rxMsaMVid = (XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,XDP_RX_MSA_MVID)
								& 0x00FFFFFF);
	rxMsaNVid = (XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,XDP_RX_MSA_NVID)
								& 0x00FFFFFF);
	while ( ((rxMsaMVid ==0 || rxMsaNVid == 0) && GetResCount < 10000)
													&& training_done == 1) {
		rxMsaMVid = (XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
												XDP_RX_MSA_MVID) & 0x00FFFFFF);
		rxMsaNVid = (XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
												XDP_RX_MSA_NVID) & 0x00FFFFFF);
		GetResCount++;
	}
	Msa[0].MVid = rxMsaMVid;
	Msa[0].NVid = rxMsaNVid;

	Msa[0].HStart = XDp_ReadReg(DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr,
															XDP_RX_MSA_HSTART);
	Msa[0].VStart = XDp_ReadReg(DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr,
															XDP_RX_MSA_VSTART);

	Msa[0].Vtm.Timing.HSyncWidth = XDp_ReadReg(
			DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr, XDP_RX_MSA_HSWIDTH);
	Msa[0].Vtm.Timing.F0PVSyncWidth = XDp_ReadReg(
			DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr, XDP_RX_MSA_VSWIDTH);

	Msa[0].Vtm.Timing.HSyncPolarity = XDp_ReadReg(
			DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr, XDP_RX_MSA_HSPOL);
	Msa[0].Vtm.Timing.VSyncPolarity = XDp_ReadReg(
			DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr, XDP_RX_MSA_VSPOL);

	recv_clk_freq = ((LineRate * 27.0)*rxMsaMVid)/rxMsaNVid;
	recv_frame_clk =
			ceil_func((recv_clk_freq*1000000.0)/(DpHres_total * DpVres_total));
	recv_frame_clk_int = recv_frame_clk;
	//Doing Approximation here
	if (recv_frame_clk_int == 59 || recv_frame_clk_int == 61) {
		recv_frame_clk_int = 60;
	} else if (recv_frame_clk_int == 29 || recv_frame_clk_int == 31) {
		recv_frame_clk_int = 30;
	} else if (recv_frame_clk_int == 76 || recv_frame_clk_int == 74) {
		recv_frame_clk_int = 75;
	}

	recv_frame_clk_int_track = recv_frame_clk_int;
	recv_clk_see = ((LineRate * 27.0)*rxMsaMVid*1000)/rxMsaNVid;

	if((recv_clk_freq*1000000)>300000000 && LaneCount==4){
		XDp_RxSetUserPixelWidth(DpRxSsInst.DpPtr, 0x04);
		pixel = 0x4;
		Msa[0].UserPixelWidth = 0x4;
	}
	else if((recv_clk_freq*1000000)>75000000 && LaneCount!=1){
		XDp_RxSetUserPixelWidth(DpRxSsInst.DpPtr, 0x02);
		pixel = 0x2;
		Msa[0].UserPixelWidth = 0x2;
	}
	else{
		XDp_RxSetUserPixelWidth(DpRxSsInst.DpPtr, 0x01);
		pixel = 0x1;
		Msa[0].UserPixelWidth = 0x1;
	}

	XDp_RxSetLineReset(DpRxSsInst.DpPtr, 1);
	rxMsamisc0 = ((XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
							XDP_RX_MSA_MISC0) >> 5) & 0x00000007);

	while (i < 100000 && training_done == 1) {
		rxMsamisc0 = ((XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
							XDP_RX_MSA_MISC0) >> 5) & 0x00000007);
		i++;
	}
	comp = ((XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
							XDP_RX_MSA_MISC0) >> 1) & 0x00000003);
	Msa[0].SynchronousClockMode = rxMsamisc0 & 1;
	bpc = Bpc[rxMsamisc0];
	Msa[0].BitsPerColor = bpc;
	Msa[0].Misc0 = XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
								XDP_RX_MSA_MISC0); //rxMsamisc0;
	Msa[0].Misc1 = XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
								XDP_RX_MSA_MISC1);
	if (training_done == 1) {
		xdbg_printf(XDBG_DEBUG_GENERAL,
		"*** Detected resolution: %d x %d @ %dHz, BPC = %d, Color = %d***\n\r",
			DpHres, DpVres,recv_frame_clk_int,bpc,comp);
	}
}
// This process takes in all the MSA values and find out resolution, BPC,
// refresh rate. Further this sets the pixel_width based on the pixel_clock and
// lane set. This is to ensure that it matches the values in TX driver. Else
// video cannot be passthrough. Approximation is implemented for refresh rates.
// Sometimes a refresh rate of 60 is detected as 59
// and vice-versa. Approximation is done for single digit.
This process takes in all the MSA values and find out resolution, BPC,
refresh rate. Further this sets the pixel_width based on the pixel_clock and
lane set. This is to ensure that it matches the values in TX driver. Else
video cannot be passthrough. Approximation is implemented for refresh rates.
Sometimes a refresh rate of 60 is detected as 59
and vice-versa. Approximation is done for single digit.
This process takes in all the MSA values and find out resolution BPC refresh rate . Further this sets the pixel_width based on the pixel_clock and lane set . This is to ensure that it matches the values in TX driver . Else video cannot be passthrough . Approximation is implemented for refresh rates . Sometimes a refresh rate of 60 is detected as 59 and vice - versa . Approximation is done for single digit .
static void Dprx_DetectResolution(void *InstancePtr)
{
	u32 DpHres = 0;
	u32 DpVres = 0;
	u32 GetResCount = 0;
	int i =0;
	do {
		DpHres = (XDp_ReadReg(DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr,
						XDP_RX_MSA_HRES));
		DpVres = (XDp_ReadReg(DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr,
						XDP_RX_MSA_VHEIGHT));
		GetResCount++;
	} while ( (((DpHres == 0) || (DpVres == 0)) && (GetResCount < 10000))
						&& training_done == 1);
	dp_msa_hres = DpHres;
	dp_msa_vres = DpVres;
	Msa[0].Vtm.Timing.HActive = dp_msa_hres;
	Msa[0].Vtm.Timing.VActive = dp_msa_vres;
	GetResCount = 0;
	DpHres_total = (XDp_ReadReg(DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr,
						XDP_RX_MSA_HTOTAL));
	DpVres_total = (XDp_ReadReg(DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr,
						XDP_RX_MSA_VTOTAL));
	while ( ((DpHres_total ==0 || DpVres_total == 0) && GetResCount < 10000)
						&& training_done == 1) {
		DpHres_total = (XDp_ReadReg(
			DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr, XDP_RX_MSA_HTOTAL));
		DpVres_total = (XDp_ReadReg(
			DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr, XDP_RX_MSA_VTOTAL));
		GetResCount++;
	}
	Msa[0].Vtm.Timing.HTotal = DpHres_total;
	Msa[0].Vtm.Timing.F0PVTotal = DpVres_total;
	GetResCount = 0;
	rxMsaMVid = (XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,XDP_RX_MSA_MVID)
								& 0x00FFFFFF);
	rxMsaNVid = (XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,XDP_RX_MSA_NVID)
								& 0x00FFFFFF);
	while ( ((rxMsaMVid ==0 || rxMsaNVid == 0) && GetResCount < 10000)
													&& training_done == 1) {
		rxMsaMVid = (XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
												XDP_RX_MSA_MVID) & 0x00FFFFFF);
		rxMsaNVid = (XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
												XDP_RX_MSA_NVID) & 0x00FFFFFF);
		GetResCount++;
	}
	Msa[0].MVid = rxMsaMVid;
	Msa[0].NVid = rxMsaNVid;
	Msa[0].HStart = XDp_ReadReg(DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr,
															XDP_RX_MSA_HSTART);
	Msa[0].VStart = XDp_ReadReg(DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr,
															XDP_RX_MSA_VSTART);
	Msa[0].Vtm.Timing.HSyncWidth = XDp_ReadReg(
			DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr, XDP_RX_MSA_HSWIDTH);
	Msa[0].Vtm.Timing.F0PVSyncWidth = XDp_ReadReg(
			DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr, XDP_RX_MSA_VSWIDTH);
	Msa[0].Vtm.Timing.HSyncPolarity = XDp_ReadReg(
			DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr, XDP_RX_MSA_HSPOL);
	Msa[0].Vtm.Timing.VSyncPolarity = XDp_ReadReg(
			DpRxSsInst.Config.DpSubCore.DpConfig.BaseAddr, XDP_RX_MSA_VSPOL);
	recv_clk_freq = ((LineRate * 27.0)*rxMsaMVid)/rxMsaNVid;
	recv_frame_clk =
			ceil_func((recv_clk_freq*1000000.0)/(DpHres_total * DpVres_total));
	recv_frame_clk_int = recv_frame_clk;
	if (recv_frame_clk_int == 59 || recv_frame_clk_int == 61) {
		recv_frame_clk_int = 60;
	} else if (recv_frame_clk_int == 29 || recv_frame_clk_int == 31) {
		recv_frame_clk_int = 30;
	} else if (recv_frame_clk_int == 76 || recv_frame_clk_int == 74) {
		recv_frame_clk_int = 75;
	}
	recv_frame_clk_int_track = recv_frame_clk_int;
	recv_clk_see = ((LineRate * 27.0)*rxMsaMVid*1000)/rxMsaNVid;
	if((recv_clk_freq*1000000)>300000000 && LaneCount==4){
		XDp_RxSetUserPixelWidth(DpRxSsInst.DpPtr, 0x04);
		pixel = 0x4;
		Msa[0].UserPixelWidth = 0x4;
	}
	else if((recv_clk_freq*1000000)>75000000 && LaneCount!=1){
		XDp_RxSetUserPixelWidth(DpRxSsInst.DpPtr, 0x02);
		pixel = 0x2;
		Msa[0].UserPixelWidth = 0x2;
	}
	else{
		XDp_RxSetUserPixelWidth(DpRxSsInst.DpPtr, 0x01);
		pixel = 0x1;
		Msa[0].UserPixelWidth = 0x1;
	}
	XDp_RxSetLineReset(DpRxSsInst.DpPtr, 1);
	rxMsamisc0 = ((XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
							XDP_RX_MSA_MISC0) >> 5) & 0x00000007);
	while (i < 100000 && training_done == 1) {
		rxMsamisc0 = ((XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
							XDP_RX_MSA_MISC0) >> 5) & 0x00000007);
		i++;
	}
	comp = ((XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
							XDP_RX_MSA_MISC0) >> 1) & 0x00000003);
	Msa[0].SynchronousClockMode = rxMsamisc0 & 1;
	bpc = Bpc[rxMsamisc0];
	Msa[0].BitsPerColor = bpc;
	Msa[0].Misc0 = XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
								XDP_RX_MSA_MISC0); 
	Msa[0].Misc1 = XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
								XDP_RX_MSA_MISC1);
	if (training_done == 1) {
		xdbg_printf(XDBG_DEBUG_GENERAL,
		"*** Detected resolution: %d x %d @ %dHz, BPC = %d, Color = %d***\n\r",
			DpHres, DpVres,recv_frame_clk_int,bpc,comp);
	}
}
static void Dprx_DetectResolution ( void * InstancePtr ) { u32 DpHres = 0 ; u32 DpVres = 0 ; u32 GetResCount = 0 ; int i = 0 ; do { DpHres = ( XDp_ReadReg ( DpRxSsInst . Config . DpSubCore . DpConfig . BaseAddr , XDP_RX_MSA_HRES ) ) ; DpVres = ( XDp_ReadReg ( DpRxSsInst . Config . DpSubCore . DpConfig . BaseAddr , XDP_RX_MSA_VHEIGHT ) ) ; GetResCount ++ ; } while ( ( ( ( DpHres == 0 ) || ( DpVres == 0 ) ) && ( GetResCount < 10000 ) ) && training_done == 1 ) ; dp_msa_hres = DpHres ; dp_msa_vres = DpVres ; Msa [ 0 ] . Vtm . Timing . HActive = dp_msa_hres ; Msa [ 0 ] . Vtm . Timing . VActive = dp_msa_vres ; GetResCount = 0 ; DpHres_total = ( XDp_ReadReg ( DpRxSsInst . Config . DpSubCore . DpConfig . BaseAddr , XDP_RX_MSA_HTOTAL ) ) ; DpVres_total = ( XDp_ReadReg ( DpRxSsInst . Config . DpSubCore . DpConfig . BaseAddr , XDP_RX_MSA_VTOTAL ) ) ; while ( ( ( DpHres_total == 0 || DpVres_total == 0 ) && GetResCount < 10000 ) && training_done == 1 ) { DpHres_total = ( XDp_ReadReg ( DpRxSsInst . Config . DpSubCore . DpConfig . BaseAddr , XDP_RX_MSA_HTOTAL ) ) ; DpVres_total = ( XDp_ReadReg ( DpRxSsInst . Config . DpSubCore . DpConfig . BaseAddr , XDP_RX_MSA_VTOTAL ) ) ; GetResCount ++ ; } Msa [ 0 ] . Vtm . Timing . HTotal = DpHres_total ; Msa [ 0 ] . Vtm . Timing . F0PVTotal = DpVres_total ; GetResCount = 0 ; rxMsaMVid = ( XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_MVID ) & 0x00FFFFFF ) ; rxMsaNVid = ( XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_NVID ) & 0x00FFFFFF ) ; while ( ( ( rxMsaMVid == 0 || rxMsaNVid == 0 ) && GetResCount < 10000 ) && training_done == 1 ) { rxMsaMVid = ( XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_MVID ) & 0x00FFFFFF ) ; rxMsaNVid = ( XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_NVID ) & 0x00FFFFFF ) ; GetResCount ++ ; } Msa [ 0 ] . MVid = rxMsaMVid ; Msa [ 0 ] . NVid = rxMsaNVid ; Msa [ 0 ] . HStart = XDp_ReadReg ( DpRxSsInst . Config . DpSubCore . DpConfig . BaseAddr , XDP_RX_MSA_HSTART ) ; Msa [ 0 ] . VStart = XDp_ReadReg ( DpRxSsInst . Config . DpSubCore . DpConfig . BaseAddr , XDP_RX_MSA_VSTART ) ; Msa [ 0 ] . Vtm . Timing . HSyncWidth = XDp_ReadReg ( DpRxSsInst . Config . DpSubCore . DpConfig . BaseAddr , XDP_RX_MSA_HSWIDTH ) ; Msa [ 0 ] . Vtm . Timing . F0PVSyncWidth = XDp_ReadReg ( DpRxSsInst . Config . DpSubCore . DpConfig . BaseAddr , XDP_RX_MSA_VSWIDTH ) ; Msa [ 0 ] . Vtm . Timing . HSyncPolarity = XDp_ReadReg ( DpRxSsInst . Config . DpSubCore . DpConfig . BaseAddr , XDP_RX_MSA_HSPOL ) ; Msa [ 0 ] . Vtm . Timing . VSyncPolarity = XDp_ReadReg ( DpRxSsInst . Config . DpSubCore . DpConfig . BaseAddr , XDP_RX_MSA_VSPOL ) ; recv_clk_freq = ( ( LineRate * 27.0 ) * rxMsaMVid ) / rxMsaNVid ; recv_frame_clk = ceil_func ( ( recv_clk_freq * 1000000.0 ) / ( DpHres_total * DpVres_total ) ) ; recv_frame_clk_int = recv_frame_clk ; if ( recv_frame_clk_int == 59 || recv_frame_clk_int == 61 ) { recv_frame_clk_int = 60 ; } else if ( recv_frame_clk_int == 29 || recv_frame_clk_int == 31 ) { recv_frame_clk_int = 30 ; } else if ( recv_frame_clk_int == 76 || recv_frame_clk_int == 74 ) { recv_frame_clk_int = 75 ; } recv_frame_clk_int_track = recv_frame_clk_int ; recv_clk_see = ( ( LineRate * 27.0 ) * rxMsaMVid * 1000 ) / rxMsaNVid ; if ( ( recv_clk_freq * 1000000 ) > 300000000 && LaneCount == 4 ) { XDp_RxSetUserPixelWidth ( DpRxSsInst . DpPtr , 0x04 ) ; pixel = 0x4 ; Msa [ 0 ] . UserPixelWidth = 0x4 ; } else if ( ( recv_clk_freq * 1000000 ) > 75000000 && LaneCount != 1 ) { XDp_RxSetUserPixelWidth ( DpRxSsInst . DpPtr , 0x02 ) ; pixel = 0x2 ; Msa [ 0 ] . UserPixelWidth = 0x2 ; } else { XDp_RxSetUserPixelWidth ( DpRxSsInst . DpPtr , 0x01 ) ; pixel = 0x1 ; Msa [ 0 ] . UserPixelWidth = 0x1 ; } XDp_RxSetLineReset ( DpRxSsInst . DpPtr , 1 ) ; rxMsamisc0 = ( ( XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_MISC0 ) >> 5 ) & 0x00000007 ) ; while ( i < 100000 && training_done == 1 ) { rxMsamisc0 = ( ( XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_MISC0 ) >> 5 ) & 0x00000007 ) ; i ++ ; } comp = ( ( XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_MISC0 ) >> 1 ) & 0x00000003 ) ; Msa [ 0 ] . SynchronousClockMode = rxMsamisc0 & 1 ; bpc = Bpc [ rxMsamisc0 ] ; Msa [ 0 ] . BitsPerColor = bpc ; Msa [ 0 ] . Misc0 = XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_MISC0 ) ; Msa [ 0 ] . Misc1 = XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_MISC1 ) ; if ( training_done == 1 ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " \n \r " , DpHres , DpVres , recv_frame_clk_int , bpc , comp ) ; } }
This process takes in all the MSA values and find out resolution, BPC,
refresh rate.
This process takes in all the MSA values and find out resolution BPC refresh rate .
//Doing Approximation here //rxMsamisc0;