XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_gtye4.c
u32 XHdmiphy1_Gtye4OutDivChReconfig(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir)
{
    u16 DrpVal;
    u16 WriteVal;
    u32 Status = XST_SUCCESS;

    if (Dir == XHDMIPHY1_DIR_RX) {
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0063, &DrpVal);
        /* Mask out RXOUT_DIV. */
        DrpVal &= ~XDRP_GTYE4_CHN_REG_0063_RXOUT_DIV_MASK;
        /* Set RXOUT_DIV. */
        WriteVal = (XHdmiphy1_DToDrpEncoding(InstancePtr, QuadId, ChId,
                        XHDMIPHY1_DIR_RX) & XDRP_GTYE4_CHN_REG_0063_FLD_RXOUT_DIV_MASK);
        DrpVal |= WriteVal;
        /* Write new DRP register value for RX dividers. */
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0063, DrpVal);
    }
    else {
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_007C, &DrpVal);
        /* Mask out TXOUT_DIV. */
        DrpVal &= ~XDRP_GTYE4_CHN_REG_007C_TXOUT_DIV_MASK;
        /* Set TXOUT_DIV. */
        WriteVal = (XHdmiphy1_DToDrpEncoding(InstancePtr, QuadId, ChId,
                        XHDMIPHY1_DIR_TX) & XDRP_GTYE4_CHN_REG_007C_FLD_TXOUT_DIV_MASK);
        DrpVal |= (WriteVal << 8);
        /* Write new DRP register value for RX dividers. */
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_007C, DrpVal);
    }

    return Status;
}
/*****************************************************************************/
/**
* This function will set the output divider logic for a given channel.
*
* @param    InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param    QuadId is the GT quad ID to operate on.
* @param    ChId is the channel ID to operate on.
* @param    Dir is an indicator for RX or TX.
*
* @return
*       - XST_SUCCESS if the configuration was successful.
*       - XST_FAILURE otherwise.
*
* @note     None.
*
******************************************************************************/
This function will set the output divider logic for a given channel.
This function will set the output divider logic for a given channel .
u32 XHdmiphy1_Gtye4OutDivChReconfig(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir)
{
    u16 DrpVal;
    u16 WriteVal;
    u32 Status = XST_SUCCESS;
    if (Dir == XHDMIPHY1_DIR_RX) {
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0063, &DrpVal);
        DrpVal &= ~XDRP_GTYE4_CHN_REG_0063_RXOUT_DIV_MASK;
        WriteVal = (XHdmiphy1_DToDrpEncoding(InstancePtr, QuadId, ChId,
                        XHDMIPHY1_DIR_RX) & XDRP_GTYE4_CHN_REG_0063_FLD_RXOUT_DIV_MASK);
        DrpVal |= WriteVal;
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0063, DrpVal);
    }
    else {
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_007C, &DrpVal);
        DrpVal &= ~XDRP_GTYE4_CHN_REG_007C_TXOUT_DIV_MASK;
        WriteVal = (XHdmiphy1_DToDrpEncoding(InstancePtr, QuadId, ChId,
                        XHDMIPHY1_DIR_TX) & XDRP_GTYE4_CHN_REG_007C_FLD_TXOUT_DIV_MASK);
        DrpVal |= (WriteVal << 8);
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_007C, DrpVal);
    }
    return Status;
}
u32 XHdmiphy1_Gtye4OutDivChReconfig ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId , XHdmiphy1_DirectionType Dir ) { u16 DrpVal ; u16 WriteVal ; u32 Status = XST_SUCCESS ; if ( Dir == XHDMIPHY1_DIR_RX ) { Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0063 , & DrpVal ) ; DrpVal &= ~ XDRP_GTYE4_CHN_REG_0063_RXOUT_DIV_MASK ; WriteVal = ( XHdmiphy1_DToDrpEncoding ( InstancePtr , QuadId , ChId , XHDMIPHY1_DIR_RX ) & XDRP_GTYE4_CHN_REG_0063_FLD_RXOUT_DIV_MASK ) ; DrpVal |= WriteVal ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0063 , DrpVal ) ; } else { Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_007C , & DrpVal ) ; DrpVal &= ~ XDRP_GTYE4_CHN_REG_007C_TXOUT_DIV_MASK ; WriteVal = ( XHdmiphy1_DToDrpEncoding ( InstancePtr , QuadId , ChId , XHDMIPHY1_DIR_TX ) & XDRP_GTYE4_CHN_REG_007C_FLD_TXOUT_DIV_MASK ) ; DrpVal |= ( WriteVal << 8 ) ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_007C , DrpVal ) ; } return Status ; }
This function will set the output divider logic for a given channel.
This function will set the output divider logic for a given channel .
/* Mask out RXOUT_DIV. */ /* Set RXOUT_DIV. */ /* Write new DRP register value for RX dividers. */ /* Mask out TXOUT_DIV. */ /* Set TXOUT_DIV. */ /* Write new DRP register value for RX dividers. */