XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c
int XSysMon_SetSeqInputMode(XSysMon *InstancePtr, u32 InputModeChMask)
{
	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * The sequencer must be in the Safe Mode before writing to
	 * these registers. Return XST_FAILURE if the channel sequencer
	 * is enabled.
	 */
	if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SAFE)) {
		return XST_FAILURE;
	}

	/*
	 * Set the input mode for the specified channels in the ADC Channel
	 * Analog-Input Mode Sequencer Registers.
	 */
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ04_OFFSET,
			 (InputModeChMask & XSM_SEQ04_CH_VALID_MASK));

	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ05_OFFSET,
			 (InputModeChMask >> XSM_SEQ_CH_AUX_SHIFT) &
			 XSM_SEQ05_CH_VALID_MASK);

	return XST_SUCCESS;
}
/****************************************************************************/
/**
*
* This function sets the Analog input mode for the specified channels in the
* ADC Channel Analog-Input Mode Sequencer Registers. The sequencer must be in
* the Safe Mode before writing to these registers.
*
* @param	InstancePtr is a pointer to the XSysMon instance.
* @param	InputModeChMask is the bit mask of all the channels for which
*		the input mode is differential mode. Use XSM_SEQ_CH__* defined
*		in xsysmon_hw.h to specify the channel numbers. Differential
*		input mode will be set for bit masks of 1 and unipolar input
*		mode for bit masks of 0.
*		The InputModeChMask is a 32 bit mask that is written to the two
*		16 bit ADC Channel Analog-Input Mode Sequencer Registers.
*
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the ADC Channel Analog-Input Mode Sequencer Registers.
*		- XST_FAILURE if the channel sequencer is enabled.
*
* @note		None.
*
*****************************************************************************/
This function sets the Analog input mode for the specified channels in the
ADC Channel Analog-Input Mode Sequencer Registers. The sequencer must be in
the Safe Mode before writing to these registers.
This function sets the Analog input mode for the specified channels in the ADC Channel Analog - Input Mode Sequencer Registers . The sequencer must be in the Safe Mode before writing to these registers .
int XSysMon_SetSeqInputMode(XSysMon *InstancePtr, u32 InputModeChMask)
{
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SAFE)) {
		return XST_FAILURE;
	}
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ04_OFFSET,
			 (InputModeChMask & XSM_SEQ04_CH_VALID_MASK));
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ05_OFFSET,
			 (InputModeChMask >> XSM_SEQ_CH_AUX_SHIFT) &
			 XSM_SEQ05_CH_VALID_MASK);
	return XST_SUCCESS;
}
int XSysMon_SetSeqInputMode ( XSysMon * InstancePtr , u32 InputModeChMask ) { Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; if ( ( XSysMon_GetSequencerMode ( InstancePtr ) != XSM_SEQ_MODE_SAFE ) ) { return XST_FAILURE ; } XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ04_OFFSET , ( InputModeChMask & XSM_SEQ04_CH_VALID_MASK ) ) ; XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ05_OFFSET , ( InputModeChMask >> XSM_SEQ_CH_AUX_SHIFT ) & XSM_SEQ05_CH_VALID_MASK ) ; return XST_SUCCESS ; }
This function sets the Analog input mode for the specified channels in the
ADC Channel Analog-Input Mode Sequencer Registers.
This function sets the Analog input mode for the specified channels in the ADC Channel Analog - Input Mode Sequencer Registers .
/*
	 * Assert the arguments.
	 */ /*
	 * The sequencer must be in the Safe Mode before writing to
	 * these registers. Return XST_FAILURE if the channel sequencer
	 * is enabled.
	 */ /*
	 * Set the input mode for the specified channels in the ADC Channel
	 * Analog-Input Mode Sequencer Registers.
	 */