XilinxProcessorIPLib/drivers/v_sditx/src/xv_sditx.c
void XV_SdiTx_StreamStart(XV_SdiTx *InstancePtr)
{
	u32 Data;
	XV_SdiTx_MuxPattern MuxPattern;

	for (int StreamId = 0; StreamId < XV_SDITX_MAX_DATASTREAM; StreamId++) {
		XV_SdiTx_SetPayloadId(InstancePtr,
		StreamId,
		InstancePtr->Stream[StreamId].PayloadId);
	}

	Data = XV_SdiTx_ReadReg(InstancePtr->Config.BaseAddress,
				XV_SDITX_MDL_CTRL_OFFSET);
	if (Data & XV_SDITX_MDL_CTRL_C_ST352_MASK) {
		for (int StreamId = 0; StreamId < XV_SDITX_MAX_DATASTREAM;
			StreamId++) {
			XV_SdiTx_SetPayloadId(InstancePtr,
					      StreamId + CHROMA_ST352_REG_OFFSET,
					      InstancePtr->Stream[StreamId].PayloadId);
		}
	}
	switch (InstancePtr->Transport.TMode) {
	case XSDIVID_MODE_SD:
	case XSDIVID_MODE_HD:
		MuxPattern = XV_SDITX_MUX_SD_HD_3GA;
		break;

	case XSDIVID_MODE_3GA:
		if (InstancePtr->Transport.IsLevelB3G == 1) {
			MuxPattern = XV_SDITX_MUX_3GB;
		} else {
			MuxPattern = XV_SDITX_MUX_SD_HD_3GA;
		}
		break;

	case XSDIVID_MODE_3GB:
		MuxPattern = XV_SDITX_MUX_3GB;
		break;

	case XSDIVID_MODE_6G:
		if ((InstancePtr->Stream[0].Video.ColorFormatId == XVIDC_CSF_YCRCB_444) ||
		(InstancePtr->Stream[0].Video.ColorFormatId == XVIDC_CSF_RGB)) {
			MuxPattern = XV_SDITX_MUX_4STREAM_6G;
		} else if (InstancePtr->Stream[0].Video.ColorFormatId == XVIDC_CSF_YCRCB_422) {
			MuxPattern = (InstancePtr->bitdepth == 10) ? XV_SDITX_MUX_8STREAM_6G_12G : XV_SDITX_MUX_4STREAM_6G;
		} else {
			MuxPattern = XV_SDITX_MUX_8STREAM_6G_12G;
		}
		break;

	case XSDIVID_MODE_12G:
		MuxPattern = XV_SDITX_MUX_8STREAM_6G_12G;
		break;

	default:
		MuxPattern = 0;
		break;
	}

#ifndef versal
	/* Workaround for the current limitation of the TX core */
	/* Read back the current mode and fractional information then program
	* it accordingly
	* GTRESET_WORKAROUND e.g. switch from 3g Lvl A 1920x1080p60 to
	* 2048x1080p60.. No GT Ready interrupt will occur since the line/bit
	* rate is same. In the context of the GT Ready interrupt, we are
	* programming the rest of the pipe i.e. the Video bridges. So these
	* bridges will never be started hence no input to SDI Tx IP. So
	* intentionally switch to fractional / other mode and then switch back
	* to required mode. In the ISR XV_SdiTxSs_GtReadyCallback() don't do
	* anything for the WORKAROUND STATE.
	*/
	Data = XV_SdiTx_ReadReg(InstancePtr->Config.BaseAddress,
	(XV_SDITX_MDL_CTRL_OFFSET));
	if (((Data & XV_SDITX_MDL_CTRL_MODE_MASK) >> XV_SDITX_MDL_CTRL_MODE_SHIFT)
			== InstancePtr->Transport.TMode
			&& ((Data & XV_SDITX_MDL_CTRL_M_MASK) >> XV_SDITX_MDL_CTRL_M_SHIFT)
			== InstancePtr->Transport.IsFractional) {

		InstancePtr->State = XV_SDITX_STATE_GTRESETDONE_WORKAROUND;
		XV_SdiTx_StartSdi(InstancePtr, InstancePtr->Transport.TMode,
					~(InstancePtr->Transport.IsFractional),
					MuxPattern);
	}
#endif

	InstancePtr->State = XV_SDITX_STATE_GTRESETDONE_NORMAL;
	XV_SdiTx_StartSdi(InstancePtr, InstancePtr->Transport.TMode,
				InstancePtr->Transport.IsFractional,
				MuxPattern);
}
/*****************************************************************************/
/**
*
* This function starts the TX SDI stream
*
* @param    InstancePtr is a pointer to the XV_SdiTx core instance.
*
* @return	None.
*
* @note     None.
*
******************************************************************************/
This function starts the TX SDI stream
This function starts the TX SDI stream
void XV_SdiTx_StreamStart(XV_SdiTx *InstancePtr)
{
	u32 Data;
	XV_SdiTx_MuxPattern MuxPattern;
	for (int StreamId = 0; StreamId < XV_SDITX_MAX_DATASTREAM; StreamId++) {
		XV_SdiTx_SetPayloadId(InstancePtr,
		StreamId,
		InstancePtr->Stream[StreamId].PayloadId);
	}
	Data = XV_SdiTx_ReadReg(InstancePtr->Config.BaseAddress,
				XV_SDITX_MDL_CTRL_OFFSET);
	if (Data & XV_SDITX_MDL_CTRL_C_ST352_MASK) {
		for (int StreamId = 0; StreamId < XV_SDITX_MAX_DATASTREAM;
			StreamId++) {
			XV_SdiTx_SetPayloadId(InstancePtr,
					      StreamId + CHROMA_ST352_REG_OFFSET,
					      InstancePtr->Stream[StreamId].PayloadId);
		}
	}
	switch (InstancePtr->Transport.TMode) {
	case XSDIVID_MODE_SD:
	case XSDIVID_MODE_HD:
		MuxPattern = XV_SDITX_MUX_SD_HD_3GA;
		break;
	case XSDIVID_MODE_3GA:
		if (InstancePtr->Transport.IsLevelB3G == 1) {
			MuxPattern = XV_SDITX_MUX_3GB;
		} else {
			MuxPattern = XV_SDITX_MUX_SD_HD_3GA;
		}
		break;
	case XSDIVID_MODE_3GB:
		MuxPattern = XV_SDITX_MUX_3GB;
		break;
	case XSDIVID_MODE_6G:
		if ((InstancePtr->Stream[0].Video.ColorFormatId == XVIDC_CSF_YCRCB_444) ||
		(InstancePtr->Stream[0].Video.ColorFormatId == XVIDC_CSF_RGB)) {
			MuxPattern = XV_SDITX_MUX_4STREAM_6G;
		} else if (InstancePtr->Stream[0].Video.ColorFormatId == XVIDC_CSF_YCRCB_422) {
			MuxPattern = (InstancePtr->bitdepth == 10) ? XV_SDITX_MUX_8STREAM_6G_12G : XV_SDITX_MUX_4STREAM_6G;
		} else {
			MuxPattern = XV_SDITX_MUX_8STREAM_6G_12G;
		}
		break;
	case XSDIVID_MODE_12G:
		MuxPattern = XV_SDITX_MUX_8STREAM_6G_12G;
		break;
	default:
		MuxPattern = 0;
		break;
	}
#ifndef versal
	Data = XV_SdiTx_ReadReg(InstancePtr->Config.BaseAddress,
	(XV_SDITX_MDL_CTRL_OFFSET));
	if (((Data & XV_SDITX_MDL_CTRL_MODE_MASK) >> XV_SDITX_MDL_CTRL_MODE_SHIFT)
			== InstancePtr->Transport.TMode
			&& ((Data & XV_SDITX_MDL_CTRL_M_MASK) >> XV_SDITX_MDL_CTRL_M_SHIFT)
			== InstancePtr->Transport.IsFractional) {
		InstancePtr->State = XV_SDITX_STATE_GTRESETDONE_WORKAROUND;
		XV_SdiTx_StartSdi(InstancePtr, InstancePtr->Transport.TMode,
					~(InstancePtr->Transport.IsFractional),
					MuxPattern);
	}
#endif
	InstancePtr->State = XV_SDITX_STATE_GTRESETDONE_NORMAL;
	XV_SdiTx_StartSdi(InstancePtr, InstancePtr->Transport.TMode,
				InstancePtr->Transport.IsFractional,
				MuxPattern);
}
void XV_SdiTx_StreamStart ( XV_SdiTx * InstancePtr ) { u32 Data ; XV_SdiTx_MuxPattern MuxPattern ; for ( int StreamId = 0 ; StreamId < XV_SDITX_MAX_DATASTREAM ; StreamId ++ ) { XV_SdiTx_SetPayloadId ( InstancePtr , StreamId , InstancePtr -> Stream [ StreamId ] . PayloadId ) ; } Data = XV_SdiTx_ReadReg ( InstancePtr -> Config . BaseAddress , XV_SDITX_MDL_CTRL_OFFSET ) ; if ( Data & XV_SDITX_MDL_CTRL_C_ST352_MASK ) { for ( int StreamId = 0 ; StreamId < XV_SDITX_MAX_DATASTREAM ; StreamId ++ ) { XV_SdiTx_SetPayloadId ( InstancePtr , StreamId + CHROMA_ST352_REG_OFFSET , InstancePtr -> Stream [ StreamId ] . PayloadId ) ; } } switch ( InstancePtr -> Transport . TMode ) { case XSDIVID_MODE_SD : case XSDIVID_MODE_HD : MuxPattern = XV_SDITX_MUX_SD_HD_3GA ; break ; case XSDIVID_MODE_3GA : if ( InstancePtr -> Transport . IsLevelB3G == 1 ) { MuxPattern = XV_SDITX_MUX_3GB ; } else { MuxPattern = XV_SDITX_MUX_SD_HD_3GA ; } break ; case XSDIVID_MODE_3GB : MuxPattern = XV_SDITX_MUX_3GB ; break ; case XSDIVID_MODE_6G : if ( ( InstancePtr -> Stream [ 0 ] . Video . ColorFormatId == XVIDC_CSF_YCRCB_444 ) || ( InstancePtr -> Stream [ 0 ] . Video . ColorFormatId == XVIDC_CSF_RGB ) ) { MuxPattern = XV_SDITX_MUX_4STREAM_6G ; } else if ( InstancePtr -> Stream [ 0 ] . Video . ColorFormatId == XVIDC_CSF_YCRCB_422 ) { MuxPattern = ( InstancePtr -> bitdepth == 10 ) ? XV_SDITX_MUX_8STREAM_6G_12G : XV_SDITX_MUX_4STREAM_6G ; } else { MuxPattern = XV_SDITX_MUX_8STREAM_6G_12G ; } break ; case XSDIVID_MODE_12G : MuxPattern = XV_SDITX_MUX_8STREAM_6G_12G ; break ; default : MuxPattern = 0 ; break ; } #ifndef versal Data = XV_SdiTx_ReadReg ( InstancePtr -> Config . BaseAddress , ( XV_SDITX_MDL_CTRL_OFFSET ) ) ; if ( ( ( Data & XV_SDITX_MDL_CTRL_MODE_MASK ) >> XV_SDITX_MDL_CTRL_MODE_SHIFT ) == InstancePtr -> Transport . TMode && ( ( Data & XV_SDITX_MDL_CTRL_M_MASK ) >> XV_SDITX_MDL_CTRL_M_SHIFT ) == InstancePtr -> Transport . IsFractional ) { InstancePtr -> State = XV_SDITX_STATE_GTRESETDONE_WORKAROUND ; XV_SdiTx_StartSdi ( InstancePtr , InstancePtr -> Transport . TMode , ~ ( InstancePtr -> Transport . IsFractional ) , MuxPattern ) ; } #endif InstancePtr -> State = XV_SDITX_STATE_GTRESETDONE_NORMAL ; XV_SdiTx_StartSdi ( InstancePtr , InstancePtr -> Transport . TMode , InstancePtr -> Transport . IsFractional , MuxPattern ) ; }
This function starts the TX SDI stream
This function starts the TX SDI stream
/* Workaround for the current limitation of the TX core */ /* Read back the current mode and fractional information then program
	* it accordingly
	* GTRESET_WORKAROUND e.g. switch from 3g Lvl A 1920x1080p60 to
	* 2048x1080p60.. No GT Ready interrupt will occur since the line/bit
	* rate is same. In the context of the GT Ready interrupt, we are
	* programming the rest of the pipe i.e. the Video bridges. So these
	* bridges will never be started hence no input to SDI Tx IP. So
	* intentionally switch to fractional / other mode and then switch back
	* to required mode. In the ISR XV_SdiTxSs_GtReadyCallback() don't do
	* anything for the WORKAROUND STATE.
	*/