src/dpdk/drivers/net/mlx5/mlx5_txq.c
void
txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
{
	const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
	unsigned int i;

	for (i = 0; (i != elts_n); ++i)
		txq_ctrl->txq.elts[i] = NULL;
	DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
		PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx, elts_n);
	txq_ctrl->txq.elts_head = 0;
	txq_ctrl->txq.elts_tail = 0;
	txq_ctrl->txq.elts_comp = 0;
}
/**
 * Allocate TX queue elements.
 *
 * @param txq_ctrl
 *   Pointer to TX queue structure.
 */
Allocate TX queue elements.
@param txq_ctrl
Pointer to TX queue structure.
Allocate TX queue elements . @param txq_ctrl Pointer to TX queue structure .
void
txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
{
	const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
	unsigned int i;
	for (i = 0; (i != elts_n); ++i)
		txq_ctrl->txq.elts[i] = NULL;
	DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
		PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx, elts_n);
	txq_ctrl->txq.elts_head = 0;
	txq_ctrl->txq.elts_tail = 0;
	txq_ctrl->txq.elts_comp = 0;
}
void txq_alloc_elts ( struct mlx5_txq_ctrl * txq_ctrl ) { const unsigned int elts_n = 1 << txq_ctrl -> txq . elts_n ; unsigned int i ; for ( i = 0 ; ( i != elts_n ) ; ++ i ) txq_ctrl -> txq . elts [ i ] = NULL ; DRV_LOG ( DEBUG , " " , PORT_ID ( txq_ctrl -> priv ) , txq_ctrl -> txq . idx , elts_n ) ; txq_ctrl -> txq . elts_head = 0 ; txq_ctrl -> txq . elts_tail = 0 ; txq_ctrl -> txq . elts_comp = 0 ; }
Allocate TX queue elements.
Allocate TX queue elements .