third_party/cairo/src/drm/cairo-drm-i965-shader.c
static uint32_t
gen4_create_sf_state (i965_device_t *device,
		      i965_shader_t *shader)
{
    struct brw_sf_unit_state *state;
    struct i965_sf_state key, *cache;
    cairo_status_t status;
    uint32_t offset;

    i965_sf_state_init (&key, shader);
    if (i965_sf_state_equal (&key, &device->sf_state))
	return device->sf_state.offset;

    cache = _cairo_hash_table_lookup (device->sf_states, &key.entry);
    if (cache != NULL) {
	offset = cache->offset;
	goto DONE;
    }

    offset = create_sf_kernel (device, shader);

    state = i965_stream_alloc (&device->general, 32, sizeof (*state));
    memset (state, 0, sizeof (*state));

    state->thread0.grf_reg_count = BRW_GRF_BLOCKS (3);
    assert ((offset & 63) == 0);
    state->thread0.kernel_start_pointer = offset >> 6;
    state->sf1.single_program_flow = 1;
    state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
    state->thread3.urb_entry_read_offset = 1;
    state->thread3.dispatch_grf_start_reg = 3;
    state->thread4.max_threads = SF_MAX_THREADS - 1;
    state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
    state->thread4.nr_urb_entries = URB_SF_ENTRIES;
    state->sf6.dest_org_vbias = 0x8;
    state->sf6.dest_org_hbias = 0x8;

    offset = i965_stream_offsetof (&device->general, state);

    cache = _cairo_freelist_alloc (&device->sf_freelist);
    if (likely (cache != NULL)) {
	i965_sf_state_init (cache, shader);
	cache->offset = offset;
	status = _cairo_hash_table_insert (device->sf_states, &cache->entry);
	if (unlikely (status))
	    _cairo_freelist_free (&device->sf_freelist, cache);
    }

  DONE:
    i965_sf_state_init (&device->sf_state, shader);
    device->sf_state.offset = offset;

    return offset;
}
/*
 * Sets up the SF state pointing at an SF kernel.
 *
 * The SF kernel does coord interp: for each attribute,
 * calculate dA/dx and dA/dy.  Hand these interpolation coefficients
 * back to SF which then hands pixels off to WM.
 */
Sets up the SF state pointing at an SF kernel.
The SF kernel does coord interp: for each attribute,
calculate dA/dx and dA/dy.  Hand these interpolation coefficients
back to SF which then hands pixels off to WM.
Sets up the SF state pointing at an SF kernel . The SF kernel does coord interp : for each attribute calculate dA / dx and dA / dy . Hand these interpolation coefficients back to SF which then hands pixels off to WM .
static uint32_t
gen4_create_sf_state (i965_device_t *device,
		      i965_shader_t *shader)
{
    struct brw_sf_unit_state *state;
    struct i965_sf_state key, *cache;
    cairo_status_t status;
    uint32_t offset;
    i965_sf_state_init (&key, shader);
    if (i965_sf_state_equal (&key, &device->sf_state))
	return device->sf_state.offset;
    cache = _cairo_hash_table_lookup (device->sf_states, &key.entry);
    if (cache != NULL) {
	offset = cache->offset;
	goto DONE;
    }
    offset = create_sf_kernel (device, shader);
    state = i965_stream_alloc (&device->general, 32, sizeof (*state));
    memset (state, 0, sizeof (*state));
    state->thread0.grf_reg_count = BRW_GRF_BLOCKS (3);
    assert ((offset & 63) == 0);
    state->thread0.kernel_start_pointer = offset >> 6;
    state->sf1.single_program_flow = 1;
    state->thread3.urb_entry_read_length = 1; 
    state->thread3.urb_entry_read_offset = 1;
    state->thread3.dispatch_grf_start_reg = 3;
    state->thread4.max_threads = SF_MAX_THREADS - 1;
    state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
    state->thread4.nr_urb_entries = URB_SF_ENTRIES;
    state->sf6.dest_org_vbias = 0x8;
    state->sf6.dest_org_hbias = 0x8;
    offset = i965_stream_offsetof (&device->general, state);
    cache = _cairo_freelist_alloc (&device->sf_freelist);
    if (likely (cache != NULL)) {
	i965_sf_state_init (cache, shader);
	cache->offset = offset;
	status = _cairo_hash_table_insert (device->sf_states, &cache->entry);
	if (unlikely (status))
	    _cairo_freelist_free (&device->sf_freelist, cache);
    }
  DONE:
    i965_sf_state_init (&device->sf_state, shader);
    device->sf_state.offset = offset;
    return offset;
}
static uint32_t gen4_create_sf_state ( i965_device_t * device , i965_shader_t * shader ) { struct brw_sf_unit_state * state ; struct i965_sf_state key , * cache ; cairo_status_t status ; uint32_t offset ; i965_sf_state_init ( & key , shader ) ; if ( i965_sf_state_equal ( & key , & device -> sf_state ) ) return device -> sf_state . offset ; cache = _cairo_hash_table_lookup ( device -> sf_states , & key . entry ) ; if ( cache != NULL ) { offset = cache -> offset ; goto DONE ; } offset = create_sf_kernel ( device , shader ) ; state = i965_stream_alloc ( & device -> general , 32 , sizeof ( * state ) ) ; memset ( state , 0 , sizeof ( * state ) ) ; state -> thread0 . grf_reg_count = BRW_GRF_BLOCKS ( 3 ) ; assert ( ( offset & 63 ) == 0 ) ; state -> thread0 . kernel_start_pointer = offset >> 6 ; state -> sf1 . single_program_flow = 1 ; state -> thread3 . urb_entry_read_length = 1 ; state -> thread3 . urb_entry_read_offset = 1 ; state -> thread3 . dispatch_grf_start_reg = 3 ; state -> thread4 . max_threads = SF_MAX_THREADS - 1 ; state -> thread4 . urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1 ; state -> thread4 . nr_urb_entries = URB_SF_ENTRIES ; state -> sf6 . dest_org_vbias = 0x8 ; state -> sf6 . dest_org_hbias = 0x8 ; offset = i965_stream_offsetof ( & device -> general , state ) ; cache = _cairo_freelist_alloc ( & device -> sf_freelist ) ; if ( likely ( cache != NULL ) ) { i965_sf_state_init ( cache , shader ) ; cache -> offset = offset ; status = _cairo_hash_table_insert ( device -> sf_states , & cache -> entry ) ; if ( unlikely ( status ) ) _cairo_freelist_free ( & device -> sf_freelist , cache ) ; } DONE : i965_sf_state_init ( & device -> sf_state , shader ) ; device -> sf_state . offset = offset ; return offset ; }
Sets up the SF state pointing at an SF kernel.
Sets up the SF state pointing at an SF kernel .
/* 1 URB per vertex */