src/dpdk/drivers/net/ixgbe/base/ixgbe_dcb_82599.c
s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw,
			   struct ixgbe_dcb_config *dcb_config)
{
	u32 reg;
	u32 q;

	/* Disable the Tx desc arbiter so that MTQC can be changed */
	reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
	reg |= IXGBE_RTTDCS_ARBDIS;
	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

	reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
	if (dcb_config->num_tcs.pg_tcs == 8) {
		/* Enable DCB for Rx with 8 TCs */
		switch (reg & IXGBE_MRQC_MRQE_MASK) {
		case 0:
		case IXGBE_MRQC_RT4TCEN:
			/* RSS disabled cases */
			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
			      IXGBE_MRQC_RT8TCEN;
			break;
		case IXGBE_MRQC_RSSEN:
		case IXGBE_MRQC_RTRSS4TCEN:
			/* RSS enabled cases */
			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
			      IXGBE_MRQC_RTRSS8TCEN;
			break;
		default:
			/*
			 * Unsupported value, assume stale data,
			 * overwrite no RSS
			 */
			ASSERT(0);
			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
			      IXGBE_MRQC_RT8TCEN;
		}
	}
	if (dcb_config->num_tcs.pg_tcs == 4) {
		/* We support both VT-on and VT-off with 4 TCs. */
		if (dcb_config->vt_mode)
			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
			      IXGBE_MRQC_VMDQRT4TCEN;
		else
			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
			      IXGBE_MRQC_RTRSS4TCEN;
	}
	IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);

	/* Enable DCB for Tx with 8 TCs */
	if (dcb_config->num_tcs.pg_tcs == 8)
		reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
	else {
		/* We support both VT-on and VT-off with 4 TCs. */
		reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
		if (dcb_config->vt_mode)
			reg |= IXGBE_MTQC_VT_ENA;
	}
	IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);

	/* Disable drop for all queues */
	for (q = 0; q < 128; q++)
		IXGBE_WRITE_REG(hw, IXGBE_QDE,
				(IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));

	/* Enable the Tx desc arbiter */
	reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
	reg &= ~IXGBE_RTTDCS_ARBDIS;
	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

	/* Enable Security TX Buffer IFG for DCB */
	reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
	reg |= IXGBE_SECTX_DCB;
	IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);

	return IXGBE_SUCCESS;
}
/**
 * ixgbe_dcb_config_82599 - Configure general DCB parameters
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure general DCB parameters.
 */
Configure general DCB parameters
@hw: pointer to hardware structure
@dcb_config: pointer to ixgbe_dcb_config structure

Configure general DCB parameters.
Configure general DCB parameters @hw : pointer to hardware structure @dcb_config : pointer to ixgbe_dcb_config structure Configure general DCB parameters .
s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw,
			   struct ixgbe_dcb_config *dcb_config)
{
	u32 reg;
	u32 q;
	reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
	reg |= IXGBE_RTTDCS_ARBDIS;
	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
	reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
	if (dcb_config->num_tcs.pg_tcs == 8) {
		switch (reg & IXGBE_MRQC_MRQE_MASK) {
		case 0:
		case IXGBE_MRQC_RT4TCEN:
			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
			      IXGBE_MRQC_RT8TCEN;
			break;
		case IXGBE_MRQC_RSSEN:
		case IXGBE_MRQC_RTRSS4TCEN:
			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
			      IXGBE_MRQC_RTRSS8TCEN;
			break;
		default:
			ASSERT(0);
			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
			      IXGBE_MRQC_RT8TCEN;
		}
	}
	if (dcb_config->num_tcs.pg_tcs == 4) {
		if (dcb_config->vt_mode)
			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
			      IXGBE_MRQC_VMDQRT4TCEN;
		else
			reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
			      IXGBE_MRQC_RTRSS4TCEN;
	}
	IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
	if (dcb_config->num_tcs.pg_tcs == 8)
		reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
	else {
		reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
		if (dcb_config->vt_mode)
			reg |= IXGBE_MTQC_VT_ENA;
	}
	IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
	for (q = 0; q < 128; q++)
		IXGBE_WRITE_REG(hw, IXGBE_QDE,
				(IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
	reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
	reg &= ~IXGBE_RTTDCS_ARBDIS;
	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
	reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
	reg |= IXGBE_SECTX_DCB;
	IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
	return IXGBE_SUCCESS;
}
s32 ixgbe_dcb_config_82599 ( struct ixgbe_hw * hw , struct ixgbe_dcb_config * dcb_config ) { u32 reg ; u32 q ; reg = IXGBE_READ_REG ( hw , IXGBE_RTTDCS ) ; reg |= IXGBE_RTTDCS_ARBDIS ; IXGBE_WRITE_REG ( hw , IXGBE_RTTDCS , reg ) ; reg = IXGBE_READ_REG ( hw , IXGBE_MRQC ) ; if ( dcb_config -> num_tcs . pg_tcs == 8 ) { switch ( reg & IXGBE_MRQC_MRQE_MASK ) { case 0 : case IXGBE_MRQC_RT4TCEN : reg = ( reg & ~ IXGBE_MRQC_MRQE_MASK ) | IXGBE_MRQC_RT8TCEN ; break ; case IXGBE_MRQC_RSSEN : case IXGBE_MRQC_RTRSS4TCEN : reg = ( reg & ~ IXGBE_MRQC_MRQE_MASK ) | IXGBE_MRQC_RTRSS8TCEN ; break ; default : ASSERT ( 0 ) ; reg = ( reg & ~ IXGBE_MRQC_MRQE_MASK ) | IXGBE_MRQC_RT8TCEN ; } } if ( dcb_config -> num_tcs . pg_tcs == 4 ) { if ( dcb_config -> vt_mode ) reg = ( reg & ~ IXGBE_MRQC_MRQE_MASK ) | IXGBE_MRQC_VMDQRT4TCEN ; else reg = ( reg & ~ IXGBE_MRQC_MRQE_MASK ) | IXGBE_MRQC_RTRSS4TCEN ; } IXGBE_WRITE_REG ( hw , IXGBE_MRQC , reg ) ; if ( dcb_config -> num_tcs . pg_tcs == 8 ) reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ ; else { reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ ; if ( dcb_config -> vt_mode ) reg |= IXGBE_MTQC_VT_ENA ; } IXGBE_WRITE_REG ( hw , IXGBE_MTQC , reg ) ; for ( q = 0 ; q < 128 ; q ++ ) IXGBE_WRITE_REG ( hw , IXGBE_QDE , ( IXGBE_QDE_WRITE | ( q << IXGBE_QDE_IDX_SHIFT ) ) ) ; reg = IXGBE_READ_REG ( hw , IXGBE_RTTDCS ) ; reg &= ~ IXGBE_RTTDCS_ARBDIS ; IXGBE_WRITE_REG ( hw , IXGBE_RTTDCS , reg ) ; reg = IXGBE_READ_REG ( hw , IXGBE_SECTXMINIFG ) ; reg |= IXGBE_SECTX_DCB ; IXGBE_WRITE_REG ( hw , IXGBE_SECTXMINIFG , reg ) ; return IXGBE_SUCCESS ; }
ixgbe_dcb_config_82599 - Configure general DCB parameters
 @hw: pointer to hardware structure
 @dcb_config: pointer to ixgbe_dcb_config structure
ixgbe_dcb_config_82599 - Configure general DCB parameters @hw : pointer to hardware structure @dcb_config : pointer to ixgbe_dcb_config structure
/* Disable the Tx desc arbiter so that MTQC can be changed */ /* Enable DCB for Rx with 8 TCs */ /* RSS disabled cases */ /* RSS enabled cases */ /*
			 * Unsupported value, assume stale data,
			 * overwrite no RSS
			 */ /* We support both VT-on and VT-off with 4 TCs. */ /* Enable DCB for Tx with 8 TCs */ /* We support both VT-on and VT-off with 4 TCs. */ /* Disable drop for all queues */ /* Enable the Tx desc arbiter */ /* Enable Security TX Buffer IFG for DCB */