XilinxProcessorIPLib/drivers/dp12txss/examples/src/kcu/xdptxss_kcu105.c
void hpd_pulse_con()
{
    u32 Status;
    u8 lane0_sts;
    u8 lane2_sts;
    u8 lane_set;
    u8 rd_204;
    u8 bw_set;

    Status = XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x202, 1, &lane0_sts);
    Status |= XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x203, 1, &lane2_sts);
    Status |= XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x204, 1, &rd_204);
    Status |= XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x101, 1, &lane_set);
    Status |= XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x100, 1, &bw_set);
    if (Status != XST_SUCCESS) {
       xdbg_printf (XDBG_DEBUG_GENERAL,"Failed to read AUX registers on HPD pulse\r\n");
    }
    bw_set = bw_set & 0x1F;
    lane_set = lane_set & 0x1F;
    rd_204 = rd_204 & 0x1;
    lane0_sts = lane0_sts & 0x55;
    lane2_sts = lane2_sts & 0x55;
#if 0
    xdbg_printf (XDBG_DEBUG_GENERAL,"lanes set : %x\r\n",lane_set);
    xdbg_printf (XDBG_DEBUG_GENERAL,"BW set : %x\r\n",bw_set);
    xdbg_printf (XDBG_DEBUG_GENERAL,"lane0 : %x\r\n",lane0_sts);
    xdbg_printf (XDBG_DEBUG_GENERAL,"lane2 : %x\r\n",lane2_sts);
#endif


#if ENABLE_HDCP_IN_DESIGN
     u8 dev_serv_intr_vec;
     u8 BStatus;
     /* Check for the CP_IRQ interrupt. Check the CP_IRQ
      * bit in the DEVICE_SERVICE_IRQ_VECTOR (0x0201) */
     Status = XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x201, 1, &dev_serv_intr_vec);
     if(dev_serv_intr_vec & 0x04) {
	/* CP_IRQ is set, read the BStatus register */
	XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x068029, 1, &BStatus);
//      xil_printf(" HPD_Pulse: CP_IRQ, (BStatus : %x) \n", BStatus);

	/* Check if the Link Integrity Failure Bit is set */
	if (BStatus & 0x04) {
#if ENABLE_HDCP_FLOW_GUIDE
		xdbg_printf(XDBG_DEBUG_GENERAL,"\033[1m\033[41m\033[37m (*<*)TxLink! \033[0m \n");
#endif
			/* State 5 : Authenticated,
			 * State 6 : Link Integrity Check */
			if(DpTxSsInst.Hdcp1xPtr->Tx.CurrentState == 6 ||
					DpTxSsInst.Hdcp1xPtr->Tx.CurrentState == 5) {
				/* Disable Encryption */
				XDpTxSs_DisableEncryption(&DpTxSsInst,0x1);
				XHdcp1xExample_Poll();

				/* Re-start authentication (the expectation is
				 * that HDCP is already in the authenticated state). */
				xdbg_printf(XDBG_DEBUG_GENERAL,"\033[1m\033[43m\033[34m (*<*)Tx-> \033[0m \n");
				XDpTxSs_Authenticate(&DpTxSsInst);
				XHdcp1xExample_Poll();
				XDpTxSs_EnableEncryption(&DpTxSsInst, 0x1);
				XHdcp1xExample_Poll();
			}
	}

	/* Check if the READY bit is set. */
		if (BStatus & 0x01) {
#if ENABLE_HDCP_FLOW_GUIDE
			xdbg_printf(XDBG_DEBUG_GENERAL,"\033[1m\033[42m\033[37m (*<*)Ready! \033[0m \n");
#endif
			/* DP TX State 8 : Wait-for-Ready */
			if(DpTxSsInst.Hdcp1xPtr->Tx.CurrentState == 8) {
				/* Disable Encryption */
				XDpTxSs_DisableEncryption(&DpTxSsInst,0x1);
//				XHdcp1xExample_Poll();

				/* Re-start authentication (the expectation is
				 * that HDCP is already in the authetnicated state. )*/
				// Post EVENT_DWNSTMREADY instead of authenticate
//				XDpTxSs_ReadDownstream(&DpTxSsInst);
//				XDpTxSs_Authenticate(&DpTxSsInst);
//				XHdcp1xExample_Poll();
			}

		}

	     /* Check if the Ro'_AVAILABLE bit is set. */
		if (BStatus & 0x02) {
#if ENABLE_HDCP_FLOW_GUIDE
		xdbg_printf(XDBG_DEBUG_GENERAL,"\033[1m\033[42m\033[37m (*<*)Ro'_AVAILABLE! \033[0m \n");
#endif
			if ((BStatus & 0x01) != 0x01) {
				XHdcp1xExample_Poll();
			}
		}

		/* Check if CP_IRQ is spurious */
		if (BStatus == 0x00) {
#if ENABLE_HDCP_FLOW_GUIDE
		xdbg_printf(XDBG_DEBUG_GENERAL,"\033[1m\033[41m\033[37m (*<*)Spurious CP_IRQ! \033[0m \n");
#endif
			/* Disable Hpd for a while (100ms) */
			XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,0x144, 0x013);

			/* Wait */
			DpPt_CustomWaitUs(DpTxSsInst.DpPtr, 2000000);

			/* Enable the all DP TX interrupts again */
			XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,0x144, 0x0);
		}

     }
#endif


    //Check if CR, symbol and alignment is lost
    //re-train if required
//     xil_printf ("is rx trained %x\r\n",IsRxTrained);

	if (need_to_retrain_rx == 0) {// && IsRxTrained == 1) {
		if (lane_set == 0x4) {
	        if ((lane0_sts != 0x55) || (lane2_sts != 0x55) || (rd_204 != 1)) {
				 XDpTxSs_SetLinkRate(&DpTxSsInst, bw_set);
				 XDpTxSs_SetLaneCount(&DpTxSsInst, lane_set);
				 if ((only_tx_active == 0) && (training_done == 1)) {
					 Status = DpTxSubsystem_Start(&DpTxSsInst, 1);
					 xdbg_printf (XDBG_DEBUG_GENERAL,"Retraining PT 4..\r\n");
				 } else if (only_tx_active == 1) {
					 Status = DpTxSubsystem_Start(&DpTxSsInst, 0);
					 xdbg_printf (XDBG_DEBUG_GENERAL,"Retraining 4..\r\n");
				 }

	        }
	     } else if (lane_set == 0x2) {
	        if ((lane0_sts != 0x55) || (rd_204 != 1)) {
				 XDpTxSs_SetLinkRate(&DpTxSsInst, bw_set);
				 XDpTxSs_SetLaneCount(&DpTxSsInst, lane_set);
				 if ((only_tx_active == 0) && (training_done == 1)) {
					 Status = DpTxSubsystem_Start(&DpTxSsInst, 1);
					 xdbg_printf (XDBG_DEBUG_GENERAL,"Retraining PT 2..\r\n");
				 } else if (only_tx_active == 1) {
					 Status = DpTxSubsystem_Start(&DpTxSsInst, 0);
					 xdbg_printf (XDBG_DEBUG_GENERAL,"Retraining 2..\r\n");
				 }
	        }

	     } else if (lane_set == 0x1) {
	        if ((lane0_sts != 0x5) || (rd_204 != 1)) {
				 XDpTxSs_SetLinkRate(&DpTxSsInst, bw_set);
				 XDpTxSs_SetLaneCount(&DpTxSsInst, lane_set);
				 if ((only_tx_active == 0) && (training_done == 1)) {
					 Status = DpTxSubsystem_Start(&DpTxSsInst, 1);
					 xdbg_printf (XDBG_DEBUG_GENERAL,"Retraining PT 1..\r\n");
				 } else if (only_tx_active == 1) {
					 Status = DpTxSubsystem_Start(&DpTxSsInst, 0);
					 xdbg_printf (XDBG_DEBUG_GENERAL,"Retraining 1..\r\n");
				 }
	        }
		} else {
			//something went wrong completely.. restart training
			if ((only_tx_active == 0) && (training_done == 1)) {
				Dprx_CheckSetupTx(&DpTxSsInst);
			}
                }
	}
	// clearing the interrupt if it is set
	// XDp_ReadReg(DpTxSsInst.DpPtr->Config.BaseAddr,0x140);
	// enable the interrupts
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,0x144, 0x0);
}
/*****************************************************************************/
/**
*
* This function is called when a Hot-Plug-Detect (HPD) pulse is received by
* the DisplayPort TX Subsystem core.
*
* @param	InstancePtr is a pointer to the XDpTxSs instance.
*
* @return	None.
*
* @note		Use the XDpTxSs_SetCallback driver function to set this
*		function as the handler for HPD pulse.
*
******************************************************************************/
This function is called when a Hot-Plug-Detect (HPD) pulse is received by
the DisplayPort TX Subsystem core.
This function is called when a Hot - Plug - Detect ( HPD ) pulse is received by the DisplayPort TX Subsystem core .
void hpd_pulse_con()
{
    u32 Status;
    u8 lane0_sts;
    u8 lane2_sts;
    u8 lane_set;
    u8 rd_204;
    u8 bw_set;
    Status = XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x202, 1, &lane0_sts);
    Status |= XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x203, 1, &lane2_sts);
    Status |= XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x204, 1, &rd_204);
    Status |= XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x101, 1, &lane_set);
    Status |= XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x100, 1, &bw_set);
    if (Status != XST_SUCCESS) {
       xdbg_printf (XDBG_DEBUG_GENERAL,"Failed to read AUX registers on HPD pulse\r\n");
    }
    bw_set = bw_set & 0x1F;
    lane_set = lane_set & 0x1F;
    rd_204 = rd_204 & 0x1;
    lane0_sts = lane0_sts & 0x55;
    lane2_sts = lane2_sts & 0x55;
#if 0
    xdbg_printf (XDBG_DEBUG_GENERAL,"lanes set : %x\r\n",lane_set);
    xdbg_printf (XDBG_DEBUG_GENERAL,"BW set : %x\r\n",bw_set);
    xdbg_printf (XDBG_DEBUG_GENERAL,"lane0 : %x\r\n",lane0_sts);
    xdbg_printf (XDBG_DEBUG_GENERAL,"lane2 : %x\r\n",lane2_sts);
#endif
#if ENABLE_HDCP_IN_DESIGN
     u8 dev_serv_intr_vec;
     u8 BStatus;
     Status = XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x201, 1, &dev_serv_intr_vec);
     if(dev_serv_intr_vec & 0x04) {
	XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x068029, 1, &BStatus);
	if (BStatus & 0x04) {
#if ENABLE_HDCP_FLOW_GUIDE
		xdbg_printf(XDBG_DEBUG_GENERAL,"\033[1m\033[41m\033[37m (*<*)TxLink! \033[0m \n");
#endif
			if(DpTxSsInst.Hdcp1xPtr->Tx.CurrentState == 6 ||
					DpTxSsInst.Hdcp1xPtr->Tx.CurrentState == 5) {
				XDpTxSs_DisableEncryption(&DpTxSsInst,0x1);
				XHdcp1xExample_Poll();
				xdbg_printf(XDBG_DEBUG_GENERAL,"\033[1m\033[43m\033[34m (*<*)Tx-> \033[0m \n");
				XDpTxSs_Authenticate(&DpTxSsInst);
				XHdcp1xExample_Poll();
				XDpTxSs_EnableEncryption(&DpTxSsInst, 0x1);
				XHdcp1xExample_Poll();
			}
	}
		if (BStatus & 0x01) {
#if ENABLE_HDCP_FLOW_GUIDE
			xdbg_printf(XDBG_DEBUG_GENERAL,"\033[1m\033[42m\033[37m (*<*)Ready! \033[0m \n");
#endif
			if(DpTxSsInst.Hdcp1xPtr->Tx.CurrentState == 8) {
				XDpTxSs_DisableEncryption(&DpTxSsInst,0x1);
			}
		}
		if (BStatus & 0x02) {
#if ENABLE_HDCP_FLOW_GUIDE
		xdbg_printf(XDBG_DEBUG_GENERAL,"\033[1m\033[42m\033[37m (*<*)Ro'_AVAILABLE! \033[0m \n");
#endif
			if ((BStatus & 0x01) != 0x01) {
				XHdcp1xExample_Poll();
			}
		}
		if (BStatus == 0x00) {
#if ENABLE_HDCP_FLOW_GUIDE
		xdbg_printf(XDBG_DEBUG_GENERAL,"\033[1m\033[41m\033[37m (*<*)Spurious CP_IRQ! \033[0m \n");
#endif
			XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,0x144, 0x013);
			DpPt_CustomWaitUs(DpTxSsInst.DpPtr, 2000000);
			XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,0x144, 0x0);
		}
     }
#endif
	if (need_to_retrain_rx == 0) {
		if (lane_set == 0x4) {
	        if ((lane0_sts != 0x55) || (lane2_sts != 0x55) || (rd_204 != 1)) {
				 XDpTxSs_SetLinkRate(&DpTxSsInst, bw_set);
				 XDpTxSs_SetLaneCount(&DpTxSsInst, lane_set);
				 if ((only_tx_active == 0) && (training_done == 1)) {
					 Status = DpTxSubsystem_Start(&DpTxSsInst, 1);
					 xdbg_printf (XDBG_DEBUG_GENERAL,"Retraining PT 4..\r\n");
				 } else if (only_tx_active == 1) {
					 Status = DpTxSubsystem_Start(&DpTxSsInst, 0);
					 xdbg_printf (XDBG_DEBUG_GENERAL,"Retraining 4..\r\n");
				 }
	        }
	     } else if (lane_set == 0x2) {
	        if ((lane0_sts != 0x55) || (rd_204 != 1)) {
				 XDpTxSs_SetLinkRate(&DpTxSsInst, bw_set);
				 XDpTxSs_SetLaneCount(&DpTxSsInst, lane_set);
				 if ((only_tx_active == 0) && (training_done == 1)) {
					 Status = DpTxSubsystem_Start(&DpTxSsInst, 1);
					 xdbg_printf (XDBG_DEBUG_GENERAL,"Retraining PT 2..\r\n");
				 } else if (only_tx_active == 1) {
					 Status = DpTxSubsystem_Start(&DpTxSsInst, 0);
					 xdbg_printf (XDBG_DEBUG_GENERAL,"Retraining 2..\r\n");
				 }
	        }
	     } else if (lane_set == 0x1) {
	        if ((lane0_sts != 0x5) || (rd_204 != 1)) {
				 XDpTxSs_SetLinkRate(&DpTxSsInst, bw_set);
				 XDpTxSs_SetLaneCount(&DpTxSsInst, lane_set);
				 if ((only_tx_active == 0) && (training_done == 1)) {
					 Status = DpTxSubsystem_Start(&DpTxSsInst, 1);
					 xdbg_printf (XDBG_DEBUG_GENERAL,"Retraining PT 1..\r\n");
				 } else if (only_tx_active == 1) {
					 Status = DpTxSubsystem_Start(&DpTxSsInst, 0);
					 xdbg_printf (XDBG_DEBUG_GENERAL,"Retraining 1..\r\n");
				 }
	        }
		} else {
			if ((only_tx_active == 0) && (training_done == 1)) {
				Dprx_CheckSetupTx(&DpTxSsInst);
			}
                }
	}
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,0x144, 0x0);
}
void hpd_pulse_con ( ) { u32 Status ; u8 lane0_sts ; u8 lane2_sts ; u8 lane_set ; u8 rd_204 ; u8 bw_set ; Status = XDp_TxAuxRead ( DpTxSsInst . DpPtr , 0x202 , 1 , & lane0_sts ) ; Status |= XDp_TxAuxRead ( DpTxSsInst . DpPtr , 0x203 , 1 , & lane2_sts ) ; Status |= XDp_TxAuxRead ( DpTxSsInst . DpPtr , 0x204 , 1 , & rd_204 ) ; Status |= XDp_TxAuxRead ( DpTxSsInst . DpPtr , 0x101 , 1 , & lane_set ) ; Status |= XDp_TxAuxRead ( DpTxSsInst . DpPtr , 0x100 , 1 , & bw_set ) ; if ( Status != XST_SUCCESS ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " ) ; } bw_set = bw_set & 0x1F ; lane_set = lane_set & 0x1F ; rd_204 = rd_204 & 0x1 ; lane0_sts = lane0_sts & 0x55 ; lane2_sts = lane2_sts & 0x55 ; #if 0 xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " , lane_set ) ; xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " , bw_set ) ; xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " , lane0_sts ) ; xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " , lane2_sts ) ; #endif #if ENABLE_HDCP_IN_DESIGN u8 dev_serv_intr_vec ; u8 BStatus ; Status = XDp_TxAuxRead ( DpTxSsInst . DpPtr , 0x201 , 1 , & dev_serv_intr_vec ) ; if ( dev_serv_intr_vec & 0x04 ) { XDp_TxAuxRead ( DpTxSsInst . DpPtr , 0x068029 , 1 , & BStatus ) ; if ( BStatus & 0x04 ) { #if ENABLE_HDCP_FLOW_GUIDE xdbg_printf ( XDBG_DEBUG_GENERAL , " \033 \033 \033 \033 \n " ) ; #endif if ( DpTxSsInst . Hdcp1xPtr -> Tx . CurrentState == 6 || DpTxSsInst . Hdcp1xPtr -> Tx . CurrentState == 5 ) { XDpTxSs_DisableEncryption ( & DpTxSsInst , 0x1 ) ; XHdcp1xExample_Poll ( ) ; xdbg_printf ( XDBG_DEBUG_GENERAL , " \033 \033 \033 \033 \n " ) ; XDpTxSs_Authenticate ( & DpTxSsInst ) ; XHdcp1xExample_Poll ( ) ; XDpTxSs_EnableEncryption ( & DpTxSsInst , 0x1 ) ; XHdcp1xExample_Poll ( ) ; } } if ( BStatus & 0x01 ) { #if ENABLE_HDCP_FLOW_GUIDE xdbg_printf ( XDBG_DEBUG_GENERAL , " \033 \033 \033 \033 \n " ) ; #endif if ( DpTxSsInst . Hdcp1xPtr -> Tx . CurrentState == 8 ) { XDpTxSs_DisableEncryption ( & DpTxSsInst , 0x1 ) ; } } if ( BStatus & 0x02 ) { #if ENABLE_HDCP_FLOW_GUIDE xdbg_printf ( XDBG_DEBUG_GENERAL , " \033 \033 \033 \033 \n " ) ; #endif if ( ( BStatus & 0x01 ) != 0x01 ) { XHdcp1xExample_Poll ( ) ; } } if ( BStatus == 0x00 ) { #if ENABLE_HDCP_FLOW_GUIDE xdbg_printf ( XDBG_DEBUG_GENERAL , " \033 \033 \033 \033 \n " ) ; #endif XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , 0x144 , 0x013 ) ; DpPt_CustomWaitUs ( DpTxSsInst . DpPtr , 2000000 ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , 0x144 , 0x0 ) ; } } #endif if ( need_to_retrain_rx == 0 ) { if ( lane_set == 0x4 ) { if ( ( lane0_sts != 0x55 ) || ( lane2_sts != 0x55 ) || ( rd_204 != 1 ) ) { XDpTxSs_SetLinkRate ( & DpTxSsInst , bw_set ) ; XDpTxSs_SetLaneCount ( & DpTxSsInst , lane_set ) ; if ( ( only_tx_active == 0 ) && ( training_done == 1 ) ) { Status = DpTxSubsystem_Start ( & DpTxSsInst , 1 ) ; xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " ) ; } else if ( only_tx_active == 1 ) { Status = DpTxSubsystem_Start ( & DpTxSsInst , 0 ) ; xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " ) ; } } } else if ( lane_set == 0x2 ) { if ( ( lane0_sts != 0x55 ) || ( rd_204 != 1 ) ) { XDpTxSs_SetLinkRate ( & DpTxSsInst , bw_set ) ; XDpTxSs_SetLaneCount ( & DpTxSsInst , lane_set ) ; if ( ( only_tx_active == 0 ) && ( training_done == 1 ) ) { Status = DpTxSubsystem_Start ( & DpTxSsInst , 1 ) ; xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " ) ; } else if ( only_tx_active == 1 ) { Status = DpTxSubsystem_Start ( & DpTxSsInst , 0 ) ; xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " ) ; } } } else if ( lane_set == 0x1 ) { if ( ( lane0_sts != 0x5 ) || ( rd_204 != 1 ) ) { XDpTxSs_SetLinkRate ( & DpTxSsInst , bw_set ) ; XDpTxSs_SetLaneCount ( & DpTxSsInst , lane_set ) ; if ( ( only_tx_active == 0 ) && ( training_done == 1 ) ) { Status = DpTxSubsystem_Start ( & DpTxSsInst , 1 ) ; xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " ) ; } else if ( only_tx_active == 1 ) { Status = DpTxSubsystem_Start ( & DpTxSsInst , 0 ) ; xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " ) ; } } } else { if ( ( only_tx_active == 0 ) && ( training_done == 1 ) ) { Dprx_CheckSetupTx ( & DpTxSsInst ) ; } } } XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , 0x144 , 0x0 ) ; }
This function is called when a Hot-Plug-Detect (HPD) pulse is received by
the DisplayPort TX Subsystem core.
This function is called when a Hot - Plug - Detect ( HPD ) pulse is received by the DisplayPort TX Subsystem core .
/* Check for the CP_IRQ interrupt. Check the CP_IRQ
      * bit in the DEVICE_SERVICE_IRQ_VECTOR (0x0201) */ /* CP_IRQ is set, read the BStatus register */ //      xil_printf(" HPD_Pulse: CP_IRQ, (BStatus : %x) \n", BStatus); /* Check if the Link Integrity Failure Bit is set */ /* State 5 : Authenticated,
			 * State 6 : Link Integrity Check */ /* Disable Encryption */ /* Re-start authentication (the expectation is
				 * that HDCP is already in the authenticated state). */ /* Check if the READY bit is set. */ /* DP TX State 8 : Wait-for-Ready */ /* Disable Encryption */ //				XHdcp1xExample_Poll(); /* Re-start authentication (the expectation is
				 * that HDCP is already in the authetnicated state. )*/ // Post EVENT_DWNSTMREADY instead of authenticate //				XDpTxSs_ReadDownstream(&DpTxSsInst); //				XDpTxSs_Authenticate(&DpTxSsInst); //				XHdcp1xExample_Poll(); /* Check if the Ro'_AVAILABLE bit is set. */ /* Check if CP_IRQ is spurious */ /* Disable Hpd for a while (100ms) */ /* Wait */ /* Enable the all DP TX interrupts again */ //Check if CR, symbol and alignment is lost //re-train if required //     xil_printf ("is rx trained %x\r\n",IsRxTrained); // && IsRxTrained == 1) { //something went wrong completely.. restart training // clearing the interrupt if it is set // XDp_ReadReg(DpTxSsInst.DpPtr->Config.BaseAddr,0x140); // enable the interrupts