XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_hdmi.c
u32 XHdmiphy1_HdmiCpllParam(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir)
{
	u32 Status;
	u64 RefClk = 0;
	u32 *RefClkPtr;
	u32 TxLineRate = 0;
	XHdmiphy1_ChannelId ChannelId = XHDMIPHY1_CHANNEL_ID_CHA;
	u8 Id, Id0, Id1;

	u8 SRArray[] = {1, 3, 5};
	u8 SRIndex;
	u8 SRValue;

	/* Suppress Warning Messages */
	ChId = ChId;

	/* TX is using CPLL. */
	if (Dir == XHDMIPHY1_DIR_TX) {

		/* Set default TX sample rate. */
		InstancePtr->HdmiTxSampleRate = 1;

		/* Set line rate.  */
		RefClkPtr = &InstancePtr->HdmiTxRefClkHz;
		if (InstancePtr->TxHdmi21Cfg.IsEnabled == 0) {
			XHdmiphy1_CfgLineRate(InstancePtr, QuadId, ChannelId,
					(u64)((*RefClkPtr) * 10));
			TxLineRate = (*RefClkPtr)  / 100000;

			/* Check if the line rate is above the 340 Mcsc. */
			if (TxLineRate >= 3400) {
				(*RefClkPtr) = (*RefClkPtr) / 4;
			}
		} else { /* InstancePtr->TxHdmi21Cfg.IsEnabled == 1 */
			XHdmiphy1_CfgLineRate(InstancePtr, QuadId, ChannelId,
					(u64)(InstancePtr->TxHdmi21Cfg.LineRate));
			TxLineRate = InstancePtr->TxHdmi21Cfg.LineRate / 100000;
		}
	}
	/* RX is using CPLL. */
	else {
		RefClkPtr = &InstancePtr->HdmiRxRefClkHz;

		/* Check if the reference clock is not below the minimum CPLL
		 * input frequency. */
		if ((*RefClkPtr) >=
				(GetGtHdmiPtr(InstancePtr))->CpllRefClkMin) {
			RefClk = (*RefClkPtr);

			/* Scaled linerate */
			if (InstancePtr->RxHdmi21Cfg.IsEnabled == 0) {
				if (InstancePtr->HdmiRxTmdsClockRatio) {
					XHdmiphy1_CfgLineRate(InstancePtr, QuadId,
						ChannelId, (RefClk * 40));
				}
				else {
					XHdmiphy1_CfgLineRate(InstancePtr, QuadId,
						ChannelId, (RefClk * 10));
				}
			} else { /* InstancePtr->RxHdmi21Cfg.IsEnabled == 1 */
				XHdmiphy1_CfgLineRate(InstancePtr, QuadId,
					ChannelId, InstancePtr->RxHdmi21Cfg.LineRate);
			}

			/* Clear DRU is enabled flag. */
			InstancePtr->HdmiRxDruIsEnabled = 0;

			/* Set RX data width. */
			XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA,
					&Id0, &Id1);
			for (Id = Id0; Id <= Id1; Id++) {
				if (InstancePtr->Config.TransceiverWidth == 2) {
					InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(Id)].
						RxDataWidth = 20;
					InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(Id)].
						RxIntDataWidth = 2;
				}
				else {
					InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(Id)].
						RxDataWidth = 40;
					InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(Id)].
						RxIntDataWidth = 4;
				}
			}

		}
		/* The reference clock is below the minimum frequency thus
		 * select the DRU. */
		else {
			if (InstancePtr->Config.DruIsPresent) {
				/* Return config not found error when TMDS ratio is 1/40 */
                if (InstancePtr->HdmiRxTmdsClockRatio) {
                    XHdmiphy1_LogWrite(InstancePtr,
                        XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR, 1);
                    XHdmiphy1_ErrorHandler(InstancePtr);
                    return (XST_FAILURE);
                }

                RefClk = XHdmiphy1_DruGetRefClkFreqHz(InstancePtr);
                /* Check DRU frequency */
			if (RefClk == XST_FAILURE) {
				XHdmiphy1_LogWrite(InstancePtr,
						XHDMIPHY1_LOG_EVT_DRU_CLK_ERR, 1);
				XHdmiphy1_ErrorHandler(InstancePtr);
				return (XST_FAILURE);
			}

				/* Round input frequency to 10 kHz. */
				RefClk = (RefClk+5000) / 10000;
				RefClk = RefClk * 10000;

				/* Set the DRU to operate at a linerate of
				 * 2.5 Gbps. */
				XHdmiphy1_CfgLineRate(InstancePtr, QuadId,
						ChannelId,
						(GetGtHdmiPtr(InstancePtr))->
						DruLineRate);

				/* Set DRU is enabled flag. */
				InstancePtr->HdmiRxDruIsEnabled = 1;

				/* Set RX data width. */
				XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA,
						&Id0, &Id1);
				for (Id = Id0; Id <= Id1; Id++) {
					InstancePtr->Quads[QuadId].Plls[
						XHDMIPHY1_CH2IDX(Id)].
						RxDataWidth = 20;
					InstancePtr->Quads[QuadId].Plls[
						XHDMIPHY1_CH2IDX(Id)].
						RxIntDataWidth = 2;
				}

				if (TxLineRate > (((GetGtHdmiPtr(InstancePtr))
						->DruLineRate) / 1000000)) {
					XHdmiphy1_LogWrite(InstancePtr,
							XHDMIPHY1_LOG_EVT_VD_NOT_SPRTD_ERR, 1);
                    XHdmiphy1_ErrorHandler(InstancePtr);
                    return (XST_FAILURE);
				}
			}
			else {
				/* Return config not found error when TMDS ratio is 1/40 */
                if (InstancePtr->HdmiRxTmdsClockRatio) {
                    XHdmiphy1_LogWrite(InstancePtr,
                        XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR, 1);
                    XHdmiphy1_ErrorHandler(InstancePtr);
                }
                else {
					XHdmiphy1_LogWrite(InstancePtr,
							XHDMIPHY1_LOG_EVT_NO_DRU, 1);
					XHdmiphy1_ErrorHandler(InstancePtr);
                }
                return (XST_FAILURE);
			}
		}
	}

	/* Try different sample rates. */
	for (SRIndex = 0; SRIndex < sizeof(SRArray); SRIndex++) {
		/* Only use oversampling when then TX is using the CPLL. */
		if (Dir == XHDMIPHY1_DIR_TX) {
			SRValue = SRArray[SRIndex];

			if (InstancePtr->TxHdmi21Cfg.IsEnabled == 0) {
				/* Multiply the reference clock with the sample rate
				 * value. */
				RefClk = ((*RefClkPtr) * SRValue);

				/* Calculate scaled line rate. */
				if (TxLineRate >= 3400) {
					XHdmiphy1_CfgLineRate(InstancePtr, QuadId,
						ChannelId, (RefClk * 40));
				}
				else {
					XHdmiphy1_CfgLineRate(InstancePtr, QuadId,
						ChannelId, (RefClk * 10));
				}
			}
			else { /* InstancePtr->TxHdmi21Cfg.IsEnabled == 1 */
				RefClk = (*RefClkPtr);
			}
		}
		/* For all other reference clocks force sample rate to one. */
		else {
			SRValue = 1;
		}

		Status = XHdmiphy1_ClkCalcParams(InstancePtr, QuadId,
					ChannelId, Dir, RefClk);
		if (Status == (XST_SUCCESS)) {
			/* Only execute when the TX is using the QPLL. */
			if (Dir == XHDMIPHY1_DIR_TX) {
				InstancePtr->HdmiTxSampleRate = SRValue;
				(*RefClkPtr) = (*RefClkPtr) * SRValue;
			}

			/* Check Userclock Frequency */
            /* (300 MHz + 0.5%) + 10 KHz (Clkdet accuracy) */
			if (301500000 <	(XHdmiphy1_GetLineRateHz(InstancePtr, QuadId,
							XHDMIPHY1_CHANNEL_ID_CH1) /
					(InstancePtr->Config.TransceiverWidth * 10))) {
				XHdmiphy1_LogWrite(InstancePtr,
						XHDMIPHY1_LOG_EVT_USRCLK_ERR, 1);
				XHdmiphy1_ErrorHandler(InstancePtr);
				return (XST_FAILURE);
			}

			return (XST_SUCCESS);
		}
	}

	XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR, 1);
	XHdmiphy1_ErrorHandler(InstancePtr);
	return (XST_FAILURE);
}
/*****************************************************************************/
/**
* This function calculates the CPLL parameters.
*
* @param	InstancePtr is a pointer to the HDMI GT core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
* @param	Dir is an indicator for RX or TX.
*
* @return
*		- XST_SUCCESS if calculated CPLL parameters updated
*		  successfully.
*		- XST_FAILURE if parameters not updated.
*
* @note		None.
*
******************************************************************************/
This function calculates the CPLL parameters.
This function calculates the CPLL parameters .
u32 XHdmiphy1_HdmiCpllParam(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir)
{
	u32 Status;
	u64 RefClk = 0;
	u32 *RefClkPtr;
	u32 TxLineRate = 0;
	XHdmiphy1_ChannelId ChannelId = XHDMIPHY1_CHANNEL_ID_CHA;
	u8 Id, Id0, Id1;
	u8 SRArray[] = {1, 3, 5};
	u8 SRIndex;
	u8 SRValue;
	ChId = ChId;
	if (Dir == XHDMIPHY1_DIR_TX) {
		InstancePtr->HdmiTxSampleRate = 1;
		RefClkPtr = &InstancePtr->HdmiTxRefClkHz;
		if (InstancePtr->TxHdmi21Cfg.IsEnabled == 0) {
			XHdmiphy1_CfgLineRate(InstancePtr, QuadId, ChannelId,
					(u64)((*RefClkPtr) * 10));
			TxLineRate = (*RefClkPtr)  / 100000;
			if (TxLineRate >= 3400) {
				(*RefClkPtr) = (*RefClkPtr) / 4;
			}
		} else { 
			XHdmiphy1_CfgLineRate(InstancePtr, QuadId, ChannelId,
					(u64)(InstancePtr->TxHdmi21Cfg.LineRate));
			TxLineRate = InstancePtr->TxHdmi21Cfg.LineRate / 100000;
		}
	}
	else {
		RefClkPtr = &InstancePtr->HdmiRxRefClkHz;
		if ((*RefClkPtr) >=
				(GetGtHdmiPtr(InstancePtr))->CpllRefClkMin) {
			RefClk = (*RefClkPtr);
			if (InstancePtr->RxHdmi21Cfg.IsEnabled == 0) {
				if (InstancePtr->HdmiRxTmdsClockRatio) {
					XHdmiphy1_CfgLineRate(InstancePtr, QuadId,
						ChannelId, (RefClk * 40));
				}
				else {
					XHdmiphy1_CfgLineRate(InstancePtr, QuadId,
						ChannelId, (RefClk * 10));
				}
			} else { 
				XHdmiphy1_CfgLineRate(InstancePtr, QuadId,
					ChannelId, InstancePtr->RxHdmi21Cfg.LineRate);
			}
			InstancePtr->HdmiRxDruIsEnabled = 0;
			XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA,
					&Id0, &Id1);
			for (Id = Id0; Id <= Id1; Id++) {
				if (InstancePtr->Config.TransceiverWidth == 2) {
					InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(Id)].
						RxDataWidth = 20;
					InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(Id)].
						RxIntDataWidth = 2;
				}
				else {
					InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(Id)].
						RxDataWidth = 40;
					InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(Id)].
						RxIntDataWidth = 4;
				}
			}
		}
		else {
			if (InstancePtr->Config.DruIsPresent) {
                if (InstancePtr->HdmiRxTmdsClockRatio) {
                    XHdmiphy1_LogWrite(InstancePtr,
                        XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR, 1);
                    XHdmiphy1_ErrorHandler(InstancePtr);
                    return (XST_FAILURE);
                }
                RefClk = XHdmiphy1_DruGetRefClkFreqHz(InstancePtr);
			if (RefClk == XST_FAILURE) {
				XHdmiphy1_LogWrite(InstancePtr,
						XHDMIPHY1_LOG_EVT_DRU_CLK_ERR, 1);
				XHdmiphy1_ErrorHandler(InstancePtr);
				return (XST_FAILURE);
			}
				RefClk = (RefClk+5000) / 10000;
				RefClk = RefClk * 10000;
				XHdmiphy1_CfgLineRate(InstancePtr, QuadId,
						ChannelId,
						(GetGtHdmiPtr(InstancePtr))->
						DruLineRate);
				InstancePtr->HdmiRxDruIsEnabled = 1;
				XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA,
						&Id0, &Id1);
				for (Id = Id0; Id <= Id1; Id++) {
					InstancePtr->Quads[QuadId].Plls[
						XHDMIPHY1_CH2IDX(Id)].
						RxDataWidth = 20;
					InstancePtr->Quads[QuadId].Plls[
						XHDMIPHY1_CH2IDX(Id)].
						RxIntDataWidth = 2;
				}
				if (TxLineRate > (((GetGtHdmiPtr(InstancePtr))
						->DruLineRate) / 1000000)) {
					XHdmiphy1_LogWrite(InstancePtr,
							XHDMIPHY1_LOG_EVT_VD_NOT_SPRTD_ERR, 1);
                    XHdmiphy1_ErrorHandler(InstancePtr);
                    return (XST_FAILURE);
				}
			}
			else {
                if (InstancePtr->HdmiRxTmdsClockRatio) {
                    XHdmiphy1_LogWrite(InstancePtr,
                        XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR, 1);
                    XHdmiphy1_ErrorHandler(InstancePtr);
                }
                else {
					XHdmiphy1_LogWrite(InstancePtr,
							XHDMIPHY1_LOG_EVT_NO_DRU, 1);
					XHdmiphy1_ErrorHandler(InstancePtr);
                }
                return (XST_FAILURE);
			}
		}
	}
	for (SRIndex = 0; SRIndex < sizeof(SRArray); SRIndex++) {
		if (Dir == XHDMIPHY1_DIR_TX) {
			SRValue = SRArray[SRIndex];
			if (InstancePtr->TxHdmi21Cfg.IsEnabled == 0) {
				RefClk = ((*RefClkPtr) * SRValue);
				if (TxLineRate >= 3400) {
					XHdmiphy1_CfgLineRate(InstancePtr, QuadId,
						ChannelId, (RefClk * 40));
				}
				else {
					XHdmiphy1_CfgLineRate(InstancePtr, QuadId,
						ChannelId, (RefClk * 10));
				}
			}
			else { 
				RefClk = (*RefClkPtr);
			}
		}
		else {
			SRValue = 1;
		}
		Status = XHdmiphy1_ClkCalcParams(InstancePtr, QuadId,
					ChannelId, Dir, RefClk);
		if (Status == (XST_SUCCESS)) {
			if (Dir == XHDMIPHY1_DIR_TX) {
				InstancePtr->HdmiTxSampleRate = SRValue;
				(*RefClkPtr) = (*RefClkPtr) * SRValue;
			}
			if (301500000 <	(XHdmiphy1_GetLineRateHz(InstancePtr, QuadId,
							XHDMIPHY1_CHANNEL_ID_CH1) /
					(InstancePtr->Config.TransceiverWidth * 10))) {
				XHdmiphy1_LogWrite(InstancePtr,
						XHDMIPHY1_LOG_EVT_USRCLK_ERR, 1);
				XHdmiphy1_ErrorHandler(InstancePtr);
				return (XST_FAILURE);
			}
			return (XST_SUCCESS);
		}
	}
	XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR, 1);
	XHdmiphy1_ErrorHandler(InstancePtr);
	return (XST_FAILURE);
}
u32 XHdmiphy1_HdmiCpllParam ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId , XHdmiphy1_DirectionType Dir ) { u32 Status ; u64 RefClk = 0 ; u32 * RefClkPtr ; u32 TxLineRate = 0 ; XHdmiphy1_ChannelId ChannelId = XHDMIPHY1_CHANNEL_ID_CHA ; u8 Id , Id0 , Id1 ; u8 SRArray [ ] = { 1 , 3 , 5 } ; u8 SRIndex ; u8 SRValue ; ChId = ChId ; if ( Dir == XHDMIPHY1_DIR_TX ) { InstancePtr -> HdmiTxSampleRate = 1 ; RefClkPtr = & InstancePtr -> HdmiTxRefClkHz ; if ( InstancePtr -> TxHdmi21Cfg . IsEnabled == 0 ) { XHdmiphy1_CfgLineRate ( InstancePtr , QuadId , ChannelId , ( u64 ) ( ( * RefClkPtr ) * 10 ) ) ; TxLineRate = ( * RefClkPtr ) / 100000 ; if ( TxLineRate >= 3400 ) { ( * RefClkPtr ) = ( * RefClkPtr ) / 4 ; } } else { XHdmiphy1_CfgLineRate ( InstancePtr , QuadId , ChannelId , ( u64 ) ( InstancePtr -> TxHdmi21Cfg . LineRate ) ) ; TxLineRate = InstancePtr -> TxHdmi21Cfg . LineRate / 100000 ; } } else { RefClkPtr = & InstancePtr -> HdmiRxRefClkHz ; if ( ( * RefClkPtr ) >= ( GetGtHdmiPtr ( InstancePtr ) ) -> CpllRefClkMin ) { RefClk = ( * RefClkPtr ) ; if ( InstancePtr -> RxHdmi21Cfg . IsEnabled == 0 ) { if ( InstancePtr -> HdmiRxTmdsClockRatio ) { XHdmiphy1_CfgLineRate ( InstancePtr , QuadId , ChannelId , ( RefClk * 40 ) ) ; } else { XHdmiphy1_CfgLineRate ( InstancePtr , QuadId , ChannelId , ( RefClk * 10 ) ) ; } } else { XHdmiphy1_CfgLineRate ( InstancePtr , QuadId , ChannelId , InstancePtr -> RxHdmi21Cfg . LineRate ) ; } InstancePtr -> HdmiRxDruIsEnabled = 0 ; XHdmiphy1_Ch2Ids ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { if ( InstancePtr -> Config . TransceiverWidth == 2 ) { InstancePtr -> Quads [ QuadId ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . RxDataWidth = 20 ; InstancePtr -> Quads [ QuadId ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . RxIntDataWidth = 2 ; } else { InstancePtr -> Quads [ QuadId ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . RxDataWidth = 40 ; InstancePtr -> Quads [ QuadId ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . RxIntDataWidth = 4 ; } } } else { if ( InstancePtr -> Config . DruIsPresent ) { if ( InstancePtr -> HdmiRxTmdsClockRatio ) { XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR , 1 ) ; XHdmiphy1_ErrorHandler ( InstancePtr ) ; return ( XST_FAILURE ) ; } RefClk = XHdmiphy1_DruGetRefClkFreqHz ( InstancePtr ) ; if ( RefClk == XST_FAILURE ) { XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_DRU_CLK_ERR , 1 ) ; XHdmiphy1_ErrorHandler ( InstancePtr ) ; return ( XST_FAILURE ) ; } RefClk = ( RefClk + 5000 ) / 10000 ; RefClk = RefClk * 10000 ; XHdmiphy1_CfgLineRate ( InstancePtr , QuadId , ChannelId , ( GetGtHdmiPtr ( InstancePtr ) ) -> DruLineRate ) ; InstancePtr -> HdmiRxDruIsEnabled = 1 ; XHdmiphy1_Ch2Ids ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ QuadId ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . RxDataWidth = 20 ; InstancePtr -> Quads [ QuadId ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . RxIntDataWidth = 2 ; } if ( TxLineRate > ( ( ( GetGtHdmiPtr ( InstancePtr ) ) -> DruLineRate ) / 1000000 ) ) { XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_VD_NOT_SPRTD_ERR , 1 ) ; XHdmiphy1_ErrorHandler ( InstancePtr ) ; return ( XST_FAILURE ) ; } } else { if ( InstancePtr -> HdmiRxTmdsClockRatio ) { XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR , 1 ) ; XHdmiphy1_ErrorHandler ( InstancePtr ) ; } else { XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_NO_DRU , 1 ) ; XHdmiphy1_ErrorHandler ( InstancePtr ) ; } return ( XST_FAILURE ) ; } } } for ( SRIndex = 0 ; SRIndex < sizeof ( SRArray ) ; SRIndex ++ ) { if ( Dir == XHDMIPHY1_DIR_TX ) { SRValue = SRArray [ SRIndex ] ; if ( InstancePtr -> TxHdmi21Cfg . IsEnabled == 0 ) { RefClk = ( ( * RefClkPtr ) * SRValue ) ; if ( TxLineRate >= 3400 ) { XHdmiphy1_CfgLineRate ( InstancePtr , QuadId , ChannelId , ( RefClk * 40 ) ) ; } else { XHdmiphy1_CfgLineRate ( InstancePtr , QuadId , ChannelId , ( RefClk * 10 ) ) ; } } else { RefClk = ( * RefClkPtr ) ; } } else { SRValue = 1 ; } Status = XHdmiphy1_ClkCalcParams ( InstancePtr , QuadId , ChannelId , Dir , RefClk ) ; if ( Status == ( XST_SUCCESS ) ) { if ( Dir == XHDMIPHY1_DIR_TX ) { InstancePtr -> HdmiTxSampleRate = SRValue ; ( * RefClkPtr ) = ( * RefClkPtr ) * SRValue ; } if ( 301500000 < ( XHdmiphy1_GetLineRateHz ( InstancePtr , QuadId , XHDMIPHY1_CHANNEL_ID_CH1 ) / ( InstancePtr -> Config . TransceiverWidth * 10 ) ) ) { XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_USRCLK_ERR , 1 ) ; XHdmiphy1_ErrorHandler ( InstancePtr ) ; return ( XST_FAILURE ) ; } return ( XST_SUCCESS ) ; } } XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_GT_CPLL_CFG_ERR , 1 ) ; XHdmiphy1_ErrorHandler ( InstancePtr ) ; return ( XST_FAILURE ) ; }
This function calculates the CPLL parameters.
This function calculates the CPLL parameters .
/* Suppress Warning Messages */ /* TX is using CPLL. */ /* Set default TX sample rate. */ /* Set line rate.  */ /* Check if the line rate is above the 340 Mcsc. */ /* InstancePtr->TxHdmi21Cfg.IsEnabled == 1 */ /* RX is using CPLL. */ /* Check if the reference clock is not below the minimum CPLL
		 * input frequency. */ /* Scaled linerate */ /* InstancePtr->RxHdmi21Cfg.IsEnabled == 1 */ /* Clear DRU is enabled flag. */ /* Set RX data width. */ /* The reference clock is below the minimum frequency thus
		 * select the DRU. */ /* Return config not found error when TMDS ratio is 1/40 */ /* Check DRU frequency */ /* Round input frequency to 10 kHz. */ /* Set the DRU to operate at a linerate of
				 * 2.5 Gbps. */ /* Set DRU is enabled flag. */ /* Set RX data width. */ /* Return config not found error when TMDS ratio is 1/40 */ /* Try different sample rates. */ /* Only use oversampling when then TX is using the CPLL. */ /* Multiply the reference clock with the sample rate
				 * value. */ /* Calculate scaled line rate. */ /* InstancePtr->TxHdmi21Cfg.IsEnabled == 1 */ /* For all other reference clocks force sample rate to one. */ /* Only execute when the TX is using the QPLL. */ /* Check Userclock Frequency */ /* (300 MHz + 0.5%) + 10 KHz (Clkdet accuracy) */