src/dpdk/drivers/net/txgbe/txgbe_rxtx.c
static int
txgbe_set_rsc(struct rte_eth_dev *dev)
{
	struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
	struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
	struct rte_eth_dev_info dev_info = { 0 };
	bool rsc_capable = false;
	uint16_t i;
	uint32_t rdrxctl;
	uint32_t rfctl;

	/* Sanity check */
	dev->dev_ops->dev_infos_get(dev, &dev_info);
	if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
		rsc_capable = true;

	if (!rsc_capable && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
		PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
				   "support it");
		return -EINVAL;
	}

	/* RSC global configuration */

	if ((rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC) &&
	     (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
		PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
				    "is disabled");
		return -EINVAL;
	}

	rfctl = rd32(hw, TXGBE_PSRCTL);
	if (rsc_capable && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
		rfctl &= ~TXGBE_PSRCTL_RSCDIA;
	else
		rfctl |= TXGBE_PSRCTL_RSCDIA;
	wr32(hw, TXGBE_PSRCTL, rfctl);

	/* If LRO hasn't been requested - we are done here. */
	if (!(rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
		return 0;

	/* Set PSRCTL.RSCACK bit */
	rdrxctl = rd32(hw, TXGBE_PSRCTL);
	rdrxctl |= TXGBE_PSRCTL_RSCACK;
	wr32(hw, TXGBE_PSRCTL, rdrxctl);

	/* Per-queue RSC configuration */
	for (i = 0; i < dev->data->nb_rx_queues; i++) {
		struct txgbe_rx_queue *rxq = dev->data->rx_queues[i];
		uint32_t srrctl =
			rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
		uint32_t psrtype =
			rd32(hw, TXGBE_POOLRSS(rxq->reg_idx));
		uint32_t eitr =
			rd32(hw, TXGBE_ITR(rxq->reg_idx));

		/*
		 * txgbe PMD doesn't support header-split at the moment.
		 */
		srrctl &= ~TXGBE_RXCFG_HDRLEN_MASK;
		srrctl |= TXGBE_RXCFG_HDRLEN(128);

		/*
		 * TODO: Consider setting the Receive Descriptor Minimum
		 * Threshold Size for an RSC case. This is not an obviously
		 * beneficiary option but the one worth considering...
		 */

		srrctl |= TXGBE_RXCFG_RSCENA;
		srrctl &= ~TXGBE_RXCFG_RSCMAX_MASK;
		srrctl |= txgbe_get_rscctl_maxdesc(rxq->mb_pool);
		psrtype |= TXGBE_POOLRSS_L4HDR;

		/*
		 * RSC: Set ITR interval corresponding to 2K ints/s.
		 *
		 * Full-sized RSC aggregations for a 10Gb/s link will
		 * arrive at about 20K aggregation/s rate.
		 *
		 * 2K inst/s rate will make only 10% of the
		 * aggregations to be closed due to the interrupt timer
		 * expiration for a streaming at wire-speed case.
		 *
		 * For a sparse streaming case this setting will yield
		 * at most 500us latency for a single RSC aggregation.
		 */
		eitr &= ~TXGBE_ITR_IVAL_MASK;
		eitr |= TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT);
		eitr |= TXGBE_ITR_WRDSA;

		wr32(hw, TXGBE_RXCFG(rxq->reg_idx), srrctl);
		wr32(hw, TXGBE_POOLRSS(rxq->reg_idx), psrtype);
		wr32(hw, TXGBE_ITR(rxq->reg_idx), eitr);

		/*
		 * RSC requires the mapping of the queue to the
		 * interrupt vector.
		 */
		txgbe_set_ivar_map(hw, 0, rxq->reg_idx, i);
	}

	dev->data->lro = 1;

	PMD_INIT_LOG(DEBUG, "enabling LRO mode");

	return 0;
}
/**
 * txgbe_set_rsc - configure RSC related port HW registers
 *
 * Configures the port's RSC related registers.
 *
 * @dev port handle
 *
 * Returns 0 in case of success or a non-zero error code
 */
configure RSC related port HW registers
Configures the port's RSC related registers.

@dev port handle

Returns 0 in case of success or a non-zero error code
configure RSC related port HW registers Configures the port ' s RSC related registers . @dev port handle Returns 0 in case of success or a non - zero error code
static int
txgbe_set_rsc(struct rte_eth_dev *dev)
{
	struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
	struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
	struct rte_eth_dev_info dev_info = { 0 };
	bool rsc_capable = false;
	uint16_t i;
	uint32_t rdrxctl;
	uint32_t rfctl;
	dev->dev_ops->dev_infos_get(dev, &dev_info);
	if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
		rsc_capable = true;
	if (!rsc_capable && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
		PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
				   "support it");
		return -EINVAL;
	}
	if ((rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC) &&
	     (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
		PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
				    "is disabled");
		return -EINVAL;
	}
	rfctl = rd32(hw, TXGBE_PSRCTL);
	if (rsc_capable && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
		rfctl &= ~TXGBE_PSRCTL_RSCDIA;
	else
		rfctl |= TXGBE_PSRCTL_RSCDIA;
	wr32(hw, TXGBE_PSRCTL, rfctl);
	if (!(rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
		return 0;
	rdrxctl = rd32(hw, TXGBE_PSRCTL);
	rdrxctl |= TXGBE_PSRCTL_RSCACK;
	wr32(hw, TXGBE_PSRCTL, rdrxctl);
	for (i = 0; i < dev->data->nb_rx_queues; i++) {
		struct txgbe_rx_queue *rxq = dev->data->rx_queues[i];
		uint32_t srrctl =
			rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
		uint32_t psrtype =
			rd32(hw, TXGBE_POOLRSS(rxq->reg_idx));
		uint32_t eitr =
			rd32(hw, TXGBE_ITR(rxq->reg_idx));
		srrctl &= ~TXGBE_RXCFG_HDRLEN_MASK;
		srrctl |= TXGBE_RXCFG_HDRLEN(128);
		srrctl |= TXGBE_RXCFG_RSCENA;
		srrctl &= ~TXGBE_RXCFG_RSCMAX_MASK;
		srrctl |= txgbe_get_rscctl_maxdesc(rxq->mb_pool);
		psrtype |= TXGBE_POOLRSS_L4HDR;
		eitr &= ~TXGBE_ITR_IVAL_MASK;
		eitr |= TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT);
		eitr |= TXGBE_ITR_WRDSA;
		wr32(hw, TXGBE_RXCFG(rxq->reg_idx), srrctl);
		wr32(hw, TXGBE_POOLRSS(rxq->reg_idx), psrtype);
		wr32(hw, TXGBE_ITR(rxq->reg_idx), eitr);
		txgbe_set_ivar_map(hw, 0, rxq->reg_idx, i);
	}
	dev->data->lro = 1;
	PMD_INIT_LOG(DEBUG, "enabling LRO mode");
	return 0;
}
static int txgbe_set_rsc ( struct rte_eth_dev * dev ) { struct rte_eth_rxmode * rx_conf = & dev -> data -> dev_conf . rxmode ; struct txgbe_hw * hw = TXGBE_DEV_HW ( dev ) ; struct rte_eth_dev_info dev_info = { 0 } ; bool rsc_capable = false ; uint16_t i ; uint32_t rdrxctl ; uint32_t rfctl ; dev -> dev_ops -> dev_infos_get ( dev , & dev_info ) ; if ( dev_info . rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO ) rsc_capable = true ; if ( ! rsc_capable && ( rx_conf -> offloads & DEV_RX_OFFLOAD_TCP_LRO ) ) { PMD_INIT_LOG ( CRIT , " " " " ) ; return - EINVAL ; } if ( ( rx_conf -> offloads & DEV_RX_OFFLOAD_KEEP_CRC ) && ( rx_conf -> offloads & DEV_RX_OFFLOAD_TCP_LRO ) ) { PMD_INIT_LOG ( CRIT , " " " " ) ; return - EINVAL ; } rfctl = rd32 ( hw , TXGBE_PSRCTL ) ; if ( rsc_capable && ( rx_conf -> offloads & DEV_RX_OFFLOAD_TCP_LRO ) ) rfctl &= ~ TXGBE_PSRCTL_RSCDIA ; else rfctl |= TXGBE_PSRCTL_RSCDIA ; wr32 ( hw , TXGBE_PSRCTL , rfctl ) ; if ( ! ( rx_conf -> offloads & DEV_RX_OFFLOAD_TCP_LRO ) ) return 0 ; rdrxctl = rd32 ( hw , TXGBE_PSRCTL ) ; rdrxctl |= TXGBE_PSRCTL_RSCACK ; wr32 ( hw , TXGBE_PSRCTL , rdrxctl ) ; for ( i = 0 ; i < dev -> data -> nb_rx_queues ; i ++ ) { struct txgbe_rx_queue * rxq = dev -> data -> rx_queues [ i ] ; uint32_t srrctl = rd32 ( hw , TXGBE_RXCFG ( rxq -> reg_idx ) ) ; uint32_t psrtype = rd32 ( hw , TXGBE_POOLRSS ( rxq -> reg_idx ) ) ; uint32_t eitr = rd32 ( hw , TXGBE_ITR ( rxq -> reg_idx ) ) ; srrctl &= ~ TXGBE_RXCFG_HDRLEN_MASK ; srrctl |= TXGBE_RXCFG_HDRLEN ( 128 ) ; srrctl |= TXGBE_RXCFG_RSCENA ; srrctl &= ~ TXGBE_RXCFG_RSCMAX_MASK ; srrctl |= txgbe_get_rscctl_maxdesc ( rxq -> mb_pool ) ; psrtype |= TXGBE_POOLRSS_L4HDR ; eitr &= ~ TXGBE_ITR_IVAL_MASK ; eitr |= TXGBE_ITR_IVAL_10G ( TXGBE_QUEUE_ITR_INTERVAL_DEFAULT ) ; eitr |= TXGBE_ITR_WRDSA ; wr32 ( hw , TXGBE_RXCFG ( rxq -> reg_idx ) , srrctl ) ; wr32 ( hw , TXGBE_POOLRSS ( rxq -> reg_idx ) , psrtype ) ; wr32 ( hw , TXGBE_ITR ( rxq -> reg_idx ) , eitr ) ; txgbe_set_ivar_map ( hw , 0 , rxq -> reg_idx , i ) ; } dev -> data -> lro = 1 ; PMD_INIT_LOG ( DEBUG , " " ) ; return 0 ; }
txgbe_set_rsc - configure RSC related port HW registers
 Configures the port's RSC related registers.
txgbe_set_rsc - configure RSC related port HW registers Configures the port ' s RSC related registers .
/* Sanity check */ /* RSC global configuration */ /* If LRO hasn't been requested - we are done here. */ /* Set PSRCTL.RSCACK bit */ /* Per-queue RSC configuration */ /*
		 * txgbe PMD doesn't support header-split at the moment.
		 */ /*
		 * TODO: Consider setting the Receive Descriptor Minimum
		 * Threshold Size for an RSC case. This is not an obviously
		 * beneficiary option but the one worth considering...
		 */ /*
		 * RSC: Set ITR interval corresponding to 2K ints/s.
		 *
		 * Full-sized RSC aggregations for a 10Gb/s link will
		 * arrive at about 20K aggregation/s rate.
		 *
		 * 2K inst/s rate will make only 10% of the
		 * aggregations to be closed due to the interrupt timer
		 * expiration for a streaming at wire-speed case.
		 *
		 * For a sparse streaming case this setting will yield
		 * at most 500us latency for a single RSC aggregation.
		 */ /*
		 * RSC requires the mapping of the queue to the
		 * interrupt vector.
		 */