XilinxProcessorIPLib/drivers/dp12txss/examples/src/kcu/xdptxss_kcu105.c
void prog_bb (u8 bw, u8 is_tx) {
#if BUFFER_BYPASS

// For Buffer Bypass, the clock output from GT is refclk
// this needs to be called before GT is init
// For KCU105 the refclk is 270Mhz
        // For 2B, 4B mode,
        // 0x14 -> 270Mhz, 135Mhz
        // 0xA -> 135Mhz, 67.5Mhz
        // 0x6 -> 81Mhz, 40.5Mhz


#if SET_TX_TO_2BYTE == 1
VPhy_Instance.Quads[0].TxMmcm.ClkFbOutFrac = 0;
VPhy_Instance.Quads[0].TxMmcm.ClkOut0Frac  = 0;
  if (is_tx == 1) { // TX only path using refclk0 of 270Mhz
        if (bw == 0x14) { //270Mhz
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 4;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 4;
        } else if (bw == 0xA) { //135Mhz
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 4;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 8;
        } else { //81Mhz
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 36;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 10;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 12;
        }
  } else { // TX is using CPLL but refclk1 of 270/135/270
          // For KCU105 the refclk is 270Mhz, 135 or 270Mhz
                // For 2B, 4B mode,
                // 0x14 -> 270Mhz, 135Mhz
                // 0xA -> 135Mhz, 67.5Mhz
                // 0x6 -> 81Mhz, 40.5Mhz
      if (bw == 0x14) { //270Mhz
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 4;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 4;
      } else if (bw == 0xA) { //135Mhz
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 8;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 8;
      } else { //81Mhz
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 36;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 10;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 12;
      }
}

#else // for 4B the clocks to be genrated are half of 2B
    if (is_tx == 1) { // TX only path using refclk0 of 270Mhz
              if (bw == 0x14) { //135Mhz
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 4;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 8;
              } else if (bw == 0xA) { //67.5Mhz
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 4;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 16;
              } else { //40.5Mhz
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 36;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 10;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 24;
              }
    } else { // TX is using CPLL but refclk1 of 270/135/270
        // For KC705 the refclk is 270Mhz, 135 or 270Mhz
              // For 2B, 4B mode,
              // 0x14 -> 270Mhz, 135Mhz
              // 0xA -> 135Mhz, 67.5Mhz
              // 0x6 -> 81Mhz, 40.5Mhz
              if (bw == 0x14) { //135Mhz
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 4;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 8;
              } else if (bw == 0xA) { //67.5Mhz
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 8;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 16;
              } else { //40.5Mhz
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 36;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 10;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 24;
              }
    }
#endif

    XVphy_MmcmStart(&VPhy_Instance, 0, XVPHY_DIR_TX);
	xil_printf ("*");
	while (!(XVphy_MmcmLocked(&VPhy_Instance, 0, XVPHY_DIR_TX))) {

	}
	xil_printf ("*~~~");
	xil_printf("\r\n");

#endif
}
//Buffer Bypass is to be used when TX operates on stable clock.
//To use this, the TX should be configured with buffer bypass option.(hw change)
Buffer Bypass is to be used when TX operates on stable clock.
To use this, the TX should be configured with buffer bypass option.(hw change)
Buffer Bypass is to be used when TX operates on stable clock . To use this the TX should be configured with buffer bypass option . ( hw change )
void prog_bb (u8 bw, u8 is_tx) {
#if BUFFER_BYPASS
#if SET_TX_TO_2BYTE == 1
VPhy_Instance.Quads[0].TxMmcm.ClkFbOutFrac = 0;
VPhy_Instance.Quads[0].TxMmcm.ClkOut0Frac  = 0;
  if (is_tx == 1) { 
        if (bw == 0x14) { 
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 4;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 4;
        } else if (bw == 0xA) { 
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 4;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 8;
        } else { 
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 36;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 10;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 12;
        }
  } else { 
          , 135 or 270Mhz
      if (bw == 0x14) { 
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 4;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 4;
      } else if (bw == 0xA) { 
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 8;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 8;
      } else { 
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 36;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 10;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 12;
      }
}
#else 
    if (is_tx == 1) { 
              if (bw == 0x14) { 
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 4;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 8;
              } else if (bw == 0xA) { 
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 4;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 16;
              } else { 
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 36;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 10;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 24;
              }
    } else { 
              if (bw == 0x14) { 
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 4;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 8;
              } else if (bw == 0xA) { 
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 8;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 1;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 16;
              } else { 
                VPhy_Instance.Quads[0].TxMmcm.ClkFbOutMult = 36;
                VPhy_Instance.Quads[0].TxMmcm.DivClkDivide = 10;
                VPhy_Instance.Quads[0].TxMmcm.ClkOut0Div   = 24;
              }
    }
#endif
    XVphy_MmcmStart(&VPhy_Instance, 0, XVPHY_DIR_TX);
	xil_printf ("*");
	while (!(XVphy_MmcmLocked(&VPhy_Instance, 0, XVPHY_DIR_TX))) {
	}
	xil_printf ("*~~~");
	xil_printf("\r\n");
#endif
}
void prog_bb ( u8 bw , u8 is_tx ) { #if BUFFER_BYPASS #if SET_TX_TO_2BYTE == 1 VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutFrac = 0 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Frac = 0 ; if ( is_tx == 1 ) { if ( bw == 0x14 ) { VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutMult = 4 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . DivClkDivide = 1 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Div = 4 ; } else if ( bw == 0xA ) { VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutMult = 4 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . DivClkDivide = 1 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Div = 8 ; } else { VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutMult = 36 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . DivClkDivide = 10 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Div = 12 ; } } else { if ( bw == 0x14 ) { VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutMult = 4 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . DivClkDivide = 1 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Div = 4 ; } else if ( bw == 0xA ) { VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutMult = 8 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . DivClkDivide = 1 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Div = 8 ; } else { VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutMult = 36 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . DivClkDivide = 10 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Div = 12 ; } } #else if ( is_tx == 1 ) { if ( bw == 0x14 ) { VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutMult = 4 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . DivClkDivide = 1 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Div = 8 ; } else if ( bw == 0xA ) { VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutMult = 4 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . DivClkDivide = 1 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Div = 16 ; } else { VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutMult = 36 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . DivClkDivide = 10 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Div = 24 ; } } else { if ( bw == 0x14 ) { VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutMult = 4 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . DivClkDivide = 1 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Div = 8 ; } else if ( bw == 0xA ) { VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutMult = 8 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . DivClkDivide = 1 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Div = 16 ; } else { VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkFbOutMult = 36 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . DivClkDivide = 10 ; VPhy_Instance . Quads [ 0 ] . TxMmcm . ClkOut0Div = 24 ; } } #endif XVphy_MmcmStart ( & VPhy_Instance , 0 , XVPHY_DIR_TX ) ; xil_printf ( " " ) ; while ( ! ( XVphy_MmcmLocked ( & VPhy_Instance , 0 , XVPHY_DIR_TX ) ) ) { } xil_printf ( " " ) ; xil_printf ( " \r \n " ) ; #endif }
Buffer Bypass is to be used when TX operates on stable clock.
Buffer Bypass is to be used when TX operates on stable clock .
// For Buffer Bypass, the clock output from GT is refclk // this needs to be called before GT is init // For KCU105 the refclk is 270Mhz // For 2B, 4B mode, // 0x14 -> 270Mhz, 135Mhz // 0xA -> 135Mhz, 67.5Mhz // 0x6 -> 81Mhz, 40.5Mhz // TX only path using refclk0 of 270Mhz //270Mhz //135Mhz //81Mhz // TX is using CPLL but refclk1 of 270/135/270 // For KCU105 the refclk is 270Mhz, 135 or 270Mhz // For 2B, 4B mode, // 0x14 -> 270Mhz, 135Mhz // 0xA -> 135Mhz, 67.5Mhz // 0x6 -> 81Mhz, 40.5Mhz //270Mhz //135Mhz //81Mhz // for 4B the clocks to be genrated are half of 2B // TX only path using refclk0 of 270Mhz //135Mhz //67.5Mhz //40.5Mhz // TX is using CPLL but refclk1 of 270/135/270 // For KC705 the refclk is 270Mhz, 135 or 270Mhz // For 2B, 4B mode, // 0x14 -> 270Mhz, 135Mhz // 0xA -> 135Mhz, 67.5Mhz // 0x6 -> 81Mhz, 40.5Mhz //135Mhz //67.5Mhz //40.5Mhz