XilinxProcessorIPLib/drivers/tmr_manager/src/xtmr_manager_intr.c
void XTMR_Manager_EnableInterrupt(XTMR_Manager *InstancePtr, u32 Mask)
{
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Write to the SEM interrupt maskregister to enable the interrupts.
	 */
	XTMR_Manager_WriteReg(InstancePtr->RegBaseAddress,
				XTM_SEMIMR_OFFSET, Mask);
	InstancePtr->SemImr = Mask;
}
/*****************************************************************************/
/**
*
* This function enables the core interrupt such that an interrupt will occur
* when any of the SEM status signals indicated by the mask are changed.
*
* @param	InstancePtr is a pointer to the XTMR_Manager instance.
* @param	Mask is a mask indicating bits that should give an interrupt.
*
* @return	None.
*
* @note		None.
*
*****************************************************************************/
This function enables the core interrupt such that an interrupt will occur
when any of the SEM status signals indicated by the mask are changed.
This function enables the core interrupt such that an interrupt will occur when any of the SEM status signals indicated by the mask are changed .
void XTMR_Manager_EnableInterrupt(XTMR_Manager *InstancePtr, u32 Mask)
{
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	XTMR_Manager_WriteReg(InstancePtr->RegBaseAddress,
				XTM_SEMIMR_OFFSET, Mask);
	InstancePtr->SemImr = Mask;
}
void XTMR_Manager_EnableInterrupt ( XTMR_Manager * InstancePtr , u32 Mask ) { Xil_AssertVoid ( InstancePtr != NULL ) ; Xil_AssertVoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; XTMR_Manager_WriteReg ( InstancePtr -> RegBaseAddress , XTM_SEMIMR_OFFSET , Mask ) ; InstancePtr -> SemImr = Mask ; }
This function enables the core interrupt such that an interrupt will occur
when any of the SEM status signals indicated by the mask are changed.
This function enables the core interrupt such that an interrupt will occur when any of the SEM status signals indicated by the mask are changed .
/*
	 * Write to the SEM interrupt maskregister to enable the interrupts.
	 */