XilinxProcessorIPLib/drivers/dp14txss/examples/src/pt_only/rx.c
void DpRxSs_PllResetHandler(void *InstancePtr)
{

	u32 ReadVal;
	/*Enable AUX Defers for training purpose*/
    ReadVal = XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
                   XDP_RX_AUX_CLK_DIVIDER);
    ReadVal = ReadVal & 0xF0FF00FF;
    ReadVal = ReadVal | (AUX_DEFER_COUNT<<24);
    XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
                   XDP_RX_AUX_CLK_DIVIDER, ReadVal);

#ifndef versal
	/* Issue resets to Video PHY - This API
	 * called after line rate is programmed */
	XVphy_BufgGtReset(&VPhyInst, XVPHY_DIR_RX,(TRUE));
	XVphy_ResetGtPll(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA,
			 XVPHY_DIR_RX,(TRUE));
	XVphy_ResetGtPll(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA,
			 XVPHY_DIR_RX, (FALSE));
	XVphy_BufgGtReset(&VPhyInst, XVPHY_DIR_RX,(FALSE));
	XVphy_WaitForResetDone(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA,
			       XVPHY_DIR_RX);
	XVphy_WaitForPllLock(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA);
#endif

#if PHY_COMP
	/*Enable all interrupts, except unplug */
	XDp_RxInterruptEnable(DpRxSsInst.DpPtr,
			0x79FFFFFF);

#else
	/*Enable all interrupts */
	XDp_RxInterruptEnable(DpRxSsInst.DpPtr,
			      XDP_RX_INTERRUPT_MASK_ALL_MASK);

#endif

	DpRxSsInst.no_video_trigger = 1;
}
/*****************************************************************************/
/**
*
* This function is the callback function for PLL reset request.
*
* @param    InstancePtr is a pointer to the XDpRxSs instance.
*
* @return    None.
*
* @note        None.
*
******************************************************************************/
This function is the callback function for PLL reset request.
This function is the callback function for PLL reset request .
void DpRxSs_PllResetHandler(void *InstancePtr)
{
	u32 ReadVal;
    ReadVal = XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
                   XDP_RX_AUX_CLK_DIVIDER);
    ReadVal = ReadVal & 0xF0FF00FF;
    ReadVal = ReadVal | (AUX_DEFER_COUNT<<24);
    XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
                   XDP_RX_AUX_CLK_DIVIDER, ReadVal);
#ifndef versal
	XVphy_BufgGtReset(&VPhyInst, XVPHY_DIR_RX,(TRUE));
	XVphy_ResetGtPll(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA,
			 XVPHY_DIR_RX,(TRUE));
	XVphy_ResetGtPll(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA,
			 XVPHY_DIR_RX, (FALSE));
	XVphy_BufgGtReset(&VPhyInst, XVPHY_DIR_RX,(FALSE));
	XVphy_WaitForResetDone(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA,
			       XVPHY_DIR_RX);
	XVphy_WaitForPllLock(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA);
#endif
#if PHY_COMP
	XDp_RxInterruptEnable(DpRxSsInst.DpPtr,
			0x79FFFFFF);
#else
	XDp_RxInterruptEnable(DpRxSsInst.DpPtr,
			      XDP_RX_INTERRUPT_MASK_ALL_MASK);
#endif
	DpRxSsInst.no_video_trigger = 1;
}
void DpRxSs_PllResetHandler ( void * InstancePtr ) { u32 ReadVal ; ReadVal = XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_AUX_CLK_DIVIDER ) ; ReadVal = ReadVal & 0xF0FF00FF ; ReadVal = ReadVal | ( AUX_DEFER_COUNT << 24 ) ; XDp_WriteReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_AUX_CLK_DIVIDER , ReadVal ) ; #ifndef versal XVphy_BufgGtReset ( & VPhyInst , XVPHY_DIR_RX , ( TRUE ) ) ; XVphy_ResetGtPll ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX , ( TRUE ) ) ; XVphy_ResetGtPll ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX , ( FALSE ) ) ; XVphy_BufgGtReset ( & VPhyInst , XVPHY_DIR_RX , ( FALSE ) ) ; XVphy_WaitForResetDone ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX ) ; XVphy_WaitForPllLock ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CHA ) ; #endif #if PHY_COMP XDp_RxInterruptEnable ( DpRxSsInst . DpPtr , 0x79FFFFFF ) ; #else XDp_RxInterruptEnable ( DpRxSsInst . DpPtr , XDP_RX_INTERRUPT_MASK_ALL_MASK ) ; #endif DpRxSsInst . no_video_trigger = 1 ; }
This function is the callback function for PLL reset request.
This function is the callback function for PLL reset request .
/*Enable AUX Defers for training purpose*/ /* Issue resets to Video PHY - This API
	 * called after line rate is programmed */ /*Enable all interrupts, except unplug */ /*Enable all interrupts */