XilinxProcessorIPLib/drivers/vphy/src/xvphy_gtye4.c
u32 XVphy_Gtye4ClkCmnReconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId CmnId)
{
	u16 DrpVal;
	u16 WriteVal;
	u8  QpllxFbdiv;
	u32 QpllxVcoRateMHz;
	u32 QpllxClkOutMHz;
    u32 Status = XST_SUCCESS;
	u16 QPLLx_CFG23;
	u16 QPLLx_LPF;

	/* Obtain current DRP register value for QPLLx_FBDIV. */
	Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x14 : 0x94, &DrpVal);
	/* Mask out QPLLx_FBDIV. */
	DrpVal &= ~(0xFF);
	/* Set QPLLx_FBDIV. */
	WriteVal = (XVphy_NToDrpEncoding(InstancePtr, QuadId, CmnId, 0) & 0xFF);
	DrpVal |= WriteVal;
	/* Write new DRP register value for QPLLx_FBDIV. */
	Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x14 : 0x94, DrpVal);

	/* Obtain current DRP register value for QPLLx_REFCLK_DIV. */
	Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x18 : 0x98, &DrpVal);
	/* Mask out QPLLx_REFCLK_DIV. */
	DrpVal &= ~(0xF80);
	/* Disable Intelligent Reference Clock Selection */
	if (XVphy_GetRefClkSourcesCount(InstancePtr) > 1) {
		DrpVal |= (1 << 6);
	}
	/* Set QPLLx_REFCLK_DIV. */
	WriteVal = (XVphy_MToDrpEncoding(InstancePtr, QuadId, CmnId) & 0x1F);
	DrpVal |= (WriteVal << 7);
	/* Write new DRP register value for QPLLx_REFCLK_DIV. */
	Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x18 : 0x98, DrpVal);

	if ((XVphy_IsHDMI(InstancePtr, XVPHY_DIR_TX)) ||
		(XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX))) {

		QpllxVcoRateMHz = XVphy_GetPllVcoFreqHz(InstancePtr, QuadId, CmnId,
				XVphy_IsTxUsingQpll(InstancePtr, QuadId, CmnId) ?
						XVPHY_DIR_TX : XVPHY_DIR_RX) / 1000000;
		QpllxClkOutMHz = QpllxVcoRateMHz / 2;

		/* PPFx_CFG */
		if (QpllxVcoRateMHz >= 16375) {
			DrpVal = 0x0F00;
		}
		else if (QpllxVcoRateMHz >= 14000) {
			DrpVal = 0x0B00;
		}
		else if (QpllxVcoRateMHz >= 13000) {
			DrpVal = 0x0900;
		}
		else if (QpllxVcoRateMHz >= 12500) {
			DrpVal = 0x0800;
		}
		else if (QpllxVcoRateMHz >= 10312) {
			DrpVal = 0x0600;
		}
		else {
			DrpVal = 0x0400;
		}
		/* Write new DRP register value for PPFx_CFG. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x0D : 0x8D, DrpVal);

		/* QPLLx_CFG2 & QPLLx_CFG3*/
        QpllxFbdiv = InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(CmnId)].
                            PllParams.NFbDiv;
        if (QpllxFbdiv <= 30) {
            if (CmnId == XVPHY_CHANNEL_ID_CMN0) {
                if (QpllxVcoRateMHz <= 11000) {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x27F;
                }
                else if (QpllxVcoRateMHz <= 14000) {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x37F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x2FF;
                }
            }
            else {
                QPLLx_CFG23 = 0x0FC1;
                QPLLx_LPF   = 0x2FF;
            }
        }
        else if (QpllxFbdiv <= 50) {
            if (CmnId == XVPHY_CHANNEL_ID_CMN0) {
                if (QpllxVcoRateMHz <= 14000) {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x37F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x31D;
                }
            }
            else {
                QPLLx_CFG23 = 0x0FC1;
                if (QpllxVcoRateMHz <= 11500) {
                    QPLLx_LPF   = 0x33F;
                }
                else {
                    QPLLx_LPF   = 0x37F;
                }
            }
        }
        else if (QpllxFbdiv <= 70) {
            if (CmnId == XVPHY_CHANNEL_ID_CMN0) {
                if (QpllxVcoRateMHz <= 11000) {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x23F;
                }
                else if (QpllxVcoRateMHz <= 14000) {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x33F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x29D;
                }
            }
            else {
                if (QpllxVcoRateMHz <= 11500) {
                    QPLLx_CFG23 = 0x0FC3;
                    QPLLx_LPF   = 0x21F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x33F;
                }
            }
        }
        else if (QpllxFbdiv <= 90) {
            if (CmnId == XVPHY_CHANNEL_ID_CMN0) {
                if (QpllxVcoRateMHz <= 14000) {
                    QPLLx_CFG23 = 0x0FC3;
                    QPLLx_LPF   = 0x21F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x37F;
                }
            }
            else {
                if (QpllxVcoRateMHz <= 9000) {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x21F;
                }
                else if (QpllxVcoRateMHz <= 11500) {
                    QPLLx_CFG23 = 0x0FC3;
                    QPLLx_LPF   = 0x21F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x33F;
                }
            }
        }
        else {
            if (CmnId == XVPHY_CHANNEL_ID_CMN0) {
                if (QpllxVcoRateMHz <= 11000) {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x21F;
                }
                else if (QpllxVcoRateMHz <= 14000) {
                    QPLLx_CFG23 = 0x0FC3;
                    QPLLx_LPF   = 0x21F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x37F;
                }
            }
            else {
                if (QpllxVcoRateMHz <= 9000) {
                    QPLLx_CFG23 = 0x0FC3;
                    QPLLx_LPF   = 0x21D;
                }
                else if (QpllxVcoRateMHz <= 11500) {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x21D;
                }
                else {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x33F;
                }
            }
        }
		/* Write new DRP register value for QPLLx_CFG2. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x11 : 0x91, QPLLx_CFG23);
		/* Write new DRP register value for QPLLx_CFG3. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x1B : 0x9B, QPLLx_CFG23);
		/* Write new DRP register value for QPLLx_LPF. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x19 : 0x99, QPLLx_LPF);

        /* QPLLx_CFG4 */
        if (QpllxClkOutMHz >= 14000) {
            DrpVal = 0x0086;
        }
        else if (QpllxClkOutMHz >= 12500) {
            DrpVal = 0x0084;
        }
        else if (QpllxClkOutMHz >= 8187) {
            DrpVal = 0x0003;
        }
        else if (QpllxClkOutMHz >= 5156) {
            DrpVal = 0x0002;
        }
        else {
            DrpVal = 0x0001;
        }
        /* Write new DRP register value for QPLLx_CFG4. */
        Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
            (CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x30 : 0xB0, DrpVal);
	}

	return Status;
}
/*****************************************************************************/
/**
* This function will configure the common channel clock settings.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	CmnId is the common channel ID to operate on.
*
* @return
*		- XST_SUCCESS if the configuration was successful.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function will configure the common channel clock settings.
This function will configure the common channel clock settings .
u32 XVphy_Gtye4ClkCmnReconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId CmnId)
{
	u16 DrpVal;
	u16 WriteVal;
	u8  QpllxFbdiv;
	u32 QpllxVcoRateMHz;
	u32 QpllxClkOutMHz;
    u32 Status = XST_SUCCESS;
	u16 QPLLx_CFG23;
	u16 QPLLx_LPF;
	Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x14 : 0x94, &DrpVal);
	DrpVal &= ~(0xFF);
	WriteVal = (XVphy_NToDrpEncoding(InstancePtr, QuadId, CmnId, 0) & 0xFF);
	DrpVal |= WriteVal;
	Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x14 : 0x94, DrpVal);
	Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x18 : 0x98, &DrpVal);
	DrpVal &= ~(0xF80);
	if (XVphy_GetRefClkSourcesCount(InstancePtr) > 1) {
		DrpVal |= (1 << 6);
	}
	WriteVal = (XVphy_MToDrpEncoding(InstancePtr, QuadId, CmnId) & 0x1F);
	DrpVal |= (WriteVal << 7);
	Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x18 : 0x98, DrpVal);
	if ((XVphy_IsHDMI(InstancePtr, XVPHY_DIR_TX)) ||
		(XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX))) {
		QpllxVcoRateMHz = XVphy_GetPllVcoFreqHz(InstancePtr, QuadId, CmnId,
				XVphy_IsTxUsingQpll(InstancePtr, QuadId, CmnId) ?
						XVPHY_DIR_TX : XVPHY_DIR_RX) / 1000000;
		QpllxClkOutMHz = QpllxVcoRateMHz / 2;
		if (QpllxVcoRateMHz >= 16375) {
			DrpVal = 0x0F00;
		}
		else if (QpllxVcoRateMHz >= 14000) {
			DrpVal = 0x0B00;
		}
		else if (QpllxVcoRateMHz >= 13000) {
			DrpVal = 0x0900;
		}
		else if (QpllxVcoRateMHz >= 12500) {
			DrpVal = 0x0800;
		}
		else if (QpllxVcoRateMHz >= 10312) {
			DrpVal = 0x0600;
		}
		else {
			DrpVal = 0x0400;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x0D : 0x8D, DrpVal);
        QpllxFbdiv = InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(CmnId)].
                            PllParams.NFbDiv;
        if (QpllxFbdiv <= 30) {
            if (CmnId == XVPHY_CHANNEL_ID_CMN0) {
                if (QpllxVcoRateMHz <= 11000) {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x27F;
                }
                else if (QpllxVcoRateMHz <= 14000) {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x37F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x2FF;
                }
            }
            else {
                QPLLx_CFG23 = 0x0FC1;
                QPLLx_LPF   = 0x2FF;
            }
        }
        else if (QpllxFbdiv <= 50) {
            if (CmnId == XVPHY_CHANNEL_ID_CMN0) {
                if (QpllxVcoRateMHz <= 14000) {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x37F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x31D;
                }
            }
            else {
                QPLLx_CFG23 = 0x0FC1;
                if (QpllxVcoRateMHz <= 11500) {
                    QPLLx_LPF   = 0x33F;
                }
                else {
                    QPLLx_LPF   = 0x37F;
                }
            }
        }
        else if (QpllxFbdiv <= 70) {
            if (CmnId == XVPHY_CHANNEL_ID_CMN0) {
                if (QpllxVcoRateMHz <= 11000) {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x23F;
                }
                else if (QpllxVcoRateMHz <= 14000) {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x33F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x29D;
                }
            }
            else {
                if (QpllxVcoRateMHz <= 11500) {
                    QPLLx_CFG23 = 0x0FC3;
                    QPLLx_LPF   = 0x21F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x33F;
                }
            }
        }
        else if (QpllxFbdiv <= 90) {
            if (CmnId == XVPHY_CHANNEL_ID_CMN0) {
                if (QpllxVcoRateMHz <= 14000) {
                    QPLLx_CFG23 = 0x0FC3;
                    QPLLx_LPF   = 0x21F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x37F;
                }
            }
            else {
                if (QpllxVcoRateMHz <= 9000) {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x21F;
                }
                else if (QpllxVcoRateMHz <= 11500) {
                    QPLLx_CFG23 = 0x0FC3;
                    QPLLx_LPF   = 0x21F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x33F;
                }
            }
        }
        else {
            if (CmnId == XVPHY_CHANNEL_ID_CMN0) {
                if (QpllxVcoRateMHz <= 11000) {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x21F;
                }
                else if (QpllxVcoRateMHz <= 14000) {
                    QPLLx_CFG23 = 0x0FC3;
                    QPLLx_LPF   = 0x21F;
                }
                else {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x37F;
                }
            }
            else {
                if (QpllxVcoRateMHz <= 9000) {
                    QPLLx_CFG23 = 0x0FC3;
                    QPLLx_LPF   = 0x21D;
                }
                else if (QpllxVcoRateMHz <= 11500) {
                    QPLLx_CFG23 = 0x0FC1;
                    QPLLx_LPF   = 0x21D;
                }
                else {
                    QPLLx_CFG23 = 0x0FC0;
                    QPLLx_LPF   = 0x33F;
                }
            }
        }
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x11 : 0x91, QPLLx_CFG23);
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x1B : 0x9B, QPLLx_CFG23);
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x19 : 0x99, QPLLx_LPF);
        if (QpllxClkOutMHz >= 14000) {
            DrpVal = 0x0086;
        }
        else if (QpllxClkOutMHz >= 12500) {
            DrpVal = 0x0084;
        }
        else if (QpllxClkOutMHz >= 8187) {
            DrpVal = 0x0003;
        }
        else if (QpllxClkOutMHz >= 5156) {
            DrpVal = 0x0002;
        }
        else {
            DrpVal = 0x0001;
        }
        Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
            (CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x30 : 0xB0, DrpVal);
	}
	return Status;
}
u32 XVphy_Gtye4ClkCmnReconfig ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId CmnId ) { u16 DrpVal ; u16 WriteVal ; u8 QpllxFbdiv ; u32 QpllxVcoRateMHz ; u32 QpllxClkOutMHz ; u32 Status = XST_SUCCESS ; u16 QPLLx_CFG23 ; u16 QPLLx_LPF ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x14 : 0x94 , & DrpVal ) ; DrpVal &= ~ ( 0xFF ) ; WriteVal = ( XVphy_NToDrpEncoding ( InstancePtr , QuadId , CmnId , 0 ) & 0xFF ) ; DrpVal |= WriteVal ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x14 : 0x94 , DrpVal ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x18 : 0x98 , & DrpVal ) ; DrpVal &= ~ ( 0xF80 ) ; if ( XVphy_GetRefClkSourcesCount ( InstancePtr ) > 1 ) { DrpVal |= ( 1 << 6 ) ; } WriteVal = ( XVphy_MToDrpEncoding ( InstancePtr , QuadId , CmnId ) & 0x1F ) ; DrpVal |= ( WriteVal << 7 ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x18 : 0x98 , DrpVal ) ; if ( ( XVphy_IsHDMI ( InstancePtr , XVPHY_DIR_TX ) ) || ( XVphy_IsHDMI ( InstancePtr , XVPHY_DIR_RX ) ) ) { QpllxVcoRateMHz = XVphy_GetPllVcoFreqHz ( InstancePtr , QuadId , CmnId , XVphy_IsTxUsingQpll ( InstancePtr , QuadId , CmnId ) ? XVPHY_DIR_TX : XVPHY_DIR_RX ) / 1000000 ; QpllxClkOutMHz = QpllxVcoRateMHz / 2 ; if ( QpllxVcoRateMHz >= 16375 ) { DrpVal = 0x0F00 ; } else if ( QpllxVcoRateMHz >= 14000 ) { DrpVal = 0x0B00 ; } else if ( QpllxVcoRateMHz >= 13000 ) { DrpVal = 0x0900 ; } else if ( QpllxVcoRateMHz >= 12500 ) { DrpVal = 0x0800 ; } else if ( QpllxVcoRateMHz >= 10312 ) { DrpVal = 0x0600 ; } else { DrpVal = 0x0400 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x0D : 0x8D , DrpVal ) ; QpllxFbdiv = InstancePtr -> Quads [ QuadId ] . Plls [ XVPHY_CH2IDX ( CmnId ) ] . PllParams . NFbDiv ; if ( QpllxFbdiv <= 30 ) { if ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) { if ( QpllxVcoRateMHz <= 11000 ) { QPLLx_CFG23 = 0x0FC1 ; QPLLx_LPF = 0x27F ; } else if ( QpllxVcoRateMHz <= 14000 ) { QPLLx_CFG23 = 0x0FC1 ; QPLLx_LPF = 0x37F ; } else { QPLLx_CFG23 = 0x0FC0 ; QPLLx_LPF = 0x2FF ; } } else { QPLLx_CFG23 = 0x0FC1 ; QPLLx_LPF = 0x2FF ; } } else if ( QpllxFbdiv <= 50 ) { if ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) { if ( QpllxVcoRateMHz <= 14000 ) { QPLLx_CFG23 = 0x0FC1 ; QPLLx_LPF = 0x37F ; } else { QPLLx_CFG23 = 0x0FC0 ; QPLLx_LPF = 0x31D ; } } else { QPLLx_CFG23 = 0x0FC1 ; if ( QpllxVcoRateMHz <= 11500 ) { QPLLx_LPF = 0x33F ; } else { QPLLx_LPF = 0x37F ; } } } else if ( QpllxFbdiv <= 70 ) { if ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) { if ( QpllxVcoRateMHz <= 11000 ) { QPLLx_CFG23 = 0x0FC0 ; QPLLx_LPF = 0x23F ; } else if ( QpllxVcoRateMHz <= 14000 ) { QPLLx_CFG23 = 0x0FC1 ; QPLLx_LPF = 0x33F ; } else { QPLLx_CFG23 = 0x0FC0 ; QPLLx_LPF = 0x29D ; } } else { if ( QpllxVcoRateMHz <= 11500 ) { QPLLx_CFG23 = 0x0FC3 ; QPLLx_LPF = 0x21F ; } else { QPLLx_CFG23 = 0x0FC1 ; QPLLx_LPF = 0x33F ; } } } else if ( QpllxFbdiv <= 90 ) { if ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) { if ( QpllxVcoRateMHz <= 14000 ) { QPLLx_CFG23 = 0x0FC3 ; QPLLx_LPF = 0x21F ; } else { QPLLx_CFG23 = 0x0FC1 ; QPLLx_LPF = 0x37F ; } } else { if ( QpllxVcoRateMHz <= 9000 ) { QPLLx_CFG23 = 0x0FC0 ; QPLLx_LPF = 0x21F ; } else if ( QpllxVcoRateMHz <= 11500 ) { QPLLx_CFG23 = 0x0FC3 ; QPLLx_LPF = 0x21F ; } else { QPLLx_CFG23 = 0x0FC0 ; QPLLx_LPF = 0x33F ; } } } else { if ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) { if ( QpllxVcoRateMHz <= 11000 ) { QPLLx_CFG23 = 0x0FC0 ; QPLLx_LPF = 0x21F ; } else if ( QpllxVcoRateMHz <= 14000 ) { QPLLx_CFG23 = 0x0FC3 ; QPLLx_LPF = 0x21F ; } else { QPLLx_CFG23 = 0x0FC1 ; QPLLx_LPF = 0x37F ; } } else { if ( QpllxVcoRateMHz <= 9000 ) { QPLLx_CFG23 = 0x0FC3 ; QPLLx_LPF = 0x21D ; } else if ( QpllxVcoRateMHz <= 11500 ) { QPLLx_CFG23 = 0x0FC1 ; QPLLx_LPF = 0x21D ; } else { QPLLx_CFG23 = 0x0FC0 ; QPLLx_LPF = 0x33F ; } } } Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x11 : 0x91 , QPLLx_CFG23 ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x1B : 0x9B , QPLLx_CFG23 ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x19 : 0x99 , QPLLx_LPF ) ; if ( QpllxClkOutMHz >= 14000 ) { DrpVal = 0x0086 ; } else if ( QpllxClkOutMHz >= 12500 ) { DrpVal = 0x0084 ; } else if ( QpllxClkOutMHz >= 8187 ) { DrpVal = 0x0003 ; } else if ( QpllxClkOutMHz >= 5156 ) { DrpVal = 0x0002 ; } else { DrpVal = 0x0001 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x30 : 0xB0 , DrpVal ) ; } return Status ; }
This function will configure the common channel clock settings.
This function will configure the common channel clock settings .
/* Obtain current DRP register value for QPLLx_FBDIV. */ /* Mask out QPLLx_FBDIV. */ /* Set QPLLx_FBDIV. */ /* Write new DRP register value for QPLLx_FBDIV. */ /* Obtain current DRP register value for QPLLx_REFCLK_DIV. */ /* Mask out QPLLx_REFCLK_DIV. */ /* Disable Intelligent Reference Clock Selection */ /* Set QPLLx_REFCLK_DIV. */ /* Write new DRP register value for QPLLx_REFCLK_DIV. */ /* PPFx_CFG */ /* Write new DRP register value for PPFx_CFG. */ /* QPLLx_CFG2 & QPLLx_CFG3*/ /* Write new DRP register value for QPLLx_CFG2. */ /* Write new DRP register value for QPLLx_CFG3. */ /* Write new DRP register value for QPLLx_LPF. */ /* QPLLx_CFG4 */ /* Write new DRP register value for QPLLx_CFG4. */