XilinxProcessorIPLib/drivers/dmaps/src/xdmaps_hw.c
void XDmaPs_ResetHw(u32 BaseAddress)
{
	u32 DbgInst;
	u32 WaitCount = 0;
	u32 ChanIndex;

	/* Disable all the interrupts */
	XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00);
	/* Clear the interrupts */
	XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
	/* Kill the dma channel threads */
	for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
		while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
				& XDMAPS_DBGSTATUS_BUSY)
				&& (WaitCount < XDMAPS_MAX_WAIT))
				WaitCount++;

		DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);	
		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);	
		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
	}	
	/* Kill the manager thread	*/
	DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);	
	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);	
	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);	
}
/*****************************************************************************/
/**
* This function perform the reset sequence to the given dmaps interface by 
* configuring the appropriate control bits in the dmaps specifc registers
* the dmaps reset squence involves the following steps
*	Disable all the interuupts 
*	Clear the pending interrupts
*	Kill all the active channel threads
*	Kill the manager thread
*
* @param   BaseAddress of the interface
*
* @return N/A
*
* @note 
* This function will not modify the slcr registers that are relavant for 
* dmaps controller
******************************************************************************/
This function perform the reset sequence to the given dmaps interface by
configuring the appropriate control bits in the dmaps specifc registers
the dmaps reset squence involves the following steps
Disable all the interuupts
Clear the pending interrupts
Kill all the active channel threads
Kill the manager thread
This function perform the reset sequence to the given dmaps interface by configuring the appropriate control bits in the dmaps specifc registers the dmaps reset squence involves the following steps Disable all the interuupts Clear the pending interrupts Kill all the active channel threads Kill the manager thread
void XDmaPs_ResetHw(u32 BaseAddress)
{
	u32 DbgInst;
	u32 WaitCount = 0;
	u32 ChanIndex;
	XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00);
	XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
	for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
		while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
				& XDMAPS_DBGSTATUS_BUSY)
				&& (WaitCount < XDMAPS_MAX_WAIT))
				WaitCount++;
		DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);	
		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);	
		XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
	}	
	DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);	
	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);	
	XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);	
}
void XDmaPs_ResetHw ( u32 BaseAddress ) { u32 DbgInst ; u32 WaitCount = 0 ; u32 ChanIndex ; XDmaPs_WriteReg ( BaseAddress , XDMAPS_INTEN_OFFSET , 0x00 ) ; XDmaPs_WriteReg ( BaseAddress , XDMAPS_INTCLR_OFFSET , XDMAPS_INTCLR_ALL_MASK ) ; for ( ChanIndex = 0 ; ChanIndex < XDMAPS_CHANNELS_PER_DEV ; ChanIndex ++ ) { while ( ( XDmaPs_ReadReg ( BaseAddress , XDMAPS_DBGSTATUS_OFFSET ) & XDMAPS_DBGSTATUS_BUSY ) && ( WaitCount < XDMAPS_MAX_WAIT ) ) WaitCount ++ ; DbgInst = XDmaPs_DBGINST0 ( 0 , 0x01 , ChanIndex , 1 ) ; XDmaPs_WriteReg ( BaseAddress , XDMAPS_DBGINST0_OFFSET , DbgInst ) ; XDmaPs_WriteReg ( BaseAddress , XDMAPS_DBGINST1_OFFSET , 0x0 ) ; XDmaPs_WriteReg ( BaseAddress , XDMAPS_DBGCMD_OFFSET , 0x0 ) ; } DbgInst = XDmaPs_DBGINST0 ( 0 , 0x01 , 0 , 0 ) ; XDmaPs_WriteReg ( BaseAddress , XDMAPS_DBGINST0_OFFSET , DbgInst ) ; XDmaPs_WriteReg ( BaseAddress , XDMAPS_DBGINST1_OFFSET , 0x0 ) ; XDmaPs_WriteReg ( BaseAddress , XDMAPS_DBGCMD_OFFSET , 0x0 ) ; }
This function perform the reset sequence to the given dmaps interface by
configuring the appropriate control bits in the dmaps specifc registers
the dmaps reset squence involves the following steps
Disable all the interuupts
Clear the pending interrupts
Kill all the active channel threads
Kill the manager thread
This function perform the reset sequence to the given dmaps interface by configuring the appropriate control bits in the dmaps specifc registers the dmaps reset squence involves the following steps Disable all the interuupts Clear the pending interrupts Kill all the active channel threads Kill the manager thread
/* Disable all the interrupts */ /* Clear the interrupts */ /* Kill the dma channel threads */ /* Kill the manager thread	*/