XilinxProcessorIPLib/drivers/dp14txss/examples/src/pt_only/rx.c
void DpRxSs_AccessErrorCounterHandler(void *InstancePtr)
{
	u32 DrpValConfig;

	u32 SymErrVal_lane01;
	u32 SymErrVal_lane23;

	u32 ReadVal;

#ifndef versal
	/*Read twice from VPHY*/
	SymErrVal_lane01 = XVphy_ReadReg(
			VIDPHY_BASEADDR,XVPHY_RX_SYM_ERR_CNTR_CH1_2_REG);
	SymErrVal_lane23 = XVphy_ReadReg(
			VIDPHY_BASEADDR,XVPHY_RX_SYM_ERR_CNTR_CH3_4_REG);

	SymErrVal_lane01 = XVphy_ReadReg(
			VIDPHY_BASEADDR,XVPHY_RX_SYM_ERR_CNTR_CH1_2_REG);
	SymErrVal_lane23 = XVphy_ReadReg(
			VIDPHY_BASEADDR,XVPHY_RX_SYM_ERR_CNTR_CH3_4_REG);

	/*Read PRBS Error Counter Value from Video PHY*/

	/*Lane 0 - Store only lower 16 bits*/
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_LOWER,
		    &DrpVal_lower_lane0);
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_UPPER,
		    &DrpVal);

	/*Lane 1 - Store only lower 16 bits*/
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_LOWER,
		    &DrpVal_lower_lane1);
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_UPPER, &DrpVal);

	/*Lane 2 - Store only lower 16 bits*/
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_LOWER,
		    &DrpVal_lower_lane2);
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_UPPER, &DrpVal);

	/*Lane 3 - Store only lower 16 bits*/
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_LOWER,
		    &DrpVal_lower_lane3);
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_UPPER, &DrpVal);
#endif
	ReadVal = XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
			XDP_RX_DPC_LINK_QUAL_CONFIG);

//	xil_printf("XDP_RX_DPC_LINK_QUAL_CONFIG: 0x%x\r\n",ReadVal);

	/*Write into DP Core - Validity bit and lower 15 bit counter value*/
    if((ReadVal&0x7) == XDP_RX_DPCD_LINK_QUAL_PRBS)
    {
	/*Write PRBS Values from GT to DPCD Error Reg Space*/
	XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
		     XDP_RX_DPC_L01_PRBS_CNTR,
		     (0x8000 | DrpVal_lower_lane0) |
		     ((0x8000 | DrpVal_lower_lane1) << 16));
	XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
		     XDP_RX_DPC_L23_PRBS_CNTR,
		     (0x8000 | DrpVal_lower_lane2) |
		     ((0x8000 | DrpVal_lower_lane3) << 16));

    }
    else
    {
	/*Write symbol error counter values from VPHY to DPCD Error Reg Space*/
	XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
		     XDP_RX_DPC_L01_PRBS_CNTR,
			 SymErrVal_lane01|0x80008000);
	XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
		     XDP_RX_DPC_L23_PRBS_CNTR,
			 SymErrVal_lane23|0x80008000);

    }

#if PRBS_ERRCNTR_CLEAR_ON_READ
    if( ((ReadVal&0x7) == XDP_RX_DPCD_LINK_QUAL_PRBS) &&
	( DrpVal_lower_lane0!=0x0 || DrpVal_lower_lane1!=0x0 ||
	  DrpVal_lower_lane2!=0x0 || DrpVal_lower_lane3!=0x0 )
      )
    {
#ifndef versal
		/* Reset PRBS7 Counters */
	DrpValConfig = XVphy_ReadReg(VPhyInst.Config.BaseAddr,
					   XVPHY_RX_CONTROL_REG);
	DrpValConfig = DrpValConfig | 0x08080808;
		XDp_WriteReg(VPhyInst.Config.BaseAddr,
				 XVPHY_RX_CONTROL_REG, DrpValConfig);
		DrpValConfig = XVphy_ReadReg(VPhyInst.Config.BaseAddr,
					   XVPHY_RX_CONTROL_REG);
		DrpValConfig = DrpValConfig & 0xF7F7F7F7;
		XVphy_WriteReg(VPhyInst.Config.BaseAddr,
						XVPHY_RX_CONTROL_REG, DrpValConfig);
#endif
    }
#endif

    xil_printf("DpRxSs_AccessErrorCounterHandler\r\n");
}
/*****************************************************************************/
/**
*
* This function is the callback function for Access prbs error count.
*
* @param    InstancePtr is a pointer to the XDpRxSs instance.
*
* @return    None.
*
* @note        None.
*
******************************************************************************/
This function is the callback function for Access prbs error count.
This function is the callback function for Access prbs error count .
void DpRxSs_AccessErrorCounterHandler(void *InstancePtr)
{
	u32 DrpValConfig;
	u32 SymErrVal_lane01;
	u32 SymErrVal_lane23;
	u32 ReadVal;
#ifndef versal
	SymErrVal_lane01 = XVphy_ReadReg(
			VIDPHY_BASEADDR,XVPHY_RX_SYM_ERR_CNTR_CH1_2_REG);
	SymErrVal_lane23 = XVphy_ReadReg(
			VIDPHY_BASEADDR,XVPHY_RX_SYM_ERR_CNTR_CH3_4_REG);
	SymErrVal_lane01 = XVphy_ReadReg(
			VIDPHY_BASEADDR,XVPHY_RX_SYM_ERR_CNTR_CH1_2_REG);
	SymErrVal_lane23 = XVphy_ReadReg(
			VIDPHY_BASEADDR,XVPHY_RX_SYM_ERR_CNTR_CH3_4_REG);
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_LOWER,
		    &DrpVal_lower_lane0);
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_UPPER,
		    &DrpVal);
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_LOWER,
		    &DrpVal_lower_lane1);
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_UPPER, &DrpVal);
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_LOWER,
		    &DrpVal_lower_lane2);
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_UPPER, &DrpVal);
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_LOWER,
		    &DrpVal_lower_lane3);
	XVphy_DrpRd(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4,
		    XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_UPPER, &DrpVal);
#endif
	ReadVal = XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
			XDP_RX_DPC_LINK_QUAL_CONFIG);
    if((ReadVal&0x7) == XDP_RX_DPCD_LINK_QUAL_PRBS)
    {
	XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
		     XDP_RX_DPC_L01_PRBS_CNTR,
		     (0x8000 | DrpVal_lower_lane0) |
		     ((0x8000 | DrpVal_lower_lane1) << 16));
	XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
		     XDP_RX_DPC_L23_PRBS_CNTR,
		     (0x8000 | DrpVal_lower_lane2) |
		     ((0x8000 | DrpVal_lower_lane3) << 16));
    }
    else
    {
	XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
		     XDP_RX_DPC_L01_PRBS_CNTR,
			 SymErrVal_lane01|0x80008000);
	XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
		     XDP_RX_DPC_L23_PRBS_CNTR,
			 SymErrVal_lane23|0x80008000);
    }
#if PRBS_ERRCNTR_CLEAR_ON_READ
    if( ((ReadVal&0x7) == XDP_RX_DPCD_LINK_QUAL_PRBS) &&
	( DrpVal_lower_lane0!=0x0 || DrpVal_lower_lane1!=0x0 ||
	  DrpVal_lower_lane2!=0x0 || DrpVal_lower_lane3!=0x0 )
      )
    {
#ifndef versal
	DrpValConfig = XVphy_ReadReg(VPhyInst.Config.BaseAddr,
					   XVPHY_RX_CONTROL_REG);
	DrpValConfig = DrpValConfig | 0x08080808;
		XDp_WriteReg(VPhyInst.Config.BaseAddr,
				 XVPHY_RX_CONTROL_REG, DrpValConfig);
		DrpValConfig = XVphy_ReadReg(VPhyInst.Config.BaseAddr,
					   XVPHY_RX_CONTROL_REG);
		DrpValConfig = DrpValConfig & 0xF7F7F7F7;
		XVphy_WriteReg(VPhyInst.Config.BaseAddr,
						XVPHY_RX_CONTROL_REG, DrpValConfig);
#endif
    }
#endif
    xil_printf("DpRxSs_AccessErrorCounterHandler\r\n");
}
void DpRxSs_AccessErrorCounterHandler ( void * InstancePtr ) { u32 DrpValConfig ; u32 SymErrVal_lane01 ; u32 SymErrVal_lane23 ; u32 ReadVal ; #ifndef versal SymErrVal_lane01 = XVphy_ReadReg ( VIDPHY_BASEADDR , XVPHY_RX_SYM_ERR_CNTR_CH1_2_REG ) ; SymErrVal_lane23 = XVphy_ReadReg ( VIDPHY_BASEADDR , XVPHY_RX_SYM_ERR_CNTR_CH3_4_REG ) ; SymErrVal_lane01 = XVphy_ReadReg ( VIDPHY_BASEADDR , XVPHY_RX_SYM_ERR_CNTR_CH1_2_REG ) ; SymErrVal_lane23 = XVphy_ReadReg ( VIDPHY_BASEADDR , XVPHY_RX_SYM_ERR_CNTR_CH3_4_REG ) ; XVphy_DrpRd ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH1 , XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_LOWER , & DrpVal_lower_lane0 ) ; XVphy_DrpRd ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH1 , XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_UPPER , & DrpVal ) ; XVphy_DrpRd ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH2 , XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_LOWER , & DrpVal_lower_lane1 ) ; XVphy_DrpRd ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH2 , XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_UPPER , & DrpVal ) ; XVphy_DrpRd ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH3 , XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_LOWER , & DrpVal_lower_lane2 ) ; XVphy_DrpRd ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH3 , XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_UPPER , & DrpVal ) ; XVphy_DrpRd ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH4 , XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_LOWER , & DrpVal_lower_lane3 ) ; XVphy_DrpRd ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH4 , XVPHY_DRP_GTHE4_PRBS_ERR_CNTR_UPPER , & DrpVal ) ; #endif ReadVal = XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_DPC_LINK_QUAL_CONFIG ) ; if ( ( ReadVal & 0x7 ) == XDP_RX_DPCD_LINK_QUAL_PRBS ) { XDp_WriteReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_DPC_L01_PRBS_CNTR , ( 0x8000 | DrpVal_lower_lane0 ) | ( ( 0x8000 | DrpVal_lower_lane1 ) << 16 ) ) ; XDp_WriteReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_DPC_L23_PRBS_CNTR , ( 0x8000 | DrpVal_lower_lane2 ) | ( ( 0x8000 | DrpVal_lower_lane3 ) << 16 ) ) ; } else { XDp_WriteReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_DPC_L01_PRBS_CNTR , SymErrVal_lane01 | 0x80008000 ) ; XDp_WriteReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_DPC_L23_PRBS_CNTR , SymErrVal_lane23 | 0x80008000 ) ; } #if PRBS_ERRCNTR_CLEAR_ON_READ if ( ( ( ReadVal & 0x7 ) == XDP_RX_DPCD_LINK_QUAL_PRBS ) && ( DrpVal_lower_lane0 != 0x0 || DrpVal_lower_lane1 != 0x0 || DrpVal_lower_lane2 != 0x0 || DrpVal_lower_lane3 != 0x0 ) ) { #ifndef versal DrpValConfig = XVphy_ReadReg ( VPhyInst . Config . BaseAddr , XVPHY_RX_CONTROL_REG ) ; DrpValConfig = DrpValConfig | 0x08080808 ; XDp_WriteReg ( VPhyInst . Config . BaseAddr , XVPHY_RX_CONTROL_REG , DrpValConfig ) ; DrpValConfig = XVphy_ReadReg ( VPhyInst . Config . BaseAddr , XVPHY_RX_CONTROL_REG ) ; DrpValConfig = DrpValConfig & 0xF7F7F7F7 ; XVphy_WriteReg ( VPhyInst . Config . BaseAddr , XVPHY_RX_CONTROL_REG , DrpValConfig ) ; #endif } #endif xil_printf ( " \r \n " ) ; }
This function is the callback function for Access prbs error count.
This function is the callback function for Access prbs error count .
/*Read twice from VPHY*/ /*Read PRBS Error Counter Value from Video PHY*/ /*Lane 0 - Store only lower 16 bits*/ /*Lane 1 - Store only lower 16 bits*/ /*Lane 2 - Store only lower 16 bits*/ /*Lane 3 - Store only lower 16 bits*/ //	xil_printf("XDP_RX_DPC_LINK_QUAL_CONFIG: 0x%x\r\n",ReadVal); /*Write into DP Core - Validity bit and lower 15 bit counter value*/ /*Write PRBS Values from GT to DPCD Error Reg Space*/ /*Write symbol error counter values from VPHY to DPCD Error Reg Space*/ /* Reset PRBS7 Counters */