XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example_intr_dma.c
static LONG EmacPsSetupIntrSystem(INTC *IntcInstancePtr,
				  XEmacPs *EmacPsInstancePtr,
				  u16 EmacPsIntrId)
{
	LONG Status;

#ifdef XPAR_INTC_0_DEVICE_ID

	#ifndef TESTAPP_GEN
	/*
	 * Initialize the interrupt controller driver so that it's ready to
	 * use.
	 */
	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	#endif

	/*
	 * Connect the handler that will be called when an interrupt
	 * for the device occurs, the handler defined above performs the
	 * specific interrupt processing for the device.
	 */
	Status = XIntc_Connect(IntcInstancePtr, EmacPsIntrId,
		(XInterruptHandler) XEmacPs_IntrHandler, EmacPsInstancePtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	#ifndef TESTAPP_GEN
/*
 * Start the interrupt controller such that interrupts are enabled for
 * all devices that cause interrupts.
 */

	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	#endif

	/*
	 * Enable the interrupt from the hardware
	 */
	XIntc_Enable(IntcInstancePtr, EmacPsIntrId);

	#ifndef TESTAPP_GEN
	/*
	 * Initialize the exception table.
	 */
	Xil_ExceptionInit();

	/*
	 * Register the interrupt controller handler with the exception table.
	 */
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
				(Xil_ExceptionHandler) XIntc_InterruptHandler,
					IntcInstancePtr);
	#endif

#else
#ifndef TESTAPP_GEN
	XScuGic_Config *GicConfig;
	Xil_ExceptionInit();

	/*
	 * Initialize the interrupt controller driver so that it is ready to
	 * use.
	 */
	GicConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
	if (NULL == GicConfig) {
		return XST_FAILURE;
	}

	Status = XScuGic_CfgInitialize(IntcInstancePtr, GicConfig,
		    GicConfig->CpuBaseAddress);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}


	/*
	 * Connect the interrupt controller interrupt handler to the hardware
	 * interrupt handling logic in the processor.
	 */
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
			(Xil_ExceptionHandler)XScuGic_InterruptHandler,
			IntcInstancePtr);
#endif

	/*
	 * Connect a device driver handler that will be called when an
	 * interrupt for the device occurs, the device driver handler performs
	 * the specific interrupt processing for the device.
	 */
	Status = XScuGic_Connect(IntcInstancePtr, EmacPsIntrId,
			(Xil_InterruptHandler) XEmacPs_IntrHandler,
			(void *) EmacPsInstancePtr);
	if (Status != XST_SUCCESS) {
		EmacPsUtilErrorTrap
			("Unable to connect ISR to interrupt controller");
		return XST_FAILURE;
	}

	/*
	 * Enable interrupts from the hardware
	 */
	XScuGic_Enable(IntcInstancePtr, EmacPsIntrId);
#endif
#ifndef TESTAPP_GEN
	/*
	 * Enable interrupts in the processor
	 */
	Xil_ExceptionEnable();
#endif
	return XST_SUCCESS;
}
/****************************************************************************/
/**
*
* This function setups the interrupt system so interrupts can occur for the
* EMACPS.
* @param	IntcInstancePtr is a pointer to the instance of the Intc driver.
* @param	EmacPsInstancePtr is a pointer to the instance of the EmacPs
*		driver.
* @param	EmacPsIntrId is the Interrupt ID and is typically
*		XPAR_<EMACPS_instance>_INTR value from xparameters.h.
*
* @return	XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note		None.
*
*****************************************************************************/
This function setups the interrupt system so interrupts can occur for the
EMACPS.
This function setups the interrupt system so interrupts can occur for the EMACPS .
static LONG EmacPsSetupIntrSystem(INTC *IntcInstancePtr,
				  XEmacPs *EmacPsInstancePtr,
				  u16 EmacPsIntrId)
{
	LONG Status;
#ifdef XPAR_INTC_0_DEVICE_ID
	#ifndef TESTAPP_GEN
	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	#endif
	Status = XIntc_Connect(IntcInstancePtr, EmacPsIntrId,
		(XInterruptHandler) XEmacPs_IntrHandler, EmacPsInstancePtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	#ifndef TESTAPP_GEN
	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	#endif
	XIntc_Enable(IntcInstancePtr, EmacPsIntrId);
	#ifndef TESTAPP_GEN
	Xil_ExceptionInit();
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
				(Xil_ExceptionHandler) XIntc_InterruptHandler,
					IntcInstancePtr);
	#endif
#else
#ifndef TESTAPP_GEN
	XScuGic_Config *GicConfig;
	Xil_ExceptionInit();
	GicConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
	if (NULL == GicConfig) {
		return XST_FAILURE;
	}
	Status = XScuGic_CfgInitialize(IntcInstancePtr, GicConfig,
		    GicConfig->CpuBaseAddress);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
			(Xil_ExceptionHandler)XScuGic_InterruptHandler,
			IntcInstancePtr);
#endif
	Status = XScuGic_Connect(IntcInstancePtr, EmacPsIntrId,
			(Xil_InterruptHandler) XEmacPs_IntrHandler,
			(void *) EmacPsInstancePtr);
	if (Status != XST_SUCCESS) {
		EmacPsUtilErrorTrap
			("Unable to connect ISR to interrupt controller");
		return XST_FAILURE;
	}
	XScuGic_Enable(IntcInstancePtr, EmacPsIntrId);
#endif
#ifndef TESTAPP_GEN
	Xil_ExceptionEnable();
#endif
	return XST_SUCCESS;
}
static LONG EmacPsSetupIntrSystem ( INTC * IntcInstancePtr , XEmacPs * EmacPsInstancePtr , u16 EmacPsIntrId ) { LONG Status ; #ifdef XPAR_INTC_0_DEVICE_ID #ifndef TESTAPP_GEN Status = XIntc_Initialize ( IntcInstancePtr , INTC_DEVICE_ID ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } #endif Status = XIntc_Connect ( IntcInstancePtr , EmacPsIntrId , ( XInterruptHandler ) XEmacPs_IntrHandler , EmacPsInstancePtr ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } #ifndef TESTAPP_GEN Status = XIntc_Start ( IntcInstancePtr , XIN_REAL_MODE ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } #endif XIntc_Enable ( IntcInstancePtr , EmacPsIntrId ) ; #ifndef TESTAPP_GEN Xil_ExceptionInit ( ) ; Xil_ExceptionRegisterHandler ( XIL_EXCEPTION_ID_INT , ( Xil_ExceptionHandler ) XIntc_InterruptHandler , IntcInstancePtr ) ; #endif #else #ifndef TESTAPP_GEN XScuGic_Config * GicConfig ; Xil_ExceptionInit ( ) ; GicConfig = XScuGic_LookupConfig ( INTC_DEVICE_ID ) ; if ( NULL == GicConfig ) { return XST_FAILURE ; } Status = XScuGic_CfgInitialize ( IntcInstancePtr , GicConfig , GicConfig -> CpuBaseAddress ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } Xil_ExceptionRegisterHandler ( XIL_EXCEPTION_ID_IRQ_INT , ( Xil_ExceptionHandler ) XScuGic_InterruptHandler , IntcInstancePtr ) ; #endif Status = XScuGic_Connect ( IntcInstancePtr , EmacPsIntrId , ( Xil_InterruptHandler ) XEmacPs_IntrHandler , ( void * ) EmacPsInstancePtr ) ; if ( Status != XST_SUCCESS ) { EmacPsUtilErrorTrap ( " " ) ; return XST_FAILURE ; } XScuGic_Enable ( IntcInstancePtr , EmacPsIntrId ) ; #endif #ifndef TESTAPP_GEN Xil_ExceptionEnable ( ) ; #endif return XST_SUCCESS ; }
This function setups the interrupt system so interrupts can occur for the
EMACPS.
This function setups the interrupt system so interrupts can occur for the EMACPS .
/*
	 * Initialize the interrupt controller driver so that it's ready to
	 * use.
	 */ /*
	 * Connect the handler that will be called when an interrupt
	 * for the device occurs, the handler defined above performs the
	 * specific interrupt processing for the device.
	 */ /*
 * Start the interrupt controller such that interrupts are enabled for
 * all devices that cause interrupts.
 */ /*
	 * Enable the interrupt from the hardware
	 */ /*
	 * Initialize the exception table.
	 */ /*
	 * Register the interrupt controller handler with the exception table.
	 */ /*
	 * Initialize the interrupt controller driver so that it is ready to
	 * use.
	 */ /*
	 * Connect the interrupt controller interrupt handler to the hardware
	 * interrupt handling logic in the processor.
	 */ /*
	 * Connect a device driver handler that will be called when an
	 * interrupt for the device occurs, the device driver handler performs
	 * the specific interrupt processing for the device.
	 */ /*
	 * Enable interrupts from the hardware
	 */ /*
	 * Enable interrupts in the processor
	 */