XilinxProcessorIPLib/drivers/v_hscaler/src/xv_hscaler_l2.c
static void XV_HScalerSetCoeff(XV_Hscaler_l2 *HscPtr)
{
  int num_phases = 1<<HscPtr->Hsc.Config.PhaseShift;
  int num_taps   = HscPtr->Hsc.Config.NumTaps/2;
  int val,i,j,offset,rdIndx;
  UINTPTR baseAddr;

  offset = (XV_HSCALER_MAX_H_TAPS - HscPtr->Hsc.Config.NumTaps)/2;
  baseAddr = XV_hscaler_Get_HwReg_hfltCoeff_BaseAddress(&HscPtr->Hsc);
  for (i = 0; i < num_phases; i++)
  {
    for(j=0; j < num_taps; j++)
    {
       rdIndx = j*2+offset;
       val = (HscPtr->coeff[i][rdIndx+1] << 16) | (HscPtr->coeff[i][rdIndx] & XHSC_MASK_LOW_16BITS);
       Xil_Out32(baseAddr+((i*num_taps+j)*4), val);
    }
  }
}
/*****************************************************************************/
/**
* This function programs the filter coefficients and phase data into core
* registers
*
* @param  HscPtr is a pointer to the core instance to be worked on.
*
* @return None
*
* @Note  This version of driver does not make use of computed coefficients.
*        User must load the coefficients, using the provided API, before
*        scaler can be used
******************************************************************************/
This function programs the filter coefficients and phase data into core
registers
This function programs the filter coefficients and phase data into core registers
static void XV_HScalerSetCoeff(XV_Hscaler_l2 *HscPtr)
{
  int num_phases = 1<<HscPtr->Hsc.Config.PhaseShift;
  int num_taps   = HscPtr->Hsc.Config.NumTaps/2;
  int val,i,j,offset,rdIndx;
  UINTPTR baseAddr;
  offset = (XV_HSCALER_MAX_H_TAPS - HscPtr->Hsc.Config.NumTaps)/2;
  baseAddr = XV_hscaler_Get_HwReg_hfltCoeff_BaseAddress(&HscPtr->Hsc);
  for (i = 0; i < num_phases; i++)
  {
    for(j=0; j < num_taps; j++)
    {
       rdIndx = j*2+offset;
       val = (HscPtr->coeff[i][rdIndx+1] << 16) | (HscPtr->coeff[i][rdIndx] & XHSC_MASK_LOW_16BITS);
       Xil_Out32(baseAddr+((i*num_taps+j)*4), val);
    }
  }
}
static void XV_HScalerSetCoeff ( XV_Hscaler_l2 * HscPtr ) { int num_phases = 1 << HscPtr -> Hsc . Config . PhaseShift ; int num_taps = HscPtr -> Hsc . Config . NumTaps / 2 ; int val , i , j , offset , rdIndx ; UINTPTR baseAddr ; offset = ( XV_HSCALER_MAX_H_TAPS - HscPtr -> Hsc . Config . NumTaps ) / 2 ; baseAddr = XV_hscaler_Get_HwReg_hfltCoeff_BaseAddress ( & HscPtr -> Hsc ) ; for ( i = 0 ; i < num_phases ; i ++ ) { for ( j = 0 ; j < num_taps ; j ++ ) { rdIndx = j * 2 + offset ; val = ( HscPtr -> coeff [ i ] [ rdIndx + 1 ] << 16 ) | ( HscPtr -> coeff [ i ] [ rdIndx ] & XHSC_MASK_LOW_16BITS ) ; Xil_Out32 ( baseAddr + ( ( i * num_taps + j ) * 4 ) , val ) ; } } }
This function programs the filter coefficients and phase data into core
registers
This function programs the filter coefficients and phase data into core registers