src/dpdk/drivers/net/e1000/igb_ethdev.c
static inline void
igb_inject_flex_filter(struct rte_eth_dev *dev,
			   struct e1000_flex_filter *filter)
{
	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
	uint32_t wufc, queueing;
	uint32_t reg_off;
	uint8_t i, j = 0;

	wufc = E1000_READ_REG(hw, E1000_WUFC);
	if (filter->index < E1000_MAX_FHFT)
		reg_off = E1000_FHFT(filter->index);
	else
		reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);

	E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
			(E1000_WUFC_FLX0 << filter->index));
	queueing = filter->filter_info.len |
		(filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
		(filter->filter_info.priority <<
			E1000_FHFT_QUEUEING_PRIO_SHIFT);
	E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
			queueing);

	for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
		E1000_WRITE_REG(hw, reg_off,
				filter->filter_info.dwords[j]);
		reg_off += sizeof(uint32_t);
		E1000_WRITE_REG(hw, reg_off,
				filter->filter_info.dwords[++j]);
		reg_off += sizeof(uint32_t);
		E1000_WRITE_REG(hw, reg_off,
			(uint32_t)filter->filter_info.mask[i]);
		reg_off += sizeof(uint32_t) * 2;
		++j;
	}
}
/* inject a igb flex filter to HW */
inject a igb flex filter to HW
inject a igb flex filter to HW
static inline void
igb_inject_flex_filter(struct rte_eth_dev *dev,
			   struct e1000_flex_filter *filter)
{
	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
	uint32_t wufc, queueing;
	uint32_t reg_off;
	uint8_t i, j = 0;
	wufc = E1000_READ_REG(hw, E1000_WUFC);
	if (filter->index < E1000_MAX_FHFT)
		reg_off = E1000_FHFT(filter->index);
	else
		reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
	E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
			(E1000_WUFC_FLX0 << filter->index));
	queueing = filter->filter_info.len |
		(filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
		(filter->filter_info.priority <<
			E1000_FHFT_QUEUEING_PRIO_SHIFT);
	E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
			queueing);
	for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
		E1000_WRITE_REG(hw, reg_off,
				filter->filter_info.dwords[j]);
		reg_off += sizeof(uint32_t);
		E1000_WRITE_REG(hw, reg_off,
				filter->filter_info.dwords[++j]);
		reg_off += sizeof(uint32_t);
		E1000_WRITE_REG(hw, reg_off,
			(uint32_t)filter->filter_info.mask[i]);
		reg_off += sizeof(uint32_t) * 2;
		++j;
	}
}
static inline void igb_inject_flex_filter ( struct rte_eth_dev * dev , struct e1000_flex_filter * filter ) { struct e1000_hw * hw = E1000_DEV_PRIVATE_TO_HW ( dev -> data -> dev_private ) ; uint32_t wufc , queueing ; uint32_t reg_off ; uint8_t i , j = 0 ; wufc = E1000_READ_REG ( hw , E1000_WUFC ) ; if ( filter -> index < E1000_MAX_FHFT ) reg_off = E1000_FHFT ( filter -> index ) ; else reg_off = E1000_FHFT_EXT ( filter -> index - E1000_MAX_FHFT ) ; E1000_WRITE_REG ( hw , E1000_WUFC , wufc | E1000_WUFC_FLEX_HQ | ( E1000_WUFC_FLX0 << filter -> index ) ) ; queueing = filter -> filter_info . len | ( filter -> queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT ) | ( filter -> filter_info . priority << E1000_FHFT_QUEUEING_PRIO_SHIFT ) ; E1000_WRITE_REG ( hw , reg_off + E1000_FHFT_QUEUEING_OFFSET , queueing ) ; for ( i = 0 ; i < E1000_FLEX_FILTERS_MASK_SIZE ; i ++ ) { E1000_WRITE_REG ( hw , reg_off , filter -> filter_info . dwords [ j ] ) ; reg_off += sizeof ( uint32_t ) ; E1000_WRITE_REG ( hw , reg_off , filter -> filter_info . dwords [ ++ j ] ) ; reg_off += sizeof ( uint32_t ) ; E1000_WRITE_REG ( hw , reg_off , ( uint32_t ) filter -> filter_info . mask [ i ] ) ; reg_off += sizeof ( uint32_t ) * 2 ; ++ j ; } }
inject a igb flex filter to HW
inject a igb flex filter to HW