XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe4.c
u32 XVphy_Gthe4ClkCmnReconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId CmnId)
{
	u16 DrpVal;
	u16 WriteVal;
	u32 QpllxVcoRateMHz;
	u32 QpllxClkOutMHz;
    u32 Status = XST_SUCCESS;

	/* Obtain current DRP register value for QPLLx_FBDIV. */
	Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x14 : 0x94, &DrpVal);
	/* Mask out QPLLx_FBDIV. */
	DrpVal &= ~(0xFF);
	/* Set QPLLx_FBDIV. */
	WriteVal = (XVphy_NToDrpEncoding(InstancePtr, QuadId, CmnId, 0) & 0xFF);
	DrpVal |= WriteVal;
	/* Write new DRP register value for QPLLx_FBDIV. */
	Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x14 : 0x94, DrpVal);

	/* Obtain current DRP register value for QPLLx_REFCLK_DIV. */
	Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x18 : 0x98, &DrpVal);
	/* Mask out QPLLx_REFCLK_DIV. */
	DrpVal &= ~(0xF80);
	/* Disable Intelligent Reference Clock Selection */
	if (XVphy_GetRefClkSourcesCount(InstancePtr) > 1) {
		DrpVal |= (1 << 6);
	}
	/* Set QPLLx_REFCLK_DIV. */
	WriteVal = (XVphy_MToDrpEncoding(InstancePtr, QuadId, CmnId) & 0x1F);
	DrpVal |= (WriteVal << 7);
	/* Write new DRP register value for QPLLx_REFCLK_DIV. */
	Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x18 : 0x98, DrpVal);

	if ((XVphy_IsHDMI(InstancePtr, XVPHY_DIR_TX)) ||
		(XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX))) {

		QpllxVcoRateMHz = XVphy_GetPllVcoFreqHz(InstancePtr, QuadId, CmnId,
				XVphy_IsTxUsingQpll(InstancePtr, QuadId, CmnId) ?
						XVPHY_DIR_TX : XVPHY_DIR_RX) / 1000000;
		QpllxClkOutMHz = QpllxVcoRateMHz / 2;

		/* PPFx_CFG */
		Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
                (CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x0D : 0x8D, &DrpVal);
		DrpVal &= ~(0x0FC0);
		/* PPF_MUX_CRNT_CTRL0 */
		if (QpllxVcoRateMHz >= 15000) {
			DrpVal |= 0x0E00;
		}
		else if (QpllxVcoRateMHz >= 11000) {
			DrpVal |= 0x0800;
		}
		else if (QpllxVcoRateMHz >= 7000) {
			DrpVal |= 0x0600;
		}
		else {
			DrpVal |= 0x0400;
		}
		/* PPF_MUX_TERM_CTRL0 */
		if (QpllxVcoRateMHz >= 13000) {
			DrpVal |= 0x0100;
		}
		else {
			DrpVal |= 0x0000;
		}
		/* Write new DRP register value for PPFx_CFG. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x0D : 0x8D, DrpVal);

		/* QPLLx_CP */
		if (InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(CmnId)].
				PllParams.NFbDiv <= 40) {
			DrpVal = 0x007F;
		}
		else {
			DrpVal = 0x03FF;
		}
		/* Write new DRP register value for QPLLx_CP. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x16 : 0x96, DrpVal);

		/* QPLLx_LPF */
		Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
            (CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x19 : 0x99, &DrpVal);
		DrpVal &= ~(0x0003);
		if (InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(CmnId)].
				PllParams.NFbDiv <= 40) {
			DrpVal |= 0x3;
		}
		else {
			DrpVal |= 0x1;
		}
		/* Write new DRP register value for QPLLx_LPF. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x19 : 0x99, DrpVal);

		/* QPLLx_CFG4 */
		Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
            (CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x30 : 0xB0, &DrpVal);
		DrpVal &= ~(0x00E7);
		/* Q_TERM_CLK */
		if (QpllxClkOutMHz >= 7500) {
			DrpVal |= 0x2 << 5;
		}
		else if (QpllxClkOutMHz >= 3500) {
			DrpVal |= 0x0 << 5;
		}
		else {
			DrpVal |= 0x6 << 5;
		}
		/* Q_DCRNT_CLK */
		if (QpllxClkOutMHz >= 7500) {
			DrpVal |= 0x5;
		}
		else if (QpllxClkOutMHz >= 5500) {
			DrpVal |= 0x4;
		}
		else {
			DrpVal |= 0x3;
		}
		/* Write new DRP register value for QPLLx_CFG4. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x30 : 0xB0, DrpVal);
	}

	return Status;
}
/*****************************************************************************/
/**
* This function will configure the common channel clock settings.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	CmnId is the common channel ID to operate on.
*
* @return
*		- XST_SUCCESS if the configuration was successful.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function will configure the common channel clock settings.
This function will configure the common channel clock settings .
u32 XVphy_Gthe4ClkCmnReconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId CmnId)
{
	u16 DrpVal;
	u16 WriteVal;
	u32 QpllxVcoRateMHz;
	u32 QpllxClkOutMHz;
    u32 Status = XST_SUCCESS;
	Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x14 : 0x94, &DrpVal);
	DrpVal &= ~(0xFF);
	WriteVal = (XVphy_NToDrpEncoding(InstancePtr, QuadId, CmnId, 0) & 0xFF);
	DrpVal |= WriteVal;
	Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x14 : 0x94, DrpVal);
	Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x18 : 0x98, &DrpVal);
	DrpVal &= ~(0xF80);
	if (XVphy_GetRefClkSourcesCount(InstancePtr) > 1) {
		DrpVal |= (1 << 6);
	}
	WriteVal = (XVphy_MToDrpEncoding(InstancePtr, QuadId, CmnId) & 0x1F);
	DrpVal |= (WriteVal << 7);
	Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x18 : 0x98, DrpVal);
	if ((XVphy_IsHDMI(InstancePtr, XVPHY_DIR_TX)) ||
		(XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX))) {
		QpllxVcoRateMHz = XVphy_GetPllVcoFreqHz(InstancePtr, QuadId, CmnId,
				XVphy_IsTxUsingQpll(InstancePtr, QuadId, CmnId) ?
						XVPHY_DIR_TX : XVPHY_DIR_RX) / 1000000;
		QpllxClkOutMHz = QpllxVcoRateMHz / 2;
		Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
                (CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x0D : 0x8D, &DrpVal);
		DrpVal &= ~(0x0FC0);
		if (QpllxVcoRateMHz >= 15000) {
			DrpVal |= 0x0E00;
		}
		else if (QpllxVcoRateMHz >= 11000) {
			DrpVal |= 0x0800;
		}
		else if (QpllxVcoRateMHz >= 7000) {
			DrpVal |= 0x0600;
		}
		else {
			DrpVal |= 0x0400;
		}
		if (QpllxVcoRateMHz >= 13000) {
			DrpVal |= 0x0100;
		}
		else {
			DrpVal |= 0x0000;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x0D : 0x8D, DrpVal);
		if (InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(CmnId)].
				PllParams.NFbDiv <= 40) {
			DrpVal = 0x007F;
		}
		else {
			DrpVal = 0x03FF;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x16 : 0x96, DrpVal);
		Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
            (CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x19 : 0x99, &DrpVal);
		DrpVal &= ~(0x0003);
		if (InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(CmnId)].
				PllParams.NFbDiv <= 40) {
			DrpVal |= 0x3;
		}
		else {
			DrpVal |= 0x1;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x19 : 0x99, DrpVal);
		Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
            (CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x30 : 0xB0, &DrpVal);
		DrpVal &= ~(0x00E7);
		if (QpllxClkOutMHz >= 7500) {
			DrpVal |= 0x2 << 5;
		}
		else if (QpllxClkOutMHz >= 3500) {
			DrpVal |= 0x0 << 5;
		}
		else {
			DrpVal |= 0x6 << 5;
		}
		if (QpllxClkOutMHz >= 7500) {
			DrpVal |= 0x5;
		}
		else if (QpllxClkOutMHz >= 5500) {
			DrpVal |= 0x4;
		}
		else {
			DrpVal |= 0x3;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x30 : 0xB0, DrpVal);
	}
	return Status;
}
u32 XVphy_Gthe4ClkCmnReconfig ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId CmnId ) { u16 DrpVal ; u16 WriteVal ; u32 QpllxVcoRateMHz ; u32 QpllxClkOutMHz ; u32 Status = XST_SUCCESS ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x14 : 0x94 , & DrpVal ) ; DrpVal &= ~ ( 0xFF ) ; WriteVal = ( XVphy_NToDrpEncoding ( InstancePtr , QuadId , CmnId , 0 ) & 0xFF ) ; DrpVal |= WriteVal ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x14 : 0x94 , DrpVal ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x18 : 0x98 , & DrpVal ) ; DrpVal &= ~ ( 0xF80 ) ; if ( XVphy_GetRefClkSourcesCount ( InstancePtr ) > 1 ) { DrpVal |= ( 1 << 6 ) ; } WriteVal = ( XVphy_MToDrpEncoding ( InstancePtr , QuadId , CmnId ) & 0x1F ) ; DrpVal |= ( WriteVal << 7 ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x18 : 0x98 , DrpVal ) ; if ( ( XVphy_IsHDMI ( InstancePtr , XVPHY_DIR_TX ) ) || ( XVphy_IsHDMI ( InstancePtr , XVPHY_DIR_RX ) ) ) { QpllxVcoRateMHz = XVphy_GetPllVcoFreqHz ( InstancePtr , QuadId , CmnId , XVphy_IsTxUsingQpll ( InstancePtr , QuadId , CmnId ) ? XVPHY_DIR_TX : XVPHY_DIR_RX ) / 1000000 ; QpllxClkOutMHz = QpllxVcoRateMHz / 2 ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x0D : 0x8D , & DrpVal ) ; DrpVal &= ~ ( 0x0FC0 ) ; if ( QpllxVcoRateMHz >= 15000 ) { DrpVal |= 0x0E00 ; } else if ( QpllxVcoRateMHz >= 11000 ) { DrpVal |= 0x0800 ; } else if ( QpllxVcoRateMHz >= 7000 ) { DrpVal |= 0x0600 ; } else { DrpVal |= 0x0400 ; } if ( QpllxVcoRateMHz >= 13000 ) { DrpVal |= 0x0100 ; } else { DrpVal |= 0x0000 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x0D : 0x8D , DrpVal ) ; if ( InstancePtr -> Quads [ QuadId ] . Plls [ XVPHY_CH2IDX ( CmnId ) ] . PllParams . NFbDiv <= 40 ) { DrpVal = 0x007F ; } else { DrpVal = 0x03FF ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x16 : 0x96 , DrpVal ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x19 : 0x99 , & DrpVal ) ; DrpVal &= ~ ( 0x0003 ) ; if ( InstancePtr -> Quads [ QuadId ] . Plls [ XVPHY_CH2IDX ( CmnId ) ] . PllParams . NFbDiv <= 40 ) { DrpVal |= 0x3 ; } else { DrpVal |= 0x1 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x19 : 0x99 , DrpVal ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x30 : 0xB0 , & DrpVal ) ; DrpVal &= ~ ( 0x00E7 ) ; if ( QpllxClkOutMHz >= 7500 ) { DrpVal |= 0x2 << 5 ; } else if ( QpllxClkOutMHz >= 3500 ) { DrpVal |= 0x0 << 5 ; } else { DrpVal |= 0x6 << 5 ; } if ( QpllxClkOutMHz >= 7500 ) { DrpVal |= 0x5 ; } else if ( QpllxClkOutMHz >= 5500 ) { DrpVal |= 0x4 ; } else { DrpVal |= 0x3 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x30 : 0xB0 , DrpVal ) ; } return Status ; }
This function will configure the common channel clock settings.
This function will configure the common channel clock settings .
/* Obtain current DRP register value for QPLLx_FBDIV. */ /* Mask out QPLLx_FBDIV. */ /* Set QPLLx_FBDIV. */ /* Write new DRP register value for QPLLx_FBDIV. */ /* Obtain current DRP register value for QPLLx_REFCLK_DIV. */ /* Mask out QPLLx_REFCLK_DIV. */ /* Disable Intelligent Reference Clock Selection */ /* Set QPLLx_REFCLK_DIV. */ /* Write new DRP register value for QPLLx_REFCLK_DIV. */ /* PPFx_CFG */ /* PPF_MUX_CRNT_CTRL0 */ /* PPF_MUX_TERM_CTRL0 */ /* Write new DRP register value for PPFx_CFG. */ /* QPLLx_CP */ /* Write new DRP register value for QPLLx_CP. */ /* QPLLx_LPF */ /* Write new DRP register value for QPLLx_LPF. */ /* QPLLx_CFG4 */ /* Q_TERM_CLK */ /* Q_DCRNT_CLK */ /* Write new DRP register value for QPLLx_CFG4. */