XilinxProcessorIPLib/drivers/tmrctr/src/xtmrctr_intr.c
void XTmrCtr_InterruptHandler(void *InstancePtr)
{
	XTmrCtr *TmrCtrPtr = NULL;
	u8 TmrCtrNumber;
	u32 ControlStatusReg;

	/*
	 * Verify that each of the inputs are valid.
	 */
	Xil_AssertVoid(InstancePtr != NULL);

	/*
	 * Convert the non-typed pointer to an timer/counter instance pointer
	 * such that there is access to the timer/counter
	 */
	TmrCtrPtr = (XTmrCtr *) InstancePtr;

	/*
	 * Loop thru each timer counter in the device and call the callback
	 * function for each timer which has caused an interrupt
	 */
	for (TmrCtrNumber = 0;
		TmrCtrNumber < XTC_DEVICE_TIMER_COUNT; TmrCtrNumber++) {

		ControlStatusReg = XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress,
						   TmrCtrNumber,
						   XTC_TCSR_OFFSET);
		/*
		 * Check if interrupt is enabled
		 */
		if (ControlStatusReg & XTC_CSR_ENABLE_INT_MASK) {

			/*
			 * Check if timer expired and interrupt occured
			 */
			if (ControlStatusReg & XTC_CSR_INT_OCCURED_MASK) {
				/*
				 * Increment statistics for the number of
				 * interrupts and call the callback to handle
				 * any application specific processing
				 */
				TmrCtrPtr->Stats.Interrupts++;
				TmrCtrPtr->Handler(TmrCtrPtr->CallBackRef,
						   TmrCtrNumber);
				/*
				 * Read the new Control/Status Register content.
				 */
				ControlStatusReg =
					XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress,
								TmrCtrNumber,
								XTC_TCSR_OFFSET);
				/*
				 * If in compare mode and a single shot rather
				 * than auto reload mode then disable the timer
				 * and reset it such so that the interrupt can
				 * be acknowledged, this should be only temporary
				 * till the hardware is fixed
				 */
				if (((ControlStatusReg &
					XTC_CSR_AUTO_RELOAD_MASK) == 0) &&
					((ControlStatusReg &
					  XTC_CSR_CAPTURE_MODE_MASK)== 0)) {
						/*
						 * Disable the timer counter and
						 * reset it such that the timer
						 * counter is loaded with the
						 * reset value allowing the
						 * interrupt to be acknowledged
						 */
						ControlStatusReg &=
							(u32)~XTC_CSR_ENABLE_TMR_MASK;

						XTmrCtr_WriteReg(
							TmrCtrPtr->BaseAddress,
							TmrCtrNumber,
							XTC_TCSR_OFFSET,
							ControlStatusReg |
							XTC_CSR_LOAD_MASK);

						/*
						 * Clear the reset condition,
						 * the reset bit must be
						 * manually cleared by a 2nd write
						 * to the register
						 */
						XTmrCtr_WriteReg(
							TmrCtrPtr->BaseAddress,
							TmrCtrNumber,
							XTC_TCSR_OFFSET,
							ControlStatusReg);
				}

				/*
				 * Acknowledge the interrupt by clearing the
				 * interrupt bit in the timer control status
				 * register, this is done after calling the
				 * handler so the application could call
				 * IsExpired, the interrupt is cleared by
				 * writing a 1 to the interrupt bit of the
				 * register without changing any of the other
				 * bits
				 */
				XTmrCtr_WriteReg(TmrCtrPtr->BaseAddress,
						 TmrCtrNumber,
						 XTC_TCSR_OFFSET,
						 ControlStatusReg |
						 XTC_CSR_INT_OCCURED_MASK);
			}
		}
	}
}
/*****************************************************************************/
/**
*
* Interrupt Service Routine (ISR) for the driver.  This function only performs
* processing for the device and does not save and restore the interrupt context.
*
* @param	InstancePtr contains a pointer to the timer/counter instance for
*		the interrupt.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
Interrupt Service Routine (ISR) for the driver.  This function only performs
processing for the device and does not save and restore the interrupt context.
Interrupt Service Routine ( ISR ) for the driver . This function only performs processing for the device and does not save and restore the interrupt context .
void XTmrCtr_InterruptHandler(void *InstancePtr)
{
	XTmrCtr *TmrCtrPtr = NULL;
	u8 TmrCtrNumber;
	u32 ControlStatusReg;
	Xil_AssertVoid(InstancePtr != NULL);
	TmrCtrPtr = (XTmrCtr *) InstancePtr;
	for (TmrCtrNumber = 0;
		TmrCtrNumber < XTC_DEVICE_TIMER_COUNT; TmrCtrNumber++) {
		ControlStatusReg = XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress,
						   TmrCtrNumber,
						   XTC_TCSR_OFFSET);
		if (ControlStatusReg & XTC_CSR_ENABLE_INT_MASK) {
			if (ControlStatusReg & XTC_CSR_INT_OCCURED_MASK) {
				TmrCtrPtr->Stats.Interrupts++;
				TmrCtrPtr->Handler(TmrCtrPtr->CallBackRef,
						   TmrCtrNumber);
				ControlStatusReg =
					XTmrCtr_ReadReg(TmrCtrPtr->BaseAddress,
								TmrCtrNumber,
								XTC_TCSR_OFFSET);
				if (((ControlStatusReg &
					XTC_CSR_AUTO_RELOAD_MASK) == 0) &&
					((ControlStatusReg &
					  XTC_CSR_CAPTURE_MODE_MASK)== 0)) {
						ControlStatusReg &=
							(u32)~XTC_CSR_ENABLE_TMR_MASK;
						XTmrCtr_WriteReg(
							TmrCtrPtr->BaseAddress,
							TmrCtrNumber,
							XTC_TCSR_OFFSET,
							ControlStatusReg |
							XTC_CSR_LOAD_MASK);
						XTmrCtr_WriteReg(
							TmrCtrPtr->BaseAddress,
							TmrCtrNumber,
							XTC_TCSR_OFFSET,
							ControlStatusReg);
				}
				XTmrCtr_WriteReg(TmrCtrPtr->BaseAddress,
						 TmrCtrNumber,
						 XTC_TCSR_OFFSET,
						 ControlStatusReg |
						 XTC_CSR_INT_OCCURED_MASK);
			}
		}
	}
}
void XTmrCtr_InterruptHandler ( void * InstancePtr ) { XTmrCtr * TmrCtrPtr = NULL ; u8 TmrCtrNumber ; u32 ControlStatusReg ; Xil_AssertVoid ( InstancePtr != NULL ) ; TmrCtrPtr = ( XTmrCtr * ) InstancePtr ; for ( TmrCtrNumber = 0 ; TmrCtrNumber < XTC_DEVICE_TIMER_COUNT ; TmrCtrNumber ++ ) { ControlStatusReg = XTmrCtr_ReadReg ( TmrCtrPtr -> BaseAddress , TmrCtrNumber , XTC_TCSR_OFFSET ) ; if ( ControlStatusReg & XTC_CSR_ENABLE_INT_MASK ) { if ( ControlStatusReg & XTC_CSR_INT_OCCURED_MASK ) { TmrCtrPtr -> Stats . Interrupts ++ ; TmrCtrPtr -> Handler ( TmrCtrPtr -> CallBackRef , TmrCtrNumber ) ; ControlStatusReg = XTmrCtr_ReadReg ( TmrCtrPtr -> BaseAddress , TmrCtrNumber , XTC_TCSR_OFFSET ) ; if ( ( ( ControlStatusReg & XTC_CSR_AUTO_RELOAD_MASK ) == 0 ) && ( ( ControlStatusReg & XTC_CSR_CAPTURE_MODE_MASK ) == 0 ) ) { ControlStatusReg &= ( u32 ) ~ XTC_CSR_ENABLE_TMR_MASK ; XTmrCtr_WriteReg ( TmrCtrPtr -> BaseAddress , TmrCtrNumber , XTC_TCSR_OFFSET , ControlStatusReg | XTC_CSR_LOAD_MASK ) ; XTmrCtr_WriteReg ( TmrCtrPtr -> BaseAddress , TmrCtrNumber , XTC_TCSR_OFFSET , ControlStatusReg ) ; } XTmrCtr_WriteReg ( TmrCtrPtr -> BaseAddress , TmrCtrNumber , XTC_TCSR_OFFSET , ControlStatusReg | XTC_CSR_INT_OCCURED_MASK ) ; } } } }
Interrupt Service Routine (ISR) for the driver.
Interrupt Service Routine ( ISR ) for the driver .
/*
	 * Verify that each of the inputs are valid.
	 */ /*
	 * Convert the non-typed pointer to an timer/counter instance pointer
	 * such that there is access to the timer/counter
	 */ /*
	 * Loop thru each timer counter in the device and call the callback
	 * function for each timer which has caused an interrupt
	 */ /*
		 * Check if interrupt is enabled
		 */ /*
			 * Check if timer expired and interrupt occured
			 */ /*
				 * Increment statistics for the number of
				 * interrupts and call the callback to handle
				 * any application specific processing
				 */ /*
				 * Read the new Control/Status Register content.
				 */ /*
				 * If in compare mode and a single shot rather
				 * than auto reload mode then disable the timer
				 * and reset it such so that the interrupt can
				 * be acknowledged, this should be only temporary
				 * till the hardware is fixed
				 */ /*
						 * Disable the timer counter and
						 * reset it such that the timer
						 * counter is loaded with the
						 * reset value allowing the
						 * interrupt to be acknowledged
						 */ /*
						 * Clear the reset condition,
						 * the reset bit must be
						 * manually cleared by a 2nd write
						 * to the register
						 */ /*
				 * Acknowledge the interrupt by clearing the
				 * interrupt bit in the timer control status
				 * register, this is done after calling the
				 * handler so the application could call
				 * IsExpired, the interrupt is cleared by
				 * writing a 1 to the interrupt bit of the
				 * register without changing any of the other
				 * bits
				 */