XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1.c
void XHdmiphy1_MmcmPowerDown(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_DirectionType Dir, u8 Hold)
{
	u32 RegOffsetCtrl;
	u32 RegVal;

	/* Suppress Warning Messages */
	QuadId = QuadId;

	if (Dir == XHDMIPHY1_DIR_TX) {
		RegOffsetCtrl = XHDMIPHY1_MMCM_TXUSRCLK_CTRL_REG;
	}
	else {
		RegOffsetCtrl = XHDMIPHY1_MMCM_RXUSRCLK_CTRL_REG;
	}

	/* Power down. */
	RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl);
	RegVal |= XHDMIPHY1_MMCM_USRCLK_CTRL_PWRDWN_MASK;
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl, RegVal);

	if (!Hold) {
		/* Power up. */
		RegVal &= ~XHDMIPHY1_MMCM_USRCLK_CTRL_PWRDWN_MASK;
		XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl,
									RegVal);
	}
}
/*****************************************************************************/
/**
* This function will power down the mixed-mode clock manager (MMCM) core.
*
* @param	InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	Dir is an indicator for TX or RX.
* @param	Hold is an indicator whether to "hold" the power down if set
*		to 1. If set to 0: power down, then power back up.
*
* @return
*		- XST_SUCCESS.
*
* @note		None.
*
******************************************************************************/
This function will power down the mixed-mode clock manager (MMCM) core.
This function will power down the mixed - mode clock manager ( MMCM ) core .
void XHdmiphy1_MmcmPowerDown(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_DirectionType Dir, u8 Hold)
{
	u32 RegOffsetCtrl;
	u32 RegVal;
	QuadId = QuadId;
	if (Dir == XHDMIPHY1_DIR_TX) {
		RegOffsetCtrl = XHDMIPHY1_MMCM_TXUSRCLK_CTRL_REG;
	}
	else {
		RegOffsetCtrl = XHDMIPHY1_MMCM_RXUSRCLK_CTRL_REG;
	}
	RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl);
	RegVal |= XHDMIPHY1_MMCM_USRCLK_CTRL_PWRDWN_MASK;
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl, RegVal);
	if (!Hold) {
		RegVal &= ~XHDMIPHY1_MMCM_USRCLK_CTRL_PWRDWN_MASK;
		XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl,
									RegVal);
	}
}
void XHdmiphy1_MmcmPowerDown ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_DirectionType Dir , u8 Hold ) { u32 RegOffsetCtrl ; u32 RegVal ; QuadId = QuadId ; if ( Dir == XHDMIPHY1_DIR_TX ) { RegOffsetCtrl = XHDMIPHY1_MMCM_TXUSRCLK_CTRL_REG ; } else { RegOffsetCtrl = XHDMIPHY1_MMCM_RXUSRCLK_CTRL_REG ; } RegVal = XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , RegOffsetCtrl ) ; RegVal |= XHDMIPHY1_MMCM_USRCLK_CTRL_PWRDWN_MASK ; XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffsetCtrl , RegVal ) ; if ( ! Hold ) { RegVal &= ~ XHDMIPHY1_MMCM_USRCLK_CTRL_PWRDWN_MASK ; XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffsetCtrl , RegVal ) ; } }
This function will power down the mixed-mode clock manager (MMCM) core.
This function will power down the mixed - mode clock manager ( MMCM ) core .
/* Suppress Warning Messages */ /* Power down. */ /* Power up. */