XilinxProcessorIPLib/drivers/csi2tx/src/xcsi2tx_intr.c
void XCsi2Tx_IntrHandler(void *InstancePtr)
{
	u32 ActiveIntr;
	u32 Mask;

	XCsi2Tx *XCsiPtr = (XCsi2Tx *)InstancePtr;

	/* Verify arguments. */
	Xil_AssertVoid(XCsiPtr != NULL);
	Xil_AssertVoid(XCsiPtr->IsReady == XIL_COMPONENT_IS_READY);

	/* Get Active interrupts */
	ActiveIntr = XCsi2Tx_GetIntrStatus(XCsiPtr);

	/* If Frame End Generation is Enabled then check for
	 * Line Count Status per Virtual Channel.
	 */
	if (XCsiPtr->Config.FEGenEnabled) {
		/* Check if the no. of lines recieved is different from
		 * the value configured in corresponding VC register.
		 * To clear the interrupt, we need to write 0x3 in the
		 * corresponding bitfield of ISR.
		 */
		Mask = ActiveIntr & XCSITX_LCSTAT_VC0_ISR_MASK;
		Mask >>= XCSITX_LCSTAT_VC0_ISR_OFFSET;
		if (Mask == XCSI2TX_LC_LESS_LINES ||
		    Mask == XCSI2TX_LC_MORE_LINES) {
			XCsiPtr->LineCountErrVC0(XCsiPtr->LCErrVC0Ref, Mask);
			ActiveIntr |= XCSITX_LCSTAT_VC0_ISR_MASK;
		}

		Mask = ActiveIntr & XCSITX_LCSTAT_VC1_ISR_MASK;
		Mask >>= XCSITX_LCSTAT_VC1_ISR_OFFSET;
		if (Mask == XCSI2TX_LC_LESS_LINES ||
		    Mask == XCSI2TX_LC_MORE_LINES) {
			XCsiPtr->LineCountErrVC1(XCsiPtr->LCErrVC1Ref, Mask);
			ActiveIntr |= XCSITX_LCSTAT_VC1_ISR_MASK;
		}

		Mask = ActiveIntr & XCSITX_LCSTAT_VC2_ISR_MASK;
		Mask >>= XCSITX_LCSTAT_VC2_ISR_OFFSET;
		if (Mask == XCSI2TX_LC_LESS_LINES ||
		    Mask == XCSI2TX_LC_MORE_LINES) {
			XCsiPtr->LineCountErrVC2(XCsiPtr->LCErrVC2Ref, Mask);
			ActiveIntr |= XCSITX_LCSTAT_VC2_ISR_MASK;
		}

		Mask = ActiveIntr & XCSITX_LCSTAT_VC3_ISR_MASK;
		Mask >>= XCSITX_LCSTAT_VC3_ISR_OFFSET;
		if (Mask == XCSI2TX_LC_LESS_LINES ||
		    Mask == XCSI2TX_LC_MORE_LINES) {
			XCsiPtr->LineCountErrVC3(XCsiPtr->LCErrVC3Ref, Mask);
			ActiveIntr |= XCSITX_LCSTAT_VC3_ISR_MASK;
		}
	}

	Mask = ActiveIntr & XCSI2TX_UNDERRUN_PIXEL_MASK;
	if (Mask) {
		/* If pixel data underrun then call
		 * corresponding callback function */
		XCsiPtr->UnderrunPixelCallBack(XCsiPtr->UnderrunPixelRef, Mask);
	}

	Mask = ActiveIntr & XCSI2TX_WRONG_DATATYPE_MASK;
	if (Mask) {
		/* If Wrong data Interrupts then call corresponding
		 * callback function */
		XCsiPtr->WrgDataTypeCallBack(XCsiPtr->WrgDataTypeRef,	Mask);
	}

	Mask = ActiveIntr & XCSI2TX_LINE_BUFF_FULL_MASK;
	if (Mask) {
		/* If Linebuffer interrupts, then call
		* corresponding callback function */
		XCsiPtr->LineBufferCallBack(XCsiPtr->LineBufferRef, Mask);
	}

	Mask = ActiveIntr & XCSI2TX_DPHY_ULPS_MASK;
	if (Mask) {
		/* Handle DPHY ULPS Errors */
		XCsiPtr->DPhyUlpsCallBack(XCsiPtr->DPhyUlpsRef, Mask);
	}


	Mask = ActiveIntr & XCSI_GPSFIFO_MASK;
	if (Mask) {
		/* Handle GPS FIFO full Errors */
		XCsiPtr->GSPFIFOCallBack(XCsiPtr->GSPFIFORef, Mask);
	}

	Mask = ActiveIntr & XCSI_INCORT_LANE_MASK;
	if (Mask) {
		/* Handle Incorrect Lane config Errors */
		XCsiPtr->IncorrectLaneCallBack(XCsiPtr->IncorrectLaneRef, Mask);
	}

	/* Clear handled interrupt(s) */
	XCsi2Tx_InterruptClear(XCsiPtr, ActiveIntr);

	return;
}
/*****************************************************************************/
/**
*
* This function is the interrupt handler for the CSI2 Tx core.
*
* This handler reads the pending interrupt from the Interrupt Status register,
* determines the source of the interrupts and calls the respective
* callbacks for the interrupts that are enabled in Interrupt Enable register,
* and finally clears the interrupts.
*
* The application is responsible for connecting this function to the interrupt
* system. Application beyond this core is also responsible for providing
* callbacks to handle interrupts and installing the callbacks using
* XCsi2Tx_SetCallBack() during initialization phase.
*
* @param	InstancePtr is a pointer to the XCsi2Tx core instance.
*
* @return	None.
*
* @note		Interrupt should be enabled to execute interrupt handler.
*
******************************************************************************/
This function is the interrupt handler for the CSI2 Tx core.
This handler reads the pending interrupt from the Interrupt Status register,
determines the source of the interrupts and calls the respective
callbacks for the interrupts that are enabled in Interrupt Enable register,
and finally clears the interrupts.

The application is responsible for connecting this function to the interrupt
system. Application beyond this core is also responsible for providing
callbacks to handle interrupts and installing the callbacks using
XCsi2Tx_SetCallBack() during initialization phase.
This function is the interrupt handler for the CSI2 Tx core . This handler reads the pending interrupt from the Interrupt Status register determines the source of the interrupts and calls the respective callbacks for the interrupts that are enabled in Interrupt Enable register and finally clears the interrupts . The application is responsible for connecting this function to the interrupt system . Application beyond this core is also responsible for providing callbacks to handle interrupts and installing the callbacks using XCsi2Tx_SetCallBack () during initialization phase .
void XCsi2Tx_IntrHandler(void *InstancePtr)
{
	u32 ActiveIntr;
	u32 Mask;
	XCsi2Tx *XCsiPtr = (XCsi2Tx *)InstancePtr;
	Xil_AssertVoid(XCsiPtr != NULL);
	Xil_AssertVoid(XCsiPtr->IsReady == XIL_COMPONENT_IS_READY);
	ActiveIntr = XCsi2Tx_GetIntrStatus(XCsiPtr);
	if (XCsiPtr->Config.FEGenEnabled) {
		Mask = ActiveIntr & XCSITX_LCSTAT_VC0_ISR_MASK;
		Mask >>= XCSITX_LCSTAT_VC0_ISR_OFFSET;
		if (Mask == XCSI2TX_LC_LESS_LINES ||
		    Mask == XCSI2TX_LC_MORE_LINES) {
			XCsiPtr->LineCountErrVC0(XCsiPtr->LCErrVC0Ref, Mask);
			ActiveIntr |= XCSITX_LCSTAT_VC0_ISR_MASK;
		}
		Mask = ActiveIntr & XCSITX_LCSTAT_VC1_ISR_MASK;
		Mask >>= XCSITX_LCSTAT_VC1_ISR_OFFSET;
		if (Mask == XCSI2TX_LC_LESS_LINES ||
		    Mask == XCSI2TX_LC_MORE_LINES) {
			XCsiPtr->LineCountErrVC1(XCsiPtr->LCErrVC1Ref, Mask);
			ActiveIntr |= XCSITX_LCSTAT_VC1_ISR_MASK;
		}
		Mask = ActiveIntr & XCSITX_LCSTAT_VC2_ISR_MASK;
		Mask >>= XCSITX_LCSTAT_VC2_ISR_OFFSET;
		if (Mask == XCSI2TX_LC_LESS_LINES ||
		    Mask == XCSI2TX_LC_MORE_LINES) {
			XCsiPtr->LineCountErrVC2(XCsiPtr->LCErrVC2Ref, Mask);
			ActiveIntr |= XCSITX_LCSTAT_VC2_ISR_MASK;
		}
		Mask = ActiveIntr & XCSITX_LCSTAT_VC3_ISR_MASK;
		Mask >>= XCSITX_LCSTAT_VC3_ISR_OFFSET;
		if (Mask == XCSI2TX_LC_LESS_LINES ||
		    Mask == XCSI2TX_LC_MORE_LINES) {
			XCsiPtr->LineCountErrVC3(XCsiPtr->LCErrVC3Ref, Mask);
			ActiveIntr |= XCSITX_LCSTAT_VC3_ISR_MASK;
		}
	}
	Mask = ActiveIntr & XCSI2TX_UNDERRUN_PIXEL_MASK;
	if (Mask) {
		XCsiPtr->UnderrunPixelCallBack(XCsiPtr->UnderrunPixelRef, Mask);
	}
	Mask = ActiveIntr & XCSI2TX_WRONG_DATATYPE_MASK;
	if (Mask) {
		XCsiPtr->WrgDataTypeCallBack(XCsiPtr->WrgDataTypeRef,	Mask);
	}
	Mask = ActiveIntr & XCSI2TX_LINE_BUFF_FULL_MASK;
	if (Mask) {
		XCsiPtr->LineBufferCallBack(XCsiPtr->LineBufferRef, Mask);
	}
	Mask = ActiveIntr & XCSI2TX_DPHY_ULPS_MASK;
	if (Mask) {
		XCsiPtr->DPhyUlpsCallBack(XCsiPtr->DPhyUlpsRef, Mask);
	}
	Mask = ActiveIntr & XCSI_GPSFIFO_MASK;
	if (Mask) {
		XCsiPtr->GSPFIFOCallBack(XCsiPtr->GSPFIFORef, Mask);
	}
	Mask = ActiveIntr & XCSI_INCORT_LANE_MASK;
	if (Mask) {
		XCsiPtr->IncorrectLaneCallBack(XCsiPtr->IncorrectLaneRef, Mask);
	}
	XCsi2Tx_InterruptClear(XCsiPtr, ActiveIntr);
	return;
}
void XCsi2Tx_IntrHandler ( void * InstancePtr ) { u32 ActiveIntr ; u32 Mask ; XCsi2Tx * XCsiPtr = ( XCsi2Tx * ) InstancePtr ; Xil_AssertVoid ( XCsiPtr != NULL ) ; Xil_AssertVoid ( XCsiPtr -> IsReady == XIL_COMPONENT_IS_READY ) ; ActiveIntr = XCsi2Tx_GetIntrStatus ( XCsiPtr ) ; if ( XCsiPtr -> Config . FEGenEnabled ) { Mask = ActiveIntr & XCSITX_LCSTAT_VC0_ISR_MASK ; Mask >>= XCSITX_LCSTAT_VC0_ISR_OFFSET ; if ( Mask == XCSI2TX_LC_LESS_LINES || Mask == XCSI2TX_LC_MORE_LINES ) { XCsiPtr -> LineCountErrVC0 ( XCsiPtr -> LCErrVC0Ref , Mask ) ; ActiveIntr |= XCSITX_LCSTAT_VC0_ISR_MASK ; } Mask = ActiveIntr & XCSITX_LCSTAT_VC1_ISR_MASK ; Mask >>= XCSITX_LCSTAT_VC1_ISR_OFFSET ; if ( Mask == XCSI2TX_LC_LESS_LINES || Mask == XCSI2TX_LC_MORE_LINES ) { XCsiPtr -> LineCountErrVC1 ( XCsiPtr -> LCErrVC1Ref , Mask ) ; ActiveIntr |= XCSITX_LCSTAT_VC1_ISR_MASK ; } Mask = ActiveIntr & XCSITX_LCSTAT_VC2_ISR_MASK ; Mask >>= XCSITX_LCSTAT_VC2_ISR_OFFSET ; if ( Mask == XCSI2TX_LC_LESS_LINES || Mask == XCSI2TX_LC_MORE_LINES ) { XCsiPtr -> LineCountErrVC2 ( XCsiPtr -> LCErrVC2Ref , Mask ) ; ActiveIntr |= XCSITX_LCSTAT_VC2_ISR_MASK ; } Mask = ActiveIntr & XCSITX_LCSTAT_VC3_ISR_MASK ; Mask >>= XCSITX_LCSTAT_VC3_ISR_OFFSET ; if ( Mask == XCSI2TX_LC_LESS_LINES || Mask == XCSI2TX_LC_MORE_LINES ) { XCsiPtr -> LineCountErrVC3 ( XCsiPtr -> LCErrVC3Ref , Mask ) ; ActiveIntr |= XCSITX_LCSTAT_VC3_ISR_MASK ; } } Mask = ActiveIntr & XCSI2TX_UNDERRUN_PIXEL_MASK ; if ( Mask ) { XCsiPtr -> UnderrunPixelCallBack ( XCsiPtr -> UnderrunPixelRef , Mask ) ; } Mask = ActiveIntr & XCSI2TX_WRONG_DATATYPE_MASK ; if ( Mask ) { XCsiPtr -> WrgDataTypeCallBack ( XCsiPtr -> WrgDataTypeRef , Mask ) ; } Mask = ActiveIntr & XCSI2TX_LINE_BUFF_FULL_MASK ; if ( Mask ) { XCsiPtr -> LineBufferCallBack ( XCsiPtr -> LineBufferRef , Mask ) ; } Mask = ActiveIntr & XCSI2TX_DPHY_ULPS_MASK ; if ( Mask ) { XCsiPtr -> DPhyUlpsCallBack ( XCsiPtr -> DPhyUlpsRef , Mask ) ; } Mask = ActiveIntr & XCSI_GPSFIFO_MASK ; if ( Mask ) { XCsiPtr -> GSPFIFOCallBack ( XCsiPtr -> GSPFIFORef , Mask ) ; } Mask = ActiveIntr & XCSI_INCORT_LANE_MASK ; if ( Mask ) { XCsiPtr -> IncorrectLaneCallBack ( XCsiPtr -> IncorrectLaneRef , Mask ) ; } XCsi2Tx_InterruptClear ( XCsiPtr , ActiveIntr ) ; return ; }
This function is the interrupt handler for the CSI2 Tx core.
This function is the interrupt handler for the CSI2 Tx core .
/* Verify arguments. */ /* Get Active interrupts */ /* If Frame End Generation is Enabled then check for
	 * Line Count Status per Virtual Channel.
	 */ /* Check if the no. of lines recieved is different from
		 * the value configured in corresponding VC register.
		 * To clear the interrupt, we need to write 0x3 in the
		 * corresponding bitfield of ISR.
		 */ /* If pixel data underrun then call
		 * corresponding callback function */ /* If Wrong data Interrupts then call corresponding
		 * callback function */ /* If Linebuffer interrupts, then call
		* corresponding callback function */ /* Handle DPHY ULPS Errors */ /* Handle GPS FIFO full Errors */ /* Handle Incorrect Lane config Errors */ /* Clear handled interrupt(s) */