src/dpdk/drivers/net/mlx4/mlx4_txq.c
static void
txq_uar_init(struct txq *txq)
{
	struct mlx4_priv *priv = txq->priv;
	struct mlx4_proc_priv *ppriv = MLX4_PROC_PRIV(PORT_ID(priv));

	MLX4_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
	MLX4_ASSERT(ppriv);
	ppriv->uar_table[txq->stats.idx] = txq->msq.db;
}
/**
 * Initialize Tx UAR registers for primary process.
 *
 * @param txq
 *   Pointer to Tx queue structure.
 */
Initialize Tx UAR registers for primary process.
@param txq
Pointer to Tx queue structure.
Initialize Tx UAR registers for primary process . @param txq Pointer to Tx queue structure .
static void
txq_uar_init(struct txq *txq)
{
	struct mlx4_priv *priv = txq->priv;
	struct mlx4_proc_priv *ppriv = MLX4_PROC_PRIV(PORT_ID(priv));
	MLX4_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
	MLX4_ASSERT(ppriv);
	ppriv->uar_table[txq->stats.idx] = txq->msq.db;
}
static void txq_uar_init ( struct txq * txq ) { struct mlx4_priv * priv = txq -> priv ; struct mlx4_proc_priv * ppriv = MLX4_PROC_PRIV ( PORT_ID ( priv ) ) ; MLX4_ASSERT ( rte_eal_process_type ( ) == RTE_PROC_PRIMARY ) ; MLX4_ASSERT ( ppriv ) ; ppriv -> uar_table [ txq -> stats . idx ] = txq -> msq . db ; }
Initialize Tx UAR registers for primary process.
Initialize Tx UAR registers for primary process .