XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss.c
static void StubTp1Callback(void *InstancePtr)
{
	XDpRxSs *DpRxSsPtr = (XDpRxSs *)InstancePtr;

	/* Verify argument.*/
	Xil_AssertVoid(DpRxSsPtr != NULL);

	if (DpRxSsPtr->DpPtr->Config.DpProtocol == XDP_PROTOCOL_DP_1_4) {
		DpRxSsPtr->ltState = 1;
		DpRxSsPtr->ceItrCounter = 0;
	}

	if (MCDP6000_IC_Rev == 0x3200) {
		XDpRxSs_MCDP6000_ResetCrPath (DpRxSsPtr, XDPRXSS_MCDP6000_IIC_SLAVE);
	}
 
	/* Read link rate */
	DpRxSsPtr->UsrOpt.LinkRate =
		XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
			XDPRXSS_DPCD_LINK_BW_SET);

	/* Read lane count */
	DpRxSsPtr->UsrOpt.LaneCount =
		XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
			XDPRXSS_DPCD_LANE_COUNT_SET);

	if (MCDP6000_IC_Rev == 0x2100) {
		XDpRxSs_MCDP6000_AccessLaneSet(DpRxSsPtr,
				XDPRXSS_MCDP6000_IIC_SLAVE);
	}

	/* Link bandwidth callback */
	if (DpRxSsPtr->LinkBwCallback) {
		DpRxSsPtr->LinkBwCallback(DpRxSsPtr->LinkBwRef);
	}

	XDpRxSs_WriteReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
		XDPRXSS_RX_PHY_CONFIG, 0x3800000);

	/* PLL reset callback */
	if (DpRxSsPtr->PllResetCallback) {
		DpRxSsPtr->PllResetCallback(DpRxSsPtr->PllResetRef);
	}

	/* Set vertical blank */
	DpRxSsPtr->VBlankEnable = 1;

	/* Enable vertical blank interrupt */
	XDp_RxInterruptEnable(DpRxSsPtr->DpPtr, XDPRXSS_INTR_VBLANK_MASK);

	/* Set vertical blank count */
	DpRxSsPtr->VBlankCount = 0;
	if (DpRxSsPtr->DpPtr->Config.DpProtocol == XDP_PROTOCOL_DP_1_4) {
		DpRxSsPtr->prevLinkRate =
			XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
						XDPRXSS_DPCD_LINK_BW_SET);
		DpRxSsPtr->prevLaneCounts =
			XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
						XDPRXSS_DPCD_LANE_COUNT_SET);
	}
}
/*****************************************************************************/
/**
*
* This routine is a stub for the asynchronous training pattern 1 interrupt
* callback. On initialization, training pattern 1 interrupt handler is set to
* this callback. It is considered as an training pattern 1 for this handler
* to be invoked.
*
* @param	InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This routine is a stub for the asynchronous training pattern 1 interrupt
callback. On initialization, training pattern 1 interrupt handler is set to
this callback. It is considered as an training pattern 1 for this handler
to be invoked.
This routine is a stub for the asynchronous training pattern 1 interrupt callback . On initialization training pattern 1 interrupt handler is set to this callback . It is considered as an training pattern 1 for this handler to be invoked .
static void StubTp1Callback(void *InstancePtr)
{
	XDpRxSs *DpRxSsPtr = (XDpRxSs *)InstancePtr;
	Xil_AssertVoid(DpRxSsPtr != NULL);
	if (DpRxSsPtr->DpPtr->Config.DpProtocol == XDP_PROTOCOL_DP_1_4) {
		DpRxSsPtr->ltState = 1;
		DpRxSsPtr->ceItrCounter = 0;
	}
	if (MCDP6000_IC_Rev == 0x3200) {
		XDpRxSs_MCDP6000_ResetCrPath (DpRxSsPtr, XDPRXSS_MCDP6000_IIC_SLAVE);
	}
	DpRxSsPtr->UsrOpt.LinkRate =
		XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
			XDPRXSS_DPCD_LINK_BW_SET);
	DpRxSsPtr->UsrOpt.LaneCount =
		XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
			XDPRXSS_DPCD_LANE_COUNT_SET);
	if (MCDP6000_IC_Rev == 0x2100) {
		XDpRxSs_MCDP6000_AccessLaneSet(DpRxSsPtr,
				XDPRXSS_MCDP6000_IIC_SLAVE);
	}
	if (DpRxSsPtr->LinkBwCallback) {
		DpRxSsPtr->LinkBwCallback(DpRxSsPtr->LinkBwRef);
	}
	XDpRxSs_WriteReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
		XDPRXSS_RX_PHY_CONFIG, 0x3800000);
	if (DpRxSsPtr->PllResetCallback) {
		DpRxSsPtr->PllResetCallback(DpRxSsPtr->PllResetRef);
	}
	DpRxSsPtr->VBlankEnable = 1;
	XDp_RxInterruptEnable(DpRxSsPtr->DpPtr, XDPRXSS_INTR_VBLANK_MASK);
	DpRxSsPtr->VBlankCount = 0;
	if (DpRxSsPtr->DpPtr->Config.DpProtocol == XDP_PROTOCOL_DP_1_4) {
		DpRxSsPtr->prevLinkRate =
			XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
						XDPRXSS_DPCD_LINK_BW_SET);
		DpRxSsPtr->prevLaneCounts =
			XDpRxSs_ReadReg(DpRxSsPtr->DpPtr->Config.BaseAddr,
						XDPRXSS_DPCD_LANE_COUNT_SET);
	}
}
static void StubTp1Callback ( void * InstancePtr ) { XDpRxSs * DpRxSsPtr = ( XDpRxSs * ) InstancePtr ; Xil_AssertVoid ( DpRxSsPtr != NULL ) ; if ( DpRxSsPtr -> DpPtr -> Config . DpProtocol == XDP_PROTOCOL_DP_1_4 ) { DpRxSsPtr -> ltState = 1 ; DpRxSsPtr -> ceItrCounter = 0 ; } if ( MCDP6000_IC_Rev == 0x3200 ) { XDpRxSs_MCDP6000_ResetCrPath ( DpRxSsPtr , XDPRXSS_MCDP6000_IIC_SLAVE ) ; } DpRxSsPtr -> UsrOpt . LinkRate = XDpRxSs_ReadReg ( DpRxSsPtr -> DpPtr -> Config . BaseAddr , XDPRXSS_DPCD_LINK_BW_SET ) ; DpRxSsPtr -> UsrOpt . LaneCount = XDpRxSs_ReadReg ( DpRxSsPtr -> DpPtr -> Config . BaseAddr , XDPRXSS_DPCD_LANE_COUNT_SET ) ; if ( MCDP6000_IC_Rev == 0x2100 ) { XDpRxSs_MCDP6000_AccessLaneSet ( DpRxSsPtr , XDPRXSS_MCDP6000_IIC_SLAVE ) ; } if ( DpRxSsPtr -> LinkBwCallback ) { DpRxSsPtr -> LinkBwCallback ( DpRxSsPtr -> LinkBwRef ) ; } XDpRxSs_WriteReg ( DpRxSsPtr -> DpPtr -> Config . BaseAddr , XDPRXSS_RX_PHY_CONFIG , 0x3800000 ) ; if ( DpRxSsPtr -> PllResetCallback ) { DpRxSsPtr -> PllResetCallback ( DpRxSsPtr -> PllResetRef ) ; } DpRxSsPtr -> VBlankEnable = 1 ; XDp_RxInterruptEnable ( DpRxSsPtr -> DpPtr , XDPRXSS_INTR_VBLANK_MASK ) ; DpRxSsPtr -> VBlankCount = 0 ; if ( DpRxSsPtr -> DpPtr -> Config . DpProtocol == XDP_PROTOCOL_DP_1_4 ) { DpRxSsPtr -> prevLinkRate = XDpRxSs_ReadReg ( DpRxSsPtr -> DpPtr -> Config . BaseAddr , XDPRXSS_DPCD_LINK_BW_SET ) ; DpRxSsPtr -> prevLaneCounts = XDpRxSs_ReadReg ( DpRxSsPtr -> DpPtr -> Config . BaseAddr , XDPRXSS_DPCD_LANE_COUNT_SET ) ; } }
This routine is a stub for the asynchronous training pattern 1 interrupt
callback.
This routine is a stub for the asynchronous training pattern 1 interrupt callback .
/* Verify argument.*/ /* Read link rate */ /* Read lane count */ /* Link bandwidth callback */ /* PLL reset callback */ /* Set vertical blank */ /* Enable vertical blank interrupt */ /* Set vertical blank count */