XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1.c
XHdmiphy1_PllType XHdmiphy1_GetPllType(XHdmiphy1 *InstancePtr, u8 QuadId,
		XHdmiphy1_DirectionType Dir, XHdmiphy1_ChannelId ChId)
{
	XHdmiphy1_PllType PllType;
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
	XHdmiphy1_SysClkDataSelType SysClkDataSel;
	XHdmiphy1_SysClkOutSelType SysClkOutSel;

	SysClkDataSel = XHdmiphy1_GetSysClkDataSel(InstancePtr, QuadId, Dir, ChId);
	SysClkOutSel = XHdmiphy1_GetSysClkOutSel(InstancePtr, QuadId, Dir, ChId);

	/* The sysclk data and output reference clocks should match. */

	if ((SysClkDataSel == XHDMIPHY1_SYSCLKSELDATA_TYPE_CPLL_OUTCLK) &&
	(SysClkOutSel == XHDMIPHY1_SYSCLKSELOUT_TYPE_CPLL_REFCLK)) {
		PllType = XHDMIPHY1_PLL_TYPE_CPLL;
	}
	else if ((SysClkDataSel == XHDMIPHY1_SYSCLKSELDATA_TYPE_QPLL_OUTCLK) &&
	(SysClkOutSel == XHDMIPHY1_SYSCLKSELOUT_TYPE_QPLL_REFCLK)) {
		PllType = XHDMIPHY1_PLL_TYPE_QPLL;
	}
	else if ((SysClkDataSel == XHDMIPHY1_SYSCLKSELDATA_TYPE_QPLL0_OUTCLK) &&
	(SysClkOutSel == XHDMIPHY1_SYSCLKSELOUT_TYPE_QPLL0_REFCLK)) {
		PllType = XHDMIPHY1_PLL_TYPE_QPLL0;
	}
	else if ((SysClkDataSel == XHDMIPHY1_SYSCLKSELDATA_TYPE_QPLL1_OUTCLK) &&
	(SysClkOutSel == XHDMIPHY1_SYSCLKSELOUT_TYPE_QPLL1_REFCLK)) {
		PllType = XHDMIPHY1_PLL_TYPE_QPLL1;
	}
	else {
		PllType = XHDMIPHY1_PLL_TYPE_UNKNOWN;
	}
#else
	/* Suppress Warning Messages */
	QuadId = QuadId;
	ChId = ChId;

	if (Dir == XHDMIPHY1_DIR_TX) {
		PllType = (XHdmiphy1_PllType) InstancePtr->Config.TxSysPllClkSel-2;
	}
	else if (Dir == XHDMIPHY1_DIR_RX) {
		PllType = (XHdmiphy1_PllType) InstancePtr->Config.RxSysPllClkSel-2;
	}
	else {
		PllType = XHDMIPHY1_PLL_TYPE_UNKNOWN;
	}
#endif

	return PllType;
}
/*****************************************************************************/
/**
* Obtain the channel's PLL reference clock selection.
*
* @param	InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	Dir is an indicator for TX or RX.
* @param	ChId is the channel ID which to operate on.
*
* @return	The PLL type being used by the channel.
*
* @note		None.
*
******************************************************************************/
Obtain the channel's PLL reference clock selection.
Obtain the channel ' s PLL reference clock selection .
XHdmiphy1_PllType XHdmiphy1_GetPllType(XHdmiphy1 *InstancePtr, u8 QuadId,
		XHdmiphy1_DirectionType Dir, XHdmiphy1_ChannelId ChId)
{
	XHdmiphy1_PllType PllType;
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
	XHdmiphy1_SysClkDataSelType SysClkDataSel;
	XHdmiphy1_SysClkOutSelType SysClkOutSel;
	SysClkDataSel = XHdmiphy1_GetSysClkDataSel(InstancePtr, QuadId, Dir, ChId);
	SysClkOutSel = XHdmiphy1_GetSysClkOutSel(InstancePtr, QuadId, Dir, ChId);
	if ((SysClkDataSel == XHDMIPHY1_SYSCLKSELDATA_TYPE_CPLL_OUTCLK) &&
	(SysClkOutSel == XHDMIPHY1_SYSCLKSELOUT_TYPE_CPLL_REFCLK)) {
		PllType = XHDMIPHY1_PLL_TYPE_CPLL;
	}
	else if ((SysClkDataSel == XHDMIPHY1_SYSCLKSELDATA_TYPE_QPLL_OUTCLK) &&
	(SysClkOutSel == XHDMIPHY1_SYSCLKSELOUT_TYPE_QPLL_REFCLK)) {
		PllType = XHDMIPHY1_PLL_TYPE_QPLL;
	}
	else if ((SysClkDataSel == XHDMIPHY1_SYSCLKSELDATA_TYPE_QPLL0_OUTCLK) &&
	(SysClkOutSel == XHDMIPHY1_SYSCLKSELOUT_TYPE_QPLL0_REFCLK)) {
		PllType = XHDMIPHY1_PLL_TYPE_QPLL0;
	}
	else if ((SysClkDataSel == XHDMIPHY1_SYSCLKSELDATA_TYPE_QPLL1_OUTCLK) &&
	(SysClkOutSel == XHDMIPHY1_SYSCLKSELOUT_TYPE_QPLL1_REFCLK)) {
		PllType = XHDMIPHY1_PLL_TYPE_QPLL1;
	}
	else {
		PllType = XHDMIPHY1_PLL_TYPE_UNKNOWN;
	}
#else
	QuadId = QuadId;
	ChId = ChId;
	if (Dir == XHDMIPHY1_DIR_TX) {
		PllType = (XHdmiphy1_PllType) InstancePtr->Config.TxSysPllClkSel-2;
	}
	else if (Dir == XHDMIPHY1_DIR_RX) {
		PllType = (XHdmiphy1_PllType) InstancePtr->Config.RxSysPllClkSel-2;
	}
	else {
		PllType = XHDMIPHY1_PLL_TYPE_UNKNOWN;
	}
#endif
	return PllType;
}
XHdmiphy1_PllType XHdmiphy1_GetPllType ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_DirectionType Dir , XHdmiphy1_ChannelId ChId ) { XHdmiphy1_PllType PllType ; #if ( XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5 ) XHdmiphy1_SysClkDataSelType SysClkDataSel ; XHdmiphy1_SysClkOutSelType SysClkOutSel ; SysClkDataSel = XHdmiphy1_GetSysClkDataSel ( InstancePtr , QuadId , Dir , ChId ) ; SysClkOutSel = XHdmiphy1_GetSysClkOutSel ( InstancePtr , QuadId , Dir , ChId ) ; if ( ( SysClkDataSel == XHDMIPHY1_SYSCLKSELDATA_TYPE_CPLL_OUTCLK ) && ( SysClkOutSel == XHDMIPHY1_SYSCLKSELOUT_TYPE_CPLL_REFCLK ) ) { PllType = XHDMIPHY1_PLL_TYPE_CPLL ; } else if ( ( SysClkDataSel == XHDMIPHY1_SYSCLKSELDATA_TYPE_QPLL_OUTCLK ) && ( SysClkOutSel == XHDMIPHY1_SYSCLKSELOUT_TYPE_QPLL_REFCLK ) ) { PllType = XHDMIPHY1_PLL_TYPE_QPLL ; } else if ( ( SysClkDataSel == XHDMIPHY1_SYSCLKSELDATA_TYPE_QPLL0_OUTCLK ) && ( SysClkOutSel == XHDMIPHY1_SYSCLKSELOUT_TYPE_QPLL0_REFCLK ) ) { PllType = XHDMIPHY1_PLL_TYPE_QPLL0 ; } else if ( ( SysClkDataSel == XHDMIPHY1_SYSCLKSELDATA_TYPE_QPLL1_OUTCLK ) && ( SysClkOutSel == XHDMIPHY1_SYSCLKSELOUT_TYPE_QPLL1_REFCLK ) ) { PllType = XHDMIPHY1_PLL_TYPE_QPLL1 ; } else { PllType = XHDMIPHY1_PLL_TYPE_UNKNOWN ; } #else QuadId = QuadId ; ChId = ChId ; if ( Dir == XHDMIPHY1_DIR_TX ) { PllType = ( XHdmiphy1_PllType ) InstancePtr -> Config . TxSysPllClkSel - 2 ; } else if ( Dir == XHDMIPHY1_DIR_RX ) { PllType = ( XHdmiphy1_PllType ) InstancePtr -> Config . RxSysPllClkSel - 2 ; } else { PllType = XHDMIPHY1_PLL_TYPE_UNKNOWN ; } #endif return PllType ; }
Obtain the channel's PLL reference clock selection.
Obtain the channel ' s PLL reference clock selection .
/* The sysclk data and output reference clocks should match. */ /* Suppress Warning Messages */