XilinxProcessorIPLib/drivers/hdcp1x/src/xhdcp1x_cipher.c
int XHdcp1x_CipherDoRequest(XHdcp1x *InstancePtr,
		XHdcp1x_CipherRequestType Request)
{
	u32 Value = 0;

	/* Verify arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(Request < (XHDCP1X_CIPHER_REQUEST_MAX));

	/* Check that it is not disabled */
	if (!XHdcp1x_CipherIsEnabled(InstancePtr)) {
		return (XST_NOT_ENABLED);
	}

	/* Determine if there is a request in progress */
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_STATUS);
	Value &= XHDCP1X_CIPHER_BITMASK_CIPHER_STATUS_REQUEST_IN_PROG;

	/* Check that it is not busy */
	if (Value != 0) {
		return (XST_DEVICE_BUSY);
	}

	/* Ensure that the register update bit is set */
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Value |= XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Value);

	/* Set the appropriate request bit
	 * and ensure that Km is always used
	 */
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_CONTROL);
	Value &= ~XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_REQUEST;
	Value |= (XHDCP1X_CIPHER_VALUE_CIPHER_CONTROL_REQUEST_BLOCK
								<< Request);
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_CONTROL, Value);

	/* Ensure that the request bit(s) get cleared for next time */
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_CONTROL);
	Value &= ~XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_REQUEST;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_CONTROL, Value);

	return (XST_SUCCESS);
}
/*****************************************************************************/
/**
* This function initiates a request within the HDCP cipher.
*
* @param	InstancePtr is the device to submit the request to.
* @param	Request is the request to submit.
*
* @return
*		- XST_SUCCESS if successful.
*		- XST_NOT_ENABLE if the core is disabled.
*		- XST_DEVICE_BUSY if the core is busy.
*
* @note		None.
*
******************************************************************************/
This function initiates a request within the HDCP cipher.
This function initiates a request within the HDCP cipher .
int XHdcp1x_CipherDoRequest(XHdcp1x *InstancePtr,
		XHdcp1x_CipherRequestType Request)
{
	u32 Value = 0;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(Request < (XHDCP1X_CIPHER_REQUEST_MAX));
	if (!XHdcp1x_CipherIsEnabled(InstancePtr)) {
		return (XST_NOT_ENABLED);
	}
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_STATUS);
	Value &= XHDCP1X_CIPHER_BITMASK_CIPHER_STATUS_REQUEST_IN_PROG;
	if (Value != 0) {
		return (XST_DEVICE_BUSY);
	}
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Value |= XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Value);
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_CONTROL);
	Value &= ~XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_REQUEST;
	Value |= (XHDCP1X_CIPHER_VALUE_CIPHER_CONTROL_REQUEST_BLOCK
								<< Request);
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_CONTROL, Value);
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_CONTROL);
	Value &= ~XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_REQUEST;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_CONTROL, Value);
	return (XST_SUCCESS);
}
int XHdcp1x_CipherDoRequest ( XHdcp1x * InstancePtr , XHdcp1x_CipherRequestType Request ) { u32 Value = 0 ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( Request < ( XHDCP1X_CIPHER_REQUEST_MAX ) ) ; if ( ! XHdcp1x_CipherIsEnabled ( InstancePtr ) ) { return ( XST_NOT_ENABLED ) ; } Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CIPHER_STATUS ) ; Value &= XHDCP1X_CIPHER_BITMASK_CIPHER_STATUS_REQUEST_IN_PROG ; if ( Value != 0 ) { return ( XST_DEVICE_BUSY ) ; } Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL ) ; Value |= XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL , Value ) ; Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CIPHER_CONTROL ) ; Value &= ~ XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_REQUEST ; Value |= ( XHDCP1X_CIPHER_VALUE_CIPHER_CONTROL_REQUEST_BLOCK << Request ) ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CIPHER_CONTROL , Value ) ; Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CIPHER_CONTROL ) ; Value &= ~ XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_REQUEST ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CIPHER_CONTROL , Value ) ; return ( XST_SUCCESS ) ; }
This function initiates a request within the HDCP cipher.
This function initiates a request within the HDCP cipher .
/* Verify arguments. */ /* Check that it is not disabled */ /* Determine if there is a request in progress */ /* Check that it is not busy */ /* Ensure that the register update bit is set */ /* Set the appropriate request bit
	 * and ensure that Km is always used
	 */ /* Ensure that the request bit(s) get cleared for next time */