src/dpdk/drivers/net/i40e/i40e_fdir.c
static inline void
i40e_init_flx_pld(struct i40e_pf *pf)
{
	struct i40e_hw *hw = I40E_PF_TO_HW(pf);
	uint8_t pctype;
	int i, index;
	uint16_t flow_type;

	/*
	 * Define the bytes stream extracted as flexible payload in
	 * field vector. By default, select 8 words from the beginning
	 * of payload as flexible payload.
	 */
	for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
		index = i * I40E_MAX_FLXPLD_FIED;
		pf->fdir.flex_set[index].src_offset = 0;
		pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
		pf->fdir.flex_set[index].dst_offset = 0;
		I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
		I40E_WRITE_REG(hw,
			I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
		I40E_WRITE_REG(hw,
			I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
		pf->fdir.flex_pit_flag[i] = 0;
	}

	/* initialize the masks */
	for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
	     pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
		flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);

		if (flow_type == RTE_ETH_FLOW_UNKNOWN)
			continue;
		pf->fdir.flex_mask[pctype].word_mask = 0;
		i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
		for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
			pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
			pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
			i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
		}
	}
}
/*
 * Initialize the configuration about bytes stream extracted as flexible payload
 * and mask setting
 */
Initialize the configuration about bytes stream extracted as flexible payload
and mask setting
Initialize the configuration about bytes stream extracted as flexible payload and mask setting
static inline void
i40e_init_flx_pld(struct i40e_pf *pf)
{
	struct i40e_hw *hw = I40E_PF_TO_HW(pf);
	uint8_t pctype;
	int i, index;
	uint16_t flow_type;
	for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
		index = i * I40E_MAX_FLXPLD_FIED;
		pf->fdir.flex_set[index].src_offset = 0;
		pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
		pf->fdir.flex_set[index].dst_offset = 0;
		I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
		I40E_WRITE_REG(hw,
			I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);
		I40E_WRITE_REG(hw,
			I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);
		pf->fdir.flex_pit_flag[i] = 0;
	}
	for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
	     pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
		flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
		if (flow_type == RTE_ETH_FLOW_UNKNOWN)
			continue;
		pf->fdir.flex_mask[pctype].word_mask = 0;
		i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
		for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
			pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
			pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
			i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
		}
	}
}
static inline void i40e_init_flx_pld ( struct i40e_pf * pf ) { struct i40e_hw * hw = I40E_PF_TO_HW ( pf ) ; uint8_t pctype ; int i , index ; uint16_t flow_type ; for ( i = I40E_FLXPLD_L2_IDX ; i < I40E_MAX_FLXPLD_LAYER ; i ++ ) { index = i * I40E_MAX_FLXPLD_FIED ; pf -> fdir . flex_set [ index ] . src_offset = 0 ; pf -> fdir . flex_set [ index ] . size = I40E_FDIR_MAX_FLEXWORD_NUM ; pf -> fdir . flex_set [ index ] . dst_offset = 0 ; I40E_WRITE_REG ( hw , I40E_PRTQF_FLX_PIT ( index ) , 0x0000C900 ) ; I40E_WRITE_REG ( hw , I40E_PRTQF_FLX_PIT ( index + 1 ) , 0x0000FC29 ) ; I40E_WRITE_REG ( hw , I40E_PRTQF_FLX_PIT ( index + 2 ) , 0x0000FC2A ) ; pf -> fdir . flex_pit_flag [ i ] = 0 ; } for ( pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP ; pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD ; pctype ++ ) { flow_type = i40e_pctype_to_flowtype ( pf -> adapter , pctype ) ; if ( flow_type == RTE_ETH_FLOW_UNKNOWN ) continue ; pf -> fdir . flex_mask [ pctype ] . word_mask = 0 ; i40e_write_rx_ctl ( hw , I40E_PRTQF_FD_FLXINSET ( pctype ) , 0 ) ; for ( i = 0 ; i < I40E_FDIR_BITMASK_NUM_WORD ; i ++ ) { pf -> fdir . flex_mask [ pctype ] . bitmask [ i ] . offset = 0 ; pf -> fdir . flex_mask [ pctype ] . bitmask [ i ] . mask = 0 ; i40e_write_rx_ctl ( hw , I40E_PRTQF_FD_MSK ( pctype , i ) , 0 ) ; } } }
Initialize the configuration about bytes stream extracted as flexible payload
 and mask setting
Initialize the configuration about bytes stream extracted as flexible payload and mask setting
/*
	 * Define the bytes stream extracted as flexible payload in
	 * field vector. By default, select 8 words from the beginning
	 * of payload as flexible payload.
	 */ /*non-used*/ /*non-used*/ /* initialize the masks */