XilinxProcessorIPLib/drivers/axiethernet/examples/xaxiethernet_example_intr_mcdma.c
int AxiEthernetSgDmaIntrMultiFrameExample(XAxiEthernet *AxiEthernetInstancePtr,
					   XMcdma *DmaInstancePtr, u8 ChanId)
{

	int Status;
	u32 TxFrameLength;
	int PayloadSize = PAYLOAD_SIZE;
	XMcdma_ChanCtrl *Rx_Chan, *Tx_Chan;
	XMcdma_Bd *BdCurPtr;
	u32 CrBits, len, i, j;
	UINTPTR TxBufPtr, RxBufPtr;
	int FrameCnt = NUM_PACKETS;

	/*
	 * Clear variables shared with callbacks
	 */
	FramesRx = 0;
	FramesTx = 0;
	DeviceErrors = 0;
	memset(RxFrame,0,sizeof(RxFrame));
	memset(TxFrame,0,sizeof(TxFrame));

	Rx_Chan = XMcdma_GetMcdmaRxChan(DmaInstancePtr, ChanId);
	Tx_Chan = XMcdma_GetMcdmaTxChan(DmaInstancePtr, ChanId);

	/*
	 * Calculate the frame length (not including FCS)
	 */
	TxFrameLength = XAE_HDR_SIZE + PayloadSize + Padding;

	AxiEnthernetSetMAC(AxiEthernetMAC, ChanId - 1);

	/*
	 * Set the MAC address
	 */
	Status = XAxiEthernet_SetMacAddress(AxiEthernetInstancePtr,
	                                    AxiEthernetMAC);
	if (Status != XST_SUCCESS) {
	      AxiEthernetUtilErrorTrap("Error setting MAC address");
	      return XST_FAILURE;
	}

	/*
	 * Setup packet to be transmitted
	 */
	AxiEthernetUtilFrameHdrFormatMAC(&TxFrame, AxiEthernetMAC);
	AxiEthernetUtilFrameHdrFormatType(&TxFrame, PayloadSize);
	AxiEthernetUtilFrameSetPayloadData(&TxFrame, PayloadSize);

	/*
	 * Flush the TX frame before giving it to DMA TX channel to transmit.
	 */
	Xil_DCacheFlushRange((UINTPTR)&TxFrame, TxFrameLength);


	/*
	 * Make sure Tx and Rx are enabled
	 */
	Status = XAxiEthernet_SetOptions(AxiEthernetInstancePtr,
				     XAE_RECEIVER_ENABLE_OPTION |
				     XAE_TRANSMITTER_ENABLE_OPTION);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting options");
		return XST_FAILURE;
	}

	/*
	 * Start the Axi Ethernet and enable its ERROR interrupts
	 */
	XAxiEthernet_Start(AxiEthernetInstancePtr);

	/*
	 * Clear out receive packet memory area
	 */
	AxiEthernetUtilFrameMemClear(&RxFrame);


	/*
	 * Enable DMA RX interrupt.
	 *
	 * Interrupt coalescing parameters are left at their default settings
	 * which is to interrupt the processor after every frame has been
	 * processed by the DMA engine.
	 */
	XMcdma_IntrEnable(Rx_Chan, XMCDMA_IRQ_ALL_MASK);

	RxBufPtr = (UINTPTR)&RxFrame;
	for (j = 0 ; j < FrameCnt ; j++) {

		/*
		 * Invalidate the RX frame before giving it to DMA RX channel to
		 * receive data.
		 */
		Xil_DCacheInvalidateRange((UINTPTR)RxBufPtr, TxFrameLength);

		Status = XMcDma_ChanSubmit(Rx_Chan, RxBufPtr,
					   TxFrameLength);
		if (Status != XST_SUCCESS) {
			xil_printf("ChanSubmit failed\n\r");
			return XST_FAILURE;
		}
		RxBufPtr += TxFrameLength;
	}

	Status = XMcDma_ChanToHw(Rx_Chan);
	if (Status != XST_SUCCESS) {
		xil_printf("XMcDma_ChanToHw failed\n\r");
		return XST_FAILURE;
	}

	/*
	 * Enable DMA transmit interrupts
	 */
	XMcdma_IntrEnable(Tx_Chan, XMCDMA_IRQ_ALL_MASK);

	BdCurPtr = (XMcdma_Bd *)XMcdma_GetChanCurBd(Tx_Chan);
	TxBufPtr = (UINTPTR)&TxFrame;
	for (j = 0 ; j < FrameCnt ; j++) {
		Xil_DCacheFlushRange((UINTPTR)TxBufPtr, TxFrameLength);

		for (i = 0 ; i < 2 ; i++) {
			CrBits = 0;

			if (i == 0)
				len = 64;
			if (i == 1)
				len = TxFrameLength - 64;

			Status = XMcDma_ChanSubmit(Tx_Chan, TxBufPtr,
						len);
			if (Status != XST_SUCCESS) {
				xil_printf("ChanSubmit failed\n\r");
				return XST_FAILURE;
			}
			if (i == 0) {
				CrBits |= XMCDMA_BD_CTRL_SOF_MASK;
			}
			if (i == 1) {
				CrBits |= XMCDMA_BD_CTRL_EOF_MASK;
			}

			XMcDma_BdSetCtrl(BdCurPtr, CrBits);
			XMCDMA_CACHE_FLUSH((UINTPTR)(BdCurPtr));
			TxBufPtr += 64;
			BdCurPtr = (XMcdma_Bd *)XMcdma_BdChainNextBd(Tx_Chan, BdCurPtr);
		}
		TxBufPtr += TxFrameLength;
		AxiEthernetUtilFrameHdrFormatMAC((EthernetFrame *)TxBufPtr, AxiEthernetMAC);
		AxiEthernetUtilFrameHdrFormatType((EthernetFrame *)TxBufPtr, PayloadSize);
		AxiEthernetUtilFrameSetPayloadData((EthernetFrame *)TxBufPtr, PayloadSize);
	}

	Status = XMcDma_ChanToHw(Tx_Chan);
	if (Status != XST_SUCCESS) {
		xil_printf("XMcDma_ChanToHw failed for Tx\n\r");
		return XST_FAILURE;
	}

	/*
	 * Wait for transmission to complete
	 */
	while (FramesTx < FrameCnt) {

	}

	/*
	 * Wait for Rx indication
	 */
	while (FramesRx < FrameCnt) {

	}


	/*
	 * Finished this example. If everything worked correctly, all TxBDs and
	 * RxBDs should be free for allocation. Stop the device.
	 */
	XAxiEthernet_Stop(AxiEthernetInstancePtr);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function demonstrates the usage of the Axi Ethernet by sending and
* receiving a multiple frames in MCDMA interrupt mode.
* Each source packet will be described by two descriptors. It will be received
* into a buffer described by a single descriptor.
*
* @param	AxiEthernetInstancePtr is a pointer to the instance of the
*		Axi Ethernet component.
* @param	DmaInstancePtr   is a pointer to the instance of the Dma
*		component.
* @param	ChanId is the MCDMA Channel number to be operate on.
*
* @return	-XST_SUCCESS to indicate success
*		-XST_FAILURE to indicate failure
*
* @note		None.
*
******************************************************************************/
This function demonstrates the usage of the Axi Ethernet by sending and
receiving a multiple frames in MCDMA interrupt mode.
Each source packet will be described by two descriptors. It will be received
into a buffer described by a single descriptor.
This function demonstrates the usage of the Axi Ethernet by sending and receiving a multiple frames in MCDMA interrupt mode . Each source packet will be described by two descriptors . It will be received into a buffer described by a single descriptor .
int AxiEthernetSgDmaIntrMultiFrameExample(XAxiEthernet *AxiEthernetInstancePtr,
					   XMcdma *DmaInstancePtr, u8 ChanId)
{
	int Status;
	u32 TxFrameLength;
	int PayloadSize = PAYLOAD_SIZE;
	XMcdma_ChanCtrl *Rx_Chan, *Tx_Chan;
	XMcdma_Bd *BdCurPtr;
	u32 CrBits, len, i, j;
	UINTPTR TxBufPtr, RxBufPtr;
	int FrameCnt = NUM_PACKETS;
	FramesRx = 0;
	FramesTx = 0;
	DeviceErrors = 0;
	memset(RxFrame,0,sizeof(RxFrame));
	memset(TxFrame,0,sizeof(TxFrame));
	Rx_Chan = XMcdma_GetMcdmaRxChan(DmaInstancePtr, ChanId);
	Tx_Chan = XMcdma_GetMcdmaTxChan(DmaInstancePtr, ChanId);
	TxFrameLength = XAE_HDR_SIZE + PayloadSize + Padding;
	AxiEnthernetSetMAC(AxiEthernetMAC, ChanId - 1);
	Status = XAxiEthernet_SetMacAddress(AxiEthernetInstancePtr,
	                                    AxiEthernetMAC);
	if (Status != XST_SUCCESS) {
	      AxiEthernetUtilErrorTrap("Error setting MAC address");
	      return XST_FAILURE;
	}
	AxiEthernetUtilFrameHdrFormatMAC(&TxFrame, AxiEthernetMAC);
	AxiEthernetUtilFrameHdrFormatType(&TxFrame, PayloadSize);
	AxiEthernetUtilFrameSetPayloadData(&TxFrame, PayloadSize);
	Xil_DCacheFlushRange((UINTPTR)&TxFrame, TxFrameLength);
	Status = XAxiEthernet_SetOptions(AxiEthernetInstancePtr,
				     XAE_RECEIVER_ENABLE_OPTION |
				     XAE_TRANSMITTER_ENABLE_OPTION);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting options");
		return XST_FAILURE;
	}
	XAxiEthernet_Start(AxiEthernetInstancePtr);
	AxiEthernetUtilFrameMemClear(&RxFrame);
	XMcdma_IntrEnable(Rx_Chan, XMCDMA_IRQ_ALL_MASK);
	RxBufPtr = (UINTPTR)&RxFrame;
	for (j = 0 ; j < FrameCnt ; j++) {
		Xil_DCacheInvalidateRange((UINTPTR)RxBufPtr, TxFrameLength);
		Status = XMcDma_ChanSubmit(Rx_Chan, RxBufPtr,
					   TxFrameLength);
		if (Status != XST_SUCCESS) {
			xil_printf("ChanSubmit failed\n\r");
			return XST_FAILURE;
		}
		RxBufPtr += TxFrameLength;
	}
	Status = XMcDma_ChanToHw(Rx_Chan);
	if (Status != XST_SUCCESS) {
		xil_printf("XMcDma_ChanToHw failed\n\r");
		return XST_FAILURE;
	}
	XMcdma_IntrEnable(Tx_Chan, XMCDMA_IRQ_ALL_MASK);
	BdCurPtr = (XMcdma_Bd *)XMcdma_GetChanCurBd(Tx_Chan);
	TxBufPtr = (UINTPTR)&TxFrame;
	for (j = 0 ; j < FrameCnt ; j++) {
		Xil_DCacheFlushRange((UINTPTR)TxBufPtr, TxFrameLength);
		for (i = 0 ; i < 2 ; i++) {
			CrBits = 0;
			if (i == 0)
				len = 64;
			if (i == 1)
				len = TxFrameLength - 64;
			Status = XMcDma_ChanSubmit(Tx_Chan, TxBufPtr,
						len);
			if (Status != XST_SUCCESS) {
				xil_printf("ChanSubmit failed\n\r");
				return XST_FAILURE;
			}
			if (i == 0) {
				CrBits |= XMCDMA_BD_CTRL_SOF_MASK;
			}
			if (i == 1) {
				CrBits |= XMCDMA_BD_CTRL_EOF_MASK;
			}
			XMcDma_BdSetCtrl(BdCurPtr, CrBits);
			XMCDMA_CACHE_FLUSH((UINTPTR)(BdCurPtr));
			TxBufPtr += 64;
			BdCurPtr = (XMcdma_Bd *)XMcdma_BdChainNextBd(Tx_Chan, BdCurPtr);
		}
		TxBufPtr += TxFrameLength;
		AxiEthernetUtilFrameHdrFormatMAC((EthernetFrame *)TxBufPtr, AxiEthernetMAC);
		AxiEthernetUtilFrameHdrFormatType((EthernetFrame *)TxBufPtr, PayloadSize);
		AxiEthernetUtilFrameSetPayloadData((EthernetFrame *)TxBufPtr, PayloadSize);
	}
	Status = XMcDma_ChanToHw(Tx_Chan);
	if (Status != XST_SUCCESS) {
		xil_printf("XMcDma_ChanToHw failed for Tx\n\r");
		return XST_FAILURE;
	}
	while (FramesTx < FrameCnt) {
	}
	while (FramesRx < FrameCnt) {
	}
	XAxiEthernet_Stop(AxiEthernetInstancePtr);
	return XST_SUCCESS;
}
int AxiEthernetSgDmaIntrMultiFrameExample ( XAxiEthernet * AxiEthernetInstancePtr , XMcdma * DmaInstancePtr , u8 ChanId ) { int Status ; u32 TxFrameLength ; int PayloadSize = PAYLOAD_SIZE ; XMcdma_ChanCtrl * Rx_Chan , * Tx_Chan ; XMcdma_Bd * BdCurPtr ; u32 CrBits , len , i , j ; UINTPTR TxBufPtr , RxBufPtr ; int FrameCnt = NUM_PACKETS ; FramesRx = 0 ; FramesTx = 0 ; DeviceErrors = 0 ; memset ( RxFrame , 0 , sizeof ( RxFrame ) ) ; memset ( TxFrame , 0 , sizeof ( TxFrame ) ) ; Rx_Chan = XMcdma_GetMcdmaRxChan ( DmaInstancePtr , ChanId ) ; Tx_Chan = XMcdma_GetMcdmaTxChan ( DmaInstancePtr , ChanId ) ; TxFrameLength = XAE_HDR_SIZE + PayloadSize + Padding ; AxiEnthernetSetMAC ( AxiEthernetMAC , ChanId - 1 ) ; Status = XAxiEthernet_SetMacAddress ( AxiEthernetInstancePtr , AxiEthernetMAC ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } AxiEthernetUtilFrameHdrFormatMAC ( & TxFrame , AxiEthernetMAC ) ; AxiEthernetUtilFrameHdrFormatType ( & TxFrame , PayloadSize ) ; AxiEthernetUtilFrameSetPayloadData ( & TxFrame , PayloadSize ) ; Xil_DCacheFlushRange ( ( UINTPTR ) & TxFrame , TxFrameLength ) ; Status = XAxiEthernet_SetOptions ( AxiEthernetInstancePtr , XAE_RECEIVER_ENABLE_OPTION | XAE_TRANSMITTER_ENABLE_OPTION ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } XAxiEthernet_Start ( AxiEthernetInstancePtr ) ; AxiEthernetUtilFrameMemClear ( & RxFrame ) ; XMcdma_IntrEnable ( Rx_Chan , XMCDMA_IRQ_ALL_MASK ) ; RxBufPtr = ( UINTPTR ) & RxFrame ; for ( j = 0 ; j < FrameCnt ; j ++ ) { Xil_DCacheInvalidateRange ( ( UINTPTR ) RxBufPtr , TxFrameLength ) ; Status = XMcDma_ChanSubmit ( Rx_Chan , RxBufPtr , TxFrameLength ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } RxBufPtr += TxFrameLength ; } Status = XMcDma_ChanToHw ( Rx_Chan ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } XMcdma_IntrEnable ( Tx_Chan , XMCDMA_IRQ_ALL_MASK ) ; BdCurPtr = ( XMcdma_Bd * ) XMcdma_GetChanCurBd ( Tx_Chan ) ; TxBufPtr = ( UINTPTR ) & TxFrame ; for ( j = 0 ; j < FrameCnt ; j ++ ) { Xil_DCacheFlushRange ( ( UINTPTR ) TxBufPtr , TxFrameLength ) ; for ( i = 0 ; i < 2 ; i ++ ) { CrBits = 0 ; if ( i == 0 ) len = 64 ; if ( i == 1 ) len = TxFrameLength - 64 ; Status = XMcDma_ChanSubmit ( Tx_Chan , TxBufPtr , len ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } if ( i == 0 ) { CrBits |= XMCDMA_BD_CTRL_SOF_MASK ; } if ( i == 1 ) { CrBits |= XMCDMA_BD_CTRL_EOF_MASK ; } XMcDma_BdSetCtrl ( BdCurPtr , CrBits ) ; XMCDMA_CACHE_FLUSH ( ( UINTPTR ) ( BdCurPtr ) ) ; TxBufPtr += 64 ; BdCurPtr = ( XMcdma_Bd * ) XMcdma_BdChainNextBd ( Tx_Chan , BdCurPtr ) ; } TxBufPtr += TxFrameLength ; AxiEthernetUtilFrameHdrFormatMAC ( ( EthernetFrame * ) TxBufPtr , AxiEthernetMAC ) ; AxiEthernetUtilFrameHdrFormatType ( ( EthernetFrame * ) TxBufPtr , PayloadSize ) ; AxiEthernetUtilFrameSetPayloadData ( ( EthernetFrame * ) TxBufPtr , PayloadSize ) ; } Status = XMcDma_ChanToHw ( Tx_Chan ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } while ( FramesTx < FrameCnt ) { } while ( FramesRx < FrameCnt ) { } XAxiEthernet_Stop ( AxiEthernetInstancePtr ) ; return XST_SUCCESS ; }
This function demonstrates the usage of the Axi Ethernet by sending and
receiving a multiple frames in MCDMA interrupt mode.
This function demonstrates the usage of the Axi Ethernet by sending and receiving a multiple frames in MCDMA interrupt mode .
/*
	 * Clear variables shared with callbacks
	 */ /*
	 * Calculate the frame length (not including FCS)
	 */ /*
	 * Set the MAC address
	 */ /*
	 * Setup packet to be transmitted
	 */ /*
	 * Flush the TX frame before giving it to DMA TX channel to transmit.
	 */ /*
	 * Make sure Tx and Rx are enabled
	 */ /*
	 * Start the Axi Ethernet and enable its ERROR interrupts
	 */ /*
	 * Clear out receive packet memory area
	 */ /*
	 * Enable DMA RX interrupt.
	 *
	 * Interrupt coalescing parameters are left at their default settings
	 * which is to interrupt the processor after every frame has been
	 * processed by the DMA engine.
	 */ /*
		 * Invalidate the RX frame before giving it to DMA RX channel to
		 * receive data.
		 */ /*
	 * Enable DMA transmit interrupts
	 */ /*
	 * Wait for transmission to complete
	 */ /*
	 * Wait for Rx indication
	 */ /*
	 * Finished this example. If everything worked correctly, all TxBDs and
	 * RxBDs should be free for allocation. Stop the device.
	 */