src/dpdk/drivers/net/i40e/base/i40e_nvm.c
enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
					u32 offset, u16 words, void *data,
					bool last_command)
{
	enum i40e_status_code ret_code = I40E_ERR_NVM;
	struct i40e_asq_cmd_details cmd_details;

	DEBUGFUNC("i40e_write_nvm_aq");

	memset(&cmd_details, 0, sizeof(cmd_details));
	cmd_details.wb_desc = &hw->nvm_wb_desc;

	/* Here we are checking the SR limit only for the flat memory model.
	 * We cannot do it for the module-based model, as we did not acquire
	 * the NVM resource yet (we cannot get the module pointer value).
	 * Firmware will check the module-based model.
	 */
	if ((offset + words) > hw->nvm.sr_size)
		DEBUGOUT("NVM write error: offset beyond Shadow RAM limit.\n");
	else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
		/* We can write only up to 4KB (one sector), in one AQ write */
		DEBUGOUT("NVM write fail error: cannot write more than 4KB in a single write.\n");
	else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
		 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
		/* A single write cannot spread over two sectors */
		DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n");
	else
		ret_code = i40e_aq_update_nvm(hw, module_pointer,
					      2 * offset,  /*bytes*/
					      2 * words,   /*bytes*/
					      data, last_command, 0,
					      &cmd_details);

	return ret_code;
}
/**
 * i40e_write_nvm_aq - Writes Shadow RAM.
 * @hw: pointer to the HW structure.
 * @module_pointer: module pointer location in words from the NVM beginning
 * @offset: offset in words from module start
 * @words: number of words to write
 * @data: buffer with words to write to the Shadow RAM
 * @last_command: tells the AdminQ that this is the last command
 *
 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
 **/
Writes Shadow RAM.
@hw: pointer to the HW structure.

Writes a 16 bit words buffer to the Shadow RAM using the admin command.
Writes Shadow RAM . @hw : pointer to the HW structure . Writes a 16 bit words buffer to the Shadow RAM using the admin command .
enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
					u32 offset, u16 words, void *data,
					bool last_command)
{
	enum i40e_status_code ret_code = I40E_ERR_NVM;
	struct i40e_asq_cmd_details cmd_details;
	DEBUGFUNC("i40e_write_nvm_aq");
	memset(&cmd_details, 0, sizeof(cmd_details));
	cmd_details.wb_desc = &hw->nvm_wb_desc;
	if ((offset + words) > hw->nvm.sr_size)
		DEBUGOUT("NVM write error: offset beyond Shadow RAM limit.\n");
	else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
		DEBUGOUT("NVM write fail error: cannot write more than 4KB in a single write.\n");
	else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
		 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
		DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n");
	else
		ret_code = i40e_aq_update_nvm(hw, module_pointer,
					      2 * offset,  
					      2 * words,   
					      data, last_command, 0,
					      &cmd_details);
	return ret_code;
}
enum i40e_status_code i40e_write_nvm_aq ( struct i40e_hw * hw , u8 module_pointer , u32 offset , u16 words , void * data , bool last_command ) { enum i40e_status_code ret_code = I40E_ERR_NVM ; struct i40e_asq_cmd_details cmd_details ; DEBUGFUNC ( " " ) ; memset ( & cmd_details , 0 , sizeof ( cmd_details ) ) ; cmd_details . wb_desc = & hw -> nvm_wb_desc ; if ( ( offset + words ) > hw -> nvm . sr_size ) DEBUGOUT ( " \n " ) ; else if ( words > I40E_SR_SECTOR_SIZE_IN_WORDS ) DEBUGOUT ( " \n " ) ; else if ( ( ( offset + ( words - 1 ) ) / I40E_SR_SECTOR_SIZE_IN_WORDS ) != ( offset / I40E_SR_SECTOR_SIZE_IN_WORDS ) ) DEBUGOUT ( " \n " ) ; else ret_code = i40e_aq_update_nvm ( hw , module_pointer , 2 * offset , 2 * words , data , last_command , 0 , & cmd_details ) ; return ret_code ; }
i40e_write_nvm_aq - Writes Shadow RAM.
i40e_write_nvm_aq - Writes Shadow RAM .
/* Here we are checking the SR limit only for the flat memory model.
	 * We cannot do it for the module-based model, as we did not acquire
	 * the NVM resource yet (we cannot get the module pointer value).
	 * Firmware will check the module-based model.
	 */ /* We can write only up to 4KB (one sector), in one AQ write */ /* A single write cannot spread over two sectors */ /*bytes*/ /*bytes*/