XilinxProcessorIPLib/drivers/wdttb/examples/xwdttb_winwdt_example.c
int WinWdtTbExample(u16 DeviceId)
{
	int Status;
	int Count = 0;
	XWdtTb_Config *Config;

	/*
	 * Initialize the WDTTB driver so that it's ready to use look up
	 * configuration in the config table, then initialize it.
	 */
	Config = XWdtTb_LookupConfig(DeviceId);
	if (NULL == Config) {
		return XST_FAILURE;
	}

	/*
	 * Initialize the watchdog timer and timebase driver so that
	 * it is ready to use.
	 */
	Status = XWdtTb_CfgInitialize(&WatchdogTimebase, Config,
			Config->BaseAddr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	if(!WatchdogTimebase.Config.IsPl) {
		/*Enable Window Watchdog Feature in WWDT */
		XWdtTb_ConfigureWDTMode(&WatchdogTimebase, XWT_WWDT);
	}

	/*
	 * Perform a self-test to ensure that the hardware was built
	 * correctly
	 */
	Status = XWdtTb_SelfTest(&WatchdogTimebase);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

#if (WDTTB_EN_WDP)
	/* Enable extra protection */
	XWdtTb_EnableExtraProtection(&WatchdogTimebase);
#else
	/* Disable extra protection */
	XWdtTb_DisableExtraProtection(&WatchdogTimebase);
#endif /* End of WDP */

	/* Configure first and second window */
	XWdtTb_SetWindowCount(&WatchdogTimebase, WDTTB_FW_COUNT,
		WDTTB_SW_COUNT);

#if (WDTTB_EN_SST)
	/* Configure Second sequence timer */
	if(!WatchdogTimebase.Config.IsPl) {
		XWdtTb_SetSSTWindow(&WatchdogTimebase, WDTTB_SST_COUNT);
	}
#endif
	/* Set interrupt position */
	XWdtTb_SetByteCount(&WatchdogTimebase, WDTTB_BYTE_COUNT);
	XWdtTb_SetByteSegment(&WatchdogTimebase, WDTTB_BYTE_SEGMENT);

#if (WDTTB_EN_SST)
	/* Enable Secondary Sequence Timer (SST) */
	XWdtTb_EnableSst(&WatchdogTimebase);
#else
	/* Disable Secondary Sequence Timer (SST) */
	XWdtTb_DisableSst(&WatchdogTimebase);
#endif /* End of SST */

#if (WDTTB_EN_PSM)
	/* Enable Program Sequence Monitor (PSM) */
	XWdtTb_EnablePsm(&WatchdogTimebase);

	/* Write TSR0 with signature */
	if(WatchdogTimebase.Config.IsPl) {
		XWdtTb_WriteReg(WatchdogTimebase.Config.BaseAddr, XWT_TSR0_OFFSET,
			WDTTB_TSR_VAL);
	} else {
		XWdtTb_WriteReg(WatchdogTimebase.Config.BaseAddr, XWT_TSR0_WWDT_OFFSET,
			WDTTB_TSR_VAL);
	}
#else
	/* Disable Program Sequence Monitor (PSM) */
	XWdtTb_DisablePsm(&WatchdogTimebase);
#endif /* End of PSM */

#if (WDTTB_EN_FC)
	/* Enable Fail Counter */
	XWdtTb_EnableFailCounter(&WatchdogTimebase);
#else
	/* Disable Fail Counter */
	XWdtTb_DisableFailCounter(&WatchdogTimebase);
#endif /* End of FC */

	/*
	 * Start the watchdog timer, the timebase is automatically reset
	 * when this occurs.
	 */
	XWdtTb_Start(&WatchdogTimebase);

	while (1) {
		xil_printf(".");

		/* Check for interrupt programmed point */
		if (XWdtTb_GetIntrStatus(&WatchdogTimebase)) {
			/* Set register space to writable */
			XWdtTb_SetRegSpaceAccessMode(&WatchdogTimebase, 1);

			/* Clear interrupt point */
			XWdtTb_IntrClear(&WatchdogTimebase);

			/* Set register space to read-only */
			XWdtTb_SetRegSpaceAccessMode(&WatchdogTimebase, 0);
#if (WDTTB_EN_PSM)
			/* Set register space to writable */
			XWdtTb_SetRegSpaceAccessMode(&WatchdogTimebase, 1);

			/* Write TSR1 with signature */
			if(WatchdogTimebase.Config.IsPl) {
				XWdtTb_WriteReg(WatchdogTimebase.Config.BaseAddr,
					XWT_TSR1_OFFSET, WDTTB_TSR_VAL);
			} else {
				XWdtTb_WriteReg(WatchdogTimebase.Config.BaseAddr,
					XWT_TSR1_WWDT_OFFSET, WDTTB_TSR_VAL);
			}
			/* Set register space to read-only */
			XWdtTb_SetRegSpaceAccessMode(&WatchdogTimebase, 0);
#endif
			/* Set register space to writable */
			XWdtTb_SetRegSpaceAccessMode(&WatchdogTimebase, 1);

			/*
			 * Restart the watchdog timer as a normal application
			 * would
			 */
			XWdtTb_RestartWdt(&WatchdogTimebase);
			Count++;
			xil_printf("\n\rRestart kick %d\n\r", Count);
		}

		/* Check for last event */
		if (XWdtTb_GetLastEvent(&WatchdogTimebase) !=
				XWDTTB_NO_BAD_EVENT) {
			/* Set register space to writable */
			XWdtTb_SetRegSpaceAccessMode(&WatchdogTimebase, 1);

			/* Stop the watchdog timer */
			XWdtTb_Stop(&WatchdogTimebase);
			return XST_FAILURE;
		}

		/*
		 * Check whether the WatchDog timer restarts twice with window
		 * feature. If the timer restarts twice then the test is
		 * passed.
		 */
		if(Count == 2) {
#if (!WDTTB_EN_SST && !WDTTB_EN_FC && !WDTTB_EN_PSM &&!WDTTB_EN_WDP)
                XWdtTb_Stop(&WatchdogTimebase);
#endif
			break;
		}
	}

#if (WDTTB_EN_SST)
	/* Wait for SST counter start */
	xil_printf("Waiting for SST to start .");
	while (!XWdtTb_IsResetPending(&WatchdogTimebase)) {
		xil_printf(".");
	}

	/* Clear reset pending */
	XWdtTb_ClearResetPending(&WatchdogTimebase);
	if(WatchdogTimebase.Config.IsPl) {
		xil_printf("\n\rSST counter value is 0x%x\n\r",
			XWdtTb_ReadReg(WatchdogTimebase.Config.BaseAddr,
				XWT_STR_OFFSET));
	} else {
		xil_printf("\n\rSST counter value is 0x%x\n\r",
			XWdtTb_ReadReg(WatchdogTimebase.Config.BaseAddr,
				XWT_STR_WWDT_OFFSET));
	}
#endif
	return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function tests the functioning of the TimeBase WatchDog Timer module
* with window feature in the polled mode.
*
* In window, this function polls interrupt programmed point in second window,
* checks the interrupt bit is set. If the bit is set clears the bit and restart
* the watchdog timer. If bit is not cleared before overflowing the second
* window, the watchdog timer resets.
*
* This function may require some time (seconds or even minutes) to execute
* because it waits for the watchdog timer to expire.
*
* @param	DeviceId is the XPAR_<WDTB_instance>_DEVICE_ID value from
*		xparameters.h.
*
* @return
*		- XST_SUCCESS, in window, there is no bad event.
*		- XST_FAILURE, otherwise.
*
* @note		None.
*
****************************************************************************/
This function tests the functioning of the TimeBase WatchDog Timer module
with window feature in the polled mode.

In window, this function polls interrupt programmed point in second window,
checks the interrupt bit is set. If the bit is set clears the bit and restart
the watchdog timer. If bit is not cleared before overflowing the second
window, the watchdog timer resets.

This function may require some time (seconds or even minutes) to execute
because it waits for the watchdog timer to expire.
This function tests the functioning of the TimeBase WatchDog Timer module with window feature in the polled mode . In window this function polls interrupt programmed point in second window checks the interrupt bit is set . If the bit is set clears the bit and restart the watchdog timer . If bit is not cleared before overflowing the second window the watchdog timer resets . This function may require some time ( seconds or even minutes ) to execute because it waits for the watchdog timer to expire .
int WinWdtTbExample(u16 DeviceId)
{
	int Status;
	int Count = 0;
	XWdtTb_Config *Config;
	Config = XWdtTb_LookupConfig(DeviceId);
	if (NULL == Config) {
		return XST_FAILURE;
	}
	Status = XWdtTb_CfgInitialize(&WatchdogTimebase, Config,
			Config->BaseAddr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	if(!WatchdogTimebase.Config.IsPl) {
		XWdtTb_ConfigureWDTMode(&WatchdogTimebase, XWT_WWDT);
	}
	Status = XWdtTb_SelfTest(&WatchdogTimebase);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
#if (WDTTB_EN_WDP)
	XWdtTb_EnableExtraProtection(&WatchdogTimebase);
#else
	XWdtTb_DisableExtraProtection(&WatchdogTimebase);
#endif 
	XWdtTb_SetWindowCount(&WatchdogTimebase, WDTTB_FW_COUNT,
		WDTTB_SW_COUNT);
#if (WDTTB_EN_SST)
	if(!WatchdogTimebase.Config.IsPl) {
		XWdtTb_SetSSTWindow(&WatchdogTimebase, WDTTB_SST_COUNT);
	}
#endif
	XWdtTb_SetByteCount(&WatchdogTimebase, WDTTB_BYTE_COUNT);
	XWdtTb_SetByteSegment(&WatchdogTimebase, WDTTB_BYTE_SEGMENT);
#if (WDTTB_EN_SST)
	XWdtTb_EnableSst(&WatchdogTimebase);
#else
	XWdtTb_DisableSst(&WatchdogTimebase);
#endif 
#if (WDTTB_EN_PSM)
	XWdtTb_EnablePsm(&WatchdogTimebase);
	if(WatchdogTimebase.Config.IsPl) {
		XWdtTb_WriteReg(WatchdogTimebase.Config.BaseAddr, XWT_TSR0_OFFSET,
			WDTTB_TSR_VAL);
	} else {
		XWdtTb_WriteReg(WatchdogTimebase.Config.BaseAddr, XWT_TSR0_WWDT_OFFSET,
			WDTTB_TSR_VAL);
	}
#else
	XWdtTb_DisablePsm(&WatchdogTimebase);
#endif 
#if (WDTTB_EN_FC)
	XWdtTb_EnableFailCounter(&WatchdogTimebase);
#else
	XWdtTb_DisableFailCounter(&WatchdogTimebase);
#endif 
	XWdtTb_Start(&WatchdogTimebase);
	while (1) {
		xil_printf(".");
		if (XWdtTb_GetIntrStatus(&WatchdogTimebase)) {
			XWdtTb_SetRegSpaceAccessMode(&WatchdogTimebase, 1);
			XWdtTb_IntrClear(&WatchdogTimebase);
			XWdtTb_SetRegSpaceAccessMode(&WatchdogTimebase, 0);
#if (WDTTB_EN_PSM)
			XWdtTb_SetRegSpaceAccessMode(&WatchdogTimebase, 1);
			if(WatchdogTimebase.Config.IsPl) {
				XWdtTb_WriteReg(WatchdogTimebase.Config.BaseAddr,
					XWT_TSR1_OFFSET, WDTTB_TSR_VAL);
			} else {
				XWdtTb_WriteReg(WatchdogTimebase.Config.BaseAddr,
					XWT_TSR1_WWDT_OFFSET, WDTTB_TSR_VAL);
			}
			XWdtTb_SetRegSpaceAccessMode(&WatchdogTimebase, 0);
#endif
			XWdtTb_SetRegSpaceAccessMode(&WatchdogTimebase, 1);
			XWdtTb_RestartWdt(&WatchdogTimebase);
			Count++;
			xil_printf("\n\rRestart kick %d\n\r", Count);
		}
		if (XWdtTb_GetLastEvent(&WatchdogTimebase) !=
				XWDTTB_NO_BAD_EVENT) {
			XWdtTb_SetRegSpaceAccessMode(&WatchdogTimebase, 1);
			XWdtTb_Stop(&WatchdogTimebase);
			return XST_FAILURE;
		}
		if(Count == 2) {
#if (!WDTTB_EN_SST && !WDTTB_EN_FC && !WDTTB_EN_PSM &&!WDTTB_EN_WDP)
                XWdtTb_Stop(&WatchdogTimebase);
#endif
			break;
		}
	}
#if (WDTTB_EN_SST)
	xil_printf("Waiting for SST to start .");
	while (!XWdtTb_IsResetPending(&WatchdogTimebase)) {
		xil_printf(".");
	}
	XWdtTb_ClearResetPending(&WatchdogTimebase);
	if(WatchdogTimebase.Config.IsPl) {
		xil_printf("\n\rSST counter value is 0x%x\n\r",
			XWdtTb_ReadReg(WatchdogTimebase.Config.BaseAddr,
				XWT_STR_OFFSET));
	} else {
		xil_printf("\n\rSST counter value is 0x%x\n\r",
			XWdtTb_ReadReg(WatchdogTimebase.Config.BaseAddr,
				XWT_STR_WWDT_OFFSET));
	}
#endif
	return XST_SUCCESS;
}
int WinWdtTbExample ( u16 DeviceId ) { int Status ; int Count = 0 ; XWdtTb_Config * Config ; Config = XWdtTb_LookupConfig ( DeviceId ) ; if ( NULL == Config ) { return XST_FAILURE ; } Status = XWdtTb_CfgInitialize ( & WatchdogTimebase , Config , Config -> BaseAddr ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } if ( ! WatchdogTimebase . Config . IsPl ) { XWdtTb_ConfigureWDTMode ( & WatchdogTimebase , XWT_WWDT ) ; } Status = XWdtTb_SelfTest ( & WatchdogTimebase ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } #if ( WDTTB_EN_WDP ) XWdtTb_EnableExtraProtection ( & WatchdogTimebase ) ; #else XWdtTb_DisableExtraProtection ( & WatchdogTimebase ) ; #endif XWdtTb_SetWindowCount ( & WatchdogTimebase , WDTTB_FW_COUNT , WDTTB_SW_COUNT ) ; #if ( WDTTB_EN_SST ) if ( ! WatchdogTimebase . Config . IsPl ) { XWdtTb_SetSSTWindow ( & WatchdogTimebase , WDTTB_SST_COUNT ) ; } #endif XWdtTb_SetByteCount ( & WatchdogTimebase , WDTTB_BYTE_COUNT ) ; XWdtTb_SetByteSegment ( & WatchdogTimebase , WDTTB_BYTE_SEGMENT ) ; #if ( WDTTB_EN_SST ) XWdtTb_EnableSst ( & WatchdogTimebase ) ; #else XWdtTb_DisableSst ( & WatchdogTimebase ) ; #endif #if ( WDTTB_EN_PSM ) XWdtTb_EnablePsm ( & WatchdogTimebase ) ; if ( WatchdogTimebase . Config . IsPl ) { XWdtTb_WriteReg ( WatchdogTimebase . Config . BaseAddr , XWT_TSR0_OFFSET , WDTTB_TSR_VAL ) ; } else { XWdtTb_WriteReg ( WatchdogTimebase . Config . BaseAddr , XWT_TSR0_WWDT_OFFSET , WDTTB_TSR_VAL ) ; } #else XWdtTb_DisablePsm ( & WatchdogTimebase ) ; #endif #if ( WDTTB_EN_FC ) XWdtTb_EnableFailCounter ( & WatchdogTimebase ) ; #else XWdtTb_DisableFailCounter ( & WatchdogTimebase ) ; #endif XWdtTb_Start ( & WatchdogTimebase ) ; while ( 1 ) { xil_printf ( " " ) ; if ( XWdtTb_GetIntrStatus ( & WatchdogTimebase ) ) { XWdtTb_SetRegSpaceAccessMode ( & WatchdogTimebase , 1 ) ; XWdtTb_IntrClear ( & WatchdogTimebase ) ; XWdtTb_SetRegSpaceAccessMode ( & WatchdogTimebase , 0 ) ; #if ( WDTTB_EN_PSM ) XWdtTb_SetRegSpaceAccessMode ( & WatchdogTimebase , 1 ) ; if ( WatchdogTimebase . Config . IsPl ) { XWdtTb_WriteReg ( WatchdogTimebase . Config . BaseAddr , XWT_TSR1_OFFSET , WDTTB_TSR_VAL ) ; } else { XWdtTb_WriteReg ( WatchdogTimebase . Config . BaseAddr , XWT_TSR1_WWDT_OFFSET , WDTTB_TSR_VAL ) ; } XWdtTb_SetRegSpaceAccessMode ( & WatchdogTimebase , 0 ) ; #endif XWdtTb_SetRegSpaceAccessMode ( & WatchdogTimebase , 1 ) ; XWdtTb_RestartWdt ( & WatchdogTimebase ) ; Count ++ ; xil_printf ( " \n \r \n \r " , Count ) ; } if ( XWdtTb_GetLastEvent ( & WatchdogTimebase ) != XWDTTB_NO_BAD_EVENT ) { XWdtTb_SetRegSpaceAccessMode ( & WatchdogTimebase , 1 ) ; XWdtTb_Stop ( & WatchdogTimebase ) ; return XST_FAILURE ; } if ( Count == 2 ) { #if ( ! WDTTB_EN_SST && ! WDTTB_EN_FC && ! WDTTB_EN_PSM && ! WDTTB_EN_WDP ) XWdtTb_Stop ( & WatchdogTimebase ) ; #endif break ; } } #if ( WDTTB_EN_SST ) xil_printf ( " " ) ; while ( ! XWdtTb_IsResetPending ( & WatchdogTimebase ) ) { xil_printf ( " " ) ; } XWdtTb_ClearResetPending ( & WatchdogTimebase ) ; if ( WatchdogTimebase . Config . IsPl ) { xil_printf ( " \n \r \n \r " , XWdtTb_ReadReg ( WatchdogTimebase . Config . BaseAddr , XWT_STR_OFFSET ) ) ; } else { xil_printf ( " \n \r \n \r " , XWdtTb_ReadReg ( WatchdogTimebase . Config . BaseAddr , XWT_STR_WWDT_OFFSET ) ) ; } #endif return XST_SUCCESS ; }
This function tests the functioning of the TimeBase WatchDog Timer module
with window feature in the polled mode.
This function tests the functioning of the TimeBase WatchDog Timer module with window feature in the polled mode .
/*
	 * Initialize the WDTTB driver so that it's ready to use look up
	 * configuration in the config table, then initialize it.
	 */ /*
	 * Initialize the watchdog timer and timebase driver so that
	 * it is ready to use.
	 */ /*Enable Window Watchdog Feature in WWDT */ /*
	 * Perform a self-test to ensure that the hardware was built
	 * correctly
	 */ /* Enable extra protection */ /* Disable extra protection */ /* End of WDP */ /* Configure first and second window */ /* Configure Second sequence timer */ /* Set interrupt position */ /* Enable Secondary Sequence Timer (SST) */ /* Disable Secondary Sequence Timer (SST) */ /* End of SST */ /* Enable Program Sequence Monitor (PSM) */ /* Write TSR0 with signature */ /* Disable Program Sequence Monitor (PSM) */ /* End of PSM */ /* Enable Fail Counter */ /* Disable Fail Counter */ /* End of FC */ /*
	 * Start the watchdog timer, the timebase is automatically reset
	 * when this occurs.
	 */ /* Check for interrupt programmed point */ /* Set register space to writable */ /* Clear interrupt point */ /* Set register space to read-only */ /* Set register space to writable */ /* Write TSR1 with signature */ /* Set register space to read-only */ /* Set register space to writable */ /*
			 * Restart the watchdog timer as a normal application
			 * would
			 */ /* Check for last event */ /* Set register space to writable */ /* Stop the watchdog timer */ /*
		 * Check whether the WatchDog timer restarts twice with window
		 * feature. If the timer restarts twice then the test is
		 * passed.
		 */ /* Wait for SST counter start */ /* Clear reset pending */