XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1.c
u32 XHdmiphy1_ResetGtPll(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u8 Hold)
{
	u32 RegVal;
	u32 MaskVal;
	u32 RegOffset;

	/* Suppress Warning Messages */
	QuadId = QuadId;

	if (Dir == XHDMIPHY1_DIR_TX) {
		RegOffset = XHDMIPHY1_TX_INIT_REG;
	}
	else {
		RegOffset = XHDMIPHY1_RX_INIT_REG;
	}
	if (ChId == XHDMIPHY1_CHANNEL_ID_CHA) {
		MaskVal = XHDMIPHY1_TXRX_INIT_PLLGTRESET_ALL_MASK;
	}
	else {
		MaskVal = XHDMIPHY1_TXRX_INIT_PLLGTRESET_MASK(ChId);
	}

	RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr, RegOffset);
	/* Assert reset. */
	RegVal |= MaskVal;
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal);

	if (!Hold) {
		/* De-assert reset. */
		RegVal &= ~MaskVal;
		XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal);
	}

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function will reset the GT's PLL logic.
*
* @param	InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID which to operate on.
* @param	Dir is an indicator for TX or RX.
* @param	Hold is an indicator whether to "hold" the reset if set to 1.
*		If set to 0: reset, then enable.
*
* @return
*		- XST_SUCCESS.
*
* @note		None.
*
******************************************************************************/
This function will reset the GT's PLL logic.
This function will reset the GT ' s PLL logic .
u32 XHdmiphy1_ResetGtPll(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir, u8 Hold)
{
	u32 RegVal;
	u32 MaskVal;
	u32 RegOffset;
	QuadId = QuadId;
	if (Dir == XHDMIPHY1_DIR_TX) {
		RegOffset = XHDMIPHY1_TX_INIT_REG;
	}
	else {
		RegOffset = XHDMIPHY1_RX_INIT_REG;
	}
	if (ChId == XHDMIPHY1_CHANNEL_ID_CHA) {
		MaskVal = XHDMIPHY1_TXRX_INIT_PLLGTRESET_ALL_MASK;
	}
	else {
		MaskVal = XHDMIPHY1_TXRX_INIT_PLLGTRESET_MASK(ChId);
	}
	RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr, RegOffset);
	RegVal |= MaskVal;
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal);
	if (!Hold) {
		RegVal &= ~MaskVal;
		XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal);
	}
	return XST_SUCCESS;
}
u32 XHdmiphy1_ResetGtPll ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId , XHdmiphy1_DirectionType Dir , u8 Hold ) { u32 RegVal ; u32 MaskVal ; u32 RegOffset ; QuadId = QuadId ; if ( Dir == XHDMIPHY1_DIR_TX ) { RegOffset = XHDMIPHY1_TX_INIT_REG ; } else { RegOffset = XHDMIPHY1_RX_INIT_REG ; } if ( ChId == XHDMIPHY1_CHANNEL_ID_CHA ) { MaskVal = XHDMIPHY1_TXRX_INIT_PLLGTRESET_ALL_MASK ; } else { MaskVal = XHDMIPHY1_TXRX_INIT_PLLGTRESET_MASK ( ChId ) ; } RegVal = XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , RegOffset ) ; RegVal |= MaskVal ; XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffset , RegVal ) ; if ( ! Hold ) { RegVal &= ~ MaskVal ; XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffset , RegVal ) ; } return XST_SUCCESS ; }
This function will reset the GT's PLL logic.
This function will reset the GT ' s PLL logic .
/* Suppress Warning Messages */ /* Assert reset. */ /* De-assert reset. */