XilinxProcessorIPLib/drivers/axipcie/examples/xaxipcie_ep_cdma_example.c
int PCIeEndPointInitialize(XAxiPcie *XlnxEndPointPtr, u16 DeviceId)
{
	int Status;
	u32 HeaderData;
	u32 InterruptMask;
	u8  BusNum;
	u8  DeviceNum;
	u8  FunctionNum;
	u8  PortNumber;
	XAxiPcie_Config *ConfigPtr;

	/* Initialization of the driver */
	ConfigPtr = XAxiPcie_LookupConfig(DeviceId);
	if (ConfigPtr == NULL) {
		xil_printf("Failed to initialize PCIe End Point Instance\r\n");
		return XST_FAILURE;
	}


	Status = XAxiPcie_CfgInitialize(XlnxEndPointPtr, ConfigPtr,
						ConfigPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		xil_printf("Failed to initialize PCIe End Point Instance\r\n");
		return Status;
	}


	/* See what interrupts are currently enabled */
	XAxiPcie_GetEnabledInterrupts(XlnxEndPointPtr, &InterruptMask);
	xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);

	/* Disable.all interrupts */
	XAxiPcie_DisableInterrupts(XlnxEndPointPtr,
						XAXIPCIE_IM_ENABLE_ALL_MASK);

	/* See what interrupts are currently pending */
	XAxiPcie_GetPendingInterrupts(XlnxEndPointPtr, &InterruptMask);
	xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);

	/* Clear the pending interrupt */
	XAxiPcie_ClearPendingInterrupts(XlnxEndPointPtr,
						XAXIPCIE_ID_CLEAR_ALL_MASK);

	/*
	 * Read enabled interrupts and pending interrupts
	 * to verify the previous two operations and also
	 * to test those two API functions
	 */
	XAxiPcie_GetEnabledInterrupts(XlnxEndPointPtr, &InterruptMask);
	xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);

	XAxiPcie_GetPendingInterrupts(XlnxEndPointPtr, &InterruptMask);
	xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);


	/* Make sure link is up. */
	Status = XAxiPcie_IsLinkUp(XlnxEndPointPtr);
	if (Status != TRUE ) {
		xil_printf("Link is not up\r\n");
		return XST_FAILURE;
	}


	xil_printf("Link is up\r\n");


	/* See if root complex has already configured this end point. */

	XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_CMD_STATUS_REG,
								&HeaderData);

	xil_printf("PCIe Command/Status Register is %08X\r\n", HeaderData);

	if (HeaderData & PCIE_CFG_CMD_BUSM_EN) {

		xil_printf("Root Complex has configured this end point\r\n");
	}
	else {
		xil_printf("Root Complex has NOT yet configured this"
							" end point\r\n");
		return XST_FAILURE;
	}

	XAxiPcie_GetRequesterId(XlnxEndPointPtr, &BusNum,
				&DeviceNum, &FunctionNum, &PortNumber);

	xil_printf("Bus Number is %02X\r\n"
				"Device Number is %02X\r\n"
				"Function Number is %02X\r\n"
				"Port Number is %02X\r\n",
				BusNum, DeviceNum, FunctionNum, PortNumber);

	/* Read my configuration space */
	XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_ID_REG,
								&HeaderData);
	xil_printf("PCIe Vendor ID/Device ID Register is %08X\r\n",
								HeaderData);

	XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_CMD_STATUS_REG,
								&HeaderData);

	xil_printf("PCIe Command/Status Register is %08X\r\n", HeaderData);

	XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_CAH_LAT_HD_REG,
								&HeaderData);

	xil_printf("PCIe Header Type/Latency Timer Register is %08X\r\n",
								HeaderData);

	XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_BAR_ZERO_REG,
								&HeaderData);

	xil_printf("PCIe BAR 0 is %08X\r\n", HeaderData);


	return XST_SUCCESS;
}
/****************************************************************************/
/**
* This initialize an IP built as an end point.
*
* @param	XlnxEndPointPtr is a pointer to an instance of XAxiPcie data
*		structure represents an end point IP.
* @param	DeviceId is PCIe IP unique ID
*
* @return
*		- XST_SUCCESS if successful
*		- XST_FAILURE if unsuccessful
*
* @note		None.
*
******************************************************************************/
This initialize an IP built as an end point.
This initialize an IP built as an end point .
int PCIeEndPointInitialize(XAxiPcie *XlnxEndPointPtr, u16 DeviceId)
{
	int Status;
	u32 HeaderData;
	u32 InterruptMask;
	u8  BusNum;
	u8  DeviceNum;
	u8  FunctionNum;
	u8  PortNumber;
	XAxiPcie_Config *ConfigPtr;
	ConfigPtr = XAxiPcie_LookupConfig(DeviceId);
	if (ConfigPtr == NULL) {
		xil_printf("Failed to initialize PCIe End Point Instance\r\n");
		return XST_FAILURE;
	}
	Status = XAxiPcie_CfgInitialize(XlnxEndPointPtr, ConfigPtr,
						ConfigPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		xil_printf("Failed to initialize PCIe End Point Instance\r\n");
		return Status;
	}
	XAxiPcie_GetEnabledInterrupts(XlnxEndPointPtr, &InterruptMask);
	xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);
	XAxiPcie_DisableInterrupts(XlnxEndPointPtr,
						XAXIPCIE_IM_ENABLE_ALL_MASK);
	XAxiPcie_GetPendingInterrupts(XlnxEndPointPtr, &InterruptMask);
	xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);
	XAxiPcie_ClearPendingInterrupts(XlnxEndPointPtr,
						XAXIPCIE_ID_CLEAR_ALL_MASK);
	XAxiPcie_GetEnabledInterrupts(XlnxEndPointPtr, &InterruptMask);
	xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);
	XAxiPcie_GetPendingInterrupts(XlnxEndPointPtr, &InterruptMask);
	xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);
	Status = XAxiPcie_IsLinkUp(XlnxEndPointPtr);
	if (Status != TRUE ) {
		xil_printf("Link is not up\r\n");
		return XST_FAILURE;
	}
	xil_printf("Link is up\r\n");
	XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_CMD_STATUS_REG,
								&HeaderData);
	xil_printf("PCIe Command/Status Register is %08X\r\n", HeaderData);
	if (HeaderData & PCIE_CFG_CMD_BUSM_EN) {
		xil_printf("Root Complex has configured this end point\r\n");
	}
	else {
		xil_printf("Root Complex has NOT yet configured this"
							" end point\r\n");
		return XST_FAILURE;
	}
	XAxiPcie_GetRequesterId(XlnxEndPointPtr, &BusNum,
				&DeviceNum, &FunctionNum, &PortNumber);
	xil_printf("Bus Number is %02X\r\n"
				"Device Number is %02X\r\n"
				"Function Number is %02X\r\n"
				"Port Number is %02X\r\n",
				BusNum, DeviceNum, FunctionNum, PortNumber);
	XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_ID_REG,
								&HeaderData);
	xil_printf("PCIe Vendor ID/Device ID Register is %08X\r\n",
								HeaderData);
	XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_CMD_STATUS_REG,
								&HeaderData);
	xil_printf("PCIe Command/Status Register is %08X\r\n", HeaderData);
	XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_CAH_LAT_HD_REG,
								&HeaderData);
	xil_printf("PCIe Header Type/Latency Timer Register is %08X\r\n",
								HeaderData);
	XAxiPcie_ReadLocalConfigSpace(XlnxEndPointPtr, PCIE_CFG_BAR_ZERO_REG,
								&HeaderData);
	xil_printf("PCIe BAR 0 is %08X\r\n", HeaderData);
	return XST_SUCCESS;
}
int PCIeEndPointInitialize ( XAxiPcie * XlnxEndPointPtr , u16 DeviceId ) { int Status ; u32 HeaderData ; u32 InterruptMask ; u8 BusNum ; u8 DeviceNum ; u8 FunctionNum ; u8 PortNumber ; XAxiPcie_Config * ConfigPtr ; ConfigPtr = XAxiPcie_LookupConfig ( DeviceId ) ; if ( ConfigPtr == NULL ) { xil_printf ( " \r \n " ) ; return XST_FAILURE ; } Status = XAxiPcie_CfgInitialize ( XlnxEndPointPtr , ConfigPtr , ConfigPtr -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \r \n " ) ; return Status ; } XAxiPcie_GetEnabledInterrupts ( XlnxEndPointPtr , & InterruptMask ) ; xil_printf ( " \r \n " , InterruptMask ) ; XAxiPcie_DisableInterrupts ( XlnxEndPointPtr , XAXIPCIE_IM_ENABLE_ALL_MASK ) ; XAxiPcie_GetPendingInterrupts ( XlnxEndPointPtr , & InterruptMask ) ; xil_printf ( " \r \n " , InterruptMask ) ; XAxiPcie_ClearPendingInterrupts ( XlnxEndPointPtr , XAXIPCIE_ID_CLEAR_ALL_MASK ) ; XAxiPcie_GetEnabledInterrupts ( XlnxEndPointPtr , & InterruptMask ) ; xil_printf ( " \r \n " , InterruptMask ) ; XAxiPcie_GetPendingInterrupts ( XlnxEndPointPtr , & InterruptMask ) ; xil_printf ( " \r \n " , InterruptMask ) ; Status = XAxiPcie_IsLinkUp ( XlnxEndPointPtr ) ; if ( Status != TRUE ) { xil_printf ( " \r \n " ) ; return XST_FAILURE ; } xil_printf ( " \r \n " ) ; XAxiPcie_ReadLocalConfigSpace ( XlnxEndPointPtr , PCIE_CFG_CMD_STATUS_REG , & HeaderData ) ; xil_printf ( " \r \n " , HeaderData ) ; if ( HeaderData & PCIE_CFG_CMD_BUSM_EN ) { xil_printf ( " \r \n " ) ; } else { xil_printf ( " " " \r \n " ) ; return XST_FAILURE ; } XAxiPcie_GetRequesterId ( XlnxEndPointPtr , & BusNum , & DeviceNum , & FunctionNum , & PortNumber ) ; xil_printf ( " \r \n " " \r \n " " \r \n " " \r \n " , BusNum , DeviceNum , FunctionNum , PortNumber ) ; XAxiPcie_ReadLocalConfigSpace ( XlnxEndPointPtr , PCIE_CFG_ID_REG , & HeaderData ) ; xil_printf ( " \r \n " , HeaderData ) ; XAxiPcie_ReadLocalConfigSpace ( XlnxEndPointPtr , PCIE_CFG_CMD_STATUS_REG , & HeaderData ) ; xil_printf ( " \r \n " , HeaderData ) ; XAxiPcie_ReadLocalConfigSpace ( XlnxEndPointPtr , PCIE_CFG_CAH_LAT_HD_REG , & HeaderData ) ; xil_printf ( " \r \n " , HeaderData ) ; XAxiPcie_ReadLocalConfigSpace ( XlnxEndPointPtr , PCIE_CFG_BAR_ZERO_REG , & HeaderData ) ; xil_printf ( " \r \n " , HeaderData ) ; return XST_SUCCESS ; }
This initialize an IP built as an end point.
This initialize an IP built as an end point .
/* Initialization of the driver */ /* See what interrupts are currently enabled */ /* Disable.all interrupts */ /* See what interrupts are currently pending */ /* Clear the pending interrupt */ /*
	 * Read enabled interrupts and pending interrupts
	 * to verify the previous two operations and also
	 * to test those two API functions
	 */ /* Make sure link is up. */ /* See if root complex has already configured this end point. */ /* Read my configuration space */