XilinxProcessorIPLib/drivers/can/src/xcan.c
int XCan_AcceptFilterSet(XCan *InstancePtr, u32 FilterIndex,
			 u32 MaskValue, u32 IdValue)
{
	u32 EnabledFilters;

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid(InstancePtr->NumOfAcceptFilters > 0);
	Xil_AssertNonvoid((FilterIndex == XCAN_AFR_UAF4_MASK) ||
			(FilterIndex == XCAN_AFR_UAF3_MASK) ||
			(FilterIndex == XCAN_AFR_UAF2_MASK) ||
			(FilterIndex == XCAN_AFR_UAF1_MASK));

	/*
	 * Check if the given filter is currently enabled. If yes, return error
	 * code.
	 */
	EnabledFilters = XCan_AcceptFilterGetEnabled(InstancePtr);
	if ((EnabledFilters & FilterIndex) == FilterIndex) {
		return XST_FAILURE;
	}

	/*
	 * If the CAN device is not ready to accept writes to AFMR and AFIR,
	 * return error code.
	 */
	if (XCan_IsAcceptFilterBusy(InstancePtr) == TRUE) {
		return XST_FAILURE;
	}

	/* Write AFMR and AFIR of the given filter */

	switch (FilterIndex) {
	case XCAN_AFR_UAF1_MASK:	/* Acceptance Filter No. 1 */
		/* Write Mask Register */
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFMR1_OFFSET,
				MaskValue);
		/* Write ID Register */
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFIR1_OFFSET,
				IdValue);
		break;
	case XCAN_AFR_UAF2_MASK:	/* Acceptance Filter No. 2 */
		/* Write Mask Register */
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFMR2_OFFSET,
				MaskValue);
		/* Write ID Register */
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFIR2_OFFSET,
				   IdValue);
		break;
	case XCAN_AFR_UAF3_MASK:	/* Acceptance Filter No. 3 */
		/* Write Mask Register */
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFMR3_OFFSET,
				MaskValue);
		/* Write ID Register */
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFIR3_OFFSET,
				IdValue);
		break;
	case XCAN_AFR_UAF4_MASK:	/* Acceptance Filter No. 4 */
		/* Write Mask Register */
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFMR4_OFFSET,
				MaskValue);
		/* Write ID Register */
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFIR4_OFFSET,
				IdValue);
		break;
	}

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function sets values to the Acceptance Filter Mask Register (AFMR) and
* Acceptance Filter ID Register (AFIR) for the specified Acceptance Filter.
* Use XCAN_IDR_* defined in xcan_l.h to create the values to set the filter.
* Read xcan.h and device specification for details.
*
* This function should be called only after:
*   - The given filter is disabled by calling XCan_AcceptFilterDisable();
*   - And the CAN device is ready to accept writes to AFMR and AFIR, i.e.,
*	 XCan_IsAcceptFilterBusy() returns FALSE.
*
* @param	InstancePtr is a pointer to the XCan instance to be worked on.
* @param	FilterIndex defines which Acceptance Filter Mask and ID Register
*		to set. Use any single XCAN_AFR_UAF*_MASK value.
* @param	MaskValue is the value to write to the chosen Acceptance Filter
*		Mask Register.
* @param	IdValue is the value to write to the chosen Acceptance Filter
*		ID Register.
*
* @return
*		- XST_SUCCESS if the values were set successfully.
*		- XST_FAILURE if the given filter was not disabled, or the CAN
*		device was not ready to accept writes to AFMR and AFIR.
*
* @note
*
* Acceptance Filter Mask and ID Registers are optional registers in Xilinx CAN
* device. If they are NOT existing in the device, this function should NOT
* be used. Calling this function in this case will cause an assertion failure.
*
******************************************************************************/
This function sets values to the Acceptance Filter Mask Register (AFMR) and
Acceptance Filter ID Register (AFIR) for the specified Acceptance Filter.
Use XCAN_IDR_* defined in xcan_l.h to create the values to set the filter.
Read xcan.h and device specification for details.

This function should be called only after:
The given filter is disabled by calling XCan_AcceptFilterDisable();
And the CAN device is ready to accept writes to AFMR and AFIR, i.e.,
XCan_IsAcceptFilterBusy() returns FALSE.
This function sets values to the Acceptance Filter Mask Register ( AFMR ) and Acceptance Filter ID Register ( AFIR ) for the specified Acceptance Filter . Use XCAN_IDR_ * defined in xcan_l . h to create the values to set the filter . Read xcan . h and device specification for details . This function should be called only after : The given filter is disabled by calling XCan_AcceptFilterDisable () ; And the CAN device is ready to accept writes to AFMR and AFIR i . e . XCan_IsAcceptFilterBusy () returns FALSE .
int XCan_AcceptFilterSet(XCan *InstancePtr, u32 FilterIndex,
			 u32 MaskValue, u32 IdValue)
{
	u32 EnabledFilters;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid(InstancePtr->NumOfAcceptFilters > 0);
	Xil_AssertNonvoid((FilterIndex == XCAN_AFR_UAF4_MASK) ||
			(FilterIndex == XCAN_AFR_UAF3_MASK) ||
			(FilterIndex == XCAN_AFR_UAF2_MASK) ||
			(FilterIndex == XCAN_AFR_UAF1_MASK));
	EnabledFilters = XCan_AcceptFilterGetEnabled(InstancePtr);
	if ((EnabledFilters & FilterIndex) == FilterIndex) {
		return XST_FAILURE;
	}
	if (XCan_IsAcceptFilterBusy(InstancePtr) == TRUE) {
		return XST_FAILURE;
	}
	switch (FilterIndex) {
	case XCAN_AFR_UAF1_MASK:	
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFMR1_OFFSET,
				MaskValue);
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFIR1_OFFSET,
				IdValue);
		break;
	case XCAN_AFR_UAF2_MASK:	
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFMR2_OFFSET,
				MaskValue);
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFIR2_OFFSET,
				   IdValue);
		break;
	case XCAN_AFR_UAF3_MASK:	
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFMR3_OFFSET,
				MaskValue);
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFIR3_OFFSET,
				IdValue);
		break;
	case XCAN_AFR_UAF4_MASK:	
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFMR4_OFFSET,
				MaskValue);
		XCan_WriteReg(InstancePtr->BaseAddress, XCAN_AFIR4_OFFSET,
				IdValue);
		break;
	}
	return XST_SUCCESS;
}
int XCan_AcceptFilterSet ( XCan * InstancePtr , u32 FilterIndex , u32 MaskValue , u32 IdValue ) { u32 EnabledFilters ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Xil_AssertNonvoid ( InstancePtr -> NumOfAcceptFilters > 0 ) ; Xil_AssertNonvoid ( ( FilterIndex == XCAN_AFR_UAF4_MASK ) || ( FilterIndex == XCAN_AFR_UAF3_MASK ) || ( FilterIndex == XCAN_AFR_UAF2_MASK ) || ( FilterIndex == XCAN_AFR_UAF1_MASK ) ) ; EnabledFilters = XCan_AcceptFilterGetEnabled ( InstancePtr ) ; if ( ( EnabledFilters & FilterIndex ) == FilterIndex ) { return XST_FAILURE ; } if ( XCan_IsAcceptFilterBusy ( InstancePtr ) == TRUE ) { return XST_FAILURE ; } switch ( FilterIndex ) { case XCAN_AFR_UAF1_MASK : XCan_WriteReg ( InstancePtr -> BaseAddress , XCAN_AFMR1_OFFSET , MaskValue ) ; XCan_WriteReg ( InstancePtr -> BaseAddress , XCAN_AFIR1_OFFSET , IdValue ) ; break ; case XCAN_AFR_UAF2_MASK : XCan_WriteReg ( InstancePtr -> BaseAddress , XCAN_AFMR2_OFFSET , MaskValue ) ; XCan_WriteReg ( InstancePtr -> BaseAddress , XCAN_AFIR2_OFFSET , IdValue ) ; break ; case XCAN_AFR_UAF3_MASK : XCan_WriteReg ( InstancePtr -> BaseAddress , XCAN_AFMR3_OFFSET , MaskValue ) ; XCan_WriteReg ( InstancePtr -> BaseAddress , XCAN_AFIR3_OFFSET , IdValue ) ; break ; case XCAN_AFR_UAF4_MASK : XCan_WriteReg ( InstancePtr -> BaseAddress , XCAN_AFMR4_OFFSET , MaskValue ) ; XCan_WriteReg ( InstancePtr -> BaseAddress , XCAN_AFIR4_OFFSET , IdValue ) ; break ; } return XST_SUCCESS ; }
This function sets values to the Acceptance Filter Mask Register (AFMR) and
Acceptance Filter ID Register (AFIR) for the specified Acceptance Filter.
This function sets values to the Acceptance Filter Mask Register ( AFMR ) and Acceptance Filter ID Register ( AFIR ) for the specified Acceptance Filter .
/*
	 * Check if the given filter is currently enabled. If yes, return error
	 * code.
	 */ /*
	 * If the CAN device is not ready to accept writes to AFMR and AFIR,
	 * return error code.
	 */ /* Write AFMR and AFIR of the given filter */ /* Acceptance Filter No. 1 */ /* Write Mask Register */ /* Write ID Register */ /* Acceptance Filter No. 2 */ /* Write Mask Register */ /* Write ID Register */ /* Acceptance Filter No. 3 */ /* Write Mask Register */ /* Write ID Register */ /* Acceptance Filter No. 4 */ /* Write Mask Register */ /* Write ID Register */