src/dpdk/drivers/net/cxgbe/base/t4_hw.c
void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
		     unsigned int start_index, unsigned int rw)
{
	int cmd = FW_LDST_ADDRSPC_TP_PIO;
	struct fw_ldst_cmd c;
	unsigned int i;
	int ret;

	for (i = 0 ; i < nregs; i++) {
		memset(&c, 0, sizeof(c));
		c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
						F_FW_CMD_REQUEST |
						(rw ? F_FW_CMD_READ :
						      F_FW_CMD_WRITE) |
						V_FW_LDST_CMD_ADDRSPACE(cmd));
		c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));

		c.u.addrval.addr = cpu_to_be32(start_index + i);
		c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
		ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
		if (ret == 0) {
			if (rw)
				vals[i] = be32_to_cpu(c.u.addrval.val);
		}
	}
}
/**
 * t4_fw_tp_pio_rw - Access TP PIO through LDST
 * @adap: the adapter
 * @vals: where the indirect register values are stored/written
 * @nregs: how many indirect registers to read/write
 * @start_idx: index of first indirect register to read/write
 * @rw: Read (1) or Write (0)
 *
 * Access TP PIO registers through LDST
 */


Access TP PIO registers through LDST
Access TP PIO registers through LDST
void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
		     unsigned int start_index, unsigned int rw)
{
	int cmd = FW_LDST_ADDRSPC_TP_PIO;
	struct fw_ldst_cmd c;
	unsigned int i;
	int ret;
	for (i = 0 ; i < nregs; i++) {
		memset(&c, 0, sizeof(c));
		c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
						F_FW_CMD_REQUEST |
						(rw ? F_FW_CMD_READ :
						      F_FW_CMD_WRITE) |
						V_FW_LDST_CMD_ADDRSPACE(cmd));
		c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
		c.u.addrval.addr = cpu_to_be32(start_index + i);
		c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
		ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
		if (ret == 0) {
			if (rw)
				vals[i] = be32_to_cpu(c.u.addrval.val);
		}
	}
}
void t4_fw_tp_pio_rw ( struct adapter * adap , u32 * vals , unsigned int nregs , unsigned int start_index , unsigned int rw ) { int cmd = FW_LDST_ADDRSPC_TP_PIO ; struct fw_ldst_cmd c ; unsigned int i ; int ret ; for ( i = 0 ; i < nregs ; i ++ ) { memset ( & c , 0 , sizeof ( c ) ) ; c . op_to_addrspace = cpu_to_be32 ( V_FW_CMD_OP ( FW_LDST_CMD ) | F_FW_CMD_REQUEST | ( rw ? F_FW_CMD_READ : F_FW_CMD_WRITE ) | V_FW_LDST_CMD_ADDRSPACE ( cmd ) ) ; c . cycles_to_len16 = cpu_to_be32 ( FW_LEN16 ( c ) ) ; c . u . addrval . addr = cpu_to_be32 ( start_index + i ) ; c . u . addrval . val = rw ? 0 : cpu_to_be32 ( vals [ i ] ) ; ret = t4_wr_mbox ( adap , adap -> mbox , & c , sizeof ( c ) , & c ) ; if ( ret == 0 ) { if ( rw ) vals [ i ] = be32_to_cpu ( c . u . addrval . val ) ; } } }
t4_fw_tp_pio_rw - Access TP PIO through LDST
 @adap: the adapter
 @vals: where the indirect register values are stored/written
 @nregs: how many indirect registers to read/write
 @start_idx: index of first indirect register to read/write
 @rw: Read (1) or Write (0)
t4_fw_tp_pio_rw - Access TP PIO through LDST @adap : the adapter @vals : where the indirect register values are stored / written @nregs : how many indirect registers to read / write @start_idx : index of first indirect register to read / write @rw : Read ( 1 ) or Write ( 0 )