emlib/src/em_cmu.c
void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc)
{
  uint32_t freq;
  uint32_t prescReg;

  /* Get divisor reg id */
  prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;

  switch (prescReg) {
    case CMU_HFPRESC_REG:
      EFM_ASSERT(presc < 32U);

      /* Configure worst case wait-states for flash and HFLE. */
      flashWaitStateMax();
      setHfLeConfig(CMU_MAX_FREQ_HFLE + 1);

      CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK)
                     | (presc << _CMU_HFPRESC_PRESC_SHIFT);

      /* Update CMSIS core clock variable (this function updates the global variable).
         Optimize flash and HFLE wait states. */
      freq = SystemCoreClockGet();
      CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);

      setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));
      break;

    case CMU_HFEXPPRESC_REG:
      EFM_ASSERT(presc < 32U);

      CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK)
                        | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT);
      break;

    case CMU_HFCLKLEPRESC_REG:
#if defined (CMU_HFPRESC_HFCLKLEPRESC_DIV8)
      EFM_ASSERT(presc < 3U);
#else
      EFM_ASSERT(presc < 2U);
#endif

      /* Specifies the clock divider for HFCLKLE. This clock divider must be set
       * high enough for the divided clock frequency to be at or below the max
       * frequency allowed for the HFCLKLE clock. */
      CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK)
                     | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
      break;

    case CMU_HFPERPRESC_REG:
      EFM_ASSERT(presc < 512U);

      CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK)
                        | (presc << _CMU_HFPERPRESC_PRESC_SHIFT);
      break;

    case CMU_HFCOREPRESC_REG:
      EFM_ASSERT(presc < 512U);

      /* Configure worst case wait-states for flash and HFLE. */
      flashWaitStateMax();
      setHfLeConfig(CMU_MAX_FREQ_HFLE + 1);

      CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK)
                         | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT);

      /* Update CMSIS core clock variable (this function updates the global variable).
         Optimize flash and HFLE wait states. */
      freq = SystemCoreClockGet();
      CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
      setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));
      break;

    case CMU_LFAPRESC0_REG:
      switch (clock) {
#if defined(RTC_PRESENT)
        case cmuClock_RTC:
          EFM_ASSERT(presc <= 32768U);

          /* Convert prescaler value to DIV exponent scale. */
          presc = CMU_PrescToLog2(presc);

          /* LF register about to be modified require sync. Busy check. */
          syncReg(CMU_SYNCBUSY_LFAPRESC0);

          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
                           | (presc << _CMU_LFAPRESC0_RTC_SHIFT);
          break;
#endif

#if defined(RTCC_PRESENT)
        case cmuClock_RTCC:
#if defined(_CMU_LFEPRESC0_RTCC_MASK)
          /* DIV1 is the only accepted value. */
          EFM_ASSERT(presc <= 0U);

          /* LF register about to be modified require sync. Busy check.. */
          syncReg(CMU_SYNCBUSY_LFEPRESC0);

          CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
                           | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
#else
          EFM_ASSERT(presc <= 32768U);

          /* Convert prescaler value to DIV exponent scale. */
          presc = CMU_PrescToLog2(presc);

          /* LF register about to be modified require sync. Busy check. */
          syncReg(CMU_SYNCBUSY_LFAPRESC0);

          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK)
                           | (presc << _CMU_LFAPRESC0_RTCC_SHIFT);
#endif
          break;
#endif

#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
        case cmuClock_LETIMER0:
          EFM_ASSERT(presc <= 32768U);

          /* Convert prescaler value to DIV exponent scale. */
          presc = CMU_PrescToLog2(presc);

          /* LF register about to be modified require sync. Busy check. */
          syncReg(CMU_SYNCBUSY_LFAPRESC0);

          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
                           | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT);
          break;
#endif

#if defined(_CMU_LFAPRESC0_LESENSE_MASK)
        case cmuClock_LESENSE:
          EFM_ASSERT(presc <= 8);

          /* Convert prescaler value to DIV exponent scale. */
          presc = CMU_PrescToLog2(presc);

          /* LF register about to be modified require sync. Busy check. */
          syncReg(CMU_SYNCBUSY_LFAPRESC0);

          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
                           | (presc << _CMU_LFAPRESC0_LESENSE_SHIFT);
          break;
#endif

#if defined(_CMU_LFAPRESC0_LCD_MASK)
        case cmuClock_LCDpre:
        case cmuClock_LCD:
        {
          EFM_ASSERT(presc <= 32768U);

          /* Convert prescaler value to DIV exponent scale. */
          presc = CMU_PrescToLog2(presc);

          /* LF register about to be modified require sync. Busy check. */
          syncReg(CMU_SYNCBUSY_LFAPRESC0);

          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)
                           | (presc << _CMU_LFAPRESC0_LCD_SHIFT);
        } break;
#endif

        default:
          EFM_ASSERT(0);
          break;
      }
      break;

    case CMU_LFBPRESC0_REG:
      switch (clock) {
#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
        case cmuClock_LEUART0:
          EFM_ASSERT(presc <= 8U);

          /* Convert prescaler value to DIV exponent scale. */
          presc = CMU_PrescToLog2(presc);

          /* LF register about to be modified require sync. Busy check. */
          syncReg(CMU_SYNCBUSY_LFBPRESC0);

          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
                           | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT);
          break;
#endif

#if defined(_CMU_LFBPRESC0_LEUART1_MASK)
        case cmuClock_LEUART1:
          EFM_ASSERT(presc <= 8U);

          /* Convert prescaler value to DIV exponent scale. */
          presc = CMU_PrescToLog2(presc);

          /* LF register about to be modified require sync. Busy check. */
          syncReg(CMU_SYNCBUSY_LFBPRESC0);

          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
                           | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT);
          break;
#endif

#if defined(_CMU_LFBPRESC0_CSEN_MASK)
        case cmuClock_CSEN_LF:
          EFM_ASSERT((presc <= 127U) && (presc >= 15U));

          /* Convert prescaler value to DIV exponent scale.
           * DIV16 is the lowest supported prescaler. */
          presc = CMU_PrescToLog2(presc) - 4;

          /* LF register about to be modified require sync. Busy check. */
          syncReg(CMU_SYNCBUSY_LFBPRESC0);

          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK)
                           | (presc << _CMU_LFBPRESC0_CSEN_SHIFT);
          break;
#endif

        default:
          EFM_ASSERT(0);
          break;
      }
      break;

    case CMU_LFEPRESC0_REG:
      switch (clock) {
#if defined(_CMU_LFEPRESC0_RTCC_MASK)
        case cmuClock_RTCC:
          EFM_ASSERT(presc <= 0U);

          /* LF register about to be modified require sync. Busy check. */
          syncReg(CMU_SYNCBUSY_LFEPRESC0);

          CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
                           | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
          break;
#endif

        default:
          EFM_ASSERT(0);
          break;
      }
      break;

    case CMU_ADCASYNCDIV_REG:
      switch (clock) {
#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK)
        case cmuClock_ADC0ASYNC:
          EFM_ASSERT(presc <= 3);
          CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKDIV_MASK)
                         | (presc << _CMU_ADCCTRL_ADC0CLKDIV_SHIFT);
          break;
#endif

#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK)
        case cmuClock_ADC1ASYNC:
          EFM_ASSERT(presc <= 3);
          CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKDIV_MASK)
                         | (presc << _CMU_ADCCTRL_ADC1CLKDIV_SHIFT);
          break;
#endif
        default:
          EFM_ASSERT(0);
          break;
      }
      break;

    default:
      EFM_ASSERT(0);
      break;
  }
}
/***************************************************************************/
/**
 * @brief
 *   Set clock prescaler.
 *
 * @note
 *   If setting a LF clock prescaler, synchronization into the low frequency
 *   domain is required. If the same register is modified before a previous
 *   update has completed, this function will stall until the previous
 *   synchronization has completed. Please refer to CMU_FreezeEnable() for
 *   a suggestion on how to reduce stalling time in some use cases.
 *
 * @param[in] clock
 *   Clock point to set prescaler for. Notice that not all clock points
 *   have a prescaler, please refer to CMU overview in the reference manual.
 *
 * @param[in] presc
 *   The clock prescaler to use.
 ******************************************************************************/
@brief
Set clock prescaler.

@note
If setting a LF clock prescaler, synchronization into the low frequency
domain is required. If the same register is modified before a previous
update has completed, this function will stall until the previous
synchronization has completed. Please refer to CMU_FreezeEnable() for
a suggestion on how to reduce stalling time in some use cases.

@param[in] clock
Clock point to set prescaler for. Notice that not all clock points
have a prescaler, please refer to CMU overview in the reference manual.

@param[in] presc
The clock prescaler to use.
@brief Set clock prescaler . @note If setting a LF clock prescaler synchronization into the low frequency domain is required . If the same register is modified before a previous update has completed this function will stall until the previous synchronization has completed . Please refer to CMU_FreezeEnable () for a suggestion on how to reduce stalling time in some use cases . @param [ in ] clock Clock point to set prescaler for . Notice that not all clock points have a prescaler please refer to CMU overview in the reference manual . @param [ in ] presc The clock prescaler to use .
void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc)
{
  uint32_t freq;
  uint32_t prescReg;
  prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
  switch (prescReg) {
    case CMU_HFPRESC_REG:
      EFM_ASSERT(presc < 32U);
      flashWaitStateMax();
      setHfLeConfig(CMU_MAX_FREQ_HFLE + 1);
      CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK)
                     | (presc << _CMU_HFPRESC_PRESC_SHIFT);
      freq = SystemCoreClockGet();
      CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
      setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));
      break;
    case CMU_HFEXPPRESC_REG:
      EFM_ASSERT(presc < 32U);
      CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK)
                        | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT);
      break;
    case CMU_HFCLKLEPRESC_REG:
#if defined (CMU_HFPRESC_HFCLKLEPRESC_DIV8)
      EFM_ASSERT(presc < 3U);
#else
      EFM_ASSERT(presc < 2U);
#endif
      CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK)
                     | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
      break;
    case CMU_HFPERPRESC_REG:
      EFM_ASSERT(presc < 512U);
      CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK)
                        | (presc << _CMU_HFPERPRESC_PRESC_SHIFT);
      break;
    case CMU_HFCOREPRESC_REG:
      EFM_ASSERT(presc < 512U);
      flashWaitStateMax();
      setHfLeConfig(CMU_MAX_FREQ_HFLE + 1);
      CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK)
                         | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT);
      freq = SystemCoreClockGet();
      CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
      setHfLeConfig(CMU_ClockFreqGet(cmuClock_HFLE));
      break;
    case CMU_LFAPRESC0_REG:
      switch (clock) {
#if defined(RTC_PRESENT)
        case cmuClock_RTC:
          EFM_ASSERT(presc <= 32768U);
          presc = CMU_PrescToLog2(presc);
          syncReg(CMU_SYNCBUSY_LFAPRESC0);
          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
                           | (presc << _CMU_LFAPRESC0_RTC_SHIFT);
          break;
#endif
#if defined(RTCC_PRESENT)
        case cmuClock_RTCC:
#if defined(_CMU_LFEPRESC0_RTCC_MASK)
          EFM_ASSERT(presc <= 0U);
          syncReg(CMU_SYNCBUSY_LFEPRESC0);
          CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
                           | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
#else
          EFM_ASSERT(presc <= 32768U);
          presc = CMU_PrescToLog2(presc);
          syncReg(CMU_SYNCBUSY_LFAPRESC0);
          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK)
                           | (presc << _CMU_LFAPRESC0_RTCC_SHIFT);
#endif
          break;
#endif
#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
        case cmuClock_LETIMER0:
          EFM_ASSERT(presc <= 32768U);
          presc = CMU_PrescToLog2(presc);
          syncReg(CMU_SYNCBUSY_LFAPRESC0);
          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
                           | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT);
          break;
#endif
#if defined(_CMU_LFAPRESC0_LESENSE_MASK)
        case cmuClock_LESENSE:
          EFM_ASSERT(presc <= 8);
          presc = CMU_PrescToLog2(presc);
          syncReg(CMU_SYNCBUSY_LFAPRESC0);
          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
                           | (presc << _CMU_LFAPRESC0_LESENSE_SHIFT);
          break;
#endif
#if defined(_CMU_LFAPRESC0_LCD_MASK)
        case cmuClock_LCDpre:
        case cmuClock_LCD:
        {
          EFM_ASSERT(presc <= 32768U);
          presc = CMU_PrescToLog2(presc);
          syncReg(CMU_SYNCBUSY_LFAPRESC0);
          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)
                           | (presc << _CMU_LFAPRESC0_LCD_SHIFT);
        } break;
#endif
        default:
          EFM_ASSERT(0);
          break;
      }
      break;
    case CMU_LFBPRESC0_REG:
      switch (clock) {
#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
        case cmuClock_LEUART0:
          EFM_ASSERT(presc <= 8U);
          presc = CMU_PrescToLog2(presc);
          syncReg(CMU_SYNCBUSY_LFBPRESC0);
          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
                           | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT);
          break;
#endif
#if defined(_CMU_LFBPRESC0_LEUART1_MASK)
        case cmuClock_LEUART1:
          EFM_ASSERT(presc <= 8U);
          presc = CMU_PrescToLog2(presc);
          syncReg(CMU_SYNCBUSY_LFBPRESC0);
          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
                           | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT);
          break;
#endif
#if defined(_CMU_LFBPRESC0_CSEN_MASK)
        case cmuClock_CSEN_LF:
          EFM_ASSERT((presc <= 127U) && (presc >= 15U));
          presc = CMU_PrescToLog2(presc) - 4;
          syncReg(CMU_SYNCBUSY_LFBPRESC0);
          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK)
                           | (presc << _CMU_LFBPRESC0_CSEN_SHIFT);
          break;
#endif
        default:
          EFM_ASSERT(0);
          break;
      }
      break;
    case CMU_LFEPRESC0_REG:
      switch (clock) {
#if defined(_CMU_LFEPRESC0_RTCC_MASK)
        case cmuClock_RTCC:
          EFM_ASSERT(presc <= 0U);
          syncReg(CMU_SYNCBUSY_LFEPRESC0);
          CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
                           | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
          break;
#endif
        default:
          EFM_ASSERT(0);
          break;
      }
      break;
    case CMU_ADCASYNCDIV_REG:
      switch (clock) {
#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK)
        case cmuClock_ADC0ASYNC:
          EFM_ASSERT(presc <= 3);
          CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKDIV_MASK)
                         | (presc << _CMU_ADCCTRL_ADC0CLKDIV_SHIFT);
          break;
#endif
#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK)
        case cmuClock_ADC1ASYNC:
          EFM_ASSERT(presc <= 3);
          CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKDIV_MASK)
                         | (presc << _CMU_ADCCTRL_ADC1CLKDIV_SHIFT);
          break;
#endif
        default:
          EFM_ASSERT(0);
          break;
      }
      break;
    default:
      EFM_ASSERT(0);
      break;
  }
}
void CMU_ClockPrescSet ( CMU_Clock_TypeDef clock , CMU_ClkPresc_TypeDef presc ) { uint32_t freq ; uint32_t prescReg ; prescReg = ( clock >> CMU_PRESC_REG_POS ) & CMU_PRESC_REG_MASK ; switch ( prescReg ) { case CMU_HFPRESC_REG : EFM_ASSERT ( presc < 32U ) ; flashWaitStateMax ( ) ; setHfLeConfig ( CMU_MAX_FREQ_HFLE + 1 ) ; CMU -> HFPRESC = ( CMU -> HFPRESC & ~ _CMU_HFPRESC_PRESC_MASK ) | ( presc << _CMU_HFPRESC_PRESC_SHIFT ) ; freq = SystemCoreClockGet ( ) ; CMU_UpdateWaitStates ( freq , VSCALE_DEFAULT ) ; setHfLeConfig ( CMU_ClockFreqGet ( cmuClock_HFLE ) ) ; break ; case CMU_HFEXPPRESC_REG : EFM_ASSERT ( presc < 32U ) ; CMU -> HFEXPPRESC = ( CMU -> HFEXPPRESC & ~ _CMU_HFEXPPRESC_PRESC_MASK ) | ( presc << _CMU_HFEXPPRESC_PRESC_SHIFT ) ; break ; case CMU_HFCLKLEPRESC_REG : #if defined ( CMU_HFPRESC_HFCLKLEPRESC_DIV8 ) EFM_ASSERT ( presc < 3U ) ; #else EFM_ASSERT ( presc < 2U ) ; #endif CMU -> HFPRESC = ( CMU -> HFPRESC & ~ _CMU_HFPRESC_HFCLKLEPRESC_MASK ) | ( presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT ) ; break ; case CMU_HFPERPRESC_REG : EFM_ASSERT ( presc < 512U ) ; CMU -> HFPERPRESC = ( CMU -> HFPERPRESC & ~ _CMU_HFPERPRESC_PRESC_MASK ) | ( presc << _CMU_HFPERPRESC_PRESC_SHIFT ) ; break ; case CMU_HFCOREPRESC_REG : EFM_ASSERT ( presc < 512U ) ; flashWaitStateMax ( ) ; setHfLeConfig ( CMU_MAX_FREQ_HFLE + 1 ) ; CMU -> HFCOREPRESC = ( CMU -> HFCOREPRESC & ~ _CMU_HFCOREPRESC_PRESC_MASK ) | ( presc << _CMU_HFCOREPRESC_PRESC_SHIFT ) ; freq = SystemCoreClockGet ( ) ; CMU_UpdateWaitStates ( freq , VSCALE_DEFAULT ) ; setHfLeConfig ( CMU_ClockFreqGet ( cmuClock_HFLE ) ) ; break ; case CMU_LFAPRESC0_REG : switch ( clock ) { #if defined ( RTC_PRESENT ) case cmuClock_RTC : EFM_ASSERT ( presc <= 32768U ) ; presc = CMU_PrescToLog2 ( presc ) ; syncReg ( CMU_SYNCBUSY_LFAPRESC0 ) ; CMU -> LFAPRESC0 = ( CMU -> LFAPRESC0 & ~ _CMU_LFAPRESC0_RTC_MASK ) | ( presc << _CMU_LFAPRESC0_RTC_SHIFT ) ; break ; #endif #if defined ( RTCC_PRESENT ) case cmuClock_RTCC : #if defined ( _CMU_LFEPRESC0_RTCC_MASK ) EFM_ASSERT ( presc <= 0U ) ; syncReg ( CMU_SYNCBUSY_LFEPRESC0 ) ; CMU -> LFEPRESC0 = ( CMU -> LFEPRESC0 & ~ _CMU_LFEPRESC0_RTCC_MASK ) | ( presc << _CMU_LFEPRESC0_RTCC_SHIFT ) ; #else EFM_ASSERT ( presc <= 32768U ) ; presc = CMU_PrescToLog2 ( presc ) ; syncReg ( CMU_SYNCBUSY_LFAPRESC0 ) ; CMU -> LFAPRESC0 = ( CMU -> LFAPRESC0 & ~ _CMU_LFAPRESC0_RTCC_MASK ) | ( presc << _CMU_LFAPRESC0_RTCC_SHIFT ) ; #endif break ; #endif #if defined ( _CMU_LFAPRESC0_LETIMER0_MASK ) case cmuClock_LETIMER0 : EFM_ASSERT ( presc <= 32768U ) ; presc = CMU_PrescToLog2 ( presc ) ; syncReg ( CMU_SYNCBUSY_LFAPRESC0 ) ; CMU -> LFAPRESC0 = ( CMU -> LFAPRESC0 & ~ _CMU_LFAPRESC0_LETIMER0_MASK ) | ( presc << _CMU_LFAPRESC0_LETIMER0_SHIFT ) ; break ; #endif #if defined ( _CMU_LFAPRESC0_LESENSE_MASK ) case cmuClock_LESENSE : EFM_ASSERT ( presc <= 8 ) ; presc = CMU_PrescToLog2 ( presc ) ; syncReg ( CMU_SYNCBUSY_LFAPRESC0 ) ; CMU -> LFAPRESC0 = ( CMU -> LFAPRESC0 & ~ _CMU_LFAPRESC0_LESENSE_MASK ) | ( presc << _CMU_LFAPRESC0_LESENSE_SHIFT ) ; break ; #endif #if defined ( _CMU_LFAPRESC0_LCD_MASK ) case cmuClock_LCDpre : case cmuClock_LCD : { EFM_ASSERT ( presc <= 32768U ) ; presc = CMU_PrescToLog2 ( presc ) ; syncReg ( CMU_SYNCBUSY_LFAPRESC0 ) ; CMU -> LFAPRESC0 = ( CMU -> LFAPRESC0 & ~ _CMU_LFAPRESC0_LCD_MASK ) | ( presc << _CMU_LFAPRESC0_LCD_SHIFT ) ; } break ; #endif default : EFM_ASSERT ( 0 ) ; break ; } break ; case CMU_LFBPRESC0_REG : switch ( clock ) { #if defined ( _CMU_LFBPRESC0_LEUART0_MASK ) case cmuClock_LEUART0 : EFM_ASSERT ( presc <= 8U ) ; presc = CMU_PrescToLog2 ( presc ) ; syncReg ( CMU_SYNCBUSY_LFBPRESC0 ) ; CMU -> LFBPRESC0 = ( CMU -> LFBPRESC0 & ~ _CMU_LFBPRESC0_LEUART0_MASK ) | ( presc << _CMU_LFBPRESC0_LEUART0_SHIFT ) ; break ; #endif #if defined ( _CMU_LFBPRESC0_LEUART1_MASK ) case cmuClock_LEUART1 : EFM_ASSERT ( presc <= 8U ) ; presc = CMU_PrescToLog2 ( presc ) ; syncReg ( CMU_SYNCBUSY_LFBPRESC0 ) ; CMU -> LFBPRESC0 = ( CMU -> LFBPRESC0 & ~ _CMU_LFBPRESC0_LEUART1_MASK ) | ( presc << _CMU_LFBPRESC0_LEUART1_SHIFT ) ; break ; #endif #if defined ( _CMU_LFBPRESC0_CSEN_MASK ) case cmuClock_CSEN_LF : EFM_ASSERT ( ( presc <= 127U ) && ( presc >= 15U ) ) ; presc = CMU_PrescToLog2 ( presc ) - 4 ; syncReg ( CMU_SYNCBUSY_LFBPRESC0 ) ; CMU -> LFBPRESC0 = ( CMU -> LFBPRESC0 & ~ _CMU_LFBPRESC0_CSEN_MASK ) | ( presc << _CMU_LFBPRESC0_CSEN_SHIFT ) ; break ; #endif default : EFM_ASSERT ( 0 ) ; break ; } break ; case CMU_LFEPRESC0_REG : switch ( clock ) { #if defined ( _CMU_LFEPRESC0_RTCC_MASK ) case cmuClock_RTCC : EFM_ASSERT ( presc <= 0U ) ; syncReg ( CMU_SYNCBUSY_LFEPRESC0 ) ; CMU -> LFEPRESC0 = ( CMU -> LFEPRESC0 & ~ _CMU_LFEPRESC0_RTCC_MASK ) | ( presc << _CMU_LFEPRESC0_RTCC_SHIFT ) ; break ; #endif default : EFM_ASSERT ( 0 ) ; break ; } break ; case CMU_ADCASYNCDIV_REG : switch ( clock ) { #if defined ( _CMU_ADCCTRL_ADC0CLKDIV_MASK ) case cmuClock_ADC0ASYNC : EFM_ASSERT ( presc <= 3 ) ; CMU -> ADCCTRL = ( CMU -> ADCCTRL & ~ _CMU_ADCCTRL_ADC0CLKDIV_MASK ) | ( presc << _CMU_ADCCTRL_ADC0CLKDIV_SHIFT ) ; break ; #endif #if defined ( _CMU_ADCCTRL_ADC1CLKDIV_MASK ) case cmuClock_ADC1ASYNC : EFM_ASSERT ( presc <= 3 ) ; CMU -> ADCCTRL = ( CMU -> ADCCTRL & ~ _CMU_ADCCTRL_ADC1CLKDIV_MASK ) | ( presc << _CMU_ADCCTRL_ADC1CLKDIV_SHIFT ) ; break ; #endif default : EFM_ASSERT ( 0 ) ; break ; } break ; default : EFM_ASSERT ( 0 ) ; break ; } }
@brief
   Set clock prescaler.
@brief Set clock prescaler .
/* Get divisor reg id */ /* Configure worst case wait-states for flash and HFLE. */ /* Update CMSIS core clock variable (this function updates the global variable).
         Optimize flash and HFLE wait states. */ /* Specifies the clock divider for HFCLKLE. This clock divider must be set
       * high enough for the divided clock frequency to be at or below the max
       * frequency allowed for the HFCLKLE clock. */ /* Configure worst case wait-states for flash and HFLE. */ /* Update CMSIS core clock variable (this function updates the global variable).
         Optimize flash and HFLE wait states. */ /* Convert prescaler value to DIV exponent scale. */ /* LF register about to be modified require sync. Busy check. */ /* DIV1 is the only accepted value. */ /* LF register about to be modified require sync. Busy check.. */ /* Convert prescaler value to DIV exponent scale. */ /* LF register about to be modified require sync. Busy check. */ /* Convert prescaler value to DIV exponent scale. */ /* LF register about to be modified require sync. Busy check. */ /* Convert prescaler value to DIV exponent scale. */ /* LF register about to be modified require sync. Busy check. */ /* Convert prescaler value to DIV exponent scale. */ /* LF register about to be modified require sync. Busy check. */ /* Convert prescaler value to DIV exponent scale. */ /* LF register about to be modified require sync. Busy check. */ /* Convert prescaler value to DIV exponent scale. */ /* LF register about to be modified require sync. Busy check. */ /* Convert prescaler value to DIV exponent scale.
           * DIV16 is the lowest supported prescaler. */ /* LF register about to be modified require sync. Busy check. */ /* LF register about to be modified require sync. Busy check. */