lib/sw_apps/zynqmp_fsbl/src/xfsbl_ddr_init.c
static u32 XFsbl_DdrcCalcCommonRegVal(struct DdrcInitData *DdrDataPtr,
		XFsbl_DimmParams *PDimmPtr, u32 *DdrCfg)
{

	DdrCfg[DDR_DEVICE_CONFIG] = (PDimmPtr->DramWidth >= 4U) ? XFsbl_GetLog2(PDimmPtr->DramWidth) - 2U : 0U;

	DdrCfg[DDR_ACTIVE_RANKS] = (PDimmPtr->NumRankAddr * 2U) + 1U;

	DdrCfg[DDR_BURST_RDWR] = PDimmPtr->BurstLength / 2U;

	DdrCfg[DDR_DATA_BUS_WIDTH] = 6U - XFsbl_GetLog2(PDimmPtr->BusWidth);

	DdrCfg[DDR_GEARDOWN_MODE] = PDimmPtr->Geardown;

	if (!(PDimmPtr->Geardown == 1U)) {
		DdrCfg[DDR_EN_2T_TIMING_MODE] = PDimmPtr->En2tTimingMode;
	}

	DdrCfg[DDR_RC_DERATE_VALUE] = (u32)XFsbl_Ceil(3.75 / PDimmPtr->ClockPeriod / 2.0);

	DdrCfg[DDR_EN_DFI_DRAM_CLK_DISABLE] = PDimmPtr->ClockStopEn;

	DdrCfg[DDR_POWERDOWN_EN] = PDimmPtr->PwrDnEn;

	DdrCfg[DDR_T_DPD_X4096] = XFSBL_MIN(((u32)XFsbl_Ceil(500000.0 / (4096.0 * PDimmPtr->ClockPeriod)) + 1U), 255U);

	DdrCfg[DDR_REFRESH_MODE] = PDimmPtr->Fgrm;

	DdrCfg[DDR_T_RFC_MIN] = (u32)XFsbl_Ceil(((PDimmPtr->TRfcPs / 1000.0) / 2.0) / PDimmPtr->ClockPeriod);

	DdrCfg[DDR_DIS_SCRUB] = PDimmPtr->EccScrub;

	DdrCfg[DDR_ECC_MODE] = PDimmPtr->Ecc << 2U;

	DdrCfg[DDR_DATA_POISON_EN] = PDimmPtr->EccPoison;

	if (PDimmPtr->Parity | PDimmPtr->Crc) {
		DdrCfg[DDR_ALERT_WAIT_FOR_SW] = 0U;
		if (!PDimmPtr->NoRetry)
			DdrCfg[DDR_CRC_PARITY_RETRY_ENABLE] = 1U;
	}

	if (PDimmPtr->Crc) {
		DdrCfg[DDR_CRC_INC_DM] = 1U;
		DdrCfg[DDR_CRC_ENABLE] = 1U;
	}

	DdrCfg[DDR_PARITY_ENABLE] = PDimmPtr->Parity;

	DdrCfg[DDR_IDLE_AFTER_RESET_X32] = XFSBL_MIN(1U + ((u32)XFsbl_Ceil(1000.0 / (32.0 * PDimmPtr->ClockPeriod))), 255U);

	DdrCfg[DDR_DIMM_ADDR_MIRR_EN] = PDimmPtr->AddrMirror;

	DdrCfg[DDR_T_FAW] = (u32)XFsbl_Ceil((PDimmPtr->TFawPs / 1000.0) /
			PDimmPtr->ClockPeriod / 2.0);

	DdrCfg[DDR_T_XP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp / 2.0), 31U);

	DdrCfg[DDR_T_RC] = (u32)XFsbl_Ceil((PDimmPtr->TRcPs / 1000.0) /
			PDimmPtr->ClockPeriod / 2.0) + 1U;

	if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
		PDimmPtr->WriteLatency = PDimmPtr->WriteLatency +
			PDimmPtr->ParityLatency;
	}
	PDimmPtr->WriteLatency += PDimmPtr->RDimm;
	DdrCfg[DDR_WRITE_LATENCY] = (u32)XFsbl_Ceil(PDimmPtr->WriteLatency / 2.0);

	if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
		PDimmPtr->ReadLatency = PDimmPtr->ReadLatency + PDimmPtr->ParityLatency;
	}
	PDimmPtr->ReadLatency += PDimmPtr->RDimm;
	DdrCfg[DDR_READ_LATENCY] = (u32)XFsbl_Ceil(PDimmPtr->ReadLatency / 2.0);

	DdrCfg[DDR_T_RCD] = (u32)XFsbl_Ceil(((PDimmPtr->TRcdPs / 1000.0) -
				PDimmPtr->AdditiveLatency) / 2.0) + 1U;

	DdrCfg[DDR_T_CCD] = (u32)XFsbl_Ceil((PDimmPtr->TCcdlPs / 1000.0) / 2.0);

	DdrCfg[DDR_T_XS_FAST_X32] = (u32)XFsbl_Ceil(((PDimmPtr->TRfc4Ps /
					1000.0) + 10.0) / PDimmPtr->ClockPeriod / 32.0 / 2.0) + 1U;

	DdrCfg[DDR_T_XS_ABORT_X32] = DdrCfg[DDR_T_XS_FAST_X32];

	DdrCfg[DDR_DDR4_WR_PREAMBLE] = PDimmPtr->WrPreamble;

	DdrCfg[DDR_T_MRD_PDA] = (u32)XFsbl_Ceil(XFSBL_MAX(16.0, 10.0 / PDimmPtr->ClockPeriod) / 2.0);

	if (!PDimmPtr->DisDfiLpSr) {
		DdrCfg[DDR_DFI_LP_EN_SR] = 0x1U;
	}

	if (!PDimmPtr->DisDfiLpPd) {
		DdrCfg[DDR_DFI_LP_EN_PD] = 0x1U;
	}

	if (!PDimmPtr->DisDfiLpMpsm) {
		DdrCfg[DDR_DFI_LP_EN_MPSM] = 0x1U;
	}

	DdrCfg[DDR_DIS_AUTO_CTRLUPD] = PDimmPtr->Slowboot;

	if (PDimmPtr->WrDrift) {
		DdrCfg[DDR_DFI_T_CTRLUP_MAX] = 0x3FFU;
	}

	DdrCfg[DDR_PHY_DBI_MODE] = !!PDimmPtr->PhyDbiMode;

	/* Calculate Address Map for the DDR */
	XFsbl_DdrCalcAddrMap(DdrDataPtr);

	if (PDimmPtr->LprNumEntries != 0U) {
		DdrCfg[DDR_LPR_NUM_ENTRIES] = PDimmPtr->LprNumEntries;
	}

	DdrCfg[DDR_DQ_NIBBLE_MAP_12_15] = PDimmPtr->Dqmap1215;
	DdrCfg[DDR_DQ_NIBBLE_MAP_8_11] = PDimmPtr->Dqmap811;
	DdrCfg[DDR_DQ_NIBBLE_MAP_4_7] = PDimmPtr->Dqmap47;
	DdrCfg[DDR_DQ_NIBBLE_MAP_0_3] = PDimmPtr->Dqmap03;

	DdrCfg[DDR_DQ_NIBBLE_MAP_28_31] = PDimmPtr->Dqmap2831;
	DdrCfg[DDR_DQ_NIBBLE_MAP_24_27] = PDimmPtr->Dqmap2427;
	DdrCfg[DDR_DQ_NIBBLE_MAP_20_23] = PDimmPtr->Dqmap2023;
	DdrCfg[DDR_DQ_NIBBLE_MAP_16_19] = PDimmPtr->Dqmap1619;

	DdrCfg[DDR_DQ_NIBBLE_MAP_44_47] = PDimmPtr->Dqmap4447;
	DdrCfg[DDR_DQ_NIBBLE_MAP_40_43] = PDimmPtr->Dqmap4043;
	DdrCfg[DDR_DQ_NIBBLE_MAP_36_39] = PDimmPtr->Dqmap3639;
	DdrCfg[DDR_DQ_NIBBLE_MAP_32_35] = PDimmPtr->Dqmap3235;

	DdrCfg[DDR_DQ_NIBBLE_MAP_60_63] = PDimmPtr->Dqmap6063;
	DdrCfg[DDR_DQ_NIBBLE_MAP_56_59] = PDimmPtr->Dqmap5659;
	DdrCfg[DDR_DQ_NIBBLE_MAP_52_55] = PDimmPtr->Dqmap5255;
	DdrCfg[DDR_DQ_NIBBLE_MAP_48_51] = PDimmPtr->Dqmap4851;

	DdrCfg[DDR_DQ_NIBBLE_MAP_CB_4_7] = PDimmPtr->Dqmap6871;
	DdrCfg[DDR_DQ_NIBBLE_MAP_CB_0_3] = PDimmPtr->Dqmap6467;

	return XFSBL_SUCCESS;
}
/*****************************************************************************/
/**
 * This function calculates the DDRC register values common to all DDR types
 *
 * @param	DdrDataPtr is pointer to DDR Initialization Data Structure
 * @param	PDimmPtr is pointer to DIMM parameters Data Structure
 * @param	DdrCfg is the array to store register field values
 *
 * @return	None
 *
 *****************************************************************************/
This function calculates the DDRC register values common to all DDR types
@param       DdrDataPtr is pointer to DDR Initialization Data Structure
@param       PDimmPtr is pointer to DIMM parameters Data Structure
@param       DdrCfg is the array to store register field values

@return      None
This function calculates the DDRC register values common to all DDR types @param DdrDataPtr is pointer to DDR Initialization Data Structure @param PDimmPtr is pointer to DIMM parameters Data Structure @param DdrCfg is the array to store register field values @return None
static u32 XFsbl_DdrcCalcCommonRegVal(struct DdrcInitData *DdrDataPtr,
		XFsbl_DimmParams *PDimmPtr, u32 *DdrCfg)
{
	DdrCfg[DDR_DEVICE_CONFIG] = (PDimmPtr->DramWidth >= 4U) ? XFsbl_GetLog2(PDimmPtr->DramWidth) - 2U : 0U;
	DdrCfg[DDR_ACTIVE_RANKS] = (PDimmPtr->NumRankAddr * 2U) + 1U;
	DdrCfg[DDR_BURST_RDWR] = PDimmPtr->BurstLength / 2U;
	DdrCfg[DDR_DATA_BUS_WIDTH] = 6U - XFsbl_GetLog2(PDimmPtr->BusWidth);
	DdrCfg[DDR_GEARDOWN_MODE] = PDimmPtr->Geardown;
	if (!(PDimmPtr->Geardown == 1U)) {
		DdrCfg[DDR_EN_2T_TIMING_MODE] = PDimmPtr->En2tTimingMode;
	}
	DdrCfg[DDR_RC_DERATE_VALUE] = (u32)XFsbl_Ceil(3.75 / PDimmPtr->ClockPeriod / 2.0);
	DdrCfg[DDR_EN_DFI_DRAM_CLK_DISABLE] = PDimmPtr->ClockStopEn;
	DdrCfg[DDR_POWERDOWN_EN] = PDimmPtr->PwrDnEn;
	DdrCfg[DDR_T_DPD_X4096] = XFSBL_MIN(((u32)XFsbl_Ceil(500000.0 / (4096.0 * PDimmPtr->ClockPeriod)) + 1U), 255U);
	DdrCfg[DDR_REFRESH_MODE] = PDimmPtr->Fgrm;
	DdrCfg[DDR_T_RFC_MIN] = (u32)XFsbl_Ceil(((PDimmPtr->TRfcPs / 1000.0) / 2.0) / PDimmPtr->ClockPeriod);
	DdrCfg[DDR_DIS_SCRUB] = PDimmPtr->EccScrub;
	DdrCfg[DDR_ECC_MODE] = PDimmPtr->Ecc << 2U;
	DdrCfg[DDR_DATA_POISON_EN] = PDimmPtr->EccPoison;
	if (PDimmPtr->Parity | PDimmPtr->Crc) {
		DdrCfg[DDR_ALERT_WAIT_FOR_SW] = 0U;
		if (!PDimmPtr->NoRetry)
			DdrCfg[DDR_CRC_PARITY_RETRY_ENABLE] = 1U;
	}
	if (PDimmPtr->Crc) {
		DdrCfg[DDR_CRC_INC_DM] = 1U;
		DdrCfg[DDR_CRC_ENABLE] = 1U;
	}
	DdrCfg[DDR_PARITY_ENABLE] = PDimmPtr->Parity;
	DdrCfg[DDR_IDLE_AFTER_RESET_X32] = XFSBL_MIN(1U + ((u32)XFsbl_Ceil(1000.0 / (32.0 * PDimmPtr->ClockPeriod))), 255U);
	DdrCfg[DDR_DIMM_ADDR_MIRR_EN] = PDimmPtr->AddrMirror;
	DdrCfg[DDR_T_FAW] = (u32)XFsbl_Ceil((PDimmPtr->TFawPs / 1000.0) /
			PDimmPtr->ClockPeriod / 2.0);
	DdrCfg[DDR_T_XP] = (u32)XFSBL_MIN(XFsbl_Ceil(PDimmPtr->TXp / 2.0), 31U);
	DdrCfg[DDR_T_RC] = (u32)XFsbl_Ceil((PDimmPtr->TRcPs / 1000.0) /
			PDimmPtr->ClockPeriod / 2.0) + 1U;
	if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
		PDimmPtr->WriteLatency = PDimmPtr->WriteLatency +
			PDimmPtr->ParityLatency;
	}
	PDimmPtr->WriteLatency += PDimmPtr->RDimm;
	DdrCfg[DDR_WRITE_LATENCY] = (u32)XFsbl_Ceil(PDimmPtr->WriteLatency / 2.0);
	if (PDimmPtr->MemType == SPD_MEMTYPE_DDR4) {
		PDimmPtr->ReadLatency = PDimmPtr->ReadLatency + PDimmPtr->ParityLatency;
	}
	PDimmPtr->ReadLatency += PDimmPtr->RDimm;
	DdrCfg[DDR_READ_LATENCY] = (u32)XFsbl_Ceil(PDimmPtr->ReadLatency / 2.0);
	DdrCfg[DDR_T_RCD] = (u32)XFsbl_Ceil(((PDimmPtr->TRcdPs / 1000.0) -
				PDimmPtr->AdditiveLatency) / 2.0) + 1U;
	DdrCfg[DDR_T_CCD] = (u32)XFsbl_Ceil((PDimmPtr->TCcdlPs / 1000.0) / 2.0);
	DdrCfg[DDR_T_XS_FAST_X32] = (u32)XFsbl_Ceil(((PDimmPtr->TRfc4Ps /
					1000.0) + 10.0) / PDimmPtr->ClockPeriod / 32.0 / 2.0) + 1U;
	DdrCfg[DDR_T_XS_ABORT_X32] = DdrCfg[DDR_T_XS_FAST_X32];
	DdrCfg[DDR_DDR4_WR_PREAMBLE] = PDimmPtr->WrPreamble;
	DdrCfg[DDR_T_MRD_PDA] = (u32)XFsbl_Ceil(XFSBL_MAX(16.0, 10.0 / PDimmPtr->ClockPeriod) / 2.0);
	if (!PDimmPtr->DisDfiLpSr) {
		DdrCfg[DDR_DFI_LP_EN_SR] = 0x1U;
	}
	if (!PDimmPtr->DisDfiLpPd) {
		DdrCfg[DDR_DFI_LP_EN_PD] = 0x1U;
	}
	if (!PDimmPtr->DisDfiLpMpsm) {
		DdrCfg[DDR_DFI_LP_EN_MPSM] = 0x1U;
	}
	DdrCfg[DDR_DIS_AUTO_CTRLUPD] = PDimmPtr->Slowboot;
	if (PDimmPtr->WrDrift) {
		DdrCfg[DDR_DFI_T_CTRLUP_MAX] = 0x3FFU;
	}
	DdrCfg[DDR_PHY_DBI_MODE] = !!PDimmPtr->PhyDbiMode;
	XFsbl_DdrCalcAddrMap(DdrDataPtr);
	if (PDimmPtr->LprNumEntries != 0U) {
		DdrCfg[DDR_LPR_NUM_ENTRIES] = PDimmPtr->LprNumEntries;
	}
	DdrCfg[DDR_DQ_NIBBLE_MAP_12_15] = PDimmPtr->Dqmap1215;
	DdrCfg[DDR_DQ_NIBBLE_MAP_8_11] = PDimmPtr->Dqmap811;
	DdrCfg[DDR_DQ_NIBBLE_MAP_4_7] = PDimmPtr->Dqmap47;
	DdrCfg[DDR_DQ_NIBBLE_MAP_0_3] = PDimmPtr->Dqmap03;
	DdrCfg[DDR_DQ_NIBBLE_MAP_28_31] = PDimmPtr->Dqmap2831;
	DdrCfg[DDR_DQ_NIBBLE_MAP_24_27] = PDimmPtr->Dqmap2427;
	DdrCfg[DDR_DQ_NIBBLE_MAP_20_23] = PDimmPtr->Dqmap2023;
	DdrCfg[DDR_DQ_NIBBLE_MAP_16_19] = PDimmPtr->Dqmap1619;
	DdrCfg[DDR_DQ_NIBBLE_MAP_44_47] = PDimmPtr->Dqmap4447;
	DdrCfg[DDR_DQ_NIBBLE_MAP_40_43] = PDimmPtr->Dqmap4043;
	DdrCfg[DDR_DQ_NIBBLE_MAP_36_39] = PDimmPtr->Dqmap3639;
	DdrCfg[DDR_DQ_NIBBLE_MAP_32_35] = PDimmPtr->Dqmap3235;
	DdrCfg[DDR_DQ_NIBBLE_MAP_60_63] = PDimmPtr->Dqmap6063;
	DdrCfg[DDR_DQ_NIBBLE_MAP_56_59] = PDimmPtr->Dqmap5659;
	DdrCfg[DDR_DQ_NIBBLE_MAP_52_55] = PDimmPtr->Dqmap5255;
	DdrCfg[DDR_DQ_NIBBLE_MAP_48_51] = PDimmPtr->Dqmap4851;
	DdrCfg[DDR_DQ_NIBBLE_MAP_CB_4_7] = PDimmPtr->Dqmap6871;
	DdrCfg[DDR_DQ_NIBBLE_MAP_CB_0_3] = PDimmPtr->Dqmap6467;
	return XFSBL_SUCCESS;
}
static u32 XFsbl_DdrcCalcCommonRegVal ( struct DdrcInitData * DdrDataPtr , XFsbl_DimmParams * PDimmPtr , u32 * DdrCfg ) { DdrCfg [ DDR_DEVICE_CONFIG ] = ( PDimmPtr -> DramWidth >= 4U ) ? XFsbl_GetLog2 ( PDimmPtr -> DramWidth ) - 2U : 0U ; DdrCfg [ DDR_ACTIVE_RANKS ] = ( PDimmPtr -> NumRankAddr * 2U ) + 1U ; DdrCfg [ DDR_BURST_RDWR ] = PDimmPtr -> BurstLength / 2U ; DdrCfg [ DDR_DATA_BUS_WIDTH ] = 6U - XFsbl_GetLog2 ( PDimmPtr -> BusWidth ) ; DdrCfg [ DDR_GEARDOWN_MODE ] = PDimmPtr -> Geardown ; if ( ! ( PDimmPtr -> Geardown == 1U ) ) { DdrCfg [ DDR_EN_2T_TIMING_MODE ] = PDimmPtr -> En2tTimingMode ; } DdrCfg [ DDR_RC_DERATE_VALUE ] = ( u32 ) XFsbl_Ceil ( 3.75 / PDimmPtr -> ClockPeriod / 2.0 ) ; DdrCfg [ DDR_EN_DFI_DRAM_CLK_DISABLE ] = PDimmPtr -> ClockStopEn ; DdrCfg [ DDR_POWERDOWN_EN ] = PDimmPtr -> PwrDnEn ; DdrCfg [ DDR_T_DPD_X4096 ] = XFSBL_MIN ( ( ( u32 ) XFsbl_Ceil ( 500000.0 / ( 4096.0 * PDimmPtr -> ClockPeriod ) ) + 1U ) , 255U ) ; DdrCfg [ DDR_REFRESH_MODE ] = PDimmPtr -> Fgrm ; DdrCfg [ DDR_T_RFC_MIN ] = ( u32 ) XFsbl_Ceil ( ( ( PDimmPtr -> TRfcPs / 1000.0 ) / 2.0 ) / PDimmPtr -> ClockPeriod ) ; DdrCfg [ DDR_DIS_SCRUB ] = PDimmPtr -> EccScrub ; DdrCfg [ DDR_ECC_MODE ] = PDimmPtr -> Ecc << 2U ; DdrCfg [ DDR_DATA_POISON_EN ] = PDimmPtr -> EccPoison ; if ( PDimmPtr -> Parity | PDimmPtr -> Crc ) { DdrCfg [ DDR_ALERT_WAIT_FOR_SW ] = 0U ; if ( ! PDimmPtr -> NoRetry ) DdrCfg [ DDR_CRC_PARITY_RETRY_ENABLE ] = 1U ; } if ( PDimmPtr -> Crc ) { DdrCfg [ DDR_CRC_INC_DM ] = 1U ; DdrCfg [ DDR_CRC_ENABLE ] = 1U ; } DdrCfg [ DDR_PARITY_ENABLE ] = PDimmPtr -> Parity ; DdrCfg [ DDR_IDLE_AFTER_RESET_X32 ] = XFSBL_MIN ( 1U + ( ( u32 ) XFsbl_Ceil ( 1000.0 / ( 32.0 * PDimmPtr -> ClockPeriod ) ) ) , 255U ) ; DdrCfg [ DDR_DIMM_ADDR_MIRR_EN ] = PDimmPtr -> AddrMirror ; DdrCfg [ DDR_T_FAW ] = ( u32 ) XFsbl_Ceil ( ( PDimmPtr -> TFawPs / 1000.0 ) / PDimmPtr -> ClockPeriod / 2.0 ) ; DdrCfg [ DDR_T_XP ] = ( u32 ) XFSBL_MIN ( XFsbl_Ceil ( PDimmPtr -> TXp / 2.0 ) , 31U ) ; DdrCfg [ DDR_T_RC ] = ( u32 ) XFsbl_Ceil ( ( PDimmPtr -> TRcPs / 1000.0 ) / PDimmPtr -> ClockPeriod / 2.0 ) + 1U ; if ( PDimmPtr -> MemType == SPD_MEMTYPE_DDR4 ) { PDimmPtr -> WriteLatency = PDimmPtr -> WriteLatency + PDimmPtr -> ParityLatency ; } PDimmPtr -> WriteLatency += PDimmPtr -> RDimm ; DdrCfg [ DDR_WRITE_LATENCY ] = ( u32 ) XFsbl_Ceil ( PDimmPtr -> WriteLatency / 2.0 ) ; if ( PDimmPtr -> MemType == SPD_MEMTYPE_DDR4 ) { PDimmPtr -> ReadLatency = PDimmPtr -> ReadLatency + PDimmPtr -> ParityLatency ; } PDimmPtr -> ReadLatency += PDimmPtr -> RDimm ; DdrCfg [ DDR_READ_LATENCY ] = ( u32 ) XFsbl_Ceil ( PDimmPtr -> ReadLatency / 2.0 ) ; DdrCfg [ DDR_T_RCD ] = ( u32 ) XFsbl_Ceil ( ( ( PDimmPtr -> TRcdPs / 1000.0 ) - PDimmPtr -> AdditiveLatency ) / 2.0 ) + 1U ; DdrCfg [ DDR_T_CCD ] = ( u32 ) XFsbl_Ceil ( ( PDimmPtr -> TCcdlPs / 1000.0 ) / 2.0 ) ; DdrCfg [ DDR_T_XS_FAST_X32 ] = ( u32 ) XFsbl_Ceil ( ( ( PDimmPtr -> TRfc4Ps / 1000.0 ) + 10.0 ) / PDimmPtr -> ClockPeriod / 32.0 / 2.0 ) + 1U ; DdrCfg [ DDR_T_XS_ABORT_X32 ] = DdrCfg [ DDR_T_XS_FAST_X32 ] ; DdrCfg [ DDR_DDR4_WR_PREAMBLE ] = PDimmPtr -> WrPreamble ; DdrCfg [ DDR_T_MRD_PDA ] = ( u32 ) XFsbl_Ceil ( XFSBL_MAX ( 16.0 , 10.0 / PDimmPtr -> ClockPeriod ) / 2.0 ) ; if ( ! PDimmPtr -> DisDfiLpSr ) { DdrCfg [ DDR_DFI_LP_EN_SR ] = 0x1U ; } if ( ! PDimmPtr -> DisDfiLpPd ) { DdrCfg [ DDR_DFI_LP_EN_PD ] = 0x1U ; } if ( ! PDimmPtr -> DisDfiLpMpsm ) { DdrCfg [ DDR_DFI_LP_EN_MPSM ] = 0x1U ; } DdrCfg [ DDR_DIS_AUTO_CTRLUPD ] = PDimmPtr -> Slowboot ; if ( PDimmPtr -> WrDrift ) { DdrCfg [ DDR_DFI_T_CTRLUP_MAX ] = 0x3FFU ; } DdrCfg [ DDR_PHY_DBI_MODE ] = ! ! PDimmPtr -> PhyDbiMode ; XFsbl_DdrCalcAddrMap ( DdrDataPtr ) ; if ( PDimmPtr -> LprNumEntries != 0U ) { DdrCfg [ DDR_LPR_NUM_ENTRIES ] = PDimmPtr -> LprNumEntries ; } DdrCfg [ DDR_DQ_NIBBLE_MAP_12_15 ] = PDimmPtr -> Dqmap1215 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_8_11 ] = PDimmPtr -> Dqmap811 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_4_7 ] = PDimmPtr -> Dqmap47 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_0_3 ] = PDimmPtr -> Dqmap03 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_28_31 ] = PDimmPtr -> Dqmap2831 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_24_27 ] = PDimmPtr -> Dqmap2427 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_20_23 ] = PDimmPtr -> Dqmap2023 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_16_19 ] = PDimmPtr -> Dqmap1619 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_44_47 ] = PDimmPtr -> Dqmap4447 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_40_43 ] = PDimmPtr -> Dqmap4043 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_36_39 ] = PDimmPtr -> Dqmap3639 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_32_35 ] = PDimmPtr -> Dqmap3235 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_60_63 ] = PDimmPtr -> Dqmap6063 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_56_59 ] = PDimmPtr -> Dqmap5659 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_52_55 ] = PDimmPtr -> Dqmap5255 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_48_51 ] = PDimmPtr -> Dqmap4851 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_CB_4_7 ] = PDimmPtr -> Dqmap6871 ; DdrCfg [ DDR_DQ_NIBBLE_MAP_CB_0_3 ] = PDimmPtr -> Dqmap6467 ; return XFSBL_SUCCESS ; }
This function calculates the DDRC register values common to all DDR types
 @param       DdrDataPtr is pointer to DDR Initialization Data Structure
 @param       PDimmPtr is pointer to DIMM parameters Data Structure
 @param       DdrCfg is the array to store register field values
This function calculates the DDRC register values common to all DDR types @param DdrDataPtr is pointer to DDR Initialization Data Structure @param PDimmPtr is pointer to DIMM parameters Data Structure @param DdrCfg is the array to store register field values
/* Calculate Address Map for the DDR */