src/dpdk/drivers/event/dlb/pf/base/dlb_osdep.h
static inline void os_fence_hcw(struct dlb_hw *hw, u64 *pp_addr)
{
	RTE_SET_USED(hw);

	/* To ensure outstanding HCWs reach the device, read the PP address. IA
	 * memory ordering prevents reads from passing older writes, and the
	 * mfence also ensures this.
	 */
	rte_mb();

	*(volatile u64 *)pp_addr;
}
/**
 * os_fence_hcw() - fence an HCW to ensure it arrives at the device
 * @hw: dlb_hw handle for a particular device.
 * @pp_addr: producer port address
 */
fence an HCW to ensure it arrives at the device
@hw: dlb_hw handle for a particular device.
@pp_addr: producer port address
fence an HCW to ensure it arrives at the device @hw : dlb_hw handle for a particular device . @pp_addr : producer port address
static inline void os_fence_hcw(struct dlb_hw *hw, u64 *pp_addr)
{
	RTE_SET_USED(hw);
	rte_mb();
	*(volatile u64 *)pp_addr;
}
static inline void os_fence_hcw ( struct dlb_hw * hw , u64 * pp_addr ) { RTE_SET_USED ( hw ) ; rte_mb ( ) ; * ( volatile u64 * ) pp_addr ; }
os_fence_hcw() - fence an HCW to ensure it arrives at the device
 @hw: dlb_hw handle for a particular device.
os_fence_hcw () - fence an HCW to ensure it arrives at the device @hw : dlb_hw handle for a particular device .
/* To ensure outstanding HCWs reach the device, read the PP address. IA
	 * memory ordering prevents reads from passing older writes, and the
	 * mfence also ensures this.
	 */