XilinxProcessorIPLib/drivers/vphy/src/xvphy.c
void XVphy_MmcmPowerDown(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir,
		u8 Hold)
{
	u32 RegOffsetCtrl;
	u32 RegVal;

	/* Suppress Warning Messages */
	QuadId = QuadId;

	if (Dir == XVPHY_DIR_TX) {
		RegOffsetCtrl = XVPHY_MMCM_TXUSRCLK_CTRL_REG;
	}
	else {
		RegOffsetCtrl = XVPHY_MMCM_RXUSRCLK_CTRL_REG;
	}

	/* Power down. */
	RegVal = XVphy_ReadReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl);
	RegVal |= XVPHY_MMCM_USRCLK_CTRL_PWRDWN_MASK;
	XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl, RegVal);

	if (!Hold) {
		/* Power up. */
		RegVal &= ~XVPHY_MMCM_USRCLK_CTRL_PWRDWN_MASK;
		XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl,
									RegVal);
	}
}
/*****************************************************************************/
/**
* This function will power down the mixed-mode clock manager (MMCM) core.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	Dir is an indicator for TX or RX.
* @param	Hold is an indicator whether to "hold" the power down if set
*		to 1. If set to 0: power down, then power back up.
*
* @return
*		- XST_SUCCESS.
*
* @note		None.
*
******************************************************************************/
This function will power down the mixed-mode clock manager (MMCM) core.
This function will power down the mixed - mode clock manager ( MMCM ) core .
void XVphy_MmcmPowerDown(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir,
		u8 Hold)
{
	u32 RegOffsetCtrl;
	u32 RegVal;
	QuadId = QuadId;
	if (Dir == XVPHY_DIR_TX) {
		RegOffsetCtrl = XVPHY_MMCM_TXUSRCLK_CTRL_REG;
	}
	else {
		RegOffsetCtrl = XVPHY_MMCM_RXUSRCLK_CTRL_REG;
	}
	RegVal = XVphy_ReadReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl);
	RegVal |= XVPHY_MMCM_USRCLK_CTRL_PWRDWN_MASK;
	XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl, RegVal);
	if (!Hold) {
		RegVal &= ~XVPHY_MMCM_USRCLK_CTRL_PWRDWN_MASK;
		XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl,
									RegVal);
	}
}
void XVphy_MmcmPowerDown ( XVphy * InstancePtr , u8 QuadId , XVphy_DirectionType Dir , u8 Hold ) { u32 RegOffsetCtrl ; u32 RegVal ; QuadId = QuadId ; if ( Dir == XVPHY_DIR_TX ) { RegOffsetCtrl = XVPHY_MMCM_TXUSRCLK_CTRL_REG ; } else { RegOffsetCtrl = XVPHY_MMCM_RXUSRCLK_CTRL_REG ; } RegVal = XVphy_ReadReg ( InstancePtr -> Config . BaseAddr , RegOffsetCtrl ) ; RegVal |= XVPHY_MMCM_USRCLK_CTRL_PWRDWN_MASK ; XVphy_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffsetCtrl , RegVal ) ; if ( ! Hold ) { RegVal &= ~ XVPHY_MMCM_USRCLK_CTRL_PWRDWN_MASK ; XVphy_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffsetCtrl , RegVal ) ; } }
This function will power down the mixed-mode clock manager (MMCM) core.
This function will power down the mixed - mode clock manager ( MMCM ) core .
/* Suppress Warning Messages */ /* Power down. */ /* Power up. */