XilinxProcessorIPLib/drivers/dp12txss/src/xdptxss_dbg.c
void XDpTxSs_ReportSinkCapInfo(XDpTxSs *InstancePtr)
{
	/* Verify argument. */
	Xil_AssertVoid(InstancePtr != NULL);

	u8 *Dpcd = InstancePtr->DpPtr->TxInstance.RxConfig.DpcdRxCapsField;

	u8 DpcdRevMajor = (Dpcd[XDP_DPCD_REV] &
				XDP_DPCD_REV_MJR_MASK) >>
					XDP_DPCD_REV_MJR_SHIFT;
	u8 DpcdRevMinor = Dpcd[XDP_DPCD_REV] & XDP_DPCD_REV_MNR_MASK;
	u8 MaxLinkRate = Dpcd[XDP_DPCD_MAX_LINK_RATE];
	u8 MaxLaneCount = Dpcd[XDP_DPCD_MAX_LANE_COUNT] &
				XDP_DPCD_MAX_LANE_COUNT_MASK;
	u8 Tps3Support = Dpcd[XDP_DPCD_MAX_LANE_COUNT] &
				XDP_DPCD_TPS3_SUPPORT_MASK;
	u8 EnhancedFrameSupport = Dpcd[XDP_DPCD_MAX_LANE_COUNT] &
				XDP_DPCD_ENHANCED_FRAME_SUPPORT_MASK;
	u8 MaxDownspreadSupport = Dpcd[XDP_DPCD_MAX_DOWNSPREAD] &
				XDP_DPCD_MAX_DOWNSPREAD_MASK;
	u8 NoAuxHandshakeRequired = Dpcd[XDP_DPCD_MAX_DOWNSPREAD] &
				XDP_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK;
	u8 NumRxPorts = (Dpcd[XDP_DPCD_NORP_PWR_V_CAP] & (0x01)) + 1;
	u8 PwrDpCap5V = Dpcd[XDP_DPCD_NORP_PWR_V_CAP] & (0x01);
	u8 PwrDpCap12V = Dpcd[XDP_DPCD_NORP_PWR_V_CAP] & (0x20);
	u8 PwrDpCap18V = Dpcd[XDP_DPCD_NORP_PWR_V_CAP] & (0x40);
	u8 DownstreamPortPresent = Dpcd[XDP_DPCD_DOWNSP_PRESENT] & (0x80);
	u8 DownPortType = (Dpcd[XDP_DPCD_DOWNSP_PRESENT] &
				XDP_DPCD_DOWNSP_TYPE_MASK) >>
					XDP_DPCD_DOWNSP_TYPE_SHIFT;
	u8 FormatConversionBlockPresent = Dpcd[XDP_DPCD_DOWNSP_PRESENT] &
					XDP_DPCD_DOWNSP_FORMAT_CONV_MASK;
	u8 DetailedCapInfoAvailable = Dpcd[XDP_DPCD_DOWNSP_PRESENT] &
					XDP_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK;
	u8 MainLinkAnsi8b10bCodingSupport = Dpcd[XDP_DPCD_ML_CH_CODING_CAP] &
						XDP_DPCD_ML_CH_CODING_MASK;
	u8 DownstreamPortCount = Dpcd[XDP_DPCD_DOWNSP_COUNT_MSA_OUI] &
					XDP_DPCD_DOWNSP_COUNT_MASK;
	u8 MsaTimingParIgnored = Dpcd[XDP_DPCD_DOWNSP_COUNT_MSA_OUI] &
					XDP_DPCD_MSA_TIMING_PAR_IGNORED_MASK;
	u8 OuiSupported = Dpcd[XDP_DPCD_DOWNSP_COUNT_MSA_OUI] &
				XDP_DPCD_OUI_SUPPORT_MASK;
	u8 RxPort0LocalEdidPresent = Dpcd[XDP_DPCD_RX_PORT0_CAP_0] &
			XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK;
	u8 RxPort0AssocPrecedePort = Dpcd[XDP_DPCD_RX_PORT0_CAP_0] &
			XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK;
	u8 RxPort0BufSizeBpl = (Dpcd[XDP_DPCD_RX_PORT0_CAP_1] + 1) * 32;
	u8 RxPort1LocalEdidPresent = Dpcd[XDP_DPCD_RX_PORT1_CAP_0] &
			XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK;
	u8 RxPort1AssocPrecedePort = Dpcd[XDP_DPCD_RX_PORT1_CAP_0] &
			XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK;
	u8 RxPort1BufSizeBpl = (Dpcd[XDP_DPCD_RX_PORT1_CAP_1] + 1) * 32;
	u8 IicSpeed = Dpcd[XDP_DPCD_I2C_SPEED_CTL_CAP];
	u8 EdpAltScramblerResetCap = Dpcd[XDP_DPCD_EDP_CFG_CAP] &(0x1);
	u8 EdpFramingChangeCap = Dpcd[XDP_DPCD_EDP_CFG_CAP] & (0x2);
	u8 TraingAuxReadInt = Dpcd[XDP_DPCD_TRAIN_AUX_RD_INTERVAL];
	u8 AdapterForceLoadSenseCap = Dpcd[XDP_DPCD_ADAPTER_CAP] & (0x01);
	u8 AdapterAltI2CPatternCap = Dpcd[XDP_DPCD_ADAPTER_CAP] & (0x02);
	u8 FauxCap = Dpcd[XDP_DPCD_FAUX_CAP] & XDP_DPCD_FAUX_CAP_MASK;
	u8 MstmCap = Dpcd[XDP_DPCD_MSTM_CAP] & XDP_DPCD_MST_CAP_MASK;
	u8 NumAudioEps = Dpcd[XDP_DPCD_NUM_AUDIO_EPS];

	xil_printf("RX capabilities:\n\r"
		"\tDPCD rev major (0x00000): %d\n\r"
		"\tDPCD rev minor (0x00000): %d\n\r"
		"\tMax link rate (0x00001): %s\n\r"
		"\tMax lane count (0x00002): %d\n\r"
		"\tTPS3 supported (0x00002): %s\n\r"
		"\tEnhanced frame support? (0x00002) %s\n\r"
		"\tMax downspread support? (0x00003) %s\n\r"
		"\tNo AUX handshake required? (0x00003)%s\n\r"
		"\t# of receiver ports (0x00004): %d\n\r"
		"\tDP power 5v cap? (0x00004) %s\n\r"
		"\tDP power 12v cap? (0x00004) %s\n\r"
		"\tDP power 18v cap? (0x00004) %s\n\r"
		"\tDownstream ports present? (0x00005) %s\n\r"
		"\tDownstreamport0 type (0x00005): %s\n\r"
		"\tFormat conversion block present (0x00005): %s\n\r"
		"\tDetailed cap info available? (0x00005) %s\n\r"
		"\tMain link ANSI 8b/10b channel coding support? (0x00006) "
			"%s\n\r"
		"\tDownstream port count (0x00007): %d\n\r"
		"\tMSA timing parameters ignored? (0x00007) %s\n\r"
		"\tOUI supported? (0x00007) %s\n\r"
		"\tReceive port0 local edid present (0x00008) %s\n\r"
		"\tReceive port0 associated to preceding port? (0x00008) "
			"%s\n\r"
		"\tReceive port0 buffer size (0x00009): %d bytes per lane\n\r"
		"\tReceive port1 local edid present (0x0000A) %s\n\r"
		"\tReceive port1 associated to preceding port? (0x0000A) "
			"%s\n\r"
		"\tReceive port1 buffer size (0x0000B): %d bytes per lane\n\r"
		"\tI2C speed (0x0000C): %s\n\r"
		"\tEDP alt scrambler reset cap? (0x0000D) %s\n\r"
		"\tEDP framing change cap? (0x0000D) %s\n\r"
		"\tTraining AUX read interval (0x0000E): %s\n\r"
		"\tAdapter force load sense cap? (0x0000F) %s\n\r"
		"\tAdapter alt i2c pattern cap? (0x0000F) %s\n\r"
		"\tFaux cap?  (0x00020) %s\n\r"
		"\tMSTM cap? (0x00021) %s\n\r"
		"\t# of audio eps (0x00022) : %d\n\r",
		DpcdRevMajor,
		DpcdRevMinor,
		(MaxLinkRate == XDP_DPCD_LINK_BW_SET_162GBPS) ? "1.62Gbps" :
		(MaxLinkRate == XDP_DPCD_LINK_BW_SET_270GBPS) ? "2.70Gbps" :
		(MaxLinkRate == XDP_DPCD_LINK_BW_SET_540GBPS) ? "5.40Gbps" :
		"Unknown link rate",
		MaxLaneCount,
		Tps3Support ? "Y" : "N",
		EnhancedFrameSupport ? "Y" : "N",
		MaxDownspreadSupport ? "Y" : "N",
		NoAuxHandshakeRequired ? "Y" : "N",
		NumRxPorts,
		PwrDpCap5V ? "Y" : "N",
		PwrDpCap12V ? "Y" : "N",
		PwrDpCap18V ? "Y" : "N",
		DownstreamPortPresent ? "Y" : "N",
		(DownPortType == XDP_DPCD_DOWNSP_TYPE_DP) ?
		"DisplayPort" :
		(DownPortType == XDP_DPCD_DOWNSP_TYPE_AVGA_ADVII) ?
			"Analog VGA or analog video over DVI-I" :
		(DownPortType == XDP_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP) ?
			"DVI, HDMI, or DP++" :
		(DownPortType == XDP_DPCD_DOWNSP_TYPE_OTHERS) ?
			"Others" : "Unknown downstream port type",
		FormatConversionBlockPresent ? "Y" : "N",
		DetailedCapInfoAvailable ? "Y" : "N",
		MainLinkAnsi8b10bCodingSupport ? "Y" : "N",
		DownstreamPortCount,
		MsaTimingParIgnored ? "Y" : "N",
		OuiSupported ? "Y" : "N",
		RxPort0LocalEdidPresent ? "Y" : "N",
		RxPort0AssocPrecedePort ? "Y" : "N",
		RxPort0BufSizeBpl,
		RxPort1LocalEdidPresent ? "Y" : "N",
		RxPort1AssocPrecedePort ? "Y" : "N",
		RxPort1BufSizeBpl,
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_NONE) ? "No control" :
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_1KBIPS) ? "1Kbps" :
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_5KBIPS) ? "5Kbps" :
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_10KBIPS) ? "10Kbps" :
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_100KBIPS) ? "100Kbps" :
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_400KBIPS) ? "400Kbps" :
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_1MBIPS) ? "1Mbps" :
			"Unknown I2C speed",
		EdpAltScramblerResetCap ? "Y" : "N",
		EdpFramingChangeCap ? "Y" : "N",
		(TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_100_400US) ?
			"100us for CR, 400us for CE" : (TraingAuxReadInt ==
			XDP_DPCD_TRAIN_AUX_RD_INT_4MS) ? "4us" :
		(TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_8MS) ? "8us" :
		(TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_12MS) ?
		"12us" : (TraingAuxReadInt ==
			XDP_DPCD_TRAIN_AUX_RD_INT_16MS) ? "16us" :
				"Unknown AUX read interval",
		AdapterForceLoadSenseCap ? "Y" : "N",
		AdapterAltI2CPatternCap ? "Y" : "N",
		FauxCap ? "Y" : "N",
		MstmCap ? "Y" : "N",
		NumAudioEps
	);

	xil_printf("\n\r");
}
/*****************************************************************************/
/**
*
* This function prints the capabilities of the DisplayPort sink.
*
* @param	InstancePtr is a pointer to the XDpTxSs core instance.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function prints the capabilities of the DisplayPort sink.
This function prints the capabilities of the DisplayPort sink .
void XDpTxSs_ReportSinkCapInfo(XDpTxSs *InstancePtr)
{
	Xil_AssertVoid(InstancePtr != NULL);
	u8 *Dpcd = InstancePtr->DpPtr->TxInstance.RxConfig.DpcdRxCapsField;
	u8 DpcdRevMajor = (Dpcd[XDP_DPCD_REV] &
				XDP_DPCD_REV_MJR_MASK) >>
					XDP_DPCD_REV_MJR_SHIFT;
	u8 DpcdRevMinor = Dpcd[XDP_DPCD_REV] & XDP_DPCD_REV_MNR_MASK;
	u8 MaxLinkRate = Dpcd[XDP_DPCD_MAX_LINK_RATE];
	u8 MaxLaneCount = Dpcd[XDP_DPCD_MAX_LANE_COUNT] &
				XDP_DPCD_MAX_LANE_COUNT_MASK;
	u8 Tps3Support = Dpcd[XDP_DPCD_MAX_LANE_COUNT] &
				XDP_DPCD_TPS3_SUPPORT_MASK;
	u8 EnhancedFrameSupport = Dpcd[XDP_DPCD_MAX_LANE_COUNT] &
				XDP_DPCD_ENHANCED_FRAME_SUPPORT_MASK;
	u8 MaxDownspreadSupport = Dpcd[XDP_DPCD_MAX_DOWNSPREAD] &
				XDP_DPCD_MAX_DOWNSPREAD_MASK;
	u8 NoAuxHandshakeRequired = Dpcd[XDP_DPCD_MAX_DOWNSPREAD] &
				XDP_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK;
	u8 NumRxPorts = (Dpcd[XDP_DPCD_NORP_PWR_V_CAP] & (0x01)) + 1;
	u8 PwrDpCap5V = Dpcd[XDP_DPCD_NORP_PWR_V_CAP] & (0x01);
	u8 PwrDpCap12V = Dpcd[XDP_DPCD_NORP_PWR_V_CAP] & (0x20);
	u8 PwrDpCap18V = Dpcd[XDP_DPCD_NORP_PWR_V_CAP] & (0x40);
	u8 DownstreamPortPresent = Dpcd[XDP_DPCD_DOWNSP_PRESENT] & (0x80);
	u8 DownPortType = (Dpcd[XDP_DPCD_DOWNSP_PRESENT] &
				XDP_DPCD_DOWNSP_TYPE_MASK) >>
					XDP_DPCD_DOWNSP_TYPE_SHIFT;
	u8 FormatConversionBlockPresent = Dpcd[XDP_DPCD_DOWNSP_PRESENT] &
					XDP_DPCD_DOWNSP_FORMAT_CONV_MASK;
	u8 DetailedCapInfoAvailable = Dpcd[XDP_DPCD_DOWNSP_PRESENT] &
					XDP_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK;
	u8 MainLinkAnsi8b10bCodingSupport = Dpcd[XDP_DPCD_ML_CH_CODING_CAP] &
						XDP_DPCD_ML_CH_CODING_MASK;
	u8 DownstreamPortCount = Dpcd[XDP_DPCD_DOWNSP_COUNT_MSA_OUI] &
					XDP_DPCD_DOWNSP_COUNT_MASK;
	u8 MsaTimingParIgnored = Dpcd[XDP_DPCD_DOWNSP_COUNT_MSA_OUI] &
					XDP_DPCD_MSA_TIMING_PAR_IGNORED_MASK;
	u8 OuiSupported = Dpcd[XDP_DPCD_DOWNSP_COUNT_MSA_OUI] &
				XDP_DPCD_OUI_SUPPORT_MASK;
	u8 RxPort0LocalEdidPresent = Dpcd[XDP_DPCD_RX_PORT0_CAP_0] &
			XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK;
	u8 RxPort0AssocPrecedePort = Dpcd[XDP_DPCD_RX_PORT0_CAP_0] &
			XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK;
	u8 RxPort0BufSizeBpl = (Dpcd[XDP_DPCD_RX_PORT0_CAP_1] + 1) * 32;
	u8 RxPort1LocalEdidPresent = Dpcd[XDP_DPCD_RX_PORT1_CAP_0] &
			XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK;
	u8 RxPort1AssocPrecedePort = Dpcd[XDP_DPCD_RX_PORT1_CAP_0] &
			XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK;
	u8 RxPort1BufSizeBpl = (Dpcd[XDP_DPCD_RX_PORT1_CAP_1] + 1) * 32;
	u8 IicSpeed = Dpcd[XDP_DPCD_I2C_SPEED_CTL_CAP];
	u8 EdpAltScramblerResetCap = Dpcd[XDP_DPCD_EDP_CFG_CAP] &(0x1);
	u8 EdpFramingChangeCap = Dpcd[XDP_DPCD_EDP_CFG_CAP] & (0x2);
	u8 TraingAuxReadInt = Dpcd[XDP_DPCD_TRAIN_AUX_RD_INTERVAL];
	u8 AdapterForceLoadSenseCap = Dpcd[XDP_DPCD_ADAPTER_CAP] & (0x01);
	u8 AdapterAltI2CPatternCap = Dpcd[XDP_DPCD_ADAPTER_CAP] & (0x02);
	u8 FauxCap = Dpcd[XDP_DPCD_FAUX_CAP] & XDP_DPCD_FAUX_CAP_MASK;
	u8 MstmCap = Dpcd[XDP_DPCD_MSTM_CAP] & XDP_DPCD_MST_CAP_MASK;
	u8 NumAudioEps = Dpcd[XDP_DPCD_NUM_AUDIO_EPS];
	xil_printf("RX capabilities:\n\r"
		"\tDPCD rev major (0x00000): %d\n\r"
		"\tDPCD rev minor (0x00000): %d\n\r"
		"\tMax link rate (0x00001): %s\n\r"
		"\tMax lane count (0x00002): %d\n\r"
		"\tTPS3 supported (0x00002): %s\n\r"
		"\tEnhanced frame support? (0x00002) %s\n\r"
		"\tMax downspread support? (0x00003) %s\n\r"
		"\tNo AUX handshake required? (0x00003)%s\n\r"
		"\t# of receiver ports (0x00004): %d\n\r"
		"\tDP power 5v cap? (0x00004) %s\n\r"
		"\tDP power 12v cap? (0x00004) %s\n\r"
		"\tDP power 18v cap? (0x00004) %s\n\r"
		"\tDownstream ports present? (0x00005) %s\n\r"
		"\tDownstreamport0 type (0x00005): %s\n\r"
		"\tFormat conversion block present (0x00005): %s\n\r"
		"\tDetailed cap info available? (0x00005) %s\n\r"
		"\tMain link ANSI 8b/10b channel coding support? (0x00006) "
			"%s\n\r"
		"\tDownstream port count (0x00007): %d\n\r"
		"\tMSA timing parameters ignored? (0x00007) %s\n\r"
		"\tOUI supported? (0x00007) %s\n\r"
		"\tReceive port0 local edid present (0x00008) %s\n\r"
		"\tReceive port0 associated to preceding port? (0x00008) "
			"%s\n\r"
		"\tReceive port0 buffer size (0x00009): %d bytes per lane\n\r"
		"\tReceive port1 local edid present (0x0000A) %s\n\r"
		"\tReceive port1 associated to preceding port? (0x0000A) "
			"%s\n\r"
		"\tReceive port1 buffer size (0x0000B): %d bytes per lane\n\r"
		"\tI2C speed (0x0000C): %s\n\r"
		"\tEDP alt scrambler reset cap? (0x0000D) %s\n\r"
		"\tEDP framing change cap? (0x0000D) %s\n\r"
		"\tTraining AUX read interval (0x0000E): %s\n\r"
		"\tAdapter force load sense cap? (0x0000F) %s\n\r"
		"\tAdapter alt i2c pattern cap? (0x0000F) %s\n\r"
		"\tFaux cap?  (0x00020) %s\n\r"
		"\tMSTM cap? (0x00021) %s\n\r"
		"\t# of audio eps (0x00022) : %d\n\r",
		DpcdRevMajor,
		DpcdRevMinor,
		(MaxLinkRate == XDP_DPCD_LINK_BW_SET_162GBPS) ? "1.62Gbps" :
		(MaxLinkRate == XDP_DPCD_LINK_BW_SET_270GBPS) ? "2.70Gbps" :
		(MaxLinkRate == XDP_DPCD_LINK_BW_SET_540GBPS) ? "5.40Gbps" :
		"Unknown link rate",
		MaxLaneCount,
		Tps3Support ? "Y" : "N",
		EnhancedFrameSupport ? "Y" : "N",
		MaxDownspreadSupport ? "Y" : "N",
		NoAuxHandshakeRequired ? "Y" : "N",
		NumRxPorts,
		PwrDpCap5V ? "Y" : "N",
		PwrDpCap12V ? "Y" : "N",
		PwrDpCap18V ? "Y" : "N",
		DownstreamPortPresent ? "Y" : "N",
		(DownPortType == XDP_DPCD_DOWNSP_TYPE_DP) ?
		"DisplayPort" :
		(DownPortType == XDP_DPCD_DOWNSP_TYPE_AVGA_ADVII) ?
			"Analog VGA or analog video over DVI-I" :
		(DownPortType == XDP_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP) ?
			"DVI, HDMI, or DP++" :
		(DownPortType == XDP_DPCD_DOWNSP_TYPE_OTHERS) ?
			"Others" : "Unknown downstream port type",
		FormatConversionBlockPresent ? "Y" : "N",
		DetailedCapInfoAvailable ? "Y" : "N",
		MainLinkAnsi8b10bCodingSupport ? "Y" : "N",
		DownstreamPortCount,
		MsaTimingParIgnored ? "Y" : "N",
		OuiSupported ? "Y" : "N",
		RxPort0LocalEdidPresent ? "Y" : "N",
		RxPort0AssocPrecedePort ? "Y" : "N",
		RxPort0BufSizeBpl,
		RxPort1LocalEdidPresent ? "Y" : "N",
		RxPort1AssocPrecedePort ? "Y" : "N",
		RxPort1BufSizeBpl,
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_NONE) ? "No control" :
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_1KBIPS) ? "1Kbps" :
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_5KBIPS) ? "5Kbps" :
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_10KBIPS) ? "10Kbps" :
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_100KBIPS) ? "100Kbps" :
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_400KBIPS) ? "400Kbps" :
		(IicSpeed == XDP_DPCD_I2C_SPEED_CTL_1MBIPS) ? "1Mbps" :
			"Unknown I2C speed",
		EdpAltScramblerResetCap ? "Y" : "N",
		EdpFramingChangeCap ? "Y" : "N",
		(TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_100_400US) ?
			"100us for CR, 400us for CE" : (TraingAuxReadInt ==
			XDP_DPCD_TRAIN_AUX_RD_INT_4MS) ? "4us" :
		(TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_8MS) ? "8us" :
		(TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_12MS) ?
		"12us" : (TraingAuxReadInt ==
			XDP_DPCD_TRAIN_AUX_RD_INT_16MS) ? "16us" :
				"Unknown AUX read interval",
		AdapterForceLoadSenseCap ? "Y" : "N",
		AdapterAltI2CPatternCap ? "Y" : "N",
		FauxCap ? "Y" : "N",
		MstmCap ? "Y" : "N",
		NumAudioEps
	);
	xil_printf("\n\r");
}
void XDpTxSs_ReportSinkCapInfo ( XDpTxSs * InstancePtr ) { Xil_AssertVoid ( InstancePtr != NULL ) ; u8 * Dpcd = InstancePtr -> DpPtr -> TxInstance . RxConfig . DpcdRxCapsField ; u8 DpcdRevMajor = ( Dpcd [ XDP_DPCD_REV ] & XDP_DPCD_REV_MJR_MASK ) >> XDP_DPCD_REV_MJR_SHIFT ; u8 DpcdRevMinor = Dpcd [ XDP_DPCD_REV ] & XDP_DPCD_REV_MNR_MASK ; u8 MaxLinkRate = Dpcd [ XDP_DPCD_MAX_LINK_RATE ] ; u8 MaxLaneCount = Dpcd [ XDP_DPCD_MAX_LANE_COUNT ] & XDP_DPCD_MAX_LANE_COUNT_MASK ; u8 Tps3Support = Dpcd [ XDP_DPCD_MAX_LANE_COUNT ] & XDP_DPCD_TPS3_SUPPORT_MASK ; u8 EnhancedFrameSupport = Dpcd [ XDP_DPCD_MAX_LANE_COUNT ] & XDP_DPCD_ENHANCED_FRAME_SUPPORT_MASK ; u8 MaxDownspreadSupport = Dpcd [ XDP_DPCD_MAX_DOWNSPREAD ] & XDP_DPCD_MAX_DOWNSPREAD_MASK ; u8 NoAuxHandshakeRequired = Dpcd [ XDP_DPCD_MAX_DOWNSPREAD ] & XDP_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK ; u8 NumRxPorts = ( Dpcd [ XDP_DPCD_NORP_PWR_V_CAP ] & ( 0x01 ) ) + 1 ; u8 PwrDpCap5V = Dpcd [ XDP_DPCD_NORP_PWR_V_CAP ] & ( 0x01 ) ; u8 PwrDpCap12V = Dpcd [ XDP_DPCD_NORP_PWR_V_CAP ] & ( 0x20 ) ; u8 PwrDpCap18V = Dpcd [ XDP_DPCD_NORP_PWR_V_CAP ] & ( 0x40 ) ; u8 DownstreamPortPresent = Dpcd [ XDP_DPCD_DOWNSP_PRESENT ] & ( 0x80 ) ; u8 DownPortType = ( Dpcd [ XDP_DPCD_DOWNSP_PRESENT ] & XDP_DPCD_DOWNSP_TYPE_MASK ) >> XDP_DPCD_DOWNSP_TYPE_SHIFT ; u8 FormatConversionBlockPresent = Dpcd [ XDP_DPCD_DOWNSP_PRESENT ] & XDP_DPCD_DOWNSP_FORMAT_CONV_MASK ; u8 DetailedCapInfoAvailable = Dpcd [ XDP_DPCD_DOWNSP_PRESENT ] & XDP_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK ; u8 MainLinkAnsi8b10bCodingSupport = Dpcd [ XDP_DPCD_ML_CH_CODING_CAP ] & XDP_DPCD_ML_CH_CODING_MASK ; u8 DownstreamPortCount = Dpcd [ XDP_DPCD_DOWNSP_COUNT_MSA_OUI ] & XDP_DPCD_DOWNSP_COUNT_MASK ; u8 MsaTimingParIgnored = Dpcd [ XDP_DPCD_DOWNSP_COUNT_MSA_OUI ] & XDP_DPCD_MSA_TIMING_PAR_IGNORED_MASK ; u8 OuiSupported = Dpcd [ XDP_DPCD_DOWNSP_COUNT_MSA_OUI ] & XDP_DPCD_OUI_SUPPORT_MASK ; u8 RxPort0LocalEdidPresent = Dpcd [ XDP_DPCD_RX_PORT0_CAP_0 ] & XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK ; u8 RxPort0AssocPrecedePort = Dpcd [ XDP_DPCD_RX_PORT0_CAP_0 ] & XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK ; u8 RxPort0BufSizeBpl = ( Dpcd [ XDP_DPCD_RX_PORT0_CAP_1 ] + 1 ) * 32 ; u8 RxPort1LocalEdidPresent = Dpcd [ XDP_DPCD_RX_PORT1_CAP_0 ] & XDP_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK ; u8 RxPort1AssocPrecedePort = Dpcd [ XDP_DPCD_RX_PORT1_CAP_0 ] & XDP_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK ; u8 RxPort1BufSizeBpl = ( Dpcd [ XDP_DPCD_RX_PORT1_CAP_1 ] + 1 ) * 32 ; u8 IicSpeed = Dpcd [ XDP_DPCD_I2C_SPEED_CTL_CAP ] ; u8 EdpAltScramblerResetCap = Dpcd [ XDP_DPCD_EDP_CFG_CAP ] & ( 0x1 ) ; u8 EdpFramingChangeCap = Dpcd [ XDP_DPCD_EDP_CFG_CAP ] & ( 0x2 ) ; u8 TraingAuxReadInt = Dpcd [ XDP_DPCD_TRAIN_AUX_RD_INTERVAL ] ; u8 AdapterForceLoadSenseCap = Dpcd [ XDP_DPCD_ADAPTER_CAP ] & ( 0x01 ) ; u8 AdapterAltI2CPatternCap = Dpcd [ XDP_DPCD_ADAPTER_CAP ] & ( 0x02 ) ; u8 FauxCap = Dpcd [ XDP_DPCD_FAUX_CAP ] & XDP_DPCD_FAUX_CAP_MASK ; u8 MstmCap = Dpcd [ XDP_DPCD_MSTM_CAP ] & XDP_DPCD_MST_CAP_MASK ; u8 NumAudioEps = Dpcd [ XDP_DPCD_NUM_AUDIO_EPS ] ; xil_printf ( " \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t " " \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t " " \n \r " " \t \n \r " " \t \n \r " " \t " " \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " , DpcdRevMajor , DpcdRevMinor , ( MaxLinkRate == XDP_DPCD_LINK_BW_SET_162GBPS ) ? " " : ( MaxLinkRate == XDP_DPCD_LINK_BW_SET_270GBPS ) ? " " : ( MaxLinkRate == XDP_DPCD_LINK_BW_SET_540GBPS ) ? " " : " " , MaxLaneCount , Tps3Support ? " " : " " , EnhancedFrameSupport ? " " : " " , MaxDownspreadSupport ? " " : " " , NoAuxHandshakeRequired ? " " : " " , NumRxPorts , PwrDpCap5V ? " " : " " , PwrDpCap12V ? " " : " " , PwrDpCap18V ? " " : " " , DownstreamPortPresent ? " " : " " , ( DownPortType == XDP_DPCD_DOWNSP_TYPE_DP ) ? " " : ( DownPortType == XDP_DPCD_DOWNSP_TYPE_AVGA_ADVII ) ? " " : ( DownPortType == XDP_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP ) ? " " : ( DownPortType == XDP_DPCD_DOWNSP_TYPE_OTHERS ) ? " " : " " , FormatConversionBlockPresent ? " " : " " , DetailedCapInfoAvailable ? " " : " " , MainLinkAnsi8b10bCodingSupport ? " " : " " , DownstreamPortCount , MsaTimingParIgnored ? " " : " " , OuiSupported ? " " : " " , RxPort0LocalEdidPresent ? " " : " " , RxPort0AssocPrecedePort ? " " : " " , RxPort0BufSizeBpl , RxPort1LocalEdidPresent ? " " : " " , RxPort1AssocPrecedePort ? " " : " " , RxPort1BufSizeBpl , ( IicSpeed == XDP_DPCD_I2C_SPEED_CTL_NONE ) ? " " : ( IicSpeed == XDP_DPCD_I2C_SPEED_CTL_1KBIPS ) ? " " : ( IicSpeed == XDP_DPCD_I2C_SPEED_CTL_5KBIPS ) ? " " : ( IicSpeed == XDP_DPCD_I2C_SPEED_CTL_10KBIPS ) ? " " : ( IicSpeed == XDP_DPCD_I2C_SPEED_CTL_100KBIPS ) ? " " : ( IicSpeed == XDP_DPCD_I2C_SPEED_CTL_400KBIPS ) ? " " : ( IicSpeed == XDP_DPCD_I2C_SPEED_CTL_1MBIPS ) ? " " : " " , EdpAltScramblerResetCap ? " " : " " , EdpFramingChangeCap ? " " : " " , ( TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_100_400US ) ? " " : ( TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_4MS ) ? " " : ( TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_8MS ) ? " " : ( TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_12MS ) ? " " : ( TraingAuxReadInt == XDP_DPCD_TRAIN_AUX_RD_INT_16MS ) ? " " : " " , AdapterForceLoadSenseCap ? " " : " " , AdapterAltI2CPatternCap ? " " : " " , FauxCap ? " " : " " , MstmCap ? " " : " " , NumAudioEps ) ; xil_printf ( " \n \r " ) ; }
This function prints the capabilities of the DisplayPort sink.
This function prints the capabilities of the DisplayPort sink .
/* Verify argument. */