src/dpdk/drivers/net/qede/qede_debug.c
static u32
qed_idle_chk_dump_rule_entries(struct ecore_hwfn *p_hwfn,
			       struct ecore_ptt *p_ptt,
			       u32 *dump_buf, bool dump,
			       const struct dbg_idle_chk_rule *input_rules,
			       u32 num_input_rules, u32 *num_failing_rules)
{
	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	u32 cond_reg_values[IDLE_CHK_MAX_ENTRIES_SIZE];
	u32 i, offset = 0;
	u16 entry_id;
	u8 reg_id;

	*num_failing_rules = 0;

	for (i = 0; i < num_input_rules; i++) {
		const struct dbg_idle_chk_cond_reg *cond_regs;
		const struct dbg_idle_chk_rule *rule;
		const union dbg_idle_chk_reg *regs;
		u16 num_reg_entries = 1;
		bool check_rule = true;
		const u32 *imm_values;

		rule = &input_rules[i];
		regs = (const union dbg_idle_chk_reg *)
			p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr +
			rule->reg_offset;
		cond_regs = &regs[0].cond_reg;
		imm_values =
		    (u32 *)p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr +
		    rule->imm_offset;

		/* Check if all condition register blocks are out of reset, and
		 * find maximal number of entries (all condition registers that
		 * are memories must have the same size, which is > 1).
		 */
		for (reg_id = 0; reg_id < rule->num_cond_regs && check_rule;
		     reg_id++) {
			u32 block_id =
				GET_FIELD(cond_regs[reg_id].data,
					  DBG_IDLE_CHK_COND_REG_BLOCK_ID);

			if (block_id >= MAX_BLOCK_ID) {
				DP_NOTICE(p_hwfn, false, "Invalid block_id\n");
				return 0;
			}

			check_rule = !dev_data->block_in_reset[block_id];
			if (cond_regs[reg_id].num_entries > num_reg_entries)
				num_reg_entries = cond_regs[reg_id].num_entries;
		}

		if (!check_rule && dump)
			continue;

		if (!dump) {
			u32 entry_dump_size =
				qed_idle_chk_dump_failure(p_hwfn,
							  p_ptt,
							  dump_buf + offset,
							  false,
							  rule->rule_id,
							  rule,
							  0,
							  NULL);

			offset += num_reg_entries * entry_dump_size;
			(*num_failing_rules) += num_reg_entries;
			continue;
		}

		/* Go over all register entries (number of entries is the same
		 * for all condition registers).
		 */
		for (entry_id = 0; entry_id < num_reg_entries; entry_id++) {
			u32 next_reg_offset = 0;

			/* Read current entry of all condition registers */
			for (reg_id = 0; reg_id < rule->num_cond_regs;
			     reg_id++) {
				const struct dbg_idle_chk_cond_reg *reg =
					&cond_regs[reg_id];
				u32 padded_entry_size, addr;
				bool wide_bus;

				/* Find GRC address (if it's a memory, the
				 * address of the specific entry is calculated).
				 */
				addr = GET_FIELD(reg->data,
						 DBG_IDLE_CHK_COND_REG_ADDRESS);
				wide_bus =
				    GET_FIELD(reg->data,
					      DBG_IDLE_CHK_COND_REG_WIDE_BUS);
				if (reg->num_entries > 1 ||
				    reg->start_entry > 0) {
					padded_entry_size =
					   reg->entry_size > 1 ?
					   OSAL_ROUNDUP_POW_OF_TWO(reg->entry_size) :
					   1;
					addr += (reg->start_entry + entry_id) *
						padded_entry_size;
				}

				/* Read registers */
				if (next_reg_offset + reg->entry_size >=
				    IDLE_CHK_MAX_ENTRIES_SIZE) {
					DP_NOTICE(p_hwfn, false,
						  "idle check registers entry is too large\n");
					return 0;
				}

				next_reg_offset +=
				    qed_grc_dump_addr_range(p_hwfn, p_ptt,
							    cond_reg_values +
							    next_reg_offset,
							    dump, addr,
							    reg->entry_size,
							    wide_bus,
							    SPLIT_TYPE_NONE, 0);
			}

			/* Call rule condition function.
			 * If returns true, it's a failure.
			 */
			if ((*cond_arr[rule->cond_id]) (cond_reg_values,
							imm_values)) {
				offset += qed_idle_chk_dump_failure(p_hwfn,
							p_ptt,
							dump_buf + offset,
							dump,
							rule->rule_id,
							rule,
							entry_id,
							cond_reg_values);
				(*num_failing_rules)++;
			}
		}
	}

	return offset;
}
/* Dumps idle check rule entries. Returns the dumped size in dwords. */
Dumps idle check rule entries. Returns the dumped size in dwords.
Dumps idle check rule entries . Returns the dumped size in dwords .
static u32
qed_idle_chk_dump_rule_entries(struct ecore_hwfn *p_hwfn,
			       struct ecore_ptt *p_ptt,
			       u32 *dump_buf, bool dump,
			       const struct dbg_idle_chk_rule *input_rules,
			       u32 num_input_rules, u32 *num_failing_rules)
{
	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	u32 cond_reg_values[IDLE_CHK_MAX_ENTRIES_SIZE];
	u32 i, offset = 0;
	u16 entry_id;
	u8 reg_id;
	*num_failing_rules = 0;
	for (i = 0; i < num_input_rules; i++) {
		const struct dbg_idle_chk_cond_reg *cond_regs;
		const struct dbg_idle_chk_rule *rule;
		const union dbg_idle_chk_reg *regs;
		u16 num_reg_entries = 1;
		bool check_rule = true;
		const u32 *imm_values;
		rule = &input_rules[i];
		regs = (const union dbg_idle_chk_reg *)
			p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr +
			rule->reg_offset;
		cond_regs = &regs[0].cond_reg;
		imm_values =
		    (u32 *)p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr +
		    rule->imm_offset;
		for (reg_id = 0; reg_id < rule->num_cond_regs && check_rule;
		     reg_id++) {
			u32 block_id =
				GET_FIELD(cond_regs[reg_id].data,
					  DBG_IDLE_CHK_COND_REG_BLOCK_ID);
			if (block_id >= MAX_BLOCK_ID) {
				DP_NOTICE(p_hwfn, false, "Invalid block_id\n");
				return 0;
			}
			check_rule = !dev_data->block_in_reset[block_id];
			if (cond_regs[reg_id].num_entries > num_reg_entries)
				num_reg_entries = cond_regs[reg_id].num_entries;
		}
		if (!check_rule && dump)
			continue;
		if (!dump) {
			u32 entry_dump_size =
				qed_idle_chk_dump_failure(p_hwfn,
							  p_ptt,
							  dump_buf + offset,
							  false,
							  rule->rule_id,
							  rule,
							  0,
							  NULL);
			offset += num_reg_entries * entry_dump_size;
			(*num_failing_rules) += num_reg_entries;
			continue;
		}
		for (entry_id = 0; entry_id < num_reg_entries; entry_id++) {
			u32 next_reg_offset = 0;
			for (reg_id = 0; reg_id < rule->num_cond_regs;
			     reg_id++) {
				const struct dbg_idle_chk_cond_reg *reg =
					&cond_regs[reg_id];
				u32 padded_entry_size, addr;
				bool wide_bus;
				addr = GET_FIELD(reg->data,
						 DBG_IDLE_CHK_COND_REG_ADDRESS);
				wide_bus =
				    GET_FIELD(reg->data,
					      DBG_IDLE_CHK_COND_REG_WIDE_BUS);
				if (reg->num_entries > 1 ||
				    reg->start_entry > 0) {
					padded_entry_size =
					   reg->entry_size > 1 ?
					   OSAL_ROUNDUP_POW_OF_TWO(reg->entry_size) :
					   1;
					addr += (reg->start_entry + entry_id) *
						padded_entry_size;
				}
				if (next_reg_offset + reg->entry_size >=
				    IDLE_CHK_MAX_ENTRIES_SIZE) {
					DP_NOTICE(p_hwfn, false,
						  "idle check registers entry is too large\n");
					return 0;
				}
				next_reg_offset +=
				    qed_grc_dump_addr_range(p_hwfn, p_ptt,
							    cond_reg_values +
							    next_reg_offset,
							    dump, addr,
							    reg->entry_size,
							    wide_bus,
							    SPLIT_TYPE_NONE, 0);
			}
			if ((*cond_arr[rule->cond_id]) (cond_reg_values,
							imm_values)) {
				offset += qed_idle_chk_dump_failure(p_hwfn,
							p_ptt,
							dump_buf + offset,
							dump,
							rule->rule_id,
							rule,
							entry_id,
							cond_reg_values);
				(*num_failing_rules)++;
			}
		}
	}
	return offset;
}
static u32 qed_idle_chk_dump_rule_entries ( struct ecore_hwfn * p_hwfn , struct ecore_ptt * p_ptt , u32 * dump_buf , bool dump , const struct dbg_idle_chk_rule * input_rules , u32 num_input_rules , u32 * num_failing_rules ) { struct dbg_tools_data * dev_data = & p_hwfn -> dbg_info ; u32 cond_reg_values [ IDLE_CHK_MAX_ENTRIES_SIZE ] ; u32 i , offset = 0 ; u16 entry_id ; u8 reg_id ; * num_failing_rules = 0 ; for ( i = 0 ; i < num_input_rules ; i ++ ) { const struct dbg_idle_chk_cond_reg * cond_regs ; const struct dbg_idle_chk_rule * rule ; const union dbg_idle_chk_reg * regs ; u16 num_reg_entries = 1 ; bool check_rule = true ; const u32 * imm_values ; rule = & input_rules [ i ] ; regs = ( const union dbg_idle_chk_reg * ) p_hwfn -> dbg_arrays [ BIN_BUF_DBG_IDLE_CHK_REGS ] . ptr + rule -> reg_offset ; cond_regs = & regs [ 0 ] . cond_reg ; imm_values = ( u32 * ) p_hwfn -> dbg_arrays [ BIN_BUF_DBG_IDLE_CHK_IMMS ] . ptr + rule -> imm_offset ; for ( reg_id = 0 ; reg_id < rule -> num_cond_regs && check_rule ; reg_id ++ ) { u32 block_id = GET_FIELD ( cond_regs [ reg_id ] . data , DBG_IDLE_CHK_COND_REG_BLOCK_ID ) ; if ( block_id >= MAX_BLOCK_ID ) { DP_NOTICE ( p_hwfn , false , " \n " ) ; return 0 ; } check_rule = ! dev_data -> block_in_reset [ block_id ] ; if ( cond_regs [ reg_id ] . num_entries > num_reg_entries ) num_reg_entries = cond_regs [ reg_id ] . num_entries ; } if ( ! check_rule && dump ) continue ; if ( ! dump ) { u32 entry_dump_size = qed_idle_chk_dump_failure ( p_hwfn , p_ptt , dump_buf + offset , false , rule -> rule_id , rule , 0 , NULL ) ; offset += num_reg_entries * entry_dump_size ; ( * num_failing_rules ) += num_reg_entries ; continue ; } for ( entry_id = 0 ; entry_id < num_reg_entries ; entry_id ++ ) { u32 next_reg_offset = 0 ; for ( reg_id = 0 ; reg_id < rule -> num_cond_regs ; reg_id ++ ) { const struct dbg_idle_chk_cond_reg * reg = & cond_regs [ reg_id ] ; u32 padded_entry_size , addr ; bool wide_bus ; addr = GET_FIELD ( reg -> data , DBG_IDLE_CHK_COND_REG_ADDRESS ) ; wide_bus = GET_FIELD ( reg -> data , DBG_IDLE_CHK_COND_REG_WIDE_BUS ) ; if ( reg -> num_entries > 1 || reg -> start_entry > 0 ) { padded_entry_size = reg -> entry_size > 1 ? OSAL_ROUNDUP_POW_OF_TWO ( reg -> entry_size ) : 1 ; addr += ( reg -> start_entry + entry_id ) * padded_entry_size ; } if ( next_reg_offset + reg -> entry_size >= IDLE_CHK_MAX_ENTRIES_SIZE ) { DP_NOTICE ( p_hwfn , false , " \n " ) ; return 0 ; } next_reg_offset += qed_grc_dump_addr_range ( p_hwfn , p_ptt , cond_reg_values + next_reg_offset , dump , addr , reg -> entry_size , wide_bus , SPLIT_TYPE_NONE , 0 ) ; } if ( ( * cond_arr [ rule -> cond_id ] ) ( cond_reg_values , imm_values ) ) { offset += qed_idle_chk_dump_failure ( p_hwfn , p_ptt , dump_buf + offset , dump , rule -> rule_id , rule , entry_id , cond_reg_values ) ; ( * num_failing_rules ) ++ ; } } } return offset ; }
Dumps idle check rule entries.
Dumps idle check rule entries .
/* Check if all condition register blocks are out of reset, and
		 * find maximal number of entries (all condition registers that
		 * are memories must have the same size, which is > 1).
		 */ /* Go over all register entries (number of entries is the same
		 * for all condition registers).
		 */ /* Read current entry of all condition registers */ /* Find GRC address (if it's a memory, the
				 * address of the specific entry is calculated).
				 */ /* Read registers */ /* Call rule condition function.
			 * If returns true, it's a failure.
			 */