XilinxProcessorIPLib/drivers/vphy/src/xvphy_gtye4.c
u32 XVphy_Gtye4RxChReconfig(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
{
	XVphy_Channel *ChPtr;
	u16 DrpVal;
	u16 WriteVal;
	u8 CfgIndex;
	XVphy_ChannelId ChIdPll;
	XVphy_PllType PllType;
	u32 PllxVcoRateMHz;
	u32 PllxClkOutMHz;
	u32 PllxClkOutDiv;
    u32 Status = XST_SUCCESS;
    u64 LineRateHz;

	ChPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(ChId)];

	/* RXCDR_CFG(CfgIndex) */
	for (CfgIndex = 0; CfgIndex < 5; CfgIndex++) {
		DrpVal = ChPtr->PllParams.Cdr[CfgIndex];
		if (!DrpVal) {
			/* Don't modify RX_CDR configuration. */
			continue;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId,
				XVPHY_DRP_RXCDR_CFG(CfgIndex), DrpVal);
		if (CfgIndex == 2) {
			Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId,
					XVPHY_DRP_RXCDR_CFG_GEN3(CfgIndex), DrpVal);
		/* RXCDR_CFG2_GEN2 */
        Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x135, &DrpVal);
		DrpVal &= ~(0x3FF);
		DrpVal |= ChPtr->PllParams.Cdr[CfgIndex] & 0x3FF;
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x135, DrpVal);
		}
	}

    /* Modify RXCDR_CFG3 for DP */
	if (InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_DP) {
		LineRateHz = XVphy_GetLineRateHz(InstancePtr, QuadId, ChId);
		if(LineRateHz==XVPHY_DP_LINK_RATE_HZ_810GBPS) {
            /* RXCDR_CFG3 */
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x11, 0x12);
            /* RXCDR_CFG3_GEN2 */
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x135, 0x12);
            /* RXCDR_CFG3_GEN3 */
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xA5, 0x12);
            /* RXCDR_CFG3_GEN4 */
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x11C, 0x12);
		} else {
            /* RXCDR_CFG3 */
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x11, 0x1A);
            /* RXCDR_CFG3_GEN2 */
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x135, 0x1A);
            /* RXCDR_CFG3_GEN3 */
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xA5, 0x1A);
            /* RXCDR_CFG3_GEN4 */
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x11C, 0x1A);
		}
	}

	if (XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX)) {
		/* RX_INT_DATAWIDTH */
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x66, &DrpVal);
		DrpVal &= ~(0x3);
		WriteVal = (Xvphy_DrpEncodeIntDataWidth(ChPtr->RxIntDataWidth) & 0x3);
		DrpVal |= WriteVal;
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x66, DrpVal);

		/* RX_DATA_WIDTH */
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x03, &DrpVal);
		DrpVal &= ~(0x1E0);
		WriteVal = (Xvphy_DrpEncodeDataWidth(ChPtr->RxDataWidth) & 0xF);
		WriteVal <<= 5;
		DrpVal |= WriteVal;
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x03, DrpVal);

		/* Determine PLL type. */
		PllType = XVphy_GetPllType(InstancePtr, QuadId, XVPHY_DIR_RX, ChId);
		/* Determine which channel(s) to operate on. */
		switch (PllType) {
			case XVPHY_PLL_TYPE_QPLL:
			case XVPHY_PLL_TYPE_QPLL0:
			case XVPHY_PLL_TYPE_PLL0:
				ChIdPll = XVPHY_CHANNEL_ID_CMN0;
				PllxClkOutDiv = 2;
				break;
			case XVPHY_PLL_TYPE_QPLL1:
			case XVPHY_PLL_TYPE_PLL1:
				ChIdPll = XVPHY_CHANNEL_ID_CMN1;
				PllxClkOutDiv = 2;
				break;
			default:
				ChIdPll = ChId;
				PllxClkOutDiv = 1;
				break;
		}

		PllxVcoRateMHz = XVphy_GetPllVcoFreqHz(InstancePtr, QuadId, ChIdPll,
				XVPHY_DIR_RX) / 1000000;
		PllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv;

		/* CH_HSPMUX_RX */
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x116, &DrpVal);
		DrpVal &= ~(0x00FF);
		if (PllxClkOutMHz >= 14000) {
			DrpVal |= 0xD0;
		}
		else if (PllxClkOutMHz >= 12500) {
			DrpVal |= 0x90;
		}
		else if (PllxClkOutMHz >= 8187) {
			DrpVal |= 0x60;
		}
		else if (PllxClkOutMHz >= 5156) {
			DrpVal |= 0x40;
		}
		else {
			DrpVal |= 0x20;
		}
		/* Write new DRP register value for CH_HSPMUX_RX. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x116, DrpVal);

        /* PREIQ_FREQ_BST */
        Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0xFB, &DrpVal);
        DrpVal &= ~(0x0030);
        if (PllxClkOutMHz >= 12500) {
		DrpVal |= 3 << 4;
        }
        else if (PllxClkOutMHz >= 8187) {
		DrpVal |= 2 << 4; /* LPM Mode */
        }
        else if (PllxClkOutMHz >= 5156) {
		DrpVal |= 1 << 4;
        }
        /* Write new DRP register value for PREIQ_FREQ_BST. */
        Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xFB, DrpVal);

		/* RXPI_CFG0 */
		if (PllxClkOutMHz > 15250) {
			DrpVal = 0xB806;
		}
		else if (PllxClkOutMHz >= 12500) {
			DrpVal = 0x3006;
		}
		else if (PllxClkOutMHz >= 10000) {
			DrpVal = 0x3004;
		}
		else if (PllxClkOutMHz >= 8187) {
			DrpVal = 0x0104;
		}
		else if (PllxClkOutMHz >= 6500) {
			DrpVal = 0x3002;
		}
		else if (PllxClkOutMHz >= 5156) {
			DrpVal = 0x0102;
		}
		else if (PllxClkOutMHz >= 3500) {
			DrpVal = 0x0100;
		}
		else {
			DrpVal = 0x0301;
		}
		/* Write new DRP register value for RXPI_CFG0. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x75, DrpVal);

	}

	Status |= XVphy_Gtye4RxPllRefClkDiv1Reconfig(InstancePtr, QuadId, ChId);

	return Status;
}
/*****************************************************************************/
/**
* This function will configure the channel's RX settings.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
*
* @return
*		- XST_SUCCESS if the configuration was successful.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function will configure the channel's RX settings.
This function will configure the channel ' s RX settings .
u32 XVphy_Gtye4RxChReconfig(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
{
	XVphy_Channel *ChPtr;
	u16 DrpVal;
	u16 WriteVal;
	u8 CfgIndex;
	XVphy_ChannelId ChIdPll;
	XVphy_PllType PllType;
	u32 PllxVcoRateMHz;
	u32 PllxClkOutMHz;
	u32 PllxClkOutDiv;
    u32 Status = XST_SUCCESS;
    u64 LineRateHz;
	ChPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(ChId)];
	for (CfgIndex = 0; CfgIndex < 5; CfgIndex++) {
		DrpVal = ChPtr->PllParams.Cdr[CfgIndex];
		if (!DrpVal) {
			continue;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId,
				XVPHY_DRP_RXCDR_CFG(CfgIndex), DrpVal);
		if (CfgIndex == 2) {
			Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId,
					XVPHY_DRP_RXCDR_CFG_GEN3(CfgIndex), DrpVal);
        Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x135, &DrpVal);
		DrpVal &= ~(0x3FF);
		DrpVal |= ChPtr->PllParams.Cdr[CfgIndex] & 0x3FF;
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x135, DrpVal);
		}
	}
	if (InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_DP) {
		LineRateHz = XVphy_GetLineRateHz(InstancePtr, QuadId, ChId);
		if(LineRateHz==XVPHY_DP_LINK_RATE_HZ_810GBPS) {
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x11, 0x12);
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x135, 0x12);
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xA5, 0x12);
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x11C, 0x12);
		} else {
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x11, 0x1A);
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x135, 0x1A);
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xA5, 0x1A);
            Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x11C, 0x1A);
		}
	}
	if (XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX)) {
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x66, &DrpVal);
		DrpVal &= ~(0x3);
		WriteVal = (Xvphy_DrpEncodeIntDataWidth(ChPtr->RxIntDataWidth) & 0x3);
		DrpVal |= WriteVal;
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x66, DrpVal);
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x03, &DrpVal);
		DrpVal &= ~(0x1E0);
		WriteVal = (Xvphy_DrpEncodeDataWidth(ChPtr->RxDataWidth) & 0xF);
		WriteVal <<= 5;
		DrpVal |= WriteVal;
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x03, DrpVal);
		PllType = XVphy_GetPllType(InstancePtr, QuadId, XVPHY_DIR_RX, ChId);
		switch (PllType) {
			case XVPHY_PLL_TYPE_QPLL:
			case XVPHY_PLL_TYPE_QPLL0:
			case XVPHY_PLL_TYPE_PLL0:
				ChIdPll = XVPHY_CHANNEL_ID_CMN0;
				PllxClkOutDiv = 2;
				break;
			case XVPHY_PLL_TYPE_QPLL1:
			case XVPHY_PLL_TYPE_PLL1:
				ChIdPll = XVPHY_CHANNEL_ID_CMN1;
				PllxClkOutDiv = 2;
				break;
			default:
				ChIdPll = ChId;
				PllxClkOutDiv = 1;
				break;
		}
		PllxVcoRateMHz = XVphy_GetPllVcoFreqHz(InstancePtr, QuadId, ChIdPll,
				XVPHY_DIR_RX) / 1000000;
		PllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv;
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x116, &DrpVal);
		DrpVal &= ~(0x00FF);
		if (PllxClkOutMHz >= 14000) {
			DrpVal |= 0xD0;
		}
		else if (PllxClkOutMHz >= 12500) {
			DrpVal |= 0x90;
		}
		else if (PllxClkOutMHz >= 8187) {
			DrpVal |= 0x60;
		}
		else if (PllxClkOutMHz >= 5156) {
			DrpVal |= 0x40;
		}
		else {
			DrpVal |= 0x20;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x116, DrpVal);
        Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0xFB, &DrpVal);
        DrpVal &= ~(0x0030);
        if (PllxClkOutMHz >= 12500) {
		DrpVal |= 3 << 4;
        }
        else if (PllxClkOutMHz >= 8187) {
		DrpVal |= 2 << 4; 
        }
        else if (PllxClkOutMHz >= 5156) {
		DrpVal |= 1 << 4;
        }
        Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xFB, DrpVal);
		if (PllxClkOutMHz > 15250) {
			DrpVal = 0xB806;
		}
		else if (PllxClkOutMHz >= 12500) {
			DrpVal = 0x3006;
		}
		else if (PllxClkOutMHz >= 10000) {
			DrpVal = 0x3004;
		}
		else if (PllxClkOutMHz >= 8187) {
			DrpVal = 0x0104;
		}
		else if (PllxClkOutMHz >= 6500) {
			DrpVal = 0x3002;
		}
		else if (PllxClkOutMHz >= 5156) {
			DrpVal = 0x0102;
		}
		else if (PllxClkOutMHz >= 3500) {
			DrpVal = 0x0100;
		}
		else {
			DrpVal = 0x0301;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x75, DrpVal);
	}
	Status |= XVphy_Gtye4RxPllRefClkDiv1Reconfig(InstancePtr, QuadId, ChId);
	return Status;
}
u32 XVphy_Gtye4RxChReconfig ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId ChId ) { XVphy_Channel * ChPtr ; u16 DrpVal ; u16 WriteVal ; u8 CfgIndex ; XVphy_ChannelId ChIdPll ; XVphy_PllType PllType ; u32 PllxVcoRateMHz ; u32 PllxClkOutMHz ; u32 PllxClkOutDiv ; u32 Status = XST_SUCCESS ; u64 LineRateHz ; ChPtr = & InstancePtr -> Quads [ QuadId ] . Plls [ XVPHY_CH2IDX ( ChId ) ] ; for ( CfgIndex = 0 ; CfgIndex < 5 ; CfgIndex ++ ) { DrpVal = ChPtr -> PllParams . Cdr [ CfgIndex ] ; if ( ! DrpVal ) { continue ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , XVPHY_DRP_RXCDR_CFG ( CfgIndex ) , DrpVal ) ; if ( CfgIndex == 2 ) { Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , XVPHY_DRP_RXCDR_CFG_GEN3 ( CfgIndex ) , DrpVal ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0x135 , & DrpVal ) ; DrpVal &= ~ ( 0x3FF ) ; DrpVal |= ChPtr -> PllParams . Cdr [ CfgIndex ] & 0x3FF ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x135 , DrpVal ) ; } } if ( InstancePtr -> Config . RxProtocol == XVPHY_PROTOCOL_DP ) { LineRateHz = XVphy_GetLineRateHz ( InstancePtr , QuadId , ChId ) ; if ( LineRateHz == XVPHY_DP_LINK_RATE_HZ_810GBPS ) { Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x11 , 0x12 ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x135 , 0x12 ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0xA5 , 0x12 ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x11C , 0x12 ) ; } else { Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x11 , 0x1A ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x135 , 0x1A ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0xA5 , 0x1A ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x11C , 0x1A ) ; } } if ( XVphy_IsHDMI ( InstancePtr , XVPHY_DIR_RX ) ) { Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0x66 , & DrpVal ) ; DrpVal &= ~ ( 0x3 ) ; WriteVal = ( Xvphy_DrpEncodeIntDataWidth ( ChPtr -> RxIntDataWidth ) & 0x3 ) ; DrpVal |= WriteVal ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x66 , DrpVal ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0x03 , & DrpVal ) ; DrpVal &= ~ ( 0x1E0 ) ; WriteVal = ( Xvphy_DrpEncodeDataWidth ( ChPtr -> RxDataWidth ) & 0xF ) ; WriteVal <<= 5 ; DrpVal |= WriteVal ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x03 , DrpVal ) ; PllType = XVphy_GetPllType ( InstancePtr , QuadId , XVPHY_DIR_RX , ChId ) ; switch ( PllType ) { case XVPHY_PLL_TYPE_QPLL : case XVPHY_PLL_TYPE_QPLL0 : case XVPHY_PLL_TYPE_PLL0 : ChIdPll = XVPHY_CHANNEL_ID_CMN0 ; PllxClkOutDiv = 2 ; break ; case XVPHY_PLL_TYPE_QPLL1 : case XVPHY_PLL_TYPE_PLL1 : ChIdPll = XVPHY_CHANNEL_ID_CMN1 ; PllxClkOutDiv = 2 ; break ; default : ChIdPll = ChId ; PllxClkOutDiv = 1 ; break ; } PllxVcoRateMHz = XVphy_GetPllVcoFreqHz ( InstancePtr , QuadId , ChIdPll , XVPHY_DIR_RX ) / 1000000 ; PllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0x116 , & DrpVal ) ; DrpVal &= ~ ( 0x00FF ) ; if ( PllxClkOutMHz >= 14000 ) { DrpVal |= 0xD0 ; } else if ( PllxClkOutMHz >= 12500 ) { DrpVal |= 0x90 ; } else if ( PllxClkOutMHz >= 8187 ) { DrpVal |= 0x60 ; } else if ( PllxClkOutMHz >= 5156 ) { DrpVal |= 0x40 ; } else { DrpVal |= 0x20 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x116 , DrpVal ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0xFB , & DrpVal ) ; DrpVal &= ~ ( 0x0030 ) ; if ( PllxClkOutMHz >= 12500 ) { DrpVal |= 3 << 4 ; } else if ( PllxClkOutMHz >= 8187 ) { DrpVal |= 2 << 4 ; } else if ( PllxClkOutMHz >= 5156 ) { DrpVal |= 1 << 4 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0xFB , DrpVal ) ; if ( PllxClkOutMHz > 15250 ) { DrpVal = 0xB806 ; } else if ( PllxClkOutMHz >= 12500 ) { DrpVal = 0x3006 ; } else if ( PllxClkOutMHz >= 10000 ) { DrpVal = 0x3004 ; } else if ( PllxClkOutMHz >= 8187 ) { DrpVal = 0x0104 ; } else if ( PllxClkOutMHz >= 6500 ) { DrpVal = 0x3002 ; } else if ( PllxClkOutMHz >= 5156 ) { DrpVal = 0x0102 ; } else if ( PllxClkOutMHz >= 3500 ) { DrpVal = 0x0100 ; } else { DrpVal = 0x0301 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x75 , DrpVal ) ; } Status |= XVphy_Gtye4RxPllRefClkDiv1Reconfig ( InstancePtr , QuadId , ChId ) ; return Status ; }
This function will configure the channel's RX settings.
This function will configure the channel ' s RX settings .
/* RXCDR_CFG(CfgIndex) */ /* Don't modify RX_CDR configuration. */ /* RXCDR_CFG2_GEN2 */ /* Modify RXCDR_CFG3 for DP */ /* RXCDR_CFG3 */ /* RXCDR_CFG3_GEN2 */ /* RXCDR_CFG3_GEN3 */ /* RXCDR_CFG3_GEN4 */ /* RXCDR_CFG3 */ /* RXCDR_CFG3_GEN2 */ /* RXCDR_CFG3_GEN3 */ /* RXCDR_CFG3_GEN4 */ /* RX_INT_DATAWIDTH */ /* RX_DATA_WIDTH */ /* Determine PLL type. */ /* Determine which channel(s) to operate on. */ /* CH_HSPMUX_RX */ /* Write new DRP register value for CH_HSPMUX_RX. */ /* PREIQ_FREQ_BST */ /* LPM Mode */ /* Write new DRP register value for PREIQ_FREQ_BST. */ /* RXPI_CFG0 */ /* Write new DRP register value for RXPI_CFG0. */