src/dpdk/drivers/net/ixgbe/base/ixgbe_x550.c
void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
{
	u32 rxctrl, pfdtxgswc;
	s32 status;
	struct ixgbe_hic_disable_rxen fw_cmd;

	DEBUGFUNC("ixgbe_enable_rx_dma_x550");

	rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
	if (rxctrl & IXGBE_RXCTRL_RXEN) {
		pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
		if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
			pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
			IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
			hw->mac.set_lben = true;
		} else {
			hw->mac.set_lben = false;
		}

		fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
		fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
		fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
		fw_cmd.port_number = (u8)hw->bus.lan_id;

		status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
					sizeof(struct ixgbe_hic_disable_rxen),
					IXGBE_HI_COMMAND_TIMEOUT, true);

		/* If we fail - disable RX using register write */
		if (status) {
			rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
			if (rxctrl & IXGBE_RXCTRL_RXEN) {
				rxctrl &= ~IXGBE_RXCTRL_RXEN;
				IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
			}
		}
	}
}
/**
 * ixgbe_disable_rx_x550 - Disable RX unit
 * @hw: pointer to hardware structure
 *
 * Enables the Rx DMA unit for x550
 **/
Disable RX unit
@hw: pointer to hardware structure

Enables the Rx DMA unit for x550
Disable RX unit @hw : pointer to hardware structure Enables the Rx DMA unit for x550
void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
{
	u32 rxctrl, pfdtxgswc;
	s32 status;
	struct ixgbe_hic_disable_rxen fw_cmd;
	DEBUGFUNC("ixgbe_enable_rx_dma_x550");
	rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
	if (rxctrl & IXGBE_RXCTRL_RXEN) {
		pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
		if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
			pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
			IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
			hw->mac.set_lben = true;
		} else {
			hw->mac.set_lben = false;
		}
		fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
		fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
		fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
		fw_cmd.port_number = (u8)hw->bus.lan_id;
		status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
					sizeof(struct ixgbe_hic_disable_rxen),
					IXGBE_HI_COMMAND_TIMEOUT, true);
		if (status) {
			rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
			if (rxctrl & IXGBE_RXCTRL_RXEN) {
				rxctrl &= ~IXGBE_RXCTRL_RXEN;
				IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
			}
		}
	}
}
void ixgbe_disable_rx_x550 ( struct ixgbe_hw * hw ) { u32 rxctrl , pfdtxgswc ; s32 status ; struct ixgbe_hic_disable_rxen fw_cmd ; DEBUGFUNC ( " " ) ; rxctrl = IXGBE_READ_REG ( hw , IXGBE_RXCTRL ) ; if ( rxctrl & IXGBE_RXCTRL_RXEN ) { pfdtxgswc = IXGBE_READ_REG ( hw , IXGBE_PFDTXGSWC ) ; if ( pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN ) { pfdtxgswc &= ~ IXGBE_PFDTXGSWC_VT_LBEN ; IXGBE_WRITE_REG ( hw , IXGBE_PFDTXGSWC , pfdtxgswc ) ; hw -> mac . set_lben = true ; } else { hw -> mac . set_lben = false ; } fw_cmd . hdr . cmd = FW_DISABLE_RXEN_CMD ; fw_cmd . hdr . buf_len = FW_DISABLE_RXEN_LEN ; fw_cmd . hdr . checksum = FW_DEFAULT_CHECKSUM ; fw_cmd . port_number = ( u8 ) hw -> bus . lan_id ; status = ixgbe_host_interface_command ( hw , ( u32 * ) & fw_cmd , sizeof ( struct ixgbe_hic_disable_rxen ) , IXGBE_HI_COMMAND_TIMEOUT , true ) ; if ( status ) { rxctrl = IXGBE_READ_REG ( hw , IXGBE_RXCTRL ) ; if ( rxctrl & IXGBE_RXCTRL_RXEN ) { rxctrl &= ~ IXGBE_RXCTRL_RXEN ; IXGBE_WRITE_REG ( hw , IXGBE_RXCTRL , rxctrl ) ; } } } }
ixgbe_disable_rx_x550 - Disable RX unit
 @hw: pointer to hardware structure
ixgbe_disable_rx_x550 - Disable RX unit @hw : pointer to hardware structure
/* If we fail - disable RX using register write */