XilinxProcessorIPLib/drivers/aiengine/src/tile/xaietile_strm.c
void XAieTile_ShimStrmMuxConfig(XAieGbl_Tile *TileInstPtr, u32 Port, u32 Input)
{
	u32 FldVal;

	XAie_AssertNonvoid(TileInstPtr != XAIE_NULL);
	XAie_AssertNonvoid(TileInstPtr->TileType == XAIEGBL_TILE_TYPE_SHIMNOC);

	FldVal = Input << ShimStrmMuxCfg.Port[Port].Lsb;
	XAieGbl_MaskWrite32(TileInstPtr->TileAddr + ShimStrmMuxCfg.CtrlOff,
			ShimStrmMuxCfg.Port[Port].Mask, FldVal);
}
/*****************************************************************************/
/**
*
* This API sets up the mux configuraiton for Shim.
*
* @param	TileInstPtr - Pointer to the Tile instance.
* @param	Port: Should be one of XAIETILE_SHIM_STRM_MUX_SOUTH2,
* XAIETILE_SHIM_STRM_MUX_SOUTH3, XAIETILE_SHIM_STRM_MUX_SOUTH6,
* or XAIETILE_SHIM_STRM_MUX_SOUTH7
* @param	Input: Should be one of XAIETILE_SHIM_STRM_MUX_PL,
* XAIETILE_SHIM_STRM_MUX_DMA, or XAIETILE_SHIM_STRM_MUX_NOC.
*
* @return	None.
*
* @note		None.
*
*******************************************************************************/
This API sets up the mux configuraiton for Shim.
This API sets up the mux configuraiton for Shim .
void XAieTile_ShimStrmMuxConfig(XAieGbl_Tile *TileInstPtr, u32 Port, u32 Input)
{
	u32 FldVal;
	XAie_AssertNonvoid(TileInstPtr != XAIE_NULL);
	XAie_AssertNonvoid(TileInstPtr->TileType == XAIEGBL_TILE_TYPE_SHIMNOC);
	FldVal = Input << ShimStrmMuxCfg.Port[Port].Lsb;
	XAieGbl_MaskWrite32(TileInstPtr->TileAddr + ShimStrmMuxCfg.CtrlOff,
			ShimStrmMuxCfg.Port[Port].Mask, FldVal);
}
void XAieTile_ShimStrmMuxConfig ( XAieGbl_Tile * TileInstPtr , u32 Port , u32 Input ) { u32 FldVal ; XAie_AssertNonvoid ( TileInstPtr != XAIE_NULL ) ; XAie_AssertNonvoid ( TileInstPtr -> TileType == XAIEGBL_TILE_TYPE_SHIMNOC ) ; FldVal = Input << ShimStrmMuxCfg . Port [ Port ] . Lsb ; XAieGbl_MaskWrite32 ( TileInstPtr -> TileAddr + ShimStrmMuxCfg . CtrlOff , ShimStrmMuxCfg . Port [ Port ] . Mask , FldVal ) ; }
This API sets up the mux configuraiton for Shim.
This API sets up the mux configuraiton for Shim .