XilinxProcessorIPLib/drivers/dp12txss/examples/src/kcu/xdptxss_kcu105.c
void Dprx_InterruptHandlerLinkBW(void *InstancePtr)
{
	u32 Status;
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,0x144, 0xFFF);
	only_tx_active = 0;
	gt_stable = 0;
    PLLRefClkSel (&VPhy_Instance, DpRxSsInst.UsrOpt.LinkRate);
    switch(DpRxSsInst.UsrOpt.LinkRate)
    {
		case 0x6:
			if(is_TX_CPLL) {
			  XVphy_PllInitialize(
				&VPhy_Instance, 0, XVPHY_CHANNEL_ID_CHA,
				ONBOARD_REF_CLK, DP159_FORWARDED_CLK,
				XVPHY_PLL_TYPE_CPLL, XVPHY_PLL_TYPE_CPLL);
			} else {
			  XVphy_PllInitialize(
			    &VPhy_Instance, 0, XVPHY_CHANNEL_ID_CHA,
				ONBOARD_REF_CLK, DP159_FORWARDED_CLK,
				XVPHY_PLL_TYPE_QPLL1, XVPHY_PLL_TYPE_CPLL);
			}
		break;

		default:
			if(is_TX_CPLL) {
			XVphy_PllInitialize(
			  &VPhy_Instance, 0, XVPHY_CHANNEL_ID_CHA,
			  ONBOARD_REF_CLK, DP159_FORWARDED_CLK,
			  XVPHY_PLL_TYPE_CPLL, XVPHY_PLL_TYPE_CPLL);
			} else {
			XVphy_PllInitialize(
			  &VPhy_Instance, 0, XVPHY_CHANNEL_ID_CHA,
			  ONBOARD_REF_CLK, DP159_FORWARDED_CLK,
			  XVPHY_PLL_TYPE_QPLL1, XVPHY_PLL_TYPE_CPLL);
			}
		break;
     }

     Status = XVphy_ClkInitialize(&VPhy_Instance, 0,
								 XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX);

     if (Status != XST_SUCCESS) {
         xdbg_printf (XDBG_DEBUG_GENERAL,
	"+++++++ RX GT configuration encountered an error (TP1) +++++++\r\n");
     }
//     Xil_DCacheFlush();
     initial_value = DpRxSsInst.UsrOpt.LinkRate;
}
//this is a handler in TP1
this is a handler in TP1
this is a handler in TP1
void Dprx_InterruptHandlerLinkBW(void *InstancePtr)
{
	u32 Status;
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,0x144, 0xFFF);
	only_tx_active = 0;
	gt_stable = 0;
    PLLRefClkSel (&VPhy_Instance, DpRxSsInst.UsrOpt.LinkRate);
    switch(DpRxSsInst.UsrOpt.LinkRate)
    {
		case 0x6:
			if(is_TX_CPLL) {
			  XVphy_PllInitialize(
				&VPhy_Instance, 0, XVPHY_CHANNEL_ID_CHA,
				ONBOARD_REF_CLK, DP159_FORWARDED_CLK,
				XVPHY_PLL_TYPE_CPLL, XVPHY_PLL_TYPE_CPLL);
			} else {
			  XVphy_PllInitialize(
			    &VPhy_Instance, 0, XVPHY_CHANNEL_ID_CHA,
				ONBOARD_REF_CLK, DP159_FORWARDED_CLK,
				XVPHY_PLL_TYPE_QPLL1, XVPHY_PLL_TYPE_CPLL);
			}
		break;
		default:
			if(is_TX_CPLL) {
			XVphy_PllInitialize(
			  &VPhy_Instance, 0, XVPHY_CHANNEL_ID_CHA,
			  ONBOARD_REF_CLK, DP159_FORWARDED_CLK,
			  XVPHY_PLL_TYPE_CPLL, XVPHY_PLL_TYPE_CPLL);
			} else {
			XVphy_PllInitialize(
			  &VPhy_Instance, 0, XVPHY_CHANNEL_ID_CHA,
			  ONBOARD_REF_CLK, DP159_FORWARDED_CLK,
			  XVPHY_PLL_TYPE_QPLL1, XVPHY_PLL_TYPE_CPLL);
			}
		break;
     }
     Status = XVphy_ClkInitialize(&VPhy_Instance, 0,
								 XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX);
     if (Status != XST_SUCCESS) {
         xdbg_printf (XDBG_DEBUG_GENERAL,
	"+++++++ RX GT configuration encountered an error (TP1) +++++++\r\n");
     }
     initial_value = DpRxSsInst.UsrOpt.LinkRate;
}
void Dprx_InterruptHandlerLinkBW ( void * InstancePtr ) { u32 Status ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , 0x144 , 0xFFF ) ; only_tx_active = 0 ; gt_stable = 0 ; PLLRefClkSel ( & VPhy_Instance , DpRxSsInst . UsrOpt . LinkRate ) ; switch ( DpRxSsInst . UsrOpt . LinkRate ) { case 0x6 : if ( is_TX_CPLL ) { XVphy_PllInitialize ( & VPhy_Instance , 0 , XVPHY_CHANNEL_ID_CHA , ONBOARD_REF_CLK , DP159_FORWARDED_CLK , XVPHY_PLL_TYPE_CPLL , XVPHY_PLL_TYPE_CPLL ) ; } else { XVphy_PllInitialize ( & VPhy_Instance , 0 , XVPHY_CHANNEL_ID_CHA , ONBOARD_REF_CLK , DP159_FORWARDED_CLK , XVPHY_PLL_TYPE_QPLL1 , XVPHY_PLL_TYPE_CPLL ) ; } break ; default : if ( is_TX_CPLL ) { XVphy_PllInitialize ( & VPhy_Instance , 0 , XVPHY_CHANNEL_ID_CHA , ONBOARD_REF_CLK , DP159_FORWARDED_CLK , XVPHY_PLL_TYPE_CPLL , XVPHY_PLL_TYPE_CPLL ) ; } else { XVphy_PllInitialize ( & VPhy_Instance , 0 , XVPHY_CHANNEL_ID_CHA , ONBOARD_REF_CLK , DP159_FORWARDED_CLK , XVPHY_PLL_TYPE_QPLL1 , XVPHY_PLL_TYPE_CPLL ) ; } break ; } Status = XVphy_ClkInitialize ( & VPhy_Instance , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX ) ; if ( Status != XST_SUCCESS ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " ) ; } initial_value = DpRxSsInst . UsrOpt . LinkRate ; }
this is a handler in TP1
this is a handler in TP1
//     Xil_DCacheFlush();