XilinxProcessorIPLib/drivers/intc/src/xintc.c
void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id)
{
	u32 Mask;
	XIntc_Config *CfgPtr;

	/*
	 * Assert the arguments
	 */
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	if (Id > 31) {
		/* Enable user required Id in Slave controller */
		CfgPtr = XIntc_LookupConfig(Id/32);
		if (CfgPtr == NULL) {
			return;
		}

		/* Convert from integer id to bit mask */
		Mask = XIntc_BitPosMask[(Id%32)];

		XIntc_Out32(CfgPtr->BaseAddress + XIN_IAR_OFFSET, Mask);
	} else {
		/*
		 * The Id is used to create the appropriate mask for the
		 * desired bit position.
		 */
		Mask = XIntc_BitPosMask[Id];

		/*
		 * Acknowledge the selected interrupt source, no read of the
		 * acknowledge register is necessary since only the bits set
		 * in the mask will be affected by the write
		 */
		XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Mask);
	}
}
/*****************************************************************************/
/**
*
* Acknowledges the interrupt source provided as the argument Id. When the
* interrupt is acknowledged, it causes the interrupt controller to clear its
* interrupt condition.In Cascade mode, acknowledges corresponding interrupt
* source of Slave controllers depending on the Id.
*
* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
* @param	Id contains the ID of the interrupt source and should be in the
*		range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being
*    		the highest priority interrupt.
*
* @return	None.
*
* @note		None.
*
****************************************************************************/
Acknowledges the interrupt source provided as the argument Id. When the
interrupt is acknowledged, it causes the interrupt controller to clear its
interrupt condition.In Cascade mode, acknowledges corresponding interrupt
source of Slave controllers depending on the Id.
Acknowledges the interrupt source provided as the argument Id . When the interrupt is acknowledged it causes the interrupt controller to clear its interrupt condition . In Cascade mode acknowledges corresponding interrupt source of Slave controllers depending on the Id .
void XIntc_Acknowledge(XIntc * InstancePtr, u8 Id)
{
	u32 Mask;
	XIntc_Config *CfgPtr;
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	if (Id > 31) {
		CfgPtr = XIntc_LookupConfig(Id/32);
		if (CfgPtr == NULL) {
			return;
		}
		Mask = XIntc_BitPosMask[(Id%32)];
		XIntc_Out32(CfgPtr->BaseAddress + XIN_IAR_OFFSET, Mask);
	} else {
		Mask = XIntc_BitPosMask[Id];
		XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Mask);
	}
}
void XIntc_Acknowledge ( XIntc * InstancePtr , u8 Id ) { u32 Mask ; XIntc_Config * CfgPtr ; Xil_AssertVoid ( InstancePtr != NULL ) ; Xil_AssertVoid ( Id < XPAR_INTC_MAX_NUM_INTR_INPUTS ) ; Xil_AssertVoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; if ( Id > 31 ) { CfgPtr = XIntc_LookupConfig ( Id / 32 ) ; if ( CfgPtr == NULL ) { return ; } Mask = XIntc_BitPosMask [ ( Id % 32 ) ] ; XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_IAR_OFFSET , Mask ) ; } else { Mask = XIntc_BitPosMask [ Id ] ; XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_IAR_OFFSET , Mask ) ; } }
Acknowledges the interrupt source provided as the argument Id.
Acknowledges the interrupt source provided as the argument Id .
/*
	 * Assert the arguments
	 */ /* Enable user required Id in Slave controller */ /* Convert from integer id to bit mask */ /*
		 * The Id is used to create the appropriate mask for the
		 * desired bit position.
		 */ /*
		 * Acknowledge the selected interrupt source, no read of the
		 * acknowledge register is necessary since only the bits set
		 * in the mask will be affected by the write
		 */