XilinxProcessorIPLib/drivers/nandps/src/xnandps.c
static void XNandPs_EccSetCfg(XNandPs *InstancePtr, u32 EccConfig)
{
	/*
	 * Check the busy status of the ECC block
	 */
	while (XNandPs_ReadReg(InstancePtr->Config.SmcBase +
		XNANDPS_ECC_STATUS_OFFSET(XNANDPS_IF1_ECC_OFFSET)) &
		XNANDPS_ECC_STATUS_MASK);
	/*
	 * Write ECC configuration register
	 */
	XNandPs_WriteReg(InstancePtr->Config.SmcBase +
		(XNANDPS_ECC_MEMCFG_OFFSET(XNANDPS_IF1_ECC_OFFSET)),
		EccConfig);
}
/*****************************************************************************/
/**
*
* This function initializes the HW ECC block based on flash.
*
* @param	InstancePtr is a pointer to the XNandPs instance.
* @param	EccConfig is the value of ECC config to update.
*
* @return	None
*
* @note		None
*
*****************************************************************************/
This function initializes the HW ECC block based on flash.
This function initializes the HW ECC block based on flash .
static void XNandPs_EccSetCfg(XNandPs *InstancePtr, u32 EccConfig)
{
	while (XNandPs_ReadReg(InstancePtr->Config.SmcBase +
		XNANDPS_ECC_STATUS_OFFSET(XNANDPS_IF1_ECC_OFFSET)) &
		XNANDPS_ECC_STATUS_MASK);
	XNandPs_WriteReg(InstancePtr->Config.SmcBase +
		(XNANDPS_ECC_MEMCFG_OFFSET(XNANDPS_IF1_ECC_OFFSET)),
		EccConfig);
}
static void XNandPs_EccSetCfg ( XNandPs * InstancePtr , u32 EccConfig ) { while ( XNandPs_ReadReg ( InstancePtr -> Config . SmcBase + XNANDPS_ECC_STATUS_OFFSET ( XNANDPS_IF1_ECC_OFFSET ) ) & XNANDPS_ECC_STATUS_MASK ) ; XNandPs_WriteReg ( InstancePtr -> Config . SmcBase + ( XNANDPS_ECC_MEMCFG_OFFSET ( XNANDPS_IF1_ECC_OFFSET ) ) , EccConfig ) ; }
This function initializes the HW ECC block based on flash.
This function initializes the HW ECC block based on flash .
/*
	 * Check the busy status of the ECC block
	 */ /*
	 * Write ECC configuration register
	 */