XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_hdmi_intr.c
void XHdmiphy1_HdmiRxGpoRisingEdgeHandler(XHdmiphy1 *InstancePtr)
{
	u8 Id, Id0, Id1;
	u8 CfgValComp;

	/* Compare the current and next CFG values */
	CfgValComp = XHdmiphy1_CheckLineRateCfg(InstancePtr, 0,
						XHDMIPHY1_CHANNEL_ID_CH1, XHDMIPHY1_DIR_RX);

	if (CfgValComp) {
		XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_RXGPO_RE, 0);
	} else {
		XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_RXGPO_RE, 1);
	}

	/* De-assert GPI port. */
	XHdmiphy1_SetGpi(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
			 XHDMIPHY1_DIR_RX, FALSE);

	/* Wait for GPO RX = 0 */
	while (XHdmiphy1_GetGpo(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
				XHDMIPHY1_DIR_RX));

	/* Configure RXRATE Port */
	XHdmiphy1_DirReconfig(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
			      XHDMIPHY1_DIR_RX);

	/* Deassert reset on GT Reset IP RX */
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, XHDMIPHY1_COMMON_INIT_REG,
			   (XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
					      XHDMIPHY1_COMMON_INIT_REG) & ~0x2));

	XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].RxState =
			XHDMIPHY1_GT_STATE_LOCK;
	}
}
/*****************************************************************************/
/**
* This function is the handler for events triggered by RX GPO Rising Edge.
*
* @param    InstancePtr is a pointer to the HDMIPHY instance.
*
* @return   None.
*
* @note     None.
*
******************************************************************************/
This function is the handler for events triggered by RX GPO Rising Edge.
This function is the handler for events triggered by RX GPO Rising Edge .
void XHdmiphy1_HdmiRxGpoRisingEdgeHandler(XHdmiphy1 *InstancePtr)
{
	u8 Id, Id0, Id1;
	u8 CfgValComp;
	CfgValComp = XHdmiphy1_CheckLineRateCfg(InstancePtr, 0,
						XHDMIPHY1_CHANNEL_ID_CH1, XHDMIPHY1_DIR_RX);
	if (CfgValComp) {
		XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_RXGPO_RE, 0);
	} else {
		XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_RXGPO_RE, 1);
	}
	XHdmiphy1_SetGpi(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
			 XHDMIPHY1_DIR_RX, FALSE);
	while (XHdmiphy1_GetGpo(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
				XHDMIPHY1_DIR_RX));
	XHdmiphy1_DirReconfig(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
			      XHDMIPHY1_DIR_RX);
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, XHDMIPHY1_COMMON_INIT_REG,
			   (XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
					      XHDMIPHY1_COMMON_INIT_REG) & ~0x2));
	XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].RxState =
			XHDMIPHY1_GT_STATE_LOCK;
	}
}
void XHdmiphy1_HdmiRxGpoRisingEdgeHandler ( XHdmiphy1 * InstancePtr ) { u8 Id , Id0 , Id1 ; u8 CfgValComp ; CfgValComp = XHdmiphy1_CheckLineRateCfg ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CH1 , XHDMIPHY1_DIR_RX ) ; if ( CfgValComp ) { XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_RXGPO_RE , 0 ) ; } else { XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_RXGPO_RE , 1 ) ; } XHdmiphy1_SetGpi ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_RX , FALSE ) ; while ( XHdmiphy1_GetGpo ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_RX ) ) ; XHdmiphy1_DirReconfig ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_RX ) ; XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_COMMON_INIT_REG , ( XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_COMMON_INIT_REG ) & ~ 0x2 ) ) ; XHdmiphy1_Ch2Ids ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . RxState = XHDMIPHY1_GT_STATE_LOCK ; } }
This function is the handler for events triggered by RX GPO Rising Edge.
This function is the handler for events triggered by RX GPO Rising Edge .
/* Compare the current and next CFG values */ /* De-assert GPI port. */ /* Wait for GPO RX = 0 */ /* Configure RXRATE Port */ /* Deassert reset on GT Reset IP RX */