XilinxProcessorIPLib/drivers/dp14txss/examples/src/pt_only/xdptxss_dp14_pt.c
u32 DpSs_PhyInit(u16 DeviceId)
{
#ifndef versal
	XVphy_Config *ConfigPtr;

	/* Obtain the device configuration for the DisplayPort RX Subsystem */
	ConfigPtr = XVphy_LookupConfig(DeviceId);
	if (!ConfigPtr) {
		return XST_FAILURE;
	}


	PLLRefClkSel (&VPhyInst, 0x14);

	XVphy_DpInitialize(&VPhyInst, ConfigPtr, 0,
			ONBOARD_REF_CLK,
			ONBOARD_REF_CLK,
			XVPHY_PLL_TYPE_QPLL1,
			XVPHY_PLL_TYPE_CPLL,
			0x14);
	//set the default vswing and pe for v0po

    //setting vswing
    XVphy_SetTxVoltageSwing(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1,
		XVPHY_GTHE4_DIFF_SWING_DP_V0P0);
    XVphy_SetTxVoltageSwing(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2,
		XVPHY_GTHE4_DIFF_SWING_DP_V0P0);
    XVphy_SetTxVoltageSwing(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3,
		XVPHY_GTHE4_DIFF_SWING_DP_V0P0);
    XVphy_SetTxVoltageSwing(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4,
		XVPHY_GTHE4_DIFF_SWING_DP_V0P0);

    //setting postcursor
    XVphy_SetTxPostCursor(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1,
		XVPHY_GTHE4_PREEMP_DP_L0);
    XVphy_SetTxPostCursor(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2,
		XVPHY_GTHE4_PREEMP_DP_L0);
    XVphy_SetTxPostCursor(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3,
		XVPHY_GTHE4_PREEMP_DP_L0);
    XVphy_SetTxPostCursor(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4,
		XVPHY_GTHE4_PREEMP_DP_L0);


#if TX_BUFFER_BYPASS
    XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1, 0x3E, DIVIDER_540);
    XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2, 0x3E, DIVIDER_540);
    XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3, 0x3E, DIVIDER_540);
    XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4, 0x3E, DIVIDER_540);
#endif

	PHY_Two_byte_set (&VPhyInst, SET_RX_TO_2BYTE, SET_TX_TO_2BYTE);

     XVphy_ResetGtPll(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_TX,(TRUE));
     XVphy_BufgGtReset(&VPhyInst, XVPHY_DIR_TX,(TRUE));

     XVphy_ResetGtPll(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_TX,(FALSE));
     XVphy_BufgGtReset(&VPhyInst, XVPHY_DIR_TX,(FALSE));


     XVphy_ResetGtPll(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX,(TRUE));
     XVphy_BufgGtReset(&VPhyInst, XVPHY_DIR_RX,(TRUE));

     XVphy_ResetGtPll(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX,(FALSE));
     XVphy_BufgGtReset(&VPhyInst, XVPHY_DIR_RX,(FALSE));
#else

     //Setting Vswing on TX
     GtCtrl (0x1F00,(5 << 8), 1);

#endif

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function configures Video Phy.
*
* @param    None.
*
* @return
*        - XST_SUCCESS if Video Phy configured successfully.
*        - XST_FAILURE, otherwise.
*
* @note        None.
*
******************************************************************************/
This function configures Video Phy.
This function configures Video Phy .
u32 DpSs_PhyInit(u16 DeviceId)
{
#ifndef versal
	XVphy_Config *ConfigPtr;
	ConfigPtr = XVphy_LookupConfig(DeviceId);
	if (!ConfigPtr) {
		return XST_FAILURE;
	}
	PLLRefClkSel (&VPhyInst, 0x14);
	XVphy_DpInitialize(&VPhyInst, ConfigPtr, 0,
			ONBOARD_REF_CLK,
			ONBOARD_REF_CLK,
			XVPHY_PLL_TYPE_QPLL1,
			XVPHY_PLL_TYPE_CPLL,
			0x14);
    XVphy_SetTxVoltageSwing(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1,
		XVPHY_GTHE4_DIFF_SWING_DP_V0P0);
    XVphy_SetTxVoltageSwing(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2,
		XVPHY_GTHE4_DIFF_SWING_DP_V0P0);
    XVphy_SetTxVoltageSwing(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3,
		XVPHY_GTHE4_DIFF_SWING_DP_V0P0);
    XVphy_SetTxVoltageSwing(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4,
		XVPHY_GTHE4_DIFF_SWING_DP_V0P0);
    XVphy_SetTxPostCursor(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1,
		XVPHY_GTHE4_PREEMP_DP_L0);
    XVphy_SetTxPostCursor(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2,
		XVPHY_GTHE4_PREEMP_DP_L0);
    XVphy_SetTxPostCursor(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3,
		XVPHY_GTHE4_PREEMP_DP_L0);
    XVphy_SetTxPostCursor(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4,
		XVPHY_GTHE4_PREEMP_DP_L0);
#if TX_BUFFER_BYPASS
    XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH1, 0x3E, DIVIDER_540);
    XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH2, 0x3E, DIVIDER_540);
    XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH3, 0x3E, DIVIDER_540);
    XVphy_DrpWr(&VPhyInst, 0, XVPHY_CHANNEL_ID_CH4, 0x3E, DIVIDER_540);
#endif
	PHY_Two_byte_set (&VPhyInst, SET_RX_TO_2BYTE, SET_TX_TO_2BYTE);
     XVphy_ResetGtPll(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_TX,(TRUE));
     XVphy_BufgGtReset(&VPhyInst, XVPHY_DIR_TX,(TRUE));
     XVphy_ResetGtPll(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_TX,(FALSE));
     XVphy_BufgGtReset(&VPhyInst, XVPHY_DIR_TX,(FALSE));
     XVphy_ResetGtPll(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX,(TRUE));
     XVphy_BufgGtReset(&VPhyInst, XVPHY_DIR_RX,(TRUE));
     XVphy_ResetGtPll(&VPhyInst, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX,(FALSE));
     XVphy_BufgGtReset(&VPhyInst, XVPHY_DIR_RX,(FALSE));
#else
     GtCtrl (0x1F00,(5 << 8), 1);
#endif
	return XST_SUCCESS;
}
u32 DpSs_PhyInit ( u16 DeviceId ) { #ifndef versal XVphy_Config * ConfigPtr ; ConfigPtr = XVphy_LookupConfig ( DeviceId ) ; if ( ! ConfigPtr ) { return XST_FAILURE ; } PLLRefClkSel ( & VPhyInst , 0x14 ) ; XVphy_DpInitialize ( & VPhyInst , ConfigPtr , 0 , ONBOARD_REF_CLK , ONBOARD_REF_CLK , XVPHY_PLL_TYPE_QPLL1 , XVPHY_PLL_TYPE_CPLL , 0x14 ) ; XVphy_SetTxVoltageSwing ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH1 , XVPHY_GTHE4_DIFF_SWING_DP_V0P0 ) ; XVphy_SetTxVoltageSwing ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH2 , XVPHY_GTHE4_DIFF_SWING_DP_V0P0 ) ; XVphy_SetTxVoltageSwing ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH3 , XVPHY_GTHE4_DIFF_SWING_DP_V0P0 ) ; XVphy_SetTxVoltageSwing ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH4 , XVPHY_GTHE4_DIFF_SWING_DP_V0P0 ) ; XVphy_SetTxPostCursor ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH1 , XVPHY_GTHE4_PREEMP_DP_L0 ) ; XVphy_SetTxPostCursor ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH2 , XVPHY_GTHE4_PREEMP_DP_L0 ) ; XVphy_SetTxPostCursor ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH3 , XVPHY_GTHE4_PREEMP_DP_L0 ) ; XVphy_SetTxPostCursor ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH4 , XVPHY_GTHE4_PREEMP_DP_L0 ) ; #if TX_BUFFER_BYPASS XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH1 , 0x3E , DIVIDER_540 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH2 , 0x3E , DIVIDER_540 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH3 , 0x3E , DIVIDER_540 ) ; XVphy_DrpWr ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CH4 , 0x3E , DIVIDER_540 ) ; #endif PHY_Two_byte_set ( & VPhyInst , SET_RX_TO_2BYTE , SET_TX_TO_2BYTE ) ; XVphy_ResetGtPll ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_TX , ( TRUE ) ) ; XVphy_BufgGtReset ( & VPhyInst , XVPHY_DIR_TX , ( TRUE ) ) ; XVphy_ResetGtPll ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_TX , ( FALSE ) ) ; XVphy_BufgGtReset ( & VPhyInst , XVPHY_DIR_TX , ( FALSE ) ) ; XVphy_ResetGtPll ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX , ( TRUE ) ) ; XVphy_BufgGtReset ( & VPhyInst , XVPHY_DIR_RX , ( TRUE ) ) ; XVphy_ResetGtPll ( & VPhyInst , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX , ( FALSE ) ) ; XVphy_BufgGtReset ( & VPhyInst , XVPHY_DIR_RX , ( FALSE ) ) ; #else GtCtrl ( 0x1F00 , ( 5 << 8 ) , 1 ) ; #endif return XST_SUCCESS ; }
This function configures Video Phy.
This function configures Video Phy .
/* Obtain the device configuration for the DisplayPort RX Subsystem */ //set the default vswing and pe for v0po //setting vswing //setting postcursor //Setting Vswing on TX