src/dpdk/drivers/net/mlx4/mlx4_rxtx.c
static void
mlx4_txq_complete(struct txq *txq, const unsigned int elts_m,
		  struct mlx4_sq *sq)
{
	unsigned int elts_tail = txq->elts_tail;
	struct mlx4_cq *cq = &txq->mcq;
	volatile struct mlx4_cqe *cqe;
	uint32_t completed;
	uint32_t cons_index = cq->cons_index;
	volatile uint32_t *first_txbb;

	/*
	 * Traverse over all CQ entries reported and handle each WQ entry
	 * reported by them.
	 */
	do {
		cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
		if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
		    !!(cons_index & cq->cqe_cnt)))
			break;
#ifdef RTE_LIBRTE_MLX4_DEBUG
		/*
		 * Make sure we read the CQE after we read the ownership bit.
		 */
		rte_io_rmb();
		if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
			     MLX4_CQE_OPCODE_ERROR)) {
			volatile struct mlx4_err_cqe *cqe_err =
				(volatile struct mlx4_err_cqe *)cqe;
			ERROR("%p CQE error - vendor syndrome: 0x%x"
			      " syndrome: 0x%x\n",
			      (void *)txq, cqe_err->vendor_err,
			      cqe_err->syndrome);
			break;
		}
#endif /* RTE_LIBRTE_MLX4_DEBUG */
		cons_index++;
	} while (1);
	completed = (cons_index - cq->cons_index) * txq->elts_comp_cd_init;
	if (unlikely(!completed))
		return;
	/* First stamping address is the end of the last one. */
	first_txbb = (&(*txq->elts)[elts_tail & elts_m])->eocb;
	elts_tail += completed;
	/* The new tail element holds the end address. */
	sq->remain_size += mlx4_txq_stamp_freed_wqe(sq, first_txbb,
		(&(*txq->elts)[elts_tail & elts_m])->eocb);
	/* Update CQ consumer index. */
	cq->cons_index = cons_index;
	*cq->set_ci_db = rte_cpu_to_be_32(cons_index & MLX4_CQ_DB_CI_MASK);
	txq->elts_tail = elts_tail;
}
/**
 * Manage Tx completions.
 *
 * When sending a burst, mlx4_tx_burst() posts several WRs.
 * To improve performance, a completion event is only required once every
 * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
 * for other WRs, but this information would not be used anyway.
 *
 * @param txq
 *   Pointer to Tx queue structure.
 * @param elts_m
 *   Tx elements number mask.
 * @param sq
 *   Pointer to the SQ structure.
 */
Manage Tx completions.
When sending a burst, mlx4_tx_burst() posts several WRs.
To improve performance, a completion event is only required once every
MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
for other WRs, but this information would not be used anyway.

@param txq
Pointer to Tx queue structure.
@param elts_m
Tx elements number mask.
@param sq
Pointer to the SQ structure.
Manage Tx completions . When sending a burst mlx4_tx_burst () posts several WRs . To improve performance a completion event is only required once every MLX4_PMD_TX_PER_COMP_REQ sends . Doing so discards completion information for other WRs but this information would not be used anyway . @param txq Pointer to Tx queue structure . @param elts_m Tx elements number mask . @param sq Pointer to the SQ structure .
static void
mlx4_txq_complete(struct txq *txq, const unsigned int elts_m,
		  struct mlx4_sq *sq)
{
	unsigned int elts_tail = txq->elts_tail;
	struct mlx4_cq *cq = &txq->mcq;
	volatile struct mlx4_cqe *cqe;
	uint32_t completed;
	uint32_t cons_index = cq->cons_index;
	volatile uint32_t *first_txbb;
	do {
		cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
		if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
		    !!(cons_index & cq->cqe_cnt)))
			break;
#ifdef RTE_LIBRTE_MLX4_DEBUG
		rte_io_rmb();
		if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
			     MLX4_CQE_OPCODE_ERROR)) {
			volatile struct mlx4_err_cqe *cqe_err =
				(volatile struct mlx4_err_cqe *)cqe;
			ERROR("%p CQE error - vendor syndrome: 0x%x"
			      " syndrome: 0x%x\n",
			      (void *)txq, cqe_err->vendor_err,
			      cqe_err->syndrome);
			break;
		}
#endif 
		cons_index++;
	} while (1);
	completed = (cons_index - cq->cons_index) * txq->elts_comp_cd_init;
	if (unlikely(!completed))
		return;
	first_txbb = (&(*txq->elts)[elts_tail & elts_m])->eocb;
	elts_tail += completed;
	sq->remain_size += mlx4_txq_stamp_freed_wqe(sq, first_txbb,
		(&(*txq->elts)[elts_tail & elts_m])->eocb);
	cq->cons_index = cons_index;
	*cq->set_ci_db = rte_cpu_to_be_32(cons_index & MLX4_CQ_DB_CI_MASK);
	txq->elts_tail = elts_tail;
}
static void mlx4_txq_complete ( struct txq * txq , const unsigned int elts_m , struct mlx4_sq * sq ) { unsigned int elts_tail = txq -> elts_tail ; struct mlx4_cq * cq = & txq -> mcq ; volatile struct mlx4_cqe * cqe ; uint32_t completed ; uint32_t cons_index = cq -> cons_index ; volatile uint32_t * first_txbb ; do { cqe = ( volatile struct mlx4_cqe * ) mlx4_get_cqe ( cq , cons_index ) ; if ( unlikely ( ! ! ( cqe -> owner_sr_opcode & MLX4_CQE_OWNER_MASK ) ^ ! ! ( cons_index & cq -> cqe_cnt ) ) ) break ; #ifdef RTE_LIBRTE_MLX4_DEBUG rte_io_rmb ( ) ; if ( unlikely ( ( cqe -> owner_sr_opcode & MLX4_CQE_OPCODE_MASK ) == MLX4_CQE_OPCODE_ERROR ) ) { volatile struct mlx4_err_cqe * cqe_err = ( volatile struct mlx4_err_cqe * ) cqe ; ERROR ( " " " \n " , ( void * ) txq , cqe_err -> vendor_err , cqe_err -> syndrome ) ; break ; } #endif cons_index ++ ; } while ( 1 ) ; completed = ( cons_index - cq -> cons_index ) * txq -> elts_comp_cd_init ; if ( unlikely ( ! completed ) ) return ; first_txbb = ( & ( * txq -> elts ) [ elts_tail & elts_m ] ) -> eocb ; elts_tail += completed ; sq -> remain_size += mlx4_txq_stamp_freed_wqe ( sq , first_txbb , ( & ( * txq -> elts ) [ elts_tail & elts_m ] ) -> eocb ) ; cq -> cons_index = cons_index ; * cq -> set_ci_db = rte_cpu_to_be_32 ( cons_index & MLX4_CQ_DB_CI_MASK ) ; txq -> elts_tail = elts_tail ; }
Manage Tx completions.
Manage Tx completions .
/*
	 * Traverse over all CQ entries reported and handle each WQ entry
	 * reported by them.
	 */ /*
		 * Make sure we read the CQE after we read the ownership bit.
		 */ /* RTE_LIBRTE_MLX4_DEBUG */ /* First stamping address is the end of the last one. */ /* The new tail element holds the end address. */ /* Update CQ consumer index. */