host-drivers/base-driver/vca/plx87xx/plx_hw.c
int
plx_add_a_lut_entry(struct plx_device *xdev, dma_addr_t addr, size_t size,
			dma_addr_t *addr_out)
{
	u32 lower_re_map_offset;
	u32 higher_re_map_offset;
	u32 permission_offset = 0;
	u64 translation_mask = xdev->a_lut_manager.segment_size - 1;
	dma_addr_t addr_masked = addr & ~translation_mask;

	int i;
	int err;
	unsigned int entry_offset;
	u32 segments_num;
	u32 segment_id;
	u32 last_permission_reg = 0;

	spin_lock(&xdev->alm_lock);

	err = plx_alm_add_entry(&xdev->a_lut_manager, xdev->pdev, addr,
		size, &segment_id, &segments_num);
	if (err && err != -EEXIST) {
		goto failed;
	}

	if (err == 0) {
		for (i = segment_id; i < segment_id + segments_num; i++) {
			entry_offset = xdev->a_lut_array_base + plx_get_a_lut_entry_offset(i);

			lower_re_map_offset = entry_offset +
					  PLX_A_LUT_LOWER_RE_MAP_SUBARRAY_OFFSET;
			higher_re_map_offset = entry_offset +
					  PLX_A_LUT_HIGHER_RE_MAP_SUBARRAY_OFFSET;
			permission_offset = entry_offset +
					  PLX_A_LUT_PERMISSION_SUBARRAY_OFFSET;

			plx_mmio_write(&xdev->mmio, (u32)(addr_masked >> 32),
				higher_re_map_offset);
			dev_dbg(&xdev->pdev->dev, "%s writing %x : %x\n",
				__func__, (u32)(addr_masked >> 32), higher_re_map_offset);
			plx_mmio_write(&xdev->mmio, (u32)(addr_masked), lower_re_map_offset);
			dev_dbg(&xdev->pdev->dev, "%s writing %x : %x\n",
				__func__,(u32)(addr_masked), lower_re_map_offset);
			wmb();
			plx_mmio_write(&xdev->mmio, PLX_A_LUT_PERMISSION_READ_ENABLE |
					PLX_A_LUT_PERMISSION_WRITE_ENABLE,
					permission_offset);
			dev_dbg(&xdev->pdev->dev, "%s writing %x : %x\n",
					__func__,PLX_A_LUT_PERMISSION_READ_ENABLE |
					PLX_A_LUT_PERMISSION_WRITE_ENABLE,
					permission_offset);
			last_permission_reg = permission_offset;
			addr_masked += xdev->a_lut_manager.segment_size;
		}

		mb();
		/*
		 * This is barrier to check that last write to register end,
		 * Check that hardware configuration finished.
		 **/
		if (last_permission_reg)
			plx_mmio_read(&xdev->mmio, last_permission_reg);
	}
	spin_unlock(&xdev->alm_lock);

	*addr_out = segment_id * (u64)xdev->a_lut_manager.segment_size +
		(addr & translation_mask);

	dev_dbg(&xdev->pdev->dev,
			"%s map entry no %i original %llx translated %llx\n",
			__func__,
			segment_id,
			(u64)addr,
			(u64)*addr_out);

	return 0;

failed:
	spin_unlock(&xdev->alm_lock);
	return -ENOMEM;
}
/**
 * plx_add_lut_entry() - add entry to A LUT array
 * @xdev: pointer to plx_device instance
 * @addr: DMA address to access memory
 *
 * This function allows other side of NTB to access address @addr by adding
 * a lookup entry to A LUT array.
 *
 * RETURNS: DMA addres to be used by the other side of NTB to access
 * @dma_addr.
 *
 * */
add entry to A LUT array
@xdev: pointer to plx_device instance
@addr: DMA address to access memory

This function allows other side of NTB to access address @addr by adding
a lookup entry to A LUT array.

DMA addres to be used by the other side of NTB to access
@dma_addr.
add entry to A LUT array @xdev : pointer to plx_device instance @addr : DMA address to access memory This function allows other side of NTB to access address @addr by adding a lookup entry to A LUT array . DMA addres to be used by the other side of NTB to access @dma_addr .
int
plx_add_a_lut_entry(struct plx_device *xdev, dma_addr_t addr, size_t size,
			dma_addr_t *addr_out)
{
	u32 lower_re_map_offset;
	u32 higher_re_map_offset;
	u32 permission_offset = 0;
	u64 translation_mask = xdev->a_lut_manager.segment_size - 1;
	dma_addr_t addr_masked = addr & ~translation_mask;
	int i;
	int err;
	unsigned int entry_offset;
	u32 segments_num;
	u32 segment_id;
	u32 last_permission_reg = 0;
	spin_lock(&xdev->alm_lock);
	err = plx_alm_add_entry(&xdev->a_lut_manager, xdev->pdev, addr,
		size, &segment_id, &segments_num);
	if (err && err != -EEXIST) {
		goto failed;
	}
	if (err == 0) {
		for (i = segment_id; i < segment_id + segments_num; i++) {
			entry_offset = xdev->a_lut_array_base + plx_get_a_lut_entry_offset(i);
			lower_re_map_offset = entry_offset +
					  PLX_A_LUT_LOWER_RE_MAP_SUBARRAY_OFFSET;
			higher_re_map_offset = entry_offset +
					  PLX_A_LUT_HIGHER_RE_MAP_SUBARRAY_OFFSET;
			permission_offset = entry_offset +
					  PLX_A_LUT_PERMISSION_SUBARRAY_OFFSET;
			plx_mmio_write(&xdev->mmio, (u32)(addr_masked >> 32),
				higher_re_map_offset);
			dev_dbg(&xdev->pdev->dev, "%s writing %x : %x\n",
				__func__, (u32)(addr_masked >> 32), higher_re_map_offset);
			plx_mmio_write(&xdev->mmio, (u32)(addr_masked), lower_re_map_offset);
			dev_dbg(&xdev->pdev->dev, "%s writing %x : %x\n",
				__func__,(u32)(addr_masked), lower_re_map_offset);
			wmb();
			plx_mmio_write(&xdev->mmio, PLX_A_LUT_PERMISSION_READ_ENABLE |
					PLX_A_LUT_PERMISSION_WRITE_ENABLE,
					permission_offset);
			dev_dbg(&xdev->pdev->dev, "%s writing %x : %x\n",
					__func__,PLX_A_LUT_PERMISSION_READ_ENABLE |
					PLX_A_LUT_PERMISSION_WRITE_ENABLE,
					permission_offset);
			last_permission_reg = permission_offset;
			addr_masked += xdev->a_lut_manager.segment_size;
		}
		mb();
		if (last_permission_reg)
			plx_mmio_read(&xdev->mmio, last_permission_reg);
	}
	spin_unlock(&xdev->alm_lock);
	*addr_out = segment_id * (u64)xdev->a_lut_manager.segment_size +
		(addr & translation_mask);
	dev_dbg(&xdev->pdev->dev,
			"%s map entry no %i original %llx translated %llx\n",
			__func__,
			segment_id,
			(u64)addr,
			(u64)*addr_out);
	return 0;
failed:
	spin_unlock(&xdev->alm_lock);
	return -ENOMEM;
}
int plx_add_a_lut_entry ( struct plx_device * xdev , dma_addr_t addr , size_t size , dma_addr_t * addr_out ) { u32 lower_re_map_offset ; u32 higher_re_map_offset ; u32 permission_offset = 0 ; u64 translation_mask = xdev -> a_lut_manager . segment_size - 1 ; dma_addr_t addr_masked = addr & ~ translation_mask ; int i ; int err ; unsigned int entry_offset ; u32 segments_num ; u32 segment_id ; u32 last_permission_reg = 0 ; spin_lock ( & xdev -> alm_lock ) ; err = plx_alm_add_entry ( & xdev -> a_lut_manager , xdev -> pdev , addr , size , & segment_id , & segments_num ) ; if ( err && err != - EEXIST ) { goto failed ; } if ( err == 0 ) { for ( i = segment_id ; i < segment_id + segments_num ; i ++ ) { entry_offset = xdev -> a_lut_array_base + plx_get_a_lut_entry_offset ( i ) ; lower_re_map_offset = entry_offset + PLX_A_LUT_LOWER_RE_MAP_SUBARRAY_OFFSET ; higher_re_map_offset = entry_offset + PLX_A_LUT_HIGHER_RE_MAP_SUBARRAY_OFFSET ; permission_offset = entry_offset + PLX_A_LUT_PERMISSION_SUBARRAY_OFFSET ; plx_mmio_write ( & xdev -> mmio , ( u32 ) ( addr_masked >> 32 ) , higher_re_map_offset ) ; dev_dbg ( & xdev -> pdev -> dev , " \n " , __func__ , ( u32 ) ( addr_masked >> 32 ) , higher_re_map_offset ) ; plx_mmio_write ( & xdev -> mmio , ( u32 ) ( addr_masked ) , lower_re_map_offset ) ; dev_dbg ( & xdev -> pdev -> dev , " \n " , __func__ , ( u32 ) ( addr_masked ) , lower_re_map_offset ) ; wmb ( ) ; plx_mmio_write ( & xdev -> mmio , PLX_A_LUT_PERMISSION_READ_ENABLE | PLX_A_LUT_PERMISSION_WRITE_ENABLE , permission_offset ) ; dev_dbg ( & xdev -> pdev -> dev , " \n " , __func__ , PLX_A_LUT_PERMISSION_READ_ENABLE | PLX_A_LUT_PERMISSION_WRITE_ENABLE , permission_offset ) ; last_permission_reg = permission_offset ; addr_masked += xdev -> a_lut_manager . segment_size ; } mb ( ) ; if ( last_permission_reg ) plx_mmio_read ( & xdev -> mmio , last_permission_reg ) ; } spin_unlock ( & xdev -> alm_lock ) ; * addr_out = segment_id * ( u64 ) xdev -> a_lut_manager . segment_size + ( addr & translation_mask ) ; dev_dbg ( & xdev -> pdev -> dev , " \n " , __func__ , segment_id , ( u64 ) addr , ( u64 ) * addr_out ) ; return 0 ; failed : spin_unlock ( & xdev -> alm_lock ) ; return - ENOMEM ; }
plx_add_lut_entry() - add entry to A LUT array
 @xdev: pointer to plx_device instance
 @addr: DMA address to access memory
plx_add_lut_entry () - add entry to A LUT array @xdev : pointer to plx_device instance @addr : DMA address to access memory
/*
		 * This is barrier to check that last write to register end,
		 * Check that hardware configuration finished.
		 **/