XilinxProcessorIPLib/drivers/dp14txss/examples/src/pt_only/xdptxss_dp14_pt.c
u32 DpSs_PlatformInit(void)
{
	u32 Status;
	u8 Buffer[2];
	int ByteCount;

	XIic_Config *ConfigPtr_IIC;     /* Pointer to configuration data */
	int result=XST_SUCCESS;
	/* Initialize the IIC driver so that it is ready to use. */
	ConfigPtr_IIC = XIic_LookupConfig(IIC_DEVICE_ID);
	if (ConfigPtr_IIC == NULL) {
	        return XST_FAILURE;
	}

	Status = XIic_CfgInitialize(&IicInstance, ConfigPtr_IIC,
			ConfigPtr_IIC->BaseAddress);
	if (Status != XST_SUCCESS) {
	        return XST_FAILURE;
	}

	XIic_Reset(&IicInstance);

	/*Initializing vck190 onboard IDT8T49N24X for audio*/
#ifdef versal

	result=IDT_8T49N24x_Init(XPAR_IIC_0_BASEADDR, I2C_IDT8N49_ADDR_1);
	if(result!=XST_SUCCESS)
	{
		xil_printf("IDT_8T49N24x_Init failed\r\n");
	}

   /*
	  * Get the CLK_WIZ Dynamic reconfiguration driver instance
	  */
	 CfgPtr_Dynamic = XClk_Wiz_LookupConfig(XPAR_CLK_WIZ_0_DEVICE_ID);
	 if (!CfgPtr_Dynamic) {
			 return XST_FAILURE;
	 }

	 /*
	  * Initialize the CLK_WIZ Dynamic reconfiguration driver
	  */
	 Status = XClk_Wiz_CfgInitialize(&ClkWiz_Dynamic, CfgPtr_Dynamic,
			  CfgPtr_Dynamic->BaseAddr);
	 if (Status != XST_SUCCESS) {
			 return XST_FAILURE;
	 }

#if (VERSAL_FABRIC_8B10B == 1)

	 CfgPtr_Dynamic_rx = XClk_Wiz_LookupConfig(XPAR_CLK_WIZ_1_DEVICE_ID);
	 if (!CfgPtr_Dynamic_rx) {
			 return XST_FAILURE;
	 }

	 /*
	  * Initialize the CLK_WIZ Dynamic reconfiguration driver
	  */
	 Status = XClk_Wiz_CfgInitialize(&ClkWiz_Dynamic_rx, CfgPtr_Dynamic_rx,
			  CfgPtr_Dynamic_rx->BaseAddr);
	 if (Status != XST_SUCCESS) {
			 return XST_FAILURE;
	 }


#endif
#endif

	/* Initialize CRC & Set default Pixel Mode to 1. */
#ifdef Rx
	VidFrameCRC_rx.Base_Addr = VIDEO_FRAME_CRC_RX_BASEADDR;
	XVidFrameCrc_Initialize(&VidFrameCRC_rx);
#endif
#ifdef Tx
	VidFrameCRC_tx.Base_Addr = VIDEO_FRAME_CRC_TX_BASEADDR;
	XVidFrameCrc_Initialize(&VidFrameCRC_tx);
#endif

	/* Initialize Timer */
	Status = XTmrCtr_Initialize(&TmrCtr, XTIMER0_DEVICE_ID);
	if (Status != XST_SUCCESS){
		xil_printf("ERR:Timer failed to initialize. \r\n");
		return XST_FAILURE;
	}
	XTmrCtr_SetResetValue(&TmrCtr, XTIMER0_DEVICE_ID, TIMER_RESET_VALUE);
	XTmrCtr_Start(&TmrCtr, XTIMER0_DEVICE_ID);

//   /* Initialize PS IIC1 */
	XIic1Ps_ConfigPtr = XIicPs_LookupConfig(XPAR_XIICPS_1_DEVICE_ID);
	if (NULL == XIic1Ps_ConfigPtr) {
			return XST_FAILURE;
	}

	Status = XIicPs_CfgInitialize(&Ps_Iic1, XIic1Ps_ConfigPtr,
								XIic1Ps_ConfigPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
			return XST_FAILURE;
	}

	XIicPs_Reset(&Ps_Iic1);
	/*
	 * Set the IIC serial clock rate.
	 */
	XIicPs_SetSClk(&Ps_Iic1, PS_IIC_CLK);

	/* Set the I2C Mux to select the HPC FMC */
#ifdef versal
	I2cMux_Ps(0x04);
#else
	Buffer[0] = 0x01;
	ByteCount = XIic_Send(XPAR_IIC_0_BASEADDR, I2C_MUX_ADDR,
			(u8*)Buffer, 1, XIIC_STOP);
	if (ByteCount != 1) {
		xil_printf("Failed to set the I2C Mux.\n\r");
	    return XST_FAILURE;
	}
#endif

	VideoFMC_Init();

#ifndef versal
	IDT_8T49N24x_SetClock(XPAR_IIC_0_BASEADDR, I2C_IDT8N49_ADDR, 0,
            270000000, TRUE);
#else
	IDT_8T49N24x_SetClock(0x0, I2C_IDT8N49_ADDR, 0,
            270000000, TRUE);
#endif

	usleep(300000);


#ifdef XPAR_XV_AXI4S_REMAP_NUM_INSTANCES

	rx_remap_Config = XV_axi4s_remap_LookupConfig(REMAP_RX_DEVICE_ID);
	Status = XV_axi4s_remap_CfgInitialize(&rx_remap, rx_remap_Config,
					      rx_remap_Config->BaseAddress);
	rx_remap.IsReady = XIL_COMPONENT_IS_READY;
	if (Status != XST_SUCCESS) {
		xil_printf("ERROR:: AXI4S_REMAP Initialization "
			   "failed %d\r\n", Status);
		return (XST_FAILURE);
	}

	tx_remap_Config = XV_axi4s_remap_LookupConfig(REMAP_TX_DEVICE_ID);
	Status = XV_axi4s_remap_CfgInitialize(&tx_remap, tx_remap_Config,
					      tx_remap_Config->BaseAddress);
	tx_remap.IsReady = XIL_COMPONENT_IS_READY;
	if (Status != XST_SUCCESS) {
		xil_printf("ERROR:: AXI4S_REMAP Initialization "
			   "failed %d\r\n", Status);
		return(XST_FAILURE);
	}

	XV_axi4s_remap_Set_width(&rx_remap, 7680);
	XV_axi4s_remap_Set_height(&rx_remap, 4320);
	XV_axi4s_remap_Set_ColorFormat(&rx_remap, 0);
	XV_axi4s_remap_Set_inPixClk(&rx_remap, 4);
	XV_axi4s_remap_Set_outPixClk(&rx_remap, 4);

	XV_axi4s_remap_Set_width(&tx_remap, 7680);
	XV_axi4s_remap_Set_height(&tx_remap, 4320);
	XV_axi4s_remap_Set_ColorFormat(&tx_remap, 0);
	XV_axi4s_remap_Set_inPixClk(&tx_remap, 4);
	XV_axi4s_remap_Set_outPixClk(&tx_remap, 4);
#endif

#if ENABLE_AUDIO

    XAxis_Switch_Config *ConfigPtr_AXIS_SWITCH_RX =
		XAxisScr_LookupConfig(XPAR_DP_RX_HIER_0_AXIS_SWITCH_0_DEVICE_ID);
     if (ConfigPtr_AXIS_SWITCH_RX == NULL) {
             return XST_FAILURE;
     }

     Status = XAxisScr_CfgInitialize(&axis_switch_rx,
		 ConfigPtr_AXIS_SWITCH_RX, ConfigPtr_AXIS_SWITCH_RX->BaseAddress);
     if (Status != XST_SUCCESS) {
             return XST_FAILURE;
     }

     XAxis_Switch_Config *ConfigPtr_AXIS_SWITCH_TX =
		 XAxisScr_LookupConfig(XPAR_DP_TX_HIER_0_AXIS_SWITCH_0_DEVICE_ID);
      if (ConfigPtr_AXIS_SWITCH_TX == NULL) {
              return XST_FAILURE;
      }

      Status = XAxisScr_CfgInitialize(&axis_switch_tx,
		  ConfigPtr_AXIS_SWITCH_TX, ConfigPtr_AXIS_SWITCH_TX->BaseAddress);
      if (Status != XST_SUCCESS) {
              return XST_FAILURE;
      }


    Config = XI2s_Tx_LookupConfig(
			XPAR_DP_RX_HIER_0_I2S_TRANSMITTER_0_DEVICE_ID);
    if (Config == NULL) {
         return XST_FAILURE;
    }

    Status = XI2s_Tx_CfgInitialize(&I2s_tx, Config, Config->BaseAddress);
    if (Status != XST_SUCCESS) {
         return XST_FAILURE;
    }

    Config_rx = XI2s_Rx_LookupConfig(
			XPAR_DP_TX_HIER_0_I2S_RECEIVER_0_DEVICE_ID);
    if (Config == NULL) {
          return XST_FAILURE;
    }

    Status = XI2s_Rx_CfgInitialize(&I2s_rx, Config_rx, Config_rx->BaseAddress);
    if (Status != XST_SUCCESS) {
          return XST_FAILURE;
    }

    aud_gpio_ConfigPtr =
            XGpio_LookupConfig(XPAR_DP_RX_HIER_0_AXI_GPIO_0_DEVICE_ID);

    if(aud_gpio_ConfigPtr == NULL) {
	aud_gpio.IsReady = 0;
            return (XST_DEVICE_NOT_FOUND);
    }

    Status = XGpio_CfgInitialize(&aud_gpio,
		aud_gpio_ConfigPtr,
			aud_gpio_ConfigPtr->BaseAddress);
    if(Status != XST_SUCCESS) {
            xil_printf("ERR:: GPIO for TPG Reset ");
            xil_printf("Initialization failed %d\r\n", Status);
            return(XST_FAILURE);
    }

#endif

	return Status;
}
/*****************************************************************************/
/**
*
* This function initialize required platform specific peripherals.
*
* @param    None.
*
* @return
*        - XST_SUCCESS if required peripherals are initialized and
*        configured successfully.
*        - XST_FAILURE, otherwise.
*
* @note        None.
*
******************************************************************************/
This function initialize required platform specific peripherals.
This function initialize required platform specific peripherals .
u32 DpSs_PlatformInit(void)
{
	u32 Status;
	u8 Buffer[2];
	int ByteCount;
	XIic_Config *ConfigPtr_IIC;     
	int result=XST_SUCCESS;
	ConfigPtr_IIC = XIic_LookupConfig(IIC_DEVICE_ID);
	if (ConfigPtr_IIC == NULL) {
	        return XST_FAILURE;
	}
	Status = XIic_CfgInitialize(&IicInstance, ConfigPtr_IIC,
			ConfigPtr_IIC->BaseAddress);
	if (Status != XST_SUCCESS) {
	        return XST_FAILURE;
	}
	XIic_Reset(&IicInstance);
#ifdef versal
	result=IDT_8T49N24x_Init(XPAR_IIC_0_BASEADDR, I2C_IDT8N49_ADDR_1);
	if(result!=XST_SUCCESS)
	{
		xil_printf("IDT_8T49N24x_Init failed\r\n");
	}
	 CfgPtr_Dynamic = XClk_Wiz_LookupConfig(XPAR_CLK_WIZ_0_DEVICE_ID);
	 if (!CfgPtr_Dynamic) {
			 return XST_FAILURE;
	 }
	 Status = XClk_Wiz_CfgInitialize(&ClkWiz_Dynamic, CfgPtr_Dynamic,
			  CfgPtr_Dynamic->BaseAddr);
	 if (Status != XST_SUCCESS) {
			 return XST_FAILURE;
	 }
#if (VERSAL_FABRIC_8B10B == 1)
	 CfgPtr_Dynamic_rx = XClk_Wiz_LookupConfig(XPAR_CLK_WIZ_1_DEVICE_ID);
	 if (!CfgPtr_Dynamic_rx) {
			 return XST_FAILURE;
	 }
	 Status = XClk_Wiz_CfgInitialize(&ClkWiz_Dynamic_rx, CfgPtr_Dynamic_rx,
			  CfgPtr_Dynamic_rx->BaseAddr);
	 if (Status != XST_SUCCESS) {
			 return XST_FAILURE;
	 }
#endif
#endif
#ifdef Rx
	VidFrameCRC_rx.Base_Addr = VIDEO_FRAME_CRC_RX_BASEADDR;
	XVidFrameCrc_Initialize(&VidFrameCRC_rx);
#endif
#ifdef Tx
	VidFrameCRC_tx.Base_Addr = VIDEO_FRAME_CRC_TX_BASEADDR;
	XVidFrameCrc_Initialize(&VidFrameCRC_tx);
#endif
	Status = XTmrCtr_Initialize(&TmrCtr, XTIMER0_DEVICE_ID);
	if (Status != XST_SUCCESS){
		xil_printf("ERR:Timer failed to initialize. \r\n");
		return XST_FAILURE;
	}
	XTmrCtr_SetResetValue(&TmrCtr, XTIMER0_DEVICE_ID, TIMER_RESET_VALUE);
	XTmrCtr_Start(&TmrCtr, XTIMER0_DEVICE_ID);
	XIic1Ps_ConfigPtr = XIicPs_LookupConfig(XPAR_XIICPS_1_DEVICE_ID);
	if (NULL == XIic1Ps_ConfigPtr) {
			return XST_FAILURE;
	}
	Status = XIicPs_CfgInitialize(&Ps_Iic1, XIic1Ps_ConfigPtr,
								XIic1Ps_ConfigPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
			return XST_FAILURE;
	}
	XIicPs_Reset(&Ps_Iic1);
	XIicPs_SetSClk(&Ps_Iic1, PS_IIC_CLK);
#ifdef versal
	I2cMux_Ps(0x04);
#else
	Buffer[0] = 0x01;
	ByteCount = XIic_Send(XPAR_IIC_0_BASEADDR, I2C_MUX_ADDR,
			(u8*)Buffer, 1, XIIC_STOP);
	if (ByteCount != 1) {
		xil_printf("Failed to set the I2C Mux.\n\r");
	    return XST_FAILURE;
	}
#endif
	VideoFMC_Init();
#ifndef versal
	IDT_8T49N24x_SetClock(XPAR_IIC_0_BASEADDR, I2C_IDT8N49_ADDR, 0,
            270000000, TRUE);
#else
	IDT_8T49N24x_SetClock(0x0, I2C_IDT8N49_ADDR, 0,
            270000000, TRUE);
#endif
	usleep(300000);
#ifdef XPAR_XV_AXI4S_REMAP_NUM_INSTANCES
	rx_remap_Config = XV_axi4s_remap_LookupConfig(REMAP_RX_DEVICE_ID);
	Status = XV_axi4s_remap_CfgInitialize(&rx_remap, rx_remap_Config,
					      rx_remap_Config->BaseAddress);
	rx_remap.IsReady = XIL_COMPONENT_IS_READY;
	if (Status != XST_SUCCESS) {
		xil_printf("ERROR:: AXI4S_REMAP Initialization "
			   "failed %d\r\n", Status);
		return (XST_FAILURE);
	}
	tx_remap_Config = XV_axi4s_remap_LookupConfig(REMAP_TX_DEVICE_ID);
	Status = XV_axi4s_remap_CfgInitialize(&tx_remap, tx_remap_Config,
					      tx_remap_Config->BaseAddress);
	tx_remap.IsReady = XIL_COMPONENT_IS_READY;
	if (Status != XST_SUCCESS) {
		xil_printf("ERROR:: AXI4S_REMAP Initialization "
			   "failed %d\r\n", Status);
		return(XST_FAILURE);
	}
	XV_axi4s_remap_Set_width(&rx_remap, 7680);
	XV_axi4s_remap_Set_height(&rx_remap, 4320);
	XV_axi4s_remap_Set_ColorFormat(&rx_remap, 0);
	XV_axi4s_remap_Set_inPixClk(&rx_remap, 4);
	XV_axi4s_remap_Set_outPixClk(&rx_remap, 4);
	XV_axi4s_remap_Set_width(&tx_remap, 7680);
	XV_axi4s_remap_Set_height(&tx_remap, 4320);
	XV_axi4s_remap_Set_ColorFormat(&tx_remap, 0);
	XV_axi4s_remap_Set_inPixClk(&tx_remap, 4);
	XV_axi4s_remap_Set_outPixClk(&tx_remap, 4);
#endif
#if ENABLE_AUDIO
    XAxis_Switch_Config *ConfigPtr_AXIS_SWITCH_RX =
		XAxisScr_LookupConfig(XPAR_DP_RX_HIER_0_AXIS_SWITCH_0_DEVICE_ID);
     if (ConfigPtr_AXIS_SWITCH_RX == NULL) {
             return XST_FAILURE;
     }
     Status = XAxisScr_CfgInitialize(&axis_switch_rx,
		 ConfigPtr_AXIS_SWITCH_RX, ConfigPtr_AXIS_SWITCH_RX->BaseAddress);
     if (Status != XST_SUCCESS) {
             return XST_FAILURE;
     }
     XAxis_Switch_Config *ConfigPtr_AXIS_SWITCH_TX =
		 XAxisScr_LookupConfig(XPAR_DP_TX_HIER_0_AXIS_SWITCH_0_DEVICE_ID);
      if (ConfigPtr_AXIS_SWITCH_TX == NULL) {
              return XST_FAILURE;
      }
      Status = XAxisScr_CfgInitialize(&axis_switch_tx,
		  ConfigPtr_AXIS_SWITCH_TX, ConfigPtr_AXIS_SWITCH_TX->BaseAddress);
      if (Status != XST_SUCCESS) {
              return XST_FAILURE;
      }
    Config = XI2s_Tx_LookupConfig(
			XPAR_DP_RX_HIER_0_I2S_TRANSMITTER_0_DEVICE_ID);
    if (Config == NULL) {
         return XST_FAILURE;
    }
    Status = XI2s_Tx_CfgInitialize(&I2s_tx, Config, Config->BaseAddress);
    if (Status != XST_SUCCESS) {
         return XST_FAILURE;
    }
    Config_rx = XI2s_Rx_LookupConfig(
			XPAR_DP_TX_HIER_0_I2S_RECEIVER_0_DEVICE_ID);
    if (Config == NULL) {
          return XST_FAILURE;
    }
    Status = XI2s_Rx_CfgInitialize(&I2s_rx, Config_rx, Config_rx->BaseAddress);
    if (Status != XST_SUCCESS) {
          return XST_FAILURE;
    }
    aud_gpio_ConfigPtr =
            XGpio_LookupConfig(XPAR_DP_RX_HIER_0_AXI_GPIO_0_DEVICE_ID);
    if(aud_gpio_ConfigPtr == NULL) {
	aud_gpio.IsReady = 0;
            return (XST_DEVICE_NOT_FOUND);
    }
    Status = XGpio_CfgInitialize(&aud_gpio,
		aud_gpio_ConfigPtr,
			aud_gpio_ConfigPtr->BaseAddress);
    if(Status != XST_SUCCESS) {
            xil_printf("ERR:: GPIO for TPG Reset ");
            xil_printf("Initialization failed %d\r\n", Status);
            return(XST_FAILURE);
    }
#endif
	return Status;
}
u32 DpSs_PlatformInit ( void ) { u32 Status ; u8 Buffer [ 2 ] ; int ByteCount ; XIic_Config * ConfigPtr_IIC ; int result = XST_SUCCESS ; ConfigPtr_IIC = XIic_LookupConfig ( IIC_DEVICE_ID ) ; if ( ConfigPtr_IIC == NULL ) { return XST_FAILURE ; } Status = XIic_CfgInitialize ( & IicInstance , ConfigPtr_IIC , ConfigPtr_IIC -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } XIic_Reset ( & IicInstance ) ; #ifdef versal result = IDT_8T49N24x_Init ( XPAR_IIC_0_BASEADDR , I2C_IDT8N49_ADDR_1 ) ; if ( result != XST_SUCCESS ) { xil_printf ( " \r \n " ) ; } CfgPtr_Dynamic = XClk_Wiz_LookupConfig ( XPAR_CLK_WIZ_0_DEVICE_ID ) ; if ( ! CfgPtr_Dynamic ) { return XST_FAILURE ; } Status = XClk_Wiz_CfgInitialize ( & ClkWiz_Dynamic , CfgPtr_Dynamic , CfgPtr_Dynamic -> BaseAddr ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } #if ( VERSAL_FABRIC_8B10B == 1 ) CfgPtr_Dynamic_rx = XClk_Wiz_LookupConfig ( XPAR_CLK_WIZ_1_DEVICE_ID ) ; if ( ! CfgPtr_Dynamic_rx ) { return XST_FAILURE ; } Status = XClk_Wiz_CfgInitialize ( & ClkWiz_Dynamic_rx , CfgPtr_Dynamic_rx , CfgPtr_Dynamic_rx -> BaseAddr ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } #endif #endif #ifdef Rx VidFrameCRC_rx . Base_Addr = VIDEO_FRAME_CRC_RX_BASEADDR ; XVidFrameCrc_Initialize ( & VidFrameCRC_rx ) ; #endif #ifdef Tx VidFrameCRC_tx . Base_Addr = VIDEO_FRAME_CRC_TX_BASEADDR ; XVidFrameCrc_Initialize ( & VidFrameCRC_tx ) ; #endif Status = XTmrCtr_Initialize ( & TmrCtr , XTIMER0_DEVICE_ID ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \r \n " ) ; return XST_FAILURE ; } XTmrCtr_SetResetValue ( & TmrCtr , XTIMER0_DEVICE_ID , TIMER_RESET_VALUE ) ; XTmrCtr_Start ( & TmrCtr , XTIMER0_DEVICE_ID ) ; XIic1Ps_ConfigPtr = XIicPs_LookupConfig ( XPAR_XIICPS_1_DEVICE_ID ) ; if ( NULL == XIic1Ps_ConfigPtr ) { return XST_FAILURE ; } Status = XIicPs_CfgInitialize ( & Ps_Iic1 , XIic1Ps_ConfigPtr , XIic1Ps_ConfigPtr -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } XIicPs_Reset ( & Ps_Iic1 ) ; XIicPs_SetSClk ( & Ps_Iic1 , PS_IIC_CLK ) ; #ifdef versal I2cMux_Ps ( 0x04 ) ; #else Buffer [ 0 ] = 0x01 ; ByteCount = XIic_Send ( XPAR_IIC_0_BASEADDR , I2C_MUX_ADDR , ( u8 * ) Buffer , 1 , XIIC_STOP ) ; if ( ByteCount != 1 ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } #endif VideoFMC_Init ( ) ; #ifndef versal IDT_8T49N24x_SetClock ( XPAR_IIC_0_BASEADDR , I2C_IDT8N49_ADDR , 0 , 270000000 , TRUE ) ; #else IDT_8T49N24x_SetClock ( 0x0 , I2C_IDT8N49_ADDR , 0 , 270000000 , TRUE ) ; #endif usleep ( 300000 ) ; #ifdef XPAR_XV_AXI4S_REMAP_NUM_INSTANCES rx_remap_Config = XV_axi4s_remap_LookupConfig ( REMAP_RX_DEVICE_ID ) ; Status = XV_axi4s_remap_CfgInitialize ( & rx_remap , rx_remap_Config , rx_remap_Config -> BaseAddress ) ; rx_remap . IsReady = XIL_COMPONENT_IS_READY ; if ( Status != XST_SUCCESS ) { xil_printf ( " " " \r \n " , Status ) ; return ( XST_FAILURE ) ; } tx_remap_Config = XV_axi4s_remap_LookupConfig ( REMAP_TX_DEVICE_ID ) ; Status = XV_axi4s_remap_CfgInitialize ( & tx_remap , tx_remap_Config , tx_remap_Config -> BaseAddress ) ; tx_remap . IsReady = XIL_COMPONENT_IS_READY ; if ( Status != XST_SUCCESS ) { xil_printf ( " " " \r \n " , Status ) ; return ( XST_FAILURE ) ; } XV_axi4s_remap_Set_width ( & rx_remap , 7680 ) ; XV_axi4s_remap_Set_height ( & rx_remap , 4320 ) ; XV_axi4s_remap_Set_ColorFormat ( & rx_remap , 0 ) ; XV_axi4s_remap_Set_inPixClk ( & rx_remap , 4 ) ; XV_axi4s_remap_Set_outPixClk ( & rx_remap , 4 ) ; XV_axi4s_remap_Set_width ( & tx_remap , 7680 ) ; XV_axi4s_remap_Set_height ( & tx_remap , 4320 ) ; XV_axi4s_remap_Set_ColorFormat ( & tx_remap , 0 ) ; XV_axi4s_remap_Set_inPixClk ( & tx_remap , 4 ) ; XV_axi4s_remap_Set_outPixClk ( & tx_remap , 4 ) ; #endif #if ENABLE_AUDIO XAxis_Switch_Config * ConfigPtr_AXIS_SWITCH_RX = XAxisScr_LookupConfig ( XPAR_DP_RX_HIER_0_AXIS_SWITCH_0_DEVICE_ID ) ; if ( ConfigPtr_AXIS_SWITCH_RX == NULL ) { return XST_FAILURE ; } Status = XAxisScr_CfgInitialize ( & axis_switch_rx , ConfigPtr_AXIS_SWITCH_RX , ConfigPtr_AXIS_SWITCH_RX -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } XAxis_Switch_Config * ConfigPtr_AXIS_SWITCH_TX = XAxisScr_LookupConfig ( XPAR_DP_TX_HIER_0_AXIS_SWITCH_0_DEVICE_ID ) ; if ( ConfigPtr_AXIS_SWITCH_TX == NULL ) { return XST_FAILURE ; } Status = XAxisScr_CfgInitialize ( & axis_switch_tx , ConfigPtr_AXIS_SWITCH_TX , ConfigPtr_AXIS_SWITCH_TX -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } Config = XI2s_Tx_LookupConfig ( XPAR_DP_RX_HIER_0_I2S_TRANSMITTER_0_DEVICE_ID ) ; if ( Config == NULL ) { return XST_FAILURE ; } Status = XI2s_Tx_CfgInitialize ( & I2s_tx , Config , Config -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } Config_rx = XI2s_Rx_LookupConfig ( XPAR_DP_TX_HIER_0_I2S_RECEIVER_0_DEVICE_ID ) ; if ( Config == NULL ) { return XST_FAILURE ; } Status = XI2s_Rx_CfgInitialize ( & I2s_rx , Config_rx , Config_rx -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } aud_gpio_ConfigPtr = XGpio_LookupConfig ( XPAR_DP_RX_HIER_0_AXI_GPIO_0_DEVICE_ID ) ; if ( aud_gpio_ConfigPtr == NULL ) { aud_gpio . IsReady = 0 ; return ( XST_DEVICE_NOT_FOUND ) ; } Status = XGpio_CfgInitialize ( & aud_gpio , aud_gpio_ConfigPtr , aud_gpio_ConfigPtr -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " " ) ; xil_printf ( " \r \n " , Status ) ; return ( XST_FAILURE ) ; } #endif return Status ; }
This function initialize required platform specific peripherals.
This function initialize required platform specific peripherals .
/* Pointer to configuration data */ /* Initialize the IIC driver so that it is ready to use. */ /*Initializing vck190 onboard IDT8T49N24X for audio*/ /*
	  * Get the CLK_WIZ Dynamic reconfiguration driver instance
	  */ /*
	  * Initialize the CLK_WIZ Dynamic reconfiguration driver
	  */ /*
	  * Initialize the CLK_WIZ Dynamic reconfiguration driver
	  */ /* Initialize CRC & Set default Pixel Mode to 1. */ /* Initialize Timer */ //   /* Initialize PS IIC1 */ /*
	 * Set the IIC serial clock rate.
	 */ /* Set the I2C Mux to select the HPC FMC */