XilinxProcessorIPLib/drivers/hwicap/src/xhwicap_srp.c
u32 XHwIcap_GetConfigReg(XHwIcap *InstancePtr, u32 ConfigReg, u32 *RegData)
{
	int Status;
	int EosRetries =0; /* Counter for checking EOS to become high */
	u32 FrameBuffer[READ_CFG_REG_COMMAND_SIZE];
	u32 Index =0;

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Create the data to be written to the ICAP.
	 */
	FrameBuffer[Index++] = XHI_DUMMY_PACKET;
	FrameBuffer[Index++] = XHI_SYNC_PACKET;
	FrameBuffer[Index++] = XHI_NOOP_PACKET;
	FrameBuffer[Index++] = XHI_NOOP_PACKET;
	FrameBuffer[Index++] = XHwIcap_Type1Read(ConfigReg) | 0x1;
	FrameBuffer[Index++] = XHI_NOOP_PACKET;
	FrameBuffer[Index++] = XHI_NOOP_PACKET;

	/*
	 * Check for EOS bit of Status Register. EOS bit becomes high after
	 * ICAP completes Start up sequence. Access to ICAP should start
	 * only after EOS bit becomes high.
	 */

	while((!(XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
			XHI_SR_OFFSET)& XHI_SR_EOS_MASK))) {

		if(EosRetries < XHI_MAX_RETRIES) {
			EosRetries++;
		}
		else {
	   		return XST_FAILURE;
		}

	}

	/*
	 * Write the data to the FIFO and intiate the transfer of data present
	 * in the FIFO to the ICAP device.
	 */
	Status = XHwIcap_DeviceWrite(InstancePtr, &FrameBuffer[0], Index);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}

	while (XHwIcap_IsDeviceBusy(InstancePtr) != FALSE);
	while ((XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
			XHI_CR_OFFSET)) & XHI_CR_WRITE_MASK);

	/*
	 * Read the Config Register using DeviceRead since
	 * DeviceRead reads depending on ICAP Width for V6
	 * and 7 series devices
  	 */
	XHwIcap_DeviceRead(InstancePtr, RegData, 1);

	return XST_SUCCESS;
}
/****************************************************************************/
/**
 *
 * This function returns the value of the specified configuration register.
 *
 * @param	InstancePtr is a pointer to the XHwIcap instance.
 * @param	ConfigReg  is a constant which represents the configuration
 *		register value to be returned. Constants specified in
 *		xhwicap_i.h.
 * 		Examples:  XHI_IDCODE, XHI_FLR.
 * @param	RegData is the value of the specified configuration
 *		register.
 *
 * @return	XST_SUCCESS or XST_FAILURE
 *
 * @note	This is a blocking call.
 *
 *****************************************************************************/
This function returns the value of the specified configuration register.
@param       InstancePtr is a pointer to the XHwIcap instance.
@param       ConfigReg  is a constant which represents the configuration
register value to be returned.



@note        This is a blocking call.
This function returns the value of the specified configuration register . @param InstancePtr is a pointer to the XHwIcap instance . @param ConfigReg is a constant which represents the configuration register value to be returned . @note This is a blocking call .
u32 XHwIcap_GetConfigReg(XHwIcap *InstancePtr, u32 ConfigReg, u32 *RegData)
{
	int Status;
	int EosRetries =0; 
	u32 FrameBuffer[READ_CFG_REG_COMMAND_SIZE];
	u32 Index =0;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	FrameBuffer[Index++] = XHI_DUMMY_PACKET;
	FrameBuffer[Index++] = XHI_SYNC_PACKET;
	FrameBuffer[Index++] = XHI_NOOP_PACKET;
	FrameBuffer[Index++] = XHI_NOOP_PACKET;
	FrameBuffer[Index++] = XHwIcap_Type1Read(ConfigReg) | 0x1;
	FrameBuffer[Index++] = XHI_NOOP_PACKET;
	FrameBuffer[Index++] = XHI_NOOP_PACKET;
	while((!(XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
			XHI_SR_OFFSET)& XHI_SR_EOS_MASK))) {
		if(EosRetries < XHI_MAX_RETRIES) {
			EosRetries++;
		}
		else {
	   		return XST_FAILURE;
		}
	}
	Status = XHwIcap_DeviceWrite(InstancePtr, &FrameBuffer[0], Index);
	if (Status != XST_SUCCESS)  {
		return XST_FAILURE;
	}
	while (XHwIcap_IsDeviceBusy(InstancePtr) != FALSE);
	while ((XHwIcap_ReadReg(InstancePtr->HwIcapConfig.BaseAddress,
			XHI_CR_OFFSET)) & XHI_CR_WRITE_MASK);
	XHwIcap_DeviceRead(InstancePtr, RegData, 1);
	return XST_SUCCESS;
}
u32 XHwIcap_GetConfigReg ( XHwIcap * InstancePtr , u32 ConfigReg , u32 * RegData ) { int Status ; int EosRetries = 0 ; u32 FrameBuffer [ READ_CFG_REG_COMMAND_SIZE ] ; u32 Index = 0 ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; FrameBuffer [ Index ++ ] = XHI_DUMMY_PACKET ; FrameBuffer [ Index ++ ] = XHI_SYNC_PACKET ; FrameBuffer [ Index ++ ] = XHI_NOOP_PACKET ; FrameBuffer [ Index ++ ] = XHI_NOOP_PACKET ; FrameBuffer [ Index ++ ] = XHwIcap_Type1Read ( ConfigReg ) | 0x1 ; FrameBuffer [ Index ++ ] = XHI_NOOP_PACKET ; FrameBuffer [ Index ++ ] = XHI_NOOP_PACKET ; while ( ( ! ( XHwIcap_ReadReg ( InstancePtr -> HwIcapConfig . BaseAddress , XHI_SR_OFFSET ) & XHI_SR_EOS_MASK ) ) ) { if ( EosRetries < XHI_MAX_RETRIES ) { EosRetries ++ ; } else { return XST_FAILURE ; } } Status = XHwIcap_DeviceWrite ( InstancePtr , & FrameBuffer [ 0 ] , Index ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } while ( XHwIcap_IsDeviceBusy ( InstancePtr ) != FALSE ) ; while ( ( XHwIcap_ReadReg ( InstancePtr -> HwIcapConfig . BaseAddress , XHI_CR_OFFSET ) ) & XHI_CR_WRITE_MASK ) ; XHwIcap_DeviceRead ( InstancePtr , RegData , 1 ) ; return XST_SUCCESS ; }
This function returns the value of the specified configuration register.
This function returns the value of the specified configuration register .
/* Counter for checking EOS to become high */ /*
	 * Create the data to be written to the ICAP.
	 */ /*
	 * Check for EOS bit of Status Register. EOS bit becomes high after
	 * ICAP completes Start up sequence. Access to ICAP should start
	 * only after EOS bit becomes high.
	 */ /*
	 * Write the data to the FIFO and intiate the transfer of data present
	 * in the FIFO to the ICAP device.
	 */ /*
	 * Read the Config Register using DeviceRead since
	 * DeviceRead reads depending on ICAP Width for V6
	 * and 7 series devices
  	 */