XilinxProcessorIPLib/drivers/aiengine/src/tile/xaietile_pl.c
u32 XAieTile_PlIntcL1IrqEventSet(XAieGbl_Tile *TileInstPtr, u8 IrqEvent,
				  u8 Event, u8 SwitchAB)
{
	u64 RegAddr;
	u8 IrqEventOff;

	XAie_AssertNonvoid(TileInstPtr != XAIE_NULL);
	XAie_AssertNonvoid(TileInstPtr->TileType != XAIEGBL_TILE_TYPE_AIETILE);
	XAie_AssertNonvoid(SwitchAB == XAIETILE_PL_BLOCK_SWITCHA ||
			   SwitchAB == XAIETILE_PL_BLOCK_SWITCHB);
	XAie_AssertNonvoid(IrqEvent >= XAIETILE_PL_INTERN_EVENT16 &&
			   IrqEvent <= XAIETILE_PL_INTERN_EVENT19);

	RegAddr = TileInstPtr->TileAddr + Shim_1stIrqCntr.IrqEventOff;
	RegAddr += SwitchAB * Shim_1stIrqCntr.SwitchOff;
	IrqEventOff = IrqEvent - XAIETILE_PL_INTERN_EVENT16;
	XAieGbl_MaskWrite32(RegAddr,
			    Shim_1stIrqCntr.IrqEventRegFld[IrqEventOff].Mask,
			    Event);
	return XAIE_SUCCESS;
}
/*****************************************************************************/
/**
*
* This sets 1st level interrupt event
*
* @param	TileInstPtr - Pointer to the Shim tile instance.
* @param	SwitchAB - Flag to indicate if it's the A or B block.
* @param	IrqEvent - Irq event (16, 17, 18, 19)
* @param	Event - Event to generate the specified Irq event
*
* @return	Success.
*
* @note		None.
*
*******************************************************************************/
This sets 1st level interrupt event
This sets 1st level interrupt event
u32 XAieTile_PlIntcL1IrqEventSet(XAieGbl_Tile *TileInstPtr, u8 IrqEvent,
				  u8 Event, u8 SwitchAB)
{
	u64 RegAddr;
	u8 IrqEventOff;
	XAie_AssertNonvoid(TileInstPtr != XAIE_NULL);
	XAie_AssertNonvoid(TileInstPtr->TileType != XAIEGBL_TILE_TYPE_AIETILE);
	XAie_AssertNonvoid(SwitchAB == XAIETILE_PL_BLOCK_SWITCHA ||
			   SwitchAB == XAIETILE_PL_BLOCK_SWITCHB);
	XAie_AssertNonvoid(IrqEvent >= XAIETILE_PL_INTERN_EVENT16 &&
			   IrqEvent <= XAIETILE_PL_INTERN_EVENT19);
	RegAddr = TileInstPtr->TileAddr + Shim_1stIrqCntr.IrqEventOff;
	RegAddr += SwitchAB * Shim_1stIrqCntr.SwitchOff;
	IrqEventOff = IrqEvent - XAIETILE_PL_INTERN_EVENT16;
	XAieGbl_MaskWrite32(RegAddr,
			    Shim_1stIrqCntr.IrqEventRegFld[IrqEventOff].Mask,
			    Event);
	return XAIE_SUCCESS;
}
u32 XAieTile_PlIntcL1IrqEventSet ( XAieGbl_Tile * TileInstPtr , u8 IrqEvent , u8 Event , u8 SwitchAB ) { u64 RegAddr ; u8 IrqEventOff ; XAie_AssertNonvoid ( TileInstPtr != XAIE_NULL ) ; XAie_AssertNonvoid ( TileInstPtr -> TileType != XAIEGBL_TILE_TYPE_AIETILE ) ; XAie_AssertNonvoid ( SwitchAB == XAIETILE_PL_BLOCK_SWITCHA || SwitchAB == XAIETILE_PL_BLOCK_SWITCHB ) ; XAie_AssertNonvoid ( IrqEvent >= XAIETILE_PL_INTERN_EVENT16 && IrqEvent <= XAIETILE_PL_INTERN_EVENT19 ) ; RegAddr = TileInstPtr -> TileAddr + Shim_1stIrqCntr . IrqEventOff ; RegAddr += SwitchAB * Shim_1stIrqCntr . SwitchOff ; IrqEventOff = IrqEvent - XAIETILE_PL_INTERN_EVENT16 ; XAieGbl_MaskWrite32 ( RegAddr , Shim_1stIrqCntr . IrqEventRegFld [ IrqEventOff ] . Mask , Event ) ; return XAIE_SUCCESS ; }
This sets 1st level interrupt event
This sets 1st level interrupt event