lib/sw_apps/zynqmp_pmufw/src/pm_power.c
s32 PmPowerRequestRpu(PmSlaveTcm* const tcm)
{
	s32 status = XST_SUCCESS;
	u32 resetMask = CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK |
			CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK;
	u32 reset;

	if (0U != pmPowerIslandRpu_g.deps) {
		goto done;
	}

	/* Ensure that the RPU island is ON */
	status = PmPowerRequest(&pmPowerIslandRpu_g.power);
	if (XST_SUCCESS != status) {
		goto ret;
	}

	/*
	 * Ensure the comparators are in clean state when rpu comes up
	 */
	XPfw_RMW32(RPU_RPU_ERR_INJ,
			RPU_RPU_ERR_INJ_DCCMINP2_MASK | RPU_RPU_ERR_INJ_DCCMINP_MASK,
			0x0);

	reset = XPfw_Read32(CRL_APB_RST_LPD_TOP);
	/* If PGE and AMBA resets are asserted, deassert them now */
	if (0U != (reset & resetMask)) {
		XPfw_Write32(CRL_APB_RST_LPD_TOP, reset & ~resetMask);
	}
	/* If RPU0 reset is asserted, halt the core and deassert its reset */
	if (0U != (reset & CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK)) {
		XPfw_RMW32(RPU_RPU_0_CFG,
			   RPU_RPU_0_CFG_NCPUHALT_MASK,
			  ~RPU_RPU_0_CFG_NCPUHALT_MASK);
		XPfw_RMW32(CRL_APB_RST_LPD_TOP,
			   CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK,
			  ~CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
	}
	/* If RPU1 reset is asserted, halt the core and deassert its reset */
	if (0U != (reset & CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK)) {
		XPfw_RMW32(RPU_RPU_1_CFG,
			   RPU_RPU_1_CFG_NCPUHALT_MASK,
			  ~RPU_RPU_1_CFG_NCPUHALT_MASK);
		XPfw_RMW32(CRL_APB_RST_LPD_TOP,
			   CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK,
			  ~CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
	}
done:
	pmPowerIslandRpu_g.deps |= tcm->id;
ret:
	return status;
}
/**
 * PmPowerRequestRpu() - Request RPU (TCM now depends on RPU)
 * @tcm		TCM which requests RPU
 *
 * @return	XST_SUCCESS or error code if powering up of RPU failed
 */


@return      XST_SUCCESS or error code if powering up of RPU failed
@return XST_SUCCESS or error code if powering up of RPU failed
s32 PmPowerRequestRpu(PmSlaveTcm* const tcm)
{
	s32 status = XST_SUCCESS;
	u32 resetMask = CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK |
			CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK;
	u32 reset;
	if (0U != pmPowerIslandRpu_g.deps) {
		goto done;
	}
	status = PmPowerRequest(&pmPowerIslandRpu_g.power);
	if (XST_SUCCESS != status) {
		goto ret;
	}
	XPfw_RMW32(RPU_RPU_ERR_INJ,
			RPU_RPU_ERR_INJ_DCCMINP2_MASK | RPU_RPU_ERR_INJ_DCCMINP_MASK,
			0x0);
	reset = XPfw_Read32(CRL_APB_RST_LPD_TOP);
	if (0U != (reset & resetMask)) {
		XPfw_Write32(CRL_APB_RST_LPD_TOP, reset & ~resetMask);
	}
	if (0U != (reset & CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK)) {
		XPfw_RMW32(RPU_RPU_0_CFG,
			   RPU_RPU_0_CFG_NCPUHALT_MASK,
			  ~RPU_RPU_0_CFG_NCPUHALT_MASK);
		XPfw_RMW32(CRL_APB_RST_LPD_TOP,
			   CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK,
			  ~CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
	}
	if (0U != (reset & CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK)) {
		XPfw_RMW32(RPU_RPU_1_CFG,
			   RPU_RPU_1_CFG_NCPUHALT_MASK,
			  ~RPU_RPU_1_CFG_NCPUHALT_MASK);
		XPfw_RMW32(CRL_APB_RST_LPD_TOP,
			   CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK,
			  ~CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
	}
done:
	pmPowerIslandRpu_g.deps |= tcm->id;
ret:
	return status;
}
s32 PmPowerRequestRpu ( PmSlaveTcm * const tcm ) { s32 status = XST_SUCCESS ; u32 resetMask = CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK | CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK ; u32 reset ; if ( 0U != pmPowerIslandRpu_g . deps ) { goto done ; } status = PmPowerRequest ( & pmPowerIslandRpu_g . power ) ; if ( XST_SUCCESS != status ) { goto ret ; } XPfw_RMW32 ( RPU_RPU_ERR_INJ , RPU_RPU_ERR_INJ_DCCMINP2_MASK | RPU_RPU_ERR_INJ_DCCMINP_MASK , 0x0 ) ; reset = XPfw_Read32 ( CRL_APB_RST_LPD_TOP ) ; if ( 0U != ( reset & resetMask ) ) { XPfw_Write32 ( CRL_APB_RST_LPD_TOP , reset & ~ resetMask ) ; } if ( 0U != ( reset & CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK ) ) { XPfw_RMW32 ( RPU_RPU_0_CFG , RPU_RPU_0_CFG_NCPUHALT_MASK , ~ RPU_RPU_0_CFG_NCPUHALT_MASK ) ; XPfw_RMW32 ( CRL_APB_RST_LPD_TOP , CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK , ~ CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK ) ; } if ( 0U != ( reset & CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK ) ) { XPfw_RMW32 ( RPU_RPU_1_CFG , RPU_RPU_1_CFG_NCPUHALT_MASK , ~ RPU_RPU_1_CFG_NCPUHALT_MASK ) ; XPfw_RMW32 ( CRL_APB_RST_LPD_TOP , CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK , ~ CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK ) ; } done : pmPowerIslandRpu_g . deps |= tcm -> id ; ret : return status ; }
PmPowerRequestRpu() - Request RPU (TCM now depends on RPU)
 @tcm         TCM which requests RPU
PmPowerRequestRpu () - Request RPU ( TCM now depends on RPU ) @tcm TCM which requests RPU
/* Ensure that the RPU island is ON */ /*
	 * Ensure the comparators are in clean state when rpu comes up
	 */ /* If PGE and AMBA resets are asserted, deassert them now */ /* If RPU0 reset is asserted, halt the core and deassert its reset */ /* If RPU1 reset is asserted, halt the core and deassert its reset */