XilinxProcessorIPLib/drivers/clockps/src/xclockps.c
static void XClock_EnableInitClocks(void)
{
	u8                Idx;
	XClock_OutputClks InitClks[] = {ACPU, DDR_REF};

	for (Idx = 0; Idx < CLK_ARRAY_SIZE(InitClks); Idx++) {
		if (XST_SUCCESS != XClock_EnableClock(InitClks[Idx])) {
			xil_printf("Warning: Failed to enable clock at "
							"index %d\n\r", Idx);
		}
	}
}
/*****************************************************************************/
/*
*
* This function enables acpu and ddr_ref clocks during initialization.
*
* @param	None.
*
* @return	None.
*
* @note		An array with list of clocks to be enabled at initialization
*		is maintained. This function walks through that array and
*		initializes all the clocks.
*
******************************************************************************/
This function enables acpu and ddr_ref clocks during initialization.
This function enables acpu and ddr_ref clocks during initialization .
static void XClock_EnableInitClocks(void)
{
	u8                Idx;
	XClock_OutputClks InitClks[] = {ACPU, DDR_REF};
	for (Idx = 0; Idx < CLK_ARRAY_SIZE(InitClks); Idx++) {
		if (XST_SUCCESS != XClock_EnableClock(InitClks[Idx])) {
			xil_printf("Warning: Failed to enable clock at "
							"index %d\n\r", Idx);
		}
	}
}
static void XClock_EnableInitClocks ( void ) { u8 Idx ; XClock_OutputClks InitClks [ ] = { ACPU , DDR_REF } ; for ( Idx = 0 ; Idx < CLK_ARRAY_SIZE ( InitClks ) ; Idx ++ ) { if ( XST_SUCCESS != XClock_EnableClock ( InitClks [ Idx ] ) ) { xil_printf ( " " " \n \r " , Idx ) ; } } }
This function enables acpu and ddr_ref clocks during initialization.
This function enables acpu and ddr_ref clocks during initialization .