XilinxProcessorIPLib/drivers/uartpsv/src/xuartpsv.c
void XUartPsv_ProgramCtrlReg(XUartPsv *InstancePtr, u32 CtrlRegister)
{
	u32 LineCtrlRegister;
	u32 TempCtrlRegister;
	u32 IsBusy;

	/*
	 * Check is TX completed. If Uart is disabled in the middle, cannot
	 * recover. So, keep this check before disable.
	 */
	IsBusy = (u32)XUartPsv_IsTransmitbusy(InstancePtr->Config.BaseAddress);
	while (IsBusy == (u32)TRUE) {
		IsBusy = (u32)XUartPsv_IsTransmitbusy(InstancePtr->Config.BaseAddress);
	}

	/* Disable UART */
	TempCtrlRegister = XUartPsv_ReadReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTCR_OFFSET);

	XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTCR_OFFSET, TempCtrlRegister & (~XUARTPSV_UARTCR_UARTEN));

	/*
	 * Flush the transmit FIFO by setting the FEN bit to 0 in the
	 * Line Control Register
	 */
	LineCtrlRegister = XUartPsv_ReadReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTLCR_OFFSET);

	LineCtrlRegister &= ~XUARTPSV_UARTLCR_FEN;
	XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTLCR_OFFSET, LineCtrlRegister);


	/* Setup the Control Register with the passed argument.*/
	XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTCR_OFFSET, CtrlRegister);

	/* By default, driver works in FIFO mode, so set FEN as it is
	 * cleared above
	 */
	LineCtrlRegister |= XUARTPSV_UARTLCR_FEN;
	XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTLCR_OFFSET, LineCtrlRegister);

	/* Enable UART */
	TempCtrlRegister = XUartPsv_ReadReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTCR_OFFSET);
	TempCtrlRegister |= XUARTPSV_UARTCR_UARTEN;
	XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTCR_OFFSET, TempCtrlRegister);
}
/*****************************************************************************/
/**
 *
 * This function reprograms the control register according to the following
 * sequence mentioned in the TRM
 *
 * Sequence to Program Control Register.
 * 	1. Disable UART
 * 	2. Check if Busy
 * 	3. Flush the transmit FIFO
 * 	4. Program the Control Register
 * 	5. Enable the Uart
 *
 * @param	InstancePtr is a pointer to the XUartPsv instance
 * @param	CtrlRegister value to be written
 *
 * @return	None.
 *
 * @note 	None.
 *
 ******************************************************************************/
This function reprograms the control register according to the following
sequence mentioned in the TRM

Sequence to Program Control Register.
1. Disable UART
2. Check if Busy
3. Flush the transmit FIFO
4. Program the Control Register
5. Enable the Uart

@param       InstancePtr is a pointer to the XUartPsv instance
@param       CtrlRegister value to be written

@return      None.

@note        None.
This function reprograms the control register according to the following sequence mentioned in the TRM Sequence to Program Control Register . 1 . Disable UART 2 . Check if Busy 3 . Flush the transmit FIFO 4 . Program the Control Register 5 . Enable the Uart @param InstancePtr is a pointer to the XUartPsv instance @param CtrlRegister value to be written @return None . @note None .
void XUartPsv_ProgramCtrlReg(XUartPsv *InstancePtr, u32 CtrlRegister)
{
	u32 LineCtrlRegister;
	u32 TempCtrlRegister;
	u32 IsBusy;
	IsBusy = (u32)XUartPsv_IsTransmitbusy(InstancePtr->Config.BaseAddress);
	while (IsBusy == (u32)TRUE) {
		IsBusy = (u32)XUartPsv_IsTransmitbusy(InstancePtr->Config.BaseAddress);
	}
	TempCtrlRegister = XUartPsv_ReadReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTCR_OFFSET);
	XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTCR_OFFSET, TempCtrlRegister & (~XUARTPSV_UARTCR_UARTEN));
	LineCtrlRegister = XUartPsv_ReadReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTLCR_OFFSET);
	LineCtrlRegister &= ~XUARTPSV_UARTLCR_FEN;
	XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTLCR_OFFSET, LineCtrlRegister);
	XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTCR_OFFSET, CtrlRegister);
	LineCtrlRegister |= XUARTPSV_UARTLCR_FEN;
	XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTLCR_OFFSET, LineCtrlRegister);
	TempCtrlRegister = XUartPsv_ReadReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTCR_OFFSET);
	TempCtrlRegister |= XUARTPSV_UARTCR_UARTEN;
	XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTCR_OFFSET, TempCtrlRegister);
}
void XUartPsv_ProgramCtrlReg ( XUartPsv * InstancePtr , u32 CtrlRegister ) { u32 LineCtrlRegister ; u32 TempCtrlRegister ; u32 IsBusy ; IsBusy = ( u32 ) XUartPsv_IsTransmitbusy ( InstancePtr -> Config . BaseAddress ) ; while ( IsBusy == ( u32 ) TRUE ) { IsBusy = ( u32 ) XUartPsv_IsTransmitbusy ( InstancePtr -> Config . BaseAddress ) ; } TempCtrlRegister = XUartPsv_ReadReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTCR_OFFSET ) ; XUartPsv_WriteReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTCR_OFFSET , TempCtrlRegister & ( ~ XUARTPSV_UARTCR_UARTEN ) ) ; LineCtrlRegister = XUartPsv_ReadReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTLCR_OFFSET ) ; LineCtrlRegister &= ~ XUARTPSV_UARTLCR_FEN ; XUartPsv_WriteReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTLCR_OFFSET , LineCtrlRegister ) ; XUartPsv_WriteReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTCR_OFFSET , CtrlRegister ) ; LineCtrlRegister |= XUARTPSV_UARTLCR_FEN ; XUartPsv_WriteReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTLCR_OFFSET , LineCtrlRegister ) ; TempCtrlRegister = XUartPsv_ReadReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTCR_OFFSET ) ; TempCtrlRegister |= XUARTPSV_UARTCR_UARTEN ; XUartPsv_WriteReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTCR_OFFSET , TempCtrlRegister ) ; }
This function reprograms the control register according to the following
 sequence mentioned in the TRM
This function reprograms the control register according to the following sequence mentioned in the TRM
/*
	 * Check is TX completed. If Uart is disabled in the middle, cannot
	 * recover. So, keep this check before disable.
	 */ /* Disable UART */ /*
	 * Flush the transmit FIFO by setting the FEN bit to 0 in the
	 * Line Control Register
	 */ /* Setup the Control Register with the passed argument.*/ /* By default, driver works in FIFO mode, so set FEN as it is
	 * cleared above
	 */ /* Enable UART */