src/dpdk/drivers/net/cxgbe/base/t4_hw.c
int t4_fixup_host_params_compat(struct adapter *adap,
				unsigned int page_size,
				unsigned int cache_line_size,
				enum chip_type chip_compat)
{
	unsigned int page_shift = cxgbe_fls(page_size) - 1;
	unsigned int sge_hps = page_shift - 10;
	unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
	unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
	unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;

	t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
		     V_HOSTPAGESIZEPF0(sge_hps) |
		     V_HOSTPAGESIZEPF1(sge_hps) |
		     V_HOSTPAGESIZEPF2(sge_hps) |
		     V_HOSTPAGESIZEPF3(sge_hps) |
		     V_HOSTPAGESIZEPF4(sge_hps) |
		     V_HOSTPAGESIZEPF5(sge_hps) |
		     V_HOSTPAGESIZEPF6(sge_hps) |
		     V_HOSTPAGESIZEPF7(sge_hps));

	if (is_t4(adap->params.chip) || is_t4(chip_compat))
		t4_set_reg_field(adap, A_SGE_CONTROL,
				 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
				 F_EGRSTATUSPAGESIZE,
				 V_INGPADBOUNDARY(fl_align_log -
						  X_INGPADBOUNDARY_SHIFT) |
				V_EGRSTATUSPAGESIZE(stat_len != 64));
	else {
		unsigned int pack_align;
		unsigned int ingpad, ingpack;
		unsigned int pcie_cap;

		/*
		 * T5 introduced the separation of the Free List Padding and
		 * Packing Boundaries.  Thus, we can select a smaller Padding
		 * Boundary to avoid uselessly chewing up PCIe Link and Memory
		 * Bandwidth, and use a Packing Boundary which is large enough
		 * to avoid false sharing between CPUs, etc.
		 *
		 * For the PCI Link, the smaller the Padding Boundary the
		 * better.  For the Memory Controller, a smaller Padding
		 * Boundary is better until we cross under the Memory Line
		 * Size (the minimum unit of transfer to/from Memory).  If we
		 * have a Padding Boundary which is smaller than the Memory
		 * Line Size, that'll involve a Read-Modify-Write cycle on the
		 * Memory Controller which is never good.
		 */

		/* We want the Packing Boundary to be based on the Cache Line
		 * Size in order to help avoid False Sharing performance
		 * issues between CPUs, etc.  We also want the Packing
		 * Boundary to incorporate the PCI-E Maximum Payload Size.  We
		 * get best performance when the Packing Boundary is a
		 * multiple of the Maximum Payload Size.
		 */
		pack_align = fl_align;
		pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
		if (pcie_cap) {
			unsigned int mps, mps_log;
			u16 devctl;

			/* The PCIe Device Control Maximum Payload Size field
			 * [bits 7:5] encodes sizes as powers of 2 starting at
			 * 128 bytes.
			 */
			t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
					    &devctl);
			mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
			mps = 1 << mps_log;
			if (mps > pack_align)
				pack_align = mps;
		}

		/*
		 * N.B. T5 has a different interpretation of the "0" value for
		 * the Packing Boundary.  This corresponds to 16 bytes instead
		 * of the expected 32 bytes.  We never have a Packing Boundary
		 * less than 32 bytes so we can't use that special value but
		 * on the other hand, if we wanted 32 bytes, the best we can
		 * really do is 64 bytes ...
		 */
		if (pack_align <= 16) {
			ingpack = X_INGPACKBOUNDARY_16B;
			fl_align = 16;
		} else if (pack_align == 32) {
			ingpack = X_INGPACKBOUNDARY_64B;
			fl_align = 64;
		} else {
			unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;

			ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
			fl_align = pack_align;
		}

		/* Use the smallest Ingress Padding which isn't smaller than
		 * the Memory Controller Read/Write Size.  We'll take that as
		 * being 8 bytes since we don't know of any system with a
		 * wider Memory Controller Bus Width.
		 */
		if (is_t5(adap->params.chip))
			ingpad = X_INGPADBOUNDARY_32B;
		else
			ingpad = X_T6_INGPADBOUNDARY_8B;
		t4_set_reg_field(adap, A_SGE_CONTROL,
				 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
				 F_EGRSTATUSPAGESIZE,
				 V_INGPADBOUNDARY(ingpad) |
				 V_EGRSTATUSPAGESIZE(stat_len != 64));
		t4_set_reg_field(adap, A_SGE_CONTROL2,
				 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
				 V_INGPACKBOUNDARY(ingpack));
	}

	/*
	 * Adjust various SGE Free List Host Buffer Sizes.
	 *
	 * The first four entries are:
	 *
	 *   0: Host Page Size
	 *   1: 64KB
	 *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
	 *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
	 *
	 * For the single-MTU buffers in unpacked mode we need to include
	 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
	 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
	 * Padding boundary.  All of these are accommodated in the Factory
	 * Default Firmware Configuration File but we need to adjust it for
	 * this host's cache line size.
	 */
	t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
	t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
		     (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
		     & ~(fl_align - 1));
	t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
		     (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
		     & ~(fl_align - 1));

	t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));

	return 0;
}
/**
 * t4_fixup_host_params_compat - fix up host-dependent parameters
 * @adap: the adapter
 * @page_size: the host's Base Page Size
 * @cache_line_size: the host's Cache Line Size
 * @chip_compat: maintain compatibility with designated chip
 *
 * Various registers in the chip contain values which are dependent on the
 * host's Base Page and Cache Line Sizes.  This function will fix all of
 * those registers with the appropriate values as passed in ...
 *
 * @chip_compat is used to limit the set of changes that are made
 * to be compatible with the indicated chip release.  This is used by
 * drivers to maintain compatibility with chip register settings when
 * the drivers haven't [yet] been updated with new chip support.
 */
fix up host-dependent parameters
@adap: the adapter
@page_size: the host's Base Page Size
@cache_line_size: the host's Cache Line Size
@chip_compat: maintain compatibility with designated chip

Various registers in the chip contain values which are dependent on the
host's Base Page and Cache Line Sizes.  This function will fix all of
those registers with the appropriate values as passed in

@chip_compat is used to limit the set of changes that are made
to be compatible with the indicated chip release.  This is used by
drivers to maintain compatibility with chip register settings when
the drivers haven't [yet] been updated with new chip support.
fix up host - dependent parameters @adap : the adapter @page_size : the host ' s Base Page Size @cache_line_size : the host ' s Cache Line Size @chip_compat : maintain compatibility with designated chip Various registers in the chip contain values which are dependent on the host ' s Base Page and Cache Line Sizes . This function will fix all of those registers with the appropriate values as passed in @chip_compat is used to limit the set of changes that are made to be compatible with the indicated chip release . This is used by drivers to maintain compatibility with chip register settings when the drivers haven ' t [ yet ] been updated with new chip support .
int t4_fixup_host_params_compat(struct adapter *adap,
				unsigned int page_size,
				unsigned int cache_line_size,
				enum chip_type chip_compat)
{
	unsigned int page_shift = cxgbe_fls(page_size) - 1;
	unsigned int sge_hps = page_shift - 10;
	unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
	unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
	unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
	t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
		     V_HOSTPAGESIZEPF0(sge_hps) |
		     V_HOSTPAGESIZEPF1(sge_hps) |
		     V_HOSTPAGESIZEPF2(sge_hps) |
		     V_HOSTPAGESIZEPF3(sge_hps) |
		     V_HOSTPAGESIZEPF4(sge_hps) |
		     V_HOSTPAGESIZEPF5(sge_hps) |
		     V_HOSTPAGESIZEPF6(sge_hps) |
		     V_HOSTPAGESIZEPF7(sge_hps));
	if (is_t4(adap->params.chip) || is_t4(chip_compat))
		t4_set_reg_field(adap, A_SGE_CONTROL,
				 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
				 F_EGRSTATUSPAGESIZE,
				 V_INGPADBOUNDARY(fl_align_log -
						  X_INGPADBOUNDARY_SHIFT) |
				V_EGRSTATUSPAGESIZE(stat_len != 64));
	else {
		unsigned int pack_align;
		unsigned int ingpad, ingpack;
		unsigned int pcie_cap;
		pack_align = fl_align;
		pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
		if (pcie_cap) {
			unsigned int mps, mps_log;
			u16 devctl;
			t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
					    &devctl);
			mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
			mps = 1 << mps_log;
			if (mps > pack_align)
				pack_align = mps;
		}
		if (pack_align <= 16) {
			ingpack = X_INGPACKBOUNDARY_16B;
			fl_align = 16;
		} else if (pack_align == 32) {
			ingpack = X_INGPACKBOUNDARY_64B;
			fl_align = 64;
		} else {
			unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
			ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
			fl_align = pack_align;
		}
		if (is_t5(adap->params.chip))
			ingpad = X_INGPADBOUNDARY_32B;
		else
			ingpad = X_T6_INGPADBOUNDARY_8B;
		t4_set_reg_field(adap, A_SGE_CONTROL,
				 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
				 F_EGRSTATUSPAGESIZE,
				 V_INGPADBOUNDARY(ingpad) |
				 V_EGRSTATUSPAGESIZE(stat_len != 64));
		t4_set_reg_field(adap, A_SGE_CONTROL2,
				 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
				 V_INGPACKBOUNDARY(ingpack));
	}
	t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
	t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
		     (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
		     & ~(fl_align - 1));
	t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
		     (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
		     & ~(fl_align - 1));
	t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
	return 0;
}
int t4_fixup_host_params_compat ( struct adapter * adap , unsigned int page_size , unsigned int cache_line_size , enum chip_type chip_compat ) { unsigned int page_shift = cxgbe_fls ( page_size ) - 1 ; unsigned int sge_hps = page_shift - 10 ; unsigned int stat_len = cache_line_size > 64 ? 128 : 64 ; unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size ; unsigned int fl_align_log = cxgbe_fls ( fl_align ) - 1 ; t4_write_reg ( adap , A_SGE_HOST_PAGE_SIZE , V_HOSTPAGESIZEPF0 ( sge_hps ) | V_HOSTPAGESIZEPF1 ( sge_hps ) | V_HOSTPAGESIZEPF2 ( sge_hps ) | V_HOSTPAGESIZEPF3 ( sge_hps ) | V_HOSTPAGESIZEPF4 ( sge_hps ) | V_HOSTPAGESIZEPF5 ( sge_hps ) | V_HOSTPAGESIZEPF6 ( sge_hps ) | V_HOSTPAGESIZEPF7 ( sge_hps ) ) ; if ( is_t4 ( adap -> params . chip ) || is_t4 ( chip_compat ) ) t4_set_reg_field ( adap , A_SGE_CONTROL , V_INGPADBOUNDARY ( M_INGPADBOUNDARY ) | F_EGRSTATUSPAGESIZE , V_INGPADBOUNDARY ( fl_align_log - X_INGPADBOUNDARY_SHIFT ) | V_EGRSTATUSPAGESIZE ( stat_len != 64 ) ) ; else { unsigned int pack_align ; unsigned int ingpad , ingpack ; unsigned int pcie_cap ; pack_align = fl_align ; pcie_cap = t4_os_find_pci_capability ( adap , PCI_CAP_ID_EXP ) ; if ( pcie_cap ) { unsigned int mps , mps_log ; u16 devctl ; t4_os_pci_read_cfg2 ( adap , pcie_cap + PCI_EXP_DEVCTL , & devctl ) ; mps_log = ( ( devctl & PCI_EXP_DEVCTL_PAYLOAD ) >> 5 ) + 7 ; mps = 1 << mps_log ; if ( mps > pack_align ) pack_align = mps ; } if ( pack_align <= 16 ) { ingpack = X_INGPACKBOUNDARY_16B ; fl_align = 16 ; } else if ( pack_align == 32 ) { ingpack = X_INGPACKBOUNDARY_64B ; fl_align = 64 ; } else { unsigned int pack_align_log = cxgbe_fls ( pack_align ) - 1 ; ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT ; fl_align = pack_align ; } if ( is_t5 ( adap -> params . chip ) ) ingpad = X_INGPADBOUNDARY_32B ; else ingpad = X_T6_INGPADBOUNDARY_8B ; t4_set_reg_field ( adap , A_SGE_CONTROL , V_INGPADBOUNDARY ( M_INGPADBOUNDARY ) | F_EGRSTATUSPAGESIZE , V_INGPADBOUNDARY ( ingpad ) | V_EGRSTATUSPAGESIZE ( stat_len != 64 ) ) ; t4_set_reg_field ( adap , A_SGE_CONTROL2 , V_INGPACKBOUNDARY ( M_INGPACKBOUNDARY ) , V_INGPACKBOUNDARY ( ingpack ) ) ; } t4_write_reg ( adap , A_SGE_FL_BUFFER_SIZE0 , page_size ) ; t4_write_reg ( adap , A_SGE_FL_BUFFER_SIZE2 , ( t4_read_reg ( adap , A_SGE_FL_BUFFER_SIZE2 ) + fl_align - 1 ) & ~ ( fl_align - 1 ) ) ; t4_write_reg ( adap , A_SGE_FL_BUFFER_SIZE3 , ( t4_read_reg ( adap , A_SGE_FL_BUFFER_SIZE3 ) + fl_align - 1 ) & ~ ( fl_align - 1 ) ) ; t4_write_reg ( adap , A_ULP_RX_TDDP_PSZ , V_HPZ0 ( page_shift - 12 ) ) ; return 0 ; }
t4_fixup_host_params_compat - fix up host-dependent parameters
 @adap: the adapter
 @page_size: the host's Base Page Size
 @cache_line_size: the host's Cache Line Size
 @chip_compat: maintain compatibility with designated chip
t4_fixup_host_params_compat - fix up host - dependent parameters @adap : the adapter @page_size : the host ' s Base Page Size @cache_line_size : the host ' s Cache Line Size @chip_compat : maintain compatibility with designated chip
/*
		 * T5 introduced the separation of the Free List Padding and
		 * Packing Boundaries.  Thus, we can select a smaller Padding
		 * Boundary to avoid uselessly chewing up PCIe Link and Memory
		 * Bandwidth, and use a Packing Boundary which is large enough
		 * to avoid false sharing between CPUs, etc.
		 *
		 * For the PCI Link, the smaller the Padding Boundary the
		 * better.  For the Memory Controller, a smaller Padding
		 * Boundary is better until we cross under the Memory Line
		 * Size (the minimum unit of transfer to/from Memory).  If we
		 * have a Padding Boundary which is smaller than the Memory
		 * Line Size, that'll involve a Read-Modify-Write cycle on the
		 * Memory Controller which is never good.
		 */ /* We want the Packing Boundary to be based on the Cache Line
		 * Size in order to help avoid False Sharing performance
		 * issues between CPUs, etc.  We also want the Packing
		 * Boundary to incorporate the PCI-E Maximum Payload Size.  We
		 * get best performance when the Packing Boundary is a
		 * multiple of the Maximum Payload Size.
		 */ /* The PCIe Device Control Maximum Payload Size field
			 * [bits 7:5] encodes sizes as powers of 2 starting at
			 * 128 bytes.
			 */ /*
		 * N.B. T5 has a different interpretation of the "0" value for
		 * the Packing Boundary.  This corresponds to 16 bytes instead
		 * of the expected 32 bytes.  We never have a Packing Boundary
		 * less than 32 bytes so we can't use that special value but
		 * on the other hand, if we wanted 32 bytes, the best we can
		 * really do is 64 bytes ...
		 */ /* Use the smallest Ingress Padding which isn't smaller than
		 * the Memory Controller Read/Write Size.  We'll take that as
		 * being 8 bytes since we don't know of any system with a
		 * wider Memory Controller Bus Width.
		 */ /*
	 * Adjust various SGE Free List Host Buffer Sizes.
	 *
	 * The first four entries are:
	 *
	 *   0: Host Page Size
	 *   1: 64KB
	 *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
	 *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
	 *
	 * For the single-MTU buffers in unpacked mode we need to include
	 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
	 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
	 * Padding boundary.  All of these are accommodated in the Factory
	 * Default Firmware Configuration File but we need to adjust it for
	 * this host's cache line size.
	 */