lib/bsp/standalone/src/arm/ARMv8/32bit/xil_cache.c
void Xil_DCacheInvalidateLine(u32 adr)
{

	u32 currmask;

	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);

	/* Select cache level 0 and D cache in CSSR */
	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
	isb();
	mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x3F)));
	/* Wait for invalidate to complete */
	dsb();
	/* Select cache level 1 and D cache in CSSR */
	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
	isb();
	mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x3F)));
	/* Wait for invalidate to complete */
	dsb();
	mtcpsr(currmask);
}
/****************************************************************************/
/**
 * @brief	Invalidate a Data cache line. The cacheline is cleaned and
 *			invalidated.
 *
 * @param	adr: 32 bit address of the data to be invalidated.
 *
 * @return	None.
 *
 * @note	In Cortex-A53, functionality to simply invalid
 *		the cachelines is not present. Such operations
 *		are a problem for an environment that supports
 *		virtualisation. It would allow one OS to invalidate
 *		a line belonging to another OS. This could lead to
 *		the other OS crashing because of the loss of essential
 *		data. Hence, such operations are promoted to clean and
 *		invalidate to avoid such corruption.
 *
 ****************************************************************************/
@brief       Invalidate a Data cache line. The cacheline is cleaned and
invalidated.

@param       adr: 32 bit address of the data to be invalidated.

@return      None.

@note        In Cortex-A53, functionality to simply invalid
the cachelines is not present. Such operations
are a problem for an environment that supports
virtualisation. It would allow one OS to invalidate
a line belonging to another OS. This could lead to
the other OS crashing because of the loss of essential
data. Hence, such operations are promoted to clean and
invalidate to avoid such corruption.
@brief Invalidate a Data cache line . The cacheline is cleaned and invalidated . @param adr : 32 bit address of the data to be invalidated . @return None . @note In Cortex - A53 functionality to simply invalid the cachelines is not present . Such operations are a problem for an environment that supports virtualisation . It would allow one OS to invalidate a line belonging to another OS . This could lead to the other OS crashing because of the loss of essential data . Hence such operations are promoted to clean and invalidate to avoid such corruption .
void Xil_DCacheInvalidateLine(u32 adr)
{
	u32 currmask;
	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);
	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
	isb();
	mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x3F)));
	dsb();
	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
	isb();
	mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x3F)));
	dsb();
	mtcpsr(currmask);
}
void Xil_DCacheInvalidateLine ( u32 adr ) { u32 currmask ; currmask = mfcpsr ( ) ; mtcpsr ( currmask | IRQ_FIQ_MASK ) ; mtcp ( XREG_CP15_CACHE_SIZE_SEL , 0x0 ) ; isb ( ) ; mtcp ( XREG_CP15_INVAL_DC_LINE_MVA_POC , ( adr & ( ~ 0x3F ) ) ) ; dsb ( ) ; mtcp ( XREG_CP15_CACHE_SIZE_SEL , 0x2 ) ; isb ( ) ; mtcp ( XREG_CP15_INVAL_DC_LINE_MVA_POC , ( adr & ( ~ 0x3F ) ) ) ; dsb ( ) ; mtcpsr ( currmask ) ; }
@brief       Invalidate a Data cache line.
@brief Invalidate a Data cache line .
/* Select cache level 0 and D cache in CSSR */ /* Wait for invalidate to complete */ /* Select cache level 1 and D cache in CSSR */ /* Wait for invalidate to complete */