XilinxProcessorIPLib/drivers/vphy/src/xvphy_hdmi_intr.c
void XVphy_HdmiRxTimerTimeoutHandler(XVphy *InstancePtr)
{
	XVphy_ChannelId ChId;
	XVphy_PllType PllType;
	u32 Status;
	u8 Id, Id0, Id1;

	XVphy_LogWrite(InstancePtr, XVPHY_LOG_EVT_RX_TMR, 1);

	/* Determine PLL type. */
	PllType = XVphy_GetPllType(InstancePtr, 0, XVPHY_DIR_RX,
			XVPHY_CHANNEL_ID_CH1);
	/* Determine which channel(s) to operate on. */
	ChId = XVphy_GetRcfgChId(InstancePtr, 0, XVPHY_DIR_RX, PllType);

	XVphy_Ch2Ids(InstancePtr, XVPHY_CHANNEL_ID_CHA, &Id0, &Id1);

	/* Set RX parameters. */
	Status = XVphy_SetHdmiRxParam(InstancePtr, 0, ChId);
	if (Status != XST_SUCCESS) {
		for (Id = Id0; Id <= Id1; Id++) {
			InstancePtr->Quads[0].Plls[XVPHY_CH2IDX(Id)].RxState =
				XVPHY_GT_STATE_IDLE;
			if (XVphy_IsBonded(InstancePtr, 0,
						XVPHY_CHANNEL_ID_CH1)) {
				InstancePtr->Quads[0].Plls[XVPHY_CH2IDX(Id)].
					TxState = XVPHY_GT_STATE_IDLE;
			}
		}

		return;
	}

	/* Enable PLL. */
	if (InstancePtr->Config.XcvrType != XVPHY_GT_TYPE_GTPE2) {
		XVphy_PowerDownGtPll(InstancePtr, 0,
			(PllType == XVPHY_PLL_TYPE_CPLL) ?
			XVPHY_CHANNEL_ID_CHA : XVPHY_CHANNEL_ID_CMNA, FALSE);
	}

	/* Enable DRU to set the clock muxes. */
	XVphy_DruEnable(InstancePtr, XVPHY_CHANNEL_ID_CHA,
			InstancePtr->HdmiRxDruIsEnabled);

	/* Update reference clock election. */
	if (InstancePtr->Config.XcvrType != XVPHY_GT_TYPE_GTPE2) {
		XVphy_CfgPllRefClkSel(InstancePtr, 0,
			((PllType == XVPHY_PLL_TYPE_CPLL) ?
				XVPHY_CHANNEL_ID_CHA : XVPHY_CHANNEL_ID_CMNA),
			((InstancePtr->HdmiRxDruIsEnabled) ?
				InstancePtr->Config.DruRefClkSel :
				InstancePtr->Config.RxRefClkSel));
	}
	/* GTP */
	else {
		XVphy_CfgPllRefClkSel(InstancePtr, 0,
			((PllType == XVPHY_PLL_TYPE_PLL0) ?
				XVPHY_CHANNEL_ID_CMN0 : XVPHY_CHANNEL_ID_CMN1),
			((InstancePtr->HdmiRxDruIsEnabled) ?
				InstancePtr->Config.DruRefClkSel :
				InstancePtr->Config.RxRefClkSel));
	}

	/* Update GT DRU mode. */
	XVphy_HdmiGtDruModeEnable(InstancePtr, InstancePtr->HdmiRxDruIsEnabled);

	/* Update RefClk selection. */
	XVphy_WriteCfgRefClkSelReg(InstancePtr, 0);

	if (InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTPE2) {
		XVphy_ResetGtTxRx(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_RX, TRUE);
        /* GTP Wizard locks the DRP access to its internal FSM during reset */
		/* Wait for reset sequence to release DRP port. */
		XVphy_WaitUs(InstancePtr, 5000);
	}

	/* Determine PLL type. */
	PllType = XVphy_GetPllType(InstancePtr, 0, XVPHY_DIR_RX,
			XVPHY_CHANNEL_ID_CH1);
	/* Determine which channel(s) to operate on. */
	ChId = XVphy_GetRcfgChId(InstancePtr, 0, XVPHY_DIR_RX, PllType);

	XVphy_ClkReconfig(InstancePtr, 0, ChId);
	XVphy_OutDivReconfig(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
			XVPHY_DIR_RX);
	if (XVphy_IsBonded(InstancePtr, 0, XVPHY_CHANNEL_ID_CH1)) {
		XVphy_OutDivReconfig(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_TX);
	}

	XVphy_DirReconfig(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX);

	/* Assert RX PLL reset. */
	XVphy_ResetGtPll(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX,
			TRUE);

	if (InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTXE2) {
		XVphy_ResetGtTxRx(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_RX, TRUE);
	}

	/* De-assert RX PLL reset. */
	XVphy_ResetGtPll(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
			XVPHY_DIR_RX, FALSE);

	/* When the TX and RX are coupled, clear GT alignment. */
	if (XVphy_IsBonded(InstancePtr, 0, XVPHY_CHANNEL_ID_CH1)) {
		if (InstancePtr->HdmiRxDruIsEnabled) {
			XVphy_LogWrite(InstancePtr, XVPHY_LOG_EVT_GT_UNBONDED, 1);
			XVphy_CfgErrIntr(InstancePtr, XVPHY_ERR_BONDED_DRU, 1);
			XVphy_ErrorHandler(InstancePtr);
#if (XPAR_VPHY_0_TRANSCEIVER == XVPHY_GTXE2)
			XVphy_CfgErrIntr(InstancePtr, XVPHY_ERR_PLL_LAYOUT, 1);
			XVphy_PllLayoutErrorHandler(InstancePtr);
#endif
		}
		else {
			XVphy_CfgErrIntr(InstancePtr, XVPHY_ERR_BONDED_DRU, 0);
			XVphy_CfgErrIntr(InstancePtr, XVPHY_ERR_PLL_LAYOUT, 0);
		}
		XVphy_ResetGtPll(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_TX, 0);
		XVphy_TxAlignStart(InstancePtr, ChId, FALSE);
	}
	for (Id = Id0; Id <= Id1; Id++) {
		InstancePtr->Quads[0].Plls[XVPHY_CH2IDX(Id)].RxState =
			XVPHY_GT_STATE_LOCK;
	}
}
/*****************************************************************************/
/**
* This function is the handler for RX timer timeout events.
*
* @param	InstancePtr is a pointer to the VPHY instance.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function is the handler for RX timer timeout events.
This function is the handler for RX timer timeout events .
void XVphy_HdmiRxTimerTimeoutHandler(XVphy *InstancePtr)
{
	XVphy_ChannelId ChId;
	XVphy_PllType PllType;
	u32 Status;
	u8 Id, Id0, Id1;
	XVphy_LogWrite(InstancePtr, XVPHY_LOG_EVT_RX_TMR, 1);
	PllType = XVphy_GetPllType(InstancePtr, 0, XVPHY_DIR_RX,
			XVPHY_CHANNEL_ID_CH1);
	ChId = XVphy_GetRcfgChId(InstancePtr, 0, XVPHY_DIR_RX, PllType);
	XVphy_Ch2Ids(InstancePtr, XVPHY_CHANNEL_ID_CHA, &Id0, &Id1);
	Status = XVphy_SetHdmiRxParam(InstancePtr, 0, ChId);
	if (Status != XST_SUCCESS) {
		for (Id = Id0; Id <= Id1; Id++) {
			InstancePtr->Quads[0].Plls[XVPHY_CH2IDX(Id)].RxState =
				XVPHY_GT_STATE_IDLE;
			if (XVphy_IsBonded(InstancePtr, 0,
						XVPHY_CHANNEL_ID_CH1)) {
				InstancePtr->Quads[0].Plls[XVPHY_CH2IDX(Id)].
					TxState = XVPHY_GT_STATE_IDLE;
			}
		}
		return;
	}
	if (InstancePtr->Config.XcvrType != XVPHY_GT_TYPE_GTPE2) {
		XVphy_PowerDownGtPll(InstancePtr, 0,
			(PllType == XVPHY_PLL_TYPE_CPLL) ?
			XVPHY_CHANNEL_ID_CHA : XVPHY_CHANNEL_ID_CMNA, FALSE);
	}
	XVphy_DruEnable(InstancePtr, XVPHY_CHANNEL_ID_CHA,
			InstancePtr->HdmiRxDruIsEnabled);
	if (InstancePtr->Config.XcvrType != XVPHY_GT_TYPE_GTPE2) {
		XVphy_CfgPllRefClkSel(InstancePtr, 0,
			((PllType == XVPHY_PLL_TYPE_CPLL) ?
				XVPHY_CHANNEL_ID_CHA : XVPHY_CHANNEL_ID_CMNA),
			((InstancePtr->HdmiRxDruIsEnabled) ?
				InstancePtr->Config.DruRefClkSel :
				InstancePtr->Config.RxRefClkSel));
	}
	else {
		XVphy_CfgPllRefClkSel(InstancePtr, 0,
			((PllType == XVPHY_PLL_TYPE_PLL0) ?
				XVPHY_CHANNEL_ID_CMN0 : XVPHY_CHANNEL_ID_CMN1),
			((InstancePtr->HdmiRxDruIsEnabled) ?
				InstancePtr->Config.DruRefClkSel :
				InstancePtr->Config.RxRefClkSel));
	}
	XVphy_HdmiGtDruModeEnable(InstancePtr, InstancePtr->HdmiRxDruIsEnabled);
	XVphy_WriteCfgRefClkSelReg(InstancePtr, 0);
	if (InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTPE2) {
		XVphy_ResetGtTxRx(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_RX, TRUE);
		XVphy_WaitUs(InstancePtr, 5000);
	}
	PllType = XVphy_GetPllType(InstancePtr, 0, XVPHY_DIR_RX,
			XVPHY_CHANNEL_ID_CH1);
	ChId = XVphy_GetRcfgChId(InstancePtr, 0, XVPHY_DIR_RX, PllType);
	XVphy_ClkReconfig(InstancePtr, 0, ChId);
	XVphy_OutDivReconfig(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
			XVPHY_DIR_RX);
	if (XVphy_IsBonded(InstancePtr, 0, XVPHY_CHANNEL_ID_CH1)) {
		XVphy_OutDivReconfig(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_TX);
	}
	XVphy_DirReconfig(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX);
	XVphy_ResetGtPll(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX,
			TRUE);
	if (InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTXE2) {
		XVphy_ResetGtTxRx(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_RX, TRUE);
	}
	XVphy_ResetGtPll(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
			XVPHY_DIR_RX, FALSE);
	if (XVphy_IsBonded(InstancePtr, 0, XVPHY_CHANNEL_ID_CH1)) {
		if (InstancePtr->HdmiRxDruIsEnabled) {
			XVphy_LogWrite(InstancePtr, XVPHY_LOG_EVT_GT_UNBONDED, 1);
			XVphy_CfgErrIntr(InstancePtr, XVPHY_ERR_BONDED_DRU, 1);
			XVphy_ErrorHandler(InstancePtr);
#if (XPAR_VPHY_0_TRANSCEIVER == XVPHY_GTXE2)
			XVphy_CfgErrIntr(InstancePtr, XVPHY_ERR_PLL_LAYOUT, 1);
			XVphy_PllLayoutErrorHandler(InstancePtr);
#endif
		}
		else {
			XVphy_CfgErrIntr(InstancePtr, XVPHY_ERR_BONDED_DRU, 0);
			XVphy_CfgErrIntr(InstancePtr, XVPHY_ERR_PLL_LAYOUT, 0);
		}
		XVphy_ResetGtPll(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_TX, 0);
		XVphy_TxAlignStart(InstancePtr, ChId, FALSE);
	}
	for (Id = Id0; Id <= Id1; Id++) {
		InstancePtr->Quads[0].Plls[XVPHY_CH2IDX(Id)].RxState =
			XVPHY_GT_STATE_LOCK;
	}
}
void XVphy_HdmiRxTimerTimeoutHandler ( XVphy * InstancePtr ) { XVphy_ChannelId ChId ; XVphy_PllType PllType ; u32 Status ; u8 Id , Id0 , Id1 ; XVphy_LogWrite ( InstancePtr , XVPHY_LOG_EVT_RX_TMR , 1 ) ; PllType = XVphy_GetPllType ( InstancePtr , 0 , XVPHY_DIR_RX , XVPHY_CHANNEL_ID_CH1 ) ; ChId = XVphy_GetRcfgChId ( InstancePtr , 0 , XVPHY_DIR_RX , PllType ) ; XVphy_Ch2Ids ( InstancePtr , XVPHY_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; Status = XVphy_SetHdmiRxParam ( InstancePtr , 0 , ChId ) ; if ( Status != XST_SUCCESS ) { for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XVPHY_CH2IDX ( Id ) ] . RxState = XVPHY_GT_STATE_IDLE ; if ( XVphy_IsBonded ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CH1 ) ) { InstancePtr -> Quads [ 0 ] . Plls [ XVPHY_CH2IDX ( Id ) ] . TxState = XVPHY_GT_STATE_IDLE ; } } return ; } if ( InstancePtr -> Config . XcvrType != XVPHY_GT_TYPE_GTPE2 ) { XVphy_PowerDownGtPll ( InstancePtr , 0 , ( PllType == XVPHY_PLL_TYPE_CPLL ) ? XVPHY_CHANNEL_ID_CHA : XVPHY_CHANNEL_ID_CMNA , FALSE ) ; } XVphy_DruEnable ( InstancePtr , XVPHY_CHANNEL_ID_CHA , InstancePtr -> HdmiRxDruIsEnabled ) ; if ( InstancePtr -> Config . XcvrType != XVPHY_GT_TYPE_GTPE2 ) { XVphy_CfgPllRefClkSel ( InstancePtr , 0 , ( ( PllType == XVPHY_PLL_TYPE_CPLL ) ? XVPHY_CHANNEL_ID_CHA : XVPHY_CHANNEL_ID_CMNA ) , ( ( InstancePtr -> HdmiRxDruIsEnabled ) ? InstancePtr -> Config . DruRefClkSel : InstancePtr -> Config . RxRefClkSel ) ) ; } else { XVphy_CfgPllRefClkSel ( InstancePtr , 0 , ( ( PllType == XVPHY_PLL_TYPE_PLL0 ) ? XVPHY_CHANNEL_ID_CMN0 : XVPHY_CHANNEL_ID_CMN1 ) , ( ( InstancePtr -> HdmiRxDruIsEnabled ) ? InstancePtr -> Config . DruRefClkSel : InstancePtr -> Config . RxRefClkSel ) ) ; } XVphy_HdmiGtDruModeEnable ( InstancePtr , InstancePtr -> HdmiRxDruIsEnabled ) ; XVphy_WriteCfgRefClkSelReg ( InstancePtr , 0 ) ; if ( InstancePtr -> Config . XcvrType == XVPHY_GT_TYPE_GTPE2 ) { XVphy_ResetGtTxRx ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX , TRUE ) ; XVphy_WaitUs ( InstancePtr , 5000 ) ; } PllType = XVphy_GetPllType ( InstancePtr , 0 , XVPHY_DIR_RX , XVPHY_CHANNEL_ID_CH1 ) ; ChId = XVphy_GetRcfgChId ( InstancePtr , 0 , XVPHY_DIR_RX , PllType ) ; XVphy_ClkReconfig ( InstancePtr , 0 , ChId ) ; XVphy_OutDivReconfig ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX ) ; if ( XVphy_IsBonded ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CH1 ) ) { XVphy_OutDivReconfig ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_TX ) ; } XVphy_DirReconfig ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX ) ; XVphy_ResetGtPll ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX , TRUE ) ; if ( InstancePtr -> Config . XcvrType == XVPHY_GT_TYPE_GTXE2 ) { XVphy_ResetGtTxRx ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX , TRUE ) ; } XVphy_ResetGtPll ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX , FALSE ) ; if ( XVphy_IsBonded ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CH1 ) ) { if ( InstancePtr -> HdmiRxDruIsEnabled ) { XVphy_LogWrite ( InstancePtr , XVPHY_LOG_EVT_GT_UNBONDED , 1 ) ; XVphy_CfgErrIntr ( InstancePtr , XVPHY_ERR_BONDED_DRU , 1 ) ; XVphy_ErrorHandler ( InstancePtr ) ; #if ( XPAR_VPHY_0_TRANSCEIVER == XVPHY_GTXE2 ) XVphy_CfgErrIntr ( InstancePtr , XVPHY_ERR_PLL_LAYOUT , 1 ) ; XVphy_PllLayoutErrorHandler ( InstancePtr ) ; #endif } else { XVphy_CfgErrIntr ( InstancePtr , XVPHY_ERR_BONDED_DRU , 0 ) ; XVphy_CfgErrIntr ( InstancePtr , XVPHY_ERR_PLL_LAYOUT , 0 ) ; } XVphy_ResetGtPll ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_TX , 0 ) ; XVphy_TxAlignStart ( InstancePtr , ChId , FALSE ) ; } for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XVPHY_CH2IDX ( Id ) ] . RxState = XVPHY_GT_STATE_LOCK ; } }
This function is the handler for RX timer timeout events.
This function is the handler for RX timer timeout events .
/* Determine PLL type. */ /* Determine which channel(s) to operate on. */ /* Set RX parameters. */ /* Enable PLL. */ /* Enable DRU to set the clock muxes. */ /* Update reference clock election. */ /* GTP */ /* Update GT DRU mode. */ /* Update RefClk selection. */ /* GTP Wizard locks the DRP access to its internal FSM during reset */ /* Wait for reset sequence to release DRP port. */ /* Determine PLL type. */ /* Determine which channel(s) to operate on. */ /* Assert RX PLL reset. */ /* De-assert RX PLL reset. */ /* When the TX and RX are coupled, clear GT alignment. */