XilinxProcessorIPLib/drivers/rfdc/src/xrfdc_clock.c
static u32 XRFdc_SetTileClkSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, XRFdc_Tile_Clock_Settings *SettingsPtr)
{
	u32 Status;
	u32 BaseAddr;
	u16 PLLSource;
	u16 NetworkCtrlReg;
	u16 DistCtrlReg;
	u16 PLLRefDivReg;
	u32 PowerStateMaskReg;
	XRFdc_PLL_Settings PLLSettings;

	PLLSource = (SettingsPtr->PLLEnable == XRFDC_ENABLED) ? XRFDC_INTERNAL_PLL_CLK : XRFDC_EXTERNAL_CLK;
	Status = XRFdc_DynamicPLLConfig(InstancePtr, Type, Tile_Id, PLLSource, SettingsPtr->RefClkFreq,
					SettingsPtr->SampleRate);
	if (Status != XRFDC_SUCCESS) {
		metal_log(METAL_LOG_ERROR, "\n Could not set up PLL settings for %s %u %s\r\n",
			  (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
		goto RETURN_PATH;
	}

	if (PLLSource == XRFDC_EXTERNAL_CLK) {
		(void)XRFdc_GetPLLConfig(InstancePtr, Type, Tile_Id, &PLLSettings);
		SettingsPtr->DivisionFactor = PLLSettings.OutputDivider;
	} else {
		SettingsPtr->DivisionFactor = 1U;
	}

	/* in cases where pll output divder is totally bypassed distribute the RX clock instead */
	if ((PLLSource == XRFDC_EXTERNAL_CLK) && (SettingsPtr->DivisionFactor == 1U) &&
	    (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_OUTDIV)) {
		SettingsPtr->DistributedClock = XRFDC_DIST_OUT_RX;
	}

	DistCtrlReg = 0;
	PLLRefDivReg = 0;
	NetworkCtrlReg = 0;
	if ((SettingsPtr->SourceTile == Tile_Id) && (SettingsPtr->SourceType == Type)) {
		if (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_NONE) {
			if (SettingsPtr->PLLEnable == XRFDC_DISABLED) {
				PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF;
				NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1;
				if (SettingsPtr->DivisionFactor < 2) {
					/*
					T1 from Self
					No PLL
					Do Not Use PLL Output Divider
					Do Not Distribute
					*/
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_LOCAL;
					DistCtrlReg |= XRFDC_DIST_CTRL_CLK_T1_SRC_LOCAL;
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_SRC;
				} else {
					/*
					T1 from Self
					No PLL
					Use PLL Output Divider
					Do Not Distribute
					*/
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC;
				}
			} else {
				/*
				T1 from Self
				PLL
				Use PLL Output Divider
				Do Not Distribute
				*/
				NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_PLL;
				PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_RX_PLL;
			}
		} else {
			if (SettingsPtr->PLLEnable == XRFDC_DISABLED) {
				NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1;
				PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF;
				if (SettingsPtr->DivisionFactor < 2) {
					/*
					T1 From Distribution (RX back)
					No PLL
					Do Not Use PLL Output Divider
					Send to Distribution
					*/
					PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF;
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST;
					DistCtrlReg |= XRFDC_DIST_CTRL_TO_T1;
					DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_LOCAL;
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_SRC;
				} else if (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_RX) {
					/*
					RX Back From Distribution
					No PLL
					Use PLL Output Divider
					Send to Distribution
					*/
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_INPUT_DIST;
					DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
					DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_LOCAL;
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC;
				} else {
					/*
					PLL Output Divider Back From Distribution
					No PLL
					Use PLL Output Divider
					Send to Distribution
					*/
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1;
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST;
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_INPUT_DIST;
					DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
					DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_PLL;
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC;
				}

			} else {
				/*
				RX Back From Distribution
				PLL
				Use PLL Output Divider
				Send to Distribution
				*/
				if (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_RX) {
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1;
					PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_DIST;
					DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
					DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_LOCAL;
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_RX_PLL;
				} else {
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST;
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_PLL;
					PLLRefDivReg |= XRFDC_PLLOPDIV_INPUT_DIST_LOCAL;
					DistCtrlReg |= XRFDC_DIST_CTRL_TO_T1;
					DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_PLL;
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_RX_PLL;
				}
			}
		}
	} else {
		if (Type == XRFDC_ADC_TILE) {
			/* This is needed if distributing a full rate clock from ADC 0/1 to ADC 2/3 */
			if ((Tile_Id > XRFDC_TILE_ID1) && (SettingsPtr->SourceTile < XRFDC_TILE_ID2) &&
			    (SettingsPtr->SourceType == XRFDC_ADC_TILE)) {
				DistCtrlReg |= XRFDC_CLK_DISTR_MUX5A_SRC_RX;
			}
		}
		if (SettingsPtr->PLLEnable == XRFDC_DISABLED) {
			PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF;
			if (SettingsPtr->DivisionFactor > 1) {
				/*
				Source From Distribution
				No PLL
				Use PLL Output Divider
				Do Not Distribute
				*/
				NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_INPUT_DIST;
				DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
				PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV;
				if (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_OUTDIV) {
					DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_PLL;
				}
			} else {
				/*
				Source From Distribution
				No PLL
				Do Not Use PLL Output Divider
				Do Not Distribute
				*/
				NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST;
				DistCtrlReg |= XRFDC_DIST_CTRL_TO_T1;
				PowerStateMaskReg = ((Type == XRFDC_ADC_TILE) ? XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV :
										XRFDC_HSCOM_PWR_STATS_DIST_EXT);
			}
		} else {
			/*
			Source From Distribution
			PLL
			Use PLL Output Divider
			Do Not Distribute
			*/
			PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_DIST;
			DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
			PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_PLL;
		}
	}

	/*Write to Registers*/
	if (Type == XRFDC_ADC_TILE) {
		BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id);
	} else {
		BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id);
	}
	BaseAddr += XRFDC_HSCOM_ADDR;
	XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_HSCOM_CLK_DSTR_OFFSET, XRFDC_HSCOM_CLK_DSTR_MASK_ALT, DistCtrlReg);
	XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CLK_NETWORK_CTRL1, XRFDC_HSCOM_NETWORK_CTRL1_MASK, NetworkCtrlReg);
	XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_PLL_REFDIV, XRFDC_PLL_REFDIV_MASK, PLLRefDivReg);
	XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_PWR_STATE_OFFSET, PowerStateMaskReg);
	Status = XRFDC_SUCCESS;
RETURN_PATH:
	return Status;
}
/*****************************************************************************/
/**
*
* This function is used to set the clock settings
*
* @param    InstancePtr is a pointer to the XRfdc instance.
* @param    Type indicates ADC/DAC.
* @param    Tile_Id indicates Tile number (0-3).
* @param    SettingsPtr pointer to set the clock settings
*
* @return
*           - XRFDC_SUCCESS if successful.
*           - XRFDC_FAILURE if no valid distribution found.
*
******************************************************************************/
This function is used to set the clock settings
This function is used to set the clock settings
static u32 XRFdc_SetTileClkSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, XRFdc_Tile_Clock_Settings *SettingsPtr)
{
	u32 Status;
	u32 BaseAddr;
	u16 PLLSource;
	u16 NetworkCtrlReg;
	u16 DistCtrlReg;
	u16 PLLRefDivReg;
	u32 PowerStateMaskReg;
	XRFdc_PLL_Settings PLLSettings;
	PLLSource = (SettingsPtr->PLLEnable == XRFDC_ENABLED) ? XRFDC_INTERNAL_PLL_CLK : XRFDC_EXTERNAL_CLK;
	Status = XRFdc_DynamicPLLConfig(InstancePtr, Type, Tile_Id, PLLSource, SettingsPtr->RefClkFreq,
					SettingsPtr->SampleRate);
	if (Status != XRFDC_SUCCESS) {
		metal_log(METAL_LOG_ERROR, "\n Could not set up PLL settings for %s %u %s\r\n",
			  (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile_Id, __func__);
		goto RETURN_PATH;
	}
	if (PLLSource == XRFDC_EXTERNAL_CLK) {
		(void)XRFdc_GetPLLConfig(InstancePtr, Type, Tile_Id, &PLLSettings);
		SettingsPtr->DivisionFactor = PLLSettings.OutputDivider;
	} else {
		SettingsPtr->DivisionFactor = 1U;
	}
	if ((PLLSource == XRFDC_EXTERNAL_CLK) && (SettingsPtr->DivisionFactor == 1U) &&
	    (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_OUTDIV)) {
		SettingsPtr->DistributedClock = XRFDC_DIST_OUT_RX;
	}
	DistCtrlReg = 0;
	PLLRefDivReg = 0;
	NetworkCtrlReg = 0;
	if ((SettingsPtr->SourceTile == Tile_Id) && (SettingsPtr->SourceType == Type)) {
		if (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_NONE) {
			if (SettingsPtr->PLLEnable == XRFDC_DISABLED) {
				PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF;
				NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1;
				if (SettingsPtr->DivisionFactor < 2) {
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_LOCAL;
					DistCtrlReg |= XRFDC_DIST_CTRL_CLK_T1_SRC_LOCAL;
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_SRC;
				} else {
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC;
				}
			} else {
				NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_PLL;
				PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_RX_PLL;
			}
		} else {
			if (SettingsPtr->PLLEnable == XRFDC_DISABLED) {
				NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1;
				PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF;
				if (SettingsPtr->DivisionFactor < 2) {
					PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF;
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST;
					DistCtrlReg |= XRFDC_DIST_CTRL_TO_T1;
					DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_LOCAL;
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_SRC;
				} else if (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_RX) {
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_INPUT_DIST;
					DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
					DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_LOCAL;
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC;
				} else {
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1;
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST;
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_INPUT_DIST;
					DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
					DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_PLL;
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC;
				}
			} else {
				if (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_RX) {
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1;
					PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_DIST;
					DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
					DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_LOCAL;
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_RX_PLL;
				} else {
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST;
					NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_PLL;
					PLLRefDivReg |= XRFDC_PLLOPDIV_INPUT_DIST_LOCAL;
					DistCtrlReg |= XRFDC_DIST_CTRL_TO_T1;
					DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_PLL;
					PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_RX_PLL;
				}
			}
		}
	} else {
		if (Type == XRFDC_ADC_TILE) {
			if ((Tile_Id > XRFDC_TILE_ID1) && (SettingsPtr->SourceTile < XRFDC_TILE_ID2) &&
			    (SettingsPtr->SourceType == XRFDC_ADC_TILE)) {
				DistCtrlReg |= XRFDC_CLK_DISTR_MUX5A_SRC_RX;
			}
		}
		if (SettingsPtr->PLLEnable == XRFDC_DISABLED) {
			PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF;
			if (SettingsPtr->DivisionFactor > 1) {
				NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_INPUT_DIST;
				DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
				PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV;
				if (SettingsPtr->DistributedClock == XRFDC_DIST_OUT_OUTDIV) {
					DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_PLL;
				}
			} else {
				NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST;
				DistCtrlReg |= XRFDC_DIST_CTRL_TO_T1;
				PowerStateMaskReg = ((Type == XRFDC_ADC_TILE) ? XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV :
										XRFDC_HSCOM_PWR_STATS_DIST_EXT);
			}
		} else {
			PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_DIST;
			DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV;
			PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_PLL;
		}
	}
	if (Type == XRFDC_ADC_TILE) {
		BaseAddr = XRFDC_ADC_TILE_DRP_ADDR(Tile_Id);
	} else {
		BaseAddr = XRFDC_DAC_TILE_DRP_ADDR(Tile_Id);
	}
	BaseAddr += XRFDC_HSCOM_ADDR;
	XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_HSCOM_CLK_DSTR_OFFSET, XRFDC_HSCOM_CLK_DSTR_MASK_ALT, DistCtrlReg);
	XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_CLK_NETWORK_CTRL1, XRFDC_HSCOM_NETWORK_CTRL1_MASK, NetworkCtrlReg);
	XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_PLL_REFDIV, XRFDC_PLL_REFDIV_MASK, PLLRefDivReg);
	XRFdc_WriteReg16(InstancePtr, BaseAddr, XRFDC_HSCOM_PWR_STATE_OFFSET, PowerStateMaskReg);
	Status = XRFDC_SUCCESS;
RETURN_PATH:
	return Status;
}
static u32 XRFdc_SetTileClkSettings ( XRFdc * InstancePtr , u32 Type , u32 Tile_Id , XRFdc_Tile_Clock_Settings * SettingsPtr ) { u32 Status ; u32 BaseAddr ; u16 PLLSource ; u16 NetworkCtrlReg ; u16 DistCtrlReg ; u16 PLLRefDivReg ; u32 PowerStateMaskReg ; XRFdc_PLL_Settings PLLSettings ; PLLSource = ( SettingsPtr -> PLLEnable == XRFDC_ENABLED ) ? XRFDC_INTERNAL_PLL_CLK : XRFDC_EXTERNAL_CLK ; Status = XRFdc_DynamicPLLConfig ( InstancePtr , Type , Tile_Id , PLLSource , SettingsPtr -> RefClkFreq , SettingsPtr -> SampleRate ) ; if ( Status != XRFDC_SUCCESS ) { metal_log ( METAL_LOG_ERROR , " \n \r \n " , ( Type == XRFDC_ADC_TILE ) ? " " : " " , Tile_Id , __func__ ) ; goto RETURN_PATH ; } if ( PLLSource == XRFDC_EXTERNAL_CLK ) { ( void ) XRFdc_GetPLLConfig ( InstancePtr , Type , Tile_Id , & PLLSettings ) ; SettingsPtr -> DivisionFactor = PLLSettings . OutputDivider ; } else { SettingsPtr -> DivisionFactor = 1U ; } if ( ( PLLSource == XRFDC_EXTERNAL_CLK ) && ( SettingsPtr -> DivisionFactor == 1U ) && ( SettingsPtr -> DistributedClock == XRFDC_DIST_OUT_OUTDIV ) ) { SettingsPtr -> DistributedClock = XRFDC_DIST_OUT_RX ; } DistCtrlReg = 0 ; PLLRefDivReg = 0 ; NetworkCtrlReg = 0 ; if ( ( SettingsPtr -> SourceTile == Tile_Id ) && ( SettingsPtr -> SourceType == Type ) ) { if ( SettingsPtr -> DistributedClock == XRFDC_DIST_OUT_NONE ) { if ( SettingsPtr -> PLLEnable == XRFDC_DISABLED ) { PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF ; NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1 ; if ( SettingsPtr -> DivisionFactor < 2 ) { NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_LOCAL ; DistCtrlReg |= XRFDC_DIST_CTRL_CLK_T1_SRC_LOCAL ; PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_SRC ; } else { PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC ; } } else { NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_PLL ; PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_RX_PLL ; } } else { if ( SettingsPtr -> PLLEnable == XRFDC_DISABLED ) { NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1 ; PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF ; if ( SettingsPtr -> DivisionFactor < 2 ) { PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF ; NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST ; DistCtrlReg |= XRFDC_DIST_CTRL_TO_T1 ; DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_LOCAL ; PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_SRC ; } else if ( SettingsPtr -> DistributedClock == XRFDC_DIST_OUT_RX ) { NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_INPUT_DIST ; DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV ; DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_LOCAL ; PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC ; } else { NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1 ; NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST ; NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_INPUT_DIST ; DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV ; DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_PLL ; PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV_SRC ; } } else { if ( SettingsPtr -> DistributedClock == XRFDC_DIST_OUT_RX ) { NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_DIST_T1 ; PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_DIST ; DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV ; DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_LOCAL ; PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_RX_PLL ; } else { NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST ; NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_REC_PLL ; PLLRefDivReg |= XRFDC_PLLOPDIV_INPUT_DIST_LOCAL ; DistCtrlReg |= XRFDC_DIST_CTRL_TO_T1 ; DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_PLL ; PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_RX_PLL ; } } } } else { if ( Type == XRFDC_ADC_TILE ) { if ( ( Tile_Id > XRFDC_TILE_ID1 ) && ( SettingsPtr -> SourceTile < XRFDC_TILE_ID2 ) && ( SettingsPtr -> SourceType == XRFDC_ADC_TILE ) ) { DistCtrlReg |= XRFDC_CLK_DISTR_MUX5A_SRC_RX ; } } if ( SettingsPtr -> PLLEnable == XRFDC_DISABLED ) { PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_OFF ; if ( SettingsPtr -> DivisionFactor > 1 ) { NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_INPUT_DIST ; DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV ; PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV ; if ( SettingsPtr -> DistributedClock == XRFDC_DIST_OUT_OUTDIV ) { DistCtrlReg |= XRFDC_DIST_CTRL_DIST_SRC_PLL ; } } else { NetworkCtrlReg |= XRFDC_NET_CTRL_CLK_T1_SRC_DIST ; DistCtrlReg |= XRFDC_DIST_CTRL_TO_T1 ; PowerStateMaskReg = ( ( Type == XRFDC_ADC_TILE ) ? XRFDC_HSCOM_PWR_STATS_DIST_EXT_DIV : XRFDC_HSCOM_PWR_STATS_DIST_EXT ) ; } } else { PLLRefDivReg |= XRFDC_PLLREFDIV_INPUT_DIST ; DistCtrlReg |= XRFDC_DIST_CTRL_TO_PLL_DIV ; PowerStateMaskReg = XRFDC_HSCOM_PWR_STATS_DIST_PLL ; } } if ( Type == XRFDC_ADC_TILE ) { BaseAddr = XRFDC_ADC_TILE_DRP_ADDR ( Tile_Id ) ; } else { BaseAddr = XRFDC_DAC_TILE_DRP_ADDR ( Tile_Id ) ; } BaseAddr += XRFDC_HSCOM_ADDR ; XRFdc_ClrSetReg ( InstancePtr , BaseAddr , XRFDC_HSCOM_CLK_DSTR_OFFSET , XRFDC_HSCOM_CLK_DSTR_MASK_ALT , DistCtrlReg ) ; XRFdc_ClrSetReg ( InstancePtr , BaseAddr , XRFDC_CLK_NETWORK_CTRL1 , XRFDC_HSCOM_NETWORK_CTRL1_MASK , NetworkCtrlReg ) ; XRFdc_ClrSetReg ( InstancePtr , BaseAddr , XRFDC_PLL_REFDIV , XRFDC_PLL_REFDIV_MASK , PLLRefDivReg ) ; XRFdc_WriteReg16 ( InstancePtr , BaseAddr , XRFDC_HSCOM_PWR_STATE_OFFSET , PowerStateMaskReg ) ; Status = XRFDC_SUCCESS ; RETURN_PATH : return Status ; }
This function is used to set the clock settings
This function is used to set the clock settings
/* in cases where pll output divder is totally bypassed distribute the RX clock instead */ /*
					T1 from Self
					No PLL
					Do Not Use PLL Output Divider
					Do Not Distribute
					*/ /*
					T1 from Self
					No PLL
					Use PLL Output Divider
					Do Not Distribute
					*/ /*
				T1 from Self
				PLL
				Use PLL Output Divider
				Do Not Distribute
				*/ /*
					T1 From Distribution (RX back)
					No PLL
					Do Not Use PLL Output Divider
					Send to Distribution
					*/ /*
					RX Back From Distribution
					No PLL
					Use PLL Output Divider
					Send to Distribution
					*/ /*
					PLL Output Divider Back From Distribution
					No PLL
					Use PLL Output Divider
					Send to Distribution
					*/ /*
				RX Back From Distribution
				PLL
				Use PLL Output Divider
				Send to Distribution
				*/ /* This is needed if distributing a full rate clock from ADC 0/1 to ADC 2/3 */ /*
				Source From Distribution
				No PLL
				Use PLL Output Divider
				Do Not Distribute
				*/ /*
				Source From Distribution
				No PLL
				Do Not Use PLL Output Divider
				Do Not Distribute
				*/ /*
			Source From Distribution
			PLL
			Use PLL Output Divider
			Do Not Distribute
			*/ /*Write to Registers*/