XilinxProcessorIPLib/drivers/uartpsv/src/xuartpsv.c
s32 XUartPsv_CfgInitialize(XUartPsv *InstancePtr,
			XUartPsv_Config * Config, UINTPTR EffectiveAddr)
{
	s32 Status;
	u32 LineCtrlRegister;
	u32 BaudRate;

	/* Assert validates the input arguments */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(Config != NULL);

	/* Setup the driver instance using passed in parameters */
	InstancePtr->Config.BaseAddress = EffectiveAddr;
	InstancePtr->Config.InputClockHz = Config->InputClockHz;
	InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;

	/* Initialize other instance data to default values */
	InstancePtr->Handler = XUartPsv_StubHandler;

	InstancePtr->SendBuffer.NextBytePtr = NULL;
	InstancePtr->SendBuffer.RemainingBytes = 0U;
	InstancePtr->SendBuffer.RequestedBytes = 0U;

	InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
	InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
	InstancePtr->ReceiveBuffer.RequestedBytes = 0U;

	/* Flag that the driver instance is ready to use */
	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;

	/*
	 * Set the default baud rate here, can be changed prior to
	 * starting the device
	 */
	BaudRate = (u32)XUARTPSV_DFT_BAUDRATE;

	Status = XUartPsv_SetBaudRate(InstancePtr, BaudRate);
	if (Status != (s32)XST_SUCCESS) {
		InstancePtr->IsReady = 0U;
	} else {
		/* Set the FIFO trigger level to 1/2 full of Fifo's size */
		XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
				XUARTPSV_UARTIFLS_OFFSET,
				((u32)XUARTPSV_UARTIFLS_RXIFLSEL_1_2 |
				(u32)XUARTPSV_UARTIFLS_TXIFLSEL_1_2));

		/*
		 * Set up the default data format: 8 bit data, 1 stop bit,
		 * no parity
		 */
		LineCtrlRegister = XUartPsv_ReadReg(InstancePtr->Config.
						BaseAddress,
						XUARTPSV_UARTLCR_OFFSET);

		/* Mask off what's already there */
		LineCtrlRegister &= (~((u32)XUARTPSV_UARTLCR_WLEN_MASK |
					(u32)XUARTPSV_UARTLCR_STP_MASK |
					(u32)XUARTPSV_UARTLCR_PARITY_MASK));

		/* Set the register value to the desired data format */
		LineCtrlRegister |= ((u32)XUARTPSV_UARTLCR_WLEN_8_BIT |
					(u32)XUARTPSV_UARTLCR_STP_1_BIT |
					(u32)XUARTPSV_UARTLCR_PARITY_NONE);

		/* Enable fifo's */
		LineCtrlRegister |= XUARTPSV_UARTLCR_FEN;

		/* Write the line controller register out */
		XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
				XUARTPSV_UARTLCR_OFFSET, LineCtrlRegister);

		/*
		 * Disable all interrupts and cleared
		 * Polled mode is the default
		 */
		XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
				XUARTPSV_UARTIMSC_OFFSET, 0x0);
		XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
				XUARTPSV_UARTICR_OFFSET,
				XUARTPSV_UARTIMSC_MASK);

		Status = (s32)XST_SUCCESS;
	}

	return Status;
}
/*****************************************************************************/
/**
*
* Initializes a specific XUartPsv instance such that it is ready to be used.
* The data format of the device is setup for 8 data bits, 1 stop bit, and no
* parity by default. The baud rate is set to a default value specified by
* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
* receive FIFO threshold is set for 8 bytes. The default operating mode of
* the driver is polled mode.
*
* @param	InstancePtr is a pointer to the XUartPsv instance.
* @param	Config is a reference to a structure containing information
*		about a specific XUartPsv driver.
* @param	EffectiveAddr is the device base address in the virtual memory
*		address space. The caller is responsible for keeping the
*		address mapping from EffectiveAddr to the device physical base
*		address unchanged once this function is invoked. Unexpected
*		errors may occur if the address mapping changes after this
*		function is called. If address translation is not used, pass
*		in the physical address instead.
*
* @return
*		- XST_SUCCESS if initialization was successful
*		- XST_UART_BAUD_ERROR if the baud rate is not possible because
*		  the inputclock frequency is not divisible with an acceptable
*		  amount of error
*
* @note
* The default configuration for the UART after initialization is:
*
* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
* - 8 data bits
* - 1 stop bit
* - no parity
* - FIFO's are enabled with a threshold of 16 ytes
*
*   All interrupts are disabled.
*
******************************************************************************/
Initializes a specific XUartPsv instance such that it is ready to be used.
The data format of the device is setup for 8 data bits, 1 stop bit, and no
parity by default. The baud rate is set to a default value specified by
Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
receive FIFO threshold is set for 8 bytes. The default operating mode of
the driver is polled mode.
Initializes a specific XUartPsv instance such that it is ready to be used . The data format of the device is setup for 8 data bits 1 stop bit and no parity by default . The baud rate is set to a default value specified by Config - > DefaultBaudRate if set otherwise it is set to 19 . 2K baud . The receive FIFO threshold is set for 8 bytes . The default operating mode of the driver is polled mode .
s32 XUartPsv_CfgInitialize(XUartPsv *InstancePtr,
			XUartPsv_Config * Config, UINTPTR EffectiveAddr)
{
	s32 Status;
	u32 LineCtrlRegister;
	u32 BaudRate;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(Config != NULL);
	InstancePtr->Config.BaseAddress = EffectiveAddr;
	InstancePtr->Config.InputClockHz = Config->InputClockHz;
	InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
	InstancePtr->Handler = XUartPsv_StubHandler;
	InstancePtr->SendBuffer.NextBytePtr = NULL;
	InstancePtr->SendBuffer.RemainingBytes = 0U;
	InstancePtr->SendBuffer.RequestedBytes = 0U;
	InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
	InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
	InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
	BaudRate = (u32)XUARTPSV_DFT_BAUDRATE;
	Status = XUartPsv_SetBaudRate(InstancePtr, BaudRate);
	if (Status != (s32)XST_SUCCESS) {
		InstancePtr->IsReady = 0U;
	} else {
		XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
				XUARTPSV_UARTIFLS_OFFSET,
				((u32)XUARTPSV_UARTIFLS_RXIFLSEL_1_2 |
				(u32)XUARTPSV_UARTIFLS_TXIFLSEL_1_2));
		LineCtrlRegister = XUartPsv_ReadReg(InstancePtr->Config.
						BaseAddress,
						XUARTPSV_UARTLCR_OFFSET);
		LineCtrlRegister &= (~((u32)XUARTPSV_UARTLCR_WLEN_MASK |
					(u32)XUARTPSV_UARTLCR_STP_MASK |
					(u32)XUARTPSV_UARTLCR_PARITY_MASK));
		LineCtrlRegister |= ((u32)XUARTPSV_UARTLCR_WLEN_8_BIT |
					(u32)XUARTPSV_UARTLCR_STP_1_BIT |
					(u32)XUARTPSV_UARTLCR_PARITY_NONE);
		LineCtrlRegister |= XUARTPSV_UARTLCR_FEN;
		XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
				XUARTPSV_UARTLCR_OFFSET, LineCtrlRegister);
		XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
				XUARTPSV_UARTIMSC_OFFSET, 0x0);
		XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
				XUARTPSV_UARTICR_OFFSET,
				XUARTPSV_UARTIMSC_MASK);
		Status = (s32)XST_SUCCESS;
	}
	return Status;
}
s32 XUartPsv_CfgInitialize ( XUartPsv * InstancePtr , XUartPsv_Config * Config , UINTPTR EffectiveAddr ) { s32 Status ; u32 LineCtrlRegister ; u32 BaudRate ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( Config != NULL ) ; InstancePtr -> Config . BaseAddress = EffectiveAddr ; InstancePtr -> Config . InputClockHz = Config -> InputClockHz ; InstancePtr -> Config . ModemPinsConnected = Config -> ModemPinsConnected ; InstancePtr -> Handler = XUartPsv_StubHandler ; InstancePtr -> SendBuffer . NextBytePtr = NULL ; InstancePtr -> SendBuffer . RemainingBytes = 0U ; InstancePtr -> SendBuffer . RequestedBytes = 0U ; InstancePtr -> ReceiveBuffer . NextBytePtr = NULL ; InstancePtr -> ReceiveBuffer . RemainingBytes = 0U ; InstancePtr -> ReceiveBuffer . RequestedBytes = 0U ; InstancePtr -> IsReady = XIL_COMPONENT_IS_READY ; BaudRate = ( u32 ) XUARTPSV_DFT_BAUDRATE ; Status = XUartPsv_SetBaudRate ( InstancePtr , BaudRate ) ; if ( Status != ( s32 ) XST_SUCCESS ) { InstancePtr -> IsReady = 0U ; } else { XUartPsv_WriteReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTIFLS_OFFSET , ( ( u32 ) XUARTPSV_UARTIFLS_RXIFLSEL_1_2 | ( u32 ) XUARTPSV_UARTIFLS_TXIFLSEL_1_2 ) ) ; LineCtrlRegister = XUartPsv_ReadReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTLCR_OFFSET ) ; LineCtrlRegister &= ( ~ ( ( u32 ) XUARTPSV_UARTLCR_WLEN_MASK | ( u32 ) XUARTPSV_UARTLCR_STP_MASK | ( u32 ) XUARTPSV_UARTLCR_PARITY_MASK ) ) ; LineCtrlRegister |= ( ( u32 ) XUARTPSV_UARTLCR_WLEN_8_BIT | ( u32 ) XUARTPSV_UARTLCR_STP_1_BIT | ( u32 ) XUARTPSV_UARTLCR_PARITY_NONE ) ; LineCtrlRegister |= XUARTPSV_UARTLCR_FEN ; XUartPsv_WriteReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTLCR_OFFSET , LineCtrlRegister ) ; XUartPsv_WriteReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTIMSC_OFFSET , 0x0 ) ; XUartPsv_WriteReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTICR_OFFSET , XUARTPSV_UARTIMSC_MASK ) ; Status = ( s32 ) XST_SUCCESS ; } return Status ; }
Initializes a specific XUartPsv instance such that it is ready to be used.
Initializes a specific XUartPsv instance such that it is ready to be used .
/* Assert validates the input arguments */ /* Setup the driver instance using passed in parameters */ /* Initialize other instance data to default values */ /* Flag that the driver instance is ready to use */ /*
	 * Set the default baud rate here, can be changed prior to
	 * starting the device
	 */ /* Set the FIFO trigger level to 1/2 full of Fifo's size */ /*
		 * Set up the default data format: 8 bit data, 1 stop bit,
		 * no parity
		 */ /* Mask off what's already there */ /* Set the register value to the desired data format */ /* Enable fifo's */ /* Write the line controller register out */ /*
		 * Disable all interrupts and cleared
		 * Polled mode is the default
		 */