XilinxProcessorIPLib/drivers/vphy/src/xvphy_gtpe2.c
u32 XVphy_Gtpe2RxChReconfig(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
{
	XVphy_Channel *ChPtr;
	u16 DrpVal;
	u8 CfgIndex;
    u32 Status = XST_SUCCESS;

	ChPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(ChId)];

	/* RXCDR_CFG(CfgIndex) */
	for (CfgIndex = 0; CfgIndex < 5; CfgIndex++) {
		DrpVal = ChPtr->PllParams.Cdr[CfgIndex];
		if (!DrpVal) {
			/* Don't modify RX_CDR configuration. */
			continue;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId,
				XVPHY_DRP_RXCDR_CFG(CfgIndex), DrpVal);
	}

	if ((XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX)) &&
	    (InstancePtr->HdmiRxDruIsEnabled)) {
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x2A,0x0);
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x2B,0x0);

		/* Set RX_DATA_WIDTH to 20 bits */
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId,
				XVPHY_DRP_RXDATAWIDTH, &DrpVal);
		DrpVal &= ~0x3800;
		DrpVal |= (3 << 11);
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId,
                XVPHY_DRP_RXDATAWIDTH, DrpVal);
	}

	Status |= XVphy_Gtpe2RxPllRefClkDiv1Reconfig(InstancePtr, QuadId, ChId);

	return Status;
}
/*****************************************************************************/
/**
* This function will configure the channel's RX settings.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
*
* @return
*		- XST_SUCCESS if the configuration was successful.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function will configure the channel's RX settings.
This function will configure the channel ' s RX settings .
u32 XVphy_Gtpe2RxChReconfig(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
{
	XVphy_Channel *ChPtr;
	u16 DrpVal;
	u8 CfgIndex;
    u32 Status = XST_SUCCESS;
	ChPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(ChId)];
	for (CfgIndex = 0; CfgIndex < 5; CfgIndex++) {
		DrpVal = ChPtr->PllParams.Cdr[CfgIndex];
		if (!DrpVal) {
			continue;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId,
				XVPHY_DRP_RXCDR_CFG(CfgIndex), DrpVal);
	}
	if ((XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX)) &&
	    (InstancePtr->HdmiRxDruIsEnabled)) {
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x2A,0x0);
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x2B,0x0);
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId,
				XVPHY_DRP_RXDATAWIDTH, &DrpVal);
		DrpVal &= ~0x3800;
		DrpVal |= (3 << 11);
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId,
                XVPHY_DRP_RXDATAWIDTH, DrpVal);
	}
	Status |= XVphy_Gtpe2RxPllRefClkDiv1Reconfig(InstancePtr, QuadId, ChId);
	return Status;
}
u32 XVphy_Gtpe2RxChReconfig ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId ChId ) { XVphy_Channel * ChPtr ; u16 DrpVal ; u8 CfgIndex ; u32 Status = XST_SUCCESS ; ChPtr = & InstancePtr -> Quads [ QuadId ] . Plls [ XVPHY_CH2IDX ( ChId ) ] ; for ( CfgIndex = 0 ; CfgIndex < 5 ; CfgIndex ++ ) { DrpVal = ChPtr -> PllParams . Cdr [ CfgIndex ] ; if ( ! DrpVal ) { continue ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , XVPHY_DRP_RXCDR_CFG ( CfgIndex ) , DrpVal ) ; } if ( ( XVphy_IsHDMI ( InstancePtr , XVPHY_DIR_RX ) ) && ( InstancePtr -> HdmiRxDruIsEnabled ) ) { Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x2A , 0x0 ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x2B , 0x0 ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , XVPHY_DRP_RXDATAWIDTH , & DrpVal ) ; DrpVal &= ~ 0x3800 ; DrpVal |= ( 3 << 11 ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , XVPHY_DRP_RXDATAWIDTH , DrpVal ) ; } Status |= XVphy_Gtpe2RxPllRefClkDiv1Reconfig ( InstancePtr , QuadId , ChId ) ; return Status ; }
This function will configure the channel's RX settings.
This function will configure the channel ' s RX settings .
/* RXCDR_CFG(CfgIndex) */ /* Don't modify RX_CDR configuration. */ /* Set RX_DATA_WIDTH to 20 bits */