XilinxProcessorIPLib/drivers/csi2tx/src/xcsi2tx_intr.c
void XCsi2Tx_InterruptClear(XCsi2Tx *InstancePtr, u32 Mask)
{
	u32 AllMask = XCSI2TX_ISR_ALLINTR_MASK;
	/* Verify arguments */
	Xil_AssertVoid(InstancePtr != NULL);

	if (InstancePtr->Config.FEGenEnabled) {
		AllMask |= XCSITX_LCSTAT_VC0_ISR_MASK;
		AllMask |= XCSITX_LCSTAT_VC1_ISR_MASK;
		AllMask |= XCSITX_LCSTAT_VC2_ISR_MASK;
		AllMask |= XCSITX_LCSTAT_VC3_ISR_MASK;
	}
	/* Checking for invalid mask bits being set */
	Xil_AssertVoid((Mask & ~AllMask) == 0);

	Mask &= XCsi2Tx_ReadReg(InstancePtr->Config.BaseAddr,
						XCSI2TX_ISR_OFFSET);

	XCsi2Tx_WriteReg(InstancePtr->Config.BaseAddr, XCSI2TX_ISR_OFFSET,
				Mask & AllMask);
}
/*****************************************************************************/
/**
* This function will clear the interrupts set in the Interrupt Status
* Register of the CSI2 Tx core
*
* @param	InstancePtr is the XCsi instance to operate on
* @param	Mask is Interrupt Mask with bits set for corresponding interrupt
* 		to be cleared in the Interrupt Status register
*
* @return 	None
*
* @note		None
*
****************************************************************************/
This function will clear the interrupts set in the Interrupt Status
Register of the CSI2 Tx core
This function will clear the interrupts set in the Interrupt Status Register of the CSI2 Tx core
void XCsi2Tx_InterruptClear(XCsi2Tx *InstancePtr, u32 Mask)
{
	u32 AllMask = XCSI2TX_ISR_ALLINTR_MASK;
	Xil_AssertVoid(InstancePtr != NULL);
	if (InstancePtr->Config.FEGenEnabled) {
		AllMask |= XCSITX_LCSTAT_VC0_ISR_MASK;
		AllMask |= XCSITX_LCSTAT_VC1_ISR_MASK;
		AllMask |= XCSITX_LCSTAT_VC2_ISR_MASK;
		AllMask |= XCSITX_LCSTAT_VC3_ISR_MASK;
	}
	Xil_AssertVoid((Mask & ~AllMask) == 0);
	Mask &= XCsi2Tx_ReadReg(InstancePtr->Config.BaseAddr,
						XCSI2TX_ISR_OFFSET);
	XCsi2Tx_WriteReg(InstancePtr->Config.BaseAddr, XCSI2TX_ISR_OFFSET,
				Mask & AllMask);
}
void XCsi2Tx_InterruptClear ( XCsi2Tx * InstancePtr , u32 Mask ) { u32 AllMask = XCSI2TX_ISR_ALLINTR_MASK ; Xil_AssertVoid ( InstancePtr != NULL ) ; if ( InstancePtr -> Config . FEGenEnabled ) { AllMask |= XCSITX_LCSTAT_VC0_ISR_MASK ; AllMask |= XCSITX_LCSTAT_VC1_ISR_MASK ; AllMask |= XCSITX_LCSTAT_VC2_ISR_MASK ; AllMask |= XCSITX_LCSTAT_VC3_ISR_MASK ; } Xil_AssertVoid ( ( Mask & ~ AllMask ) == 0 ) ; Mask &= XCsi2Tx_ReadReg ( InstancePtr -> Config . BaseAddr , XCSI2TX_ISR_OFFSET ) ; XCsi2Tx_WriteReg ( InstancePtr -> Config . BaseAddr , XCSI2TX_ISR_OFFSET , Mask & AllMask ) ; }
This function will clear the interrupts set in the Interrupt Status
Register of the CSI2 Tx core
This function will clear the interrupts set in the Interrupt Status Register of the CSI2 Tx core
/* Verify arguments */ /* Checking for invalid mask bits being set */