XilinxProcessorIPLib/drivers/rfdc/src/xrfdc_clock.c
u32 XRFdc_GetClkDistribution(XRFdc *InstancePtr, XRFdc_Distribution_System_Settings *DistributionSystemPtr)
{
	u32 Status;
	u32 ClockDetReg;
	u32 DistRegCurrent;
	u32 DistRegSrc;
	s8 CurrentTile;
	u8 DelayOutSourceLeft;
	u8 DelayOutSourceRight;
	XRFdc_Tile_Clock_Settings *ClockSettingsPtr;
	u32 Type;
	u32 SrcType;
	u32 Tile;
	u32 SrcTile;
	u8 PkgSrcTile;
	u8 Distribution;
	u8 i;
	u8 PrevSrc;
	u8 FirstTile;
	u8 TileLayout;
	XRFdc_Distribution_Settings *DistributionSettingsPtr;
	XRFdc_PLL_Settings PLLSettings;

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(DistributionSystemPtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);

	if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
		Status = XRFDC_FAILURE;
		metal_log(METAL_LOG_ERROR, "\n Requested fuctionality not available for this IP in %s\r\n", __func__);
		goto RETURN_PATH;
	}
	memset(DistributionSystemPtr, 0, sizeof(XRFdc_Distribution_System_Settings));
	TileLayout = XRFdc_GetTileLayout(InstancePtr);
	FirstTile = (TileLayout == XRFDC_3ADC_2DAC_TILES) ? XRFDC_CLK_DST_TILE_228 : XRFDC_CLK_DST_TILE_231;
	PrevSrc = XRFDC_CLK_DST_INVALID;

	for (CurrentTile = FirstTile, Distribution = 0; CurrentTile <= XRFDC_CLK_DST_TILE_224; CurrentTile++) {
		XRFdc_DistTile2TypeTile(InstancePtr, CurrentTile, &Type, &Tile);
		Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile);
		if (Status != XRFDC_SUCCESS) {
			continue;
		}
		DelayOutSourceLeft = 0;
		DelayOutSourceRight = 0;

		ClockDetReg = XRFdc_RDReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile), XRFDC_CLOCK_DETECT_OFFSET,
					  XRFDC_CLOCK_DETECT_SRC_MASK);
		if (ClockDetReg != XRFDC_DISABLED) {
			for (i = 0; i <= XRFDC_CLK_DST_TILE_224 - FirstTile; i++) {
				if ((ClockDetReg >> (i << 1)) == XRFDC_ENABLED) {
					PkgSrcTile = XRFDC_CLK_DST_TILE_224 - i;
					if (PrevSrc != PkgSrcTile) {
						if (PrevSrc != XRFDC_CLK_DST_INVALID) {
							Distribution++;
						}
						DistributionSettingsPtr =
							&(DistributionSystemPtr->Distributions[Distribution]);
						XRFdc_DistTile2TypeTile(InstancePtr, PkgSrcTile, &SrcType, &SrcTile);
						DistributionSettingsPtr->Info.LowerBound = CurrentTile;
						DistributionSettingsPtr->SourceTileId = SrcTile;
						DistributionSettingsPtr->SourceType = SrcType;
						DistributionSettingsPtr->Info.MaxDelay = 0U;
						DistributionSettingsPtr->Info.MinDelay = 0xFFU;
						DistributionSettingsPtr->EdgeTileIds[0] = Tile;
						DistributionSettingsPtr->EdgeTypes[0] = Type;
						DistRegSrc = XRFdc_ReadReg16(InstancePtr,
									     XRFDC_DRP_BASE(SrcType, SrcTile) +
										     XRFDC_HSCOM_ADDR,
									     XRFDC_HSCOM_CLK_DSTR_OFFSET);
					}
					ClockSettingsPtr = &(DistributionSettingsPtr->Info.ClkSettings[Type][Tile]);
					DistributionSettingsPtr->EdgeTileIds[1] = Tile;
					DistributionSettingsPtr->EdgeTypes[1] = Type;
					PrevSrc = PkgSrcTile;
					DistRegCurrent = XRFdc_ReadReg16(InstancePtr,
									 XRFDC_DRP_BASE(Type, Tile) + XRFDC_HSCOM_ADDR,
									 XRFDC_HSCOM_CLK_DSTR_OFFSET);
					if (((DistRegCurrent & XRFDC_DIST_CTRL_DIST_SRC_LOCAL) ==
					     XRFDC_DIST_CTRL_DIST_SRC_LOCAL) &&
					    (PkgSrcTile == CurrentTile)) {
						ClockSettingsPtr->DistributedClock = XRFDC_DIST_OUT_RX;
					} else if ((DistRegCurrent & XRFDC_DIST_CTRL_DIST_SRC_PLL) ==
						   XRFDC_DIST_CTRL_DIST_SRC_PLL) {
						ClockSettingsPtr->DistributedClock = XRFDC_DIST_OUT_OUTDIV;
					} else {
						ClockSettingsPtr->DistributedClock = XRFDC_DIST_OUT_NONE;
					}

					if (DistRegSrc & XRFDC_CLK_DISTR_MUX7_SRC_STH) {
						DelayOutSourceLeft = XRFDC_DLY_UNIT;
					} else if (DistRegSrc & XRFDC_CLK_DISTR_MUX6_SRC_NTH) {
						DelayOutSourceRight = XRFDC_DLY_UNIT;
					}
					if (CurrentTile > PkgSrcTile) {
						ClockSettingsPtr->Delay =
							DelayOutSourceRight + ((CurrentTile - PkgSrcTile) << 1);
						if ((DistRegCurrent & XRFDC_CLK_DISTR_MUX4A_SRC_INT) ==
						    XRFDC_DISABLED) {
							ClockSettingsPtr->Delay += XRFDC_DLY_UNIT;
						}
					} else if (CurrentTile == PkgSrcTile) {
						if (ClockSettingsPtr->DistributedClock != XRFDC_DIST_OUT_NONE) {
							ClockSettingsPtr->Delay =
								DelayOutSourceLeft + DelayOutSourceRight + 2;
						}
					} else {
						ClockSettingsPtr->Delay =
							DelayOutSourceLeft + ((PkgSrcTile - CurrentTile) << 1);
						if (DistRegCurrent & XRFDC_CLK_DISTR_MUX4A_SRC_INT) {
							ClockSettingsPtr->Delay += XRFDC_DLY_UNIT;
						}
					}

					DistributionSettingsPtr->Info.Source = PkgSrcTile;
					DistributionSettingsPtr->Info.UpperBound = CurrentTile;
					DistributionSettingsPtr->Info.MaxDelay = XRFDC_MAX(
						DistributionSettingsPtr->Info.MaxDelay, (ClockSettingsPtr->Delay));
					DistributionSettingsPtr->Info.MinDelay = XRFDC_MIN(
						DistributionSettingsPtr->Info.MinDelay, (ClockSettingsPtr->Delay));
					DistributionSettingsPtr->Info.IsDelayBalanced =
						(DistributionSettingsPtr->Info.MaxDelay ==
						 DistributionSettingsPtr->Info.MinDelay) ?
							1 :
							0;
					ClockSettingsPtr->SourceType = SrcType;
					ClockSettingsPtr->SourceTile = SrcTile;
					(void)XRFdc_GetPLLConfig(InstancePtr, Type, Tile, &PLLSettings);
					ClockSettingsPtr->PLLEnable = PLLSettings.Enabled;
					ClockSettingsPtr->DivisionFactor =
						((ClockSettingsPtr->PLLEnable == XRFDC_ENABLED) ?
							 1 :
							 PLLSettings.OutputDivider);
					ClockSettingsPtr->RefClkFreq = PLLSettings.RefClkFreq;
					ClockSettingsPtr->SampleRate = PLLSettings.SampleRate * XRFDC_MILLI;
					DistributionSettingsPtr->SampleRates[Type][Tile] = ClockSettingsPtr->SampleRate;
					if (PkgSrcTile == CurrentTile) {
						DistributionSettingsPtr->DistributedClock =
							ClockSettingsPtr->DistributedClock;
						DistributionSettingsPtr->DistRefClkFreq = ClockSettingsPtr->RefClkFreq;
					}
					break;
				}
			}
		} else {
			metal_log(METAL_LOG_WARNING,
				  "\n Distribution system misconfiguration detected for %s %u in %s\r\n",
				  (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile, __func__);
		}
	}
	for (Distribution = Distribution + 1U; Distribution < XRFDC_MAX_DISTRS; Distribution++) {
		DistributionSystemPtr->Distributions[Distribution].SourceTileId = XRFDC_CLK_DST_INVALID;
	}
	Status = XRFDC_SUCCESS;
RETURN_PATH:
	return Status;
}
/*****************************************************************************/
/**
*
* This function is used to get the clock distribution
*
* @param        InstancePtr is a pointer to the XRfdc instance.
* @param        DistributionSettingsPtr pointer to get the distribution settings
*
* @return
*           - XRFDC_SUCCESS if successful.
*           - XRFDC_FAILURE if no valid distribution found.
*
******************************************************************************/
This function is used to get the clock distribution
This function is used to get the clock distribution
u32 XRFdc_GetClkDistribution(XRFdc *InstancePtr, XRFdc_Distribution_System_Settings *DistributionSystemPtr)
{
	u32 Status;
	u32 ClockDetReg;
	u32 DistRegCurrent;
	u32 DistRegSrc;
	s8 CurrentTile;
	u8 DelayOutSourceLeft;
	u8 DelayOutSourceRight;
	XRFdc_Tile_Clock_Settings *ClockSettingsPtr;
	u32 Type;
	u32 SrcType;
	u32 Tile;
	u32 SrcTile;
	u8 PkgSrcTile;
	u8 Distribution;
	u8 i;
	u8 PrevSrc;
	u8 FirstTile;
	u8 TileLayout;
	XRFdc_Distribution_Settings *DistributionSettingsPtr;
	XRFdc_PLL_Settings PLLSettings;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(DistributionSystemPtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);
	if (InstancePtr->RFdc_Config.IPType < XRFDC_GEN3) {
		Status = XRFDC_FAILURE;
		metal_log(METAL_LOG_ERROR, "\n Requested fuctionality not available for this IP in %s\r\n", __func__);
		goto RETURN_PATH;
	}
	memset(DistributionSystemPtr, 0, sizeof(XRFdc_Distribution_System_Settings));
	TileLayout = XRFdc_GetTileLayout(InstancePtr);
	FirstTile = (TileLayout == XRFDC_3ADC_2DAC_TILES) ? XRFDC_CLK_DST_TILE_228 : XRFDC_CLK_DST_TILE_231;
	PrevSrc = XRFDC_CLK_DST_INVALID;
	for (CurrentTile = FirstTile, Distribution = 0; CurrentTile <= XRFDC_CLK_DST_TILE_224; CurrentTile++) {
		XRFdc_DistTile2TypeTile(InstancePtr, CurrentTile, &Type, &Tile);
		Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile);
		if (Status != XRFDC_SUCCESS) {
			continue;
		}
		DelayOutSourceLeft = 0;
		DelayOutSourceRight = 0;
		ClockDetReg = XRFdc_RDReg(InstancePtr, XRFDC_CTRL_STS_BASE(Type, Tile), XRFDC_CLOCK_DETECT_OFFSET,
					  XRFDC_CLOCK_DETECT_SRC_MASK);
		if (ClockDetReg != XRFDC_DISABLED) {
			for (i = 0; i <= XRFDC_CLK_DST_TILE_224 - FirstTile; i++) {
				if ((ClockDetReg >> (i << 1)) == XRFDC_ENABLED) {
					PkgSrcTile = XRFDC_CLK_DST_TILE_224 - i;
					if (PrevSrc != PkgSrcTile) {
						if (PrevSrc != XRFDC_CLK_DST_INVALID) {
							Distribution++;
						}
						DistributionSettingsPtr =
							&(DistributionSystemPtr->Distributions[Distribution]);
						XRFdc_DistTile2TypeTile(InstancePtr, PkgSrcTile, &SrcType, &SrcTile);
						DistributionSettingsPtr->Info.LowerBound = CurrentTile;
						DistributionSettingsPtr->SourceTileId = SrcTile;
						DistributionSettingsPtr->SourceType = SrcType;
						DistributionSettingsPtr->Info.MaxDelay = 0U;
						DistributionSettingsPtr->Info.MinDelay = 0xFFU;
						DistributionSettingsPtr->EdgeTileIds[0] = Tile;
						DistributionSettingsPtr->EdgeTypes[0] = Type;
						DistRegSrc = XRFdc_ReadReg16(InstancePtr,
									     XRFDC_DRP_BASE(SrcType, SrcTile) +
										     XRFDC_HSCOM_ADDR,
									     XRFDC_HSCOM_CLK_DSTR_OFFSET);
					}
					ClockSettingsPtr = &(DistributionSettingsPtr->Info.ClkSettings[Type][Tile]);
					DistributionSettingsPtr->EdgeTileIds[1] = Tile;
					DistributionSettingsPtr->EdgeTypes[1] = Type;
					PrevSrc = PkgSrcTile;
					DistRegCurrent = XRFdc_ReadReg16(InstancePtr,
									 XRFDC_DRP_BASE(Type, Tile) + XRFDC_HSCOM_ADDR,
									 XRFDC_HSCOM_CLK_DSTR_OFFSET);
					if (((DistRegCurrent & XRFDC_DIST_CTRL_DIST_SRC_LOCAL) ==
					     XRFDC_DIST_CTRL_DIST_SRC_LOCAL) &&
					    (PkgSrcTile == CurrentTile)) {
						ClockSettingsPtr->DistributedClock = XRFDC_DIST_OUT_RX;
					} else if ((DistRegCurrent & XRFDC_DIST_CTRL_DIST_SRC_PLL) ==
						   XRFDC_DIST_CTRL_DIST_SRC_PLL) {
						ClockSettingsPtr->DistributedClock = XRFDC_DIST_OUT_OUTDIV;
					} else {
						ClockSettingsPtr->DistributedClock = XRFDC_DIST_OUT_NONE;
					}
					if (DistRegSrc & XRFDC_CLK_DISTR_MUX7_SRC_STH) {
						DelayOutSourceLeft = XRFDC_DLY_UNIT;
					} else if (DistRegSrc & XRFDC_CLK_DISTR_MUX6_SRC_NTH) {
						DelayOutSourceRight = XRFDC_DLY_UNIT;
					}
					if (CurrentTile > PkgSrcTile) {
						ClockSettingsPtr->Delay =
							DelayOutSourceRight + ((CurrentTile - PkgSrcTile) << 1);
						if ((DistRegCurrent & XRFDC_CLK_DISTR_MUX4A_SRC_INT) ==
						    XRFDC_DISABLED) {
							ClockSettingsPtr->Delay += XRFDC_DLY_UNIT;
						}
					} else if (CurrentTile == PkgSrcTile) {
						if (ClockSettingsPtr->DistributedClock != XRFDC_DIST_OUT_NONE) {
							ClockSettingsPtr->Delay =
								DelayOutSourceLeft + DelayOutSourceRight + 2;
						}
					} else {
						ClockSettingsPtr->Delay =
							DelayOutSourceLeft + ((PkgSrcTile - CurrentTile) << 1);
						if (DistRegCurrent & XRFDC_CLK_DISTR_MUX4A_SRC_INT) {
							ClockSettingsPtr->Delay += XRFDC_DLY_UNIT;
						}
					}
					DistributionSettingsPtr->Info.Source = PkgSrcTile;
					DistributionSettingsPtr->Info.UpperBound = CurrentTile;
					DistributionSettingsPtr->Info.MaxDelay = XRFDC_MAX(
						DistributionSettingsPtr->Info.MaxDelay, (ClockSettingsPtr->Delay));
					DistributionSettingsPtr->Info.MinDelay = XRFDC_MIN(
						DistributionSettingsPtr->Info.MinDelay, (ClockSettingsPtr->Delay));
					DistributionSettingsPtr->Info.IsDelayBalanced =
						(DistributionSettingsPtr->Info.MaxDelay ==
						 DistributionSettingsPtr->Info.MinDelay) ?
							1 :
							0;
					ClockSettingsPtr->SourceType = SrcType;
					ClockSettingsPtr->SourceTile = SrcTile;
					(void)XRFdc_GetPLLConfig(InstancePtr, Type, Tile, &PLLSettings);
					ClockSettingsPtr->PLLEnable = PLLSettings.Enabled;
					ClockSettingsPtr->DivisionFactor =
						((ClockSettingsPtr->PLLEnable == XRFDC_ENABLED) ?
							 1 :
							 PLLSettings.OutputDivider);
					ClockSettingsPtr->RefClkFreq = PLLSettings.RefClkFreq;
					ClockSettingsPtr->SampleRate = PLLSettings.SampleRate * XRFDC_MILLI;
					DistributionSettingsPtr->SampleRates[Type][Tile] = ClockSettingsPtr->SampleRate;
					if (PkgSrcTile == CurrentTile) {
						DistributionSettingsPtr->DistributedClock =
							ClockSettingsPtr->DistributedClock;
						DistributionSettingsPtr->DistRefClkFreq = ClockSettingsPtr->RefClkFreq;
					}
					break;
				}
			}
		} else {
			metal_log(METAL_LOG_WARNING,
				  "\n Distribution system misconfiguration detected for %s %u in %s\r\n",
				  (Type == XRFDC_ADC_TILE) ? "ADC" : "DAC", Tile, __func__);
		}
	}
	for (Distribution = Distribution + 1U; Distribution < XRFDC_MAX_DISTRS; Distribution++) {
		DistributionSystemPtr->Distributions[Distribution].SourceTileId = XRFDC_CLK_DST_INVALID;
	}
	Status = XRFDC_SUCCESS;
RETURN_PATH:
	return Status;
}
u32 XRFdc_GetClkDistribution ( XRFdc * InstancePtr , XRFdc_Distribution_System_Settings * DistributionSystemPtr ) { u32 Status ; u32 ClockDetReg ; u32 DistRegCurrent ; u32 DistRegSrc ; s8 CurrentTile ; u8 DelayOutSourceLeft ; u8 DelayOutSourceRight ; XRFdc_Tile_Clock_Settings * ClockSettingsPtr ; u32 Type ; u32 SrcType ; u32 Tile ; u32 SrcTile ; u8 PkgSrcTile ; u8 Distribution ; u8 i ; u8 PrevSrc ; u8 FirstTile ; u8 TileLayout ; XRFdc_Distribution_Settings * DistributionSettingsPtr ; XRFdc_PLL_Settings PLLSettings ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( DistributionSystemPtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XRFDC_COMPONENT_IS_READY ) ; if ( InstancePtr -> RFdc_Config . IPType < XRFDC_GEN3 ) { Status = XRFDC_FAILURE ; metal_log ( METAL_LOG_ERROR , " \n \r \n " , __func__ ) ; goto RETURN_PATH ; } memset ( DistributionSystemPtr , 0 , sizeof ( XRFdc_Distribution_System_Settings ) ) ; TileLayout = XRFdc_GetTileLayout ( InstancePtr ) ; FirstTile = ( TileLayout == XRFDC_3ADC_2DAC_TILES ) ? XRFDC_CLK_DST_TILE_228 : XRFDC_CLK_DST_TILE_231 ; PrevSrc = XRFDC_CLK_DST_INVALID ; for ( CurrentTile = FirstTile , Distribution = 0 ; CurrentTile <= XRFDC_CLK_DST_TILE_224 ; CurrentTile ++ ) { XRFdc_DistTile2TypeTile ( InstancePtr , CurrentTile , & Type , & Tile ) ; Status = XRFdc_CheckTileEnabled ( InstancePtr , Type , Tile ) ; if ( Status != XRFDC_SUCCESS ) { continue ; } DelayOutSourceLeft = 0 ; DelayOutSourceRight = 0 ; ClockDetReg = XRFdc_RDReg ( InstancePtr , XRFDC_CTRL_STS_BASE ( Type , Tile ) , XRFDC_CLOCK_DETECT_OFFSET , XRFDC_CLOCK_DETECT_SRC_MASK ) ; if ( ClockDetReg != XRFDC_DISABLED ) { for ( i = 0 ; i <= XRFDC_CLK_DST_TILE_224 - FirstTile ; i ++ ) { if ( ( ClockDetReg >> ( i << 1 ) ) == XRFDC_ENABLED ) { PkgSrcTile = XRFDC_CLK_DST_TILE_224 - i ; if ( PrevSrc != PkgSrcTile ) { if ( PrevSrc != XRFDC_CLK_DST_INVALID ) { Distribution ++ ; } DistributionSettingsPtr = & ( DistributionSystemPtr -> Distributions [ Distribution ] ) ; XRFdc_DistTile2TypeTile ( InstancePtr , PkgSrcTile , & SrcType , & SrcTile ) ; DistributionSettingsPtr -> Info . LowerBound = CurrentTile ; DistributionSettingsPtr -> SourceTileId = SrcTile ; DistributionSettingsPtr -> SourceType = SrcType ; DistributionSettingsPtr -> Info . MaxDelay = 0U ; DistributionSettingsPtr -> Info . MinDelay = 0xFFU ; DistributionSettingsPtr -> EdgeTileIds [ 0 ] = Tile ; DistributionSettingsPtr -> EdgeTypes [ 0 ] = Type ; DistRegSrc = XRFdc_ReadReg16 ( InstancePtr , XRFDC_DRP_BASE ( SrcType , SrcTile ) + XRFDC_HSCOM_ADDR , XRFDC_HSCOM_CLK_DSTR_OFFSET ) ; } ClockSettingsPtr = & ( DistributionSettingsPtr -> Info . ClkSettings [ Type ] [ Tile ] ) ; DistributionSettingsPtr -> EdgeTileIds [ 1 ] = Tile ; DistributionSettingsPtr -> EdgeTypes [ 1 ] = Type ; PrevSrc = PkgSrcTile ; DistRegCurrent = XRFdc_ReadReg16 ( InstancePtr , XRFDC_DRP_BASE ( Type , Tile ) + XRFDC_HSCOM_ADDR , XRFDC_HSCOM_CLK_DSTR_OFFSET ) ; if ( ( ( DistRegCurrent & XRFDC_DIST_CTRL_DIST_SRC_LOCAL ) == XRFDC_DIST_CTRL_DIST_SRC_LOCAL ) && ( PkgSrcTile == CurrentTile ) ) { ClockSettingsPtr -> DistributedClock = XRFDC_DIST_OUT_RX ; } else if ( ( DistRegCurrent & XRFDC_DIST_CTRL_DIST_SRC_PLL ) == XRFDC_DIST_CTRL_DIST_SRC_PLL ) { ClockSettingsPtr -> DistributedClock = XRFDC_DIST_OUT_OUTDIV ; } else { ClockSettingsPtr -> DistributedClock = XRFDC_DIST_OUT_NONE ; } if ( DistRegSrc & XRFDC_CLK_DISTR_MUX7_SRC_STH ) { DelayOutSourceLeft = XRFDC_DLY_UNIT ; } else if ( DistRegSrc & XRFDC_CLK_DISTR_MUX6_SRC_NTH ) { DelayOutSourceRight = XRFDC_DLY_UNIT ; } if ( CurrentTile > PkgSrcTile ) { ClockSettingsPtr -> Delay = DelayOutSourceRight + ( ( CurrentTile - PkgSrcTile ) << 1 ) ; if ( ( DistRegCurrent & XRFDC_CLK_DISTR_MUX4A_SRC_INT ) == XRFDC_DISABLED ) { ClockSettingsPtr -> Delay += XRFDC_DLY_UNIT ; } } else if ( CurrentTile == PkgSrcTile ) { if ( ClockSettingsPtr -> DistributedClock != XRFDC_DIST_OUT_NONE ) { ClockSettingsPtr -> Delay = DelayOutSourceLeft + DelayOutSourceRight + 2 ; } } else { ClockSettingsPtr -> Delay = DelayOutSourceLeft + ( ( PkgSrcTile - CurrentTile ) << 1 ) ; if ( DistRegCurrent & XRFDC_CLK_DISTR_MUX4A_SRC_INT ) { ClockSettingsPtr -> Delay += XRFDC_DLY_UNIT ; } } DistributionSettingsPtr -> Info . Source = PkgSrcTile ; DistributionSettingsPtr -> Info . UpperBound = CurrentTile ; DistributionSettingsPtr -> Info . MaxDelay = XRFDC_MAX ( DistributionSettingsPtr -> Info . MaxDelay , ( ClockSettingsPtr -> Delay ) ) ; DistributionSettingsPtr -> Info . MinDelay = XRFDC_MIN ( DistributionSettingsPtr -> Info . MinDelay , ( ClockSettingsPtr -> Delay ) ) ; DistributionSettingsPtr -> Info . IsDelayBalanced = ( DistributionSettingsPtr -> Info . MaxDelay == DistributionSettingsPtr -> Info . MinDelay ) ? 1 : 0 ; ClockSettingsPtr -> SourceType = SrcType ; ClockSettingsPtr -> SourceTile = SrcTile ; ( void ) XRFdc_GetPLLConfig ( InstancePtr , Type , Tile , & PLLSettings ) ; ClockSettingsPtr -> PLLEnable = PLLSettings . Enabled ; ClockSettingsPtr -> DivisionFactor = ( ( ClockSettingsPtr -> PLLEnable == XRFDC_ENABLED ) ? 1 : PLLSettings . OutputDivider ) ; ClockSettingsPtr -> RefClkFreq = PLLSettings . RefClkFreq ; ClockSettingsPtr -> SampleRate = PLLSettings . SampleRate * XRFDC_MILLI ; DistributionSettingsPtr -> SampleRates [ Type ] [ Tile ] = ClockSettingsPtr -> SampleRate ; if ( PkgSrcTile == CurrentTile ) { DistributionSettingsPtr -> DistributedClock = ClockSettingsPtr -> DistributedClock ; DistributionSettingsPtr -> DistRefClkFreq = ClockSettingsPtr -> RefClkFreq ; } break ; } } } else { metal_log ( METAL_LOG_WARNING , " \n \r \n " , ( Type == XRFDC_ADC_TILE ) ? " " : " " , Tile , __func__ ) ; } } for ( Distribution = Distribution + 1U ; Distribution < XRFDC_MAX_DISTRS ; Distribution ++ ) { DistributionSystemPtr -> Distributions [ Distribution ] . SourceTileId = XRFDC_CLK_DST_INVALID ; } Status = XRFDC_SUCCESS ; RETURN_PATH : return Status ; }
This function is used to get the clock distribution
This function is used to get the clock distribution