XilinxProcessorIPLib/drivers/axidma/src/xaxidma.c
int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config)
{
	UINTPTR BaseAddr;
	int TimeOut;
	int Index;
	u32 MaxTransferLen;

	InstancePtr->Initialized = 0;

	if(!Config) {
		return XST_INVALID_PARAM;
	}

	BaseAddr = Config->BaseAddr;

	/* Setup the instance */
	memset(InstancePtr, 0, sizeof(XAxiDma));
	InstancePtr->RegBase = BaseAddr;

	/* Get hardware setting information from the configuration structure
	 */
	InstancePtr->HasMm2S = Config->HasMm2S;
	InstancePtr->HasS2Mm = Config->HasS2Mm;

	InstancePtr->HasSg = Config->HasSg;

	InstancePtr->MicroDmaMode = Config->MicroDmaMode;
	InstancePtr->AddrWidth = Config->AddrWidth;

	/* Get the number of channels */
	InstancePtr->TxNumChannels = Config->Mm2sNumChannels;
	InstancePtr->RxNumChannels = Config->S2MmNumChannels;

	/* This condition is for IP version < 6.00a */
	if (!InstancePtr->TxNumChannels)
		InstancePtr->TxNumChannels = 1;
	if (!InstancePtr->RxNumChannels)
		InstancePtr->RxNumChannels = 1;

	if ((InstancePtr->RxNumChannels > 1) ||
		(InstancePtr->TxNumChannels > 1)) {
		MaxTransferLen =
			XAXIDMA_MCHAN_MAX_TRANSFER_LEN;
	}
	else {
		MaxTransferLen = (1U << Config->SgLengthWidth) - 1;
	}

	/* Initialize the ring structures */
	InstancePtr->TxBdRing.RunState = AXIDMA_CHANNEL_HALTED;
	InstancePtr->TxBdRing.IsRxChannel = 0;
	if (!InstancePtr->MicroDmaMode) {
		InstancePtr->TxBdRing.MaxTransferLen = MaxTransferLen;
	}
	else {
		/* In MicroDMA mode, Maximum length that can be transferred
		 * is '(Memory Data Width / 8) * Burst Size'
		 */
		InstancePtr->TxBdRing.MaxTransferLen =
				((Config->Mm2SDataWidth / 8) *
				 Config->Mm2SBurstSize);
	}
	InstancePtr->TxBdRing.RingIndex = 0;

	for (Index = 0; Index < InstancePtr->RxNumChannels; Index++) {
		InstancePtr->RxBdRing[Index].RunState
						 = AXIDMA_CHANNEL_HALTED;
		InstancePtr->RxBdRing[Index].IsRxChannel = 1;
		InstancePtr->RxBdRing[Index].RingIndex = Index;
	}

	if (InstancePtr->HasMm2S) {
		InstancePtr->TxBdRing.ChanBase =
				BaseAddr + XAXIDMA_TX_OFFSET;
		InstancePtr->TxBdRing.HasStsCntrlStrm =
					Config->HasStsCntrlStrm;
		if (InstancePtr->AddrWidth > 32)
			InstancePtr->TxBdRing.Addr_ext = 1;
		else
			InstancePtr->TxBdRing.Addr_ext = 0;

		InstancePtr->TxBdRing.HasDRE = Config->HasMm2SDRE;
		InstancePtr->TxBdRing.DataWidth =
			((unsigned int)Config->Mm2SDataWidth >> 3);
	}

	if (InstancePtr->HasS2Mm) {
		for (Index = 0;
			Index < InstancePtr->RxNumChannels; Index++) {
			InstancePtr->RxBdRing[Index].ChanBase =
					BaseAddr + XAXIDMA_RX_OFFSET;
			InstancePtr->RxBdRing[Index].HasStsCntrlStrm =
					Config->HasStsCntrlStrm;
			InstancePtr->RxBdRing[Index].HasDRE =
					Config->HasS2MmDRE;
			InstancePtr->RxBdRing[Index].DataWidth =
			((unsigned int)Config->S2MmDataWidth >> 3);

			if (!InstancePtr->MicroDmaMode) {
				InstancePtr->RxBdRing[Index].MaxTransferLen =
							MaxTransferLen;
			}
			else {
			/* In MicroDMA mode, Maximum length that can be transferred
			 * is '(Memory Data Width / 8) * Burst Size'
			 */
				InstancePtr->RxBdRing[Index].MaxTransferLen =
						((Config->S2MmDataWidth / 8) *
						Config->S2MmBurstSize);
			}
			if (InstancePtr->AddrWidth > 32)
				InstancePtr->RxBdRing[Index].Addr_ext = 1;
			else
				InstancePtr->RxBdRing[Index].Addr_ext = 0;
		}
	}

	/* Reset the engine so the hardware starts from a known state
	 */
	XAxiDma_Reset(InstancePtr);

	/* At the initialization time, hardware should finish reset quickly
	 */
	TimeOut = XAXIDMA_RESET_TIMEOUT;

	while (TimeOut) {

		if(XAxiDma_ResetIsDone(InstancePtr)) {
			break;
		}

		TimeOut -= 1;

	}

	if (!TimeOut) {
		xdbg_printf(XDBG_DEBUG_ERROR, "Failed reset in"
							"initialize\r\n");

		/* Need system hard reset to recover
		 */
		InstancePtr->Initialized = 0;
		return XST_DMA_ERROR;
	}

	/* Initialization is successful
	 */
	InstancePtr->Initialized = 1;

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
 * This function initializes a DMA engine.  This function must be called
 * prior to using a DMA engine. Initializing a engine includes setting
 * up the register base address, setting up the instance data, and ensuring the
 * hardware is in a quiescent state.
 *
 * @param	InstancePtr is a pointer to the DMA engine instance to be
 *		worked on.
 * @param	Config is a pointer to an XAxiDma_Config structure. It contains
 *		the information about the hardware build, including base
 *		address,and whether status control stream (StsCntrlStrm), MM2S
 *		and S2MM are included in the build.
 *
 * @return
 * 		- XST_SUCCESS for successful initialization
 * 		- XST_INVALID_PARAM if pointer to the configuration structure
 *		is NULL
 * 		- XST_DMA_ERROR if reset operation failed at the end of
 *		initialization
 *
 * @note	We assume the hardware building tool will check and error out
 *		for a hardware build that has no transfer channels.
 *****************************************************************************/
This function initializes a DMA engine.  This function must be called
prior to using a DMA engine. Initializing a engine includes setting
up the register base address, setting up the instance data, and ensuring the
hardware is in a quiescent state.

@param       InstancePtr is a pointer to the DMA engine instance to be
worked on.
@param       Config is a pointer to an XAxiDma_Config structure. It contains
the information about the hardware build, including base
address,and whether status control stream (StsCntrlStrm), MM2S
and S2MM are included in the build.

@return
- XST_SUCCESS for successful initialization
- XST_INVALID_PARAM if pointer to the configuration structure
is NULL
- XST_DMA_ERROR if reset operation failed at the end of
initialization

@note        We assume the hardware building tool will check and error out
for a hardware build that has no transfer channels.
This function initializes a DMA engine . This function must be called prior to using a DMA engine . Initializing a engine includes setting up the register base address setting up the instance data and ensuring the hardware is in a quiescent state . @param InstancePtr is a pointer to the DMA engine instance to be worked on . @param Config is a pointer to an XAxiDma_Config structure . It contains the information about the hardware build including base address and whether status control stream ( StsCntrlStrm ) MM2S and S2MM are included in the build . @return - XST_SUCCESS for successful initialization - XST_INVALID_PARAM if pointer to the configuration structure is NULL - XST_DMA_ERROR if reset operation failed at the end of initialization @note We assume the hardware building tool will check and error out for a hardware build that has no transfer channels .
int XAxiDma_CfgInitialize(XAxiDma * InstancePtr, XAxiDma_Config *Config)
{
	UINTPTR BaseAddr;
	int TimeOut;
	int Index;
	u32 MaxTransferLen;
	InstancePtr->Initialized = 0;
	if(!Config) {
		return XST_INVALID_PARAM;
	}
	BaseAddr = Config->BaseAddr;
	memset(InstancePtr, 0, sizeof(XAxiDma));
	InstancePtr->RegBase = BaseAddr;
	InstancePtr->HasMm2S = Config->HasMm2S;
	InstancePtr->HasS2Mm = Config->HasS2Mm;
	InstancePtr->HasSg = Config->HasSg;
	InstancePtr->MicroDmaMode = Config->MicroDmaMode;
	InstancePtr->AddrWidth = Config->AddrWidth;
	InstancePtr->TxNumChannels = Config->Mm2sNumChannels;
	InstancePtr->RxNumChannels = Config->S2MmNumChannels;
	if (!InstancePtr->TxNumChannels)
		InstancePtr->TxNumChannels = 1;
	if (!InstancePtr->RxNumChannels)
		InstancePtr->RxNumChannels = 1;
	if ((InstancePtr->RxNumChannels > 1) ||
		(InstancePtr->TxNumChannels > 1)) {
		MaxTransferLen =
			XAXIDMA_MCHAN_MAX_TRANSFER_LEN;
	}
	else {
		MaxTransferLen = (1U << Config->SgLengthWidth) - 1;
	}
	InstancePtr->TxBdRing.RunState = AXIDMA_CHANNEL_HALTED;
	InstancePtr->TxBdRing.IsRxChannel = 0;
	if (!InstancePtr->MicroDmaMode) {
		InstancePtr->TxBdRing.MaxTransferLen = MaxTransferLen;
	}
	else {
		InstancePtr->TxBdRing.MaxTransferLen =
				((Config->Mm2SDataWidth / 8) *
				 Config->Mm2SBurstSize);
	}
	InstancePtr->TxBdRing.RingIndex = 0;
	for (Index = 0; Index < InstancePtr->RxNumChannels; Index++) {
		InstancePtr->RxBdRing[Index].RunState
						 = AXIDMA_CHANNEL_HALTED;
		InstancePtr->RxBdRing[Index].IsRxChannel = 1;
		InstancePtr->RxBdRing[Index].RingIndex = Index;
	}
	if (InstancePtr->HasMm2S) {
		InstancePtr->TxBdRing.ChanBase =
				BaseAddr + XAXIDMA_TX_OFFSET;
		InstancePtr->TxBdRing.HasStsCntrlStrm =
					Config->HasStsCntrlStrm;
		if (InstancePtr->AddrWidth > 32)
			InstancePtr->TxBdRing.Addr_ext = 1;
		else
			InstancePtr->TxBdRing.Addr_ext = 0;
		InstancePtr->TxBdRing.HasDRE = Config->HasMm2SDRE;
		InstancePtr->TxBdRing.DataWidth =
			((unsigned int)Config->Mm2SDataWidth >> 3);
	}
	if (InstancePtr->HasS2Mm) {
		for (Index = 0;
			Index < InstancePtr->RxNumChannels; Index++) {
			InstancePtr->RxBdRing[Index].ChanBase =
					BaseAddr + XAXIDMA_RX_OFFSET;
			InstancePtr->RxBdRing[Index].HasStsCntrlStrm =
					Config->HasStsCntrlStrm;
			InstancePtr->RxBdRing[Index].HasDRE =
					Config->HasS2MmDRE;
			InstancePtr->RxBdRing[Index].DataWidth =
			((unsigned int)Config->S2MmDataWidth >> 3);
			if (!InstancePtr->MicroDmaMode) {
				InstancePtr->RxBdRing[Index].MaxTransferLen =
							MaxTransferLen;
			}
			else {
				InstancePtr->RxBdRing[Index].MaxTransferLen =
						((Config->S2MmDataWidth / 8) *
						Config->S2MmBurstSize);
			}
			if (InstancePtr->AddrWidth > 32)
				InstancePtr->RxBdRing[Index].Addr_ext = 1;
			else
				InstancePtr->RxBdRing[Index].Addr_ext = 0;
		}
	}
	XAxiDma_Reset(InstancePtr);
	TimeOut = XAXIDMA_RESET_TIMEOUT;
	while (TimeOut) {
		if(XAxiDma_ResetIsDone(InstancePtr)) {
			break;
		}
		TimeOut -= 1;
	}
	if (!TimeOut) {
		xdbg_printf(XDBG_DEBUG_ERROR, "Failed reset in"
							"initialize\r\n");
		InstancePtr->Initialized = 0;
		return XST_DMA_ERROR;
	}
	InstancePtr->Initialized = 1;
	return XST_SUCCESS;
}
int XAxiDma_CfgInitialize ( XAxiDma * InstancePtr , XAxiDma_Config * Config ) { UINTPTR BaseAddr ; int TimeOut ; int Index ; u32 MaxTransferLen ; InstancePtr -> Initialized = 0 ; if ( ! Config ) { return XST_INVALID_PARAM ; } BaseAddr = Config -> BaseAddr ; memset ( InstancePtr , 0 , sizeof ( XAxiDma ) ) ; InstancePtr -> RegBase = BaseAddr ; InstancePtr -> HasMm2S = Config -> HasMm2S ; InstancePtr -> HasS2Mm = Config -> HasS2Mm ; InstancePtr -> HasSg = Config -> HasSg ; InstancePtr -> MicroDmaMode = Config -> MicroDmaMode ; InstancePtr -> AddrWidth = Config -> AddrWidth ; InstancePtr -> TxNumChannels = Config -> Mm2sNumChannels ; InstancePtr -> RxNumChannels = Config -> S2MmNumChannels ; if ( ! InstancePtr -> TxNumChannels ) InstancePtr -> TxNumChannels = 1 ; if ( ! InstancePtr -> RxNumChannels ) InstancePtr -> RxNumChannels = 1 ; if ( ( InstancePtr -> RxNumChannels > 1 ) || ( InstancePtr -> TxNumChannels > 1 ) ) { MaxTransferLen = XAXIDMA_MCHAN_MAX_TRANSFER_LEN ; } else { MaxTransferLen = ( 1U << Config -> SgLengthWidth ) - 1 ; } InstancePtr -> TxBdRing . RunState = AXIDMA_CHANNEL_HALTED ; InstancePtr -> TxBdRing . IsRxChannel = 0 ; if ( ! InstancePtr -> MicroDmaMode ) { InstancePtr -> TxBdRing . MaxTransferLen = MaxTransferLen ; } else { InstancePtr -> TxBdRing . MaxTransferLen = ( ( Config -> Mm2SDataWidth / 8 ) * Config -> Mm2SBurstSize ) ; } InstancePtr -> TxBdRing . RingIndex = 0 ; for ( Index = 0 ; Index < InstancePtr -> RxNumChannels ; Index ++ ) { InstancePtr -> RxBdRing [ Index ] . RunState = AXIDMA_CHANNEL_HALTED ; InstancePtr -> RxBdRing [ Index ] . IsRxChannel = 1 ; InstancePtr -> RxBdRing [ Index ] . RingIndex = Index ; } if ( InstancePtr -> HasMm2S ) { InstancePtr -> TxBdRing . ChanBase = BaseAddr + XAXIDMA_TX_OFFSET ; InstancePtr -> TxBdRing . HasStsCntrlStrm = Config -> HasStsCntrlStrm ; if ( InstancePtr -> AddrWidth > 32 ) InstancePtr -> TxBdRing . Addr_ext = 1 ; else InstancePtr -> TxBdRing . Addr_ext = 0 ; InstancePtr -> TxBdRing . HasDRE = Config -> HasMm2SDRE ; InstancePtr -> TxBdRing . DataWidth = ( ( unsigned int ) Config -> Mm2SDataWidth >> 3 ) ; } if ( InstancePtr -> HasS2Mm ) { for ( Index = 0 ; Index < InstancePtr -> RxNumChannels ; Index ++ ) { InstancePtr -> RxBdRing [ Index ] . ChanBase = BaseAddr + XAXIDMA_RX_OFFSET ; InstancePtr -> RxBdRing [ Index ] . HasStsCntrlStrm = Config -> HasStsCntrlStrm ; InstancePtr -> RxBdRing [ Index ] . HasDRE = Config -> HasS2MmDRE ; InstancePtr -> RxBdRing [ Index ] . DataWidth = ( ( unsigned int ) Config -> S2MmDataWidth >> 3 ) ; if ( ! InstancePtr -> MicroDmaMode ) { InstancePtr -> RxBdRing [ Index ] . MaxTransferLen = MaxTransferLen ; } else { InstancePtr -> RxBdRing [ Index ] . MaxTransferLen = ( ( Config -> S2MmDataWidth / 8 ) * Config -> S2MmBurstSize ) ; } if ( InstancePtr -> AddrWidth > 32 ) InstancePtr -> RxBdRing [ Index ] . Addr_ext = 1 ; else InstancePtr -> RxBdRing [ Index ] . Addr_ext = 0 ; } } XAxiDma_Reset ( InstancePtr ) ; TimeOut = XAXIDMA_RESET_TIMEOUT ; while ( TimeOut ) { if ( XAxiDma_ResetIsDone ( InstancePtr ) ) { break ; } TimeOut -= 1 ; } if ( ! TimeOut ) { xdbg_printf ( XDBG_DEBUG_ERROR , " " " \r \n " ) ; InstancePtr -> Initialized = 0 ; return XST_DMA_ERROR ; } InstancePtr -> Initialized = 1 ; return XST_SUCCESS ; }
This function initializes a DMA engine.
This function initializes a DMA engine .
/* Setup the instance */ /* Get hardware setting information from the configuration structure
	 */ /* Get the number of channels */ /* This condition is for IP version < 6.00a */ /* Initialize the ring structures */ /* In MicroDMA mode, Maximum length that can be transferred
		 * is '(Memory Data Width / 8) * Burst Size'
		 */ /* In MicroDMA mode, Maximum length that can be transferred
			 * is '(Memory Data Width / 8) * Burst Size'
			 */ /* Reset the engine so the hardware starts from a known state
	 */ /* At the initialization time, hardware should finish reset quickly
	 */ /* Need system hard reset to recover
		 */ /* Initialization is successful
	 */