src/dpdk/drivers/net/mlx5/mlx5_rxq.c
static void
rxq_sync_cq(struct mlx5_rxq_data *rxq)
{
	const uint16_t cqe_n = 1 << rxq->cqe_n;
	const uint16_t cqe_mask = cqe_n - 1;
	volatile struct mlx5_cqe *cqe;
	int ret, i;

	i = cqe_n;
	do {
		cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask];
		ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
		if (ret == MLX5_CQE_STATUS_HW_OWN)
			break;
		if (ret == MLX5_CQE_STATUS_ERR) {
			rxq->cq_ci++;
			continue;
		}
		MLX5_ASSERT(ret == MLX5_CQE_STATUS_SW_OWN);
		if (MLX5_CQE_FORMAT(cqe->op_own) != MLX5_COMPRESSED) {
			rxq->cq_ci++;
			continue;
		}
		/* Compute the next non compressed CQE. */
		rxq->cq_ci += rte_be_to_cpu_32(cqe->byte_cnt);

	} while (--i);
	/* Move all CQEs to HW ownership, including possible MiniCQEs. */
	for (i = 0; i < cqe_n; i++) {
		cqe = &(*rxq->cqes)[i];
		cqe->op_own = MLX5_CQE_INVALIDATE;
	}
	/* Resync CQE and WQE (WQ in RESET state). */
	rte_io_wmb();
	*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
	rte_io_wmb();
	*rxq->rq_db = rte_cpu_to_be_32(0);
	rte_io_wmb();
}
/* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */
Fetches and drops all SW-owned and error CQEs to synchronize CQ.
Fetches and drops all SW - owned and error CQEs to synchronize CQ .
static void
rxq_sync_cq(struct mlx5_rxq_data *rxq)
{
	const uint16_t cqe_n = 1 << rxq->cqe_n;
	const uint16_t cqe_mask = cqe_n - 1;
	volatile struct mlx5_cqe *cqe;
	int ret, i;
	i = cqe_n;
	do {
		cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask];
		ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
		if (ret == MLX5_CQE_STATUS_HW_OWN)
			break;
		if (ret == MLX5_CQE_STATUS_ERR) {
			rxq->cq_ci++;
			continue;
		}
		MLX5_ASSERT(ret == MLX5_CQE_STATUS_SW_OWN);
		if (MLX5_CQE_FORMAT(cqe->op_own) != MLX5_COMPRESSED) {
			rxq->cq_ci++;
			continue;
		}
		rxq->cq_ci += rte_be_to_cpu_32(cqe->byte_cnt);
	} while (--i);
	for (i = 0; i < cqe_n; i++) {
		cqe = &(*rxq->cqes)[i];
		cqe->op_own = MLX5_CQE_INVALIDATE;
	}
	rte_io_wmb();
	*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
	rte_io_wmb();
	*rxq->rq_db = rte_cpu_to_be_32(0);
	rte_io_wmb();
}
static void rxq_sync_cq ( struct mlx5_rxq_data * rxq ) { const uint16_t cqe_n = 1 << rxq -> cqe_n ; const uint16_t cqe_mask = cqe_n - 1 ; volatile struct mlx5_cqe * cqe ; int ret , i ; i = cqe_n ; do { cqe = & ( * rxq -> cqes ) [ rxq -> cq_ci & cqe_mask ] ; ret = check_cqe ( cqe , cqe_n , rxq -> cq_ci ) ; if ( ret == MLX5_CQE_STATUS_HW_OWN ) break ; if ( ret == MLX5_CQE_STATUS_ERR ) { rxq -> cq_ci ++ ; continue ; } MLX5_ASSERT ( ret == MLX5_CQE_STATUS_SW_OWN ) ; if ( MLX5_CQE_FORMAT ( cqe -> op_own ) != MLX5_COMPRESSED ) { rxq -> cq_ci ++ ; continue ; } rxq -> cq_ci += rte_be_to_cpu_32 ( cqe -> byte_cnt ) ; } while ( -- i ) ; for ( i = 0 ; i < cqe_n ; i ++ ) { cqe = & ( * rxq -> cqes ) [ i ] ; cqe -> op_own = MLX5_CQE_INVALIDATE ; } rte_io_wmb ( ) ; * rxq -> cq_db = rte_cpu_to_be_32 ( rxq -> cq_ci ) ; rte_io_wmb ( ) ; * rxq -> rq_db = rte_cpu_to_be_32 ( 0 ) ; rte_io_wmb ( ) ; }
Fetches and drops all SW-owned and error CQEs to synchronize CQ.
Fetches and drops all SW - owned and error CQEs to synchronize CQ .
/* Compute the next non compressed CQE. */ /* Move all CQEs to HW ownership, including possible MiniCQEs. */ /* Resync CQE and WQE (WQ in RESET state). */