src/system_mt7687.c
void cmnCpuClkConfigureTo192M(void)
{
    volatile uint32_t reg;
    volatile uint32_t *pTopCfgCM4CKG = (volatile uint32_t *)TOP_CFG_CM4_CKG_EN0;

    // Step1. Power on PLL1 & 2
    cmnPLL1ON_PLL2ON(TRUE);

    // Step2. CM4_RF_CLK_SW set to PLL2(960)
    reg = cmnReadRegister32(pTopCfgCM4CKG);
    reg = reg & ~(CM4_WBTAC_MCU_CK_SEL_MASK << CM4_WBTAC_MCU_CK_SEL_SHIFT);
    reg = reg | (CM4_WBTAC_MCU_CK_SEL_WIFI_PLL_960 << CM4_WBTAC_MCU_CK_SEL_SHIFT);
    cmnWriteRegister32(pTopCfgCM4CKG, reg);

    while (reg != cmnReadRegister32(pTopCfgCM4CKG));

    // Step3. set divider to 1+8/2=5, ->  960/5=192Mhz
    reg = cmnReadRegister32(pTopCfgCM4CKG);
    reg = reg & ~(CM4_MCU_DIV_SEL_MASK << CM4_MCU_DIV_SEL_SHIFT);
    reg = reg | (8 << CM4_MCU_DIV_SEL_SHIFT);
    cmnWriteRegister32(pTopCfgCM4CKG, reg);

    // Step4. CM4_HCLK_SW set to PLL_CK
    reg = cmnReadRegister32(pTopCfgCM4CKG);
    reg = reg & ~(CM4_HCLK_SEL_MASK << CM4_HCLK_SEL_SHIFT);
    reg = reg | (CM4_HCLK_SEL_PLL << CM4_HCLK_SEL_SHIFT);
    cmnWriteRegister32(pTopCfgCM4CKG, reg);
    gCpuFrequency = MCU_FREQUENCY_192MHZ;
    SystemCoreClockUpdate();
    SysTick_Set(SystemCoreClock / 1000); /* 1ms trigger */
    return;
}
/**
  * @brief  This function is to config CPU frequency to 192Mhz.
  * @param  None
  * @retval None
  */
@brief  This function is to config CPU frequency to 192Mhz.
@param  None
@retval None
@brief This function is to config CPU frequency to 192Mhz . @param None @retval None
void cmnCpuClkConfigureTo192M(void)
{
    volatile uint32_t reg;
    volatile uint32_t *pTopCfgCM4CKG = (volatile uint32_t *)TOP_CFG_CM4_CKG_EN0;
    cmnPLL1ON_PLL2ON(TRUE);
    reg = cmnReadRegister32(pTopCfgCM4CKG);
    reg = reg & ~(CM4_WBTAC_MCU_CK_SEL_MASK << CM4_WBTAC_MCU_CK_SEL_SHIFT);
    reg = reg | (CM4_WBTAC_MCU_CK_SEL_WIFI_PLL_960 << CM4_WBTAC_MCU_CK_SEL_SHIFT);
    cmnWriteRegister32(pTopCfgCM4CKG, reg);
    while (reg != cmnReadRegister32(pTopCfgCM4CKG));
    reg = cmnReadRegister32(pTopCfgCM4CKG);
    reg = reg & ~(CM4_MCU_DIV_SEL_MASK << CM4_MCU_DIV_SEL_SHIFT);
    reg = reg | (8 << CM4_MCU_DIV_SEL_SHIFT);
    cmnWriteRegister32(pTopCfgCM4CKG, reg);
    reg = cmnReadRegister32(pTopCfgCM4CKG);
    reg = reg & ~(CM4_HCLK_SEL_MASK << CM4_HCLK_SEL_SHIFT);
    reg = reg | (CM4_HCLK_SEL_PLL << CM4_HCLK_SEL_SHIFT);
    cmnWriteRegister32(pTopCfgCM4CKG, reg);
    gCpuFrequency = MCU_FREQUENCY_192MHZ;
    SystemCoreClockUpdate();
    SysTick_Set(SystemCoreClock / 1000); 
    return;
}
void cmnCpuClkConfigureTo192M ( void ) { volatile uint32_t reg ; volatile uint32_t * pTopCfgCM4CKG = ( volatile uint32_t * ) TOP_CFG_CM4_CKG_EN0 ; cmnPLL1ON_PLL2ON ( TRUE ) ; reg = cmnReadRegister32 ( pTopCfgCM4CKG ) ; reg = reg & ~ ( CM4_WBTAC_MCU_CK_SEL_MASK << CM4_WBTAC_MCU_CK_SEL_SHIFT ) ; reg = reg | ( CM4_WBTAC_MCU_CK_SEL_WIFI_PLL_960 << CM4_WBTAC_MCU_CK_SEL_SHIFT ) ; cmnWriteRegister32 ( pTopCfgCM4CKG , reg ) ; while ( reg != cmnReadRegister32 ( pTopCfgCM4CKG ) ) ; reg = cmnReadRegister32 ( pTopCfgCM4CKG ) ; reg = reg & ~ ( CM4_MCU_DIV_SEL_MASK << CM4_MCU_DIV_SEL_SHIFT ) ; reg = reg | ( 8 << CM4_MCU_DIV_SEL_SHIFT ) ; cmnWriteRegister32 ( pTopCfgCM4CKG , reg ) ; reg = cmnReadRegister32 ( pTopCfgCM4CKG ) ; reg = reg & ~ ( CM4_HCLK_SEL_MASK << CM4_HCLK_SEL_SHIFT ) ; reg = reg | ( CM4_HCLK_SEL_PLL << CM4_HCLK_SEL_SHIFT ) ; cmnWriteRegister32 ( pTopCfgCM4CKG , reg ) ; gCpuFrequency = MCU_FREQUENCY_192MHZ ; SystemCoreClockUpdate ( ) ; SysTick_Set ( SystemCoreClock / 1000 ) ; return ; }
@brief  This function is to config CPU frequency to 192Mhz.
@brief This function is to config CPU frequency to 192Mhz .
// Step1. Power on PLL1 & 2 // Step2. CM4_RF_CLK_SW set to PLL2(960) // Step3. set divider to 1+8/2=5, ->  960/5=192Mhz // Step4. CM4_HCLK_SW set to PLL_CK /* 1ms trigger */