XilinxProcessorIPLib/drivers/vphy/src/xvphy_gtpe2.c
u32 XVphy_Gtpe2ClkCmnReconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId CmnId)
{
	u16 DrpVal;
	u16 WriteVal;
    u32 Status = XST_SUCCESS;

	/* Obtain current DRP register value for PLL dividers. */
	Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x04 : 0x2B, &DrpVal);
	/* Mask out clock divider bits. */
	DrpVal &= ~(0x1FFF);
	/* Set CPLL_FBDIV. */
	WriteVal = (XVphy_NToDrpEncoding(InstancePtr, QuadId, CmnId, 2) & 0x3F);
	DrpVal |= WriteVal;
	/* Set CPLL_FBDIV_45. */
	WriteVal = (XVphy_NToDrpEncoding(InstancePtr, QuadId, CmnId, 1) & 0x1);
	DrpVal |= (WriteVal << 7);
	/* Set CPLL_REFCLKDIV. */
	WriteVal = (XVphy_MToDrpEncoding(InstancePtr, QuadId, CmnId) & 0x1F);
	DrpVal |= (WriteVal << 9);
	/* Write new DRP register value for PLL dividers. */
	Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x04 : 0x2B, DrpVal);

	return Status;
}
/*****************************************************************************/
/**
* This function will configure the common channel clock settings.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	CmnId is the common channel ID to operate on.
*
* @return
*		- XST_SUCCESS if the configuration was successful.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function will configure the common channel clock settings.
This function will configure the common channel clock settings .
u32 XVphy_Gtpe2ClkCmnReconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId CmnId)
{
	u16 DrpVal;
	u16 WriteVal;
    u32 Status = XST_SUCCESS;
	Status |= XVphy_DrpRd(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x04 : 0x2B, &DrpVal);
	DrpVal &= ~(0x1FFF);
	WriteVal = (XVphy_NToDrpEncoding(InstancePtr, QuadId, CmnId, 2) & 0x3F);
	DrpVal |= WriteVal;
	WriteVal = (XVphy_NToDrpEncoding(InstancePtr, QuadId, CmnId, 1) & 0x1);
	DrpVal |= (WriteVal << 7);
	WriteVal = (XVphy_MToDrpEncoding(InstancePtr, QuadId, CmnId) & 0x1F);
	DrpVal |= (WriteVal << 9);
	Status |= XVphy_DrpWr(InstancePtr, QuadId, XVPHY_CHANNEL_ID_CMN,
			(CmnId == XVPHY_CHANNEL_ID_CMN0) ? 0x04 : 0x2B, DrpVal);
	return Status;
}
u32 XVphy_Gtpe2ClkCmnReconfig ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId CmnId ) { u16 DrpVal ; u16 WriteVal ; u32 Status = XST_SUCCESS ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x04 : 0x2B , & DrpVal ) ; DrpVal &= ~ ( 0x1FFF ) ; WriteVal = ( XVphy_NToDrpEncoding ( InstancePtr , QuadId , CmnId , 2 ) & 0x3F ) ; DrpVal |= WriteVal ; WriteVal = ( XVphy_NToDrpEncoding ( InstancePtr , QuadId , CmnId , 1 ) & 0x1 ) ; DrpVal |= ( WriteVal << 7 ) ; WriteVal = ( XVphy_MToDrpEncoding ( InstancePtr , QuadId , CmnId ) & 0x1F ) ; DrpVal |= ( WriteVal << 9 ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , XVPHY_CHANNEL_ID_CMN , ( CmnId == XVPHY_CHANNEL_ID_CMN0 ) ? 0x04 : 0x2B , DrpVal ) ; return Status ; }
This function will configure the common channel clock settings.
This function will configure the common channel clock settings .
/* Obtain current DRP register value for PLL dividers. */ /* Mask out clock divider bits. */ /* Set CPLL_FBDIV. */ /* Set CPLL_FBDIV_45. */ /* Set CPLL_REFCLKDIV. */ /* Write new DRP register value for PLL dividers. */