XilinxProcessorIPLib/drivers/xxvethernet/examples/xxxvethernet_example_intr_mcdma.c
int XxvEthernetSgDmaIntrSingleFrameExample(XXxvEthernet *XxvEthernetInstancePtr,
										   XMcdma *DmaInstancePtr, u8 ChanId)
{
	int Status;
	u32 TxFrameLength;
	u32 RxFrameLength;
	int PayloadSize = PAYLOAD_SIZE;
	XMcdma_ChanCtrl *Rx_Chan, *Tx_Chan;
	XMcdma_Bd *BdCurPtr, *Bd1Ptr;
	u32 BdSts, CrBits, len, i;
	UINTPTR TxBufPtr;

	/*
	 * Clear variables shared with callbacks
	 */
	FramesRx = 0;
	FramesTx = 0;
	DeviceErrors = 0;
	memset(RxFrame,0,sizeof(RxFrame));
	memset(TxFrame,0,sizeof(TxFrame));

	Rx_Chan = XMcdma_GetMcdmaRxChan(DmaInstancePtr, ChanId);
	Tx_Chan = XMcdma_GetMcdmaTxChan(DmaInstancePtr, ChanId);

	/*
	 * Calculate the frame length (not including FCS)
	 */
	TxFrameLength = XXE_HDR_SIZE + PayloadSize;

	AxiEnetMapper(ChanId);

	xil_printf("ChanId %d, MacAddr: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x \n\r", ChanId,
			MacAddr[0], MacAddr[1], MacAddr[2], MacAddr[3], MacAddr[4], MacAddr[5]);

	/*
	 * Setup packet to be transmitted
	 */
	XxvEthernetUtilFrameHdrFormatMAC(&TxFrame, MacAddr, MacAddr);
	/* If sending externally */
	/* XxvEthernetUtilFrameHdrFormatMAC(&TxFrame, MacAddr, XxvEthernetMAC); */
	XxvEthernetUtilFrameHdrFormatType(&TxFrame, PayloadSize);
	XxvEthernetUtilFrameSetPayloadData(&TxFrame, PayloadSize);

	/*
	 * Flush the TX frame before giving it to DMA TX channel to transmit.
	 */
	Xil_DCacheFlushRange((UINTPTR)&TxFrame, TxFrameLength);

	/*
	 * Clear out receive packet memory area
	 */
	XxvEthernetUtilFrameMemClear(&RxFrame);

	/*
	 * Invalidate the RX frame before giving it to DMA RX channel to
	 * receive data.
	 */
	Xil_DCacheInvalidateRange((UINTPTR)&RxFrame, TxFrameLength);

	/*
	 * Enable DMA RX interrupt.
	 *
	 * Interrupt coalescing parameters are left at their default settings
	 * which is to interrupt the processor after every frame has been
	 * processed by the DMA engine.
	 */
	XMcdma_IntrEnable(Rx_Chan, XMCDMA_IRQ_ALL_MASK);


	Status = XMcDma_ChanSubmit(Rx_Chan, (UINTPTR)&RxFrame,
				   TxFrameLength);
	if (Status != XST_SUCCESS) {
		xil_printf("ChanSubmit failed\n\r");
		return XST_FAILURE;
	}

	Status = XMcDma_ChanToHw(Rx_Chan);
	if (Status != XST_SUCCESS) {
			xil_printf("XMcDma_ChanToHw failed\n\r");
			return XST_FAILURE;
	}

	/*
	 * Enable DMA transmit interrupts
	 */
	XMcdma_IntrEnable(Tx_Chan, XMCDMA_IRQ_ALL_MASK);

	BdCurPtr = (XMcdma_Bd *)XMcdma_GetChanCurBd(Tx_Chan);
	TxBufPtr = (UINTPTR)&TxFrame;
	for (i = 0 ; i < 2 ; i++) {
		CrBits = 0;

		if (i == 0)
			len = 64;
		if (i == 1)
			len = TxFrameLength - 64;

		Status = XMcDma_ChanSubmit(Tx_Chan, TxBufPtr,
								   len);
		if (Status != XST_SUCCESS) {
			xil_printf("ChanSubmit failed\n\r");
			return XST_FAILURE;
		}
		if (i == 0) {
			CrBits |= XMCDMA_BD_CTRL_SOF_MASK;
		}
		if (i == 1) {
			CrBits |= XMCDMA_BD_CTRL_EOF_MASK;
		}

		XMcDma_BdSetCtrl(BdCurPtr, CrBits);
		XMCDMA_CACHE_FLUSH((UINTPTR)(BdCurPtr));
		TxBufPtr += 64;
		BdCurPtr = (XMcdma_Bd *)XMcdma_BdChainNextBd(Tx_Chan, BdCurPtr);
	}

	Status = XMcDma_ChanToHw(Tx_Chan);
	if (Status != XST_SUCCESS) {
		xil_printf("XMcDma_ChanToHw failed for Tx\n\r");
		return XST_FAILURE;
	}

	/*
	 * Start the device. Transmission commences now!
	 */
	if (XXxvEthernet_Start(XxvEthernetInstancePtr)) {
		return XST_FAILURE;
	}

	/*
	 * Wait for transmission to complete
	 */
	while (!FramesTx);

	/*
	 * Now that the frame has been sent, post process our TxBDs.
	 * Since we have only submitted 2 to HW, then there should be only 2 ready
	 * for post processing.
	 */
	if (XMcdma_BdChainFromHW(Tx_Chan, 2, &Bd1Ptr) == 0) {
		XxvEthernetUtilErrorTrap("TxBDs were not ready for post processing");
		return XST_FAILURE;
	}

	Status = XMcdma_BdChainFree(Tx_Chan, 2, Bd1Ptr);
	if (Status != XST_SUCCESS) {
		XxvEthernetUtilErrorTrap("Error freeing TxBDs");
	}

	/*
	 * Wait for Rx indication
	 */
	while (!FramesRx);


	/*
	 * Now that the frame has been received, post process our RxBD.
	 * Since we have only submitted 1 to HW, then there should be only 1
	 * ready for post processing.
	 */
	if (XMcdma_BdChainFromHW(Rx_Chan, 1, &Bd1Ptr) == 0) {
		XxvEthernetUtilErrorTrap("RxBD was not ready for post processing");
		return XST_FAILURE;
	}

	BdCurPtr = Bd1Ptr;
	BdSts = XMcDma_BdGetSts(BdCurPtr);
	if ((BdSts & XMCDMA_BD_STS_ALL_ERR_MASK) ||
		(!(BdSts & XMCDMA_BD_STS_COMPLETE_MASK))) {
			XxvEthernetUtilErrorTrap("Rx Error");
			return XST_FAILURE;
	}
	else {
		RxFrameLength =  XMcdma_BdRead64((BdCurPtr), XMCDMA_BD_STS_OFFSET)
							& 0x007FFFFF;
	}

	if (RxFrameLength != TxFrameLength) {
		xil_printf("RxFrameLength 0x%x, TxFrameLength 0x%x \n\r", RxFrameLength, TxFrameLength);
		XxvEthernetUtilErrorTrap("Length mismatch");
		return XST_FAILURE;
	}


	if (XxvEthernetUtilFrameVerify(&TxFrame, &RxFrame) != 0) {
		XxvEthernetUtilErrorTrap("Data mismatch");
		return XST_FAILURE;
	}

	Status = XMcdma_BdChainFree(Rx_Chan, 1, Bd1Ptr);
	if (Status != XST_SUCCESS) {
		XxvEthernetUtilErrorTrap("Error freeing TxBDs");
	}

	/*
	 * Finished this example. If everything worked correctly, all TxBDs and
	 * RxBDs should be free for allocation. Stop the device.
	 */
	XXxvEthernet_Stop(XxvEthernetInstancePtr);

	xil_printf("ChanId %d Single frame interrupt example passed \n\r", ChanId);
	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function demonstrates the usage of the Xxv Ethernet by sending and
* receiving a single frame in interrupt mode using MCDMA.
* The source packet will be described by two descriptors. It will be received
* into a buffer described by a single descriptor.
*
* @param	XxvEthernetInstancePtr is a pointer to the instance of the
*		Xxv Ethernet component.
* @param	DmaInstancePtr   is a pointer to the instance of the Dma
*		component.
*
* @return	-XST_SUCCESS to indicate success
*		-XST_FAILURE to indicate failure
*
* @note		None.
*
******************************************************************************/
This function demonstrates the usage of the Xxv Ethernet by sending and
receiving a single frame in interrupt mode using MCDMA.
The source packet will be described by two descriptors. It will be received
into a buffer described by a single descriptor.
This function demonstrates the usage of the Xxv Ethernet by sending and receiving a single frame in interrupt mode using MCDMA . The source packet will be described by two descriptors . It will be received into a buffer described by a single descriptor .
int XxvEthernetSgDmaIntrSingleFrameExample(XXxvEthernet *XxvEthernetInstancePtr,
										   XMcdma *DmaInstancePtr, u8 ChanId)
{
	int Status;
	u32 TxFrameLength;
	u32 RxFrameLength;
	int PayloadSize = PAYLOAD_SIZE;
	XMcdma_ChanCtrl *Rx_Chan, *Tx_Chan;
	XMcdma_Bd *BdCurPtr, *Bd1Ptr;
	u32 BdSts, CrBits, len, i;
	UINTPTR TxBufPtr;
	FramesRx = 0;
	FramesTx = 0;
	DeviceErrors = 0;
	memset(RxFrame,0,sizeof(RxFrame));
	memset(TxFrame,0,sizeof(TxFrame));
	Rx_Chan = XMcdma_GetMcdmaRxChan(DmaInstancePtr, ChanId);
	Tx_Chan = XMcdma_GetMcdmaTxChan(DmaInstancePtr, ChanId);
	TxFrameLength = XXE_HDR_SIZE + PayloadSize;
	AxiEnetMapper(ChanId);
	xil_printf("ChanId %d, MacAddr: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x \n\r", ChanId,
			MacAddr[0], MacAddr[1], MacAddr[2], MacAddr[3], MacAddr[4], MacAddr[5]);
	XxvEthernetUtilFrameHdrFormatMAC(&TxFrame, MacAddr, MacAddr);
	XxvEthernetUtilFrameHdrFormatType(&TxFrame, PayloadSize);
	XxvEthernetUtilFrameSetPayloadData(&TxFrame, PayloadSize);
	Xil_DCacheFlushRange((UINTPTR)&TxFrame, TxFrameLength);
	XxvEthernetUtilFrameMemClear(&RxFrame);
	Xil_DCacheInvalidateRange((UINTPTR)&RxFrame, TxFrameLength);
	XMcdma_IntrEnable(Rx_Chan, XMCDMA_IRQ_ALL_MASK);
	Status = XMcDma_ChanSubmit(Rx_Chan, (UINTPTR)&RxFrame,
				   TxFrameLength);
	if (Status != XST_SUCCESS) {
		xil_printf("ChanSubmit failed\n\r");
		return XST_FAILURE;
	}
	Status = XMcDma_ChanToHw(Rx_Chan);
	if (Status != XST_SUCCESS) {
			xil_printf("XMcDma_ChanToHw failed\n\r");
			return XST_FAILURE;
	}
	XMcdma_IntrEnable(Tx_Chan, XMCDMA_IRQ_ALL_MASK);
	BdCurPtr = (XMcdma_Bd *)XMcdma_GetChanCurBd(Tx_Chan);
	TxBufPtr = (UINTPTR)&TxFrame;
	for (i = 0 ; i < 2 ; i++) {
		CrBits = 0;
		if (i == 0)
			len = 64;
		if (i == 1)
			len = TxFrameLength - 64;
		Status = XMcDma_ChanSubmit(Tx_Chan, TxBufPtr,
								   len);
		if (Status != XST_SUCCESS) {
			xil_printf("ChanSubmit failed\n\r");
			return XST_FAILURE;
		}
		if (i == 0) {
			CrBits |= XMCDMA_BD_CTRL_SOF_MASK;
		}
		if (i == 1) {
			CrBits |= XMCDMA_BD_CTRL_EOF_MASK;
		}
		XMcDma_BdSetCtrl(BdCurPtr, CrBits);
		XMCDMA_CACHE_FLUSH((UINTPTR)(BdCurPtr));
		TxBufPtr += 64;
		BdCurPtr = (XMcdma_Bd *)XMcdma_BdChainNextBd(Tx_Chan, BdCurPtr);
	}
	Status = XMcDma_ChanToHw(Tx_Chan);
	if (Status != XST_SUCCESS) {
		xil_printf("XMcDma_ChanToHw failed for Tx\n\r");
		return XST_FAILURE;
	}
	if (XXxvEthernet_Start(XxvEthernetInstancePtr)) {
		return XST_FAILURE;
	}
	while (!FramesTx);
	if (XMcdma_BdChainFromHW(Tx_Chan, 2, &Bd1Ptr) == 0) {
		XxvEthernetUtilErrorTrap("TxBDs were not ready for post processing");
		return XST_FAILURE;
	}
	Status = XMcdma_BdChainFree(Tx_Chan, 2, Bd1Ptr);
	if (Status != XST_SUCCESS) {
		XxvEthernetUtilErrorTrap("Error freeing TxBDs");
	}
	while (!FramesRx);
	if (XMcdma_BdChainFromHW(Rx_Chan, 1, &Bd1Ptr) == 0) {
		XxvEthernetUtilErrorTrap("RxBD was not ready for post processing");
		return XST_FAILURE;
	}
	BdCurPtr = Bd1Ptr;
	BdSts = XMcDma_BdGetSts(BdCurPtr);
	if ((BdSts & XMCDMA_BD_STS_ALL_ERR_MASK) ||
		(!(BdSts & XMCDMA_BD_STS_COMPLETE_MASK))) {
			XxvEthernetUtilErrorTrap("Rx Error");
			return XST_FAILURE;
	}
	else {
		RxFrameLength =  XMcdma_BdRead64((BdCurPtr), XMCDMA_BD_STS_OFFSET)
							& 0x007FFFFF;
	}
	if (RxFrameLength != TxFrameLength) {
		xil_printf("RxFrameLength 0x%x, TxFrameLength 0x%x \n\r", RxFrameLength, TxFrameLength);
		XxvEthernetUtilErrorTrap("Length mismatch");
		return XST_FAILURE;
	}
	if (XxvEthernetUtilFrameVerify(&TxFrame, &RxFrame) != 0) {
		XxvEthernetUtilErrorTrap("Data mismatch");
		return XST_FAILURE;
	}
	Status = XMcdma_BdChainFree(Rx_Chan, 1, Bd1Ptr);
	if (Status != XST_SUCCESS) {
		XxvEthernetUtilErrorTrap("Error freeing TxBDs");
	}
	XXxvEthernet_Stop(XxvEthernetInstancePtr);
	xil_printf("ChanId %d Single frame interrupt example passed \n\r", ChanId);
	return XST_SUCCESS;
}
int XxvEthernetSgDmaIntrSingleFrameExample ( XXxvEthernet * XxvEthernetInstancePtr , XMcdma * DmaInstancePtr , u8 ChanId ) { int Status ; u32 TxFrameLength ; u32 RxFrameLength ; int PayloadSize = PAYLOAD_SIZE ; XMcdma_ChanCtrl * Rx_Chan , * Tx_Chan ; XMcdma_Bd * BdCurPtr , * Bd1Ptr ; u32 BdSts , CrBits , len , i ; UINTPTR TxBufPtr ; FramesRx = 0 ; FramesTx = 0 ; DeviceErrors = 0 ; memset ( RxFrame , 0 , sizeof ( RxFrame ) ) ; memset ( TxFrame , 0 , sizeof ( TxFrame ) ) ; Rx_Chan = XMcdma_GetMcdmaRxChan ( DmaInstancePtr , ChanId ) ; Tx_Chan = XMcdma_GetMcdmaTxChan ( DmaInstancePtr , ChanId ) ; TxFrameLength = XXE_HDR_SIZE + PayloadSize ; AxiEnetMapper ( ChanId ) ; xil_printf ( " \n \r " , ChanId , MacAddr [ 0 ] , MacAddr [ 1 ] , MacAddr [ 2 ] , MacAddr [ 3 ] , MacAddr [ 4 ] , MacAddr [ 5 ] ) ; XxvEthernetUtilFrameHdrFormatMAC ( & TxFrame , MacAddr , MacAddr ) ; XxvEthernetUtilFrameHdrFormatType ( & TxFrame , PayloadSize ) ; XxvEthernetUtilFrameSetPayloadData ( & TxFrame , PayloadSize ) ; Xil_DCacheFlushRange ( ( UINTPTR ) & TxFrame , TxFrameLength ) ; XxvEthernetUtilFrameMemClear ( & RxFrame ) ; Xil_DCacheInvalidateRange ( ( UINTPTR ) & RxFrame , TxFrameLength ) ; XMcdma_IntrEnable ( Rx_Chan , XMCDMA_IRQ_ALL_MASK ) ; Status = XMcDma_ChanSubmit ( Rx_Chan , ( UINTPTR ) & RxFrame , TxFrameLength ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } Status = XMcDma_ChanToHw ( Rx_Chan ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } XMcdma_IntrEnable ( Tx_Chan , XMCDMA_IRQ_ALL_MASK ) ; BdCurPtr = ( XMcdma_Bd * ) XMcdma_GetChanCurBd ( Tx_Chan ) ; TxBufPtr = ( UINTPTR ) & TxFrame ; for ( i = 0 ; i < 2 ; i ++ ) { CrBits = 0 ; if ( i == 0 ) len = 64 ; if ( i == 1 ) len = TxFrameLength - 64 ; Status = XMcDma_ChanSubmit ( Tx_Chan , TxBufPtr , len ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } if ( i == 0 ) { CrBits |= XMCDMA_BD_CTRL_SOF_MASK ; } if ( i == 1 ) { CrBits |= XMCDMA_BD_CTRL_EOF_MASK ; } XMcDma_BdSetCtrl ( BdCurPtr , CrBits ) ; XMCDMA_CACHE_FLUSH ( ( UINTPTR ) ( BdCurPtr ) ) ; TxBufPtr += 64 ; BdCurPtr = ( XMcdma_Bd * ) XMcdma_BdChainNextBd ( Tx_Chan , BdCurPtr ) ; } Status = XMcDma_ChanToHw ( Tx_Chan ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " \n \r " ) ; return XST_FAILURE ; } if ( XXxvEthernet_Start ( XxvEthernetInstancePtr ) ) { return XST_FAILURE ; } while ( ! FramesTx ) ; if ( XMcdma_BdChainFromHW ( Tx_Chan , 2 , & Bd1Ptr ) == 0 ) { XxvEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } Status = XMcdma_BdChainFree ( Tx_Chan , 2 , Bd1Ptr ) ; if ( Status != XST_SUCCESS ) { XxvEthernetUtilErrorTrap ( " " ) ; } while ( ! FramesRx ) ; if ( XMcdma_BdChainFromHW ( Rx_Chan , 1 , & Bd1Ptr ) == 0 ) { XxvEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } BdCurPtr = Bd1Ptr ; BdSts = XMcDma_BdGetSts ( BdCurPtr ) ; if ( ( BdSts & XMCDMA_BD_STS_ALL_ERR_MASK ) || ( ! ( BdSts & XMCDMA_BD_STS_COMPLETE_MASK ) ) ) { XxvEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } else { RxFrameLength = XMcdma_BdRead64 ( ( BdCurPtr ) , XMCDMA_BD_STS_OFFSET ) & 0x007FFFFF ; } if ( RxFrameLength != TxFrameLength ) { xil_printf ( " \n \r " , RxFrameLength , TxFrameLength ) ; XxvEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } if ( XxvEthernetUtilFrameVerify ( & TxFrame , & RxFrame ) != 0 ) { XxvEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } Status = XMcdma_BdChainFree ( Rx_Chan , 1 , Bd1Ptr ) ; if ( Status != XST_SUCCESS ) { XxvEthernetUtilErrorTrap ( " " ) ; } XXxvEthernet_Stop ( XxvEthernetInstancePtr ) ; xil_printf ( " \n \r " , ChanId ) ; return XST_SUCCESS ; }
This function demonstrates the usage of the Xxv Ethernet by sending and
receiving a single frame in interrupt mode using MCDMA.
This function demonstrates the usage of the Xxv Ethernet by sending and receiving a single frame in interrupt mode using MCDMA .
/*
	 * Clear variables shared with callbacks
	 */ /*
	 * Calculate the frame length (not including FCS)
	 */ /*
	 * Setup packet to be transmitted
	 */ /* If sending externally */ /* XxvEthernetUtilFrameHdrFormatMAC(&TxFrame, MacAddr, XxvEthernetMAC); */ /*
	 * Flush the TX frame before giving it to DMA TX channel to transmit.
	 */ /*
	 * Clear out receive packet memory area
	 */ /*
	 * Invalidate the RX frame before giving it to DMA RX channel to
	 * receive data.
	 */ /*
	 * Enable DMA RX interrupt.
	 *
	 * Interrupt coalescing parameters are left at their default settings
	 * which is to interrupt the processor after every frame has been
	 * processed by the DMA engine.
	 */ /*
	 * Enable DMA transmit interrupts
	 */ /*
	 * Start the device. Transmission commences now!
	 */ /*
	 * Wait for transmission to complete
	 */ /*
	 * Now that the frame has been sent, post process our TxBDs.
	 * Since we have only submitted 2 to HW, then there should be only 2 ready
	 * for post processing.
	 */ /*
	 * Wait for Rx indication
	 */ /*
	 * Now that the frame has been received, post process our RxBD.
	 * Since we have only submitted 1 to HW, then there should be only 1
	 * ready for post processing.
	 */ /*
	 * Finished this example. If everything worked correctly, all TxBDs and
	 * RxBDs should be free for allocation. Stop the device.
	 */