XilinxProcessorIPLib/drivers/dp12txss/examples/src/kcu/xdptxss_kcu105.c
void DpPt_TxSetMsaValuesImmediate(void *InstancePtr)
{

	/* Set the main stream attributes to the associated DisplayPort TX core
	 * registers. */
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_HTOTAL +
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
						XDP_RX_MSA_HTOTAL));

	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_VTOTAL +
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
						XDP_RX_MSA_VTOTAL));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,XDP_TX_MAIN_STREAM_POLARITY+
			StreamOffsetAddr[0],
			XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_MSA_HSPOL)|
			(XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,XDP_RX_MSA_VSPOL) <<
			XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_HSWIDTH+
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
					XDP_RX_MSA_HSWIDTH));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_VSWIDTH +
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
					XDP_RX_MSA_VSWIDTH));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_HRES +
			StreamOffsetAddr[0],
			XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_MSA_HRES));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_VRES +
			StreamOffsetAddr[0],
			XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_MSA_VHEIGHT));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_HSTART +
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
					XDP_RX_MSA_HSTART));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_VSTART +
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
					XDP_RX_MSA_VSTART));
       XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_MISC0 +
		   StreamOffsetAddr[0], ((XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
                                        XDP_RX_MSA_MISC0)) & 0xFFFFFFFE));

	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_MISC1 +
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
					XDP_RX_MSA_MISC1));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_USER_PIXEL_WIDTH +
			StreamOffsetAddr[0], pixel);
     /* Check for YUV422, BPP has to be set using component value to 2 */
     if( ( (XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_MSA_MISC0))
				 & 0x6 ) == 0x2  ) {
//           xil_printf("%s:: YUV422 \r\n", __func__);
           DpTxSsInst.DpPtr->TxInstance.MsaConfig[0].ComponentFormat = 0x1;
           Msa[0].ComponentFormat = 0x1;
     }
     else {
//           xil_printf("%s:: RGB or YUV444 \r\n", __func__);
           DpTxSsInst.DpPtr->TxInstance.MsaConfig[0].ComponentFormat = 0x0;
           Msa[0].ComponentFormat = 0x0;
     }


}
/*
 * This function is a call back to write the MSA values to Tx as they are
 * read from the Rx, instead of reading them from the Video common library
 */
This function is a call back to write the MSA values to Tx as they are
read from the Rx, instead of reading them from the Video common library
This function is a call back to write the MSA values to Tx as they are read from the Rx instead of reading them from the Video common library
void DpPt_TxSetMsaValuesImmediate(void *InstancePtr)
{
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_HTOTAL +
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
						XDP_RX_MSA_HTOTAL));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_VTOTAL +
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
						XDP_RX_MSA_VTOTAL));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,XDP_TX_MAIN_STREAM_POLARITY+
			StreamOffsetAddr[0],
			XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_MSA_HSPOL)|
			(XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,XDP_RX_MSA_VSPOL) <<
			XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_HSWIDTH+
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
					XDP_RX_MSA_HSWIDTH));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_VSWIDTH +
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
					XDP_RX_MSA_VSWIDTH));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_HRES +
			StreamOffsetAddr[0],
			XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_MSA_HRES));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_VRES +
			StreamOffsetAddr[0],
			XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_MSA_VHEIGHT));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_HSTART +
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
					XDP_RX_MSA_HSTART));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_VSTART +
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
					XDP_RX_MSA_VSTART));
       XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_MISC0 +
		   StreamOffsetAddr[0], ((XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
                                        XDP_RX_MSA_MISC0)) & 0xFFFFFFFE));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_MAIN_STREAM_MISC1 +
			StreamOffsetAddr[0], XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
					XDP_RX_MSA_MISC1));
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_USER_PIXEL_WIDTH +
			StreamOffsetAddr[0], pixel);
     if( ( (XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_MSA_MISC0))
				 & 0x6 ) == 0x2  ) {
           DpTxSsInst.DpPtr->TxInstance.MsaConfig[0].ComponentFormat = 0x1;
           Msa[0].ComponentFormat = 0x1;
     }
     else {
           DpTxSsInst.DpPtr->TxInstance.MsaConfig[0].ComponentFormat = 0x0;
           Msa[0].ComponentFormat = 0x0;
     }
}
void DpPt_TxSetMsaValuesImmediate ( void * InstancePtr ) { XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_MAIN_STREAM_HTOTAL + StreamOffsetAddr [ 0 ] , XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_HTOTAL ) ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_MAIN_STREAM_VTOTAL + StreamOffsetAddr [ 0 ] , XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_VTOTAL ) ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_MAIN_STREAM_POLARITY + StreamOffsetAddr [ 0 ] , XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_HSPOL ) | ( XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_VSPOL ) << XDP_TX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT ) ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_MAIN_STREAM_HSWIDTH + StreamOffsetAddr [ 0 ] , XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_HSWIDTH ) ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_MAIN_STREAM_VSWIDTH + StreamOffsetAddr [ 0 ] , XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_VSWIDTH ) ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_MAIN_STREAM_HRES + StreamOffsetAddr [ 0 ] , XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_HRES ) ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_MAIN_STREAM_VRES + StreamOffsetAddr [ 0 ] , XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_VHEIGHT ) ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_MAIN_STREAM_HSTART + StreamOffsetAddr [ 0 ] , XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_HSTART ) ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_MAIN_STREAM_VSTART + StreamOffsetAddr [ 0 ] , XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_VSTART ) ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_MAIN_STREAM_MISC0 + StreamOffsetAddr [ 0 ] , ( ( XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_MISC0 ) ) & 0xFFFFFFFE ) ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_MAIN_STREAM_MISC1 + StreamOffsetAddr [ 0 ] , XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_MISC1 ) ) ; XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_USER_PIXEL_WIDTH + StreamOffsetAddr [ 0 ] , pixel ) ; if ( ( ( XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MSA_MISC0 ) ) & 0x6 ) == 0x2 ) { DpTxSsInst . DpPtr -> TxInstance . MsaConfig [ 0 ] . ComponentFormat = 0x1 ; Msa [ 0 ] . ComponentFormat = 0x1 ; } else { DpTxSsInst . DpPtr -> TxInstance . MsaConfig [ 0 ] . ComponentFormat = 0x0 ; Msa [ 0 ] . ComponentFormat = 0x0 ; } }
This function is a call back to write the MSA values to Tx as they are
 read from the Rx, instead of reading them from the Video common library
This function is a call back to write the MSA values to Tx as they are read from the Rx instead of reading them from the Video common library
/* Set the main stream attributes to the associated DisplayPort TX core
	 * registers. */ /* Check for YUV422, BPP has to be set using component value to 2 */ //           xil_printf("%s:: YUV422 \r\n", __func__); //           xil_printf("%s:: RGB or YUV444 \r\n", __func__);