XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_gtye4.c
u32 XHdmiphy1_Gtye4RxChReconfig(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId)
{
    XHdmiphy1_Channel *ChPtr;
    u16 DrpVal, DrpVal2;
    u16 WriteVal;
    u8 CfgIndex;
    XHdmiphy1_ChannelId ChIdPll;
    XHdmiphy1_PllType PllType;
    u32 PllxVcoRateMHz;
    u32 PllxClkOutMHz;
    u32 PllxClkOutDiv;
    u32 Status = XST_SUCCESS;
    u64 LineRateKHz;

    ChPtr = &InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(ChId)];
    /* RXCDR_CFG(CfgIndex) */
    for (CfgIndex = 0; CfgIndex < 5; CfgIndex++) {
        DrpVal = ChPtr->PllParams.Cdr[CfgIndex];
        if (!DrpVal) {
            /* Don't modify RX_CDR configuration. */
            continue;
        }
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId,
                    XHDMIPHY1_DRP_RXCDR_CFG(CfgIndex), DrpVal);
        if (CfgIndex == 2) {
            Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId,
                        XHDMIPHY1_DRP_RXCDR_CFG_GEN3(CfgIndex), DrpVal);
        /* RXCDR_CFG2_GEN2 */
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XHDMIPHY1_DRP_RXCDR_CFG2_GEN2, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_0011_RXCDR_CGF2_GEN2_MASK);
        DrpVal |= ChPtr->PllParams.Cdr[CfgIndex] & XDRP_GTYE4_CHN_REG_0011_RXCDR_CGF2_GEN2_MASK;
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XHDMIPHY1_DRP_RXCDR_CFG2_GEN2, DrpVal);
        }
    }

    if (XHdmiphy1_IsHDMI(InstancePtr, XHDMIPHY1_DIR_RX)) {
	/* Determine PLL type. */
        PllType = XHdmiphy1_GetPllType(InstancePtr, QuadId, XHDMIPHY1_DIR_RX,
                    ChId);
        /* Determine which channel(s) to operate on. */
        switch (PllType) {
            case XHDMIPHY1_PLL_TYPE_QPLL:
            case XHDMIPHY1_PLL_TYPE_QPLL0:
                ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN0;
                PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL1;
                break;
            case XHDMIPHY1_PLL_TYPE_QPLL1:
                ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN1;
                PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL1;
                break;
            default:
                ChIdPll = ChId;
                PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL2;
                break;
        }

        LineRateKHz = XHdmiphy1_GetLineRateHz(InstancePtr, QuadId, ChIdPll) / 1000;
	/* ADAPT_CFG1 */
	if(LineRateKHz <= XHDMIPHY1_DRP_LINERATEKHZ_1) {
		DrpVal = XHDMIPHY1_DRP_ADAPT_CFG1_VAL1;
	} else {
		DrpVal = XHDMIPHY1_DRP_ADAPT_CFG1_VAL2;
	}
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0092, DrpVal);

        /* RX_XMODE_SEL */
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00D3, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_00D3_RX_MODE_SEL_MASK);
		if(LineRateKHz <= XHDMIPHY1_DRP_LINERATEKHZ_2) {
			DrpVal |= 0x1 << 1;
		} else {
			DrpVal |= 0x0;
		}
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00D3, DrpVal);

        /* RX_WIDEMODE_CDR Encoding */
        switch (ChPtr->RxDataWidth) {
        case 80:
		WriteVal = 0x2 << 2;
            break;
        case 64:
		if(LineRateKHz > XHDMIPHY1_DRP_LINERATEKHZ_3) {
			WriteVal = 0x2 << 2;
		} else {
			WriteVal = 0x1 << 2;
		}
            break;
        case 40:
		if(LineRateKHz > XHDMIPHY1_DRP_LINERATEKHZ_2) {
			WriteVal = 0x1 << 2;
		} else {
			WriteVal = 0x0;
		}
            break;
        case 32:
		if(LineRateKHz > XHDMIPHY1_DRP_LINERATEKHZ_1) {
			WriteVal = 0x1 << 2;
		} else {
			WriteVal = 0x0;
		}
            break;
        default:
		WriteVal = 0x0;
            break;
        }

        /* RX_INT_DATAWIDTH & RX_WIDEMODE_CDR */
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0066, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_0066_RX_INT_DATAWIDTH_MASK);
        /* Update RX_WIDEMODE_CDR Value */
        DrpVal |= WriteVal & XDRP_GTYE4_CHN_REG_0066_RX_WIDEMODE_CDR_MASK;
        WriteVal = (XHdmiphy1_DrpEncodeIntDataWidth(ChPtr->RxIntDataWidth) &
			XDRP_GTYE4_CHN_REG_0066_RX_WIDEMODE_CDR_MASK_VAL);
        /* Update RX_INT_DATAWIDTH Value*/
        DrpVal |= WriteVal & XDRP_GTYE4_CHN_REG_0066_RX_WIDEMODE_CDR_MASK_VAL;

        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0066, DrpVal);

        /* RX_DATA_WIDTH */
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0003, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_0003_RX_DATAWIDTH_MASK);
        WriteVal = (XHdmiphy1_DrpEncodeDataWidth(ChPtr->RxDataWidth) & 0xF);
        WriteVal <<= 5;
        DrpVal |= WriteVal;
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0003, DrpVal);

        PllxVcoRateMHz = XHdmiphy1_GetPllVcoFreqHz(InstancePtr, QuadId,
                            ChIdPll, XHDMIPHY1_DIR_RX) / 1000000;
        PllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv;

        /* CH_HSPMUX_RX */
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0116, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_0116_CH_RX_HSPMUX_MASK);
        if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE5) {
            DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL1;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4) {
            DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL2;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
            DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL3;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7) {
            DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL4;
        }
        else {
            DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL5;
        }

        /* Write new DRP register value for CH_HSPMUX_RX. */
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0116, DrpVal);
        /* PREIQ_FREQ_BST */
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00FB, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_00FB_PREIQ_FREQ_BST_MASK);
        if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4) {
        DrpVal |= 3 << 4;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
        DrpVal |= 2 << 4; /* LPM Mode */
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7) {
        DrpVal |= 1 << 4;
        }
        /* Write new DRP register value for PREIQ_FREQ_BST. */
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00FB, DrpVal);

        /* RXPI_CFG0 */
        if (PllxClkOutMHz > XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE8) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL1;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL2;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL3;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL4;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE9) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL5;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL6;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL7;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL8;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE10) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL9;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL10;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL11;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL12;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE11) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL13;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL14;
        }
        else {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL15;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL16;
        }

        /* Write new DRP register value for RXPI_CFG0. */
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0075, DrpVal);
        /* Write new DRP register value for RXPI_CFG1. */
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00D2, DrpVal2);

    }

    Status |= XHdmiphy1_Gtye4RxPllRefClkDiv1Reconfig(InstancePtr, QuadId,
                ChId);

    return Status;
}
/*****************************************************************************/
/**
* This function will configure the channel's RX settings.
*
* @param    InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param    QuadId is the GT quad ID to operate on.
* @param    ChId is the channel ID to operate on.
*
* @return
*       - XST_SUCCESS if the configuration was successful.
*       - XST_FAILURE otherwise.
*
* @note     None.
*
******************************************************************************/
This function will configure the channel's RX settings.
This function will configure the channel ' s RX settings .
u32 XHdmiphy1_Gtye4RxChReconfig(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId)
{
    XHdmiphy1_Channel *ChPtr;
    u16 DrpVal, DrpVal2;
    u16 WriteVal;
    u8 CfgIndex;
    XHdmiphy1_ChannelId ChIdPll;
    XHdmiphy1_PllType PllType;
    u32 PllxVcoRateMHz;
    u32 PllxClkOutMHz;
    u32 PllxClkOutDiv;
    u32 Status = XST_SUCCESS;
    u64 LineRateKHz;
    ChPtr = &InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(ChId)];
    for (CfgIndex = 0; CfgIndex < 5; CfgIndex++) {
        DrpVal = ChPtr->PllParams.Cdr[CfgIndex];
        if (!DrpVal) {
            continue;
        }
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId,
                    XHDMIPHY1_DRP_RXCDR_CFG(CfgIndex), DrpVal);
        if (CfgIndex == 2) {
            Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId,
                        XHDMIPHY1_DRP_RXCDR_CFG_GEN3(CfgIndex), DrpVal);
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XHDMIPHY1_DRP_RXCDR_CFG2_GEN2, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_0011_RXCDR_CGF2_GEN2_MASK);
        DrpVal |= ChPtr->PllParams.Cdr[CfgIndex] & XDRP_GTYE4_CHN_REG_0011_RXCDR_CGF2_GEN2_MASK;
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XHDMIPHY1_DRP_RXCDR_CFG2_GEN2, DrpVal);
        }
    }
    if (XHdmiphy1_IsHDMI(InstancePtr, XHDMIPHY1_DIR_RX)) {
        PllType = XHdmiphy1_GetPllType(InstancePtr, QuadId, XHDMIPHY1_DIR_RX,
                    ChId);
        switch (PllType) {
            case XHDMIPHY1_PLL_TYPE_QPLL:
            case XHDMIPHY1_PLL_TYPE_QPLL0:
                ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN0;
                PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL1;
                break;
            case XHDMIPHY1_PLL_TYPE_QPLL1:
                ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN1;
                PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL1;
                break;
            default:
                ChIdPll = ChId;
                PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL2;
                break;
        }
        LineRateKHz = XHdmiphy1_GetLineRateHz(InstancePtr, QuadId, ChIdPll) / 1000;
	if(LineRateKHz <= XHDMIPHY1_DRP_LINERATEKHZ_1) {
		DrpVal = XHDMIPHY1_DRP_ADAPT_CFG1_VAL1;
	} else {
		DrpVal = XHDMIPHY1_DRP_ADAPT_CFG1_VAL2;
	}
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0092, DrpVal);
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00D3, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_00D3_RX_MODE_SEL_MASK);
		if(LineRateKHz <= XHDMIPHY1_DRP_LINERATEKHZ_2) {
			DrpVal |= 0x1 << 1;
		} else {
			DrpVal |= 0x0;
		}
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00D3, DrpVal);
        switch (ChPtr->RxDataWidth) {
        case 80:
		WriteVal = 0x2 << 2;
            break;
        case 64:
		if(LineRateKHz > XHDMIPHY1_DRP_LINERATEKHZ_3) {
			WriteVal = 0x2 << 2;
		} else {
			WriteVal = 0x1 << 2;
		}
            break;
        case 40:
		if(LineRateKHz > XHDMIPHY1_DRP_LINERATEKHZ_2) {
			WriteVal = 0x1 << 2;
		} else {
			WriteVal = 0x0;
		}
            break;
        case 32:
		if(LineRateKHz > XHDMIPHY1_DRP_LINERATEKHZ_1) {
			WriteVal = 0x1 << 2;
		} else {
			WriteVal = 0x0;
		}
            break;
        default:
		WriteVal = 0x0;
            break;
        }
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0066, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_0066_RX_INT_DATAWIDTH_MASK);
        DrpVal |= WriteVal & XDRP_GTYE4_CHN_REG_0066_RX_WIDEMODE_CDR_MASK;
        WriteVal = (XHdmiphy1_DrpEncodeIntDataWidth(ChPtr->RxIntDataWidth) &
			XDRP_GTYE4_CHN_REG_0066_RX_WIDEMODE_CDR_MASK_VAL);
        DrpVal |= WriteVal & XDRP_GTYE4_CHN_REG_0066_RX_WIDEMODE_CDR_MASK_VAL;
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0066, DrpVal);
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0003, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_0003_RX_DATAWIDTH_MASK);
        WriteVal = (XHdmiphy1_DrpEncodeDataWidth(ChPtr->RxDataWidth) & 0xF);
        WriteVal <<= 5;
        DrpVal |= WriteVal;
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0003, DrpVal);
        PllxVcoRateMHz = XHdmiphy1_GetPllVcoFreqHz(InstancePtr, QuadId,
                            ChIdPll, XHDMIPHY1_DIR_RX) / 1000000;
        PllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv;
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0116, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_0116_CH_RX_HSPMUX_MASK);
        if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE5) {
            DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL1;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4) {
            DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL2;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
            DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL3;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7) {
            DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL4;
        }
        else {
            DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL5;
        }
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0116, DrpVal);
        Status |= XHdmiphy1_DrpRd(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00FB, &DrpVal);
        DrpVal &= ~(XDRP_GTYE4_CHN_REG_00FB_PREIQ_FREQ_BST_MASK);
        if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4) {
        DrpVal |= 3 << 4;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
        DrpVal |= 2 << 4; 
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7) {
        DrpVal |= 1 << 4;
        }
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00FB, DrpVal);
        if (PllxClkOutMHz > XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE8) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL1;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL2;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL3;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL4;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE9) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL5;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL6;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL7;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL8;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE10) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL9;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL10;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL11;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL12;
        }
        else if (PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE11) {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL13;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL14;
        }
        else {
            DrpVal  = XHDMIPHY1_DRP_RXPI_CFG0_VAL15;
            DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL16;
        }
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_0075, DrpVal);
        Status |= XHdmiphy1_DrpWr(InstancePtr, QuadId, ChId, XDRP_GTYE4_CHN_REG_00D2, DrpVal2);
    }
    Status |= XHdmiphy1_Gtye4RxPllRefClkDiv1Reconfig(InstancePtr, QuadId,
                ChId);
    return Status;
}
u32 XHdmiphy1_Gtye4RxChReconfig ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId ) { XHdmiphy1_Channel * ChPtr ; u16 DrpVal , DrpVal2 ; u16 WriteVal ; u8 CfgIndex ; XHdmiphy1_ChannelId ChIdPll ; XHdmiphy1_PllType PllType ; u32 PllxVcoRateMHz ; u32 PllxClkOutMHz ; u32 PllxClkOutDiv ; u32 Status = XST_SUCCESS ; u64 LineRateKHz ; ChPtr = & InstancePtr -> Quads [ QuadId ] . Plls [ XHDMIPHY1_CH2IDX ( ChId ) ] ; for ( CfgIndex = 0 ; CfgIndex < 5 ; CfgIndex ++ ) { DrpVal = ChPtr -> PllParams . Cdr [ CfgIndex ] ; if ( ! DrpVal ) { continue ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XHDMIPHY1_DRP_RXCDR_CFG ( CfgIndex ) , DrpVal ) ; if ( CfgIndex == 2 ) { Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XHDMIPHY1_DRP_RXCDR_CFG_GEN3 ( CfgIndex ) , DrpVal ) ; Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XHDMIPHY1_DRP_RXCDR_CFG2_GEN2 , & DrpVal ) ; DrpVal &= ~ ( XDRP_GTYE4_CHN_REG_0011_RXCDR_CGF2_GEN2_MASK ) ; DrpVal |= ChPtr -> PllParams . Cdr [ CfgIndex ] & XDRP_GTYE4_CHN_REG_0011_RXCDR_CGF2_GEN2_MASK ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XHDMIPHY1_DRP_RXCDR_CFG2_GEN2 , DrpVal ) ; } } if ( XHdmiphy1_IsHDMI ( InstancePtr , XHDMIPHY1_DIR_RX ) ) { PllType = XHdmiphy1_GetPllType ( InstancePtr , QuadId , XHDMIPHY1_DIR_RX , ChId ) ; switch ( PllType ) { case XHDMIPHY1_PLL_TYPE_QPLL : case XHDMIPHY1_PLL_TYPE_QPLL0 : ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN0 ; PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL1 ; break ; case XHDMIPHY1_PLL_TYPE_QPLL1 : ChIdPll = XHDMIPHY1_CHANNEL_ID_CMN1 ; PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL1 ; break ; default : ChIdPll = ChId ; PllxClkOutDiv = XHDMIPHY1_DRP_PLL_CLKOUT_DIV_VAL2 ; break ; } LineRateKHz = XHdmiphy1_GetLineRateHz ( InstancePtr , QuadId , ChIdPll ) / 1000 ; if ( LineRateKHz <= XHDMIPHY1_DRP_LINERATEKHZ_1 ) { DrpVal = XHDMIPHY1_DRP_ADAPT_CFG1_VAL1 ; } else { DrpVal = XHDMIPHY1_DRP_ADAPT_CFG1_VAL2 ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0092 , DrpVal ) ; Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00D3 , & DrpVal ) ; DrpVal &= ~ ( XDRP_GTYE4_CHN_REG_00D3_RX_MODE_SEL_MASK ) ; if ( LineRateKHz <= XHDMIPHY1_DRP_LINERATEKHZ_2 ) { DrpVal |= 0x1 << 1 ; } else { DrpVal |= 0x0 ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00D3 , DrpVal ) ; switch ( ChPtr -> RxDataWidth ) { case 80 : WriteVal = 0x2 << 2 ; break ; case 64 : if ( LineRateKHz > XHDMIPHY1_DRP_LINERATEKHZ_3 ) { WriteVal = 0x2 << 2 ; } else { WriteVal = 0x1 << 2 ; } break ; case 40 : if ( LineRateKHz > XHDMIPHY1_DRP_LINERATEKHZ_2 ) { WriteVal = 0x1 << 2 ; } else { WriteVal = 0x0 ; } break ; case 32 : if ( LineRateKHz > XHDMIPHY1_DRP_LINERATEKHZ_1 ) { WriteVal = 0x1 << 2 ; } else { WriteVal = 0x0 ; } break ; default : WriteVal = 0x0 ; break ; } Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0066 , & DrpVal ) ; DrpVal &= ~ ( XDRP_GTYE4_CHN_REG_0066_RX_INT_DATAWIDTH_MASK ) ; DrpVal |= WriteVal & XDRP_GTYE4_CHN_REG_0066_RX_WIDEMODE_CDR_MASK ; WriteVal = ( XHdmiphy1_DrpEncodeIntDataWidth ( ChPtr -> RxIntDataWidth ) & XDRP_GTYE4_CHN_REG_0066_RX_WIDEMODE_CDR_MASK_VAL ) ; DrpVal |= WriteVal & XDRP_GTYE4_CHN_REG_0066_RX_WIDEMODE_CDR_MASK_VAL ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0066 , DrpVal ) ; Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0003 , & DrpVal ) ; DrpVal &= ~ ( XDRP_GTYE4_CHN_REG_0003_RX_DATAWIDTH_MASK ) ; WriteVal = ( XHdmiphy1_DrpEncodeDataWidth ( ChPtr -> RxDataWidth ) & 0xF ) ; WriteVal <<= 5 ; DrpVal |= WriteVal ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0003 , DrpVal ) ; PllxVcoRateMHz = XHdmiphy1_GetPllVcoFreqHz ( InstancePtr , QuadId , ChIdPll , XHDMIPHY1_DIR_RX ) / 1000000 ; PllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv ; Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0116 , & DrpVal ) ; DrpVal &= ~ ( XDRP_GTYE4_CHN_REG_0116_CH_RX_HSPMUX_MASK ) ; if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE5 ) { DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL1 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4 ) { DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL2 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6 ) { DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL3 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7 ) { DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL4 ; } else { DrpVal |= XHDMIPHY1_DRP_CH_HSPMUX_VAL5 ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0116 , DrpVal ) ; Status |= XHdmiphy1_DrpRd ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00FB , & DrpVal ) ; DrpVal &= ~ ( XDRP_GTYE4_CHN_REG_00FB_PREIQ_FREQ_BST_MASK ) ; if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4 ) { DrpVal |= 3 << 4 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6 ) { DrpVal |= 2 << 4 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7 ) { DrpVal |= 1 << 4 ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00FB , DrpVal ) ; if ( PllxClkOutMHz > XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE8 ) { DrpVal = XHDMIPHY1_DRP_RXPI_CFG0_VAL1 ; DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL2 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE4 ) { DrpVal = XHDMIPHY1_DRP_RXPI_CFG0_VAL3 ; DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL4 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE9 ) { DrpVal = XHDMIPHY1_DRP_RXPI_CFG0_VAL5 ; DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL6 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE6 ) { DrpVal = XHDMIPHY1_DRP_RXPI_CFG0_VAL7 ; DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL8 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE10 ) { DrpVal = XHDMIPHY1_DRP_RXPI_CFG0_VAL9 ; DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL10 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE7 ) { DrpVal = XHDMIPHY1_DRP_RXPI_CFG0_VAL11 ; DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL12 ; } else if ( PllxClkOutMHz >= XHDMIPHY1_DRP_PLLx_CLKOUT_RANGE11 ) { DrpVal = XHDMIPHY1_DRP_RXPI_CFG0_VAL13 ; DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL14 ; } else { DrpVal = XHDMIPHY1_DRP_RXPI_CFG0_VAL15 ; DrpVal2 = XHDMIPHY1_DRP_RXPI_CFG0_VAL16 ; } Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_0075 , DrpVal ) ; Status |= XHdmiphy1_DrpWr ( InstancePtr , QuadId , ChId , XDRP_GTYE4_CHN_REG_00D2 , DrpVal2 ) ; } Status |= XHdmiphy1_Gtye4RxPllRefClkDiv1Reconfig ( InstancePtr , QuadId , ChId ) ; return Status ; }
This function will configure the channel's RX settings.
This function will configure the channel ' s RX settings .
/* RXCDR_CFG(CfgIndex) */ /* Don't modify RX_CDR configuration. */ /* RXCDR_CFG2_GEN2 */ /* Determine PLL type. */ /* Determine which channel(s) to operate on. */ /* ADAPT_CFG1 */ /* RX_XMODE_SEL */ /* RX_WIDEMODE_CDR Encoding */ /* RX_INT_DATAWIDTH & RX_WIDEMODE_CDR */ /* Update RX_WIDEMODE_CDR Value */ /* Update RX_INT_DATAWIDTH Value*/ /* RX_DATA_WIDTH */ /* CH_HSPMUX_RX */ /* Write new DRP register value for CH_HSPMUX_RX. */ /* PREIQ_FREQ_BST */ /* LPM Mode */ /* Write new DRP register value for PREIQ_FREQ_BST. */ /* RXPI_CFG0 */ /* Write new DRP register value for RXPI_CFG0. */ /* Write new DRP register value for RXPI_CFG1. */