src/dpdk/drivers/common/iavf/iavf_adminq.c
enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
					     struct iavf_arq_event_info *e,
					     u16 *pending)
{
	enum iavf_status ret_code = IAVF_SUCCESS;
	u16 ntc = hw->aq.arq.next_to_clean;
	struct iavf_aq_desc *desc;
	struct iavf_dma_mem *bi;
	u16 desc_idx;
	u16 datalen;
	u16 flags;
	u16 ntu;

	/* pre-clean the event info */
	iavf_memset(&e->desc, 0, sizeof(e->desc), IAVF_NONDMA_MEM);

	/* take the lock before we start messing with the ring */
	iavf_acquire_spinlock(&hw->aq.arq_spinlock);

	if (hw->aq.arq.count == 0) {
		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
			   "AQRX: Admin queue not initialized.\n");
		ret_code = IAVF_ERR_QUEUE_EMPTY;
		goto clean_arq_element_err;
	}

	/* set next_to_use to head */
	ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;
	if (ntu == ntc) {
		/* nothing to do - shouldn't need to update ring's values */
		ret_code = IAVF_ERR_ADMIN_QUEUE_NO_WORK;
		goto clean_arq_element_out;
	}

	/* now clean the next descriptor */
	desc = IAVF_ADMINQ_DESC(hw->aq.arq, ntc);
	desc_idx = ntc;

	hw->aq.arq_last_status =
		(enum iavf_admin_queue_err)LE16_TO_CPU(desc->retval);
	flags = LE16_TO_CPU(desc->flags);
	if (flags & IAVF_AQ_FLAG_ERR) {
		ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;
		iavf_debug(hw,
			   IAVF_DEBUG_AQ_MESSAGE,
			   "AQRX: Event received with error 0x%X.\n",
			   hw->aq.arq_last_status);
	}

	iavf_memcpy(&e->desc, desc, sizeof(struct iavf_aq_desc),
		    IAVF_DMA_TO_NONDMA);
	datalen = LE16_TO_CPU(desc->datalen);
	e->msg_len = min(datalen, e->buf_len);
	if (e->msg_buf != NULL && (e->msg_len != 0))
		iavf_memcpy(e->msg_buf,
			    hw->aq.arq.r.arq_bi[desc_idx].va,
			    e->msg_len, IAVF_DMA_TO_NONDMA);

	iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
	iavf_debug_aq(hw, IAVF_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
		      hw->aq.arq_buf_size);

	/* Restore the original datalen and buffer address in the desc,
	 * FW updates datalen to indicate the event message
	 * size
	 */
	bi = &hw->aq.arq.r.arq_bi[ntc];
	iavf_memset((void *)desc, 0, sizeof(struct iavf_aq_desc), IAVF_DMA_MEM);

	desc->flags = CPU_TO_LE16(IAVF_AQ_FLAG_BUF);
	if (hw->aq.arq_buf_size > IAVF_AQ_LARGE_BUF)
		desc->flags |= CPU_TO_LE16(IAVF_AQ_FLAG_LB);
	desc->datalen = CPU_TO_LE16((u16)bi->size);
	desc->params.external.addr_high = CPU_TO_LE32(IAVF_HI_DWORD(bi->pa));
	desc->params.external.addr_low = CPU_TO_LE32(IAVF_LO_DWORD(bi->pa));

	/* set tail = the last cleaned desc index. */
	wr32(hw, hw->aq.arq.tail, ntc);
	/* ntc is updated to tail + 1 */
	ntc++;
	if (ntc == hw->aq.num_arq_entries)
		ntc = 0;
	hw->aq.arq.next_to_clean = ntc;
	hw->aq.arq.next_to_use = ntu;

clean_arq_element_out:
	/* Set pending if needed, unlock and return */
	if (pending != NULL)
		*pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
clean_arq_element_err:
	iavf_release_spinlock(&hw->aq.arq_spinlock);

	return ret_code;
}
/**
 *  iavf_clean_arq_element
 *  @hw: pointer to the hw struct
 *  @e: event info from the receive descriptor, includes any buffers
 *  @pending: number of events that could be left to process
 *
 *  This function cleans one Admin Receive Queue element and returns
 *  the contents through e.  It can also return how many events are
 *  left to process through 'pending'
 **/
iavf_clean_arq_element
@hw: pointer to the hw struct
@e: event info from the receive descriptor, includes any buffers
@pending: number of events that could be left to process

This function cleans one Admin Receive Queue element and returns
the contents through e.  It can also return how many events are
left to process through 'pending'
iavf_clean_arq_element @hw : pointer to the hw struct @e : event info from the receive descriptor includes any buffers @pending : number of events that could be left to process This function cleans one Admin Receive Queue element and returns the contents through e . It can also return how many events are left to process through ' pending '
enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
					     struct iavf_arq_event_info *e,
					     u16 *pending)
{
	enum iavf_status ret_code = IAVF_SUCCESS;
	u16 ntc = hw->aq.arq.next_to_clean;
	struct iavf_aq_desc *desc;
	struct iavf_dma_mem *bi;
	u16 desc_idx;
	u16 datalen;
	u16 flags;
	u16 ntu;
	iavf_memset(&e->desc, 0, sizeof(e->desc), IAVF_NONDMA_MEM);
	iavf_acquire_spinlock(&hw->aq.arq_spinlock);
	if (hw->aq.arq.count == 0) {
		iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
			   "AQRX: Admin queue not initialized.\n");
		ret_code = IAVF_ERR_QUEUE_EMPTY;
		goto clean_arq_element_err;
	}
	ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;
	if (ntu == ntc) {
		ret_code = IAVF_ERR_ADMIN_QUEUE_NO_WORK;
		goto clean_arq_element_out;
	}
	desc = IAVF_ADMINQ_DESC(hw->aq.arq, ntc);
	desc_idx = ntc;
	hw->aq.arq_last_status =
		(enum iavf_admin_queue_err)LE16_TO_CPU(desc->retval);
	flags = LE16_TO_CPU(desc->flags);
	if (flags & IAVF_AQ_FLAG_ERR) {
		ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;
		iavf_debug(hw,
			   IAVF_DEBUG_AQ_MESSAGE,
			   "AQRX: Event received with error 0x%X.\n",
			   hw->aq.arq_last_status);
	}
	iavf_memcpy(&e->desc, desc, sizeof(struct iavf_aq_desc),
		    IAVF_DMA_TO_NONDMA);
	datalen = LE16_TO_CPU(desc->datalen);
	e->msg_len = min(datalen, e->buf_len);
	if (e->msg_buf != NULL && (e->msg_len != 0))
		iavf_memcpy(e->msg_buf,
			    hw->aq.arq.r.arq_bi[desc_idx].va,
			    e->msg_len, IAVF_DMA_TO_NONDMA);
	iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
	iavf_debug_aq(hw, IAVF_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
		      hw->aq.arq_buf_size);
	bi = &hw->aq.arq.r.arq_bi[ntc];
	iavf_memset((void *)desc, 0, sizeof(struct iavf_aq_desc), IAVF_DMA_MEM);
	desc->flags = CPU_TO_LE16(IAVF_AQ_FLAG_BUF);
	if (hw->aq.arq_buf_size > IAVF_AQ_LARGE_BUF)
		desc->flags |= CPU_TO_LE16(IAVF_AQ_FLAG_LB);
	desc->datalen = CPU_TO_LE16((u16)bi->size);
	desc->params.external.addr_high = CPU_TO_LE32(IAVF_HI_DWORD(bi->pa));
	desc->params.external.addr_low = CPU_TO_LE32(IAVF_LO_DWORD(bi->pa));
	wr32(hw, hw->aq.arq.tail, ntc);
	ntc++;
	if (ntc == hw->aq.num_arq_entries)
		ntc = 0;
	hw->aq.arq.next_to_clean = ntc;
	hw->aq.arq.next_to_use = ntu;
clean_arq_element_out:
	if (pending != NULL)
		*pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
clean_arq_element_err:
	iavf_release_spinlock(&hw->aq.arq_spinlock);
	return ret_code;
}
enum iavf_status iavf_clean_arq_element ( struct iavf_hw * hw , struct iavf_arq_event_info * e , u16 * pending ) { enum iavf_status ret_code = IAVF_SUCCESS ; u16 ntc = hw -> aq . arq . next_to_clean ; struct iavf_aq_desc * desc ; struct iavf_dma_mem * bi ; u16 desc_idx ; u16 datalen ; u16 flags ; u16 ntu ; iavf_memset ( & e -> desc , 0 , sizeof ( e -> desc ) , IAVF_NONDMA_MEM ) ; iavf_acquire_spinlock ( & hw -> aq . arq_spinlock ) ; if ( hw -> aq . arq . count == 0 ) { iavf_debug ( hw , IAVF_DEBUG_AQ_MESSAGE , " \n " ) ; ret_code = IAVF_ERR_QUEUE_EMPTY ; goto clean_arq_element_err ; } ntu = rd32 ( hw , hw -> aq . arq . head ) & IAVF_VF_ARQH1_ARQH_MASK ; if ( ntu == ntc ) { ret_code = IAVF_ERR_ADMIN_QUEUE_NO_WORK ; goto clean_arq_element_out ; } desc = IAVF_ADMINQ_DESC ( hw -> aq . arq , ntc ) ; desc_idx = ntc ; hw -> aq . arq_last_status = ( enum iavf_admin_queue_err ) LE16_TO_CPU ( desc -> retval ) ; flags = LE16_TO_CPU ( desc -> flags ) ; if ( flags & IAVF_AQ_FLAG_ERR ) { ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR ; iavf_debug ( hw , IAVF_DEBUG_AQ_MESSAGE , " \n " , hw -> aq . arq_last_status ) ; } iavf_memcpy ( & e -> desc , desc , sizeof ( struct iavf_aq_desc ) , IAVF_DMA_TO_NONDMA ) ; datalen = LE16_TO_CPU ( desc -> datalen ) ; e -> msg_len = min ( datalen , e -> buf_len ) ; if ( e -> msg_buf != NULL && ( e -> msg_len != 0 ) ) iavf_memcpy ( e -> msg_buf , hw -> aq . arq . r . arq_bi [ desc_idx ] . va , e -> msg_len , IAVF_DMA_TO_NONDMA ) ; iavf_debug ( hw , IAVF_DEBUG_AQ_MESSAGE , " \n " ) ; iavf_debug_aq ( hw , IAVF_DEBUG_AQ_COMMAND , ( void * ) desc , e -> msg_buf , hw -> aq . arq_buf_size ) ; bi = & hw -> aq . arq . r . arq_bi [ ntc ] ; iavf_memset ( ( void * ) desc , 0 , sizeof ( struct iavf_aq_desc ) , IAVF_DMA_MEM ) ; desc -> flags = CPU_TO_LE16 ( IAVF_AQ_FLAG_BUF ) ; if ( hw -> aq . arq_buf_size > IAVF_AQ_LARGE_BUF ) desc -> flags |= CPU_TO_LE16 ( IAVF_AQ_FLAG_LB ) ; desc -> datalen = CPU_TO_LE16 ( ( u16 ) bi -> size ) ; desc -> params . external . addr_high = CPU_TO_LE32 ( IAVF_HI_DWORD ( bi -> pa ) ) ; desc -> params . external . addr_low = CPU_TO_LE32 ( IAVF_LO_DWORD ( bi -> pa ) ) ; wr32 ( hw , hw -> aq . arq . tail , ntc ) ; ntc ++ ; if ( ntc == hw -> aq . num_arq_entries ) ntc = 0 ; hw -> aq . arq . next_to_clean = ntc ; hw -> aq . arq . next_to_use = ntu ; clean_arq_element_out : if ( pending != NULL ) * pending = ( ntc > ntu ? hw -> aq . arq . count : 0 ) + ( ntu - ntc ) ; clean_arq_element_err : iavf_release_spinlock ( & hw -> aq . arq_spinlock ) ; return ret_code ; }
iavf_clean_arq_element
  @hw: pointer to the hw struct
  @e: event info from the receive descriptor, includes any buffers
  @pending: number of events that could be left to process
iavf_clean_arq_element @hw : pointer to the hw struct @e : event info from the receive descriptor includes any buffers @pending : number of events that could be left to process
/* pre-clean the event info */ /* take the lock before we start messing with the ring */ /* set next_to_use to head */ /* nothing to do - shouldn't need to update ring's values */ /* now clean the next descriptor */ /* Restore the original datalen and buffer address in the desc,
	 * FW updates datalen to indicate the event message
	 * size
	 */ /* set tail = the last cleaned desc index. */ /* ntc is updated to tail + 1 */ /* Set pending if needed, unlock and return */