target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c
static void rtl838x_pie_init(struct rtl838x_switch_priv *priv)
{
	int i;
	u32 template_selectors;

	mutex_init(&priv->pie_mutex);

	// Enable ACL lookup on all ports, including CPU_PORT
	for (i = 0; i <= priv->cpu_port; i++)
		sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i));

	// Power on all PIE blocks
	for (i = 0; i < priv->n_pie_blocks; i++)
		sw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL);

	// Include IPG in metering
	sw_w32(1, RTL838X_METER_GLB_CTRL);

	// Delete all present rules
	rtl838x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);

	// Routing bypasses source port filter: disable write-protection, first
	sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL);
	sw_w32_mask(0, 1, RTL838X_DMY_REG27);
	sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL);

	// Enable predefined templates 0, 1 and 2 for even blocks
	template_selectors = 0 | (1 << 3) | (2 << 6);
	for (i = 0; i < 6; i += 2)
		sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));

	// Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks
	template_selectors = 0 | (3 << 3) | (4 << 6);
	for (i = 1; i < priv->n_pie_blocks; i += 2)
		sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));

	// Group each pair of physical blocks together to a logical block
	sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL);
}
/*
 * Initializes the Packet Inspection Engine:
 * powers it up, enables default matching templates for all blocks
 * and clears all rules possibly installed by u-boot
 */
Initializes the Packet Inspection Engine:
powers it up, enables default matching templates for all blocks
and clears all rules possibly installed by u-boot
Initializes the Packet Inspection Engine : powers it up enables default matching templates for all blocks and clears all rules possibly installed by u - boot
static void rtl838x_pie_init(struct rtl838x_switch_priv *priv)
{
	int i;
	u32 template_selectors;
	mutex_init(&priv->pie_mutex);
	for (i = 0; i <= priv->cpu_port; i++)
		sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i));
	for (i = 0; i < priv->n_pie_blocks; i++)
		sw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL);
	sw_w32(1, RTL838X_METER_GLB_CTRL);
	rtl838x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);
	sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL);
	sw_w32_mask(0, 1, RTL838X_DMY_REG27);
	sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL);
	template_selectors = 0 | (1 << 3) | (2 << 6);
	for (i = 0; i < 6; i += 2)
		sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
	template_selectors = 0 | (3 << 3) | (4 << 6);
	for (i = 1; i < priv->n_pie_blocks; i += 2)
		sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));
	sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL);
}
static void rtl838x_pie_init ( struct rtl838x_switch_priv * priv ) { int i ; u32 template_selectors ; mutex_init ( & priv -> pie_mutex ) ; for ( i = 0 ; i <= priv -> cpu_port ; i ++ ) sw_w32 ( 1 , RTL838X_ACL_PORT_LOOKUP_CTRL ( i ) ) ; for ( i = 0 ; i < priv -> n_pie_blocks ; i ++ ) sw_w32_mask ( 0 , BIT ( i ) , RTL838X_ACL_BLK_PWR_CTRL ) ; sw_w32 ( 1 , RTL838X_METER_GLB_CTRL ) ; rtl838x_pie_rule_del ( priv , 0 , priv -> n_pie_blocks * PIE_BLOCK_SIZE - 1 ) ; sw_w32_mask ( 0 , 3 , RTL838X_INT_RW_CTRL ) ; sw_w32_mask ( 0 , 1 , RTL838X_DMY_REG27 ) ; sw_w32_mask ( 3 , 0 , RTL838X_INT_RW_CTRL ) ; template_selectors = 0 | ( 1 << 3 ) | ( 2 << 6 ) ; for ( i = 0 ; i < 6 ; i += 2 ) sw_w32 ( template_selectors , RTL838X_ACL_BLK_TMPLTE_CTRL ( i ) ) ; template_selectors = 0 | ( 3 << 3 ) | ( 4 << 6 ) ; for ( i = 1 ; i < priv -> n_pie_blocks ; i += 2 ) sw_w32 ( template_selectors , RTL838X_ACL_BLK_TMPLTE_CTRL ( i ) ) ; sw_w32 ( 0b10101010101 , RTL838X_ACL_BLK_GROUP_CTRL ) ; }
Initializes the Packet Inspection Engine:
 powers it up, enables default matching templates for all blocks
 and clears all rules possibly installed by u-boot
Initializes the Packet Inspection Engine : powers it up enables default matching templates for all blocks and clears all rules possibly installed by u - boot
// Enable ACL lookup on all ports, including CPU_PORT // Power on all PIE blocks // Include IPG in metering // Delete all present rules // Routing bypasses source port filter: disable write-protection, first // Enable predefined templates 0, 1 and 2 for even blocks // Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks // Group each pair of physical blocks together to a logical block