hal/rtl8192e/pci/rtl8192ee_xmit.c
void fill_txdesc_own(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *txdesc, u32 current_desc_idx)
{
	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
	struct rtw_tx_ring	*ring;
	u16	queue_idx = 0, next_desc_idx;

	queue_idx = rtw_get_ff_hwaddr(pxmitframe);
	ring = &pxmitpriv->tx_ring[queue_idx];

	buf_desc_debug("TX: enter %s(%d), queue_idx = %d, desc_idx = %x, txdesc = %x, pointer = 0x%08x, dma_startaddr = 0x%08x\n ", \
		__FUNCTION__, __LINE__, queue_idx, current_desc_idx, (u32)txdesc, \
		       rtw_read32(padapter, get_txbd_rw_reg(queue_idx)),
		       (u32)ring->dma);

	if (txdesc == NULL)
		return;

	if (queue_idx == BCN_QUEUE_INX) {
		/* Adapter->CurrentTXWritePoint[QueueIndex] = Adapter->CurrentTXReadPoint[QueueIndex] =0; */

		SET_TX_BUFF_DESC_OWN_92E(txdesc, 1);

		/* kick start */
		rtw_write8(padapter, REG_RX_RXBD_NUM + 1,
			   rtw_read8(padapter, REG_RX_RXBD_NUM + 1) | BIT(4));

		return;
	}

	/* 8192EE_TODO */
	if (0) {
		int i, j;
		u8 *buf = pxmitframe->buf_addr + TX_WIFI_INFO_SIZE;
		RTW_INFO("##############%s###############\n", __FUNCTION__);


		for (i = 0; i < 32; i++) {
			if ((i % 16 == 0) && (i != 0))
				_dbgdump("\n");
			_dbgdump("%02X ", *(buf + i));

			if (i % 4 == 3)
				_dbgdump("\t");
		}
		RTW_INFO("\n#############################\n");

	}
	/* 8192EE_TODO */

	/* update h/w index */
	/* for tx side, if own bit is set in packet index n, host pointer (write pointer) point to index n + 1. */
	next_desc_idx = (current_desc_idx + 1) % ring->entries;
	rtw_write16(padapter, get_txbd_rw_reg(queue_idx), next_desc_idx);
	buf_desc_debug("TX: exit %s(%d), after update h/w idx, pointer = 0x%08x\n", __FUNCTION__, __LINE__, rtw_read32(padapter, get_txbd_rw_reg(queue_idx)));
#if 0
	Adapter->CurrentTXWritePoint[QueueIndex] = ((Adapter->CurrentTXWritePoint[QueueIndex] + 1) % MaxTxDesc);

	if (Adapter->AvailableDescToWrite[QueueIndex] > 1) {
		Adapter->AvailableDescToWrite[QueueIndex]--;

		PlatformEFIOWrite2Byte(Adapter, GetDescAddressFromQueueIndex(QueueIndex), Adapter->CurrentTXWritePoint[QueueIndex]);

		if (QueueIndex == 1)
			lasttxwpoint = CurrentTXWritePoint;
	}


	if (Adapter->AvailableDescToWrite[QueueIndex] < (MaxTxDesc - 15)) {
		u2Byte PointDiff = 0;
		tmp4Byte = PlatformEFIORead4Byte(Adapter, GetDescAddressFromQueueIndex(QueueIndex)); /* be queue. */
		CurrentTXReadPoint = (u2Byte)((tmp4Byte >> 16) & 0x0fff);
		CurrentTXWritePoint = (u2Byte)((tmp4Byte) & 0x0fff);

		Adapter->CurrentTXWritePoint[QueueIndex] = CurrentTXWritePoint;

		if (Adapter->CurrentTXWritePoint[QueueIndex] != CurrentTXWritePoint)
			RT_DISP(FRW_POINT, FRW_POINT_DBG, ("CurrentTXWritePoint[%d] = %d !=   TmpValue %x\n", QueueIndex, Adapter->CurrentTXWritePoint[QueueIndex], tmp4Byte));
		Adapter->CurrentTXReadPoint[QueueIndex] = CurrentTXReadPoint;
		PointDiff = ((CurrentTXReadPoint > CurrentTXWritePoint) ? (CurrentTXReadPoint - CurrentTXWritePoint) : (TX_DESC_NUM_92E-CurrentTXWritePoint + CurrentTXReadPoint));

		Adapter->AvailableDescToWrite[QueueIndex] = PointDiff;
	}
#endif
}
/*
  * Update Read/Write pointer
  *		Read pointer is h/w descriptor index
  *		Write pointer is host desciptor index: For tx side, if own bit is set in packet index n,
  *										host pointer (write pointer) point to index n + 1.)
  */
Update Read/Write pointer
Read pointer is h/w descriptor index
Write pointer is host desciptor index: For tx side, if own bit is set in packet index n,
host pointer (write pointer) point to index n + 1.)
Update Read / Write pointer Read pointer is h / w descriptor index Write pointer is host desciptor index : For tx side if own bit is set in packet index n host pointer ( write pointer ) point to index n + 1 . )
void fill_txdesc_own(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *txdesc, u32 current_desc_idx)
{
	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
	struct rtw_tx_ring	*ring;
	u16	queue_idx = 0, next_desc_idx;
	queue_idx = rtw_get_ff_hwaddr(pxmitframe);
	ring = &pxmitpriv->tx_ring[queue_idx];
	buf_desc_debug("TX: enter %s(%d), queue_idx = %d, desc_idx = %x, txdesc = %x, pointer = 0x%08x, dma_startaddr = 0x%08x\n ", \
		__FUNCTION__, __LINE__, queue_idx, current_desc_idx, (u32)txdesc, \
		       rtw_read32(padapter, get_txbd_rw_reg(queue_idx)),
		       (u32)ring->dma);
	if (txdesc == NULL)
		return;
	if (queue_idx == BCN_QUEUE_INX) {
		SET_TX_BUFF_DESC_OWN_92E(txdesc, 1);
		rtw_write8(padapter, REG_RX_RXBD_NUM + 1,
			   rtw_read8(padapter, REG_RX_RXBD_NUM + 1) | BIT(4));
		return;
	}
	if (0) {
		int i, j;
		u8 *buf = pxmitframe->buf_addr + TX_WIFI_INFO_SIZE;
		RTW_INFO("##############%s###############\n", __FUNCTION__);
		for (i = 0; i < 32; i++) {
			if ((i % 16 == 0) && (i != 0))
				_dbgdump("\n");
			_dbgdump("%02X ", *(buf + i));
			if (i % 4 == 3)
				_dbgdump("\t");
		}
		RTW_INFO("\n#############################\n");
	}
	next_desc_idx = (current_desc_idx + 1) % ring->entries;
	rtw_write16(padapter, get_txbd_rw_reg(queue_idx), next_desc_idx);
	buf_desc_debug("TX: exit %s(%d), after update h/w idx, pointer = 0x%08x\n", __FUNCTION__, __LINE__, rtw_read32(padapter, get_txbd_rw_reg(queue_idx)));
#if 0
	Adapter->CurrentTXWritePoint[QueueIndex] = ((Adapter->CurrentTXWritePoint[QueueIndex] + 1) % MaxTxDesc);
	if (Adapter->AvailableDescToWrite[QueueIndex] > 1) {
		Adapter->AvailableDescToWrite[QueueIndex]--;
		PlatformEFIOWrite2Byte(Adapter, GetDescAddressFromQueueIndex(QueueIndex), Adapter->CurrentTXWritePoint[QueueIndex]);
		if (QueueIndex == 1)
			lasttxwpoint = CurrentTXWritePoint;
	}
	if (Adapter->AvailableDescToWrite[QueueIndex] < (MaxTxDesc - 15)) {
		u2Byte PointDiff = 0;
		tmp4Byte = PlatformEFIORead4Byte(Adapter, GetDescAddressFromQueueIndex(QueueIndex)); 
		CurrentTXReadPoint = (u2Byte)((tmp4Byte >> 16) & 0x0fff);
		CurrentTXWritePoint = (u2Byte)((tmp4Byte) & 0x0fff);
		Adapter->CurrentTXWritePoint[QueueIndex] = CurrentTXWritePoint;
		if (Adapter->CurrentTXWritePoint[QueueIndex] != CurrentTXWritePoint)
			RT_DISP(FRW_POINT, FRW_POINT_DBG, ("CurrentTXWritePoint[%d] = %d !=   TmpValue %x\n", QueueIndex, Adapter->CurrentTXWritePoint[QueueIndex], tmp4Byte));
		Adapter->CurrentTXReadPoint[QueueIndex] = CurrentTXReadPoint;
		PointDiff = ((CurrentTXReadPoint > CurrentTXWritePoint) ? (CurrentTXReadPoint - CurrentTXWritePoint) : (TX_DESC_NUM_92E-CurrentTXWritePoint + CurrentTXReadPoint));
		Adapter->AvailableDescToWrite[QueueIndex] = PointDiff;
	}
#endif
}
void fill_txdesc_own ( _adapter * padapter , struct xmit_frame * pxmitframe , u8 * txdesc , u32 current_desc_idx ) { struct xmit_priv * pxmitpriv = & padapter -> xmitpriv ; struct rtw_tx_ring * ring ; u16 queue_idx = 0 , next_desc_idx ; queue_idx = rtw_get_ff_hwaddr ( pxmitframe ) ; ring = & pxmitpriv -> tx_ring [ queue_idx ] ; buf_desc_debug ( " \n " , __FUNCTION__ , __LINE__ , queue_idx , current_desc_idx , ( u32 ) txdesc , rtw_read32 ( padapter , get_txbd_rw_reg ( queue_idx ) ) , ( u32 ) ring -> dma ) ; if ( txdesc == NULL ) return ; if ( queue_idx == BCN_QUEUE_INX ) { SET_TX_BUFF_DESC_OWN_92E ( txdesc , 1 ) ; rtw_write8 ( padapter , REG_RX_RXBD_NUM + 1 , rtw_read8 ( padapter , REG_RX_RXBD_NUM + 1 ) | BIT ( 4 ) ) ; return ; } if ( 0 ) { int i , j ; u8 * buf = pxmitframe -> buf_addr + TX_WIFI_INFO_SIZE ; RTW_INFO ( " \n " , __FUNCTION__ ) ; for ( i = 0 ; i < 32 ; i ++ ) { if ( ( i % 16 == 0 ) && ( i != 0 ) ) _dbgdump ( " \n " ) ; _dbgdump ( " " , * ( buf + i ) ) ; if ( i % 4 == 3 ) _dbgdump ( " \t " ) ; } RTW_INFO ( " \n \n " ) ; } next_desc_idx = ( current_desc_idx + 1 ) % ring -> entries ; rtw_write16 ( padapter , get_txbd_rw_reg ( queue_idx ) , next_desc_idx ) ; buf_desc_debug ( " \n " , __FUNCTION__ , __LINE__ , rtw_read32 ( padapter , get_txbd_rw_reg ( queue_idx ) ) ) ; #if 0 Adapter -> CurrentTXWritePoint [ QueueIndex ] = ( ( Adapter -> CurrentTXWritePoint [ QueueIndex ] + 1 ) % MaxTxDesc ) ; if ( Adapter -> AvailableDescToWrite [ QueueIndex ] > 1 ) { Adapter -> AvailableDescToWrite [ QueueIndex ] -- ; PlatformEFIOWrite2Byte ( Adapter , GetDescAddressFromQueueIndex ( QueueIndex ) , Adapter -> CurrentTXWritePoint [ QueueIndex ] ) ; if ( QueueIndex == 1 ) lasttxwpoint = CurrentTXWritePoint ; } if ( Adapter -> AvailableDescToWrite [ QueueIndex ] < ( MaxTxDesc - 15 ) ) { u2Byte PointDiff = 0 ; tmp4Byte = PlatformEFIORead4Byte ( Adapter , GetDescAddressFromQueueIndex ( QueueIndex ) ) ; CurrentTXReadPoint = ( u2Byte ) ( ( tmp4Byte >> 16 ) & 0x0fff ) ; CurrentTXWritePoint = ( u2Byte ) ( ( tmp4Byte ) & 0x0fff ) ; Adapter -> CurrentTXWritePoint [ QueueIndex ] = CurrentTXWritePoint ; if ( Adapter -> CurrentTXWritePoint [ QueueIndex ] != CurrentTXWritePoint ) RT_DISP ( FRW_POINT , FRW_POINT_DBG , ( " \n " , QueueIndex , Adapter -> CurrentTXWritePoint [ QueueIndex ] , tmp4Byte ) ) ; Adapter -> CurrentTXReadPoint [ QueueIndex ] = CurrentTXReadPoint ; PointDiff = ( ( CurrentTXReadPoint > CurrentTXWritePoint ) ? ( CurrentTXReadPoint - CurrentTXWritePoint ) : ( TX_DESC_NUM_92E - CurrentTXWritePoint + CurrentTXReadPoint ) ) ; Adapter -> AvailableDescToWrite [ QueueIndex ] = PointDiff ; } #endif }
Update Read/Write pointer
             Read pointer is h/w descriptor index
             Write pointer is host desciptor index: For tx side, if own bit is set in packet index n,
                                                                             host pointer (write pointer) point to index n + 1.)
Update Read / Write pointer Read pointer is h / w descriptor index Write pointer is host desciptor index : For tx side if own bit is set in packet index n host pointer ( write pointer ) point to index n + 1 . )
/* Adapter->CurrentTXWritePoint[QueueIndex] = Adapter->CurrentTXReadPoint[QueueIndex] =0; */ /* kick start */ /* 8192EE_TODO */ /* 8192EE_TODO */ /* update h/w index */ /* for tx side, if own bit is set in packet index n, host pointer (write pointer) point to index n + 1. */ /* be queue. */