XilinxProcessorIPLib/drivers/qspips/src/xqspips_options.c
int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
			 u8 DelayAfter, u8 DelayInit)
{
	u32 DelayRegister;

	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Do not allow the delays to change while a transfer is in
	 * progress. Not thread-safe.
	 */
	if (InstancePtr->IsBusy) {
		return XST_DEVICE_BUSY;
	}

	/* Shift, Mask and OR the values to build the register settings */
	DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT;
	DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT;
	DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT;
	DelayRegister |= (u32) DelayInit;

	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
			  XQSPIPS_DR_OFFSET, DelayRegister);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function sets the delay register for the QSPI device driver.
* The delay register controls the Delay Between Transfers, Delay After
* Transfers, and the Delay Initially. The default value is 0x0. The range of
* each delay value is 0-255.
*
* @param	InstancePtr is a pointer to the XQspiPs instance.
* @param	DelayNss is the delay to de-assert slave select between
*		two word transfers.
* @param	DelayBtwn is the delay between one Slave Select being
*		de-activated and the activation of another slave. The delay is
*		the number of master clock periods given by DelayBtwn + 2.
* @param	DelayAfter define the delay between the last bit of the current
*		byte transfer and the first bit of the next byte transfer.
*		The delay in number of master clock periods is given as:
*		CHPA=0:DelayInit+DelayAfter+3
*		CHPA=1:DelayAfter+1
* @param	DelayInit is the delay between asserting the slave select signal
*		and the first bit transfer. The delay int number of master clock
*		periods is DelayInit+1.
*
* @return
*		- XST_SUCCESS if delays are successfully set.
*		- XST_DEVICE_BUSY if the device is currently transferring data.
*		The transfer must complete or be aborted before setting options.
*
* @note		None.
*
******************************************************************************/
This function sets the delay register for the QSPI device driver.
The delay register controls the Delay Between Transfers, Delay After
Transfers, and the Delay Initially. The default value is 0x0. The range of
each delay value is 0-255.
This function sets the delay register for the QSPI device driver . The delay register controls the Delay Between Transfers Delay After Transfers and the Delay Initially . The default value is 0x0 . The range of each delay value is 0 - 255 .
int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
			 u8 DelayAfter, u8 DelayInit)
{
	u32 DelayRegister;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	if (InstancePtr->IsBusy) {
		return XST_DEVICE_BUSY;
	}
	DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT;
	DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT;
	DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT;
	DelayRegister |= (u32) DelayInit;
	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
			  XQSPIPS_DR_OFFSET, DelayRegister);
	return XST_SUCCESS;
}
int XQspiPs_SetDelays ( XQspiPs * InstancePtr , u8 DelayNss , u8 DelayBtwn , u8 DelayAfter , u8 DelayInit ) { u32 DelayRegister ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; if ( InstancePtr -> IsBusy ) { return XST_DEVICE_BUSY ; } DelayRegister = ( u32 ) DelayNss << XQSPIPS_DR_NSS_SHIFT ; DelayRegister |= ( u32 ) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT ; DelayRegister |= ( u32 ) DelayAfter << XQSPIPS_DR_AFTER_SHIFT ; DelayRegister |= ( u32 ) DelayInit ; XQspiPs_WriteReg ( InstancePtr -> Config . BaseAddress , XQSPIPS_DR_OFFSET , DelayRegister ) ; return XST_SUCCESS ; }
This function sets the delay register for the QSPI device driver.
This function sets the delay register for the QSPI device driver .
/*
	 * Do not allow the delays to change while a transfer is in
	 * progress. Not thread-safe.
	 */ /* Shift, Mask and OR the values to build the register settings */