XilinxProcessorIPLib/drivers/dp14txss/examples/src/pt_only/tx.c
void hpd_pulse_con(XDpTxSs *InstancePtr, XDpTxSs_MainStreamAttributes Msa[4])
{
	//who populates this data ?
	u8 lane0_sts = InstancePtr->UsrHpdPulseData.Lane0Sts;
	u8 lane2_sts = InstancePtr->UsrHpdPulseData.Lane2Sts;
	u8 laneAlignStatus = InstancePtr->UsrHpdPulseData.LaneAlignStatus;
	u8 bw_set = InstancePtr->UsrHpdPulseData.BwSet;
	u8 lane_set = InstancePtr->UsrHpdPulseData.LaneSet;

	u8 retrain_link=0;

	if (!XVidC_EdidIsHeaderValid(InstancePtr->UsrHpdEventData.EdidOrg)) {
		XDp_TxGetEdidBlock(DpTxSsInst.DpPtr,
				DpTxSsInst.UsrHpdEventData.EdidOrg, 0);
	}

	u8 checksumMatch = 0;
	while (checksumMatch == 0) {
		if (CalculateChecksum(DpTxSsInst.UsrHpdEventData.EdidOrg, 128)) {
			XDp_TxGetEdidBlock(DpTxSsInst.DpPtr,
					DpTxSsInst.UsrHpdEventData.EdidOrg,0);
			checksumMatch = 0;
		}else
			checksumMatch = 1;
		}

	lane_set = lane_set & 0x1F;
	bw_set = bw_set & 0x1F;
	laneAlignStatus = laneAlignStatus & 0x1;

	if(bw_set != XDP_TX_LINK_BW_SET_162GBPS
			&& bw_set != XDP_TX_LINK_BW_SET_270GBPS
			&& bw_set != XDP_TX_LINK_BW_SET_540GBPS
			&& bw_set != XDP_TX_LINK_BW_SET_810GBPS
			){
		//Not all MOnitors are capable of 1E
		bw_set = linkrate_tx_run;
		retrain_link = 1;
	}
	if(lane_set != XDP_TX_LANE_COUNT_SET_1
			&& lane_set != XDP_TX_LANE_COUNT_SET_2
			&& lane_set != XDP_TX_LANE_COUNT_SET_4){
		//Not all links are trained at 4
		lane_set = lanecount_tx_run;
		retrain_link = 1;
	}

	lane0_sts = lane0_sts & 0x77;
	lane2_sts = lane2_sts & 0x77;
	if (lane_set == XDP_TX_LANE_COUNT_SET_4) {
		if ((lane0_sts !=
				(XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_1_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_1_CE_DONE_MASK |
				XDP_DPCD_STATUS_LANE_1_SL_DONE_MASK)
				) || (lane2_sts !=
				(XDP_DPCD_STATUS_LANE_2_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_2_CE_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_2_SL_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_3_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_3_CE_DONE_MASK |
				XDP_DPCD_STATUS_LANE_3_SL_DONE_MASK)
				) || (laneAlignStatus != 1)) {
			retrain_link = 1;
		}
	} else if (lane_set == XDP_TX_LANE_COUNT_SET_2) {
		if ((lane0_sts !=
				(XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_1_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_1_CE_DONE_MASK |
				XDP_DPCD_STATUS_LANE_1_SL_DONE_MASK)
				) || (laneAlignStatus != 1)) {
			retrain_link = 1;
		}
	} else if (lane_set == XDP_TX_LANE_COUNT_SET_1) {
		lane0_sts = lane0_sts & 0x7;
		if ((lane0_sts !=
				(XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK |
				XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK)
				) || (laneAlignStatus != 1)) {
			retrain_link = 1;
		}
	}

	if (retrain_link == 1) {
//		sink_power_cycle();
		XDpTxSs_SetLinkRate(&DpTxSsInst, bw_set);
		XDpTxSs_SetLaneCount(&DpTxSsInst, lane_set);
//		XDpTxSs_Start(&DpTxSsInst);
		DpTxSubsystem_Start(&DpTxSsInst, Msa);
		i2s_started = 0;
	}

	/* Mask Unsued Interrupts
	 *
	 */
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_INTERRUPT_MASK, 0x0);
}
/*****************************************************************************/
/**
*
* This function is the main hpd pulse process.
*
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function is the main hpd pulse process.
This function is the main hpd pulse process .
void hpd_pulse_con(XDpTxSs *InstancePtr, XDpTxSs_MainStreamAttributes Msa[4])
{
	u8 lane0_sts = InstancePtr->UsrHpdPulseData.Lane0Sts;
	u8 lane2_sts = InstancePtr->UsrHpdPulseData.Lane2Sts;
	u8 laneAlignStatus = InstancePtr->UsrHpdPulseData.LaneAlignStatus;
	u8 bw_set = InstancePtr->UsrHpdPulseData.BwSet;
	u8 lane_set = InstancePtr->UsrHpdPulseData.LaneSet;
	u8 retrain_link=0;
	if (!XVidC_EdidIsHeaderValid(InstancePtr->UsrHpdEventData.EdidOrg)) {
		XDp_TxGetEdidBlock(DpTxSsInst.DpPtr,
				DpTxSsInst.UsrHpdEventData.EdidOrg, 0);
	}
	u8 checksumMatch = 0;
	while (checksumMatch == 0) {
		if (CalculateChecksum(DpTxSsInst.UsrHpdEventData.EdidOrg, 128)) {
			XDp_TxGetEdidBlock(DpTxSsInst.DpPtr,
					DpTxSsInst.UsrHpdEventData.EdidOrg,0);
			checksumMatch = 0;
		}else
			checksumMatch = 1;
		}
	lane_set = lane_set & 0x1F;
	bw_set = bw_set & 0x1F;
	laneAlignStatus = laneAlignStatus & 0x1;
	if(bw_set != XDP_TX_LINK_BW_SET_162GBPS
			&& bw_set != XDP_TX_LINK_BW_SET_270GBPS
			&& bw_set != XDP_TX_LINK_BW_SET_540GBPS
			&& bw_set != XDP_TX_LINK_BW_SET_810GBPS
			){
		bw_set = linkrate_tx_run;
		retrain_link = 1;
	}
	if(lane_set != XDP_TX_LANE_COUNT_SET_1
			&& lane_set != XDP_TX_LANE_COUNT_SET_2
			&& lane_set != XDP_TX_LANE_COUNT_SET_4){
		lane_set = lanecount_tx_run;
		retrain_link = 1;
	}
	lane0_sts = lane0_sts & 0x77;
	lane2_sts = lane2_sts & 0x77;
	if (lane_set == XDP_TX_LANE_COUNT_SET_4) {
		if ((lane0_sts !=
				(XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_1_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_1_CE_DONE_MASK |
				XDP_DPCD_STATUS_LANE_1_SL_DONE_MASK)
				) || (lane2_sts !=
				(XDP_DPCD_STATUS_LANE_2_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_2_CE_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_2_SL_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_3_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_3_CE_DONE_MASK |
				XDP_DPCD_STATUS_LANE_3_SL_DONE_MASK)
				) || (laneAlignStatus != 1)) {
			retrain_link = 1;
		}
	} else if (lane_set == XDP_TX_LANE_COUNT_SET_2) {
		if ((lane0_sts !=
				(XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_1_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_1_CE_DONE_MASK |
				XDP_DPCD_STATUS_LANE_1_SL_DONE_MASK)
				) || (laneAlignStatus != 1)) {
			retrain_link = 1;
		}
	} else if (lane_set == XDP_TX_LANE_COUNT_SET_1) {
		lane0_sts = lane0_sts & 0x7;
		if ((lane0_sts !=
				(XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK |
				   XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK |
				XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK)
				) || (laneAlignStatus != 1)) {
			retrain_link = 1;
		}
	}
	if (retrain_link == 1) {
		XDpTxSs_SetLinkRate(&DpTxSsInst, bw_set);
		XDpTxSs_SetLaneCount(&DpTxSsInst, lane_set);
		DpTxSubsystem_Start(&DpTxSsInst, Msa);
		i2s_started = 0;
	}
	XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,
			XDP_TX_INTERRUPT_MASK, 0x0);
}
void hpd_pulse_con ( XDpTxSs * InstancePtr , XDpTxSs_MainStreamAttributes Msa [ 4 ] ) { u8 lane0_sts = InstancePtr -> UsrHpdPulseData . Lane0Sts ; u8 lane2_sts = InstancePtr -> UsrHpdPulseData . Lane2Sts ; u8 laneAlignStatus = InstancePtr -> UsrHpdPulseData . LaneAlignStatus ; u8 bw_set = InstancePtr -> UsrHpdPulseData . BwSet ; u8 lane_set = InstancePtr -> UsrHpdPulseData . LaneSet ; u8 retrain_link = 0 ; if ( ! XVidC_EdidIsHeaderValid ( InstancePtr -> UsrHpdEventData . EdidOrg ) ) { XDp_TxGetEdidBlock ( DpTxSsInst . DpPtr , DpTxSsInst . UsrHpdEventData . EdidOrg , 0 ) ; } u8 checksumMatch = 0 ; while ( checksumMatch == 0 ) { if ( CalculateChecksum ( DpTxSsInst . UsrHpdEventData . EdidOrg , 128 ) ) { XDp_TxGetEdidBlock ( DpTxSsInst . DpPtr , DpTxSsInst . UsrHpdEventData . EdidOrg , 0 ) ; checksumMatch = 0 ; } else checksumMatch = 1 ; } lane_set = lane_set & 0x1F ; bw_set = bw_set & 0x1F ; laneAlignStatus = laneAlignStatus & 0x1 ; if ( bw_set != XDP_TX_LINK_BW_SET_162GBPS && bw_set != XDP_TX_LINK_BW_SET_270GBPS && bw_set != XDP_TX_LINK_BW_SET_540GBPS && bw_set != XDP_TX_LINK_BW_SET_810GBPS ) { bw_set = linkrate_tx_run ; retrain_link = 1 ; } if ( lane_set != XDP_TX_LANE_COUNT_SET_1 && lane_set != XDP_TX_LANE_COUNT_SET_2 && lane_set != XDP_TX_LANE_COUNT_SET_4 ) { lane_set = lanecount_tx_run ; retrain_link = 1 ; } lane0_sts = lane0_sts & 0x77 ; lane2_sts = lane2_sts & 0x77 ; if ( lane_set == XDP_TX_LANE_COUNT_SET_4 ) { if ( ( lane0_sts != ( XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK | XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK | XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK | XDP_DPCD_STATUS_LANE_1_CR_DONE_MASK | XDP_DPCD_STATUS_LANE_1_CE_DONE_MASK | XDP_DPCD_STATUS_LANE_1_SL_DONE_MASK ) ) || ( lane2_sts != ( XDP_DPCD_STATUS_LANE_2_CR_DONE_MASK | XDP_DPCD_STATUS_LANE_2_CE_DONE_MASK | XDP_DPCD_STATUS_LANE_2_SL_DONE_MASK | XDP_DPCD_STATUS_LANE_3_CR_DONE_MASK | XDP_DPCD_STATUS_LANE_3_CE_DONE_MASK | XDP_DPCD_STATUS_LANE_3_SL_DONE_MASK ) ) || ( laneAlignStatus != 1 ) ) { retrain_link = 1 ; } } else if ( lane_set == XDP_TX_LANE_COUNT_SET_2 ) { if ( ( lane0_sts != ( XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK | XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK | XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK | XDP_DPCD_STATUS_LANE_1_CR_DONE_MASK | XDP_DPCD_STATUS_LANE_1_CE_DONE_MASK | XDP_DPCD_STATUS_LANE_1_SL_DONE_MASK ) ) || ( laneAlignStatus != 1 ) ) { retrain_link = 1 ; } } else if ( lane_set == XDP_TX_LANE_COUNT_SET_1 ) { lane0_sts = lane0_sts & 0x7 ; if ( ( lane0_sts != ( XDP_DPCD_STATUS_LANE_0_CR_DONE_MASK | XDP_DPCD_STATUS_LANE_0_CE_DONE_MASK | XDP_DPCD_STATUS_LANE_0_SL_DONE_MASK ) ) || ( laneAlignStatus != 1 ) ) { retrain_link = 1 ; } } if ( retrain_link == 1 ) { XDpTxSs_SetLinkRate ( & DpTxSsInst , bw_set ) ; XDpTxSs_SetLaneCount ( & DpTxSsInst , lane_set ) ; DpTxSubsystem_Start ( & DpTxSsInst , Msa ) ; i2s_started = 0 ; } XDp_WriteReg ( DpTxSsInst . DpPtr -> Config . BaseAddr , XDP_TX_INTERRUPT_MASK , 0x0 ) ; }
This function is the main hpd pulse process.
This function is the main hpd pulse process .
//who populates this data ? //Not all MOnitors are capable of 1E //Not all links are trained at 4 //		sink_power_cycle(); //		XDpTxSs_Start(&DpTxSsInst); /* Mask Unsued Interrupts
	 *
	 */