XilinxProcessorIPLib/drivers/uartpsv/src/xuartpsv_intr.c
void XUartPsv_SetInterruptMask(XUartPsv *InstancePtr, u32 Mask)
{
	u32 TempMask = Mask;
	/* Assert validates the input arguments */
	Xil_AssertVoid(InstancePtr != NULL);

	TempMask &= (u32)XUARTPSV_UARTIMSC_MASK;

	/* Write the mask to the mask set/clear Register */
	XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTIMSC_OFFSET, TempMask);

}
/*****************************************************************************/
/**
*
* This function sets the interrupt mask.
*
* @param	InstancePtr is a pointer to the XUartPsv instance
* @param	Mask contains the interrupts to be enabled or disabled.
*		A '1' enables an interrupt, and a '0' disables.
*
* @return	None.
*
* @note 	None.
*
******************************************************************************/
This function sets the interrupt mask.
This function sets the interrupt mask .
void XUartPsv_SetInterruptMask(XUartPsv *InstancePtr, u32 Mask)
{
	u32 TempMask = Mask;
	Xil_AssertVoid(InstancePtr != NULL);
	TempMask &= (u32)XUARTPSV_UARTIMSC_MASK;
	XUartPsv_WriteReg(InstancePtr->Config.BaseAddress,
			XUARTPSV_UARTIMSC_OFFSET, TempMask);
}
void XUartPsv_SetInterruptMask ( XUartPsv * InstancePtr , u32 Mask ) { u32 TempMask = Mask ; Xil_AssertVoid ( InstancePtr != NULL ) ; TempMask &= ( u32 ) XUARTPSV_UARTIMSC_MASK ; XUartPsv_WriteReg ( InstancePtr -> Config . BaseAddress , XUARTPSV_UARTIMSC_OFFSET , TempMask ) ; }
This function sets the interrupt mask.
This function sets the interrupt mask .
/* Assert validates the input arguments */ /* Write the mask to the mask set/clear Register */