lib/sw_apps/zynqmp_pmufw/src/idle_hooks.c
void NodeGemIdle(u32 BaseAddress)
{
	u32 Reg;
	u32 Timeout = MAX_TIMEOUT;

	/* Make sure MDIO is in IDLE state */
	do {
		Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWSR_OFFSET);
	} while ((!(Reg & XEMACPS_NWSR_MDIOIDLE_MASK)) && --Timeout);

	if (Timeout == 0) {
		PmWarn("gem not idle\r\n");
	}

	/* Disable all interrupts */
	XEmacPs_WriteReg(BaseAddress, XEMACPS_IDR_OFFSET, XEMACPS_IXR_ALL_MASK);

	/* Halt the TX traffic */
	Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWCTRL_OFFSET);
	Reg |= XEMACPS_NWCTRL_HALTTX_MASK;
	XEmacPs_WriteReg(BaseAddress, XEMACPS_NWCTRL_OFFSET, Reg);

	/* Do not accept RX frames addressed to broadcast address */
	Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWCFG_OFFSET);
	Reg |= XEMACPS_NWCFG_BCASTDI_MASK;	/* No Broadcast bit */
	XEmacPs_WriteReg(BaseAddress, XEMACPS_NWCFG_OFFSET, Reg);

	/* Disable specific address filtering and thereby stop accept other RX frames */
	XEmacPs_WriteReg(BaseAddress, XEMACPS_LADDR1L_OFFSET, 0x0);
	XEmacPs_WriteReg(BaseAddress, XEMACPS_LADDR2L_OFFSET, 0x0);
	XEmacPs_WriteReg(BaseAddress, XEMACPS_LADDR3L_OFFSET, 0x0);
	XEmacPs_WriteReg(BaseAddress, XEMACPS_LADDR4L_OFFSET, 0x0);

	/*
	 * Check for the DMA stop. Poll on the current bd ptr and make sure it
	 * doesn't move for considerable time.
	 */
	/* Wait for TX DMA to stop */
	Timeout = DMA_STOP_TIMEOUT; /* Worst case timeout */
	do {
		Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_TXQBASE_OFFSET);
		usleep(REG_POLL_STATUS_DELAY);
	} while ((Reg != XEmacPs_ReadReg(BaseAddress, XEMACPS_TXQBASE_OFFSET)) && --Timeout);

	if (0 == Timeout) {
		PmWarn("GEM TX Not Idled\r\n");
	}

	/* Wait for RX DMA to stop */
	Timeout = DMA_STOP_TIMEOUT; /* Worst case timeout */
	do {
		Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_RXQBASE_OFFSET);
		usleep(REG_POLL_STATUS_DELAY);
	} while ((Reg != XEmacPs_ReadReg(BaseAddress, XEMACPS_RXQBASE_OFFSET)) && --Timeout);

	if (0 == Timeout) {
		PmWarn("GEM RX Not Idled\r\n");
	}

	/* Disable the receiver & transmitter */
	Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWCTRL_OFFSET);
	Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
	Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
	XEmacPs_WriteReg(BaseAddress, XEMACPS_NWCTRL_OFFSET, Reg);
}
/**
 * NodeGemIdle() - Custom code to idle the GEM
 *
 * @BaseAddress: GEM base address
 */
Custom code to idle the GEM
@BaseAddress: GEM base address
Custom code to idle the GEM @BaseAddress : GEM base address
void NodeGemIdle(u32 BaseAddress)
{
	u32 Reg;
	u32 Timeout = MAX_TIMEOUT;
	do {
		Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWSR_OFFSET);
	} while ((!(Reg & XEMACPS_NWSR_MDIOIDLE_MASK)) && --Timeout);
	if (Timeout == 0) {
		PmWarn("gem not idle\r\n");
	}
	XEmacPs_WriteReg(BaseAddress, XEMACPS_IDR_OFFSET, XEMACPS_IXR_ALL_MASK);
	Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWCTRL_OFFSET);
	Reg |= XEMACPS_NWCTRL_HALTTX_MASK;
	XEmacPs_WriteReg(BaseAddress, XEMACPS_NWCTRL_OFFSET, Reg);
	Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWCFG_OFFSET);
	Reg |= XEMACPS_NWCFG_BCASTDI_MASK;	
	XEmacPs_WriteReg(BaseAddress, XEMACPS_NWCFG_OFFSET, Reg);
	XEmacPs_WriteReg(BaseAddress, XEMACPS_LADDR1L_OFFSET, 0x0);
	XEmacPs_WriteReg(BaseAddress, XEMACPS_LADDR2L_OFFSET, 0x0);
	XEmacPs_WriteReg(BaseAddress, XEMACPS_LADDR3L_OFFSET, 0x0);
	XEmacPs_WriteReg(BaseAddress, XEMACPS_LADDR4L_OFFSET, 0x0);
	Timeout = DMA_STOP_TIMEOUT; 
	do {
		Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_TXQBASE_OFFSET);
		usleep(REG_POLL_STATUS_DELAY);
	} while ((Reg != XEmacPs_ReadReg(BaseAddress, XEMACPS_TXQBASE_OFFSET)) && --Timeout);
	if (0 == Timeout) {
		PmWarn("GEM TX Not Idled\r\n");
	}
	Timeout = DMA_STOP_TIMEOUT; 
	do {
		Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_RXQBASE_OFFSET);
		usleep(REG_POLL_STATUS_DELAY);
	} while ((Reg != XEmacPs_ReadReg(BaseAddress, XEMACPS_RXQBASE_OFFSET)) && --Timeout);
	if (0 == Timeout) {
		PmWarn("GEM RX Not Idled\r\n");
	}
	Reg = XEmacPs_ReadReg(BaseAddress, XEMACPS_NWCTRL_OFFSET);
	Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
	Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
	XEmacPs_WriteReg(BaseAddress, XEMACPS_NWCTRL_OFFSET, Reg);
}
void NodeGemIdle ( u32 BaseAddress ) { u32 Reg ; u32 Timeout = MAX_TIMEOUT ; do { Reg = XEmacPs_ReadReg ( BaseAddress , XEMACPS_NWSR_OFFSET ) ; } while ( ( ! ( Reg & XEMACPS_NWSR_MDIOIDLE_MASK ) ) && -- Timeout ) ; if ( Timeout == 0 ) { PmWarn ( " \r \n " ) ; } XEmacPs_WriteReg ( BaseAddress , XEMACPS_IDR_OFFSET , XEMACPS_IXR_ALL_MASK ) ; Reg = XEmacPs_ReadReg ( BaseAddress , XEMACPS_NWCTRL_OFFSET ) ; Reg |= XEMACPS_NWCTRL_HALTTX_MASK ; XEmacPs_WriteReg ( BaseAddress , XEMACPS_NWCTRL_OFFSET , Reg ) ; Reg = XEmacPs_ReadReg ( BaseAddress , XEMACPS_NWCFG_OFFSET ) ; Reg |= XEMACPS_NWCFG_BCASTDI_MASK ; XEmacPs_WriteReg ( BaseAddress , XEMACPS_NWCFG_OFFSET , Reg ) ; XEmacPs_WriteReg ( BaseAddress , XEMACPS_LADDR1L_OFFSET , 0x0 ) ; XEmacPs_WriteReg ( BaseAddress , XEMACPS_LADDR2L_OFFSET , 0x0 ) ; XEmacPs_WriteReg ( BaseAddress , XEMACPS_LADDR3L_OFFSET , 0x0 ) ; XEmacPs_WriteReg ( BaseAddress , XEMACPS_LADDR4L_OFFSET , 0x0 ) ; Timeout = DMA_STOP_TIMEOUT ; do { Reg = XEmacPs_ReadReg ( BaseAddress , XEMACPS_TXQBASE_OFFSET ) ; usleep ( REG_POLL_STATUS_DELAY ) ; } while ( ( Reg != XEmacPs_ReadReg ( BaseAddress , XEMACPS_TXQBASE_OFFSET ) ) && -- Timeout ) ; if ( 0 == Timeout ) { PmWarn ( " \r \n " ) ; } Timeout = DMA_STOP_TIMEOUT ; do { Reg = XEmacPs_ReadReg ( BaseAddress , XEMACPS_RXQBASE_OFFSET ) ; usleep ( REG_POLL_STATUS_DELAY ) ; } while ( ( Reg != XEmacPs_ReadReg ( BaseAddress , XEMACPS_RXQBASE_OFFSET ) ) && -- Timeout ) ; if ( 0 == Timeout ) { PmWarn ( " \r \n " ) ; } Reg = XEmacPs_ReadReg ( BaseAddress , XEMACPS_NWCTRL_OFFSET ) ; Reg &= ( u32 ) ( ~ XEMACPS_NWCTRL_RXEN_MASK ) ; Reg &= ( u32 ) ( ~ XEMACPS_NWCTRL_TXEN_MASK ) ; XEmacPs_WriteReg ( BaseAddress , XEMACPS_NWCTRL_OFFSET , Reg ) ; }
NodeGemIdle() - Custom code to idle the GEM
 @BaseAddress: GEM base address
NodeGemIdle () - Custom code to idle the GEM @BaseAddress : GEM base address
/* Make sure MDIO is in IDLE state */ /* Disable all interrupts */ /* Halt the TX traffic */ /* Do not accept RX frames addressed to broadcast address */ /* No Broadcast bit */ /* Disable specific address filtering and thereby stop accept other RX frames */ /*
	 * Check for the DMA stop. Poll on the current bd ptr and make sure it
	 * doesn't move for considerable time.
	 */ /* Wait for TX DMA to stop */ /* Worst case timeout */ /* Wait for RX DMA to stop */ /* Worst case timeout */ /* Disable the receiver & transmitter */