src/dpdk/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c
static int
nfp_enable_bars(struct nfp_pcie_user *nfp)
{
	struct nfp_bar *bar;
	int x, start, end;

	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
		start = 4;
		end = 1;
	} else {
		start = 7;
		end = 4;
	}
	for (x = start; x > end; x--) {
		bar = &nfp->bar[x - 1];
		bar->barcfg = 0;
		bar->nfp = nfp;
		bar->index = x;
		bar->mask = (1 << (nfp->barsz - 3)) - 1;
		bar->bitsize = nfp->barsz - 3;
		bar->base = 0;
		bar->iomem = NULL;
		bar->lock = 0;
		bar->csr = nfp->cfg +
			   NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(bar->index >> 3,
							   bar->index & 7);

		bar->iomem = nfp->cfg + (bar->index << bar->bitsize);
	}
	return 0;
}
/*
 * Map all PCI bars. We assume that the BAR with the PCIe config block is
 * already mapped.
 *
 * BAR0.0: Reserved for General Mapping (for MSI-X access to PCIe SRAM)
 *
 *         Halving PCItoCPPBars for primary and secondary processes.
 *         NFP PMD just requires two fixed slots, one for configuration BAR,
 *         and another for accessing the hw queues. Another slot is needed
 *         for setting the link up or down. Secondary processes do not need
 *         to map the first two slots again, but it requires one slot for
 *         accessing the link, even if it is not likely the secondary process
 *         starting the port. This implies a limit of secondary processes
 *         supported. Due to this requirement and future extensions requiring
 *         new slots per process, only one secondary process is supported by
 *         now.
 */
Map all PCI bars. We assume that the BAR with the PCIe config block is
already mapped.

BAR0.0: Reserved for General Mapping (for MSI-X access to PCIe SRAM)

Halving PCItoCPPBars for primary and secondary processes.
NFP PMD just requires two fixed slots, one for configuration BAR,
and another for accessing the hw queues. Another slot is needed
for setting the link up or down. Secondary processes do not need
to map the first two slots again, but it requires one slot for
accessing the link, even if it is not likely the secondary process
starting the port. This implies a limit of secondary processes
supported. Due to this requirement and future extensions requiring
new slots per process, only one secondary process is supported by
now.
Map all PCI bars . We assume that the BAR with the PCIe config block is already mapped . BAR0 . 0 : Reserved for General Mapping ( for MSI - X access to PCIe SRAM ) Halving PCItoCPPBars for primary and secondary processes . NFP PMD just requires two fixed slots one for configuration BAR and another for accessing the hw queues . Another slot is needed for setting the link up or down . Secondary processes do not need to map the first two slots again but it requires one slot for accessing the link even if it is not likely the secondary process starting the port . This implies a limit of secondary processes supported . Due to this requirement and future extensions requiring new slots per process only one secondary process is supported by now .
static int
nfp_enable_bars(struct nfp_pcie_user *nfp)
{
	struct nfp_bar *bar;
	int x, start, end;
	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
		start = 4;
		end = 1;
	} else {
		start = 7;
		end = 4;
	}
	for (x = start; x > end; x--) {
		bar = &nfp->bar[x - 1];
		bar->barcfg = 0;
		bar->nfp = nfp;
		bar->index = x;
		bar->mask = (1 << (nfp->barsz - 3)) - 1;
		bar->bitsize = nfp->barsz - 3;
		bar->base = 0;
		bar->iomem = NULL;
		bar->lock = 0;
		bar->csr = nfp->cfg +
			   NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(bar->index >> 3,
							   bar->index & 7);
		bar->iomem = nfp->cfg + (bar->index << bar->bitsize);
	}
	return 0;
}
static int nfp_enable_bars ( struct nfp_pcie_user * nfp ) { struct nfp_bar * bar ; int x , start , end ; if ( rte_eal_process_type ( ) == RTE_PROC_PRIMARY ) { start = 4 ; end = 1 ; } else { start = 7 ; end = 4 ; } for ( x = start ; x > end ; x -- ) { bar = & nfp -> bar [ x - 1 ] ; bar -> barcfg = 0 ; bar -> nfp = nfp ; bar -> index = x ; bar -> mask = ( 1 << ( nfp -> barsz - 3 ) ) - 1 ; bar -> bitsize = nfp -> barsz - 3 ; bar -> base = 0 ; bar -> iomem = NULL ; bar -> lock = 0 ; bar -> csr = nfp -> cfg + NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR ( bar -> index >> 3 , bar -> index & 7 ) ; bar -> iomem = nfp -> cfg + ( bar -> index << bar -> bitsize ) ; } return 0 ; }
Map all PCI bars.
Map all PCI bars .