XilinxProcessorIPLib/drivers/axiethernet/examples/xaxiethernet_example_polled.c
int AxiEthernetMultipleFramesPolledExample(void)
{
	u32 FramesToLoopback;
	u32 PayloadSize;
	u32 TxFrameLength;
	u32 RxFrameLength;
	u32 FifoFreeBytes;
	u32 Index;

	/*
	 * Start the Axi Ethernet device
	 */
	XAxiEthernet_Start(&AxiEthernetInstance);

	/*
	 * Setup the number of frames to loopback (FramesToLoopback) and the
	 * size of the frame (PayloadSize) to loopback. The default settings
	 * should work for every case. Modifying the settings can cause
	 * problems, see discussion below:
	 *
	 * If PayloadSize is set small and FramesToLoopback high, then it is
	 * possible to cause the transmit status FIFO to overflow.
	 *
	 * If PayloadSize is set large and FramesToLoopback high, then it is
	 * possible to cause the transmit packet FIFO to overflow.
	 *
	 * Either of these scenarios may be worth trying out to observe how
	 * the driver reacts. The exact values to cause these types of errors
	 * will vary due to the sizes of the FIFOs selected at hardware build
	 * time. But the following settings should create problems for all
	 * FIFO sizes:
	 *
	 * Transmit status FIFO overflow
	 *    PayloadSize = 1
	 *    FramesToLoopback = 1000
	 *
	 * Transmit packet FIFO overflow
	 *    PayloadSize = 1500
	 *    FramesToLoopback = 16
	 *
	 * These values should always work without error
	 *    PayloadSize = 100
	 *    FramesToLoopback = 5
	 */
	PayloadSize = 100;
	FramesToLoopback = 5;

	/*
	 * Calculate Tx frame length (not including FCS)
	 */
	TxFrameLength = XAE_HDR_SIZE + PayloadSize;

	/*
	 * Setup the packet to be transmitted
	 */
	AxiEthernetUtilFrameHdrFormatMAC(&TxFrame, AxiEthernetMAC);
	AxiEthernetUtilFrameHdrFormatType(&TxFrame, PayloadSize);
	AxiEthernetUtilFrameSetPayloadData(&TxFrame, PayloadSize);

	/****************/
	/* Send packets */
	/****************/

	/*
	 * Since we may be interested to see what happens when FIFOs overflow,
	 * don't check for room in the transmit packet FIFO prior to writing
	 * to it.
	 */

	/*
	 * Write frame data to FIFO
	 * Fifo core only allows loading and sending one frame at a time.
	 */
	for (Index = 0; Index < FramesToLoopback; Index++) {
		/* Make sure there is room in the FIFO */
		do {
			FifoFreeBytes = XLlFifo_TxVacancy(&FifoInstance);
		} while (FifoFreeBytes < TxFrameLength);

		XLlFifo_Write(&FifoInstance, TxFrame, TxFrameLength);
		XLlFifo_TxSetLen(&FifoInstance, TxFrameLength);

		switch (AxiEthernetPollForTxStatus()) {
		case XST_SUCCESS:	/* Got a successful transmit status */
			break;

		case XST_NO_DATA:	/* Timed out */
			AxiEthernetUtilErrorTrap("Tx timeout");
			return XST_FAILURE;
			break;

		default:	/* Some other error */
			AxiEthernetResetDevice();
			return XST_FAILURE;
		}
	}

	/**********************/
	/* Receive the packet */
	/**********************/

	/*
	 * Wait for the packets to arrive
	 * The Fifo core only allows us to pull out one frame at a time.
	 */
	for (Index = 0; Index < FramesToLoopback; ) {
		/*
		 * Wait for packet Rx
		 */
		switch (AxiEthernetPollForRxStatus()) {
		case XST_SUCCESS:	/* Got a successful receive status */
			break;

		case XST_NO_DATA:	/* Timed out */
			AxiEthernetUtilErrorTrap("Rx timeout");
			return XST_FAILURE;
			break;

		default:	/* Some other error */
			AxiEthernetResetDevice();
			return XST_FAILURE;
		}

		while(XLlFifo_RxOccupancy(&FifoInstance)) {
			/*
			 * A packet has arrived, get its length
			 */
			RxFrameLength = XLlFifo_RxGetLen(&FifoInstance);

			/*
			 * Verify the received frame length
			 */
			if ((RxFrameLength) != TxFrameLength) {
				AxiEthernetUtilErrorTrap("Receive length incorrect");
				return XST_FAILURE;
			}
			/*
			 * Read the received packet data
			 */
			XLlFifo_Read(&FifoInstance, &RxFrame, RxFrameLength);

			if (AxiEthernetUtilFrameVerify
						(&TxFrame, &RxFrame) != 0) {
				AxiEthernetUtilErrorTrap("Receive Data Mismatch");
				return XST_FAILURE;
			}

			Index++;
		}
	}

	/*
	 * Stop device
	 */
	XAxiEthernet_Stop(&AxiEthernetInstance);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This example uses polled mode to queue up multiple frames in the packet
* FIFOs before sending them in a single burst. Receive packets are handled in
* a similar way.
*
* @param	None.
*
* @return	-XST_SUCCESS to indicate success
*		-XST_FAILURE to indicate failure
*
* @note		None.
*
******************************************************************************/
This example uses polled mode to queue up multiple frames in the packet
FIFOs before sending them in a single burst. Receive packets are handled in
a similar way.
This example uses polled mode to queue up multiple frames in the packet FIFOs before sending them in a single burst . Receive packets are handled in a similar way .
int AxiEthernetMultipleFramesPolledExample(void)
{
	u32 FramesToLoopback;
	u32 PayloadSize;
	u32 TxFrameLength;
	u32 RxFrameLength;
	u32 FifoFreeBytes;
	u32 Index;
	XAxiEthernet_Start(&AxiEthernetInstance);
	PayloadSize = 100;
	FramesToLoopback = 5;
	TxFrameLength = XAE_HDR_SIZE + PayloadSize;
	AxiEthernetUtilFrameHdrFormatMAC(&TxFrame, AxiEthernetMAC);
	AxiEthernetUtilFrameHdrFormatType(&TxFrame, PayloadSize);
	AxiEthernetUtilFrameSetPayloadData(&TxFrame, PayloadSize);
	for (Index = 0; Index < FramesToLoopback; Index++) {
		do {
			FifoFreeBytes = XLlFifo_TxVacancy(&FifoInstance);
		} while (FifoFreeBytes < TxFrameLength);
		XLlFifo_Write(&FifoInstance, TxFrame, TxFrameLength);
		XLlFifo_TxSetLen(&FifoInstance, TxFrameLength);
		switch (AxiEthernetPollForTxStatus()) {
		case XST_SUCCESS:	
			break;
		case XST_NO_DATA:	
			AxiEthernetUtilErrorTrap("Tx timeout");
			return XST_FAILURE;
			break;
		default:	
			AxiEthernetResetDevice();
			return XST_FAILURE;
		}
	}
	for (Index = 0; Index < FramesToLoopback; ) {
		switch (AxiEthernetPollForRxStatus()) {
		case XST_SUCCESS:	
			break;
		case XST_NO_DATA:	
			AxiEthernetUtilErrorTrap("Rx timeout");
			return XST_FAILURE;
			break;
		default:	
			AxiEthernetResetDevice();
			return XST_FAILURE;
		}
		while(XLlFifo_RxOccupancy(&FifoInstance)) {
			RxFrameLength = XLlFifo_RxGetLen(&FifoInstance);
			if ((RxFrameLength) != TxFrameLength) {
				AxiEthernetUtilErrorTrap("Receive length incorrect");
				return XST_FAILURE;
			}
			XLlFifo_Read(&FifoInstance, &RxFrame, RxFrameLength);
			if (AxiEthernetUtilFrameVerify
						(&TxFrame, &RxFrame) != 0) {
				AxiEthernetUtilErrorTrap("Receive Data Mismatch");
				return XST_FAILURE;
			}
			Index++;
		}
	}
	XAxiEthernet_Stop(&AxiEthernetInstance);
	return XST_SUCCESS;
}
int AxiEthernetMultipleFramesPolledExample ( void ) { u32 FramesToLoopback ; u32 PayloadSize ; u32 TxFrameLength ; u32 RxFrameLength ; u32 FifoFreeBytes ; u32 Index ; XAxiEthernet_Start ( & AxiEthernetInstance ) ; PayloadSize = 100 ; FramesToLoopback = 5 ; TxFrameLength = XAE_HDR_SIZE + PayloadSize ; AxiEthernetUtilFrameHdrFormatMAC ( & TxFrame , AxiEthernetMAC ) ; AxiEthernetUtilFrameHdrFormatType ( & TxFrame , PayloadSize ) ; AxiEthernetUtilFrameSetPayloadData ( & TxFrame , PayloadSize ) ; for ( Index = 0 ; Index < FramesToLoopback ; Index ++ ) { do { FifoFreeBytes = XLlFifo_TxVacancy ( & FifoInstance ) ; } while ( FifoFreeBytes < TxFrameLength ) ; XLlFifo_Write ( & FifoInstance , TxFrame , TxFrameLength ) ; XLlFifo_TxSetLen ( & FifoInstance , TxFrameLength ) ; switch ( AxiEthernetPollForTxStatus ( ) ) { case XST_SUCCESS : break ; case XST_NO_DATA : AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; break ; default : AxiEthernetResetDevice ( ) ; return XST_FAILURE ; } } for ( Index = 0 ; Index < FramesToLoopback ; ) { switch ( AxiEthernetPollForRxStatus ( ) ) { case XST_SUCCESS : break ; case XST_NO_DATA : AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; break ; default : AxiEthernetResetDevice ( ) ; return XST_FAILURE ; } while ( XLlFifo_RxOccupancy ( & FifoInstance ) ) { RxFrameLength = XLlFifo_RxGetLen ( & FifoInstance ) ; if ( ( RxFrameLength ) != TxFrameLength ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } XLlFifo_Read ( & FifoInstance , & RxFrame , RxFrameLength ) ; if ( AxiEthernetUtilFrameVerify ( & TxFrame , & RxFrame ) != 0 ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } Index ++ ; } } XAxiEthernet_Stop ( & AxiEthernetInstance ) ; return XST_SUCCESS ; }
This example uses polled mode to queue up multiple frames in the packet
FIFOs before sending them in a single burst.
This example uses polled mode to queue up multiple frames in the packet FIFOs before sending them in a single burst .
/*
	 * Start the Axi Ethernet device
	 */ /*
	 * Setup the number of frames to loopback (FramesToLoopback) and the
	 * size of the frame (PayloadSize) to loopback. The default settings
	 * should work for every case. Modifying the settings can cause
	 * problems, see discussion below:
	 *
	 * If PayloadSize is set small and FramesToLoopback high, then it is
	 * possible to cause the transmit status FIFO to overflow.
	 *
	 * If PayloadSize is set large and FramesToLoopback high, then it is
	 * possible to cause the transmit packet FIFO to overflow.
	 *
	 * Either of these scenarios may be worth trying out to observe how
	 * the driver reacts. The exact values to cause these types of errors
	 * will vary due to the sizes of the FIFOs selected at hardware build
	 * time. But the following settings should create problems for all
	 * FIFO sizes:
	 *
	 * Transmit status FIFO overflow
	 *    PayloadSize = 1
	 *    FramesToLoopback = 1000
	 *
	 * Transmit packet FIFO overflow
	 *    PayloadSize = 1500
	 *    FramesToLoopback = 16
	 *
	 * These values should always work without error
	 *    PayloadSize = 100
	 *    FramesToLoopback = 5
	 */ /*
	 * Calculate Tx frame length (not including FCS)
	 */ /*
	 * Setup the packet to be transmitted
	 */ /****************/ /* Send packets */ /****************/ /*
	 * Since we may be interested to see what happens when FIFOs overflow,
	 * don't check for room in the transmit packet FIFO prior to writing
	 * to it.
	 */ /*
	 * Write frame data to FIFO
	 * Fifo core only allows loading and sending one frame at a time.
	 */ /* Make sure there is room in the FIFO */ /* Got a successful transmit status */ /* Timed out */ /* Some other error */ /**********************/ /* Receive the packet */ /**********************/ /*
	 * Wait for the packets to arrive
	 * The Fifo core only allows us to pull out one frame at a time.
	 */ /*
		 * Wait for packet Rx
		 */ /* Got a successful receive status */ /* Timed out */ /* Some other error */ /*
			 * A packet has arrived, get its length
			 */ /*
			 * Verify the received frame length
			 */ /*
			 * Read the received packet data
			 */ /*
	 * Stop device
	 */