src/dpdk/drivers/net/cxgbe/base/t4_hw.c
int t4_fl_pkt_align(struct adapter *adap)
{
	u32 sge_control, sge_control2;
	unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;

	sge_control = t4_read_reg(adap, A_SGE_CONTROL);

	/* T4 uses a single control field to specify both the PCIe Padding and
	 * Packing Boundary.  T5 introduced the ability to specify these
	 * separately.  The actual Ingress Packet Data alignment boundary
	 * within Packed Buffer Mode is the maximum of these two
	 * specifications.
	 */
	if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
		ingpad_shift = X_INGPADBOUNDARY_SHIFT;
	else
		ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;

	ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);

	fl_align = ingpadboundary;
	if (!is_t4(adap->params.chip)) {
		sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
		ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
		if (ingpackboundary == X_INGPACKBOUNDARY_16B)
			ingpackboundary = 16;
		else
			ingpackboundary = 1 << (ingpackboundary +
					X_INGPACKBOUNDARY_SHIFT);

		fl_align = max(ingpadboundary, ingpackboundary);
	}
	return fl_align;
}
/**
 * t4_fl_pkt_align - return the fl packet alignment
 * @adap: the adapter
 *
 * T4 has a single field to specify the packing and padding boundary.
 * T5 onwards has separate fields for this and hence the alignment for
 * next packet offset is maximum of these two.
 */
return the fl packet alignment
@adap: the adapter

T4 has a single field to specify the packing and padding boundary.
T5 onwards has separate fields for this and hence the alignment for
next packet offset is maximum of these two.
return the fl packet alignment @adap : the adapter T4 has a single field to specify the packing and padding boundary . T5 onwards has separate fields for this and hence the alignment for next packet offset is maximum of these two .
int t4_fl_pkt_align(struct adapter *adap)
{
	u32 sge_control, sge_control2;
	unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
	sge_control = t4_read_reg(adap, A_SGE_CONTROL);
	if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
		ingpad_shift = X_INGPADBOUNDARY_SHIFT;
	else
		ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
	ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
	fl_align = ingpadboundary;
	if (!is_t4(adap->params.chip)) {
		sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
		ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
		if (ingpackboundary == X_INGPACKBOUNDARY_16B)
			ingpackboundary = 16;
		else
			ingpackboundary = 1 << (ingpackboundary +
					X_INGPACKBOUNDARY_SHIFT);
		fl_align = max(ingpadboundary, ingpackboundary);
	}
	return fl_align;
}
int t4_fl_pkt_align ( struct adapter * adap ) { u32 sge_control , sge_control2 ; unsigned int ingpadboundary , ingpackboundary , fl_align , ingpad_shift ; sge_control = t4_read_reg ( adap , A_SGE_CONTROL ) ; if ( CHELSIO_CHIP_VERSION ( adap -> params . chip ) <= CHELSIO_T5 ) ingpad_shift = X_INGPADBOUNDARY_SHIFT ; else ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT ; ingpadboundary = 1 << ( G_INGPADBOUNDARY ( sge_control ) + ingpad_shift ) ; fl_align = ingpadboundary ; if ( ! is_t4 ( adap -> params . chip ) ) { sge_control2 = t4_read_reg ( adap , A_SGE_CONTROL2 ) ; ingpackboundary = G_INGPACKBOUNDARY ( sge_control2 ) ; if ( ingpackboundary == X_INGPACKBOUNDARY_16B ) ingpackboundary = 16 ; else ingpackboundary = 1 << ( ingpackboundary + X_INGPACKBOUNDARY_SHIFT ) ; fl_align = max ( ingpadboundary , ingpackboundary ) ; } return fl_align ; }
t4_fl_pkt_align - return the fl packet alignment
 @adap: the adapter
t4_fl_pkt_align - return the fl packet alignment @adap : the adapter
/* T4 uses a single control field to specify both the PCIe Padding and
	 * Packing Boundary.  T5 introduced the ability to specify these
	 * separately.  The actual Ingress Packet Data alignment boundary
	 * within Packed Buffer Mode is the maximum of these two
	 * specifications.
	 */