lib/sw_apps/zynqmp_pmufw/src/pm_proc.c
static s32 PmProcTrSleepToActive(PmProc* const proc)
{
	s32 status;

	PmInfo("%s sleep->active\r\n", proc->node.name);
	status = PmProcWake(proc);
	DISABLE_WAKE(proc->mask);

	return status;
}
/**
 * PmProcTrSleepToActive() - FSM transition from sleep to active state
 * @proc    Pointer to processor whose FSM is changing state
 *
 * @return  Operation status
 *
 * @note    Processor had previously called self suspend and before it had
 *          executed wfi PMU has received PM API request to force power down
 *          of this processor. Therefore, PMU does not wait for wfi interrupt
 *          from this processor to come, but puts it to sleep.
 */
FSM transition from sleep to active state
@proc    Pointer to processor whose FSM is changing state

@return  Operation status

@note    Processor had previously called self suspend and before it had
executed wfi PMU has received PM API request to force power down
of this processor. Therefore, PMU does not wait for wfi interrupt
from this processor to come, but puts it to sleep.
FSM transition from sleep to active state @proc Pointer to processor whose FSM is changing state @return Operation status @note Processor had previously called self suspend and before it had executed wfi PMU has received PM API request to force power down of this processor . Therefore PMU does not wait for wfi interrupt from this processor to come but puts it to sleep .
static s32 PmProcTrSleepToActive(PmProc* const proc)
{
	s32 status;
	PmInfo("%s sleep->active\r\n", proc->node.name);
	status = PmProcWake(proc);
	DISABLE_WAKE(proc->mask);
	return status;
}
static s32 PmProcTrSleepToActive ( PmProc * const proc ) { s32 status ; PmInfo ( " \r \n " , proc -> node . name ) ; status = PmProcWake ( proc ) ; DISABLE_WAKE ( proc -> mask ) ; return status ; }
PmProcTrSleepToActive() - FSM transition from sleep to active state
 @proc    Pointer to processor whose FSM is changing state
PmProcTrSleepToActive () - FSM transition from sleep to active state @proc Pointer to processor whose FSM is changing state