XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1.c
u32 XHdmiphy1_DrpWr(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, u16 Addr, u16 Val)
{
	return XHdmiphy1_DrpAccess(InstancePtr, QuadId, ChId,
			XHDMIPHY1_DIR_TX, /* Write. */
			Addr, &Val);
}
/*****************************************************************************/
/**
* This function will initiate a write DRP transaction. It is a wrapper around
* XHdmiphy1_DrpAccess.
*
* @param	InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID on which to direct the DRP access.
* @param	Addr is the DRP address to issue the DRP access to.
* @param	Val is the value to write to the DRP address.
*
* @return
*		- XST_SUCCESS if the DRP access was successful.
*		- XST_FAILURE otherwise, if the busy bit did not go low, or if
*		  the ready bit did not go high.
*
* @note		None.
*
******************************************************************************/
This function will initiate a write DRP transaction. It is a wrapper around
XHdmiphy1_DrpAccess.
This function will initiate a write DRP transaction . It is a wrapper around XHdmiphy1_DrpAccess .
u32 XHdmiphy1_DrpWr(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, u16 Addr, u16 Val)
{
	return XHdmiphy1_DrpAccess(InstancePtr, QuadId, ChId,
			XHDMIPHY1_DIR_TX, 
			Addr, &Val);
}
u32 XHdmiphy1_DrpWr ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId , u16 Addr , u16 Val ) { return XHdmiphy1_DrpAccess ( InstancePtr , QuadId , ChId , XHDMIPHY1_DIR_TX , Addr , & Val ) ; }
This function will initiate a write DRP transaction.
This function will initiate a write DRP transaction .
/* Write. */