XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe4.c
u32 XVphy_Gthe4ClkChReconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId ChId)
{
	u16 DrpVal;
	u16 WriteVal;
	u32 CpllxVcoRateMHz;
    u32 Status = XST_SUCCESS;

	/* Obtain current DRP register value for PLL dividers. */
	Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x28, &DrpVal);
	/* Mask out clock divider bits. */
	DrpVal &= ~(0xFF80);
	/* Set CPLL_FBDIV. */
	WriteVal = (XVphy_NToDrpEncoding(InstancePtr, QuadId, ChId, 2) & 0xFF);
	DrpVal |= (WriteVal << 8);
	/* Set CPLL_FBDIV_45. */
	WriteVal = (XVphy_NToDrpEncoding(InstancePtr, QuadId, ChId, 1) & 0x1);
	DrpVal |= (WriteVal << 7);
	/* Write new DRP register value for PLL dividers. */
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x28, DrpVal);

	/* Write CPLL Ref Clk Div. */
	Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x2A, &DrpVal);
	/* Mask out clock divider bits. */
	DrpVal &= ~(0xF800);
	/* Set CPLL_REFCLKDIV. */
	WriteVal = (XVphy_MToDrpEncoding(InstancePtr, QuadId, ChId) & 0x1F);
	DrpVal |= (WriteVal << 11);
	/* Write new DRP register value for PLL dividers. */
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x2A, DrpVal);

	CpllxVcoRateMHz = XVphy_GetPllVcoFreqHz(InstancePtr, QuadId, ChId,
			XVphy_IsTxUsingCpll(InstancePtr, QuadId, ChId) ?
					XVPHY_DIR_TX : XVPHY_DIR_RX) / 1000000;

	/* CPLL_CFG0 */
	if (CpllxVcoRateMHz <= 3000) {
		DrpVal = 0x01FA;
	}
	else if (CpllxVcoRateMHz <= 4250) {
		DrpVal = 0x0FFA;
	}
	else {
		DrpVal = 0x03FE;
	}
	/* Write new DRP register value for CPLL_CFG0. */
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xCB, DrpVal);

	/* CPLL_CFG1 */
	if (CpllxVcoRateMHz <= 3000) {
		DrpVal = 0x0023;
	}
	else {
		DrpVal = 0x0021;
	}
	/* Write new DRP register value for CPLL_CFG1. */
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xCC, DrpVal);

	/* CPLL_CFG2 */
	if (CpllxVcoRateMHz <= 3000) {
		DrpVal = 0x0002;
	}
	else if (CpllxVcoRateMHz <= 4250) {
		DrpVal = 0x0202;
	}
	else {
		DrpVal = 0x0203;
	}
	/* Write new DRP register value for CPLL_CFG2. */
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xBC, DrpVal);

	/* Configure CPLL Calibration Registers */
	XVphy_CfgCpllCalPeriodandTol(InstancePtr, QuadId, ChId,
			(XVphy_IsTxUsingCpll(InstancePtr, QuadId, ChId) ?
								XVPHY_DIR_TX : XVPHY_DIR_RX),
			InstancePtr->Config.DrpClkFreq);

	return Status;
}
/*****************************************************************************/
/**
* This function will configure the channel clock settings.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
*
* @return
*		- XST_SUCCESS if the configuration was successful.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function will configure the channel clock settings.
This function will configure the channel clock settings .
u32 XVphy_Gthe4ClkChReconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId ChId)
{
	u16 DrpVal;
	u16 WriteVal;
	u32 CpllxVcoRateMHz;
    u32 Status = XST_SUCCESS;
	Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x28, &DrpVal);
	DrpVal &= ~(0xFF80);
	WriteVal = (XVphy_NToDrpEncoding(InstancePtr, QuadId, ChId, 2) & 0xFF);
	DrpVal |= (WriteVal << 8);
	WriteVal = (XVphy_NToDrpEncoding(InstancePtr, QuadId, ChId, 1) & 0x1);
	DrpVal |= (WriteVal << 7);
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x28, DrpVal);
	Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x2A, &DrpVal);
	DrpVal &= ~(0xF800);
	WriteVal = (XVphy_MToDrpEncoding(InstancePtr, QuadId, ChId) & 0x1F);
	DrpVal |= (WriteVal << 11);
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x2A, DrpVal);
	CpllxVcoRateMHz = XVphy_GetPllVcoFreqHz(InstancePtr, QuadId, ChId,
			XVphy_IsTxUsingCpll(InstancePtr, QuadId, ChId) ?
					XVPHY_DIR_TX : XVPHY_DIR_RX) / 1000000;
	if (CpllxVcoRateMHz <= 3000) {
		DrpVal = 0x01FA;
	}
	else if (CpllxVcoRateMHz <= 4250) {
		DrpVal = 0x0FFA;
	}
	else {
		DrpVal = 0x03FE;
	}
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xCB, DrpVal);
	if (CpllxVcoRateMHz <= 3000) {
		DrpVal = 0x0023;
	}
	else {
		DrpVal = 0x0021;
	}
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xCC, DrpVal);
	if (CpllxVcoRateMHz <= 3000) {
		DrpVal = 0x0002;
	}
	else if (CpllxVcoRateMHz <= 4250) {
		DrpVal = 0x0202;
	}
	else {
		DrpVal = 0x0203;
	}
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xBC, DrpVal);
	XVphy_CfgCpllCalPeriodandTol(InstancePtr, QuadId, ChId,
			(XVphy_IsTxUsingCpll(InstancePtr, QuadId, ChId) ?
								XVPHY_DIR_TX : XVPHY_DIR_RX),
			InstancePtr->Config.DrpClkFreq);
	return Status;
}
u32 XVphy_Gthe4ClkChReconfig ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId ChId ) { u16 DrpVal ; u16 WriteVal ; u32 CpllxVcoRateMHz ; u32 Status = XST_SUCCESS ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0x28 , & DrpVal ) ; DrpVal &= ~ ( 0xFF80 ) ; WriteVal = ( XVphy_NToDrpEncoding ( InstancePtr , QuadId , ChId , 2 ) & 0xFF ) ; DrpVal |= ( WriteVal << 8 ) ; WriteVal = ( XVphy_NToDrpEncoding ( InstancePtr , QuadId , ChId , 1 ) & 0x1 ) ; DrpVal |= ( WriteVal << 7 ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x28 , DrpVal ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0x2A , & DrpVal ) ; DrpVal &= ~ ( 0xF800 ) ; WriteVal = ( XVphy_MToDrpEncoding ( InstancePtr , QuadId , ChId ) & 0x1F ) ; DrpVal |= ( WriteVal << 11 ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x2A , DrpVal ) ; CpllxVcoRateMHz = XVphy_GetPllVcoFreqHz ( InstancePtr , QuadId , ChId , XVphy_IsTxUsingCpll ( InstancePtr , QuadId , ChId ) ? XVPHY_DIR_TX : XVPHY_DIR_RX ) / 1000000 ; if ( CpllxVcoRateMHz <= 3000 ) { DrpVal = 0x01FA ; } else if ( CpllxVcoRateMHz <= 4250 ) { DrpVal = 0x0FFA ; } else { DrpVal = 0x03FE ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0xCB , DrpVal ) ; if ( CpllxVcoRateMHz <= 3000 ) { DrpVal = 0x0023 ; } else { DrpVal = 0x0021 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0xCC , DrpVal ) ; if ( CpllxVcoRateMHz <= 3000 ) { DrpVal = 0x0002 ; } else if ( CpllxVcoRateMHz <= 4250 ) { DrpVal = 0x0202 ; } else { DrpVal = 0x0203 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0xBC , DrpVal ) ; XVphy_CfgCpllCalPeriodandTol ( InstancePtr , QuadId , ChId , ( XVphy_IsTxUsingCpll ( InstancePtr , QuadId , ChId ) ? XVPHY_DIR_TX : XVPHY_DIR_RX ) , InstancePtr -> Config . DrpClkFreq ) ; return Status ; }
This function will configure the channel clock settings.
This function will configure the channel clock settings .
/* Obtain current DRP register value for PLL dividers. */ /* Mask out clock divider bits. */ /* Set CPLL_FBDIV. */ /* Set CPLL_FBDIV_45. */ /* Write new DRP register value for PLL dividers. */ /* Write CPLL Ref Clk Div. */ /* Mask out clock divider bits. */ /* Set CPLL_REFCLKDIV. */ /* Write new DRP register value for PLL dividers. */ /* CPLL_CFG0 */ /* Write new DRP register value for CPLL_CFG0. */ /* CPLL_CFG1 */ /* Write new DRP register value for CPLL_CFG1. */ /* CPLL_CFG2 */ /* Write new DRP register value for CPLL_CFG2. */ /* Configure CPLL Calibration Registers */