bluepill/libopencm3/lib/stm32/f4/rcc.c
void rcc_plli2s_config(uint16_t n, uint8_t r)
{
	RCC_PLLI2SCFGR = (
	  ((n & RCC_PLLI2SCFGR_PLLI2SN_MASK) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) |
	  ((r & RCC_PLLI2SCFGR_PLLI2SR_MASK) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT));
}
/**
 * Set the dividers for the PLLI2S clock outputs
 * @param n valid range depends on target device, check your RefManual.
 * @param r valid range is 2..7
 */
Set the dividers for the PLLI2S clock outputs
@param n valid range depends on target device, check your RefManual.
@param r valid range is 2..7
Set the dividers for the PLLI2S clock outputs @param n valid range depends on target device check your RefManual . @param r valid range is 2 .. 7
void rcc_plli2s_config(uint16_t n, uint8_t r)
{
	RCC_PLLI2SCFGR = (
	  ((n & RCC_PLLI2SCFGR_PLLI2SN_MASK) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) |
	  ((r & RCC_PLLI2SCFGR_PLLI2SR_MASK) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT));
}
void rcc_plli2s_config ( uint16_t n , uint8_t r ) { RCC_PLLI2SCFGR = ( ( ( n & RCC_PLLI2SCFGR_PLLI2SN_MASK ) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT ) | ( ( r & RCC_PLLI2SCFGR_PLLI2SR_MASK ) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT ) ) ; }
Set the dividers for the PLLI2S clock outputs
 @param n valid range depends on target device, check your RefManual.
Set the dividers for the PLLI2S clock outputs @param n valid range depends on target device check your RefManual .