XilinxProcessorIPLib/drivers/v_sdirxss/examples/xuhdsdi_example/xuhdsdi_example.c
void RxStreamUpCallback(void *CallbackRef)
{
	u32 Si5324_ClkIn;
	XSdiVid_TransMode RxTransMode;
	u8 IsFractional;
	XVidC_VideoStream *SdiRxSsVidStreamPtr;

	SdiRxSsVidStreamPtr = XV_SdiRxSs_GetVideoStream(&SdiRxSs, 0);

	IsFractional = XV_SdiRxSs_GetTransportBitRate(&SdiRxSs);

	RxTransMode =  XV_SdiRxSs_GetTransportMode(&SdiRxSs);


	switch (RxTransMode) {
		case XSDIVID_MODE_SD:
			if (IsFractional == 0) {
				Si5324_ClkIn = FREQ_27_MHz;

			} else if (IsFractional == 1) {
				Si5324_ClkIn = FREQ_27_MHz;
			}
			break;

		case XSDIVID_MODE_HD:
			if (IsFractional == 0) {
				Si5324_ClkIn = FREQ_74_25_MHz;
			} else if (IsFractional == 1) {
				Si5324_ClkIn = FREQ_74_25_MHz/1.001;
			}
			break;

		case XSDIVID_MODE_3GA:
		case XSDIVID_MODE_3GB:
		case XSDIVID_MODE_6G:
			if (IsFractional == 0) {
				Si5324_ClkIn = FREQ_148_5_MHz;
			} else if (IsFractional == 1) {
				Si5324_ClkIn = FREQ_148_5_MHz/1.001;
			}
			break;

		case XSDIVID_MODE_12G:
			if (IsFractional == 0) {
				Si5324_ClkIn = FREQ_297_MHz;
			} else if (IsFractional == 1) {
				Si5324_ClkIn = FREQ_297_MHz/1.001;
			}
			break;

		default:
			Si5324_ClkIn = FREQ_148_5_MHz;
			break;
	}

	xil_printf("INFO>> SDI Rx: Input Locked\r\n");

	/* The output clock frequency is set to 148.5MHz because the QPLL1's
	 * reference clock is set as 148.5MHz.
	 */
	if (IsFractional == 0) {
	I2cClk(Si5324_ClkIn, FREQ_148_5_MHz);
	} else if (IsFractional == 1) {
		I2cClk(Si5324_ClkIn, FREQ_148_5_MHz/1.001);
	}

	/* Waiting for SI5328 Lock */
	usleep(1000000);

	/* QPLL1 reset */
	Xil_Out32((UINTPTR)(GPIO_0_TX_RST), (u32)(0x00000001));
	usleep(1);
	Xil_Out32((UINTPTR)(GPIO_0_TX_RST), (u32)(0x00000000));

	StartTxAfterRxFlag = (TRUE);
	XV_SdiRxSs_StreamFlowEnable(&SdiRxSs);

	#ifdef XPAR_XSDIAUD_NUM_INSTANCES
	/* Enable SDI Audio Pass-Through or AES Audio Playback (from this ISR) */
	XSdiAud_IntrEnable(&SdiExtract, XSDIAUD_INT_EN_AUD_STAT_UPDATE_MASK);

	/* Enable AES Capture */
	if (XSDIAudioMode == XSDI_AES_CAPTURE_PLAYBACK)
	{
		XSdiEnableAESAudioCapture();
	}
	#endif
}
/*****************************************************************************/
/**
 *
 * This function is called when the RX Lock occurs, it calculates the frequency
 * wrt RxTransMode, programs SI5324 with the calculated frequency and then
 * enables Rx stream flow IPs.
 *
 * @param	CallbackRef is a callback function reference.
 *
 * @return	None.
 *
 * @note	None.
 *
 ******************************************************************************/
This function is called when the RX Lock occurs, it calculates the frequency
wrt RxTransMode, programs SI5324 with the calculated frequency and then
enables Rx stream flow IPs.

@param       CallbackRef is a callback function reference.

@return      None.

@note        None.
This function is called when the RX Lock occurs it calculates the frequency wrt RxTransMode programs SI5324 with the calculated frequency and then enables Rx stream flow IPs . @param CallbackRef is a callback function reference . @return None . @note None .
void RxStreamUpCallback(void *CallbackRef)
{
	u32 Si5324_ClkIn;
	XSdiVid_TransMode RxTransMode;
	u8 IsFractional;
	XVidC_VideoStream *SdiRxSsVidStreamPtr;
	SdiRxSsVidStreamPtr = XV_SdiRxSs_GetVideoStream(&SdiRxSs, 0);
	IsFractional = XV_SdiRxSs_GetTransportBitRate(&SdiRxSs);
	RxTransMode =  XV_SdiRxSs_GetTransportMode(&SdiRxSs);
	switch (RxTransMode) {
		case XSDIVID_MODE_SD:
			if (IsFractional == 0) {
				Si5324_ClkIn = FREQ_27_MHz;
			} else if (IsFractional == 1) {
				Si5324_ClkIn = FREQ_27_MHz;
			}
			break;
		case XSDIVID_MODE_HD:
			if (IsFractional == 0) {
				Si5324_ClkIn = FREQ_74_25_MHz;
			} else if (IsFractional == 1) {
				Si5324_ClkIn = FREQ_74_25_MHz/1.001;
			}
			break;
		case XSDIVID_MODE_3GA:
		case XSDIVID_MODE_3GB:
		case XSDIVID_MODE_6G:
			if (IsFractional == 0) {
				Si5324_ClkIn = FREQ_148_5_MHz;
			} else if (IsFractional == 1) {
				Si5324_ClkIn = FREQ_148_5_MHz/1.001;
			}
			break;
		case XSDIVID_MODE_12G:
			if (IsFractional == 0) {
				Si5324_ClkIn = FREQ_297_MHz;
			} else if (IsFractional == 1) {
				Si5324_ClkIn = FREQ_297_MHz/1.001;
			}
			break;
		default:
			Si5324_ClkIn = FREQ_148_5_MHz;
			break;
	}
	xil_printf("INFO>> SDI Rx: Input Locked\r\n");
	if (IsFractional == 0) {
	I2cClk(Si5324_ClkIn, FREQ_148_5_MHz);
	} else if (IsFractional == 1) {
		I2cClk(Si5324_ClkIn, FREQ_148_5_MHz/1.001);
	}
	usleep(1000000);
	Xil_Out32((UINTPTR)(GPIO_0_TX_RST), (u32)(0x00000001));
	usleep(1);
	Xil_Out32((UINTPTR)(GPIO_0_TX_RST), (u32)(0x00000000));
	StartTxAfterRxFlag = (TRUE);
	XV_SdiRxSs_StreamFlowEnable(&SdiRxSs);
	#ifdef XPAR_XSDIAUD_NUM_INSTANCES
	XSdiAud_IntrEnable(&SdiExtract, XSDIAUD_INT_EN_AUD_STAT_UPDATE_MASK);
	if (XSDIAudioMode == XSDI_AES_CAPTURE_PLAYBACK)
	{
		XSdiEnableAESAudioCapture();
	}
	#endif
}
void RxStreamUpCallback ( void * CallbackRef ) { u32 Si5324_ClkIn ; XSdiVid_TransMode RxTransMode ; u8 IsFractional ; XVidC_VideoStream * SdiRxSsVidStreamPtr ; SdiRxSsVidStreamPtr = XV_SdiRxSs_GetVideoStream ( & SdiRxSs , 0 ) ; IsFractional = XV_SdiRxSs_GetTransportBitRate ( & SdiRxSs ) ; RxTransMode = XV_SdiRxSs_GetTransportMode ( & SdiRxSs ) ; switch ( RxTransMode ) { case XSDIVID_MODE_SD : if ( IsFractional == 0 ) { Si5324_ClkIn = FREQ_27_MHz ; } else if ( IsFractional == 1 ) { Si5324_ClkIn = FREQ_27_MHz ; } break ; case XSDIVID_MODE_HD : if ( IsFractional == 0 ) { Si5324_ClkIn = FREQ_74_25_MHz ; } else if ( IsFractional == 1 ) { Si5324_ClkIn = FREQ_74_25_MHz / 1.001 ; } break ; case XSDIVID_MODE_3GA : case XSDIVID_MODE_3GB : case XSDIVID_MODE_6G : if ( IsFractional == 0 ) { Si5324_ClkIn = FREQ_148_5_MHz ; } else if ( IsFractional == 1 ) { Si5324_ClkIn = FREQ_148_5_MHz / 1.001 ; } break ; case XSDIVID_MODE_12G : if ( IsFractional == 0 ) { Si5324_ClkIn = FREQ_297_MHz ; } else if ( IsFractional == 1 ) { Si5324_ClkIn = FREQ_297_MHz / 1.001 ; } break ; default : Si5324_ClkIn = FREQ_148_5_MHz ; break ; } xil_printf ( " \r \n " ) ; if ( IsFractional == 0 ) { I2cClk ( Si5324_ClkIn , FREQ_148_5_MHz ) ; } else if ( IsFractional == 1 ) { I2cClk ( Si5324_ClkIn , FREQ_148_5_MHz / 1.001 ) ; } usleep ( 1000000 ) ; Xil_Out32 ( ( UINTPTR ) ( GPIO_0_TX_RST ) , ( u32 ) ( 0x00000001 ) ) ; usleep ( 1 ) ; Xil_Out32 ( ( UINTPTR ) ( GPIO_0_TX_RST ) , ( u32 ) ( 0x00000000 ) ) ; StartTxAfterRxFlag = ( TRUE ) ; XV_SdiRxSs_StreamFlowEnable ( & SdiRxSs ) ; #ifdef XPAR_XSDIAUD_NUM_INSTANCES XSdiAud_IntrEnable ( & SdiExtract , XSDIAUD_INT_EN_AUD_STAT_UPDATE_MASK ) ; if ( XSDIAudioMode == XSDI_AES_CAPTURE_PLAYBACK ) { XSdiEnableAESAudioCapture ( ) ; } #endif }
This function is called when the RX Lock occurs, it calculates the frequency
 wrt RxTransMode, programs SI5324 with the calculated frequency and then
 enables Rx stream flow IPs.
This function is called when the RX Lock occurs it calculates the frequency wrt RxTransMode programs SI5324 with the calculated frequency and then enables Rx stream flow IPs .
/* The output clock frequency is set to 148.5MHz because the QPLL1's
	 * reference clock is set as 148.5MHz.
	 */ /* Waiting for SI5328 Lock */ /* QPLL1 reset */ /* Enable SDI Audio Pass-Through or AES Audio Playback (from this ISR) */ /* Enable AES Capture */