asf/common/services/clock/sam3u/pll.h
static inline void pll_config_init(struct pll_config *p_cfg,
		enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)
{
	uint32_t vco_hz;

	Assert(e_src < PLL_NR_SOURCES);

	if (ul_div == 0 && ul_mul == 0) { /* Must only be true for UTMI PLL */
		p_cfg->ctrl = CKGR_UCKR_UPLLCOUNT(PLL_COUNT);
	} else { /* PLLA */
		/* Calculate internal VCO frequency */
		vco_hz = osc_get_rate(e_src) / ul_div;
		Assert(vco_hz >= PLL_INPUT_MIN_HZ);
		Assert(vco_hz <= PLL_INPUT_MAX_HZ);

		vco_hz *= ul_mul;
		Assert(vco_hz >= PLL_OUTPUT_MIN_HZ);
		Assert(vco_hz <= PLL_OUTPUT_MAX_HZ);

		/* PMC hardware will automatically make it mul+1 */
		p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) |
			CKGR_PLLAR_DIVA(ul_div) |
			CKGR_PLLAR_PLLACOUNT(PLL_COUNT);
	}
}
/**
 * \note The SAM3U PLL hardware interprets mul as mul+1. For readability the
 *       hardware mul+1 is hidden in this implementation. Use mul as mul
 *       effective value.
 */
\note The SAM3U PLL hardware interprets mul as mul+1. For readability the
hardware mul+1 is hidden in this implementation. Use mul as mul
effective value.
\ note The SAM3U PLL hardware interprets mul as mul + 1 . For readability the hardware mul + 1 is hidden in this implementation . Use mul as mul effective value .
static inline void pll_config_init(struct pll_config *p_cfg,
		enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)
{
	uint32_t vco_hz;
	Assert(e_src < PLL_NR_SOURCES);
	if (ul_div == 0 && ul_mul == 0) { 
		p_cfg->ctrl = CKGR_UCKR_UPLLCOUNT(PLL_COUNT);
	} else { 
		vco_hz = osc_get_rate(e_src) / ul_div;
		Assert(vco_hz >= PLL_INPUT_MIN_HZ);
		Assert(vco_hz <= PLL_INPUT_MAX_HZ);
		vco_hz *= ul_mul;
		Assert(vco_hz >= PLL_OUTPUT_MIN_HZ);
		Assert(vco_hz <= PLL_OUTPUT_MAX_HZ);
		p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) |
			CKGR_PLLAR_DIVA(ul_div) |
			CKGR_PLLAR_PLLACOUNT(PLL_COUNT);
	}
}
static inline void pll_config_init ( struct pll_config * p_cfg , enum pll_source e_src , uint32_t ul_div , uint32_t ul_mul ) { uint32_t vco_hz ; Assert ( e_src < PLL_NR_SOURCES ) ; if ( ul_div == 0 && ul_mul == 0 ) { p_cfg -> ctrl = CKGR_UCKR_UPLLCOUNT ( PLL_COUNT ) ; } else { vco_hz = osc_get_rate ( e_src ) / ul_div ; Assert ( vco_hz >= PLL_INPUT_MIN_HZ ) ; Assert ( vco_hz <= PLL_INPUT_MAX_HZ ) ; vco_hz *= ul_mul ; Assert ( vco_hz >= PLL_OUTPUT_MIN_HZ ) ; Assert ( vco_hz <= PLL_OUTPUT_MAX_HZ ) ; p_cfg -> ctrl = CKGR_PLLAR_MULA ( ul_mul - 1 ) | CKGR_PLLAR_DIVA ( ul_div ) | CKGR_PLLAR_PLLACOUNT ( PLL_COUNT ) ; } }
\note The SAM3U PLL hardware interprets mul as mul+1.
\ note The SAM3U PLL hardware interprets mul as mul + 1 .
/* Must only be true for UTMI PLL */ /* PLLA */ /* Calculate internal VCO frequency */ /* PMC hardware will automatically make it mul+1 */