XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c
int XSysMon_SetSeqAvgEnables(XSysMon *InstancePtr, u64 AvgEnableChMask)
{
	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * The sequencer must be disabled for writing any of these registers.
	 * Return XST_FAILURE if the channel sequencer is enabled.
	 */
	if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SAFE)) {
		return XST_FAILURE;
	}

	/*
	 * Enable/disable the averaging for the specified channels in the
	 * ADC Channel Averaging Enables Sequencer Registers.
	 */
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ02_OFFSET,
			 (AvgEnableChMask & XSM_SEQ02_CH_VALID_MASK));

	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ03_OFFSET,
			 (AvgEnableChMask >> XSM_SEQ_CH_AUX_SHIFT) &
			 XSM_SEQ03_CH_VALID_MASK);

	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			XSM_SEQ09_OFFSET,
			(AvgEnableChMask >> XSM_SEQ_CH_VUSR_SHIFT) &
			 XSM_SEQ09_CH_VALID_MASK);

	return XST_SUCCESS;
}
/****************************************************************************/
/**
*
* This function enables the averaging for the specified channels in the ADC
* Channel Averaging Enable Sequencer Registers. The sequencer must be in
* the Safe Mode before writing to these registers.
*
* @param	InstancePtr is a pointer to the XSysMon instance.
* @param	AvgEnableChMask is the bit mask of all the channels for which
*		averaging is to be enabled. Use XSM_SEQ_CH__* defined in
*		xsysmon_hw.h to specify the Channel numbers. Averaging will be
*		enabled for bit masks of 1 and disabled for bit mask of 0.
*		The AvgEnableChMask is a 64 bit mask that is written to the
*		three 16 bit ADC Channel Averaging Enable Sequencer Registers.
*
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the ADC Channel Averaging Enables Sequencer Registers.
*		- XST_FAILURE if the channel sequencer is enabled.
*
* @note		None.
*
*****************************************************************************/
This function enables the averaging for the specified channels in the ADC
Channel Averaging Enable Sequencer Registers. The sequencer must be in
the Safe Mode before writing to these registers.
This function enables the averaging for the specified channels in the ADC Channel Averaging Enable Sequencer Registers . The sequencer must be in the Safe Mode before writing to these registers .
int XSysMon_SetSeqAvgEnables(XSysMon *InstancePtr, u64 AvgEnableChMask)
{
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SAFE)) {
		return XST_FAILURE;
	}
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ02_OFFSET,
			 (AvgEnableChMask & XSM_SEQ02_CH_VALID_MASK));
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ03_OFFSET,
			 (AvgEnableChMask >> XSM_SEQ_CH_AUX_SHIFT) &
			 XSM_SEQ03_CH_VALID_MASK);
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			XSM_SEQ09_OFFSET,
			(AvgEnableChMask >> XSM_SEQ_CH_VUSR_SHIFT) &
			 XSM_SEQ09_CH_VALID_MASK);
	return XST_SUCCESS;
}
int XSysMon_SetSeqAvgEnables ( XSysMon * InstancePtr , u64 AvgEnableChMask ) { Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; if ( ( XSysMon_GetSequencerMode ( InstancePtr ) != XSM_SEQ_MODE_SAFE ) ) { return XST_FAILURE ; } XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ02_OFFSET , ( AvgEnableChMask & XSM_SEQ02_CH_VALID_MASK ) ) ; XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ03_OFFSET , ( AvgEnableChMask >> XSM_SEQ_CH_AUX_SHIFT ) & XSM_SEQ03_CH_VALID_MASK ) ; XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ09_OFFSET , ( AvgEnableChMask >> XSM_SEQ_CH_VUSR_SHIFT ) & XSM_SEQ09_CH_VALID_MASK ) ; return XST_SUCCESS ; }
This function enables the averaging for the specified channels in the ADC
Channel Averaging Enable Sequencer Registers.
This function enables the averaging for the specified channels in the ADC Channel Averaging Enable Sequencer Registers .
/*
	 * Assert the arguments.
	 */ /*
	 * The sequencer must be disabled for writing any of these registers.
	 * Return XST_FAILURE if the channel sequencer is enabled.
	 */ /*
	 * Enable/disable the averaging for the specified channels in the
	 * ADC Channel Averaging Enables Sequencer Registers.
	 */