lib/sw_apps/zynqmp_fsbl/src/xfsbl_ddr_init.c
u32 XFsbl_ComputeDdr3Params(u8 *SpdData, struct DdrcInitData *DdrDataPtr)
{
	struct Ddr3SpdEeprom *Ddr3SpdData = (struct Ddr3SpdEeprom *)SpdData;
	XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;

	u32 MtbPs;
	u32 Ftb10thPs;
	u32 Status = XFSBL_FAILURE;

	memset(PDimmPtr->Mpart, 0U, sizeof(PDimmPtr->Mpart));
	if ((Ddr3SpdData->InfoSizeCrc & 0xFU) > 1U)
		memcpy(PDimmPtr->Mpart, Ddr3SpdData->Mpart, sizeof(PDimmPtr->Mpart) - 1U);

	PDimmPtr->MemType = Ddr3SpdData->MemType;
	PDimmPtr->NRanks = ((Ddr3SpdData->Organization >> 3U) & 0x7U) + 1U;
	PDimmPtr->RankDensity = XFsbl_ComputeDdr3RankSize(Ddr3SpdData);
	PDimmPtr->Capacity = PDimmPtr->NRanks * PDimmPtr->RankDensity;
	PDimmPtr->BusWidth = 1U << (3U + (Ddr3SpdData->BusWidth & 0x7U));
	if ((Ddr3SpdData->BusWidth >> 3U) & 0x3U)
		PDimmPtr->EccBusWidth = 8U;
	else
		PDimmPtr->EccBusWidth = 0U;
	PDimmPtr->DramWidth = 1U << ((Ddr3SpdData->Organization & 0x7U) + 2U);

	PDimmPtr->AddrMirror = 0U;
	PDimmPtr->RDimm = 0U;
	switch (Ddr3SpdData->ModuleType & DDR3_SPD_MODULETYPE_MASK) {
		case DDR3_SPD_MODULETYPE_RDIMM:
		case DDR3_SPD_MODULETYPE_MINI_RDIMM:
		case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
			PDimmPtr->RDimm = 1U;
			break;

		case DDR3_SPD_MODULETYPE_UDIMM:
		case DDR3_SPD_MODULETYPE_SO_DIMM:
		case DDR3_SPD_MODULETYPE_MICRO_DIMM:
		case DDR3_SPD_MODULETYPE_MINI_UDIMM:
		case DDR3_SPD_MODULETYPE_MINI_CDIMM:
		case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
		case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
		case DDR3_SPD_MODULETYPE_LRDIMM:
		case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
		case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
			if (Ddr3SpdData->ModSection.unbuffered.AddrMapping & 0x1U)
				PDimmPtr->AddrMirror = 1U;
			break;

		default:
			/* Do nothing as Status is initialized to XFSBL_FAILURE */
			goto END;
	}

	PDimmPtr->NBanksPerSdramDevice = 8U << ((Ddr3SpdData->DensityBanks >> 4U) & 0x7U);
	PDimmPtr->NumRowAddr = ((Ddr3SpdData->Addressing >> 3U) & 0x7U) + 12U;
	PDimmPtr->NumColAddr = (Ddr3SpdData->Addressing & 0x7U) + 9U;
	PDimmPtr->NumBankAddr = ((Ddr3SpdData->DensityBanks >> 4U) & 0x3U) + 2U;
	PDimmPtr->NumBgAddr = (Ddr3SpdData->DensityBanks >> 6U) & 0x3U;
	PDimmPtr->NumRankAddr = XFsbl_GetLog2(PDimmPtr->NRanks);

	PDimmPtr->BurstLength = 8U;
	PDimmPtr->RowDensity = XFsbl_GetLog2(PDimmPtr->RankDensity);

	MtbPs = (Ddr3SpdData->MtbDividend * 1000U) / Ddr3SpdData->MtbDivisor;
	PDimmPtr->MtbPs = MtbPs;

	Ftb10thPs =
		((Ddr3SpdData->FtbDiv & 0xF0U) >> 4U) * 10U / (Ddr3SpdData->FtbDiv & 0x0fU);
	PDimmPtr->Ftb10thPs = Ftb10thPs;
	PDimmPtr->TckminXPs = Ddr3SpdData->TckMin * MtbPs +
		(Ddr3SpdData->FineTckMin * Ftb10thPs) / 10U;

	PDimmPtr->CaslatX  = ((Ddr3SpdData->CaslatMsb << 8U) | Ddr3SpdData->CaslatLsb) << 4U;

	PDimmPtr->TaaPs = Ddr3SpdData->TaaMin * MtbPs +
		(Ddr3SpdData->FineTaaMin * Ftb10thPs) / 10U;

	PDimmPtr->TwrPs = Ddr3SpdData->TwrMin * MtbPs;

	PDimmPtr->TRcdPs = Ddr3SpdData->TrcdMin * MtbPs +
		(Ddr3SpdData->FineTrcdMin * Ftb10thPs) / 10U;

	PDimmPtr->TRrdPs = Ddr3SpdData->TrrdMin * MtbPs;

	PDimmPtr->TRpPs = Ddr3SpdData->TrpMin * MtbPs +
		(Ddr3SpdData->FineTrpMin * Ftb10thPs) / 10U;

	PDimmPtr->TRasPs = (((Ddr3SpdData->TrasTrcExt & 0xFU) << 8U) | Ddr3SpdData->TrasMinLsb)
		* MtbPs;
	PDimmPtr->TRcPs = (((Ddr3SpdData->TrasTrcExt & 0xF0U) << 4U) | Ddr3SpdData->TrcMinLsb)
		* MtbPs + (Ddr3SpdData->FineTrcMin * Ftb10thPs) / 10U;
	PDimmPtr->TRfcPs = ((Ddr3SpdData->TrfcMinMsb << 8U) | Ddr3SpdData->TrfcMinLsb)
		* MtbPs;
	PDimmPtr->TwtrPs = Ddr3SpdData->TwtrMin * MtbPs;

	PDimmPtr->TrtpPs = Ddr3SpdData->TrtpMin * MtbPs;

	PDimmPtr->TRefi = 7800000U;
	if ((Ddr3SpdData->ThermRefOpt & 0x1U) && !(Ddr3SpdData->ThermRefOpt & 0x2U)) {
		PDimmPtr->TRefi = 3900000U;
	}

	PDimmPtr->TFawPs = (((Ddr3SpdData->TfawMsb & 0xFU) << 8U) | Ddr3SpdData->TfawMin)
		* MtbPs;
	Status = XFSBL_SUCCESS;

END:
	return Status;
}
/*****************************************************************************/
/**
 * This function computes DIMM parameters based upon the SPD information in
 * Dd34SpdData. Writes the results to the XFsbl_DimmParams structure pointed
 * by PDimmPtr.
 *
 * @param	DdrDataPtr is pointer to DDR Initialization Data Structure
 * @param	SpdData is the array containing the SPD data from DIMM EEPROM
 *
 * @return	XFSBL_SUCCESS or XFSBL_FAILURE
 *
 *****************************************************************************/
This function computes DIMM parameters based upon the SPD information in
Dd34SpdData. Writes the results to the XFsbl_DimmParams structure pointed
by PDimmPtr.

@param       DdrDataPtr is pointer to DDR Initialization Data Structure
@param       SpdData is the array containing the SPD data from DIMM EEPROM


This function computes DIMM parameters based upon the SPD information in Dd34SpdData . Writes the results to the XFsbl_DimmParams structure pointed by PDimmPtr . @param DdrDataPtr is pointer to DDR Initialization Data Structure @param SpdData is the array containing the SPD data from DIMM EEPROM
u32 XFsbl_ComputeDdr3Params(u8 *SpdData, struct DdrcInitData *DdrDataPtr)
{
	struct Ddr3SpdEeprom *Ddr3SpdData = (struct Ddr3SpdEeprom *)SpdData;
	XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
	u32 MtbPs;
	u32 Ftb10thPs;
	u32 Status = XFSBL_FAILURE;
	memset(PDimmPtr->Mpart, 0U, sizeof(PDimmPtr->Mpart));
	if ((Ddr3SpdData->InfoSizeCrc & 0xFU) > 1U)
		memcpy(PDimmPtr->Mpart, Ddr3SpdData->Mpart, sizeof(PDimmPtr->Mpart) - 1U);
	PDimmPtr->MemType = Ddr3SpdData->MemType;
	PDimmPtr->NRanks = ((Ddr3SpdData->Organization >> 3U) & 0x7U) + 1U;
	PDimmPtr->RankDensity = XFsbl_ComputeDdr3RankSize(Ddr3SpdData);
	PDimmPtr->Capacity = PDimmPtr->NRanks * PDimmPtr->RankDensity;
	PDimmPtr->BusWidth = 1U << (3U + (Ddr3SpdData->BusWidth & 0x7U));
	if ((Ddr3SpdData->BusWidth >> 3U) & 0x3U)
		PDimmPtr->EccBusWidth = 8U;
	else
		PDimmPtr->EccBusWidth = 0U;
	PDimmPtr->DramWidth = 1U << ((Ddr3SpdData->Organization & 0x7U) + 2U);
	PDimmPtr->AddrMirror = 0U;
	PDimmPtr->RDimm = 0U;
	switch (Ddr3SpdData->ModuleType & DDR3_SPD_MODULETYPE_MASK) {
		case DDR3_SPD_MODULETYPE_RDIMM:
		case DDR3_SPD_MODULETYPE_MINI_RDIMM:
		case DDR3_SPD_MODULETYPE_72B_SO_RDIMM:
			PDimmPtr->RDimm = 1U;
			break;
		case DDR3_SPD_MODULETYPE_UDIMM:
		case DDR3_SPD_MODULETYPE_SO_DIMM:
		case DDR3_SPD_MODULETYPE_MICRO_DIMM:
		case DDR3_SPD_MODULETYPE_MINI_UDIMM:
		case DDR3_SPD_MODULETYPE_MINI_CDIMM:
		case DDR3_SPD_MODULETYPE_72B_SO_UDIMM:
		case DDR3_SPD_MODULETYPE_72B_SO_CDIMM:
		case DDR3_SPD_MODULETYPE_LRDIMM:
		case DDR3_SPD_MODULETYPE_16B_SO_DIMM:
		case DDR3_SPD_MODULETYPE_32B_SO_DIMM:
			if (Ddr3SpdData->ModSection.unbuffered.AddrMapping & 0x1U)
				PDimmPtr->AddrMirror = 1U;
			break;
		default:
			goto END;
	}
	PDimmPtr->NBanksPerSdramDevice = 8U << ((Ddr3SpdData->DensityBanks >> 4U) & 0x7U);
	PDimmPtr->NumRowAddr = ((Ddr3SpdData->Addressing >> 3U) & 0x7U) + 12U;
	PDimmPtr->NumColAddr = (Ddr3SpdData->Addressing & 0x7U) + 9U;
	PDimmPtr->NumBankAddr = ((Ddr3SpdData->DensityBanks >> 4U) & 0x3U) + 2U;
	PDimmPtr->NumBgAddr = (Ddr3SpdData->DensityBanks >> 6U) & 0x3U;
	PDimmPtr->NumRankAddr = XFsbl_GetLog2(PDimmPtr->NRanks);
	PDimmPtr->BurstLength = 8U;
	PDimmPtr->RowDensity = XFsbl_GetLog2(PDimmPtr->RankDensity);
	MtbPs = (Ddr3SpdData->MtbDividend * 1000U) / Ddr3SpdData->MtbDivisor;
	PDimmPtr->MtbPs = MtbPs;
	Ftb10thPs =
		((Ddr3SpdData->FtbDiv & 0xF0U) >> 4U) * 10U / (Ddr3SpdData->FtbDiv & 0x0fU);
	PDimmPtr->Ftb10thPs = Ftb10thPs;
	PDimmPtr->TckminXPs = Ddr3SpdData->TckMin * MtbPs +
		(Ddr3SpdData->FineTckMin * Ftb10thPs) / 10U;
	PDimmPtr->CaslatX  = ((Ddr3SpdData->CaslatMsb << 8U) | Ddr3SpdData->CaslatLsb) << 4U;
	PDimmPtr->TaaPs = Ddr3SpdData->TaaMin * MtbPs +
		(Ddr3SpdData->FineTaaMin * Ftb10thPs) / 10U;
	PDimmPtr->TwrPs = Ddr3SpdData->TwrMin * MtbPs;
	PDimmPtr->TRcdPs = Ddr3SpdData->TrcdMin * MtbPs +
		(Ddr3SpdData->FineTrcdMin * Ftb10thPs) / 10U;
	PDimmPtr->TRrdPs = Ddr3SpdData->TrrdMin * MtbPs;
	PDimmPtr->TRpPs = Ddr3SpdData->TrpMin * MtbPs +
		(Ddr3SpdData->FineTrpMin * Ftb10thPs) / 10U;
	PDimmPtr->TRasPs = (((Ddr3SpdData->TrasTrcExt & 0xFU) << 8U) | Ddr3SpdData->TrasMinLsb)
		* MtbPs;
	PDimmPtr->TRcPs = (((Ddr3SpdData->TrasTrcExt & 0xF0U) << 4U) | Ddr3SpdData->TrcMinLsb)
		* MtbPs + (Ddr3SpdData->FineTrcMin * Ftb10thPs) / 10U;
	PDimmPtr->TRfcPs = ((Ddr3SpdData->TrfcMinMsb << 8U) | Ddr3SpdData->TrfcMinLsb)
		* MtbPs;
	PDimmPtr->TwtrPs = Ddr3SpdData->TwtrMin * MtbPs;
	PDimmPtr->TrtpPs = Ddr3SpdData->TrtpMin * MtbPs;
	PDimmPtr->TRefi = 7800000U;
	if ((Ddr3SpdData->ThermRefOpt & 0x1U) && !(Ddr3SpdData->ThermRefOpt & 0x2U)) {
		PDimmPtr->TRefi = 3900000U;
	}
	PDimmPtr->TFawPs = (((Ddr3SpdData->TfawMsb & 0xFU) << 8U) | Ddr3SpdData->TfawMin)
		* MtbPs;
	Status = XFSBL_SUCCESS;
END:
	return Status;
}
u32 XFsbl_ComputeDdr3Params ( u8 * SpdData , struct DdrcInitData * DdrDataPtr ) { struct Ddr3SpdEeprom * Ddr3SpdData = ( struct Ddr3SpdEeprom * ) SpdData ; XFsbl_DimmParams * PDimmPtr = & DdrDataPtr -> PDimm ; u32 MtbPs ; u32 Ftb10thPs ; u32 Status = XFSBL_FAILURE ; memset ( PDimmPtr -> Mpart , 0U , sizeof ( PDimmPtr -> Mpart ) ) ; if ( ( Ddr3SpdData -> InfoSizeCrc & 0xFU ) > 1U ) memcpy ( PDimmPtr -> Mpart , Ddr3SpdData -> Mpart , sizeof ( PDimmPtr -> Mpart ) - 1U ) ; PDimmPtr -> MemType = Ddr3SpdData -> MemType ; PDimmPtr -> NRanks = ( ( Ddr3SpdData -> Organization >> 3U ) & 0x7U ) + 1U ; PDimmPtr -> RankDensity = XFsbl_ComputeDdr3RankSize ( Ddr3SpdData ) ; PDimmPtr -> Capacity = PDimmPtr -> NRanks * PDimmPtr -> RankDensity ; PDimmPtr -> BusWidth = 1U << ( 3U + ( Ddr3SpdData -> BusWidth & 0x7U ) ) ; if ( ( Ddr3SpdData -> BusWidth >> 3U ) & 0x3U ) PDimmPtr -> EccBusWidth = 8U ; else PDimmPtr -> EccBusWidth = 0U ; PDimmPtr -> DramWidth = 1U << ( ( Ddr3SpdData -> Organization & 0x7U ) + 2U ) ; PDimmPtr -> AddrMirror = 0U ; PDimmPtr -> RDimm = 0U ; switch ( Ddr3SpdData -> ModuleType & DDR3_SPD_MODULETYPE_MASK ) { case DDR3_SPD_MODULETYPE_RDIMM : case DDR3_SPD_MODULETYPE_MINI_RDIMM : case DDR3_SPD_MODULETYPE_72B_SO_RDIMM : PDimmPtr -> RDimm = 1U ; break ; case DDR3_SPD_MODULETYPE_UDIMM : case DDR3_SPD_MODULETYPE_SO_DIMM : case DDR3_SPD_MODULETYPE_MICRO_DIMM : case DDR3_SPD_MODULETYPE_MINI_UDIMM : case DDR3_SPD_MODULETYPE_MINI_CDIMM : case DDR3_SPD_MODULETYPE_72B_SO_UDIMM : case DDR3_SPD_MODULETYPE_72B_SO_CDIMM : case DDR3_SPD_MODULETYPE_LRDIMM : case DDR3_SPD_MODULETYPE_16B_SO_DIMM : case DDR3_SPD_MODULETYPE_32B_SO_DIMM : if ( Ddr3SpdData -> ModSection . unbuffered . AddrMapping & 0x1U ) PDimmPtr -> AddrMirror = 1U ; break ; default : goto END ; } PDimmPtr -> NBanksPerSdramDevice = 8U << ( ( Ddr3SpdData -> DensityBanks >> 4U ) & 0x7U ) ; PDimmPtr -> NumRowAddr = ( ( Ddr3SpdData -> Addressing >> 3U ) & 0x7U ) + 12U ; PDimmPtr -> NumColAddr = ( Ddr3SpdData -> Addressing & 0x7U ) + 9U ; PDimmPtr -> NumBankAddr = ( ( Ddr3SpdData -> DensityBanks >> 4U ) & 0x3U ) + 2U ; PDimmPtr -> NumBgAddr = ( Ddr3SpdData -> DensityBanks >> 6U ) & 0x3U ; PDimmPtr -> NumRankAddr = XFsbl_GetLog2 ( PDimmPtr -> NRanks ) ; PDimmPtr -> BurstLength = 8U ; PDimmPtr -> RowDensity = XFsbl_GetLog2 ( PDimmPtr -> RankDensity ) ; MtbPs = ( Ddr3SpdData -> MtbDividend * 1000U ) / Ddr3SpdData -> MtbDivisor ; PDimmPtr -> MtbPs = MtbPs ; Ftb10thPs = ( ( Ddr3SpdData -> FtbDiv & 0xF0U ) >> 4U ) * 10U / ( Ddr3SpdData -> FtbDiv & 0x0fU ) ; PDimmPtr -> Ftb10thPs = Ftb10thPs ; PDimmPtr -> TckminXPs = Ddr3SpdData -> TckMin * MtbPs + ( Ddr3SpdData -> FineTckMin * Ftb10thPs ) / 10U ; PDimmPtr -> CaslatX = ( ( Ddr3SpdData -> CaslatMsb << 8U ) | Ddr3SpdData -> CaslatLsb ) << 4U ; PDimmPtr -> TaaPs = Ddr3SpdData -> TaaMin * MtbPs + ( Ddr3SpdData -> FineTaaMin * Ftb10thPs ) / 10U ; PDimmPtr -> TwrPs = Ddr3SpdData -> TwrMin * MtbPs ; PDimmPtr -> TRcdPs = Ddr3SpdData -> TrcdMin * MtbPs + ( Ddr3SpdData -> FineTrcdMin * Ftb10thPs ) / 10U ; PDimmPtr -> TRrdPs = Ddr3SpdData -> TrrdMin * MtbPs ; PDimmPtr -> TRpPs = Ddr3SpdData -> TrpMin * MtbPs + ( Ddr3SpdData -> FineTrpMin * Ftb10thPs ) / 10U ; PDimmPtr -> TRasPs = ( ( ( Ddr3SpdData -> TrasTrcExt & 0xFU ) << 8U ) | Ddr3SpdData -> TrasMinLsb ) * MtbPs ; PDimmPtr -> TRcPs = ( ( ( Ddr3SpdData -> TrasTrcExt & 0xF0U ) << 4U ) | Ddr3SpdData -> TrcMinLsb ) * MtbPs + ( Ddr3SpdData -> FineTrcMin * Ftb10thPs ) / 10U ; PDimmPtr -> TRfcPs = ( ( Ddr3SpdData -> TrfcMinMsb << 8U ) | Ddr3SpdData -> TrfcMinLsb ) * MtbPs ; PDimmPtr -> TwtrPs = Ddr3SpdData -> TwtrMin * MtbPs ; PDimmPtr -> TrtpPs = Ddr3SpdData -> TrtpMin * MtbPs ; PDimmPtr -> TRefi = 7800000U ; if ( ( Ddr3SpdData -> ThermRefOpt & 0x1U ) && ! ( Ddr3SpdData -> ThermRefOpt & 0x2U ) ) { PDimmPtr -> TRefi = 3900000U ; } PDimmPtr -> TFawPs = ( ( ( Ddr3SpdData -> TfawMsb & 0xFU ) << 8U ) | Ddr3SpdData -> TfawMin ) * MtbPs ; Status = XFSBL_SUCCESS ; END : return Status ; }
This function computes DIMM parameters based upon the SPD information in
 Dd34SpdData.
This function computes DIMM parameters based upon the SPD information in Dd34SpdData .
/* Do nothing as Status is initialized to XFSBL_FAILURE */