src/dpdk/drivers/net/iavf/iavf_rxtx.c
uint16_t
iavf_recv_pkts_flex_rxd(void *rx_queue,
			struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
{
	volatile union iavf_rx_desc *rx_ring;
	volatile union iavf_rx_flex_desc *rxdp;
	struct iavf_rx_queue *rxq;
	union iavf_rx_flex_desc rxd;
	struct rte_mbuf *rxe;
	struct rte_eth_dev *dev;
	struct rte_mbuf *rxm;
	struct rte_mbuf *nmb;
	uint16_t nb_rx;
	uint16_t rx_stat_err0;
	uint16_t rx_packet_len;
	uint16_t rx_id, nb_hold;
	uint64_t dma_addr;
	uint64_t pkt_flags;
	const uint32_t *ptype_tbl;

	nb_rx = 0;
	nb_hold = 0;
	rxq = rx_queue;
	rx_id = rxq->rx_tail;
	rx_ring = rxq->rx_ring;
	ptype_tbl = rxq->vsi->adapter->ptype_tbl;

	while (nb_rx < nb_pkts) {
		rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
		rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);

		/* Check the DD bit first */
		if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
			break;
		IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);

		nmb = rte_mbuf_raw_alloc(rxq->mp);
		if (unlikely(!nmb)) {
			dev = &rte_eth_devices[rxq->port_id];
			dev->data->rx_mbuf_alloc_failed++;
			PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
				   "queue_id=%u", rxq->port_id, rxq->queue_id);
			break;
		}

		rxd = *rxdp;
		nb_hold++;
		rxe = rxq->sw_ring[rx_id];
		rx_id++;
		if (unlikely(rx_id == rxq->nb_rx_desc))
			rx_id = 0;

		/* Prefetch next mbuf */
		rte_prefetch0(rxq->sw_ring[rx_id]);

		/* When next RX descriptor is on a cache line boundary,
		 * prefetch the next 4 RX descriptors and next 8 pointers
		 * to mbufs.
		 */
		if ((rx_id & 0x3) == 0) {
			rte_prefetch0(&rx_ring[rx_id]);
			rte_prefetch0(rxq->sw_ring[rx_id]);
		}
		rxm = rxe;
		dma_addr =
			rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
		rxdp->read.hdr_addr = 0;
		rxdp->read.pkt_addr = dma_addr;

		rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
				IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;

		rxm->data_off = RTE_PKTMBUF_HEADROOM;
		rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
		rxm->nb_segs = 1;
		rxm->next = NULL;
		rxm->pkt_len = rx_packet_len;
		rxm->data_len = rx_packet_len;
		rxm->port = rxq->port_id;
		rxm->ol_flags = 0;
		rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
			rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
		iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
		rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
		pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
		rxm->ol_flags |= pkt_flags;

		rx_pkts[nb_rx++] = rxm;
	}
	rxq->rx_tail = rx_id;

	iavf_update_rx_tail(rxq, nb_hold, rx_id);

	return nb_rx;
}
/* implement recv_pkts for flexible Rx descriptor */
implement recv_pkts for flexible Rx descriptor
implement recv_pkts for flexible Rx descriptor
uint16_t
iavf_recv_pkts_flex_rxd(void *rx_queue,
			struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
{
	volatile union iavf_rx_desc *rx_ring;
	volatile union iavf_rx_flex_desc *rxdp;
	struct iavf_rx_queue *rxq;
	union iavf_rx_flex_desc rxd;
	struct rte_mbuf *rxe;
	struct rte_eth_dev *dev;
	struct rte_mbuf *rxm;
	struct rte_mbuf *nmb;
	uint16_t nb_rx;
	uint16_t rx_stat_err0;
	uint16_t rx_packet_len;
	uint16_t rx_id, nb_hold;
	uint64_t dma_addr;
	uint64_t pkt_flags;
	const uint32_t *ptype_tbl;
	nb_rx = 0;
	nb_hold = 0;
	rxq = rx_queue;
	rx_id = rxq->rx_tail;
	rx_ring = rxq->rx_ring;
	ptype_tbl = rxq->vsi->adapter->ptype_tbl;
	while (nb_rx < nb_pkts) {
		rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
		rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
		if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
			break;
		IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
		nmb = rte_mbuf_raw_alloc(rxq->mp);
		if (unlikely(!nmb)) {
			dev = &rte_eth_devices[rxq->port_id];
			dev->data->rx_mbuf_alloc_failed++;
			PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
				   "queue_id=%u", rxq->port_id, rxq->queue_id);
			break;
		}
		rxd = *rxdp;
		nb_hold++;
		rxe = rxq->sw_ring[rx_id];
		rx_id++;
		if (unlikely(rx_id == rxq->nb_rx_desc))
			rx_id = 0;
		rte_prefetch0(rxq->sw_ring[rx_id]);
		if ((rx_id & 0x3) == 0) {
			rte_prefetch0(&rx_ring[rx_id]);
			rte_prefetch0(rxq->sw_ring[rx_id]);
		}
		rxm = rxe;
		dma_addr =
			rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
		rxdp->read.hdr_addr = 0;
		rxdp->read.pkt_addr = dma_addr;
		rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
				IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
		rxm->data_off = RTE_PKTMBUF_HEADROOM;
		rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
		rxm->nb_segs = 1;
		rxm->next = NULL;
		rxm->pkt_len = rx_packet_len;
		rxm->data_len = rx_packet_len;
		rxm->port = rxq->port_id;
		rxm->ol_flags = 0;
		rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
			rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
		iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
		rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
		pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
		rxm->ol_flags |= pkt_flags;
		rx_pkts[nb_rx++] = rxm;
	}
	rxq->rx_tail = rx_id;
	iavf_update_rx_tail(rxq, nb_hold, rx_id);
	return nb_rx;
}
uint16_t iavf_recv_pkts_flex_rxd ( void * rx_queue , struct rte_mbuf * * rx_pkts , uint16_t nb_pkts ) { volatile union iavf_rx_desc * rx_ring ; volatile union iavf_rx_flex_desc * rxdp ; struct iavf_rx_queue * rxq ; union iavf_rx_flex_desc rxd ; struct rte_mbuf * rxe ; struct rte_eth_dev * dev ; struct rte_mbuf * rxm ; struct rte_mbuf * nmb ; uint16_t nb_rx ; uint16_t rx_stat_err0 ; uint16_t rx_packet_len ; uint16_t rx_id , nb_hold ; uint64_t dma_addr ; uint64_t pkt_flags ; const uint32_t * ptype_tbl ; nb_rx = 0 ; nb_hold = 0 ; rxq = rx_queue ; rx_id = rxq -> rx_tail ; rx_ring = rxq -> rx_ring ; ptype_tbl = rxq -> vsi -> adapter -> ptype_tbl ; while ( nb_rx < nb_pkts ) { rxdp = ( volatile union iavf_rx_flex_desc * ) & rx_ring [ rx_id ] ; rx_stat_err0 = rte_le_to_cpu_16 ( rxdp -> wb . status_error0 ) ; if ( ! ( rx_stat_err0 & ( 1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S ) ) ) break ; IAVF_DUMP_RX_DESC ( rxq , rxdp , rx_id ) ; nmb = rte_mbuf_raw_alloc ( rxq -> mp ) ; if ( unlikely ( ! nmb ) ) { dev = & rte_eth_devices [ rxq -> port_id ] ; dev -> data -> rx_mbuf_alloc_failed ++ ; PMD_RX_LOG ( DEBUG , " " " " , rxq -> port_id , rxq -> queue_id ) ; break ; } rxd = * rxdp ; nb_hold ++ ; rxe = rxq -> sw_ring [ rx_id ] ; rx_id ++ ; if ( unlikely ( rx_id == rxq -> nb_rx_desc ) ) rx_id = 0 ; rte_prefetch0 ( rxq -> sw_ring [ rx_id ] ) ; if ( ( rx_id & 0x3 ) == 0 ) { rte_prefetch0 ( & rx_ring [ rx_id ] ) ; rte_prefetch0 ( rxq -> sw_ring [ rx_id ] ) ; } rxm = rxe ; dma_addr = rte_cpu_to_le_64 ( rte_mbuf_data_iova_default ( nmb ) ) ; rxdp -> read . hdr_addr = 0 ; rxdp -> read . pkt_addr = dma_addr ; rx_packet_len = ( rte_le_to_cpu_16 ( rxd . wb . pkt_len ) & IAVF_RX_FLX_DESC_PKT_LEN_M ) - rxq -> crc_len ; rxm -> data_off = RTE_PKTMBUF_HEADROOM ; rte_prefetch0 ( RTE_PTR_ADD ( rxm -> buf_addr , RTE_PKTMBUF_HEADROOM ) ) ; rxm -> nb_segs = 1 ; rxm -> next = NULL ; rxm -> pkt_len = rx_packet_len ; rxm -> data_len = rx_packet_len ; rxm -> port = rxq -> port_id ; rxm -> ol_flags = 0 ; rxm -> packet_type = ptype_tbl [ IAVF_RX_FLEX_DESC_PTYPE_M & rte_le_to_cpu_16 ( rxd . wb . ptype_flex_flags0 ) ] ; iavf_flex_rxd_to_vlan_tci ( rxm , & rxd ) ; rxq -> rxd_to_pkt_fields ( rxq , rxm , & rxd ) ; pkt_flags = iavf_flex_rxd_error_to_pkt_flags ( rx_stat_err0 ) ; rxm -> ol_flags |= pkt_flags ; rx_pkts [ nb_rx ++ ] = rxm ; } rxq -> rx_tail = rx_id ; iavf_update_rx_tail ( rxq , nb_hold , rx_id ) ; return nb_rx ; }
implement recv_pkts for flexible Rx descriptor
implement recv_pkts for flexible Rx descriptor
/* Check the DD bit first */ /* Prefetch next mbuf */ /* When next RX descriptor is on a cache line boundary,
		 * prefetch the next 4 RX descriptors and next 8 pointers
		 * to mbufs.
		 */