XilinxProcessorIPLib/drivers/vphy/src/xvphy_gtpe2.c
u32 XVphy_Gtpe2TxPllRefClkDiv1Reconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId ChId)
{
	u16 DrpVal;
	u32 TxRefClkHz;
	XVphy_Channel *CmnPtr;
	XVphy_ChannelId CmnId;
	XVphy_PllType PllType;
    u32 Status = XST_SUCCESS;

	if (XVphy_IsHDMI(InstancePtr, XVPHY_DIR_TX)) {
		TxRefClkHz = InstancePtr->HdmiTxRefClkHz;
	}
	else {
		PllType = XVphy_GetPllType(InstancePtr, QuadId, XVPHY_DIR_TX, ChId);
		CmnId = XVphy_GetRcfgChId(InstancePtr, QuadId, XVPHY_DIR_TX, PllType);
		CmnPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(CmnId)];
		TxRefClkHz = XVphy_GetQuadRefClkFreq(InstancePtr, QuadId,
								CmnPtr->PllRefClkSel);
	}

	Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, XVPHY_DRP_TXCLK25, &DrpVal);
	DrpVal &= ~(0x1F);
	DrpVal |= XVphy_DrpEncodeClk25(TxRefClkHz);
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, XVPHY_DRP_TXCLK25,
                    DrpVal);
	return Status;
}
/*****************************************************************************/
/**
* This function will configure the channel's TX CLKDIV1 settings.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
*
* @return
*		- XST_SUCCESS if the configuration was successful.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function will configure the channel's TX CLKDIV1 settings.
This function will configure the channel ' s TX CLKDIV1 settings .
u32 XVphy_Gtpe2TxPllRefClkDiv1Reconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId ChId)
{
	u16 DrpVal;
	u32 TxRefClkHz;
	XVphy_Channel *CmnPtr;
	XVphy_ChannelId CmnId;
	XVphy_PllType PllType;
    u32 Status = XST_SUCCESS;
	if (XVphy_IsHDMI(InstancePtr, XVPHY_DIR_TX)) {
		TxRefClkHz = InstancePtr->HdmiTxRefClkHz;
	}
	else {
		PllType = XVphy_GetPllType(InstancePtr, QuadId, XVPHY_DIR_TX, ChId);
		CmnId = XVphy_GetRcfgChId(InstancePtr, QuadId, XVPHY_DIR_TX, PllType);
		CmnPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(CmnId)];
		TxRefClkHz = XVphy_GetQuadRefClkFreq(InstancePtr, QuadId,
								CmnPtr->PllRefClkSel);
	}
	Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, XVPHY_DRP_TXCLK25, &DrpVal);
	DrpVal &= ~(0x1F);
	DrpVal |= XVphy_DrpEncodeClk25(TxRefClkHz);
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, XVPHY_DRP_TXCLK25,
                    DrpVal);
	return Status;
}
u32 XVphy_Gtpe2TxPllRefClkDiv1Reconfig ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId ChId ) { u16 DrpVal ; u32 TxRefClkHz ; XVphy_Channel * CmnPtr ; XVphy_ChannelId CmnId ; XVphy_PllType PllType ; u32 Status = XST_SUCCESS ; if ( XVphy_IsHDMI ( InstancePtr , XVPHY_DIR_TX ) ) { TxRefClkHz = InstancePtr -> HdmiTxRefClkHz ; } else { PllType = XVphy_GetPllType ( InstancePtr , QuadId , XVPHY_DIR_TX , ChId ) ; CmnId = XVphy_GetRcfgChId ( InstancePtr , QuadId , XVPHY_DIR_TX , PllType ) ; CmnPtr = & InstancePtr -> Quads [ QuadId ] . Plls [ XVPHY_CH2IDX ( CmnId ) ] ; TxRefClkHz = XVphy_GetQuadRefClkFreq ( InstancePtr , QuadId , CmnPtr -> PllRefClkSel ) ; } Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , XVPHY_DRP_TXCLK25 , & DrpVal ) ; DrpVal &= ~ ( 0x1F ) ; DrpVal |= XVphy_DrpEncodeClk25 ( TxRefClkHz ) ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , XVPHY_DRP_TXCLK25 , DrpVal ) ; return Status ; }
This function will configure the channel's TX CLKDIV1 settings.
This function will configure the channel ' s TX CLKDIV1 settings .