src/dpdk/drivers/net/ixgbe/base/ixgbe_dcb_82599.c
s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
					   u16 *max, u8 *bwg_id, u8 *tsa)
{
	u32 reg, max_credits;
	u8  i;

	/* Clear the per-Tx queue credits; we use per-TC instead */
	for (i = 0; i < 128; i++) {
		IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
		IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
	}

	/* Configure traffic class credits and priority */
	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
		max_credits = max[i];
		reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
		reg |= (u32)(refill[i]);
		reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;

		if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
			reg |= IXGBE_RTTDT2C_GSP;

		if (tsa[i] == ixgbe_dcb_tsa_strict)
			reg |= IXGBE_RTTDT2C_LSP;

		IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
	}

	/*
	 * Configure Tx descriptor plane (recycle mode; WSP) and
	 * enable arbiter
	 */
	reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

	return IXGBE_SUCCESS;
}
/**
 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
 * @hw: pointer to hardware structure
 * @refill: refill credits index by traffic class
 * @max: max credits index by traffic class
 * @bwg_id: bandwidth grouping indexed by traffic class
 * @tsa: transmission selection algorithm indexed by traffic class
 *
 * Configure Tx Descriptor Arbiter and credits for each traffic class.
 */
Config Tx Desc.

Configure Tx Descriptor Arbiter and credits for each traffic class.
Config Tx Desc . Configure Tx Descriptor Arbiter and credits for each traffic class .
s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
					   u16 *max, u8 *bwg_id, u8 *tsa)
{
	u32 reg, max_credits;
	u8  i;
	for (i = 0; i < 128; i++) {
		IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
		IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
	}
	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
		max_credits = max[i];
		reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
		reg |= (u32)(refill[i]);
		reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
		if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
			reg |= IXGBE_RTTDT2C_GSP;
		if (tsa[i] == ixgbe_dcb_tsa_strict)
			reg |= IXGBE_RTTDT2C_LSP;
		IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
	}
	reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
	return IXGBE_SUCCESS;
}
s32 ixgbe_dcb_config_tx_desc_arbiter_82599 ( struct ixgbe_hw * hw , u16 * refill , u16 * max , u8 * bwg_id , u8 * tsa ) { u32 reg , max_credits ; u8 i ; for ( i = 0 ; i < 128 ; i ++ ) { IXGBE_WRITE_REG ( hw , IXGBE_RTTDQSEL , i ) ; IXGBE_WRITE_REG ( hw , IXGBE_RTTDT1C , 0 ) ; } for ( i = 0 ; i < IXGBE_DCB_MAX_TRAFFIC_CLASS ; i ++ ) { max_credits = max [ i ] ; reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT ; reg |= ( u32 ) ( refill [ i ] ) ; reg |= ( u32 ) ( bwg_id [ i ] ) << IXGBE_RTTDT2C_BWG_SHIFT ; if ( tsa [ i ] == ixgbe_dcb_tsa_group_strict_cee ) reg |= IXGBE_RTTDT2C_GSP ; if ( tsa [ i ] == ixgbe_dcb_tsa_strict ) reg |= IXGBE_RTTDT2C_LSP ; IXGBE_WRITE_REG ( hw , IXGBE_RTTDT2C ( i ) , reg ) ; } reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM ; IXGBE_WRITE_REG ( hw , IXGBE_RTTDCS , reg ) ; return IXGBE_SUCCESS ; }
ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc.
ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc .
/* Clear the per-Tx queue credits; we use per-TC instead */ /* Configure traffic class credits and priority */ /*
	 * Configure Tx descriptor plane (recycle mode; WSP) and
	 * enable arbiter
	 */