XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c
void XSysMon_SetAdcClkDivisor(XSysMon *InstancePtr, u8 Divisor)
{
	/*
	 * Assert the arguments.
	 */
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Write the divisor value into the Configuration Register #2.
	 */
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR2_OFFSET,
			 Divisor << XSM_CFR2_CD_SHIFT);

}
/****************************************************************************/
/**
*
* The function sets the frequency of the ADCCLK by configuring the DCLK to
* ADCCLK ratio in the Configuration Register #2.
*
* @param	InstancePtr is a pointer to the XSysMon instance.
* @param	Divisor is clock divisor used to derive ADCCLK from DCLK.
*		Valid values of the divisor are
*		 - 8 to 255 for V5 SysMon.
*		 - 0 to 255 for V6/7 Series and Zynq XADC.
*                Values 0, 1, 2 are all mapped to 2.
*		Refer to the device specification for more details.
*
* @return	None.
*
* @note		- The ADCCLK is an internal clock used by the ADC and is
*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
*		divided by the user selection in the Configuration Register 2.
*		- There is no Assert on the minimum value of the Divisor. Users
*		must take care such that the minimum value of Divisor used is
*		8, in case of V5 SysMon.
*
*****************************************************************************/
The function sets the frequency of the ADCCLK by configuring the DCLK to
ADCCLK ratio in the Configuration Register #2.
The function sets the frequency of the ADCCLK by configuring the DCLK to ADCCLK ratio in the Configuration Register #2 .
void XSysMon_SetAdcClkDivisor(XSysMon *InstancePtr, u8 Divisor)
{
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR2_OFFSET,
			 Divisor << XSM_CFR2_CD_SHIFT);
}
void XSysMon_SetAdcClkDivisor ( XSysMon * InstancePtr , u8 Divisor ) { Xil_AssertVoid ( InstancePtr != NULL ) ; Xil_AssertVoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_CFR2_OFFSET , Divisor << XSM_CFR2_CD_SHIFT ) ; }
The function sets the frequency of the ADCCLK by configuring the DCLK to
ADCCLK ratio in the Configuration Register #2.
The function sets the frequency of the ADCCLK by configuring the DCLK to ADCCLK ratio in the Configuration Register #2 .
/*
	 * Assert the arguments.
	 */ /*
	 * Write the divisor value into the Configuration Register #2.
	 */