XilinxProcessorIPLib/drivers/v_hdmitxss1/examples/xhdmi_example/video_fmc.c
void Vfmc_Gpio_Ch4_DataClock_Sel(XVfmc *VfmcPtr,
		XVfmc_Gpio_Ch4_DataClkSel DataClkSel)
{
	u32 Data;

	/* Skip if Tx Mezzanine is Active type since it is using the 4th GT
	 * channel as the TMDS Clock and Data source
	 */
	if (((DataClkSel == VFMC_GPIO_TX_CH4_As_DataAndClock) ||
		 (DataClkSel == VFMC_GPIO_TX_CH4_As_ClockOut)) &&
		(VfmcPtr->TxMezzType != VFMC_MEZZ_HDMI_PASSIVE)) {
		return;
	}

	Data = XGpio_DiscreteRead(&VfmcPtr->Gpio, 1);

	if (DataClkSel == VFMC_GPIO_TX_CH4_As_DataAndClock) {
		Data |=   0x00000004 | VFMC_GPIO_TX_LED1;
	} else if (DataClkSel == VFMC_GPIO_TX_CH4_As_ClockOut) {
		Data &= ~(0x00000004 | VFMC_GPIO_TX_LED1);
	} else if (DataClkSel == VFMC_GPIO_RX_CH4_As_Data) {
		Data |=   0x00040000 | VFMC_GPIO_RX_LED1;
	} else if (DataClkSel == VFMC_GPIO_RX_CH4_As_Clock) {
		Data &= ~(0x00040000 | VFMC_GPIO_RX_LED1);
	}

	XGpio_DiscreteWrite(&VfmcPtr->Gpio, 1, Data);

}
/*****************************************************************************/
/**
*
* This function Sets the clock or data selection for channel 4 of the
* TX or RX mezzanine cards.
*
* @param  DataClkSel - Ch4 Selection based on  XVfmc_Gpio_Ch4_DataClkSel
*                      typdef.
*                      TX
*                      --> VFMC_GPIO_TX_CH4_As_DataAndClock
*                      --> VFMC_GPIO_TX_CH4_As_ClockOut
*                      RX
*                      --> VFMC_GPIO_RX_CH4_As_Data
*                      --> VFMC_GPIO_RX_CH4_As_Clock
*
* @return None.
*
* @note   - LED1 - ON Ch4 as Data ;  OFF- Clock
* 		  - Ignore configuration of TxMezz is Active type
*
******************************************************************************/
This function Sets the clock or data selection for channel 4 of the
TX or RX mezzanine cards.
This function Sets the clock or data selection for channel 4 of the TX or RX mezzanine cards .
void Vfmc_Gpio_Ch4_DataClock_Sel(XVfmc *VfmcPtr,
		XVfmc_Gpio_Ch4_DataClkSel DataClkSel)
{
	u32 Data;
	if (((DataClkSel == VFMC_GPIO_TX_CH4_As_DataAndClock) ||
		 (DataClkSel == VFMC_GPIO_TX_CH4_As_ClockOut)) &&
		(VfmcPtr->TxMezzType != VFMC_MEZZ_HDMI_PASSIVE)) {
		return;
	}
	Data = XGpio_DiscreteRead(&VfmcPtr->Gpio, 1);
	if (DataClkSel == VFMC_GPIO_TX_CH4_As_DataAndClock) {
		Data |=   0x00000004 | VFMC_GPIO_TX_LED1;
	} else if (DataClkSel == VFMC_GPIO_TX_CH4_As_ClockOut) {
		Data &= ~(0x00000004 | VFMC_GPIO_TX_LED1);
	} else if (DataClkSel == VFMC_GPIO_RX_CH4_As_Data) {
		Data |=   0x00040000 | VFMC_GPIO_RX_LED1;
	} else if (DataClkSel == VFMC_GPIO_RX_CH4_As_Clock) {
		Data &= ~(0x00040000 | VFMC_GPIO_RX_LED1);
	}
	XGpio_DiscreteWrite(&VfmcPtr->Gpio, 1, Data);
}
void Vfmc_Gpio_Ch4_DataClock_Sel ( XVfmc * VfmcPtr , XVfmc_Gpio_Ch4_DataClkSel DataClkSel ) { u32 Data ; if ( ( ( DataClkSel == VFMC_GPIO_TX_CH4_As_DataAndClock ) || ( DataClkSel == VFMC_GPIO_TX_CH4_As_ClockOut ) ) && ( VfmcPtr -> TxMezzType != VFMC_MEZZ_HDMI_PASSIVE ) ) { return ; } Data = XGpio_DiscreteRead ( & VfmcPtr -> Gpio , 1 ) ; if ( DataClkSel == VFMC_GPIO_TX_CH4_As_DataAndClock ) { Data |= 0x00000004 | VFMC_GPIO_TX_LED1 ; } else if ( DataClkSel == VFMC_GPIO_TX_CH4_As_ClockOut ) { Data &= ~ ( 0x00000004 | VFMC_GPIO_TX_LED1 ) ; } else if ( DataClkSel == VFMC_GPIO_RX_CH4_As_Data ) { Data |= 0x00040000 | VFMC_GPIO_RX_LED1 ; } else if ( DataClkSel == VFMC_GPIO_RX_CH4_As_Clock ) { Data &= ~ ( 0x00040000 | VFMC_GPIO_RX_LED1 ) ; } XGpio_DiscreteWrite ( & VfmcPtr -> Gpio , 1 , Data ) ; }
This function Sets the clock or data selection for channel 4 of the
TX or RX mezzanine cards.
This function Sets the clock or data selection for channel 4 of the TX or RX mezzanine cards .
/* Skip if Tx Mezzanine is Active type since it is using the 4th GT
	 * channel as the TMDS Clock and Data source
	 */