XilinxProcessorIPLib/drivers/i2stx/src/xi2stx_intr.c
void XI2s_Tx_IntrHandler(void *InstancePtr)
{
	u32 Data;
	u32 EnableMask;

	/* Convert the non-typed pointer to a XI2S_Tx instance pointer */
	XI2s_Tx *TxPtr = (XI2s_Tx *)InstancePtr;

	/* Verify arguments */
	Xil_AssertVoid(TxPtr != NULL);
	Xil_AssertVoid(TxPtr->IsReady == XIL_COMPONENT_IS_READY);

	/* Read the interrupt status register */
	Data = XI2s_Tx_ReadReg(TxPtr->Config.BaseAddress,
			XI2S_TX_IRQSTS_OFFSET);

	/* Read the interrupt control register */
	EnableMask = XI2s_Tx_ReadReg(TxPtr->Config.BaseAddress,
			XI2S_TX_IRQCTRL_OFFSET);
	/* AES Block Complete Detected */
	if (Data & EnableMask & XI2S_TX_INTR_AES_BLKCMPLT_MASK) {
		/* Clear AES Block Complete event */
		XI2s_Tx_IntrClear(TxPtr, XI2S_TX_INTR_AES_BLKCMPLT_MASK);
		XI2s_Tx_LogWrite(TxPtr, XI2S_TX_AES_BLKCMPLT_EVT, 0);

		/* Call the AES Block Complete Handler */
		if (TxPtr->AesBlkCmpltHandler)
			TxPtr->AesBlkCmpltHandler(TxPtr->AesBlkCmpltRef);
	}
	/* AES Block Synchronization Error */
	if (Data & EnableMask & XI2S_TX_INTR_AES_BLKSYNCERR_MASK) {
		/* Clear AES Block Synchronization Error event */
		XI2s_Tx_IntrClear(TxPtr, XI2S_TX_INTR_AES_BLKSYNCERR_MASK);
		XI2s_Tx_LogWrite(TxPtr, XI2S_TX_AES_BLKSYNCERR_EVT, 0);

		/* Call the AES Block Synchronization Error Handler */
		if (TxPtr->AesBlkSyncErrHandler)
			TxPtr->AesBlkSyncErrHandler(TxPtr->AesBlkSyncErrRef);
	}
	/* AES Channel Status Updated */
	if (Data & EnableMask & XI2S_TX_INTR_AES_CHSTSUPD_MASK) {
		/* Clear the AES Channel Status Updated event */
		XI2s_Tx_IntrClear(TxPtr, XI2S_TX_INTR_AES_CHSTSUPD_MASK);
		XI2s_Tx_LogWrite(TxPtr, XI2S_TX_AES_CHSTSUPD_EVT, 0);

		/* Call the AES Channel Status Updated Handler */
		if (TxPtr->AesChStsUpdHandler)
			TxPtr->AesChStsUpdHandler(TxPtr->AesChStsUpdRef);
	}
	/* Audio Underflow Detected */
	if (Data & EnableMask & XI2S_TX_INTR_AUDUNDRFLW_MASK) {
		/* Clear the Audio Underflow Detected event */
		XI2s_Tx_IntrClear(TxPtr, XI2S_TX_INTR_AUDUNDRFLW_MASK);
		XI2s_Tx_LogWrite(TxPtr, XI2S_TX_AUD_UNDRFLW_EVT, 0);

		/* Call the Audio Underflow Detected Handler */
		if (TxPtr->AudUndrflwHandler)
			TxPtr->AudUndrflwHandler(TxPtr->AudUndrflwRef);
	}
}
/*****************************************************************************/
/**
 *
 * This function is the interrupt handler for the I2S Transmitter driver.
 *
 * This handler reads the pending interrupt from the I2S Transmitter peripheral,
 * determines the source of the interrupts, clears the interrupts and calls
 * callbacks accordingly.
 *
 *
 * @param InstancePtr is a pointer to the XI2s_Tx instance.
 *
 * @return None.
 *
 * @note None.
 *
 *****************************************************************************/
This function is the interrupt handler for the I2S Transmitter driver.
This handler reads the pending interrupt from the I2S Transmitter peripheral,
determines the source of the interrupts, clears the interrupts and calls
callbacks accordingly.

@param InstancePtr is a pointer to the XI2s_Tx instance.

@return None.

@note None.
This function is the interrupt handler for the I2S Transmitter driver . This handler reads the pending interrupt from the I2S Transmitter peripheral determines the source of the interrupts clears the interrupts and calls callbacks accordingly . @param InstancePtr is a pointer to the XI2s_Tx instance . @return None . @note None .
void XI2s_Tx_IntrHandler(void *InstancePtr)
{
	u32 Data;
	u32 EnableMask;
	XI2s_Tx *TxPtr = (XI2s_Tx *)InstancePtr;
	Xil_AssertVoid(TxPtr != NULL);
	Xil_AssertVoid(TxPtr->IsReady == XIL_COMPONENT_IS_READY);
	Data = XI2s_Tx_ReadReg(TxPtr->Config.BaseAddress,
			XI2S_TX_IRQSTS_OFFSET);
	EnableMask = XI2s_Tx_ReadReg(TxPtr->Config.BaseAddress,
			XI2S_TX_IRQCTRL_OFFSET);
	if (Data & EnableMask & XI2S_TX_INTR_AES_BLKCMPLT_MASK) {
		XI2s_Tx_IntrClear(TxPtr, XI2S_TX_INTR_AES_BLKCMPLT_MASK);
		XI2s_Tx_LogWrite(TxPtr, XI2S_TX_AES_BLKCMPLT_EVT, 0);
		if (TxPtr->AesBlkCmpltHandler)
			TxPtr->AesBlkCmpltHandler(TxPtr->AesBlkCmpltRef);
	}
	if (Data & EnableMask & XI2S_TX_INTR_AES_BLKSYNCERR_MASK) {
		XI2s_Tx_IntrClear(TxPtr, XI2S_TX_INTR_AES_BLKSYNCERR_MASK);
		XI2s_Tx_LogWrite(TxPtr, XI2S_TX_AES_BLKSYNCERR_EVT, 0);
		if (TxPtr->AesBlkSyncErrHandler)
			TxPtr->AesBlkSyncErrHandler(TxPtr->AesBlkSyncErrRef);
	}
	if (Data & EnableMask & XI2S_TX_INTR_AES_CHSTSUPD_MASK) {
		XI2s_Tx_IntrClear(TxPtr, XI2S_TX_INTR_AES_CHSTSUPD_MASK);
		XI2s_Tx_LogWrite(TxPtr, XI2S_TX_AES_CHSTSUPD_EVT, 0);
		if (TxPtr->AesChStsUpdHandler)
			TxPtr->AesChStsUpdHandler(TxPtr->AesChStsUpdRef);
	}
	if (Data & EnableMask & XI2S_TX_INTR_AUDUNDRFLW_MASK) {
		XI2s_Tx_IntrClear(TxPtr, XI2S_TX_INTR_AUDUNDRFLW_MASK);
		XI2s_Tx_LogWrite(TxPtr, XI2S_TX_AUD_UNDRFLW_EVT, 0);
		if (TxPtr->AudUndrflwHandler)
			TxPtr->AudUndrflwHandler(TxPtr->AudUndrflwRef);
	}
}
void XI2s_Tx_IntrHandler ( void * InstancePtr ) { u32 Data ; u32 EnableMask ; XI2s_Tx * TxPtr = ( XI2s_Tx * ) InstancePtr ; Xil_AssertVoid ( TxPtr != NULL ) ; Xil_AssertVoid ( TxPtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Data = XI2s_Tx_ReadReg ( TxPtr -> Config . BaseAddress , XI2S_TX_IRQSTS_OFFSET ) ; EnableMask = XI2s_Tx_ReadReg ( TxPtr -> Config . BaseAddress , XI2S_TX_IRQCTRL_OFFSET ) ; if ( Data & EnableMask & XI2S_TX_INTR_AES_BLKCMPLT_MASK ) { XI2s_Tx_IntrClear ( TxPtr , XI2S_TX_INTR_AES_BLKCMPLT_MASK ) ; XI2s_Tx_LogWrite ( TxPtr , XI2S_TX_AES_BLKCMPLT_EVT , 0 ) ; if ( TxPtr -> AesBlkCmpltHandler ) TxPtr -> AesBlkCmpltHandler ( TxPtr -> AesBlkCmpltRef ) ; } if ( Data & EnableMask & XI2S_TX_INTR_AES_BLKSYNCERR_MASK ) { XI2s_Tx_IntrClear ( TxPtr , XI2S_TX_INTR_AES_BLKSYNCERR_MASK ) ; XI2s_Tx_LogWrite ( TxPtr , XI2S_TX_AES_BLKSYNCERR_EVT , 0 ) ; if ( TxPtr -> AesBlkSyncErrHandler ) TxPtr -> AesBlkSyncErrHandler ( TxPtr -> AesBlkSyncErrRef ) ; } if ( Data & EnableMask & XI2S_TX_INTR_AES_CHSTSUPD_MASK ) { XI2s_Tx_IntrClear ( TxPtr , XI2S_TX_INTR_AES_CHSTSUPD_MASK ) ; XI2s_Tx_LogWrite ( TxPtr , XI2S_TX_AES_CHSTSUPD_EVT , 0 ) ; if ( TxPtr -> AesChStsUpdHandler ) TxPtr -> AesChStsUpdHandler ( TxPtr -> AesChStsUpdRef ) ; } if ( Data & EnableMask & XI2S_TX_INTR_AUDUNDRFLW_MASK ) { XI2s_Tx_IntrClear ( TxPtr , XI2S_TX_INTR_AUDUNDRFLW_MASK ) ; XI2s_Tx_LogWrite ( TxPtr , XI2S_TX_AUD_UNDRFLW_EVT , 0 ) ; if ( TxPtr -> AudUndrflwHandler ) TxPtr -> AudUndrflwHandler ( TxPtr -> AudUndrflwRef ) ; } }
This function is the interrupt handler for the I2S Transmitter driver.
This function is the interrupt handler for the I2S Transmitter driver .
/* Convert the non-typed pointer to a XI2S_Tx instance pointer */ /* Verify arguments */ /* Read the interrupt status register */ /* Read the interrupt control register */ /* AES Block Complete Detected */ /* Clear AES Block Complete event */ /* Call the AES Block Complete Handler */ /* AES Block Synchronization Error */ /* Clear AES Block Synchronization Error event */ /* Call the AES Block Synchronization Error Handler */ /* AES Channel Status Updated */ /* Clear the AES Channel Status Updated event */ /* Call the AES Channel Status Updated Handler */ /* Audio Underflow Detected */ /* Clear the Audio Underflow Detected event */ /* Call the Audio Underflow Detected Handler */