XilinxProcessorIPLib/drivers/aiengine/src/pm/xaiepm_clock.c
static u8 _XAiePm_ClockGateColumn(XAieGbl_Tile *TilePtr){

	u64 RegAddr = TilePtr->TileAddr;
	XAieGbl_Write32(RegAddr + XAIEGBL_PL_TILCLOCTRL, CLOCK_GATE_VAL);
	return XAIE_SUCCESS;
}
/************************** Function Definitions *****************************/
/*****************************************************************************/
/*
* This is an internal API to clock gate entire column if no tile in that col
* is used.
*
* @param	TilePtr - Pointer to the shim tile of the col to be gated.
*
* @return	XAIE_SUCCESS on success
*
* @note		None
*
*******************************************************************************/
Function Definitions
This is an internal API to clock gate entire column if no tile in that col
is used.
Function Definitions This is an internal API to clock gate entire column if no tile in that col is used .
static u8 _XAiePm_ClockGateColumn(XAieGbl_Tile *TilePtr){
	u64 RegAddr = TilePtr->TileAddr;
	XAieGbl_Write32(RegAddr + XAIEGBL_PL_TILCLOCTRL, CLOCK_GATE_VAL);
	return XAIE_SUCCESS;
}
static u8 _XAiePm_ClockGateColumn ( XAieGbl_Tile * TilePtr ) { u64 RegAddr = TilePtr -> TileAddr ; XAieGbl_Write32 ( RegAddr + XAIEGBL_PL_TILCLOCTRL , CLOCK_GATE_VAL ) ; return XAIE_SUCCESS ; }
Function Definitions
This is an internal API to clock gate entire column if no tile in that col
is used.
Function Definitions This is an internal API to clock gate entire column if no tile in that col is used .