XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1.c
static u32 XHdmiphy1_DrpAccess(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir,
        u16 Addr, u16 *Val)
{
	u32 RegOffsetCtrl;
	u32 RegOffsetSts;
	u32 RegVal;
	u8 Retry;

	/* Suppress Warning Messages */
	QuadId = QuadId;

	/* Determine which DRP registers to use based on channel. */
	if (XHDMIPHY1_ISCMN(ChId)) {
		RegOffsetCtrl = XHDMIPHY1_DRP_CONTROL_COMMON_REG;
		RegOffsetSts = XHDMIPHY1_DRP_STATUS_COMMON_REG;
	}
	else if (XHDMIPHY1_ISTXMMCM(ChId)) {
		RegOffsetCtrl = XHDMIPHY1_DRP_CONTROL_TXMMCM_REG;
		RegOffsetSts = XHDMIPHY1_DRP_STATUS_TXMMCM_REG;
	}
	else if (XHDMIPHY1_ISRXMMCM(ChId)) {
		RegOffsetCtrl = XHDMIPHY1_DRP_CONTROL_RXMMCM_REG;
		RegOffsetSts = XHDMIPHY1_DRP_STATUS_RXMMCM_REG;
	}
	else {
		RegOffsetCtrl = XHDMIPHY1_DRP_CONTROL_CH1_REG +
			(4 * XHDMIPHY1_CH2IDX(ChId));
		RegOffsetSts = XHDMIPHY1_DRP_STATUS_CH1_REG +
			(4 * (XHDMIPHY1_CH2IDX(ChId)));
	}

	/* Wait until the DRP status indicates that it is not busy.*/
	Retry = 0;
	do {
		RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
								RegOffsetSts);
		if (Retry > 150) {
			return XST_FAILURE;
		}
		Retry++;
	} while (RegVal & XHDMIPHY1_DRP_STATUS_DRPBUSY_MASK);

	/* Write the command to the channel's DRP. */
	RegVal = (Addr & XHDMIPHY1_DRP_CONTROL_DRPADDR_MASK);
	RegVal |= XHDMIPHY1_DRP_CONTROL_DRPEN_MASK;
	if (Dir == XHDMIPHY1_DIR_TX) {
		/* Enable write. */
		RegVal |= XHDMIPHY1_DRP_CONTROL_DRPWE_MASK;
		RegVal |= ((*Val << XHDMIPHY1_DRP_CONTROL_DRPDI_SHIFT) &
						XHDMIPHY1_DRP_CONTROL_DRPDI_MASK);
	}
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl, RegVal);

	/* Wait until the DRP status indicates ready.*/
	Retry = 0;
	do {
		RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
								RegOffsetSts);
		if (Retry > 150) {
			return XST_FAILURE;
		}
		Retry++;
	} while (!(RegVal & XHDMIPHY1_DRP_STATUS_DRPRDY_MASK));

	if (Dir == XHDMIPHY1_DIR_RX) {
		/* Mask non-data out for read. */
		RegVal &= XHDMIPHY1_DRP_STATUS_DRPO_MASK;
		/* Populate Val with read contents. */
		*Val = RegVal;
	}
	return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function will initiate a DRP transaction (either read or write).
*
* @param	InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID on which to direct the DRP access.
* @param	Dir is an indicator for write (TX) or read (RX).
* @param	Addr is the DRP address to issue the DRP access to.
* @param	Val is a pointer to the data value. In write mode, this pointer
*		will hold the value to write. In read mode, this pointer will
*		be populated with the read value.
*
* @return
*		- XST_SUCCESS if the DRP access was successful.
*		- XST_FAILURE otherwise, if the busy bit did not go low, or if
*		  the ready bit did not go high.
*
* @note		In read mode (Dir == XHDMIPHY1_DIR_RX), the data pointed to by Val
*		will be populated with the u16 value that was read._
*
******************************************************************************/
This function will initiate a DRP transaction (either read or write).
This function will initiate a DRP transaction ( either read or write ) .
static u32 XHdmiphy1_DrpAccess(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir,
        u16 Addr, u16 *Val)
{
	u32 RegOffsetCtrl;
	u32 RegOffsetSts;
	u32 RegVal;
	u8 Retry;
	QuadId = QuadId;
	if (XHDMIPHY1_ISCMN(ChId)) {
		RegOffsetCtrl = XHDMIPHY1_DRP_CONTROL_COMMON_REG;
		RegOffsetSts = XHDMIPHY1_DRP_STATUS_COMMON_REG;
	}
	else if (XHDMIPHY1_ISTXMMCM(ChId)) {
		RegOffsetCtrl = XHDMIPHY1_DRP_CONTROL_TXMMCM_REG;
		RegOffsetSts = XHDMIPHY1_DRP_STATUS_TXMMCM_REG;
	}
	else if (XHDMIPHY1_ISRXMMCM(ChId)) {
		RegOffsetCtrl = XHDMIPHY1_DRP_CONTROL_RXMMCM_REG;
		RegOffsetSts = XHDMIPHY1_DRP_STATUS_RXMMCM_REG;
	}
	else {
		RegOffsetCtrl = XHDMIPHY1_DRP_CONTROL_CH1_REG +
			(4 * XHDMIPHY1_CH2IDX(ChId));
		RegOffsetSts = XHDMIPHY1_DRP_STATUS_CH1_REG +
			(4 * (XHDMIPHY1_CH2IDX(ChId)));
	}
	Retry = 0;
	do {
		RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
								RegOffsetSts);
		if (Retry > 150) {
			return XST_FAILURE;
		}
		Retry++;
	} while (RegVal & XHDMIPHY1_DRP_STATUS_DRPBUSY_MASK);
	RegVal = (Addr & XHDMIPHY1_DRP_CONTROL_DRPADDR_MASK);
	RegVal |= XHDMIPHY1_DRP_CONTROL_DRPEN_MASK;
	if (Dir == XHDMIPHY1_DIR_TX) {
		RegVal |= XHDMIPHY1_DRP_CONTROL_DRPWE_MASK;
		RegVal |= ((*Val << XHDMIPHY1_DRP_CONTROL_DRPDI_SHIFT) &
						XHDMIPHY1_DRP_CONTROL_DRPDI_MASK);
	}
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl, RegVal);
	Retry = 0;
	do {
		RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
								RegOffsetSts);
		if (Retry > 150) {
			return XST_FAILURE;
		}
		Retry++;
	} while (!(RegVal & XHDMIPHY1_DRP_STATUS_DRPRDY_MASK));
	if (Dir == XHDMIPHY1_DIR_RX) {
		RegVal &= XHDMIPHY1_DRP_STATUS_DRPO_MASK;
		*Val = RegVal;
	}
	return XST_SUCCESS;
}
static u32 XHdmiphy1_DrpAccess ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId , XHdmiphy1_DirectionType Dir , u16 Addr , u16 * Val ) { u32 RegOffsetCtrl ; u32 RegOffsetSts ; u32 RegVal ; u8 Retry ; QuadId = QuadId ; if ( XHDMIPHY1_ISCMN ( ChId ) ) { RegOffsetCtrl = XHDMIPHY1_DRP_CONTROL_COMMON_REG ; RegOffsetSts = XHDMIPHY1_DRP_STATUS_COMMON_REG ; } else if ( XHDMIPHY1_ISTXMMCM ( ChId ) ) { RegOffsetCtrl = XHDMIPHY1_DRP_CONTROL_TXMMCM_REG ; RegOffsetSts = XHDMIPHY1_DRP_STATUS_TXMMCM_REG ; } else if ( XHDMIPHY1_ISRXMMCM ( ChId ) ) { RegOffsetCtrl = XHDMIPHY1_DRP_CONTROL_RXMMCM_REG ; RegOffsetSts = XHDMIPHY1_DRP_STATUS_RXMMCM_REG ; } else { RegOffsetCtrl = XHDMIPHY1_DRP_CONTROL_CH1_REG + ( 4 * XHDMIPHY1_CH2IDX ( ChId ) ) ; RegOffsetSts = XHDMIPHY1_DRP_STATUS_CH1_REG + ( 4 * ( XHDMIPHY1_CH2IDX ( ChId ) ) ) ; } Retry = 0 ; do { RegVal = XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , RegOffsetSts ) ; if ( Retry > 150 ) { return XST_FAILURE ; } Retry ++ ; } while ( RegVal & XHDMIPHY1_DRP_STATUS_DRPBUSY_MASK ) ; RegVal = ( Addr & XHDMIPHY1_DRP_CONTROL_DRPADDR_MASK ) ; RegVal |= XHDMIPHY1_DRP_CONTROL_DRPEN_MASK ; if ( Dir == XHDMIPHY1_DIR_TX ) { RegVal |= XHDMIPHY1_DRP_CONTROL_DRPWE_MASK ; RegVal |= ( ( * Val << XHDMIPHY1_DRP_CONTROL_DRPDI_SHIFT ) & XHDMIPHY1_DRP_CONTROL_DRPDI_MASK ) ; } XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffsetCtrl , RegVal ) ; Retry = 0 ; do { RegVal = XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , RegOffsetSts ) ; if ( Retry > 150 ) { return XST_FAILURE ; } Retry ++ ; } while ( ! ( RegVal & XHDMIPHY1_DRP_STATUS_DRPRDY_MASK ) ) ; if ( Dir == XHDMIPHY1_DIR_RX ) { RegVal &= XHDMIPHY1_DRP_STATUS_DRPO_MASK ; * Val = RegVal ; } return XST_SUCCESS ; }
This function will initiate a DRP transaction (either read or write).
This function will initiate a DRP transaction ( either read or write ) .
/* Suppress Warning Messages */ /* Determine which DRP registers to use based on channel. */ /* Wait until the DRP status indicates that it is not busy.*/ /* Write the command to the channel's DRP. */ /* Enable write. */ /* Wait until the DRP status indicates ready.*/ /* Mask non-data out for read. */ /* Populate Val with read contents. */