AllJoyn/Samples/BACnetAdapter/bacnet-stack-0.8.2/ports/xplained/ASF/xmega/drivers/twi/twim.c
status_code_t twi_master_init(TWI_t * twi,
    const twi_options_t * opt)
{
    uint8_t const ctrla =
        CONF_TWIM_INTLVL | TWI_MASTER_RIEN_bm | TWI_MASTER_WIEN_bm |
        TWI_MASTER_ENABLE_bm;

    twi->MASTER.BAUD = opt->speed_reg;
    twi->MASTER.CTRLA = ctrla;
    twi->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc;

    transfer.locked = false;
    transfer.status = STATUS_OK;

    /* Enable configured PMIC interrupt level. */

    PMIC.CTRL |= CONF_PMIC_INTLVL;

    cpu_irq_enable();

    return STATUS_OK;
}
/**
 * \brief Initialize the twi master module
 *
 * \param twi       Base address of the TWI (i.e. &TWIC).
 * \param *opt      Options for initializing the twi module
 *                  (see \ref twi_options_t)
 * \retval STATUS_OK        Transaction is successful
 * \retval ERR_INVALID_ARG  Invalid arguments in \c opt.
 */
\brief Initialize the twi master module
\param twi       Base address of the TWI .
\param *opt      Options for initializing the twi module

\retval STATUS_OK        Transaction is successful
\retval ERR_INVALID_ARG  Invalid arguments in \c opt.
\ brief Initialize the twi master module \ param twi Base address of the TWI . \ param * opt Options for initializing the twi module \ retval STATUS_OK Transaction is successful \ retval ERR_INVALID_ARG Invalid arguments in \ c opt .
status_code_t twi_master_init(TWI_t * twi,
    const twi_options_t * opt)
{
    uint8_t const ctrla =
        CONF_TWIM_INTLVL | TWI_MASTER_RIEN_bm | TWI_MASTER_WIEN_bm |
        TWI_MASTER_ENABLE_bm;
    twi->MASTER.BAUD = opt->speed_reg;
    twi->MASTER.CTRLA = ctrla;
    twi->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc;
    transfer.locked = false;
    transfer.status = STATUS_OK;
    PMIC.CTRL |= CONF_PMIC_INTLVL;
    cpu_irq_enable();
    return STATUS_OK;
}
status_code_t twi_master_init ( TWI_t * twi , const twi_options_t * opt ) { uint8_t const ctrla = CONF_TWIM_INTLVL | TWI_MASTER_RIEN_bm | TWI_MASTER_WIEN_bm | TWI_MASTER_ENABLE_bm ; twi -> MASTER . BAUD = opt -> speed_reg ; twi -> MASTER . CTRLA = ctrla ; twi -> MASTER . STATUS = TWI_MASTER_BUSSTATE_IDLE_gc ; transfer . locked = false ; transfer . status = STATUS_OK ; PMIC . CTRL |= CONF_PMIC_INTLVL ; cpu_irq_enable ( ) ; return STATUS_OK ; }
\brief Initialize the twi master module
 \param twi       Base address of the TWI (i.e.
\ brief Initialize the twi master module \ param twi Base address of the TWI ( i . e .
/* Enable configured PMIC interrupt level. */