src/dpdk/drivers/net/txgbe/txgbe_rxtx.c
static inline int
txgbe_xmit_cleanup(struct txgbe_tx_queue *txq)
{
	struct txgbe_tx_entry *sw_ring = txq->sw_ring;
	volatile struct txgbe_tx_desc *txr = txq->tx_ring;
	uint16_t last_desc_cleaned = txq->last_desc_cleaned;
	uint16_t nb_tx_desc = txq->nb_tx_desc;
	uint16_t desc_to_clean_to;
	uint16_t nb_tx_to_clean;
	uint32_t status;

	/* Determine the last descriptor needing to be cleaned */
	desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_free_thresh);
	if (desc_to_clean_to >= nb_tx_desc)
		desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);

	/* Check to make sure the last descriptor to clean is done */
	desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
	status = txr[desc_to_clean_to].dw3;
	if (!(status & rte_cpu_to_le_32(TXGBE_TXD_DD))) {
		PMD_TX_FREE_LOG(DEBUG,
				"TX descriptor %4u is not done"
				"(port=%d queue=%d)",
				desc_to_clean_to,
				txq->port_id, txq->queue_id);
		if (txq->nb_tx_free >> 1 < txq->tx_free_thresh)
			txgbe_set32_masked(txq->tdc_reg_addr,
				TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH);
		/* Failed to clean any descriptors, better luck next time */
		return -(1);
	}

	/* Figure out how many descriptors will be cleaned */
	if (last_desc_cleaned > desc_to_clean_to)
		nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
							desc_to_clean_to);
	else
		nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
						last_desc_cleaned);

	PMD_TX_FREE_LOG(DEBUG,
			"Cleaning %4u TX descriptors: %4u to %4u "
			"(port=%d queue=%d)",
			nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
			txq->port_id, txq->queue_id);

	/*
	 * The last descriptor to clean is done, so that means all the
	 * descriptors from the last descriptor that was cleaned
	 * up to the last descriptor with the RS bit set
	 * are done. Only reset the threshold descriptor.
	 */
	txr[desc_to_clean_to].dw3 = 0;

	/* Update the txq to reflect the last descriptor that was cleaned */
	txq->last_desc_cleaned = desc_to_clean_to;
	txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);

	/* No Error */
	return 0;
}
/* Reset transmit descriptors after they have been used */
Reset transmit descriptors after they have been used
Reset transmit descriptors after they have been used
static inline int
txgbe_xmit_cleanup(struct txgbe_tx_queue *txq)
{
	struct txgbe_tx_entry *sw_ring = txq->sw_ring;
	volatile struct txgbe_tx_desc *txr = txq->tx_ring;
	uint16_t last_desc_cleaned = txq->last_desc_cleaned;
	uint16_t nb_tx_desc = txq->nb_tx_desc;
	uint16_t desc_to_clean_to;
	uint16_t nb_tx_to_clean;
	uint32_t status;
	desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_free_thresh);
	if (desc_to_clean_to >= nb_tx_desc)
		desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
	desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
	status = txr[desc_to_clean_to].dw3;
	if (!(status & rte_cpu_to_le_32(TXGBE_TXD_DD))) {
		PMD_TX_FREE_LOG(DEBUG,
				"TX descriptor %4u is not done"
				"(port=%d queue=%d)",
				desc_to_clean_to,
				txq->port_id, txq->queue_id);
		if (txq->nb_tx_free >> 1 < txq->tx_free_thresh)
			txgbe_set32_masked(txq->tdc_reg_addr,
				TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH);
		return -(1);
	}
	if (last_desc_cleaned > desc_to_clean_to)
		nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
							desc_to_clean_to);
	else
		nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
						last_desc_cleaned);
	PMD_TX_FREE_LOG(DEBUG,
			"Cleaning %4u TX descriptors: %4u to %4u "
			"(port=%d queue=%d)",
			nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
			txq->port_id, txq->queue_id);
	txr[desc_to_clean_to].dw3 = 0;
	txq->last_desc_cleaned = desc_to_clean_to;
	txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
	return 0;
}
static inline int txgbe_xmit_cleanup ( struct txgbe_tx_queue * txq ) { struct txgbe_tx_entry * sw_ring = txq -> sw_ring ; volatile struct txgbe_tx_desc * txr = txq -> tx_ring ; uint16_t last_desc_cleaned = txq -> last_desc_cleaned ; uint16_t nb_tx_desc = txq -> nb_tx_desc ; uint16_t desc_to_clean_to ; uint16_t nb_tx_to_clean ; uint32_t status ; desc_to_clean_to = ( uint16_t ) ( last_desc_cleaned + txq -> tx_free_thresh ) ; if ( desc_to_clean_to >= nb_tx_desc ) desc_to_clean_to = ( uint16_t ) ( desc_to_clean_to - nb_tx_desc ) ; desc_to_clean_to = sw_ring [ desc_to_clean_to ] . last_id ; status = txr [ desc_to_clean_to ] . dw3 ; if ( ! ( status & rte_cpu_to_le_32 ( TXGBE_TXD_DD ) ) ) { PMD_TX_FREE_LOG ( DEBUG , " " " " , desc_to_clean_to , txq -> port_id , txq -> queue_id ) ; if ( txq -> nb_tx_free >> 1 < txq -> tx_free_thresh ) txgbe_set32_masked ( txq -> tdc_reg_addr , TXGBE_TXCFG_FLUSH , TXGBE_TXCFG_FLUSH ) ; return - ( 1 ) ; } if ( last_desc_cleaned > desc_to_clean_to ) nb_tx_to_clean = ( uint16_t ) ( ( nb_tx_desc - last_desc_cleaned ) + desc_to_clean_to ) ; else nb_tx_to_clean = ( uint16_t ) ( desc_to_clean_to - last_desc_cleaned ) ; PMD_TX_FREE_LOG ( DEBUG , " " " " , nb_tx_to_clean , last_desc_cleaned , desc_to_clean_to , txq -> port_id , txq -> queue_id ) ; txr [ desc_to_clean_to ] . dw3 = 0 ; txq -> last_desc_cleaned = desc_to_clean_to ; txq -> nb_tx_free = ( uint16_t ) ( txq -> nb_tx_free + nb_tx_to_clean ) ; return 0 ; }
Reset transmit descriptors after they have been used
Reset transmit descriptors after they have been used
/* Determine the last descriptor needing to be cleaned */ /* Check to make sure the last descriptor to clean is done */ /* Failed to clean any descriptors, better luck next time */ /* Figure out how many descriptors will be cleaned */ /*
	 * The last descriptor to clean is done, so that means all the
	 * descriptors from the last descriptor that was cleaned
	 * up to the last descriptor with the RS bit set
	 * are done. Only reset the threshold descriptor.
	 */ /* Update the txq to reflect the last descriptor that was cleaned */ /* No Error */