XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_hdmi_intr.c
void XHdmiphy1_HdmiTxTimerTimeoutHandler(XHdmiphy1 *InstancePtr)
{
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    XHdmiphy1_ChannelId ChId;
    XHdmiphy1_PllType PllType;
#else
	u8 CfgValComp;
#endif
    u8 Id, Id0, Id1;

    if (!InstancePtr->TxHdmi21Cfg.IsEnabled) {
        XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_TX_TMR, 1);
    }

#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    /* Determine PLL type. */
    PllType = XHdmiphy1_GetPllType(InstancePtr, 0, XHDMIPHY1_DIR_TX,
            XHDMIPHY1_CHANNEL_ID_CH1);
    /* Determine which channel(s) to operate on. */
    ChId = XHdmiphy1_GetRcfgChId(InstancePtr, 0, XHDMIPHY1_DIR_TX, PllType);

    /* Start TX MMCM. */
    XHdmiphy1_MmcmStart(InstancePtr, 0, XHDMIPHY1_DIR_TX);

    /* Enable PLL. */
    XHdmiphy1_PowerDownGtPll(InstancePtr, 0,
        (PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
        XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA, FALSE);

    if (PllType != XHDMIPHY1_PLL_TYPE_CPLL) {
        /* Set QPLL Selection in PIO. */
        XHdmiphy1_WriteCfgRefClkSelReg(InstancePtr, 0);
    }

    XHdmiphy1_ClkReconfig(InstancePtr, 0, ChId);
    XHdmiphy1_OutDivReconfig(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
            XHDMIPHY1_DIR_TX);
    if ((InstancePtr->Config.XcvrType == XHDMIPHY1_GT_TYPE_GTHE4) ||
        (InstancePtr->Config.XcvrType == XHDMIPHY1_GT_TYPE_GTYE4)) {
        XHdmiphy1_SetBufgGtDiv(InstancePtr, XHDMIPHY1_DIR_TX,
                (PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
                InstancePtr->Quads[0].Plls[0].TxOutDiv :
                (InstancePtr->Quads[0].Plls[0].TxOutDiv != 16) ?
                        InstancePtr->Quads[0].Plls[0].TxOutDiv :
                        InstancePtr->Quads[0].Plls[0].TxOutDiv / 2);
    }

    XHdmiphy1_DirReconfig(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
        XHDMIPHY1_DIR_TX);

    /* Assert PLL reset. */
    XHdmiphy1_ResetGtPll(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
            XHDMIPHY1_DIR_TX, TRUE);

    /* De-assert PLL reset. */
    XHdmiphy1_ResetGtPll(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
            XHDMIPHY1_DIR_TX, FALSE);

    if ((InstancePtr->Config.XcvrType == XHDMIPHY1_GT_TYPE_GTHE4) ||
        (InstancePtr->Config.XcvrType == XHDMIPHY1_GT_TYPE_GTYE4)) {
        /* Clear GT alignment. */
        XHdmiphy1_TxAlignStart(InstancePtr, ChId, FALSE);
    }

    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].TxState =
            XHDMIPHY1_GT_STATE_LOCK;
    }
#else
    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].TxState =
            XHDMIPHY1_GT_STATE_GPO_RE;
    }

    /* Compare the current and next CFG values */
	CfgValComp = XHdmiphy1_CheckLineRateCfg(InstancePtr, 0,
					XHDMIPHY1_CHANNEL_ID_CH1, XHDMIPHY1_DIR_TX);

	if (!CfgValComp) {
		/* Assert GPI port. */
		XHdmiphy1_SetGpi(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
				XHDMIPHY1_DIR_TX, TRUE);
	}
	else {
		XHdmiphy1_HdmiTxGpoRisingEdgeHandler(InstancePtr);
	}
#endif
}
/*****************************************************************************/
/**
* This function is the handler for TX timer timeout events.
*
* @param    InstancePtr is a pointer to the HDMIPHY instance.
*
* @return   None.
*
* @note     None.
*
******************************************************************************/
This function is the handler for TX timer timeout events.
This function is the handler for TX timer timeout events .
void XHdmiphy1_HdmiTxTimerTimeoutHandler(XHdmiphy1 *InstancePtr)
{
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    XHdmiphy1_ChannelId ChId;
    XHdmiphy1_PllType PllType;
#else
	u8 CfgValComp;
#endif
    u8 Id, Id0, Id1;
    if (!InstancePtr->TxHdmi21Cfg.IsEnabled) {
        XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_TX_TMR, 1);
    }
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    PllType = XHdmiphy1_GetPllType(InstancePtr, 0, XHDMIPHY1_DIR_TX,
            XHDMIPHY1_CHANNEL_ID_CH1);
    ChId = XHdmiphy1_GetRcfgChId(InstancePtr, 0, XHDMIPHY1_DIR_TX, PllType);
    XHdmiphy1_MmcmStart(InstancePtr, 0, XHDMIPHY1_DIR_TX);
    XHdmiphy1_PowerDownGtPll(InstancePtr, 0,
        (PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
        XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA, FALSE);
    if (PllType != XHDMIPHY1_PLL_TYPE_CPLL) {
        XHdmiphy1_WriteCfgRefClkSelReg(InstancePtr, 0);
    }
    XHdmiphy1_ClkReconfig(InstancePtr, 0, ChId);
    XHdmiphy1_OutDivReconfig(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
            XHDMIPHY1_DIR_TX);
    if ((InstancePtr->Config.XcvrType == XHDMIPHY1_GT_TYPE_GTHE4) ||
        (InstancePtr->Config.XcvrType == XHDMIPHY1_GT_TYPE_GTYE4)) {
        XHdmiphy1_SetBufgGtDiv(InstancePtr, XHDMIPHY1_DIR_TX,
                (PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
                InstancePtr->Quads[0].Plls[0].TxOutDiv :
                (InstancePtr->Quads[0].Plls[0].TxOutDiv != 16) ?
                        InstancePtr->Quads[0].Plls[0].TxOutDiv :
                        InstancePtr->Quads[0].Plls[0].TxOutDiv / 2);
    }
    XHdmiphy1_DirReconfig(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
        XHDMIPHY1_DIR_TX);
    XHdmiphy1_ResetGtPll(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
            XHDMIPHY1_DIR_TX, TRUE);
    XHdmiphy1_ResetGtPll(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
            XHDMIPHY1_DIR_TX, FALSE);
    if ((InstancePtr->Config.XcvrType == XHDMIPHY1_GT_TYPE_GTHE4) ||
        (InstancePtr->Config.XcvrType == XHDMIPHY1_GT_TYPE_GTYE4)) {
        XHdmiphy1_TxAlignStart(InstancePtr, ChId, FALSE);
    }
    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].TxState =
            XHDMIPHY1_GT_STATE_LOCK;
    }
#else
    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].TxState =
            XHDMIPHY1_GT_STATE_GPO_RE;
    }
	CfgValComp = XHdmiphy1_CheckLineRateCfg(InstancePtr, 0,
					XHDMIPHY1_CHANNEL_ID_CH1, XHDMIPHY1_DIR_TX);
	if (!CfgValComp) {
		XHdmiphy1_SetGpi(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
				XHDMIPHY1_DIR_TX, TRUE);
	}
	else {
		XHdmiphy1_HdmiTxGpoRisingEdgeHandler(InstancePtr);
	}
#endif
}
void XHdmiphy1_HdmiTxTimerTimeoutHandler ( XHdmiphy1 * InstancePtr ) { #if ( XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5 ) XHdmiphy1_ChannelId ChId ; XHdmiphy1_PllType PllType ; #else u8 CfgValComp ; #endif u8 Id , Id0 , Id1 ; if ( ! InstancePtr -> TxHdmi21Cfg . IsEnabled ) { XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_TX_TMR , 1 ) ; } #if ( XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5 ) PllType = XHdmiphy1_GetPllType ( InstancePtr , 0 , XHDMIPHY1_DIR_TX , XHDMIPHY1_CHANNEL_ID_CH1 ) ; ChId = XHdmiphy1_GetRcfgChId ( InstancePtr , 0 , XHDMIPHY1_DIR_TX , PllType ) ; XHdmiphy1_MmcmStart ( InstancePtr , 0 , XHDMIPHY1_DIR_TX ) ; XHdmiphy1_PowerDownGtPll ( InstancePtr , 0 , ( PllType == XHDMIPHY1_PLL_TYPE_CPLL ) ? XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA , FALSE ) ; if ( PllType != XHDMIPHY1_PLL_TYPE_CPLL ) { XHdmiphy1_WriteCfgRefClkSelReg ( InstancePtr , 0 ) ; } XHdmiphy1_ClkReconfig ( InstancePtr , 0 , ChId ) ; XHdmiphy1_OutDivReconfig ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_TX ) ; if ( ( InstancePtr -> Config . XcvrType == XHDMIPHY1_GT_TYPE_GTHE4 ) || ( InstancePtr -> Config . XcvrType == XHDMIPHY1_GT_TYPE_GTYE4 ) ) { XHdmiphy1_SetBufgGtDiv ( InstancePtr , XHDMIPHY1_DIR_TX , ( PllType == XHDMIPHY1_PLL_TYPE_CPLL ) ? InstancePtr -> Quads [ 0 ] . Plls [ 0 ] . TxOutDiv : ( InstancePtr -> Quads [ 0 ] . Plls [ 0 ] . TxOutDiv != 16 ) ? InstancePtr -> Quads [ 0 ] . Plls [ 0 ] . TxOutDiv : InstancePtr -> Quads [ 0 ] . Plls [ 0 ] . TxOutDiv / 2 ) ; } XHdmiphy1_DirReconfig ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_TX ) ; XHdmiphy1_ResetGtPll ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_TX , TRUE ) ; XHdmiphy1_ResetGtPll ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_TX , FALSE ) ; if ( ( InstancePtr -> Config . XcvrType == XHDMIPHY1_GT_TYPE_GTHE4 ) || ( InstancePtr -> Config . XcvrType == XHDMIPHY1_GT_TYPE_GTYE4 ) ) { XHdmiphy1_TxAlignStart ( InstancePtr , ChId , FALSE ) ; } XHdmiphy1_Ch2Ids ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . TxState = XHDMIPHY1_GT_STATE_LOCK ; } #else XHdmiphy1_Ch2Ids ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . TxState = XHDMIPHY1_GT_STATE_GPO_RE ; } CfgValComp = XHdmiphy1_CheckLineRateCfg ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CH1 , XHDMIPHY1_DIR_TX ) ; if ( ! CfgValComp ) { XHdmiphy1_SetGpi ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_TX , TRUE ) ; } else { XHdmiphy1_HdmiTxGpoRisingEdgeHandler ( InstancePtr ) ; } #endif }
This function is the handler for TX timer timeout events.
This function is the handler for TX timer timeout events .
/* Determine PLL type. */ /* Determine which channel(s) to operate on. */ /* Start TX MMCM. */ /* Enable PLL. */ /* Set QPLL Selection in PIO. */ /* Assert PLL reset. */ /* De-assert PLL reset. */ /* Clear GT alignment. */ /* Compare the current and next CFG values */ /* Assert GPI port. */