XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_gtye4.c
u32 XHdmiphy1_Gtye4CfgSetCdr(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId)
{
    XHdmiphy1_Channel *ChPtr;
    u8 RxOutDiv;
    u32 Status = XST_SUCCESS;

    /* Set CDR values only for CPLLs. */
    if ((ChId < XHDMIPHY1_CHANNEL_ID_CH1) ||
        (ChId > XHDMIPHY1_CHANNEL_ID_CH4)) {
        return XST_FAILURE;
    }

    ChPtr = &InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(ChId)];
    RxOutDiv = ChPtr->RxOutDiv;

    ChPtr->PllParams.Cdr[0] = XHDMIPHY1_RXCDR_CFG_WORD0;
    ChPtr->PllParams.Cdr[1] = XHDMIPHY1_RXCDR_CFG_WORD1;
    ChPtr->PllParams.Cdr[3] = XHDMIPHY1_RXCDR_CFG_WORD3;
    ChPtr->PllParams.Cdr[4] = XHDMIPHY1_RXCDR_CFG_WORD4;
    if (XHdmiphy1_IsHDMI(InstancePtr, XHDMIPHY1_DIR_RX)) {
        /* RxOutDiv = 1  => Cdr[2] = 0x0265
         * RxOutDiv = 2  => Cdr[2] = 0x0255
         * RxOutDiv = 4  => Cdr[2] = 0x0245
         * RxOutDiv = 8  => Cdr[2] = 0x0235
         * RxOutDiv = 16 => Cdr[2] = 0x0225 */

		ChPtr->PllParams.Cdr[2] = XHDMIPHY1_RXCDR_CFG_WORD2;

        while (RxOutDiv >>= 1) {
            ChPtr->PllParams.Cdr[2] -= XHDMIPHY1_RXCDR_CFG_WORD2_RXDIV;
        }
    }
    else {
        Status = XST_FAILURE;
    }

    return Status;
}
/*****************************************************************************/
/**
* This function will set the clock and data recovery (CDR) values for a given
* channel.
*
* @param    InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param    QuadId is the GT quad ID to operate on.
* @param    ChId is the channel ID to operate on.
*
* @return
*       - XST_SUCCESS if the configuration was successful.
*       - XST_FAILURE otherwise.
*
* @note     None.
*
******************************************************************************/
This function will set the clock and data recovery (CDR) values for a given
channel.
This function will set the clock and data recovery ( CDR ) values for a given channel .
u32 XHdmiphy1_Gtye4CfgSetCdr(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId)
{
    XHdmiphy1_Channel *ChPtr;
    u8 RxOutDiv;
    u32 Status = XST_SUCCESS;
    if ((ChId < XHDMIPHY1_CHANNEL_ID_CH1) ||
        (ChId > XHDMIPHY1_CHANNEL_ID_CH4)) {
        return XST_FAILURE;
    }
    ChPtr = &InstancePtr->Quads[QuadId].Plls[XHDMIPHY1_CH2IDX(ChId)];
    RxOutDiv = ChPtr->RxOutDiv;
    ChPtr->PllParams.Cdr[0] = XHDMIPHY1_RXCDR_CFG_WORD0;
    ChPtr->PllParams.Cdr[1] = XHDMIPHY1_RXCDR_CFG_WORD1;
    ChPtr->PllParams.Cdr[3] = XHDMIPHY1_RXCDR_CFG_WORD3;
    ChPtr->PllParams.Cdr[4] = XHDMIPHY1_RXCDR_CFG_WORD4;
    if (XHdmiphy1_IsHDMI(InstancePtr, XHDMIPHY1_DIR_RX)) {
		ChPtr->PllParams.Cdr[2] = XHDMIPHY1_RXCDR_CFG_WORD2;
        while (RxOutDiv >>= 1) {
            ChPtr->PllParams.Cdr[2] -= XHDMIPHY1_RXCDR_CFG_WORD2_RXDIV;
        }
    }
    else {
        Status = XST_FAILURE;
    }
    return Status;
}
u32 XHdmiphy1_Gtye4CfgSetCdr ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId ) { XHdmiphy1_Channel * ChPtr ; u8 RxOutDiv ; u32 Status = XST_SUCCESS ; if ( ( ChId < XHDMIPHY1_CHANNEL_ID_CH1 ) || ( ChId > XHDMIPHY1_CHANNEL_ID_CH4 ) ) { return XST_FAILURE ; } ChPtr = & InstancePtr -> Quads [ QuadId ] . Plls [ XHDMIPHY1_CH2IDX ( ChId ) ] ; RxOutDiv = ChPtr -> RxOutDiv ; ChPtr -> PllParams . Cdr [ 0 ] = XHDMIPHY1_RXCDR_CFG_WORD0 ; ChPtr -> PllParams . Cdr [ 1 ] = XHDMIPHY1_RXCDR_CFG_WORD1 ; ChPtr -> PllParams . Cdr [ 3 ] = XHDMIPHY1_RXCDR_CFG_WORD3 ; ChPtr -> PllParams . Cdr [ 4 ] = XHDMIPHY1_RXCDR_CFG_WORD4 ; if ( XHdmiphy1_IsHDMI ( InstancePtr , XHDMIPHY1_DIR_RX ) ) { ChPtr -> PllParams . Cdr [ 2 ] = XHDMIPHY1_RXCDR_CFG_WORD2 ; while ( RxOutDiv >>= 1 ) { ChPtr -> PllParams . Cdr [ 2 ] -= XHDMIPHY1_RXCDR_CFG_WORD2_RXDIV ; } } else { Status = XST_FAILURE ; } return Status ; }
This function will set the clock and data recovery (CDR) values for a given
channel.
This function will set the clock and data recovery ( CDR ) values for a given channel .
/* Set CDR values only for CPLLs. */ /* RxOutDiv = 1  => Cdr[2] = 0x0265
         * RxOutDiv = 2  => Cdr[2] = 0x0255
         * RxOutDiv = 4  => Cdr[2] = 0x0245
         * RxOutDiv = 8  => Cdr[2] = 0x0235
         * RxOutDiv = 16 => Cdr[2] = 0x0225 */