XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_hdmi.c
void XHdmiphy1_DruSetCenterFreqHz(XHdmiphy1 *InstancePtr,
        XHdmiphy1_ChannelId ChId, u64 CenterFreqHz)
{
	u32 CenterFreqL;
	u32 CenterFreqH;
	u32 RegOffset;
	u8 Id, Id0, Id1;

	/* Split the 64-bit input into 2 32-bit values. */
	CenterFreqL = (u32)CenterFreqHz;
	CenterFreqHz >>= 32;
	CenterFreqHz &= XHDMIPHY1_DRU_CFREQ_H_MASK;;
	CenterFreqH = (u32)CenterFreqHz;

	XHdmiphy1_Ch2Ids(InstancePtr, ChId, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		RegOffset = XHDMIPHY1_DRU_CFREQ_L_REG(Id);
		XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffset,
				CenterFreqL);

		RegOffset = XHDMIPHY1_DRU_CFREQ_H_REG(Id);
		XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffset,
				CenterFreqH);
	}
}
/*****************************************************************************/
/**
* This function sets the DRU center frequency.
*
* @param	InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param	ChId specifies the channel ID.
* @param	CenterFreqHz is the frequency value to set.
*
* @return	None.
*
******************************************************************************/
This function sets the DRU center frequency.
This function sets the DRU center frequency .
void XHdmiphy1_DruSetCenterFreqHz(XHdmiphy1 *InstancePtr,
        XHdmiphy1_ChannelId ChId, u64 CenterFreqHz)
{
	u32 CenterFreqL;
	u32 CenterFreqH;
	u32 RegOffset;
	u8 Id, Id0, Id1;
	CenterFreqL = (u32)CenterFreqHz;
	CenterFreqHz >>= 32;
	CenterFreqHz &= XHDMIPHY1_DRU_CFREQ_H_MASK;;
	CenterFreqH = (u32)CenterFreqHz;
	XHdmiphy1_Ch2Ids(InstancePtr, ChId, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		RegOffset = XHDMIPHY1_DRU_CFREQ_L_REG(Id);
		XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffset,
				CenterFreqL);
		RegOffset = XHDMIPHY1_DRU_CFREQ_H_REG(Id);
		XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffset,
				CenterFreqH);
	}
}
void XHdmiphy1_DruSetCenterFreqHz ( XHdmiphy1 * InstancePtr , XHdmiphy1_ChannelId ChId , u64 CenterFreqHz ) { u32 CenterFreqL ; u32 CenterFreqH ; u32 RegOffset ; u8 Id , Id0 , Id1 ; CenterFreqL = ( u32 ) CenterFreqHz ; CenterFreqHz >>= 32 ; CenterFreqHz &= XHDMIPHY1_DRU_CFREQ_H_MASK ; ; CenterFreqH = ( u32 ) CenterFreqHz ; XHdmiphy1_Ch2Ids ( InstancePtr , ChId , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { RegOffset = XHDMIPHY1_DRU_CFREQ_L_REG ( Id ) ; XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffset , CenterFreqL ) ; RegOffset = XHDMIPHY1_DRU_CFREQ_H_REG ( Id ) ; XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffset , CenterFreqH ) ; } }
This function sets the DRU center frequency.
This function sets the DRU center frequency .
/* Split the 64-bit input into 2 32-bit values. */