XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c
u64 XSysMon_GetSeqChEnables(XSysMon *InstancePtr)
{
	u32 RegValEnable;
	u32 RegValEnable1;
	u64 RetVal = 0x0;

	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Read the channel enable bits for all the channels from the ADC
	 * Channel Selection Register.
	 */
	RegValEnable = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
				XSM_SEQ00_OFFSET) & XSM_SEQ00_CH_VALID_MASK;
	RegValEnable |= (XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ01_OFFSET) & XSM_SEQ01_CH_VALID_MASK) <<
			 XSM_SEQ_CH_AUX_SHIFT;

	RegValEnable1 = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
				XSM_SEQ08_OFFSET) & XSM_SEQ08_CH_VALID_MASK;

	RetVal = RegValEnable1;
	RetVal = (RetVal << XSM_SEQ_CH_VUSR_SHIFT);
	RetVal = RetVal | RegValEnable;

	return RetVal;
}
/****************************************************************************/
/**
*
* This function gets the channel enable bits status from the ADC Channel
* Selection Sequencer Registers.
*
* @param	InstancePtr is a pointer to the XSysMon instance.
*
* @return	Gets the channel enable bits. Use XSM_SEQ_CH_* defined in
*		xsysmon_hw.h to interpret the Channel numbers. Bit masks of 1
*		are the channels that are enabled and bit mask of 0 are
*		the channels that are disabled.
*
* @return	None.
*
* @note		None.
*
*****************************************************************************/
This function gets the channel enable bits status from the ADC Channel
Selection Sequencer Registers.
This function gets the channel enable bits status from the ADC Channel Selection Sequencer Registers .
u64 XSysMon_GetSeqChEnables(XSysMon *InstancePtr)
{
	u32 RegValEnable;
	u32 RegValEnable1;
	u64 RetVal = 0x0;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	RegValEnable = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
				XSM_SEQ00_OFFSET) & XSM_SEQ00_CH_VALID_MASK;
	RegValEnable |= (XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ01_OFFSET) & XSM_SEQ01_CH_VALID_MASK) <<
			 XSM_SEQ_CH_AUX_SHIFT;
	RegValEnable1 = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
				XSM_SEQ08_OFFSET) & XSM_SEQ08_CH_VALID_MASK;
	RetVal = RegValEnable1;
	RetVal = (RetVal << XSM_SEQ_CH_VUSR_SHIFT);
	RetVal = RetVal | RegValEnable;
	return RetVal;
}
u64 XSysMon_GetSeqChEnables ( XSysMon * InstancePtr ) { u32 RegValEnable ; u32 RegValEnable1 ; u64 RetVal = 0x0 ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; RegValEnable = XSysMon_ReadReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ00_OFFSET ) & XSM_SEQ00_CH_VALID_MASK ; RegValEnable |= ( XSysMon_ReadReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ01_OFFSET ) & XSM_SEQ01_CH_VALID_MASK ) << XSM_SEQ_CH_AUX_SHIFT ; RegValEnable1 = XSysMon_ReadReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ08_OFFSET ) & XSM_SEQ08_CH_VALID_MASK ; RetVal = RegValEnable1 ; RetVal = ( RetVal << XSM_SEQ_CH_VUSR_SHIFT ) ; RetVal = RetVal | RegValEnable ; return RetVal ; }
This function gets the channel enable bits status from the ADC Channel
Selection Sequencer Registers.
This function gets the channel enable bits status from the ADC Channel Selection Sequencer Registers .
/*
	 * Assert the arguments.
	 */ /*
	 * Read the channel enable bits for all the channels from the ADC
	 * Channel Selection Register.
	 */