emlib/src/em_cmu.c
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
{
#if defined(_SILICON_LABS_32B_SERIES_1)
  CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1));

#elif defined(_SILICON_LABS_32B_SERIES_0)
  uint32_t freq;
  uint32_t divReg;

  /* Get divisor reg id */
  divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;

  switch (divReg) {
#if defined(_CMU_CTRL_HFCLKDIV_MASK)
    case CMU_HFCLKDIV_REG:
      EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_8));

      /* Configure worst case wait states for flash access before setting divisor */
      flashWaitStateMax();

      /* Set divider */
      CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK)
                  | ((div - 1) << _CMU_CTRL_HFCLKDIV_SHIFT);

      /* Update CMSIS core clock variable */
      /* (The function will update the global variable) */
      freq = SystemCoreClockGet();

      /* Optimize flash access wait state setting for current core clk */
      CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
      break;
#endif

    case CMU_HFPERCLKDIV_REG:
      EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));
      /* Convert to correct scale */
      div = CMU_DivToLog2(div);
      CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
                         | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
      break;

    case CMU_HFCORECLKDIV_REG:
      EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));

      /* Configure worst case wait states for flash access before setting divisor */
      flashWaitStateMax();

#if defined(CMU_MAX_FREQ_HFLE)
      setHfLeConfig(SystemHFClockGet() / div);
#endif

      /* Convert to correct scale */
      div = CMU_DivToLog2(div);

      CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV
                           & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
                          | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);

      /* Update CMSIS core clock variable */
      /* (The function will update the global variable) */
      freq = SystemCoreClockGet();

      /* Optimize wait state setting for current core clk */
      CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
      break;

    case CMU_LFAPRESC0_REG:
      switch (clock) {
        case cmuClock_RTC:
          EFM_ASSERT(div <= cmuClkDiv_32768);

          /* LF register about to be modified require sync. busy check */
          syncReg(CMU_SYNCBUSY_LFAPRESC0);

          /* Convert to correct scale */
          div = CMU_DivToLog2(div);

          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
                           | (div << _CMU_LFAPRESC0_RTC_SHIFT);
          break;

#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
        case cmuClock_LETIMER0:
          EFM_ASSERT(div <= cmuClkDiv_32768);

          /* LF register about to be modified require sync. busy check */
          syncReg(CMU_SYNCBUSY_LFAPRESC0);

          /* Convert to correct scale */
          div = CMU_DivToLog2(div);

          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
                           | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT);
          break;
#endif

#if defined(LCD_PRESENT)
        case cmuClock_LCDpre:
          EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128));

          /* LF register about to be modified require sync. busy check */
          syncReg(CMU_SYNCBUSY_LFAPRESC0);

          /* Convert to correct scale */
          div = CMU_DivToLog2(div);

          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)
                           | ((div - CMU_DivToLog2(cmuClkDiv_16))
                              << _CMU_LFAPRESC0_LCD_SHIFT);
          break;
#endif /* defined(LCD_PRESENT) */

#if defined(LESENSE_PRESENT)
        case cmuClock_LESENSE:
          EFM_ASSERT(div <= cmuClkDiv_8);

          /* LF register about to be modified require sync. busy check */
          syncReg(CMU_SYNCBUSY_LFAPRESC0);

          /* Convert to correct scale */
          div = CMU_DivToLog2(div);

          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
                           | (div << _CMU_LFAPRESC0_LESENSE_SHIFT);
          break;
#endif /* defined(LESENSE_PRESENT) */

        default:
          EFM_ASSERT(0);
          break;
      }
      break;

    case CMU_LFBPRESC0_REG:
      switch (clock) {
#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
        case cmuClock_LEUART0:
          EFM_ASSERT(div <= cmuClkDiv_8);

          /* LF register about to be modified require sync. busy check */
          syncReg(CMU_SYNCBUSY_LFBPRESC0);

          /* Convert to correct scale */
          div = CMU_DivToLog2(div);

          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
                           | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT);
          break;
#endif

#if defined(_CMU_LFBPRESC0_LEUART1_MASK)
        case cmuClock_LEUART1:
          EFM_ASSERT(div <= cmuClkDiv_8);

          /* LF register about to be modified require sync. busy check */
          syncReg(CMU_SYNCBUSY_LFBPRESC0);

          /* Convert to correct scale */
          div = CMU_DivToLog2(div);

          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
                           | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);
          break;
#endif

        default:
          EFM_ASSERT(0);
          break;
      }
      break;

    default:
      EFM_ASSERT(0);
      break;
  }
#endif
}
/***************************************************************************/
/**
 * @brief
 *   Set clock divisor/prescaler.
 *
 * @note
 *   If setting a LF clock prescaler, synchronization into the low frequency
 *   domain is required. If the same register is modified before a previous
 *   update has completed, this function will stall until the previous
 *   synchronization has completed. Please refer to CMU_FreezeEnable() for
 *   a suggestion on how to reduce stalling time in some use cases.
 *
 * @param[in] clock
 *   Clock point to set divisor/prescaler for. Notice that not all clock points
 *   have a divisor/prescaler, please refer to CMU overview in the reference
 *   manual.
 *
 * @param[in] div
 *   The clock divisor to use (<= cmuClkDiv_512).
 ******************************************************************************/
@brief
Set clock divisor/prescaler.

@note
If setting a LF clock prescaler, synchronization into the low frequency
domain is required. If the same register is modified before a previous
update has completed, this function will stall until the previous
synchronization has completed. Please refer to CMU_FreezeEnable() for
a suggestion on how to reduce stalling time in some use cases.

@param[in] clock
Clock point to set divisor/prescaler for. Notice that not all clock points
have a divisor/prescaler, please refer to CMU overview in the reference
manual.

@param[in] div
The clock divisor to use (<= cmuClkDiv_512).
@brief Set clock divisor / prescaler . @note If setting a LF clock prescaler synchronization into the low frequency domain is required . If the same register is modified before a previous update has completed this function will stall until the previous synchronization has completed . Please refer to CMU_FreezeEnable () for a suggestion on how to reduce stalling time in some use cases . @param [ in ] clock Clock point to set divisor / prescaler for . Notice that not all clock points have a divisor / prescaler please refer to CMU overview in the reference manual . @param [ in ] div The clock divisor to use ( < = cmuClkDiv_512 ) .
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
{
#if defined(_SILICON_LABS_32B_SERIES_1)
  CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1));
#elif defined(_SILICON_LABS_32B_SERIES_0)
  uint32_t freq;
  uint32_t divReg;
  divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
  switch (divReg) {
#if defined(_CMU_CTRL_HFCLKDIV_MASK)
    case CMU_HFCLKDIV_REG:
      EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_8));
      flashWaitStateMax();
      CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK)
                  | ((div - 1) << _CMU_CTRL_HFCLKDIV_SHIFT);
      freq = SystemCoreClockGet();
      CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
      break;
#endif
    case CMU_HFPERCLKDIV_REG:
      EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));
      div = CMU_DivToLog2(div);
      CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
                         | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
      break;
    case CMU_HFCORECLKDIV_REG:
      EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));
      flashWaitStateMax();
#if defined(CMU_MAX_FREQ_HFLE)
      setHfLeConfig(SystemHFClockGet() / div);
#endif
      div = CMU_DivToLog2(div);
      CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV
                           & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
                          | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
      freq = SystemCoreClockGet();
      CMU_UpdateWaitStates(freq, VSCALE_DEFAULT);
      break;
    case CMU_LFAPRESC0_REG:
      switch (clock) {
        case cmuClock_RTC:
          EFM_ASSERT(div <= cmuClkDiv_32768);
          syncReg(CMU_SYNCBUSY_LFAPRESC0);
          div = CMU_DivToLog2(div);
          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
                           | (div << _CMU_LFAPRESC0_RTC_SHIFT);
          break;
#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
        case cmuClock_LETIMER0:
          EFM_ASSERT(div <= cmuClkDiv_32768);
          syncReg(CMU_SYNCBUSY_LFAPRESC0);
          div = CMU_DivToLog2(div);
          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
                           | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT);
          break;
#endif
#if defined(LCD_PRESENT)
        case cmuClock_LCDpre:
          EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128));
          syncReg(CMU_SYNCBUSY_LFAPRESC0);
          div = CMU_DivToLog2(div);
          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)
                           | ((div - CMU_DivToLog2(cmuClkDiv_16))
                              << _CMU_LFAPRESC0_LCD_SHIFT);
          break;
#endif 
#if defined(LESENSE_PRESENT)
        case cmuClock_LESENSE:
          EFM_ASSERT(div <= cmuClkDiv_8);
          syncReg(CMU_SYNCBUSY_LFAPRESC0);
          div = CMU_DivToLog2(div);
          CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
                           | (div << _CMU_LFAPRESC0_LESENSE_SHIFT);
          break;
#endif 
        default:
          EFM_ASSERT(0);
          break;
      }
      break;
    case CMU_LFBPRESC0_REG:
      switch (clock) {
#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
        case cmuClock_LEUART0:
          EFM_ASSERT(div <= cmuClkDiv_8);
          syncReg(CMU_SYNCBUSY_LFBPRESC0);
          div = CMU_DivToLog2(div);
          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
                           | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT);
          break;
#endif
#if defined(_CMU_LFBPRESC0_LEUART1_MASK)
        case cmuClock_LEUART1:
          EFM_ASSERT(div <= cmuClkDiv_8);
          syncReg(CMU_SYNCBUSY_LFBPRESC0);
          div = CMU_DivToLog2(div);
          CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
                           | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);
          break;
#endif
        default:
          EFM_ASSERT(0);
          break;
      }
      break;
    default:
      EFM_ASSERT(0);
      break;
  }
#endif
}
void CMU_ClockDivSet ( CMU_Clock_TypeDef clock , CMU_ClkDiv_TypeDef div ) { #if defined ( _SILICON_LABS_32B_SERIES_1 ) CMU_ClockPrescSet ( clock , ( CMU_ClkPresc_TypeDef ) ( div - 1 ) ) ; #elif defined ( _SILICON_LABS_32B_SERIES_0 ) uint32_t freq ; uint32_t divReg ; divReg = ( clock >> CMU_DIV_REG_POS ) & CMU_DIV_REG_MASK ; switch ( divReg ) { #if defined ( _CMU_CTRL_HFCLKDIV_MASK ) case CMU_HFCLKDIV_REG : EFM_ASSERT ( ( div >= cmuClkDiv_1 ) && ( div <= cmuClkDiv_8 ) ) ; flashWaitStateMax ( ) ; CMU -> CTRL = ( CMU -> CTRL & ~ _CMU_CTRL_HFCLKDIV_MASK ) | ( ( div - 1 ) << _CMU_CTRL_HFCLKDIV_SHIFT ) ; freq = SystemCoreClockGet ( ) ; CMU_UpdateWaitStates ( freq , VSCALE_DEFAULT ) ; break ; #endif case CMU_HFPERCLKDIV_REG : EFM_ASSERT ( ( div >= cmuClkDiv_1 ) && ( div <= cmuClkDiv_512 ) ) ; div = CMU_DivToLog2 ( div ) ; CMU -> HFPERCLKDIV = ( CMU -> HFPERCLKDIV & ~ _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK ) | ( div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT ) ; break ; case CMU_HFCORECLKDIV_REG : EFM_ASSERT ( ( div >= cmuClkDiv_1 ) && ( div <= cmuClkDiv_512 ) ) ; flashWaitStateMax ( ) ; #if defined ( CMU_MAX_FREQ_HFLE ) setHfLeConfig ( SystemHFClockGet ( ) / div ) ; #endif div = CMU_DivToLog2 ( div ) ; CMU -> HFCORECLKDIV = ( CMU -> HFCORECLKDIV & ~ _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK ) | ( div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT ) ; freq = SystemCoreClockGet ( ) ; CMU_UpdateWaitStates ( freq , VSCALE_DEFAULT ) ; break ; case CMU_LFAPRESC0_REG : switch ( clock ) { case cmuClock_RTC : EFM_ASSERT ( div <= cmuClkDiv_32768 ) ; syncReg ( CMU_SYNCBUSY_LFAPRESC0 ) ; div = CMU_DivToLog2 ( div ) ; CMU -> LFAPRESC0 = ( CMU -> LFAPRESC0 & ~ _CMU_LFAPRESC0_RTC_MASK ) | ( div << _CMU_LFAPRESC0_RTC_SHIFT ) ; break ; #if defined ( _CMU_LFAPRESC0_LETIMER0_MASK ) case cmuClock_LETIMER0 : EFM_ASSERT ( div <= cmuClkDiv_32768 ) ; syncReg ( CMU_SYNCBUSY_LFAPRESC0 ) ; div = CMU_DivToLog2 ( div ) ; CMU -> LFAPRESC0 = ( CMU -> LFAPRESC0 & ~ _CMU_LFAPRESC0_LETIMER0_MASK ) | ( div << _CMU_LFAPRESC0_LETIMER0_SHIFT ) ; break ; #endif #if defined ( LCD_PRESENT ) case cmuClock_LCDpre : EFM_ASSERT ( ( div >= cmuClkDiv_16 ) && ( div <= cmuClkDiv_128 ) ) ; syncReg ( CMU_SYNCBUSY_LFAPRESC0 ) ; div = CMU_DivToLog2 ( div ) ; CMU -> LFAPRESC0 = ( CMU -> LFAPRESC0 & ~ _CMU_LFAPRESC0_LCD_MASK ) | ( ( div - CMU_DivToLog2 ( cmuClkDiv_16 ) ) << _CMU_LFAPRESC0_LCD_SHIFT ) ; break ; #endif #if defined ( LESENSE_PRESENT ) case cmuClock_LESENSE : EFM_ASSERT ( div <= cmuClkDiv_8 ) ; syncReg ( CMU_SYNCBUSY_LFAPRESC0 ) ; div = CMU_DivToLog2 ( div ) ; CMU -> LFAPRESC0 = ( CMU -> LFAPRESC0 & ~ _CMU_LFAPRESC0_LESENSE_MASK ) | ( div << _CMU_LFAPRESC0_LESENSE_SHIFT ) ; break ; #endif default : EFM_ASSERT ( 0 ) ; break ; } break ; case CMU_LFBPRESC0_REG : switch ( clock ) { #if defined ( _CMU_LFBPRESC0_LEUART0_MASK ) case cmuClock_LEUART0 : EFM_ASSERT ( div <= cmuClkDiv_8 ) ; syncReg ( CMU_SYNCBUSY_LFBPRESC0 ) ; div = CMU_DivToLog2 ( div ) ; CMU -> LFBPRESC0 = ( CMU -> LFBPRESC0 & ~ _CMU_LFBPRESC0_LEUART0_MASK ) | ( ( ( uint32_t ) div ) << _CMU_LFBPRESC0_LEUART0_SHIFT ) ; break ; #endif #if defined ( _CMU_LFBPRESC0_LEUART1_MASK ) case cmuClock_LEUART1 : EFM_ASSERT ( div <= cmuClkDiv_8 ) ; syncReg ( CMU_SYNCBUSY_LFBPRESC0 ) ; div = CMU_DivToLog2 ( div ) ; CMU -> LFBPRESC0 = ( CMU -> LFBPRESC0 & ~ _CMU_LFBPRESC0_LEUART1_MASK ) | ( ( ( uint32_t ) div ) << _CMU_LFBPRESC0_LEUART1_SHIFT ) ; break ; #endif default : EFM_ASSERT ( 0 ) ; break ; } break ; default : EFM_ASSERT ( 0 ) ; break ; } #endif }
@brief
   Set clock divisor/prescaler.
@brief Set clock divisor / prescaler .
/* Get divisor reg id */ /* Configure worst case wait states for flash access before setting divisor */ /* Set divider */ /* Update CMSIS core clock variable */ /* (The function will update the global variable) */ /* Optimize flash access wait state setting for current core clk */ /* Convert to correct scale */ /* Configure worst case wait states for flash access before setting divisor */ /* Convert to correct scale */ /* Update CMSIS core clock variable */ /* (The function will update the global variable) */ /* Optimize wait state setting for current core clk */ /* LF register about to be modified require sync. busy check */ /* Convert to correct scale */ /* LF register about to be modified require sync. busy check */ /* Convert to correct scale */ /* LF register about to be modified require sync. busy check */ /* Convert to correct scale */ /* defined(LCD_PRESENT) */ /* LF register about to be modified require sync. busy check */ /* Convert to correct scale */ /* defined(LESENSE_PRESENT) */ /* LF register about to be modified require sync. busy check */ /* Convert to correct scale */ /* LF register about to be modified require sync. busy check */ /* Convert to correct scale */