src/dpdk/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c
static inline void
print_static_reg_debug_info(void *mmio_base)
{
	uint16_t config = fpga_reg_read_16(mmio_base,
			FPGA_5GNR_FEC_CONFIGURATION);
	uint8_t qmap_done = fpga_reg_read_8(mmio_base,
			FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE);
	uint16_t lb_factor = fpga_reg_read_16(mmio_base,
			FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR);
	uint16_t ring_desc_len = fpga_reg_read_16(mmio_base,
			FPGA_5GNR_FEC_RING_DESC_LEN);
	uint16_t flr_time_out = fpga_reg_read_16(mmio_base,
			FPGA_5GNR_FEC_FLR_TIME_OUT);

	rte_bbdev_log_debug("UL.DL Weights = %u.%u",
			((uint8_t)config), ((uint8_t)(config >> 8)));
	rte_bbdev_log_debug("UL.DL Load Balance = %u.%u",
			((uint8_t)lb_factor), ((uint8_t)(lb_factor >> 8)));
	rte_bbdev_log_debug("Queue-PF/VF Mapping Table = %s",
			(qmap_done > 0) ? "READY" : "NOT-READY");
	rte_bbdev_log_debug("Ring Descriptor Size = %u bytes",
			ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES);
	rte_bbdev_log_debug("FLR Timeout = %f usec",
			(float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT);
}
/* Read Static Register of FPGA 5GNR FEC device */
Read Static Register of FPGA 5GNR FEC device
Read Static Register of FPGA 5GNR FEC device
static inline void
print_static_reg_debug_info(void *mmio_base)
{
	uint16_t config = fpga_reg_read_16(mmio_base,
			FPGA_5GNR_FEC_CONFIGURATION);
	uint8_t qmap_done = fpga_reg_read_8(mmio_base,
			FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE);
	uint16_t lb_factor = fpga_reg_read_16(mmio_base,
			FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR);
	uint16_t ring_desc_len = fpga_reg_read_16(mmio_base,
			FPGA_5GNR_FEC_RING_DESC_LEN);
	uint16_t flr_time_out = fpga_reg_read_16(mmio_base,
			FPGA_5GNR_FEC_FLR_TIME_OUT);
	rte_bbdev_log_debug("UL.DL Weights = %u.%u",
			((uint8_t)config), ((uint8_t)(config >> 8)));
	rte_bbdev_log_debug("UL.DL Load Balance = %u.%u",
			((uint8_t)lb_factor), ((uint8_t)(lb_factor >> 8)));
	rte_bbdev_log_debug("Queue-PF/VF Mapping Table = %s",
			(qmap_done > 0) ? "READY" : "NOT-READY");
	rte_bbdev_log_debug("Ring Descriptor Size = %u bytes",
			ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES);
	rte_bbdev_log_debug("FLR Timeout = %f usec",
			(float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT);
}
static inline void print_static_reg_debug_info ( void * mmio_base ) { uint16_t config = fpga_reg_read_16 ( mmio_base , FPGA_5GNR_FEC_CONFIGURATION ) ; uint8_t qmap_done = fpga_reg_read_8 ( mmio_base , FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE ) ; uint16_t lb_factor = fpga_reg_read_16 ( mmio_base , FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR ) ; uint16_t ring_desc_len = fpga_reg_read_16 ( mmio_base , FPGA_5GNR_FEC_RING_DESC_LEN ) ; uint16_t flr_time_out = fpga_reg_read_16 ( mmio_base , FPGA_5GNR_FEC_FLR_TIME_OUT ) ; rte_bbdev_log_debug ( " " , ( ( uint8_t ) config ) , ( ( uint8_t ) ( config >> 8 ) ) ) ; rte_bbdev_log_debug ( " " , ( ( uint8_t ) lb_factor ) , ( ( uint8_t ) ( lb_factor >> 8 ) ) ) ; rte_bbdev_log_debug ( " " , ( qmap_done > 0 ) ? " " : " " ) ; rte_bbdev_log_debug ( " " , ring_desc_len * FPGA_RING_DESC_LEN_UNIT_BYTES ) ; rte_bbdev_log_debug ( " " , ( float ) flr_time_out * FPGA_FLR_TIMEOUT_UNIT ) ; }
Read Static Register of FPGA 5GNR FEC device
Read Static Register of FPGA 5GNR FEC device