src/dpdk/drivers/net/ixgbe/base/ixgbe_dcb_82599.c
s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
{
	u32 i, j, fcrtl, reg;
	u8 max_tc = 0;

	/* Enable Transmit Priority Flow Control */
	IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);

	/* Enable Receive Priority Flow Control */
	reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
	reg |= IXGBE_MFLCN_DPF;

	/*
	 * X540 supports per TC Rx priority flow control.  So
	 * clear all TCs and only enable those that should be
	 * enabled.
	 */
	reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);

	if (hw->mac.type >= ixgbe_mac_X540)
		reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;

	if (pfc_en)
		reg |= IXGBE_MFLCN_RPFCE;

	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);

	for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) {
		if (map[i] > max_tc)
			max_tc = map[i];
	}


	/* Configure PFC Tx thresholds per TC */
	for (i = 0; i <= max_tc; i++) {
		int enabled = 0;

		for (j = 0; j < IXGBE_DCB_MAX_USER_PRIORITY; j++) {
			if ((map[j] == i) && (pfc_en & (1 << j))) {
				enabled = 1;
				break;
			}
		}

		if (enabled) {
			reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
		} else {
			/*
			 * In order to prevent Tx hangs when the internal Tx
			 * switch is enabled we must set the high water mark
			 * to the Rx packet buffer size - 24KB.  This allows
			 * the Tx switch to function even under heavy Rx
			 * workloads.
			 */
			reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
		}

		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
	}

	for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
		IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
	}

	/* Configure pause time (2 TCs per register) */
	reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
	for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

	/* Configure flow control refresh threshold value */
	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);

	return IXGBE_SUCCESS;
}
/**
 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
 * @hw: pointer to hardware structure
 * @pfc_en: enabled pfc bitmask
 * @map: priority to tc assignments indexed by priority
 *
 * Configure Priority Flow Control (PFC) for each traffic class.
 */
Configure priority flow control
@hw: pointer to hardware structure
@pfc_en: enabled pfc bitmask
@map: priority to tc assignments indexed by priority

Configure Priority Flow Control (PFC) for each traffic class.
Configure priority flow control @hw : pointer to hardware structure @pfc_en : enabled pfc bitmask @map : priority to tc assignments indexed by priority Configure Priority Flow Control ( PFC ) for each traffic class .
s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
{
	u32 i, j, fcrtl, reg;
	u8 max_tc = 0;
	IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);
	reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
	reg |= IXGBE_MFLCN_DPF;
	reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
	if (hw->mac.type >= ixgbe_mac_X540)
		reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
	if (pfc_en)
		reg |= IXGBE_MFLCN_RPFCE;
	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
	for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) {
		if (map[i] > max_tc)
			max_tc = map[i];
	}
	for (i = 0; i <= max_tc; i++) {
		int enabled = 0;
		for (j = 0; j < IXGBE_DCB_MAX_USER_PRIORITY; j++) {
			if ((map[j] == i) && (pfc_en & (1 << j))) {
				enabled = 1;
				break;
			}
		}
		if (enabled) {
			reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
		} else {
			reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
		}
		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
	}
	for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
		IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
	}
	reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
	for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
	return IXGBE_SUCCESS;
}
s32 ixgbe_dcb_config_pfc_82599 ( struct ixgbe_hw * hw , u8 pfc_en , u8 * map ) { u32 i , j , fcrtl , reg ; u8 max_tc = 0 ; IXGBE_WRITE_REG ( hw , IXGBE_FCCFG , IXGBE_FCCFG_TFCE_PRIORITY ) ; reg = IXGBE_READ_REG ( hw , IXGBE_MFLCN ) ; reg |= IXGBE_MFLCN_DPF ; reg &= ~ ( IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE ) ; if ( hw -> mac . type >= ixgbe_mac_X540 ) reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT ; if ( pfc_en ) reg |= IXGBE_MFLCN_RPFCE ; IXGBE_WRITE_REG ( hw , IXGBE_MFLCN , reg ) ; for ( i = 0 ; i < IXGBE_DCB_MAX_USER_PRIORITY ; i ++ ) { if ( map [ i ] > max_tc ) max_tc = map [ i ] ; } for ( i = 0 ; i <= max_tc ; i ++ ) { int enabled = 0 ; for ( j = 0 ; j < IXGBE_DCB_MAX_USER_PRIORITY ; j ++ ) { if ( ( map [ j ] == i ) && ( pfc_en & ( 1 << j ) ) ) { enabled = 1 ; break ; } } if ( enabled ) { reg = ( hw -> fc . high_water [ i ] << 10 ) | IXGBE_FCRTH_FCEN ; fcrtl = ( hw -> fc . low_water [ i ] << 10 ) | IXGBE_FCRTL_XONE ; IXGBE_WRITE_REG ( hw , IXGBE_FCRTL_82599 ( i ) , fcrtl ) ; } else { reg = IXGBE_READ_REG ( hw , IXGBE_RXPBSIZE ( i ) ) - 24576 ; IXGBE_WRITE_REG ( hw , IXGBE_FCRTL_82599 ( i ) , 0 ) ; } IXGBE_WRITE_REG ( hw , IXGBE_FCRTH_82599 ( i ) , reg ) ; } for ( ; i < IXGBE_DCB_MAX_TRAFFIC_CLASS ; i ++ ) { IXGBE_WRITE_REG ( hw , IXGBE_FCRTL_82599 ( i ) , 0 ) ; IXGBE_WRITE_REG ( hw , IXGBE_FCRTH_82599 ( i ) , 0 ) ; } reg = hw -> fc . pause_time | ( hw -> fc . pause_time << 16 ) ; for ( i = 0 ; i < ( IXGBE_DCB_MAX_TRAFFIC_CLASS / 2 ) ; i ++ ) IXGBE_WRITE_REG ( hw , IXGBE_FCTTV ( i ) , reg ) ; IXGBE_WRITE_REG ( hw , IXGBE_FCRTV , hw -> fc . pause_time / 2 ) ; return IXGBE_SUCCESS ; }
ixgbe_dcb_config_pfc_82599 - Configure priority flow control
 @hw: pointer to hardware structure
 @pfc_en: enabled pfc bitmask
 @map: priority to tc assignments indexed by priority
ixgbe_dcb_config_pfc_82599 - Configure priority flow control @hw : pointer to hardware structure @pfc_en : enabled pfc bitmask @map : priority to tc assignments indexed by priority
/* Enable Transmit Priority Flow Control */ /* Enable Receive Priority Flow Control */ /*
	 * X540 supports per TC Rx priority flow control.  So
	 * clear all TCs and only enable those that should be
	 * enabled.
	 */ /* Configure PFC Tx thresholds per TC */ /*
			 * In order to prevent Tx hangs when the internal Tx
			 * switch is enabled we must set the high water mark
			 * to the Rx packet buffer size - 24KB.  This allows
			 * the Tx switch to function even under heavy Rx
			 * workloads.
			 */ /* Configure pause time (2 TCs per register) */ /* Configure flow control refresh threshold value */