lib/sw_apps/zynqmp_fsbl/src/xfsbl_ddr_init.c
static u32 XFsbl_Ddr4Init(u8 *SpdData, struct DdrcInitData *DdrDataPtr)
{
	XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
	u32 DdrCfg[300U] = XFSBL_DDRC_REG_DEFVAL;
	u32 PhyCfg[512U] = XFSBL_PHY_REG_DEFVAL;
	u32 Status;
	u32 RegVal;

	XFsbl_ComputeDdr4Params(SpdData, DdrDataPtr);
	/* Initialize the Parameters with their default values */
	XFsbl_InitilizeDdrParams(DdrDataPtr);

	/* Assert Reset for DDR controller */
	RegVal = Xil_In32(CRF_APB_RST_DDR_SS_OFFSET);
	RegVal |= 0x00000008U;
	Xil_Out32(CRF_APB_RST_DDR_SS_OFFSET, RegVal);


	Status = XFsbl_DdrcCalcCommonRegVal(DdrDataPtr, PDimmPtr, DdrCfg);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}

	Status = XFsbl_DdrcCalcDdr4RegVal(PDimmPtr, DdrCfg);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}

	DdrCfg[DDR_DFI_TPHY_RDCSLAT] = DdrCfg[DDR_DFI_T_RDDATA_EN] - 2U;

	if (!PDimmPtr->RDimm) {
		DdrCfg[DDR_DFI_TPHY_WRCSLAT] = DdrCfg[DDR_DFI_TPHY_WRLAT] - 2U;
	}

	/* Store the MR values which will be used for PHY Registers */
	PDimmPtr->Mr = DdrCfg[DDR_MR];
	PDimmPtr->Emr = DdrCfg[DDR_EMR];
	PDimmPtr->Emr2 = DdrCfg[DDR_EMR2];
	PDimmPtr->Emr3 = DdrCfg[DDR_EMR3];
	PDimmPtr->Mr4 = DdrCfg[DDR_MR4];
	PDimmPtr->Mr5 = DdrCfg[DDR_MR5];
	PDimmPtr->Mr6 = DdrCfg[DDR_MR6];

	XFsbl_DdrcRegsWrite(PDimmPtr, DdrCfg);

	/* De-assert Reset for DDR controller */
	RegVal = Xil_In32(CRF_APB_RST_DDR_SS_OFFSET);
	RegVal &= ~0x0000000CU;
	Xil_Out32(CRF_APB_RST_DDR_SS_OFFSET, RegVal);

	Status = XFsbl_PhyCalcCommonRegVal(PDimmPtr, PhyCfg);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}

	Status = XFsbl_PhyCalcDdr4RegVal(PDimmPtr, PhyCfg);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}

	XFsbl_PhyRegsWrite(PDimmPtr, PhyCfg);

	Status = XFSBL_SUCCESS;
END:
	return Status;
}
/*****************************************************************************/
/**
 * This function calculates and writes DDR controller registers
 *
 * @param	DdrDataPtr is pointer to DDR Initialization Data Structure
 *
 * @return	None
 *
 *****************************************************************************/
This function calculates and writes DDR controller registers
@param       DdrDataPtr is pointer to DDR Initialization Data Structure

@return      None
This function calculates and writes DDR controller registers @param DdrDataPtr is pointer to DDR Initialization Data Structure @return None
static u32 XFsbl_Ddr4Init(u8 *SpdData, struct DdrcInitData *DdrDataPtr)
{
	XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
	u32 DdrCfg[300U] = XFSBL_DDRC_REG_DEFVAL;
	u32 PhyCfg[512U] = XFSBL_PHY_REG_DEFVAL;
	u32 Status;
	u32 RegVal;
	XFsbl_ComputeDdr4Params(SpdData, DdrDataPtr);
	XFsbl_InitilizeDdrParams(DdrDataPtr);
	RegVal = Xil_In32(CRF_APB_RST_DDR_SS_OFFSET);
	RegVal |= 0x00000008U;
	Xil_Out32(CRF_APB_RST_DDR_SS_OFFSET, RegVal);
	Status = XFsbl_DdrcCalcCommonRegVal(DdrDataPtr, PDimmPtr, DdrCfg);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}
	Status = XFsbl_DdrcCalcDdr4RegVal(PDimmPtr, DdrCfg);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}
	DdrCfg[DDR_DFI_TPHY_RDCSLAT] = DdrCfg[DDR_DFI_T_RDDATA_EN] - 2U;
	if (!PDimmPtr->RDimm) {
		DdrCfg[DDR_DFI_TPHY_WRCSLAT] = DdrCfg[DDR_DFI_TPHY_WRLAT] - 2U;
	}
	PDimmPtr->Mr = DdrCfg[DDR_MR];
	PDimmPtr->Emr = DdrCfg[DDR_EMR];
	PDimmPtr->Emr2 = DdrCfg[DDR_EMR2];
	PDimmPtr->Emr3 = DdrCfg[DDR_EMR3];
	PDimmPtr->Mr4 = DdrCfg[DDR_MR4];
	PDimmPtr->Mr5 = DdrCfg[DDR_MR5];
	PDimmPtr->Mr6 = DdrCfg[DDR_MR6];
	XFsbl_DdrcRegsWrite(PDimmPtr, DdrCfg);
	RegVal = Xil_In32(CRF_APB_RST_DDR_SS_OFFSET);
	RegVal &= ~0x0000000CU;
	Xil_Out32(CRF_APB_RST_DDR_SS_OFFSET, RegVal);
	Status = XFsbl_PhyCalcCommonRegVal(PDimmPtr, PhyCfg);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}
	Status = XFsbl_PhyCalcDdr4RegVal(PDimmPtr, PhyCfg);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}
	XFsbl_PhyRegsWrite(PDimmPtr, PhyCfg);
	Status = XFSBL_SUCCESS;
END:
	return Status;
}
static u32 XFsbl_Ddr4Init ( u8 * SpdData , struct DdrcInitData * DdrDataPtr ) { XFsbl_DimmParams * PDimmPtr = & DdrDataPtr -> PDimm ; u32 DdrCfg [ 300U ] = XFSBL_DDRC_REG_DEFVAL ; u32 PhyCfg [ 512U ] = XFSBL_PHY_REG_DEFVAL ; u32 Status ; u32 RegVal ; XFsbl_ComputeDdr4Params ( SpdData , DdrDataPtr ) ; XFsbl_InitilizeDdrParams ( DdrDataPtr ) ; RegVal = Xil_In32 ( CRF_APB_RST_DDR_SS_OFFSET ) ; RegVal |= 0x00000008U ; Xil_Out32 ( CRF_APB_RST_DDR_SS_OFFSET , RegVal ) ; Status = XFsbl_DdrcCalcCommonRegVal ( DdrDataPtr , PDimmPtr , DdrCfg ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } Status = XFsbl_DdrcCalcDdr4RegVal ( PDimmPtr , DdrCfg ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } DdrCfg [ DDR_DFI_TPHY_RDCSLAT ] = DdrCfg [ DDR_DFI_T_RDDATA_EN ] - 2U ; if ( ! PDimmPtr -> RDimm ) { DdrCfg [ DDR_DFI_TPHY_WRCSLAT ] = DdrCfg [ DDR_DFI_TPHY_WRLAT ] - 2U ; } PDimmPtr -> Mr = DdrCfg [ DDR_MR ] ; PDimmPtr -> Emr = DdrCfg [ DDR_EMR ] ; PDimmPtr -> Emr2 = DdrCfg [ DDR_EMR2 ] ; PDimmPtr -> Emr3 = DdrCfg [ DDR_EMR3 ] ; PDimmPtr -> Mr4 = DdrCfg [ DDR_MR4 ] ; PDimmPtr -> Mr5 = DdrCfg [ DDR_MR5 ] ; PDimmPtr -> Mr6 = DdrCfg [ DDR_MR6 ] ; XFsbl_DdrcRegsWrite ( PDimmPtr , DdrCfg ) ; RegVal = Xil_In32 ( CRF_APB_RST_DDR_SS_OFFSET ) ; RegVal &= ~ 0x0000000CU ; Xil_Out32 ( CRF_APB_RST_DDR_SS_OFFSET , RegVal ) ; Status = XFsbl_PhyCalcCommonRegVal ( PDimmPtr , PhyCfg ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } Status = XFsbl_PhyCalcDdr4RegVal ( PDimmPtr , PhyCfg ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } XFsbl_PhyRegsWrite ( PDimmPtr , PhyCfg ) ; Status = XFSBL_SUCCESS ; END : return Status ; }
This function calculates and writes DDR controller registers
 @param       DdrDataPtr is pointer to DDR Initialization Data Structure
This function calculates and writes DDR controller registers @param DdrDataPtr is pointer to DDR Initialization Data Structure
/* Initialize the Parameters with their default values */ /* Assert Reset for DDR controller */ /* Store the MR values which will be used for PHY Registers */ /* De-assert Reset for DDR controller */