XilinxProcessorIPLib/drivers/xdmapcie/examples/xdmapcie_rc_enumerate_example.c
int PcieInitRootComplex(XDmaPcie *XdmaPciePtr, u16 DeviceId)
{
	int Status;
	u32 HeaderData;
	u32 InterruptMask;
	u8  BusNumber;
	u8  DeviceNumber;
	u8  FunNumber;
	u8  PortNumber;

	XDmaPcie_Config *ConfigPtr;

	ConfigPtr = XDmaPcie_LookupConfig(DeviceId);

	Status = XDmaPcie_CfgInitialize(XdmaPciePtr, ConfigPtr,
						ConfigPtr->BaseAddress);

	if (Status != XST_SUCCESS) {
		xil_printf("Failed to initialize PCIe Root Complex"
							"IP Instance\r\n");
		return XST_FAILURE;
	}

	if(!XdmaPciePtr->Config.IncludeRootComplex) {
		xil_printf("Failed to initialize...XDMA PCIE is configured"
							" as endpoint\r\n");
		return XST_FAILURE;
	}


	/* See what interrupts are currently enabled */
	XDmaPcie_GetEnabledInterrupts(XdmaPciePtr, &InterruptMask);
	xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);

	/* Make sure all interrupts disabled. */
	XDmaPcie_DisableInterrupts(XdmaPciePtr, XDMAPCIE_IM_ENABLE_ALL_MASK);


	/* See what interrupts are currently pending */
	XDmaPcie_GetPendingInterrupts(XdmaPciePtr, &InterruptMask);
	xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);

	/* Just if there is any pending interrupt then clear it.*/
	XDmaPcie_ClearPendingInterrupts(XdmaPciePtr,
						XDMAPCIE_ID_CLEAR_ALL_MASK);

	/*
	 * Read enabled interrupts and pending interrupts
	 * to verify the previous two operations and also
	 * to test those two API functions
	 */

	XDmaPcie_GetEnabledInterrupts(XdmaPciePtr, &InterruptMask);
	xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);

	XDmaPcie_GetPendingInterrupts(XdmaPciePtr, &InterruptMask);
	xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);

	/* Make sure link is up. */
	int Retries;
	Status = FALSE;
	/* check if the link is up or not */
        for (Retries = 0; Retries < XDMAPCIE_LINK_WAIT_MAX_RETRIES; Retries++) {
		if (XDmaPcie_IsLinkUp(XdmaPciePtr)){
			Status = TRUE;
		}
                usleep(XDMAPCIE_LINK_WAIT_USLEEP_MIN);
	}
	if (Status != TRUE ) {
		xil_printf("Link is not up\r\n");
		return XST_FAILURE;
	}

	xil_printf("Link is up\r\n");

	/*
	 * Read back requester ID.
	 */
	XDmaPcie_GetRequesterId(XdmaPciePtr, &BusNumber,
				&DeviceNumber, &FunNumber, &PortNumber);

	xil_printf("Bus Number is %02X\r\n"
			"Device Number is %02X\r\n"
				"Function Number is %02X\r\n"
					"Port Number is %02X\r\n",
			BusNumber, DeviceNumber, FunNumber, PortNumber);


	/* Set up the PCIe header of this Root Complex */
	XDmaPcie_ReadLocalConfigSpace(XdmaPciePtr,
					PCIE_CFG_CMD_STATUS_REG, &HeaderData);

	HeaderData |= (PCIE_CFG_CMD_BUSM_EN | PCIE_CFG_CMD_MEM_EN |
				PCIE_CFG_CMD_IO_EN | PCIE_CFG_CMD_PARITY |
							PCIE_CFG_CMD_SERR_EN);

	XDmaPcie_WriteLocalConfigSpace(XdmaPciePtr,
					PCIE_CFG_CMD_STATUS_REG, HeaderData);

	/*
	 * Read back local config reg.
	 * to verify the write.
	 */

	XDmaPcie_ReadLocalConfigSpace(XdmaPciePtr,
					PCIE_CFG_CMD_STATUS_REG, &HeaderData);

	xil_printf("PCIe Local Config Space is %8X at register"
					" CommandStatus\r\n", HeaderData);

	/*
	 * Set up Bus number
	 */

	HeaderData = PCIE_CFG_PRIM_SEC_BUS;

	XDmaPcie_WriteLocalConfigSpace(XdmaPciePtr,
					PCIE_CFG_PRI_SEC_BUS_REG, HeaderData);

	/*
	 * Read back local config reg.
	 * to verify the write.
	 */
	XDmaPcie_ReadLocalConfigSpace(XdmaPciePtr,
					PCIE_CFG_PRI_SEC_BUS_REG, &HeaderData);

	xil_printf("PCIe Local Config Space is %8X at register "
					"Prim Sec. Bus\r\n", HeaderData);

	/* Now it is ready to function */

	xil_printf("Root Complex IP Instance has been successfully"
							" initialized\r\n");

	return XST_SUCCESS;
}
/****************************************************************************/
/**
* This function initializes a XDMA PCIe IP built as a root complex
*
*
* @param	XdmaPciePtr is a pointer to an instance of XDmaPcie data
*		structure represents a root complex IP.
* @param 	DeviceId is XDMA PCIe IP unique ID
*
* @return
*		- XST_SUCCESS if successful.
*		- XST_FAILURE if unsuccessful.
*
* @note 	None.
*
*
******************************************************************************/
This function initializes a XDMA PCIe IP built as a root complex
This function initializes a XDMA PCIe IP built as a root complex
int PcieInitRootComplex(XDmaPcie *XdmaPciePtr, u16 DeviceId)
{
	int Status;
	u32 HeaderData;
	u32 InterruptMask;
	u8  BusNumber;
	u8  DeviceNumber;
	u8  FunNumber;
	u8  PortNumber;
	XDmaPcie_Config *ConfigPtr;
	ConfigPtr = XDmaPcie_LookupConfig(DeviceId);
	Status = XDmaPcie_CfgInitialize(XdmaPciePtr, ConfigPtr,
						ConfigPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		xil_printf("Failed to initialize PCIe Root Complex"
							"IP Instance\r\n");
		return XST_FAILURE;
	}
	if(!XdmaPciePtr->Config.IncludeRootComplex) {
		xil_printf("Failed to initialize...XDMA PCIE is configured"
							" as endpoint\r\n");
		return XST_FAILURE;
	}
	XDmaPcie_GetEnabledInterrupts(XdmaPciePtr, &InterruptMask);
	xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);
	XDmaPcie_DisableInterrupts(XdmaPciePtr, XDMAPCIE_IM_ENABLE_ALL_MASK);
	XDmaPcie_GetPendingInterrupts(XdmaPciePtr, &InterruptMask);
	xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);
	XDmaPcie_ClearPendingInterrupts(XdmaPciePtr,
						XDMAPCIE_ID_CLEAR_ALL_MASK);
	XDmaPcie_GetEnabledInterrupts(XdmaPciePtr, &InterruptMask);
	xil_printf("Interrupts currently enabled are %8X\r\n", InterruptMask);
	XDmaPcie_GetPendingInterrupts(XdmaPciePtr, &InterruptMask);
	xil_printf("Interrupts currently pending are %8X\r\n", InterruptMask);
	int Retries;
	Status = FALSE;
        for (Retries = 0; Retries < XDMAPCIE_LINK_WAIT_MAX_RETRIES; Retries++) {
		if (XDmaPcie_IsLinkUp(XdmaPciePtr)){
			Status = TRUE;
		}
                usleep(XDMAPCIE_LINK_WAIT_USLEEP_MIN);
	}
	if (Status != TRUE ) {
		xil_printf("Link is not up\r\n");
		return XST_FAILURE;
	}
	xil_printf("Link is up\r\n");
	XDmaPcie_GetRequesterId(XdmaPciePtr, &BusNumber,
				&DeviceNumber, &FunNumber, &PortNumber);
	xil_printf("Bus Number is %02X\r\n"
			"Device Number is %02X\r\n"
				"Function Number is %02X\r\n"
					"Port Number is %02X\r\n",
			BusNumber, DeviceNumber, FunNumber, PortNumber);
	XDmaPcie_ReadLocalConfigSpace(XdmaPciePtr,
					PCIE_CFG_CMD_STATUS_REG, &HeaderData);
	HeaderData |= (PCIE_CFG_CMD_BUSM_EN | PCIE_CFG_CMD_MEM_EN |
				PCIE_CFG_CMD_IO_EN | PCIE_CFG_CMD_PARITY |
							PCIE_CFG_CMD_SERR_EN);
	XDmaPcie_WriteLocalConfigSpace(XdmaPciePtr,
					PCIE_CFG_CMD_STATUS_REG, HeaderData);
	XDmaPcie_ReadLocalConfigSpace(XdmaPciePtr,
					PCIE_CFG_CMD_STATUS_REG, &HeaderData);
	xil_printf("PCIe Local Config Space is %8X at register"
					" CommandStatus\r\n", HeaderData);
	HeaderData = PCIE_CFG_PRIM_SEC_BUS;
	XDmaPcie_WriteLocalConfigSpace(XdmaPciePtr,
					PCIE_CFG_PRI_SEC_BUS_REG, HeaderData);
	XDmaPcie_ReadLocalConfigSpace(XdmaPciePtr,
					PCIE_CFG_PRI_SEC_BUS_REG, &HeaderData);
	xil_printf("PCIe Local Config Space is %8X at register "
					"Prim Sec. Bus\r\n", HeaderData);
	xil_printf("Root Complex IP Instance has been successfully"
							" initialized\r\n");
	return XST_SUCCESS;
}
int PcieInitRootComplex ( XDmaPcie * XdmaPciePtr , u16 DeviceId ) { int Status ; u32 HeaderData ; u32 InterruptMask ; u8 BusNumber ; u8 DeviceNumber ; u8 FunNumber ; u8 PortNumber ; XDmaPcie_Config * ConfigPtr ; ConfigPtr = XDmaPcie_LookupConfig ( DeviceId ) ; Status = XDmaPcie_CfgInitialize ( XdmaPciePtr , ConfigPtr , ConfigPtr -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { xil_printf ( " " " \r \n " ) ; return XST_FAILURE ; } if ( ! XdmaPciePtr -> Config . IncludeRootComplex ) { xil_printf ( " " " \r \n " ) ; return XST_FAILURE ; } XDmaPcie_GetEnabledInterrupts ( XdmaPciePtr , & InterruptMask ) ; xil_printf ( " \r \n " , InterruptMask ) ; XDmaPcie_DisableInterrupts ( XdmaPciePtr , XDMAPCIE_IM_ENABLE_ALL_MASK ) ; XDmaPcie_GetPendingInterrupts ( XdmaPciePtr , & InterruptMask ) ; xil_printf ( " \r \n " , InterruptMask ) ; XDmaPcie_ClearPendingInterrupts ( XdmaPciePtr , XDMAPCIE_ID_CLEAR_ALL_MASK ) ; XDmaPcie_GetEnabledInterrupts ( XdmaPciePtr , & InterruptMask ) ; xil_printf ( " \r \n " , InterruptMask ) ; XDmaPcie_GetPendingInterrupts ( XdmaPciePtr , & InterruptMask ) ; xil_printf ( " \r \n " , InterruptMask ) ; int Retries ; Status = FALSE ; for ( Retries = 0 ; Retries < XDMAPCIE_LINK_WAIT_MAX_RETRIES ; Retries ++ ) { if ( XDmaPcie_IsLinkUp ( XdmaPciePtr ) ) { Status = TRUE ; } usleep ( XDMAPCIE_LINK_WAIT_USLEEP_MIN ) ; } if ( Status != TRUE ) { xil_printf ( " \r \n " ) ; return XST_FAILURE ; } xil_printf ( " \r \n " ) ; XDmaPcie_GetRequesterId ( XdmaPciePtr , & BusNumber , & DeviceNumber , & FunNumber , & PortNumber ) ; xil_printf ( " \r \n " " \r \n " " \r \n " " \r \n " , BusNumber , DeviceNumber , FunNumber , PortNumber ) ; XDmaPcie_ReadLocalConfigSpace ( XdmaPciePtr , PCIE_CFG_CMD_STATUS_REG , & HeaderData ) ; HeaderData |= ( PCIE_CFG_CMD_BUSM_EN | PCIE_CFG_CMD_MEM_EN | PCIE_CFG_CMD_IO_EN | PCIE_CFG_CMD_PARITY | PCIE_CFG_CMD_SERR_EN ) ; XDmaPcie_WriteLocalConfigSpace ( XdmaPciePtr , PCIE_CFG_CMD_STATUS_REG , HeaderData ) ; XDmaPcie_ReadLocalConfigSpace ( XdmaPciePtr , PCIE_CFG_CMD_STATUS_REG , & HeaderData ) ; xil_printf ( " " " \r \n " , HeaderData ) ; HeaderData = PCIE_CFG_PRIM_SEC_BUS ; XDmaPcie_WriteLocalConfigSpace ( XdmaPciePtr , PCIE_CFG_PRI_SEC_BUS_REG , HeaderData ) ; XDmaPcie_ReadLocalConfigSpace ( XdmaPciePtr , PCIE_CFG_PRI_SEC_BUS_REG , & HeaderData ) ; xil_printf ( " " " \r \n " , HeaderData ) ; xil_printf ( " " " \r \n " ) ; return XST_SUCCESS ; }
This function initializes a XDMA PCIe IP built as a root complex
This function initializes a XDMA PCIe IP built as a root complex
/* See what interrupts are currently enabled */ /* Make sure all interrupts disabled. */ /* See what interrupts are currently pending */ /* Just if there is any pending interrupt then clear it.*/ /*
	 * Read enabled interrupts and pending interrupts
	 * to verify the previous two operations and also
	 * to test those two API functions
	 */ /* Make sure link is up. */ /* check if the link is up or not */ /*
	 * Read back requester ID.
	 */ /* Set up the PCIe header of this Root Complex */ /*
	 * Read back local config reg.
	 * to verify the write.
	 */ /*
	 * Set up Bus number
	 */ /*
	 * Read back local config reg.
	 * to verify the write.
	 */ /* Now it is ready to function */