XilinxProcessorIPLib/drivers/nandps/src/xnandps.c
int XNandPs_WriteSpareBytes(XNandPs *InstancePtr, u32 Page, u8 *Buf)
{
	u32 Col;
	u32 Length;
	u32 DataPhaseAddr;
	u32 Status;

	Xil_AssertNonvoid(Buf != NULL);

	/*
	 * Bypass the ECC block in the SMC controller since
	 * we don't calculate ECC for spare bytes.
	 */
	if (InstancePtr->EccMode == XNANDPS_ECC_HW) {
		XNandPs_EccDisable(InstancePtr);
	}

	Col = InstancePtr->Geometry.BytesPerPage;
	Length = InstancePtr->Geometry.SpareBytesPerPage;

	XNandPs_SendCommand(InstancePtr, &OnfiCommands[PAGE_PROGRAM], Page, Col);

	/*
	 * Write to the spare area
	 */
	XNandPs_WriteBuf(InstancePtr, Buf, (Length -
				XNANDPS_AXI_DATA_WIDTH));
	/*
	 * Last transaction clear chip select
	 */
	DataPhaseAddr = InstancePtr->DataPhaseAddr;
	DataPhaseAddr |= XNANDPS_CLR_CS;
	InstancePtr->DataPhaseAddr = DataPhaseAddr;
	Buf += (Length - XNANDPS_AXI_DATA_WIDTH);
	XNandPs_WriteBuf(InstancePtr, Buf, XNANDPS_AXI_DATA_WIDTH);

	/*
	 * Poll the Memory controller status register for BUSY input signal
	 */
	while (XNandPs_IsBusy(InstancePtr) == TRUE) {
	}

	/*
	 * Clear the interrupt condition
	 */
	XNandPs_WriteReg((InstancePtr->Config.SmcBase +
			XNANDPS_MEMC_CLR_CONFIG_OFFSET),
			XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK);
	/*
	 * Check SR[0] bit
	 */
	Status = Onfi_CmdReadStatus(InstancePtr);
	if (Status & ONFI_STATUS_FAIL) {
		return XST_FAILURE;
	}

	/*
	 * Re-enable ECC block in the SMC controller
	 */
	if (InstancePtr->EccMode == XNANDPS_ECC_HW) {
		Status = XNandPs_EccHwInit(InstancePtr);
		if (Status != XST_SUCCESS)
			return XST_FAILURE;
	}

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function write to the spare area of a page.
*
* @param	InstancePtr is the pointer to the XNandPs instance.
* @param	Page is the page number to write.
* @param	Buf is pointer to the buffer which holds the data.
*
* @return
*		- XST_SUCCESS if successful.
*		- XST_FAILURE if fail.
*
* @note		None.
*
******************************************************************************/
This function write to the spare area of a page.
This function write to the spare area of a page .
int XNandPs_WriteSpareBytes(XNandPs *InstancePtr, u32 Page, u8 *Buf)
{
	u32 Col;
	u32 Length;
	u32 DataPhaseAddr;
	u32 Status;
	Xil_AssertNonvoid(Buf != NULL);
	if (InstancePtr->EccMode == XNANDPS_ECC_HW) {
		XNandPs_EccDisable(InstancePtr);
	}
	Col = InstancePtr->Geometry.BytesPerPage;
	Length = InstancePtr->Geometry.SpareBytesPerPage;
	XNandPs_SendCommand(InstancePtr, &OnfiCommands[PAGE_PROGRAM], Page, Col);
	XNandPs_WriteBuf(InstancePtr, Buf, (Length -
				XNANDPS_AXI_DATA_WIDTH));
	DataPhaseAddr = InstancePtr->DataPhaseAddr;
	DataPhaseAddr |= XNANDPS_CLR_CS;
	InstancePtr->DataPhaseAddr = DataPhaseAddr;
	Buf += (Length - XNANDPS_AXI_DATA_WIDTH);
	XNandPs_WriteBuf(InstancePtr, Buf, XNANDPS_AXI_DATA_WIDTH);
	while (XNandPs_IsBusy(InstancePtr) == TRUE) {
	}
	XNandPs_WriteReg((InstancePtr->Config.SmcBase +
			XNANDPS_MEMC_CLR_CONFIG_OFFSET),
			XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK);
	Status = Onfi_CmdReadStatus(InstancePtr);
	if (Status & ONFI_STATUS_FAIL) {
		return XST_FAILURE;
	}
	if (InstancePtr->EccMode == XNANDPS_ECC_HW) {
		Status = XNandPs_EccHwInit(InstancePtr);
		if (Status != XST_SUCCESS)
			return XST_FAILURE;
	}
	return XST_SUCCESS;
}
int XNandPs_WriteSpareBytes ( XNandPs * InstancePtr , u32 Page , u8 * Buf ) { u32 Col ; u32 Length ; u32 DataPhaseAddr ; u32 Status ; Xil_AssertNonvoid ( Buf != NULL ) ; if ( InstancePtr -> EccMode == XNANDPS_ECC_HW ) { XNandPs_EccDisable ( InstancePtr ) ; } Col = InstancePtr -> Geometry . BytesPerPage ; Length = InstancePtr -> Geometry . SpareBytesPerPage ; XNandPs_SendCommand ( InstancePtr , & OnfiCommands [ PAGE_PROGRAM ] , Page , Col ) ; XNandPs_WriteBuf ( InstancePtr , Buf , ( Length - XNANDPS_AXI_DATA_WIDTH ) ) ; DataPhaseAddr = InstancePtr -> DataPhaseAddr ; DataPhaseAddr |= XNANDPS_CLR_CS ; InstancePtr -> DataPhaseAddr = DataPhaseAddr ; Buf += ( Length - XNANDPS_AXI_DATA_WIDTH ) ; XNandPs_WriteBuf ( InstancePtr , Buf , XNANDPS_AXI_DATA_WIDTH ) ; while ( XNandPs_IsBusy ( InstancePtr ) == TRUE ) { } XNandPs_WriteReg ( ( InstancePtr -> Config . SmcBase + XNANDPS_MEMC_CLR_CONFIG_OFFSET ) , XNANDPS_MEMC_CLR_CONFIG_INT_CLR1_MASK ) ; Status = Onfi_CmdReadStatus ( InstancePtr ) ; if ( Status & ONFI_STATUS_FAIL ) { return XST_FAILURE ; } if ( InstancePtr -> EccMode == XNANDPS_ECC_HW ) { Status = XNandPs_EccHwInit ( InstancePtr ) ; if ( Status != XST_SUCCESS ) return XST_FAILURE ; } return XST_SUCCESS ; }
This function write to the spare area of a page.
This function write to the spare area of a page .
/*
	 * Bypass the ECC block in the SMC controller since
	 * we don't calculate ECC for spare bytes.
	 */ /*
	 * Write to the spare area
	 */ /*
	 * Last transaction clear chip select
	 */ /*
	 * Poll the Memory controller status register for BUSY input signal
	 */ /*
	 * Clear the interrupt condition
	 */ /*
	 * Check SR[0] bit
	 */ /*
	 * Re-enable ECC block in the SMC controller
	 */