XilinxProcessorIPLib/drivers/v_hdmitxss1/src/xv_hdmitxss1_frl.c
int XV_HdmiTxSs1_StartFrlTraining(XV_HdmiTxSs1 *InstancePtr,
		XHdmiC_MaxFrlRate FrlRate)
{
#ifdef XV_HDMITXSS1_LOG_ENABLE
	XV_HdmiTxSs1_LogWrite(InstancePtr, XV_HDMITXSS1_LOG_EVT_FRL_START,
			FrlRate);
#endif

	return XV_HdmiTx1_StartFrlTraining(InstancePtr->HdmiTx1Ptr,
			FrlRate);
}
/*****************************************************************************/
/**
*
* This function starts the Fixed Rate Link Training.
*
* @param    InstancePtr is a pointer to the XV_HdmiTxSs1 core instance.
*
* @param    FrlRate specifies the FRL rate to be attempted
* 			- 0 = FRL Not Supported
* 			- 1 = 3 Lanes 3Gbps
* 			- 2 = 4 Lanes 3Gbps
*			- 3 = 4 Lanes 6Gbsp
*			- 4 = 4 Lanes 8Gbps
*			- 5 = 4 Lanes 10Gbps
*			- 6 = 4 Lanes 12Gbps
*
* @return	Status on if FrlTraining can be started or not.
*
* @note     None.
*
******************************************************************************/
This function starts the Fixed Rate Link Training.
This function starts the Fixed Rate Link Training .
int XV_HdmiTxSs1_StartFrlTraining(XV_HdmiTxSs1 *InstancePtr,
		XHdmiC_MaxFrlRate FrlRate)
{
#ifdef XV_HDMITXSS1_LOG_ENABLE
	XV_HdmiTxSs1_LogWrite(InstancePtr, XV_HDMITXSS1_LOG_EVT_FRL_START,
			FrlRate);
#endif
	return XV_HdmiTx1_StartFrlTraining(InstancePtr->HdmiTx1Ptr,
			FrlRate);
}
int XV_HdmiTxSs1_StartFrlTraining ( XV_HdmiTxSs1 * InstancePtr , XHdmiC_MaxFrlRate FrlRate ) { #ifdef XV_HDMITXSS1_LOG_ENABLE XV_HdmiTxSs1_LogWrite ( InstancePtr , XV_HDMITXSS1_LOG_EVT_FRL_START , FrlRate ) ; #endif return XV_HdmiTx1_StartFrlTraining ( InstancePtr -> HdmiTx1Ptr , FrlRate ) ; }
This function starts the Fixed Rate Link Training.
This function starts the Fixed Rate Link Training .