XilinxProcessorIPLib/drivers/vphy/src/xvphy_hdmi_intr.c
void XVphy_HdmiTxClkDetFreqChangeHandler(XVphy *InstancePtr)
{
	XVphy_PllType PllType;
	u8 Id, Id0, Id1;

#if (XPAR_VPHY_0_TRANSCEIVER == XVPHY_GTXE2)
	/* Ignore TX freq change when on bonded mode. */
	if (XVphy_IsBonded(InstancePtr, 0, XVPHY_CHANNEL_ID_CH1)) {
		return;
	}
#endif

	XVphy_LogWrite(InstancePtr, XVPHY_LOG_EVT_TX_FREQ, 0);

	/* Determine PLL type. */
	PllType = XVphy_GetPllType(InstancePtr, 0, XVPHY_DIR_TX,
			XVPHY_CHANNEL_ID_CH1);

	/* Assert GT TX reset. */
	if ((InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTXE2) ||
	    (InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTPE2)) {
		XVphy_ResetGtTxRx(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_TX, TRUE);
	}

	/* If the TX frequency has changed, the PLL is always disabled. */
	if (InstancePtr->Config.XcvrType != XVPHY_GT_TYPE_GTPE2) {
		XVphy_PowerDownGtPll(InstancePtr, 0,
			(PllType == XVPHY_PLL_TYPE_CPLL) ?
			XVPHY_CHANNEL_ID_CHA : XVPHY_CHANNEL_ID_CMNA, TRUE);
	}
	XVphy_ResetGtPll(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_TX,
			TRUE);
	if (InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTXE2) {
		XVphy_GtUserRdyEnable(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
		XVPHY_DIR_TX, FALSE);
	}

	/* Mask the MMCM Lock */
	XVphy_MmcmLockedMaskEnable(InstancePtr, 0, XVPHY_DIR_TX, TRUE);

	/* Disable TX MMCM. */
	/* XVphy_MmcmPowerDown(InstancePtr, 0, XVPHY_DIR_TX, TRUE); */

	/* Clear TX timer. */
	XVphy_ClkDetTimerClear(InstancePtr, 0, XVPHY_DIR_TX);

	/* Clear GT alignment. */
	XVphy_TxAlignStart(InstancePtr, XVPHY_CHANNEL_ID_CHA, FALSE);

	/* De-assert GT TX reset. */
	if ((InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTXE2) ||
	    (InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTPE2)) {
		XVphy_ResetGtTxRx(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_TX, FALSE);
	}

	XVphy_Ch2Ids(InstancePtr, XVPHY_CHANNEL_ID_CHA, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		InstancePtr->Quads[0].Plls[XVPHY_CH2IDX(Id)].TxState =
			XVPHY_GT_STATE_IDLE;
	}

	/* If there is no reference clock, load TX timer in usec. */
	if (XVphy_ClkDetGetRefClkFreqHz(InstancePtr, XVPHY_DIR_TX)) {
		XVphy_ClkDetTimerLoad(InstancePtr, 0, XVPHY_DIR_TX,
						InstancePtr->Config.AxiLiteClkFreq/1000);
	}

	/* Callback to re-initialize. */
	if (InstancePtr->HdmiTxInitCallback) {
		InstancePtr->HdmiTxInitCallback(InstancePtr->HdmiTxInitRef);
	}
}
/*****************************************************************************/
/**
* This function is the handler for events triggered by a change in TX frequency
* as detected by the HDMI clock detector logic.
*
* @param	InstancePtr is a pointer to the VPHY instance.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function is the handler for events triggered by a change in TX frequency
as detected by the HDMI clock detector logic.
This function is the handler for events triggered by a change in TX frequency as detected by the HDMI clock detector logic .
void XVphy_HdmiTxClkDetFreqChangeHandler(XVphy *InstancePtr)
{
	XVphy_PllType PllType;
	u8 Id, Id0, Id1;
#if (XPAR_VPHY_0_TRANSCEIVER == XVPHY_GTXE2)
	if (XVphy_IsBonded(InstancePtr, 0, XVPHY_CHANNEL_ID_CH1)) {
		return;
	}
#endif
	XVphy_LogWrite(InstancePtr, XVPHY_LOG_EVT_TX_FREQ, 0);
	PllType = XVphy_GetPllType(InstancePtr, 0, XVPHY_DIR_TX,
			XVPHY_CHANNEL_ID_CH1);
	if ((InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTXE2) ||
	    (InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTPE2)) {
		XVphy_ResetGtTxRx(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_TX, TRUE);
	}
	if (InstancePtr->Config.XcvrType != XVPHY_GT_TYPE_GTPE2) {
		XVphy_PowerDownGtPll(InstancePtr, 0,
			(PllType == XVPHY_PLL_TYPE_CPLL) ?
			XVPHY_CHANNEL_ID_CHA : XVPHY_CHANNEL_ID_CMNA, TRUE);
	}
	XVphy_ResetGtPll(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_TX,
			TRUE);
	if (InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTXE2) {
		XVphy_GtUserRdyEnable(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
		XVPHY_DIR_TX, FALSE);
	}
	XVphy_MmcmLockedMaskEnable(InstancePtr, 0, XVPHY_DIR_TX, TRUE);
	XVphy_ClkDetTimerClear(InstancePtr, 0, XVPHY_DIR_TX);
	XVphy_TxAlignStart(InstancePtr, XVPHY_CHANNEL_ID_CHA, FALSE);
	if ((InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTXE2) ||
	    (InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTPE2)) {
		XVphy_ResetGtTxRx(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_TX, FALSE);
	}
	XVphy_Ch2Ids(InstancePtr, XVPHY_CHANNEL_ID_CHA, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		InstancePtr->Quads[0].Plls[XVPHY_CH2IDX(Id)].TxState =
			XVPHY_GT_STATE_IDLE;
	}
	if (XVphy_ClkDetGetRefClkFreqHz(InstancePtr, XVPHY_DIR_TX)) {
		XVphy_ClkDetTimerLoad(InstancePtr, 0, XVPHY_DIR_TX,
						InstancePtr->Config.AxiLiteClkFreq/1000);
	}
	if (InstancePtr->HdmiTxInitCallback) {
		InstancePtr->HdmiTxInitCallback(InstancePtr->HdmiTxInitRef);
	}
}
void XVphy_HdmiTxClkDetFreqChangeHandler ( XVphy * InstancePtr ) { XVphy_PllType PllType ; u8 Id , Id0 , Id1 ; #if ( XPAR_VPHY_0_TRANSCEIVER == XVPHY_GTXE2 ) if ( XVphy_IsBonded ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CH1 ) ) { return ; } #endif XVphy_LogWrite ( InstancePtr , XVPHY_LOG_EVT_TX_FREQ , 0 ) ; PllType = XVphy_GetPllType ( InstancePtr , 0 , XVPHY_DIR_TX , XVPHY_CHANNEL_ID_CH1 ) ; if ( ( InstancePtr -> Config . XcvrType == XVPHY_GT_TYPE_GTXE2 ) || ( InstancePtr -> Config . XcvrType == XVPHY_GT_TYPE_GTPE2 ) ) { XVphy_ResetGtTxRx ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_TX , TRUE ) ; } if ( InstancePtr -> Config . XcvrType != XVPHY_GT_TYPE_GTPE2 ) { XVphy_PowerDownGtPll ( InstancePtr , 0 , ( PllType == XVPHY_PLL_TYPE_CPLL ) ? XVPHY_CHANNEL_ID_CHA : XVPHY_CHANNEL_ID_CMNA , TRUE ) ; } XVphy_ResetGtPll ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_TX , TRUE ) ; if ( InstancePtr -> Config . XcvrType == XVPHY_GT_TYPE_GTXE2 ) { XVphy_GtUserRdyEnable ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_TX , FALSE ) ; } XVphy_MmcmLockedMaskEnable ( InstancePtr , 0 , XVPHY_DIR_TX , TRUE ) ; XVphy_ClkDetTimerClear ( InstancePtr , 0 , XVPHY_DIR_TX ) ; XVphy_TxAlignStart ( InstancePtr , XVPHY_CHANNEL_ID_CHA , FALSE ) ; if ( ( InstancePtr -> Config . XcvrType == XVPHY_GT_TYPE_GTXE2 ) || ( InstancePtr -> Config . XcvrType == XVPHY_GT_TYPE_GTPE2 ) ) { XVphy_ResetGtTxRx ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_TX , FALSE ) ; } XVphy_Ch2Ids ( InstancePtr , XVPHY_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XVPHY_CH2IDX ( Id ) ] . TxState = XVPHY_GT_STATE_IDLE ; } if ( XVphy_ClkDetGetRefClkFreqHz ( InstancePtr , XVPHY_DIR_TX ) ) { XVphy_ClkDetTimerLoad ( InstancePtr , 0 , XVPHY_DIR_TX , InstancePtr -> Config . AxiLiteClkFreq / 1000 ) ; } if ( InstancePtr -> HdmiTxInitCallback ) { InstancePtr -> HdmiTxInitCallback ( InstancePtr -> HdmiTxInitRef ) ; } }
This function is the handler for events triggered by a change in TX frequency
as detected by the HDMI clock detector logic.
This function is the handler for events triggered by a change in TX frequency as detected by the HDMI clock detector logic .
/* Ignore TX freq change when on bonded mode. */ /* Determine PLL type. */ /* Assert GT TX reset. */ /* If the TX frequency has changed, the PLL is always disabled. */ /* Mask the MMCM Lock */ /* Disable TX MMCM. */ /* XVphy_MmcmPowerDown(InstancePtr, 0, XVPHY_DIR_TX, TRUE); */ /* Clear TX timer. */ /* Clear GT alignment. */ /* De-assert GT TX reset. */ /* If there is no reference clock, load TX timer in usec. */ /* Callback to re-initialize. */