XilinxProcessorIPLib/drivers/intc/src/xintc.c
static void XIntc_InitializeSlaves(XIntc * InstancePtr)
{
	int Index;
	u32 Mask;
	XIntc_Config *CfgPtr;
	int Id;

	Mask = XIntc_BitPosMask[31]; /* Convert from integer id to bit mask */

	/* Enable interrupt id with 31 for Master
	 * interrupt controller
	 */
	XIntc_Out32(InstancePtr->CfgPtr->BaseAddress + XIN_IER_OFFSET, Mask);

	for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1; Index++) {
		CfgPtr = XIntc_LookupConfig(Index);
		if (CfgPtr == NULL) {
			return;
		}

		XIntc_Out32(CfgPtr->BaseAddress + XIN_IAR_OFFSET,
							0xFFFFFFFF);
		if (CfgPtr->IntcType != XIN_INTC_LAST) {

			/* Enable interrupt ids with 31 for secondary
			 * interrupt controllers
			 */
			XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
									Mask);
		} else {
			XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET, 0x0);
		}

		/* Disable Interrupt output */
		XIntc_Out32(CfgPtr->BaseAddress + XIN_MER_OFFSET, 0);

		/* Set all interrupts as normal mode if Fast Interrupts
		 * are enabled
		 */
		if(CfgPtr->FastIntr == TRUE) {
			XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0);

#ifdef XPAR_MICROBLAZE_BASE_VECTORS
			if (CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
				for (Id = 0; Id < 32 ; Id++)
				{
					XIntc_Out64(CfgPtr->BaseAddress +
						XIN_IVEAR_OFFSET + (Id * 8),
						XPAR_MICROBLAZE_BASE_VECTORS + 0x10);
				}
			} else {
				for (Id = 0; Id < 32 ; Id++)
				{
					XIntc_Out32(CfgPtr->BaseAddress +
						XIN_IVAR_OFFSET + (Id * 4),
						XPAR_MICROBLAZE_BASE_VECTORS + 0x10);
				}
			}
#else
			if (CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
				for (Id = 0; Id < 32 ; Id++)
				{
					XIntc_Out64(CfgPtr->BaseAddress +
						XIN_IVEAR_OFFSET + (Id * 8), 0x10);
				}
			} else {
				for (Id = 0; Id < 32 ; Id++)
				{
					XIntc_Out32(CfgPtr->BaseAddress +
						XIN_IVAR_OFFSET + (Id * 4), 0x10);
				}
			}
#endif
		}

		/*
		 * Initialize all the data needed to perform interrupt
		 * processing for each interrupt ID up to the maximum used
		 */
		for (Id = 0; Id < (CfgPtr->NumberofIntrs + CfgPtr->NumberofSwIntrs); Id++) {

			/*
			 * Initialize the handler to point to a stub to handle an
			 * interrupt which has not been connected to a handler.
			 * Only initialize it if the handler is 0 or
			 * XNullHandler, which means it was not initialized
			 * statically by the tools/user.Set the callback
			 * reference to this instance so that unhandled
			 * interrupts can be tracked.
			 */
			if ((CfgPtr->HandlerTable[Id].Handler == 0) ||
				    (CfgPtr->HandlerTable[Id].Handler ==
				     XNullHandler)) {
				CfgPtr->HandlerTable[Id].Handler = StubHandler;
			}
			CfgPtr->HandlerTable[Id].CallBackRef = InstancePtr;
		}
	}
}
/*****************************************************************************/
/**
*
* Initializes Slave controllers in Cascade mode. The initialization entails:
*	- Initial vector table with stub function calls
*	- All interrupt sources are disabled for last controller.
*	- All interrupt sources are disabled except sources to 31 pin of
*	  primary and secondary controllers
*	- Interrupt outputs are disabled
*
* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
*
* @return	None
*
* @note		None.
*
******************************************************************************/
Initializes Slave controllers in Cascade mode. The initialization entails:
Initial vector table with stub function calls
All interrupt sources are disabled for last controller.
All interrupt sources are disabled except sources to 31 pin of
primary and secondary controllers
Interrupt outputs are disabled
Initializes Slave controllers in Cascade mode . The initialization entails : Initial vector table with stub function calls All interrupt sources are disabled for last controller . All interrupt sources are disabled except sources to 31 pin of primary and secondary controllers Interrupt outputs are disabled
static void XIntc_InitializeSlaves(XIntc * InstancePtr)
{
	int Index;
	u32 Mask;
	XIntc_Config *CfgPtr;
	int Id;
	Mask = XIntc_BitPosMask[31]; 
	XIntc_Out32(InstancePtr->CfgPtr->BaseAddress + XIN_IER_OFFSET, Mask);
	for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1; Index++) {
		CfgPtr = XIntc_LookupConfig(Index);
		if (CfgPtr == NULL) {
			return;
		}
		XIntc_Out32(CfgPtr->BaseAddress + XIN_IAR_OFFSET,
							0xFFFFFFFF);
		if (CfgPtr->IntcType != XIN_INTC_LAST) {
			XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET,
									Mask);
		} else {
			XIntc_Out32(CfgPtr->BaseAddress + XIN_IER_OFFSET, 0x0);
		}
		XIntc_Out32(CfgPtr->BaseAddress + XIN_MER_OFFSET, 0);
		if(CfgPtr->FastIntr == TRUE) {
			XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0);
#ifdef XPAR_MICROBLAZE_BASE_VECTORS
			if (CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
				for (Id = 0; Id < 32 ; Id++)
				{
					XIntc_Out64(CfgPtr->BaseAddress +
						XIN_IVEAR_OFFSET + (Id * 8),
						XPAR_MICROBLAZE_BASE_VECTORS + 0x10);
				}
			} else {
				for (Id = 0; Id < 32 ; Id++)
				{
					XIntc_Out32(CfgPtr->BaseAddress +
						XIN_IVAR_OFFSET + (Id * 4),
						XPAR_MICROBLAZE_BASE_VECTORS + 0x10);
				}
			}
#else
			if (CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
				for (Id = 0; Id < 32 ; Id++)
				{
					XIntc_Out64(CfgPtr->BaseAddress +
						XIN_IVEAR_OFFSET + (Id * 8), 0x10);
				}
			} else {
				for (Id = 0; Id < 32 ; Id++)
				{
					XIntc_Out32(CfgPtr->BaseAddress +
						XIN_IVAR_OFFSET + (Id * 4), 0x10);
				}
			}
#endif
		}
		for (Id = 0; Id < (CfgPtr->NumberofIntrs + CfgPtr->NumberofSwIntrs); Id++) {
			if ((CfgPtr->HandlerTable[Id].Handler == 0) ||
				    (CfgPtr->HandlerTable[Id].Handler ==
				     XNullHandler)) {
				CfgPtr->HandlerTable[Id].Handler = StubHandler;
			}
			CfgPtr->HandlerTable[Id].CallBackRef = InstancePtr;
		}
	}
}
static void XIntc_InitializeSlaves ( XIntc * InstancePtr ) { int Index ; u32 Mask ; XIntc_Config * CfgPtr ; int Id ; Mask = XIntc_BitPosMask [ 31 ] ; XIntc_Out32 ( InstancePtr -> CfgPtr -> BaseAddress + XIN_IER_OFFSET , Mask ) ; for ( Index = 1 ; Index <= XPAR_XINTC_NUM_INSTANCES - 1 ; Index ++ ) { CfgPtr = XIntc_LookupConfig ( Index ) ; if ( CfgPtr == NULL ) { return ; } XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_IAR_OFFSET , 0xFFFFFFFF ) ; if ( CfgPtr -> IntcType != XIN_INTC_LAST ) { XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_IER_OFFSET , Mask ) ; } else { XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_IER_OFFSET , 0x0 ) ; } XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_MER_OFFSET , 0 ) ; if ( CfgPtr -> FastIntr == TRUE ) { XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_IMR_OFFSET , 0 ) ; #ifdef XPAR_MICROBLAZE_BASE_VECTORS if ( CfgPtr -> VectorAddrWidth > XINTC_STANDARD_VECTOR_ADDRESS_WIDTH ) { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out64 ( CfgPtr -> BaseAddress + XIN_IVEAR_OFFSET + ( Id * 8 ) , XPAR_MICROBLAZE_BASE_VECTORS + 0x10 ) ; } } else { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_IVAR_OFFSET + ( Id * 4 ) , XPAR_MICROBLAZE_BASE_VECTORS + 0x10 ) ; } } #else if ( CfgPtr -> VectorAddrWidth > XINTC_STANDARD_VECTOR_ADDRESS_WIDTH ) { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out64 ( CfgPtr -> BaseAddress + XIN_IVEAR_OFFSET + ( Id * 8 ) , 0x10 ) ; } } else { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_IVAR_OFFSET + ( Id * 4 ) , 0x10 ) ; } } #endif } for ( Id = 0 ; Id < ( CfgPtr -> NumberofIntrs + CfgPtr -> NumberofSwIntrs ) ; Id ++ ) { if ( ( CfgPtr -> HandlerTable [ Id ] . Handler == 0 ) || ( CfgPtr -> HandlerTable [ Id ] . Handler == XNullHandler ) ) { CfgPtr -> HandlerTable [ Id ] . Handler = StubHandler ; } CfgPtr -> HandlerTable [ Id ] . CallBackRef = InstancePtr ; } } }
Initializes Slave controllers in Cascade mode.
Initializes Slave controllers in Cascade mode .
/* Convert from integer id to bit mask */ /* Enable interrupt id with 31 for Master
	 * interrupt controller
	 */ /* Enable interrupt ids with 31 for secondary
			 * interrupt controllers
			 */ /* Disable Interrupt output */ /* Set all interrupts as normal mode if Fast Interrupts
		 * are enabled
		 */ /*
		 * Initialize all the data needed to perform interrupt
		 * processing for each interrupt ID up to the maximum used
		 */ /*
			 * Initialize the handler to point to a stub to handle an
			 * interrupt which has not been connected to a handler.
			 * Only initialize it if the handler is 0 or
			 * XNullHandler, which means it was not initialized
			 * statically by the tools/user.Set the callback
			 * reference to this instance so that unhandled
			 * interrupts can be tracked.
			 */