XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1.c
u32 XHdmiphy1_PllInitialize(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId,
		XHdmiphy1_PllRefClkSelType QpllRefClkSel,
		XHdmiphy1_PllRefClkSelType CpllRefClkSel,
		XHdmiphy1_PllType TxPllSelect, XHdmiphy1_PllType RxPllSelect)
{
	/* Suppress Warning Messages */
	ChId = ChId;

	/* Set configuration in software. */
    XHdmiphy1_CfgPllRefClkSel(InstancePtr, QuadId,
            XHDMIPHY1_CHANNEL_ID_CMNA, QpllRefClkSel);
    XHdmiphy1_CfgPllRefClkSel(InstancePtr, QuadId,
            XHDMIPHY1_CHANNEL_ID_CHA, CpllRefClkSel);
	XHdmiphy1_CfgSysClkDataSel(InstancePtr, QuadId, XHDMIPHY1_DIR_TX,
			XHdmiphy1_Pll2SysClkData(TxPllSelect));
	XHdmiphy1_CfgSysClkDataSel(InstancePtr, QuadId, XHDMIPHY1_DIR_RX,
			XHdmiphy1_Pll2SysClkData(RxPllSelect));
	XHdmiphy1_CfgSysClkOutSel(InstancePtr, QuadId, XHDMIPHY1_DIR_TX,
			XHdmiphy1_Pll2SysClkOut(TxPllSelect));
	XHdmiphy1_CfgSysClkOutSel(InstancePtr, QuadId, XHDMIPHY1_DIR_RX,
			XHdmiphy1_Pll2SysClkOut(RxPllSelect));

	/* Write configuration to hardware at once. */
	XHdmiphy1_WriteCfgRefClkSelReg(InstancePtr, QuadId);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function will initialize the PLL selection for a given channel.
*
* @param	InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
* @param	QpllRefClkSel is the QPLL reference clock selection for the
*		quad.
* @param	CpllRefClkSel is the CPLL reference clock selection for the
*		quad.
* @param	TxPllSelect is the reference clock selection for the quad's
*		TX PLL dividers.
* @param	RxPllSelect is the reference clock selection for the quad's
*		RX PLL dividers.
*
* @return
*		- XST_SUCCESS.
*
* @note		None.
*
******************************************************************************/
This function will initialize the PLL selection for a given channel.
This function will initialize the PLL selection for a given channel .
u32 XHdmiphy1_PllInitialize(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId,
		XHdmiphy1_PllRefClkSelType QpllRefClkSel,
		XHdmiphy1_PllRefClkSelType CpllRefClkSel,
		XHdmiphy1_PllType TxPllSelect, XHdmiphy1_PllType RxPllSelect)
{
	ChId = ChId;
    XHdmiphy1_CfgPllRefClkSel(InstancePtr, QuadId,
            XHDMIPHY1_CHANNEL_ID_CMNA, QpllRefClkSel);
    XHdmiphy1_CfgPllRefClkSel(InstancePtr, QuadId,
            XHDMIPHY1_CHANNEL_ID_CHA, CpllRefClkSel);
	XHdmiphy1_CfgSysClkDataSel(InstancePtr, QuadId, XHDMIPHY1_DIR_TX,
			XHdmiphy1_Pll2SysClkData(TxPllSelect));
	XHdmiphy1_CfgSysClkDataSel(InstancePtr, QuadId, XHDMIPHY1_DIR_RX,
			XHdmiphy1_Pll2SysClkData(RxPllSelect));
	XHdmiphy1_CfgSysClkOutSel(InstancePtr, QuadId, XHDMIPHY1_DIR_TX,
			XHdmiphy1_Pll2SysClkOut(TxPllSelect));
	XHdmiphy1_CfgSysClkOutSel(InstancePtr, QuadId, XHDMIPHY1_DIR_RX,
			XHdmiphy1_Pll2SysClkOut(RxPllSelect));
	XHdmiphy1_WriteCfgRefClkSelReg(InstancePtr, QuadId);
	return XST_SUCCESS;
}
u32 XHdmiphy1_PllInitialize ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId , XHdmiphy1_PllRefClkSelType QpllRefClkSel , XHdmiphy1_PllRefClkSelType CpllRefClkSel , XHdmiphy1_PllType TxPllSelect , XHdmiphy1_PllType RxPllSelect ) { ChId = ChId ; XHdmiphy1_CfgPllRefClkSel ( InstancePtr , QuadId , XHDMIPHY1_CHANNEL_ID_CMNA , QpllRefClkSel ) ; XHdmiphy1_CfgPllRefClkSel ( InstancePtr , QuadId , XHDMIPHY1_CHANNEL_ID_CHA , CpllRefClkSel ) ; XHdmiphy1_CfgSysClkDataSel ( InstancePtr , QuadId , XHDMIPHY1_DIR_TX , XHdmiphy1_Pll2SysClkData ( TxPllSelect ) ) ; XHdmiphy1_CfgSysClkDataSel ( InstancePtr , QuadId , XHDMIPHY1_DIR_RX , XHdmiphy1_Pll2SysClkData ( RxPllSelect ) ) ; XHdmiphy1_CfgSysClkOutSel ( InstancePtr , QuadId , XHDMIPHY1_DIR_TX , XHdmiphy1_Pll2SysClkOut ( TxPllSelect ) ) ; XHdmiphy1_CfgSysClkOutSel ( InstancePtr , QuadId , XHDMIPHY1_DIR_RX , XHdmiphy1_Pll2SysClkOut ( RxPllSelect ) ) ; XHdmiphy1_WriteCfgRefClkSelReg ( InstancePtr , QuadId ) ; return XST_SUCCESS ; }
This function will initialize the PLL selection for a given channel.
This function will initialize the PLL selection for a given channel .
/* Suppress Warning Messages */ /* Set configuration in software. */ /* Write configuration to hardware at once. */