lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c
static u32 XFsbl_BoardConfig(void)
{
	XIicPs I2c0Instance, I2c1Instance;
	XIicPs_Config *I2c0CfgPtr;
	s32 Status;
	u32 UStatus;
#if defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106)
	u8 WriteBuffer[BUF_LEN] = {0U};
#endif
#if defined(XPS_BOARD_ZCU216) || defined(XPS_BOARD_ZCU208)
	XIicPs_Config *I2c1CfgPtr;
#endif

#if defined(XPS_BOARD_ZCU102)
	u32 ICMCfgLane[NUM_GT_LANES];
#endif

	/* Initialize the IIC0 driver so that it is ready to use */
	I2c0CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);
	if (I2c0CfgPtr == NULL) {
		UStatus = XFSBL_ERROR_I2C_INIT;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_INIT\r\n");
		goto END;
	}

	Status = XIicPs_CfgInitialize(&I2c0Instance, I2c0CfgPtr,
			I2c0CfgPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_ERROR_I2C_INIT;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_INIT\r\n");
		goto END;
	}

#if defined(XPS_BOARD_ZCU216) || defined(XPS_BOARD_ZCU208)
	/* Initialize the IIC1 driver so that it is ready to use */
	I2c1CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_1_DEVICE_ID);
	if (I2c1CfgPtr == NULL) {
		UStatus = XFSBL_ERROR_I2C_INIT;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_INIT\r\n");
		goto END;
	}
	Status = XIicPs_CfgInitialize(&I2c1Instance, I2c1CfgPtr,
			I2c1CfgPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_ERROR_I2C_INIT;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_INIT\r\n");
		goto END;
	}
#endif

#if defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106)
	/* Set the IIC serial clock rate */
	Status = XIicPs_SetSClk(&I2c0Instance, IIC_SCLK_RATE_IOEXP);
	if (Status != XST_SUCCESS) {
		UStatus  = XFSBL_ERROR_I2C_SET_SCLK;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_SET_SCLK\r\n");
		goto END;
	}
	/* Configure I/O pins as Output */
	WriteBuffer[0U] = CMD_CFG_0_REG;
	WriteBuffer[1U] = DATA_OUTPUT;
	Status = XIicPs_MasterSendPolled(&I2c0Instance,
		WriteBuffer, 2U, IOEXPANDER1_ADDR);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_ERROR_I2C_WRITE;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_WRITE\r\n");
		goto END;
	}

	/* Wait until bus is idle to start another transfer */
	while (XIicPs_BusIsBusy(&I2c0Instance) == TRUE) {
		/*For MISRA C compliance*/
	}

	/*
	 * Deasserting I2C_MUX_RESETB
	 * And GEM3 Resetb
	 * Selecting lanes based on configuration
	 */
	WriteBuffer[0U] = CMD_OUTPUT_0_REG;
	WriteBuffer[1U] = DATA_COMMON_CFG;

#if defined(XPS_BOARD_ZCU102)
	ICMCfgLane[0U] = XFsbl_In32(SERDES_ICM_CFG0) & SERDES_ICM_CFG0_L0_ICM_CFG_MASK;
	ICMCfgLane[1U] = (XFsbl_In32(SERDES_ICM_CFG0) &
		SERDES_ICM_CFG0_L1_ICM_CFG_MASK) >> SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT;
	ICMCfgLane[2U] = XFsbl_In32(SERDES_ICM_CFG1) & (SERDES_ICM_CFG1_L2_ICM_CFG_MASK);
	ICMCfgLane[3U] = (XFsbl_In32(SERDES_ICM_CFG1) &
		SERDES_ICM_CFG1_L3_ICM_CFG_MASK) >> SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT;

	/* For ZCU102 board, check if GT combination is valid against the lane# */
	if (((ICMCfgLane[0U] != ICM_CFG_VAL_PCIE)
			&& (ICMCfgLane[0U] != ICM_CFG_VAL_DP)
			&& (ICMCfgLane[0U] != ICM_CFG_VAL_PWRDN)) ||
		((ICMCfgLane[1U] != ICM_CFG_VAL_PCIE)
			&& (ICMCfgLane[1U] != ICM_CFG_VAL_DP)
			&& (ICMCfgLane[1U] != ICM_CFG_VAL_PWRDN)) ||
		((ICMCfgLane[2U] != ICM_CFG_VAL_PCIE)
			&& (ICMCfgLane[2U] != ICM_CFG_VAL_USB)
			&& (ICMCfgLane[2U] != ICM_CFG_VAL_PWRDN)) ||
		((ICMCfgLane[3U] != ICM_CFG_VAL_PCIE)
			&& (ICMCfgLane[3U] != ICM_CFG_VAL_SATA)
			&& (ICMCfgLane[3U] != ICM_CFG_VAL_PWRDN))) {

		UStatus = XFSBL_ERROR_GT_LANE_SELECTION;
		XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_GT_LANE_SELECTION\r\n");
		goto END;
	}

	/**
	 * If any of the lanes are of PCIe or PowerDown, that particular lane
	 * shall be configured as PCIe, else shall be configured
	 * as DP/USB/SATA, as applicable to that lane.
	 *
	 * Lane# 	WriteBuffer[1] bit#		bit value '0'	bit value '1'
	 * --------------------------------------------------------------
	 * Lane0			0					PCIe		DP
	 * Lane1			1					PCIe		DP
	 * Lane2			2					PCIe		USB
	 * Lane3			3					PCIe		SATA
	 */

	if (ICMCfgLane[0U] == ICM_CFG_VAL_DP) {
		WriteBuffer[1U] |= DATA_GT_L0_DP_CFG;
	}

	if (ICMCfgLane[1U] == ICM_CFG_VAL_DP) {
		WriteBuffer[1U] |= DATA_GT_L1_DP_CFG;
	}

	if (ICMCfgLane[2U] == ICM_CFG_VAL_USB) {
		WriteBuffer[1U] |= DATA_GT_L2_USB_CFG;
	}

	if (ICMCfgLane[3U] == ICM_CFG_VAL_SATA) {
		WriteBuffer[1U] |= DATA_GT_L3_SATA_CFG;
	}
#endif

	/* Send the Data */
	Status = XIicPs_MasterSendPolled(&I2c0Instance,
			WriteBuffer, 2U, IOEXPANDER1_ADDR);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_ERROR_I2C_WRITE;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_WRITE\r\n");
		goto END;
	}

	/* Wait until bus is idle */
	while (XIicPs_BusIsBusy(&I2c0Instance) == TRUE) {
		/*For MISRA C compliance*/
	}
#endif


	Status = XFsbl_FMCEnable(&I2c0Instance, &I2c1Instance);
	if (Status != XST_SUCCESS) {
		XFsbl_Printf(DEBUG_INFO, "FMC VADJ Configuration Not Successful");
	}
	XFsbl_Printf(DEBUG_INFO, "Board Configuration successful\n\r");
	UStatus = XFSBL_SUCCESS;

END:

	return UStatus;

}
/*****************************************************************************/
/**
 * This function is used to perform GT configuration for ZCU102 board.
 * It also provides reset to GEM, enables FMC ADJ
 *
 * @param none
 *
 * @return
 * 		- XFSBL_SUCCESS for successful configuration
 * 		- errors as mentioned in xfsbl_error.h
 *
 *****************************************************************************/
This function is used to perform GT configuration for ZCU102 board.
It also provides reset to GEM, enables FMC ADJ

@param none

@return
- XFSBL_SUCCESS for successful configuration
- errors as mentioned in xfsbl_error.h
This function is used to perform GT configuration for ZCU102 board . It also provides reset to GEM enables FMC ADJ @param none @return - XFSBL_SUCCESS for successful configuration - errors as mentioned in xfsbl_error . h
static u32 XFsbl_BoardConfig(void)
{
	XIicPs I2c0Instance, I2c1Instance;
	XIicPs_Config *I2c0CfgPtr;
	s32 Status;
	u32 UStatus;
#if defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106)
	u8 WriteBuffer[BUF_LEN] = {0U};
#endif
#if defined(XPS_BOARD_ZCU216) || defined(XPS_BOARD_ZCU208)
	XIicPs_Config *I2c1CfgPtr;
#endif
#if defined(XPS_BOARD_ZCU102)
	u32 ICMCfgLane[NUM_GT_LANES];
#endif
	I2c0CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);
	if (I2c0CfgPtr == NULL) {
		UStatus = XFSBL_ERROR_I2C_INIT;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_INIT\r\n");
		goto END;
	}
	Status = XIicPs_CfgInitialize(&I2c0Instance, I2c0CfgPtr,
			I2c0CfgPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_ERROR_I2C_INIT;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_INIT\r\n");
		goto END;
	}
#if defined(XPS_BOARD_ZCU216) || defined(XPS_BOARD_ZCU208)
	I2c1CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_1_DEVICE_ID);
	if (I2c1CfgPtr == NULL) {
		UStatus = XFSBL_ERROR_I2C_INIT;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_INIT\r\n");
		goto END;
	}
	Status = XIicPs_CfgInitialize(&I2c1Instance, I2c1CfgPtr,
			I2c1CfgPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_ERROR_I2C_INIT;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_INIT\r\n");
		goto END;
	}
#endif
#if defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106)
	Status = XIicPs_SetSClk(&I2c0Instance, IIC_SCLK_RATE_IOEXP);
	if (Status != XST_SUCCESS) {
		UStatus  = XFSBL_ERROR_I2C_SET_SCLK;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_SET_SCLK\r\n");
		goto END;
	}
	WriteBuffer[0U] = CMD_CFG_0_REG;
	WriteBuffer[1U] = DATA_OUTPUT;
	Status = XIicPs_MasterSendPolled(&I2c0Instance,
		WriteBuffer, 2U, IOEXPANDER1_ADDR);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_ERROR_I2C_WRITE;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_WRITE\r\n");
		goto END;
	}
	while (XIicPs_BusIsBusy(&I2c0Instance) == TRUE) {
	}
	WriteBuffer[0U] = CMD_OUTPUT_0_REG;
	WriteBuffer[1U] = DATA_COMMON_CFG;
#if defined(XPS_BOARD_ZCU102)
	ICMCfgLane[0U] = XFsbl_In32(SERDES_ICM_CFG0) & SERDES_ICM_CFG0_L0_ICM_CFG_MASK;
	ICMCfgLane[1U] = (XFsbl_In32(SERDES_ICM_CFG0) &
		SERDES_ICM_CFG0_L1_ICM_CFG_MASK) >> SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT;
	ICMCfgLane[2U] = XFsbl_In32(SERDES_ICM_CFG1) & (SERDES_ICM_CFG1_L2_ICM_CFG_MASK);
	ICMCfgLane[3U] = (XFsbl_In32(SERDES_ICM_CFG1) &
		SERDES_ICM_CFG1_L3_ICM_CFG_MASK) >> SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT;
	if (((ICMCfgLane[0U] != ICM_CFG_VAL_PCIE)
			&& (ICMCfgLane[0U] != ICM_CFG_VAL_DP)
			&& (ICMCfgLane[0U] != ICM_CFG_VAL_PWRDN)) ||
		((ICMCfgLane[1U] != ICM_CFG_VAL_PCIE)
			&& (ICMCfgLane[1U] != ICM_CFG_VAL_DP)
			&& (ICMCfgLane[1U] != ICM_CFG_VAL_PWRDN)) ||
		((ICMCfgLane[2U] != ICM_CFG_VAL_PCIE)
			&& (ICMCfgLane[2U] != ICM_CFG_VAL_USB)
			&& (ICMCfgLane[2U] != ICM_CFG_VAL_PWRDN)) ||
		((ICMCfgLane[3U] != ICM_CFG_VAL_PCIE)
			&& (ICMCfgLane[3U] != ICM_CFG_VAL_SATA)
			&& (ICMCfgLane[3U] != ICM_CFG_VAL_PWRDN))) {
		UStatus = XFSBL_ERROR_GT_LANE_SELECTION;
		XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_GT_LANE_SELECTION\r\n");
		goto END;
	}
	if (ICMCfgLane[0U] == ICM_CFG_VAL_DP) {
		WriteBuffer[1U] |= DATA_GT_L0_DP_CFG;
	}
	if (ICMCfgLane[1U] == ICM_CFG_VAL_DP) {
		WriteBuffer[1U] |= DATA_GT_L1_DP_CFG;
	}
	if (ICMCfgLane[2U] == ICM_CFG_VAL_USB) {
		WriteBuffer[1U] |= DATA_GT_L2_USB_CFG;
	}
	if (ICMCfgLane[3U] == ICM_CFG_VAL_SATA) {
		WriteBuffer[1U] |= DATA_GT_L3_SATA_CFG;
	}
#endif
	Status = XIicPs_MasterSendPolled(&I2c0Instance,
			WriteBuffer, 2U, IOEXPANDER1_ADDR);
	if (Status != XST_SUCCESS) {
		UStatus = XFSBL_ERROR_I2C_WRITE;
		XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_I2C_WRITE\r\n");
		goto END;
	}
	while (XIicPs_BusIsBusy(&I2c0Instance) == TRUE) {
	}
#endif
	Status = XFsbl_FMCEnable(&I2c0Instance, &I2c1Instance);
	if (Status != XST_SUCCESS) {
		XFsbl_Printf(DEBUG_INFO, "FMC VADJ Configuration Not Successful");
	}
	XFsbl_Printf(DEBUG_INFO, "Board Configuration successful\n\r");
	UStatus = XFSBL_SUCCESS;
END:
	return UStatus;
}
static u32 XFsbl_BoardConfig ( void ) { XIicPs I2c0Instance , I2c1Instance ; XIicPs_Config * I2c0CfgPtr ; s32 Status ; u32 UStatus ; #if defined ( XPS_BOARD_ZCU102 ) || defined ( XPS_BOARD_ZCU106 ) u8 WriteBuffer [ BUF_LEN ] = { 0U } ; #endif #if defined ( XPS_BOARD_ZCU216 ) || defined ( XPS_BOARD_ZCU208 ) XIicPs_Config * I2c1CfgPtr ; #endif #if defined ( XPS_BOARD_ZCU102 ) u32 ICMCfgLane [ NUM_GT_LANES ] ; #endif I2c0CfgPtr = XIicPs_LookupConfig ( XPAR_XIICPS_0_DEVICE_ID ) ; if ( I2c0CfgPtr == NULL ) { UStatus = XFSBL_ERROR_I2C_INIT ; XFsbl_Printf ( DEBUG_GENERAL , " \r \n " ) ; goto END ; } Status = XIicPs_CfgInitialize ( & I2c0Instance , I2c0CfgPtr , I2c0CfgPtr -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_ERROR_I2C_INIT ; XFsbl_Printf ( DEBUG_GENERAL , " \r \n " ) ; goto END ; } #if defined ( XPS_BOARD_ZCU216 ) || defined ( XPS_BOARD_ZCU208 ) I2c1CfgPtr = XIicPs_LookupConfig ( XPAR_XIICPS_1_DEVICE_ID ) ; if ( I2c1CfgPtr == NULL ) { UStatus = XFSBL_ERROR_I2C_INIT ; XFsbl_Printf ( DEBUG_GENERAL , " \r \n " ) ; goto END ; } Status = XIicPs_CfgInitialize ( & I2c1Instance , I2c1CfgPtr , I2c1CfgPtr -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_ERROR_I2C_INIT ; XFsbl_Printf ( DEBUG_GENERAL , " \r \n " ) ; goto END ; } #endif #if defined ( XPS_BOARD_ZCU102 ) || defined ( XPS_BOARD_ZCU106 ) Status = XIicPs_SetSClk ( & I2c0Instance , IIC_SCLK_RATE_IOEXP ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_ERROR_I2C_SET_SCLK ; XFsbl_Printf ( DEBUG_GENERAL , " \r \n " ) ; goto END ; } WriteBuffer [ 0U ] = CMD_CFG_0_REG ; WriteBuffer [ 1U ] = DATA_OUTPUT ; Status = XIicPs_MasterSendPolled ( & I2c0Instance , WriteBuffer , 2U , IOEXPANDER1_ADDR ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_ERROR_I2C_WRITE ; XFsbl_Printf ( DEBUG_GENERAL , " \r \n " ) ; goto END ; } while ( XIicPs_BusIsBusy ( & I2c0Instance ) == TRUE ) { } WriteBuffer [ 0U ] = CMD_OUTPUT_0_REG ; WriteBuffer [ 1U ] = DATA_COMMON_CFG ; #if defined ( XPS_BOARD_ZCU102 ) ICMCfgLane [ 0U ] = XFsbl_In32 ( SERDES_ICM_CFG0 ) & SERDES_ICM_CFG0_L0_ICM_CFG_MASK ; ICMCfgLane [ 1U ] = ( XFsbl_In32 ( SERDES_ICM_CFG0 ) & SERDES_ICM_CFG0_L1_ICM_CFG_MASK ) >> SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT ; ICMCfgLane [ 2U ] = XFsbl_In32 ( SERDES_ICM_CFG1 ) & ( SERDES_ICM_CFG1_L2_ICM_CFG_MASK ) ; ICMCfgLane [ 3U ] = ( XFsbl_In32 ( SERDES_ICM_CFG1 ) & SERDES_ICM_CFG1_L3_ICM_CFG_MASK ) >> SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT ; if ( ( ( ICMCfgLane [ 0U ] != ICM_CFG_VAL_PCIE ) && ( ICMCfgLane [ 0U ] != ICM_CFG_VAL_DP ) && ( ICMCfgLane [ 0U ] != ICM_CFG_VAL_PWRDN ) ) || ( ( ICMCfgLane [ 1U ] != ICM_CFG_VAL_PCIE ) && ( ICMCfgLane [ 1U ] != ICM_CFG_VAL_DP ) && ( ICMCfgLane [ 1U ] != ICM_CFG_VAL_PWRDN ) ) || ( ( ICMCfgLane [ 2U ] != ICM_CFG_VAL_PCIE ) && ( ICMCfgLane [ 2U ] != ICM_CFG_VAL_USB ) && ( ICMCfgLane [ 2U ] != ICM_CFG_VAL_PWRDN ) ) || ( ( ICMCfgLane [ 3U ] != ICM_CFG_VAL_PCIE ) && ( ICMCfgLane [ 3U ] != ICM_CFG_VAL_SATA ) && ( ICMCfgLane [ 3U ] != ICM_CFG_VAL_PWRDN ) ) ) { UStatus = XFSBL_ERROR_GT_LANE_SELECTION ; XFsbl_Printf ( DEBUG_GENERAL , " \r \n " ) ; goto END ; } if ( ICMCfgLane [ 0U ] == ICM_CFG_VAL_DP ) { WriteBuffer [ 1U ] |= DATA_GT_L0_DP_CFG ; } if ( ICMCfgLane [ 1U ] == ICM_CFG_VAL_DP ) { WriteBuffer [ 1U ] |= DATA_GT_L1_DP_CFG ; } if ( ICMCfgLane [ 2U ] == ICM_CFG_VAL_USB ) { WriteBuffer [ 1U ] |= DATA_GT_L2_USB_CFG ; } if ( ICMCfgLane [ 3U ] == ICM_CFG_VAL_SATA ) { WriteBuffer [ 1U ] |= DATA_GT_L3_SATA_CFG ; } #endif Status = XIicPs_MasterSendPolled ( & I2c0Instance , WriteBuffer , 2U , IOEXPANDER1_ADDR ) ; if ( Status != XST_SUCCESS ) { UStatus = XFSBL_ERROR_I2C_WRITE ; XFsbl_Printf ( DEBUG_GENERAL , " \r \n " ) ; goto END ; } while ( XIicPs_BusIsBusy ( & I2c0Instance ) == TRUE ) { } #endif Status = XFsbl_FMCEnable ( & I2c0Instance , & I2c1Instance ) ; if ( Status != XST_SUCCESS ) { XFsbl_Printf ( DEBUG_INFO , " " ) ; } XFsbl_Printf ( DEBUG_INFO , " \n \r " ) ; UStatus = XFSBL_SUCCESS ; END : return UStatus ; }
This function is used to perform GT configuration for ZCU102 board.
This function is used to perform GT configuration for ZCU102 board .
/* Initialize the IIC0 driver so that it is ready to use */ /* Initialize the IIC1 driver so that it is ready to use */ /* Set the IIC serial clock rate */ /* Configure I/O pins as Output */ /* Wait until bus is idle to start another transfer */ /*For MISRA C compliance*/ /*
	 * Deasserting I2C_MUX_RESETB
	 * And GEM3 Resetb
	 * Selecting lanes based on configuration
	 */ /* For ZCU102 board, check if GT combination is valid against the lane# */ /**
	 * If any of the lanes are of PCIe or PowerDown, that particular lane
	 * shall be configured as PCIe, else shall be configured
	 * as DP/USB/SATA, as applicable to that lane.
	 *
	 * Lane# 	WriteBuffer[1] bit#		bit value '0'	bit value '1'
	 * --------------------------------------------------------------
	 * Lane0			0					PCIe		DP
	 * Lane1			1					PCIe		DP
	 * Lane2			2					PCIe		USB
	 * Lane3			3					PCIe		SATA
	 */ /* Send the Data */ /* Wait until bus is idle */ /*For MISRA C compliance*/