XilinxProcessorIPLib/drivers/tft/src/xtft.c
void XTft_EnableDisplay(XTft* InstancePtr)
{
	u32 CtrlReg;

	/*
	 * Assert validates the input arguments.
	 */
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Read the Control Register.
	 */
	CtrlReg = XTft_ReadReg(InstancePtr, XTFT_CR_OFFSET);

	/*
	 * Set the Display Enable bit.
	 */
	CtrlReg |= XTFT_CR_TDE_MASK;

	/*
	 * Write to the Control Register.
	 */
	XTft_WriteReg(InstancePtr, XTFT_CR_OFFSET, CtrlReg);

}
/***************************************************************************/
/**
*
* This function enables the TFT display by setting the Display Enable bit in
* the Control register.
*
* @param	InstancePtr is a pointer to the XTft instance.
*
* @return	None.
*
* @note		None.
*
****************************************************************************/
This function enables the TFT display by setting the Display Enable bit in
the Control register.
This function enables the TFT display by setting the Display Enable bit in the Control register .
void XTft_EnableDisplay(XTft* InstancePtr)
{
	u32 CtrlReg;
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	CtrlReg = XTft_ReadReg(InstancePtr, XTFT_CR_OFFSET);
	CtrlReg |= XTFT_CR_TDE_MASK;
	XTft_WriteReg(InstancePtr, XTFT_CR_OFFSET, CtrlReg);
}
void XTft_EnableDisplay ( XTft * InstancePtr ) { u32 CtrlReg ; Xil_AssertVoid ( InstancePtr != NULL ) ; Xil_AssertVoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; CtrlReg = XTft_ReadReg ( InstancePtr , XTFT_CR_OFFSET ) ; CtrlReg |= XTFT_CR_TDE_MASK ; XTft_WriteReg ( InstancePtr , XTFT_CR_OFFSET , CtrlReg ) ; }
This function enables the TFT display by setting the Display Enable bit in
the Control register.
This function enables the TFT display by setting the Display Enable bit in the Control register .
/*
	 * Assert validates the input arguments.
	 */ /*
	 * Read the Control Register.
	 */ /*
	 * Set the Display Enable bit.
	 */ /*
	 * Write to the Control Register.
	 */