src/dpdk/drivers/net/mlx5/mlx5_txq.c
void
txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
{
	struct mlx5_priv *priv = txq_ctrl->priv;
	struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
#ifndef RTE_ARCH_64
	unsigned int lock_idx;
#endif
	const size_t page_size = rte_mem_page_size();
	if (page_size == (size_t)-1) {
		DRV_LOG(ERR, "Failed to get mem page size");
		rte_errno = ENOMEM;
	}

	if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
		return;
	MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
	MLX5_ASSERT(ppriv);
	ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
	txq_uar_ncattr_init(txq_ctrl, page_size);
#ifndef RTE_ARCH_64
	/* Assign an UAR lock according to UAR page number */
	lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
		   MLX5_UAR_PAGE_NUM_MASK;
	txq_ctrl->txq.uar_lock = &priv->sh->uar_lock[lock_idx];
#endif
}
/**
 * Initialize Tx UAR registers for primary process.
 *
 * @param txq_ctrl
 *   Pointer to Tx queue control structure.
 */
Initialize Tx UAR registers for primary process.
@param txq_ctrl
Pointer to Tx queue control structure.
Initialize Tx UAR registers for primary process . @param txq_ctrl Pointer to Tx queue control structure .
void
txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
{
	struct mlx5_priv *priv = txq_ctrl->priv;
	struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
#ifndef RTE_ARCH_64
	unsigned int lock_idx;
#endif
	const size_t page_size = rte_mem_page_size();
	if (page_size == (size_t)-1) {
		DRV_LOG(ERR, "Failed to get mem page size");
		rte_errno = ENOMEM;
	}
	if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
		return;
	MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
	MLX5_ASSERT(ppriv);
	ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
	txq_uar_ncattr_init(txq_ctrl, page_size);
#ifndef RTE_ARCH_64
	lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
		   MLX5_UAR_PAGE_NUM_MASK;
	txq_ctrl->txq.uar_lock = &priv->sh->uar_lock[lock_idx];
#endif
}
void txq_uar_init ( struct mlx5_txq_ctrl * txq_ctrl ) { struct mlx5_priv * priv = txq_ctrl -> priv ; struct mlx5_proc_priv * ppriv = MLX5_PROC_PRIV ( PORT_ID ( priv ) ) ; #ifndef RTE_ARCH_64 unsigned int lock_idx ; #endif const size_t page_size = rte_mem_page_size ( ) ; if ( page_size == ( size_t ) -1 ) { DRV_LOG ( ERR , " " ) ; rte_errno = ENOMEM ; } if ( txq_ctrl -> type != MLX5_TXQ_TYPE_STANDARD ) return ; MLX5_ASSERT ( rte_eal_process_type ( ) == RTE_PROC_PRIMARY ) ; MLX5_ASSERT ( ppriv ) ; ppriv -> uar_table [ txq_ctrl -> txq . idx ] = txq_ctrl -> bf_reg ; txq_uar_ncattr_init ( txq_ctrl , page_size ) ; #ifndef RTE_ARCH_64 lock_idx = ( txq_ctrl -> uar_mmap_offset / page_size ) & MLX5_UAR_PAGE_NUM_MASK ; txq_ctrl -> txq . uar_lock = & priv -> sh -> uar_lock [ lock_idx ] ; #endif }
Initialize Tx UAR registers for primary process.
Initialize Tx UAR registers for primary process .
/* Assign an UAR lock according to UAR page number */