lib/bsp/standalone/src/arm/ARMv8/32bit/xil_cache.c
void Xil_ICacheInvalidateLine(u32 adr)
{
	u32 currmask;

	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);

	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x1);
	/*Invalidate I Cache line*/
	mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, adr & (~0x3F));
	/* Wait for invalidate to complete */
	dsb();
	mtcpsr(currmask);
}
/****************************************************************************/
/**
 * @brief	Invalidate an instruction cache line. If the instruction
 *		specified by the address is cached by the instruction cache,
 *		the cachecline  containing that instruction is invalidated.
 *
 * @param	adr: 32bit address of the instruction to be invalidated..
 *
 * @return	None.
 *
 * @note	The bottom 4 bits are set to 0, forced by architecture.
 *
 ****************************************************************************/
@brief       Invalidate an instruction cache line. If the instruction
specified by the address is cached by the instruction cache,
the cachecline  containing that instruction is invalidated.

@param       adr: 32bit address of the instruction to be invalidated

@return      None.

@note        The bottom 4 bits are set to 0, forced by architecture.
@brief Invalidate an instruction cache line . If the instruction specified by the address is cached by the instruction cache the cachecline containing that instruction is invalidated . @param adr : 32bit address of the instruction to be invalidated @return None . @note The bottom 4 bits are set to 0 forced by architecture .
void Xil_ICacheInvalidateLine(u32 adr)
{
	u32 currmask;
	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);
	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x1);
	mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, adr & (~0x3F));
	dsb();
	mtcpsr(currmask);
}
void Xil_ICacheInvalidateLine ( u32 adr ) { u32 currmask ; currmask = mfcpsr ( ) ; mtcpsr ( currmask | IRQ_FIQ_MASK ) ; mtcp ( XREG_CP15_CACHE_SIZE_SEL , 0x1 ) ; mtcp ( XREG_CP15_INVAL_IC_LINE_MVA_POU , adr & ( ~ 0x3F ) ) ; dsb ( ) ; mtcpsr ( currmask ) ; }
@brief       Invalidate an instruction cache line.
@brief Invalidate an instruction cache line .
/*Invalidate I Cache line*/ /* Wait for invalidate to complete */