XilinxProcessorIPLib/drivers/vphy/src/xvphy_gtpe2.c
u32 XVphy_Gtpe2CfgSetCdr(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
{
	XVphy_Channel *ChPtr, *CmnPtr;
	XVphy_ChannelId CmnId;
	XVphy_PllType PllType;
	u32 PllClkInFreqHz;

	/* Set CDR values only for CPLLs. */
	if ((ChId < XVPHY_CHANNEL_ID_CH1) || (ChId > XVPHY_CHANNEL_ID_CH4)) {
		return XST_FAILURE;
	}

	ChPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(ChId)];

	ChPtr->PllParams.Cdr[0] = 0x1010;
	ChPtr->PllParams.Cdr[1] = 0x2104;
	ChPtr->PllParams.Cdr[3] = 0x07FE;

	if (InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_DP) {
		PllType = XVphy_GetPllType(InstancePtr, QuadId, XVPHY_DIR_RX, ChId);
		CmnId = XVphy_GetRcfgChId(InstancePtr, QuadId, XVPHY_DIR_RX, PllType);
		CmnPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(CmnId)];
		PllClkInFreqHz = XVphy_GetQuadRefClkFreq(InstancePtr, QuadId,
					CmnPtr->CpllRefClkSel);

		if (PllClkInFreqHz == 270000000) {
		    ChPtr->PllParams.Cdr[2] = 0x4060;
			ChPtr->PllParams.Cdr[4] = 0x0001;
		}
		else if (PllClkInFreqHz == 135000000) {
		    ChPtr->PllParams.Cdr[2] = 0x2060;
			ChPtr->PllParams.Cdr[4] = 0x0011;
		}
		/* RBR does not use DP159 forwarded clock and expects 162MHz. */
		else {
		    ChPtr->PllParams.Cdr[2] = 0x2060;
			ChPtr->PllParams.Cdr[4] = 0x0001;
		}
	}

	else if (XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX)) {

		ChPtr->PllParams.Cdr[4] = 0x0001;

		/* Update the RXCDR_CFG2 settings. */
		switch (ChPtr->RxOutDiv) {
			case 1:
				ChPtr->PllParams.Cdr[2] = 0x4060;
				break;
			case 2:
				ChPtr->PllParams.Cdr[2] = 0x2060;
				break;
			case 4:
				ChPtr->PllParams.Cdr[2] = 0x1060;
				break;
			case 8:
				ChPtr->PllParams.Cdr[2] = 0x0860;
				break;
			default:
				ChPtr->PllParams.Cdr[2] = 0x1060;
				break;
		}
	}

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function will set the clock and data recovery (CDR) values for a given
* channel.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
*
* @return
*		- XST_SUCCESS if the configuration was successful.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function will set the clock and data recovery (CDR) values for a given
channel.
This function will set the clock and data recovery ( CDR ) values for a given channel .
u32 XVphy_Gtpe2CfgSetCdr(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
{
	XVphy_Channel *ChPtr, *CmnPtr;
	XVphy_ChannelId CmnId;
	XVphy_PllType PllType;
	u32 PllClkInFreqHz;
	if ((ChId < XVPHY_CHANNEL_ID_CH1) || (ChId > XVPHY_CHANNEL_ID_CH4)) {
		return XST_FAILURE;
	}
	ChPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(ChId)];
	ChPtr->PllParams.Cdr[0] = 0x1010;
	ChPtr->PllParams.Cdr[1] = 0x2104;
	ChPtr->PllParams.Cdr[3] = 0x07FE;
	if (InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_DP) {
		PllType = XVphy_GetPllType(InstancePtr, QuadId, XVPHY_DIR_RX, ChId);
		CmnId = XVphy_GetRcfgChId(InstancePtr, QuadId, XVPHY_DIR_RX, PllType);
		CmnPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(CmnId)];
		PllClkInFreqHz = XVphy_GetQuadRefClkFreq(InstancePtr, QuadId,
					CmnPtr->CpllRefClkSel);
		if (PllClkInFreqHz == 270000000) {
		    ChPtr->PllParams.Cdr[2] = 0x4060;
			ChPtr->PllParams.Cdr[4] = 0x0001;
		}
		else if (PllClkInFreqHz == 135000000) {
		    ChPtr->PllParams.Cdr[2] = 0x2060;
			ChPtr->PllParams.Cdr[4] = 0x0011;
		}
		else {
		    ChPtr->PllParams.Cdr[2] = 0x2060;
			ChPtr->PllParams.Cdr[4] = 0x0001;
		}
	}
	else if (XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX)) {
		ChPtr->PllParams.Cdr[4] = 0x0001;
		switch (ChPtr->RxOutDiv) {
			case 1:
				ChPtr->PllParams.Cdr[2] = 0x4060;
				break;
			case 2:
				ChPtr->PllParams.Cdr[2] = 0x2060;
				break;
			case 4:
				ChPtr->PllParams.Cdr[2] = 0x1060;
				break;
			case 8:
				ChPtr->PllParams.Cdr[2] = 0x0860;
				break;
			default:
				ChPtr->PllParams.Cdr[2] = 0x1060;
				break;
		}
	}
	return XST_SUCCESS;
}
u32 XVphy_Gtpe2CfgSetCdr ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId ChId ) { XVphy_Channel * ChPtr , * CmnPtr ; XVphy_ChannelId CmnId ; XVphy_PllType PllType ; u32 PllClkInFreqHz ; if ( ( ChId < XVPHY_CHANNEL_ID_CH1 ) || ( ChId > XVPHY_CHANNEL_ID_CH4 ) ) { return XST_FAILURE ; } ChPtr = & InstancePtr -> Quads [ QuadId ] . Plls [ XVPHY_CH2IDX ( ChId ) ] ; ChPtr -> PllParams . Cdr [ 0 ] = 0x1010 ; ChPtr -> PllParams . Cdr [ 1 ] = 0x2104 ; ChPtr -> PllParams . Cdr [ 3 ] = 0x07FE ; if ( InstancePtr -> Config . RxProtocol == XVPHY_PROTOCOL_DP ) { PllType = XVphy_GetPllType ( InstancePtr , QuadId , XVPHY_DIR_RX , ChId ) ; CmnId = XVphy_GetRcfgChId ( InstancePtr , QuadId , XVPHY_DIR_RX , PllType ) ; CmnPtr = & InstancePtr -> Quads [ QuadId ] . Plls [ XVPHY_CH2IDX ( CmnId ) ] ; PllClkInFreqHz = XVphy_GetQuadRefClkFreq ( InstancePtr , QuadId , CmnPtr -> CpllRefClkSel ) ; if ( PllClkInFreqHz == 270000000 ) { ChPtr -> PllParams . Cdr [ 2 ] = 0x4060 ; ChPtr -> PllParams . Cdr [ 4 ] = 0x0001 ; } else if ( PllClkInFreqHz == 135000000 ) { ChPtr -> PllParams . Cdr [ 2 ] = 0x2060 ; ChPtr -> PllParams . Cdr [ 4 ] = 0x0011 ; } else { ChPtr -> PllParams . Cdr [ 2 ] = 0x2060 ; ChPtr -> PllParams . Cdr [ 4 ] = 0x0001 ; } } else if ( XVphy_IsHDMI ( InstancePtr , XVPHY_DIR_RX ) ) { ChPtr -> PllParams . Cdr [ 4 ] = 0x0001 ; switch ( ChPtr -> RxOutDiv ) { case 1 : ChPtr -> PllParams . Cdr [ 2 ] = 0x4060 ; break ; case 2 : ChPtr -> PllParams . Cdr [ 2 ] = 0x2060 ; break ; case 4 : ChPtr -> PllParams . Cdr [ 2 ] = 0x1060 ; break ; case 8 : ChPtr -> PllParams . Cdr [ 2 ] = 0x0860 ; break ; default : ChPtr -> PllParams . Cdr [ 2 ] = 0x1060 ; break ; } } return XST_SUCCESS ; }
This function will set the clock and data recovery (CDR) values for a given
channel.
This function will set the clock and data recovery ( CDR ) values for a given channel .
/* Set CDR values only for CPLLs. */ /* RBR does not use DP159 forwarded clock and expects 162MHz. */ /* Update the RXCDR_CFG2 settings. */