XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c
int XSysMon_SetSeqAcqTime(XSysMon *InstancePtr, u32 AcqCyclesChMask)
{
	/*
	 * Assert the arguments.
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * The sequencer must be in the Safe Mode before writing
	 * to these registers. Return XST_FAILURE if the channel
	 * sequencer is enabled.
	 */
	if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SAFE)) {
		return XST_FAILURE;
	}

	/*
	 * Set the Acquisition time for the specified channels in the
	 * ADC Channel Acquisition Time Sequencer Registers.
	 */
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ06_OFFSET,
			 (AcqCyclesChMask & XSM_SEQ06_CH_VALID_MASK));

	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ07_OFFSET,
			 (AcqCyclesChMask >> XSM_SEQ_CH_AUX_SHIFT) &
			 XSM_SEQ07_CH_VALID_MASK);

	return XST_SUCCESS;
}
/****************************************************************************/
/**
*
* This function sets the number of Acquisition cycles in the ADC Channel
* Acquisition Time Sequencer Registers. The sequencer must be in the Safe Mode
* before writing to these registers.
*
* @param	InstancePtr is a pointer to the XSysMon instance.
* @param	AcqCyclesChMask is the bit mask of all the channels for which
*		the number of acquisition cycles is to be extended.
*		Use XSM_SEQ_CH__* defined in xsysmon_hw.h to specify the Channel
*		numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
*		for bit masks of 1 and will be the default 4 ADCCLK cycles for
*		bit masks of 0.
*		The AcqCyclesChMask is a 32 bit mask that is written to the two
*		16 bit ADC Channel Acquisition Time Sequencer Registers.
*
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the Channel Sequencer Registers.
*		- XST_FAILURE if the channel sequencer is enabled.
*
* @note		None.
*
*****************************************************************************/
This function sets the number of Acquisition cycles in the ADC Channel
Acquisition Time Sequencer Registers. The sequencer must be in the Safe Mode
before writing to these registers.
This function sets the number of Acquisition cycles in the ADC Channel Acquisition Time Sequencer Registers . The sequencer must be in the Safe Mode before writing to these registers .
int XSysMon_SetSeqAcqTime(XSysMon *InstancePtr, u32 AcqCyclesChMask)
{
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	if ((XSysMon_GetSequencerMode(InstancePtr) != XSM_SEQ_MODE_SAFE)) {
		return XST_FAILURE;
	}
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ06_OFFSET,
			 (AcqCyclesChMask & XSM_SEQ06_CH_VALID_MASK));
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress,
			 XSM_SEQ07_OFFSET,
			 (AcqCyclesChMask >> XSM_SEQ_CH_AUX_SHIFT) &
			 XSM_SEQ07_CH_VALID_MASK);
	return XST_SUCCESS;
}
int XSysMon_SetSeqAcqTime ( XSysMon * InstancePtr , u32 AcqCyclesChMask ) { Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; if ( ( XSysMon_GetSequencerMode ( InstancePtr ) != XSM_SEQ_MODE_SAFE ) ) { return XST_FAILURE ; } XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ06_OFFSET , ( AcqCyclesChMask & XSM_SEQ06_CH_VALID_MASK ) ) ; XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_SEQ07_OFFSET , ( AcqCyclesChMask >> XSM_SEQ_CH_AUX_SHIFT ) & XSM_SEQ07_CH_VALID_MASK ) ; return XST_SUCCESS ; }
This function sets the number of Acquisition cycles in the ADC Channel
Acquisition Time Sequencer Registers.
This function sets the number of Acquisition cycles in the ADC Channel Acquisition Time Sequencer Registers .
/*
	 * Assert the arguments.
	 */ /*
	 * The sequencer must be in the Safe Mode before writing
	 * to these registers. Return XST_FAILURE if the channel
	 * sequencer is enabled.
	 */ /*
	 * Set the Acquisition time for the specified channels in the
	 * ADC Channel Acquisition Time Sequencer Registers.
	 */