src/dpdk/drivers/net/qede/qede_debug.c
static u32 qed_grc_dump_read_from_vfc(struct ecore_hwfn *p_hwfn,
				      struct ecore_ptt *p_ptt,
				      struct storm_defs *storm,
				      u32 *cmd_data,
				      u32 cmd_size,
				      u32 *addr_data,
				      u32 addr_size,
				      u32 resp_size, u32 *dump_buf)
{
	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	u32 vfc_status, polling_ms, polling_count = 0, i;
	u32 reg_addr, sem_base;
	bool is_ready = false;

	sem_base = storm->sem_fast_mem_addr;
	polling_ms = VFC_POLLING_DELAY_MS *
	    s_hw_type_defs[dev_data->hw_type].delay_factor;

	/* Write VFC command */
	ARR_REG_WR(p_hwfn,
		   p_ptt,
		   sem_base + SEM_FAST_REG_VFC_DATA_WR,
		   cmd_data, cmd_size);

	/* Write VFC address */
	ARR_REG_WR(p_hwfn,
		   p_ptt,
		   sem_base + SEM_FAST_REG_VFC_ADDR,
		   addr_data, addr_size);

	/* Read response */
	for (i = 0; i < resp_size; i++) {
		/* Poll until ready */
		do {
			reg_addr = sem_base + SEM_FAST_REG_VFC_STATUS;
			qed_grc_dump_addr_range(p_hwfn,
						p_ptt,
						&vfc_status,
						true,
						BYTES_TO_DWORDS(reg_addr),
						1,
						false, SPLIT_TYPE_NONE, 0);
			is_ready = vfc_status &
				   OSAL_BIT(VFC_STATUS_RESP_READY_BIT);

			if (!is_ready) {
				if (polling_count++ == VFC_POLLING_COUNT)
					return 0;

				OSAL_MSLEEP(polling_ms);
			}
		} while (!is_ready);

		reg_addr = sem_base + SEM_FAST_REG_VFC_DATA_RD;
		qed_grc_dump_addr_range(p_hwfn,
					p_ptt,
					dump_buf + i,
					true,
					BYTES_TO_DWORDS(reg_addr),
					1, false, SPLIT_TYPE_NONE, 0);
	}

	return resp_size;
}
/* Reads data from VFC. Returns the number of dwords read (0 on error).
 * Sizes are specified in dwords.
 */
Reads data from VFC. Returns the number of dwords read (0 on error).
Sizes are specified in dwords.
Reads data from VFC . Returns the number of dwords read ( 0 on error ) . Sizes are specified in dwords .
static u32 qed_grc_dump_read_from_vfc(struct ecore_hwfn *p_hwfn,
				      struct ecore_ptt *p_ptt,
				      struct storm_defs *storm,
				      u32 *cmd_data,
				      u32 cmd_size,
				      u32 *addr_data,
				      u32 addr_size,
				      u32 resp_size, u32 *dump_buf)
{
	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	u32 vfc_status, polling_ms, polling_count = 0, i;
	u32 reg_addr, sem_base;
	bool is_ready = false;
	sem_base = storm->sem_fast_mem_addr;
	polling_ms = VFC_POLLING_DELAY_MS *
	    s_hw_type_defs[dev_data->hw_type].delay_factor;
	ARR_REG_WR(p_hwfn,
		   p_ptt,
		   sem_base + SEM_FAST_REG_VFC_DATA_WR,
		   cmd_data, cmd_size);
	ARR_REG_WR(p_hwfn,
		   p_ptt,
		   sem_base + SEM_FAST_REG_VFC_ADDR,
		   addr_data, addr_size);
	for (i = 0; i < resp_size; i++) {
		do {
			reg_addr = sem_base + SEM_FAST_REG_VFC_STATUS;
			qed_grc_dump_addr_range(p_hwfn,
						p_ptt,
						&vfc_status,
						true,
						BYTES_TO_DWORDS(reg_addr),
						1,
						false, SPLIT_TYPE_NONE, 0);
			is_ready = vfc_status &
				   OSAL_BIT(VFC_STATUS_RESP_READY_BIT);
			if (!is_ready) {
				if (polling_count++ == VFC_POLLING_COUNT)
					return 0;
				OSAL_MSLEEP(polling_ms);
			}
		} while (!is_ready);
		reg_addr = sem_base + SEM_FAST_REG_VFC_DATA_RD;
		qed_grc_dump_addr_range(p_hwfn,
					p_ptt,
					dump_buf + i,
					true,
					BYTES_TO_DWORDS(reg_addr),
					1, false, SPLIT_TYPE_NONE, 0);
	}
	return resp_size;
}
static u32 qed_grc_dump_read_from_vfc ( struct ecore_hwfn * p_hwfn , struct ecore_ptt * p_ptt , struct storm_defs * storm , u32 * cmd_data , u32 cmd_size , u32 * addr_data , u32 addr_size , u32 resp_size , u32 * dump_buf ) { struct dbg_tools_data * dev_data = & p_hwfn -> dbg_info ; u32 vfc_status , polling_ms , polling_count = 0 , i ; u32 reg_addr , sem_base ; bool is_ready = false ; sem_base = storm -> sem_fast_mem_addr ; polling_ms = VFC_POLLING_DELAY_MS * s_hw_type_defs [ dev_data -> hw_type ] . delay_factor ; ARR_REG_WR ( p_hwfn , p_ptt , sem_base + SEM_FAST_REG_VFC_DATA_WR , cmd_data , cmd_size ) ; ARR_REG_WR ( p_hwfn , p_ptt , sem_base + SEM_FAST_REG_VFC_ADDR , addr_data , addr_size ) ; for ( i = 0 ; i < resp_size ; i ++ ) { do { reg_addr = sem_base + SEM_FAST_REG_VFC_STATUS ; qed_grc_dump_addr_range ( p_hwfn , p_ptt , & vfc_status , true , BYTES_TO_DWORDS ( reg_addr ) , 1 , false , SPLIT_TYPE_NONE , 0 ) ; is_ready = vfc_status & OSAL_BIT ( VFC_STATUS_RESP_READY_BIT ) ; if ( ! is_ready ) { if ( polling_count ++ == VFC_POLLING_COUNT ) return 0 ; OSAL_MSLEEP ( polling_ms ) ; } } while ( ! is_ready ) ; reg_addr = sem_base + SEM_FAST_REG_VFC_DATA_RD ; qed_grc_dump_addr_range ( p_hwfn , p_ptt , dump_buf + i , true , BYTES_TO_DWORDS ( reg_addr ) , 1 , false , SPLIT_TYPE_NONE , 0 ) ; } return resp_size ; }
Reads data from VFC.
Reads data from VFC .
/* Write VFC command */ /* Write VFC address */ /* Read response */ /* Poll until ready */