src/dpdk/drivers/net/cxgbe/base/t4_hw.c
unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
{
	unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
	unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
							  A_MPS_CMN_CTL));

	if (pidx >= nports) {
		dev_warn(adap, "TP Port Index %d >= Nports %d\n",
			 pidx, nports);
		return 0;
	}

	switch (chip_version) {
	case CHELSIO_T4:
	case CHELSIO_T5:
		/* Note that this happens to be the same values as the MPS
		 * Buffer Group Map for these Chips.  But we replicate the code
		 * here because they're really separate concepts.
		 */
		switch (nports) {
		case 1: return 0xf;
		case 2: return 3 << (2 * pidx);
		case 4: return 1 << pidx;
		}
		break;

	case CHELSIO_T6:
		switch (nports) {
		case 2: return 1 << pidx;
		}
		break;
	}

	dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
		chip_version, nports);
	return 0;
}
/**
 * t4_get_tp_ch_map - return TP ingress channels associated with a port
 * @adapter: the adapter
 * @pidx: the port index
 *
 * Returns a bitmap indicating which TP Ingress Channels are associated with
 * a given Port.  Bit i is set if TP Ingress Channel i is used by the Port.
 */
return TP ingress channels associated with a port
@adapter: the adapter
@pidx: the port index

Returns a bitmap indicating which TP Ingress Channels are associated with
a given Port.  Bit i is set if TP Ingress Channel i is used by the Port.
return TP ingress channels associated with a port @adapter : the adapter @pidx : the port index Returns a bitmap indicating which TP Ingress Channels are associated with a given Port . Bit i is set if TP Ingress Channel i is used by the Port .
unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
{
	unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
	unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
							  A_MPS_CMN_CTL));
	if (pidx >= nports) {
		dev_warn(adap, "TP Port Index %d >= Nports %d\n",
			 pidx, nports);
		return 0;
	}
	switch (chip_version) {
	case CHELSIO_T4:
	case CHELSIO_T5:
		switch (nports) {
		case 1: return 0xf;
		case 2: return 3 << (2 * pidx);
		case 4: return 1 << pidx;
		}
		break;
	case CHELSIO_T6:
		switch (nports) {
		case 2: return 1 << pidx;
		}
		break;
	}
	dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
		chip_version, nports);
	return 0;
}
unsigned int t4_get_tp_ch_map ( struct adapter * adapter , unsigned int pidx ) { unsigned int chip_version = CHELSIO_CHIP_VERSION ( adapter -> params . chip ) ; unsigned int nports = 1 << G_NUMPORTS ( t4_read_reg ( adapter , A_MPS_CMN_CTL ) ) ; if ( pidx >= nports ) { dev_warn ( adap , " \n " , pidx , nports ) ; return 0 ; } switch ( chip_version ) { case CHELSIO_T4 : case CHELSIO_T5 : switch ( nports ) { case 1 : return 0xf ; case 2 : return 3 << ( 2 * pidx ) ; case 4 : return 1 << pidx ; } break ; case CHELSIO_T6 : switch ( nports ) { case 2 : return 1 << pidx ; } break ; } dev_err ( adapter , " \n " , chip_version , nports ) ; return 0 ; }
t4_get_tp_ch_map - return TP ingress channels associated with a port
 @adapter: the adapter
 @pidx: the port index
t4_get_tp_ch_map - return TP ingress channels associated with a port @adapter : the adapter @pidx : the port index
/* Note that this happens to be the same values as the MPS
		 * Buffer Group Map for these Chips.  But we replicate the code
		 * here because they're really separate concepts.
		 */