XilinxProcessorIPLib/drivers/dp12rxss/src/xdprxss_selftest.c
u32 XDpRxSs_SelfTest(XDpRxSs *InstancePtr)
{
	u32 Status;

	/* Verify argument. */
	Xil_AssertNonvoid(InstancePtr != NULL);

	/* Check DP availability */
	if (InstancePtr->DpPtr) {
		Status = XDp_SelfTest(InstancePtr->DpPtr);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::DP Self test "
				"failed\n\r");
			return XST_FAILURE;
		}
	}

#if (XPAR_XHDCP_NUM_INSTANCES > 0)
	if ((InstancePtr->Hdcp1xPtr) && (InstancePtr->Config.HdcpEnable)) {
		Status = XHdcp1x_SelfTest(InstancePtr->Hdcp1xPtr);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::HDCP Self test "
				"failed\r\n");
			return XST_FAILURE;
		}
	}

	if (InstancePtr->TmrCtrPtr) {
		Status = XTmrCtr_SelfTest(InstancePtr->TmrCtrPtr, 0);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::Timer Counter "
				"Self test failed\r\n");
			return XST_FAILURE;
		}
	}
#endif

	/* Check IIC availability */
	if (InstancePtr->IicPtr) {
		Status = (u32)XIic_SelfTest(InstancePtr->IicPtr);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::IIC Self test "
				"failed\n\r");
			return XST_FAILURE;
		}
	}

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function performs self test on DisplayPort Receiver Subsystem
* sub-cores.
*
* @param	InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return
*		- XST_SUCCESS if self test passed.
*		- Otherwise, prints self test failed message.
*
* @note		None.
*
******************************************************************************/
This function performs self test on DisplayPort Receiver Subsystem
sub-cores.
This function performs self test on DisplayPort Receiver Subsystem sub - cores .
u32 XDpRxSs_SelfTest(XDpRxSs *InstancePtr)
{
	u32 Status;
	Xil_AssertNonvoid(InstancePtr != NULL);
	if (InstancePtr->DpPtr) {
		Status = XDp_SelfTest(InstancePtr->DpPtr);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::DP Self test "
				"failed\n\r");
			return XST_FAILURE;
		}
	}
#if (XPAR_XHDCP_NUM_INSTANCES > 0)
	if ((InstancePtr->Hdcp1xPtr) && (InstancePtr->Config.HdcpEnable)) {
		Status = XHdcp1x_SelfTest(InstancePtr->Hdcp1xPtr);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::HDCP Self test "
				"failed\r\n");
			return XST_FAILURE;
		}
	}
	if (InstancePtr->TmrCtrPtr) {
		Status = XTmrCtr_SelfTest(InstancePtr->TmrCtrPtr, 0);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::Timer Counter "
				"Self test failed\r\n");
			return XST_FAILURE;
		}
	}
#endif
	if (InstancePtr->IicPtr) {
		Status = (u32)XIic_SelfTest(InstancePtr->IicPtr);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"ERR::IIC Self test "
				"failed\n\r");
			return XST_FAILURE;
		}
	}
	return XST_SUCCESS;
}
u32 XDpRxSs_SelfTest ( XDpRxSs * InstancePtr ) { u32 Status ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; if ( InstancePtr -> DpPtr ) { Status = XDp_SelfTest ( InstancePtr -> DpPtr ) ; if ( Status != XST_SUCCESS ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " " " \n \r " ) ; return XST_FAILURE ; } } #if ( XPAR_XHDCP_NUM_INSTANCES > 0 ) if ( ( InstancePtr -> Hdcp1xPtr ) && ( InstancePtr -> Config . HdcpEnable ) ) { Status = XHdcp1x_SelfTest ( InstancePtr -> Hdcp1xPtr ) ; if ( Status != XST_SUCCESS ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " " " \r \n " ) ; return XST_FAILURE ; } } if ( InstancePtr -> TmrCtrPtr ) { Status = XTmrCtr_SelfTest ( InstancePtr -> TmrCtrPtr , 0 ) ; if ( Status != XST_SUCCESS ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " " " \r \n " ) ; return XST_FAILURE ; } } #endif if ( InstancePtr -> IicPtr ) { Status = ( u32 ) XIic_SelfTest ( InstancePtr -> IicPtr ) ; if ( Status != XST_SUCCESS ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " " " \n \r " ) ; return XST_FAILURE ; } } return XST_SUCCESS ; }
This function performs self test on DisplayPort Receiver Subsystem
sub-cores.
This function performs self test on DisplayPort Receiver Subsystem sub - cores .
/* Verify argument. */ /* Check DP availability */ /* Check IIC availability */