XilinxProcessorIPLib/drivers/axiethernet/examples/xaxiethernet_example_util.c
int AxiEthernetUtilEnterLoopback(XAxiEthernet *AxiEthernetInstancePtr,
								int Speed)
{
	u16 PhyReg0;
	signed int PhyAddr;
	u8 PhyType;
	u16 PhyModel;
	u16 PhyReg20;	/* Extended PHY specific Register (Reg 20)
			   of Marvell 88E1111 PHY */
	u16 PhyReg21;	/* Control Register MAC (Reg 21)
			   of Marvell 88E1116R PHY */

	/* Get the Phy Interface */
	PhyType = XAxiEthernet_GetPhysicalInterface(AxiEthernetInstancePtr);

	/* Detect the PHY address */
	if (PhyType != XAE_PHY_TYPE_1000BASE_X) {
		PhyAddr = AxiEthernetDetectPHY(AxiEthernetInstancePtr);
	} else {
		PhyAddr = XPAR_AXIETHERNET_0_PHYADDR;
	}

	XAxiEthernet_PhyRead(AxiEthernetInstancePtr, PhyAddr,
				PHY_R3_PHY_IDENT_REG, &PhyModel);
	PhyModel = PhyModel & PHY_MODEL_NUM_MASK;

	/* Clear the PHY of any existing bits by zeroing this out */
	PhyReg0 = PhyReg20 = PhyReg21 = 0;

	switch (Speed) {
	case XAE_SPEED_10_MBPS:
		PhyReg0 |= PHY_R0_DFT_SPD_10;
		PhyReg20 |= PHY_R20_DFT_SPD_10;
		PhyReg21 |= PHY_REG21_10;
		break;

	case XAE_SPEED_100_MBPS:
		PhyReg0 |= PHY_R0_DFT_SPD_100;
		PhyReg20 |= PHY_R20_DFT_SPD_100;
		PhyReg21 |= PHY_REG21_100;
		break;

	case XAE_SPEED_1000_MBPS:
		PhyReg0 |= PHY_R0_DFT_SPD_1000;
		PhyReg20 |= PHY_R20_DFT_SPD_1000;
		PhyReg21 |= PHY_REG21_1000;
		break;

	case XAE_SPEED_2500_MBPS:
		PhyReg0 |= PHY_R0_DFT_SPD_2500;
		PhyReg20 |= PHY_R20_DFT_SPD_1000;
		PhyReg21 |= PHY_REG21_1000;
		break;

	default:
		AxiEthernetUtilErrorTrap("Intg_LinkSpeed not 10, 100, or 1000 mbps");
		return XST_FAILURE;
	}

	/* RGMII mode Phy specific registers initialization */
	if ((PhyType == XAE_PHY_TYPE_RGMII_2_0) ||
		(PhyType == XAE_PHY_TYPE_RGMII_1_3)) {
		if (PhyModel == MARVEL_PHY_88E1111_MODEL) {
			PhyReg20 |= PHY_R20_RX_DLY;
			/*
			 * Adding Rx delay. Configuring loopback speed.
			 */
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
						PhyAddr, PHY_R20_EXTND_CTRL_REG,
						PhyReg20);
		} else if (PhyModel == MARVEL_PHY_88E1116R_MODEL) {
			/*
			 * Switching to PAGE2
			 */
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
						PhyAddr,
						PHY_R22_PAGE_ADDR_REG, 2);
			/*
			 * Adding Tx and Rx delay. Configuring loopback speed.
			 */
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
						PhyAddr,
						PHY_PG2_R21_CTRL_REG, PhyReg21);
			/*
			 * Switching to PAGE0
			 */
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
						PhyAddr,
						PHY_R22_PAGE_ADDR_REG, 0);
		}
		PhyReg0 &= (~PHY_R0_ANEG_ENABLE);
	}

	/* Configure interface modes */
	if (PhyModel == MARVEL_PHY_88E1111_MODEL) {
		if ((PhyType == XAE_PHY_TYPE_RGMII_2_0) ||
				(PhyType == XAE_PHY_TYPE_RGMII_1_3))  {
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
					PhyAddr, PHY_R27_EXTND_STS_REG,
					PHY_R27_MAC_CONFIG_RGMII);
		} else if (PhyType == XAE_PHY_TYPE_SGMII) {
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
					PhyAddr, PHY_R27_EXTND_STS_REG,
					PHY_R27_MAC_CONFIG_SGMII);
		} else if ((PhyType == XAE_PHY_TYPE_GMII) ||
				(PhyType == XAE_PHY_TYPE_MII)) {
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
					PhyAddr, PHY_R27_EXTND_STS_REG,
					PHY_R27_MAC_CONFIG_GMII );
		}
	}

	/* Set the speed and put the PHY in reset, then put the PHY in loopback */
	XAxiEthernet_PhyWrite(AxiEthernetInstancePtr, PhyAddr,
				PHY_R0_CTRL_REG,
				PhyReg0 | PHY_R0_RESET);
	AxiEthernetUtilPhyDelay(AXIETHERNET_PHY_DELAY_SEC);
	XAxiEthernet_PhyRead(AxiEthernetInstancePtr,PhyAddr,
				PHY_R0_CTRL_REG, &PhyReg0);
	if (!ExternalLoopback) {
		XAxiEthernet_PhyWrite(AxiEthernetInstancePtr, PhyAddr,
					PHY_R0_CTRL_REG,
					PhyReg0 | PHY_R0_LOOPBACK);
	}

	if ((PhyModel == TI_PHY_MODEL) && (PhyType == XAE_PHY_TYPE_SGMII)) {
		XAxiEthernet_PhyRead(AxiEthernetInstancePtr,PhyAddr,
				     PHY_R0_CTRL_REG, &PhyReg0);
		PhyReg0 &= (~PHY_R0_ANEG_ENABLE);
		XAxiEthernet_PhyWrite(AxiEthernetInstancePtr, PhyAddr,
				      PHY_R0_CTRL_REG, PhyReg0 );
		AxiEtherentConfigureTIPhy(AxiEthernetInstancePtr, PhyAddr);
	}

	if ((PhyType == XAE_PHY_TYPE_SGMII) ||
		(PhyType == XAE_PHY_TYPE_1000BASE_X)) {
		AxiEthernetUtilConfigureInternalPhy(AxiEthernetInstancePtr, Speed);
	}

	AxiEthernetUtilPhyDelay(1);

	return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function sets the PHY to loopback mode. This works with the marvell PHY
* common on ML40x evaluation boards.
*
* @param	AxiEthernetInstancePtr is a pointer to the instance of the
*		AxiEthernet component.
* @param	Speed is the loopback speed 10, 100, or 1000 Mbit.
*
* @return
*		- XST_SUCCESS if successful.
*		- XST_FAILURE, in case of failure..
*
* @note		None.
*
******************************************************************************/
This function sets the PHY to loopback mode. This works with the marvell PHY
common on ML40x evaluation boards.
This function sets the PHY to loopback mode . This works with the marvell PHY common on ML40x evaluation boards .
int AxiEthernetUtilEnterLoopback(XAxiEthernet *AxiEthernetInstancePtr,
								int Speed)
{
	u16 PhyReg0;
	signed int PhyAddr;
	u8 PhyType;
	u16 PhyModel;
	u16 PhyReg20;	
	u16 PhyReg21;	
	PhyType = XAxiEthernet_GetPhysicalInterface(AxiEthernetInstancePtr);
	if (PhyType != XAE_PHY_TYPE_1000BASE_X) {
		PhyAddr = AxiEthernetDetectPHY(AxiEthernetInstancePtr);
	} else {
		PhyAddr = XPAR_AXIETHERNET_0_PHYADDR;
	}
	XAxiEthernet_PhyRead(AxiEthernetInstancePtr, PhyAddr,
				PHY_R3_PHY_IDENT_REG, &PhyModel);
	PhyModel = PhyModel & PHY_MODEL_NUM_MASK;
	PhyReg0 = PhyReg20 = PhyReg21 = 0;
	switch (Speed) {
	case XAE_SPEED_10_MBPS:
		PhyReg0 |= PHY_R0_DFT_SPD_10;
		PhyReg20 |= PHY_R20_DFT_SPD_10;
		PhyReg21 |= PHY_REG21_10;
		break;
	case XAE_SPEED_100_MBPS:
		PhyReg0 |= PHY_R0_DFT_SPD_100;
		PhyReg20 |= PHY_R20_DFT_SPD_100;
		PhyReg21 |= PHY_REG21_100;
		break;
	case XAE_SPEED_1000_MBPS:
		PhyReg0 |= PHY_R0_DFT_SPD_1000;
		PhyReg20 |= PHY_R20_DFT_SPD_1000;
		PhyReg21 |= PHY_REG21_1000;
		break;
	case XAE_SPEED_2500_MBPS:
		PhyReg0 |= PHY_R0_DFT_SPD_2500;
		PhyReg20 |= PHY_R20_DFT_SPD_1000;
		PhyReg21 |= PHY_REG21_1000;
		break;
	default:
		AxiEthernetUtilErrorTrap("Intg_LinkSpeed not 10, 100, or 1000 mbps");
		return XST_FAILURE;
	}
	if ((PhyType == XAE_PHY_TYPE_RGMII_2_0) ||
		(PhyType == XAE_PHY_TYPE_RGMII_1_3)) {
		if (PhyModel == MARVEL_PHY_88E1111_MODEL) {
			PhyReg20 |= PHY_R20_RX_DLY;
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
						PhyAddr, PHY_R20_EXTND_CTRL_REG,
						PhyReg20);
		} else if (PhyModel == MARVEL_PHY_88E1116R_MODEL) {
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
						PhyAddr,
						PHY_R22_PAGE_ADDR_REG, 2);
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
						PhyAddr,
						PHY_PG2_R21_CTRL_REG, PhyReg21);
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
						PhyAddr,
						PHY_R22_PAGE_ADDR_REG, 0);
		}
		PhyReg0 &= (~PHY_R0_ANEG_ENABLE);
	}
	if (PhyModel == MARVEL_PHY_88E1111_MODEL) {
		if ((PhyType == XAE_PHY_TYPE_RGMII_2_0) ||
				(PhyType == XAE_PHY_TYPE_RGMII_1_3))  {
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
					PhyAddr, PHY_R27_EXTND_STS_REG,
					PHY_R27_MAC_CONFIG_RGMII);
		} else if (PhyType == XAE_PHY_TYPE_SGMII) {
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
					PhyAddr, PHY_R27_EXTND_STS_REG,
					PHY_R27_MAC_CONFIG_SGMII);
		} else if ((PhyType == XAE_PHY_TYPE_GMII) ||
				(PhyType == XAE_PHY_TYPE_MII)) {
			XAxiEthernet_PhyWrite(AxiEthernetInstancePtr,
					PhyAddr, PHY_R27_EXTND_STS_REG,
					PHY_R27_MAC_CONFIG_GMII );
		}
	}
	XAxiEthernet_PhyWrite(AxiEthernetInstancePtr, PhyAddr,
				PHY_R0_CTRL_REG,
				PhyReg0 | PHY_R0_RESET);
	AxiEthernetUtilPhyDelay(AXIETHERNET_PHY_DELAY_SEC);
	XAxiEthernet_PhyRead(AxiEthernetInstancePtr,PhyAddr,
				PHY_R0_CTRL_REG, &PhyReg0);
	if (!ExternalLoopback) {
		XAxiEthernet_PhyWrite(AxiEthernetInstancePtr, PhyAddr,
					PHY_R0_CTRL_REG,
					PhyReg0 | PHY_R0_LOOPBACK);
	}
	if ((PhyModel == TI_PHY_MODEL) && (PhyType == XAE_PHY_TYPE_SGMII)) {
		XAxiEthernet_PhyRead(AxiEthernetInstancePtr,PhyAddr,
				     PHY_R0_CTRL_REG, &PhyReg0);
		PhyReg0 &= (~PHY_R0_ANEG_ENABLE);
		XAxiEthernet_PhyWrite(AxiEthernetInstancePtr, PhyAddr,
				      PHY_R0_CTRL_REG, PhyReg0 );
		AxiEtherentConfigureTIPhy(AxiEthernetInstancePtr, PhyAddr);
	}
	if ((PhyType == XAE_PHY_TYPE_SGMII) ||
		(PhyType == XAE_PHY_TYPE_1000BASE_X)) {
		AxiEthernetUtilConfigureInternalPhy(AxiEthernetInstancePtr, Speed);
	}
	AxiEthernetUtilPhyDelay(1);
	return XST_SUCCESS;
}
int AxiEthernetUtilEnterLoopback ( XAxiEthernet * AxiEthernetInstancePtr , int Speed ) { u16 PhyReg0 ; signed int PhyAddr ; u8 PhyType ; u16 PhyModel ; u16 PhyReg20 ; u16 PhyReg21 ; PhyType = XAxiEthernet_GetPhysicalInterface ( AxiEthernetInstancePtr ) ; if ( PhyType != XAE_PHY_TYPE_1000BASE_X ) { PhyAddr = AxiEthernetDetectPHY ( AxiEthernetInstancePtr ) ; } else { PhyAddr = XPAR_AXIETHERNET_0_PHYADDR ; } XAxiEthernet_PhyRead ( AxiEthernetInstancePtr , PhyAddr , PHY_R3_PHY_IDENT_REG , & PhyModel ) ; PhyModel = PhyModel & PHY_MODEL_NUM_MASK ; PhyReg0 = PhyReg20 = PhyReg21 = 0 ; switch ( Speed ) { case XAE_SPEED_10_MBPS : PhyReg0 |= PHY_R0_DFT_SPD_10 ; PhyReg20 |= PHY_R20_DFT_SPD_10 ; PhyReg21 |= PHY_REG21_10 ; break ; case XAE_SPEED_100_MBPS : PhyReg0 |= PHY_R0_DFT_SPD_100 ; PhyReg20 |= PHY_R20_DFT_SPD_100 ; PhyReg21 |= PHY_REG21_100 ; break ; case XAE_SPEED_1000_MBPS : PhyReg0 |= PHY_R0_DFT_SPD_1000 ; PhyReg20 |= PHY_R20_DFT_SPD_1000 ; PhyReg21 |= PHY_REG21_1000 ; break ; case XAE_SPEED_2500_MBPS : PhyReg0 |= PHY_R0_DFT_SPD_2500 ; PhyReg20 |= PHY_R20_DFT_SPD_1000 ; PhyReg21 |= PHY_REG21_1000 ; break ; default : AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } if ( ( PhyType == XAE_PHY_TYPE_RGMII_2_0 ) || ( PhyType == XAE_PHY_TYPE_RGMII_1_3 ) ) { if ( PhyModel == MARVEL_PHY_88E1111_MODEL ) { PhyReg20 |= PHY_R20_RX_DLY ; XAxiEthernet_PhyWrite ( AxiEthernetInstancePtr , PhyAddr , PHY_R20_EXTND_CTRL_REG , PhyReg20 ) ; } else if ( PhyModel == MARVEL_PHY_88E1116R_MODEL ) { XAxiEthernet_PhyWrite ( AxiEthernetInstancePtr , PhyAddr , PHY_R22_PAGE_ADDR_REG , 2 ) ; XAxiEthernet_PhyWrite ( AxiEthernetInstancePtr , PhyAddr , PHY_PG2_R21_CTRL_REG , PhyReg21 ) ; XAxiEthernet_PhyWrite ( AxiEthernetInstancePtr , PhyAddr , PHY_R22_PAGE_ADDR_REG , 0 ) ; } PhyReg0 &= ( ~ PHY_R0_ANEG_ENABLE ) ; } if ( PhyModel == MARVEL_PHY_88E1111_MODEL ) { if ( ( PhyType == XAE_PHY_TYPE_RGMII_2_0 ) || ( PhyType == XAE_PHY_TYPE_RGMII_1_3 ) ) { XAxiEthernet_PhyWrite ( AxiEthernetInstancePtr , PhyAddr , PHY_R27_EXTND_STS_REG , PHY_R27_MAC_CONFIG_RGMII ) ; } else if ( PhyType == XAE_PHY_TYPE_SGMII ) { XAxiEthernet_PhyWrite ( AxiEthernetInstancePtr , PhyAddr , PHY_R27_EXTND_STS_REG , PHY_R27_MAC_CONFIG_SGMII ) ; } else if ( ( PhyType == XAE_PHY_TYPE_GMII ) || ( PhyType == XAE_PHY_TYPE_MII ) ) { XAxiEthernet_PhyWrite ( AxiEthernetInstancePtr , PhyAddr , PHY_R27_EXTND_STS_REG , PHY_R27_MAC_CONFIG_GMII ) ; } } XAxiEthernet_PhyWrite ( AxiEthernetInstancePtr , PhyAddr , PHY_R0_CTRL_REG , PhyReg0 | PHY_R0_RESET ) ; AxiEthernetUtilPhyDelay ( AXIETHERNET_PHY_DELAY_SEC ) ; XAxiEthernet_PhyRead ( AxiEthernetInstancePtr , PhyAddr , PHY_R0_CTRL_REG , & PhyReg0 ) ; if ( ! ExternalLoopback ) { XAxiEthernet_PhyWrite ( AxiEthernetInstancePtr , PhyAddr , PHY_R0_CTRL_REG , PhyReg0 | PHY_R0_LOOPBACK ) ; } if ( ( PhyModel == TI_PHY_MODEL ) && ( PhyType == XAE_PHY_TYPE_SGMII ) ) { XAxiEthernet_PhyRead ( AxiEthernetInstancePtr , PhyAddr , PHY_R0_CTRL_REG , & PhyReg0 ) ; PhyReg0 &= ( ~ PHY_R0_ANEG_ENABLE ) ; XAxiEthernet_PhyWrite ( AxiEthernetInstancePtr , PhyAddr , PHY_R0_CTRL_REG , PhyReg0 ) ; AxiEtherentConfigureTIPhy ( AxiEthernetInstancePtr , PhyAddr ) ; } if ( ( PhyType == XAE_PHY_TYPE_SGMII ) || ( PhyType == XAE_PHY_TYPE_1000BASE_X ) ) { AxiEthernetUtilConfigureInternalPhy ( AxiEthernetInstancePtr , Speed ) ; } AxiEthernetUtilPhyDelay ( 1 ) ; return XST_SUCCESS ; }
This function sets the PHY to loopback mode.
This function sets the PHY to loopback mode .
/* Extended PHY specific Register (Reg 20)
			   of Marvell 88E1111 PHY */ /* Control Register MAC (Reg 21)
			   of Marvell 88E1116R PHY */ /* Get the Phy Interface */ /* Detect the PHY address */ /* Clear the PHY of any existing bits by zeroing this out */ /* RGMII mode Phy specific registers initialization */ /*
			 * Adding Rx delay. Configuring loopback speed.
			 */ /*
			 * Switching to PAGE2
			 */ /*
			 * Adding Tx and Rx delay. Configuring loopback speed.
			 */ /*
			 * Switching to PAGE0
			 */ /* Configure interface modes */ /* Set the speed and put the PHY in reset, then put the PHY in loopback */