XilinxProcessorIPLib/drivers/v_sdirx/src/xv_sdirx.c
void XV_SdiRx_DebugInfo(XV_SdiRx *InstancePtr, XV_SdiRx_DebugSelId SelId)
{
	u32 Data;

	/* Verify argument. */
	Xil_AssertVoid(InstancePtr != NULL);

	switch (SelId) {
	case 0:
		/* Print stream information */
		XVidC_ReportStreamInfo(&InstancePtr->Stream[0].Video);
		break;
	case 1:
		/* Print timing information */
		XVidC_ReportTiming(&InstancePtr->Stream[0].Video.Timing,
		InstancePtr->Stream[0].Video.IsInterlaced);
		break;
	case 2:
		/* Print SDI specific information */
		xil_printf("\tSDI Mode:         ");

		switch (InstancePtr->Transport.TMode) {
		case 0:
			xil_printf("HD");
			break;

		case 1:
			xil_printf("SD");
			break;

		case 2:
			if (!InstancePtr->Transport.IsLevelB3G)
				xil_printf("3GA");
			else
				xil_printf("3GB");
			break;

		case 3:
			xil_printf("3GB");
			break;

		case 4:
			xil_printf("6G");
			break;

		case 5:
			xil_printf("12G");
			break;

		default:
			xil_printf("INVALID");
			break;
		}

		xil_printf("\n\r");

		xil_printf("\tBit Rate:         %s\n\r",
		InstancePtr->Transport.IsFractional ? "Fractional" : "Integer");
		xil_printf("\tST352 Payload:    0x%X\n\r",
		InstancePtr->Stream[0].PayloadId);
		break;
	case 3:
		Data = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
					XV_SDIRX_TS_DET_STS_OFFSET);
		xil_printf("  Transport Locked: %d\r\n",
				(Data & XV_SDIRX_TS_DET_STS_T_LOCKED_MASK));
		xil_printf("  Transport Scan: %d\r\n",
				(Data & XV_SDIRX_TS_DET_STS_T_SCAN_MASK)
				>> XV_SDIRX_TS_DET_STS_T_SCAN_SHIFT);
		xil_printf("  Transport Family: %d\r\n",
				(Data & XV_SDIRX_TS_DET_STS_T_FAMILY_MASK)
				>> XV_SDIRX_TS_DET_STS_T_FAMILY_SHIFT);
		xil_printf("  Transport Rate: %d\r\n",
				(Data & XV_SDIRX_TS_DET_STS_T_RATE_MASK)
				>> XV_SDIRX_TS_DET_STS_T_RATE_SHIFT);

		Data = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
					XV_SDIRX_STS_SB_RX_TDATA_OFFSET);
		xil_printf("  Fractional Bit Rate: %d\r\n", (Data
				& XV_SDIRX_STS_SB_RX_TDATA_SDICTRL_BIT_RATE_MASK)
				>> XV_SDIRX_STS_SB_RX_TDATA_SDICTRL_BIT_RATE_SHIFT);

		Data = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
					XV_SDIRX_RX_ERR_OFFSET);
		xil_printf("  CRC Error Counts: %d%\r\n",
				Data & XV_SDIRX_RX_ERR_MASK);

		xil_printf("\r\n");
		xil_printf("RX Video Bridge:\r\n");
		Data = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
					XV_SDIRX_MODE_DET_STS_OFFSET);
		xil_printf("  Bridge Select: ");
		if (((Data & XV_SDIRX_MODE_DET_STS_MODE_MASK) == 5)
			|| (Data & XV_SDIRX_MODE_DET_STS_MODE_MASK) == 6) {
			xil_printf("12G SDI Bridge");
		} else if ((Data & XV_SDIRX_MODE_DET_STS_MODE_MASK) == 2) {
			xil_printf("3G SDI Bridge");
		} else {
			xil_printf("SDI Bridge is not 3G/12G");
		}

		xil_printf("\r\n");

		xil_printf("  Mode Locked: %d\r\n",
				(Data & XV_SDIRX_BRIDGE_STS_MODE_LOCKED_MASK)
				>> XV_SDIRX_BRIDGE_STS_MODE_LOCKED_SHIFT);
		xil_printf("  SDI Mode: ");
		switch ((Data & XV_SDIRX_BRIDGE_STS_MODE_MASK)
			>> XV_SDIRX_BRIDGE_STS_MODE_SHIFT) {
		case 0:
			xil_printf("HD");
			break;

		case 1:
			xil_printf("SD");
			break;

		case 2:
			xil_printf("3G");
			break;

		case 4:
			xil_printf("6G");
			break;

		case 5:
			xil_printf("12G Integer");
			break;

		case 6:
			xil_printf("12G Fractional");
			break;

		default:
			xil_printf("INVALID");
			break;
		}

		xil_printf("\r\n\r\n");

		xil_printf("RX AXIS Bridge:\r\n");
		Data = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
					XV_SDIRX_ISR_OFFSET);
		xil_printf("  Overflow: %d\r\n", (Data & XV_SDIRX_ISR_OVERFLOW_MASK)
						>> XV_SDIRX_ISR_OVERFLOW_SHIFT);
		xil_printf("  Underflow: %d\r\n", (Data & XV_SDIRX_ISR_OVERFLOW_MASK)
						>> XV_SDIRX_ISR_UNDERFLOW_SHIFT);
		break;
	case 4:
		for (int i = 0; i <= XV_SDIRX_REGISTER_SIZE; i++) {
			Data = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress, (i*4));
			xil_printf("Address: 0x%X Data: 0x%X\r\n",
				(InstancePtr->Config.BaseAddress + (i*4)), Data);
		}
		break;
	default:
		break;
	}
}
/******************************************************************************/
/**
*
* This function prints debug information of Stream 0 on STDIO/Uart console.
*
* @param	InstancePtr is a pointer to the XV_SdiRx core instance.
* @param	SelId specifies which debug information to be printed out
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function prints debug information of Stream 0 on STDIO/Uart console.
This function prints debug information of Stream 0 on STDIO / Uart console .
void XV_SdiRx_DebugInfo(XV_SdiRx *InstancePtr, XV_SdiRx_DebugSelId SelId)
{
	u32 Data;
	Xil_AssertVoid(InstancePtr != NULL);
	switch (SelId) {
	case 0:
		XVidC_ReportStreamInfo(&InstancePtr->Stream[0].Video);
		break;
	case 1:
		XVidC_ReportTiming(&InstancePtr->Stream[0].Video.Timing,
		InstancePtr->Stream[0].Video.IsInterlaced);
		break;
	case 2:
		xil_printf("\tSDI Mode:         ");
		switch (InstancePtr->Transport.TMode) {
		case 0:
			xil_printf("HD");
			break;
		case 1:
			xil_printf("SD");
			break;
		case 2:
			if (!InstancePtr->Transport.IsLevelB3G)
				xil_printf("3GA");
			else
				xil_printf("3GB");
			break;
		case 3:
			xil_printf("3GB");
			break;
		case 4:
			xil_printf("6G");
			break;
		case 5:
			xil_printf("12G");
			break;
		default:
			xil_printf("INVALID");
			break;
		}
		xil_printf("\n\r");
		xil_printf("\tBit Rate:         %s\n\r",
		InstancePtr->Transport.IsFractional ? "Fractional" : "Integer");
		xil_printf("\tST352 Payload:    0x%X\n\r",
		InstancePtr->Stream[0].PayloadId);
		break;
	case 3:
		Data = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
					XV_SDIRX_TS_DET_STS_OFFSET);
		xil_printf("  Transport Locked: %d\r\n",
				(Data & XV_SDIRX_TS_DET_STS_T_LOCKED_MASK));
		xil_printf("  Transport Scan: %d\r\n",
				(Data & XV_SDIRX_TS_DET_STS_T_SCAN_MASK)
				>> XV_SDIRX_TS_DET_STS_T_SCAN_SHIFT);
		xil_printf("  Transport Family: %d\r\n",
				(Data & XV_SDIRX_TS_DET_STS_T_FAMILY_MASK)
				>> XV_SDIRX_TS_DET_STS_T_FAMILY_SHIFT);
		xil_printf("  Transport Rate: %d\r\n",
				(Data & XV_SDIRX_TS_DET_STS_T_RATE_MASK)
				>> XV_SDIRX_TS_DET_STS_T_RATE_SHIFT);
		Data = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
					XV_SDIRX_STS_SB_RX_TDATA_OFFSET);
		xil_printf("  Fractional Bit Rate: %d\r\n", (Data
				& XV_SDIRX_STS_SB_RX_TDATA_SDICTRL_BIT_RATE_MASK)
				>> XV_SDIRX_STS_SB_RX_TDATA_SDICTRL_BIT_RATE_SHIFT);
		Data = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
					XV_SDIRX_RX_ERR_OFFSET);
		xil_printf("  CRC Error Counts: %d%\r\n",
				Data & XV_SDIRX_RX_ERR_MASK);
		xil_printf("\r\n");
		xil_printf("RX Video Bridge:\r\n");
		Data = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
					XV_SDIRX_MODE_DET_STS_OFFSET);
		xil_printf("  Bridge Select: ");
		if (((Data & XV_SDIRX_MODE_DET_STS_MODE_MASK) == 5)
			|| (Data & XV_SDIRX_MODE_DET_STS_MODE_MASK) == 6) {
			xil_printf("12G SDI Bridge");
		} else if ((Data & XV_SDIRX_MODE_DET_STS_MODE_MASK) == 2) {
			xil_printf("3G SDI Bridge");
		} else {
			xil_printf("SDI Bridge is not 3G/12G");
		}
		xil_printf("\r\n");
		xil_printf("  Mode Locked: %d\r\n",
				(Data & XV_SDIRX_BRIDGE_STS_MODE_LOCKED_MASK)
				>> XV_SDIRX_BRIDGE_STS_MODE_LOCKED_SHIFT);
		xil_printf("  SDI Mode: ");
		switch ((Data & XV_SDIRX_BRIDGE_STS_MODE_MASK)
			>> XV_SDIRX_BRIDGE_STS_MODE_SHIFT) {
		case 0:
			xil_printf("HD");
			break;
		case 1:
			xil_printf("SD");
			break;
		case 2:
			xil_printf("3G");
			break;
		case 4:
			xil_printf("6G");
			break;
		case 5:
			xil_printf("12G Integer");
			break;
		case 6:
			xil_printf("12G Fractional");
			break;
		default:
			xil_printf("INVALID");
			break;
		}
		xil_printf("\r\n\r\n");
		xil_printf("RX AXIS Bridge:\r\n");
		Data = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
					XV_SDIRX_ISR_OFFSET);
		xil_printf("  Overflow: %d\r\n", (Data & XV_SDIRX_ISR_OVERFLOW_MASK)
						>> XV_SDIRX_ISR_OVERFLOW_SHIFT);
		xil_printf("  Underflow: %d\r\n", (Data & XV_SDIRX_ISR_OVERFLOW_MASK)
						>> XV_SDIRX_ISR_UNDERFLOW_SHIFT);
		break;
	case 4:
		for (int i = 0; i <= XV_SDIRX_REGISTER_SIZE; i++) {
			Data = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress, (i*4));
			xil_printf("Address: 0x%X Data: 0x%X\r\n",
				(InstancePtr->Config.BaseAddress + (i*4)), Data);
		}
		break;
	default:
		break;
	}
}
void XV_SdiRx_DebugInfo ( XV_SdiRx * InstancePtr , XV_SdiRx_DebugSelId SelId ) { u32 Data ; Xil_AssertVoid ( InstancePtr != NULL ) ; switch ( SelId ) { case 0 : XVidC_ReportStreamInfo ( & InstancePtr -> Stream [ 0 ] . Video ) ; break ; case 1 : XVidC_ReportTiming ( & InstancePtr -> Stream [ 0 ] . Video . Timing , InstancePtr -> Stream [ 0 ] . Video . IsInterlaced ) ; break ; case 2 : xil_printf ( " \t " ) ; switch ( InstancePtr -> Transport . TMode ) { case 0 : xil_printf ( " " ) ; break ; case 1 : xil_printf ( " " ) ; break ; case 2 : if ( ! InstancePtr -> Transport . IsLevelB3G ) xil_printf ( " " ) ; else xil_printf ( " " ) ; break ; case 3 : xil_printf ( " " ) ; break ; case 4 : xil_printf ( " " ) ; break ; case 5 : xil_printf ( " " ) ; break ; default : xil_printf ( " " ) ; break ; } xil_printf ( " \n \r " ) ; xil_printf ( " \t \n \r " , InstancePtr -> Transport . IsFractional ? " " : " " ) ; xil_printf ( " \t \n \r " , InstancePtr -> Stream [ 0 ] . PayloadId ) ; break ; case 3 : Data = XV_SdiRx_ReadReg ( InstancePtr -> Config . BaseAddress , XV_SDIRX_TS_DET_STS_OFFSET ) ; xil_printf ( " \r \n " , ( Data & XV_SDIRX_TS_DET_STS_T_LOCKED_MASK ) ) ; xil_printf ( " \r \n " , ( Data & XV_SDIRX_TS_DET_STS_T_SCAN_MASK ) >> XV_SDIRX_TS_DET_STS_T_SCAN_SHIFT ) ; xil_printf ( " \r \n " , ( Data & XV_SDIRX_TS_DET_STS_T_FAMILY_MASK ) >> XV_SDIRX_TS_DET_STS_T_FAMILY_SHIFT ) ; xil_printf ( " \r \n " , ( Data & XV_SDIRX_TS_DET_STS_T_RATE_MASK ) >> XV_SDIRX_TS_DET_STS_T_RATE_SHIFT ) ; Data = XV_SdiRx_ReadReg ( InstancePtr -> Config . BaseAddress , XV_SDIRX_STS_SB_RX_TDATA_OFFSET ) ; xil_printf ( " \r \n " , ( Data & XV_SDIRX_STS_SB_RX_TDATA_SDICTRL_BIT_RATE_MASK ) >> XV_SDIRX_STS_SB_RX_TDATA_SDICTRL_BIT_RATE_SHIFT ) ; Data = XV_SdiRx_ReadReg ( InstancePtr -> Config . BaseAddress , XV_SDIRX_RX_ERR_OFFSET ) ; xil_printf ( " \r \n " , Data & XV_SDIRX_RX_ERR_MASK ) ; xil_printf ( " \r \n " ) ; xil_printf ( " \r \n " ) ; Data = XV_SdiRx_ReadReg ( InstancePtr -> Config . BaseAddress , XV_SDIRX_MODE_DET_STS_OFFSET ) ; xil_printf ( " " ) ; if ( ( ( Data & XV_SDIRX_MODE_DET_STS_MODE_MASK ) == 5 ) || ( Data & XV_SDIRX_MODE_DET_STS_MODE_MASK ) == 6 ) { xil_printf ( " " ) ; } else if ( ( Data & XV_SDIRX_MODE_DET_STS_MODE_MASK ) == 2 ) { xil_printf ( " " ) ; } else { xil_printf ( " " ) ; } xil_printf ( " \r \n " ) ; xil_printf ( " \r \n " , ( Data & XV_SDIRX_BRIDGE_STS_MODE_LOCKED_MASK ) >> XV_SDIRX_BRIDGE_STS_MODE_LOCKED_SHIFT ) ; xil_printf ( " " ) ; switch ( ( Data & XV_SDIRX_BRIDGE_STS_MODE_MASK ) >> XV_SDIRX_BRIDGE_STS_MODE_SHIFT ) { case 0 : xil_printf ( " " ) ; break ; case 1 : xil_printf ( " " ) ; break ; case 2 : xil_printf ( " " ) ; break ; case 4 : xil_printf ( " " ) ; break ; case 5 : xil_printf ( " " ) ; break ; case 6 : xil_printf ( " " ) ; break ; default : xil_printf ( " " ) ; break ; } xil_printf ( " \r \n \r \n " ) ; xil_printf ( " \r \n " ) ; Data = XV_SdiRx_ReadReg ( InstancePtr -> Config . BaseAddress , XV_SDIRX_ISR_OFFSET ) ; xil_printf ( " \r \n " , ( Data & XV_SDIRX_ISR_OVERFLOW_MASK ) >> XV_SDIRX_ISR_OVERFLOW_SHIFT ) ; xil_printf ( " \r \n " , ( Data & XV_SDIRX_ISR_OVERFLOW_MASK ) >> XV_SDIRX_ISR_UNDERFLOW_SHIFT ) ; break ; case 4 : for ( int i = 0 ; i <= XV_SDIRX_REGISTER_SIZE ; i ++ ) { Data = XV_SdiRx_ReadReg ( InstancePtr -> Config . BaseAddress , ( i * 4 ) ) ; xil_printf ( " \r \n " , ( InstancePtr -> Config . BaseAddress + ( i * 4 ) ) , Data ) ; } break ; default : break ; } }
This function prints debug information of Stream 0 on STDIO/Uart console.
This function prints debug information of Stream 0 on STDIO / Uart console .
/* Verify argument. */ /* Print stream information */ /* Print timing information */ /* Print SDI specific information */