XilinxProcessorIPLib/drivers/iic/src/xiic_intr.c
static void TxErrorHandler(XIic *InstancePtr)
{
	u32 IntrStatus;
	u32 CntlReg;

	/*
	 * When Sending as a slave, Tx error signals end of msg. Not Addressed
	 * As Slave will handle the callbacks. this is used to only flush
	 * the Tx fifo. The addressed as slave bit is gone as soon as the bus
	 * has been released such that the buffer pointers are used to determine
	 * the direction of transfer (send or receive).
	 */
	if (InstancePtr->RecvBufferPtr == NULL) {
		/*
		 * Master Receiver finished reading message. Flush Tx fifo to
		 * remove an 0xFF that was written to prevent bus throttling,
		 * and disable all transmit and receive interrupts.
		 */
		XIic_FlushTxFifo(InstancePtr);
		XIic_DisableIntr(InstancePtr->BaseAddress,
				  XIIC_TX_RX_INTERRUPTS);

		/*
		 * If operating in Master mode, call status handler to indicate
		 * NOACK occurred.
		 */
		IntrStatus = XIic_ReadIisr(InstancePtr->BaseAddress);
		if ((IntrStatus & XIIC_INTR_AAS_MASK) == 0) {
			InstancePtr->StatusHandler(InstancePtr->
						   StatusCallBackRef,
						   XII_SLAVE_NO_ACK_EVENT);
		} else {
			/* Decrement the Tx Error since Tx Error interrupt
			 * implies transmit complete while sending as Slave
			 */
			 InstancePtr->Stats.TxErrors--;
		}

		return;
	}

	/*
	 * Data in the receive register from either master or slave receive
	 * When:slave, indicates master sent last byte, message completed.
	 * When:master, indicates a master Receive with one byte received. When
	 * a byte is in Rx reg then the Tx error indicates the Rx data was
	 * recovered normally Tx errors are not enabled such that this should
	 * not occur.
	 */
	IntrStatus = XIic_ReadIisr(InstancePtr->BaseAddress);
	if (IntrStatus & XIIC_INTR_RX_FULL_MASK) {
		/* Rx Reg/FIFO has data,  Disable Tx error interrupts */

		XIic_DisableIntr(InstancePtr->BaseAddress,
				  XIIC_INTR_TX_ERROR_MASK);
		return;
	}

	XIic_FlushTxFifo(InstancePtr);

	/*
	 * Disable and clear Tx empty, � empty, Rx Full or Tx error interrupts.
	 */
	XIic_DisableIntr(InstancePtr->BaseAddress, XIIC_TX_RX_INTERRUPTS);
	XIic_ClearIntr(InstancePtr->BaseAddress, XIIC_TX_RX_INTERRUPTS);

	/* Clear MSMS as on Tx error when Rxing, the bus will be
	 * stopped but MSMS bit is still set. Reset to proper state
	 */
	CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
	CntlReg &= ~XIIC_CR_MSMS_MASK;
	XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET, CntlReg);


	/*
	 * Set FIFO occupancy depth = 1 so that the first byte will throttle
	 * next receive msg.
	 */
	XIic_WriteReg(InstancePtr->BaseAddress, XIIC_RFD_REG_OFFSET, 0);

	/*
	 * Call the event callback.
	 */
	InstancePtr->StatusHandler(InstancePtr->StatusCallBackRef,
				   XII_SLAVE_NO_ACK_EVENT);
}
/*****************************************************************************/
/**
*
* This interrupt occurs four different ways: Two as master and two as slave.
* Master:
* <pre>
*  (1) Transmitter (IMPLIES AN ERROR)
*      The slave receiver did not acknowledge properly.
*  (2) Receiver (Implies Tx complete)
*      Interrupt caused by setting TxAck high in the IIC to indicate to the
*      the last byte has been transmitted.
* </pre>
*
* Slave:
* <pre>
*  (3) Transmitter (Implies Tx complete)
*      Interrupt caused by master device indicating last byte of the message
*      has been transmitted.
*  (4) Receiver (IMPLIES AN ERROR)
*      Interrupt caused by setting TxAck high in the IIC to indicate Rx
*      IIC had a problem - set by this device and condition already known
*      and interrupt is not enabled.
* </pre>
*
* This interrupt is enabled during Master send and receive and disabled
* when this device knows it is going to send a negative acknowledge (Ack = No).
*
* Signals user of Tx error via status callback sending: XII_TX_ERROR_EVENT
*
* When MasterRecv has no message to send and only receives one byte of data
* from the salve device, the TxError must be enabled to catch addressing
* errors, yet there is not opportunity to disable TxError when there is no
* data to send allowing disabling on last byte. When the slave sends the
* only byte the NOAck causes a Tx Error. To disregard this as no real error,
* when there is data in the Receive FIFO/register then the error was not
* a device address write error, but a NOACK read error - to be ignored.
* To work with or without FIFO's, the Rx Data interrupt is used to indicate
* data is in the Rx register.
*
* @param	InstancePtr is a pointer to the XIic instance to be worked on.
*
* @return	None.
*
******************************************************************************/
This interrupt occurs four different ways: Two as master and two as slave.
Master:

(1) Transmitter (IMPLIES AN ERROR)
The slave receiver did not acknowledge properly.
(2) Receiver (Implies Tx complete)
Interrupt caused by setting TxAck high in the IIC to indicate to the
the last byte has been transmitted.


(3) Transmitter (Implies Tx complete)
Interrupt caused by master device indicating last byte of the message
has been transmitted.
(4) Receiver (IMPLIES AN ERROR)
Interrupt caused by setting TxAck high in the IIC to indicate Rx
IIC had a problem - set by this device and condition already known
and interrupt is not enabled.

This interrupt is enabled during Master send and receive and disabled
when this device knows it is going to send a negative acknowledge (Ack = No).

Signals user of Tx error via status callback sending: XII_TX_ERROR_EVENT

When MasterRecv has no message to send and only receives one byte of data
from the salve device, the TxError must be enabled to catch addressing
errors, yet there is not opportunity to disable TxError when there is no
data to send allowing disabling on last byte. When the slave sends the
only byte the NOAck causes a Tx Error. To disregard this as no real error,
when there is data in the Receive FIFO/register then the error was not
a device address write error, but a NOACK read error - to be ignored.
To work with or without FIFO's, the Rx Data interrupt is used to indicate
data is in the Rx register.
This interrupt occurs four different ways : Two as master and two as slave . Master : ( 1 ) Transmitter ( IMPLIES AN ERROR ) The slave receiver did not acknowledge properly . ( 2 ) Receiver ( Implies Tx complete ) Interrupt caused by setting TxAck high in the IIC to indicate to the the last byte has been transmitted . ( 3 ) Transmitter ( Implies Tx complete ) Interrupt caused by master device indicating last byte of the message has been transmitted . ( 4 ) Receiver ( IMPLIES AN ERROR ) Interrupt caused by setting TxAck high in the IIC to indicate Rx IIC had a problem - set by this device and condition already known and interrupt is not enabled . This interrupt is enabled during Master send and receive and disabled when this device knows it is going to send a negative acknowledge ( Ack = No ) . Signals user of Tx error via status callback sending : XII_TX_ERROR_EVENT When MasterRecv has no message to send and only receives one byte of data from the salve device the TxError must be enabled to catch addressing errors yet there is not opportunity to disable TxError when there is no data to send allowing disabling on last byte . When the slave sends the only byte the NOAck causes a Tx Error . To disregard this as no real error when there is data in the Receive FIFO / register then the error was not a device address write error but a NOACK read error - to be ignored . To work with or without FIFO ' s the Rx Data interrupt is used to indicate data is in the Rx register .
static void TxErrorHandler(XIic *InstancePtr)
{
	u32 IntrStatus;
	u32 CntlReg;
	if (InstancePtr->RecvBufferPtr == NULL) {
		XIic_FlushTxFifo(InstancePtr);
		XIic_DisableIntr(InstancePtr->BaseAddress,
				  XIIC_TX_RX_INTERRUPTS);
		IntrStatus = XIic_ReadIisr(InstancePtr->BaseAddress);
		if ((IntrStatus & XIIC_INTR_AAS_MASK) == 0) {
			InstancePtr->StatusHandler(InstancePtr->
						   StatusCallBackRef,
						   XII_SLAVE_NO_ACK_EVENT);
		} else {
			 InstancePtr->Stats.TxErrors--;
		}
		return;
	}
	IntrStatus = XIic_ReadIisr(InstancePtr->BaseAddress);
	if (IntrStatus & XIIC_INTR_RX_FULL_MASK) {
		XIic_DisableIntr(InstancePtr->BaseAddress,
				  XIIC_INTR_TX_ERROR_MASK);
		return;
	}
	XIic_FlushTxFifo(InstancePtr);
	XIic_DisableIntr(InstancePtr->BaseAddress, XIIC_TX_RX_INTERRUPTS);
	XIic_ClearIntr(InstancePtr->BaseAddress, XIIC_TX_RX_INTERRUPTS);
	CntlReg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
	CntlReg &= ~XIIC_CR_MSMS_MASK;
	XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET, CntlReg);
	XIic_WriteReg(InstancePtr->BaseAddress, XIIC_RFD_REG_OFFSET, 0);
	InstancePtr->StatusHandler(InstancePtr->StatusCallBackRef,
				   XII_SLAVE_NO_ACK_EVENT);
}
static void TxErrorHandler ( XIic * InstancePtr ) { u32 IntrStatus ; u32 CntlReg ; if ( InstancePtr -> RecvBufferPtr == NULL ) { XIic_FlushTxFifo ( InstancePtr ) ; XIic_DisableIntr ( InstancePtr -> BaseAddress , XIIC_TX_RX_INTERRUPTS ) ; IntrStatus = XIic_ReadIisr ( InstancePtr -> BaseAddress ) ; if ( ( IntrStatus & XIIC_INTR_AAS_MASK ) == 0 ) { InstancePtr -> StatusHandler ( InstancePtr -> StatusCallBackRef , XII_SLAVE_NO_ACK_EVENT ) ; } else { InstancePtr -> Stats . TxErrors -- ; } return ; } IntrStatus = XIic_ReadIisr ( InstancePtr -> BaseAddress ) ; if ( IntrStatus & XIIC_INTR_RX_FULL_MASK ) { XIic_DisableIntr ( InstancePtr -> BaseAddress , XIIC_INTR_TX_ERROR_MASK ) ; return ; } XIic_FlushTxFifo ( InstancePtr ) ; XIic_DisableIntr ( InstancePtr -> BaseAddress , XIIC_TX_RX_INTERRUPTS ) ; XIic_ClearIntr ( InstancePtr -> BaseAddress , XIIC_TX_RX_INTERRUPTS ) ; CntlReg = XIic_ReadReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET ) ; CntlReg &= ~ XIIC_CR_MSMS_MASK ; XIic_WriteReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET , CntlReg ) ; XIic_WriteReg ( InstancePtr -> BaseAddress , XIIC_RFD_REG_OFFSET , 0 ) ; InstancePtr -> StatusHandler ( InstancePtr -> StatusCallBackRef , XII_SLAVE_NO_ACK_EVENT ) ; }
This interrupt occurs four different ways: Two as master and two as slave.
This interrupt occurs four different ways : Two as master and two as slave .
/*
	 * When Sending as a slave, Tx error signals end of msg. Not Addressed
	 * As Slave will handle the callbacks. this is used to only flush
	 * the Tx fifo. The addressed as slave bit is gone as soon as the bus
	 * has been released such that the buffer pointers are used to determine
	 * the direction of transfer (send or receive).
	 */ /*
		 * Master Receiver finished reading message. Flush Tx fifo to
		 * remove an 0xFF that was written to prevent bus throttling,
		 * and disable all transmit and receive interrupts.
		 */ /*
		 * If operating in Master mode, call status handler to indicate
		 * NOACK occurred.
		 */ /* Decrement the Tx Error since Tx Error interrupt
			 * implies transmit complete while sending as Slave
			 */ /*
	 * Data in the receive register from either master or slave receive
	 * When:slave, indicates master sent last byte, message completed.
	 * When:master, indicates a master Receive with one byte received. When
	 * a byte is in Rx reg then the Tx error indicates the Rx data was
	 * recovered normally Tx errors are not enabled such that this should
	 * not occur.
	 */ /* Rx Reg/FIFO has data,  Disable Tx error interrupts */ /*
	 * Disable and clear Tx empty, � empty, Rx Full or Tx error interrupts.
	 */ /* Clear MSMS as on Tx error when Rxing, the bus will be
	 * stopped but MSMS bit is still set. Reset to proper state
	 */ /*
	 * Set FIFO occupancy depth = 1 so that the first byte will throttle
	 * next receive msg.
	 */ /*
	 * Call the event callback.
	 */