XilinxProcessorIPLib/drivers/dp12rxss/examples/src/zcu_rx/xdprxss_zcu102_rxonly.c
u32 DpRxSs_Setup(void)
{
    u32 ReadVal;

    /*Disable Rx*/
    XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_LINK_ENABLE, 0x0);

    /* Load Custom EDID */
    LoadEDID();

    /*Disable All Interrupts*/
    XDp_RxInterruptDisable(DpRxSsInst.DpPtr, 0xFFFFFFFF);

    /*Enable Training related interrupts*/
    XDp_RxInterruptEnable(DpRxSsInst.DpPtr,
            XDP_RX_INTERRUPT_MASK_TP1_MASK|XDP_RX_INTERRUPT_MASK_TP2_MASK|
            XDP_RX_INTERRUPT_MASK_TP3_MASK|
            XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK|
            XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK);

    /* Setting AUX Defer Count of Link Status Reads to 8 during Link Training
     * 8 Defer counts is chosen to handle worst case time interrupt service
     * load (PL system working at 100 MHz) when working with R5
     * */
    ReadVal = XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
		XDP_RX_AUX_CLK_DIVIDER);
    ReadVal |= ReadVal | (AUX_DEFER_COUNT<<24);
    XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
		XDP_RX_AUX_CLK_DIVIDER, ReadVal);

    /*Setting BS Idle timeout value to long value*/
    XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
                                    XDP_RX_BS_IDLE_TIME, DP_BS_IDLE_TIMEOUT);

    if(LINK_TRAINING_DEBUG==1)
    {
        /*Updating Vswing Iteration Count*/
        RxTrainConfig.ChEqOption = 0;
        RxTrainConfig.ClockRecoveryOption = 1;
        RxTrainConfig.Itr1Premp = 0;
        RxTrainConfig.Itr2Premp = 0;
        RxTrainConfig.Itr3Premp = 0;
        RxTrainConfig.Itr4Premp = 0;
        RxTrainConfig.Itr5Premp = 0;
        RxTrainConfig.MinVoltageSwing = 1;
        RxTrainConfig.SetPreemp = 1;
        RxTrainConfig.SetVswing = 0;
        RxTrainConfig.VswingLoopCount = 3;

        XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
			XDP_RX_MIN_VOLTAGE_SWING,
                RxTrainConfig.MinVoltageSwing |
                (RxTrainConfig.ClockRecoveryOption << 2) |
                (RxTrainConfig.VswingLoopCount << 4) |
                (RxTrainConfig.SetVswing << 8) |
                (RxTrainConfig.ChEqOption << 10) |
                (RxTrainConfig.SetPreemp << 12) |
                (RxTrainConfig.Itr1Premp << 14) |
                (RxTrainConfig.Itr2Premp << 16) |
                (RxTrainConfig.Itr3Premp << 18) |
                (RxTrainConfig.Itr4Premp << 20) |
                (RxTrainConfig.Itr5Premp << 22)
                );
    }

    /*Enable CRC Support*/
    XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_CRC_CONFIG,
                                        VidFrameCRC.TEST_CRC_SUPPORTED<<5);

    /*Enable Rx*/
    XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_LINK_ENABLE, 0x1);

    return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function configures DisplayPort RX Subsystem.
*
* @param    None.
*
* @return
*        - XST_SUCCESS if DP RX Subsystem configured successfully.
*        - XST_FAILURE, otherwise.
*
* @note        None.
*
******************************************************************************/
This function configures DisplayPort RX Subsystem.
This function configures DisplayPort RX Subsystem .
u32 DpRxSs_Setup(void)
{
    u32 ReadVal;
    XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_LINK_ENABLE, 0x0);
    LoadEDID();
    XDp_RxInterruptDisable(DpRxSsInst.DpPtr, 0xFFFFFFFF);
    XDp_RxInterruptEnable(DpRxSsInst.DpPtr,
            XDP_RX_INTERRUPT_MASK_TP1_MASK|XDP_RX_INTERRUPT_MASK_TP2_MASK|
            XDP_RX_INTERRUPT_MASK_TP3_MASK|
            XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK|
            XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK);
    ReadVal = XDp_ReadReg(DpRxSsInst.DpPtr->Config.BaseAddr,
		XDP_RX_AUX_CLK_DIVIDER);
    ReadVal |= ReadVal | (AUX_DEFER_COUNT<<24);
    XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
		XDP_RX_AUX_CLK_DIVIDER, ReadVal);
    XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
                                    XDP_RX_BS_IDLE_TIME, DP_BS_IDLE_TIMEOUT);
    if(LINK_TRAINING_DEBUG==1)
    {
        RxTrainConfig.ChEqOption = 0;
        RxTrainConfig.ClockRecoveryOption = 1;
        RxTrainConfig.Itr1Premp = 0;
        RxTrainConfig.Itr2Premp = 0;
        RxTrainConfig.Itr3Premp = 0;
        RxTrainConfig.Itr4Premp = 0;
        RxTrainConfig.Itr5Premp = 0;
        RxTrainConfig.MinVoltageSwing = 1;
        RxTrainConfig.SetPreemp = 1;
        RxTrainConfig.SetVswing = 0;
        RxTrainConfig.VswingLoopCount = 3;
        XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr,
			XDP_RX_MIN_VOLTAGE_SWING,
                RxTrainConfig.MinVoltageSwing |
                (RxTrainConfig.ClockRecoveryOption << 2) |
                (RxTrainConfig.VswingLoopCount << 4) |
                (RxTrainConfig.SetVswing << 8) |
                (RxTrainConfig.ChEqOption << 10) |
                (RxTrainConfig.SetPreemp << 12) |
                (RxTrainConfig.Itr1Premp << 14) |
                (RxTrainConfig.Itr2Premp << 16) |
                (RxTrainConfig.Itr3Premp << 18) |
                (RxTrainConfig.Itr4Premp << 20) |
                (RxTrainConfig.Itr5Premp << 22)
                );
    }
    XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_CRC_CONFIG,
                                        VidFrameCRC.TEST_CRC_SUPPORTED<<5);
    XDp_WriteReg(DpRxSsInst.DpPtr->Config.BaseAddr, XDP_RX_LINK_ENABLE, 0x1);
    return XST_SUCCESS;
}
u32 DpRxSs_Setup ( void ) { u32 ReadVal ; XDp_WriteReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_LINK_ENABLE , 0x0 ) ; LoadEDID ( ) ; XDp_RxInterruptDisable ( DpRxSsInst . DpPtr , 0xFFFFFFFF ) ; XDp_RxInterruptEnable ( DpRxSsInst . DpPtr , XDP_RX_INTERRUPT_MASK_TP1_MASK | XDP_RX_INTERRUPT_MASK_TP2_MASK | XDP_RX_INTERRUPT_MASK_TP3_MASK | XDP_RX_INTERRUPT_MASK_POWER_STATE_MASK | XDP_RX_INTERRUPT_MASK_BW_CHANGE_MASK ) ; ReadVal = XDp_ReadReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_AUX_CLK_DIVIDER ) ; ReadVal |= ReadVal | ( AUX_DEFER_COUNT << 24 ) ; XDp_WriteReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_AUX_CLK_DIVIDER , ReadVal ) ; XDp_WriteReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_BS_IDLE_TIME , DP_BS_IDLE_TIMEOUT ) ; if ( LINK_TRAINING_DEBUG == 1 ) { RxTrainConfig . ChEqOption = 0 ; RxTrainConfig . ClockRecoveryOption = 1 ; RxTrainConfig . Itr1Premp = 0 ; RxTrainConfig . Itr2Premp = 0 ; RxTrainConfig . Itr3Premp = 0 ; RxTrainConfig . Itr4Premp = 0 ; RxTrainConfig . Itr5Premp = 0 ; RxTrainConfig . MinVoltageSwing = 1 ; RxTrainConfig . SetPreemp = 1 ; RxTrainConfig . SetVswing = 0 ; RxTrainConfig . VswingLoopCount = 3 ; XDp_WriteReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_MIN_VOLTAGE_SWING , RxTrainConfig . MinVoltageSwing | ( RxTrainConfig . ClockRecoveryOption << 2 ) | ( RxTrainConfig . VswingLoopCount << 4 ) | ( RxTrainConfig . SetVswing << 8 ) | ( RxTrainConfig . ChEqOption << 10 ) | ( RxTrainConfig . SetPreemp << 12 ) | ( RxTrainConfig . Itr1Premp << 14 ) | ( RxTrainConfig . Itr2Premp << 16 ) | ( RxTrainConfig . Itr3Premp << 18 ) | ( RxTrainConfig . Itr4Premp << 20 ) | ( RxTrainConfig . Itr5Premp << 22 ) ) ; } XDp_WriteReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_CRC_CONFIG , VidFrameCRC . TEST_CRC_SUPPORTED << 5 ) ; XDp_WriteReg ( DpRxSsInst . DpPtr -> Config . BaseAddr , XDP_RX_LINK_ENABLE , 0x1 ) ; return XST_SUCCESS ; }
This function configures DisplayPort RX Subsystem.
This function configures DisplayPort RX Subsystem .
/*Disable Rx*/ /* Load Custom EDID */ /*Disable All Interrupts*/ /*Enable Training related interrupts*/ /* Setting AUX Defer Count of Link Status Reads to 8 during Link Training
     * 8 Defer counts is chosen to handle worst case time interrupt service
     * load (PL system working at 100 MHz) when working with R5
     * */ /*Setting BS Idle timeout value to long value*/ /*Updating Vswing Iteration Count*/ /*Enable CRC Support*/ /*Enable Rx*/