lib/bsp/standalone/src/arm/cortexr5/platform/versal/mpu.c
void Init_MPU(void)
{
	u32 Addr;
	u32 RegSize = 0U;
	u32 Attrib;
	u32 RegNum = 0, i;
	u64 size;

	Xil_DisableMPURegions();

	Addr = 0x00000000U;
#ifdef	XPAR_AXI_NOC_DDR_LOW_0_BASEADDR
	/* If the DDR is present, configure region as per DDR size */
	size = (XPAR_AXI_NOC_DDR_LOW_0_HIGHADDR - XPAR_AXI_NOC_DDR_LOW_0_BASEADDR) + 1;
	if (size < 0x80000000) {
		/* Lookup the size.  */
		for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
			if (size <= region_size[i].size) {
				RegSize = region_size[i].encoding;
				break;
			}
		}
	} else {
#ifdef XPAR_AIE_NUM_INSTANCES
		/* If AIE is mapped, DDR space is reduced to 1GB */
		RegSize = REGION_1G;
#else
		/* if the DDR size is > 2GB, truncate it to 2GB */
		RegSize = REGION_2G;
#endif
	}
#else
	/* For DDRless system, configure region for TCM */
	RegSize = REGION_256K;
#endif

	Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;

	/*
	 * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL.
	 *         256 MB - LPD-AFI
	 *          64 MB - VCU controller
	 *         192 MB - FPD-AFI-0
	 *         256 MB - FPD-AFI-1
	 *
	 *
	 */
	Addr = 0x80000000;
	RegSize = REGION_1G;
	Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;

	/* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */
	Addr = 0xC0000000U;
	RegSize = REGION_512M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;

	/* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */
	Addr = 0xE0000000U;
	RegSize = REGION_256M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;

	/* 128M of device memory from 0xF0000000 to 0xF7FFFFFF for PMC */
	Addr = 0xF0000000U;
	RegSize = REGION_128M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	RegNum++;

	/* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */
	Addr = 0xF8000000U;
	RegSize = REGION_16M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;

	/* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */
	Addr = 0xF9000000U;
	RegSize = REGION_1M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;

	/* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */
	Addr = 0xFD000000U;
	RegSize = REGION_16M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;

	/* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */
	Addr = 0xFE000000U;
	RegSize = REGION_16M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;

	/*
	 * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves,
	 * CSU, PMU, TCM, OCM
	 */
	Addr = 0xFF000000U;
	RegSize = REGION_16M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;

	/**
	 * 1G of remapped adddress space from 0x40000000 to 0x7FFFFFFF for AIE.
	 * The number of allocated MPU regions would be 12, 4 being free for
	 * the user.
	 * TODO: The value assigned to Addr must be parsed from XSA if the
	 * remap address is part of it (currently we are not sure if that's
	 * the case).
	 */
#ifdef XPAR_AIE_NUM_INSTANCES
	Addr = 0x40000000U;
	RegSize = REGION_1G;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW  ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;
#endif

	/* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */
	Addr = 0xFFFC0000U;
	RegSize = REGION_256K;
	Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW  ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);

	/* A total of 11 MPU regions are allocated with another 5 being free for users */

}
/*****************************************************************************
*
* Initialize MPU for during bootup with predefined region attributes.
*
* @param	None.
*
* @return	None.
*
*
******************************************************************************/
Initialize MPU for during bootup with predefined region attributes.
Initialize MPU for during bootup with predefined region attributes .
void Init_MPU(void)
{
	u32 Addr;
	u32 RegSize = 0U;
	u32 Attrib;
	u32 RegNum = 0, i;
	u64 size;
	Xil_DisableMPURegions();
	Addr = 0x00000000U;
#ifdef	XPAR_AXI_NOC_DDR_LOW_0_BASEADDR
	size = (XPAR_AXI_NOC_DDR_LOW_0_HIGHADDR - XPAR_AXI_NOC_DDR_LOW_0_BASEADDR) + 1;
	if (size < 0x80000000) {
		for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
			if (size <= region_size[i].size) {
				RegSize = region_size[i].encoding;
				break;
			}
		}
	} else {
#ifdef XPAR_AIE_NUM_INSTANCES
		RegSize = REGION_1G;
#else
		RegSize = REGION_2G;
#endif
	}
#else
	RegSize = REGION_256K;
#endif
	Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;
	Addr = 0x80000000;
	RegSize = REGION_1G;
	Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;
	Addr = 0xC0000000U;
	RegSize = REGION_512M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;
	Addr = 0xE0000000U;
	RegSize = REGION_256M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;
	Addr = 0xF0000000U;
	RegSize = REGION_128M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	RegNum++;
	Addr = 0xF8000000U;
	RegSize = REGION_16M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;
	Addr = 0xF9000000U;
	RegSize = REGION_1M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;
	Addr = 0xFD000000U;
	RegSize = REGION_16M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;
	Addr = 0xFE000000U;
	RegSize = REGION_16M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;
	Addr = 0xFF000000U;
	RegSize = REGION_16M;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;
#ifdef XPAR_AIE_NUM_INSTANCES
	Addr = 0x40000000U;
	RegSize = REGION_1G;
	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW  ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
	RegNum++;
#endif
	Addr = 0xFFFC0000U;
	RegSize = REGION_256K;
	Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW  ;
	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
	Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
}
void Init_MPU ( void ) { u32 Addr ; u32 RegSize = 0U ; u32 Attrib ; u32 RegNum = 0 , i ; u64 size ; Xil_DisableMPURegions ( ) ; Addr = 0x00000000U ; #ifdef XPAR_AXI_NOC_DDR_LOW_0_BASEADDR size = ( XPAR_AXI_NOC_DDR_LOW_0_HIGHADDR - XPAR_AXI_NOC_DDR_LOW_0_BASEADDR ) + 1 ; if ( size < 0x80000000 ) { for ( i = 0 ; i < sizeof region_size / sizeof region_size [ 0 ] ; i ++ ) { if ( size <= region_size [ i ] . size ) { RegSize = region_size [ i ] . encoding ; break ; } } } else { #ifdef XPAR_AIE_NUM_INSTANCES RegSize = REGION_1G ; #else RegSize = REGION_2G ; #endif } #else RegSize = REGION_256K ; #endif Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW ; Xil_SetAttribute ( Addr , RegSize , RegNum , Attrib ) ; Update_MpuConfig_Array ( Addr , RegSize , RegNum , Attrib ) ; RegNum ++ ; Addr = 0x80000000 ; RegSize = REGION_1G ; Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ; Xil_SetAttribute ( Addr , RegSize , RegNum , Attrib ) ; Update_MpuConfig_Array ( Addr , RegSize , RegNum , Attrib ) ; RegNum ++ ; Addr = 0xC0000000U ; RegSize = REGION_512M ; Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; Xil_SetAttribute ( Addr , RegSize , RegNum , Attrib ) ; Update_MpuConfig_Array ( Addr , RegSize , RegNum , Attrib ) ; RegNum ++ ; Addr = 0xE0000000U ; RegSize = REGION_256M ; Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; Xil_SetAttribute ( Addr , RegSize , RegNum , Attrib ) ; Update_MpuConfig_Array ( Addr , RegSize , RegNum , Attrib ) ; RegNum ++ ; Addr = 0xF0000000U ; RegSize = REGION_128M ; Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; Update_MpuConfig_Array ( Addr , RegSize , RegNum , Attrib ) ; Xil_SetAttribute ( Addr , RegSize , RegNum , Attrib ) ; RegNum ++ ; Addr = 0xF8000000U ; RegSize = REGION_16M ; Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; Xil_SetAttribute ( Addr , RegSize , RegNum , Attrib ) ; Update_MpuConfig_Array ( Addr , RegSize , RegNum , Attrib ) ; RegNum ++ ; Addr = 0xF9000000U ; RegSize = REGION_1M ; Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; Xil_SetAttribute ( Addr , RegSize , RegNum , Attrib ) ; Update_MpuConfig_Array ( Addr , RegSize , RegNum , Attrib ) ; RegNum ++ ; Addr = 0xFD000000U ; RegSize = REGION_16M ; Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; Xil_SetAttribute ( Addr , RegSize , RegNum , Attrib ) ; Update_MpuConfig_Array ( Addr , RegSize , RegNum , Attrib ) ; RegNum ++ ; Addr = 0xFE000000U ; RegSize = REGION_16M ; Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; Xil_SetAttribute ( Addr , RegSize , RegNum , Attrib ) ; Update_MpuConfig_Array ( Addr , RegSize , RegNum , Attrib ) ; RegNum ++ ; Addr = 0xFF000000U ; RegSize = REGION_16M ; Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; Xil_SetAttribute ( Addr , RegSize , RegNum , Attrib ) ; Update_MpuConfig_Array ( Addr , RegSize , RegNum , Attrib ) ; RegNum ++ ; #ifdef XPAR_AIE_NUM_INSTANCES Addr = 0x40000000U ; RegSize = REGION_1G ; Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; Xil_SetAttribute ( Addr , RegSize , RegNum , Attrib ) ; Update_MpuConfig_Array ( Addr , RegSize , RegNum , Attrib ) ; RegNum ++ ; #endif Addr = 0xFFFC0000U ; RegSize = REGION_256K ; Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW ; Xil_SetAttribute ( Addr , RegSize , RegNum , Attrib ) ; Update_MpuConfig_Array ( Addr , RegSize , RegNum , Attrib ) ; }
Initialize MPU for during bootup with predefined region attributes.
Initialize MPU for during bootup with predefined region attributes .
/* If the DDR is present, configure region as per DDR size */ /* Lookup the size.  */ /* If AIE is mapped, DDR space is reduced to 1GB */ /* if the DDR size is > 2GB, truncate it to 2GB */ /* For DDRless system, configure region for TCM */ /*
	 * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL.
	 *         256 MB - LPD-AFI
	 *          64 MB - VCU controller
	 *         192 MB - FPD-AFI-0
	 *         256 MB - FPD-AFI-1
	 *
	 *
	 */ /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */ /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */ /* 128M of device memory from 0xF0000000 to 0xF7FFFFFF for PMC */ /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */ /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */ /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */ /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */ /*
	 * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves,
	 * CSU, PMU, TCM, OCM
	 */ /**
	 * 1G of remapped adddress space from 0x40000000 to 0x7FFFFFFF for AIE.
	 * The number of allocated MPU regions would be 12, 4 being free for
	 * the user.
	 * TODO: The value assigned to Addr must be parsed from XSA if the
	 * remap address is part of it (currently we are not sure if that's
	 * the case).
	 */ /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */ /* A total of 11 MPU regions are allocated with another 5 being free for users */