XilinxProcessorIPLib/drivers/iic/src/xiic_master.c
static void SendSlaveAddr(XIic *InstancePtr)
{
	u32 CRreg;

	/*
	 * Set the control register for Master Receive, repeated start must be
	 * set before writing the address, MSMS should be already set, don't
	 * set here so if arbitration is lost or some other reason we don't
	 * want MSMS set in case of error.
	 */
	CRreg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);

	CRreg |= XIIC_CR_REPEATED_START_MASK;
	CRreg &= ~XIIC_CR_DIR_IS_TX_MASK;

	XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET, CRreg);

	/*
	 * Send the 1st byte of the 10 bit address as a read operation, enable
	 * the receive interrupt to know when data is received, assuming that
	 * the receive FIFO threshold has been previously set.
	 */
	XIic_Send10BitAddrByte1(InstancePtr->AddrOfSlave, XIIC_READ_OPERATION);

	XIic_ClearEnableIntr(InstancePtr->BaseAddress, XIIC_INTR_RX_FULL_MASK);
}
/******************************************************************************
*
* This function sends the proper byte of the address as well as generate the
* proper address bit fields depending on the address byte required and the
* direction of the data (write or read).
*
* A master receiving has the restriction that the direction must be switched
* from write to read when the third address byte is transmitted.
* For the last byte of the 10 bit address, repeated start must be set prior
* to writing the address. If repeated start options is enabled, the
* control register is written before the address is written to the Tx reg.
*
* @param	InstancePtr is a pointer to the XIic instance to be worked on.
*
* @return	None.
*
* @note
*
* This function does read/modify/write to the device control register. Calling
* functions must ensure critical sections are used.
*
******************************************************************************/
This function sends the proper byte of the address as well as generate the
proper address bit fields depending on the address byte required and the
direction of the data (write or read).

A master receiving has the restriction that the direction must be switched
from write to read when the third address byte is transmitted.
For the last byte of the 10 bit address, repeated start must be set prior
to writing the address. If repeated start options is enabled, the
control register is written before the address is written to the Tx reg.
This function sends the proper byte of the address as well as generate the proper address bit fields depending on the address byte required and the direction of the data ( write or read ) . A master receiving has the restriction that the direction must be switched from write to read when the third address byte is transmitted . For the last byte of the 10 bit address repeated start must be set prior to writing the address . If repeated start options is enabled the control register is written before the address is written to the Tx reg .
static void SendSlaveAddr(XIic *InstancePtr)
{
	u32 CRreg;
	CRreg = XIic_ReadReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET);
	CRreg |= XIIC_CR_REPEATED_START_MASK;
	CRreg &= ~XIIC_CR_DIR_IS_TX_MASK;
	XIic_WriteReg(InstancePtr->BaseAddress, XIIC_CR_REG_OFFSET, CRreg);
	XIic_Send10BitAddrByte1(InstancePtr->AddrOfSlave, XIIC_READ_OPERATION);
	XIic_ClearEnableIntr(InstancePtr->BaseAddress, XIIC_INTR_RX_FULL_MASK);
}
static void SendSlaveAddr ( XIic * InstancePtr ) { u32 CRreg ; CRreg = XIic_ReadReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET ) ; CRreg |= XIIC_CR_REPEATED_START_MASK ; CRreg &= ~ XIIC_CR_DIR_IS_TX_MASK ; XIic_WriteReg ( InstancePtr -> BaseAddress , XIIC_CR_REG_OFFSET , CRreg ) ; XIic_Send10BitAddrByte1 ( InstancePtr -> AddrOfSlave , XIIC_READ_OPERATION ) ; XIic_ClearEnableIntr ( InstancePtr -> BaseAddress , XIIC_INTR_RX_FULL_MASK ) ; }
This function sends the proper byte of the address as well as generate the
proper address bit fields depending on the address byte required and the
direction of the data (write or read).
This function sends the proper byte of the address as well as generate the proper address bit fields depending on the address byte required and the direction of the data ( write or read ) .
/*
	 * Set the control register for Master Receive, repeated start must be
	 * set before writing the address, MSMS should be already set, don't
	 * set here so if arbitration is lost or some other reason we don't
	 * want MSMS set in case of error.
	 */ /*
	 * Send the 1st byte of the 10 bit address as a read operation, enable
	 * the receive interrupt to know when data is received, assuming that
	 * the receive FIFO threshold has been previously set.
	 */