XilinxProcessorIPLib/drivers/sysmonpsu/src/xsysmonpsu.c
s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask,
		u32 SysmonBlk)
{
	s32 Status;
	UINTPTR EffectiveBaseAddress;

	/* Assert the arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));

	/*
	 * The sequencer must be in the Default Safe Mode before writing
	 * to these registers. Return XST_FAILURE if the channel sequencer
	 * is enabled.
	 */
	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk) != XSM_SEQ_MODE_SAFE)) {
		Status = (s32)XST_FAILURE;
		goto End;
	}

	/* Calculate the effective baseaddress based on the Sysmon instance. */
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);

	/*
	 * Enable the specified channels in the ADC Channel Selection Sequencer
	 * Registers.
	 */
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH0_OFFSET,
			 (u32)(ChEnableMask & XSYSMONPSU_SEQ_CH0_VALID_MASK));

	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH1_OFFSET,
			 (u32)(ChEnableMask >> XSM_SEQ_CH_SHIFT) &
			 XSYSMONPSU_SEQ_CH1_VALID_MASK);

	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH2_OFFSET,
				 (u32)(ChEnableMask >> XSM_SEQ_CH2_SHIFT) &
			 XSYSMONPSU_SEQ_CH2_VALID_MASK);

	Status = (s32)XST_SUCCESS;

End:
	return Status;
}
/****************************************************************************/
/**
*
* This function enables the specified channels in the ADC Channel Selection
* Sequencer Registers. The sequencer must be in the Safe Mode before writing
* to these registers.
*
* @param	InstancePtr is a pointer to the XSysMonPsu instance.
* @param	ChEnableMask is the bit mask of all the channels to be enabled.
*		Use XSYSMONPSU_SEQ_CH* defined in xsysmon_hw.h to specify the Channel
*		numbers. Bit masks of 1 will be enabled and bit mask of 0 will
*		be disabled.
*		The ChEnableMask is a 64 bit mask that is written to the three
*		16 bit ADC Channel Selection Sequencer Registers.
* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
*       block or PL Sysmon block register region.
*
* @return
*		- XST_SUCCESS if the given values were written successfully to
*		the ADC Channel Selection Sequencer Registers.
*		- XST_FAILURE if the channel sequencer is enabled.
*
* @note		None.
*
*****************************************************************************/
This function enables the specified channels in the ADC Channel Selection
Sequencer Registers. The sequencer must be in the Safe Mode before writing
to these registers.
This function enables the specified channels in the ADC Channel Selection Sequencer Registers . The sequencer must be in the Safe Mode before writing to these registers .
s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask,
		u32 SysmonBlk)
{
	s32 Status;
	UINTPTR EffectiveBaseAddress;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk) != XSM_SEQ_MODE_SAFE)) {
		Status = (s32)XST_FAILURE;
		goto End;
	}
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH0_OFFSET,
			 (u32)(ChEnableMask & XSYSMONPSU_SEQ_CH0_VALID_MASK));
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH1_OFFSET,
			 (u32)(ChEnableMask >> XSM_SEQ_CH_SHIFT) &
			 XSYSMONPSU_SEQ_CH1_VALID_MASK);
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH2_OFFSET,
				 (u32)(ChEnableMask >> XSM_SEQ_CH2_SHIFT) &
			 XSYSMONPSU_SEQ_CH2_VALID_MASK);
	Status = (s32)XST_SUCCESS;
End:
	return Status;
}
s32 XSysMonPsu_SetSeqChEnables ( XSysMonPsu * InstancePtr , u64 ChEnableMask , u32 SysmonBlk ) { s32 Status ; UINTPTR EffectiveBaseAddress ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Xil_AssertNonvoid ( ( SysmonBlk == XSYSMON_PS ) || ( SysmonBlk == XSYSMON_PL ) ) ; if ( ( XSysMonPsu_GetSequencerMode ( InstancePtr , SysmonBlk ) != XSM_SEQ_MODE_SAFE ) ) { Status = ( s32 ) XST_FAILURE ; goto End ; } EffectiveBaseAddress = XSysMonPsu_GetEffBaseAddress ( InstancePtr -> Config . BaseAddress , SysmonBlk ) ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_SEQ_CH0_OFFSET , ( u32 ) ( ChEnableMask & XSYSMONPSU_SEQ_CH0_VALID_MASK ) ) ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_SEQ_CH1_OFFSET , ( u32 ) ( ChEnableMask >> XSM_SEQ_CH_SHIFT ) & XSYSMONPSU_SEQ_CH1_VALID_MASK ) ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_SEQ_CH2_OFFSET , ( u32 ) ( ChEnableMask >> XSM_SEQ_CH2_SHIFT ) & XSYSMONPSU_SEQ_CH2_VALID_MASK ) ; Status = ( s32 ) XST_SUCCESS ; End : return Status ; }
This function enables the specified channels in the ADC Channel Selection
Sequencer Registers.
This function enables the specified channels in the ADC Channel Selection Sequencer Registers .
/* Assert the arguments. */ /*
	 * The sequencer must be in the Default Safe Mode before writing
	 * to these registers. Return XST_FAILURE if the channel sequencer
	 * is enabled.
	 */ /* Calculate the effective baseaddress based on the Sysmon instance. */ /*
	 * Enable the specified channels in the ADC Channel Selection Sequencer
	 * Registers.
	 */