XilinxProcessorIPLib/drivers/v_multi_scaler/examples/xv_multi_scaler_example.c
void XV_Reset_MultiScaler(void)
{
#if defined XPAR_GPIO_0_BASEADDR
	u32 count;
	*(u32 *)(GPIO_BASE) = 0xFF;
	for (count = 0; count <1000; count++);
	*(u32 *)(GPIO_BASE) = 0x0;
	for (count = 0; count <1000; count++);
	*(u32 *)(GPIO_BASE) = 0xFF;
	for (count = 0; count <1000; count++);
#else
	XV_multi_scaler_WriteReg(XPAR_PSU_GPIO_0_BASEADDR,
	XGPIOPS_MASK_DATA_3_LSW_OFFSET, 0xFFFF0000);
	XV_multi_scaler_WriteReg(XPAR_PSU_GPIO_0_BASEADDR,
	XGPIOPS_DIRM_3_OFFSET, 0xFFFFFFFF);
	XV_multi_scaler_WriteReg(XPAR_PSU_GPIO_0_BASEADDR,
	XGPIOPS_OEN_3_OFFSET, 0xFFFFFFFF);
	XV_multi_scaler_WriteReg(XPAR_PSU_GPIO_0_BASEADDR,
	XGPIOPS_DATA_3_OFFSET, 0x00000001);
	XV_multi_scaler_WriteReg(XPAR_PSU_GPIO_0_BASEADDR,
	XGPIOPS_DATA_3_OFFSET, 0x00000000);
	XV_multi_scaler_WriteReg(XPAR_PSU_GPIO_0_BASEADDR,
	XGPIOPS_DATA_3_OFFSET, 0x00000001);
#endif
}
/*****************************************************************************/
/**
 *
 * This function drives the reset pin of core high to start multiscaler core.
 *
 * @return
 *
 * @note	This function assumes a Microblaze or ARM system and no
 *	operating system is used.
 *
 ******************************************************************************/
This function drives the reset pin of core high to start multiscaler core.
@return

@note        This function assumes a Microblaze or ARM system and no
operating system is used.
This function drives the reset pin of core high to start multiscaler core . @return @note This function assumes a Microblaze or ARM system and no operating system is used .
void XV_Reset_MultiScaler(void)
{
#if defined XPAR_GPIO_0_BASEADDR
	u32 count;
	*(u32 *)(GPIO_BASE) = 0xFF;
	for (count = 0; count <1000; count++);
	*(u32 *)(GPIO_BASE) = 0x0;
	for (count = 0; count <1000; count++);
	*(u32 *)(GPIO_BASE) = 0xFF;
	for (count = 0; count <1000; count++);
#else
	XV_multi_scaler_WriteReg(XPAR_PSU_GPIO_0_BASEADDR,
	XGPIOPS_MASK_DATA_3_LSW_OFFSET, 0xFFFF0000);
	XV_multi_scaler_WriteReg(XPAR_PSU_GPIO_0_BASEADDR,
	XGPIOPS_DIRM_3_OFFSET, 0xFFFFFFFF);
	XV_multi_scaler_WriteReg(XPAR_PSU_GPIO_0_BASEADDR,
	XGPIOPS_OEN_3_OFFSET, 0xFFFFFFFF);
	XV_multi_scaler_WriteReg(XPAR_PSU_GPIO_0_BASEADDR,
	XGPIOPS_DATA_3_OFFSET, 0x00000001);
	XV_multi_scaler_WriteReg(XPAR_PSU_GPIO_0_BASEADDR,
	XGPIOPS_DATA_3_OFFSET, 0x00000000);
	XV_multi_scaler_WriteReg(XPAR_PSU_GPIO_0_BASEADDR,
	XGPIOPS_DATA_3_OFFSET, 0x00000001);
#endif
}
void XV_Reset_MultiScaler ( void ) { #if defined XPAR_GPIO_0_BASEADDR u32 count ; * ( u32 * ) ( GPIO_BASE ) = 0xFF ; for ( count = 0 ; count < 1000 ; count ++ ) ; * ( u32 * ) ( GPIO_BASE ) = 0x0 ; for ( count = 0 ; count < 1000 ; count ++ ) ; * ( u32 * ) ( GPIO_BASE ) = 0xFF ; for ( count = 0 ; count < 1000 ; count ++ ) ; #else XV_multi_scaler_WriteReg ( XPAR_PSU_GPIO_0_BASEADDR , XGPIOPS_MASK_DATA_3_LSW_OFFSET , 0xFFFF0000 ) ; XV_multi_scaler_WriteReg ( XPAR_PSU_GPIO_0_BASEADDR , XGPIOPS_DIRM_3_OFFSET , 0xFFFFFFFF ) ; XV_multi_scaler_WriteReg ( XPAR_PSU_GPIO_0_BASEADDR , XGPIOPS_OEN_3_OFFSET , 0xFFFFFFFF ) ; XV_multi_scaler_WriteReg ( XPAR_PSU_GPIO_0_BASEADDR , XGPIOPS_DATA_3_OFFSET , 0x00000001 ) ; XV_multi_scaler_WriteReg ( XPAR_PSU_GPIO_0_BASEADDR , XGPIOPS_DATA_3_OFFSET , 0x00000000 ) ; XV_multi_scaler_WriteReg ( XPAR_PSU_GPIO_0_BASEADDR , XGPIOPS_DATA_3_OFFSET , 0x00000001 ) ; #endif }
This function drives the reset pin of core high to start multiscaler core.
This function drives the reset pin of core high to start multiscaler core .