XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_hdmi.c
void XHdmiphy1_PatgenSetRatio(XHdmiphy1 *InstancePtr, u8 QuadId,
        u64 TxLineRate)
{
	u32 RegVal;

	/* Suppress Warning Messages */
    QuadId = QuadId;

	RegVal = (XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
				XHDMIPHY1_PATGEN_CTRL_REG)
				& ~XHDMIPHY1_PATGEN_CTRL_RATIO_MASK);

	if ((TxLineRate >= 3400) && (InstancePtr->HdmiTxSampleRate == 1)) {
		RegVal |= XHDMIPHY1_Patgen_Ratio_40 &
                        XHDMIPHY1_PATGEN_CTRL_RATIO_MASK;
	}
	else {
		RegVal |= InstancePtr->HdmiTxSampleRate &
						XHDMIPHY1_PATGEN_CTRL_RATIO_MASK;
	}

	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr,
						XHDMIPHY1_PATGEN_CTRL_REG, RegVal);
}
/*****************************************************************************/
/**
* This function sets the Pattern Generator for the GT Channel 4 when it is
* used to generate the TX TMDS Clock.
*
* @param	InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
* @param	TxLineRate in Mbps.
*
* @return	None.
*
******************************************************************************/
This function sets the Pattern Generator for the GT Channel 4 when it is
used to generate the TX TMDS Clock.
This function sets the Pattern Generator for the GT Channel 4 when it is used to generate the TX TMDS Clock .
void XHdmiphy1_PatgenSetRatio(XHdmiphy1 *InstancePtr, u8 QuadId,
        u64 TxLineRate)
{
	u32 RegVal;
    QuadId = QuadId;
	RegVal = (XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
				XHDMIPHY1_PATGEN_CTRL_REG)
				& ~XHDMIPHY1_PATGEN_CTRL_RATIO_MASK);
	if ((TxLineRate >= 3400) && (InstancePtr->HdmiTxSampleRate == 1)) {
		RegVal |= XHDMIPHY1_Patgen_Ratio_40 &
                        XHDMIPHY1_PATGEN_CTRL_RATIO_MASK;
	}
	else {
		RegVal |= InstancePtr->HdmiTxSampleRate &
						XHDMIPHY1_PATGEN_CTRL_RATIO_MASK;
	}
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr,
						XHDMIPHY1_PATGEN_CTRL_REG, RegVal);
}
void XHdmiphy1_PatgenSetRatio ( XHdmiphy1 * InstancePtr , u8 QuadId , u64 TxLineRate ) { u32 RegVal ; QuadId = QuadId ; RegVal = ( XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_PATGEN_CTRL_REG ) & ~ XHDMIPHY1_PATGEN_CTRL_RATIO_MASK ) ; if ( ( TxLineRate >= 3400 ) && ( InstancePtr -> HdmiTxSampleRate == 1 ) ) { RegVal |= XHDMIPHY1_Patgen_Ratio_40 & XHDMIPHY1_PATGEN_CTRL_RATIO_MASK ; } else { RegVal |= InstancePtr -> HdmiTxSampleRate & XHDMIPHY1_PATGEN_CTRL_RATIO_MASK ; } XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_PATGEN_CTRL_REG , RegVal ) ; }
This function sets the Pattern Generator for the GT Channel 4 when it is
used to generate the TX TMDS Clock.
This function sets the Pattern Generator for the GT Channel 4 when it is used to generate the TX TMDS Clock .
/* Suppress Warning Messages */