XilinxProcessorIPLib/drivers/dp12txss/examples/src/kcu/dppt_vid_phy_config.c
void Dppt_Tx_SetRefClocks(u8 DPLinkRate_Value, u8 Prog, u8 is_TX_CPLL)
{
//	XSpi SPI_LMK04906;  /* SPI Device Point*/

//	PLL_init_Seting(&SPI_LMK04906, CLK270MHz_DIVIDER);
	PLL_init_Seting(&SPI_LMK04906);
	xil_printf("Programming 270 MHz Clock for GTREFCLK0...\r\n");

}
//Board specific - Ref Clock settings
Board specific - Ref Clock settings
Board specific - Ref Clock settings
void Dppt_Tx_SetRefClocks(u8 DPLinkRate_Value, u8 Prog, u8 is_TX_CPLL)
{
	PLL_init_Seting(&SPI_LMK04906);
	xil_printf("Programming 270 MHz Clock for GTREFCLK0...\r\n");
}
void Dppt_Tx_SetRefClocks ( u8 DPLinkRate_Value , u8 Prog , u8 is_TX_CPLL ) { PLL_init_Seting ( & SPI_LMK04906 ) ; xil_printf ( " \r \n " ) ; }
Board specific - Ref Clock settings
Board specific - Ref Clock settings
//	XSpi SPI_LMK04906;  /* SPI Device Point*/ //	PLL_init_Seting(&SPI_LMK04906, CLK270MHz_DIVIDER);