lib/bsp/standalone/src/arm/ARMv8/32bit/xil_cache.c
void Xil_DCacheFlushRange(INTPTR adr, u32 len)
{
	const u32 cacheline = 64U;
	u32 end;
	u32 tempadr = adr;
	u32 tempend;
	u32 currmask;

	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);
	if (len != 0U) {
		end = tempadr + len;
		tempend = end;

		if ((tempadr & (cacheline-1U)) != 0U) {
			tempadr &= (~(cacheline - 1U));
			Xil_DCacheFlushLine(tempadr);
			tempadr += cacheline;
		}
		if ((tempend & (cacheline-1U)) != 0U) {
			tempend &= (~(cacheline - 1U));
			Xil_DCacheFlushLine(tempend);
		}

		while (tempadr < tempend) {
			/* Select cache level 0 and D cache in CSSR */
			mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
			/* Invalidate Data cache line */
			mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC,
				(tempadr & (~0x3F)));
			/* Wait for invalidate to complete */
			dsb();
			/* Select cache level 0 and D cache in CSSR */
			mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
			/* Invalidate Data cache line */
			mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC,
				(tempadr & (~0x3F)));
			/* Wait for invalidate to complete */
			dsb();
			tempadr += cacheline;
		}
	}
	mtcpsr(currmask);
}
/****************************************************************************/
/**
 * @brief	Flush the Data cache for the given address range.
 *		If the bytes specified by the address range are cached
 *		by the Data cache, the cachelines containing those bytes
 *		are invalidated. If the cachelines are modified (dirty),
 *		they are written to system memory before the lines are
 *		invalidated.
 *
 * @param	adr: 32bit start address of the range to be flushed.
 * @param	len: Length of range to be flushed in bytes.
 *
 * @return	None.
 *
 ****************************************************************************/
@brief       Flush the Data cache for the given address range.
If the bytes specified by the address range are cached
by the Data cache, the cachelines containing those bytes
are invalidated. If the cachelines are modified (dirty),
they are written to system memory before the lines are
invalidated.

@param       adr: 32bit start address of the range to be flushed.
@param       len: Length of range to be flushed in bytes.

@return      None.
@brief Flush the Data cache for the given address range . If the bytes specified by the address range are cached by the Data cache the cachelines containing those bytes are invalidated . If the cachelines are modified ( dirty ) they are written to system memory before the lines are invalidated . @param adr : 32bit start address of the range to be flushed . @param len : Length of range to be flushed in bytes . @return None .
void Xil_DCacheFlushRange(INTPTR adr, u32 len)
{
	const u32 cacheline = 64U;
	u32 end;
	u32 tempadr = adr;
	u32 tempend;
	u32 currmask;
	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);
	if (len != 0U) {
		end = tempadr + len;
		tempend = end;
		if ((tempadr & (cacheline-1U)) != 0U) {
			tempadr &= (~(cacheline - 1U));
			Xil_DCacheFlushLine(tempadr);
			tempadr += cacheline;
		}
		if ((tempend & (cacheline-1U)) != 0U) {
			tempend &= (~(cacheline - 1U));
			Xil_DCacheFlushLine(tempend);
		}
		while (tempadr < tempend) {
			mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
			mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC,
				(tempadr & (~0x3F)));
			dsb();
			mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
			mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC,
				(tempadr & (~0x3F)));
			dsb();
			tempadr += cacheline;
		}
	}
	mtcpsr(currmask);
}
void Xil_DCacheFlushRange ( INTPTR adr , u32 len ) { const u32 cacheline = 64U ; u32 end ; u32 tempadr = adr ; u32 tempend ; u32 currmask ; currmask = mfcpsr ( ) ; mtcpsr ( currmask | IRQ_FIQ_MASK ) ; if ( len != 0U ) { end = tempadr + len ; tempend = end ; if ( ( tempadr & ( cacheline - 1U ) ) != 0U ) { tempadr &= ( ~ ( cacheline - 1U ) ) ; Xil_DCacheFlushLine ( tempadr ) ; tempadr += cacheline ; } if ( ( tempend & ( cacheline - 1U ) ) != 0U ) { tempend &= ( ~ ( cacheline - 1U ) ) ; Xil_DCacheFlushLine ( tempend ) ; } while ( tempadr < tempend ) { mtcp ( XREG_CP15_CACHE_SIZE_SEL , 0x0 ) ; mtcp ( XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC , ( tempadr & ( ~ 0x3F ) ) ) ; dsb ( ) ; mtcp ( XREG_CP15_CACHE_SIZE_SEL , 0x2 ) ; mtcp ( XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC , ( tempadr & ( ~ 0x3F ) ) ) ; dsb ( ) ; tempadr += cacheline ; } } mtcpsr ( currmask ) ; }
@brief       Flush the Data cache for the given address range.
@brief Flush the Data cache for the given address range .
/* Select cache level 0 and D cache in CSSR */ /* Invalidate Data cache line */ /* Wait for invalidate to complete */ /* Select cache level 0 and D cache in CSSR */ /* Invalidate Data cache line */ /* Wait for invalidate to complete */