src/dpdk/drivers/net/ice/base/ice_common.c
static bool
ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
		      struct ice_aqc_list_caps_elem *elem, const char *prefix)
{
	u32 logical_id = LE32_TO_CPU(elem->logical_id);
	u32 phys_id = LE32_TO_CPU(elem->phys_id);
	u32 number = LE32_TO_CPU(elem->number);
	u16 cap = LE16_TO_CPU(elem->cap);
	bool found = true;

	switch (cap) {
	case ICE_AQC_CAPS_VALID_FUNCTIONS:
		caps->valid_functions = number;
		ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
			  caps->valid_functions);
		break;
	case ICE_AQC_CAPS_DCB:
		caps->dcb = (number == 1);
		caps->active_tc_bitmap = logical_id;
		caps->maxtc = phys_id;
		ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
		ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
			  caps->active_tc_bitmap);
		ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
		break;
	case ICE_AQC_CAPS_RSS:
		caps->rss_table_size = number;
		caps->rss_table_entry_width = logical_id;
		ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
			  caps->rss_table_size);
		ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
			  caps->rss_table_entry_width);
		break;
	case ICE_AQC_CAPS_RXQS:
		caps->num_rxq = number;
		caps->rxq_first_id = phys_id;
		ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
			  caps->num_rxq);
		ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
			  caps->rxq_first_id);
		break;
	case ICE_AQC_CAPS_TXQS:
		caps->num_txq = number;
		caps->txq_first_id = phys_id;
		ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
			  caps->num_txq);
		ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
			  caps->txq_first_id);
		break;
	case ICE_AQC_CAPS_MSIX:
		caps->num_msix_vectors = number;
		caps->msix_vector_first_id = phys_id;
		ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
			  caps->num_msix_vectors);
		ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
			  caps->msix_vector_first_id);
		break;
	case ICE_AQC_CAPS_NVM_MGMT:
		caps->sec_rev_disabled =
			(number & ICE_NVM_MGMT_SEC_REV_DISABLED) ?
			true : false;
		ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix,
			  caps->sec_rev_disabled);
		caps->update_disabled =
			(number & ICE_NVM_MGMT_UPDATE_DISABLED) ?
			true : false;
		ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix,
			  caps->update_disabled);
		caps->nvm_unified_update =
			(number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
			true : false;
		ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
			  caps->nvm_unified_update);
		break;
	case ICE_AQC_CAPS_MAX_MTU:
		caps->max_mtu = number;
		ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
			  prefix, caps->max_mtu);
		break;
	default:
		/* Not one of the recognized common capabilities */
		found = false;
	}

	return found;
}
/**
 * ice_parse_common_caps - parse common device/function capabilities
 * @hw: pointer to the HW struct
 * @caps: pointer to common capabilities structure
 * @elem: the capability element to parse
 * @prefix: message prefix for tracing capabilities
 *
 * Given a capability element, extract relevant details into the common
 * capability structure.
 *
 * Returns: true if the capability matches one of the common capability ids,
 * false otherwise.
 */
parse common device/function capabilities
@hw: pointer to the HW struct
@caps: pointer to common capabilities structure
@elem: the capability element to parse
@prefix: message prefix for tracing capabilities

Given a capability element, extract relevant details into the common
capability structure.

true if the capability matches one of the common capability ids,
false otherwise.
parse common device / function capabilities @hw : pointer to the HW struct @caps : pointer to common capabilities structure @elem : the capability element to parse @prefix : message prefix for tracing capabilities Given a capability element extract relevant details into the common capability structure . true if the capability matches one of the common capability ids false otherwise .
static bool
ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
		      struct ice_aqc_list_caps_elem *elem, const char *prefix)
{
	u32 logical_id = LE32_TO_CPU(elem->logical_id);
	u32 phys_id = LE32_TO_CPU(elem->phys_id);
	u32 number = LE32_TO_CPU(elem->number);
	u16 cap = LE16_TO_CPU(elem->cap);
	bool found = true;
	switch (cap) {
	case ICE_AQC_CAPS_VALID_FUNCTIONS:
		caps->valid_functions = number;
		ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
			  caps->valid_functions);
		break;
	case ICE_AQC_CAPS_DCB:
		caps->dcb = (number == 1);
		caps->active_tc_bitmap = logical_id;
		caps->maxtc = phys_id;
		ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
		ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
			  caps->active_tc_bitmap);
		ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
		break;
	case ICE_AQC_CAPS_RSS:
		caps->rss_table_size = number;
		caps->rss_table_entry_width = logical_id;
		ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
			  caps->rss_table_size);
		ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
			  caps->rss_table_entry_width);
		break;
	case ICE_AQC_CAPS_RXQS:
		caps->num_rxq = number;
		caps->rxq_first_id = phys_id;
		ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
			  caps->num_rxq);
		ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
			  caps->rxq_first_id);
		break;
	case ICE_AQC_CAPS_TXQS:
		caps->num_txq = number;
		caps->txq_first_id = phys_id;
		ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
			  caps->num_txq);
		ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
			  caps->txq_first_id);
		break;
	case ICE_AQC_CAPS_MSIX:
		caps->num_msix_vectors = number;
		caps->msix_vector_first_id = phys_id;
		ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
			  caps->num_msix_vectors);
		ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
			  caps->msix_vector_first_id);
		break;
	case ICE_AQC_CAPS_NVM_MGMT:
		caps->sec_rev_disabled =
			(number & ICE_NVM_MGMT_SEC_REV_DISABLED) ?
			true : false;
		ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix,
			  caps->sec_rev_disabled);
		caps->update_disabled =
			(number & ICE_NVM_MGMT_UPDATE_DISABLED) ?
			true : false;
		ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix,
			  caps->update_disabled);
		caps->nvm_unified_update =
			(number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
			true : false;
		ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
			  caps->nvm_unified_update);
		break;
	case ICE_AQC_CAPS_MAX_MTU:
		caps->max_mtu = number;
		ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
			  prefix, caps->max_mtu);
		break;
	default:
		found = false;
	}
	return found;
}
static bool ice_parse_common_caps ( struct ice_hw * hw , struct ice_hw_common_caps * caps , struct ice_aqc_list_caps_elem * elem , const char * prefix ) { u32 logical_id = LE32_TO_CPU ( elem -> logical_id ) ; u32 phys_id = LE32_TO_CPU ( elem -> phys_id ) ; u32 number = LE32_TO_CPU ( elem -> number ) ; u16 cap = LE16_TO_CPU ( elem -> cap ) ; bool found = true ; switch ( cap ) { case ICE_AQC_CAPS_VALID_FUNCTIONS : caps -> valid_functions = number ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> valid_functions ) ; break ; case ICE_AQC_CAPS_DCB : caps -> dcb = ( number == 1 ) ; caps -> active_tc_bitmap = logical_id ; caps -> maxtc = phys_id ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> dcb ) ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> active_tc_bitmap ) ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> maxtc ) ; break ; case ICE_AQC_CAPS_RSS : caps -> rss_table_size = number ; caps -> rss_table_entry_width = logical_id ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> rss_table_size ) ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> rss_table_entry_width ) ; break ; case ICE_AQC_CAPS_RXQS : caps -> num_rxq = number ; caps -> rxq_first_id = phys_id ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> num_rxq ) ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> rxq_first_id ) ; break ; case ICE_AQC_CAPS_TXQS : caps -> num_txq = number ; caps -> txq_first_id = phys_id ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> num_txq ) ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> txq_first_id ) ; break ; case ICE_AQC_CAPS_MSIX : caps -> num_msix_vectors = number ; caps -> msix_vector_first_id = phys_id ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> num_msix_vectors ) ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> msix_vector_first_id ) ; break ; case ICE_AQC_CAPS_NVM_MGMT : caps -> sec_rev_disabled = ( number & ICE_NVM_MGMT_SEC_REV_DISABLED ) ? true : false ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> sec_rev_disabled ) ; caps -> update_disabled = ( number & ICE_NVM_MGMT_UPDATE_DISABLED ) ? true : false ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> update_disabled ) ; caps -> nvm_unified_update = ( number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT ) ? true : false ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> nvm_unified_update ) ; break ; case ICE_AQC_CAPS_MAX_MTU : caps -> max_mtu = number ; ice_debug ( hw , ICE_DBG_INIT , " \n " , prefix , caps -> max_mtu ) ; break ; default : found = false ; } return found ; }
ice_parse_common_caps - parse common device/function capabilities
 @hw: pointer to the HW struct
 @caps: pointer to common capabilities structure
 @elem: the capability element to parse
 @prefix: message prefix for tracing capabilities
ice_parse_common_caps - parse common device / function capabilities @hw : pointer to the HW struct @caps : pointer to common capabilities structure @elem : the capability element to parse @prefix : message prefix for tracing capabilities
/* Not one of the recognized common capabilities */