src/memory/memory.c
void update_memory() {
  if(freq_is_ready(FREQ_DOMAIN_L1)) {
    cycle_count = freq_cycle_count(FREQ_DOMAIN_L1);

    perf_pred_cycle();

    pref_update();
    update_memory_queues();
    update_on_chip_memory_stats();

    mem_process_mlc_fill_reqs();
    mem_process_l1_fill_reqs();
  }

  if(freq_is_ready(FREQ_DOMAIN_MEMORY)) {
    cycle_count = freq_cycle_count(FREQ_DOMAIN_MEMORY);

    // dram_process_main_memory_reqs();
    ramulator_tick();
  }

  if(freq_is_ready(FREQ_DOMAIN_L1)) {
    cycle_count = freq_cycle_count(FREQ_DOMAIN_L1);

    mem_process_bus_out_reqs();
    mem_process_l1_reqs();
    mem_process_mlc_reqs();
  }

  for(uns proc_id = 0; proc_id < NUM_CORES; proc_id++) {
    if(freq_is_ready(FREQ_DOMAIN_CORES[proc_id])) {
      cycle_count = freq_cycle_count(FREQ_DOMAIN_CORES[proc_id]);
      mem_process_core_fill_reqs(proc_id);
    }
  }
}
/**
 * @brief simulate the memory system for one cycle
 * functions are called in reverse order, that's fill queues (req going back to
 * cpu), first, then ramulator (DRAM), then request queues (reg going down to
 * mem)
 *
 */
@brief simulate the memory system for one cycle
functions are called in reverse order, that's fill queues (req going back to
cpu), first, then ramulator (DRAM), then request queues (reg going down to
mem)
@brief simulate the memory system for one cycle functions are called in reverse order that ' s fill queues ( req going back to cpu ) first then ramulator ( DRAM ) then request queues ( reg going down to mem )
void update_memory() {
  if(freq_is_ready(FREQ_DOMAIN_L1)) {
    cycle_count = freq_cycle_count(FREQ_DOMAIN_L1);
    perf_pred_cycle();
    pref_update();
    update_memory_queues();
    update_on_chip_memory_stats();
    mem_process_mlc_fill_reqs();
    mem_process_l1_fill_reqs();
  }
  if(freq_is_ready(FREQ_DOMAIN_MEMORY)) {
    cycle_count = freq_cycle_count(FREQ_DOMAIN_MEMORY);
    ramulator_tick();
  }
  if(freq_is_ready(FREQ_DOMAIN_L1)) {
    cycle_count = freq_cycle_count(FREQ_DOMAIN_L1);
    mem_process_bus_out_reqs();
    mem_process_l1_reqs();
    mem_process_mlc_reqs();
  }
  for(uns proc_id = 0; proc_id < NUM_CORES; proc_id++) {
    if(freq_is_ready(FREQ_DOMAIN_CORES[proc_id])) {
      cycle_count = freq_cycle_count(FREQ_DOMAIN_CORES[proc_id]);
      mem_process_core_fill_reqs(proc_id);
    }
  }
}
void update_memory ( ) { if ( freq_is_ready ( FREQ_DOMAIN_L1 ) ) { cycle_count = freq_cycle_count ( FREQ_DOMAIN_L1 ) ; perf_pred_cycle ( ) ; pref_update ( ) ; update_memory_queues ( ) ; update_on_chip_memory_stats ( ) ; mem_process_mlc_fill_reqs ( ) ; mem_process_l1_fill_reqs ( ) ; } if ( freq_is_ready ( FREQ_DOMAIN_MEMORY ) ) { cycle_count = freq_cycle_count ( FREQ_DOMAIN_MEMORY ) ; ramulator_tick ( ) ; } if ( freq_is_ready ( FREQ_DOMAIN_L1 ) ) { cycle_count = freq_cycle_count ( FREQ_DOMAIN_L1 ) ; mem_process_bus_out_reqs ( ) ; mem_process_l1_reqs ( ) ; mem_process_mlc_reqs ( ) ; } for ( uns proc_id = 0 ; proc_id < NUM_CORES ; proc_id ++ ) { if ( freq_is_ready ( FREQ_DOMAIN_CORES [ proc_id ] ) ) { cycle_count = freq_cycle_count ( FREQ_DOMAIN_CORES [ proc_id ] ) ; mem_process_core_fill_reqs ( proc_id ) ; } } }
@brief simulate the memory system for one cycle
 functions are called in reverse order, that's fill queues (req going back to
 cpu), first, then ramulator (DRAM), then request queues (reg going down to
 mem)
@brief simulate the memory system for one cycle functions are called in reverse order that ' s fill queues ( req going back to cpu ) first then ramulator ( DRAM ) then request queues ( reg going down to mem )
// dram_process_main_memory_reqs();