XilinxProcessorIPLib/drivers/hdcp1x/src/xhdcp1x_cipher.c
int XHdcp1x_CipherEnableEncryption(XHdcp1x *InstancePtr, u64 StreamMap)
{
	u32 Value = 0;

	/* Verify arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);

	/* Check that it is not disabled */
	if (!XHdcp1x_CipherIsEnabled(InstancePtr)) {
		return (XST_NOT_ENABLED);
	}

	/* Check that it is not a receiver */
	if (XHdcp1x_IsRX(InstancePtr)) {
		return (XST_FAILURE);
	}

	/* Check for nothing to do */
	if (StreamMap == 0) {
		return (XST_SUCCESS);
	}

	/* Clear the register update bit */
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Value &= ~XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Value);

	/* Update the LS 32-bits */
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L);
	Value |= ((u32) (StreamMap & 0xFFFFFFFFul));
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L, Value);

	/* Write the MS 32-bits */
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H);
	Value |= ((u32) ((StreamMap >> 32) & 0xFFFFFFFFul));
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H, Value);

	/* Ensure that the XOR is enabled */
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_CONTROL);
	Value |= XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_XOR_ENABLE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_CONTROL, Value);

	/* Set the register update bit */
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Value |= XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Value);

	/* Check if XORInProgress bit is set in the status register*/
	if (!XHdcp1x_CipherXorInProgress(InstancePtr)) {
		/* Do nothing for now. We can depend on the Cipher
		 * to set the XorInProgress in status register when
		 * we receive protected content. */
	}

	return (XST_SUCCESS);
}
/*****************************************************************************/
/**
* This function enables encryption on a set of streams.
*
* @param	InstancePtr is the device to configure.
* @param	StreamMap is the bit map of streams to enable encryption on.
*
* @return
*		- XST_SUCCESS if successful.
*		- XST_NOT_ENABLE if the core is not enabled.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function enables encryption on a set of streams.
This function enables encryption on a set of streams .
int XHdcp1x_CipherEnableEncryption(XHdcp1x *InstancePtr, u64 StreamMap)
{
	u32 Value = 0;
	Xil_AssertNonvoid(InstancePtr != NULL);
	if (!XHdcp1x_CipherIsEnabled(InstancePtr)) {
		return (XST_NOT_ENABLED);
	}
	if (XHdcp1x_IsRX(InstancePtr)) {
		return (XST_FAILURE);
	}
	if (StreamMap == 0) {
		return (XST_SUCCESS);
	}
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Value &= ~XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Value);
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L);
	Value |= ((u32) (StreamMap & 0xFFFFFFFFul));
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L, Value);
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H);
	Value |= ((u32) ((StreamMap >> 32) & 0xFFFFFFFFul));
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H, Value);
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_CONTROL);
	Value |= XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_XOR_ENABLE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CIPHER_CONTROL, Value);
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Value |= XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Value);
	if (!XHdcp1x_CipherXorInProgress(InstancePtr)) {
	}
	return (XST_SUCCESS);
}
int XHdcp1x_CipherEnableEncryption ( XHdcp1x * InstancePtr , u64 StreamMap ) { u32 Value = 0 ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; if ( ! XHdcp1x_CipherIsEnabled ( InstancePtr ) ) { return ( XST_NOT_ENABLED ) ; } if ( XHdcp1x_IsRX ( InstancePtr ) ) { return ( XST_FAILURE ) ; } if ( StreamMap == 0 ) { return ( XST_SUCCESS ) ; } Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL ) ; Value &= ~ XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL , Value ) ; Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L ) ; Value |= ( ( u32 ) ( StreamMap & 0xFFFFFFFFul ) ) ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L , Value ) ; Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H ) ; Value |= ( ( u32 ) ( ( StreamMap >> 32 ) & 0xFFFFFFFFul ) ) ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H , Value ) ; Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CIPHER_CONTROL ) ; Value |= XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_XOR_ENABLE ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CIPHER_CONTROL , Value ) ; Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL ) ; Value |= XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL , Value ) ; if ( ! XHdcp1x_CipherXorInProgress ( InstancePtr ) ) { } return ( XST_SUCCESS ) ; }
This function enables encryption on a set of streams.
This function enables encryption on a set of streams .
/* Verify arguments. */ /* Check that it is not disabled */ /* Check that it is not a receiver */ /* Check for nothing to do */ /* Clear the register update bit */ /* Update the LS 32-bits */ /* Write the MS 32-bits */ /* Ensure that the XOR is enabled */ /* Set the register update bit */ /* Check if XORInProgress bit is set in the status register*/ /* Do nothing for now. We can depend on the Cipher
		 * to set the XorInProgress in status register when
		 * we receive protected content. */