src/dpdk/drivers/net/cxgbe/base/t4_hw.c
int t4_prep_adapter(struct adapter *adapter)
{
	int ret, ver;
	u32 pl_rev;

	ret = t4_wait_dev_ready(adapter);
	if (ret < 0)
		return ret;

	pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
	adapter->params.pci.device_id = adapter->pdev->id.device_id;
	adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;

	/*
	 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
	 * ADAPTER (VERSION << 4 | REVISION)
	 */
	ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
	adapter->params.chip = 0;
	switch (ver) {
	case CHELSIO_T5:
		adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
		adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
		adapter->params.arch.mps_tcam_size =
						NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
		adapter->params.arch.mps_rplc_size = 128;
		adapter->params.arch.nchan = NCHAN;
		adapter->params.arch.vfcount = 128;
		/* Congestion map is for 4 channels so that
		 * MPS can have 4 priority per port.
		 */
		adapter->params.arch.cng_ch_bits_log = 2;
		break;
	case CHELSIO_T6:
		adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
		adapter->params.arch.sge_fl_db = 0;
		adapter->params.arch.mps_tcam_size =
						NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
		adapter->params.arch.mps_rplc_size = 256;
		adapter->params.arch.nchan = 2;
		adapter->params.arch.vfcount = 256;
		/* Congestion map is for 2 channels so that
		 * MPS can have 8 priority per port.
		 */
		adapter->params.arch.cng_ch_bits_log = 3;
		break;
	default:
		dev_err(adapter, "%s: Device %d is not supported\n",
			__func__, adapter->params.pci.device_id);
		return -EINVAL;
	}

	adapter->params.pci.vpd_cap_addr =
		t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);

	ret = t4_get_flash_params(adapter);
	if (ret < 0) {
		dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
			-ret);
		return ret;
	}

	adapter->params.cim_la_size = CIMLA_SIZE;

	init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);

	/*
	 * Default port and clock for debugging in case we can't reach FW.
	 */
	adapter->params.nports = 1;
	adapter->params.portvec = 1;
	adapter->params.vpd.cclk = 50000;

	/* Set pci completion timeout value to 4 seconds. */
	set_pcie_completion_timeout(adapter, 0xd);
	return 0;
}
/**
 * t4_prep_adapter - prepare SW and HW for operation
 * @adapter: the adapter
 *
 * Initialize adapter SW state for the various HW modules, set initial
 * values for some adapter tunables, take PHYs out of reset, and
 * initialize the MDIO interface.
 */
prepare SW and HW for operation
@adapter: the adapter

Initialize adapter SW state for the various HW modules, set initial
values for some adapter tunables, take PHYs out of reset, and
initialize the MDIO interface.
prepare SW and HW for operation @adapter : the adapter Initialize adapter SW state for the various HW modules set initial values for some adapter tunables take PHYs out of reset and initialize the MDIO interface .
int t4_prep_adapter(struct adapter *adapter)
{
	int ret, ver;
	u32 pl_rev;
	ret = t4_wait_dev_ready(adapter);
	if (ret < 0)
		return ret;
	pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
	adapter->params.pci.device_id = adapter->pdev->id.device_id;
	adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
	ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
	adapter->params.chip = 0;
	switch (ver) {
	case CHELSIO_T5:
		adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
		adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
		adapter->params.arch.mps_tcam_size =
						NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
		adapter->params.arch.mps_rplc_size = 128;
		adapter->params.arch.nchan = NCHAN;
		adapter->params.arch.vfcount = 128;
		adapter->params.arch.cng_ch_bits_log = 2;
		break;
	case CHELSIO_T6:
		adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
		adapter->params.arch.sge_fl_db = 0;
		adapter->params.arch.mps_tcam_size =
						NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
		adapter->params.arch.mps_rplc_size = 256;
		adapter->params.arch.nchan = 2;
		adapter->params.arch.vfcount = 256;
		adapter->params.arch.cng_ch_bits_log = 3;
		break;
	default:
		dev_err(adapter, "%s: Device %d is not supported\n",
			__func__, adapter->params.pci.device_id);
		return -EINVAL;
	}
	adapter->params.pci.vpd_cap_addr =
		t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
	ret = t4_get_flash_params(adapter);
	if (ret < 0) {
		dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
			-ret);
		return ret;
	}
	adapter->params.cim_la_size = CIMLA_SIZE;
	init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
	adapter->params.nports = 1;
	adapter->params.portvec = 1;
	adapter->params.vpd.cclk = 50000;
	set_pcie_completion_timeout(adapter, 0xd);
	return 0;
}
int t4_prep_adapter ( struct adapter * adapter ) { int ret , ver ; u32 pl_rev ; ret = t4_wait_dev_ready ( adapter ) ; if ( ret < 0 ) return ret ; pl_rev = G_REV ( t4_read_reg ( adapter , A_PL_REV ) ) ; adapter -> params . pci . device_id = adapter -> pdev -> id . device_id ; adapter -> params . pci . vendor_id = adapter -> pdev -> id . vendor_id ; ver = CHELSIO_PCI_ID_VER ( adapter -> params . pci . device_id ) ; adapter -> params . chip = 0 ; switch ( ver ) { case CHELSIO_T5 : adapter -> params . chip |= CHELSIO_CHIP_CODE ( CHELSIO_T5 , pl_rev ) ; adapter -> params . arch . sge_fl_db = F_DBPRIO | F_DBTYPE ; adapter -> params . arch . mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES ; adapter -> params . arch . mps_rplc_size = 128 ; adapter -> params . arch . nchan = NCHAN ; adapter -> params . arch . vfcount = 128 ; adapter -> params . arch . cng_ch_bits_log = 2 ; break ; case CHELSIO_T6 : adapter -> params . chip |= CHELSIO_CHIP_CODE ( CHELSIO_T6 , pl_rev ) ; adapter -> params . arch . sge_fl_db = 0 ; adapter -> params . arch . mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES ; adapter -> params . arch . mps_rplc_size = 256 ; adapter -> params . arch . nchan = 2 ; adapter -> params . arch . vfcount = 256 ; adapter -> params . arch . cng_ch_bits_log = 3 ; break ; default : dev_err ( adapter , " \n " , __func__ , adapter -> params . pci . device_id ) ; return - EINVAL ; } adapter -> params . pci . vpd_cap_addr = t4_os_find_pci_capability ( adapter , PCI_CAP_ID_VPD ) ; ret = t4_get_flash_params ( adapter ) ; if ( ret < 0 ) { dev_err ( adapter , " \n " , - ret ) ; return ret ; } adapter -> params . cim_la_size = CIMLA_SIZE ; init_cong_ctrl ( adapter -> params . a_wnd , adapter -> params . b_wnd ) ; adapter -> params . nports = 1 ; adapter -> params . portvec = 1 ; adapter -> params . vpd . cclk = 50000 ; set_pcie_completion_timeout ( adapter , 0xd ) ; return 0 ; }
t4_prep_adapter - prepare SW and HW for operation
 @adapter: the adapter
t4_prep_adapter - prepare SW and HW for operation @adapter : the adapter
/*
	 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
	 * ADAPTER (VERSION << 4 | REVISION)
	 */ /* Congestion map is for 4 channels so that
		 * MPS can have 4 priority per port.
		 */ /* Congestion map is for 2 channels so that
		 * MPS can have 8 priority per port.
		 */ /*
	 * Default port and clock for debugging in case we can't reach FW.
	 */ /* Set pci completion timeout value to 4 seconds. */