XilinxProcessorIPLib/drivers/aiengine/src/tile/xaietile_strm.c
void XAieTile_StrmConfigMstr(XAieGbl_Tile *TileInstPtr, u8 Master, u8 Enable,
						u8 PktEnable, u8 Config)
{
	u64 RegAddr;
	u32 RegVal = 0U;
        u8 DropHdr = 0U;
        XAieGbl_RegStrmMstr *RegPtr;

	XAie_AssertNonvoid(TileInstPtr != XAIE_NULL);

       	if(TileInstPtr->TileType == XAIEGBL_TILE_TYPE_AIETILE) {
                RegPtr = &TileStrmMstr[Master];
        } else {
                RegPtr = &ShimStrmMstr[Master];
        }

	/* Get the address of Master port config reg */
	RegAddr = TileInstPtr->TileAddr + RegPtr->RegOff;

	if(Enable == XAIE_ENABLE) {
                /* Extract the drop header field */
                DropHdr = XAie_GetField(Config, RegPtr->DrpHdr.Lsb,
                                                RegPtr->DrpHdr.Mask);
		/* Frame the 32-bit reg value */
		RegVal = XAie_SetField(Enable, RegPtr->MstrEn.Lsb,
					RegPtr->MstrEn.Mask) |
			XAie_SetField(PktEnable, RegPtr->PktEn.Lsb,
					RegPtr->PktEn.Mask) |
                        XAie_SetField(DropHdr, RegPtr->DrpHdr.Lsb,
					RegPtr->DrpHdr.Mask) |
			XAie_SetField(Config, RegPtr->Config.Lsb,
					RegPtr->Config.Mask);
	}
	XAieGbl_Write32(RegAddr, RegVal);
}
/************************** Function Definitions *****************************/
/*****************************************************************************/
/**
*
* This API is used to configure the selected master port of the stream switch
* in the corresponding tile as per the parameters.
*
* @param	TileInstPtr - Pointer to the Tile instance.
* @param	Master - Master port ID value.
* @param	Enable - Enable/Disable the master port
*		(1-Enable,0-Disable).

* @param	PktEnable - Enable/Disable the packet switching mode
*		(1-Enable,0-Disable).

* @param	Config - Config value to be used for circuit/packet sw.
*		Applicable only when Enable==1.
*		Bit encoding when PktEnable==1: 7-Drop header on packet,
*		6:3-Mask, 2:0-Arbiter
*		Bit encoding when PktEnable==0: 7:5-Rsvd, 4:0-Slave port ID to
*		which the master port need to connect to
*		Use the macro "xaietile_strm.c::XAIETILE_STRSW_MPORT_CFGPKT()" to
*		frame the 8-bit Config.
*
* @return	None.
*
* @note		None.
*
*******************************************************************************/
Function Definitions
This API is used to configure the selected master port of the stream switch
in the corresponding tile as per the parameters.
Function Definitions This API is used to configure the selected master port of the stream switch in the corresponding tile as per the parameters .
void XAieTile_StrmConfigMstr(XAieGbl_Tile *TileInstPtr, u8 Master, u8 Enable,
						u8 PktEnable, u8 Config)
{
	u64 RegAddr;
	u32 RegVal = 0U;
        u8 DropHdr = 0U;
        XAieGbl_RegStrmMstr *RegPtr;
	XAie_AssertNonvoid(TileInstPtr != XAIE_NULL);
       	if(TileInstPtr->TileType == XAIEGBL_TILE_TYPE_AIETILE) {
                RegPtr = &TileStrmMstr[Master];
        } else {
                RegPtr = &ShimStrmMstr[Master];
        }
	RegAddr = TileInstPtr->TileAddr + RegPtr->RegOff;
	if(Enable == XAIE_ENABLE) {
                DropHdr = XAie_GetField(Config, RegPtr->DrpHdr.Lsb,
                                                RegPtr->DrpHdr.Mask);
		RegVal = XAie_SetField(Enable, RegPtr->MstrEn.Lsb,
					RegPtr->MstrEn.Mask) |
			XAie_SetField(PktEnable, RegPtr->PktEn.Lsb,
					RegPtr->PktEn.Mask) |
                        XAie_SetField(DropHdr, RegPtr->DrpHdr.Lsb,
					RegPtr->DrpHdr.Mask) |
			XAie_SetField(Config, RegPtr->Config.Lsb,
					RegPtr->Config.Mask);
	}
	XAieGbl_Write32(RegAddr, RegVal);
}
void XAieTile_StrmConfigMstr ( XAieGbl_Tile * TileInstPtr , u8 Master , u8 Enable , u8 PktEnable , u8 Config ) { u64 RegAddr ; u32 RegVal = 0U ; u8 DropHdr = 0U ; XAieGbl_RegStrmMstr * RegPtr ; XAie_AssertNonvoid ( TileInstPtr != XAIE_NULL ) ; if ( TileInstPtr -> TileType == XAIEGBL_TILE_TYPE_AIETILE ) { RegPtr = & TileStrmMstr [ Master ] ; } else { RegPtr = & ShimStrmMstr [ Master ] ; } RegAddr = TileInstPtr -> TileAddr + RegPtr -> RegOff ; if ( Enable == XAIE_ENABLE ) { DropHdr = XAie_GetField ( Config , RegPtr -> DrpHdr . Lsb , RegPtr -> DrpHdr . Mask ) ; RegVal = XAie_SetField ( Enable , RegPtr -> MstrEn . Lsb , RegPtr -> MstrEn . Mask ) | XAie_SetField ( PktEnable , RegPtr -> PktEn . Lsb , RegPtr -> PktEn . Mask ) | XAie_SetField ( DropHdr , RegPtr -> DrpHdr . Lsb , RegPtr -> DrpHdr . Mask ) | XAie_SetField ( Config , RegPtr -> Config . Lsb , RegPtr -> Config . Mask ) ; } XAieGbl_Write32 ( RegAddr , RegVal ) ; }
Function Definitions
This API is used to configure the selected master port of the stream switch
in the corresponding tile as per the parameters.
Function Definitions This API is used to configure the selected master port of the stream switch in the corresponding tile as per the parameters .
/* Get the address of Master port config reg */ /* Extract the drop header field */ /* Frame the 32-bit reg value */