lib/sw_apps/zynqmp_fsbl/src/xfsbl_ddr_init.c
static u32 XFsbl_PhyCalcCommonRegVal(XFsbl_DimmParams *PDimmPtr, u32 *PhyCfg)
{
	u32 MemSize = 0U;
	u32 Lp4DramSize = 0U;
	u32 NumRank = 0U;

	PhyCfg[PHY_ADCP] = PDimmPtr->AddrMirror;

	if (!PDimmPtr->PhyClkGate) {
		PhyCfg[PHY_GATEACRDCLK] = 0x2U;
		PhyCfg[PHY_GATEACDDRCLK] = 0x2U;
		PhyCfg[PHY_GATEACCTLCLK] = 0x2U;
	}

	if (PDimmPtr->FreqB) {
		PhyCfg[PHY_DDLPGACT] = 1U;
		PhyCfg[PHY_DDLPGRW] = 1U;
	}

	PhyCfg[PHY_TPLLPD] = (u32)XFsbl_Ceil(1000U / (PDimmPtr->ClockPeriod * 2U));

	PhyCfg[PHY_TPLLGS] = (u32)XFsbl_Ceil(4000.0 / (PDimmPtr->ClockPeriod * 2U));

	PhyCfg[PHY_TPLLLOCK] = (u32)XFsbl_Ceil(100000.0 / (PDimmPtr->ClockPeriod * 2U));

	PhyCfg[PHY_TPLLRST] = (u32)XFsbl_Ceil(9000.0 / (PDimmPtr->ClockPeriod * 2U));

	PhyCfg[PHY_PLLBYP] = PDimmPtr->PllByp;

	if (PDimmPtr->CtlClkFreq >  668U) {
		PhyCfg[PHY_FRQSEL] = 8U;
		PhyCfg[PHY_CPPC] = 5U;
		PhyCfg[PHY_CPIC] = 0U;
	} else if (PDimmPtr->CtlClkFreq >  560U) {
		PhyCfg[PHY_FRQSEL] = 0U;
		PhyCfg[PHY_CPPC] = 7U;
		PhyCfg[PHY_CPIC] = 0U;
	} else if (PDimmPtr->CtlClkFreq >  471U) {
		PhyCfg[PHY_FRQSEL] = 1U;
		PhyCfg[PHY_CPPC] = 8U;
		PhyCfg[PHY_CPIC] = 0U;
	} else if (PDimmPtr->CtlClkFreq >  396U) {
		PhyCfg[PHY_FRQSEL] = 2U;
		PhyCfg[PHY_CPPC] = 9U;
		PhyCfg[PHY_CPIC] = 0U;
	} else if (PDimmPtr->CtlClkFreq >  332U) {
		PhyCfg[PHY_FRQSEL] = 3U;
		PhyCfg[PHY_CPPC] = 10U;
		PhyCfg[PHY_CPIC] = 0U;
	} else if (PDimmPtr->CtlClkFreq >  279U) {
		PhyCfg[PHY_FRQSEL] = 4U;
		PhyCfg[PHY_CPPC] = 6U;
		PhyCfg[PHY_CPIC] = 1U;
	} else if (PDimmPtr->CtlClkFreq >  235U) {
		PhyCfg[PHY_FRQSEL] = 5U;
		PhyCfg[PHY_CPPC] = 8U;
	} else if (PDimmPtr->CtlClkFreq >  197U) {
		PhyCfg[PHY_FRQSEL] = 6U;
		PhyCfg[PHY_CPPC] = 9U;
		PhyCfg[PHY_CPIC] = 2U;
	} else if (PDimmPtr->CtlClkFreq >= 166U) {
		PhyCfg[PHY_FRQSEL] = 7U;
		PhyCfg[PHY_CPPC] = 10U;
		PhyCfg[PHY_CPIC] = 3U;
	}

	PhyCfg[PHY_PUAD] = (u32)(10U / PDimmPtr->ClockPeriod / 2.0);

	if (PDimmPtr->UDimm & PDimmPtr->AddrMirror)
		PhyCfg[PHY_UDIMM] = 1U;

	if (PDimmPtr->En2tTimingMode) {
		PhyCfg[PHY_TRAS] = (u32)XFsbl_Ceil(((PDimmPtr->TRasPs / 1000.0) /
					PDimmPtr->ClockPeriod / 2.0)) * 2U;
	} else {
		PhyCfg[PHY_TRAS] = XFsbl_Round(((PDimmPtr->TRasPs / 1000.0) /
					PDimmPtr->ClockPeriod / 2.0)) * 2U;
	}

	PhyCfg[PHY_TRP] = (PDimmPtr->TRpPs / 1000.0) + 2U;

	PhyCfg[PHY_TFAW] = (u32)XFsbl_Ceil((PDimmPtr->TFawPs / 1000.0) / PDimmPtr->ClockPeriod);

	PhyCfg[PHY_TRFC] = (u32)XFsbl_Ceil((PDimmPtr->TRfcPs / 1000.0) / PDimmPtr->ClockPeriod);

	PhyCfg[PHY_TRC] = (u32)XFsbl_Ceil((PDimmPtr->TRcPs / 1000.0) / PDimmPtr->ClockPeriod) + 1U;

	PhyCfg[PHY_TWTR] = PDimmPtr->TWtr;

	PhyCfg[PHY_PUBWL] = PDimmPtr->WriteLatency;

	PhyCfg[PHY_PUBRL] = PDimmPtr->ReadLatency;

	PhyCfg[PHY_ERROUTODT] = PDimmPtr->Crc;

	PhyCfg[PHY_RDIMM] = PDimmPtr->RDimm;

	PhyCfg[PHY_DTDRS] = PDimmPtr->NumRankAddr;

	PhyCfg[PHY_RANKEN] = (2U * PDimmPtr->NumRankAddr) + 1U;

	Lp4DramSize = (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) ? 32U : PDimmPtr->DramWidth;

	NumRank = (PDimmPtr->Zc1656 || PDimmPtr->HasEccComp) ? 0U : PDimmPtr->NumRankAddr;
	MemSize = ((PDimmPtr->BusWidth / Lp4DramSize) * PDimmPtr->Capacity * (1U << NumRank)) / 8U;
	PhyCfg[PHY_SEED] = (0x12340000U) | MemSize;

	PhyCfg[PHY_DVMIN] = (PDimmPtr->Lp4NoOdt) ? 0x27U : 0U;

	PhyCfg[PHY_PGWAIT_FRQA] = (u32)(40U / (PDimmPtr->ClockPeriod) / 2U);

	if (PDimmPtr->HostDrv == 34U) {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xDU;
	} else if (PDimmPtr->HostDrv == 40U) {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xBU;
	} else if (PDimmPtr->HostDrv == 48U) {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x9U;
	} else if (PDimmPtr->HostDrv == 60U) {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x7U;
	} else if (PDimmPtr->HostDrv == 80U) {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x5U;
	} else if (PDimmPtr->HostDrv == 120U) {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x3U;
	} else {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xBU;
	}

	PhyCfg[PHY_ZPROG_ASYM_DRV_PU] = PhyCfg[PHY_ZPROG_ASYM_DRV_PD];

	return XFSBL_SUCCESS;
}
/*****************************************************************************/
/**
 * This function calculates the PHY register values common to all DDR types
 *
 * @param	PDimmPtr is pointer to DIMM parameters Data Structure
 * @param	PhyCfg is the array to store register field values
 *
 * @return	None
 *
 *****************************************************************************/
This function calculates the PHY register values common to all DDR types
@param       PDimmPtr is pointer to DIMM parameters Data Structure
@param       PhyCfg is the array to store register field values

@return      None
This function calculates the PHY register values common to all DDR types @param PDimmPtr is pointer to DIMM parameters Data Structure @param PhyCfg is the array to store register field values @return None
static u32 XFsbl_PhyCalcCommonRegVal(XFsbl_DimmParams *PDimmPtr, u32 *PhyCfg)
{
	u32 MemSize = 0U;
	u32 Lp4DramSize = 0U;
	u32 NumRank = 0U;
	PhyCfg[PHY_ADCP] = PDimmPtr->AddrMirror;
	if (!PDimmPtr->PhyClkGate) {
		PhyCfg[PHY_GATEACRDCLK] = 0x2U;
		PhyCfg[PHY_GATEACDDRCLK] = 0x2U;
		PhyCfg[PHY_GATEACCTLCLK] = 0x2U;
	}
	if (PDimmPtr->FreqB) {
		PhyCfg[PHY_DDLPGACT] = 1U;
		PhyCfg[PHY_DDLPGRW] = 1U;
	}
	PhyCfg[PHY_TPLLPD] = (u32)XFsbl_Ceil(1000U / (PDimmPtr->ClockPeriod * 2U));
	PhyCfg[PHY_TPLLGS] = (u32)XFsbl_Ceil(4000.0 / (PDimmPtr->ClockPeriod * 2U));
	PhyCfg[PHY_TPLLLOCK] = (u32)XFsbl_Ceil(100000.0 / (PDimmPtr->ClockPeriod * 2U));
	PhyCfg[PHY_TPLLRST] = (u32)XFsbl_Ceil(9000.0 / (PDimmPtr->ClockPeriod * 2U));
	PhyCfg[PHY_PLLBYP] = PDimmPtr->PllByp;
	if (PDimmPtr->CtlClkFreq >  668U) {
		PhyCfg[PHY_FRQSEL] = 8U;
		PhyCfg[PHY_CPPC] = 5U;
		PhyCfg[PHY_CPIC] = 0U;
	} else if (PDimmPtr->CtlClkFreq >  560U) {
		PhyCfg[PHY_FRQSEL] = 0U;
		PhyCfg[PHY_CPPC] = 7U;
		PhyCfg[PHY_CPIC] = 0U;
	} else if (PDimmPtr->CtlClkFreq >  471U) {
		PhyCfg[PHY_FRQSEL] = 1U;
		PhyCfg[PHY_CPPC] = 8U;
		PhyCfg[PHY_CPIC] = 0U;
	} else if (PDimmPtr->CtlClkFreq >  396U) {
		PhyCfg[PHY_FRQSEL] = 2U;
		PhyCfg[PHY_CPPC] = 9U;
		PhyCfg[PHY_CPIC] = 0U;
	} else if (PDimmPtr->CtlClkFreq >  332U) {
		PhyCfg[PHY_FRQSEL] = 3U;
		PhyCfg[PHY_CPPC] = 10U;
		PhyCfg[PHY_CPIC] = 0U;
	} else if (PDimmPtr->CtlClkFreq >  279U) {
		PhyCfg[PHY_FRQSEL] = 4U;
		PhyCfg[PHY_CPPC] = 6U;
		PhyCfg[PHY_CPIC] = 1U;
	} else if (PDimmPtr->CtlClkFreq >  235U) {
		PhyCfg[PHY_FRQSEL] = 5U;
		PhyCfg[PHY_CPPC] = 8U;
	} else if (PDimmPtr->CtlClkFreq >  197U) {
		PhyCfg[PHY_FRQSEL] = 6U;
		PhyCfg[PHY_CPPC] = 9U;
		PhyCfg[PHY_CPIC] = 2U;
	} else if (PDimmPtr->CtlClkFreq >= 166U) {
		PhyCfg[PHY_FRQSEL] = 7U;
		PhyCfg[PHY_CPPC] = 10U;
		PhyCfg[PHY_CPIC] = 3U;
	}
	PhyCfg[PHY_PUAD] = (u32)(10U / PDimmPtr->ClockPeriod / 2.0);
	if (PDimmPtr->UDimm & PDimmPtr->AddrMirror)
		PhyCfg[PHY_UDIMM] = 1U;
	if (PDimmPtr->En2tTimingMode) {
		PhyCfg[PHY_TRAS] = (u32)XFsbl_Ceil(((PDimmPtr->TRasPs / 1000.0) /
					PDimmPtr->ClockPeriod / 2.0)) * 2U;
	} else {
		PhyCfg[PHY_TRAS] = XFsbl_Round(((PDimmPtr->TRasPs / 1000.0) /
					PDimmPtr->ClockPeriod / 2.0)) * 2U;
	}
	PhyCfg[PHY_TRP] = (PDimmPtr->TRpPs / 1000.0) + 2U;
	PhyCfg[PHY_TFAW] = (u32)XFsbl_Ceil((PDimmPtr->TFawPs / 1000.0) / PDimmPtr->ClockPeriod);
	PhyCfg[PHY_TRFC] = (u32)XFsbl_Ceil((PDimmPtr->TRfcPs / 1000.0) / PDimmPtr->ClockPeriod);
	PhyCfg[PHY_TRC] = (u32)XFsbl_Ceil((PDimmPtr->TRcPs / 1000.0) / PDimmPtr->ClockPeriod) + 1U;
	PhyCfg[PHY_TWTR] = PDimmPtr->TWtr;
	PhyCfg[PHY_PUBWL] = PDimmPtr->WriteLatency;
	PhyCfg[PHY_PUBRL] = PDimmPtr->ReadLatency;
	PhyCfg[PHY_ERROUTODT] = PDimmPtr->Crc;
	PhyCfg[PHY_RDIMM] = PDimmPtr->RDimm;
	PhyCfg[PHY_DTDRS] = PDimmPtr->NumRankAddr;
	PhyCfg[PHY_RANKEN] = (2U * PDimmPtr->NumRankAddr) + 1U;
	Lp4DramSize = (PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) ? 32U : PDimmPtr->DramWidth;
	NumRank = (PDimmPtr->Zc1656 || PDimmPtr->HasEccComp) ? 0U : PDimmPtr->NumRankAddr;
	MemSize = ((PDimmPtr->BusWidth / Lp4DramSize) * PDimmPtr->Capacity * (1U << NumRank)) / 8U;
	PhyCfg[PHY_SEED] = (0x12340000U) | MemSize;
	PhyCfg[PHY_DVMIN] = (PDimmPtr->Lp4NoOdt) ? 0x27U : 0U;
	PhyCfg[PHY_PGWAIT_FRQA] = (u32)(40U / (PDimmPtr->ClockPeriod) / 2U);
	if (PDimmPtr->HostDrv == 34U) {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xDU;
	} else if (PDimmPtr->HostDrv == 40U) {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xBU;
	} else if (PDimmPtr->HostDrv == 48U) {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x9U;
	} else if (PDimmPtr->HostDrv == 60U) {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x7U;
	} else if (PDimmPtr->HostDrv == 80U) {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x5U;
	} else if (PDimmPtr->HostDrv == 120U) {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0x3U;
	} else {
		PhyCfg[PHY_ZPROG_ASYM_DRV_PD] = 0xBU;
	}
	PhyCfg[PHY_ZPROG_ASYM_DRV_PU] = PhyCfg[PHY_ZPROG_ASYM_DRV_PD];
	return XFSBL_SUCCESS;
}
static u32 XFsbl_PhyCalcCommonRegVal ( XFsbl_DimmParams * PDimmPtr , u32 * PhyCfg ) { u32 MemSize = 0U ; u32 Lp4DramSize = 0U ; u32 NumRank = 0U ; PhyCfg [ PHY_ADCP ] = PDimmPtr -> AddrMirror ; if ( ! PDimmPtr -> PhyClkGate ) { PhyCfg [ PHY_GATEACRDCLK ] = 0x2U ; PhyCfg [ PHY_GATEACDDRCLK ] = 0x2U ; PhyCfg [ PHY_GATEACCTLCLK ] = 0x2U ; } if ( PDimmPtr -> FreqB ) { PhyCfg [ PHY_DDLPGACT ] = 1U ; PhyCfg [ PHY_DDLPGRW ] = 1U ; } PhyCfg [ PHY_TPLLPD ] = ( u32 ) XFsbl_Ceil ( 1000U / ( PDimmPtr -> ClockPeriod * 2U ) ) ; PhyCfg [ PHY_TPLLGS ] = ( u32 ) XFsbl_Ceil ( 4000.0 / ( PDimmPtr -> ClockPeriod * 2U ) ) ; PhyCfg [ PHY_TPLLLOCK ] = ( u32 ) XFsbl_Ceil ( 100000.0 / ( PDimmPtr -> ClockPeriod * 2U ) ) ; PhyCfg [ PHY_TPLLRST ] = ( u32 ) XFsbl_Ceil ( 9000.0 / ( PDimmPtr -> ClockPeriod * 2U ) ) ; PhyCfg [ PHY_PLLBYP ] = PDimmPtr -> PllByp ; if ( PDimmPtr -> CtlClkFreq > 668U ) { PhyCfg [ PHY_FRQSEL ] = 8U ; PhyCfg [ PHY_CPPC ] = 5U ; PhyCfg [ PHY_CPIC ] = 0U ; } else if ( PDimmPtr -> CtlClkFreq > 560U ) { PhyCfg [ PHY_FRQSEL ] = 0U ; PhyCfg [ PHY_CPPC ] = 7U ; PhyCfg [ PHY_CPIC ] = 0U ; } else if ( PDimmPtr -> CtlClkFreq > 471U ) { PhyCfg [ PHY_FRQSEL ] = 1U ; PhyCfg [ PHY_CPPC ] = 8U ; PhyCfg [ PHY_CPIC ] = 0U ; } else if ( PDimmPtr -> CtlClkFreq > 396U ) { PhyCfg [ PHY_FRQSEL ] = 2U ; PhyCfg [ PHY_CPPC ] = 9U ; PhyCfg [ PHY_CPIC ] = 0U ; } else if ( PDimmPtr -> CtlClkFreq > 332U ) { PhyCfg [ PHY_FRQSEL ] = 3U ; PhyCfg [ PHY_CPPC ] = 10U ; PhyCfg [ PHY_CPIC ] = 0U ; } else if ( PDimmPtr -> CtlClkFreq > 279U ) { PhyCfg [ PHY_FRQSEL ] = 4U ; PhyCfg [ PHY_CPPC ] = 6U ; PhyCfg [ PHY_CPIC ] = 1U ; } else if ( PDimmPtr -> CtlClkFreq > 235U ) { PhyCfg [ PHY_FRQSEL ] = 5U ; PhyCfg [ PHY_CPPC ] = 8U ; } else if ( PDimmPtr -> CtlClkFreq > 197U ) { PhyCfg [ PHY_FRQSEL ] = 6U ; PhyCfg [ PHY_CPPC ] = 9U ; PhyCfg [ PHY_CPIC ] = 2U ; } else if ( PDimmPtr -> CtlClkFreq >= 166U ) { PhyCfg [ PHY_FRQSEL ] = 7U ; PhyCfg [ PHY_CPPC ] = 10U ; PhyCfg [ PHY_CPIC ] = 3U ; } PhyCfg [ PHY_PUAD ] = ( u32 ) ( 10U / PDimmPtr -> ClockPeriod / 2.0 ) ; if ( PDimmPtr -> UDimm & PDimmPtr -> AddrMirror ) PhyCfg [ PHY_UDIMM ] = 1U ; if ( PDimmPtr -> En2tTimingMode ) { PhyCfg [ PHY_TRAS ] = ( u32 ) XFsbl_Ceil ( ( ( PDimmPtr -> TRasPs / 1000.0 ) / PDimmPtr -> ClockPeriod / 2.0 ) ) * 2U ; } else { PhyCfg [ PHY_TRAS ] = XFsbl_Round ( ( ( PDimmPtr -> TRasPs / 1000.0 ) / PDimmPtr -> ClockPeriod / 2.0 ) ) * 2U ; } PhyCfg [ PHY_TRP ] = ( PDimmPtr -> TRpPs / 1000.0 ) + 2U ; PhyCfg [ PHY_TFAW ] = ( u32 ) XFsbl_Ceil ( ( PDimmPtr -> TFawPs / 1000.0 ) / PDimmPtr -> ClockPeriod ) ; PhyCfg [ PHY_TRFC ] = ( u32 ) XFsbl_Ceil ( ( PDimmPtr -> TRfcPs / 1000.0 ) / PDimmPtr -> ClockPeriod ) ; PhyCfg [ PHY_TRC ] = ( u32 ) XFsbl_Ceil ( ( PDimmPtr -> TRcPs / 1000.0 ) / PDimmPtr -> ClockPeriod ) + 1U ; PhyCfg [ PHY_TWTR ] = PDimmPtr -> TWtr ; PhyCfg [ PHY_PUBWL ] = PDimmPtr -> WriteLatency ; PhyCfg [ PHY_PUBRL ] = PDimmPtr -> ReadLatency ; PhyCfg [ PHY_ERROUTODT ] = PDimmPtr -> Crc ; PhyCfg [ PHY_RDIMM ] = PDimmPtr -> RDimm ; PhyCfg [ PHY_DTDRS ] = PDimmPtr -> NumRankAddr ; PhyCfg [ PHY_RANKEN ] = ( 2U * PDimmPtr -> NumRankAddr ) + 1U ; Lp4DramSize = ( PDimmPtr -> MemType == SPD_MEMTYPE_LPDDR4 ) ? 32U : PDimmPtr -> DramWidth ; NumRank = ( PDimmPtr -> Zc1656 || PDimmPtr -> HasEccComp ) ? 0U : PDimmPtr -> NumRankAddr ; MemSize = ( ( PDimmPtr -> BusWidth / Lp4DramSize ) * PDimmPtr -> Capacity * ( 1U << NumRank ) ) / 8U ; PhyCfg [ PHY_SEED ] = ( 0x12340000U ) | MemSize ; PhyCfg [ PHY_DVMIN ] = ( PDimmPtr -> Lp4NoOdt ) ? 0x27U : 0U ; PhyCfg [ PHY_PGWAIT_FRQA ] = ( u32 ) ( 40U / ( PDimmPtr -> ClockPeriod ) / 2U ) ; if ( PDimmPtr -> HostDrv == 34U ) { PhyCfg [ PHY_ZPROG_ASYM_DRV_PD ] = 0xDU ; } else if ( PDimmPtr -> HostDrv == 40U ) { PhyCfg [ PHY_ZPROG_ASYM_DRV_PD ] = 0xBU ; } else if ( PDimmPtr -> HostDrv == 48U ) { PhyCfg [ PHY_ZPROG_ASYM_DRV_PD ] = 0x9U ; } else if ( PDimmPtr -> HostDrv == 60U ) { PhyCfg [ PHY_ZPROG_ASYM_DRV_PD ] = 0x7U ; } else if ( PDimmPtr -> HostDrv == 80U ) { PhyCfg [ PHY_ZPROG_ASYM_DRV_PD ] = 0x5U ; } else if ( PDimmPtr -> HostDrv == 120U ) { PhyCfg [ PHY_ZPROG_ASYM_DRV_PD ] = 0x3U ; } else { PhyCfg [ PHY_ZPROG_ASYM_DRV_PD ] = 0xBU ; } PhyCfg [ PHY_ZPROG_ASYM_DRV_PU ] = PhyCfg [ PHY_ZPROG_ASYM_DRV_PD ] ; return XFSBL_SUCCESS ; }
This function calculates the PHY register values common to all DDR types
 @param       PDimmPtr is pointer to DIMM parameters Data Structure
 @param       PhyCfg is the array to store register field values
This function calculates the PHY register values common to all DDR types @param PDimmPtr is pointer to DIMM parameters Data Structure @param PhyCfg is the array to store register field values