XilinxProcessorIPLib/drivers/dp12rxss/src/xdprxss.c
u32 XDpRxSs_CfgInitialize(XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr,
				UINTPTR EffectiveAddr)
{
#if (XPAR_XHDCP_NUM_INSTANCES > 0)
	XHdcp1x_Config Hdcp1xConfig;
#endif
	XIic_Config IicConfig;
	XDp_Config DpConfig;
	u32 Status;

	/* Verify arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(CfgPtr != NULL);
	Xil_AssertNonvoid(EffectiveAddr != (u32)0x0);

	/* Setup the instance */
	(void)memset((void *)InstancePtr, 0, sizeof(XDpRxSs));
	(void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr,
			sizeof(XDpRxSs_Config));

	InstancePtr->Config.BaseAddress = EffectiveAddr;

	/* Get included sub-cores in the DisplayPort RX Subsystem */
	DpRxSs_GetIncludedSubCores(InstancePtr);

	/* Check for IIC availability */
	if (InstancePtr->IicPtr) {
		xdbg_printf((XDBG_DEBUG_GENERAL),"SS INFO: Initializing "
			"IIC IP\n\r");

		/* Calculate absolute base address of IIC sub-core */
		InstancePtr->Config.IicSubCore.IicConfig.BaseAddress +=
					InstancePtr->Config.BaseAddress;

		/* Copy IIC config into local IIC config */
		(void)memcpy((void *)&(IicConfig),
			(const void *)&CfgPtr->IicSubCore.IicConfig,
				sizeof(IicConfig));

		/* IIC config initialize */
		IicConfig.BaseAddress += InstancePtr->Config.BaseAddress;
		Status = XIic_CfgInitialize(InstancePtr->IicPtr, &IicConfig,
				IicConfig.BaseAddress);
		if ((Status != XST_SUCCESS) && (Status !=
						XST_DEVICE_IS_STARTED)) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: IIC "
				"initialization failed!\n\r");
			return XST_FAILURE;
		}

		/* Reset DP159 */
		XDpRxSs_Dp159Reset(InstancePtr->IicPtr, TRUE);

		/* IIC initialization for dynamic functionality */
		Status = XIic_DynamicInitialize(InstancePtr->IicPtr);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: IIC "
				"dynamic initialization failed!\n\r");
			return XST_FAILURE;
		}
	}

	/* Check for DisplayPort availability */
	if (InstancePtr->DpPtr) {
		xdbg_printf((XDBG_DEBUG_GENERAL),"SS INFO: Initializing "
			"DisplayPort Receiver IP\n\r");

		/* Assign number of streams to one when MST is not enabled */
		if (InstancePtr->Config.MstSupport) {
			InstancePtr->UsrOpt.NumOfStreams =
					InstancePtr->Config.NumMstStreams;
		}
		else {
			InstancePtr->Config.DpSubCore.DpConfig.NumMstStreams =
				1;
			InstancePtr->UsrOpt.NumOfStreams = 1;
			InstancePtr->Config.NumMstStreams = 1;
		}

		/* Calculate absolute base address of DP sub-core */
		InstancePtr->Config.DpSubCore.DpConfig.BaseAddr +=
					InstancePtr->Config.BaseAddress;

		/* Copy DP config into local DP config */
		(void)memcpy((void *)&(DpConfig),
			(const void *)&CfgPtr->DpSubCore.DpConfig,
				sizeof(XDp_Config));

		/* DisplayPort config initialize */
		DpConfig.BaseAddr += InstancePtr->Config.BaseAddress;
		XDp_CfgInitialize(InstancePtr->DpPtr, &DpConfig,
				DpConfig.BaseAddr);

		/* Set maximum link rate for the first time */
		XDp_RxSetLinkRate(InstancePtr->DpPtr,
				InstancePtr->DpPtr->Config.MaxLinkRate);

		/* Set maximum lane count for the first time */
		XDp_RxSetLaneCount(InstancePtr->DpPtr,
				InstancePtr->Config.MaxLaneCount);

		/* Bring DP159 out of reset */
		XDpRxSs_Dp159Reset(InstancePtr->IicPtr, FALSE);

		/* Wait for us */
		XDp_WaitUs(InstancePtr->DpPtr, 1000);

		/* Initialize DP159 */
		XDpRxSs_Dp159Initialize(InstancePtr->IicPtr);

		/* Wait for us */
		XDp_WaitUs(InstancePtr->DpPtr, 1000);

		/* Initialize default training pattern callbacks in DP RX
		 * Subsystem
		 */
		XDp_RxSetCallback(InstancePtr->DpPtr, XDP_RX_HANDLER_TP1,
				StubTp1Callback, (void *)InstancePtr);
		XDp_RxSetCallback(InstancePtr->DpPtr, XDP_RX_HANDLER_TP2,
				StubTp2Callback, (void *)InstancePtr);
		XDp_RxSetCallback(InstancePtr->DpPtr, XDP_RX_HANDLER_TP3,
				StubTp2Callback, (void *)InstancePtr);
		XDp_RxSetCallback(InstancePtr->DpPtr, XDP_RX_HANDLER_UNPLUG,
				StubUnplugCallback, (void *)InstancePtr);

		/* Initialize configurable parameters */
		InstancePtr->UsrOpt.Bpc = InstancePtr->Config.MaxBpc;
		InstancePtr->UsrOpt.LaneCount =
					InstancePtr->Config.MaxLaneCount;
		InstancePtr->UsrOpt.LinkRate =
					InstancePtr->DpPtr->Config.MaxLinkRate;
		InstancePtr->UsrOpt.MstSupport =
				InstancePtr->Config.MstSupport;

		/* Populate the RX core's ports with default values */
		DpRxSs_PopulateDpRxPorts(InstancePtr);
	}

#if (XPAR_XHDCP_NUM_INSTANCES > 0)
	/* Check for Timer Counter availability */
	XTmrCtr_Config *ConfigPtr;
	if (InstancePtr->TmrCtrPtr != NULL) {
		xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Initializing Timer "
			"Counter IP \n\r");

		ConfigPtr = XTmrCtr_LookupConfig(InstancePtr->Config.TmrCtrSubCore.TmrCtrConfig.DeviceId);
		if (!ConfigPtr) {
			return XST_DEVICE_NOT_FOUND;
		}

		/* Calculate absolute base address of Timer Counter sub-core */
		XTmrCtr_CfgInitialize(InstancePtr->TmrCtrPtr, ConfigPtr,
				ConfigPtr->BaseAddress +
				InstancePtr->Config.BaseAddress);
		Status = XTmrCtr_InitHw(InstancePtr->TmrCtrPtr);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: Timer "
				"Counter initialization failed\n\r");
			return XST_FAILURE;
		}

		/* Configure the callback */
		XTmrCtr_SetHandler(InstancePtr->TmrCtrPtr,
				(XTmrCtr_Handler)DpRxSs_TimeOutCallback,
					InstancePtr);

		/* Enable the specified options for Timer Counter zero */
		XTmrCtr_SetOptions(InstancePtr->TmrCtrPtr, 0,
			XTC_DOWN_COUNT_OPTION | XTC_INT_MODE_OPTION);

		/* Set the reset value to Timer Counter zero */
		XTmrCtr_SetResetValue(InstancePtr->TmrCtrPtr, 0,
					XDPRXSS_TMRCTR_RST_VAL);

		/* Initialize the HDCP timer functions */
		XHdcp1x_SetTimerStart(InstancePtr->Hdcp1xPtr,
						&DpRxSs_HdcpStartTimer);
		XHdcp1x_SetTimerStop(InstancePtr->Hdcp1xPtr,
						&DpRxSs_HdcpStopTimer);
		XHdcp1x_SetTimerDelay(InstancePtr->Hdcp1xPtr,
						&DpRxSs_HdcpBusyDelay);
	}

	/* Check for HDCP availability */
	if ((InstancePtr->Hdcp1xPtr != NULL) &&
					(InstancePtr->Config.HdcpEnable)) {
		xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Initializing HDCP IP "
				"\n\r");

		/* Calculate absolute base address of HDCP sub-core */
		InstancePtr->Config.Hdcp1xSubCore.Hdcp1xConfig.BaseAddress +=
					InstancePtr->Config.BaseAddress;
		(void)memcpy((void *)&(Hdcp1xConfig),
			(const void *)&CfgPtr->Hdcp1xSubCore.Hdcp1xConfig,
				sizeof(XHdcp1x_Config));

		/* HDCP config initialize */
		Hdcp1xConfig.BaseAddress += InstancePtr->Config.BaseAddress;
		Status = XHdcp1x_CfgInitialize(InstancePtr->Hdcp1xPtr,
				&Hdcp1xConfig, (void *)InstancePtr->DpPtr,
				Hdcp1xConfig.BaseAddress);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: HDCP "
				"initialization failed\n\r");
			return XST_FAILURE;
		}

		/* Set key selection value for RX */
		XHdcp1x_SetKeySelect(InstancePtr->Hdcp1xPtr, 0x1);

		XHdcp1x_LateInit(InstancePtr->Hdcp1xPtr);
	}
#endif

	/* Set the flag to indicate the subsystem is ready */
	InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);

	XDpRxSs_SetCallBack(InstancePtr, XDPRXSS_DRV_HANDLER_DP_NO_VID_EVENT,
				XDpRxSs_DrvNoVideoHandler, InstancePtr);
	XDpRxSs_SetCallBack(InstancePtr, XDPRXSS_DRV_HANDLER_DP_VID_EVENT,
				XDpRxSs_DrvVideoHandler, InstancePtr);
	XDpRxSs_SetCallBack(InstancePtr, XDPRXSS_DRV_HANDLER_DP_PWR_CHG_EVENT,
				XDpRxSs_DrvPowerChangeHandler, InstancePtr);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function initializes the DisplayPort Receiver Subsystem core. This
* function must be called prior to using the core. Initialization of the core
* includes setting up the instance data and ensuring the hardware is in a
* quiescent state.
*
* @param	InstancePtr is a pointer to the XDpRxSs core instance.
* @param	CfgPtr points to the configuration structure associated with
*		the DisplayPort RX Subsystem core.
* @param	EffectiveAddr is the base address of the device. If address
*		translation is being used, then this parameter must reflect the
*		virtual base address. Otherwise, the physical address should be
*		used.
*
* @return
*		- XST_DEVICE_NOT_FOUND if sub-core not found.
*		- XST_FAILURE if sub-core initialization failed.
*		- XST_SUCCESS if XDpRxSs_CfgInitialize successful.
*
* @note		None.
*
******************************************************************************/
This function initializes the DisplayPort Receiver Subsystem core. This
function must be called prior to using the core. Initialization of the core
includes setting up the instance data and ensuring the hardware is in a
quiescent state.
This function initializes the DisplayPort Receiver Subsystem core . This function must be called prior to using the core . Initialization of the core includes setting up the instance data and ensuring the hardware is in a quiescent state .
u32 XDpRxSs_CfgInitialize(XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr,
				UINTPTR EffectiveAddr)
{
#if (XPAR_XHDCP_NUM_INSTANCES > 0)
	XHdcp1x_Config Hdcp1xConfig;
#endif
	XIic_Config IicConfig;
	XDp_Config DpConfig;
	u32 Status;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(CfgPtr != NULL);
	Xil_AssertNonvoid(EffectiveAddr != (u32)0x0);
	(void)memset((void *)InstancePtr, 0, sizeof(XDpRxSs));
	(void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr,
			sizeof(XDpRxSs_Config));
	InstancePtr->Config.BaseAddress = EffectiveAddr;
	DpRxSs_GetIncludedSubCores(InstancePtr);
	if (InstancePtr->IicPtr) {
		xdbg_printf((XDBG_DEBUG_GENERAL),"SS INFO: Initializing "
			"IIC IP\n\r");
		InstancePtr->Config.IicSubCore.IicConfig.BaseAddress +=
					InstancePtr->Config.BaseAddress;
		(void)memcpy((void *)&(IicConfig),
			(const void *)&CfgPtr->IicSubCore.IicConfig,
				sizeof(IicConfig));
		IicConfig.BaseAddress += InstancePtr->Config.BaseAddress;
		Status = XIic_CfgInitialize(InstancePtr->IicPtr, &IicConfig,
				IicConfig.BaseAddress);
		if ((Status != XST_SUCCESS) && (Status !=
						XST_DEVICE_IS_STARTED)) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: IIC "
				"initialization failed!\n\r");
			return XST_FAILURE;
		}
		XDpRxSs_Dp159Reset(InstancePtr->IicPtr, TRUE);
		Status = XIic_DynamicInitialize(InstancePtr->IicPtr);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: IIC "
				"dynamic initialization failed!\n\r");
			return XST_FAILURE;
		}
	}
	if (InstancePtr->DpPtr) {
		xdbg_printf((XDBG_DEBUG_GENERAL),"SS INFO: Initializing "
			"DisplayPort Receiver IP\n\r");
		if (InstancePtr->Config.MstSupport) {
			InstancePtr->UsrOpt.NumOfStreams =
					InstancePtr->Config.NumMstStreams;
		}
		else {
			InstancePtr->Config.DpSubCore.DpConfig.NumMstStreams =
				1;
			InstancePtr->UsrOpt.NumOfStreams = 1;
			InstancePtr->Config.NumMstStreams = 1;
		}
		InstancePtr->Config.DpSubCore.DpConfig.BaseAddr +=
					InstancePtr->Config.BaseAddress;
		(void)memcpy((void *)&(DpConfig),
			(const void *)&CfgPtr->DpSubCore.DpConfig,
				sizeof(XDp_Config));
		DpConfig.BaseAddr += InstancePtr->Config.BaseAddress;
		XDp_CfgInitialize(InstancePtr->DpPtr, &DpConfig,
				DpConfig.BaseAddr);
		XDp_RxSetLinkRate(InstancePtr->DpPtr,
				InstancePtr->DpPtr->Config.MaxLinkRate);
		XDp_RxSetLaneCount(InstancePtr->DpPtr,
				InstancePtr->Config.MaxLaneCount);
		XDpRxSs_Dp159Reset(InstancePtr->IicPtr, FALSE);
		XDp_WaitUs(InstancePtr->DpPtr, 1000);
		XDpRxSs_Dp159Initialize(InstancePtr->IicPtr);
		XDp_WaitUs(InstancePtr->DpPtr, 1000);
		XDp_RxSetCallback(InstancePtr->DpPtr, XDP_RX_HANDLER_TP1,
				StubTp1Callback, (void *)InstancePtr);
		XDp_RxSetCallback(InstancePtr->DpPtr, XDP_RX_HANDLER_TP2,
				StubTp2Callback, (void *)InstancePtr);
		XDp_RxSetCallback(InstancePtr->DpPtr, XDP_RX_HANDLER_TP3,
				StubTp2Callback, (void *)InstancePtr);
		XDp_RxSetCallback(InstancePtr->DpPtr, XDP_RX_HANDLER_UNPLUG,
				StubUnplugCallback, (void *)InstancePtr);
		InstancePtr->UsrOpt.Bpc = InstancePtr->Config.MaxBpc;
		InstancePtr->UsrOpt.LaneCount =
					InstancePtr->Config.MaxLaneCount;
		InstancePtr->UsrOpt.LinkRate =
					InstancePtr->DpPtr->Config.MaxLinkRate;
		InstancePtr->UsrOpt.MstSupport =
				InstancePtr->Config.MstSupport;
		DpRxSs_PopulateDpRxPorts(InstancePtr);
	}
#if (XPAR_XHDCP_NUM_INSTANCES > 0)
	XTmrCtr_Config *ConfigPtr;
	if (InstancePtr->TmrCtrPtr != NULL) {
		xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Initializing Timer "
			"Counter IP \n\r");
		ConfigPtr = XTmrCtr_LookupConfig(InstancePtr->Config.TmrCtrSubCore.TmrCtrConfig.DeviceId);
		if (!ConfigPtr) {
			return XST_DEVICE_NOT_FOUND;
		}
		XTmrCtr_CfgInitialize(InstancePtr->TmrCtrPtr, ConfigPtr,
				ConfigPtr->BaseAddress +
				InstancePtr->Config.BaseAddress);
		Status = XTmrCtr_InitHw(InstancePtr->TmrCtrPtr);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: Timer "
				"Counter initialization failed\n\r");
			return XST_FAILURE;
		}
		XTmrCtr_SetHandler(InstancePtr->TmrCtrPtr,
				(XTmrCtr_Handler)DpRxSs_TimeOutCallback,
					InstancePtr);
		XTmrCtr_SetOptions(InstancePtr->TmrCtrPtr, 0,
			XTC_DOWN_COUNT_OPTION | XTC_INT_MODE_OPTION);
		XTmrCtr_SetResetValue(InstancePtr->TmrCtrPtr, 0,
					XDPRXSS_TMRCTR_RST_VAL);
		XHdcp1x_SetTimerStart(InstancePtr->Hdcp1xPtr,
						&DpRxSs_HdcpStartTimer);
		XHdcp1x_SetTimerStop(InstancePtr->Hdcp1xPtr,
						&DpRxSs_HdcpStopTimer);
		XHdcp1x_SetTimerDelay(InstancePtr->Hdcp1xPtr,
						&DpRxSs_HdcpBusyDelay);
	}
	if ((InstancePtr->Hdcp1xPtr != NULL) &&
					(InstancePtr->Config.HdcpEnable)) {
		xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Initializing HDCP IP "
				"\n\r");
		InstancePtr->Config.Hdcp1xSubCore.Hdcp1xConfig.BaseAddress +=
					InstancePtr->Config.BaseAddress;
		(void)memcpy((void *)&(Hdcp1xConfig),
			(const void *)&CfgPtr->Hdcp1xSubCore.Hdcp1xConfig,
				sizeof(XHdcp1x_Config));
		Hdcp1xConfig.BaseAddress += InstancePtr->Config.BaseAddress;
		Status = XHdcp1x_CfgInitialize(InstancePtr->Hdcp1xPtr,
				&Hdcp1xConfig, (void *)InstancePtr->DpPtr,
				Hdcp1xConfig.BaseAddress);
		if (Status != XST_SUCCESS) {
			xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: HDCP "
				"initialization failed\n\r");
			return XST_FAILURE;
		}
		XHdcp1x_SetKeySelect(InstancePtr->Hdcp1xPtr, 0x1);
		XHdcp1x_LateInit(InstancePtr->Hdcp1xPtr);
	}
#endif
	InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
	XDpRxSs_SetCallBack(InstancePtr, XDPRXSS_DRV_HANDLER_DP_NO_VID_EVENT,
				XDpRxSs_DrvNoVideoHandler, InstancePtr);
	XDpRxSs_SetCallBack(InstancePtr, XDPRXSS_DRV_HANDLER_DP_VID_EVENT,
				XDpRxSs_DrvVideoHandler, InstancePtr);
	XDpRxSs_SetCallBack(InstancePtr, XDPRXSS_DRV_HANDLER_DP_PWR_CHG_EVENT,
				XDpRxSs_DrvPowerChangeHandler, InstancePtr);
	return XST_SUCCESS;
}
u32 XDpRxSs_CfgInitialize ( XDpRxSs * InstancePtr , XDpRxSs_Config * CfgPtr , UINTPTR EffectiveAddr ) { #if ( XPAR_XHDCP_NUM_INSTANCES > 0 ) XHdcp1x_Config Hdcp1xConfig ; #endif XIic_Config IicConfig ; XDp_Config DpConfig ; u32 Status ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( CfgPtr != NULL ) ; Xil_AssertNonvoid ( EffectiveAddr != ( u32 ) 0x0 ) ; ( void ) memset ( ( void * ) InstancePtr , 0 , sizeof ( XDpRxSs ) ) ; ( void ) memcpy ( ( void * ) & ( InstancePtr -> Config ) , ( const void * ) CfgPtr , sizeof ( XDpRxSs_Config ) ) ; InstancePtr -> Config . BaseAddress = EffectiveAddr ; DpRxSs_GetIncludedSubCores ( InstancePtr ) ; if ( InstancePtr -> IicPtr ) { xdbg_printf ( ( XDBG_DEBUG_GENERAL ) , " " " \n \r " ) ; InstancePtr -> Config . IicSubCore . IicConfig . BaseAddress += InstancePtr -> Config . BaseAddress ; ( void ) memcpy ( ( void * ) & ( IicConfig ) , ( const void * ) & CfgPtr -> IicSubCore . IicConfig , sizeof ( IicConfig ) ) ; IicConfig . BaseAddress += InstancePtr -> Config . BaseAddress ; Status = XIic_CfgInitialize ( InstancePtr -> IicPtr , & IicConfig , IicConfig . BaseAddress ) ; if ( ( Status != XST_SUCCESS ) && ( Status != XST_DEVICE_IS_STARTED ) ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " " " \n \r " ) ; return XST_FAILURE ; } XDpRxSs_Dp159Reset ( InstancePtr -> IicPtr , TRUE ) ; Status = XIic_DynamicInitialize ( InstancePtr -> IicPtr ) ; if ( Status != XST_SUCCESS ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " " " \n \r " ) ; return XST_FAILURE ; } } if ( InstancePtr -> DpPtr ) { xdbg_printf ( ( XDBG_DEBUG_GENERAL ) , " " " \n \r " ) ; if ( InstancePtr -> Config . MstSupport ) { InstancePtr -> UsrOpt . NumOfStreams = InstancePtr -> Config . NumMstStreams ; } else { InstancePtr -> Config . DpSubCore . DpConfig . NumMstStreams = 1 ; InstancePtr -> UsrOpt . NumOfStreams = 1 ; InstancePtr -> Config . NumMstStreams = 1 ; } InstancePtr -> Config . DpSubCore . DpConfig . BaseAddr += InstancePtr -> Config . BaseAddress ; ( void ) memcpy ( ( void * ) & ( DpConfig ) , ( const void * ) & CfgPtr -> DpSubCore . DpConfig , sizeof ( XDp_Config ) ) ; DpConfig . BaseAddr += InstancePtr -> Config . BaseAddress ; XDp_CfgInitialize ( InstancePtr -> DpPtr , & DpConfig , DpConfig . BaseAddr ) ; XDp_RxSetLinkRate ( InstancePtr -> DpPtr , InstancePtr -> DpPtr -> Config . MaxLinkRate ) ; XDp_RxSetLaneCount ( InstancePtr -> DpPtr , InstancePtr -> Config . MaxLaneCount ) ; XDpRxSs_Dp159Reset ( InstancePtr -> IicPtr , FALSE ) ; XDp_WaitUs ( InstancePtr -> DpPtr , 1000 ) ; XDpRxSs_Dp159Initialize ( InstancePtr -> IicPtr ) ; XDp_WaitUs ( InstancePtr -> DpPtr , 1000 ) ; XDp_RxSetCallback ( InstancePtr -> DpPtr , XDP_RX_HANDLER_TP1 , StubTp1Callback , ( void * ) InstancePtr ) ; XDp_RxSetCallback ( InstancePtr -> DpPtr , XDP_RX_HANDLER_TP2 , StubTp2Callback , ( void * ) InstancePtr ) ; XDp_RxSetCallback ( InstancePtr -> DpPtr , XDP_RX_HANDLER_TP3 , StubTp2Callback , ( void * ) InstancePtr ) ; XDp_RxSetCallback ( InstancePtr -> DpPtr , XDP_RX_HANDLER_UNPLUG , StubUnplugCallback , ( void * ) InstancePtr ) ; InstancePtr -> UsrOpt . Bpc = InstancePtr -> Config . MaxBpc ; InstancePtr -> UsrOpt . LaneCount = InstancePtr -> Config . MaxLaneCount ; InstancePtr -> UsrOpt . LinkRate = InstancePtr -> DpPtr -> Config . MaxLinkRate ; InstancePtr -> UsrOpt . MstSupport = InstancePtr -> Config . MstSupport ; DpRxSs_PopulateDpRxPorts ( InstancePtr ) ; } #if ( XPAR_XHDCP_NUM_INSTANCES > 0 ) XTmrCtr_Config * ConfigPtr ; if ( InstancePtr -> TmrCtrPtr != NULL ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " " " \n \r " ) ; ConfigPtr = XTmrCtr_LookupConfig ( InstancePtr -> Config . TmrCtrSubCore . TmrCtrConfig . DeviceId ) ; if ( ! ConfigPtr ) { return XST_DEVICE_NOT_FOUND ; } XTmrCtr_CfgInitialize ( InstancePtr -> TmrCtrPtr , ConfigPtr , ConfigPtr -> BaseAddress + InstancePtr -> Config . BaseAddress ) ; Status = XTmrCtr_InitHw ( InstancePtr -> TmrCtrPtr ) ; if ( Status != XST_SUCCESS ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " " " \n \r " ) ; return XST_FAILURE ; } XTmrCtr_SetHandler ( InstancePtr -> TmrCtrPtr , ( XTmrCtr_Handler ) DpRxSs_TimeOutCallback , InstancePtr ) ; XTmrCtr_SetOptions ( InstancePtr -> TmrCtrPtr , 0 , XTC_DOWN_COUNT_OPTION | XTC_INT_MODE_OPTION ) ; XTmrCtr_SetResetValue ( InstancePtr -> TmrCtrPtr , 0 , XDPRXSS_TMRCTR_RST_VAL ) ; XHdcp1x_SetTimerStart ( InstancePtr -> Hdcp1xPtr , & DpRxSs_HdcpStartTimer ) ; XHdcp1x_SetTimerStop ( InstancePtr -> Hdcp1xPtr , & DpRxSs_HdcpStopTimer ) ; XHdcp1x_SetTimerDelay ( InstancePtr -> Hdcp1xPtr , & DpRxSs_HdcpBusyDelay ) ; } if ( ( InstancePtr -> Hdcp1xPtr != NULL ) && ( InstancePtr -> Config . HdcpEnable ) ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " " " \n \r " ) ; InstancePtr -> Config . Hdcp1xSubCore . Hdcp1xConfig . BaseAddress += InstancePtr -> Config . BaseAddress ; ( void ) memcpy ( ( void * ) & ( Hdcp1xConfig ) , ( const void * ) & CfgPtr -> Hdcp1xSubCore . Hdcp1xConfig , sizeof ( XHdcp1x_Config ) ) ; Hdcp1xConfig . BaseAddress += InstancePtr -> Config . BaseAddress ; Status = XHdcp1x_CfgInitialize ( InstancePtr -> Hdcp1xPtr , & Hdcp1xConfig , ( void * ) InstancePtr -> DpPtr , Hdcp1xConfig . BaseAddress ) ; if ( Status != XST_SUCCESS ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " " " \n \r " ) ; return XST_FAILURE ; } XHdcp1x_SetKeySelect ( InstancePtr -> Hdcp1xPtr , 0x1 ) ; XHdcp1x_LateInit ( InstancePtr -> Hdcp1xPtr ) ; } #endif InstancePtr -> IsReady = ( u32 ) ( XIL_COMPONENT_IS_READY ) ; XDpRxSs_SetCallBack ( InstancePtr , XDPRXSS_DRV_HANDLER_DP_NO_VID_EVENT , XDpRxSs_DrvNoVideoHandler , InstancePtr ) ; XDpRxSs_SetCallBack ( InstancePtr , XDPRXSS_DRV_HANDLER_DP_VID_EVENT , XDpRxSs_DrvVideoHandler , InstancePtr ) ; XDpRxSs_SetCallBack ( InstancePtr , XDPRXSS_DRV_HANDLER_DP_PWR_CHG_EVENT , XDpRxSs_DrvPowerChangeHandler , InstancePtr ) ; return XST_SUCCESS ; }
This function initializes the DisplayPort Receiver Subsystem core.
This function initializes the DisplayPort Receiver Subsystem core .
/* Verify arguments. */ /* Setup the instance */ /* Get included sub-cores in the DisplayPort RX Subsystem */ /* Check for IIC availability */ /* Calculate absolute base address of IIC sub-core */ /* Copy IIC config into local IIC config */ /* IIC config initialize */ /* Reset DP159 */ /* IIC initialization for dynamic functionality */ /* Check for DisplayPort availability */ /* Assign number of streams to one when MST is not enabled */ /* Calculate absolute base address of DP sub-core */ /* Copy DP config into local DP config */ /* DisplayPort config initialize */ /* Set maximum link rate for the first time */ /* Set maximum lane count for the first time */ /* Bring DP159 out of reset */ /* Wait for us */ /* Initialize DP159 */ /* Wait for us */ /* Initialize default training pattern callbacks in DP RX
		 * Subsystem
		 */ /* Initialize configurable parameters */ /* Populate the RX core's ports with default values */ /* Check for Timer Counter availability */ /* Calculate absolute base address of Timer Counter sub-core */ /* Configure the callback */ /* Enable the specified options for Timer Counter zero */ /* Set the reset value to Timer Counter zero */ /* Initialize the HDCP timer functions */ /* Check for HDCP availability */ /* Calculate absolute base address of HDCP sub-core */ /* HDCP config initialize */ /* Set key selection value for RX */ /* Set the flag to indicate the subsystem is ready */