src/dpdk/drivers/net/qede/qede_debug.c
static enum dbg_status qed_grc_dump(struct ecore_hwfn *p_hwfn,
				    struct ecore_ptt *p_ptt,
				    u32 *dump_buf,
				    bool dump, u32 *num_dumped_dwords)
{
	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	u32 dwords_read, offset = 0;
	bool parities_masked = false;
	u8 i;

	*num_dumped_dwords = 0;
	dev_data->num_regs_read = 0;

	/* Update reset state */
	if (dump)
		qed_update_blocks_reset_state(p_hwfn, p_ptt);

	/* Dump global params */
	offset += qed_dump_common_global_params(p_hwfn,
						p_ptt,
						dump_buf + offset, dump, 4);
	offset += qed_dump_str_param(dump_buf + offset,
				     dump, "dump-type", "grc-dump");
	offset += qed_dump_num_param(dump_buf + offset,
				     dump,
				     "num-lcids",
				     NUM_OF_LCIDS);
	offset += qed_dump_num_param(dump_buf + offset,
				     dump,
				     "num-ltids",
				     NUM_OF_LTIDS);
	offset += qed_dump_num_param(dump_buf + offset,
				     dump, "num-ports", dev_data->num_ports);

	/* Dump reset registers (dumped before taking blocks out of reset ) */
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS))
		offset += qed_grc_dump_reset_regs(p_hwfn,
						  p_ptt,
						  dump_buf + offset, dump);

	/* Take all blocks out of reset (using reset registers) */
	if (dump) {
		qed_grc_unreset_blocks(p_hwfn, p_ptt, false);
		qed_update_blocks_reset_state(p_hwfn, p_ptt);
	}

	/* Disable all parities using MFW command */
	if (dump &&
	    !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP)) {
		parities_masked = !ecore_mcp_mask_parities(p_hwfn, p_ptt, 1);
		if (!parities_masked) {
			DP_NOTICE(p_hwfn, false,
				  "Failed to mask parities using MFW\n");
			if (qed_grc_get_param
			    (p_hwfn, DBG_GRC_PARAM_PARITY_SAFE))
				return DBG_STATUS_MCP_COULD_NOT_MASK_PRTY;
		}
	}

	/* Dump modified registers (dumped before modifying them) */
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS))
		offset += qed_grc_dump_modified_regs(p_hwfn,
						     p_ptt,
						     dump_buf + offset, dump);

	/* Stall storms */
	if (dump &&
	    (qed_grc_is_included(p_hwfn,
				 DBG_GRC_PARAM_DUMP_IOR) ||
	     qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC)))
		qed_grc_stall_storms(p_hwfn, p_ptt, true);

	/* Dump all regs  */
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) {
		bool block_enable[MAX_BLOCK_ID];

		/* Dump all blocks except MCP */
		for (i = 0; i < MAX_BLOCK_ID; i++)
			block_enable[i] = true;
		block_enable[BLOCK_MCP] = false;
		offset += qed_grc_dump_registers(p_hwfn,
						 p_ptt,
						 dump_buf +
						 offset,
						 dump,
						 block_enable, NULL);

		/* Dump special registers */
		offset += qed_grc_dump_special_regs(p_hwfn,
						    p_ptt,
						    dump_buf + offset, dump);
	}

	/* Dump memories */
	offset += qed_grc_dump_memories(p_hwfn, p_ptt, dump_buf + offset, dump);

	/* Dump MCP */
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MCP))
		offset += qed_grc_dump_mcp(p_hwfn,
					   p_ptt, dump_buf + offset, dump);

	/* Dump context */
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX))
		offset += qed_grc_dump_ctx(p_hwfn,
					   p_ptt, dump_buf + offset, dump);

	/* Dump RSS memories */
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_RSS))
		offset += qed_grc_dump_rss(p_hwfn,
					   p_ptt, dump_buf + offset, dump);

	/* Dump Big RAM */
	for (i = 0; i < NUM_BIG_RAM_TYPES; i++)
		if (qed_grc_is_included(p_hwfn, s_big_ram_defs[i].grc_param))
			offset += qed_grc_dump_big_ram(p_hwfn,
						       p_ptt,
						       dump_buf + offset,
						       dump, i);

	/* Dump VFC */
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC)) {
		dwords_read = qed_grc_dump_vfc(p_hwfn,
					       p_ptt, dump_buf + offset, dump);
		offset += dwords_read;
		if (!dwords_read)
			return DBG_STATUS_VFC_READ_ERROR;
	}

	/* Dump PHY tbus */
	if (qed_grc_is_included(p_hwfn,
				DBG_GRC_PARAM_DUMP_PHY) && dev_data->chip_id ==
	    CHIP_K2 && dev_data->hw_type == HW_TYPE_ASIC)
		offset += qed_grc_dump_phy(p_hwfn,
					   p_ptt, dump_buf + offset, dump);

	/* Dump MCP HW Dump */
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MCP_HW_DUMP) &&
	    !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP) && 1)
		offset += qed_grc_dump_mcp_hw_dump(p_hwfn,
						   p_ptt,
						   dump_buf + offset, dump);

	/* Dump static debug data (only if not during debug bus recording) */
	if (qed_grc_is_included(p_hwfn,
				DBG_GRC_PARAM_DUMP_STATIC) &&
	    (!dump || dev_data->bus.state == DBG_BUS_STATE_IDLE))
		offset += qed_grc_dump_static_debug(p_hwfn,
						    p_ptt,
						    dump_buf + offset, dump);

	/* Dump last section */
	offset += qed_dump_last_section(dump_buf, offset, dump);

	if (dump) {
		/* Unstall storms */
		if (qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_UNSTALL))
			qed_grc_stall_storms(p_hwfn, p_ptt, false);

		/* Clear parity status */
		qed_grc_clear_all_prty(p_hwfn, p_ptt);

		/* Enable all parities using MFW command */
		if (parities_masked)
			ecore_mcp_mask_parities(p_hwfn, p_ptt, 0);
	}

	*num_dumped_dwords = offset;

	return DBG_STATUS_OK;
}
/* Performs GRC Dump to the specified buffer.
 * Returns the dumped size in dwords.
 */
Performs GRC Dump to the specified buffer.
Returns the dumped size in dwords.
Performs GRC Dump to the specified buffer . Returns the dumped size in dwords .
static enum dbg_status qed_grc_dump(struct ecore_hwfn *p_hwfn,
				    struct ecore_ptt *p_ptt,
				    u32 *dump_buf,
				    bool dump, u32 *num_dumped_dwords)
{
	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	u32 dwords_read, offset = 0;
	bool parities_masked = false;
	u8 i;
	*num_dumped_dwords = 0;
	dev_data->num_regs_read = 0;
	if (dump)
		qed_update_blocks_reset_state(p_hwfn, p_ptt);
	offset += qed_dump_common_global_params(p_hwfn,
						p_ptt,
						dump_buf + offset, dump, 4);
	offset += qed_dump_str_param(dump_buf + offset,
				     dump, "dump-type", "grc-dump");
	offset += qed_dump_num_param(dump_buf + offset,
				     dump,
				     "num-lcids",
				     NUM_OF_LCIDS);
	offset += qed_dump_num_param(dump_buf + offset,
				     dump,
				     "num-ltids",
				     NUM_OF_LTIDS);
	offset += qed_dump_num_param(dump_buf + offset,
				     dump, "num-ports", dev_data->num_ports);
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS))
		offset += qed_grc_dump_reset_regs(p_hwfn,
						  p_ptt,
						  dump_buf + offset, dump);
	if (dump) {
		qed_grc_unreset_blocks(p_hwfn, p_ptt, false);
		qed_update_blocks_reset_state(p_hwfn, p_ptt);
	}
	if (dump &&
	    !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP)) {
		parities_masked = !ecore_mcp_mask_parities(p_hwfn, p_ptt, 1);
		if (!parities_masked) {
			DP_NOTICE(p_hwfn, false,
				  "Failed to mask parities using MFW\n");
			if (qed_grc_get_param
			    (p_hwfn, DBG_GRC_PARAM_PARITY_SAFE))
				return DBG_STATUS_MCP_COULD_NOT_MASK_PRTY;
		}
	}
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS))
		offset += qed_grc_dump_modified_regs(p_hwfn,
						     p_ptt,
						     dump_buf + offset, dump);
	if (dump &&
	    (qed_grc_is_included(p_hwfn,
				 DBG_GRC_PARAM_DUMP_IOR) ||
	     qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC)))
		qed_grc_stall_storms(p_hwfn, p_ptt, true);
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) {
		bool block_enable[MAX_BLOCK_ID];
		for (i = 0; i < MAX_BLOCK_ID; i++)
			block_enable[i] = true;
		block_enable[BLOCK_MCP] = false;
		offset += qed_grc_dump_registers(p_hwfn,
						 p_ptt,
						 dump_buf +
						 offset,
						 dump,
						 block_enable, NULL);
		offset += qed_grc_dump_special_regs(p_hwfn,
						    p_ptt,
						    dump_buf + offset, dump);
	}
	offset += qed_grc_dump_memories(p_hwfn, p_ptt, dump_buf + offset, dump);
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MCP))
		offset += qed_grc_dump_mcp(p_hwfn,
					   p_ptt, dump_buf + offset, dump);
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX))
		offset += qed_grc_dump_ctx(p_hwfn,
					   p_ptt, dump_buf + offset, dump);
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_RSS))
		offset += qed_grc_dump_rss(p_hwfn,
					   p_ptt, dump_buf + offset, dump);
	for (i = 0; i < NUM_BIG_RAM_TYPES; i++)
		if (qed_grc_is_included(p_hwfn, s_big_ram_defs[i].grc_param))
			offset += qed_grc_dump_big_ram(p_hwfn,
						       p_ptt,
						       dump_buf + offset,
						       dump, i);
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC)) {
		dwords_read = qed_grc_dump_vfc(p_hwfn,
					       p_ptt, dump_buf + offset, dump);
		offset += dwords_read;
		if (!dwords_read)
			return DBG_STATUS_VFC_READ_ERROR;
	}
	if (qed_grc_is_included(p_hwfn,
				DBG_GRC_PARAM_DUMP_PHY) && dev_data->chip_id ==
	    CHIP_K2 && dev_data->hw_type == HW_TYPE_ASIC)
		offset += qed_grc_dump_phy(p_hwfn,
					   p_ptt, dump_buf + offset, dump);
	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MCP_HW_DUMP) &&
	    !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP) && 1)
		offset += qed_grc_dump_mcp_hw_dump(p_hwfn,
						   p_ptt,
						   dump_buf + offset, dump);
	if (qed_grc_is_included(p_hwfn,
				DBG_GRC_PARAM_DUMP_STATIC) &&
	    (!dump || dev_data->bus.state == DBG_BUS_STATE_IDLE))
		offset += qed_grc_dump_static_debug(p_hwfn,
						    p_ptt,
						    dump_buf + offset, dump);
	offset += qed_dump_last_section(dump_buf, offset, dump);
	if (dump) {
		if (qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_UNSTALL))
			qed_grc_stall_storms(p_hwfn, p_ptt, false);
		qed_grc_clear_all_prty(p_hwfn, p_ptt);
		if (parities_masked)
			ecore_mcp_mask_parities(p_hwfn, p_ptt, 0);
	}
	*num_dumped_dwords = offset;
	return DBG_STATUS_OK;
}
static enum dbg_status qed_grc_dump ( struct ecore_hwfn * p_hwfn , struct ecore_ptt * p_ptt , u32 * dump_buf , bool dump , u32 * num_dumped_dwords ) { struct dbg_tools_data * dev_data = & p_hwfn -> dbg_info ; u32 dwords_read , offset = 0 ; bool parities_masked = false ; u8 i ; * num_dumped_dwords = 0 ; dev_data -> num_regs_read = 0 ; if ( dump ) qed_update_blocks_reset_state ( p_hwfn , p_ptt ) ; offset += qed_dump_common_global_params ( p_hwfn , p_ptt , dump_buf + offset , dump , 4 ) ; offset += qed_dump_str_param ( dump_buf + offset , dump , " " , " " ) ; offset += qed_dump_num_param ( dump_buf + offset , dump , " " , NUM_OF_LCIDS ) ; offset += qed_dump_num_param ( dump_buf + offset , dump , " " , NUM_OF_LTIDS ) ; offset += qed_dump_num_param ( dump_buf + offset , dump , " " , dev_data -> num_ports ) ; if ( qed_grc_is_included ( p_hwfn , DBG_GRC_PARAM_DUMP_REGS ) ) offset += qed_grc_dump_reset_regs ( p_hwfn , p_ptt , dump_buf + offset , dump ) ; if ( dump ) { qed_grc_unreset_blocks ( p_hwfn , p_ptt , false ) ; qed_update_blocks_reset_state ( p_hwfn , p_ptt ) ; } if ( dump && ! qed_grc_get_param ( p_hwfn , DBG_GRC_PARAM_NO_MCP ) ) { parities_masked = ! ecore_mcp_mask_parities ( p_hwfn , p_ptt , 1 ) ; if ( ! parities_masked ) { DP_NOTICE ( p_hwfn , false , " \n " ) ; if ( qed_grc_get_param ( p_hwfn , DBG_GRC_PARAM_PARITY_SAFE ) ) return DBG_STATUS_MCP_COULD_NOT_MASK_PRTY ; } } if ( qed_grc_is_included ( p_hwfn , DBG_GRC_PARAM_DUMP_REGS ) ) offset += qed_grc_dump_modified_regs ( p_hwfn , p_ptt , dump_buf + offset , dump ) ; if ( dump && ( qed_grc_is_included ( p_hwfn , DBG_GRC_PARAM_DUMP_IOR ) || qed_grc_is_included ( p_hwfn , DBG_GRC_PARAM_DUMP_VFC ) ) ) qed_grc_stall_storms ( p_hwfn , p_ptt , true ) ; if ( qed_grc_is_included ( p_hwfn , DBG_GRC_PARAM_DUMP_REGS ) ) { bool block_enable [ MAX_BLOCK_ID ] ; for ( i = 0 ; i < MAX_BLOCK_ID ; i ++ ) block_enable [ i ] = true ; block_enable [ BLOCK_MCP ] = false ; offset += qed_grc_dump_registers ( p_hwfn , p_ptt , dump_buf + offset , dump , block_enable , NULL ) ; offset += qed_grc_dump_special_regs ( p_hwfn , p_ptt , dump_buf + offset , dump ) ; } offset += qed_grc_dump_memories ( p_hwfn , p_ptt , dump_buf + offset , dump ) ; if ( qed_grc_is_included ( p_hwfn , DBG_GRC_PARAM_DUMP_MCP ) ) offset += qed_grc_dump_mcp ( p_hwfn , p_ptt , dump_buf + offset , dump ) ; if ( qed_grc_is_included ( p_hwfn , DBG_GRC_PARAM_DUMP_CM_CTX ) ) offset += qed_grc_dump_ctx ( p_hwfn , p_ptt , dump_buf + offset , dump ) ; if ( qed_grc_is_included ( p_hwfn , DBG_GRC_PARAM_DUMP_RSS ) ) offset += qed_grc_dump_rss ( p_hwfn , p_ptt , dump_buf + offset , dump ) ; for ( i = 0 ; i < NUM_BIG_RAM_TYPES ; i ++ ) if ( qed_grc_is_included ( p_hwfn , s_big_ram_defs [ i ] . grc_param ) ) offset += qed_grc_dump_big_ram ( p_hwfn , p_ptt , dump_buf + offset , dump , i ) ; if ( qed_grc_is_included ( p_hwfn , DBG_GRC_PARAM_DUMP_VFC ) ) { dwords_read = qed_grc_dump_vfc ( p_hwfn , p_ptt , dump_buf + offset , dump ) ; offset += dwords_read ; if ( ! dwords_read ) return DBG_STATUS_VFC_READ_ERROR ; } if ( qed_grc_is_included ( p_hwfn , DBG_GRC_PARAM_DUMP_PHY ) && dev_data -> chip_id == CHIP_K2 && dev_data -> hw_type == HW_TYPE_ASIC ) offset += qed_grc_dump_phy ( p_hwfn , p_ptt , dump_buf + offset , dump ) ; if ( qed_grc_is_included ( p_hwfn , DBG_GRC_PARAM_DUMP_MCP_HW_DUMP ) && ! qed_grc_get_param ( p_hwfn , DBG_GRC_PARAM_NO_MCP ) && 1 ) offset += qed_grc_dump_mcp_hw_dump ( p_hwfn , p_ptt , dump_buf + offset , dump ) ; if ( qed_grc_is_included ( p_hwfn , DBG_GRC_PARAM_DUMP_STATIC ) && ( ! dump || dev_data -> bus . state == DBG_BUS_STATE_IDLE ) ) offset += qed_grc_dump_static_debug ( p_hwfn , p_ptt , dump_buf + offset , dump ) ; offset += qed_dump_last_section ( dump_buf , offset , dump ) ; if ( dump ) { if ( qed_grc_get_param ( p_hwfn , DBG_GRC_PARAM_UNSTALL ) ) qed_grc_stall_storms ( p_hwfn , p_ptt , false ) ; qed_grc_clear_all_prty ( p_hwfn , p_ptt ) ; if ( parities_masked ) ecore_mcp_mask_parities ( p_hwfn , p_ptt , 0 ) ; } * num_dumped_dwords = offset ; return DBG_STATUS_OK ; }
Performs GRC Dump to the specified buffer.
Performs GRC Dump to the specified buffer .
/* Update reset state */ /* Dump global params */ /* Dump reset registers (dumped before taking blocks out of reset ) */ /* Take all blocks out of reset (using reset registers) */ /* Disable all parities using MFW command */ /* Dump modified registers (dumped before modifying them) */ /* Stall storms */ /* Dump all regs  */ /* Dump all blocks except MCP */ /* Dump special registers */ /* Dump memories */ /* Dump MCP */ /* Dump context */ /* Dump RSS memories */ /* Dump Big RAM */ /* Dump VFC */ /* Dump PHY tbus */ /* Dump MCP HW Dump */ /* Dump static debug data (only if not during debug bus recording) */ /* Dump last section */ /* Unstall storms */ /* Clear parity status */ /* Enable all parities using MFW command */