XilinxProcessorIPLib/drivers/aiengine/src/tile/xaietile_noc.c
void XAieTile_NoCIntcL2Enable(XAieGbl_Tile *TileInstPtr, u16 InterruptBitMask)
{
	XAie_AssertNonvoid(TileInstPtr != XAIE_NULL);
	XAie_AssertNonvoid(TileInstPtr->TileType == XAIEGBL_TILE_TYPE_SHIMNOC);

	XAieGbl_Write32(TileInstPtr->TileAddr + XAIEGBL_NOC_INTCON2NDLEVENA,
							InterruptBitMask);
}
/******************************************************************************/
/**
 *
 * This API configures the 2nd level interrupt controller to be triggered by a
 * groups of interrupts defined at the 1st level section
 *
 * @param	TileInstPtr - Pointer to the Tile instance. Should be shim NoC
 *				tile
 * @param	InterruptBitMask - Group of events to trigger 2nd level
 *					controller
 *
 * @return	None
 *
 * @note	None
 *
 ******************************************************************************/
This API configures the 2nd level interrupt controller to be triggered by a
groups of interrupts defined at the 1st level section

@param       TileInstPtr - Pointer to the Tile instance. Should be shim NoC
tile
@param       InterruptBitMask - Group of events to trigger 2nd level
controller

@return      None

@note        None
This API configures the 2nd level interrupt controller to be triggered by a groups of interrupts defined at the 1st level section @param TileInstPtr - Pointer to the Tile instance . Should be shim NoC tile @param InterruptBitMask - Group of events to trigger 2nd level controller @return None @note None
void XAieTile_NoCIntcL2Enable(XAieGbl_Tile *TileInstPtr, u16 InterruptBitMask)
{
	XAie_AssertNonvoid(TileInstPtr != XAIE_NULL);
	XAie_AssertNonvoid(TileInstPtr->TileType == XAIEGBL_TILE_TYPE_SHIMNOC);
	XAieGbl_Write32(TileInstPtr->TileAddr + XAIEGBL_NOC_INTCON2NDLEVENA,
							InterruptBitMask);
}
void XAieTile_NoCIntcL2Enable ( XAieGbl_Tile * TileInstPtr , u16 InterruptBitMask ) { XAie_AssertNonvoid ( TileInstPtr != XAIE_NULL ) ; XAie_AssertNonvoid ( TileInstPtr -> TileType == XAIEGBL_TILE_TYPE_SHIMNOC ) ; XAieGbl_Write32 ( TileInstPtr -> TileAddr + XAIEGBL_NOC_INTCON2NDLEVENA , InterruptBitMask ) ; }
This API configures the 2nd level interrupt controller to be triggered by a
 groups of interrupts defined at the 1st level section
This API configures the 2nd level interrupt controller to be triggered by a groups of interrupts defined at the 1st level section