src/dpdk/drivers/net/qede/qede_debug.c
static u32 qed_grc_dump_modified_regs(struct ecore_hwfn *p_hwfn,
				      struct ecore_ptt *p_ptt,
				      u32 *dump_buf, bool dump)
{
	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	u32 block_id, offset = 0, stall_regs_offset;
	const struct dbg_attn_reg *attn_reg_arr;
	u8 storm_id, reg_idx, num_attn_regs;
	u32 num_reg_entries = 0;

	/* Write empty header for attention registers */
	offset += qed_grc_dump_regs_hdr(dump_buf,
					false,
					0, SPLIT_TYPE_NONE, 0, "ATTN_REGS");

	/* Write parity registers */
	for (block_id = 0; block_id < NUM_PHYS_BLOCKS; block_id++) {
		if (dev_data->block_in_reset[block_id] && dump)
			continue;

		attn_reg_arr = qed_get_block_attn_regs(p_hwfn,
						       (enum block_id)block_id,
						       ATTN_TYPE_PARITY,
						       &num_attn_regs);

		for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) {
			const struct dbg_attn_reg *reg_data =
				&attn_reg_arr[reg_idx];
			u16 modes_buf_offset;
			bool eval_mode;
			u32 addr;

			/* Check mode */
			eval_mode = GET_FIELD(reg_data->mode.data,
					      DBG_MODE_HDR_EVAL_MODE) > 0;
			modes_buf_offset =
				GET_FIELD(reg_data->mode.data,
					  DBG_MODE_HDR_MODES_BUF_OFFSET);
			if (eval_mode &&
			    !qed_is_mode_match(p_hwfn, &modes_buf_offset))
				continue;

			/* Mode match: read & dump registers */
			addr = reg_data->mask_address;
			offset += qed_grc_dump_reg_entry(p_hwfn,
							 p_ptt,
							 dump_buf + offset,
							 dump,
							 addr,
							 1, false,
							 SPLIT_TYPE_NONE, 0);
			addr = GET_FIELD(reg_data->data,
					 DBG_ATTN_REG_STS_ADDRESS);
			offset += qed_grc_dump_reg_entry(p_hwfn,
							 p_ptt,
							 dump_buf + offset,
							 dump,
							 addr,
							 1, false,
							 SPLIT_TYPE_NONE, 0);
			num_reg_entries += 2;
		}
	}

	/* Overwrite header for attention registers */
	if (dump)
		qed_grc_dump_regs_hdr(dump_buf,
				      true,
				      num_reg_entries,
				      SPLIT_TYPE_NONE, 0, "ATTN_REGS");

	/* Write empty header for stall registers */
	stall_regs_offset = offset;
	offset += qed_grc_dump_regs_hdr(dump_buf,
					false, 0, SPLIT_TYPE_NONE, 0, "REGS");

	/* Write Storm stall status registers */
	for (storm_id = 0, num_reg_entries = 0; storm_id < MAX_DBG_STORMS;
	     storm_id++) {
		struct storm_defs *storm = &s_storm_defs[storm_id];
		u32 addr;

		if (dev_data->block_in_reset[storm->sem_block_id] && dump)
			continue;

		addr =
		    BYTES_TO_DWORDS(storm->sem_fast_mem_addr +
				    SEM_FAST_REG_STALLED);
		offset += qed_grc_dump_reg_entry(p_hwfn,
						 p_ptt,
						 dump_buf + offset,
						 dump,
						 addr,
						 1,
						 false, SPLIT_TYPE_NONE, 0);
		num_reg_entries++;
	}

	/* Overwrite header for stall registers */
	if (dump)
		qed_grc_dump_regs_hdr(dump_buf + stall_regs_offset,
				      true,
				      num_reg_entries,
				      SPLIT_TYPE_NONE, 0, "REGS");

	return offset;
}
/* Dump registers that are modified during GRC Dump and therefore must be
 * dumped first. Returns the dumped size in dwords.
 */
Dump registers that are modified during GRC Dump and therefore must be
dumped first. Returns the dumped size in dwords.
Dump registers that are modified during GRC Dump and therefore must be dumped first . Returns the dumped size in dwords .
static u32 qed_grc_dump_modified_regs(struct ecore_hwfn *p_hwfn,
				      struct ecore_ptt *p_ptt,
				      u32 *dump_buf, bool dump)
{
	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
	u32 block_id, offset = 0, stall_regs_offset;
	const struct dbg_attn_reg *attn_reg_arr;
	u8 storm_id, reg_idx, num_attn_regs;
	u32 num_reg_entries = 0;
	offset += qed_grc_dump_regs_hdr(dump_buf,
					false,
					0, SPLIT_TYPE_NONE, 0, "ATTN_REGS");
	for (block_id = 0; block_id < NUM_PHYS_BLOCKS; block_id++) {
		if (dev_data->block_in_reset[block_id] && dump)
			continue;
		attn_reg_arr = qed_get_block_attn_regs(p_hwfn,
						       (enum block_id)block_id,
						       ATTN_TYPE_PARITY,
						       &num_attn_regs);
		for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) {
			const struct dbg_attn_reg *reg_data =
				&attn_reg_arr[reg_idx];
			u16 modes_buf_offset;
			bool eval_mode;
			u32 addr;
			eval_mode = GET_FIELD(reg_data->mode.data,
					      DBG_MODE_HDR_EVAL_MODE) > 0;
			modes_buf_offset =
				GET_FIELD(reg_data->mode.data,
					  DBG_MODE_HDR_MODES_BUF_OFFSET);
			if (eval_mode &&
			    !qed_is_mode_match(p_hwfn, &modes_buf_offset))
				continue;
			addr = reg_data->mask_address;
			offset += qed_grc_dump_reg_entry(p_hwfn,
							 p_ptt,
							 dump_buf + offset,
							 dump,
							 addr,
							 1, false,
							 SPLIT_TYPE_NONE, 0);
			addr = GET_FIELD(reg_data->data,
					 DBG_ATTN_REG_STS_ADDRESS);
			offset += qed_grc_dump_reg_entry(p_hwfn,
							 p_ptt,
							 dump_buf + offset,
							 dump,
							 addr,
							 1, false,
							 SPLIT_TYPE_NONE, 0);
			num_reg_entries += 2;
		}
	}
	if (dump)
		qed_grc_dump_regs_hdr(dump_buf,
				      true,
				      num_reg_entries,
				      SPLIT_TYPE_NONE, 0, "ATTN_REGS");
	stall_regs_offset = offset;
	offset += qed_grc_dump_regs_hdr(dump_buf,
					false, 0, SPLIT_TYPE_NONE, 0, "REGS");
	for (storm_id = 0, num_reg_entries = 0; storm_id < MAX_DBG_STORMS;
	     storm_id++) {
		struct storm_defs *storm = &s_storm_defs[storm_id];
		u32 addr;
		if (dev_data->block_in_reset[storm->sem_block_id] && dump)
			continue;
		addr =
		    BYTES_TO_DWORDS(storm->sem_fast_mem_addr +
				    SEM_FAST_REG_STALLED);
		offset += qed_grc_dump_reg_entry(p_hwfn,
						 p_ptt,
						 dump_buf + offset,
						 dump,
						 addr,
						 1,
						 false, SPLIT_TYPE_NONE, 0);
		num_reg_entries++;
	}
	if (dump)
		qed_grc_dump_regs_hdr(dump_buf + stall_regs_offset,
				      true,
				      num_reg_entries,
				      SPLIT_TYPE_NONE, 0, "REGS");
	return offset;
}
static u32 qed_grc_dump_modified_regs ( struct ecore_hwfn * p_hwfn , struct ecore_ptt * p_ptt , u32 * dump_buf , bool dump ) { struct dbg_tools_data * dev_data = & p_hwfn -> dbg_info ; u32 block_id , offset = 0 , stall_regs_offset ; const struct dbg_attn_reg * attn_reg_arr ; u8 storm_id , reg_idx , num_attn_regs ; u32 num_reg_entries = 0 ; offset += qed_grc_dump_regs_hdr ( dump_buf , false , 0 , SPLIT_TYPE_NONE , 0 , " " ) ; for ( block_id = 0 ; block_id < NUM_PHYS_BLOCKS ; block_id ++ ) { if ( dev_data -> block_in_reset [ block_id ] && dump ) continue ; attn_reg_arr = qed_get_block_attn_regs ( p_hwfn , ( enum block_id ) block_id , ATTN_TYPE_PARITY , & num_attn_regs ) ; for ( reg_idx = 0 ; reg_idx < num_attn_regs ; reg_idx ++ ) { const struct dbg_attn_reg * reg_data = & attn_reg_arr [ reg_idx ] ; u16 modes_buf_offset ; bool eval_mode ; u32 addr ; eval_mode = GET_FIELD ( reg_data -> mode . data , DBG_MODE_HDR_EVAL_MODE ) > 0 ; modes_buf_offset = GET_FIELD ( reg_data -> mode . data , DBG_MODE_HDR_MODES_BUF_OFFSET ) ; if ( eval_mode && ! qed_is_mode_match ( p_hwfn , & modes_buf_offset ) ) continue ; addr = reg_data -> mask_address ; offset += qed_grc_dump_reg_entry ( p_hwfn , p_ptt , dump_buf + offset , dump , addr , 1 , false , SPLIT_TYPE_NONE , 0 ) ; addr = GET_FIELD ( reg_data -> data , DBG_ATTN_REG_STS_ADDRESS ) ; offset += qed_grc_dump_reg_entry ( p_hwfn , p_ptt , dump_buf + offset , dump , addr , 1 , false , SPLIT_TYPE_NONE , 0 ) ; num_reg_entries += 2 ; } } if ( dump ) qed_grc_dump_regs_hdr ( dump_buf , true , num_reg_entries , SPLIT_TYPE_NONE , 0 , " " ) ; stall_regs_offset = offset ; offset += qed_grc_dump_regs_hdr ( dump_buf , false , 0 , SPLIT_TYPE_NONE , 0 , " " ) ; for ( storm_id = 0 , num_reg_entries = 0 ; storm_id < MAX_DBG_STORMS ; storm_id ++ ) { struct storm_defs * storm = & s_storm_defs [ storm_id ] ; u32 addr ; if ( dev_data -> block_in_reset [ storm -> sem_block_id ] && dump ) continue ; addr = BYTES_TO_DWORDS ( storm -> sem_fast_mem_addr + SEM_FAST_REG_STALLED ) ; offset += qed_grc_dump_reg_entry ( p_hwfn , p_ptt , dump_buf + offset , dump , addr , 1 , false , SPLIT_TYPE_NONE , 0 ) ; num_reg_entries ++ ; } if ( dump ) qed_grc_dump_regs_hdr ( dump_buf + stall_regs_offset , true , num_reg_entries , SPLIT_TYPE_NONE , 0 , " " ) ; return offset ; }
Dump registers that are modified during GRC Dump and therefore must be
 dumped first.
Dump registers that are modified during GRC Dump and therefore must be dumped first .
/* Write empty header for attention registers */ /* Write parity registers */ /* Check mode */ /* Mode match: read & dump registers */ /* Overwrite header for attention registers */ /* Write empty header for stall registers */ /* Write Storm stall status registers */ /* Overwrite header for stall registers */