XilinxProcessorIPLib/drivers/intc/src/xintc.c
int XIntc_Start(XIntc * InstancePtr, u8 Mode)
{
	u32 MasterEnable = XIN_INT_MASTER_ENABLE_MASK;
	XIntc_Config *CfgPtr;
	int Index;

	/*
	 * Assert the arguments
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid((Mode == XIN_SIMULATION_MODE) ||
			(Mode == XIN_REAL_MODE))
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);

	/*
	 * Check for simulation mode
	 */
	if (Mode == XIN_REAL_MODE) {
		MasterEnable |= XIN_INT_HARDWARE_ENABLE_MASK;
	}

	/*
	 * Indicate the instance is ready to be used and is started before we
	 * enable the device.
	 */
	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;

	/* Start the Slaves for Cascade Mode */
	if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
		for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1; Index++)
		{
			CfgPtr = XIntc_LookupConfig(Index);
			XIntc_Out32(CfgPtr->BaseAddress + XIN_MER_OFFSET,
					MasterEnable);
		}
	}

	/* Start the master */
	XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, MasterEnable);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* Starts the interrupt controller by enabling the output from the controller
* to the processor. Interrupts may be generated by the interrupt controller
* after this function is called.
*
* It is necessary for the caller to connect the interrupt handler of this
* component to the proper interrupt source. This function also starts Slave
* controllers in Cascade mode.
*
* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
* @param	Mode determines if software is allowed to simulate interrupts or
*		real interrupts are allowed to occur. Note that these modes are
*		mutually exclusive. The interrupt controller hardware resets in
*		a mode that allows software to simulate interrupts until this
*		mode is exited. It cannot be reentered once it has been exited.
*
*		One of the following values should be used for the mode.
*		- XIN_SIMULATION_MODE enables simulation of interrupts only
*		- XIN_REAL_MODE enables hardware interrupts only
*
* @return
* 		- XST_SUCCESS if the device was started successfully
* 		- XST_FAILURE if simulation mode was specified and it could not
*		be set because real mode has already been entered.
*
* @note 	Must be called after XIntc initialization is completed.
*
******************************************************************************/
Starts the interrupt controller by enabling the output from the controller
to the processor. Interrupts may be generated by the interrupt controller
after this function is called.

It is necessary for the caller to connect the interrupt handler of this
component to the proper interrupt source. This function also starts Slave
controllers in Cascade mode.
Starts the interrupt controller by enabling the output from the controller to the processor . Interrupts may be generated by the interrupt controller after this function is called . It is necessary for the caller to connect the interrupt handler of this component to the proper interrupt source . This function also starts Slave controllers in Cascade mode .
int XIntc_Start(XIntc * InstancePtr, u8 Mode)
{
	u32 MasterEnable = XIN_INT_MASTER_ENABLE_MASK;
	XIntc_Config *CfgPtr;
	int Index;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid((Mode == XIN_SIMULATION_MODE) ||
			(Mode == XIN_REAL_MODE))
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	if (Mode == XIN_REAL_MODE) {
		MasterEnable |= XIN_INT_HARDWARE_ENABLE_MASK;
	}
	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
	if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
		for (Index = 1; Index <= XPAR_XINTC_NUM_INSTANCES - 1; Index++)
		{
			CfgPtr = XIntc_LookupConfig(Index);
			XIntc_Out32(CfgPtr->BaseAddress + XIN_MER_OFFSET,
					MasterEnable);
		}
	}
	XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, MasterEnable);
	return XST_SUCCESS;
}
int XIntc_Start ( XIntc * InstancePtr , u8 Mode ) { u32 MasterEnable = XIN_INT_MASTER_ENABLE_MASK ; XIntc_Config * CfgPtr ; int Index ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( ( Mode == XIN_SIMULATION_MODE ) || ( Mode == XIN_REAL_MODE ) ) Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; if ( Mode == XIN_REAL_MODE ) { MasterEnable |= XIN_INT_HARDWARE_ENABLE_MASK ; } InstancePtr -> IsStarted = XIL_COMPONENT_IS_STARTED ; if ( InstancePtr -> CfgPtr -> IntcType != XIN_INTC_NOCASCADE ) { for ( Index = 1 ; Index <= XPAR_XINTC_NUM_INSTANCES - 1 ; Index ++ ) { CfgPtr = XIntc_LookupConfig ( Index ) ; XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_MER_OFFSET , MasterEnable ) ; } } XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_MER_OFFSET , MasterEnable ) ; return XST_SUCCESS ; }
Starts the interrupt controller by enabling the output from the controller
to the processor.
Starts the interrupt controller by enabling the output from the controller to the processor .
/*
	 * Assert the arguments
	 */ /*
	 * Check for simulation mode
	 */ /*
	 * Indicate the instance is ready to be used and is started before we
	 * enable the device.
	 */ /* Start the Slaves for Cascade Mode */ /* Start the master */