XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_hdmi_intr.c
void XHdmiphy1_HdmiGtTxResetDoneLockHandler(XHdmiphy1 *InstancePtr)
{
    u8 Id, Id0, Id1;
	XHdmiphy1_PllType PllType;
    XHdmiphy1_ChannelId ChId;

    XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_TX_RST_DONE, 0);

    /* Determine PLL type. */
    PllType = XHdmiphy1_GetPllType(InstancePtr, 0, XHDMIPHY1_DIR_TX,
                       XHDMIPHY1_CHANNEL_ID_CH1);
    /* Determine which channel(s) to operate on. */
    ChId = XHdmiphy1_GetRcfgChId(InstancePtr, 0, XHDMIPHY1_DIR_TX,
                PllType);

    /* Set TX TMDS Clock Pattern Generator */
    if ((InstancePtr->Config.UseGtAsTxTmdsClk == TRUE) &&
         ((InstancePtr->TxHdmi21Cfg.IsEnabled == 0) ||
         (InstancePtr->TxHdmi21Cfg.IsEnabled == 1 &&
                InstancePtr->TxHdmi21Cfg.NChannels == 3))) {
         XHdmiphy1_PatgenSetRatio(InstancePtr, 0,
                       (u64)((XHdmiphy1_GetLineRateHz(InstancePtr,
                                    0, ChId)) / 1000000));
         XHdmiphy1_PatgenEnable(InstancePtr, 0, TRUE);
    } else {
         XHdmiphy1_PatgenEnable(InstancePtr, 0, FALSE);
    }

#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    if ((InstancePtr->Config.XcvrType == XHDMIPHY1_GT_TYPE_GTHE4) ||
        (InstancePtr->Config.XcvrType == XHDMIPHY1_GT_TYPE_GTYE4)) {
        XHdmiphy1_TxAlignReset(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, TRUE);
        XHdmiphy1_TxAlignReset(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, FALSE);
    }

    /* GT alignment. */
    XHdmiphy1_TxAlignStart(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, TRUE);
    XHdmiphy1_TxAlignStart(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, FALSE);

    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].TxState =
            XHDMIPHY1_GT_STATE_ALIGN;
    }
#else
	/* Deassert TX LNKRDY MASK */
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, XHDMIPHY1_TX_INIT_REG,
			(XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
					XHDMIPHY1_TX_INIT_REG) & ~0x10101010));

    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].TxState =
        	XHDMIPHY1_GT_STATE_READY;
    }

    /* TX ready callback. */
    if (InstancePtr->HdmiTxReadyCallback) {
        InstancePtr->HdmiTxReadyCallback(InstancePtr->HdmiTxReadyRef);
    }
#endif
}
/*****************************************************************************/
/**
* This function is the handler for events triggered by GT TX reset lock done.
*
* @param    InstancePtr is a pointer to the HDMIPHY instance.
*
* @return   None.
*
* @note     None.
*
******************************************************************************/
This function is the handler for events triggered by GT TX reset lock done.
This function is the handler for events triggered by GT TX reset lock done .
void XHdmiphy1_HdmiGtTxResetDoneLockHandler(XHdmiphy1 *InstancePtr)
{
    u8 Id, Id0, Id1;
	XHdmiphy1_PllType PllType;
    XHdmiphy1_ChannelId ChId;
    XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_TX_RST_DONE, 0);
    PllType = XHdmiphy1_GetPllType(InstancePtr, 0, XHDMIPHY1_DIR_TX,
                       XHDMIPHY1_CHANNEL_ID_CH1);
    ChId = XHdmiphy1_GetRcfgChId(InstancePtr, 0, XHDMIPHY1_DIR_TX,
                PllType);
    if ((InstancePtr->Config.UseGtAsTxTmdsClk == TRUE) &&
         ((InstancePtr->TxHdmi21Cfg.IsEnabled == 0) ||
         (InstancePtr->TxHdmi21Cfg.IsEnabled == 1 &&
                InstancePtr->TxHdmi21Cfg.NChannels == 3))) {
         XHdmiphy1_PatgenSetRatio(InstancePtr, 0,
                       (u64)((XHdmiphy1_GetLineRateHz(InstancePtr,
                                    0, ChId)) / 1000000));
         XHdmiphy1_PatgenEnable(InstancePtr, 0, TRUE);
    } else {
         XHdmiphy1_PatgenEnable(InstancePtr, 0, FALSE);
    }
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    if ((InstancePtr->Config.XcvrType == XHDMIPHY1_GT_TYPE_GTHE4) ||
        (InstancePtr->Config.XcvrType == XHDMIPHY1_GT_TYPE_GTYE4)) {
        XHdmiphy1_TxAlignReset(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, TRUE);
        XHdmiphy1_TxAlignReset(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, FALSE);
    }
    XHdmiphy1_TxAlignStart(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, TRUE);
    XHdmiphy1_TxAlignStart(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, FALSE);
    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].TxState =
            XHDMIPHY1_GT_STATE_ALIGN;
    }
#else
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, XHDMIPHY1_TX_INIT_REG,
			(XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
					XHDMIPHY1_TX_INIT_REG) & ~0x10101010));
    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].TxState =
        	XHDMIPHY1_GT_STATE_READY;
    }
    if (InstancePtr->HdmiTxReadyCallback) {
        InstancePtr->HdmiTxReadyCallback(InstancePtr->HdmiTxReadyRef);
    }
#endif
}
void XHdmiphy1_HdmiGtTxResetDoneLockHandler ( XHdmiphy1 * InstancePtr ) { u8 Id , Id0 , Id1 ; XHdmiphy1_PllType PllType ; XHdmiphy1_ChannelId ChId ; XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_TX_RST_DONE , 0 ) ; PllType = XHdmiphy1_GetPllType ( InstancePtr , 0 , XHDMIPHY1_DIR_TX , XHDMIPHY1_CHANNEL_ID_CH1 ) ; ChId = XHdmiphy1_GetRcfgChId ( InstancePtr , 0 , XHDMIPHY1_DIR_TX , PllType ) ; if ( ( InstancePtr -> Config . UseGtAsTxTmdsClk == TRUE ) && ( ( InstancePtr -> TxHdmi21Cfg . IsEnabled == 0 ) || ( InstancePtr -> TxHdmi21Cfg . IsEnabled == 1 && InstancePtr -> TxHdmi21Cfg . NChannels == 3 ) ) ) { XHdmiphy1_PatgenSetRatio ( InstancePtr , 0 , ( u64 ) ( ( XHdmiphy1_GetLineRateHz ( InstancePtr , 0 , ChId ) ) / 1000000 ) ) ; XHdmiphy1_PatgenEnable ( InstancePtr , 0 , TRUE ) ; } else { XHdmiphy1_PatgenEnable ( InstancePtr , 0 , FALSE ) ; } #if ( XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5 ) if ( ( InstancePtr -> Config . XcvrType == XHDMIPHY1_GT_TYPE_GTHE4 ) || ( InstancePtr -> Config . XcvrType == XHDMIPHY1_GT_TYPE_GTYE4 ) ) { XHdmiphy1_TxAlignReset ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , TRUE ) ; XHdmiphy1_TxAlignReset ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , FALSE ) ; } XHdmiphy1_TxAlignStart ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , TRUE ) ; XHdmiphy1_TxAlignStart ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , FALSE ) ; XHdmiphy1_Ch2Ids ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . TxState = XHDMIPHY1_GT_STATE_ALIGN ; } #else XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_TX_INIT_REG , ( XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_TX_INIT_REG ) & ~ 0x10101010 ) ) ; XHdmiphy1_Ch2Ids ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . TxState = XHDMIPHY1_GT_STATE_READY ; } if ( InstancePtr -> HdmiTxReadyCallback ) { InstancePtr -> HdmiTxReadyCallback ( InstancePtr -> HdmiTxReadyRef ) ; } #endif }
This function is the handler for events triggered by GT TX reset lock done.
This function is the handler for events triggered by GT TX reset lock done .
/* Determine PLL type. */ /* Determine which channel(s) to operate on. */ /* Set TX TMDS Clock Pattern Generator */ /* GT alignment. */ /* Deassert TX LNKRDY MASK */ /* TX ready callback. */