src/dpdk/drivers/net/txgbe/base/txgbe_hw.c
void txgbe_clear_tx_pending(struct txgbe_hw *hw)
{
	u32 hlreg0, i, poll;

	/*
	 * If double reset is not requested then all transactions should
	 * already be clear and as such there is no work to do
	 */
	if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
		return;

	hlreg0 = rd32(hw, TXGBE_PSRCTL);
	wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);

	/* Wait for a last completion before clearing buffers */
	txgbe_flush(hw);
	msec_delay(3);

	/*
	 * Before proceeding, make sure that the PCIe block does not have
	 * transactions pending.
	 */
	poll = (800 * 11) / 10;
	for (i = 0; i < poll; i++)
		usec_delay(100);

	/* Flush all writes and allow 20usec for all transactions to clear */
	txgbe_flush(hw);
	usec_delay(20);

	/* restore previous register values */
	wr32(hw, TXGBE_PSRCTL, hlreg0);
}
/**
 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
 * @hw: pointer to the hardware structure
 *
 * The MACs can experience issues if TX work is still pending
 * when a reset occurs.  This function prevents this by flushing the PCIe
 * buffers on the system.
 **/
Clear pending TX work from the PCIe fifo
@hw: pointer to the hardware structure

The MACs can experience issues if TX work is still pending
when a reset occurs.  This function prevents this by flushing the PCIe
buffers on the system.
Clear pending TX work from the PCIe fifo @hw : pointer to the hardware structure The MACs can experience issues if TX work is still pending when a reset occurs . This function prevents this by flushing the PCIe buffers on the system .
void txgbe_clear_tx_pending(struct txgbe_hw *hw)
{
	u32 hlreg0, i, poll;
	if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
		return;
	hlreg0 = rd32(hw, TXGBE_PSRCTL);
	wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
	txgbe_flush(hw);
	msec_delay(3);
	poll = (800 * 11) / 10;
	for (i = 0; i < poll; i++)
		usec_delay(100);
	txgbe_flush(hw);
	usec_delay(20);
	wr32(hw, TXGBE_PSRCTL, hlreg0);
}
void txgbe_clear_tx_pending ( struct txgbe_hw * hw ) { u32 hlreg0 , i , poll ; if ( ! ( hw -> mac . flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED ) ) return ; hlreg0 = rd32 ( hw , TXGBE_PSRCTL ) ; wr32 ( hw , TXGBE_PSRCTL , hlreg0 | TXGBE_PSRCTL_LBENA ) ; txgbe_flush ( hw ) ; msec_delay ( 3 ) ; poll = ( 800 * 11 ) / 10 ; for ( i = 0 ; i < poll ; i ++ ) usec_delay ( 100 ) ; txgbe_flush ( hw ) ; usec_delay ( 20 ) ; wr32 ( hw , TXGBE_PSRCTL , hlreg0 ) ; }
txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
 @hw: pointer to the hardware structure
txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo @hw : pointer to the hardware structure
/*
	 * If double reset is not requested then all transactions should
	 * already be clear and as such there is no work to do
	 */ /* Wait for a last completion before clearing buffers */ /*
	 * Before proceeding, make sure that the PCIe block does not have
	 * transactions pending.
	 */ /* Flush all writes and allow 20usec for all transactions to clear */ /* restore previous register values */