XilinxProcessorIPLib/drivers/dp12txss/src/xdptxss_intr.c
void XDpTxSs_HpdEventProcess(void *InstancePtr)
{
	u32 Status = XST_SUCCESS;
	XDpTxSs *XDpTxSsPtr = (XDpTxSs *)InstancePtr;

	/* Verify arguments. */
	Xil_AssertVoid(XDpTxSsPtr != NULL);
	Xil_AssertVoid(XDpTxSsPtr->IsReady == XIL_COMPONENT_IS_READY);
	XDpTxSs_UsrHpdEventData *UsrHpdEventData = &XDpTxSsPtr->UsrHpdEventData;

	if (XDp_TxIsConnected(XDpTxSsPtr->DpPtr)) {
		/* From here is the requirement per DP spec */
		Status = XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_MAX_LINK_RATE, 1,
				&UsrHpdEventData->MaxCapNew);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_MAX_LANE_COUNT, 1,
				&UsrHpdEventData->MaxCapLanesNew);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr, XDP_DPCD_REV, 12,
				UsrHpdEventData->Tmp);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_SINK_COUNT, 6,	UsrHpdEventData->Tmp);

		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr, XDP_DPCD_REV, 11,
				&UsrHpdEventData->Dpcd);
		Status |= XDp_TxGetEdidBlock(XDpTxSsPtr->DpPtr,
				UsrHpdEventData->EdidOrg, 0);

		if (UsrHpdEventData->EdidOrg[XDP_EDID_EXT_BLOCK_COUNT] > 0)
                       Status |= XDp_TxGetEdidBlock(XDpTxSsPtr->DpPtr,
                                                    UsrHpdEventData->EdidOrg_1,
                                                    1);
               if (UsrHpdEventData->EdidOrg_1[XDP_EDID_EXT_BLOCK_COUNT] > 1)
                        Status |= XDp_TxGetEdidBlock(XDpTxSsPtr->DpPtr,
                                                     UsrHpdEventData->EdidOrg_2,
                                                     2);

		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr, XDP_DPCD_SINK_COUNT,
				1, &UsrHpdEventData->Rd200);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_STATUS_LANE_0_1, 1,
				&UsrHpdEventData->Lane0Sts);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_STATUS_LANE_2_3, 1,
				&UsrHpdEventData->Lane2Sts);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_MAX_LINK_RATE, 1,
				&UsrHpdEventData->MaxCapNew);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_MAX_LANE_COUNT, 1,
				&UsrHpdEventData->MaxCapLanesNew);
	}

	if(Status != XST_SUCCESS){
		xdbg_printf(XDBG_DEBUG_GENERAL, "AUX access had trouble!\r\n");
	}
}
/*****************************************************************************/
/**
*
* This function is process some DP driver read as per DP spec on HPD EVENT.
*
* @param	InstancePtr is a pointer to the XDpTxSs core instance that
*		just interrupted.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function is process some DP driver read as per DP spec on HPD EVENT.
This function is process some DP driver read as per DP spec on HPD EVENT .
void XDpTxSs_HpdEventProcess(void *InstancePtr)
{
	u32 Status = XST_SUCCESS;
	XDpTxSs *XDpTxSsPtr = (XDpTxSs *)InstancePtr;
	Xil_AssertVoid(XDpTxSsPtr != NULL);
	Xil_AssertVoid(XDpTxSsPtr->IsReady == XIL_COMPONENT_IS_READY);
	XDpTxSs_UsrHpdEventData *UsrHpdEventData = &XDpTxSsPtr->UsrHpdEventData;
	if (XDp_TxIsConnected(XDpTxSsPtr->DpPtr)) {
		Status = XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_MAX_LINK_RATE, 1,
				&UsrHpdEventData->MaxCapNew);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_MAX_LANE_COUNT, 1,
				&UsrHpdEventData->MaxCapLanesNew);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr, XDP_DPCD_REV, 12,
				UsrHpdEventData->Tmp);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_SINK_COUNT, 6,	UsrHpdEventData->Tmp);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr, XDP_DPCD_REV, 11,
				&UsrHpdEventData->Dpcd);
		Status |= XDp_TxGetEdidBlock(XDpTxSsPtr->DpPtr,
				UsrHpdEventData->EdidOrg, 0);
		if (UsrHpdEventData->EdidOrg[XDP_EDID_EXT_BLOCK_COUNT] > 0)
                       Status |= XDp_TxGetEdidBlock(XDpTxSsPtr->DpPtr,
                                                    UsrHpdEventData->EdidOrg_1,
                                                    1);
               if (UsrHpdEventData->EdidOrg_1[XDP_EDID_EXT_BLOCK_COUNT] > 1)
                        Status |= XDp_TxGetEdidBlock(XDpTxSsPtr->DpPtr,
                                                     UsrHpdEventData->EdidOrg_2,
                                                     2);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr, XDP_DPCD_SINK_COUNT,
				1, &UsrHpdEventData->Rd200);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_STATUS_LANE_0_1, 1,
				&UsrHpdEventData->Lane0Sts);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_STATUS_LANE_2_3, 1,
				&UsrHpdEventData->Lane2Sts);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_MAX_LINK_RATE, 1,
				&UsrHpdEventData->MaxCapNew);
		Status |= XDp_TxAuxRead(XDpTxSsPtr->DpPtr,
				XDP_DPCD_MAX_LANE_COUNT, 1,
				&UsrHpdEventData->MaxCapLanesNew);
	}
	if(Status != XST_SUCCESS){
		xdbg_printf(XDBG_DEBUG_GENERAL, "AUX access had trouble!\r\n");
	}
}
void XDpTxSs_HpdEventProcess ( void * InstancePtr ) { u32 Status = XST_SUCCESS ; XDpTxSs * XDpTxSsPtr = ( XDpTxSs * ) InstancePtr ; Xil_AssertVoid ( XDpTxSsPtr != NULL ) ; Xil_AssertVoid ( XDpTxSsPtr -> IsReady == XIL_COMPONENT_IS_READY ) ; XDpTxSs_UsrHpdEventData * UsrHpdEventData = & XDpTxSsPtr -> UsrHpdEventData ; if ( XDp_TxIsConnected ( XDpTxSsPtr -> DpPtr ) ) { Status = XDp_TxAuxRead ( XDpTxSsPtr -> DpPtr , XDP_DPCD_MAX_LINK_RATE , 1 , & UsrHpdEventData -> MaxCapNew ) ; Status |= XDp_TxAuxRead ( XDpTxSsPtr -> DpPtr , XDP_DPCD_MAX_LANE_COUNT , 1 , & UsrHpdEventData -> MaxCapLanesNew ) ; Status |= XDp_TxAuxRead ( XDpTxSsPtr -> DpPtr , XDP_DPCD_REV , 12 , UsrHpdEventData -> Tmp ) ; Status |= XDp_TxAuxRead ( XDpTxSsPtr -> DpPtr , XDP_DPCD_SINK_COUNT , 6 , UsrHpdEventData -> Tmp ) ; Status |= XDp_TxAuxRead ( XDpTxSsPtr -> DpPtr , XDP_DPCD_REV , 11 , & UsrHpdEventData -> Dpcd ) ; Status |= XDp_TxGetEdidBlock ( XDpTxSsPtr -> DpPtr , UsrHpdEventData -> EdidOrg , 0 ) ; if ( UsrHpdEventData -> EdidOrg [ XDP_EDID_EXT_BLOCK_COUNT ] > 0 ) Status |= XDp_TxGetEdidBlock ( XDpTxSsPtr -> DpPtr , UsrHpdEventData -> EdidOrg_1 , 1 ) ; if ( UsrHpdEventData -> EdidOrg_1 [ XDP_EDID_EXT_BLOCK_COUNT ] > 1 ) Status |= XDp_TxGetEdidBlock ( XDpTxSsPtr -> DpPtr , UsrHpdEventData -> EdidOrg_2 , 2 ) ; Status |= XDp_TxAuxRead ( XDpTxSsPtr -> DpPtr , XDP_DPCD_SINK_COUNT , 1 , & UsrHpdEventData -> Rd200 ) ; Status |= XDp_TxAuxRead ( XDpTxSsPtr -> DpPtr , XDP_DPCD_STATUS_LANE_0_1 , 1 , & UsrHpdEventData -> Lane0Sts ) ; Status |= XDp_TxAuxRead ( XDpTxSsPtr -> DpPtr , XDP_DPCD_STATUS_LANE_2_3 , 1 , & UsrHpdEventData -> Lane2Sts ) ; Status |= XDp_TxAuxRead ( XDpTxSsPtr -> DpPtr , XDP_DPCD_MAX_LINK_RATE , 1 , & UsrHpdEventData -> MaxCapNew ) ; Status |= XDp_TxAuxRead ( XDpTxSsPtr -> DpPtr , XDP_DPCD_MAX_LANE_COUNT , 1 , & UsrHpdEventData -> MaxCapLanesNew ) ; } if ( Status != XST_SUCCESS ) { xdbg_printf ( XDBG_DEBUG_GENERAL , " \r \n " ) ; } }
This function is process some DP driver read as per DP spec on HPD EVENT.
This function is process some DP driver read as per DP spec on HPD EVENT .
/* Verify arguments. */ /* From here is the requirement per DP spec */