XilinxProcessorIPLib/drivers/hdcp1x/src/xhdcp1x_cipher.c
int XHdcp1x_CipherSetNumLanes(XHdcp1x *InstancePtr, u32 NumLanes)
{
	int Status = XST_SUCCESS;
	u32 Value = 0;

	/* Verify arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(NumLanes > 0);
	Xil_AssertNonvoid(NumLanes <= 4);

	/* Check for HDMI */
	if (XHdcp1x_IsHDMI(InstancePtr)) {
		/* Verify NumLanes (again) */
		Xil_AssertNonvoid(NumLanes == 1);

		/* Update the control register */
		Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CONTROL);
		Value &= ~XHDCP1X_CIPHER_BITMASK_CONTROL_NUM_LANES;
		Value |= (NumLanes << 4);
		XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CONTROL, Value);
	}
	/* Otherwise - must be DP */
	else {
		/* Verify NumLanes (again) */
		Xil_AssertNonvoid(NumLanes != 3);

		/* Update the control register */
		Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CONTROL);
		Value &= ~XHDCP1X_CIPHER_BITMASK_CONTROL_NUM_LANES;
		Value |= (NumLanes << 4);
		XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CONTROL, Value);
	}

	return (Status);
}
/*****************************************************************************/
/**
* This function configures the number of lanes of the HDCP cipher.
*
* @param	InstancePtr is the device to configure.
* @param	NumLanes is the number of lanes to configure.
*
* @return
*		- XST_SUCCESS if successful.
*
* @note		None.
*
******************************************************************************/
This function configures the number of lanes of the HDCP cipher.
This function configures the number of lanes of the HDCP cipher .
int XHdcp1x_CipherSetNumLanes(XHdcp1x *InstancePtr, u32 NumLanes)
{
	int Status = XST_SUCCESS;
	u32 Value = 0;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(NumLanes > 0);
	Xil_AssertNonvoid(NumLanes <= 4);
	if (XHdcp1x_IsHDMI(InstancePtr)) {
		Xil_AssertNonvoid(NumLanes == 1);
		Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CONTROL);
		Value &= ~XHDCP1X_CIPHER_BITMASK_CONTROL_NUM_LANES;
		Value |= (NumLanes << 4);
		XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CONTROL, Value);
	}
	else {
		Xil_AssertNonvoid(NumLanes != 3);
		Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CONTROL);
		Value &= ~XHDCP1X_CIPHER_BITMASK_CONTROL_NUM_LANES;
		Value |= (NumLanes << 4);
		XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CONTROL, Value);
	}
	return (Status);
}
int XHdcp1x_CipherSetNumLanes ( XHdcp1x * InstancePtr , u32 NumLanes ) { int Status = XST_SUCCESS ; u32 Value = 0 ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( NumLanes > 0 ) ; Xil_AssertNonvoid ( NumLanes <= 4 ) ; if ( XHdcp1x_IsHDMI ( InstancePtr ) ) { Xil_AssertNonvoid ( NumLanes == 1 ) ; Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL ) ; Value &= ~ XHDCP1X_CIPHER_BITMASK_CONTROL_NUM_LANES ; Value |= ( NumLanes << 4 ) ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL , Value ) ; } else { Xil_AssertNonvoid ( NumLanes != 3 ) ; Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL ) ; Value &= ~ XHDCP1X_CIPHER_BITMASK_CONTROL_NUM_LANES ; Value |= ( NumLanes << 4 ) ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL , Value ) ; } return ( Status ) ; }
This function configures the number of lanes of the HDCP cipher.
This function configures the number of lanes of the HDCP cipher .
/* Verify arguments. */ /* Check for HDMI */ /* Verify NumLanes (again) */ /* Update the control register */ /* Otherwise - must be DP */ /* Verify NumLanes (again) */ /* Update the control register */