src/dpdk/drivers/net/i40e/i40e_ethdev.c
uint64_t
i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
{
	uint64_t val = 0;
	uint16_t i;

	struct inset_map {
		uint64_t inset;
		uint64_t inset_reg;
	};

	static const struct inset_map inset_map_common[] = {
		{I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
		{I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
		{I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
		{I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
		{I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
		{I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
		{I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
		{I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
		{I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
		{I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
		{I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
		{I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
		{I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
		{I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
		{I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
		{I40E_INSET_TUNNEL_DMAC,
			I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
		{I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
		{I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
		{I40E_INSET_TUNNEL_SRC_PORT,
			I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
		{I40E_INSET_TUNNEL_DST_PORT,
			I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
		{I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
		{I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
		{I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
		{I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
		{I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
		{I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
		{I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
		{I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
		{I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
	};

    /* some different registers map in x722*/
	static const struct inset_map inset_map_diff_x722[] = {
		{I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
		{I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
		{I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
		{I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
	};

	static const struct inset_map inset_map_diff_not_x722[] = {
		{I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
		{I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
		{I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
		{I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
	};

	if (input == 0)
		return val;

	/* Translate input set to register aware inset */
	if (type == I40E_MAC_X722) {
		for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
			if (input & inset_map_diff_x722[i].inset)
				val |= inset_map_diff_x722[i].inset_reg;
		}
	} else {
		for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
			if (input & inset_map_diff_not_x722[i].inset)
				val |= inset_map_diff_not_x722[i].inset_reg;
		}
	}

	for (i = 0; i < RTE_DIM(inset_map_common); i++) {
		if (input & inset_map_common[i].inset)
			val |= inset_map_common[i].inset_reg;
	}

	return val;
}
/**
 * Translate the input set from bit masks to register aware bit masks
 * and vice versa
 */
Translate the input set from bit masks to register aware bit masks
and vice versa
Translate the input set from bit masks to register aware bit masks and vice versa
uint64_t
i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
{
	uint64_t val = 0;
	uint16_t i;
	struct inset_map {
		uint64_t inset;
		uint64_t inset_reg;
	};
	static const struct inset_map inset_map_common[] = {
		{I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
		{I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
		{I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
		{I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
		{I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
		{I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
		{I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
		{I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
		{I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
		{I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
		{I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
		{I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
		{I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
		{I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
		{I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
		{I40E_INSET_TUNNEL_DMAC,
			I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
		{I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
		{I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
		{I40E_INSET_TUNNEL_SRC_PORT,
			I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
		{I40E_INSET_TUNNEL_DST_PORT,
			I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
		{I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
		{I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
		{I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
		{I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
		{I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
		{I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
		{I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
		{I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
		{I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
	};
	static const struct inset_map inset_map_diff_x722[] = {
		{I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
		{I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
		{I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
		{I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
	};
	static const struct inset_map inset_map_diff_not_x722[] = {
		{I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
		{I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
		{I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
		{I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
	};
	if (input == 0)
		return val;
	if (type == I40E_MAC_X722) {
		for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
			if (input & inset_map_diff_x722[i].inset)
				val |= inset_map_diff_x722[i].inset_reg;
		}
	} else {
		for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
			if (input & inset_map_diff_not_x722[i].inset)
				val |= inset_map_diff_not_x722[i].inset_reg;
		}
	}
	for (i = 0; i < RTE_DIM(inset_map_common); i++) {
		if (input & inset_map_common[i].inset)
			val |= inset_map_common[i].inset_reg;
	}
	return val;
}
uint64_t i40e_translate_input_set_reg ( enum i40e_mac_type type , uint64_t input ) { uint64_t val = 0 ; uint16_t i ; struct inset_map { uint64_t inset ; uint64_t inset_reg ; } ; static const struct inset_map inset_map_common [ ] = { { I40E_INSET_DMAC , I40E_REG_INSET_L2_DMAC } , { I40E_INSET_SMAC , I40E_REG_INSET_L2_SMAC } , { I40E_INSET_VLAN_OUTER , I40E_REG_INSET_L2_OUTER_VLAN } , { I40E_INSET_VLAN_INNER , I40E_REG_INSET_L2_INNER_VLAN } , { I40E_INSET_LAST_ETHER_TYPE , I40E_REG_INSET_LAST_ETHER_TYPE } , { I40E_INSET_IPV4_TOS , I40E_REG_INSET_L3_IP4_TOS } , { I40E_INSET_IPV6_SRC , I40E_REG_INSET_L3_SRC_IP6 } , { I40E_INSET_IPV6_DST , I40E_REG_INSET_L3_DST_IP6 } , { I40E_INSET_IPV6_TC , I40E_REG_INSET_L3_IP6_TC } , { I40E_INSET_IPV6_NEXT_HDR , I40E_REG_INSET_L3_IP6_NEXT_HDR } , { I40E_INSET_IPV6_HOP_LIMIT , I40E_REG_INSET_L3_IP6_HOP_LIMIT } , { I40E_INSET_SRC_PORT , I40E_REG_INSET_L4_SRC_PORT } , { I40E_INSET_DST_PORT , I40E_REG_INSET_L4_DST_PORT } , { I40E_INSET_SCTP_VT , I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG } , { I40E_INSET_TUNNEL_ID , I40E_REG_INSET_TUNNEL_ID } , { I40E_INSET_TUNNEL_DMAC , I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC } , { I40E_INSET_TUNNEL_IPV4_DST , I40E_REG_INSET_TUNNEL_L3_DST_IP4 } , { I40E_INSET_TUNNEL_IPV6_DST , I40E_REG_INSET_TUNNEL_L3_DST_IP6 } , { I40E_INSET_TUNNEL_SRC_PORT , I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT } , { I40E_INSET_TUNNEL_DST_PORT , I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT } , { I40E_INSET_VLAN_TUNNEL , I40E_REG_INSET_TUNNEL_VLAN } , { I40E_INSET_FLEX_PAYLOAD_W1 , I40E_REG_INSET_FLEX_PAYLOAD_WORD1 } , { I40E_INSET_FLEX_PAYLOAD_W2 , I40E_REG_INSET_FLEX_PAYLOAD_WORD2 } , { I40E_INSET_FLEX_PAYLOAD_W3 , I40E_REG_INSET_FLEX_PAYLOAD_WORD3 } , { I40E_INSET_FLEX_PAYLOAD_W4 , I40E_REG_INSET_FLEX_PAYLOAD_WORD4 } , { I40E_INSET_FLEX_PAYLOAD_W5 , I40E_REG_INSET_FLEX_PAYLOAD_WORD5 } , { I40E_INSET_FLEX_PAYLOAD_W6 , I40E_REG_INSET_FLEX_PAYLOAD_WORD6 } , { I40E_INSET_FLEX_PAYLOAD_W7 , I40E_REG_INSET_FLEX_PAYLOAD_WORD7 } , { I40E_INSET_FLEX_PAYLOAD_W8 , I40E_REG_INSET_FLEX_PAYLOAD_WORD8 } , } ; static const struct inset_map inset_map_diff_x722 [ ] = { { I40E_INSET_IPV4_SRC , I40E_X722_REG_INSET_L3_SRC_IP4 } , { I40E_INSET_IPV4_DST , I40E_X722_REG_INSET_L3_DST_IP4 } , { I40E_INSET_IPV4_PROTO , I40E_X722_REG_INSET_L3_IP4_PROTO } , { I40E_INSET_IPV4_TTL , I40E_X722_REG_INSET_L3_IP4_TTL } , } ; static const struct inset_map inset_map_diff_not_x722 [ ] = { { I40E_INSET_IPV4_SRC , I40E_REG_INSET_L3_SRC_IP4 } , { I40E_INSET_IPV4_DST , I40E_REG_INSET_L3_DST_IP4 } , { I40E_INSET_IPV4_PROTO , I40E_REG_INSET_L3_IP4_PROTO } , { I40E_INSET_IPV4_TTL , I40E_REG_INSET_L3_IP4_TTL } , } ; if ( input == 0 ) return val ; if ( type == I40E_MAC_X722 ) { for ( i = 0 ; i < RTE_DIM ( inset_map_diff_x722 ) ; i ++ ) { if ( input & inset_map_diff_x722 [ i ] . inset ) val |= inset_map_diff_x722 [ i ] . inset_reg ; } } else { for ( i = 0 ; i < RTE_DIM ( inset_map_diff_not_x722 ) ; i ++ ) { if ( input & inset_map_diff_not_x722 [ i ] . inset ) val |= inset_map_diff_not_x722 [ i ] . inset_reg ; } } for ( i = 0 ; i < RTE_DIM ( inset_map_common ) ; i ++ ) { if ( input & inset_map_common [ i ] . inset ) val |= inset_map_common [ i ] . inset_reg ; } return val ; }
Translate the input set from bit masks to register aware bit masks
 and vice versa
Translate the input set from bit masks to register aware bit masks and vice versa
/* some different registers map in x722*/ /* Translate input set to register aware inset */