src/memory/memory.c
Flag mem_process_mlc_hit_access(Mem_Req* req, Mem_Queue_Entry* mlc_queue_entry,
                                Addr* line_addr, MLC_Data* data,
                                int lru_position) {
  if(!req->done_func ||
     req->done_func(req)) { /* If done_func is not complete we will keep
                               accessing MLC until done_func returns TRUE */

    if(data) { /* not perfect mlc */
      if((req->type == MRT_DFETCH) || (req->type == MRT_DSTORE) ||
         (req->type == MRT_IFETCH)) {
        if(data->prefetch) {  // prefetch hit
          DEBUG(req->proc_id, "%7lld mlc prefetch hit %d\n", cycle_count,
                (int)(req->addr));
          STAT_EVENT(req->proc_id, MLC_PREF_HIT);
          if(!data->seen_prefetch) {
            data->seen_prefetch = TRUE;

            STAT_EVENT(req->proc_id, MLC_PREF_UNIQUE_HIT);
            STAT_EVENT(req->proc_id, PREF_MLC_TOTAL_USED);
            STAT_EVENT(req->proc_id, CORE_PREF_MLC_USED);
            STAT_EVENT(req->proc_id, CORE_MLC_PREF_FILL_USED);
          }
        }
      }

      if(req->type == MRT_DPRF || req->type == MRT_IPRF ||
         req->demand_match_prefetch) {
        STAT_EVENT(req->proc_id, MLC_PREF_REQ_HIT);
        STAT_EVENT(req->proc_id, CORE_MLC_PREF_REQ_HIT);
      } else if((req->type == MRT_DFETCH) || (req->type == MRT_DSTORE) ||
                (req->type == MRT_IFETCH)) {
        STAT_EVENT(req->proc_id, MLC_DEMAND_HIT);
        STAT_EVENT(req->proc_id, CORE_MLC_DEMAND_HIT);
      } else {  // CMP Watch out RA
        STAT_EVENT(req->proc_id, MLC_WB_HIT);
        STAT_EVENT(req->proc_id, CORE_MLC_WB_HIT);
      }
      data->dirty |= (req->type == MRT_WB);
    }

    if((req->type == MRT_DFETCH) || (req->type == MRT_DSTORE) ||
       (req->type == MRT_IFETCH)) {
      STAT_EVENT(req->proc_id, MLC_HIT);
      STAT_EVENT(req->proc_id, CORE_MLC_HIT);
      STAT_EVENT(req->proc_id, MLC_HIT_ONPATH + req->off_path);
      if(0 && DEBUG_EXC_INSERTS) {
        printf("addr:%s hit in MLC type:%s\n", hexstr64s(req->addr),
               Mem_Req_Type_str(req->type));
      }
    }

    STAT_EVENT_ALL(MLC_HIT_ALL);
    STAT_EVENT_ALL(MLC_HIT_ALL_ONPATH + req->off_path);

    // cmp IGNORE
    if(req->off_path)
      STAT_EVENT(req->proc_id, MLC_HIT_OFFPATH_IFETCH + MIN2(req->type, 6));
    else
      STAT_EVENT(req->proc_id, MLC_HIT_ONPATH_IFETCH + MIN2(req->type, 6));

    if(MLC_WRITE_THROUGH && (req->type == MRT_WB)) {
      req->state     = MRS_L1_NEW;
      req->rdy_cycle = cycle_count + MLCQ_TO_L1Q_TRANSFER_LATENCY;
    } else {  // writeback done
      /* Remove the entry from request buffer */
      req->state = MRS_MLC_HIT_DONE;
      mem_free_reqbuf(req);
    }

    /* Set the priority so that this entry will be removed from the mlc_queue */
    mlc_queue_entry->priority = Mem_Req_Priority_Offset[MRT_MIN_PRIORITY];

    return TRUE;
  } else {
    return FALSE;
  }
}
/**************************************************************************************/
/* mem_process_mlc_hit_access: */
/* Returns TRUE if mlc access is complete and needs to be removed from mlc_queue
 */
Returns TRUE if mlc access is complete and needs to be removed from mlc_queue
Returns TRUE if mlc access is complete and needs to be removed from mlc_queue
Flag mem_process_mlc_hit_access(Mem_Req* req, Mem_Queue_Entry* mlc_queue_entry,
                                Addr* line_addr, MLC_Data* data,
                                int lru_position) {
  if(!req->done_func ||
     req->done_func(req)) { 
    if(data) { 
      if((req->type == MRT_DFETCH) || (req->type == MRT_DSTORE) ||
         (req->type == MRT_IFETCH)) {
        if(data->prefetch) {  
          DEBUG(req->proc_id, "%7lld mlc prefetch hit %d\n", cycle_count,
                (int)(req->addr));
          STAT_EVENT(req->proc_id, MLC_PREF_HIT);
          if(!data->seen_prefetch) {
            data->seen_prefetch = TRUE;
            STAT_EVENT(req->proc_id, MLC_PREF_UNIQUE_HIT);
            STAT_EVENT(req->proc_id, PREF_MLC_TOTAL_USED);
            STAT_EVENT(req->proc_id, CORE_PREF_MLC_USED);
            STAT_EVENT(req->proc_id, CORE_MLC_PREF_FILL_USED);
          }
        }
      }
      if(req->type == MRT_DPRF || req->type == MRT_IPRF ||
         req->demand_match_prefetch) {
        STAT_EVENT(req->proc_id, MLC_PREF_REQ_HIT);
        STAT_EVENT(req->proc_id, CORE_MLC_PREF_REQ_HIT);
      } else if((req->type == MRT_DFETCH) || (req->type == MRT_DSTORE) ||
                (req->type == MRT_IFETCH)) {
        STAT_EVENT(req->proc_id, MLC_DEMAND_HIT);
        STAT_EVENT(req->proc_id, CORE_MLC_DEMAND_HIT);
      } else {  
        STAT_EVENT(req->proc_id, MLC_WB_HIT);
        STAT_EVENT(req->proc_id, CORE_MLC_WB_HIT);
      }
      data->dirty |= (req->type == MRT_WB);
    }
    if((req->type == MRT_DFETCH) || (req->type == MRT_DSTORE) ||
       (req->type == MRT_IFETCH)) {
      STAT_EVENT(req->proc_id, MLC_HIT);
      STAT_EVENT(req->proc_id, CORE_MLC_HIT);
      STAT_EVENT(req->proc_id, MLC_HIT_ONPATH + req->off_path);
      if(0 && DEBUG_EXC_INSERTS) {
        printf("addr:%s hit in MLC type:%s\n", hexstr64s(req->addr),
               Mem_Req_Type_str(req->type));
      }
    }
    STAT_EVENT_ALL(MLC_HIT_ALL);
    STAT_EVENT_ALL(MLC_HIT_ALL_ONPATH + req->off_path);
    if(req->off_path)
      STAT_EVENT(req->proc_id, MLC_HIT_OFFPATH_IFETCH + MIN2(req->type, 6));
    else
      STAT_EVENT(req->proc_id, MLC_HIT_ONPATH_IFETCH + MIN2(req->type, 6));
    if(MLC_WRITE_THROUGH && (req->type == MRT_WB)) {
      req->state     = MRS_L1_NEW;
      req->rdy_cycle = cycle_count + MLCQ_TO_L1Q_TRANSFER_LATENCY;
    } else {  
      req->state = MRS_MLC_HIT_DONE;
      mem_free_reqbuf(req);
    }
    mlc_queue_entry->priority = Mem_Req_Priority_Offset[MRT_MIN_PRIORITY];
    return TRUE;
  } else {
    return FALSE;
  }
}
Flag mem_process_mlc_hit_access ( Mem_Req * req , Mem_Queue_Entry * mlc_queue_entry , Addr * line_addr , MLC_Data * data , int lru_position ) { if ( ! req -> done_func || req -> done_func ( req ) ) { if ( data ) { if ( ( req -> type == MRT_DFETCH ) || ( req -> type == MRT_DSTORE ) || ( req -> type == MRT_IFETCH ) ) { if ( data -> prefetch ) { DEBUG ( req -> proc_id , " \n " , cycle_count , ( int ) ( req -> addr ) ) ; STAT_EVENT ( req -> proc_id , MLC_PREF_HIT ) ; if ( ! data -> seen_prefetch ) { data -> seen_prefetch = TRUE ; STAT_EVENT ( req -> proc_id , MLC_PREF_UNIQUE_HIT ) ; STAT_EVENT ( req -> proc_id , PREF_MLC_TOTAL_USED ) ; STAT_EVENT ( req -> proc_id , CORE_PREF_MLC_USED ) ; STAT_EVENT ( req -> proc_id , CORE_MLC_PREF_FILL_USED ) ; } } } if ( req -> type == MRT_DPRF || req -> type == MRT_IPRF || req -> demand_match_prefetch ) { STAT_EVENT ( req -> proc_id , MLC_PREF_REQ_HIT ) ; STAT_EVENT ( req -> proc_id , CORE_MLC_PREF_REQ_HIT ) ; } else if ( ( req -> type == MRT_DFETCH ) || ( req -> type == MRT_DSTORE ) || ( req -> type == MRT_IFETCH ) ) { STAT_EVENT ( req -> proc_id , MLC_DEMAND_HIT ) ; STAT_EVENT ( req -> proc_id , CORE_MLC_DEMAND_HIT ) ; } else { STAT_EVENT ( req -> proc_id , MLC_WB_HIT ) ; STAT_EVENT ( req -> proc_id , CORE_MLC_WB_HIT ) ; } data -> dirty |= ( req -> type == MRT_WB ) ; } if ( ( req -> type == MRT_DFETCH ) || ( req -> type == MRT_DSTORE ) || ( req -> type == MRT_IFETCH ) ) { STAT_EVENT ( req -> proc_id , MLC_HIT ) ; STAT_EVENT ( req -> proc_id , CORE_MLC_HIT ) ; STAT_EVENT ( req -> proc_id , MLC_HIT_ONPATH + req -> off_path ) ; if ( 0 && DEBUG_EXC_INSERTS ) { printf ( " \n " , hexstr64s ( req -> addr ) , Mem_Req_Type_str ( req -> type ) ) ; } } STAT_EVENT_ALL ( MLC_HIT_ALL ) ; STAT_EVENT_ALL ( MLC_HIT_ALL_ONPATH + req -> off_path ) ; if ( req -> off_path ) STAT_EVENT ( req -> proc_id , MLC_HIT_OFFPATH_IFETCH + MIN2 ( req -> type , 6 ) ) ; else STAT_EVENT ( req -> proc_id , MLC_HIT_ONPATH_IFETCH + MIN2 ( req -> type , 6 ) ) ; if ( MLC_WRITE_THROUGH && ( req -> type == MRT_WB ) ) { req -> state = MRS_L1_NEW ; req -> rdy_cycle = cycle_count + MLCQ_TO_L1Q_TRANSFER_LATENCY ; } else { req -> state = MRS_MLC_HIT_DONE ; mem_free_reqbuf ( req ) ; } mlc_queue_entry -> priority = Mem_Req_Priority_Offset [ MRT_MIN_PRIORITY ] ; return TRUE ; } else { return FALSE ; } }
mem_process_mlc_hit_access:
Returns TRUE if mlc access is complete and needs to be removed from mlc_queue
mem_process_mlc_hit_access : Returns TRUE if mlc access is complete and needs to be removed from mlc_queue
/* If done_func is not complete we will keep
                               accessing MLC until done_func returns TRUE */ /* not perfect mlc */ // prefetch hit // CMP Watch out RA // cmp IGNORE // writeback done /* Remove the entry from request buffer */ /* Set the priority so that this entry will be removed from the mlc_queue */