XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1.c
u32 XHdmiphy1_SetPrbsSel(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir,
        XHdmiphy1_PrbsPattern Pattern)
{
	u32 RegVal;
	u32 MaskVal;
	u32 RegOffset;
	u32 PrbsEnc = 0x0;
	u8 Id, Id0, Id1;

	/* Suppress Warning Messages */
	QuadId = QuadId;

	if (Dir == XHDMIPHY1_DIR_TX) {
		RegOffset = XHDMIPHY1_TX_CONTROL_REG;
		if (ChId == XHDMIPHY1_CHANNEL_ID_CHA) {
			MaskVal =  XHDMIPHY1_TX_CONTROL_TXPRBSSEL_ALL_MASK;
		}
		else {
			MaskVal = XHDMIPHY1_TX_CONTROL_TXPRBSSEL_MASK(ChId);
		}
		PrbsEnc = (u32) (((Pattern & 0x8) << 1) | (Pattern & 0x7));
	}
	else {
		RegOffset = XHDMIPHY1_RX_CONTROL_REG;
		if (ChId == XHDMIPHY1_CHANNEL_ID_CHA) {
			MaskVal = XHDMIPHY1_RX_CONTROL_RXPRBSSEL_ALL_MASK;
		}
		else {
			MaskVal = XHDMIPHY1_RX_CONTROL_RXPRBSSEL_MASK(ChId);
		}
		PrbsEnc = (u32) (Pattern & 0xF);
	}

	/* Read TX|RX Control Register */
	RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr, RegOffset);

	/* Mask out PRBS Register bits */
	RegVal &= ~MaskVal;

	XHdmiphy1_Ch2Ids(InstancePtr, ChId, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		RegVal |= PrbsEnc << ((Dir == XHDMIPHY1_DIR_TX) ?
					XHDMIPHY1_TX_CONTROL_TXPRBSSEL_SHIFT(Id) :
					XHDMIPHY1_RX_CONTROL_RXPRBSSEL_SHIFT(Id));
	}

	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function will set the TX/RXPRBSEL of the GT
*
* @param	InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID which to operate on.
* @param	Dir is an indicator for TX or RX.
* @param	Pattern is the pattern XHdmiphy1_PrbsPattern
*
* @return
*		- XST_SUCCESS.
*
* @note		None.
*
******************************************************************************/
This function will set the TX/RXPRBSEL of the GT
This function will set the TX / RXPRBSEL of the GT
u32 XHdmiphy1_SetPrbsSel(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir,
        XHdmiphy1_PrbsPattern Pattern)
{
	u32 RegVal;
	u32 MaskVal;
	u32 RegOffset;
	u32 PrbsEnc = 0x0;
	u8 Id, Id0, Id1;
	QuadId = QuadId;
	if (Dir == XHDMIPHY1_DIR_TX) {
		RegOffset = XHDMIPHY1_TX_CONTROL_REG;
		if (ChId == XHDMIPHY1_CHANNEL_ID_CHA) {
			MaskVal =  XHDMIPHY1_TX_CONTROL_TXPRBSSEL_ALL_MASK;
		}
		else {
			MaskVal = XHDMIPHY1_TX_CONTROL_TXPRBSSEL_MASK(ChId);
		}
		PrbsEnc = (u32) (((Pattern & 0x8) << 1) | (Pattern & 0x7));
	}
	else {
		RegOffset = XHDMIPHY1_RX_CONTROL_REG;
		if (ChId == XHDMIPHY1_CHANNEL_ID_CHA) {
			MaskVal = XHDMIPHY1_RX_CONTROL_RXPRBSSEL_ALL_MASK;
		}
		else {
			MaskVal = XHDMIPHY1_RX_CONTROL_RXPRBSSEL_MASK(ChId);
		}
		PrbsEnc = (u32) (Pattern & 0xF);
	}
	RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr, RegOffset);
	RegVal &= ~MaskVal;
	XHdmiphy1_Ch2Ids(InstancePtr, ChId, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		RegVal |= PrbsEnc << ((Dir == XHDMIPHY1_DIR_TX) ?
					XHDMIPHY1_TX_CONTROL_TXPRBSSEL_SHIFT(Id) :
					XHDMIPHY1_RX_CONTROL_RXPRBSSEL_SHIFT(Id));
	}
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal);
	return XST_SUCCESS;
}
u32 XHdmiphy1_SetPrbsSel ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId , XHdmiphy1_DirectionType Dir , XHdmiphy1_PrbsPattern Pattern ) { u32 RegVal ; u32 MaskVal ; u32 RegOffset ; u32 PrbsEnc = 0x0 ; u8 Id , Id0 , Id1 ; QuadId = QuadId ; if ( Dir == XHDMIPHY1_DIR_TX ) { RegOffset = XHDMIPHY1_TX_CONTROL_REG ; if ( ChId == XHDMIPHY1_CHANNEL_ID_CHA ) { MaskVal = XHDMIPHY1_TX_CONTROL_TXPRBSSEL_ALL_MASK ; } else { MaskVal = XHDMIPHY1_TX_CONTROL_TXPRBSSEL_MASK ( ChId ) ; } PrbsEnc = ( u32 ) ( ( ( Pattern & 0x8 ) << 1 ) | ( Pattern & 0x7 ) ) ; } else { RegOffset = XHDMIPHY1_RX_CONTROL_REG ; if ( ChId == XHDMIPHY1_CHANNEL_ID_CHA ) { MaskVal = XHDMIPHY1_RX_CONTROL_RXPRBSSEL_ALL_MASK ; } else { MaskVal = XHDMIPHY1_RX_CONTROL_RXPRBSSEL_MASK ( ChId ) ; } PrbsEnc = ( u32 ) ( Pattern & 0xF ) ; } RegVal = XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , RegOffset ) ; RegVal &= ~ MaskVal ; XHdmiphy1_Ch2Ids ( InstancePtr , ChId , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { RegVal |= PrbsEnc << ( ( Dir == XHDMIPHY1_DIR_TX ) ? XHDMIPHY1_TX_CONTROL_TXPRBSSEL_SHIFT ( Id ) : XHDMIPHY1_RX_CONTROL_RXPRBSSEL_SHIFT ( Id ) ) ; } XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffset , RegVal ) ; return XST_SUCCESS ; }
This function will set the TX/RXPRBSEL of the GT
This function will set the TX / RXPRBSEL of the GT
/* Suppress Warning Messages */ /* Read TX|RX Control Register */ /* Mask out PRBS Register bits */