XilinxProcessorIPLib/drivers/sysmonpsu/src/xsysmonpsu.c
u64 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
	u64 RegVal;
	UINTPTR EffectiveBaseAddress;

	/* Assert the arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));

	/* Calculate the effective baseaddress based on the Sysmon instance. */
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);

	/*
	 * Read the channel enable bits for all the channels from the ADC
	 * Channel Selection Register.
	 */
	RegVal = (u64)XSysmonPsu_ReadReg(EffectiveBaseAddress +
			XSYSMONPSU_SEQ_CH0_OFFSET) & XSYSMONPSU_SEQ_CH0_VALID_MASK;
	RegVal |= ((u64)XSysmonPsu_ReadReg(EffectiveBaseAddress +
			XSYSMONPSU_SEQ_CH1_OFFSET) & XSYSMONPSU_SEQ_CH1_VALID_MASK) <<
					XSM_SEQ_CH_SHIFT;
	RegVal |= ((u64)XSysmonPsu_ReadReg(EffectiveBaseAddress +
			XSYSMONPSU_SEQ_CH2_OFFSET) &
			XSYSMONPSU_SEQ_CH2_VALID_MASK) << XSM_SEQ_CH2_SHIFT;

	return RegVal;
}
/****************************************************************************/
/**
*
* This function gets the channel enable bits status from the ADC Channel
* Selection Sequencer Registers.
*
* @param	InstancePtr is a pointer to the XSysMonPsu instance.
* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
*       block or PL Sysmon block register region.
*
* @return	Gets the channel enable bits. Use XSYSMONPSU_SEQ_CH* defined in
*		xsysmonpsu_hw.h to interpret the Channel numbers. Bit masks of 1
*		are the channels that are enabled and bit mask of 0 are
*		the channels that are disabled.
*
* @return	None.
*
* @note		None.
*
*****************************************************************************/
This function gets the channel enable bits status from the ADC Channel
Selection Sequencer Registers.
This function gets the channel enable bits status from the ADC Channel Selection Sequencer Registers .
u64 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
	u64 RegVal;
	UINTPTR EffectiveBaseAddress;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);
	RegVal = (u64)XSysmonPsu_ReadReg(EffectiveBaseAddress +
			XSYSMONPSU_SEQ_CH0_OFFSET) & XSYSMONPSU_SEQ_CH0_VALID_MASK;
	RegVal |= ((u64)XSysmonPsu_ReadReg(EffectiveBaseAddress +
			XSYSMONPSU_SEQ_CH1_OFFSET) & XSYSMONPSU_SEQ_CH1_VALID_MASK) <<
					XSM_SEQ_CH_SHIFT;
	RegVal |= ((u64)XSysmonPsu_ReadReg(EffectiveBaseAddress +
			XSYSMONPSU_SEQ_CH2_OFFSET) &
			XSYSMONPSU_SEQ_CH2_VALID_MASK) << XSM_SEQ_CH2_SHIFT;
	return RegVal;
}
u64 XSysMonPsu_GetSeqChEnables ( XSysMonPsu * InstancePtr , u32 SysmonBlk ) { u64 RegVal ; UINTPTR EffectiveBaseAddress ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Xil_AssertNonvoid ( ( SysmonBlk == XSYSMON_PS ) || ( SysmonBlk == XSYSMON_PL ) ) ; EffectiveBaseAddress = XSysMonPsu_GetEffBaseAddress ( InstancePtr -> Config . BaseAddress , SysmonBlk ) ; RegVal = ( u64 ) XSysmonPsu_ReadReg ( EffectiveBaseAddress + XSYSMONPSU_SEQ_CH0_OFFSET ) & XSYSMONPSU_SEQ_CH0_VALID_MASK ; RegVal |= ( ( u64 ) XSysmonPsu_ReadReg ( EffectiveBaseAddress + XSYSMONPSU_SEQ_CH1_OFFSET ) & XSYSMONPSU_SEQ_CH1_VALID_MASK ) << XSM_SEQ_CH_SHIFT ; RegVal |= ( ( u64 ) XSysmonPsu_ReadReg ( EffectiveBaseAddress + XSYSMONPSU_SEQ_CH2_OFFSET ) & XSYSMONPSU_SEQ_CH2_VALID_MASK ) << XSM_SEQ_CH2_SHIFT ; return RegVal ; }
This function gets the channel enable bits status from the ADC Channel
Selection Sequencer Registers.
This function gets the channel enable bits status from the ADC Channel Selection Sequencer Registers .
/* Assert the arguments. */ /* Calculate the effective baseaddress based on the Sysmon instance. */ /*
	 * Read the channel enable bits for all the channels from the ADC
	 * Channel Selection Register.
	 */