XilinxProcessorIPLib/drivers/aienginev2/src/stream_switch/xaie_ss_aieml.c
AieRC _XAieMl_MemTile_StrmSwCheckPortValidity(StrmSwPortType Slave,
		u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum)
{
	AieRC RC = XAIE_OK;

	switch(Slave) {
	case TRACE:
		if(Master == SOUTH || (Master == DMA && MstrPortNum == 5U)) {
			break;
		}
		RC = XAIE_ERR_STREAM_PORT;
		break;
	case DMA:
		if((Master == DMA && SlvPortNum == MstrPortNum) ||
				Master != DMA){
			break;
		}
		RC = XAIE_ERR_STREAM_PORT;
		break;
	case CTRL:
		if((Master == DMA && MstrPortNum != 5U) || Master == CTRL) {
			RC = XAIE_ERR_STREAM_PORT;
		}
		break;
	case SOUTH:
	case NORTH:
		if((Master == SOUTH || Master == NORTH) &&
			SlvPortNum != MstrPortNum) {
			RC = XAIE_ERR_STREAM_PORT;
		}
		break;
	default:
		RC = XAIE_ERR_STREAM_PORT;
		break;
	}

	return RC;
}
/**
*
* This api verifies if a stream switch connection exists within the ports.
* Less valid ports exist in the MemTile, but certain combinations exist.
* The method assumes both ports exist, and the relevant tile is an MEM-Tile.
*
* @param	Slave: The type of the slave port.
* @param	SlvPortNum: The number of the slave port.
* @param	Master: The type of the master port.
* @param	MstrPortNum: The number of the master port.
*
* @return	XAIE_OK if a stream switch connection is possible.
* 		XAIE_ERR_STREAM_PORT if the connection isn't possible.
*
* @note		Internal API for AIE-ML. This API shouldn't be called directly.
* 		It is invoked using a function pointer within the Stream
* 		Module data structure.
*
*****************************************************************************/
This api verifies if a stream switch connection exists within the ports.
Less valid ports exist in the MemTile, but certain combinations exist.
The method assumes both ports exist, and the relevant tile is an MEM-Tile.
This api verifies if a stream switch connection exists within the ports . Less valid ports exist in the MemTile but certain combinations exist . The method assumes both ports exist and the relevant tile is an MEM - Tile .
AieRC _XAieMl_MemTile_StrmSwCheckPortValidity(StrmSwPortType Slave,
		u8 SlvPortNum, StrmSwPortType Master, u8 MstrPortNum)
{
	AieRC RC = XAIE_OK;
	switch(Slave) {
	case TRACE:
		if(Master == SOUTH || (Master == DMA && MstrPortNum == 5U)) {
			break;
		}
		RC = XAIE_ERR_STREAM_PORT;
		break;
	case DMA:
		if((Master == DMA && SlvPortNum == MstrPortNum) ||
				Master != DMA){
			break;
		}
		RC = XAIE_ERR_STREAM_PORT;
		break;
	case CTRL:
		if((Master == DMA && MstrPortNum != 5U) || Master == CTRL) {
			RC = XAIE_ERR_STREAM_PORT;
		}
		break;
	case SOUTH:
	case NORTH:
		if((Master == SOUTH || Master == NORTH) &&
			SlvPortNum != MstrPortNum) {
			RC = XAIE_ERR_STREAM_PORT;
		}
		break;
	default:
		RC = XAIE_ERR_STREAM_PORT;
		break;
	}
	return RC;
}
AieRC _XAieMl_MemTile_StrmSwCheckPortValidity ( StrmSwPortType Slave , u8 SlvPortNum , StrmSwPortType Master , u8 MstrPortNum ) { AieRC RC = XAIE_OK ; switch ( Slave ) { case TRACE : if ( Master == SOUTH || ( Master == DMA && MstrPortNum == 5U ) ) { break ; } RC = XAIE_ERR_STREAM_PORT ; break ; case DMA : if ( ( Master == DMA && SlvPortNum == MstrPortNum ) || Master != DMA ) { break ; } RC = XAIE_ERR_STREAM_PORT ; break ; case CTRL : if ( ( Master == DMA && MstrPortNum != 5U ) || Master == CTRL ) { RC = XAIE_ERR_STREAM_PORT ; } break ; case SOUTH : case NORTH : if ( ( Master == SOUTH || Master == NORTH ) && SlvPortNum != MstrPortNum ) { RC = XAIE_ERR_STREAM_PORT ; } break ; default : RC = XAIE_ERR_STREAM_PORT ; break ; } return RC ; }
This api verifies if a stream switch connection exists within the ports.
This api verifies if a stream switch connection exists within the ports .