src/dpdk/drivers/net/i40e/i40e_ethdev.c
static void
i40e_pf_global_rss_reset(struct i40e_pf *pf)
{
	struct i40e_hw *hw = I40E_PF_TO_HW(pf);
	uint32_t reg, reg_val;
	int i;

	/* Reset global RSS function sets */
	reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
	if (!(reg_val & I40E_GLQF_CTL_HTOEP_MASK)) {
		reg_val |= I40E_GLQF_CTL_HTOEP_MASK;
		i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg_val);
	}

	for (i = 0; i <= I40E_FILTER_PCTYPE_L2_PAYLOAD; i++) {
		uint64_t inset;
		int j, pctype;

		if (hw->mac.type == I40E_MAC_X722)
			pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(i));
		else
			pctype = i;

		/* Reset pctype insets */
		inset = i40e_get_default_input_set(i);
		if (inset) {
			pf->hash_input_set[pctype] = inset;
			inset = i40e_translate_input_set_reg(hw->mac.type,
							     inset);

			reg = I40E_GLQF_HASH_INSET(0, pctype);
			i40e_check_write_global_reg(hw, reg, (uint32_t)inset);
			reg = I40E_GLQF_HASH_INSET(1, pctype);
			i40e_check_write_global_reg(hw, reg,
						    (uint32_t)(inset >> 32));

			/* Clear unused mask registers of the pctype */
			for (j = 0; j < I40E_INSET_MASK_NUM_REG; j++) {
				reg = I40E_GLQF_HASH_MSK(j, pctype);
				i40e_check_write_global_reg(hw, reg, 0);
			}
		}

		/* Reset pctype symmetric sets */
		reg = I40E_GLQF_HSYM(pctype);
		reg_val = i40e_read_rx_ctl(hw, reg);
		if (reg_val & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
			reg_val &= ~I40E_GLQF_HSYM_SYMH_ENA_MASK;
			i40e_write_global_rx_ctl(hw, reg, reg_val);
		}
	}
	I40E_WRITE_FLUSH(hw);
}
/* Reset the global configure of hash function and input sets */
Reset the global configure of hash function and input sets
Reset the global configure of hash function and input sets
static void
i40e_pf_global_rss_reset(struct i40e_pf *pf)
{
	struct i40e_hw *hw = I40E_PF_TO_HW(pf);
	uint32_t reg, reg_val;
	int i;
	reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
	if (!(reg_val & I40E_GLQF_CTL_HTOEP_MASK)) {
		reg_val |= I40E_GLQF_CTL_HTOEP_MASK;
		i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg_val);
	}
	for (i = 0; i <= I40E_FILTER_PCTYPE_L2_PAYLOAD; i++) {
		uint64_t inset;
		int j, pctype;
		if (hw->mac.type == I40E_MAC_X722)
			pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(i));
		else
			pctype = i;
		inset = i40e_get_default_input_set(i);
		if (inset) {
			pf->hash_input_set[pctype] = inset;
			inset = i40e_translate_input_set_reg(hw->mac.type,
							     inset);
			reg = I40E_GLQF_HASH_INSET(0, pctype);
			i40e_check_write_global_reg(hw, reg, (uint32_t)inset);
			reg = I40E_GLQF_HASH_INSET(1, pctype);
			i40e_check_write_global_reg(hw, reg,
						    (uint32_t)(inset >> 32));
			for (j = 0; j < I40E_INSET_MASK_NUM_REG; j++) {
				reg = I40E_GLQF_HASH_MSK(j, pctype);
				i40e_check_write_global_reg(hw, reg, 0);
			}
		}
		reg = I40E_GLQF_HSYM(pctype);
		reg_val = i40e_read_rx_ctl(hw, reg);
		if (reg_val & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
			reg_val &= ~I40E_GLQF_HSYM_SYMH_ENA_MASK;
			i40e_write_global_rx_ctl(hw, reg, reg_val);
		}
	}
	I40E_WRITE_FLUSH(hw);
}
static void i40e_pf_global_rss_reset ( struct i40e_pf * pf ) { struct i40e_hw * hw = I40E_PF_TO_HW ( pf ) ; uint32_t reg , reg_val ; int i ; reg_val = i40e_read_rx_ctl ( hw , I40E_GLQF_CTL ) ; if ( ! ( reg_val & I40E_GLQF_CTL_HTOEP_MASK ) ) { reg_val |= I40E_GLQF_CTL_HTOEP_MASK ; i40e_write_global_rx_ctl ( hw , I40E_GLQF_CTL , reg_val ) ; } for ( i = 0 ; i <= I40E_FILTER_PCTYPE_L2_PAYLOAD ; i ++ ) { uint64_t inset ; int j , pctype ; if ( hw -> mac . type == I40E_MAC_X722 ) pctype = i40e_read_rx_ctl ( hw , I40E_GLQF_FD_PCTYPES ( i ) ) ; else pctype = i ; inset = i40e_get_default_input_set ( i ) ; if ( inset ) { pf -> hash_input_set [ pctype ] = inset ; inset = i40e_translate_input_set_reg ( hw -> mac . type , inset ) ; reg = I40E_GLQF_HASH_INSET ( 0 , pctype ) ; i40e_check_write_global_reg ( hw , reg , ( uint32_t ) inset ) ; reg = I40E_GLQF_HASH_INSET ( 1 , pctype ) ; i40e_check_write_global_reg ( hw , reg , ( uint32_t ) ( inset >> 32 ) ) ; for ( j = 0 ; j < I40E_INSET_MASK_NUM_REG ; j ++ ) { reg = I40E_GLQF_HASH_MSK ( j , pctype ) ; i40e_check_write_global_reg ( hw , reg , 0 ) ; } } reg = I40E_GLQF_HSYM ( pctype ) ; reg_val = i40e_read_rx_ctl ( hw , reg ) ; if ( reg_val & I40E_GLQF_HSYM_SYMH_ENA_MASK ) { reg_val &= ~ I40E_GLQF_HSYM_SYMH_ENA_MASK ; i40e_write_global_rx_ctl ( hw , reg , reg_val ) ; } } I40E_WRITE_FLUSH ( hw ) ; }
Reset the global configure of hash function and input sets
Reset the global configure of hash function and input sets
/* Reset global RSS function sets */ /* Reset pctype insets */ /* Clear unused mask registers of the pctype */ /* Reset pctype symmetric sets */