XilinxProcessorIPLib/drivers/dpdma/src/xdpdma.c
static int XDpDma_ConfigChannelState(XDpDma *InstancePtr, u8 ChannelNum,
				     XDpDma_ChannelState Enable)
{
	u32 Mask = 0;
	u32 RegVal = 0;
	/* Verify arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1);
	Xil_AssertNonvoid(Enable <= XDPDMA_PAUSE);

	Mask = XDPDMA_CH_CNTL_EN_MASK | XDPDMA_CH_CNTL_PAUSE_MASK;
	switch(Enable) {
		case XDPDMA_ENABLE:
			RegVal = XDPDMA_CH_CNTL_EN_MASK;
			break;
		case XDPDMA_DISABLE:
			if (XDpDma_ConfigChannelState(InstancePtr, ChannelNum,
						      XDPDMA_PAUSE) ==
						      XST_FAILURE) {
				return (int)XST_FAILURE;
			}
			if (XDpDma_WaitPendingTransaction(InstancePtr,
							  ChannelNum) ==
							  XST_FAILURE) {
				return (int)XST_FAILURE;
			}

			RegVal = (u32)XDPDMA_DISABLE;
			Mask = XDPDMA_CH_CNTL_EN_MASK;
			break;
		case XDPDMA_IDLE:
			if (XDpDma_ConfigChannelState(InstancePtr, ChannelNum,
						      XDPDMA_DISABLE) ==
						      XST_FAILURE) {
				return (int)XST_FAILURE;
			}

			RegVal = 0U;
			break;
		case XDPDMA_PAUSE:
			RegVal = (u32)XDPDMA_PAUSE;
			break;
		default:
			/* This will never occur */
			break;
	}
	XDpDma_ReadModifyWrite(InstancePtr->Config.BaseAddr,
			       XDPDMA_CH0_CNTL + XDPDMA_CH_OFFSET *
			       (u32)ChannelNum, RegVal, Mask);
	return (int)XST_SUCCESS;
}
/*************************************************************************/
/**
 *
 * This function controls the hardware channels of the DPDMA.
 *
 *
 * @param    InstancePtr is a pointer to the driver instance.
 * @param    ChannelNum is the physical channel number of the DPDMA.
 * @param    ChannelState is an enum of type XDpDma_ChannelState.
 *
 * @return   XST_SUCCESS when the mentioned channel is enabled successfully.
 *	     XST_FAILURE when the mentioned channel fails to be enabled.
 *
 * @note     None.
 *
 * **************************************************************************/
This function controls the hardware channels of the DPDMA.
@param    InstancePtr is a pointer to the driver instance.
@param    ChannelNum is the physical channel number of the DPDMA.
@param    ChannelState is an enum of type XDpDma_ChannelState.

@return   XST_SUCCESS when the mentioned channel is enabled successfully.
XST_FAILURE when the mentioned channel fails to be enabled.

@note     None.
This function controls the hardware channels of the DPDMA . @param InstancePtr is a pointer to the driver instance . @param ChannelNum is the physical channel number of the DPDMA . @param ChannelState is an enum of type XDpDma_ChannelState . @return XST_SUCCESS when the mentioned channel is enabled successfully . XST_FAILURE when the mentioned channel fails to be enabled . @note None .
static int XDpDma_ConfigChannelState(XDpDma *InstancePtr, u8 ChannelNum,
				     XDpDma_ChannelState Enable)
{
	u32 Mask = 0;
	u32 RegVal = 0;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1);
	Xil_AssertNonvoid(Enable <= XDPDMA_PAUSE);
	Mask = XDPDMA_CH_CNTL_EN_MASK | XDPDMA_CH_CNTL_PAUSE_MASK;
	switch(Enable) {
		case XDPDMA_ENABLE:
			RegVal = XDPDMA_CH_CNTL_EN_MASK;
			break;
		case XDPDMA_DISABLE:
			if (XDpDma_ConfigChannelState(InstancePtr, ChannelNum,
						      XDPDMA_PAUSE) ==
						      XST_FAILURE) {
				return (int)XST_FAILURE;
			}
			if (XDpDma_WaitPendingTransaction(InstancePtr,
							  ChannelNum) ==
							  XST_FAILURE) {
				return (int)XST_FAILURE;
			}
			RegVal = (u32)XDPDMA_DISABLE;
			Mask = XDPDMA_CH_CNTL_EN_MASK;
			break;
		case XDPDMA_IDLE:
			if (XDpDma_ConfigChannelState(InstancePtr, ChannelNum,
						      XDPDMA_DISABLE) ==
						      XST_FAILURE) {
				return (int)XST_FAILURE;
			}
			RegVal = 0U;
			break;
		case XDPDMA_PAUSE:
			RegVal = (u32)XDPDMA_PAUSE;
			break;
		default:
			break;
	}
	XDpDma_ReadModifyWrite(InstancePtr->Config.BaseAddr,
			       XDPDMA_CH0_CNTL + XDPDMA_CH_OFFSET *
			       (u32)ChannelNum, RegVal, Mask);
	return (int)XST_SUCCESS;
}
static int XDpDma_ConfigChannelState ( XDpDma * InstancePtr , u8 ChannelNum , XDpDma_ChannelState Enable ) { u32 Mask = 0 ; u32 RegVal = 0 ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( ChannelNum <= XDPDMA_AUDIO_CHANNEL1 ) ; Xil_AssertNonvoid ( Enable <= XDPDMA_PAUSE ) ; Mask = XDPDMA_CH_CNTL_EN_MASK | XDPDMA_CH_CNTL_PAUSE_MASK ; switch ( Enable ) { case XDPDMA_ENABLE : RegVal = XDPDMA_CH_CNTL_EN_MASK ; break ; case XDPDMA_DISABLE : if ( XDpDma_ConfigChannelState ( InstancePtr , ChannelNum , XDPDMA_PAUSE ) == XST_FAILURE ) { return ( int ) XST_FAILURE ; } if ( XDpDma_WaitPendingTransaction ( InstancePtr , ChannelNum ) == XST_FAILURE ) { return ( int ) XST_FAILURE ; } RegVal = ( u32 ) XDPDMA_DISABLE ; Mask = XDPDMA_CH_CNTL_EN_MASK ; break ; case XDPDMA_IDLE : if ( XDpDma_ConfigChannelState ( InstancePtr , ChannelNum , XDPDMA_DISABLE ) == XST_FAILURE ) { return ( int ) XST_FAILURE ; } RegVal = 0U ; break ; case XDPDMA_PAUSE : RegVal = ( u32 ) XDPDMA_PAUSE ; break ; default : break ; } XDpDma_ReadModifyWrite ( InstancePtr -> Config . BaseAddr , XDPDMA_CH0_CNTL + XDPDMA_CH_OFFSET * ( u32 ) ChannelNum , RegVal , Mask ) ; return ( int ) XST_SUCCESS ; }
This function controls the hardware channels of the DPDMA.
This function controls the hardware channels of the DPDMA .
/* Verify arguments. */ /* This will never occur */