lib/bsp/standalone/src/arm/ARMv8/32bit/xil_cache.c
void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
{
	const u32 cacheline = 64U;
	u32 end;
	u32 tempadr = adr;
	u32 tempend;
	u32 currmask;

	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);

	if (len != 0x00000000U) {
		end = tempadr + len;
		tempend = end;
		tempadr &= ~(cacheline - 0x00000001U);

		/* Select cache Level 0 I-cache in CSSR */
		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x1);
		while (tempadr < tempend) {
			/*Invalidate I Cache line*/
			mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, adr & (~0x3F));

			tempadr += cacheline;
		}
	}
/* Wait for invalidate to complete */
	dsb();
	mtcpsr(currmask);
}
/****************************************************************************/
/**
 * @brief	Invalidate the instruction cache for the given address range.
 *		If the instructions specified by the address range are cached
 *		by the instrunction cache, the cachelines containing those
 *		instructions are invalidated.
 *
 * @param	adr: 32bit start address of the range to be invalidated.
 * @param	len: Length of the range to be invalidated in bytes.
 *
 * @return	None.
 *
 ****************************************************************************/
@brief       Invalidate the instruction cache for the given address range.
If the instructions specified by the address range are cached
by the instrunction cache, the cachelines containing those
instructions are invalidated.

@param       adr: 32bit start address of the range to be invalidated.
@param       len: Length of the range to be invalidated in bytes.

@return      None.
@brief Invalidate the instruction cache for the given address range . If the instructions specified by the address range are cached by the instrunction cache the cachelines containing those instructions are invalidated . @param adr : 32bit start address of the range to be invalidated . @param len : Length of the range to be invalidated in bytes . @return None .
void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
{
	const u32 cacheline = 64U;
	u32 end;
	u32 tempadr = adr;
	u32 tempend;
	u32 currmask;
	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);
	if (len != 0x00000000U) {
		end = tempadr + len;
		tempend = end;
		tempadr &= ~(cacheline - 0x00000001U);
		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x1);
		while (tempadr < tempend) {
			mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, adr & (~0x3F));
			tempadr += cacheline;
		}
	}
	dsb();
	mtcpsr(currmask);
}
void Xil_ICacheInvalidateRange ( INTPTR adr , u32 len ) { const u32 cacheline = 64U ; u32 end ; u32 tempadr = adr ; u32 tempend ; u32 currmask ; currmask = mfcpsr ( ) ; mtcpsr ( currmask | IRQ_FIQ_MASK ) ; if ( len != 0x00000000U ) { end = tempadr + len ; tempend = end ; tempadr &= ~ ( cacheline - 0x00000001U ) ; mtcp ( XREG_CP15_CACHE_SIZE_SEL , 0x1 ) ; while ( tempadr < tempend ) { mtcp ( XREG_CP15_INVAL_IC_LINE_MVA_POU , adr & ( ~ 0x3F ) ) ; tempadr += cacheline ; } } dsb ( ) ; mtcpsr ( currmask ) ; }
@brief       Invalidate the instruction cache for the given address range.
@brief Invalidate the instruction cache for the given address range .
/* Select cache Level 0 I-cache in CSSR */ /*Invalidate I Cache line*/ /* Wait for invalidate to complete */