src/dpdk/drivers/net/e1000/igb_rxtx.c
static inline void
igbe_set_xmit_ctx(struct igb_tx_queue* txq,
		volatile struct e1000_adv_tx_context_desc *ctx_txd,
		uint64_t ol_flags, union igb_tx_offload tx_offload)
{
	uint32_t type_tucmd_mlhl;
	uint32_t mss_l4len_idx;
	uint32_t ctx_idx, ctx_curr;
	uint32_t vlan_macip_lens;
	union igb_tx_offload tx_offload_mask;

	ctx_curr = txq->ctx_curr;
	ctx_idx = ctx_curr + txq->ctx_start;

	tx_offload_mask.data = 0;
	type_tucmd_mlhl = 0;

	/* Specify which HW CTX to upload. */
	mss_l4len_idx = (ctx_idx << E1000_ADVTXD_IDX_SHIFT);

	if (ol_flags & PKT_TX_VLAN_PKT)
		tx_offload_mask.data |= TX_VLAN_CMP_MASK;

	/* check if TCP segmentation required for this packet */
	if (ol_flags & PKT_TX_TCP_SEG) {
		/* implies IP cksum in IPv4 */
		if (ol_flags & PKT_TX_IP_CKSUM)
			type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4 |
				E1000_ADVTXD_TUCMD_L4T_TCP |
				E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
		else
			type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV6 |
				E1000_ADVTXD_TUCMD_L4T_TCP |
				E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;

		tx_offload_mask.data |= TX_TSO_CMP_MASK;
		mss_l4len_idx |= tx_offload.tso_segsz << E1000_ADVTXD_MSS_SHIFT;
		mss_l4len_idx |= tx_offload.l4_len << E1000_ADVTXD_L4LEN_SHIFT;
	} else { /* no TSO, check if hardware checksum is needed */
		if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
			tx_offload_mask.data |= TX_MACIP_LEN_CMP_MASK;

		if (ol_flags & PKT_TX_IP_CKSUM)
			type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4;

		switch (ol_flags & PKT_TX_L4_MASK) {
		case PKT_TX_UDP_CKSUM:
			type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP |
				E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
			mss_l4len_idx |= sizeof(struct rte_udp_hdr)
				<< E1000_ADVTXD_L4LEN_SHIFT;
			break;
		case PKT_TX_TCP_CKSUM:
			type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP |
				E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
			mss_l4len_idx |= sizeof(struct rte_tcp_hdr)
				<< E1000_ADVTXD_L4LEN_SHIFT;
			break;
		case PKT_TX_SCTP_CKSUM:
			type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP |
				E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
			mss_l4len_idx |= sizeof(struct rte_sctp_hdr)
				<< E1000_ADVTXD_L4LEN_SHIFT;
			break;
		default:
			type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV |
				E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
			break;
		}
	}

	txq->ctx_cache[ctx_curr].flags = ol_flags;
	txq->ctx_cache[ctx_curr].tx_offload.data =
		tx_offload_mask.data & tx_offload.data;
	txq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;

	ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
	vlan_macip_lens = (uint32_t)tx_offload.data;
	ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
	ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
	ctx_txd->u.seqnum_seed = 0;
}
/*
 * Advanced context descriptor are almost same between igb/ixgbe
 * This is a separate function, looking for optimization opportunity here
 * Rework required to go with the pre-defined values.
 */
Advanced context descriptor are almost same between igb/ixgbe
This is a separate function, looking for optimization opportunity here
Rework required to go with the pre-defined values.
Advanced context descriptor are almost same between igb / ixgbe This is a separate function looking for optimization opportunity here Rework required to go with the pre - defined values .
static inline void
igbe_set_xmit_ctx(struct igb_tx_queue* txq,
		volatile struct e1000_adv_tx_context_desc *ctx_txd,
		uint64_t ol_flags, union igb_tx_offload tx_offload)
{
	uint32_t type_tucmd_mlhl;
	uint32_t mss_l4len_idx;
	uint32_t ctx_idx, ctx_curr;
	uint32_t vlan_macip_lens;
	union igb_tx_offload tx_offload_mask;
	ctx_curr = txq->ctx_curr;
	ctx_idx = ctx_curr + txq->ctx_start;
	tx_offload_mask.data = 0;
	type_tucmd_mlhl = 0;
	mss_l4len_idx = (ctx_idx << E1000_ADVTXD_IDX_SHIFT);
	if (ol_flags & PKT_TX_VLAN_PKT)
		tx_offload_mask.data |= TX_VLAN_CMP_MASK;
	if (ol_flags & PKT_TX_TCP_SEG) {
		if (ol_flags & PKT_TX_IP_CKSUM)
			type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4 |
				E1000_ADVTXD_TUCMD_L4T_TCP |
				E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
		else
			type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV6 |
				E1000_ADVTXD_TUCMD_L4T_TCP |
				E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
		tx_offload_mask.data |= TX_TSO_CMP_MASK;
		mss_l4len_idx |= tx_offload.tso_segsz << E1000_ADVTXD_MSS_SHIFT;
		mss_l4len_idx |= tx_offload.l4_len << E1000_ADVTXD_L4LEN_SHIFT;
	} else { 
		if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
			tx_offload_mask.data |= TX_MACIP_LEN_CMP_MASK;
		if (ol_flags & PKT_TX_IP_CKSUM)
			type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4;
		switch (ol_flags & PKT_TX_L4_MASK) {
		case PKT_TX_UDP_CKSUM:
			type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP |
				E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
			mss_l4len_idx |= sizeof(struct rte_udp_hdr)
				<< E1000_ADVTXD_L4LEN_SHIFT;
			break;
		case PKT_TX_TCP_CKSUM:
			type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP |
				E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
			mss_l4len_idx |= sizeof(struct rte_tcp_hdr)
				<< E1000_ADVTXD_L4LEN_SHIFT;
			break;
		case PKT_TX_SCTP_CKSUM:
			type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP |
				E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
			mss_l4len_idx |= sizeof(struct rte_sctp_hdr)
				<< E1000_ADVTXD_L4LEN_SHIFT;
			break;
		default:
			type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV |
				E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
			break;
		}
	}
	txq->ctx_cache[ctx_curr].flags = ol_flags;
	txq->ctx_cache[ctx_curr].tx_offload.data =
		tx_offload_mask.data & tx_offload.data;
	txq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;
	ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
	vlan_macip_lens = (uint32_t)tx_offload.data;
	ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
	ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
	ctx_txd->u.seqnum_seed = 0;
}
static inline void igbe_set_xmit_ctx ( struct igb_tx_queue * txq , volatile struct e1000_adv_tx_context_desc * ctx_txd , uint64_t ol_flags , union igb_tx_offload tx_offload ) { uint32_t type_tucmd_mlhl ; uint32_t mss_l4len_idx ; uint32_t ctx_idx , ctx_curr ; uint32_t vlan_macip_lens ; union igb_tx_offload tx_offload_mask ; ctx_curr = txq -> ctx_curr ; ctx_idx = ctx_curr + txq -> ctx_start ; tx_offload_mask . data = 0 ; type_tucmd_mlhl = 0 ; mss_l4len_idx = ( ctx_idx << E1000_ADVTXD_IDX_SHIFT ) ; if ( ol_flags & PKT_TX_VLAN_PKT ) tx_offload_mask . data |= TX_VLAN_CMP_MASK ; if ( ol_flags & PKT_TX_TCP_SEG ) { if ( ol_flags & PKT_TX_IP_CKSUM ) type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4 | E1000_ADVTXD_TUCMD_L4T_TCP | E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT ; else type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV6 | E1000_ADVTXD_TUCMD_L4T_TCP | E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT ; tx_offload_mask . data |= TX_TSO_CMP_MASK ; mss_l4len_idx |= tx_offload . tso_segsz << E1000_ADVTXD_MSS_SHIFT ; mss_l4len_idx |= tx_offload . l4_len << E1000_ADVTXD_L4LEN_SHIFT ; } else { if ( ol_flags & ( PKT_TX_IP_CKSUM | PKT_TX_L4_MASK ) ) tx_offload_mask . data |= TX_MACIP_LEN_CMP_MASK ; if ( ol_flags & PKT_TX_IP_CKSUM ) type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4 ; switch ( ol_flags & PKT_TX_L4_MASK ) { case PKT_TX_UDP_CKSUM : type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP | E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT ; mss_l4len_idx |= sizeof ( struct rte_udp_hdr ) << E1000_ADVTXD_L4LEN_SHIFT ; break ; case PKT_TX_TCP_CKSUM : type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP | E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT ; mss_l4len_idx |= sizeof ( struct rte_tcp_hdr ) << E1000_ADVTXD_L4LEN_SHIFT ; break ; case PKT_TX_SCTP_CKSUM : type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP | E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT ; mss_l4len_idx |= sizeof ( struct rte_sctp_hdr ) << E1000_ADVTXD_L4LEN_SHIFT ; break ; default : type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV | E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT ; break ; } } txq -> ctx_cache [ ctx_curr ] . flags = ol_flags ; txq -> ctx_cache [ ctx_curr ] . tx_offload . data = tx_offload_mask . data & tx_offload . data ; txq -> ctx_cache [ ctx_curr ] . tx_offload_mask = tx_offload_mask ; ctx_txd -> type_tucmd_mlhl = rte_cpu_to_le_32 ( type_tucmd_mlhl ) ; vlan_macip_lens = ( uint32_t ) tx_offload . data ; ctx_txd -> vlan_macip_lens = rte_cpu_to_le_32 ( vlan_macip_lens ) ; ctx_txd -> mss_l4len_idx = rte_cpu_to_le_32 ( mss_l4len_idx ) ; ctx_txd -> u . seqnum_seed = 0 ; }
Advanced context descriptor are almost same between igb/ixgbe
 This is a separate function, looking for optimization opportunity here
 Rework required to go with the pre-defined values.
Advanced context descriptor are almost same between igb / ixgbe This is a separate function looking for optimization opportunity here Rework required to go with the pre - defined values .
/* Specify which HW CTX to upload. */ /* check if TCP segmentation required for this packet */ /* implies IP cksum in IPv4 */ /* no TSO, check if hardware checksum is needed */