sys/dev/netif/ath/hal/ath_hal/ar5416/ar5416_reset.c
HAL_BOOL
ar5416SetTransmitPower(struct ath_hal *ah,
	const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
{
#define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))

    MODAL_EEP_HEADER	*pModal;
    struct ath_hal_5212 *ahp = AH5212(ah);
    int16_t		ratesArray[Ar5416RateSize];
    int16_t		txPowerIndexOffset = 0;
    uint8_t		ht40PowerIncForPdadc = 2;	
    int			i;
    
    uint16_t		cfgCtl;
    uint16_t		powerLimit;
    uint16_t		twiceAntennaReduction;
    uint16_t		twiceMaxRegulatoryPower;
    int16_t		maxPower;
    HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
    struct ar5416eeprom	*pEepData = &ee->ee_base;

    HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);

    /* Setup info for the actual eeprom */
    OS_MEMZERO(ratesArray, sizeof(ratesArray));
    cfgCtl = ath_hal_getctl(ah, chan);
    powerLimit = chan->ic_maxregpower * 2;
    twiceAntennaReduction = chan->ic_maxantgain;
    twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 
    pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
    HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
	__func__,chan->ic_freq, cfgCtl );      
  
    if (IS_EEP_MINOR_V2(ah)) {
        ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
    }
 
    if (!ar5416SetPowerPerRateTable(ah, pEepData,  chan,
                                    &ratesArray[0],cfgCtl,
                                    twiceAntennaReduction,
				    twiceMaxRegulatoryPower, powerLimit)) {
        HALDEBUG(ah, HAL_DEBUG_ANY,
	    "%s: unable to set tx power per rate table\n", __func__);
        return AH_FALSE;
    }

    if (!ar5416SetPowerCalTable(ah,  pEepData, chan, &txPowerIndexOffset)) {
        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
	    __func__);
        return AH_FALSE;
    }
  
    maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]);

    if (IEEE80211_IS_CHAN_2GHZ(chan)) {
        maxPower = AH_MAX(maxPower, ratesArray[rate1l]);
    }

    if (IEEE80211_IS_CHAN_HT40(chan)) {
        maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]);
    }

    ahp->ah_tx6PowerInHalfDbm = maxPower;   
    AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;
    ahp->ah_txPowerIndexOffset = txPowerIndexOffset;

    /*
     * txPowerIndexOffset is set by the SetPowerTable() call -
     *  adjust the rate table (0 offset if rates EEPROM not loaded)
     */
    for (i = 0; i < NELEM(ratesArray); i++) {
        ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
        if (ratesArray[i] > AR5416_MAX_RATE_POWER)
            ratesArray[i] = AR5416_MAX_RATE_POWER;
    }

#ifdef AH_EEPROM_DUMP
    ar5416PrintPowerPerRate(ah, ratesArray);
#endif

    /* Write the OFDM power per rate set */
    OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
        POW_SM(ratesArray[rate18mb], 24)
          | POW_SM(ratesArray[rate12mb], 16)
          | POW_SM(ratesArray[rate9mb], 8)
          | POW_SM(ratesArray[rate6mb], 0)
    );
    OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
        POW_SM(ratesArray[rate54mb], 24)
          | POW_SM(ratesArray[rate48mb], 16)
          | POW_SM(ratesArray[rate36mb], 8)
          | POW_SM(ratesArray[rate24mb], 0)
    );

    if (IEEE80211_IS_CHAN_2GHZ(chan)) {
        /* Write the CCK power per rate set */
        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
            POW_SM(ratesArray[rate2s], 24)
              | POW_SM(ratesArray[rate2l],  16)
              | POW_SM(ratesArray[rateXr],  8) /* XR target power */
              | POW_SM(ratesArray[rate1l],   0)
        );
        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
            POW_SM(ratesArray[rate11s], 24)
              | POW_SM(ratesArray[rate11l], 16)
              | POW_SM(ratesArray[rate5_5s], 8)
              | POW_SM(ratesArray[rate5_5l], 0)
        );
    HALDEBUG(ah, HAL_DEBUG_RESET,
	"%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n",
	    __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3),
	    OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 
    }

    /* Write the HT20 power per rate set */
    OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
        POW_SM(ratesArray[rateHt20_3], 24)
          | POW_SM(ratesArray[rateHt20_2], 16)
          | POW_SM(ratesArray[rateHt20_1], 8)
          | POW_SM(ratesArray[rateHt20_0], 0)
    );
    OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
        POW_SM(ratesArray[rateHt20_7], 24)
          | POW_SM(ratesArray[rateHt20_6], 16)
          | POW_SM(ratesArray[rateHt20_5], 8)
          | POW_SM(ratesArray[rateHt20_4], 0)
    );

    if (IEEE80211_IS_CHAN_HT40(chan)) {
        /* Write the HT40 power per rate set */
	/* Correct PAR difference between HT40 and HT20/LEGACY */
        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
            POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24)
              | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16)
              | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8)
              | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0)
        );
        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
            POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24)
              | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16)
              | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8)
              | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0)
        );
        /* Write the Dup/Ext 40 power per rate set */
        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
            POW_SM(ratesArray[rateExtOfdm], 24)
              | POW_SM(ratesArray[rateExtCck], 16)
              | POW_SM(ratesArray[rateDupOfdm], 8)
              | POW_SM(ratesArray[rateDupCck], 0)
        );
    }

    /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */
    OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
        POW_SM(pModal->pwrDecreaseFor3Chain, 6)
          | POW_SM(pModal->pwrDecreaseFor2Chain, 0)
    );
    return AH_TRUE;
#undef POW_SM
}
/**************************************************************
 * ar5416SetTransmitPower
 *
 * Set the transmit power in the baseband for the given
 * operating channel and mode.
 */
ar5416SetTransmitPower
Set the transmit power in the baseband for the given
operating channel and mode.
ar5416SetTransmitPower Set the transmit power in the baseband for the given operating channel and mode .
HAL_BOOL
ar5416SetTransmitPower(struct ath_hal *ah,
	const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
{
#define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
    MODAL_EEP_HEADER	*pModal;
    struct ath_hal_5212 *ahp = AH5212(ah);
    int16_t		ratesArray[Ar5416RateSize];
    int16_t		txPowerIndexOffset = 0;
    uint8_t		ht40PowerIncForPdadc = 2;	
    int			i;
    uint16_t		cfgCtl;
    uint16_t		powerLimit;
    uint16_t		twiceAntennaReduction;
    uint16_t		twiceMaxRegulatoryPower;
    int16_t		maxPower;
    HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
    struct ar5416eeprom	*pEepData = &ee->ee_base;
    HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
    OS_MEMZERO(ratesArray, sizeof(ratesArray));
    cfgCtl = ath_hal_getctl(ah, chan);
    powerLimit = chan->ic_maxregpower * 2;
    twiceAntennaReduction = chan->ic_maxantgain;
    twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 
    pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
    HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
	__func__,chan->ic_freq, cfgCtl );      
    if (IS_EEP_MINOR_V2(ah)) {
        ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
    }
    if (!ar5416SetPowerPerRateTable(ah, pEepData,  chan,
                                    &ratesArray[0],cfgCtl,
                                    twiceAntennaReduction,
				    twiceMaxRegulatoryPower, powerLimit)) {
        HALDEBUG(ah, HAL_DEBUG_ANY,
	    "%s: unable to set tx power per rate table\n", __func__);
        return AH_FALSE;
    }
    if (!ar5416SetPowerCalTable(ah,  pEepData, chan, &txPowerIndexOffset)) {
        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
	    __func__);
        return AH_FALSE;
    }
    maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]);
    if (IEEE80211_IS_CHAN_2GHZ(chan)) {
        maxPower = AH_MAX(maxPower, ratesArray[rate1l]);
    }
    if (IEEE80211_IS_CHAN_HT40(chan)) {
        maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]);
    }
    ahp->ah_tx6PowerInHalfDbm = maxPower;   
    AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;
    ahp->ah_txPowerIndexOffset = txPowerIndexOffset;
    for (i = 0; i < NELEM(ratesArray); i++) {
        ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
        if (ratesArray[i] > AR5416_MAX_RATE_POWER)
            ratesArray[i] = AR5416_MAX_RATE_POWER;
    }
#ifdef AH_EEPROM_DUMP
    ar5416PrintPowerPerRate(ah, ratesArray);
#endif
    OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
        POW_SM(ratesArray[rate18mb], 24)
          | POW_SM(ratesArray[rate12mb], 16)
          | POW_SM(ratesArray[rate9mb], 8)
          | POW_SM(ratesArray[rate6mb], 0)
    );
    OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
        POW_SM(ratesArray[rate54mb], 24)
          | POW_SM(ratesArray[rate48mb], 16)
          | POW_SM(ratesArray[rate36mb], 8)
          | POW_SM(ratesArray[rate24mb], 0)
    );
    if (IEEE80211_IS_CHAN_2GHZ(chan)) {
        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
            POW_SM(ratesArray[rate2s], 24)
              | POW_SM(ratesArray[rate2l],  16)
              | POW_SM(ratesArray[rateXr],  8) 
              | POW_SM(ratesArray[rate1l],   0)
        );
        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
            POW_SM(ratesArray[rate11s], 24)
              | POW_SM(ratesArray[rate11l], 16)
              | POW_SM(ratesArray[rate5_5s], 8)
              | POW_SM(ratesArray[rate5_5l], 0)
        );
    HALDEBUG(ah, HAL_DEBUG_RESET,
	"%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n",
	    __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3),
	    OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 
    }
    OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
        POW_SM(ratesArray[rateHt20_3], 24)
          | POW_SM(ratesArray[rateHt20_2], 16)
          | POW_SM(ratesArray[rateHt20_1], 8)
          | POW_SM(ratesArray[rateHt20_0], 0)
    );
    OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
        POW_SM(ratesArray[rateHt20_7], 24)
          | POW_SM(ratesArray[rateHt20_6], 16)
          | POW_SM(ratesArray[rateHt20_5], 8)
          | POW_SM(ratesArray[rateHt20_4], 0)
    );
    if (IEEE80211_IS_CHAN_HT40(chan)) {
        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
            POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24)
              | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16)
              | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8)
              | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0)
        );
        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
            POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24)
              | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16)
              | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8)
              | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0)
        );
        OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
            POW_SM(ratesArray[rateExtOfdm], 24)
              | POW_SM(ratesArray[rateExtCck], 16)
              | POW_SM(ratesArray[rateDupOfdm], 8)
              | POW_SM(ratesArray[rateDupCck], 0)
        );
    }
    OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
        POW_SM(pModal->pwrDecreaseFor3Chain, 6)
          | POW_SM(pModal->pwrDecreaseFor2Chain, 0)
    );
    return AH_TRUE;
#undef POW_SM
}
HAL_BOOL ar5416SetTransmitPower ( struct ath_hal * ah , const struct ieee80211_channel * chan , uint16_t * rfXpdGain ) { #define POW_SM ( _r , _s )      (((_r) & 0x3f) << (_s)) MODAL_EEP_HEADER * pModal ; struct ath_hal_5212 * ahp = AH5212 ( ah ) ; int16_t ratesArray [ Ar5416RateSize ] ; int16_t txPowerIndexOffset = 0 ; uint8_t ht40PowerIncForPdadc = 2 ; int i ; uint16_t cfgCtl ; uint16_t powerLimit ; uint16_t twiceAntennaReduction ; uint16_t twiceMaxRegulatoryPower ; int16_t maxPower ; HAL_EEPROM_v14 * ee = AH_PRIVATE ( ah ) -> ah_eeprom ; struct ar5416eeprom * pEepData = & ee -> ee_base ; HALASSERT ( AH_PRIVATE ( ah ) -> ah_eeversion >= AR_EEPROM_VER14_1 ) ; OS_MEMZERO ( ratesArray , sizeof ( ratesArray ) ) ; cfgCtl = ath_hal_getctl ( ah , chan ) ; powerLimit = chan -> ic_maxregpower * 2 ; twiceAntennaReduction = chan -> ic_maxantgain ; twiceMaxRegulatoryPower = AH_MIN ( MAX_RATE_POWER , AH_PRIVATE ( ah ) -> ah_powerLimit ) ; pModal = & pEepData -> modalHeader [ IEEE80211_IS_CHAN_2GHZ ( chan ) ] ; HALDEBUG ( ah , HAL_DEBUG_RESET , " \n " , __func__ , chan -> ic_freq , cfgCtl ) ; if ( IS_EEP_MINOR_V2 ( ah ) ) { ht40PowerIncForPdadc = pModal -> ht40PowerIncForPdadc ; } if ( ! ar5416SetPowerPerRateTable ( ah , pEepData , chan , & ratesArray [ 0 ] , cfgCtl , twiceAntennaReduction , twiceMaxRegulatoryPower , powerLimit ) ) { HALDEBUG ( ah , HAL_DEBUG_ANY , " \n " , __func__ ) ; return AH_FALSE ; } if ( ! ar5416SetPowerCalTable ( ah , pEepData , chan , & txPowerIndexOffset ) ) { HALDEBUG ( ah , HAL_DEBUG_ANY , " \n " , __func__ ) ; return AH_FALSE ; } maxPower = AH_MAX ( ratesArray [ rate6mb ] , ratesArray [ rateHt20_0 ] ) ; if ( IEEE80211_IS_CHAN_2GHZ ( chan ) ) { maxPower = AH_MAX ( maxPower , ratesArray [ rate1l ] ) ; } if ( IEEE80211_IS_CHAN_HT40 ( chan ) ) { maxPower = AH_MAX ( maxPower , ratesArray [ rateHt40_0 ] ) ; } ahp -> ah_tx6PowerInHalfDbm = maxPower ; AH_PRIVATE ( ah ) -> ah_maxPowerLevel = maxPower ; ahp -> ah_txPowerIndexOffset = txPowerIndexOffset ; for ( i = 0 ; i < NELEM ( ratesArray ) ; i ++ ) { ratesArray [ i ] = ( int16_t ) ( txPowerIndexOffset + ratesArray [ i ] ) ; if ( ratesArray [ i ] > AR5416_MAX_RATE_POWER ) ratesArray [ i ] = AR5416_MAX_RATE_POWER ; } #ifdef AH_EEPROM_DUMP ar5416PrintPowerPerRate ( ah , ratesArray ) ; #endif OS_REG_WRITE ( ah , AR_PHY_POWER_TX_RATE1 , POW_SM ( ratesArray [ rate18mb ] , 24 ) | POW_SM ( ratesArray [ rate12mb ] , 16 ) | POW_SM ( ratesArray [ rate9mb ] , 8 ) | POW_SM ( ratesArray [ rate6mb ] , 0 ) ) ; OS_REG_WRITE ( ah , AR_PHY_POWER_TX_RATE2 , POW_SM ( ratesArray [ rate54mb ] , 24 ) | POW_SM ( ratesArray [ rate48mb ] , 16 ) | POW_SM ( ratesArray [ rate36mb ] , 8 ) | POW_SM ( ratesArray [ rate24mb ] , 0 ) ) ; if ( IEEE80211_IS_CHAN_2GHZ ( chan ) ) { OS_REG_WRITE ( ah , AR_PHY_POWER_TX_RATE3 , POW_SM ( ratesArray [ rate2s ] , 24 ) | POW_SM ( ratesArray [ rate2l ] , 16 ) | POW_SM ( ratesArray [ rateXr ] , 8 ) | POW_SM ( ratesArray [ rate1l ] , 0 ) ) ; OS_REG_WRITE ( ah , AR_PHY_POWER_TX_RATE4 , POW_SM ( ratesArray [ rate11s ] , 24 ) | POW_SM ( ratesArray [ rate11l ] , 16 ) | POW_SM ( ratesArray [ rate5_5s ] , 8 ) | POW_SM ( ratesArray [ rate5_5l ] , 0 ) ) ; HALDEBUG ( ah , HAL_DEBUG_RESET , " \n " , __func__ , OS_REG_READ ( ah , AR_PHY_POWER_TX_RATE3 ) , OS_REG_READ ( ah , AR_PHY_POWER_TX_RATE4 ) ) ; } OS_REG_WRITE ( ah , AR_PHY_POWER_TX_RATE5 , POW_SM ( ratesArray [ rateHt20_3 ] , 24 ) | POW_SM ( ratesArray [ rateHt20_2 ] , 16 ) | POW_SM ( ratesArray [ rateHt20_1 ] , 8 ) | POW_SM ( ratesArray [ rateHt20_0 ] , 0 ) ) ; OS_REG_WRITE ( ah , AR_PHY_POWER_TX_RATE6 , POW_SM ( ratesArray [ rateHt20_7 ] , 24 ) | POW_SM ( ratesArray [ rateHt20_6 ] , 16 ) | POW_SM ( ratesArray [ rateHt20_5 ] , 8 ) | POW_SM ( ratesArray [ rateHt20_4 ] , 0 ) ) ; if ( IEEE80211_IS_CHAN_HT40 ( chan ) ) { OS_REG_WRITE ( ah , AR_PHY_POWER_TX_RATE7 , POW_SM ( ratesArray [ rateHt40_3 ] + ht40PowerIncForPdadc , 24 ) | POW_SM ( ratesArray [ rateHt40_2 ] + ht40PowerIncForPdadc , 16 ) | POW_SM ( ratesArray [ rateHt40_1 ] + ht40PowerIncForPdadc , 8 ) | POW_SM ( ratesArray [ rateHt40_0 ] + ht40PowerIncForPdadc , 0 ) ) ; OS_REG_WRITE ( ah , AR_PHY_POWER_TX_RATE8 , POW_SM ( ratesArray [ rateHt40_7 ] + ht40PowerIncForPdadc , 24 ) | POW_SM ( ratesArray [ rateHt40_6 ] + ht40PowerIncForPdadc , 16 ) | POW_SM ( ratesArray [ rateHt40_5 ] + ht40PowerIncForPdadc , 8 ) | POW_SM ( ratesArray [ rateHt40_4 ] + ht40PowerIncForPdadc , 0 ) ) ; OS_REG_WRITE ( ah , AR_PHY_POWER_TX_RATE9 , POW_SM ( ratesArray [ rateExtOfdm ] , 24 ) | POW_SM ( ratesArray [ rateExtCck ] , 16 ) | POW_SM ( ratesArray [ rateDupOfdm ] , 8 ) | POW_SM ( ratesArray [ rateDupCck ] , 0 ) ) ; } OS_REG_WRITE ( ah , AR_PHY_POWER_TX_SUB , POW_SM ( pModal -> pwrDecreaseFor3Chain , 6 ) | POW_SM ( pModal -> pwrDecreaseFor2Chain , 0 ) ) ; return AH_TRUE ; #undef  POW_SM }
ar5416SetTransmitPower
 Set the transmit power in the baseband for the given
 operating channel and mode.
ar5416SetTransmitPower Set the transmit power in the baseband for the given operating channel and mode .
/* Setup info for the actual eeprom */ /*
     * txPowerIndexOffset is set by the SetPowerTable() call -
     *  adjust the rate table (0 offset if rates EEPROM not loaded)
     */ /* Write the OFDM power per rate set */ /* Write the CCK power per rate set */ /* XR target power */ /* Write the HT20 power per rate set */ /* Write the HT40 power per rate set */ /* Correct PAR difference between HT40 and HT20/LEGACY */ /* Write the Dup/Ext 40 power per rate set */ /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */