host-drivers/base-driver/vca/plx87xx/plx_hw.c
int plx_hw_init(struct plx_device *xdev, struct pci_dev *pdev)
{
	u32 val;
	int rc;

	spin_lock_init(&xdev->alm_lock);

	rc = pci_read_config_dword(pdev, PLX_PORT_ID, &val);
	if (rc) {
		dev_err(&pdev->dev, "can't read config dword: %d\n", rc);
		return rc;
	}
	xdev->link_side = !!(val & (1 << 31));
	xdev->port_id = val & 0x1;
	xdev->reg_base = _plx_get_reg_base(xdev->link_side, xdev->port_id);
	xdev->reg_base_peer = _plx_get_reg_base(!xdev->link_side, xdev->port_id);

	xdev->a_lut = false;
	xdev->a_lut_peer = false;
#ifdef VCA_ALUT_CARD_SIDE
	if (xdev->link_side) {
		xdev->a_lut = true;
	} else {
		xdev->a_lut_peer = true;
	}
#endif
#ifdef VCA_ALUT_HOST_SIDE
	if (xdev->link_side) {
		xdev->a_lut_peer = true;
	} else {
		xdev->a_lut = true;
	}
#endif

	if (!xdev->link_side) {
		rc = plx_check_eeprom(xdev);
		if (rc)
			return rc;
 	}

	if (xdev->link_side) {
		xdev->intr_reg_base = 0x10;
	} else {
		xdev->peer_intr_reg_base = 0x10;
	}

	switch (pdev->device)
	{
		case INTEL_VCA_CPU2_UPSTREAM_ID:
		case INTEL_VCA_PCI_NODE2_ID:
			xdev->num_ntbs = 1;
			break;

		case INTEL_VCA_CPU0_UPSTREAM_ID:
		case INTEL_VCA_CPU1_UPSTREAM_ID:
		case INTEL_VCA_PCI_NODE0_ID:
		case INTEL_VCA_PCI_NODE1_ID:
			xdev->num_ntbs = 2;
			break;

		case INTEL_VCA_CARD_UPSTREAM_ID:
		case PLX_PCI_DEVICE_87A0:
		case PLX_PCI_DEVICE_87A1:
		case PLX_PCI_DEVICE_87B0:
		case PLX_PCI_DEVICE_87B1:
		default:
			dev_info(&xdev->pdev->dev, "Device 0x%x doesn't explicity identify VCA node. Assuming two NTBs. Switch to newer EEPROM\n",
				pdev->device);
			xdev->num_ntbs = 2;
			break;
	}

	if (xdev->num_ntbs == 2) {
		if (!xdev->link_side)
			xdev->a_lut_array_base = (!xdev->port_id)?0x38000:0x3a000;
		else
			xdev->a_lut_array_base = (!xdev->port_id)?0x39000:0x3b000;
	} else {
		if (!xdev->link_side)
			xdev->a_lut_array_base = 0x38000;
		else
			xdev->a_lut_array_base = 0x3a000;
	}
	dev_info(&xdev->pdev->dev, "SOMNATH: A-LUT array base port is %x\n",
		xdev->a_lut_array_base);

	rc = plx_program_rid_lut(xdev, pdev);
	if (rc) {
		dev_err(&pdev->dev, "can't program RID LUT: %d\n", rc);
		return rc;
	}
	rc = plx_program_rid_lut_dma(xdev, pdev);
	if (rc) {
		dev_err(&pdev->dev, "can't program RID LUT DMA: %d\n", rc);
		return rc;
	}

	rc = _plx_a_lut_enable(xdev, pdev);
	if (rc) {
		dev_err(&pdev->dev, "can't configure A LUT: %d\n", rc);
		return rc;
	}

	dev_info(&pdev->dev, "link_side %d reg_base 0x%x reg_base_peer 0x%x "\
		    "port id 0x%x a_lut %d a_lut_peer %d\n", xdev->link_side,
		    xdev->reg_base, xdev->reg_base_peer, xdev->port_id, xdev->a_lut,
		    xdev->a_lut_peer);

	spin_lock(&xdev->alm_lock);

	rc = plx_alm_init(&xdev->a_lut_manager, xdev->pdev,
		xdev->num_ntbs, xdev->aper.len);

	dev_info(&xdev->pdev->dev,
		"programmed a lut segment size to %llx num segments:%x num ntbs:%x\n",
		xdev->a_lut_manager.segment_size, xdev->a_lut_manager.segments_num,
		xdev->num_ntbs);

	spin_unlock(&xdev->alm_lock);

	return rc;
}
/*
 * plx_hw_init - Initialize any hardware specific information
 *
 * @xdev: pointer to plx_device instance
 * @pdev: The PCIe device
 *
 * RETURNS: 0 on success and errno on failure
 */
Initialize any hardware specific information
@xdev: pointer to plx_device instance
@pdev: The PCIe device

0 on success and errno on failure
Initialize any hardware specific information @xdev : pointer to plx_device instance @pdev : The PCIe device 0 on success and errno on failure
int plx_hw_init(struct plx_device *xdev, struct pci_dev *pdev)
{
	u32 val;
	int rc;
	spin_lock_init(&xdev->alm_lock);
	rc = pci_read_config_dword(pdev, PLX_PORT_ID, &val);
	if (rc) {
		dev_err(&pdev->dev, "can't read config dword: %d\n", rc);
		return rc;
	}
	xdev->link_side = !!(val & (1 << 31));
	xdev->port_id = val & 0x1;
	xdev->reg_base = _plx_get_reg_base(xdev->link_side, xdev->port_id);
	xdev->reg_base_peer = _plx_get_reg_base(!xdev->link_side, xdev->port_id);
	xdev->a_lut = false;
	xdev->a_lut_peer = false;
#ifdef VCA_ALUT_CARD_SIDE
	if (xdev->link_side) {
		xdev->a_lut = true;
	} else {
		xdev->a_lut_peer = true;
	}
#endif
#ifdef VCA_ALUT_HOST_SIDE
	if (xdev->link_side) {
		xdev->a_lut_peer = true;
	} else {
		xdev->a_lut = true;
	}
#endif
	if (!xdev->link_side) {
		rc = plx_check_eeprom(xdev);
		if (rc)
			return rc;
 	}
	if (xdev->link_side) {
		xdev->intr_reg_base = 0x10;
	} else {
		xdev->peer_intr_reg_base = 0x10;
	}
	switch (pdev->device)
	{
		case INTEL_VCA_CPU2_UPSTREAM_ID:
		case INTEL_VCA_PCI_NODE2_ID:
			xdev->num_ntbs = 1;
			break;
		case INTEL_VCA_CPU0_UPSTREAM_ID:
		case INTEL_VCA_CPU1_UPSTREAM_ID:
		case INTEL_VCA_PCI_NODE0_ID:
		case INTEL_VCA_PCI_NODE1_ID:
			xdev->num_ntbs = 2;
			break;
		case INTEL_VCA_CARD_UPSTREAM_ID:
		case PLX_PCI_DEVICE_87A0:
		case PLX_PCI_DEVICE_87A1:
		case PLX_PCI_DEVICE_87B0:
		case PLX_PCI_DEVICE_87B1:
		default:
			dev_info(&xdev->pdev->dev, "Device 0x%x doesn't explicity identify VCA node. Assuming two NTBs. Switch to newer EEPROM\n",
				pdev->device);
			xdev->num_ntbs = 2;
			break;
	}
	if (xdev->num_ntbs == 2) {
		if (!xdev->link_side)
			xdev->a_lut_array_base = (!xdev->port_id)?0x38000:0x3a000;
		else
			xdev->a_lut_array_base = (!xdev->port_id)?0x39000:0x3b000;
	} else {
		if (!xdev->link_side)
			xdev->a_lut_array_base = 0x38000;
		else
			xdev->a_lut_array_base = 0x3a000;
	}
	dev_info(&xdev->pdev->dev, "SOMNATH: A-LUT array base port is %x\n",
		xdev->a_lut_array_base);
	rc = plx_program_rid_lut(xdev, pdev);
	if (rc) {
		dev_err(&pdev->dev, "can't program RID LUT: %d\n", rc);
		return rc;
	}
	rc = plx_program_rid_lut_dma(xdev, pdev);
	if (rc) {
		dev_err(&pdev->dev, "can't program RID LUT DMA: %d\n", rc);
		return rc;
	}
	rc = _plx_a_lut_enable(xdev, pdev);
	if (rc) {
		dev_err(&pdev->dev, "can't configure A LUT: %d\n", rc);
		return rc;
	}
	dev_info(&pdev->dev, "link_side %d reg_base 0x%x reg_base_peer 0x%x "\
		    "port id 0x%x a_lut %d a_lut_peer %d\n", xdev->link_side,
		    xdev->reg_base, xdev->reg_base_peer, xdev->port_id, xdev->a_lut,
		    xdev->a_lut_peer);
	spin_lock(&xdev->alm_lock);
	rc = plx_alm_init(&xdev->a_lut_manager, xdev->pdev,
		xdev->num_ntbs, xdev->aper.len);
	dev_info(&xdev->pdev->dev,
		"programmed a lut segment size to %llx num segments:%x num ntbs:%x\n",
		xdev->a_lut_manager.segment_size, xdev->a_lut_manager.segments_num,
		xdev->num_ntbs);
	spin_unlock(&xdev->alm_lock);
	return rc;
}
int plx_hw_init ( struct plx_device * xdev , struct pci_dev * pdev ) { u32 val ; int rc ; spin_lock_init ( & xdev -> alm_lock ) ; rc = pci_read_config_dword ( pdev , PLX_PORT_ID , & val ) ; if ( rc ) { dev_err ( & pdev -> dev , " \n " , rc ) ; return rc ; } xdev -> link_side = ! ! ( val & ( 1 << 31 ) ) ; xdev -> port_id = val & 0x1 ; xdev -> reg_base = _plx_get_reg_base ( xdev -> link_side , xdev -> port_id ) ; xdev -> reg_base_peer = _plx_get_reg_base ( ! xdev -> link_side , xdev -> port_id ) ; xdev -> a_lut = false ; xdev -> a_lut_peer = false ; #ifdef VCA_ALUT_CARD_SIDE if ( xdev -> link_side ) { xdev -> a_lut = true ; } else { xdev -> a_lut_peer = true ; } #endif #ifdef VCA_ALUT_HOST_SIDE if ( xdev -> link_side ) { xdev -> a_lut_peer = true ; } else { xdev -> a_lut = true ; } #endif if ( ! xdev -> link_side ) { rc = plx_check_eeprom ( xdev ) ; if ( rc ) return rc ; } if ( xdev -> link_side ) { xdev -> intr_reg_base = 0x10 ; } else { xdev -> peer_intr_reg_base = 0x10 ; } switch ( pdev -> device ) { case INTEL_VCA_CPU2_UPSTREAM_ID : case INTEL_VCA_PCI_NODE2_ID : xdev -> num_ntbs = 1 ; break ; case INTEL_VCA_CPU0_UPSTREAM_ID : case INTEL_VCA_CPU1_UPSTREAM_ID : case INTEL_VCA_PCI_NODE0_ID : case INTEL_VCA_PCI_NODE1_ID : xdev -> num_ntbs = 2 ; break ; case INTEL_VCA_CARD_UPSTREAM_ID : case PLX_PCI_DEVICE_87A0 : case PLX_PCI_DEVICE_87A1 : case PLX_PCI_DEVICE_87B0 : case PLX_PCI_DEVICE_87B1 : default : dev_info ( & xdev -> pdev -> dev , " \n " , pdev -> device ) ; xdev -> num_ntbs = 2 ; break ; } if ( xdev -> num_ntbs == 2 ) { if ( ! xdev -> link_side ) xdev -> a_lut_array_base = ( ! xdev -> port_id ) ? 0x38000 : 0x3a000 ; else xdev -> a_lut_array_base = ( ! xdev -> port_id ) ? 0x39000 : 0x3b000 ; } else { if ( ! xdev -> link_side ) xdev -> a_lut_array_base = 0x38000 ; else xdev -> a_lut_array_base = 0x3a000 ; } dev_info ( & xdev -> pdev -> dev , " \n " , xdev -> a_lut_array_base ) ; rc = plx_program_rid_lut ( xdev , pdev ) ; if ( rc ) { dev_err ( & pdev -> dev , " \n " , rc ) ; return rc ; } rc = plx_program_rid_lut_dma ( xdev , pdev ) ; if ( rc ) { dev_err ( & pdev -> dev , " \n " , rc ) ; return rc ; } rc = _plx_a_lut_enable ( xdev , pdev ) ; if ( rc ) { dev_err ( & pdev -> dev , " \n " , rc ) ; return rc ; } dev_info ( & pdev -> dev , " " " \n " , xdev -> link_side , xdev -> reg_base , xdev -> reg_base_peer , xdev -> port_id , xdev -> a_lut , xdev -> a_lut_peer ) ; spin_lock ( & xdev -> alm_lock ) ; rc = plx_alm_init ( & xdev -> a_lut_manager , xdev -> pdev , xdev -> num_ntbs , xdev -> aper . len ) ; dev_info ( & xdev -> pdev -> dev , " \n " , xdev -> a_lut_manager . segment_size , xdev -> a_lut_manager . segments_num , xdev -> num_ntbs ) ; spin_unlock ( & xdev -> alm_lock ) ; return rc ; }
plx_hw_init - Initialize any hardware specific information
 @xdev: pointer to plx_device instance
 @pdev: The PCIe device
plx_hw_init - Initialize any hardware specific information @xdev : pointer to plx_device instance @pdev : The PCIe device