XilinxProcessorIPLib/drivers/vphy/src/xvphy.c
u32 XVphy_SetPrbsSel(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId,
		XVphy_DirectionType Dir, XVphy_PrbsPattern Pattern)
{
	u32 RegVal;
	u32 MaskVal;
	u32 RegOffset;
	u32 PrbsEnc = 0x0;
	u8 Id, Id0, Id1;

	/* Suppress Warning Messages */
	QuadId = QuadId;

	if (Dir == XVPHY_DIR_TX) {
		RegOffset = XVPHY_TX_CONTROL_REG;
		if (ChId == XVPHY_CHANNEL_ID_CHA) {
			MaskVal =  XVPHY_TX_CONTROL_TXPRBSSEL_ALL_MASK;
		}
		else {
			MaskVal = XVPHY_TX_CONTROL_TXPRBSSEL_MASK(ChId);
		}
		PrbsEnc = (u32) (((Pattern & 0x8) << 1) | (Pattern & 0x7));
	}
	else {
		RegOffset = XVPHY_RX_CONTROL_REG;
		if (ChId == XVPHY_CHANNEL_ID_CHA) {
			MaskVal = XVPHY_RX_CONTROL_RXPRBSSEL_ALL_MASK;
		}
		else {
			MaskVal = XVPHY_RX_CONTROL_RXPRBSSEL_MASK(ChId);
		}
		PrbsEnc = (u32) (Pattern & 0xF);
	}

	/* Read TX|RX Control Register */
	RegVal = XVphy_ReadReg(InstancePtr->Config.BaseAddr, RegOffset);

	/* Mask out PRBS Register bits */
	RegVal &= ~MaskVal;

	XVphy_Ch2Ids(InstancePtr, ChId, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		RegVal |= PrbsEnc << ((Dir == XVPHY_DIR_TX) ?
					XVPHY_TX_CONTROL_TXPRBSSEL_SHIFT(Id) :
					XVPHY_RX_CONTROL_RXPRBSSEL_SHIFT(Id));
	}

	XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function will set the TX/RXPRBSEL of the GT
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID which to operate on.
* @param	Dir is an indicator for TX or RX.
* @param	Pattern is the pattern XVphy_PrbsPattern
*
* @return
*		- XST_SUCCESS.
*
* @note		None.
*
******************************************************************************/
This function will set the TX/RXPRBSEL of the GT
This function will set the TX / RXPRBSEL of the GT
u32 XVphy_SetPrbsSel(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId,
		XVphy_DirectionType Dir, XVphy_PrbsPattern Pattern)
{
	u32 RegVal;
	u32 MaskVal;
	u32 RegOffset;
	u32 PrbsEnc = 0x0;
	u8 Id, Id0, Id1;
	QuadId = QuadId;
	if (Dir == XVPHY_DIR_TX) {
		RegOffset = XVPHY_TX_CONTROL_REG;
		if (ChId == XVPHY_CHANNEL_ID_CHA) {
			MaskVal =  XVPHY_TX_CONTROL_TXPRBSSEL_ALL_MASK;
		}
		else {
			MaskVal = XVPHY_TX_CONTROL_TXPRBSSEL_MASK(ChId);
		}
		PrbsEnc = (u32) (((Pattern & 0x8) << 1) | (Pattern & 0x7));
	}
	else {
		RegOffset = XVPHY_RX_CONTROL_REG;
		if (ChId == XVPHY_CHANNEL_ID_CHA) {
			MaskVal = XVPHY_RX_CONTROL_RXPRBSSEL_ALL_MASK;
		}
		else {
			MaskVal = XVPHY_RX_CONTROL_RXPRBSSEL_MASK(ChId);
		}
		PrbsEnc = (u32) (Pattern & 0xF);
	}
	RegVal = XVphy_ReadReg(InstancePtr->Config.BaseAddr, RegOffset);
	RegVal &= ~MaskVal;
	XVphy_Ch2Ids(InstancePtr, ChId, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		RegVal |= PrbsEnc << ((Dir == XVPHY_DIR_TX) ?
					XVPHY_TX_CONTROL_TXPRBSSEL_SHIFT(Id) :
					XVPHY_RX_CONTROL_RXPRBSSEL_SHIFT(Id));
	}
	XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal);
	return XST_SUCCESS;
}
u32 XVphy_SetPrbsSel ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId ChId , XVphy_DirectionType Dir , XVphy_PrbsPattern Pattern ) { u32 RegVal ; u32 MaskVal ; u32 RegOffset ; u32 PrbsEnc = 0x0 ; u8 Id , Id0 , Id1 ; QuadId = QuadId ; if ( Dir == XVPHY_DIR_TX ) { RegOffset = XVPHY_TX_CONTROL_REG ; if ( ChId == XVPHY_CHANNEL_ID_CHA ) { MaskVal = XVPHY_TX_CONTROL_TXPRBSSEL_ALL_MASK ; } else { MaskVal = XVPHY_TX_CONTROL_TXPRBSSEL_MASK ( ChId ) ; } PrbsEnc = ( u32 ) ( ( ( Pattern & 0x8 ) << 1 ) | ( Pattern & 0x7 ) ) ; } else { RegOffset = XVPHY_RX_CONTROL_REG ; if ( ChId == XVPHY_CHANNEL_ID_CHA ) { MaskVal = XVPHY_RX_CONTROL_RXPRBSSEL_ALL_MASK ; } else { MaskVal = XVPHY_RX_CONTROL_RXPRBSSEL_MASK ( ChId ) ; } PrbsEnc = ( u32 ) ( Pattern & 0xF ) ; } RegVal = XVphy_ReadReg ( InstancePtr -> Config . BaseAddr , RegOffset ) ; RegVal &= ~ MaskVal ; XVphy_Ch2Ids ( InstancePtr , ChId , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { RegVal |= PrbsEnc << ( ( Dir == XVPHY_DIR_TX ) ? XVPHY_TX_CONTROL_TXPRBSSEL_SHIFT ( Id ) : XVPHY_RX_CONTROL_RXPRBSSEL_SHIFT ( Id ) ) ; } XVphy_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffset , RegVal ) ; return XST_SUCCESS ; }
This function will set the TX/RXPRBSEL of the GT
This function will set the TX / RXPRBSEL of the GT
/* Suppress Warning Messages */ /* Read TX|RX Control Register */ /* Mask out PRBS Register bits */