XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_hdmi_intr.c
void XHdmiphy1_HdmiTxClkDetFreqChangeHandler(XHdmiphy1 *InstancePtr)
{
    XHdmiphy1_PllType PllType;
    u8 Id, Id0, Id1;

    if (InstancePtr->TxHdmi21Cfg.IsEnabled) {
        if (InstancePtr->Config.TxRefClkSel !=
                InstancePtr->Config.TxFrlRefClkSel) {
            return;
        }
    }
    XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_TX_FREQ, 0);

	/* Set TX TMDS Clock Pattern Generator */
	if ((InstancePtr->Config.UseGtAsTxTmdsClk == TRUE) &&
		((InstancePtr->TxHdmi21Cfg.IsEnabled == 0) ||
		 (InstancePtr->TxHdmi21Cfg.IsEnabled == 1 &&
			InstancePtr->TxHdmi21Cfg.NChannels == 3))) {
		XHdmiphy1_PatgenEnable(InstancePtr, 0, FALSE);
	}

	/* Determine PLL type. */
    PllType = XHdmiphy1_GetPllType(InstancePtr, 0, XHDMIPHY1_DIR_TX,
            XHDMIPHY1_CHANNEL_ID_CH1);

	/* If the TX frequency has changed, the PLL is always disabled. */
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    XHdmiphy1_PowerDownGtPll(InstancePtr, 0,
        (PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
        XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA, TRUE);

    XHdmiphy1_ResetGtPll(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
            XHDMIPHY1_DIR_TX, TRUE);
#else
	/* Suppress Warning Messages */
    PllType = PllType;

    /* Mask RESET DONE */
	/* Deassert TX LNKRDY MASK */
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, XHDMIPHY1_TX_INIT_REG,
			(XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
					XHDMIPHY1_TX_INIT_REG) | 0x10101010));
#endif
    /* Mask the MMCM Lock */
    XHdmiphy1_MmcmLockedMaskEnable(InstancePtr, 0, XHDMIPHY1_DIR_TX, TRUE);

    /* Disable TX MMCM. */
    /* XHdmiphy1_MmcmPowerDown(InstancePtr, 0, XHDMIPHY1_DIR_TX, TRUE); */

    /* Clear TX timer. */
    XHdmiphy1_ClkDetTimerClear(InstancePtr, 0, XHDMIPHY1_DIR_TX);

#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    /* Clear GT alignment. */
    XHdmiphy1_TxAlignStart(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, FALSE);
#endif

    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].TxState =
            XHDMIPHY1_GT_STATE_IDLE;
    }

    /* If there is no reference clock, load TX timer in usec. */
    if (XHdmiphy1_ClkDetGetRefClkFreqHz(InstancePtr, XHDMIPHY1_DIR_TX)) {
        XHdmiphy1_ClkDetTimerLoad(InstancePtr, 0, XHDMIPHY1_DIR_TX,
                        InstancePtr->Config.AxiLiteClkFreq/1000);
    }

    /* Callback to re-initialize. */
    if (InstancePtr->HdmiTxInitCallback) {
        InstancePtr->HdmiTxInitCallback(InstancePtr->HdmiTxInitRef);
    }
}
/*****************************************************************************/
/**
* This function is the handler for events triggered by a change in TX frequency
* as detected by the HDMI clock detector logic.
*
* @param    InstancePtr is a pointer to the HDMIPHY instance.
*
* @return   None.
*
* @note     None.
*
******************************************************************************/
This function is the handler for events triggered by a change in TX frequency
as detected by the HDMI clock detector logic.
This function is the handler for events triggered by a change in TX frequency as detected by the HDMI clock detector logic .
void XHdmiphy1_HdmiTxClkDetFreqChangeHandler(XHdmiphy1 *InstancePtr)
{
    XHdmiphy1_PllType PllType;
    u8 Id, Id0, Id1;
    if (InstancePtr->TxHdmi21Cfg.IsEnabled) {
        if (InstancePtr->Config.TxRefClkSel !=
                InstancePtr->Config.TxFrlRefClkSel) {
            return;
        }
    }
    XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_TX_FREQ, 0);
	if ((InstancePtr->Config.UseGtAsTxTmdsClk == TRUE) &&
		((InstancePtr->TxHdmi21Cfg.IsEnabled == 0) ||
		 (InstancePtr->TxHdmi21Cfg.IsEnabled == 1 &&
			InstancePtr->TxHdmi21Cfg.NChannels == 3))) {
		XHdmiphy1_PatgenEnable(InstancePtr, 0, FALSE);
	}
    PllType = XHdmiphy1_GetPllType(InstancePtr, 0, XHDMIPHY1_DIR_TX,
            XHDMIPHY1_CHANNEL_ID_CH1);
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    XHdmiphy1_PowerDownGtPll(InstancePtr, 0,
        (PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
        XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA, TRUE);
    XHdmiphy1_ResetGtPll(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
            XHDMIPHY1_DIR_TX, TRUE);
#else
    PllType = PllType;
	XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr, XHDMIPHY1_TX_INIT_REG,
			(XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
					XHDMIPHY1_TX_INIT_REG) | 0x10101010));
#endif
    XHdmiphy1_MmcmLockedMaskEnable(InstancePtr, 0, XHDMIPHY1_DIR_TX, TRUE);
    XHdmiphy1_ClkDetTimerClear(InstancePtr, 0, XHDMIPHY1_DIR_TX);
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    XHdmiphy1_TxAlignStart(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, FALSE);
#endif
    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].TxState =
            XHDMIPHY1_GT_STATE_IDLE;
    }
    if (XHdmiphy1_ClkDetGetRefClkFreqHz(InstancePtr, XHDMIPHY1_DIR_TX)) {
        XHdmiphy1_ClkDetTimerLoad(InstancePtr, 0, XHDMIPHY1_DIR_TX,
                        InstancePtr->Config.AxiLiteClkFreq/1000);
    }
    if (InstancePtr->HdmiTxInitCallback) {
        InstancePtr->HdmiTxInitCallback(InstancePtr->HdmiTxInitRef);
    }
}
void XHdmiphy1_HdmiTxClkDetFreqChangeHandler ( XHdmiphy1 * InstancePtr ) { XHdmiphy1_PllType PllType ; u8 Id , Id0 , Id1 ; if ( InstancePtr -> TxHdmi21Cfg . IsEnabled ) { if ( InstancePtr -> Config . TxRefClkSel != InstancePtr -> Config . TxFrlRefClkSel ) { return ; } } XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_TX_FREQ , 0 ) ; if ( ( InstancePtr -> Config . UseGtAsTxTmdsClk == TRUE ) && ( ( InstancePtr -> TxHdmi21Cfg . IsEnabled == 0 ) || ( InstancePtr -> TxHdmi21Cfg . IsEnabled == 1 && InstancePtr -> TxHdmi21Cfg . NChannels == 3 ) ) ) { XHdmiphy1_PatgenEnable ( InstancePtr , 0 , FALSE ) ; } PllType = XHdmiphy1_GetPllType ( InstancePtr , 0 , XHDMIPHY1_DIR_TX , XHDMIPHY1_CHANNEL_ID_CH1 ) ; #if ( XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5 ) XHdmiphy1_PowerDownGtPll ( InstancePtr , 0 , ( PllType == XHDMIPHY1_PLL_TYPE_CPLL ) ? XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA , TRUE ) ; XHdmiphy1_ResetGtPll ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_TX , TRUE ) ; #else PllType = PllType ; XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_TX_INIT_REG , ( XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_TX_INIT_REG ) | 0x10101010 ) ) ; #endif XHdmiphy1_MmcmLockedMaskEnable ( InstancePtr , 0 , XHDMIPHY1_DIR_TX , TRUE ) ; XHdmiphy1_ClkDetTimerClear ( InstancePtr , 0 , XHDMIPHY1_DIR_TX ) ; #if ( XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5 ) XHdmiphy1_TxAlignStart ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , FALSE ) ; #endif XHdmiphy1_Ch2Ids ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . TxState = XHDMIPHY1_GT_STATE_IDLE ; } if ( XHdmiphy1_ClkDetGetRefClkFreqHz ( InstancePtr , XHDMIPHY1_DIR_TX ) ) { XHdmiphy1_ClkDetTimerLoad ( InstancePtr , 0 , XHDMIPHY1_DIR_TX , InstancePtr -> Config . AxiLiteClkFreq / 1000 ) ; } if ( InstancePtr -> HdmiTxInitCallback ) { InstancePtr -> HdmiTxInitCallback ( InstancePtr -> HdmiTxInitRef ) ; } }
This function is the handler for events triggered by a change in TX frequency
as detected by the HDMI clock detector logic.
This function is the handler for events triggered by a change in TX frequency as detected by the HDMI clock detector logic .
/* Set TX TMDS Clock Pattern Generator */ /* Determine PLL type. */ /* If the TX frequency has changed, the PLL is always disabled. */ /* Suppress Warning Messages */ /* Mask RESET DONE */ /* Deassert TX LNKRDY MASK */ /* Mask the MMCM Lock */ /* Disable TX MMCM. */ /* XHdmiphy1_MmcmPowerDown(InstancePtr, 0, XHDMIPHY1_DIR_TX, TRUE); */ /* Clear TX timer. */ /* Clear GT alignment. */ /* If there is no reference clock, load TX timer in usec. */ /* Callback to re-initialize. */