XilinxProcessorIPLib/drivers/vphy/src/xvphy_hdmi_intr.c
void XVphy_HdmiRxClkDetFreqChangeHandler(XVphy *InstancePtr)
{
	XVphy_PllType PllType;
	u32 RxRefClkHz;
	u8 Id, Id0, Id1;

	XVphy_LogWrite(InstancePtr, XVPHY_LOG_EVT_RX_FREQ, 0);

	XVphy_Ch2Ids(InstancePtr, XVPHY_CHANNEL_ID_CHA, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		InstancePtr->Quads[0].Plls[XVPHY_CH2IDX(Id)].RxState =
			XVPHY_GT_STATE_IDLE;
	}

	/* Mask the MMCM Lock */
	XVphy_MmcmLockedMaskEnable(InstancePtr, 0, XVPHY_DIR_RX, TRUE);

	/* Determine PLL type and RX reference clock selection. */
	PllType = XVphy_GetPllType(InstancePtr, 0, XVPHY_DIR_RX,
			XVPHY_CHANNEL_ID_CH1);

	/* Fetch New RX Reference Clock Frequency */
	RxRefClkHz = XVphy_ClkDetGetRefClkFreqHz(InstancePtr, XVPHY_DIR_RX);

	/* Round input frequency to 10 kHz. */
	RxRefClkHz = (RxRefClkHz+5000) / 10000;
	RxRefClkHz = RxRefClkHz * 10000;

	/* Store RX reference clock. */
	InstancePtr->HdmiRxRefClkHz = RxRefClkHz;

	/* If the RX frequency has changed, the PLL is always disabled. */
	if (InstancePtr->Config.XcvrType != XVPHY_GT_TYPE_GTPE2) {
		XVphy_PowerDownGtPll(InstancePtr, 0,
			(PllType == XVPHY_PLL_TYPE_CPLL) ?
			XVPHY_CHANNEL_ID_CHA : XVPHY_CHANNEL_ID_CMNA, TRUE);
	}

	XVphy_ResetGtPll(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX,
			TRUE);

	/* When the GT TX and RX are coupled, then disable the QPLL. */
	if (XVphy_IsBonded(InstancePtr, 0, XVPHY_CHANNEL_ID_CH1)) {
		/* Mask the MMCM Lock */
		XVphy_MmcmLockedMaskEnable(InstancePtr, 0, XVPHY_DIR_TX, TRUE);
		XVphy_PowerDownGtPll(InstancePtr, 0,
			(PllType == XVPHY_PLL_TYPE_CPLL) ?
			XVPHY_CHANNEL_ID_CMNA : XVPHY_CHANNEL_ID_CHA, TRUE);
		XVphy_ResetGtPll(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
			XVPHY_DIR_TX, 1);
		XVphy_ResetGtTxRx(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_TX, TRUE);
	}

	/* Assert GT RX reset */
	if ((InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTXE2) ||
	    (InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTPE2)) {
		XVphy_ResetGtTxRx(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_RX, FALSE);
	}

	/* If DRU is present, disable it and assert reset. */
	if (InstancePtr->Config.DruIsPresent) {
		XVphy_DruReset(InstancePtr, XVPHY_CHANNEL_ID_CHA, TRUE);
		XVphy_DruEnable(InstancePtr, XVPHY_CHANNEL_ID_CHA, FALSE);
	}

	/* Clear RX timer. */
	XVphy_ClkDetTimerClear(InstancePtr, 0, XVPHY_DIR_RX);

	/* If there is reference clock, load RX timer in usec.
	 * The reference clock should be larger than 25Mhz. We are using a 20Mhz
	 * instead to keep some margin for errors. */
	if (RxRefClkHz > 20000000) {
		XVphy_ClkDetTimerLoad(InstancePtr, 0, XVPHY_DIR_RX,
						InstancePtr->Config.AxiLiteClkFreq/1000);

		/* Callback to re-initialize. */
		if (InstancePtr->HdmiRxInitCallback) {
			InstancePtr->HdmiRxInitCallback(InstancePtr->HdmiRxInitRef);
		}
	}
}
/*****************************************************************************/
/**
* This function is the handler for events triggered by a change in RX frequency
* as detected by the HDMI clock detector logic.
*
* @param	InstancePtr is a pointer to the VPHY instance.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function is the handler for events triggered by a change in RX frequency
as detected by the HDMI clock detector logic.
This function is the handler for events triggered by a change in RX frequency as detected by the HDMI clock detector logic .
void XVphy_HdmiRxClkDetFreqChangeHandler(XVphy *InstancePtr)
{
	XVphy_PllType PllType;
	u32 RxRefClkHz;
	u8 Id, Id0, Id1;
	XVphy_LogWrite(InstancePtr, XVPHY_LOG_EVT_RX_FREQ, 0);
	XVphy_Ch2Ids(InstancePtr, XVPHY_CHANNEL_ID_CHA, &Id0, &Id1);
	for (Id = Id0; Id <= Id1; Id++) {
		InstancePtr->Quads[0].Plls[XVPHY_CH2IDX(Id)].RxState =
			XVPHY_GT_STATE_IDLE;
	}
	XVphy_MmcmLockedMaskEnable(InstancePtr, 0, XVPHY_DIR_RX, TRUE);
	PllType = XVphy_GetPllType(InstancePtr, 0, XVPHY_DIR_RX,
			XVPHY_CHANNEL_ID_CH1);
	RxRefClkHz = XVphy_ClkDetGetRefClkFreqHz(InstancePtr, XVPHY_DIR_RX);
	RxRefClkHz = (RxRefClkHz+5000) / 10000;
	RxRefClkHz = RxRefClkHz * 10000;
	InstancePtr->HdmiRxRefClkHz = RxRefClkHz;
	if (InstancePtr->Config.XcvrType != XVPHY_GT_TYPE_GTPE2) {
		XVphy_PowerDownGtPll(InstancePtr, 0,
			(PllType == XVPHY_PLL_TYPE_CPLL) ?
			XVPHY_CHANNEL_ID_CHA : XVPHY_CHANNEL_ID_CMNA, TRUE);
	}
	XVphy_ResetGtPll(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA, XVPHY_DIR_RX,
			TRUE);
	if (XVphy_IsBonded(InstancePtr, 0, XVPHY_CHANNEL_ID_CH1)) {
		XVphy_MmcmLockedMaskEnable(InstancePtr, 0, XVPHY_DIR_TX, TRUE);
		XVphy_PowerDownGtPll(InstancePtr, 0,
			(PllType == XVPHY_PLL_TYPE_CPLL) ?
			XVPHY_CHANNEL_ID_CMNA : XVPHY_CHANNEL_ID_CHA, TRUE);
		XVphy_ResetGtPll(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
			XVPHY_DIR_TX, 1);
		XVphy_ResetGtTxRx(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_TX, TRUE);
	}
	if ((InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTXE2) ||
	    (InstancePtr->Config.XcvrType == XVPHY_GT_TYPE_GTPE2)) {
		XVphy_ResetGtTxRx(InstancePtr, 0, XVPHY_CHANNEL_ID_CHA,
				XVPHY_DIR_RX, FALSE);
	}
	if (InstancePtr->Config.DruIsPresent) {
		XVphy_DruReset(InstancePtr, XVPHY_CHANNEL_ID_CHA, TRUE);
		XVphy_DruEnable(InstancePtr, XVPHY_CHANNEL_ID_CHA, FALSE);
	}
	XVphy_ClkDetTimerClear(InstancePtr, 0, XVPHY_DIR_RX);
	if (RxRefClkHz > 20000000) {
		XVphy_ClkDetTimerLoad(InstancePtr, 0, XVPHY_DIR_RX,
						InstancePtr->Config.AxiLiteClkFreq/1000);
		if (InstancePtr->HdmiRxInitCallback) {
			InstancePtr->HdmiRxInitCallback(InstancePtr->HdmiRxInitRef);
		}
	}
}
void XVphy_HdmiRxClkDetFreqChangeHandler ( XVphy * InstancePtr ) { XVphy_PllType PllType ; u32 RxRefClkHz ; u8 Id , Id0 , Id1 ; XVphy_LogWrite ( InstancePtr , XVPHY_LOG_EVT_RX_FREQ , 0 ) ; XVphy_Ch2Ids ( InstancePtr , XVPHY_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XVPHY_CH2IDX ( Id ) ] . RxState = XVPHY_GT_STATE_IDLE ; } XVphy_MmcmLockedMaskEnable ( InstancePtr , 0 , XVPHY_DIR_RX , TRUE ) ; PllType = XVphy_GetPllType ( InstancePtr , 0 , XVPHY_DIR_RX , XVPHY_CHANNEL_ID_CH1 ) ; RxRefClkHz = XVphy_ClkDetGetRefClkFreqHz ( InstancePtr , XVPHY_DIR_RX ) ; RxRefClkHz = ( RxRefClkHz + 5000 ) / 10000 ; RxRefClkHz = RxRefClkHz * 10000 ; InstancePtr -> HdmiRxRefClkHz = RxRefClkHz ; if ( InstancePtr -> Config . XcvrType != XVPHY_GT_TYPE_GTPE2 ) { XVphy_PowerDownGtPll ( InstancePtr , 0 , ( PllType == XVPHY_PLL_TYPE_CPLL ) ? XVPHY_CHANNEL_ID_CHA : XVPHY_CHANNEL_ID_CMNA , TRUE ) ; } XVphy_ResetGtPll ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX , TRUE ) ; if ( XVphy_IsBonded ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CH1 ) ) { XVphy_MmcmLockedMaskEnable ( InstancePtr , 0 , XVPHY_DIR_TX , TRUE ) ; XVphy_PowerDownGtPll ( InstancePtr , 0 , ( PllType == XVPHY_PLL_TYPE_CPLL ) ? XVPHY_CHANNEL_ID_CMNA : XVPHY_CHANNEL_ID_CHA , TRUE ) ; XVphy_ResetGtPll ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_TX , 1 ) ; XVphy_ResetGtTxRx ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_TX , TRUE ) ; } if ( ( InstancePtr -> Config . XcvrType == XVPHY_GT_TYPE_GTXE2 ) || ( InstancePtr -> Config . XcvrType == XVPHY_GT_TYPE_GTPE2 ) ) { XVphy_ResetGtTxRx ( InstancePtr , 0 , XVPHY_CHANNEL_ID_CHA , XVPHY_DIR_RX , FALSE ) ; } if ( InstancePtr -> Config . DruIsPresent ) { XVphy_DruReset ( InstancePtr , XVPHY_CHANNEL_ID_CHA , TRUE ) ; XVphy_DruEnable ( InstancePtr , XVPHY_CHANNEL_ID_CHA , FALSE ) ; } XVphy_ClkDetTimerClear ( InstancePtr , 0 , XVPHY_DIR_RX ) ; if ( RxRefClkHz > 20000000 ) { XVphy_ClkDetTimerLoad ( InstancePtr , 0 , XVPHY_DIR_RX , InstancePtr -> Config . AxiLiteClkFreq / 1000 ) ; if ( InstancePtr -> HdmiRxInitCallback ) { InstancePtr -> HdmiRxInitCallback ( InstancePtr -> HdmiRxInitRef ) ; } } }
This function is the handler for events triggered by a change in RX frequency
as detected by the HDMI clock detector logic.
This function is the handler for events triggered by a change in RX frequency as detected by the HDMI clock detector logic .
/* Mask the MMCM Lock */ /* Determine PLL type and RX reference clock selection. */ /* Fetch New RX Reference Clock Frequency */ /* Round input frequency to 10 kHz. */ /* Store RX reference clock. */ /* If the RX frequency has changed, the PLL is always disabled. */ /* When the GT TX and RX are coupled, then disable the QPLL. */ /* Mask the MMCM Lock */ /* Assert GT RX reset */ /* If DRU is present, disable it and assert reset. */ /* Clear RX timer. */ /* If there is reference clock, load RX timer in usec.
	 * The reference clock should be larger than 25Mhz. We are using a 20Mhz
	 * instead to keep some margin for errors. */ /* Callback to re-initialize. */