lib/bsp/standalone/src/arm/ARMv8/32bit/xil_cache.c
void Xil_ICacheInvalidate(void)
{
	unsigned int currmask;

	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);
	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x1);
	dsb();
	/* invalidate the instruction cache */
	mtcp(XREG_CP15_INVAL_IC_POU, 0x0);
	/* Wait for invalidate to complete */
	dsb();
	mtcpsr(currmask);
}
/****************************************************************************/
/**
 * @brief	Invalidate the entire instruction cache.
 *
 * @return	None.
 *
 ****************************************************************************/
@brief       Invalidate the entire instruction cache.
@return      None.
@brief Invalidate the entire instruction cache . @return None .
void Xil_ICacheInvalidate(void)
{
	unsigned int currmask;
	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);
	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x1);
	dsb();
	mtcp(XREG_CP15_INVAL_IC_POU, 0x0);
	dsb();
	mtcpsr(currmask);
}
void Xil_ICacheInvalidate ( void ) { unsigned int currmask ; currmask = mfcpsr ( ) ; mtcpsr ( currmask | IRQ_FIQ_MASK ) ; mtcp ( XREG_CP15_CACHE_SIZE_SEL , 0x1 ) ; dsb ( ) ; mtcp ( XREG_CP15_INVAL_IC_POU , 0x0 ) ; dsb ( ) ; mtcpsr ( currmask ) ; }
@brief       Invalidate the entire instruction cache.
@brief Invalidate the entire instruction cache .
/* invalidate the instruction cache */ /* Wait for invalidate to complete */