lib/sw_apps/zynqmp_fsbl/src/xfsbl_ddr_init.c
u32 XFsbl_DdrInit(void)
{
	u32 Status;
	u8 SpdData[512U];
#if !(defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
	|| defined(XPS_BOARD_ZCU111) || defined(XPS_BOARD_ZCU216) \
	|| defined(XPS_BOARD_ZCU208)) || defined(XFSBL_ENABLE_DDR_SR)
	u32 RegVal;
#endif

	/* Define and Initialize the DDR Initialization data */
	struct DdrcInitData DdrData = {
		.AddrMapCsBit0 = 0x0U,
		.AddrMapRowBits2To10 = 0x0U,
	};

	/* Get the Model Part Number from the SPD stored in EEPROM */
	Status = XFsbl_IicReadSpdEeprom(SpdData);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}

#if defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
	|| defined(XPS_BOARD_ZCU111) || defined(XPS_BOARD_ZCU216) \
	|| defined(XPS_BOARD_ZCU208)
	/* ZCU102, ZCU106 and ZCU111, ZCU216 and ZCU208 Boards have support
	 * only for DDR4 DIMMs. Skip checking for DDR type for these boards.
	 */
	Status = XFsbl_Ddr4Init(SpdData, &DdrData);
	if (XFSBL_SUCCESS != Status) {
		Status = XFSBL_FAILURE;
		goto END;
	}
#else
	/* Determine the DIMM parameters to be used for register writes */
	Status = XFsbl_DdrComputeDimmParameters(SpdData, &DdrData);
	if (Status != XFSBL_SUCCESS) {
		goto END;
	}

	/* Initialize the Parameters with their default values */
	XFsbl_InitilizeDdrParams(&DdrData);

	/* Assert Reset for DDR controller */
	RegVal = Xil_In32(CRF_APB_RST_DDR_SS_OFFSET);
	RegVal |= 0x00000008U;
	Xil_Out32(CRF_APB_RST_DDR_SS_OFFSET, RegVal);

	/* Calculate and Write all the registers of DDR Controller */
	Status = XFsbl_DdrcRegsInit(&DdrData);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}

	/* De-assert Reset for DDR controller */
	RegVal = Xil_In32(CRF_APB_RST_DDR_SS_OFFSET);
	RegVal &= ~0x0000000CU;
	Xil_Out32(CRF_APB_RST_DDR_SS_OFFSET, RegVal);

	/* Calculate and Write all the registers of DDR-PHY Controller */
	Status = XFsbl_PhyRegsInit(&DdrData);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}
#endif

#ifdef XFSBL_ENABLE_DDR_SR
	/* Check if DDR is in self refresh mode */
	RegVal = Xil_In32(XFSBL_DDR_STATUS_REGISTER_OFFSET) &
		DDR_STATUS_FLAG_MASK;
	if (!RegVal) {
		/* Execute the Training Sequence */
		Status = XFsbl_DdrcPhyTraining(&DdrData);
		if (Status != XFSBL_SUCCESS) {
			Status = XFSBL_FAILURE;
			goto END;
		}
	}
#else
	/* Execute the Training Sequence */
	Status = XFsbl_DdrcPhyTraining(&DdrData);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}
#endif

	Status = XFSBL_SUCCESS;
END:
	return Status;
}
/*****************************************************************************/
/**
 * This function checks for the DDR SPD data and Initializes the same based on
 * configuration parameters obtained from SPD data.
 *
 * @param	None
 *
 * @return	returns the error codes described in xfsbl_error.h on any error
 *			returns XFSBL_SUCCESS on success
 *
 *****************************************************************************/
This function checks for the DDR SPD data and Initializes the same based on
configuration parameters obtained from SPD data.

@param       None

@return      returns the error codes described in xfsbl_error.h on any error
returns XFSBL_SUCCESS on success
This function checks for the DDR SPD data and Initializes the same based on configuration parameters obtained from SPD data . @param None @return returns the error codes described in xfsbl_error . h on any error returns XFSBL_SUCCESS on success
u32 XFsbl_DdrInit(void)
{
	u32 Status;
	u8 SpdData[512U];
#if !(defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
	|| defined(XPS_BOARD_ZCU111) || defined(XPS_BOARD_ZCU216) \
	|| defined(XPS_BOARD_ZCU208)) || defined(XFSBL_ENABLE_DDR_SR)
	u32 RegVal;
#endif
	struct DdrcInitData DdrData = {
		.AddrMapCsBit0 = 0x0U,
		.AddrMapRowBits2To10 = 0x0U,
	};
	Status = XFsbl_IicReadSpdEeprom(SpdData);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}
#if defined(XPS_BOARD_ZCU102) || defined(XPS_BOARD_ZCU106) \
	|| defined(XPS_BOARD_ZCU111) || defined(XPS_BOARD_ZCU216) \
	|| defined(XPS_BOARD_ZCU208)
	Status = XFsbl_Ddr4Init(SpdData, &DdrData);
	if (XFSBL_SUCCESS != Status) {
		Status = XFSBL_FAILURE;
		goto END;
	}
#else
	Status = XFsbl_DdrComputeDimmParameters(SpdData, &DdrData);
	if (Status != XFSBL_SUCCESS) {
		goto END;
	}
	XFsbl_InitilizeDdrParams(&DdrData);
	RegVal = Xil_In32(CRF_APB_RST_DDR_SS_OFFSET);
	RegVal |= 0x00000008U;
	Xil_Out32(CRF_APB_RST_DDR_SS_OFFSET, RegVal);
	Status = XFsbl_DdrcRegsInit(&DdrData);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}
	RegVal = Xil_In32(CRF_APB_RST_DDR_SS_OFFSET);
	RegVal &= ~0x0000000CU;
	Xil_Out32(CRF_APB_RST_DDR_SS_OFFSET, RegVal);
	Status = XFsbl_PhyRegsInit(&DdrData);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}
#endif
#ifdef XFSBL_ENABLE_DDR_SR
	RegVal = Xil_In32(XFSBL_DDR_STATUS_REGISTER_OFFSET) &
		DDR_STATUS_FLAG_MASK;
	if (!RegVal) {
		Status = XFsbl_DdrcPhyTraining(&DdrData);
		if (Status != XFSBL_SUCCESS) {
			Status = XFSBL_FAILURE;
			goto END;
		}
	}
#else
	Status = XFsbl_DdrcPhyTraining(&DdrData);
	if (Status != XFSBL_SUCCESS) {
		Status = XFSBL_FAILURE;
		goto END;
	}
#endif
	Status = XFSBL_SUCCESS;
END:
	return Status;
}
u32 XFsbl_DdrInit ( void ) { u32 Status ; u8 SpdData [ 512U ] ; #if ! ( defined ( XPS_BOARD_ZCU102 ) || defined ( XPS_BOARD_ZCU106 ) || defined ( XPS_BOARD_ZCU111 ) || defined ( XPS_BOARD_ZCU216 ) || defined ( XPS_BOARD_ZCU208 ) ) || defined ( XFSBL_ENABLE_DDR_SR ) u32 RegVal ; #endif struct DdrcInitData DdrData = { . AddrMapCsBit0 = 0x0U , . AddrMapRowBits2To10 = 0x0U , } ; Status = XFsbl_IicReadSpdEeprom ( SpdData ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } #if defined ( XPS_BOARD_ZCU102 ) || defined ( XPS_BOARD_ZCU106 ) || defined ( XPS_BOARD_ZCU111 ) || defined ( XPS_BOARD_ZCU216 ) || defined ( XPS_BOARD_ZCU208 ) Status = XFsbl_Ddr4Init ( SpdData , & DdrData ) ; if ( XFSBL_SUCCESS != Status ) { Status = XFSBL_FAILURE ; goto END ; } #else Status = XFsbl_DdrComputeDimmParameters ( SpdData , & DdrData ) ; if ( Status != XFSBL_SUCCESS ) { goto END ; } XFsbl_InitilizeDdrParams ( & DdrData ) ; RegVal = Xil_In32 ( CRF_APB_RST_DDR_SS_OFFSET ) ; RegVal |= 0x00000008U ; Xil_Out32 ( CRF_APB_RST_DDR_SS_OFFSET , RegVal ) ; Status = XFsbl_DdrcRegsInit ( & DdrData ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } RegVal = Xil_In32 ( CRF_APB_RST_DDR_SS_OFFSET ) ; RegVal &= ~ 0x0000000CU ; Xil_Out32 ( CRF_APB_RST_DDR_SS_OFFSET , RegVal ) ; Status = XFsbl_PhyRegsInit ( & DdrData ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } #endif #ifdef XFSBL_ENABLE_DDR_SR RegVal = Xil_In32 ( XFSBL_DDR_STATUS_REGISTER_OFFSET ) & DDR_STATUS_FLAG_MASK ; if ( ! RegVal ) { Status = XFsbl_DdrcPhyTraining ( & DdrData ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } } #else Status = XFsbl_DdrcPhyTraining ( & DdrData ) ; if ( Status != XFSBL_SUCCESS ) { Status = XFSBL_FAILURE ; goto END ; } #endif Status = XFSBL_SUCCESS ; END : return Status ; }
This function checks for the DDR SPD data and Initializes the same based on
 configuration parameters obtained from SPD data.
This function checks for the DDR SPD data and Initializes the same based on configuration parameters obtained from SPD data .
/* Define and Initialize the DDR Initialization data */ /* Get the Model Part Number from the SPD stored in EEPROM */ /* ZCU102, ZCU106 and ZCU111, ZCU216 and ZCU208 Boards have support
	 * only for DDR4 DIMMs. Skip checking for DDR type for these boards.
	 */ /* Determine the DIMM parameters to be used for register writes */ /* Initialize the Parameters with their default values */ /* Assert Reset for DDR controller */ /* Calculate and Write all the registers of DDR Controller */ /* De-assert Reset for DDR controller */ /* Calculate and Write all the registers of DDR-PHY Controller */ /* Check if DDR is in self refresh mode */ /* Execute the Training Sequence */ /* Execute the Training Sequence */