XilinxProcessorIPLib/drivers/vphy/src/xvphy_gtpe2.c
u32 XVphy_Gtpe2RxPllRefClkDiv1Reconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId ChId)
{
	u16 DrpVal;
	u32 RxRefClkHz;
	XVphy_Channel *CmnPtr;
	XVphy_ChannelId CmnId;
	XVphy_PllType PllType;
    u32 Status = XST_SUCCESS;

	if (XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX)) {
		RxRefClkHz = InstancePtr->HdmiRxRefClkHz;
	}
	else {
		PllType = XVphy_GetPllType(InstancePtr, QuadId, XVPHY_DIR_RX, ChId);
		CmnId = XVphy_GetRcfgChId(InstancePtr, QuadId, XVPHY_DIR_RX, PllType);
		CmnPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(CmnId)];
		RxRefClkHz = XVphy_GetQuadRefClkFreq(InstancePtr, QuadId,
								CmnPtr->PllRefClkSel);
	}

	Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, XVPHY_DRP_RXDATAWIDTH,
                &DrpVal);
	DrpVal &= ~(0x07C0);
	DrpVal |= XVphy_DrpEncodeClk25(RxRefClkHz) << 6;
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, XVPHY_DRP_RXDATAWIDTH,
                DrpVal);
	return Status;
}
/*****************************************************************************/
/**
* This function will configure the channel's RX CLKDIV1 settings.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
*
* @return
*		- XST_SUCCESS if the configuration was successful.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function will configure the channel's RX CLKDIV1 settings.
This function will configure the channel ' s RX CLKDIV1 settings .
u32 XVphy_Gtpe2RxPllRefClkDiv1Reconfig(XVphy *InstancePtr, u8 QuadId,
		XVphy_ChannelId ChId)
{
	u16 DrpVal;
	u32 RxRefClkHz;
	XVphy_Channel *CmnPtr;
	XVphy_ChannelId CmnId;
	XVphy_PllType PllType;
    u32 Status = XST_SUCCESS;
	if (XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX)) {
		RxRefClkHz = InstancePtr->HdmiRxRefClkHz;
	}
	else {
		PllType = XVphy_GetPllType(InstancePtr, QuadId, XVPHY_DIR_RX, ChId);
		CmnId = XVphy_GetRcfgChId(InstancePtr, QuadId, XVPHY_DIR_RX, PllType);
		CmnPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(CmnId)];
		RxRefClkHz = XVphy_GetQuadRefClkFreq(InstancePtr, QuadId,
								CmnPtr->PllRefClkSel);
	}
	Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, XVPHY_DRP_RXDATAWIDTH,
                &DrpVal);
	DrpVal &= ~(0x07C0);
	DrpVal |= XVphy_DrpEncodeClk25(RxRefClkHz) << 6;
	Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, XVPHY_DRP_RXDATAWIDTH,
                DrpVal);
	return Status;
}
u32 XVphy_Gtpe2RxPllRefClkDiv1Reconfig ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId ChId ) { u16 DrpVal ; u32 RxRefClkHz ; XVphy_Channel * CmnPtr ; XVphy_ChannelId CmnId ; XVphy_PllType PllType ; u32 Status = XST_SUCCESS ; if ( XVphy_IsHDMI ( InstancePtr , XVPHY_DIR_RX ) ) { RxRefClkHz = InstancePtr -> HdmiRxRefClkHz ; } else { PllType = XVphy_GetPllType ( InstancePtr , QuadId , XVPHY_DIR_RX , ChId ) ; CmnId = XVphy_GetRcfgChId ( InstancePtr , QuadId , XVPHY_DIR_RX , PllType ) ; CmnPtr = & InstancePtr -> Quads [ QuadId ] . Plls [ XVPHY_CH2IDX ( CmnId ) ] ; RxRefClkHz = XVphy_GetQuadRefClkFreq ( InstancePtr , QuadId , CmnPtr -> PllRefClkSel ) ; } Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , XVPHY_DRP_RXDATAWIDTH , & DrpVal ) ; DrpVal &= ~ ( 0x07C0 ) ; DrpVal |= XVphy_DrpEncodeClk25 ( RxRefClkHz ) << 6 ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , XVPHY_DRP_RXDATAWIDTH , DrpVal ) ; return Status ; }
This function will configure the channel's RX CLKDIV1 settings.
This function will configure the channel ' s RX CLKDIV1 settings .