lib/sw_apps/zynqmp_fsbl/src/xfsbl_ddr_init.c
u32 XFsbl_ComputeLpDdrParams(u8 *SpdData, struct DdrcInitData *DdrDataPtr)
{
	struct LpDdrSpdEeprom *LpDdrSpdData = (struct LpDdrSpdEeprom *)SpdData;
	XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;

	memset(PDimmPtr->Mpart, 0U, sizeof(PDimmPtr->Mpart));
	if ((LpDdrSpdData->InfoSizeCrc & 0xFU) > 2U)
		memcpy(PDimmPtr->Mpart, LpDdrSpdData->Mpart, sizeof(PDimmPtr->Mpart) - 1U);

	PDimmPtr->MemType = LpDdrSpdData->MemType;
	PDimmPtr->NRanks = ((LpDdrSpdData->Organization >> 3U) & 0x7U) + 1U;
	PDimmPtr->RankDensity = XFsbl_ComputeLpDdrRankSize(LpDdrSpdData);
	PDimmPtr->Capacity = (PDimmPtr->NRanks * PDimmPtr->RankDensity) / (1024U * 1024U);
	PDimmPtr->BusWidth = 1U << (3U + (LpDdrSpdData->BusWidth & 0x7U));
	if ((LpDdrSpdData->BusWidth >> 3U) & 0x3U)
		PDimmPtr->EccBusWidth = 8U;
	else
		PDimmPtr->EccBusWidth = 0U;
	PDimmPtr->DramWidth = 1U << ((LpDdrSpdData->Organization & 0x7U) + 2U);

	PDimmPtr->AddrMirror = 0U;
	PDimmPtr->RDimm = 0U;

	PDimmPtr->NumRowAddr = ((LpDdrSpdData->Addressing >> 3U) & 0x7U) + 12U;
	PDimmPtr->NumColAddr = (LpDdrSpdData->Addressing & 0x7U) + 9U;
	PDimmPtr->NumBankAddr = ((LpDdrSpdData->DensityBanks >> 4U) & 0x3U) + 2U;
	PDimmPtr->NumBgAddr = (LpDdrSpdData->DensityBanks >> 6U) & 0x3U;
	PDimmPtr->NumRankAddr = XFsbl_GetLog2(PDimmPtr->NRanks);

	PDimmPtr->BurstLength = 8U;
	PDimmPtr->RowDensity = XFsbl_GetLog2(PDimmPtr->RankDensity);

	if ((LpDdrSpdData->Timebases & 0xFU) == 0x0U) {
		PDimmPtr->MtbPs = 125U;
		PDimmPtr->Ftb10thPs = 10U;
	}

	PDimmPtr->TckminXPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TckMin, LpDdrSpdData->FineTckMin);

	PDimmPtr->SpeedBin = (u32)XFsbl_Ceil(2000000.0 / PDimmPtr->TckminXPs);

	PDimmPtr->FreqMhz = 1000000.0 / PDimmPtr->TckminXPs;

	PDimmPtr->ClockPeriod = PDimmPtr->TckminXPs / 1000.0;

	PDimmPtr->TckmaxPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TckMax, LpDdrSpdData->FineTckMax);

	PDimmPtr->CaslatX  = (LpDdrSpdData->CaslatB1 << 7U)	|
		(LpDdrSpdData->CaslatB2 << 15U)	|
		(LpDdrSpdData->CaslatB3 << 23U);

	PDimmPtr->TaaPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TaaMin, LpDdrSpdData->FineTaaMin);

	PDimmPtr->CasLatency = (u32)XFsbl_Ceil(PDimmPtr->TaaPs / 1000.0) + 1U;

	PDimmPtr->CasWriteLatency = XFsbl_Ceil(PDimmPtr->TaaPs / 1000.0);

	PDimmPtr->TRcdPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TrcdMin, LpDdrSpdData->FineTrcdMin);

	PDimmPtr->TrpabPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TrpabMin, LpDdrSpdData->FineTrpabMin);
	PDimmPtr->TrppbPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TrppbMin, LpDdrSpdData->FineTrppbMin);

	PDimmPtr->TRfcAbPs = ((LpDdrSpdData->TrfcabMinMsb << 8U) |
			(LpDdrSpdData->TrfcabMinLsb)) *
		PDimmPtr->MtbPs;
	PDimmPtr->TRfcPbPs = ((LpDdrSpdData->TrfcpbMinMsb << 8U) |
			(LpDdrSpdData->TrfcpbMinLsb)) *
		PDimmPtr->MtbPs;

	if ((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) ||
			((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) &&
			 (PDimmPtr->Capacity != 1024U))) {
		PDimmPtr->TRefi = 3900000U;
	} else {
		PDimmPtr->TRefi = 7800000U;
	}

	return XFSBL_SUCCESS;
}
/*****************************************************************************/
/**
 * This function computes DIMM parameters based upon the SPD information in
 * LpDdrSpdData. Writes the results to the XFsbl_DimmParams structure pointed
 * by PDimmPtr.
 *
 * @param	DdrDataPtr is pointer to DDR Initialization Data Structure
 * @param	SpdData is the array containing the SPD data from DIMM EEPROM
 *
 * @return	XFSBL_SUCCESS or XFSBL_FAILURE
 *
 *****************************************************************************/
This function computes DIMM parameters based upon the SPD information in
LpDdrSpdData. Writes the results to the XFsbl_DimmParams structure pointed
by PDimmPtr.

@param       DdrDataPtr is pointer to DDR Initialization Data Structure
@param       SpdData is the array containing the SPD data from DIMM EEPROM


This function computes DIMM parameters based upon the SPD information in LpDdrSpdData . Writes the results to the XFsbl_DimmParams structure pointed by PDimmPtr . @param DdrDataPtr is pointer to DDR Initialization Data Structure @param SpdData is the array containing the SPD data from DIMM EEPROM
u32 XFsbl_ComputeLpDdrParams(u8 *SpdData, struct DdrcInitData *DdrDataPtr)
{
	struct LpDdrSpdEeprom *LpDdrSpdData = (struct LpDdrSpdEeprom *)SpdData;
	XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
	memset(PDimmPtr->Mpart, 0U, sizeof(PDimmPtr->Mpart));
	if ((LpDdrSpdData->InfoSizeCrc & 0xFU) > 2U)
		memcpy(PDimmPtr->Mpart, LpDdrSpdData->Mpart, sizeof(PDimmPtr->Mpart) - 1U);
	PDimmPtr->MemType = LpDdrSpdData->MemType;
	PDimmPtr->NRanks = ((LpDdrSpdData->Organization >> 3U) & 0x7U) + 1U;
	PDimmPtr->RankDensity = XFsbl_ComputeLpDdrRankSize(LpDdrSpdData);
	PDimmPtr->Capacity = (PDimmPtr->NRanks * PDimmPtr->RankDensity) / (1024U * 1024U);
	PDimmPtr->BusWidth = 1U << (3U + (LpDdrSpdData->BusWidth & 0x7U));
	if ((LpDdrSpdData->BusWidth >> 3U) & 0x3U)
		PDimmPtr->EccBusWidth = 8U;
	else
		PDimmPtr->EccBusWidth = 0U;
	PDimmPtr->DramWidth = 1U << ((LpDdrSpdData->Organization & 0x7U) + 2U);
	PDimmPtr->AddrMirror = 0U;
	PDimmPtr->RDimm = 0U;
	PDimmPtr->NumRowAddr = ((LpDdrSpdData->Addressing >> 3U) & 0x7U) + 12U;
	PDimmPtr->NumColAddr = (LpDdrSpdData->Addressing & 0x7U) + 9U;
	PDimmPtr->NumBankAddr = ((LpDdrSpdData->DensityBanks >> 4U) & 0x3U) + 2U;
	PDimmPtr->NumBgAddr = (LpDdrSpdData->DensityBanks >> 6U) & 0x3U;
	PDimmPtr->NumRankAddr = XFsbl_GetLog2(PDimmPtr->NRanks);
	PDimmPtr->BurstLength = 8U;
	PDimmPtr->RowDensity = XFsbl_GetLog2(PDimmPtr->RankDensity);
	if ((LpDdrSpdData->Timebases & 0xFU) == 0x0U) {
		PDimmPtr->MtbPs = 125U;
		PDimmPtr->Ftb10thPs = 10U;
	}
	PDimmPtr->TckminXPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TckMin, LpDdrSpdData->FineTckMin);
	PDimmPtr->SpeedBin = (u32)XFsbl_Ceil(2000000.0 / PDimmPtr->TckminXPs);
	PDimmPtr->FreqMhz = 1000000.0 / PDimmPtr->TckminXPs;
	PDimmPtr->ClockPeriod = PDimmPtr->TckminXPs / 1000.0;
	PDimmPtr->TckmaxPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TckMax, LpDdrSpdData->FineTckMax);
	PDimmPtr->CaslatX  = (LpDdrSpdData->CaslatB1 << 7U)	|
		(LpDdrSpdData->CaslatB2 << 15U)	|
		(LpDdrSpdData->CaslatB3 << 23U);
	PDimmPtr->TaaPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TaaMin, LpDdrSpdData->FineTaaMin);
	PDimmPtr->CasLatency = (u32)XFsbl_Ceil(PDimmPtr->TaaPs / 1000.0) + 1U;
	PDimmPtr->CasWriteLatency = XFsbl_Ceil(PDimmPtr->TaaPs / 1000.0);
	PDimmPtr->TRcdPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TrcdMin, LpDdrSpdData->FineTrcdMin);
	PDimmPtr->TrpabPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TrpabMin, LpDdrSpdData->FineTrpabMin);
	PDimmPtr->TrppbPs = XFSBL_SPD_TO_PS(LpDdrSpdData->TrppbMin, LpDdrSpdData->FineTrppbMin);
	PDimmPtr->TRfcAbPs = ((LpDdrSpdData->TrfcabMinMsb << 8U) |
			(LpDdrSpdData->TrfcabMinLsb)) *
		PDimmPtr->MtbPs;
	PDimmPtr->TRfcPbPs = ((LpDdrSpdData->TrfcpbMinMsb << 8U) |
			(LpDdrSpdData->TrfcpbMinLsb)) *
		PDimmPtr->MtbPs;
	if ((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR4) ||
			((PDimmPtr->MemType == SPD_MEMTYPE_LPDDR3) &&
			 (PDimmPtr->Capacity != 1024U))) {
		PDimmPtr->TRefi = 3900000U;
	} else {
		PDimmPtr->TRefi = 7800000U;
	}
	return XFSBL_SUCCESS;
}
u32 XFsbl_ComputeLpDdrParams ( u8 * SpdData , struct DdrcInitData * DdrDataPtr ) { struct LpDdrSpdEeprom * LpDdrSpdData = ( struct LpDdrSpdEeprom * ) SpdData ; XFsbl_DimmParams * PDimmPtr = & DdrDataPtr -> PDimm ; memset ( PDimmPtr -> Mpart , 0U , sizeof ( PDimmPtr -> Mpart ) ) ; if ( ( LpDdrSpdData -> InfoSizeCrc & 0xFU ) > 2U ) memcpy ( PDimmPtr -> Mpart , LpDdrSpdData -> Mpart , sizeof ( PDimmPtr -> Mpart ) - 1U ) ; PDimmPtr -> MemType = LpDdrSpdData -> MemType ; PDimmPtr -> NRanks = ( ( LpDdrSpdData -> Organization >> 3U ) & 0x7U ) + 1U ; PDimmPtr -> RankDensity = XFsbl_ComputeLpDdrRankSize ( LpDdrSpdData ) ; PDimmPtr -> Capacity = ( PDimmPtr -> NRanks * PDimmPtr -> RankDensity ) / ( 1024U * 1024U ) ; PDimmPtr -> BusWidth = 1U << ( 3U + ( LpDdrSpdData -> BusWidth & 0x7U ) ) ; if ( ( LpDdrSpdData -> BusWidth >> 3U ) & 0x3U ) PDimmPtr -> EccBusWidth = 8U ; else PDimmPtr -> EccBusWidth = 0U ; PDimmPtr -> DramWidth = 1U << ( ( LpDdrSpdData -> Organization & 0x7U ) + 2U ) ; PDimmPtr -> AddrMirror = 0U ; PDimmPtr -> RDimm = 0U ; PDimmPtr -> NumRowAddr = ( ( LpDdrSpdData -> Addressing >> 3U ) & 0x7U ) + 12U ; PDimmPtr -> NumColAddr = ( LpDdrSpdData -> Addressing & 0x7U ) + 9U ; PDimmPtr -> NumBankAddr = ( ( LpDdrSpdData -> DensityBanks >> 4U ) & 0x3U ) + 2U ; PDimmPtr -> NumBgAddr = ( LpDdrSpdData -> DensityBanks >> 6U ) & 0x3U ; PDimmPtr -> NumRankAddr = XFsbl_GetLog2 ( PDimmPtr -> NRanks ) ; PDimmPtr -> BurstLength = 8U ; PDimmPtr -> RowDensity = XFsbl_GetLog2 ( PDimmPtr -> RankDensity ) ; if ( ( LpDdrSpdData -> Timebases & 0xFU ) == 0x0U ) { PDimmPtr -> MtbPs = 125U ; PDimmPtr -> Ftb10thPs = 10U ; } PDimmPtr -> TckminXPs = XFSBL_SPD_TO_PS ( LpDdrSpdData -> TckMin , LpDdrSpdData -> FineTckMin ) ; PDimmPtr -> SpeedBin = ( u32 ) XFsbl_Ceil ( 2000000.0 / PDimmPtr -> TckminXPs ) ; PDimmPtr -> FreqMhz = 1000000.0 / PDimmPtr -> TckminXPs ; PDimmPtr -> ClockPeriod = PDimmPtr -> TckminXPs / 1000.0 ; PDimmPtr -> TckmaxPs = XFSBL_SPD_TO_PS ( LpDdrSpdData -> TckMax , LpDdrSpdData -> FineTckMax ) ; PDimmPtr -> CaslatX = ( LpDdrSpdData -> CaslatB1 << 7U ) | ( LpDdrSpdData -> CaslatB2 << 15U ) | ( LpDdrSpdData -> CaslatB3 << 23U ) ; PDimmPtr -> TaaPs = XFSBL_SPD_TO_PS ( LpDdrSpdData -> TaaMin , LpDdrSpdData -> FineTaaMin ) ; PDimmPtr -> CasLatency = ( u32 ) XFsbl_Ceil ( PDimmPtr -> TaaPs / 1000.0 ) + 1U ; PDimmPtr -> CasWriteLatency = XFsbl_Ceil ( PDimmPtr -> TaaPs / 1000.0 ) ; PDimmPtr -> TRcdPs = XFSBL_SPD_TO_PS ( LpDdrSpdData -> TrcdMin , LpDdrSpdData -> FineTrcdMin ) ; PDimmPtr -> TrpabPs = XFSBL_SPD_TO_PS ( LpDdrSpdData -> TrpabMin , LpDdrSpdData -> FineTrpabMin ) ; PDimmPtr -> TrppbPs = XFSBL_SPD_TO_PS ( LpDdrSpdData -> TrppbMin , LpDdrSpdData -> FineTrppbMin ) ; PDimmPtr -> TRfcAbPs = ( ( LpDdrSpdData -> TrfcabMinMsb << 8U ) | ( LpDdrSpdData -> TrfcabMinLsb ) ) * PDimmPtr -> MtbPs ; PDimmPtr -> TRfcPbPs = ( ( LpDdrSpdData -> TrfcpbMinMsb << 8U ) | ( LpDdrSpdData -> TrfcpbMinLsb ) ) * PDimmPtr -> MtbPs ; if ( ( PDimmPtr -> MemType == SPD_MEMTYPE_LPDDR4 ) || ( ( PDimmPtr -> MemType == SPD_MEMTYPE_LPDDR3 ) && ( PDimmPtr -> Capacity != 1024U ) ) ) { PDimmPtr -> TRefi = 3900000U ; } else { PDimmPtr -> TRefi = 7800000U ; } return XFSBL_SUCCESS ; }
This function computes DIMM parameters based upon the SPD information in
 LpDdrSpdData.
This function computes DIMM parameters based upon the SPD information in LpDdrSpdData .