src/dpdk/drivers/net/mlx5/mlx5_txq.c
static void
txq_uar_ncattr_init(struct mlx5_txq_ctrl *txq_ctrl, size_t page_size)
{
	struct mlx5_priv *priv = txq_ctrl->priv;
	off_t cmd;

	txq_ctrl->txq.db_heu = priv->config.dbnc == MLX5_TXDB_HEURISTIC;
	txq_ctrl->txq.db_nc = 0;
	/* Check the doorbell register mapping type. */
	cmd = txq_ctrl->uar_mmap_offset / page_size;
	cmd >>= MLX5_UAR_MMAP_CMD_SHIFT;
	cmd &= MLX5_UAR_MMAP_CMD_MASK;
	if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD)
		txq_ctrl->txq.db_nc = 1;
}
/**
 * Configure the doorbell register non-cached attribute.
 *
 * @param txq_ctrl
 *   Pointer to Tx queue control structure.
 * @param page_size
 *   Systme page size
 */
Configure the doorbell register non-cached attribute.
@param txq_ctrl
Pointer to Tx queue control structure.
@param page_size
Systme page size
Configure the doorbell register non - cached attribute . @param txq_ctrl Pointer to Tx queue control structure . @param page_size Systme page size
static void
txq_uar_ncattr_init(struct mlx5_txq_ctrl *txq_ctrl, size_t page_size)
{
	struct mlx5_priv *priv = txq_ctrl->priv;
	off_t cmd;
	txq_ctrl->txq.db_heu = priv->config.dbnc == MLX5_TXDB_HEURISTIC;
	txq_ctrl->txq.db_nc = 0;
	cmd = txq_ctrl->uar_mmap_offset / page_size;
	cmd >>= MLX5_UAR_MMAP_CMD_SHIFT;
	cmd &= MLX5_UAR_MMAP_CMD_MASK;
	if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD)
		txq_ctrl->txq.db_nc = 1;
}
static void txq_uar_ncattr_init ( struct mlx5_txq_ctrl * txq_ctrl , size_t page_size ) { struct mlx5_priv * priv = txq_ctrl -> priv ; off_t cmd ; txq_ctrl -> txq . db_heu = priv -> config . dbnc == MLX5_TXDB_HEURISTIC ; txq_ctrl -> txq . db_nc = 0 ; cmd = txq_ctrl -> uar_mmap_offset / page_size ; cmd >>= MLX5_UAR_MMAP_CMD_SHIFT ; cmd &= MLX5_UAR_MMAP_CMD_MASK ; if ( cmd == MLX5_MMAP_GET_NC_PAGES_CMD ) txq_ctrl -> txq . db_nc = 1 ; }
Configure the doorbell register non-cached attribute.
Configure the doorbell register non - cached attribute .
/* Check the doorbell register mapping type. */