src/dpdk/drivers/net/ixgbe/base/ixgbe_x550.c
s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
{
	u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;

	DEBUGFUNC("ixgbe_dmac_config_tcs_X550");

	/* Configure DMA coalescing enabled */
	switch (hw->mac.dmac_config.link_speed) {
	case IXGBE_LINK_SPEED_10_FULL:
	case IXGBE_LINK_SPEED_100_FULL:
		pb_headroom = IXGBE_DMACRXT_100M;
		break;
	case IXGBE_LINK_SPEED_1GB_FULL:
		pb_headroom = IXGBE_DMACRXT_1G;
		break;
	default:
		pb_headroom = IXGBE_DMACRXT_10G;
		break;
	}

	maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
			     IXGBE_MHADD_MFS_SHIFT) / 1024);

	/* Set the per Rx packet buffer receive threshold */
	for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
		reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
		reg &= ~IXGBE_DMCTH_DMACRXT_MASK;

		if (tc < hw->mac.dmac_config.num_tcs) {
			/* Get Rx PB size */
			rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
			rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
				IXGBE_RXPBSIZE_SHIFT;

			/* Calculate receive buffer threshold in kilobytes */
			if (rx_pb_size > pb_headroom)
				rx_pb_size = rx_pb_size - pb_headroom;
			else
				rx_pb_size = 0;

			/* Minimum of MFS shall be set for DMCTH */
			reg |= (rx_pb_size > maxframe_size_kb) ?
				rx_pb_size : maxframe_size_kb;
		}
		IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
	}
	return IXGBE_SUCCESS;
}
/**
 * ixgbe_dmac_config_tcs_X550
 * @hw: pointer to hardware structure
 *
 * Configure DMA coalescing threshold per TC. The dmac enable bit must
 * be cleared before configuring.
 **/
ixgbe_dmac_config_tcs_X550
@hw: pointer to hardware structure

Configure DMA coalescing threshold per TC. The dmac enable bit must
be cleared before configuring.
ixgbe_dmac_config_tcs_X550 @hw : pointer to hardware structure Configure DMA coalescing threshold per TC . The dmac enable bit must be cleared before configuring .
s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
{
	u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
	DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
	switch (hw->mac.dmac_config.link_speed) {
	case IXGBE_LINK_SPEED_10_FULL:
	case IXGBE_LINK_SPEED_100_FULL:
		pb_headroom = IXGBE_DMACRXT_100M;
		break;
	case IXGBE_LINK_SPEED_1GB_FULL:
		pb_headroom = IXGBE_DMACRXT_1G;
		break;
	default:
		pb_headroom = IXGBE_DMACRXT_10G;
		break;
	}
	maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
			     IXGBE_MHADD_MFS_SHIFT) / 1024);
	for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
		reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
		reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
		if (tc < hw->mac.dmac_config.num_tcs) {
			rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
			rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
				IXGBE_RXPBSIZE_SHIFT;
			if (rx_pb_size > pb_headroom)
				rx_pb_size = rx_pb_size - pb_headroom;
			else
				rx_pb_size = 0;
			reg |= (rx_pb_size > maxframe_size_kb) ?
				rx_pb_size : maxframe_size_kb;
		}
		IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
	}
	return IXGBE_SUCCESS;
}
s32 ixgbe_dmac_config_tcs_X550 ( struct ixgbe_hw * hw ) { u32 tc , reg , pb_headroom , rx_pb_size , maxframe_size_kb ; DEBUGFUNC ( " " ) ; switch ( hw -> mac . dmac_config . link_speed ) { case IXGBE_LINK_SPEED_10_FULL : case IXGBE_LINK_SPEED_100_FULL : pb_headroom = IXGBE_DMACRXT_100M ; break ; case IXGBE_LINK_SPEED_1GB_FULL : pb_headroom = IXGBE_DMACRXT_1G ; break ; default : pb_headroom = IXGBE_DMACRXT_10G ; break ; } maxframe_size_kb = ( ( IXGBE_READ_REG ( hw , IXGBE_MAXFRS ) >> IXGBE_MHADD_MFS_SHIFT ) / 1024 ) ; for ( tc = 0 ; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS ; tc ++ ) { reg = IXGBE_READ_REG ( hw , IXGBE_DMCTH ( tc ) ) ; reg &= ~ IXGBE_DMCTH_DMACRXT_MASK ; if ( tc < hw -> mac . dmac_config . num_tcs ) { rx_pb_size = IXGBE_READ_REG ( hw , IXGBE_RXPBSIZE ( tc ) ) ; rx_pb_size = ( rx_pb_size & IXGBE_RXPBSIZE_MASK ) >> IXGBE_RXPBSIZE_SHIFT ; if ( rx_pb_size > pb_headroom ) rx_pb_size = rx_pb_size - pb_headroom ; else rx_pb_size = 0 ; reg |= ( rx_pb_size > maxframe_size_kb ) ? rx_pb_size : maxframe_size_kb ; } IXGBE_WRITE_REG ( hw , IXGBE_DMCTH ( tc ) , reg ) ; } return IXGBE_SUCCESS ; }
ixgbe_dmac_config_tcs_X550
 @hw: pointer to hardware structure
ixgbe_dmac_config_tcs_X550 @hw : pointer to hardware structure
/* Configure DMA coalescing enabled */ /* Set the per Rx packet buffer receive threshold */ /* Get Rx PB size */ /* Calculate receive buffer threshold in kilobytes */ /* Minimum of MFS shall be set for DMCTH */