target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c
static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
{
	u32 v, w;
	// Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1
	struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);

	// The table has a size of 7 registers, 64 entries
	v = BIT(20); // mac entry valid, port type is 0: individual
	v |= (m->p_id & 0x3f) << 13;
	v |= (m->vid & 0xfff); // Set the interface_id to the vlan id

	w = m->vid_mask;
	w |= (m->p_id_mask & 0x3f) << 13;

	sw_w32(v, rtl_table_data(r, 0));
	sw_w32(w, rtl_table_data(r, 3));

	// Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0
	sw_w32((u32)(m->mac), rtl_table_data(r, 2));
	sw_w32(m->mac >> 32, rtl_table_data(r, 1));

	// Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0
	sw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4));
	sw_w32((u32)m->mac_mask, rtl_table_data(r, 5));

	sw_w32(m->action & 0x7, rtl_table_data(r, 6));

	pr_debug("%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\n", __func__, idx,
		sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
		sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
		sw_r32(rtl_table_data(r, 6))
	);
	rtl_table_write(r, idx);
	rtl_table_release(r);
}
/*
 * Writes a MAC entry for L3 termination as entry point for routing
 * into the hardware table
 * idx is the index into the L3_ROUTER_MAC table
 */
Writes a MAC entry for L3 termination as entry point for routing
into the hardware table
idx is the index into the L3_ROUTER_MAC table
Writes a MAC entry for L3 termination as entry point for routing into the hardware table idx is the index into the L3_ROUTER_MAC table
static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
{
	u32 v, w;
	struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
	v = BIT(20); 
	v |= (m->p_id & 0x3f) << 13;
	v |= (m->vid & 0xfff); 
	w = m->vid_mask;
	w |= (m->p_id_mask & 0x3f) << 13;
	sw_w32(v, rtl_table_data(r, 0));
	sw_w32(w, rtl_table_data(r, 3));
	sw_w32((u32)(m->mac), rtl_table_data(r, 2));
	sw_w32(m->mac >> 32, rtl_table_data(r, 1));
	sw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4));
	sw_w32((u32)m->mac_mask, rtl_table_data(r, 5));
	sw_w32(m->action & 0x7, rtl_table_data(r, 6));
	pr_debug("%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\n", __func__, idx,
		sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
		sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
		sw_r32(rtl_table_data(r, 6))
	);
	rtl_table_write(r, idx);
	rtl_table_release(r);
}
static void rtl930x_set_l3_router_mac ( u32 idx , struct rtl93xx_rt_mac * m ) { u32 v , w ; struct table_reg * r = rtl_table_get ( RTL9300_TBL_1 , 0 ) ; v = BIT ( 20 ) ; v |= ( m -> p_id & 0x3f ) << 13 ; v |= ( m -> vid & 0xfff ) ; w = m -> vid_mask ; w |= ( m -> p_id_mask & 0x3f ) << 13 ; sw_w32 ( v , rtl_table_data ( r , 0 ) ) ; sw_w32 ( w , rtl_table_data ( r , 3 ) ) ; sw_w32 ( ( u32 ) ( m -> mac ) , rtl_table_data ( r , 2 ) ) ; sw_w32 ( m -> mac >> 32 , rtl_table_data ( r , 1 ) ) ; sw_w32 ( ( u32 ) ( m -> mac_mask >> 32 ) , rtl_table_data ( r , 4 ) ) ; sw_w32 ( ( u32 ) m -> mac_mask , rtl_table_data ( r , 5 ) ) ; sw_w32 ( m -> action & 0x7 , rtl_table_data ( r , 6 ) ) ; pr_debug ( " \n " , __func__ , idx , sw_r32 ( rtl_table_data ( r , 0 ) ) , sw_r32 ( rtl_table_data ( r , 1 ) ) , sw_r32 ( rtl_table_data ( r , 2 ) ) , sw_r32 ( rtl_table_data ( r , 3 ) ) , sw_r32 ( rtl_table_data ( r , 4 ) ) , sw_r32 ( rtl_table_data ( r , 5 ) ) , sw_r32 ( rtl_table_data ( r , 6 ) ) ) ; rtl_table_write ( r , idx ) ; rtl_table_release ( r ) ; }
Writes a MAC entry for L3 termination as entry point for routing
 into the hardware table
 idx is the index into the L3_ROUTER_MAC table
Writes a MAC entry for L3 termination as entry point for routing into the hardware table idx is the index into the L3_ROUTER_MAC table
// Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 // The table has a size of 7 registers, 64 entries // mac entry valid, port type is 0: individual // Set the interface_id to the vlan id // Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0 // Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0