XilinxProcessorIPLib/drivers/vphy/src/xvphy.c
u32 XVphy_ResetGtPll(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId,
		XVphy_DirectionType Dir, u8 Hold)
{
	u32 RegVal;
	u32 MaskVal;
	u32 RegOffset;

	/* Suppress Warning Messages */
	QuadId = QuadId;

	if (Dir == XVPHY_DIR_TX) {
		RegOffset = XVPHY_TX_INIT_REG;
	}
	else {
		RegOffset = XVPHY_RX_INIT_REG;
	}
	if (ChId == XVPHY_CHANNEL_ID_CHA) {
		MaskVal = XVPHY_TXRX_INIT_PLLGTRESET_ALL_MASK;
	}
	else {
		MaskVal = XVPHY_TXRX_INIT_PLLGTRESET_MASK(ChId);
	}

	RegVal = XVphy_ReadReg(InstancePtr->Config.BaseAddr, RegOffset);
	/* Assert reset. */
	RegVal |= MaskVal;
	XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal);

	if (!Hold) {
		/* De-assert reset. */
		RegVal &= ~MaskVal;
		XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal);
	}

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function will reset the GT's PLL logic.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID which to operate on.
* @param	Dir is an indicator for TX or RX.
* @param	Hold is an indicator whether to "hold" the reset if set to 1.
*		If set to 0: reset, then enable.
*
* @return
*		- XST_SUCCESS.
*
* @note		None.
*
******************************************************************************/
This function will reset the GT's PLL logic.
This function will reset the GT ' s PLL logic .
u32 XVphy_ResetGtPll(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId,
		XVphy_DirectionType Dir, u8 Hold)
{
	u32 RegVal;
	u32 MaskVal;
	u32 RegOffset;
	QuadId = QuadId;
	if (Dir == XVPHY_DIR_TX) {
		RegOffset = XVPHY_TX_INIT_REG;
	}
	else {
		RegOffset = XVPHY_RX_INIT_REG;
	}
	if (ChId == XVPHY_CHANNEL_ID_CHA) {
		MaskVal = XVPHY_TXRX_INIT_PLLGTRESET_ALL_MASK;
	}
	else {
		MaskVal = XVPHY_TXRX_INIT_PLLGTRESET_MASK(ChId);
	}
	RegVal = XVphy_ReadReg(InstancePtr->Config.BaseAddr, RegOffset);
	RegVal |= MaskVal;
	XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal);
	if (!Hold) {
		RegVal &= ~MaskVal;
		XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal);
	}
	return XST_SUCCESS;
}
u32 XVphy_ResetGtPll ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId ChId , XVphy_DirectionType Dir , u8 Hold ) { u32 RegVal ; u32 MaskVal ; u32 RegOffset ; QuadId = QuadId ; if ( Dir == XVPHY_DIR_TX ) { RegOffset = XVPHY_TX_INIT_REG ; } else { RegOffset = XVPHY_RX_INIT_REG ; } if ( ChId == XVPHY_CHANNEL_ID_CHA ) { MaskVal = XVPHY_TXRX_INIT_PLLGTRESET_ALL_MASK ; } else { MaskVal = XVPHY_TXRX_INIT_PLLGTRESET_MASK ( ChId ) ; } RegVal = XVphy_ReadReg ( InstancePtr -> Config . BaseAddr , RegOffset ) ; RegVal |= MaskVal ; XVphy_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffset , RegVal ) ; if ( ! Hold ) { RegVal &= ~ MaskVal ; XVphy_WriteReg ( InstancePtr -> Config . BaseAddr , RegOffset , RegVal ) ; } return XST_SUCCESS ; }
This function will reset the GT's PLL logic.
This function will reset the GT ' s PLL logic .
/* Suppress Warning Messages */ /* Assert reset. */ /* De-assert reset. */