src/dpdk/drivers/net/txgbe/txgbe_rxtx.c
static void
txgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
{
	struct rte_eth_vmdq_rx_conf *cfg;
	struct txgbe_hw *hw;
	enum rte_eth_nb_pools num_pools;
	uint32_t mrqc, vt_ctl, vlanctrl;
	uint32_t vmolr = 0;
	int i;

	PMD_INIT_FUNC_TRACE();
	hw = TXGBE_DEV_HW(dev);
	cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
	num_pools = cfg->nb_queue_pools;

	txgbe_rss_disable(dev);

	/* enable vmdq */
	mrqc = TXGBE_PORTCTL_NUMVT_64;
	wr32m(hw, TXGBE_PORTCTL, TXGBE_PORTCTL_NUMVT_MASK, mrqc);

	/* turn on virtualisation and set the default pool */
	vt_ctl = TXGBE_POOLCTL_RPLEN;
	if (cfg->enable_default_pool)
		vt_ctl |= TXGBE_POOLCTL_DEFPL(cfg->default_pool);
	else
		vt_ctl |= TXGBE_POOLCTL_DEFDSA;

	wr32(hw, TXGBE_POOLCTL, vt_ctl);

	for (i = 0; i < (int)num_pools; i++) {
		vmolr = txgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
		wr32(hw, TXGBE_POOLETHCTL(i), vmolr);
	}

	/* enable vlan filtering and allow all vlan tags through */
	vlanctrl = rd32(hw, TXGBE_VLANCTL);
	vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
	wr32(hw, TXGBE_VLANCTL, vlanctrl);

	/* enable all vlan filters */
	for (i = 0; i < NUM_VFTA_REGISTERS; i++)
		wr32(hw, TXGBE_VLANTBL(i), UINT32_MAX);

	/* pool enabling for receive - 64 */
	wr32(hw, TXGBE_POOLRXENA(0), UINT32_MAX);
	if (num_pools == ETH_64_POOLS)
		wr32(hw, TXGBE_POOLRXENA(1), UINT32_MAX);

	/*
	 * allow pools to read specific mac addresses
	 * In this case, all pools should be able to read from mac addr 0
	 */
	wr32(hw, TXGBE_ETHADDRIDX, 0);
	wr32(hw, TXGBE_ETHADDRASSL, 0xFFFFFFFF);
	wr32(hw, TXGBE_ETHADDRASSH, 0xFFFFFFFF);

	/* set up filters for vlan tags as configured */
	for (i = 0; i < cfg->nb_pool_maps; i++) {
		/* set vlan id in VF register and set the valid bit */
		wr32(hw, TXGBE_PSRVLANIDX, i);
		wr32(hw, TXGBE_PSRVLAN, (TXGBE_PSRVLAN_EA |
				TXGBE_PSRVLAN_VID(cfg->pool_map[i].vlan_id)));
		/*
		 * Put the allowed pools in VFB reg. As we only have 16 or 64
		 * pools, we only need to use the first half of the register
		 * i.e. bits 0-31
		 */
		if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
			wr32(hw, TXGBE_PSRVLANPLM(0),
				(cfg->pool_map[i].pools & UINT32_MAX));
		else
			wr32(hw, TXGBE_PSRVLANPLM(1),
				((cfg->pool_map[i].pools >> 32) & UINT32_MAX));
	}

	/* Tx General Switch Control Enables VMDQ loopback */
	if (cfg->enable_loop_back) {
		wr32(hw, TXGBE_PSRCTL, TXGBE_PSRCTL_LBENA);
		for (i = 0; i < 64; i++)
			wr32m(hw, TXGBE_POOLETHCTL(i),
				TXGBE_POOLETHCTL_LLB, TXGBE_POOLETHCTL_LLB);
	}

	txgbe_flush(hw);
}
/*
 * VMDq only support for 10 GbE NIC.
 */
VMDq only support for 10 GbE NIC.
VMDq only support for 10 GbE NIC .
static void
txgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
{
	struct rte_eth_vmdq_rx_conf *cfg;
	struct txgbe_hw *hw;
	enum rte_eth_nb_pools num_pools;
	uint32_t mrqc, vt_ctl, vlanctrl;
	uint32_t vmolr = 0;
	int i;
	PMD_INIT_FUNC_TRACE();
	hw = TXGBE_DEV_HW(dev);
	cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
	num_pools = cfg->nb_queue_pools;
	txgbe_rss_disable(dev);
	mrqc = TXGBE_PORTCTL_NUMVT_64;
	wr32m(hw, TXGBE_PORTCTL, TXGBE_PORTCTL_NUMVT_MASK, mrqc);
	vt_ctl = TXGBE_POOLCTL_RPLEN;
	if (cfg->enable_default_pool)
		vt_ctl |= TXGBE_POOLCTL_DEFPL(cfg->default_pool);
	else
		vt_ctl |= TXGBE_POOLCTL_DEFDSA;
	wr32(hw, TXGBE_POOLCTL, vt_ctl);
	for (i = 0; i < (int)num_pools; i++) {
		vmolr = txgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
		wr32(hw, TXGBE_POOLETHCTL(i), vmolr);
	}
	vlanctrl = rd32(hw, TXGBE_VLANCTL);
	vlanctrl |= TXGBE_VLANCTL_VFE; 
	wr32(hw, TXGBE_VLANCTL, vlanctrl);
	for (i = 0; i < NUM_VFTA_REGISTERS; i++)
		wr32(hw, TXGBE_VLANTBL(i), UINT32_MAX);
	wr32(hw, TXGBE_POOLRXENA(0), UINT32_MAX);
	if (num_pools == ETH_64_POOLS)
		wr32(hw, TXGBE_POOLRXENA(1), UINT32_MAX);
	wr32(hw, TXGBE_ETHADDRIDX, 0);
	wr32(hw, TXGBE_ETHADDRASSL, 0xFFFFFFFF);
	wr32(hw, TXGBE_ETHADDRASSH, 0xFFFFFFFF);
	for (i = 0; i < cfg->nb_pool_maps; i++) {
		wr32(hw, TXGBE_PSRVLANIDX, i);
		wr32(hw, TXGBE_PSRVLAN, (TXGBE_PSRVLAN_EA |
				TXGBE_PSRVLAN_VID(cfg->pool_map[i].vlan_id)));
		if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
			wr32(hw, TXGBE_PSRVLANPLM(0),
				(cfg->pool_map[i].pools & UINT32_MAX));
		else
			wr32(hw, TXGBE_PSRVLANPLM(1),
				((cfg->pool_map[i].pools >> 32) & UINT32_MAX));
	}
	if (cfg->enable_loop_back) {
		wr32(hw, TXGBE_PSRCTL, TXGBE_PSRCTL_LBENA);
		for (i = 0; i < 64; i++)
			wr32m(hw, TXGBE_POOLETHCTL(i),
				TXGBE_POOLETHCTL_LLB, TXGBE_POOLETHCTL_LLB);
	}
	txgbe_flush(hw);
}
static void txgbe_vmdq_rx_hw_configure ( struct rte_eth_dev * dev ) { struct rte_eth_vmdq_rx_conf * cfg ; struct txgbe_hw * hw ; enum rte_eth_nb_pools num_pools ; uint32_t mrqc , vt_ctl , vlanctrl ; uint32_t vmolr = 0 ; int i ; PMD_INIT_FUNC_TRACE ( ) ; hw = TXGBE_DEV_HW ( dev ) ; cfg = & dev -> data -> dev_conf . rx_adv_conf . vmdq_rx_conf ; num_pools = cfg -> nb_queue_pools ; txgbe_rss_disable ( dev ) ; mrqc = TXGBE_PORTCTL_NUMVT_64 ; wr32m ( hw , TXGBE_PORTCTL , TXGBE_PORTCTL_NUMVT_MASK , mrqc ) ; vt_ctl = TXGBE_POOLCTL_RPLEN ; if ( cfg -> enable_default_pool ) vt_ctl |= TXGBE_POOLCTL_DEFPL ( cfg -> default_pool ) ; else vt_ctl |= TXGBE_POOLCTL_DEFDSA ; wr32 ( hw , TXGBE_POOLCTL , vt_ctl ) ; for ( i = 0 ; i < ( int ) num_pools ; i ++ ) { vmolr = txgbe_convert_vm_rx_mask_to_val ( cfg -> rx_mode , vmolr ) ; wr32 ( hw , TXGBE_POOLETHCTL ( i ) , vmolr ) ; } vlanctrl = rd32 ( hw , TXGBE_VLANCTL ) ; vlanctrl |= TXGBE_VLANCTL_VFE ; wr32 ( hw , TXGBE_VLANCTL , vlanctrl ) ; for ( i = 0 ; i < NUM_VFTA_REGISTERS ; i ++ ) wr32 ( hw , TXGBE_VLANTBL ( i ) , UINT32_MAX ) ; wr32 ( hw , TXGBE_POOLRXENA ( 0 ) , UINT32_MAX ) ; if ( num_pools == ETH_64_POOLS ) wr32 ( hw , TXGBE_POOLRXENA ( 1 ) , UINT32_MAX ) ; wr32 ( hw , TXGBE_ETHADDRIDX , 0 ) ; wr32 ( hw , TXGBE_ETHADDRASSL , 0xFFFFFFFF ) ; wr32 ( hw , TXGBE_ETHADDRASSH , 0xFFFFFFFF ) ; for ( i = 0 ; i < cfg -> nb_pool_maps ; i ++ ) { wr32 ( hw , TXGBE_PSRVLANIDX , i ) ; wr32 ( hw , TXGBE_PSRVLAN , ( TXGBE_PSRVLAN_EA | TXGBE_PSRVLAN_VID ( cfg -> pool_map [ i ] . vlan_id ) ) ) ; if ( ( ( cfg -> pool_map [ i ] . pools >> 32 ) & UINT32_MAX ) == 0 ) wr32 ( hw , TXGBE_PSRVLANPLM ( 0 ) , ( cfg -> pool_map [ i ] . pools & UINT32_MAX ) ) ; else wr32 ( hw , TXGBE_PSRVLANPLM ( 1 ) , ( ( cfg -> pool_map [ i ] . pools >> 32 ) & UINT32_MAX ) ) ; } if ( cfg -> enable_loop_back ) { wr32 ( hw , TXGBE_PSRCTL , TXGBE_PSRCTL_LBENA ) ; for ( i = 0 ; i < 64 ; i ++ ) wr32m ( hw , TXGBE_POOLETHCTL ( i ) , TXGBE_POOLETHCTL_LLB , TXGBE_POOLETHCTL_LLB ) ; } txgbe_flush ( hw ) ; }
VMDq only support for 10 GbE NIC.
VMDq only support for 10 GbE NIC .
/* enable vmdq */ /* turn on virtualisation and set the default pool */ /* enable vlan filtering and allow all vlan tags through */ /* enable vlan filters */ /* enable all vlan filters */ /* pool enabling for receive - 64 */ /*
	 * allow pools to read specific mac addresses
	 * In this case, all pools should be able to read from mac addr 0
	 */ /* set up filters for vlan tags as configured */ /* set vlan id in VF register and set the valid bit */ /*
		 * Put the allowed pools in VFB reg. As we only have 16 or 64
		 * pools, we only need to use the first half of the register
		 * i.e. bits 0-31
		 */ /* Tx General Switch Control Enables VMDQ loopback */