XilinxProcessorIPLib/drivers/aiengine/src/pm/xaiepm_clock.c
static u8 _XAiePm_ClockGateTile(XAieGbl *AieInst, u8 col, u8 row){

	XAieGbl_Tile *TilePtr;
	u32 NumRows;
	u64 RegAddr;

	NumRows = AieInst->Config->NumRows;
	TilePtr = AieInst->Tiles;
	TilePtr += col * (NumRows + 1U) + (row - 1U);
	RegAddr = TilePtr->TileAddr;
	XAieGbl_MaskWrite32(RegAddr + XAIEGBL_CORE_TILCLOCTRL,
				XAIEGBL_CORE_TILCLOCTRL_NEXTILCLOENA_MASK,
								CLOCK_GATE_VAL);
	return XAIE_SUCCESS;
}
/*****************************************************************************/
/*
*
* This is an internal API to clock gate the next tile in column.
*
* @param	AieInst - Pointer to the Aie instance.
* @param	row - row number of the tile to be gated
* @param	col - col number of the tile to be gated
*
* @return	XAIE_SUCCESS on success
*
* @note		None
*
*******************************************************************************/
This is an internal API to clock gate the next tile in column.
This is an internal API to clock gate the next tile in column .
static u8 _XAiePm_ClockGateTile(XAieGbl *AieInst, u8 col, u8 row){
	XAieGbl_Tile *TilePtr;
	u32 NumRows;
	u64 RegAddr;
	NumRows = AieInst->Config->NumRows;
	TilePtr = AieInst->Tiles;
	TilePtr += col * (NumRows + 1U) + (row - 1U);
	RegAddr = TilePtr->TileAddr;
	XAieGbl_MaskWrite32(RegAddr + XAIEGBL_CORE_TILCLOCTRL,
				XAIEGBL_CORE_TILCLOCTRL_NEXTILCLOENA_MASK,
								CLOCK_GATE_VAL);
	return XAIE_SUCCESS;
}
static u8 _XAiePm_ClockGateTile ( XAieGbl * AieInst , u8 col , u8 row ) { XAieGbl_Tile * TilePtr ; u32 NumRows ; u64 RegAddr ; NumRows = AieInst -> Config -> NumRows ; TilePtr = AieInst -> Tiles ; TilePtr += col * ( NumRows + 1U ) + ( row - 1U ) ; RegAddr = TilePtr -> TileAddr ; XAieGbl_MaskWrite32 ( RegAddr + XAIEGBL_CORE_TILCLOCTRL , XAIEGBL_CORE_TILCLOCTRL_NEXTILCLOENA_MASK , CLOCK_GATE_VAL ) ; return XAIE_SUCCESS ; }
This is an internal API to clock gate the next tile in column.
This is an internal API to clock gate the next tile in column .