lib/sw_apps/zynqmp_fsbl/src/xfsbl_ddr_init.c
static void XFsbl_DdrCalcAddrMap(struct DdrcInitData *DdrDataPtr)
{
	XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
	u32 HifAddr[40U] = {0U};
	u32 RegVal[12U];
	u32 Index;

#if (XFSBL_VIDEOBUF != 0U)
	/* Calculate the HIF Addresses when Video Buffers are Enabled */
	XFsbl_DdrCalcHifAddrVideo(DdrDataPtr, HifAddr, VideoBuf);
#elif (XFSBL_BRCMAPPING == 1U)
	if (PDimmPtr->MemType != SPD_MEMTYPE_DDR4) {
		/*
		 * Calculate the HIF Addresses for Non-DDR4 Mapping
		 */
		XFsbl_DdrCalcHifAddr(DdrDataPtr, HifAddr);
	} else {
		/*
		 * Calculate the HIF Addresses when Bank-Row-Column Mapping is
		 * Enabled
		 */
		XFsbl_DdrCalcHifAddrBrcMap(DdrDataPtr, HifAddr);
	}
#else
	if (PDimmPtr->MemType != SPD_MEMTYPE_DDR4) {
		/*
		 * Calculate the HIF Addresses for Non-DDR4 Mapping
		 */
		XFsbl_DdrCalcHifAddr(DdrDataPtr, HifAddr);

	} else {
#if (XFSBL_DDR4ADDRMAPPING == 1U)
		/*
		 * Calculate the HIF Addresses when DDR4 Address Mapping
		 * is Enabled
		 */
		XFsbl_DdrCalcHifAddrMemMap(DdrDataPtr, HifAddr);
#else
		/*
		 * Calculate the HIF Addresses for default DDR4 Mapping
		 */
		XFsbl_DdrCalcDdr4HifAddr(DdrDataPtr, HifAddr);
#endif
	}
#endif

    if (PDimmPtr->BusWidth <= 32U) {
	for (Index = 0U; Index < 39U; Index++) {
		HifAddr[Index] = HifAddr[Index + 1U];
	}
	HifAddr[39U] = 0U;
    }

    if (PDimmPtr->BusWidth == 16U) {
	for (Index = 0U; Index < 39U; Index++) {
		HifAddr[Index] = HifAddr[Index + 1U];
	}
	HifAddr[39U] = 0U;
    }

	/* Calculate Bank Address Map based on HIF Addresses */
	XFsbl_DdrCalcBankAddr(DdrDataPtr, HifAddr);

	/* Calculate Column Address Map based on HIF Addresses */
	XFsbl_DdrCalcColAddr(DdrDataPtr, HifAddr);

	/* Calculate Row Address Map based on HIF Addresses */
	XFsbl_DdrCalcRowAddr(DdrDataPtr, HifAddr);

	/* Calculate Bank Group Address Map based on HIF Addresses */
	XFsbl_DdrCalcBgAddr(DdrDataPtr, HifAddr);

	/* Rank Width is 0U for the New DIMM */
	DdrDataPtr->AddrMapCsBit0 = 0x1FU;

	/* Address Map Register 0U */
	RegVal[0U] = ((DdrDataPtr->AddrMapCsBit0 & 0x1FU) << 0U);

	/* Address Map Register 1U */
	RegVal[1U]  = ((DdrDataPtr->AddrMapBankBit[2U] &
				0x1FU) << 16U);
	RegVal[1U] |= ((DdrDataPtr->AddrMapBankBit[1U] &
				0x1FU) << 8U);
	RegVal[1U] |= ((DdrDataPtr->AddrMapBankBit[0U] &
				0x1FU) << 0U);

	/* Address Map Register 2U */
	RegVal[2U]  = ((DdrDataPtr->AddrMapColBit[5U] &
				0xFU) << 24U);
	RegVal[2U] |= ((DdrDataPtr->AddrMapColBit[4U] &
				0xFU) << 16U);
	RegVal[2U] |= ((DdrDataPtr->AddrMapColBit[3U] &
				0xFU) << 8U);
	RegVal[2U] |= ((DdrDataPtr->AddrMapColBit[2U] &
				0xFU) << 0U);

	/* Address Map Register 3U */
	RegVal[3U]  = ((DdrDataPtr->AddrMapColBit[9U] &
				0xFU) << 24U);
	RegVal[3U] |= ((DdrDataPtr->AddrMapColBit[8U] &
				0xFU) << 16U);
	RegVal[3U] |= ((DdrDataPtr->AddrMapColBit[7U] &
				0xFU) << 8U);
	RegVal[3U] |= ((DdrDataPtr->AddrMapColBit[6U] &
				0xFU) << 0U);

	/* Address Map Register 4U */
	RegVal[4U]  = ((DdrDataPtr->AddrMapColBit[11U] &
				0xFU) << 8U);
	RegVal[4U] |= ((DdrDataPtr->AddrMapColBit[10U] &
				0xFU) << 0U);

	/* Address Map Register 5U */
	RegVal[5U] = ((DdrDataPtr->AddrMapRowBit[11U] &
				0xFU) << 24U);
	RegVal[5U] |= ((DdrDataPtr->AddrMapRowBits2To10 &
				0xFU) << 16U);
	RegVal[5U] |= ((DdrDataPtr->AddrMapRowBit[1U] &
				0xFU) << 8U);
	RegVal[5U] |= ((DdrDataPtr->AddrMapRowBit[0U] &
				0xFU) << 0U);

	/* Address Map Register 6U */
	RegVal[6U] = ((DdrDataPtr->AddrMapRowBit[15U] &
				0xFU) << 24U);
	RegVal[6U] |= ((DdrDataPtr->AddrMapRowBit[14U] &
				0xFU) << 16U);
	RegVal[6U] |= ((DdrDataPtr->AddrMapRowBit[13U] &
				0xFU) << 8U);
	RegVal[6U] |= ((DdrDataPtr->AddrMapRowBit[12U] &
				0xFU) << 0U);

	/* Address Map Register 7U */
	RegVal[7U] = ((DdrDataPtr->AddrMapRowBit[17U] &
				0xFU) << 8U);
	RegVal[7U] |= ((DdrDataPtr->AddrMapRowBit[16U] &
				0xFU) << 0U);

	/* Address Map Register 8U */
	RegVal[8U]  = ((DdrDataPtr->AddrMapBgBit[1U] &
				0x1FU) << 8U);
	RegVal[8U] |= ((DdrDataPtr->AddrMapBgBit[0U] &
				0x1FU) << 0U);

	/* Address Map Register 9U */
	RegVal[9U]  = ((DdrDataPtr->AddrMapRowBit[5U] &
				0xFU) << 24U);
	RegVal[9U] |= ((DdrDataPtr->AddrMapRowBit[4U] &
				0xFU) << 16U);
	RegVal[9U] |= ((DdrDataPtr->AddrMapRowBit[3U] &
				0xFU) << 8U);
	RegVal[9U] |= ((DdrDataPtr->AddrMapRowBit[2U] &
				0xFU) << 0U);

	/* Address Map Register 10U */
	RegVal[10U]  = ((DdrDataPtr->AddrMapRowBit[9U] &
				0xFU) << 24U);
	RegVal[10U] |= ((DdrDataPtr->AddrMapRowBit[8U] &
				0xFU) << 16U);
	RegVal[10U] |= ((DdrDataPtr->AddrMapRowBit[7U] &
				0xFU) << 8U);
	RegVal[10U] |= ((DdrDataPtr->AddrMapRowBit[6U] &
				0xFU) << 0U);

	/* Address Map Register 11U */
	RegVal[11U] = ((DdrDataPtr->AddrMapRowBit[10U] &
				0xFU) << 0U);

	for (Index = 0U; Index < 12U; Index ++) {
		Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x200U + (Index * 4U), RegVal[Index]);
	}
}
/*****************************************************************************/
/**
 * This function calculates the Address Mapping of the DDR
 *
 * @param	DdrDataPtr is pointer to DDR Initialization Data Structure
 *
 * @return	None
 *
 *****************************************************************************/
This function calculates the Address Mapping of the DDR
@param       DdrDataPtr is pointer to DDR Initialization Data Structure

@return      None
This function calculates the Address Mapping of the DDR @param DdrDataPtr is pointer to DDR Initialization Data Structure @return None
static void XFsbl_DdrCalcAddrMap(struct DdrcInitData *DdrDataPtr)
{
	XFsbl_DimmParams *PDimmPtr = &DdrDataPtr->PDimm;
	u32 HifAddr[40U] = {0U};
	u32 RegVal[12U];
	u32 Index;
#if (XFSBL_VIDEOBUF != 0U)
	XFsbl_DdrCalcHifAddrVideo(DdrDataPtr, HifAddr, VideoBuf);
#elif (XFSBL_BRCMAPPING == 1U)
	if (PDimmPtr->MemType != SPD_MEMTYPE_DDR4) {
		XFsbl_DdrCalcHifAddr(DdrDataPtr, HifAddr);
	} else {
		XFsbl_DdrCalcHifAddrBrcMap(DdrDataPtr, HifAddr);
	}
#else
	if (PDimmPtr->MemType != SPD_MEMTYPE_DDR4) {
		XFsbl_DdrCalcHifAddr(DdrDataPtr, HifAddr);
	} else {
#if (XFSBL_DDR4ADDRMAPPING == 1U)
		XFsbl_DdrCalcHifAddrMemMap(DdrDataPtr, HifAddr);
#else
		XFsbl_DdrCalcDdr4HifAddr(DdrDataPtr, HifAddr);
#endif
	}
#endif
    if (PDimmPtr->BusWidth <= 32U) {
	for (Index = 0U; Index < 39U; Index++) {
		HifAddr[Index] = HifAddr[Index + 1U];
	}
	HifAddr[39U] = 0U;
    }
    if (PDimmPtr->BusWidth == 16U) {
	for (Index = 0U; Index < 39U; Index++) {
		HifAddr[Index] = HifAddr[Index + 1U];
	}
	HifAddr[39U] = 0U;
    }
	XFsbl_DdrCalcBankAddr(DdrDataPtr, HifAddr);
	XFsbl_DdrCalcColAddr(DdrDataPtr, HifAddr);
	XFsbl_DdrCalcRowAddr(DdrDataPtr, HifAddr);
	XFsbl_DdrCalcBgAddr(DdrDataPtr, HifAddr);
	DdrDataPtr->AddrMapCsBit0 = 0x1FU;
	RegVal[0U] = ((DdrDataPtr->AddrMapCsBit0 & 0x1FU) << 0U);
	RegVal[1U]  = ((DdrDataPtr->AddrMapBankBit[2U] &
				0x1FU) << 16U);
	RegVal[1U] |= ((DdrDataPtr->AddrMapBankBit[1U] &
				0x1FU) << 8U);
	RegVal[1U] |= ((DdrDataPtr->AddrMapBankBit[0U] &
				0x1FU) << 0U);
	RegVal[2U]  = ((DdrDataPtr->AddrMapColBit[5U] &
				0xFU) << 24U);
	RegVal[2U] |= ((DdrDataPtr->AddrMapColBit[4U] &
				0xFU) << 16U);
	RegVal[2U] |= ((DdrDataPtr->AddrMapColBit[3U] &
				0xFU) << 8U);
	RegVal[2U] |= ((DdrDataPtr->AddrMapColBit[2U] &
				0xFU) << 0U);
	RegVal[3U]  = ((DdrDataPtr->AddrMapColBit[9U] &
				0xFU) << 24U);
	RegVal[3U] |= ((DdrDataPtr->AddrMapColBit[8U] &
				0xFU) << 16U);
	RegVal[3U] |= ((DdrDataPtr->AddrMapColBit[7U] &
				0xFU) << 8U);
	RegVal[3U] |= ((DdrDataPtr->AddrMapColBit[6U] &
				0xFU) << 0U);
	RegVal[4U]  = ((DdrDataPtr->AddrMapColBit[11U] &
				0xFU) << 8U);
	RegVal[4U] |= ((DdrDataPtr->AddrMapColBit[10U] &
				0xFU) << 0U);
	RegVal[5U] = ((DdrDataPtr->AddrMapRowBit[11U] &
				0xFU) << 24U);
	RegVal[5U] |= ((DdrDataPtr->AddrMapRowBits2To10 &
				0xFU) << 16U);
	RegVal[5U] |= ((DdrDataPtr->AddrMapRowBit[1U] &
				0xFU) << 8U);
	RegVal[5U] |= ((DdrDataPtr->AddrMapRowBit[0U] &
				0xFU) << 0U);
	RegVal[6U] = ((DdrDataPtr->AddrMapRowBit[15U] &
				0xFU) << 24U);
	RegVal[6U] |= ((DdrDataPtr->AddrMapRowBit[14U] &
				0xFU) << 16U);
	RegVal[6U] |= ((DdrDataPtr->AddrMapRowBit[13U] &
				0xFU) << 8U);
	RegVal[6U] |= ((DdrDataPtr->AddrMapRowBit[12U] &
				0xFU) << 0U);
	RegVal[7U] = ((DdrDataPtr->AddrMapRowBit[17U] &
				0xFU) << 8U);
	RegVal[7U] |= ((DdrDataPtr->AddrMapRowBit[16U] &
				0xFU) << 0U);
	RegVal[8U]  = ((DdrDataPtr->AddrMapBgBit[1U] &
				0x1FU) << 8U);
	RegVal[8U] |= ((DdrDataPtr->AddrMapBgBit[0U] &
				0x1FU) << 0U);
	RegVal[9U]  = ((DdrDataPtr->AddrMapRowBit[5U] &
				0xFU) << 24U);
	RegVal[9U] |= ((DdrDataPtr->AddrMapRowBit[4U] &
				0xFU) << 16U);
	RegVal[9U] |= ((DdrDataPtr->AddrMapRowBit[3U] &
				0xFU) << 8U);
	RegVal[9U] |= ((DdrDataPtr->AddrMapRowBit[2U] &
				0xFU) << 0U);
	RegVal[10U]  = ((DdrDataPtr->AddrMapRowBit[9U] &
				0xFU) << 24U);
	RegVal[10U] |= ((DdrDataPtr->AddrMapRowBit[8U] &
				0xFU) << 16U);
	RegVal[10U] |= ((DdrDataPtr->AddrMapRowBit[7U] &
				0xFU) << 8U);
	RegVal[10U] |= ((DdrDataPtr->AddrMapRowBit[6U] &
				0xFU) << 0U);
	RegVal[11U] = ((DdrDataPtr->AddrMapRowBit[10U] &
				0xFU) << 0U);
	for (Index = 0U; Index < 12U; Index ++) {
		Xil_Out32(XFSBL_DDRC_BASE_ADDR + 0x200U + (Index * 4U), RegVal[Index]);
	}
}
static void XFsbl_DdrCalcAddrMap ( struct DdrcInitData * DdrDataPtr ) { XFsbl_DimmParams * PDimmPtr = & DdrDataPtr -> PDimm ; u32 HifAddr [ 40U ] = { 0U } ; u32 RegVal [ 12U ] ; u32 Index ; #if ( XFSBL_VIDEOBUF != 0U ) XFsbl_DdrCalcHifAddrVideo ( DdrDataPtr , HifAddr , VideoBuf ) ; #elif ( XFSBL_BRCMAPPING == 1U ) if ( PDimmPtr -> MemType != SPD_MEMTYPE_DDR4 ) { XFsbl_DdrCalcHifAddr ( DdrDataPtr , HifAddr ) ; } else { XFsbl_DdrCalcHifAddrBrcMap ( DdrDataPtr , HifAddr ) ; } #else if ( PDimmPtr -> MemType != SPD_MEMTYPE_DDR4 ) { XFsbl_DdrCalcHifAddr ( DdrDataPtr , HifAddr ) ; } else { #if ( XFSBL_DDR4ADDRMAPPING == 1U ) XFsbl_DdrCalcHifAddrMemMap ( DdrDataPtr , HifAddr ) ; #else XFsbl_DdrCalcDdr4HifAddr ( DdrDataPtr , HifAddr ) ; #endif } #endif if ( PDimmPtr -> BusWidth <= 32U ) { for ( Index = 0U ; Index < 39U ; Index ++ ) { HifAddr [ Index ] = HifAddr [ Index + 1U ] ; } HifAddr [ 39U ] = 0U ; } if ( PDimmPtr -> BusWidth == 16U ) { for ( Index = 0U ; Index < 39U ; Index ++ ) { HifAddr [ Index ] = HifAddr [ Index + 1U ] ; } HifAddr [ 39U ] = 0U ; } XFsbl_DdrCalcBankAddr ( DdrDataPtr , HifAddr ) ; XFsbl_DdrCalcColAddr ( DdrDataPtr , HifAddr ) ; XFsbl_DdrCalcRowAddr ( DdrDataPtr , HifAddr ) ; XFsbl_DdrCalcBgAddr ( DdrDataPtr , HifAddr ) ; DdrDataPtr -> AddrMapCsBit0 = 0x1FU ; RegVal [ 0U ] = ( ( DdrDataPtr -> AddrMapCsBit0 & 0x1FU ) << 0U ) ; RegVal [ 1U ] = ( ( DdrDataPtr -> AddrMapBankBit [ 2U ] & 0x1FU ) << 16U ) ; RegVal [ 1U ] |= ( ( DdrDataPtr -> AddrMapBankBit [ 1U ] & 0x1FU ) << 8U ) ; RegVal [ 1U ] |= ( ( DdrDataPtr -> AddrMapBankBit [ 0U ] & 0x1FU ) << 0U ) ; RegVal [ 2U ] = ( ( DdrDataPtr -> AddrMapColBit [ 5U ] & 0xFU ) << 24U ) ; RegVal [ 2U ] |= ( ( DdrDataPtr -> AddrMapColBit [ 4U ] & 0xFU ) << 16U ) ; RegVal [ 2U ] |= ( ( DdrDataPtr -> AddrMapColBit [ 3U ] & 0xFU ) << 8U ) ; RegVal [ 2U ] |= ( ( DdrDataPtr -> AddrMapColBit [ 2U ] & 0xFU ) << 0U ) ; RegVal [ 3U ] = ( ( DdrDataPtr -> AddrMapColBit [ 9U ] & 0xFU ) << 24U ) ; RegVal [ 3U ] |= ( ( DdrDataPtr -> AddrMapColBit [ 8U ] & 0xFU ) << 16U ) ; RegVal [ 3U ] |= ( ( DdrDataPtr -> AddrMapColBit [ 7U ] & 0xFU ) << 8U ) ; RegVal [ 3U ] |= ( ( DdrDataPtr -> AddrMapColBit [ 6U ] & 0xFU ) << 0U ) ; RegVal [ 4U ] = ( ( DdrDataPtr -> AddrMapColBit [ 11U ] & 0xFU ) << 8U ) ; RegVal [ 4U ] |= ( ( DdrDataPtr -> AddrMapColBit [ 10U ] & 0xFU ) << 0U ) ; RegVal [ 5U ] = ( ( DdrDataPtr -> AddrMapRowBit [ 11U ] & 0xFU ) << 24U ) ; RegVal [ 5U ] |= ( ( DdrDataPtr -> AddrMapRowBits2To10 & 0xFU ) << 16U ) ; RegVal [ 5U ] |= ( ( DdrDataPtr -> AddrMapRowBit [ 1U ] & 0xFU ) << 8U ) ; RegVal [ 5U ] |= ( ( DdrDataPtr -> AddrMapRowBit [ 0U ] & 0xFU ) << 0U ) ; RegVal [ 6U ] = ( ( DdrDataPtr -> AddrMapRowBit [ 15U ] & 0xFU ) << 24U ) ; RegVal [ 6U ] |= ( ( DdrDataPtr -> AddrMapRowBit [ 14U ] & 0xFU ) << 16U ) ; RegVal [ 6U ] |= ( ( DdrDataPtr -> AddrMapRowBit [ 13U ] & 0xFU ) << 8U ) ; RegVal [ 6U ] |= ( ( DdrDataPtr -> AddrMapRowBit [ 12U ] & 0xFU ) << 0U ) ; RegVal [ 7U ] = ( ( DdrDataPtr -> AddrMapRowBit [ 17U ] & 0xFU ) << 8U ) ; RegVal [ 7U ] |= ( ( DdrDataPtr -> AddrMapRowBit [ 16U ] & 0xFU ) << 0U ) ; RegVal [ 8U ] = ( ( DdrDataPtr -> AddrMapBgBit [ 1U ] & 0x1FU ) << 8U ) ; RegVal [ 8U ] |= ( ( DdrDataPtr -> AddrMapBgBit [ 0U ] & 0x1FU ) << 0U ) ; RegVal [ 9U ] = ( ( DdrDataPtr -> AddrMapRowBit [ 5U ] & 0xFU ) << 24U ) ; RegVal [ 9U ] |= ( ( DdrDataPtr -> AddrMapRowBit [ 4U ] & 0xFU ) << 16U ) ; RegVal [ 9U ] |= ( ( DdrDataPtr -> AddrMapRowBit [ 3U ] & 0xFU ) << 8U ) ; RegVal [ 9U ] |= ( ( DdrDataPtr -> AddrMapRowBit [ 2U ] & 0xFU ) << 0U ) ; RegVal [ 10U ] = ( ( DdrDataPtr -> AddrMapRowBit [ 9U ] & 0xFU ) << 24U ) ; RegVal [ 10U ] |= ( ( DdrDataPtr -> AddrMapRowBit [ 8U ] & 0xFU ) << 16U ) ; RegVal [ 10U ] |= ( ( DdrDataPtr -> AddrMapRowBit [ 7U ] & 0xFU ) << 8U ) ; RegVal [ 10U ] |= ( ( DdrDataPtr -> AddrMapRowBit [ 6U ] & 0xFU ) << 0U ) ; RegVal [ 11U ] = ( ( DdrDataPtr -> AddrMapRowBit [ 10U ] & 0xFU ) << 0U ) ; for ( Index = 0U ; Index < 12U ; Index ++ ) { Xil_Out32 ( XFSBL_DDRC_BASE_ADDR + 0x200U + ( Index * 4U ) , RegVal [ Index ] ) ; } }
This function calculates the Address Mapping of the DDR
 @param       DdrDataPtr is pointer to DDR Initialization Data Structure
This function calculates the Address Mapping of the DDR @param DdrDataPtr is pointer to DDR Initialization Data Structure
/* Calculate the HIF Addresses when Video Buffers are Enabled */ /*
		 * Calculate the HIF Addresses for Non-DDR4 Mapping
		 */ /*
		 * Calculate the HIF Addresses when Bank-Row-Column Mapping is
		 * Enabled
		 */ /*
		 * Calculate the HIF Addresses for Non-DDR4 Mapping
		 */ /*
		 * Calculate the HIF Addresses when DDR4 Address Mapping
		 * is Enabled
		 */ /*
		 * Calculate the HIF Addresses for default DDR4 Mapping
		 */ /* Calculate Bank Address Map based on HIF Addresses */ /* Calculate Column Address Map based on HIF Addresses */ /* Calculate Row Address Map based on HIF Addresses */ /* Calculate Bank Group Address Map based on HIF Addresses */ /* Rank Width is 0U for the New DIMM */ /* Address Map Register 0U */ /* Address Map Register 1U */ /* Address Map Register 2U */ /* Address Map Register 3U */ /* Address Map Register 4U */ /* Address Map Register 5U */ /* Address Map Register 6U */ /* Address Map Register 7U */ /* Address Map Register 8U */ /* Address Map Register 9U */ /* Address Map Register 10U */ /* Address Map Register 11U */