src/dpdk/drivers/net/cxgbe/base/t4_hw.c
void t4_init_link_config(struct port_info *pi, u32 pcaps, u32 acaps,
			 u8 mdio_addr, u8 port_type, u8 mod_type)
{
	u8 fec_rs = 0, fec_baser = 0, fec_none = 0;
	struct link_config *lc = &pi->link_cfg;

	lc->pcaps = pcaps;
	lc->acaps = acaps;
	lc->admin_caps = acaps;
	lc->link_caps = 0;

	lc->mdio_addr = mdio_addr;
	lc->port_type = port_type;
	lc->mod_type = mod_type;

	lc->link_ok = 0;
	lc->link_down_rc = 0;

	/* Turn Tx and Rx pause off by default */
	lc->admin_caps &= ~V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC);
	lc->admin_caps &= ~V_FW_PORT_CAP32_802_3(M_FW_PORT_CAP32_802_3);
	if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)
		lc->admin_caps &= ~FW_PORT_CAP32_FORCE_PAUSE;

	/* Reset FEC caps to default values */
	if (lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) {
		if (lc->acaps & FW_PORT_CAP32_FEC_RS)
			fec_rs = 1;
		else if (lc->acaps & FW_PORT_CAP32_FEC_BASER_RS)
			fec_baser = 1;
		else
			fec_none = 1;

		lc->admin_caps &= ~V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC);
		t4_set_link_fec(pi, fec_rs, fec_baser, fec_none,
				&lc->admin_caps);
	}

	if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)
		lc->admin_caps &= ~FW_PORT_CAP32_FORCE_FEC;

	/* Reset MDI to AUTO */
	if (lc->pcaps & FW_PORT_CAP32_MDIAUTO) {
		lc->admin_caps &= ~V_FW_PORT_CAP32_MDI(M_FW_PORT_CAP32_MDI);
		lc->admin_caps |= V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
	}
}
/**
 * t4_init_link_config - initialize a link's SW state
 * @pi: the port info
 * @pcaps: link Port Capabilities
 * @acaps: link current Advertised Port Capabilities
 * @mdio_addr : address of the PHY
 * @port_type : firmware port type
 * @mod_type  : firmware module type
 *
 * Initializes the SW state maintained for each link, including the link's
 * capabilities and default speed/flow-control/autonegotiation settings.
 */


Initializes the SW state maintained for each link, including the link's
capabilities and default speed/flow-control/autonegotiation settings.
Initializes the SW state maintained for each link including the link ' s capabilities and default speed / flow - control / autonegotiation settings .
void t4_init_link_config(struct port_info *pi, u32 pcaps, u32 acaps,
			 u8 mdio_addr, u8 port_type, u8 mod_type)
{
	u8 fec_rs = 0, fec_baser = 0, fec_none = 0;
	struct link_config *lc = &pi->link_cfg;
	lc->pcaps = pcaps;
	lc->acaps = acaps;
	lc->admin_caps = acaps;
	lc->link_caps = 0;
	lc->mdio_addr = mdio_addr;
	lc->port_type = port_type;
	lc->mod_type = mod_type;
	lc->link_ok = 0;
	lc->link_down_rc = 0;
	lc->admin_caps &= ~V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC);
	lc->admin_caps &= ~V_FW_PORT_CAP32_802_3(M_FW_PORT_CAP32_802_3);
	if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)
		lc->admin_caps &= ~FW_PORT_CAP32_FORCE_PAUSE;
	if (lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) {
		if (lc->acaps & FW_PORT_CAP32_FEC_RS)
			fec_rs = 1;
		else if (lc->acaps & FW_PORT_CAP32_FEC_BASER_RS)
			fec_baser = 1;
		else
			fec_none = 1;
		lc->admin_caps &= ~V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC);
		t4_set_link_fec(pi, fec_rs, fec_baser, fec_none,
				&lc->admin_caps);
	}
	if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)
		lc->admin_caps &= ~FW_PORT_CAP32_FORCE_FEC;
	if (lc->pcaps & FW_PORT_CAP32_MDIAUTO) {
		lc->admin_caps &= ~V_FW_PORT_CAP32_MDI(M_FW_PORT_CAP32_MDI);
		lc->admin_caps |= V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
	}
}
void t4_init_link_config ( struct port_info * pi , u32 pcaps , u32 acaps , u8 mdio_addr , u8 port_type , u8 mod_type ) { u8 fec_rs = 0 , fec_baser = 0 , fec_none = 0 ; struct link_config * lc = & pi -> link_cfg ; lc -> pcaps = pcaps ; lc -> acaps = acaps ; lc -> admin_caps = acaps ; lc -> link_caps = 0 ; lc -> mdio_addr = mdio_addr ; lc -> port_type = port_type ; lc -> mod_type = mod_type ; lc -> link_ok = 0 ; lc -> link_down_rc = 0 ; lc -> admin_caps &= ~ V_FW_PORT_CAP32_FC ( M_FW_PORT_CAP32_FC ) ; lc -> admin_caps &= ~ V_FW_PORT_CAP32_802_3 ( M_FW_PORT_CAP32_802_3 ) ; if ( lc -> pcaps & FW_PORT_CAP32_FORCE_PAUSE ) lc -> admin_caps &= ~ FW_PORT_CAP32_FORCE_PAUSE ; if ( lc -> pcaps & V_FW_PORT_CAP32_FEC ( M_FW_PORT_CAP32_FEC ) ) { if ( lc -> acaps & FW_PORT_CAP32_FEC_RS ) fec_rs = 1 ; else if ( lc -> acaps & FW_PORT_CAP32_FEC_BASER_RS ) fec_baser = 1 ; else fec_none = 1 ; lc -> admin_caps &= ~ V_FW_PORT_CAP32_FEC ( M_FW_PORT_CAP32_FEC ) ; t4_set_link_fec ( pi , fec_rs , fec_baser , fec_none , & lc -> admin_caps ) ; } if ( lc -> pcaps & FW_PORT_CAP32_FORCE_FEC ) lc -> admin_caps &= ~ FW_PORT_CAP32_FORCE_FEC ; if ( lc -> pcaps & FW_PORT_CAP32_MDIAUTO ) { lc -> admin_caps &= ~ V_FW_PORT_CAP32_MDI ( M_FW_PORT_CAP32_MDI ) ; lc -> admin_caps |= V_FW_PORT_CAP32_MDI ( FW_PORT_CAP32_MDI_AUTO ) ; } }
t4_init_link_config - initialize a link's SW state
 @pi: the port info
 @pcaps: link Port Capabilities
 @acaps: link current Advertised Port Capabilities
 @mdio_addr : address of the PHY
 @port_type : firmware port type
 @mod_type  : firmware module type
t4_init_link_config - initialize a link ' s SW state @pi : the port info @pcaps : link Port Capabilities @acaps : link current Advertised Port Capabilities @mdio_addr : address of the PHY @port_type : firmware port type @mod_type : firmware module type
/* Turn Tx and Rx pause off by default */ /* Reset FEC caps to default values */ /* Reset MDI to AUTO */