XilinxProcessorIPLib/drivers/dp14txss/examples/src/zcu_pt_dp14_hdcp/xvid_clk_gen.c
int wait_for_lock(void)
{
	u32 count, error;
	count = error = 0;
	volatile u32 rdata=0;
	rdata = XClk_Wiz_ReadReg(CLK_WIZ_BASE, 0x04) & 1;

	while(!rdata){
		if(count == 10000){
			error++;
			break;
		}
		count++;
		rdata = XClk_Wiz_ReadReg(CLK_WIZ_BASE, 0x04) & 1;
	}
	return error;
}
/*****************************************************************************/
/**
*
* This function waits for PLL lock
*
* @return	pass/fail result. If there is error, none-zero value will return
*
* @note		None.
*
******************************************************************************/
This function waits for PLL lock
This function waits for PLL lock
int wait_for_lock(void)
{
	u32 count, error;
	count = error = 0;
	volatile u32 rdata=0;
	rdata = XClk_Wiz_ReadReg(CLK_WIZ_BASE, 0x04) & 1;
	while(!rdata){
		if(count == 10000){
			error++;
			break;
		}
		count++;
		rdata = XClk_Wiz_ReadReg(CLK_WIZ_BASE, 0x04) & 1;
	}
	return error;
}
int wait_for_lock ( void ) { u32 count , error ; count = error = 0 ; volatile u32 rdata = 0 ; rdata = XClk_Wiz_ReadReg ( CLK_WIZ_BASE , 0x04 ) & 1 ; while ( ! rdata ) { if ( count == 10000 ) { error ++ ; break ; } count ++ ; rdata = XClk_Wiz_ReadReg ( CLK_WIZ_BASE , 0x04 ) & 1 ; } return error ; }
This function waits for PLL lock
This function waits for PLL lock