XilinxProcessorIPLib/drivers/axiethernet/examples/xaxiethernet_example_intr_sgdma.c
int AxiEthernetSgDmaIntrCoalescingExample(XAxiEthernet *AxiEthernetInstancePtr,
						XAxiDma *DmaInstancePtr)
{
	int Status;
	u32 TxFrameLength;
	int PayloadSize = 100;
	u32 Index;
	u32 NumBd;
	u16 Threshold = 10;
	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(DmaInstancePtr);
	XAxiDma_Bd *BdPtr;
	XAxiDma_Bd *BdCurPtr;

	/*
	 * Clear variables shared with callbacks
	 */
	FramesRx = 0;
	FramesTx = 0;
	DeviceErrors = 0;

	/*
	 * Calculate the frame length (not including FCS)
	 */
	TxFrameLength = XAE_HDR_SIZE + PayloadSize;

	/*
	 * Setup packet to be transmitted. The same packet will be
	 * transmitted over and over
	 */
	AxiEthernetUtilFrameHdrFormatMAC(&TxFrame, AxiEthernetMAC);
	AxiEthernetUtilFrameHdrFormatType(&TxFrame, PayloadSize);
	AxiEthernetUtilFrameSetPayloadData(&TxFrame, PayloadSize);

	/*
	 * Flush the TX frame before giving it to DMA TX channel to transmit.
	 */
	Xil_DCacheFlushRange((UINTPTR)&TxFrame, TxFrameLength);

	/*
	 * Make sure Tx and Rx are enabled
	 */
	Status = XAxiEthernet_SetOptions(AxiEthernetInstancePtr,
				     XAE_TRANSMITTER_ENABLE_OPTION);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting options");
		return XST_FAILURE;
	}

	/*
	 * We don't care about the receive channel for this example,
	 * so turn it off, in case it was turned on earlier.
	 */

	Status = XAxiEthernet_ClearOptions(AxiEthernetInstancePtr,
				       XAE_RECEIVER_ENABLE_OPTION);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error clearing option");
		return XST_FAILURE;
	}

	/*
	 * Set the interrupt coalescing parameters for the test. The waitbound
	 * timer is set to 1 (ms) to catch the last few frames.
	 *
	 * If you set variable Threshold to some value larger than TXBD_CNT,
	 * then there can never be enough frames sent to meet the threshold.
	 * In this case the waitbound timer will always cause the interrupt to
	 * occur.
	 */
	Status = XAxiDma_BdRingSetCoalesce(TxRingPtr, Threshold, 255);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting coalescing settings");
		return XST_FAILURE;
	}

	/*
	 * Enable the send interrupts. Nothing should be transmitted yet as the
	 * device has not been started
	 */
	XAxiDma_BdRingIntEnable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);

	/*
	 * Prime the engine, allocate all BDs and assign them to the same buffer
	 */
	Status = XAxiDma_BdRingAlloc(TxRingPtr, Threshold, &BdPtr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error allocating TxBDs prior to starting");
		return XST_FAILURE;
	}

	/*
	 * Setup the TxBDs
	 */
	BdCurPtr = BdPtr;

	for (Index = 0; Index < Threshold; Index++) {
		XAxiDma_BdSetBufAddr(BdCurPtr, (UINTPTR)&TxFrame);
#ifndef XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL
		XAxiDma_BdSetLength(BdCurPtr, TxFrameLength);
#else
		XAxiDma_BdSetLength(BdCurPtr, TxFrameLength,
					TxRingPtr->MaxTransferLen);
#endif

		XAxiDma_BdSetCtrl(BdCurPtr, XAXIDMA_BD_CTRL_TXSOF_MASK |
				     XAXIDMA_BD_CTRL_TXEOF_MASK);
		BdCurPtr = (XAxiDma_Bd *) XAxiDma_BdRingNext(TxRingPtr, BdCurPtr);
	}

	/*
	 *  Enqueue all TxBDs to HW
	 */
	Status = XAxiDma_BdRingToHw(TxRingPtr, Threshold, BdPtr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error committing TxBDs prior to starting");
		return XST_FAILURE;
	}

	/*
	 * Start the device. Transmission commences now!
	 */
	XAxiEthernet_Start(AxiEthernetInstancePtr);

	/*
	 * Wait for the interrupt
	 */
	while (!FramesTx);

	NumBd = XAxiDma_BdRingFromHw(TxRingPtr, Threshold, &BdPtr);
	if (NumBd != Threshold) {
		AxiEthernetUtilErrorTrap("Error in interrupt coalescing");
	}
	else {
		/*
		 * Don't bother to check the BDs status, just free them
		 */
		Status = XAxiDma_BdRingFree(TxRingPtr, Threshold, BdPtr);
		if (Status != XST_SUCCESS) {
			AxiEthernetUtilErrorTrap("Error freeing TxBDs");
		}
	}

	/*
	 * Done sending frames. Stop the device
	 */
	XAxiEthernet_Stop(AxiEthernetInstancePtr);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This example sends frames with the interrupt coalescing settings altered
* from their defaults.
*
* The default settings will interrupt the processor after every frame has been
* sent. This example will increase the threshold resulting in lower CPU
* utilization since it spends less time servicing interrupts.
*
* @param	AxiEthernetInstancePtr is a pointer to the instance of the
*		Axi Ethernet component.
* @param	DmaInstancePtr   is a pointer to the instance of the Dma
*		component.
*
* @return	-XST_SUCCESS to indicate success
*		-XST_FAILURE to indicate failure
*
* @note     None.
*
******************************************************************************/
This example sends frames with the interrupt coalescing settings altered
from their defaults.

The default settings will interrupt the processor after every frame has been
sent. This example will increase the threshold resulting in lower CPU
utilization since it spends less time servicing interrupts.
This example sends frames with the interrupt coalescing settings altered from their defaults . The default settings will interrupt the processor after every frame has been sent . This example will increase the threshold resulting in lower CPU utilization since it spends less time servicing interrupts .
int AxiEthernetSgDmaIntrCoalescingExample(XAxiEthernet *AxiEthernetInstancePtr,
						XAxiDma *DmaInstancePtr)
{
	int Status;
	u32 TxFrameLength;
	int PayloadSize = 100;
	u32 Index;
	u32 NumBd;
	u16 Threshold = 10;
	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(DmaInstancePtr);
	XAxiDma_Bd *BdPtr;
	XAxiDma_Bd *BdCurPtr;
	FramesRx = 0;
	FramesTx = 0;
	DeviceErrors = 0;
	TxFrameLength = XAE_HDR_SIZE + PayloadSize;
	AxiEthernetUtilFrameHdrFormatMAC(&TxFrame, AxiEthernetMAC);
	AxiEthernetUtilFrameHdrFormatType(&TxFrame, PayloadSize);
	AxiEthernetUtilFrameSetPayloadData(&TxFrame, PayloadSize);
	Xil_DCacheFlushRange((UINTPTR)&TxFrame, TxFrameLength);
	Status = XAxiEthernet_SetOptions(AxiEthernetInstancePtr,
				     XAE_TRANSMITTER_ENABLE_OPTION);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting options");
		return XST_FAILURE;
	}
	Status = XAxiEthernet_ClearOptions(AxiEthernetInstancePtr,
				       XAE_RECEIVER_ENABLE_OPTION);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error clearing option");
		return XST_FAILURE;
	}
	Status = XAxiDma_BdRingSetCoalesce(TxRingPtr, Threshold, 255);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting coalescing settings");
		return XST_FAILURE;
	}
	XAxiDma_BdRingIntEnable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);
	Status = XAxiDma_BdRingAlloc(TxRingPtr, Threshold, &BdPtr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error allocating TxBDs prior to starting");
		return XST_FAILURE;
	}
	BdCurPtr = BdPtr;
	for (Index = 0; Index < Threshold; Index++) {
		XAxiDma_BdSetBufAddr(BdCurPtr, (UINTPTR)&TxFrame);
#ifndef XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL
		XAxiDma_BdSetLength(BdCurPtr, TxFrameLength);
#else
		XAxiDma_BdSetLength(BdCurPtr, TxFrameLength,
					TxRingPtr->MaxTransferLen);
#endif
		XAxiDma_BdSetCtrl(BdCurPtr, XAXIDMA_BD_CTRL_TXSOF_MASK |
				     XAXIDMA_BD_CTRL_TXEOF_MASK);
		BdCurPtr = (XAxiDma_Bd *) XAxiDma_BdRingNext(TxRingPtr, BdCurPtr);
	}
	Status = XAxiDma_BdRingToHw(TxRingPtr, Threshold, BdPtr);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error committing TxBDs prior to starting");
		return XST_FAILURE;
	}
	XAxiEthernet_Start(AxiEthernetInstancePtr);
	while (!FramesTx);
	NumBd = XAxiDma_BdRingFromHw(TxRingPtr, Threshold, &BdPtr);
	if (NumBd != Threshold) {
		AxiEthernetUtilErrorTrap("Error in interrupt coalescing");
	}
	else {
		Status = XAxiDma_BdRingFree(TxRingPtr, Threshold, BdPtr);
		if (Status != XST_SUCCESS) {
			AxiEthernetUtilErrorTrap("Error freeing TxBDs");
		}
	}
	XAxiEthernet_Stop(AxiEthernetInstancePtr);
	return XST_SUCCESS;
}
int AxiEthernetSgDmaIntrCoalescingExample ( XAxiEthernet * AxiEthernetInstancePtr , XAxiDma * DmaInstancePtr ) { int Status ; u32 TxFrameLength ; int PayloadSize = 100 ; u32 Index ; u32 NumBd ; u16 Threshold = 10 ; XAxiDma_BdRing * TxRingPtr = XAxiDma_GetTxRing ( DmaInstancePtr ) ; XAxiDma_Bd * BdPtr ; XAxiDma_Bd * BdCurPtr ; FramesRx = 0 ; FramesTx = 0 ; DeviceErrors = 0 ; TxFrameLength = XAE_HDR_SIZE + PayloadSize ; AxiEthernetUtilFrameHdrFormatMAC ( & TxFrame , AxiEthernetMAC ) ; AxiEthernetUtilFrameHdrFormatType ( & TxFrame , PayloadSize ) ; AxiEthernetUtilFrameSetPayloadData ( & TxFrame , PayloadSize ) ; Xil_DCacheFlushRange ( ( UINTPTR ) & TxFrame , TxFrameLength ) ; Status = XAxiEthernet_SetOptions ( AxiEthernetInstancePtr , XAE_TRANSMITTER_ENABLE_OPTION ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } Status = XAxiEthernet_ClearOptions ( AxiEthernetInstancePtr , XAE_RECEIVER_ENABLE_OPTION ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } Status = XAxiDma_BdRingSetCoalesce ( TxRingPtr , Threshold , 255 ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } XAxiDma_BdRingIntEnable ( TxRingPtr , XAXIDMA_IRQ_ALL_MASK ) ; Status = XAxiDma_BdRingAlloc ( TxRingPtr , Threshold , & BdPtr ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } BdCurPtr = BdPtr ; for ( Index = 0 ; Index < Threshold ; Index ++ ) { XAxiDma_BdSetBufAddr ( BdCurPtr , ( UINTPTR ) & TxFrame ) ; #ifndef XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL XAxiDma_BdSetLength ( BdCurPtr , TxFrameLength ) ; #else XAxiDma_BdSetLength ( BdCurPtr , TxFrameLength , TxRingPtr -> MaxTransferLen ) ; #endif XAxiDma_BdSetCtrl ( BdCurPtr , XAXIDMA_BD_CTRL_TXSOF_MASK | XAXIDMA_BD_CTRL_TXEOF_MASK ) ; BdCurPtr = ( XAxiDma_Bd * ) XAxiDma_BdRingNext ( TxRingPtr , BdCurPtr ) ; } Status = XAxiDma_BdRingToHw ( TxRingPtr , Threshold , BdPtr ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } XAxiEthernet_Start ( AxiEthernetInstancePtr ) ; while ( ! FramesTx ) ; NumBd = XAxiDma_BdRingFromHw ( TxRingPtr , Threshold , & BdPtr ) ; if ( NumBd != Threshold ) { AxiEthernetUtilErrorTrap ( " " ) ; } else { Status = XAxiDma_BdRingFree ( TxRingPtr , Threshold , BdPtr ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; } } XAxiEthernet_Stop ( AxiEthernetInstancePtr ) ; return XST_SUCCESS ; }
This example sends frames with the interrupt coalescing settings altered
from their defaults.
This example sends frames with the interrupt coalescing settings altered from their defaults .
/*
	 * Clear variables shared with callbacks
	 */ /*
	 * Calculate the frame length (not including FCS)
	 */ /*
	 * Setup packet to be transmitted. The same packet will be
	 * transmitted over and over
	 */ /*
	 * Flush the TX frame before giving it to DMA TX channel to transmit.
	 */ /*
	 * Make sure Tx and Rx are enabled
	 */ /*
	 * We don't care about the receive channel for this example,
	 * so turn it off, in case it was turned on earlier.
	 */ /*
	 * Set the interrupt coalescing parameters for the test. The waitbound
	 * timer is set to 1 (ms) to catch the last few frames.
	 *
	 * If you set variable Threshold to some value larger than TXBD_CNT,
	 * then there can never be enough frames sent to meet the threshold.
	 * In this case the waitbound timer will always cause the interrupt to
	 * occur.
	 */ /*
	 * Enable the send interrupts. Nothing should be transmitted yet as the
	 * device has not been started
	 */ /*
	 * Prime the engine, allocate all BDs and assign them to the same buffer
	 */ /*
	 * Setup the TxBDs
	 */ /*
	 *  Enqueue all TxBDs to HW
	 */ /*
	 * Start the device. Transmission commences now!
	 */ /*
	 * Wait for the interrupt
	 */ /*
		 * Don't bother to check the BDs status, just free them
		 */ /*
	 * Done sending frames. Stop the device
	 */