XilinxProcessorIPLib/drivers/dp12rxss/src/xdprxss_dbg.c
void XDpRxSs_ReportLinkInfo(XDpRxSs *InstancePtr)
{
	XDp_Config *RxConfig = &InstancePtr->DpPtr->Config;
	u32 RegValue;
	u32 Index;

	/* Verify argument. */
	Xil_AssertVoid(InstancePtr != NULL);

	/* Read link rate and lane count */
	xil_printf("\n\rLINK_BW_SET (0x400) status in DPCD = 0x%x\n\r",
			XDpRxSs_ReadReg(RxConfig->BaseAddr,
					XDP_RX_DPCD_LINK_BW_SET));
	xil_printf("LANE_COUNT_SET (0x404) status in DPCD = 0x%x\n\r",
			XDpRxSs_ReadReg(RxConfig->BaseAddr,
					XDP_RX_DPCD_LANE_COUNT_SET));

	/* Read lanes status */
	xil_printf("\n\rLANE0_1_STATUS (0x043C) in DPCD = 0x%x\n\r",
			XDpRxSs_ReadReg(RxConfig->BaseAddr,
				XDP_RX_DPCD_LANE01_STATUS));
	xil_printf("LANE2_3_STATUS (0x440) in DPCD = 0x%x\n\r",
			XDpRxSs_ReadReg(RxConfig->BaseAddr,
				XDP_RX_DPCD_LANE23_STATUS));

	/* Read symbol error which is RC register. Two times read is required
	 * due to during training if this register is read it gives all F's,
	 * second time read it gives proper value.
	 */
	for (Index = 0; Index < 2; Index++) {
		RegValue = XDpRxSs_ReadReg(RxConfig->BaseAddr,
				XDP_RX_DPCD_SYM_ERR_CNT01);
	}
	xil_printf("\n\rSYM_ERR_CNT01 (0x448) = 0x%x\n\r", RegValue);

	for (Index = 0; Index < 2; Index++) {
		RegValue = XDpRxSs_ReadReg(RxConfig->BaseAddr,
				XDP_RX_DPCD_SYM_ERR_CNT23);
	}
	xil_printf("SYM_ERR_CNT23 (0x44C) = 0x%x\n\r", RegValue);

	/* PHY status */
	xil_printf("\n\rPHY_STATUS (0x208) = 0x%x\n\r",
		XDpRxSs_ReadReg(RxConfig->BaseAddr, XDP_RX_PHY_STATUS));

	xil_printf("\n\r");
}
/*****************************************************************************/
/**
*
* This function prints the link status, selected resolution, link rate /lane
* count symbol error.
*
* @param	InstancePtr is a pointer to the XDpRxSs core instance.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function prints the link status, selected resolution, link rate /lane
count symbol error.
This function prints the link status selected resolution link rate / lane count symbol error .
void XDpRxSs_ReportLinkInfo(XDpRxSs *InstancePtr)
{
	XDp_Config *RxConfig = &InstancePtr->DpPtr->Config;
	u32 RegValue;
	u32 Index;
	Xil_AssertVoid(InstancePtr != NULL);
	xil_printf("\n\rLINK_BW_SET (0x400) status in DPCD = 0x%x\n\r",
			XDpRxSs_ReadReg(RxConfig->BaseAddr,
					XDP_RX_DPCD_LINK_BW_SET));
	xil_printf("LANE_COUNT_SET (0x404) status in DPCD = 0x%x\n\r",
			XDpRxSs_ReadReg(RxConfig->BaseAddr,
					XDP_RX_DPCD_LANE_COUNT_SET));
	xil_printf("\n\rLANE0_1_STATUS (0x043C) in DPCD = 0x%x\n\r",
			XDpRxSs_ReadReg(RxConfig->BaseAddr,
				XDP_RX_DPCD_LANE01_STATUS));
	xil_printf("LANE2_3_STATUS (0x440) in DPCD = 0x%x\n\r",
			XDpRxSs_ReadReg(RxConfig->BaseAddr,
				XDP_RX_DPCD_LANE23_STATUS));
	for (Index = 0; Index < 2; Index++) {
		RegValue = XDpRxSs_ReadReg(RxConfig->BaseAddr,
				XDP_RX_DPCD_SYM_ERR_CNT01);
	}
	xil_printf("\n\rSYM_ERR_CNT01 (0x448) = 0x%x\n\r", RegValue);
	for (Index = 0; Index < 2; Index++) {
		RegValue = XDpRxSs_ReadReg(RxConfig->BaseAddr,
				XDP_RX_DPCD_SYM_ERR_CNT23);
	}
	xil_printf("SYM_ERR_CNT23 (0x44C) = 0x%x\n\r", RegValue);
	xil_printf("\n\rPHY_STATUS (0x208) = 0x%x\n\r",
		XDpRxSs_ReadReg(RxConfig->BaseAddr, XDP_RX_PHY_STATUS));
	xil_printf("\n\r");
}
void XDpRxSs_ReportLinkInfo ( XDpRxSs * InstancePtr ) { XDp_Config * RxConfig = & InstancePtr -> DpPtr -> Config ; u32 RegValue ; u32 Index ; Xil_AssertVoid ( InstancePtr != NULL ) ; xil_printf ( " \n \r \n \r " , XDpRxSs_ReadReg ( RxConfig -> BaseAddr , XDP_RX_DPCD_LINK_BW_SET ) ) ; xil_printf ( " \n \r " , XDpRxSs_ReadReg ( RxConfig -> BaseAddr , XDP_RX_DPCD_LANE_COUNT_SET ) ) ; xil_printf ( " \n \r \n \r " , XDpRxSs_ReadReg ( RxConfig -> BaseAddr , XDP_RX_DPCD_LANE01_STATUS ) ) ; xil_printf ( " \n \r " , XDpRxSs_ReadReg ( RxConfig -> BaseAddr , XDP_RX_DPCD_LANE23_STATUS ) ) ; for ( Index = 0 ; Index < 2 ; Index ++ ) { RegValue = XDpRxSs_ReadReg ( RxConfig -> BaseAddr , XDP_RX_DPCD_SYM_ERR_CNT01 ) ; } xil_printf ( " \n \r \n \r " , RegValue ) ; for ( Index = 0 ; Index < 2 ; Index ++ ) { RegValue = XDpRxSs_ReadReg ( RxConfig -> BaseAddr , XDP_RX_DPCD_SYM_ERR_CNT23 ) ; } xil_printf ( " \n \r " , RegValue ) ; xil_printf ( " \n \r \n \r " , XDpRxSs_ReadReg ( RxConfig -> BaseAddr , XDP_RX_PHY_STATUS ) ) ; xil_printf ( " \n \r " ) ; }
This function prints the link status, selected resolution, link rate /lane
count symbol error.
This function prints the link status selected resolution link rate / lane count symbol error .
/* Verify argument. */ /* Read link rate and lane count */ /* Read lanes status */ /* Read symbol error which is RC register. Two times read is required
	 * due to during training if this register is read it gives all F's,
	 * second time read it gives proper value.
	 */ /* PHY status */