XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_hdmi_intr.c
void XHdmiphy1_HdmiRxTimerTimeoutHandler(XHdmiphy1 *InstancePtr)
{
    XHdmiphy1_ChannelId ChId;
    XHdmiphy1_PllType PllType;
    u32 Status;
    u8 Id, Id0, Id1;
#if (XPAR_HDMIPHY1_0_TRANSCEIVER == XHDMIPHY1_GTYE5)
	u8 CfgValComp;
#endif

    if (!InstancePtr->RxHdmi21Cfg.IsEnabled) {
        XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_RX_TMR, 1);
    } else {
		if (InstancePtr->Config.RxRefClkSel ==
				InstancePtr->Config.RxFrlRefClkSel) {
			/* Set MMCM CLKINSEL to CLK1 */
			XHdmiphy1_MmcmSetClkinsel(InstancePtr, 0, XHDMIPHY1_DIR_RX,
					XHDMIPHY1_MMCM_CLKINSEL_CLKIN1);

			/* Start RX MMCM. */
			XHdmiphy1_MmcmStart(InstancePtr, 0, XHDMIPHY1_DIR_RX);
		}
    }

    /* Determine PLL type. */
    PllType = XHdmiphy1_GetPllType(InstancePtr, 0, XHDMIPHY1_DIR_RX,
            XHDMIPHY1_CHANNEL_ID_CH1);
    /* Determine which channel(s) to operate on. */
    ChId = XHdmiphy1_GetRcfgChId(InstancePtr, 0, XHDMIPHY1_DIR_RX, PllType);

    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);


    /* Set RX parameters. */
    Status = XHdmiphy1_SetHdmiRxParam(InstancePtr, 0, ChId);
    if (Status != XST_SUCCESS) {
        for (Id = Id0; Id <= Id1; Id++) {
            InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].RxState =
                XHDMIPHY1_GT_STATE_IDLE;
        }

        return;
    }

    /* Enable DRU to set the clock muxes. */
    XHdmiphy1_DruEnable(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA,
            InstancePtr->HdmiRxDruIsEnabled);

    /* Update GT DRU mode. */
    XHdmiphy1_HdmiGtDruModeEnable(InstancePtr,
    		InstancePtr->HdmiRxDruIsEnabled);

#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    /* Enable PLL. */
    XHdmiphy1_PowerDownGtPll(InstancePtr, 0,
        (PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
        XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA, FALSE);

    /* Update reference clock election. */
    if (InstancePtr->RxHdmi21Cfg.IsEnabled == FALSE) {
        XHdmiphy1_CfgPllRefClkSel(InstancePtr, 0,
            ((PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
                XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA),
            ((InstancePtr->HdmiRxDruIsEnabled) ?
                InstancePtr->Config.DruRefClkSel :
                InstancePtr->Config.RxRefClkSel));
    }

    /* Update RefClk selection. */
    XHdmiphy1_WriteCfgRefClkSelReg(InstancePtr, 0);

    /* Determine PLL type. */
    PllType = XHdmiphy1_GetPllType(InstancePtr, 0, XHDMIPHY1_DIR_RX,
            XHDMIPHY1_CHANNEL_ID_CH1);
    /* Determine which channel(s) to operate on. */
    ChId = XHdmiphy1_GetRcfgChId(InstancePtr, 0, XHDMIPHY1_DIR_RX, PllType);

    XHdmiphy1_ClkReconfig(InstancePtr, 0, ChId);
    XHdmiphy1_OutDivReconfig(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
            XHDMIPHY1_DIR_RX);

    XHdmiphy1_DirReconfig(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
        XHDMIPHY1_DIR_RX);

    /* Assert RX PLL reset. */
    XHdmiphy1_ResetGtPll(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
        XHDMIPHY1_DIR_RX, TRUE);

    /* De-assert RX PLL reset. */
    XHdmiphy1_ResetGtPll(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
            XHDMIPHY1_DIR_RX, FALSE);

    for (Id = Id0; Id <= Id1; Id++) {
            InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].RxState =
			XHDMIPHY1_GT_STATE_LOCK;
    }


#else
	XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].RxState =
            XHDMIPHY1_GT_STATE_GPO_RE;
    }

    /* Compare the current and next CFG values */
	CfgValComp = XHdmiphy1_CheckLineRateCfg(InstancePtr, 0,
					XHDMIPHY1_CHANNEL_ID_CH1, XHDMIPHY1_DIR_RX);

	if (!CfgValComp) {
		/* Assert GPI port. */
		XHdmiphy1_SetGpi(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
				XHDMIPHY1_DIR_RX, TRUE);
	}
	else {
		XHdmiphy1_HdmiRxGpoRisingEdgeHandler(InstancePtr);
	}
#endif
}
/*****************************************************************************/
/**
* This function is the handler for RX timer timeout events.
*
* @param    InstancePtr is a pointer to the HDMIPHY instance.
*
* @return   None.
*
* @note     None.
*
******************************************************************************/
This function is the handler for RX timer timeout events.
This function is the handler for RX timer timeout events .
void XHdmiphy1_HdmiRxTimerTimeoutHandler(XHdmiphy1 *InstancePtr)
{
    XHdmiphy1_ChannelId ChId;
    XHdmiphy1_PllType PllType;
    u32 Status;
    u8 Id, Id0, Id1;
#if (XPAR_HDMIPHY1_0_TRANSCEIVER == XHDMIPHY1_GTYE5)
	u8 CfgValComp;
#endif
    if (!InstancePtr->RxHdmi21Cfg.IsEnabled) {
        XHdmiphy1_LogWrite(InstancePtr, XHDMIPHY1_LOG_EVT_RX_TMR, 1);
    } else {
		if (InstancePtr->Config.RxRefClkSel ==
				InstancePtr->Config.RxFrlRefClkSel) {
			XHdmiphy1_MmcmSetClkinsel(InstancePtr, 0, XHDMIPHY1_DIR_RX,
					XHDMIPHY1_MMCM_CLKINSEL_CLKIN1);
			XHdmiphy1_MmcmStart(InstancePtr, 0, XHDMIPHY1_DIR_RX);
		}
    }
    PllType = XHdmiphy1_GetPllType(InstancePtr, 0, XHDMIPHY1_DIR_RX,
            XHDMIPHY1_CHANNEL_ID_CH1);
    ChId = XHdmiphy1_GetRcfgChId(InstancePtr, 0, XHDMIPHY1_DIR_RX, PllType);
    XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    Status = XHdmiphy1_SetHdmiRxParam(InstancePtr, 0, ChId);
    if (Status != XST_SUCCESS) {
        for (Id = Id0; Id <= Id1; Id++) {
            InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].RxState =
                XHDMIPHY1_GT_STATE_IDLE;
        }
        return;
    }
    XHdmiphy1_DruEnable(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA,
            InstancePtr->HdmiRxDruIsEnabled);
    XHdmiphy1_HdmiGtDruModeEnable(InstancePtr,
    		InstancePtr->HdmiRxDruIsEnabled);
#if (XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5)
    XHdmiphy1_PowerDownGtPll(InstancePtr, 0,
        (PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
        XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA, FALSE);
    if (InstancePtr->RxHdmi21Cfg.IsEnabled == FALSE) {
        XHdmiphy1_CfgPllRefClkSel(InstancePtr, 0,
            ((PllType == XHDMIPHY1_PLL_TYPE_CPLL) ?
                XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA),
            ((InstancePtr->HdmiRxDruIsEnabled) ?
                InstancePtr->Config.DruRefClkSel :
                InstancePtr->Config.RxRefClkSel));
    }
    XHdmiphy1_WriteCfgRefClkSelReg(InstancePtr, 0);
    PllType = XHdmiphy1_GetPllType(InstancePtr, 0, XHDMIPHY1_DIR_RX,
            XHDMIPHY1_CHANNEL_ID_CH1);
    ChId = XHdmiphy1_GetRcfgChId(InstancePtr, 0, XHDMIPHY1_DIR_RX, PllType);
    XHdmiphy1_ClkReconfig(InstancePtr, 0, ChId);
    XHdmiphy1_OutDivReconfig(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
            XHDMIPHY1_DIR_RX);
    XHdmiphy1_DirReconfig(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
        XHDMIPHY1_DIR_RX);
    XHdmiphy1_ResetGtPll(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
        XHDMIPHY1_DIR_RX, TRUE);
    XHdmiphy1_ResetGtPll(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
            XHDMIPHY1_DIR_RX, FALSE);
    for (Id = Id0; Id <= Id1; Id++) {
            InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].RxState =
			XHDMIPHY1_GT_STATE_LOCK;
    }
#else
	XHdmiphy1_Ch2Ids(InstancePtr, XHDMIPHY1_CHANNEL_ID_CHA, &Id0, &Id1);
    for (Id = Id0; Id <= Id1; Id++) {
        InstancePtr->Quads[0].Plls[XHDMIPHY1_CH2IDX(Id)].RxState =
            XHDMIPHY1_GT_STATE_GPO_RE;
    }
	CfgValComp = XHdmiphy1_CheckLineRateCfg(InstancePtr, 0,
					XHDMIPHY1_CHANNEL_ID_CH1, XHDMIPHY1_DIR_RX);
	if (!CfgValComp) {
		XHdmiphy1_SetGpi(InstancePtr, 0, XHDMIPHY1_CHANNEL_ID_CHA,
				XHDMIPHY1_DIR_RX, TRUE);
	}
	else {
		XHdmiphy1_HdmiRxGpoRisingEdgeHandler(InstancePtr);
	}
#endif
}
void XHdmiphy1_HdmiRxTimerTimeoutHandler ( XHdmiphy1 * InstancePtr ) { XHdmiphy1_ChannelId ChId ; XHdmiphy1_PllType PllType ; u32 Status ; u8 Id , Id0 , Id1 ; #if ( XPAR_HDMIPHY1_0_TRANSCEIVER == XHDMIPHY1_GTYE5 ) u8 CfgValComp ; #endif if ( ! InstancePtr -> RxHdmi21Cfg . IsEnabled ) { XHdmiphy1_LogWrite ( InstancePtr , XHDMIPHY1_LOG_EVT_RX_TMR , 1 ) ; } else { if ( InstancePtr -> Config . RxRefClkSel == InstancePtr -> Config . RxFrlRefClkSel ) { XHdmiphy1_MmcmSetClkinsel ( InstancePtr , 0 , XHDMIPHY1_DIR_RX , XHDMIPHY1_MMCM_CLKINSEL_CLKIN1 ) ; XHdmiphy1_MmcmStart ( InstancePtr , 0 , XHDMIPHY1_DIR_RX ) ; } } PllType = XHdmiphy1_GetPllType ( InstancePtr , 0 , XHDMIPHY1_DIR_RX , XHDMIPHY1_CHANNEL_ID_CH1 ) ; ChId = XHdmiphy1_GetRcfgChId ( InstancePtr , 0 , XHDMIPHY1_DIR_RX , PllType ) ; XHdmiphy1_Ch2Ids ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; Status = XHdmiphy1_SetHdmiRxParam ( InstancePtr , 0 , ChId ) ; if ( Status != XST_SUCCESS ) { for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . RxState = XHDMIPHY1_GT_STATE_IDLE ; } return ; } XHdmiphy1_DruEnable ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , InstancePtr -> HdmiRxDruIsEnabled ) ; XHdmiphy1_HdmiGtDruModeEnable ( InstancePtr , InstancePtr -> HdmiRxDruIsEnabled ) ; #if ( XPAR_HDMIPHY1_0_TRANSCEIVER != XHDMIPHY1_GTYE5 ) XHdmiphy1_PowerDownGtPll ( InstancePtr , 0 , ( PllType == XHDMIPHY1_PLL_TYPE_CPLL ) ? XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA , FALSE ) ; if ( InstancePtr -> RxHdmi21Cfg . IsEnabled == FALSE ) { XHdmiphy1_CfgPllRefClkSel ( InstancePtr , 0 , ( ( PllType == XHDMIPHY1_PLL_TYPE_CPLL ) ? XHDMIPHY1_CHANNEL_ID_CHA : XHDMIPHY1_CHANNEL_ID_CMNA ) , ( ( InstancePtr -> HdmiRxDruIsEnabled ) ? InstancePtr -> Config . DruRefClkSel : InstancePtr -> Config . RxRefClkSel ) ) ; } XHdmiphy1_WriteCfgRefClkSelReg ( InstancePtr , 0 ) ; PllType = XHdmiphy1_GetPllType ( InstancePtr , 0 , XHDMIPHY1_DIR_RX , XHDMIPHY1_CHANNEL_ID_CH1 ) ; ChId = XHdmiphy1_GetRcfgChId ( InstancePtr , 0 , XHDMIPHY1_DIR_RX , PllType ) ; XHdmiphy1_ClkReconfig ( InstancePtr , 0 , ChId ) ; XHdmiphy1_OutDivReconfig ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_RX ) ; XHdmiphy1_DirReconfig ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_RX ) ; XHdmiphy1_ResetGtPll ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_RX , TRUE ) ; XHdmiphy1_ResetGtPll ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_RX , FALSE ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . RxState = XHDMIPHY1_GT_STATE_LOCK ; } #else XHdmiphy1_Ch2Ids ( InstancePtr , XHDMIPHY1_CHANNEL_ID_CHA , & Id0 , & Id1 ) ; for ( Id = Id0 ; Id <= Id1 ; Id ++ ) { InstancePtr -> Quads [ 0 ] . Plls [ XHDMIPHY1_CH2IDX ( Id ) ] . RxState = XHDMIPHY1_GT_STATE_GPO_RE ; } CfgValComp = XHdmiphy1_CheckLineRateCfg ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CH1 , XHDMIPHY1_DIR_RX ) ; if ( ! CfgValComp ) { XHdmiphy1_SetGpi ( InstancePtr , 0 , XHDMIPHY1_CHANNEL_ID_CHA , XHDMIPHY1_DIR_RX , TRUE ) ; } else { XHdmiphy1_HdmiRxGpoRisingEdgeHandler ( InstancePtr ) ; } #endif }
This function is the handler for RX timer timeout events.
This function is the handler for RX timer timeout events .
/* Set MMCM CLKINSEL to CLK1 */ /* Start RX MMCM. */ /* Determine PLL type. */ /* Determine which channel(s) to operate on. */ /* Set RX parameters. */ /* Enable DRU to set the clock muxes. */ /* Update GT DRU mode. */ /* Enable PLL. */ /* Update reference clock election. */ /* Update RefClk selection. */ /* Determine PLL type. */ /* Determine which channel(s) to operate on. */ /* Assert RX PLL reset. */ /* De-assert RX PLL reset. */ /* Compare the current and next CFG values */ /* Assert GPI port. */