src/dpdk/drivers/net/igc/base/igc_mac.c
static int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index)
{
	u32 rar_low, rar_high;

	DEBUGFUNC("igc_rar_set_generic");

	/* HW expects these in little endian so we reverse the byte order
	 * from network order (big endian) to little endian
	 */
	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));

	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));

	/* If MAC address zero, no need to set the AV bit */
	if (rar_low || rar_high)
		rar_high |= IGC_RAH_AV;

	/* Some bridges will combine consecutive 32-bit writes into
	 * a single burst write, which will malfunction on some parts.
	 * The flushes avoid this.
	 */
	IGC_WRITE_REG(hw, IGC_RAL(index), rar_low);
	IGC_WRITE_FLUSH(hw);
	IGC_WRITE_REG(hw, IGC_RAH(index), rar_high);
	IGC_WRITE_FLUSH(hw);

	return IGC_SUCCESS;
}
/**
 *  igc_rar_set_generic - Set receive address register
 *  @hw: pointer to the HW structure
 *  @addr: pointer to the receive address
 *  @index: receive address array register
 *
 *  Sets the receive address array register at index to the address passed
 *  in by addr.
 **/
Set receive address register
@hw: pointer to the HW structure
@addr: pointer to the receive address
@index: receive address array register

Sets the receive address array register at index to the address passed
in by addr.
Set receive address register @hw : pointer to the HW structure @addr : pointer to the receive address @index : receive address array register Sets the receive address array register at index to the address passed in by addr .
static int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index)
{
	u32 rar_low, rar_high;
	DEBUGFUNC("igc_rar_set_generic");
	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
	if (rar_low || rar_high)
		rar_high |= IGC_RAH_AV;
	IGC_WRITE_REG(hw, IGC_RAL(index), rar_low);
	IGC_WRITE_FLUSH(hw);
	IGC_WRITE_REG(hw, IGC_RAH(index), rar_high);
	IGC_WRITE_FLUSH(hw);
	return IGC_SUCCESS;
}
static int igc_rar_set_generic ( struct igc_hw * hw , u8 * addr , u32 index ) { u32 rar_low , rar_high ; DEBUGFUNC ( " " ) ; rar_low = ( ( u32 ) addr [ 0 ] | ( ( u32 ) addr [ 1 ] << 8 ) | ( ( u32 ) addr [ 2 ] << 16 ) | ( ( u32 ) addr [ 3 ] << 24 ) ) ; rar_high = ( ( u32 ) addr [ 4 ] | ( ( u32 ) addr [ 5 ] << 8 ) ) ; if ( rar_low || rar_high ) rar_high |= IGC_RAH_AV ; IGC_WRITE_REG ( hw , IGC_RAL ( index ) , rar_low ) ; IGC_WRITE_FLUSH ( hw ) ; IGC_WRITE_REG ( hw , IGC_RAH ( index ) , rar_high ) ; IGC_WRITE_FLUSH ( hw ) ; return IGC_SUCCESS ; }
igc_rar_set_generic - Set receive address register
  @hw: pointer to the HW structure
  @addr: pointer to the receive address
  @index: receive address array register
igc_rar_set_generic - Set receive address register @hw : pointer to the HW structure @addr : pointer to the receive address @index : receive address array register
/* HW expects these in little endian so we reverse the byte order
	 * from network order (big endian) to little endian
	 */ /* If MAC address zero, no need to set the AV bit */ /* Some bridges will combine consecutive 32-bit writes into
	 * a single burst write, which will malfunction on some parts.
	 * The flushes avoid this.
	 */