XilinxProcessorIPLib/drivers/sysmonpsu/src/xsysmonpsu.c
u8 XSysMonPsu_UpdateAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
	u16 Divisor;
	UINTPTR EffectiveBaseAddress;
	u32 RegValue;
	u32 InputFreq;
	u32 Count = 0U;

	/* Assert the arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));

	/* Calculate the effective baseaddress based on the Sysmon instance. */
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);

	InputFreq = InstancePtr->Config.InputClockMHz;
	/* Read the divisor value from the Configuration Register 2. */
	Divisor = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
							XSYSMONPSU_CFG_REG2_OFFSET);
	Divisor = Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT;

	while (Count < XSM_POLL_TIMEOUT) {
		if (Divisor == 0U) {
			if ((SysmonBlk == XSYSMON_PS) &&
			((InputFreq/8U) >= 1U) && ((InputFreq/8U) <= 26U)) {
				break;
			}
			if ((SysmonBlk == XSYSMON_PL) &&
			((InputFreq/2U) >= 1U) && ((InputFreq/2U) <= 26U)) {
				break;
			}
		} else if (((InputFreq/Divisor) >= 1U) &&
				((InputFreq/Divisor) <= 26U)) {
			break;
		} else {
			Divisor += 1U;
		}
		Count += 1U;
	}

	/*
	 * Read the Configuration Register 2 and the clear the clock divisor
	 * bits.
	 */
	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
					XSYSMONPSU_CFG_REG2_OFFSET);
	RegValue &= ~(XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK);

	/* Write the divisor value into the Configuration Register 2. */
	RegValue |= ((u32)Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT) &
					XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK;
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET,
			 RegValue);

	return (u8)Divisor;
}
/****************************************************************************/
/**
*
* The function update the ADCCLK divisor to the Configuration Register 2.
*
* @param	InstancePtr is a pointer to the XSysMon instance.
* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
*       block or PL Sysmon block register region.
*
* @return	The divisor update  the Configuration Register 2.
*
* @note		The ADCCLK is an internal clock used by the ADC and is
*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
*		divided by the user selection in the Configuration Register 2.
*
*****************************************************************************/
The function update the ADCCLK divisor to the Configuration Register 2.
The function update the ADCCLK divisor to the Configuration Register 2 .
u8 XSysMonPsu_UpdateAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
{
	u16 Divisor;
	UINTPTR EffectiveBaseAddress;
	u32 RegValue;
	u32 InputFreq;
	u32 Count = 0U;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);
	InputFreq = InstancePtr->Config.InputClockMHz;
	Divisor = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
							XSYSMONPSU_CFG_REG2_OFFSET);
	Divisor = Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT;
	while (Count < XSM_POLL_TIMEOUT) {
		if (Divisor == 0U) {
			if ((SysmonBlk == XSYSMON_PS) &&
			((InputFreq/8U) >= 1U) && ((InputFreq/8U) <= 26U)) {
				break;
			}
			if ((SysmonBlk == XSYSMON_PL) &&
			((InputFreq/2U) >= 1U) && ((InputFreq/2U) <= 26U)) {
				break;
			}
		} else if (((InputFreq/Divisor) >= 1U) &&
				((InputFreq/Divisor) <= 26U)) {
			break;
		} else {
			Divisor += 1U;
		}
		Count += 1U;
	}
	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
					XSYSMONPSU_CFG_REG2_OFFSET);
	RegValue &= ~(XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK);
	RegValue |= ((u32)Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT) &
					XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK;
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET,
			 RegValue);
	return (u8)Divisor;
}
u8 XSysMonPsu_UpdateAdcClkDivisor ( XSysMonPsu * InstancePtr , u32 SysmonBlk ) { u16 Divisor ; UINTPTR EffectiveBaseAddress ; u32 RegValue ; u32 InputFreq ; u32 Count = 0U ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( ( SysmonBlk == XSYSMON_PS ) || ( SysmonBlk == XSYSMON_PL ) ) ; EffectiveBaseAddress = XSysMonPsu_GetEffBaseAddress ( InstancePtr -> Config . BaseAddress , SysmonBlk ) ; InputFreq = InstancePtr -> Config . InputClockMHz ; Divisor = ( u16 ) XSysmonPsu_ReadReg ( EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET ) ; Divisor = Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT ; while ( Count < XSM_POLL_TIMEOUT ) { if ( Divisor == 0U ) { if ( ( SysmonBlk == XSYSMON_PS ) && ( ( InputFreq / 8U ) >= 1U ) && ( ( InputFreq / 8U ) <= 26U ) ) { break ; } if ( ( SysmonBlk == XSYSMON_PL ) && ( ( InputFreq / 2U ) >= 1U ) && ( ( InputFreq / 2U ) <= 26U ) ) { break ; } } else if ( ( ( InputFreq / Divisor ) >= 1U ) && ( ( InputFreq / Divisor ) <= 26U ) ) { break ; } else { Divisor += 1U ; } Count += 1U ; } RegValue = XSysmonPsu_ReadReg ( EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET ) ; RegValue &= ~ ( XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK ) ; RegValue |= ( ( u32 ) Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT ) & XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET , RegValue ) ; return ( u8 ) Divisor ; }
The function update the ADCCLK divisor to the Configuration Register 2.
The function update the ADCCLK divisor to the Configuration Register 2 .
/* Assert the arguments. */ /* Calculate the effective baseaddress based on the Sysmon instance. */ /* Read the divisor value from the Configuration Register 2. */ /*
	 * Read the Configuration Register 2 and the clear the clock divisor
	 * bits.
	 */ /* Write the divisor value into the Configuration Register 2. */