XilinxProcessorIPLib/drivers/hdcp1x/src/xhdcp1x_port_hdmi_rx.c
static int XHdcp1x_PortHdmiRxDisable(XHdcp1x *InstancePtr)
{
	u8 Offset = 0;
	u8 Value = 0;
	int NumLeft = 0;
	int Status = XST_SUCCESS;

	/* Verify arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->Port.PhyIfPtr != NULL);

	/* Clear the hdcp registers */
	Value = 0;
	Offset = 0x05;
	/* Clear HDCP register space from 0x05 to AKSV (0x10) */
	NumLeft = 11;
	while (NumLeft-- > 0) {
		XHdcp1x_PortHdmiRxWrite(InstancePtr, Offset++, &Value, 1);
	}
	/* Clear the HDCP RSVD (0x16) register */
	Offset = 22;
	NumLeft = 2;
	while (NumLeft-- > 0) {
		XHdcp1x_PortHdmiRxWrite(InstancePtr, Offset++, &Value, 1);
	}
	/* Clear HDCP register space from VH0 (0x20) to RSVD (0x34) */
	Offset = 32;
	NumLeft = 20;
	while (NumLeft-- > 0) {
		XHdcp1x_PortHdmiRxWrite(InstancePtr, Offset++, &Value, 1);
	}
	/* Clear HDCP register space for Bcaps (0x40) */
	XHdcp1x_PortHdmiRxWrite(InstancePtr, XHDCP1X_PORT_OFFSET_BCAPS,
					&Value, 1);

	/* Clear HDCP register space for Bstatus (0x41 and 0x42).
	 * Do not clear HDMI_MODE field. */
	XHdcp1x_PortHdmiRxWrite(InstancePtr, XHDCP1X_PORT_OFFSET_BSTATUS,
					&Value, 1);
	XHdcp1x_PortHdmiRxRead(InstancePtr, (XHDCP1X_PORT_OFFSET_BSTATUS + 1),
					&Value, 1);
	Value &= (XHDCP1X_PORT_BIT_BSTATUS_HDMI_MODE >> 8);
	XHdcp1x_PortHdmiRxWrite(InstancePtr, (XHDCP1X_PORT_OFFSET_BSTATUS + 1),
					&Value, 1);

	/* Clear HDCP register space for KSV FIFO (0x43) */
	Value = 0;
	XHdcp1x_PortHdmiRxWrite(InstancePtr, XHDCP1X_PORT_OFFSET_KSVFIFO,
					&Value, 1);

	return (Status);
}
/*****************************************************************************/
/**
* This function disables a HDCP port device.
*
* @param	InstancePtr is the id of the device to disable.
*
* @return
*		- XST_SUCCESS if successful.
*
* @note		None.
*
******************************************************************************/
This function disables a HDCP port device.
This function disables a HDCP port device .
static int XHdcp1x_PortHdmiRxDisable(XHdcp1x *InstancePtr)
{
	u8 Offset = 0;
	u8 Value = 0;
	int NumLeft = 0;
	int Status = XST_SUCCESS;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->Port.PhyIfPtr != NULL);
	Value = 0;
	Offset = 0x05;
	NumLeft = 11;
	while (NumLeft-- > 0) {
		XHdcp1x_PortHdmiRxWrite(InstancePtr, Offset++, &Value, 1);
	}
	Offset = 22;
	NumLeft = 2;
	while (NumLeft-- > 0) {
		XHdcp1x_PortHdmiRxWrite(InstancePtr, Offset++, &Value, 1);
	}
	Offset = 32;
	NumLeft = 20;
	while (NumLeft-- > 0) {
		XHdcp1x_PortHdmiRxWrite(InstancePtr, Offset++, &Value, 1);
	}
	XHdcp1x_PortHdmiRxWrite(InstancePtr, XHDCP1X_PORT_OFFSET_BCAPS,
					&Value, 1);
	XHdcp1x_PortHdmiRxWrite(InstancePtr, XHDCP1X_PORT_OFFSET_BSTATUS,
					&Value, 1);
	XHdcp1x_PortHdmiRxRead(InstancePtr, (XHDCP1X_PORT_OFFSET_BSTATUS + 1),
					&Value, 1);
	Value &= (XHDCP1X_PORT_BIT_BSTATUS_HDMI_MODE >> 8);
	XHdcp1x_PortHdmiRxWrite(InstancePtr, (XHDCP1X_PORT_OFFSET_BSTATUS + 1),
					&Value, 1);
	Value = 0;
	XHdcp1x_PortHdmiRxWrite(InstancePtr, XHDCP1X_PORT_OFFSET_KSVFIFO,
					&Value, 1);
	return (Status);
}
static int XHdcp1x_PortHdmiRxDisable ( XHdcp1x * InstancePtr ) { u8 Offset = 0 ; u8 Value = 0 ; int NumLeft = 0 ; int Status = XST_SUCCESS ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> Port . PhyIfPtr != NULL ) ; Value = 0 ; Offset = 0x05 ; NumLeft = 11 ; while ( NumLeft -- > 0 ) { XHdcp1x_PortHdmiRxWrite ( InstancePtr , Offset ++ , & Value , 1 ) ; } Offset = 22 ; NumLeft = 2 ; while ( NumLeft -- > 0 ) { XHdcp1x_PortHdmiRxWrite ( InstancePtr , Offset ++ , & Value , 1 ) ; } Offset = 32 ; NumLeft = 20 ; while ( NumLeft -- > 0 ) { XHdcp1x_PortHdmiRxWrite ( InstancePtr , Offset ++ , & Value , 1 ) ; } XHdcp1x_PortHdmiRxWrite ( InstancePtr , XHDCP1X_PORT_OFFSET_BCAPS , & Value , 1 ) ; XHdcp1x_PortHdmiRxWrite ( InstancePtr , XHDCP1X_PORT_OFFSET_BSTATUS , & Value , 1 ) ; XHdcp1x_PortHdmiRxRead ( InstancePtr , ( XHDCP1X_PORT_OFFSET_BSTATUS + 1 ) , & Value , 1 ) ; Value &= ( XHDCP1X_PORT_BIT_BSTATUS_HDMI_MODE >> 8 ) ; XHdcp1x_PortHdmiRxWrite ( InstancePtr , ( XHDCP1X_PORT_OFFSET_BSTATUS + 1 ) , & Value , 1 ) ; Value = 0 ; XHdcp1x_PortHdmiRxWrite ( InstancePtr , XHDCP1X_PORT_OFFSET_KSVFIFO , & Value , 1 ) ; return ( Status ) ; }
This function disables a HDCP port device.
This function disables a HDCP port device .
/* Verify arguments. */ /* Clear the hdcp registers */ /* Clear HDCP register space from 0x05 to AKSV (0x10) */ /* Clear the HDCP RSVD (0x16) register */ /* Clear HDCP register space from VH0 (0x20) to RSVD (0x34) */ /* Clear HDCP register space for Bcaps (0x40) */ /* Clear HDCP register space for Bstatus (0x41 and 0x42).
	 * Do not clear HDMI_MODE field. */ /* Clear HDCP register space for KSV FIFO (0x43) */