src/dpdk/drivers/net/ixgbe/base/ixgbe_x550.c
s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
				u32 device_type, u16 phy_data)
{
	s32 status;
	u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;

	DEBUGFUNC("ixgbe_write_phy_reg_x550a");

	if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
		status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
						 phy_data);
		hw->mac.ops.release_swfw_sync(hw, mask);
	} else {
		status = IXGBE_ERR_SWFW_SYNC;
	}

	return status;
}
/**
 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
 * @hw: pointer to hardware structure
 * @reg_addr: 32 bit PHY register to write
 * @device_type: 5 bit device type
 * @phy_data: Data to write to the PHY register
 *
 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
 * The PHY Token is needed since the MDIO is shared between to MAC instances.
 **/
Writes specified PHY register
@hw: pointer to hardware structure
@reg_addr: 32 bit PHY register to write
@device_type: 5 bit device type
@phy_data: Data to write to the PHY register

Writes a value to specified PHY register using the SWFW lock and PHY Token.
The PHY Token is needed since the MDIO is shared between to MAC instances.
Writes specified PHY register @hw : pointer to hardware structure @reg_addr : 32 bit PHY register to write @device_type : 5 bit device type @phy_data : Data to write to the PHY register Writes a value to specified PHY register using the SWFW lock and PHY Token . The PHY Token is needed since the MDIO is shared between to MAC instances .
s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
				u32 device_type, u16 phy_data)
{
	s32 status;
	u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
	DEBUGFUNC("ixgbe_write_phy_reg_x550a");
	if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
		status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
						 phy_data);
		hw->mac.ops.release_swfw_sync(hw, mask);
	} else {
		status = IXGBE_ERR_SWFW_SYNC;
	}
	return status;
}
s32 ixgbe_write_phy_reg_x550a ( struct ixgbe_hw * hw , u32 reg_addr , u32 device_type , u16 phy_data ) { s32 status ; u32 mask = hw -> phy . phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM ; DEBUGFUNC ( " " ) ; if ( hw -> mac . ops . acquire_swfw_sync ( hw , mask ) == IXGBE_SUCCESS ) { status = hw -> phy . ops . write_reg_mdi ( hw , reg_addr , device_type , phy_data ) ; hw -> mac . ops . release_swfw_sync ( hw , mask ) ; } else { status = IXGBE_ERR_SWFW_SYNC ; } return status ; }
ixgbe_write_phy_reg_x550a - Writes specified PHY register
 @hw: pointer to hardware structure
 @reg_addr: 32 bit PHY register to write
 @device_type: 5 bit device type
 @phy_data: Data to write to the PHY register
ixgbe_write_phy_reg_x550a - Writes specified PHY register @hw : pointer to hardware structure @reg_addr : 32 bit PHY register to write @device_type : 5 bit device type @phy_data : Data to write to the PHY register