XilinxProcessorIPLib/drivers/board_common/src/rfclk/src/xrfclk.c
u32 XRFClk_ConfigOutputDividerAndMUXOnLMK(u32 PortId, u32 DCLKoutX_DIV,
					  u32 DCLKoutX_MUX, u32 SDCLKoutY_MUX,
					  u32 SYSREF_DIV)
{
	u32 ret = XST_SUCCESS;
#ifdef XPS_BOARD_ZCU111
	(void)PortId;
	(void)DCLKoutX_DIV;
	(void)DCLKoutX_MUX;
	(void)SDCLKoutY_MUX;
	(void)SYSREF_DIV;
	LOG("not supported");
	ret = XST_FAILURE;
#else
	Xil_AssertNonvoid((PortId <= LMK_PORT_ID_MAX) && (PortId > 0));
	Xil_AssertNonvoid(DCLKoutX_DIV <= LMK_DCLKOUTX_DIV_MAX);
	Xil_AssertNonvoid(DCLKoutX_MUX <= LMK_DCLKOUTX_MUX_MAX);
	Xil_AssertNonvoid(SDCLKoutY_MUX <= LMK_SDCLKOUTY_MUX_MAX);
	Xil_AssertNonvoid((SYSREF_DIV >= LMK_SYSREF_DIV_MIN) &&
			  (SYSREF_DIV <= LMK_SYSREF_DIV_MAX));

	u32 Addr;
	u8 data;
	if ((PortId >= LMK_PORT_ID_MAX) || (PortId == 0) ||
	    (DCLKoutX_DIV > LMK_DCLKOUTX_DIV_MAX) ||
	    (DCLKoutX_MUX > LMK_DCLKOUTX_MUX_MAX) ||
	    (SDCLKoutY_MUX > LMK_SDCLKOUTY_MUX_MAX) ||
	    (SYSREF_DIV < LMK_SYSREF_DIV_MIN) ||
	    (SYSREF_DIV > LMK_SYSREF_DIV_MAX)) {
		LOG("wrong LMK settings");
		return XST_FAILURE;
	}

	/* Set DCLKoutX_DIV */
	Addr = (LMK_DCLKOUTX_DIV_PORT0_ADDR + LMK_ADDRESS_STEP * PortId)
	       << LMK_ADDRESS_SHIFT;
	data = DCLKoutX_DIV;
	if (XST_SUCCESS != XRFClk_WriteReg(RFCLK_LMK, Addr + data)) {
		LOG("Set DCLKoutX_DIV");
		return XST_FAILURE;
	}

	/* Set DCLKoutX_MUX */
	Addr = (LMK_DCLKOUTX_MUX_PORT0_ADDR + LMK_ADDRESS_STEP * PortId)
	       << LMK_ADDRESS_SHIFT;
	data = DCLKoutX_MUX;
	if (XST_SUCCESS != XRFClk_WriteReg(RFCLK_LMK, Addr + data)) {
		LOG("Set DCLKoutX_MUX");
		return XST_FAILURE;
	}

	/* Set SDCLKoutY_MUX */
	Addr = (LMK_SDCLKOUTY_MUX_PORT0_ADDR + LMK_ADDRESS_STEP * PortId)
	       << LMK_ADDRESS_SHIFT;
	data = DCLKoutX_MUX;
	if (XST_SUCCESS != XRFClk_WriteReg(RFCLK_LMK, Addr + data)) {
		LOG("Set DCLKoutY_DIV");
		return XST_FAILURE;
	}

	/* Set SYSREF_DIV */
	Addr = LMK_SYSREF_DIV_MSB_PORT0_ADDR << LMK_ADDRESS_SHIFT;
	data = (SYSREF_DIV >> 8) & 0xff;
	if (XST_SUCCESS != XRFClk_WriteReg(RFCLK_LMK, Addr + data)) {
		LOG("Set SYSREF_DIV");
		return XST_FAILURE;
	}
	Addr = LMK_SYSREF_DIV_LSB_PORT0_ADDR << LMK_ADDRESS_SHIFT;
	data = SYSREF_DIV & 0xff;
	if (XST_SUCCESS != XRFClk_WriteReg(RFCLK_LMK, Addr + data)) {
		LOG("update SYSREF_DIV");
		return XST_FAILURE;
	}
#endif
	return ret;
}
/****************************************************************************/
/**
*
* This function is used to configure a clock divider and the output port MUX
* state on LMK04828. For the details consult tables 16, 18, 19 and 25 in
* the lmk04828.pdf datasheet.
*
* @param	PortId indicates a LMK04828 port id, [1:7].
* @param	DCLKoutX_DIV sets divider for the clock output [0:31].
* @param	DCLKoutX_MUX selects input to the device clk buffer [0:3].
* @param	SDCLKoutY_MUX sets input to SDCLKoutY [0:1].
* @param	SYSREF_DIV sets SYSREF output divider [8:8191]
*
* @return
*	- XST_SUCCESS if successful.
*	- XST_FAILURE if failed.
*
* @note		None
*
****************************************************************************/
This function is used to configure a clock divider and the output port MUX
state on LMK04828. For the details consult tables 16, 18, 19 and 25 in
the lmk04828.pdf datasheet.
This function is used to configure a clock divider and the output port MUX state on LMK04828 . For the details consult tables 16 18 19 and 25 in the lmk04828 . pdf datasheet .
u32 XRFClk_ConfigOutputDividerAndMUXOnLMK(u32 PortId, u32 DCLKoutX_DIV,
					  u32 DCLKoutX_MUX, u32 SDCLKoutY_MUX,
					  u32 SYSREF_DIV)
{
	u32 ret = XST_SUCCESS;
#ifdef XPS_BOARD_ZCU111
	(void)PortId;
	(void)DCLKoutX_DIV;
	(void)DCLKoutX_MUX;
	(void)SDCLKoutY_MUX;
	(void)SYSREF_DIV;
	LOG("not supported");
	ret = XST_FAILURE;
#else
	Xil_AssertNonvoid((PortId <= LMK_PORT_ID_MAX) && (PortId > 0));
	Xil_AssertNonvoid(DCLKoutX_DIV <= LMK_DCLKOUTX_DIV_MAX);
	Xil_AssertNonvoid(DCLKoutX_MUX <= LMK_DCLKOUTX_MUX_MAX);
	Xil_AssertNonvoid(SDCLKoutY_MUX <= LMK_SDCLKOUTY_MUX_MAX);
	Xil_AssertNonvoid((SYSREF_DIV >= LMK_SYSREF_DIV_MIN) &&
			  (SYSREF_DIV <= LMK_SYSREF_DIV_MAX));
	u32 Addr;
	u8 data;
	if ((PortId >= LMK_PORT_ID_MAX) || (PortId == 0) ||
	    (DCLKoutX_DIV > LMK_DCLKOUTX_DIV_MAX) ||
	    (DCLKoutX_MUX > LMK_DCLKOUTX_MUX_MAX) ||
	    (SDCLKoutY_MUX > LMK_SDCLKOUTY_MUX_MAX) ||
	    (SYSREF_DIV < LMK_SYSREF_DIV_MIN) ||
	    (SYSREF_DIV > LMK_SYSREF_DIV_MAX)) {
		LOG("wrong LMK settings");
		return XST_FAILURE;
	}
	Addr = (LMK_DCLKOUTX_DIV_PORT0_ADDR + LMK_ADDRESS_STEP * PortId)
	       << LMK_ADDRESS_SHIFT;
	data = DCLKoutX_DIV;
	if (XST_SUCCESS != XRFClk_WriteReg(RFCLK_LMK, Addr + data)) {
		LOG("Set DCLKoutX_DIV");
		return XST_FAILURE;
	}
	Addr = (LMK_DCLKOUTX_MUX_PORT0_ADDR + LMK_ADDRESS_STEP * PortId)
	       << LMK_ADDRESS_SHIFT;
	data = DCLKoutX_MUX;
	if (XST_SUCCESS != XRFClk_WriteReg(RFCLK_LMK, Addr + data)) {
		LOG("Set DCLKoutX_MUX");
		return XST_FAILURE;
	}
	Addr = (LMK_SDCLKOUTY_MUX_PORT0_ADDR + LMK_ADDRESS_STEP * PortId)
	       << LMK_ADDRESS_SHIFT;
	data = DCLKoutX_MUX;
	if (XST_SUCCESS != XRFClk_WriteReg(RFCLK_LMK, Addr + data)) {
		LOG("Set DCLKoutY_DIV");
		return XST_FAILURE;
	}
	Addr = LMK_SYSREF_DIV_MSB_PORT0_ADDR << LMK_ADDRESS_SHIFT;
	data = (SYSREF_DIV >> 8) & 0xff;
	if (XST_SUCCESS != XRFClk_WriteReg(RFCLK_LMK, Addr + data)) {
		LOG("Set SYSREF_DIV");
		return XST_FAILURE;
	}
	Addr = LMK_SYSREF_DIV_LSB_PORT0_ADDR << LMK_ADDRESS_SHIFT;
	data = SYSREF_DIV & 0xff;
	if (XST_SUCCESS != XRFClk_WriteReg(RFCLK_LMK, Addr + data)) {
		LOG("update SYSREF_DIV");
		return XST_FAILURE;
	}
#endif
	return ret;
}
u32 XRFClk_ConfigOutputDividerAndMUXOnLMK ( u32 PortId , u32 DCLKoutX_DIV , u32 DCLKoutX_MUX , u32 SDCLKoutY_MUX , u32 SYSREF_DIV ) { u32 ret = XST_SUCCESS ; #ifdef XPS_BOARD_ZCU111 ( void ) PortId ; ( void ) DCLKoutX_DIV ; ( void ) DCLKoutX_MUX ; ( void ) SDCLKoutY_MUX ; ( void ) SYSREF_DIV ; LOG ( " " ) ; ret = XST_FAILURE ; #else Xil_AssertNonvoid ( ( PortId <= LMK_PORT_ID_MAX ) && ( PortId > 0 ) ) ; Xil_AssertNonvoid ( DCLKoutX_DIV <= LMK_DCLKOUTX_DIV_MAX ) ; Xil_AssertNonvoid ( DCLKoutX_MUX <= LMK_DCLKOUTX_MUX_MAX ) ; Xil_AssertNonvoid ( SDCLKoutY_MUX <= LMK_SDCLKOUTY_MUX_MAX ) ; Xil_AssertNonvoid ( ( SYSREF_DIV >= LMK_SYSREF_DIV_MIN ) && ( SYSREF_DIV <= LMK_SYSREF_DIV_MAX ) ) ; u32 Addr ; u8 data ; if ( ( PortId >= LMK_PORT_ID_MAX ) || ( PortId == 0 ) || ( DCLKoutX_DIV > LMK_DCLKOUTX_DIV_MAX ) || ( DCLKoutX_MUX > LMK_DCLKOUTX_MUX_MAX ) || ( SDCLKoutY_MUX > LMK_SDCLKOUTY_MUX_MAX ) || ( SYSREF_DIV < LMK_SYSREF_DIV_MIN ) || ( SYSREF_DIV > LMK_SYSREF_DIV_MAX ) ) { LOG ( " " ) ; return XST_FAILURE ; } Addr = ( LMK_DCLKOUTX_DIV_PORT0_ADDR + LMK_ADDRESS_STEP * PortId ) << LMK_ADDRESS_SHIFT ; data = DCLKoutX_DIV ; if ( XST_SUCCESS != XRFClk_WriteReg ( RFCLK_LMK , Addr + data ) ) { LOG ( " " ) ; return XST_FAILURE ; } Addr = ( LMK_DCLKOUTX_MUX_PORT0_ADDR + LMK_ADDRESS_STEP * PortId ) << LMK_ADDRESS_SHIFT ; data = DCLKoutX_MUX ; if ( XST_SUCCESS != XRFClk_WriteReg ( RFCLK_LMK , Addr + data ) ) { LOG ( " " ) ; return XST_FAILURE ; } Addr = ( LMK_SDCLKOUTY_MUX_PORT0_ADDR + LMK_ADDRESS_STEP * PortId ) << LMK_ADDRESS_SHIFT ; data = DCLKoutX_MUX ; if ( XST_SUCCESS != XRFClk_WriteReg ( RFCLK_LMK , Addr + data ) ) { LOG ( " " ) ; return XST_FAILURE ; } Addr = LMK_SYSREF_DIV_MSB_PORT0_ADDR << LMK_ADDRESS_SHIFT ; data = ( SYSREF_DIV >> 8 ) & 0xff ; if ( XST_SUCCESS != XRFClk_WriteReg ( RFCLK_LMK , Addr + data ) ) { LOG ( " " ) ; return XST_FAILURE ; } Addr = LMK_SYSREF_DIV_LSB_PORT0_ADDR << LMK_ADDRESS_SHIFT ; data = SYSREF_DIV & 0xff ; if ( XST_SUCCESS != XRFClk_WriteReg ( RFCLK_LMK , Addr + data ) ) { LOG ( " " ) ; return XST_FAILURE ; } #endif return ret ; }
This function is used to configure a clock divider and the output port MUX
state on LMK04828.
This function is used to configure a clock divider and the output port MUX state on LMK04828 .
/* Set DCLKoutX_DIV */ /* Set DCLKoutX_MUX */ /* Set SDCLKoutY_MUX */ /* Set SYSREF_DIV */