lib/bsp/standalone/src/arm/ARMv8/32bit/xil_cache.c
void Xil_DCacheFlushLine(u32 adr)
{
	u32 currmask;

	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);

	/* Select cache level 0 and D cache in CSSR */
	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
	isb();
	mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x3F)));
	/* Wait for invalidate to complete */
	dsb();
	/* Select cache level 1 and D cache in CSSR */
	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
	isb();
	mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x3F)));
	/* Wait for invalidate to complete */
	dsb();
	mtcpsr(currmask);
}
/****************************************************************************/
/**
 * @brief	Flush a Data cache line. If the byte specified by the
 *		address (adr) is cached by the Data cache, the cacheline
 *		containing that byte is invalidated. If the cacheline is
 *		modified (dirty), the entire contents of the cacheline are
 *		written to system memory before the line is invalidated.
 *
 * @param	adr: 32bit address of the data to be flushed.
 *
 * @return	None.
 *
 * @note	The bottom 4 bits are set to 0, forced by architecture.
 *
 ****************************************************************************/
@brief       Flush a Data cache line. If the byte specified by the
address (adr) is cached by the Data cache, the cacheline
containing that byte is invalidated. If the cacheline is
modified (dirty), the entire contents of the cacheline are
written to system memory before the line is invalidated.

@param       adr: 32bit address of the data to be flushed.

@return      None.

@note        The bottom 4 bits are set to 0, forced by architecture.
@brief Flush a Data cache line . If the byte specified by the address ( adr ) is cached by the Data cache the cacheline containing that byte is invalidated . If the cacheline is modified ( dirty ) the entire contents of the cacheline are written to system memory before the line is invalidated . @param adr : 32bit address of the data to be flushed . @return None . @note The bottom 4 bits are set to 0 forced by architecture .
void Xil_DCacheFlushLine(u32 adr)
{
	u32 currmask;
	currmask = mfcpsr();
	mtcpsr(currmask | IRQ_FIQ_MASK);
	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
	isb();
	mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x3F)));
	dsb();
	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
	isb();
	mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x3F)));
	dsb();
	mtcpsr(currmask);
}
void Xil_DCacheFlushLine ( u32 adr ) { u32 currmask ; currmask = mfcpsr ( ) ; mtcpsr ( currmask | IRQ_FIQ_MASK ) ; mtcp ( XREG_CP15_CACHE_SIZE_SEL , 0x0 ) ; isb ( ) ; mtcp ( XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC , ( adr & ( ~ 0x3F ) ) ) ; dsb ( ) ; mtcp ( XREG_CP15_CACHE_SIZE_SEL , 0x2 ) ; isb ( ) ; mtcp ( XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC , ( adr & ( ~ 0x3F ) ) ) ; dsb ( ) ; mtcpsr ( currmask ) ; }
@brief       Flush a Data cache line.
@brief Flush a Data cache line .
/* Select cache level 0 and D cache in CSSR */ /* Wait for invalidate to complete */ /* Select cache level 1 and D cache in CSSR */ /* Wait for invalidate to complete */