XilinxProcessorIPLib/drivers/emacps/examples/xemacps_example_intr_dma.c
void XEmacPsClkSetup(XEmacPs *EmacPsInstancePtr, u16 EmacPsIntrId)
{
	u32 ClkCntrl;
	u32 BaseAddress = EmacPsInstancePtr->Config.BaseAddress;

	if (GemVersion == 2)
	{
		/*************************************/
		/* Setup device for first-time usage */
		/*************************************/

	/* SLCR unlock */
	*(volatile unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
	if (BaseAddress == ZYNQ_EMACPS_0_BASEADDR) {
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
		/* GEM0 1G clock configuration*/
		ClkCntrl =
		*(volatile unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR);
		ClkCntrl &= EMACPS_SLCR_DIV_MASK;
		ClkCntrl |= (EmacPsInstancePtr->Config.S1GDiv1 << 20);
		ClkCntrl |= (EmacPsInstancePtr->Config.S1GDiv0 << 8);
		*(volatile unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) =
								ClkCntrl;
#endif
	} else if (BaseAddress == ZYNQ_EMACPS_1_BASEADDR) {
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1
		/* GEM1 1G clock configuration*/
		ClkCntrl =
		*(volatile unsigned int *)(SLCR_GEM1_CLK_CTRL_ADDR);
		ClkCntrl &= EMACPS_SLCR_DIV_MASK;
		ClkCntrl |= (EmacPsInstancePtr->Config.S1GDiv1 << 20);
		ClkCntrl |= (EmacPsInstancePtr->Config.S1GDiv0 << 8);
		*(volatile unsigned int *)(SLCR_GEM1_CLK_CTRL_ADDR) =
								ClkCntrl;
#endif
	}
	/* SLCR lock */
	*(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
	#ifndef __MICROBLAZE__
	sleep(1);
	#else
	unsigned long count=0;
	while(count < 0xffff)
	{
		count++;
	}
	#endif
	}

	if ((GemVersion == GEMVERSION_ZYNQMP) && ((Platform & PLATFORM_MASK) == PLATFORM_SILICON)) {

#ifdef XPAR_PSU_CRL_APB_S_AXI_BASEADDR
		if (BaseAddress == ZYNQMP_EMACPS_0_BASEADDR) {
			/* GEM0 1G clock configuration*/
			ClkCntrl =
			*(volatile unsigned int *)(CRL_GEM0_REF_CTRL);
			ClkCntrl &= ~CRL_GEM_DIV_MASK;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv1 << CRL_GEM_DIV1_SHIFT;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv0 << CRL_GEM_DIV0_SHIFT;
			*(volatile unsigned int *)(CRL_GEM0_REF_CTRL) =
									ClkCntrl;

		}
		if (BaseAddress == ZYNQMP_EMACPS_1_BASEADDR) {

			/* GEM1 1G clock configuration*/
			ClkCntrl =
			*(volatile unsigned int *)(CRL_GEM1_REF_CTRL);
			ClkCntrl &= ~CRL_GEM_DIV_MASK;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv1 << CRL_GEM_DIV1_SHIFT;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv0 << CRL_GEM_DIV0_SHIFT;
			*(volatile unsigned int *)(CRL_GEM1_REF_CTRL) =
									ClkCntrl;
		}
		if (BaseAddress == ZYNQMP_EMACPS_2_BASEADDR) {

			/* GEM2 1G clock configuration*/
			ClkCntrl =
			*(volatile unsigned int *)(CRL_GEM2_REF_CTRL);
			ClkCntrl &= ~CRL_GEM_DIV_MASK;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv1 << CRL_GEM_DIV1_SHIFT;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv0 << CRL_GEM_DIV0_SHIFT;
			*(volatile unsigned int *)(CRL_GEM2_REF_CTRL) =
									ClkCntrl;

		}
		if (BaseAddress == ZYNQMP_EMACPS_3_BASEADDR) {
			/* GEM3 1G clock configuration*/
			ClkCntrl =
			*(volatile unsigned int *)(CRL_GEM3_REF_CTRL);
			ClkCntrl &= ~CRL_GEM_DIV_MASK;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv1 << CRL_GEM_DIV1_SHIFT;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv0 << CRL_GEM_DIV0_SHIFT;
			*(volatile unsigned int *)(CRL_GEM3_REF_CTRL) =
									ClkCntrl;
		}
#endif
	}
	if ((GemVersion == GEMVERSION_VERSAL) &&
		((Platform & PLATFORM_MASK_VERSAL) == PLATFORM_VERSALSIL)) {

#ifdef XPAR_PSV_CRL_0_S_AXI_BASEADDR
		if (BaseAddress == VERSAL_EMACPS_0_BASEADDR) {
			/* GEM0 1G clock configuration*/
#if EL1_NONSECURE
			Xil_Smc(PM_SET_DIVIDER_SMC_FID, (((u64)EmacPsInstancePtr->Config.S1GDiv0 << 32) | CLK_GEM0_REF), 0, 0, 0, 0, 0, 0);
#else
			ClkCntrl = Xil_In32((UINTPTR)CRL_GEM0_REF_CTRL);
			ClkCntrl &= ~CRL_GEM_DIV_VERSAL_MASK;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv0 << CRL_GEM_DIV_VERSAL_SHIFT;
			Xil_Out32((UINTPTR)CRL_GEM0_REF_CTRL, ClkCntrl);
#endif
		}
		if (BaseAddress == VERSAL_EMACPS_0_BASEADDR) {

			/* GEM1 1G clock configuration*/
#if EL1_NONSECURE
			Xil_Smc(PM_SET_DIVIDER_SMC_FID, (((u64)EmacPsInstancePtr->Config.S1GDiv0 << 32) | CLK_GEM1_REF), 0, 0, 0, 0, 0, 0);
#else
			ClkCntrl = Xil_In32((UINTPTR)CRL_GEM1_REF_CTRL);
			ClkCntrl &= ~CRL_GEM_DIV_VERSAL_MASK;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv0 << CRL_GEM_DIV_VERSAL_SHIFT;
			Xil_Out32((UINTPTR)CRL_GEM1_REF_CTRL, ClkCntrl);
#endif
		}
#endif
	}
}
/****************************************************************************/
/**
*
* This function sets up the clock divisors for 1000Mbps.
*
* @param	EmacPsInstancePtr is a pointer to the instance of the EmacPs
*			driver.
* @param	EmacPsIntrId is the Interrupt ID and is typically
*			XPAR_<EMACPS_instance>_INTR value from xparameters.h.
* @return	None.
*
* @note		None.
*
*****************************************************************************/
This function sets up the clock divisors for 1000Mbps.
This function sets up the clock divisors for 1000Mbps .
void XEmacPsClkSetup(XEmacPs *EmacPsInstancePtr, u16 EmacPsIntrId)
{
	u32 ClkCntrl;
	u32 BaseAddress = EmacPsInstancePtr->Config.BaseAddress;
	if (GemVersion == 2)
	{
	*(volatile unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
	if (BaseAddress == ZYNQ_EMACPS_0_BASEADDR) {
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
		ClkCntrl =
		*(volatile unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR);
		ClkCntrl &= EMACPS_SLCR_DIV_MASK;
		ClkCntrl |= (EmacPsInstancePtr->Config.S1GDiv1 << 20);
		ClkCntrl |= (EmacPsInstancePtr->Config.S1GDiv0 << 8);
		*(volatile unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) =
								ClkCntrl;
#endif
	} else if (BaseAddress == ZYNQ_EMACPS_1_BASEADDR) {
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1
		ClkCntrl =
		*(volatile unsigned int *)(SLCR_GEM1_CLK_CTRL_ADDR);
		ClkCntrl &= EMACPS_SLCR_DIV_MASK;
		ClkCntrl |= (EmacPsInstancePtr->Config.S1GDiv1 << 20);
		ClkCntrl |= (EmacPsInstancePtr->Config.S1GDiv0 << 8);
		*(volatile unsigned int *)(SLCR_GEM1_CLK_CTRL_ADDR) =
								ClkCntrl;
#endif
	}
	*(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
	#ifndef __MICROBLAZE__
	sleep(1);
	#else
	unsigned long count=0;
	while(count < 0xffff)
	{
		count++;
	}
	#endif
	}
	if ((GemVersion == GEMVERSION_ZYNQMP) && ((Platform & PLATFORM_MASK) == PLATFORM_SILICON)) {
#ifdef XPAR_PSU_CRL_APB_S_AXI_BASEADDR
		if (BaseAddress == ZYNQMP_EMACPS_0_BASEADDR) {
			ClkCntrl =
			*(volatile unsigned int *)(CRL_GEM0_REF_CTRL);
			ClkCntrl &= ~CRL_GEM_DIV_MASK;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv1 << CRL_GEM_DIV1_SHIFT;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv0 << CRL_GEM_DIV0_SHIFT;
			*(volatile unsigned int *)(CRL_GEM0_REF_CTRL) =
									ClkCntrl;
		}
		if (BaseAddress == ZYNQMP_EMACPS_1_BASEADDR) {
			ClkCntrl =
			*(volatile unsigned int *)(CRL_GEM1_REF_CTRL);
			ClkCntrl &= ~CRL_GEM_DIV_MASK;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv1 << CRL_GEM_DIV1_SHIFT;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv0 << CRL_GEM_DIV0_SHIFT;
			*(volatile unsigned int *)(CRL_GEM1_REF_CTRL) =
									ClkCntrl;
		}
		if (BaseAddress == ZYNQMP_EMACPS_2_BASEADDR) {
			ClkCntrl =
			*(volatile unsigned int *)(CRL_GEM2_REF_CTRL);
			ClkCntrl &= ~CRL_GEM_DIV_MASK;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv1 << CRL_GEM_DIV1_SHIFT;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv0 << CRL_GEM_DIV0_SHIFT;
			*(volatile unsigned int *)(CRL_GEM2_REF_CTRL) =
									ClkCntrl;
		}
		if (BaseAddress == ZYNQMP_EMACPS_3_BASEADDR) {
			ClkCntrl =
			*(volatile unsigned int *)(CRL_GEM3_REF_CTRL);
			ClkCntrl &= ~CRL_GEM_DIV_MASK;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv1 << CRL_GEM_DIV1_SHIFT;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv0 << CRL_GEM_DIV0_SHIFT;
			*(volatile unsigned int *)(CRL_GEM3_REF_CTRL) =
									ClkCntrl;
		}
#endif
	}
	if ((GemVersion == GEMVERSION_VERSAL) &&
		((Platform & PLATFORM_MASK_VERSAL) == PLATFORM_VERSALSIL)) {
#ifdef XPAR_PSV_CRL_0_S_AXI_BASEADDR
		if (BaseAddress == VERSAL_EMACPS_0_BASEADDR) {
#if EL1_NONSECURE
			Xil_Smc(PM_SET_DIVIDER_SMC_FID, (((u64)EmacPsInstancePtr->Config.S1GDiv0 << 32) | CLK_GEM0_REF), 0, 0, 0, 0, 0, 0);
#else
			ClkCntrl = Xil_In32((UINTPTR)CRL_GEM0_REF_CTRL);
			ClkCntrl &= ~CRL_GEM_DIV_VERSAL_MASK;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv0 << CRL_GEM_DIV_VERSAL_SHIFT;
			Xil_Out32((UINTPTR)CRL_GEM0_REF_CTRL, ClkCntrl);
#endif
		}
		if (BaseAddress == VERSAL_EMACPS_0_BASEADDR) {
#if EL1_NONSECURE
			Xil_Smc(PM_SET_DIVIDER_SMC_FID, (((u64)EmacPsInstancePtr->Config.S1GDiv0 << 32) | CLK_GEM1_REF), 0, 0, 0, 0, 0, 0);
#else
			ClkCntrl = Xil_In32((UINTPTR)CRL_GEM1_REF_CTRL);
			ClkCntrl &= ~CRL_GEM_DIV_VERSAL_MASK;
			ClkCntrl |= EmacPsInstancePtr->Config.S1GDiv0 << CRL_GEM_DIV_VERSAL_SHIFT;
			Xil_Out32((UINTPTR)CRL_GEM1_REF_CTRL, ClkCntrl);
#endif
		}
#endif
	}
}
void XEmacPsClkSetup ( XEmacPs * EmacPsInstancePtr , u16 EmacPsIntrId ) { u32 ClkCntrl ; u32 BaseAddress = EmacPsInstancePtr -> Config . BaseAddress ; if ( GemVersion == 2 ) { * ( volatile unsigned int * ) ( SLCR_UNLOCK_ADDR ) = SLCR_UNLOCK_KEY_VALUE ; if ( BaseAddress == ZYNQ_EMACPS_0_BASEADDR ) { #ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 ClkCntrl = * ( volatile unsigned int * ) ( SLCR_GEM0_CLK_CTRL_ADDR ) ; ClkCntrl &= EMACPS_SLCR_DIV_MASK ; ClkCntrl |= ( EmacPsInstancePtr -> Config . S1GDiv1 << 20 ) ; ClkCntrl |= ( EmacPsInstancePtr -> Config . S1GDiv0 << 8 ) ; * ( volatile unsigned int * ) ( SLCR_GEM0_CLK_CTRL_ADDR ) = ClkCntrl ; #endif } else if ( BaseAddress == ZYNQ_EMACPS_1_BASEADDR ) { #ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 ClkCntrl = * ( volatile unsigned int * ) ( SLCR_GEM1_CLK_CTRL_ADDR ) ; ClkCntrl &= EMACPS_SLCR_DIV_MASK ; ClkCntrl |= ( EmacPsInstancePtr -> Config . S1GDiv1 << 20 ) ; ClkCntrl |= ( EmacPsInstancePtr -> Config . S1GDiv0 << 8 ) ; * ( volatile unsigned int * ) ( SLCR_GEM1_CLK_CTRL_ADDR ) = ClkCntrl ; #endif } * ( unsigned int * ) ( SLCR_LOCK_ADDR ) = SLCR_LOCK_KEY_VALUE ; #ifndef __MICROBLAZE__ sleep ( 1 ) ; #else unsigned long count = 0 ; while ( count < 0xffff ) { count ++ ; } #endif } if ( ( GemVersion == GEMVERSION_ZYNQMP ) && ( ( Platform & PLATFORM_MASK ) == PLATFORM_SILICON ) ) { #ifdef XPAR_PSU_CRL_APB_S_AXI_BASEADDR if ( BaseAddress == ZYNQMP_EMACPS_0_BASEADDR ) { ClkCntrl = * ( volatile unsigned int * ) ( CRL_GEM0_REF_CTRL ) ; ClkCntrl &= ~ CRL_GEM_DIV_MASK ; ClkCntrl |= EmacPsInstancePtr -> Config . S1GDiv1 << CRL_GEM_DIV1_SHIFT ; ClkCntrl |= EmacPsInstancePtr -> Config . S1GDiv0 << CRL_GEM_DIV0_SHIFT ; * ( volatile unsigned int * ) ( CRL_GEM0_REF_CTRL ) = ClkCntrl ; } if ( BaseAddress == ZYNQMP_EMACPS_1_BASEADDR ) { ClkCntrl = * ( volatile unsigned int * ) ( CRL_GEM1_REF_CTRL ) ; ClkCntrl &= ~ CRL_GEM_DIV_MASK ; ClkCntrl |= EmacPsInstancePtr -> Config . S1GDiv1 << CRL_GEM_DIV1_SHIFT ; ClkCntrl |= EmacPsInstancePtr -> Config . S1GDiv0 << CRL_GEM_DIV0_SHIFT ; * ( volatile unsigned int * ) ( CRL_GEM1_REF_CTRL ) = ClkCntrl ; } if ( BaseAddress == ZYNQMP_EMACPS_2_BASEADDR ) { ClkCntrl = * ( volatile unsigned int * ) ( CRL_GEM2_REF_CTRL ) ; ClkCntrl &= ~ CRL_GEM_DIV_MASK ; ClkCntrl |= EmacPsInstancePtr -> Config . S1GDiv1 << CRL_GEM_DIV1_SHIFT ; ClkCntrl |= EmacPsInstancePtr -> Config . S1GDiv0 << CRL_GEM_DIV0_SHIFT ; * ( volatile unsigned int * ) ( CRL_GEM2_REF_CTRL ) = ClkCntrl ; } if ( BaseAddress == ZYNQMP_EMACPS_3_BASEADDR ) { ClkCntrl = * ( volatile unsigned int * ) ( CRL_GEM3_REF_CTRL ) ; ClkCntrl &= ~ CRL_GEM_DIV_MASK ; ClkCntrl |= EmacPsInstancePtr -> Config . S1GDiv1 << CRL_GEM_DIV1_SHIFT ; ClkCntrl |= EmacPsInstancePtr -> Config . S1GDiv0 << CRL_GEM_DIV0_SHIFT ; * ( volatile unsigned int * ) ( CRL_GEM3_REF_CTRL ) = ClkCntrl ; } #endif } if ( ( GemVersion == GEMVERSION_VERSAL ) && ( ( Platform & PLATFORM_MASK_VERSAL ) == PLATFORM_VERSALSIL ) ) { #ifdef XPAR_PSV_CRL_0_S_AXI_BASEADDR if ( BaseAddress == VERSAL_EMACPS_0_BASEADDR ) { #if EL1_NONSECURE Xil_Smc ( PM_SET_DIVIDER_SMC_FID , ( ( ( u64 ) EmacPsInstancePtr -> Config . S1GDiv0 << 32 ) | CLK_GEM0_REF ) , 0 , 0 , 0 , 0 , 0 , 0 ) ; #else ClkCntrl = Xil_In32 ( ( UINTPTR ) CRL_GEM0_REF_CTRL ) ; ClkCntrl &= ~ CRL_GEM_DIV_VERSAL_MASK ; ClkCntrl |= EmacPsInstancePtr -> Config . S1GDiv0 << CRL_GEM_DIV_VERSAL_SHIFT ; Xil_Out32 ( ( UINTPTR ) CRL_GEM0_REF_CTRL , ClkCntrl ) ; #endif } if ( BaseAddress == VERSAL_EMACPS_0_BASEADDR ) { #if EL1_NONSECURE Xil_Smc ( PM_SET_DIVIDER_SMC_FID , ( ( ( u64 ) EmacPsInstancePtr -> Config . S1GDiv0 << 32 ) | CLK_GEM1_REF ) , 0 , 0 , 0 , 0 , 0 , 0 ) ; #else ClkCntrl = Xil_In32 ( ( UINTPTR ) CRL_GEM1_REF_CTRL ) ; ClkCntrl &= ~ CRL_GEM_DIV_VERSAL_MASK ; ClkCntrl |= EmacPsInstancePtr -> Config . S1GDiv0 << CRL_GEM_DIV_VERSAL_SHIFT ; Xil_Out32 ( ( UINTPTR ) CRL_GEM1_REF_CTRL , ClkCntrl ) ; #endif } #endif } }
This function sets up the clock divisors for 1000Mbps.
This function sets up the clock divisors for 1000Mbps .
/*************************************/ /* Setup device for first-time usage */ /*************************************/ /* SLCR unlock */ /* GEM0 1G clock configuration*/ /* GEM1 1G clock configuration*/ /* SLCR lock */ /* GEM0 1G clock configuration*/ /* GEM1 1G clock configuration*/ /* GEM2 1G clock configuration*/ /* GEM3 1G clock configuration*/ /* GEM0 1G clock configuration*/ /* GEM1 1G clock configuration*/