XilinxProcessorIPLib/drivers/v_hdmitxss1/examples/xhdmi_example/idt_8t49n24x.c
int IDT_8T49N24x_SetClock(void *IicPtr, u8 I2CSlaveAddress, int FIn,
							int FOut, u8 FreeRun)
{
	int Result;

	if ((FIn < IDT_8T49N24X_FIN_MIN) &&
	   (FIn > IDT_8T49N24X_FIN_MAX)) {
		return XST_FAILURE;
	}
	
	if ((FOut < IDT_8T49N24X_FOUT_MIN) &&
		(FOut > IDT_8T49N24X_FOUT_MAX)) {
		return XST_FAILURE;
	}
	
	IDT_8T49N24x_Settings RegSettings;

	/* Calculate settings */
	IDT_8T49N24x_CalculateSettings(FIn, FOut, &RegSettings);

	/* Disable DPLL and APLL calibration */
	Result = IDT_8T49N24x_Enable(IicPtr, I2CSlaveAddress, FALSE);

	/* Mode */
	if (FreeRun == TRUE) {
		/* Disable reference clock input 0 */
		Result = IDT_8T49N24x_ReferenceInput(IicPtr, I2CSlaveAddress,
							0, FALSE);

		/* Disable reference clock input 1 */
		Result = IDT_8T49N24x_ReferenceInput(IicPtr, I2CSlaveAddress,
							1, FALSE);

		/* Set synthesizer mode */
		Result = IDT_8T49N24x_Mode(IicPtr, I2CSlaveAddress, TRUE);
	}

	else {
		/* Enable reference clock input 0 */
		Result = IDT_8T49N24x_ReferenceInput(IicPtr, I2CSlaveAddress,
							0, TRUE);

		/* Disable reference clock input 1 */
		Result = IDT_8T49N24x_ReferenceInput(IicPtr, I2CSlaveAddress,
							1, FALSE);

		/* Set jitter attentuator mode */
		Result = IDT_8T49N24x_Mode(IicPtr, I2CSlaveAddress, FALSE);
	}

	/* Pre-divider Input 0 */
	Result = IDT_8T49N24x_PreDivider(IicPtr, I2CSlaveAddress,
							RegSettings.PRE_x, 0);

	/* Pre-divider Input 1 */
	Result = IDT_8T49N24x_PreDivider(IicPtr, I2CSlaveAddress,
							RegSettings.PRE_x, 1);

	/* M1 feedback Input 0 */
	Result = IDT_8T49N24x_M1Feedback(IicPtr, I2CSlaveAddress,
							RegSettings.M1_x, 0);

	/* M1 feedback Input 1 */
	Result = IDT_8T49N24x_M1Feedback(IicPtr, I2CSlaveAddress,
							RegSettings.M1_x, 1);

	/* DSM integer */
	Result = IDT_8T49N24x_DSMInteger(IicPtr, I2CSlaveAddress,
							RegSettings.DSM_INT);

	/* DSM fractional */
	Result = IDT_8T49N24x_DSMFractional(IicPtr, I2CSlaveAddress,
							RegSettings.DSM_FRAC);

	/* Output divider integer output 2 */
	Result = IDT_8T49N24x_OutputDividerInteger(IicPtr, I2CSlaveAddress,
							RegSettings.N_Qx, 2);

	/* Output divider integer output 3 */
	Result = IDT_8T49N24x_OutputDividerInteger(IicPtr, I2CSlaveAddress,
							RegSettings.N_Qx, 3);

	/* Output divider fractional output 2 */
	Result = IDT_8T49N24x_OutputDividerFractional(IicPtr,
							I2CSlaveAddress, RegSettings.NFRAC_Qx, 2);

	/* Output divider fractional output 3 */
	Result = IDT_8T49N24x_OutputDividerFractional(IicPtr,
							I2CSlaveAddress, RegSettings.NFRAC_Qx, 3);

	/* Input monitor control 0 */
	Result = IDT_8T49N24x_InputMonitorControl(IicPtr, I2CSlaveAddress,
							RegSettings.LOS_x, 0);

	/* Input monitor control 1 */
	Result = IDT_8T49N24x_InputMonitorControl(IicPtr, I2CSlaveAddress,
							RegSettings.LOS_x, 1);

	/* Enable DPLL and APLL calibration */
	Result = IDT_8T49N24x_Enable(IicPtr, I2CSlaveAddress, TRUE);

	return Result;
}
/*****************************************************************************/
/**
*
* This function calculates and sets the IDT 8TN49N24x device with the 
* given clock configuration.
*
* @param I2CBaseAddress is the baseaddress of the I2C core.
* @param I2CSlaveAddress is the 7-bit I2C slave address.
* @param FIn specifies the input frequency.
* @param FOut specifies the output frequency.
* @param FreeRun specifies if the operation mode is locked/synthesizer mode.
*    - TRUE Synthesizer mode (Fout only)
*    - FALSE Locked mode (Fout locked to Fin)
*
* @return
*    - XST_SUCCESS Initialization was successful.
*    - XST_FAILURE I2C write error or incorrect parameters detected.
*
* @note 
*
******************************************************************************/
This function calculates and sets the IDT 8TN49N24x device with the
given clock configuration.
This function calculates and sets the IDT 8TN49N24x device with the given clock configuration .
int IDT_8T49N24x_SetClock(void *IicPtr, u8 I2CSlaveAddress, int FIn,
							int FOut, u8 FreeRun)
{
	int Result;
	if ((FIn < IDT_8T49N24X_FIN_MIN) &&
	   (FIn > IDT_8T49N24X_FIN_MAX)) {
		return XST_FAILURE;
	}
	if ((FOut < IDT_8T49N24X_FOUT_MIN) &&
		(FOut > IDT_8T49N24X_FOUT_MAX)) {
		return XST_FAILURE;
	}
	IDT_8T49N24x_Settings RegSettings;
	IDT_8T49N24x_CalculateSettings(FIn, FOut, &RegSettings);
	Result = IDT_8T49N24x_Enable(IicPtr, I2CSlaveAddress, FALSE);
	if (FreeRun == TRUE) {
		Result = IDT_8T49N24x_ReferenceInput(IicPtr, I2CSlaveAddress,
							0, FALSE);
		Result = IDT_8T49N24x_ReferenceInput(IicPtr, I2CSlaveAddress,
							1, FALSE);
		Result = IDT_8T49N24x_Mode(IicPtr, I2CSlaveAddress, TRUE);
	}
	else {
		Result = IDT_8T49N24x_ReferenceInput(IicPtr, I2CSlaveAddress,
							0, TRUE);
		Result = IDT_8T49N24x_ReferenceInput(IicPtr, I2CSlaveAddress,
							1, FALSE);
		Result = IDT_8T49N24x_Mode(IicPtr, I2CSlaveAddress, FALSE);
	}
	Result = IDT_8T49N24x_PreDivider(IicPtr, I2CSlaveAddress,
							RegSettings.PRE_x, 0);
	Result = IDT_8T49N24x_PreDivider(IicPtr, I2CSlaveAddress,
							RegSettings.PRE_x, 1);
	Result = IDT_8T49N24x_M1Feedback(IicPtr, I2CSlaveAddress,
							RegSettings.M1_x, 0);
	Result = IDT_8T49N24x_M1Feedback(IicPtr, I2CSlaveAddress,
							RegSettings.M1_x, 1);
	Result = IDT_8T49N24x_DSMInteger(IicPtr, I2CSlaveAddress,
							RegSettings.DSM_INT);
	Result = IDT_8T49N24x_DSMFractional(IicPtr, I2CSlaveAddress,
							RegSettings.DSM_FRAC);
	Result = IDT_8T49N24x_OutputDividerInteger(IicPtr, I2CSlaveAddress,
							RegSettings.N_Qx, 2);
	Result = IDT_8T49N24x_OutputDividerInteger(IicPtr, I2CSlaveAddress,
							RegSettings.N_Qx, 3);
	Result = IDT_8T49N24x_OutputDividerFractional(IicPtr,
							I2CSlaveAddress, RegSettings.NFRAC_Qx, 2);
	Result = IDT_8T49N24x_OutputDividerFractional(IicPtr,
							I2CSlaveAddress, RegSettings.NFRAC_Qx, 3);
	Result = IDT_8T49N24x_InputMonitorControl(IicPtr, I2CSlaveAddress,
							RegSettings.LOS_x, 0);
	Result = IDT_8T49N24x_InputMonitorControl(IicPtr, I2CSlaveAddress,
							RegSettings.LOS_x, 1);
	Result = IDT_8T49N24x_Enable(IicPtr, I2CSlaveAddress, TRUE);
	return Result;
}
int IDT_8T49N24x_SetClock ( void * IicPtr , u8 I2CSlaveAddress , int FIn , int FOut , u8 FreeRun ) { int Result ; if ( ( FIn < IDT_8T49N24X_FIN_MIN ) && ( FIn > IDT_8T49N24X_FIN_MAX ) ) { return XST_FAILURE ; } if ( ( FOut < IDT_8T49N24X_FOUT_MIN ) && ( FOut > IDT_8T49N24X_FOUT_MAX ) ) { return XST_FAILURE ; } IDT_8T49N24x_Settings RegSettings ; IDT_8T49N24x_CalculateSettings ( FIn , FOut , & RegSettings ) ; Result = IDT_8T49N24x_Enable ( IicPtr , I2CSlaveAddress , FALSE ) ; if ( FreeRun == TRUE ) { Result = IDT_8T49N24x_ReferenceInput ( IicPtr , I2CSlaveAddress , 0 , FALSE ) ; Result = IDT_8T49N24x_ReferenceInput ( IicPtr , I2CSlaveAddress , 1 , FALSE ) ; Result = IDT_8T49N24x_Mode ( IicPtr , I2CSlaveAddress , TRUE ) ; } else { Result = IDT_8T49N24x_ReferenceInput ( IicPtr , I2CSlaveAddress , 0 , TRUE ) ; Result = IDT_8T49N24x_ReferenceInput ( IicPtr , I2CSlaveAddress , 1 , FALSE ) ; Result = IDT_8T49N24x_Mode ( IicPtr , I2CSlaveAddress , FALSE ) ; } Result = IDT_8T49N24x_PreDivider ( IicPtr , I2CSlaveAddress , RegSettings . PRE_x , 0 ) ; Result = IDT_8T49N24x_PreDivider ( IicPtr , I2CSlaveAddress , RegSettings . PRE_x , 1 ) ; Result = IDT_8T49N24x_M1Feedback ( IicPtr , I2CSlaveAddress , RegSettings . M1_x , 0 ) ; Result = IDT_8T49N24x_M1Feedback ( IicPtr , I2CSlaveAddress , RegSettings . M1_x , 1 ) ; Result = IDT_8T49N24x_DSMInteger ( IicPtr , I2CSlaveAddress , RegSettings . DSM_INT ) ; Result = IDT_8T49N24x_DSMFractional ( IicPtr , I2CSlaveAddress , RegSettings . DSM_FRAC ) ; Result = IDT_8T49N24x_OutputDividerInteger ( IicPtr , I2CSlaveAddress , RegSettings . N_Qx , 2 ) ; Result = IDT_8T49N24x_OutputDividerInteger ( IicPtr , I2CSlaveAddress , RegSettings . N_Qx , 3 ) ; Result = IDT_8T49N24x_OutputDividerFractional ( IicPtr , I2CSlaveAddress , RegSettings . NFRAC_Qx , 2 ) ; Result = IDT_8T49N24x_OutputDividerFractional ( IicPtr , I2CSlaveAddress , RegSettings . NFRAC_Qx , 3 ) ; Result = IDT_8T49N24x_InputMonitorControl ( IicPtr , I2CSlaveAddress , RegSettings . LOS_x , 0 ) ; Result = IDT_8T49N24x_InputMonitorControl ( IicPtr , I2CSlaveAddress , RegSettings . LOS_x , 1 ) ; Result = IDT_8T49N24x_Enable ( IicPtr , I2CSlaveAddress , TRUE ) ; return Result ; }
This function calculates and sets the IDT 8TN49N24x device with the
given clock configuration.
This function calculates and sets the IDT 8TN49N24x device with the given clock configuration .
/* Calculate settings */ /* Disable DPLL and APLL calibration */ /* Mode */ /* Disable reference clock input 0 */ /* Disable reference clock input 1 */ /* Set synthesizer mode */ /* Enable reference clock input 0 */ /* Disable reference clock input 1 */ /* Set jitter attentuator mode */ /* Pre-divider Input 0 */ /* Pre-divider Input 1 */ /* M1 feedback Input 0 */ /* M1 feedback Input 1 */ /* DSM integer */ /* DSM fractional */ /* Output divider integer output 2 */ /* Output divider integer output 3 */ /* Output divider fractional output 2 */ /* Output divider fractional output 3 */ /* Input monitor control 0 */ /* Input monitor control 1 */ /* Enable DPLL and APLL calibration */