src/dpdk/drivers/net/igc/base/igc_base.c
s32 igc_init_hw_base(struct igc_hw *hw)
{
	struct igc_mac_info *mac = &hw->mac;
	s32 ret_val;
	u16 i, rar_count = mac->rar_entry_count;

	DEBUGFUNC("igc_init_hw_base");

	/* Setup the receive address */
	igc_init_rx_addrs_generic(hw, rar_count);

	/* Zero out the Multicast HASH table */
	DEBUGOUT("Zeroing the MTA\n");
	for (i = 0; i < mac->mta_reg_count; i++)
		IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, 0);

	/* Zero out the Unicast HASH table */
	DEBUGOUT("Zeroing the UTA\n");
	for (i = 0; i < mac->uta_reg_count; i++)
		IGC_WRITE_REG_ARRAY(hw, IGC_UTA, i, 0);

	/* Setup link and flow control */
	ret_val = mac->ops.setup_link(hw);
	/*
	 * Clear all of the statistics registers (clear on read).  It is
	 * important that we do this after we have tried to establish link
	 * because the symbol error count will increment wildly if there
	 * is no link.
	 */
	igc_clear_hw_cntrs_base_generic(hw);

	return ret_val;
}
/**
 *  igc_init_hw_base - Initialize hardware
 *  @hw: pointer to the HW structure
 *
 *  This inits the hardware readying it for operation.
 **/
Initialize hardware
@hw: pointer to the HW structure

This inits the hardware readying it for operation.
Initialize hardware @hw : pointer to the HW structure This inits the hardware readying it for operation .
s32 igc_init_hw_base(struct igc_hw *hw)
{
	struct igc_mac_info *mac = &hw->mac;
	s32 ret_val;
	u16 i, rar_count = mac->rar_entry_count;
	DEBUGFUNC("igc_init_hw_base");
	igc_init_rx_addrs_generic(hw, rar_count);
	DEBUGOUT("Zeroing the MTA\n");
	for (i = 0; i < mac->mta_reg_count; i++)
		IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, 0);
	DEBUGOUT("Zeroing the UTA\n");
	for (i = 0; i < mac->uta_reg_count; i++)
		IGC_WRITE_REG_ARRAY(hw, IGC_UTA, i, 0);
	ret_val = mac->ops.setup_link(hw);
	igc_clear_hw_cntrs_base_generic(hw);
	return ret_val;
}
s32 igc_init_hw_base ( struct igc_hw * hw ) { struct igc_mac_info * mac = & hw -> mac ; s32 ret_val ; u16 i , rar_count = mac -> rar_entry_count ; DEBUGFUNC ( " " ) ; igc_init_rx_addrs_generic ( hw , rar_count ) ; DEBUGOUT ( " \n " ) ; for ( i = 0 ; i < mac -> mta_reg_count ; i ++ ) IGC_WRITE_REG_ARRAY ( hw , IGC_MTA , i , 0 ) ; DEBUGOUT ( " \n " ) ; for ( i = 0 ; i < mac -> uta_reg_count ; i ++ ) IGC_WRITE_REG_ARRAY ( hw , IGC_UTA , i , 0 ) ; ret_val = mac -> ops . setup_link ( hw ) ; igc_clear_hw_cntrs_base_generic ( hw ) ; return ret_val ; }
igc_init_hw_base - Initialize hardware
  @hw: pointer to the HW structure
igc_init_hw_base - Initialize hardware @hw : pointer to the HW structure
/* Setup the receive address */ /* Zero out the Multicast HASH table */ /* Zero out the Unicast HASH table */ /* Setup link and flow control */ /*
	 * Clear all of the statistics registers (clear on read).  It is
	 * important that we do this after we have tried to establish link
	 * because the symbol error count will increment wildly if there
	 * is no link.
	 */