XilinxProcessorIPLib/drivers/sysmon/src/xsysmon.c
void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u32 AlmEnableMask)
{
	u32 RegValue;

	/*
	 * Assert the arguments.
	 */
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertVoid(AlmEnableMask <= XSM_CFR_ALM_ALL_MASK);

	RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
				   XSM_CFR1_OFFSET);
	RegValue &= (u32)~XSM_CFR1_ALM_ALL_MASK;
	RegValue |= (~AlmEnableMask & XSM_CFR1_ALM_ALL_MASK);

	/*
	 * Enable/disables the alarm enables for the specified alarm bits in the
	 * Configuration Register 1.
	 */
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR1_OFFSET,
			 RegValue);

#if XPAR_SYSMON_0_IP_TYPE == SYSTEM_MANAGEMENT
	/*
	 * Enable/disables the alarm enables for the specified alarm bits in the
	 * Configuration Register 3.
	 */
	RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
					   XSM_CFR3_OFFSET);
	RegValue &= (u32)~XSM_CFR3_ALM_ALL_MASK;
	RegValue |= (~(AlmEnableMask >> 16) & XSM_CFR3_ALM_ALL_MASK);

	XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR3_OFFSET,
			 RegValue);
#endif
}
/****************************************************************************/
/**
*
* This function enables the alarm outputs for the specified alarms in the
* Configuration Registers 1 and 3:
*
*		- OT for Over Temperature (XSM_CFR_OT_MASK)
*		- ALM0 for On board Temperature (XSM_CFR_ALM_TEMP_MASK)
*		- ALM1 for VCCINT (XSM_CFR_ALM_VCCINT_MASK)
*		- ALM2 for VCCAUX (XSM_CFR_ALM_VCCAUX_MASK)
* 		- ALM3 for VBRAM (XSM_CFR_ALM_VBRAM_MASK)for 7 Series and Zynq
* 		- ALM4 for VCCPINT (XSM_CFR_ALM_VCCPINT_MASK) for Zynq
*		- ALM5 for VCCPAUX (XSM_CFR_ALM_VCCPAUX_MASK) for Zynq
* 		- ALM6 for VCCPDRO (XSM_CFR_ALM_VCCPDRO_MASK) for Zynq
* 		- ALM8 for VUSER0 (XSM_CFR_ALM_VUSR0_MASK) for Ultrascale
* 		- ALM9 for VUSER1 (XSM_CFR_ALM_VUSR1_MASK) for Ultrascale
* 		- ALM10 for VUSER2 (XSM_CFR_ALM_VUSR2_MASK) for Ultrascale
* 		- ALM11 for VUSER3 (XSM_CFR_ALM_VUSR3_MASK) for Ultrascale
*
* @param	InstancePtr is a pointer to the XSysMon instance.
* @param	AlmEnableMask is the bit-mask of the alarm outputs to be enabled
*		in the Configuration Register 1.
*		Bit positions of 1 will be enabled. Bit positions of 0 will be
*		disabled. This mask is formed by OR'ing XSM_CFR_ALM_*_MASK,
*		XSM_CFR_ALM_*_MASK and XSM_CFR_OT_MASK masks defined in
*		xsysmon_hw.h.
*
* @return	None.
*
* @note		The implementation of the alarm enables in the Configuration
*		register 1 is such that the alarms for bit positions of 1 will
*		be disabled and alarms for bit positions of 0 will be enabled.
*		The alarm outputs specified by the AlmEnableMask are negated
*		before writing to the Configuration Register 1.
*
*****************************************************************************/
This function enables the alarm outputs for the specified alarms in the
Configuration Registers 1 and 3.


This function enables the alarm outputs for the specified alarms in the Configuration Registers 1 and 3 .
void XSysMon_SetAlarmEnables(XSysMon *InstancePtr, u32 AlmEnableMask)
{
	u32 RegValue;
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertVoid(AlmEnableMask <= XSM_CFR_ALM_ALL_MASK);
	RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
				   XSM_CFR1_OFFSET);
	RegValue &= (u32)~XSM_CFR1_ALM_ALL_MASK;
	RegValue |= (~AlmEnableMask & XSM_CFR1_ALM_ALL_MASK);
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR1_OFFSET,
			 RegValue);
#if XPAR_SYSMON_0_IP_TYPE == SYSTEM_MANAGEMENT
	RegValue = XSysMon_ReadReg(InstancePtr->Config.BaseAddress,
					   XSM_CFR3_OFFSET);
	RegValue &= (u32)~XSM_CFR3_ALM_ALL_MASK;
	RegValue |= (~(AlmEnableMask >> 16) & XSM_CFR3_ALM_ALL_MASK);
	XSysMon_WriteReg(InstancePtr->Config.BaseAddress, XSM_CFR3_OFFSET,
			 RegValue);
#endif
}
void XSysMon_SetAlarmEnables ( XSysMon * InstancePtr , u32 AlmEnableMask ) { u32 RegValue ; Xil_AssertVoid ( InstancePtr != NULL ) ; Xil_AssertVoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Xil_AssertVoid ( AlmEnableMask <= XSM_CFR_ALM_ALL_MASK ) ; RegValue = XSysMon_ReadReg ( InstancePtr -> Config . BaseAddress , XSM_CFR1_OFFSET ) ; RegValue &= ( u32 ) ~ XSM_CFR1_ALM_ALL_MASK ; RegValue |= ( ~ AlmEnableMask & XSM_CFR1_ALM_ALL_MASK ) ; XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_CFR1_OFFSET , RegValue ) ; #if XPAR_SYSMON_0_IP_TYPE == SYSTEM_MANAGEMENT RegValue = XSysMon_ReadReg ( InstancePtr -> Config . BaseAddress , XSM_CFR3_OFFSET ) ; RegValue &= ( u32 ) ~ XSM_CFR3_ALM_ALL_MASK ; RegValue |= ( ~ ( AlmEnableMask >> 16 ) & XSM_CFR3_ALM_ALL_MASK ) ; XSysMon_WriteReg ( InstancePtr -> Config . BaseAddress , XSM_CFR3_OFFSET , RegValue ) ; #endif }
This function enables the alarm outputs for the specified alarms in the
Configuration Registers 1 and 3:
This function enables the alarm outputs for the specified alarms in the Configuration Registers 1 and 3 :
/*
	 * Assert the arguments.
	 */ /*
	 * Enable/disables the alarm enables for the specified alarm bits in the
	 * Configuration Register 1.
	 */ /*
	 * Enable/disables the alarm enables for the specified alarm bits in the
	 * Configuration Register 3.
	 */