src/dpdk/drivers/net/ixgbe/base/ixgbe_dcb_82599.c
s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
					   u16 *max, u8 *bwg_id, u8 *tsa,
					   u8 *map)
{
	u32 reg;
	u8 i;

	/*
	 * Disable the arbiter before changing parameters
	 * (always enable recycle mode; SP; arb delay)
	 */
	reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
	      (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
	      IXGBE_RTTPCS_ARBDIS;
	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);

	/*
	 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
	 * bits sets for the UPs that needs to be mappped to that TC.
	 * e.g if priorities 6 and 7 are to be mapped to a TC then the
	 * up_to_tc_bitmap value for that TC will be 11000000 in binary.
	 */
	reg = 0;
	for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
		reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));

	IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);

	/* Configure traffic class credits and priority */
	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
		reg = refill[i];
		reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
		reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;

		if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
			reg |= IXGBE_RTTPT2C_GSP;

		if (tsa[i] == ixgbe_dcb_tsa_strict)
			reg |= IXGBE_RTTPT2C_LSP;

		IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
	}

	/*
	 * Configure Tx packet plane (recycle mode; SP; arb delay) and
	 * enable arbiter
	 */
	reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
	      (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);

	return IXGBE_SUCCESS;
}
/**
 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
 * @hw: pointer to hardware structure
 * @refill: refill credits index by traffic class
 * @max: max credits index by traffic class
 * @bwg_id: bandwidth grouping indexed by traffic class
 * @tsa: transmission selection algorithm indexed by traffic class
 * @map: priority to tc assignments indexed by priority
 *
 * Configure Tx Packet Arbiter and credits for each traffic class.
 */


Configure Tx Packet Arbiter and credits for each traffic class.
Configure Tx Packet Arbiter and credits for each traffic class .
s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
					   u16 *max, u8 *bwg_id, u8 *tsa,
					   u8 *map)
{
	u32 reg;
	u8 i;
	reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
	      (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
	      IXGBE_RTTPCS_ARBDIS;
	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
	reg = 0;
	for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
		reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
	IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
		reg = refill[i];
		reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
		reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
		if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
			reg |= IXGBE_RTTPT2C_GSP;
		if (tsa[i] == ixgbe_dcb_tsa_strict)
			reg |= IXGBE_RTTPT2C_LSP;
		IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
	}
	reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
	      (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
	return IXGBE_SUCCESS;
}
s32 ixgbe_dcb_config_tx_data_arbiter_82599 ( struct ixgbe_hw * hw , u16 * refill , u16 * max , u8 * bwg_id , u8 * tsa , u8 * map ) { u32 reg ; u8 i ; reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | ( IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT ) | IXGBE_RTTPCS_ARBDIS ; IXGBE_WRITE_REG ( hw , IXGBE_RTTPCS , reg ) ; reg = 0 ; for ( i = 0 ; i < IXGBE_DCB_MAX_USER_PRIORITY ; i ++ ) reg |= ( map [ i ] << ( i * IXGBE_RTTUP2TC_UP_SHIFT ) ) ; IXGBE_WRITE_REG ( hw , IXGBE_RTTUP2TC , reg ) ; for ( i = 0 ; i < IXGBE_DCB_MAX_TRAFFIC_CLASS ; i ++ ) { reg = refill [ i ] ; reg |= ( u32 ) ( max [ i ] ) << IXGBE_RTTPT2C_MCL_SHIFT ; reg |= ( u32 ) ( bwg_id [ i ] ) << IXGBE_RTTPT2C_BWG_SHIFT ; if ( tsa [ i ] == ixgbe_dcb_tsa_group_strict_cee ) reg |= IXGBE_RTTPT2C_GSP ; if ( tsa [ i ] == ixgbe_dcb_tsa_strict ) reg |= IXGBE_RTTPT2C_LSP ; IXGBE_WRITE_REG ( hw , IXGBE_RTTPT2C ( i ) , reg ) ; } reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | ( IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT ) ; IXGBE_WRITE_REG ( hw , IXGBE_RTTPCS , reg ) ; return IXGBE_SUCCESS ; }
ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
 @hw: pointer to hardware structure
 @refill: refill credits index by traffic class
 @max: max credits index by traffic class
 @bwg_id: bandwidth grouping indexed by traffic class
 @tsa: transmission selection algorithm indexed by traffic class
 @map: priority to tc assignments indexed by priority
ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter @hw : pointer to hardware structure @refill : refill credits index by traffic class @max : max credits index by traffic class @bwg_id : bandwidth grouping indexed by traffic class @tsa : transmission selection algorithm indexed by traffic class @map : priority to tc assignments indexed by priority
/*
	 * Disable the arbiter before changing parameters
	 * (always enable recycle mode; SP; arb delay)
	 */ /*
	 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
	 * bits sets for the UPs that needs to be mappped to that TC.
	 * e.g if priorities 6 and 7 are to be mapped to a TC then the
	 * up_to_tc_bitmap value for that TC will be 11000000 in binary.
	 */ /* Configure traffic class credits and priority */ /*
	 * Configure Tx packet plane (recycle mode; SP; arb delay) and
	 * enable arbiter
	 */