XilinxProcessorIPLib/drivers/nandps/src/xnandps.c
static void XNandPs_EccSetMemCmd1(XNandPs *InstancePtr, u32 EccCmd)
{
	/*
	 * Set the ECC mem command1 register
	 */
	XNandPs_WriteReg(InstancePtr->Config.SmcBase +
		(XNANDPS_ECC_MEMCMD1_OFFSET(XNANDPS_IF1_ECC_OFFSET)),
		EccCmd);
}
/*****************************************************************************/
/**
*
* This function writes ECC MEM CMD1 register with EccCmd value.
*
* @param	InstancePtr is a pointer to the XNandPs instance.
* @param	EccCmd is register value to write.
*
* @return	None
*
* @note		None
*
*****************************************************************************/
This function writes ECC MEM CMD1 register with EccCmd value.
This function writes ECC MEM CMD1 register with EccCmd value .
static void XNandPs_EccSetMemCmd1(XNandPs *InstancePtr, u32 EccCmd)
{
	XNandPs_WriteReg(InstancePtr->Config.SmcBase +
		(XNANDPS_ECC_MEMCMD1_OFFSET(XNANDPS_IF1_ECC_OFFSET)),
		EccCmd);
}
static void XNandPs_EccSetMemCmd1 ( XNandPs * InstancePtr , u32 EccCmd ) { XNandPs_WriteReg ( InstancePtr -> Config . SmcBase + ( XNANDPS_ECC_MEMCMD1_OFFSET ( XNANDPS_IF1_ECC_OFFSET ) ) , EccCmd ) ; }
This function writes ECC MEM CMD1 register with EccCmd value.
This function writes ECC MEM CMD1 register with EccCmd value .
/*
	 * Set the ECC mem command1 register
	 */