test_pool/pcie/operating_system/test_os_p009.c
static
uint32_t
check_pcie_cfg_space(uint32_t bdf)
{
    uint32_t reg_value;
    uint32_t next_cap;
    uint32_t err = 0;
    uint32_t cid;

    // Search through regular PCIe cfg space first (start at first implemented cap)
    val_pcie_read_cfg(bdf, TYPE01_CPR, &reg_value);
    // DWORD aligned: next_cap[1:0] are hardwired to '0'
    next_cap = VAL_EXTRACT_BITS(reg_value, 2, 7) << 2;

    while (next_cap) {

        val_pcie_read_cfg(bdf, next_cap, &reg_value);
        next_cap = VAL_EXTRACT_BITS(reg_value, 7, 15);
        cid = VAL_EXTRACT_BITS(reg_value, 0, 7);

        // Check PCIe Cap IDs are in range
        if (cid > PCIE_CAP_ID_END) {
            val_print(ACS_PRINT_ERR,
                "\n       Invalid Cap ID: 0x%x found in regular cfg space", cid);
            err = 1;
        }
    }

    // Search through extended PCIe cfg space next
    next_cap = PCIE_ECAP_START;

    while (next_cap) {

        val_pcie_read_cfg(bdf, next_cap, &reg_value);
        next_cap = VAL_EXTRACT_BITS(reg_value, 20, 31);
        cid = VAL_EXTRACT_BITS(reg_value, 0, 15);

        // Check PCIe Ext Cap IDs are in range
        if (cid > PCIE_ECAP_ID_END) {
            val_print(ACS_PRINT_ERR,
                "\n       Invalid Cap ID: 0x%x found in extended cfg space", cid);
            err = 1;
        }
    }

    return err;
}
/*
 Check if vendor specific data are presented as non-PCIe compliant capabilities
 in either the regular or extended PCIe spaces
 returns: 0 - No violations present    1 - One or more violations present
 */
Check if vendor specific data are presented as non-PCIe compliant capabilities
in either the regular or extended PCIe spaces
returns: 0 - No violations present    1 - One or more violations present
Check if vendor specific data are presented as non - PCIe compliant capabilities in either the regular or extended PCIe spaces returns : 0 - No violations present 1 - One or more violations present
static
uint32_t
check_pcie_cfg_space(uint32_t bdf)
{
    uint32_t reg_value;
    uint32_t next_cap;
    uint32_t err = 0;
    uint32_t cid;
    val_pcie_read_cfg(bdf, TYPE01_CPR, &reg_value);
    next_cap = VAL_EXTRACT_BITS(reg_value, 2, 7) << 2;
    while (next_cap) {
        val_pcie_read_cfg(bdf, next_cap, &reg_value);
        next_cap = VAL_EXTRACT_BITS(reg_value, 7, 15);
        cid = VAL_EXTRACT_BITS(reg_value, 0, 7);
        if (cid > PCIE_CAP_ID_END) {
            val_print(ACS_PRINT_ERR,
                "\n       Invalid Cap ID: 0x%x found in regular cfg space", cid);
            err = 1;
        }
    }
    next_cap = PCIE_ECAP_START;
    while (next_cap) {
        val_pcie_read_cfg(bdf, next_cap, &reg_value);
        next_cap = VAL_EXTRACT_BITS(reg_value, 20, 31);
        cid = VAL_EXTRACT_BITS(reg_value, 0, 15);
        if (cid > PCIE_ECAP_ID_END) {
            val_print(ACS_PRINT_ERR,
                "\n       Invalid Cap ID: 0x%x found in extended cfg space", cid);
            err = 1;
        }
    }
    return err;
}
static uint32_t check_pcie_cfg_space ( uint32_t bdf ) { uint32_t reg_value ; uint32_t next_cap ; uint32_t err = 0 ; uint32_t cid ; val_pcie_read_cfg ( bdf , TYPE01_CPR , & reg_value ) ; next_cap = VAL_EXTRACT_BITS ( reg_value , 2 , 7 ) << 2 ; while ( next_cap ) { val_pcie_read_cfg ( bdf , next_cap , & reg_value ) ; next_cap = VAL_EXTRACT_BITS ( reg_value , 7 , 15 ) ; cid = VAL_EXTRACT_BITS ( reg_value , 0 , 7 ) ; if ( cid > PCIE_CAP_ID_END ) { val_print ( ACS_PRINT_ERR , " \n " , cid ) ; err = 1 ; } } next_cap = PCIE_ECAP_START ; while ( next_cap ) { val_pcie_read_cfg ( bdf , next_cap , & reg_value ) ; next_cap = VAL_EXTRACT_BITS ( reg_value , 20 , 31 ) ; cid = VAL_EXTRACT_BITS ( reg_value , 0 , 15 ) ; if ( cid > PCIE_ECAP_ID_END ) { val_print ( ACS_PRINT_ERR , " \n " , cid ) ; err = 1 ; } } return err ; }
Check if vendor specific data are presented as non-PCIe compliant capabilities
in either the regular or extended PCIe spaces
returns: 0 - No violations present    1 - One or more violations present
Check if vendor specific data are presented as non - PCIe compliant capabilities in either the regular or extended PCIe spaces returns : 0 - No violations present 1 - One or more violations present
// Search through regular PCIe cfg space first (start at first implemented cap) // DWORD aligned: next_cap[1:0] are hardwired to '0' // Check PCIe Cap IDs are in range // Search through extended PCIe cfg space next // Check PCIe Ext Cap IDs are in range