src/dpdk/drivers/net/ixgbe/base/ixgbe_x540.c
s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
{
	s32 status;
	u32 ctrl, i;
	u32 swfw_mask = hw->phy.phy_semaphore_mask;

	DEBUGFUNC("ixgbe_reset_hw_X540");

	/* Call adapter stop to disable tx/rx and clear interrupts */
	status = hw->mac.ops.stop_adapter(hw);
	if (status != IXGBE_SUCCESS)
		goto reset_hw_out;

	/* flush pending Tx transactions */
	ixgbe_clear_tx_pending(hw);

mac_reset_top:
	status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
	if (status != IXGBE_SUCCESS) {
		ERROR_REPORT2(IXGBE_ERROR_CAUTION,
			"semaphore failed with %d", status);
		return IXGBE_ERR_SWFW_SYNC;
	}
	ctrl = IXGBE_CTRL_RST;
	ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
	IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
	IXGBE_WRITE_FLUSH(hw);
	hw->mac.ops.release_swfw_sync(hw, swfw_mask);

	/* Poll for reset bit to self-clear indicating reset is complete */
	for (i = 0; i < 10; i++) {
		usec_delay(1);
		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
		if (!(ctrl & IXGBE_CTRL_RST_MASK))
			break;
	}

	if (ctrl & IXGBE_CTRL_RST_MASK) {
		status = IXGBE_ERR_RESET_FAILED;
		ERROR_REPORT1(IXGBE_ERROR_POLLING,
			     "Reset polling failed to complete.\n");
	}
	msec_delay(100);

	/*
	 * Double resets are required for recovery from certain error
	 * conditions.  Between resets, it is necessary to stall to allow time
	 * for any pending HW events to complete.
	 */
	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
		goto mac_reset_top;
	}

	/* Set the Rx packet buffer size. */
	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);

	/* Store the permanent mac address */
	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);

	/*
	 * Store MAC address from RAR0, clear receive address registers, and
	 * clear the multicast table.  Also reset num_rar_entries to 128,
	 * since we modify this value when programming the SAN MAC address.
	 */
	hw->mac.num_rar_entries = 128;
	hw->mac.ops.init_rx_addrs(hw);

	/* Store the permanent SAN mac address */
	hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);

	/* Add the SAN MAC address to the RAR only if it's a valid address */
	if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
		/* Save the SAN MAC RAR index */
		hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;

		hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
				    hw->mac.san_addr, 0, IXGBE_RAH_AV);

		/* clear VMDq pool/queue selection for this RAR */
		hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
				       IXGBE_CLEAR_VMDQ_ALL);

		/* Reserve the last RAR for the SAN MAC address */
		hw->mac.num_rar_entries--;
	}

	/* Store the alternative WWNN/WWPN prefix */
	hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
				   &hw->mac.wwpn_prefix);

reset_hw_out:
	return status;
}
/**
 * ixgbe_reset_hw_X540 - Perform hardware reset
 * @hw: pointer to hardware structure
 *
 * Resets the hardware by resetting the transmit and receive units, masks
 * and clears all interrupts, and perform a reset.
 **/
Perform hardware reset
@hw: pointer to hardware structure

Resets the hardware by resetting the transmit and receive units, masks
and clears all interrupts, and perform a reset.
Perform hardware reset @hw : pointer to hardware structure Resets the hardware by resetting the transmit and receive units masks and clears all interrupts and perform a reset .
s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
{
	s32 status;
	u32 ctrl, i;
	u32 swfw_mask = hw->phy.phy_semaphore_mask;
	DEBUGFUNC("ixgbe_reset_hw_X540");
	status = hw->mac.ops.stop_adapter(hw);
	if (status != IXGBE_SUCCESS)
		goto reset_hw_out;
	ixgbe_clear_tx_pending(hw);
mac_reset_top:
	status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
	if (status != IXGBE_SUCCESS) {
		ERROR_REPORT2(IXGBE_ERROR_CAUTION,
			"semaphore failed with %d", status);
		return IXGBE_ERR_SWFW_SYNC;
	}
	ctrl = IXGBE_CTRL_RST;
	ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
	IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
	IXGBE_WRITE_FLUSH(hw);
	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
	for (i = 0; i < 10; i++) {
		usec_delay(1);
		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
		if (!(ctrl & IXGBE_CTRL_RST_MASK))
			break;
	}
	if (ctrl & IXGBE_CTRL_RST_MASK) {
		status = IXGBE_ERR_RESET_FAILED;
		ERROR_REPORT1(IXGBE_ERROR_POLLING,
			     "Reset polling failed to complete.\n");
	}
	msec_delay(100);
	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
		goto mac_reset_top;
	}
	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
	hw->mac.num_rar_entries = 128;
	hw->mac.ops.init_rx_addrs(hw);
	hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
	if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
		hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
		hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
				    hw->mac.san_addr, 0, IXGBE_RAH_AV);
		hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
				       IXGBE_CLEAR_VMDQ_ALL);
		hw->mac.num_rar_entries--;
	}
	hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
				   &hw->mac.wwpn_prefix);
reset_hw_out:
	return status;
}
s32 ixgbe_reset_hw_X540 ( struct ixgbe_hw * hw ) { s32 status ; u32 ctrl , i ; u32 swfw_mask = hw -> phy . phy_semaphore_mask ; DEBUGFUNC ( " " ) ; status = hw -> mac . ops . stop_adapter ( hw ) ; if ( status != IXGBE_SUCCESS ) goto reset_hw_out ; ixgbe_clear_tx_pending ( hw ) ; mac_reset_top : status = hw -> mac . ops . acquire_swfw_sync ( hw , swfw_mask ) ; if ( status != IXGBE_SUCCESS ) { ERROR_REPORT2 ( IXGBE_ERROR_CAUTION , " " , status ) ; return IXGBE_ERR_SWFW_SYNC ; } ctrl = IXGBE_CTRL_RST ; ctrl |= IXGBE_READ_REG ( hw , IXGBE_CTRL ) ; IXGBE_WRITE_REG ( hw , IXGBE_CTRL , ctrl ) ; IXGBE_WRITE_FLUSH ( hw ) ; hw -> mac . ops . release_swfw_sync ( hw , swfw_mask ) ; for ( i = 0 ; i < 10 ; i ++ ) { usec_delay ( 1 ) ; ctrl = IXGBE_READ_REG ( hw , IXGBE_CTRL ) ; if ( ! ( ctrl & IXGBE_CTRL_RST_MASK ) ) break ; } if ( ctrl & IXGBE_CTRL_RST_MASK ) { status = IXGBE_ERR_RESET_FAILED ; ERROR_REPORT1 ( IXGBE_ERROR_POLLING , " \n " ) ; } msec_delay ( 100 ) ; if ( hw -> mac . flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED ) { hw -> mac . flags &= ~ IXGBE_FLAGS_DOUBLE_RESET_REQUIRED ; goto mac_reset_top ; } IXGBE_WRITE_REG ( hw , IXGBE_RXPBSIZE ( 0 ) , 384 << IXGBE_RXPBSIZE_SHIFT ) ; hw -> mac . ops . get_mac_addr ( hw , hw -> mac . perm_addr ) ; hw -> mac . num_rar_entries = 128 ; hw -> mac . ops . init_rx_addrs ( hw ) ; hw -> mac . ops . get_san_mac_addr ( hw , hw -> mac . san_addr ) ; if ( ixgbe_validate_mac_addr ( hw -> mac . san_addr ) == 0 ) { hw -> mac . san_mac_rar_index = hw -> mac . num_rar_entries - 1 ; hw -> mac . ops . set_rar ( hw , hw -> mac . san_mac_rar_index , hw -> mac . san_addr , 0 , IXGBE_RAH_AV ) ; hw -> mac . ops . clear_vmdq ( hw , hw -> mac . san_mac_rar_index , IXGBE_CLEAR_VMDQ_ALL ) ; hw -> mac . num_rar_entries -- ; } hw -> mac . ops . get_wwn_prefix ( hw , & hw -> mac . wwnn_prefix , & hw -> mac . wwpn_prefix ) ; reset_hw_out : return status ; }
ixgbe_reset_hw_X540 - Perform hardware reset
 @hw: pointer to hardware structure
ixgbe_reset_hw_X540 - Perform hardware reset @hw : pointer to hardware structure
/* Call adapter stop to disable tx/rx and clear interrupts */ /* flush pending Tx transactions */ /* Poll for reset bit to self-clear indicating reset is complete */ /*
	 * Double resets are required for recovery from certain error
	 * conditions.  Between resets, it is necessary to stall to allow time
	 * for any pending HW events to complete.
	 */ /* Set the Rx packet buffer size. */ /* Store the permanent mac address */ /*
	 * Store MAC address from RAR0, clear receive address registers, and
	 * clear the multicast table.  Also reset num_rar_entries to 128,
	 * since we modify this value when programming the SAN MAC address.
	 */ /* Store the permanent SAN mac address */ /* Add the SAN MAC address to the RAR only if it's a valid address */ /* Save the SAN MAC RAR index */ /* clear VMDq pool/queue selection for this RAR */ /* Reserve the last RAR for the SAN MAC address */ /* Store the alternative WWNN/WWPN prefix */