XilinxProcessorIPLib/drivers/dp12txss/src/xdptxss_dbg.c
void XDpTxSs_ReportMsaInfo(XDpTxSs *InstancePtr)
{

	/* Verify argument. */
	Xil_AssertVoid(InstancePtr != NULL);

	XDp_Config *TxConfig = &InstancePtr->DpPtr->Config;

	xil_printf("TX MSA registers:\n\r"
			"\tClocks, H Total      	(0x180) : %ld\n\r"
			"\tClocks, V Total      	(0x184) : %ld\n\r"
			"\tPolarity (V / H)     	(0x188) : %ld\n\r"
			"\tHSync Width          	(0x18C) : %ld\n\r"
			"\tVSync Width          	(0x190) : %ld\n\r"
			"\tHorz Resolution      	(0x194) : %ld\n\r"
			"\tVert Resolution      	(0x198) : %ld\n\r"
			"\tHorz Start           	(0x19C) : %ld\n\r"
			"\tVert Start           	(0x1A0) : %ld\n\r"
			"\tMisc0                	(0x1A4) : 0x%08lX\n\r"
			"\tMisc1                	(0x1A8) : 0x%08lX\n\r"
			"\tUser Pixel Width     	(0x1B8) : %ld\n\r"
			"\tM Vid                	(0x1AC) : %ld\n\r"
			"\tN Vid                	(0x1B4) : %ld\n\r"
			"\tTransfer Unit Size   	(0x1B0) : %ld\n\r"
			"\tUser Data Count      	(0x1BC) : %ld\n\r"
			"\tMinimum bytes per TU 	(0x1C4) : %ld\n\r"
			"\tFractional bytes per TU	(0x1C8) : %ld\n\r"
			"\tInit wait              	(0x1CC) : %ld\n\r",
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HTOTAL),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VTOTAL),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_POLARITY),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HSWIDTH),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VSWIDTH),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HRES),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VRES),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HSTART),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VSTART),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_MISC0),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_MISC1),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_USER_PIXEL_WIDTH),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_M_VID),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_N_VID),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_TU_SIZE),
		XDp_ReadReg(TxConfig->BaseAddr,
				XDP_TX_USER_DATA_COUNT_PER_LANE),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MIN_BYTES_PER_TU),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_FRAC_BYTES_PER_TU),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_INIT_WAIT)
	);

	xil_printf("\n\r");
}
/*****************************************************************************/
/**
*
* This function prints the current main stream attributes from the DisplayPort
* TX core.
*
* @param	InstancePtr is a pointer to the XDpTxSs core instance.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function prints the current main stream attributes from the DisplayPort
TX core.
This function prints the current main stream attributes from the DisplayPort TX core .
void XDpTxSs_ReportMsaInfo(XDpTxSs *InstancePtr)
{
	Xil_AssertVoid(InstancePtr != NULL);
	XDp_Config *TxConfig = &InstancePtr->DpPtr->Config;
	xil_printf("TX MSA registers:\n\r"
			"\tClocks, H Total      	(0x180) : %ld\n\r"
			"\tClocks, V Total      	(0x184) : %ld\n\r"
			"\tPolarity (V / H)     	(0x188) : %ld\n\r"
			"\tHSync Width          	(0x18C) : %ld\n\r"
			"\tVSync Width          	(0x190) : %ld\n\r"
			"\tHorz Resolution      	(0x194) : %ld\n\r"
			"\tVert Resolution      	(0x198) : %ld\n\r"
			"\tHorz Start           	(0x19C) : %ld\n\r"
			"\tVert Start           	(0x1A0) : %ld\n\r"
			"\tMisc0                	(0x1A4) : 0x%08lX\n\r"
			"\tMisc1                	(0x1A8) : 0x%08lX\n\r"
			"\tUser Pixel Width     	(0x1B8) : %ld\n\r"
			"\tM Vid                	(0x1AC) : %ld\n\r"
			"\tN Vid                	(0x1B4) : %ld\n\r"
			"\tTransfer Unit Size   	(0x1B0) : %ld\n\r"
			"\tUser Data Count      	(0x1BC) : %ld\n\r"
			"\tMinimum bytes per TU 	(0x1C4) : %ld\n\r"
			"\tFractional bytes per TU	(0x1C8) : %ld\n\r"
			"\tInit wait              	(0x1CC) : %ld\n\r",
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HTOTAL),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VTOTAL),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_POLARITY),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HSWIDTH),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VSWIDTH),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HRES),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VRES),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_HSTART),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_VSTART),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_MISC0),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MAIN_STREAM_MISC1),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_USER_PIXEL_WIDTH),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_M_VID),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_N_VID),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_TU_SIZE),
		XDp_ReadReg(TxConfig->BaseAddr,
				XDP_TX_USER_DATA_COUNT_PER_LANE),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_MIN_BYTES_PER_TU),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_FRAC_BYTES_PER_TU),
		XDp_ReadReg(TxConfig->BaseAddr, XDP_TX_INIT_WAIT)
	);
	xil_printf("\n\r");
}
void XDpTxSs_ReportMsaInfo ( XDpTxSs * InstancePtr ) { Xil_AssertVoid ( InstancePtr != NULL ) ; XDp_Config * TxConfig = & InstancePtr -> DpPtr -> Config ; xil_printf ( " \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " " \t \n \r " , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_MAIN_STREAM_HTOTAL ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_MAIN_STREAM_VTOTAL ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_MAIN_STREAM_POLARITY ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_MAIN_STREAM_HSWIDTH ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_MAIN_STREAM_VSWIDTH ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_MAIN_STREAM_HRES ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_MAIN_STREAM_VRES ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_MAIN_STREAM_HSTART ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_MAIN_STREAM_VSTART ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_MAIN_STREAM_MISC0 ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_MAIN_STREAM_MISC1 ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_USER_PIXEL_WIDTH ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_M_VID ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_N_VID ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_TU_SIZE ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_USER_DATA_COUNT_PER_LANE ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_MIN_BYTES_PER_TU ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_FRAC_BYTES_PER_TU ) , XDp_ReadReg ( TxConfig -> BaseAddr , XDP_TX_INIT_WAIT ) ) ; xil_printf ( " \n \r " ) ; }
This function prints the current main stream attributes from the DisplayPort
TX core.
This function prints the current main stream attributes from the DisplayPort TX core .
/* Verify argument. */