XilinxProcessorIPLib/drivers/sysmonpsu/src/xsysmonpsu.c
void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor,
            u32 SysmonBlk)
{
	u32 RegValue;
	UINTPTR EffectiveBaseAddress;

	/* Assert the arguments. */
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));

	/* Calculate the effective baseaddress based on the Sysmon instance. */
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);

	/*
	 * Read the Configuration Register 2 and the clear the clock divisor
	 * bits.
	 */
	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
					XSYSMONPSU_CFG_REG2_OFFSET);
	RegValue &= ~(XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK);

	/* Write the divisor value into the Configuration Register 2. */
	RegValue |= ((u32)Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT) &
					XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK;
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET,
			 RegValue);

}
/****************************************************************************/
/**
*
* The function sets the frequency of the ADCCLK by configuring the DCLK to
* ADCCLK ratio in the Configuration Register #2.
*
* @param	InstancePtr is a pointer to the XSysMonPsu instance.
* @param	Divisor is clock divisor used to derive ADCCLK from DCLK.
*		Valid values of the divisor are
*		PS:
*		 - 0 means divide by 8.
*		 - 1,2 means divide by 2.
*		 - 3 to 255 means divide by that value.
*       PL:
*		 - 0,1,2 means divide by 2.
*		 - 3 to 255 means divide by that value.
*		Refer to the device specification for more details.
* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
*       block or PL Sysmon block register region.
*
* @return	None.
*
* @note		- The ADCCLK is an internal clock used by the ADC and is
*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
*		divided by the user selection in the Configuration Register 2.
*		- There is no Assert on the minimum value of the Divisor.
*
*****************************************************************************/
The function sets the frequency of the ADCCLK by configuring the DCLK to
ADCCLK ratio in the Configuration Register #2.
The function sets the frequency of the ADCCLK by configuring the DCLK to ADCCLK ratio in the Configuration Register #2 .
void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor,
            u32 SysmonBlk)
{
	u32 RegValue;
	UINTPTR EffectiveBaseAddress;
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);
	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
					XSYSMONPSU_CFG_REG2_OFFSET);
	RegValue &= ~(XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK);
	RegValue |= ((u32)Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT) &
					XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK;
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET,
			 RegValue);
}
void XSysMonPsu_SetAdcClkDivisor ( XSysMonPsu * InstancePtr , u8 Divisor , u32 SysmonBlk ) { u32 RegValue ; UINTPTR EffectiveBaseAddress ; Xil_AssertVoid ( InstancePtr != NULL ) ; Xil_AssertVoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Xil_AssertVoid ( ( SysmonBlk == XSYSMON_PS ) || ( SysmonBlk == XSYSMON_PL ) ) ; EffectiveBaseAddress = XSysMonPsu_GetEffBaseAddress ( InstancePtr -> Config . BaseAddress , SysmonBlk ) ; RegValue = XSysmonPsu_ReadReg ( EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET ) ; RegValue &= ~ ( XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK ) ; RegValue |= ( ( u32 ) Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT ) & XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET , RegValue ) ; }
The function sets the frequency of the ADCCLK by configuring the DCLK to
ADCCLK ratio in the Configuration Register #2.
The function sets the frequency of the ADCCLK by configuring the DCLK to ADCCLK ratio in the Configuration Register #2 .
/* Assert the arguments. */ /* Calculate the effective baseaddress based on the Sysmon instance. */ /*
	 * Read the Configuration Register 2 and the clear the clock divisor
	 * bits.
	 */ /* Write the divisor value into the Configuration Register 2. */