XilinxProcessorIPLib/drivers/intc/src/xintc.c
int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
				XFastInterruptHandler Handler)
{
	u32 Imr;
	u32 CurrentIER;
	u32 Mask;
	XIntc_Config *CfgPtr;

	/*
	 * Assert the arguments
	 */
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
	Xil_AssertNonvoid(Handler != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid(InstancePtr->CfgPtr->FastIntr == TRUE);


	if (Id > 31) {
		/* Enable user required Id in Slave controller */
		CfgPtr = XIntc_LookupConfig(Id/32);
		if (CfgPtr == NULL) {
			return XST_FAILURE;
		}

		if (CfgPtr->FastIntr != TRUE) {
			/*Fast interrupts of slave controller are not enabled*/
			return XST_FAILURE;
		}

		/* Get the Enabled Interrupts */
		CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);

		/* Convert from integer id to bit mask */
		Mask = XIntc_BitPosMask[(Id%32)];

		/* Disable the Interrupt if it was enabled before calling
		 * this function
		 */
		if (CurrentIER & Mask) {
			XIntc_Disable(InstancePtr, Id);
		}

		if (CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			XIntc_Out64(CfgPtr->BaseAddress + XIN_IVEAR_OFFSET +
					((Id%32) * 8), (UINTPTR) Handler);
		} else {
			XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET +
					((Id%32) * 4), (UINTPTR) Handler);
		}

		/* Slave controllers in Cascade Mode should have all as Fast
		 * interrupts or Normal interrupts, mixed interrupts are not
		 * supported
		 */
		XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF);

		/* Enable the Interrupt if it was enabled before calling this
		 * function
		 */
		if (CurrentIER & Mask) {
			XIntc_Enable(InstancePtr, Id);
		}
	}
	else {
		/* Get the Enabled Interrupts */
		CurrentIER = XIntc_In32(InstancePtr->BaseAddress +
							 XIN_IER_OFFSET);
		/* Convert from integer id to bit mask */
		Mask = XIntc_BitPosMask[Id];

		/* Disable the Interrupt if it was enabled before calling
		 * this function
		 */
		if (CurrentIER & Mask) {
			XIntc_Disable(InstancePtr, Id);
		}

		if (InstancePtr->CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			XIntc_Out64(InstancePtr->BaseAddress +
				XIN_IVEAR_OFFSET + (Id * 8), (UINTPTR) Handler);
		} else {
			XIntc_Out32(InstancePtr->BaseAddress +
				XIN_IVAR_OFFSET + (Id * 4), (UINTPTR) Handler);
		}

		Imr = XIntc_In32(InstancePtr->BaseAddress + XIN_IMR_OFFSET);
		XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET,
							Imr | Mask);

		/* Enable the Interrupt if it was enabled before
		 * calling this function
		 */
		if (CurrentIER & Mask) {
			XIntc_Enable(InstancePtr, Id);
		}

	}

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* Makes the connection between the Id of the interrupt source and the
* associated handler that is to run when the interrupt is recognized.In Cascade
* mode, connects handler to corresponding Slave controller IVAR/IVEAR register
* depending on the Id and sets all interrupt sources of the Slave controller as
* fast interrupts.
*
* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
* @param	Id contains the ID of the interrupt source and should be in the
*		range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS - 1 with 0 being
*		the highest priority interrupt.
* @param	Handler for specified interrupt id. It must be declared with
*           "fast_interrupt" attribute.
*           e.g. static void MyHandler(void) __attribute__ ((fast_interrupt));
*
* @return
*		- XST_SUCCESS
*
* @note
* 		Slave controllers in Cascade Mode should have all as Fast
* 		interrupts or Normal interrupts, mixed interrupts are not
*		supported
*
* WARNING: The handler provided as an argument will overwrite any handler
* that was previously connected.
*
****************************************************************************/
Makes the connection between the Id of the interrupt source and the
associated handler that is to run when the interrupt is recognized.In Cascade
mode, connects handler to corresponding Slave controller IVAR/IVEAR register
depending on the Id and sets all interrupt sources of the Slave controller as
fast interrupts.
Makes the connection between the Id of the interrupt source and the associated handler that is to run when the interrupt is recognized . In Cascade mode connects handler to corresponding Slave controller IVAR / IVEAR register depending on the Id and sets all interrupt sources of the Slave controller as fast interrupts .
int XIntc_ConnectFastHandler(XIntc *InstancePtr, u8 Id,
				XFastInterruptHandler Handler)
{
	u32 Imr;
	u32 CurrentIER;
	u32 Mask;
	XIntc_Config *CfgPtr;
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
	Xil_AssertNonvoid(Handler != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertNonvoid(InstancePtr->CfgPtr->FastIntr == TRUE);
	if (Id > 31) {
		CfgPtr = XIntc_LookupConfig(Id/32);
		if (CfgPtr == NULL) {
			return XST_FAILURE;
		}
		if (CfgPtr->FastIntr != TRUE) {
			return XST_FAILURE;
		}
		CurrentIER = XIntc_In32(CfgPtr->BaseAddress + XIN_IER_OFFSET);
		Mask = XIntc_BitPosMask[(Id%32)];
		if (CurrentIER & Mask) {
			XIntc_Disable(InstancePtr, Id);
		}
		if (CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			XIntc_Out64(CfgPtr->BaseAddress + XIN_IVEAR_OFFSET +
					((Id%32) * 8), (UINTPTR) Handler);
		} else {
			XIntc_Out32(CfgPtr->BaseAddress + XIN_IVAR_OFFSET +
					((Id%32) * 4), (UINTPTR) Handler);
		}
		XIntc_Out32(CfgPtr->BaseAddress + XIN_IMR_OFFSET, 0xFFFFFFFF);
		if (CurrentIER & Mask) {
			XIntc_Enable(InstancePtr, Id);
		}
	}
	else {
		CurrentIER = XIntc_In32(InstancePtr->BaseAddress +
							 XIN_IER_OFFSET);
		Mask = XIntc_BitPosMask[Id];
		if (CurrentIER & Mask) {
			XIntc_Disable(InstancePtr, Id);
		}
		if (InstancePtr->CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			XIntc_Out64(InstancePtr->BaseAddress +
				XIN_IVEAR_OFFSET + (Id * 8), (UINTPTR) Handler);
		} else {
			XIntc_Out32(InstancePtr->BaseAddress +
				XIN_IVAR_OFFSET + (Id * 4), (UINTPTR) Handler);
		}
		Imr = XIntc_In32(InstancePtr->BaseAddress + XIN_IMR_OFFSET);
		XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET,
							Imr | Mask);
		if (CurrentIER & Mask) {
			XIntc_Enable(InstancePtr, Id);
		}
	}
	return XST_SUCCESS;
}
int XIntc_ConnectFastHandler ( XIntc * InstancePtr , u8 Id , XFastInterruptHandler Handler ) { u32 Imr ; u32 CurrentIER ; u32 Mask ; XIntc_Config * CfgPtr ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; Xil_AssertNonvoid ( Id < XPAR_INTC_MAX_NUM_INTR_INPUTS ) ; Xil_AssertNonvoid ( Handler != NULL ) ; Xil_AssertNonvoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Xil_AssertNonvoid ( InstancePtr -> CfgPtr -> FastIntr == TRUE ) ; if ( Id > 31 ) { CfgPtr = XIntc_LookupConfig ( Id / 32 ) ; if ( CfgPtr == NULL ) { return XST_FAILURE ; } if ( CfgPtr -> FastIntr != TRUE ) { return XST_FAILURE ; } CurrentIER = XIntc_In32 ( CfgPtr -> BaseAddress + XIN_IER_OFFSET ) ; Mask = XIntc_BitPosMask [ ( Id % 32 ) ] ; if ( CurrentIER & Mask ) { XIntc_Disable ( InstancePtr , Id ) ; } if ( CfgPtr -> VectorAddrWidth > XINTC_STANDARD_VECTOR_ADDRESS_WIDTH ) { XIntc_Out64 ( CfgPtr -> BaseAddress + XIN_IVEAR_OFFSET + ( ( Id % 32 ) * 8 ) , ( UINTPTR ) Handler ) ; } else { XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_IVAR_OFFSET + ( ( Id % 32 ) * 4 ) , ( UINTPTR ) Handler ) ; } XIntc_Out32 ( CfgPtr -> BaseAddress + XIN_IMR_OFFSET , 0xFFFFFFFF ) ; if ( CurrentIER & Mask ) { XIntc_Enable ( InstancePtr , Id ) ; } } else { CurrentIER = XIntc_In32 ( InstancePtr -> BaseAddress + XIN_IER_OFFSET ) ; Mask = XIntc_BitPosMask [ Id ] ; if ( CurrentIER & Mask ) { XIntc_Disable ( InstancePtr , Id ) ; } if ( InstancePtr -> CfgPtr -> VectorAddrWidth > XINTC_STANDARD_VECTOR_ADDRESS_WIDTH ) { XIntc_Out64 ( InstancePtr -> BaseAddress + XIN_IVEAR_OFFSET + ( Id * 8 ) , ( UINTPTR ) Handler ) ; } else { XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_IVAR_OFFSET + ( Id * 4 ) , ( UINTPTR ) Handler ) ; } Imr = XIntc_In32 ( InstancePtr -> BaseAddress + XIN_IMR_OFFSET ) ; XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_IMR_OFFSET , Imr | Mask ) ; if ( CurrentIER & Mask ) { XIntc_Enable ( InstancePtr , Id ) ; } } return XST_SUCCESS ; }
Makes the connection between the Id of the interrupt source and the
associated handler that is to run when the interrupt is recognized.In Cascade
mode, connects handler to corresponding Slave controller IVAR/IVEAR register
depending on the Id and sets all interrupt sources of the Slave controller as
fast interrupts.
Makes the connection between the Id of the interrupt source and the associated handler that is to run when the interrupt is recognized . In Cascade mode connects handler to corresponding Slave controller IVAR / IVEAR register depending on the Id and sets all interrupt sources of the Slave controller as fast interrupts .
/*
	 * Assert the arguments
	 */ /* Enable user required Id in Slave controller */ /*Fast interrupts of slave controller are not enabled*/ /* Get the Enabled Interrupts */ /* Convert from integer id to bit mask */ /* Disable the Interrupt if it was enabled before calling
		 * this function
		 */ /* Slave controllers in Cascade Mode should have all as Fast
		 * interrupts or Normal interrupts, mixed interrupts are not
		 * supported
		 */ /* Enable the Interrupt if it was enabled before calling this
		 * function
		 */ /* Get the Enabled Interrupts */ /* Convert from integer id to bit mask */ /* Disable the Interrupt if it was enabled before calling
		 * this function
		 */ /* Enable the Interrupt if it was enabled before
		 * calling this function
		 */