lib/sw_apps/zynqmp_pmufw/src/pm_binding.c
s32 XPfw_PmWakeHandler(const u32 srcMask)
{
	s32 status = XST_INVALID_PARAM;

#if defined(PMU_MIO_INPUT_PIN) && (PMU_MIO_INPUT_PIN >= 0U) \
				&& (PMU_MIO_INPUT_PIN <= 5U)
	if ((PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK << PMU_MIO_INPUT_PIN) == srcMask) {
		PmShutdownInterruptHandler();
		return XST_SUCCESS;
	}
#endif
	if (0U != (PMU_IOMODULE_GPI1_GIC_WAKES_ALL_MASK & srcMask))  {
		/* Processor GIC wake */
		PmProc* proc = PmProcGetByWakeMask(srcMask);
		if ((NULL != proc) && (NULL != proc->master)) {
			status = PmMasterWakeProc(proc);
		} else {
			status = XST_INVALID_PARAM;
		}
	} else if (0U != (PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_MASK & srcMask)) {
		status = PmMasterWake(&pmMasterApu_g);
	} else if (0U != (PMU_IOMODULE_GPI1_MIO_WAKE_ALL_MASK & srcMask)) {
		status = PmExternWakeMasters();
	} else if (0U != (PMU_IOMODULE_GPI1_USB_0_WAKE_MASK & srcMask)) {
		status = PmWakeMasterBySlave(&pmSlaveUsb0_g.slv);
	} else if (0U != (PMU_IOMODULE_GPI1_USB_1_WAKE_MASK & srcMask)) {
		status = PmWakeMasterBySlave(&pmSlaveUsb1_g.slv);
	} else {
		/* For MISRA compliance */
	}

	return status;
}
/**
 * XPfw_PmWakeHandler() - Call from GPI1 interrupt to process wake request
 * @srcMask     Value read from GPI1 register which determines interrupt source
 *
 * @return      Status of performing wake-up (XST_INVALID_PARAM if wake is a
 *              processor wake event but processor is not found, status of
 *              performing wake otherwise)
 *
 * @note    Call from GPI1 interrupt routine to process wake request. Must not
 *          clear GPI1 interrupt before this function returns.
 *          If the wake source is one of GIC wakes, source of the interrupt
 *          (peripheral that actually generated interrupt to GIC) cannot be
 *          determined, and target should be immediately woken-up (target is
 *          processor whose GIC wake bit is set in srcMask). If the wake is the
 *          FPD GIC Proxy interrupt, the APU needs to be woken up.
 */
Call from GPI1 interrupt to process wake request
@srcMask     Value read from GPI1 register which determines interrupt source

@return      Status of performing wake-up (XST_INVALID_PARAM if wake is a
processor wake event but processor is not found, status of
performing wake otherwise)

@note    Call from GPI1 interrupt routine to process wake request. Must not
clear GPI1 interrupt before this function returns.
If the wake source is one of GIC wakes, source of the interrupt
(peripheral that actually generated interrupt to GIC) cannot be
determined, and target should be immediately woken-up (target is
processor whose GIC wake bit is set in srcMask). If the wake is the
FPD GIC Proxy interrupt, the APU needs to be woken up.
Call from GPI1 interrupt to process wake request @srcMask Value read from GPI1 register which determines interrupt source @return Status of performing wake - up ( XST_INVALID_PARAM if wake is a processor wake event but processor is not found status of performing wake otherwise ) @note Call from GPI1 interrupt routine to process wake request . Must not clear GPI1 interrupt before this function returns . If the wake source is one of GIC wakes source of the interrupt ( peripheral that actually generated interrupt to GIC ) cannot be determined and target should be immediately woken - up ( target is processor whose GIC wake bit is set in srcMask ) . If the wake is the FPD GIC Proxy interrupt the APU needs to be woken up .
s32 XPfw_PmWakeHandler(const u32 srcMask)
{
	s32 status = XST_INVALID_PARAM;
#if defined(PMU_MIO_INPUT_PIN) && (PMU_MIO_INPUT_PIN >= 0U) \
				&& (PMU_MIO_INPUT_PIN <= 5U)
	if ((PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK << PMU_MIO_INPUT_PIN) == srcMask) {
		PmShutdownInterruptHandler();
		return XST_SUCCESS;
	}
#endif
	if (0U != (PMU_IOMODULE_GPI1_GIC_WAKES_ALL_MASK & srcMask))  {
		PmProc* proc = PmProcGetByWakeMask(srcMask);
		if ((NULL != proc) && (NULL != proc->master)) {
			status = PmMasterWakeProc(proc);
		} else {
			status = XST_INVALID_PARAM;
		}
	} else if (0U != (PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_MASK & srcMask)) {
		status = PmMasterWake(&pmMasterApu_g);
	} else if (0U != (PMU_IOMODULE_GPI1_MIO_WAKE_ALL_MASK & srcMask)) {
		status = PmExternWakeMasters();
	} else if (0U != (PMU_IOMODULE_GPI1_USB_0_WAKE_MASK & srcMask)) {
		status = PmWakeMasterBySlave(&pmSlaveUsb0_g.slv);
	} else if (0U != (PMU_IOMODULE_GPI1_USB_1_WAKE_MASK & srcMask)) {
		status = PmWakeMasterBySlave(&pmSlaveUsb1_g.slv);
	} else {
	}
	return status;
}
s32 XPfw_PmWakeHandler ( const u32 srcMask ) { s32 status = XST_INVALID_PARAM ; #if defined ( PMU_MIO_INPUT_PIN ) && ( PMU_MIO_INPUT_PIN >= 0U ) && ( PMU_MIO_INPUT_PIN <= 5U ) if ( ( PMU_IOMODULE_GPI1_MIO_WAKE_0_MASK << PMU_MIO_INPUT_PIN ) == srcMask ) { PmShutdownInterruptHandler ( ) ; return XST_SUCCESS ; } #endif if ( 0U != ( PMU_IOMODULE_GPI1_GIC_WAKES_ALL_MASK & srcMask ) ) { PmProc * proc = PmProcGetByWakeMask ( srcMask ) ; if ( ( NULL != proc ) && ( NULL != proc -> master ) ) { status = PmMasterWakeProc ( proc ) ; } else { status = XST_INVALID_PARAM ; } } else if ( 0U != ( PMU_IOMODULE_GPI1_FPD_WAKE_GIC_PROXY_MASK & srcMask ) ) { status = PmMasterWake ( & pmMasterApu_g ) ; } else if ( 0U != ( PMU_IOMODULE_GPI1_MIO_WAKE_ALL_MASK & srcMask ) ) { status = PmExternWakeMasters ( ) ; } else if ( 0U != ( PMU_IOMODULE_GPI1_USB_0_WAKE_MASK & srcMask ) ) { status = PmWakeMasterBySlave ( & pmSlaveUsb0_g . slv ) ; } else if ( 0U != ( PMU_IOMODULE_GPI1_USB_1_WAKE_MASK & srcMask ) ) { status = PmWakeMasterBySlave ( & pmSlaveUsb1_g . slv ) ; } else { } return status ; }
XPfw_PmWakeHandler() - Call from GPI1 interrupt to process wake request
 @srcMask     Value read from GPI1 register which determines interrupt source
XPfw_PmWakeHandler () - Call from GPI1 interrupt to process wake request @srcMask Value read from GPI1 register which determines interrupt source
/* Processor GIC wake */ /* For MISRA compliance */