lib/sw_apps/zynqmp_pmufw/src/pm_system.c
static void PmSystemPosHaltRpu(void)
{
	/* Halt RPU0 */
	XPfw_RMW32(CRL_APB_RST_LPD_TOP,CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK,
		   CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
	XPfw_RMW32(RPU_RPU_0_CFG, RPU_RPU_0_CFG_NCPUHALT_MASK,
		  ~RPU_RPU_0_CFG_NCPUHALT_MASK);
	XPfw_RMW32(CRL_APB_RST_LPD_TOP, CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK,
		  ~CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);

	/* Halt RPU1 */
	XPfw_RMW32(CRL_APB_RST_LPD_TOP, CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK,
		   CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
	XPfw_RMW32(RPU_RPU_1_CFG, RPU_RPU_1_CFG_NCPUHALT_MASK,
		  ~RPU_RPU_1_CFG_NCPUHALT_MASK);
	XPfw_RMW32(CRL_APB_RST_LPD_TOP, CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK,
		  ~CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
}
/**
 * PmSystemPosHaltRpu() - Halt RPU0 and RPU1 cores in order to access TCMs
 */
Halt RPU0 and RPU1 cores in order to access TCMs
Halt RPU0 and RPU1 cores in order to access TCMs
static void PmSystemPosHaltRpu(void)
{
	XPfw_RMW32(CRL_APB_RST_LPD_TOP,CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK,
		   CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
	XPfw_RMW32(RPU_RPU_0_CFG, RPU_RPU_0_CFG_NCPUHALT_MASK,
		  ~RPU_RPU_0_CFG_NCPUHALT_MASK);
	XPfw_RMW32(CRL_APB_RST_LPD_TOP, CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK,
		  ~CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
	XPfw_RMW32(CRL_APB_RST_LPD_TOP, CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK,
		   CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
	XPfw_RMW32(RPU_RPU_1_CFG, RPU_RPU_1_CFG_NCPUHALT_MASK,
		  ~RPU_RPU_1_CFG_NCPUHALT_MASK);
	XPfw_RMW32(CRL_APB_RST_LPD_TOP, CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK,
		  ~CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
}
static void PmSystemPosHaltRpu ( void ) { XPfw_RMW32 ( CRL_APB_RST_LPD_TOP , CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK , CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK ) ; XPfw_RMW32 ( RPU_RPU_0_CFG , RPU_RPU_0_CFG_NCPUHALT_MASK , ~ RPU_RPU_0_CFG_NCPUHALT_MASK ) ; XPfw_RMW32 ( CRL_APB_RST_LPD_TOP , CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK , ~ CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK ) ; XPfw_RMW32 ( CRL_APB_RST_LPD_TOP , CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK , CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK ) ; XPfw_RMW32 ( RPU_RPU_1_CFG , RPU_RPU_1_CFG_NCPUHALT_MASK , ~ RPU_RPU_1_CFG_NCPUHALT_MASK ) ; XPfw_RMW32 ( CRL_APB_RST_LPD_TOP , CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK , ~ CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK ) ; }
PmSystemPosHaltRpu() - Halt RPU0 and RPU1 cores in order to access TCMs
PmSystemPosHaltRpu () - Halt RPU0 and RPU1 cores in order to access TCMs
/* Halt RPU0 */ /* Halt RPU1 */