XilinxProcessorIPLib/drivers/axiethernet/examples/xaxiethernet_example_intr_sgdma.c
int AxiEthernetSgDmaIntrExample(INTC *IntcInstancePtr,
				XAxiEthernet *AxiEthernetInstancePtr,
				XAxiDma *DmaInstancePtr,
				u16 AxiEthernetDeviceId,
				u16 AxiDmaDeviceId,
				u16 AxiEthernetIntrId,
				u16 DmaRxIntrId,
				u16 DmaTxIntrId)
{
	int Status;
	int LoopbackSpeed;
	XAxiEthernet_Config *MacCfgPtr;
	XAxiDma_Config* DmaConfig;
	XAxiDma_BdRing *RxRingPtr = XAxiDma_GetRxRing(DmaInstancePtr);
	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(DmaInstancePtr);
	XAxiDma_Bd BdTemplate;

	/*************************************/
	/* Setup device for first-time usage */
	/*************************************/

	/*
	 *  Get the configuration of AxiEthernet hardware.
	 */
	MacCfgPtr = XAxiEthernet_LookupConfig(AxiEthernetDeviceId);

	/*
	 * Check whether DMA is present or not
	 */
	if(MacCfgPtr->AxiDevType != XPAR_AXI_DMA) {
		AxiEthernetUtilErrorTrap
			("Device HW not configured for SGDMA mode\r\n");
		return XST_FAILURE;
	}

	DmaConfig = XAxiDma_LookupConfig(AxiDmaDeviceId);
	/*
	 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
	 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
	 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
	 * would ensure a reset of AxiEthernet.
	 */
	Status = XAxiDma_CfgInitialize(DmaInstancePtr, DmaConfig);
	if(Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error initializing DMA\r\n");
		return XST_FAILURE;
	}

	/*
	 * Initialize AxiEthernet hardware.
	 */
	Status = XAxiEthernet_CfgInitialize(AxiEthernetInstancePtr, MacCfgPtr,
					MacCfgPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error in initialize");
		return XST_FAILURE;
	}

	/*
	 * Set the MAC address
	 */
	Status = XAxiEthernet_SetMacAddress(AxiEthernetInstancePtr,
							AxiEthernetMAC);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting MAC address");
		return XST_FAILURE;
	}

#if defined(__aarch64__)
	Xil_SetTlbAttributes((UINTPTR) TxBdSpace, NORM_NONCACHE | INNER_SHAREABLE);
	Xil_SetTlbAttributes((UINTPTR) RxBdSpace, NORM_NONCACHE | INNER_SHAREABLE);
#endif
	/*
	 * Setup RxBD space.
	 *
	 * We have already defined a properly aligned area of memory to store
	 * RxBDs at the beginning of this source code file so just pass its
	 * address into the function. No MMU is being used so the physical and
	 * virtual addresses are the same.
	 *
	 * Setup a BD template for the Rx channel. This template will be
	 * copied to every RxBD. We will not have to explicitly set these
	 * again.
	 */

	/*
	 * Disable all RX interrupts before RxBD space setup
	 */
	XAxiDma_BdRingIntDisable(RxRingPtr, XAXIDMA_IRQ_ALL_MASK);

	/*
	 * Create the RxBD ring
	 */
	Status = XAxiDma_BdRingCreate(RxRingPtr, (UINTPTR) &RxBdSpace,
				     (UINTPTR) &RxBdSpace, BD_ALIGNMENT, RXBD_CNT);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting up RxBD space");
		return XST_FAILURE;
	}

	XAxiDma_BdClear(&BdTemplate);
	Status = XAxiDma_BdRingClone(RxRingPtr, &BdTemplate);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error initializing RxBD space");
		return XST_FAILURE;
	}

	/*
	 * Setup TxBD space.
	 *
	 * Like RxBD space, we have already defined a properly aligned area of
	 * memory to use.
	 */

	/*
	 * Create the TxBD ring
	 */
	Status = XAxiDma_BdRingCreate(TxRingPtr, (UINTPTR) &TxBdSpace,
				(UINTPTR) &TxBdSpace, BD_ALIGNMENT, TXBD_CNT);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting up TxBD space");
		return XST_FAILURE;
	}
	/*
	 * We reuse the bd template, as the same one will work for both rx
	 * and tx.
	 */
	Status = XAxiDma_BdRingClone(TxRingPtr, &BdTemplate);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error initializing TxBD space");
		return XST_FAILURE;
	}

	/*
	 * Set PHY to loopback, speed depends on phy type.
	 * MII is 100 and all others are 1000.
	 */
	if (XAxiEthernet_GetPhysicalInterface(AxiEthernetInstancePtr) ==
						XAE_PHY_TYPE_MII) {
		LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED;
	} else {
		LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED_1G;
	}
	AxiEthernetUtilEnterLoopback(AxiEthernetInstancePtr, LoopbackSpeed);
	/*
	 * Set PHY<-->MAC data clock
	 */
	Status =  XAxiEthernet_SetOperatingSpeed(AxiEthernetInstancePtr,
							(u16)LoopbackSpeed);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Setting the operating speed of the MAC needs a delay.  There
	 * doesn't seem to be register to poll, so please consider this
	 * during your application design.
	 */
	AxiEthernetUtilPhyDelay(2);

	/*
	 * Connect to the interrupt controller and enable interrupts
	 */
	Status = AxiEthernetSetupIntrSystem(IntcInstancePtr,
						AxiEthernetInstancePtr,
						DmaInstancePtr,
						AxiEthernetIntrId,
						DmaRxIntrId,
						DmaTxIntrId);


	/****************************/
	/* Run through the examples */
	/****************************/

	/*
	 * Run the AxiEthernet DMA Single Frame Interrupt example
	 */
	Status = AxiEthernetSgDmaIntrSingleFrameExample(AxiEthernetInstancePtr,
						  DmaInstancePtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}


	/*
	 * Run the Axi Ethernet DMA Interrupt Coalescing example
	 */
	Status = AxiEthernetSgDmaIntrCoalescingExample(AxiEthernetInstancePtr,
						 DmaInstancePtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Tx/Rx Partial checksum offload will be disabled when any of
	 * Tx/Rx VLAN features are built in hardware.
	 */
	if (XAxiEthernet_IsRxPartialCsum(AxiEthernetInstancePtr) &&
		XAxiEthernet_IsTxPartialCsum(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsTxVlanTran(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsTxVlanStrp(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsTxVlanTag(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsRxVlanTran(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsRxVlanStrp(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsRxVlanTag(AxiEthernetInstancePtr))  {
		Status = AxiEthernetSgDmaPartialChecksumOffloadExample
			(AxiEthernetInstancePtr,DmaInstancePtr);

		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}
	}


	/*
	 * Tx/Rx Full checksum offload will be disabled when any of
	 * Tx/Rx VLAN features are built in hardware.
	 */
	if (XAxiEthernet_IsRxFullCsum(AxiEthernetInstancePtr) &&
		XAxiEthernet_IsTxFullCsum(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsTxVlanTran(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsTxVlanStrp(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsTxVlanTag(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsRxVlanTran(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsRxVlanStrp(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsRxVlanTag(AxiEthernetInstancePtr))  {
		Status = AxiEthernetSgDmaFullChecksumOffloadExample
		(AxiEthernetInstancePtr,DmaInstancePtr);

		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}
	}

	/*
	 * Disable the interrupts for the Axi Ethernet device
	 */
	AxiEthernetDisableIntrSystem(IntcInstancePtr, AxiEthernetIntrId,
						DmaRxIntrId, DmaTxIntrId);

	/*
	 * Stop the device
	 */
	XAxiEthernet_Stop(AxiEthernetInstancePtr);

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function demonstrates the usage usage of the Axi Ethernet by sending
* and receiving frames in interrupt driven SGDMA mode.
*
*
* @param	IntcInstancePtr is a pointer to the instance of the Intc
*		component.
* @param	AxiEthernetInstancePtr is a pointer to the instance of the
*		AxiEthernet component.
* @param	DmaInstancePtr is a pointer to the instance of the AXIDMA
*		component.
* @param	AxiEthernetDeviceId is Device ID of the Axi Ethernet Device ,
*		typically XPAR_<AXIETHERNET_instance>_DEVICE_ID value from
*		xparameters.h.
* @param	AxiDmaDeviceId is Device ID of the Axi DMAA Device ,
*		typically XPAR_<AXIDMA_instance>_DEVICE_ID value from
*		xparameters.h.
* @param	AxiEthernetIntrId is the Interrupt ID and is typically
*		XPAR_<INTC_instance>_<AXIETHERNET_instance>_VEC_ID
*		value from xparameters.h.
* @param	DmaRxIntrId is the interrupt id for DMA Rx and is typically
*		taken from XPAR_<AXIETHERNET_instance>_CONNECTED_DMARX_INTR
* @param	DmaTxIntrId is the interrupt id for DMA Tx and is typically
*		taken from XPAR_<AXIETHERNET_instance>_CONNECTED_DMATX_INTR
*
* @return	-XST_SUCCESS to indicate success
*		-XST_FAILURE to indicate failure
*
* @note		AxiDma hardware must be initialized before initializing
*		AxiEthernet. Since AxiDma reset line is connected to the
*		AxiEthernet reset line, a reset of AxiDma hardware during its
*		initialization would reset AxiEthernet.
*
******************************************************************************/
This function demonstrates the usage usage of the Axi Ethernet by sending
and receiving frames in interrupt driven SGDMA mode.
This function demonstrates the usage usage of the Axi Ethernet by sending and receiving frames in interrupt driven SGDMA mode .
int AxiEthernetSgDmaIntrExample(INTC *IntcInstancePtr,
				XAxiEthernet *AxiEthernetInstancePtr,
				XAxiDma *DmaInstancePtr,
				u16 AxiEthernetDeviceId,
				u16 AxiDmaDeviceId,
				u16 AxiEthernetIntrId,
				u16 DmaRxIntrId,
				u16 DmaTxIntrId)
{
	int Status;
	int LoopbackSpeed;
	XAxiEthernet_Config *MacCfgPtr;
	XAxiDma_Config* DmaConfig;
	XAxiDma_BdRing *RxRingPtr = XAxiDma_GetRxRing(DmaInstancePtr);
	XAxiDma_BdRing *TxRingPtr = XAxiDma_GetTxRing(DmaInstancePtr);
	XAxiDma_Bd BdTemplate;
	MacCfgPtr = XAxiEthernet_LookupConfig(AxiEthernetDeviceId);
	if(MacCfgPtr->AxiDevType != XPAR_AXI_DMA) {
		AxiEthernetUtilErrorTrap
			("Device HW not configured for SGDMA mode\r\n");
		return XST_FAILURE;
	}
	DmaConfig = XAxiDma_LookupConfig(AxiDmaDeviceId);
	Status = XAxiDma_CfgInitialize(DmaInstancePtr, DmaConfig);
	if(Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error initializing DMA\r\n");
		return XST_FAILURE;
	}
	Status = XAxiEthernet_CfgInitialize(AxiEthernetInstancePtr, MacCfgPtr,
					MacCfgPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error in initialize");
		return XST_FAILURE;
	}
	Status = XAxiEthernet_SetMacAddress(AxiEthernetInstancePtr,
							AxiEthernetMAC);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting MAC address");
		return XST_FAILURE;
	}
#if defined(__aarch64__)
	Xil_SetTlbAttributes((UINTPTR) TxBdSpace, NORM_NONCACHE | INNER_SHAREABLE);
	Xil_SetTlbAttributes((UINTPTR) RxBdSpace, NORM_NONCACHE | INNER_SHAREABLE);
#endif
	XAxiDma_BdRingIntDisable(RxRingPtr, XAXIDMA_IRQ_ALL_MASK);
	Status = XAxiDma_BdRingCreate(RxRingPtr, (UINTPTR) &RxBdSpace,
				     (UINTPTR) &RxBdSpace, BD_ALIGNMENT, RXBD_CNT);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting up RxBD space");
		return XST_FAILURE;
	}
	XAxiDma_BdClear(&BdTemplate);
	Status = XAxiDma_BdRingClone(RxRingPtr, &BdTemplate);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error initializing RxBD space");
		return XST_FAILURE;
	}
	Status = XAxiDma_BdRingCreate(TxRingPtr, (UINTPTR) &TxBdSpace,
				(UINTPTR) &TxBdSpace, BD_ALIGNMENT, TXBD_CNT);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error setting up TxBD space");
		return XST_FAILURE;
	}
	Status = XAxiDma_BdRingClone(TxRingPtr, &BdTemplate);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Error initializing TxBD space");
		return XST_FAILURE;
	}
	if (XAxiEthernet_GetPhysicalInterface(AxiEthernetInstancePtr) ==
						XAE_PHY_TYPE_MII) {
		LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED;
	} else {
		LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED_1G;
	}
	AxiEthernetUtilEnterLoopback(AxiEthernetInstancePtr, LoopbackSpeed);
	Status =  XAxiEthernet_SetOperatingSpeed(AxiEthernetInstancePtr,
							(u16)LoopbackSpeed);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	AxiEthernetUtilPhyDelay(2);
	Status = AxiEthernetSetupIntrSystem(IntcInstancePtr,
						AxiEthernetInstancePtr,
						DmaInstancePtr,
						AxiEthernetIntrId,
						DmaRxIntrId,
						DmaTxIntrId);
	Status = AxiEthernetSgDmaIntrSingleFrameExample(AxiEthernetInstancePtr,
						  DmaInstancePtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	Status = AxiEthernetSgDmaIntrCoalescingExample(AxiEthernetInstancePtr,
						 DmaInstancePtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	if (XAxiEthernet_IsRxPartialCsum(AxiEthernetInstancePtr) &&
		XAxiEthernet_IsTxPartialCsum(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsTxVlanTran(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsTxVlanStrp(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsTxVlanTag(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsRxVlanTran(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsRxVlanStrp(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsRxVlanTag(AxiEthernetInstancePtr))  {
		Status = AxiEthernetSgDmaPartialChecksumOffloadExample
			(AxiEthernetInstancePtr,DmaInstancePtr);
		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}
	}
	if (XAxiEthernet_IsRxFullCsum(AxiEthernetInstancePtr) &&
		XAxiEthernet_IsTxFullCsum(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsTxVlanTran(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsTxVlanStrp(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsTxVlanTag(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsRxVlanTran(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsRxVlanStrp(AxiEthernetInstancePtr) &&
		!XAxiEthernet_IsRxVlanTag(AxiEthernetInstancePtr))  {
		Status = AxiEthernetSgDmaFullChecksumOffloadExample
		(AxiEthernetInstancePtr,DmaInstancePtr);
		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}
	}
	AxiEthernetDisableIntrSystem(IntcInstancePtr, AxiEthernetIntrId,
						DmaRxIntrId, DmaTxIntrId);
	XAxiEthernet_Stop(AxiEthernetInstancePtr);
	return XST_SUCCESS;
}
int AxiEthernetSgDmaIntrExample ( INTC * IntcInstancePtr , XAxiEthernet * AxiEthernetInstancePtr , XAxiDma * DmaInstancePtr , u16 AxiEthernetDeviceId , u16 AxiDmaDeviceId , u16 AxiEthernetIntrId , u16 DmaRxIntrId , u16 DmaTxIntrId ) { int Status ; int LoopbackSpeed ; XAxiEthernet_Config * MacCfgPtr ; XAxiDma_Config * DmaConfig ; XAxiDma_BdRing * RxRingPtr = XAxiDma_GetRxRing ( DmaInstancePtr ) ; XAxiDma_BdRing * TxRingPtr = XAxiDma_GetTxRing ( DmaInstancePtr ) ; XAxiDma_Bd BdTemplate ; MacCfgPtr = XAxiEthernet_LookupConfig ( AxiEthernetDeviceId ) ; if ( MacCfgPtr -> AxiDevType != XPAR_AXI_DMA ) { AxiEthernetUtilErrorTrap ( " \r \n " ) ; return XST_FAILURE ; } DmaConfig = XAxiDma_LookupConfig ( AxiDmaDeviceId ) ; Status = XAxiDma_CfgInitialize ( DmaInstancePtr , DmaConfig ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " \r \n " ) ; return XST_FAILURE ; } Status = XAxiEthernet_CfgInitialize ( AxiEthernetInstancePtr , MacCfgPtr , MacCfgPtr -> BaseAddress ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } Status = XAxiEthernet_SetMacAddress ( AxiEthernetInstancePtr , AxiEthernetMAC ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } #if defined ( __aarch64__ ) Xil_SetTlbAttributes ( ( UINTPTR ) TxBdSpace , NORM_NONCACHE | INNER_SHAREABLE ) ; Xil_SetTlbAttributes ( ( UINTPTR ) RxBdSpace , NORM_NONCACHE | INNER_SHAREABLE ) ; #endif XAxiDma_BdRingIntDisable ( RxRingPtr , XAXIDMA_IRQ_ALL_MASK ) ; Status = XAxiDma_BdRingCreate ( RxRingPtr , ( UINTPTR ) & RxBdSpace , ( UINTPTR ) & RxBdSpace , BD_ALIGNMENT , RXBD_CNT ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } XAxiDma_BdClear ( & BdTemplate ) ; Status = XAxiDma_BdRingClone ( RxRingPtr , & BdTemplate ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } Status = XAxiDma_BdRingCreate ( TxRingPtr , ( UINTPTR ) & TxBdSpace , ( UINTPTR ) & TxBdSpace , BD_ALIGNMENT , TXBD_CNT ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } Status = XAxiDma_BdRingClone ( TxRingPtr , & BdTemplate ) ; if ( Status != XST_SUCCESS ) { AxiEthernetUtilErrorTrap ( " " ) ; return XST_FAILURE ; } if ( XAxiEthernet_GetPhysicalInterface ( AxiEthernetInstancePtr ) == XAE_PHY_TYPE_MII ) { LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED ; } else { LoopbackSpeed = AXIETHERNET_LOOPBACK_SPEED_1G ; } AxiEthernetUtilEnterLoopback ( AxiEthernetInstancePtr , LoopbackSpeed ) ; Status = XAxiEthernet_SetOperatingSpeed ( AxiEthernetInstancePtr , ( u16 ) LoopbackSpeed ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } AxiEthernetUtilPhyDelay ( 2 ) ; Status = AxiEthernetSetupIntrSystem ( IntcInstancePtr , AxiEthernetInstancePtr , DmaInstancePtr , AxiEthernetIntrId , DmaRxIntrId , DmaTxIntrId ) ; Status = AxiEthernetSgDmaIntrSingleFrameExample ( AxiEthernetInstancePtr , DmaInstancePtr ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } Status = AxiEthernetSgDmaIntrCoalescingExample ( AxiEthernetInstancePtr , DmaInstancePtr ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } if ( XAxiEthernet_IsRxPartialCsum ( AxiEthernetInstancePtr ) && XAxiEthernet_IsTxPartialCsum ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsTxVlanTran ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsTxVlanStrp ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsTxVlanTag ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsRxVlanTran ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsRxVlanStrp ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsRxVlanTag ( AxiEthernetInstancePtr ) ) { Status = AxiEthernetSgDmaPartialChecksumOffloadExample ( AxiEthernetInstancePtr , DmaInstancePtr ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } } if ( XAxiEthernet_IsRxFullCsum ( AxiEthernetInstancePtr ) && XAxiEthernet_IsTxFullCsum ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsTxVlanTran ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsTxVlanStrp ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsTxVlanTag ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsRxVlanTran ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsRxVlanStrp ( AxiEthernetInstancePtr ) && ! XAxiEthernet_IsRxVlanTag ( AxiEthernetInstancePtr ) ) { Status = AxiEthernetSgDmaFullChecksumOffloadExample ( AxiEthernetInstancePtr , DmaInstancePtr ) ; if ( Status != XST_SUCCESS ) { return XST_FAILURE ; } } AxiEthernetDisableIntrSystem ( IntcInstancePtr , AxiEthernetIntrId , DmaRxIntrId , DmaTxIntrId ) ; XAxiEthernet_Stop ( AxiEthernetInstancePtr ) ; return XST_SUCCESS ; }
This function demonstrates the usage usage of the Axi Ethernet by sending
and receiving frames in interrupt driven SGDMA mode.
This function demonstrates the usage usage of the Axi Ethernet by sending and receiving frames in interrupt driven SGDMA mode .
/*************************************/ /* Setup device for first-time usage */ /*************************************/ /*
	 *  Get the configuration of AxiEthernet hardware.
	 */ /*
	 * Check whether DMA is present or not
	 */ /*
	 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
	 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
	 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
	 * would ensure a reset of AxiEthernet.
	 */ /*
	 * Initialize AxiEthernet hardware.
	 */ /*
	 * Set the MAC address
	 */ /*
	 * Setup RxBD space.
	 *
	 * We have already defined a properly aligned area of memory to store
	 * RxBDs at the beginning of this source code file so just pass its
	 * address into the function. No MMU is being used so the physical and
	 * virtual addresses are the same.
	 *
	 * Setup a BD template for the Rx channel. This template will be
	 * copied to every RxBD. We will not have to explicitly set these
	 * again.
	 */ /*
	 * Disable all RX interrupts before RxBD space setup
	 */ /*
	 * Create the RxBD ring
	 */ /*
	 * Setup TxBD space.
	 *
	 * Like RxBD space, we have already defined a properly aligned area of
	 * memory to use.
	 */ /*
	 * Create the TxBD ring
	 */ /*
	 * We reuse the bd template, as the same one will work for both rx
	 * and tx.
	 */ /*
	 * Set PHY to loopback, speed depends on phy type.
	 * MII is 100 and all others are 1000.
	 */ /*
	 * Set PHY<-->MAC data clock
	 */ /*
	 * Setting the operating speed of the MAC needs a delay.  There
	 * doesn't seem to be register to poll, so please consider this
	 * during your application design.
	 */ /*
	 * Connect to the interrupt controller and enable interrupts
	 */ /****************************/ /* Run through the examples */ /****************************/ /*
	 * Run the AxiEthernet DMA Single Frame Interrupt example
	 */ /*
	 * Run the Axi Ethernet DMA Interrupt Coalescing example
	 */ /*
	 * Tx/Rx Partial checksum offload will be disabled when any of
	 * Tx/Rx VLAN features are built in hardware.
	 */ /*
	 * Tx/Rx Full checksum offload will be disabled when any of
	 * Tx/Rx VLAN features are built in hardware.
	 */ /*
	 * Disable the interrupts for the Axi Ethernet device
	 */ /*
	 * Stop the device
	 */