XilinxProcessorIPLib/drivers/v_hdmiphy1/src/xhdmiphy1_gtye4.c
u32 XHdmiphy1_CfgCpllCalPeriodandTol(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir,
        u32 FreeRunClkFreq)
{
    u64 CpllCalPeriod;
    u64 CpllCalTolerance;
    u64 PllVcoFreqHz;
    u32 RegVal;

    /* Check if ChID is not a GT Channel */
    if (!XHDMIPHY1_ISCH(ChId)) {
        return XST_FAILURE;
    }

    PllVcoFreqHz = XHdmiphy1_GetPllVcoFreqHz(InstancePtr, QuadId, ChId, Dir);
    CpllCalPeriod = PllVcoFreqHz * 200 / (u64)FreeRunClkFreq;
    if (CpllCalPeriod % 10) {
        CpllCalTolerance = (CpllCalPeriod / 10) + 1;
    }
    else {
        CpllCalTolerance = CpllCalPeriod / 10;
    }

    /* Read CPLL Calibration Period Value */
    RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
              XHDMIPHY1_CPLL_CAL_PERIOD_REG) & ~XHDMIPHY1_CPLL_CAL_PERIOD_MASK;
    RegVal |= CpllCalPeriod & XHDMIPHY1_CPLL_CAL_PERIOD_MASK;
    /* Write new CPLL Calibration Period Value */
    XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr,
                    XHDMIPHY1_CPLL_CAL_PERIOD_REG, RegVal);

    /* Read CPLL Calibration Tolerance Value */
    RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
                XHDMIPHY1_CPLL_CAL_TOL_REG) & ~XHDMIPHY1_CPLL_CAL_TOL_MASK;
    RegVal |= CpllCalTolerance & XHDMIPHY1_CPLL_CAL_TOL_MASK;
    /* Write new CPLL Calibration Tolerance Value */
    XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr,
                    XHDMIPHY1_CPLL_CAL_TOL_REG, RegVal);

    return XST_SUCCESS;
}
/*****************************************************************************/
/**
* This function configures the CPLL Calibration period and the count tolerance
* registers.
*
* CpllCalPeriod    = ((fPLLClkin * N1 * N2) / (20 * M)) /
*                       (16000 / (4 * fFreeRunClk))
* CpllCalTolerance = CpllCalPeriod * 0.10
*
* @param    InstancePtr is a pointer to the XHdmiphy1 core instance.
* @param    QuadId is the GT quad ID to operate on.
* @param    Dir is an indicator for TX or RX.
* @param    FreeRunClkFreq is the freerunning clock freq in Hz
*            driving the GT Wiz instance
*
* @return   XST_SUCCESS / XST_FAILURE
*
* @note     None.
*
******************************************************************************/
This function configures the CPLL Calibration period and the count tolerance
registers.


This function configures the CPLL Calibration period and the count tolerance registers .
u32 XHdmiphy1_CfgCpllCalPeriodandTol(XHdmiphy1 *InstancePtr, u8 QuadId,
        XHdmiphy1_ChannelId ChId, XHdmiphy1_DirectionType Dir,
        u32 FreeRunClkFreq)
{
    u64 CpllCalPeriod;
    u64 CpllCalTolerance;
    u64 PllVcoFreqHz;
    u32 RegVal;
    if (!XHDMIPHY1_ISCH(ChId)) {
        return XST_FAILURE;
    }
    PllVcoFreqHz = XHdmiphy1_GetPllVcoFreqHz(InstancePtr, QuadId, ChId, Dir);
    CpllCalPeriod = PllVcoFreqHz * 200 / (u64)FreeRunClkFreq;
    if (CpllCalPeriod % 10) {
        CpllCalTolerance = (CpllCalPeriod / 10) + 1;
    }
    else {
        CpllCalTolerance = CpllCalPeriod / 10;
    }
    RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
              XHDMIPHY1_CPLL_CAL_PERIOD_REG) & ~XHDMIPHY1_CPLL_CAL_PERIOD_MASK;
    RegVal |= CpllCalPeriod & XHDMIPHY1_CPLL_CAL_PERIOD_MASK;
    XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr,
                    XHDMIPHY1_CPLL_CAL_PERIOD_REG, RegVal);
    RegVal = XHdmiphy1_ReadReg(InstancePtr->Config.BaseAddr,
                XHDMIPHY1_CPLL_CAL_TOL_REG) & ~XHDMIPHY1_CPLL_CAL_TOL_MASK;
    RegVal |= CpllCalTolerance & XHDMIPHY1_CPLL_CAL_TOL_MASK;
    XHdmiphy1_WriteReg(InstancePtr->Config.BaseAddr,
                    XHDMIPHY1_CPLL_CAL_TOL_REG, RegVal);
    return XST_SUCCESS;
}
u32 XHdmiphy1_CfgCpllCalPeriodandTol ( XHdmiphy1 * InstancePtr , u8 QuadId , XHdmiphy1_ChannelId ChId , XHdmiphy1_DirectionType Dir , u32 FreeRunClkFreq ) { u64 CpllCalPeriod ; u64 CpllCalTolerance ; u64 PllVcoFreqHz ; u32 RegVal ; if ( ! XHDMIPHY1_ISCH ( ChId ) ) { return XST_FAILURE ; } PllVcoFreqHz = XHdmiphy1_GetPllVcoFreqHz ( InstancePtr , QuadId , ChId , Dir ) ; CpllCalPeriod = PllVcoFreqHz * 200 / ( u64 ) FreeRunClkFreq ; if ( CpllCalPeriod % 10 ) { CpllCalTolerance = ( CpllCalPeriod / 10 ) + 1 ; } else { CpllCalTolerance = CpllCalPeriod / 10 ; } RegVal = XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_CPLL_CAL_PERIOD_REG ) & ~ XHDMIPHY1_CPLL_CAL_PERIOD_MASK ; RegVal |= CpllCalPeriod & XHDMIPHY1_CPLL_CAL_PERIOD_MASK ; XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_CPLL_CAL_PERIOD_REG , RegVal ) ; RegVal = XHdmiphy1_ReadReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_CPLL_CAL_TOL_REG ) & ~ XHDMIPHY1_CPLL_CAL_TOL_MASK ; RegVal |= CpllCalTolerance & XHDMIPHY1_CPLL_CAL_TOL_MASK ; XHdmiphy1_WriteReg ( InstancePtr -> Config . BaseAddr , XHDMIPHY1_CPLL_CAL_TOL_REG , RegVal ) ; return XST_SUCCESS ; }
This function configures the CPLL Calibration period and the count tolerance
registers.
This function configures the CPLL Calibration period and the count tolerance registers .
/* Check if ChID is not a GT Channel */ /* Read CPLL Calibration Period Value */ /* Write new CPLL Calibration Period Value */ /* Read CPLL Calibration Tolerance Value */ /* Write new CPLL Calibration Tolerance Value */