XilinxProcessorIPLib/drivers/sysmonpsu/src/xsysmonpsu.c
void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
		u32 SysmonBlk)
{
	u32 RegValue;
	UINTPTR EffectiveBaseAddress;

	/* Assert the arguments. */
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertVoid(AlmEnableMask <=
			(XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK |
			((u32)XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK << XSM_CFG_ALARM_SHIFT)));
	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));

	/* Calculate the effective baseaddress based on the Sysmon instance. */
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);

	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
					XSYSMONPSU_CFG_REG1_OFFSET);
	RegValue &= ~((u32)XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
	RegValue |= (~AlmEnableMask & (u32)XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);

	/*
	 * Enable/disables the alarm enables for the specified alarm bits in the
	 * Configuration Register 1.
	 */
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG1_OFFSET,
			 RegValue);
	/* Upper 16 bits of AlmEnableMask are valid only for PS */
	if (SysmonBlk == XSYSMON_PS) {
		RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
					XSYSMONPSU_CFG_REG3_OFFSET);
		RegValue &= ~((u32)XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
		RegValue |= (~(AlmEnableMask >> XSM_CFG_ALARM_SHIFT) &
				(u32)XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
		XSysmonPsu_WriteReg(EffectiveBaseAddress +
			XSYSMONPSU_CFG_REG3_OFFSET, RegValue);
	}
}
/****************************************************************************/
/**
*
* This function enables the alarm outputs for the specified alarms in the
* Configuration Registers 1:
*
*		- OT for Over Temperature (XSYSMONPSU_CFR_REG1_ALRM_OT_MASK)
*		- ALM0 for On board Temperature (XSYSMONPSU_CFR_REG1_ALRM_TEMP_MASK)
*		- ALM1 for SUPPLY1 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY1_MASK)
*		- ALM2 for SUPPLY2 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY2_MASK)
* 		- ALM3 for SUPPLY3 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY3_MASK)
* 		- ALM4 for SUPPLY4 (XSYSMONPSU_CFR_REG1_ALRM__SUPPLY4_MASK)
*		- ALM5 for SUPPLY5 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY5_MASK)
* 		- ALM6 for SUPPLY6 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY6_MASK)
*
* @param	InstancePtr is a pointer to the XSysMonPsu instance.
* @param	AlmEnableMask is the bit-mask of the alarm outputs to be enabled
*		in the Configuration Registers 1 and 3.
*		Bit positions of 1 will be enabled. Bit positions of 0 will be
*		disabled. This mask is formed by OR'ing XSYSMONPSU_CFR_REG1_ALRM_*_MASK
*		masks defined in xsysmonpsu.h, but XSM_CFR_ALM_SUPPLY8_MASK to
*		XSM_CFR_ALM_SUPPLY13_MASK are applicable only for PS.
* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
*       block or PL Sysmon block register region.
*
* @return	None.
*
* @note		The implementation of the alarm enables in the Configuration
*		register 1 is such that the alarms for bit positions of 0 will
*		be enabled and alarms for bit positions of 1 will be disabled.
*		The alarm outputs specified by the AlmEnableMask are negated
*		before writing to the Configuration Register 1 because it
*		was Disable register bits.
*		Upper 16 bits of AlmEnableMask are applicable only for PS.
*
*****************************************************************************/
This function enables the alarm outputs for the specified alarms in the
Configuration Registers 1.


This function enables the alarm outputs for the specified alarms in the Configuration Registers 1 .
void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
		u32 SysmonBlk)
{
	u32 RegValue;
	UINTPTR EffectiveBaseAddress;
	Xil_AssertVoid(InstancePtr != NULL);
	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	Xil_AssertVoid(AlmEnableMask <=
			(XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK |
			((u32)XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK << XSM_CFG_ALARM_SHIFT)));
	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
	EffectiveBaseAddress =
			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
					SysmonBlk);
	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
					XSYSMONPSU_CFG_REG1_OFFSET);
	RegValue &= ~((u32)XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
	RegValue |= (~AlmEnableMask & (u32)XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG1_OFFSET,
			 RegValue);
	if (SysmonBlk == XSYSMON_PS) {
		RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
					XSYSMONPSU_CFG_REG3_OFFSET);
		RegValue &= ~((u32)XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
		RegValue |= (~(AlmEnableMask >> XSM_CFG_ALARM_SHIFT) &
				(u32)XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
		XSysmonPsu_WriteReg(EffectiveBaseAddress +
			XSYSMONPSU_CFG_REG3_OFFSET, RegValue);
	}
}
void XSysMonPsu_SetAlarmEnables ( XSysMonPsu * InstancePtr , u32 AlmEnableMask , u32 SysmonBlk ) { u32 RegValue ; UINTPTR EffectiveBaseAddress ; Xil_AssertVoid ( InstancePtr != NULL ) ; Xil_AssertVoid ( InstancePtr -> IsReady == XIL_COMPONENT_IS_READY ) ; Xil_AssertVoid ( AlmEnableMask <= ( XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK | ( ( u32 ) XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK << XSM_CFG_ALARM_SHIFT ) ) ) ; Xil_AssertVoid ( ( SysmonBlk == XSYSMON_PS ) || ( SysmonBlk == XSYSMON_PL ) ) ; EffectiveBaseAddress = XSysMonPsu_GetEffBaseAddress ( InstancePtr -> Config . BaseAddress , SysmonBlk ) ; RegValue = XSysmonPsu_ReadReg ( EffectiveBaseAddress + XSYSMONPSU_CFG_REG1_OFFSET ) ; RegValue &= ~ ( ( u32 ) XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK ) ; RegValue |= ( ~ AlmEnableMask & ( u32 ) XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK ) ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_CFG_REG1_OFFSET , RegValue ) ; if ( SysmonBlk == XSYSMON_PS ) { RegValue = XSysmonPsu_ReadReg ( EffectiveBaseAddress + XSYSMONPSU_CFG_REG3_OFFSET ) ; RegValue &= ~ ( ( u32 ) XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK ) ; RegValue |= ( ~ ( AlmEnableMask >> XSM_CFG_ALARM_SHIFT ) & ( u32 ) XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK ) ; XSysmonPsu_WriteReg ( EffectiveBaseAddress + XSYSMONPSU_CFG_REG3_OFFSET , RegValue ) ; } }
This function enables the alarm outputs for the specified alarms in the
Configuration Registers 1:
This function enables the alarm outputs for the specified alarms in the Configuration Registers 1 :
/* Assert the arguments. */ /* Calculate the effective baseaddress based on the Sysmon instance. */ /*
	 * Enable/disables the alarm enables for the specified alarm bits in the
	 * Configuration Register 1.
	 */ /* Upper 16 bits of AlmEnableMask are valid only for PS */