XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe4.c
u32 XVphy_Gthe4TxChReconfig(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
{
	XVphy_Channel *ChPtr;
	u32 ReturnVal;
	u16 DrpVal;
	u16 WriteVal;
	XVphy_ChannelId ChIdPll;
	XVphy_PllType PllType;
	u32 PllxVcoRateMHz;
	u32 PllxClkOutMHz;
	u32 PllxClkOutDiv;
    u32 Status = XST_SUCCESS;

	ReturnVal = XVphy_Gthe4TxPllRefClkDiv1Reconfig(InstancePtr, QuadId, ChId);
	if (!XVphy_IsHDMI(InstancePtr, XVPHY_DIR_TX)) {
		return ReturnVal;
	}

	/* Determine PLL type. */
	PllType = XVphy_GetPllType(InstancePtr, QuadId, XVPHY_DIR_TX, ChId);
	/* Determine which channel(s) to operate on. */
	switch (PllType) {
		case XVPHY_PLL_TYPE_QPLL:
		case XVPHY_PLL_TYPE_QPLL0:
		case XVPHY_PLL_TYPE_PLL0:
			ChIdPll = XVPHY_CHANNEL_ID_CMN0;
			PllxClkOutDiv = 2;
			break;
		case XVPHY_PLL_TYPE_QPLL1:
		case XVPHY_PLL_TYPE_PLL1:
			ChIdPll = XVPHY_CHANNEL_ID_CMN1;
			PllxClkOutDiv = 2;
			break;
		default:
			ChIdPll = ChId;
			PllxClkOutDiv = 1;
			break;
	}

	if (XVphy_IsHDMI(InstancePtr, XVPHY_DIR_TX)) {

		ChPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(ChId)];
		/* TX_INT_DATAWIDTH */
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x85, &DrpVal);
		DrpVal &= ~(0x3 << 10);
		WriteVal = ((Xvphy_DrpEncodeIntDataWidth(ChPtr->
						TxIntDataWidth) & 0x3) << 10);
		DrpVal |= WriteVal;
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x85, DrpVal);

		/* TX_DATA_WIDTH */
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x7A, &DrpVal);
		DrpVal &= ~(0xF);
		WriteVal = (Xvphy_DrpEncodeDataWidth(ChPtr->TxDataWidth) & 0xF);
		DrpVal |= WriteVal;
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x7A, DrpVal);

		PllxVcoRateMHz = XVphy_GetPllVcoFreqHz(InstancePtr, QuadId, ChIdPll,
				XVPHY_DIR_TX) / 1000000;
		PllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv;

		/* TXPI_CFG */
		if (PllxClkOutMHz >= 5500) {
			DrpVal = 0x0000;
		}
		else if (PllxClkOutMHz >= 3500) {
			DrpVal = 0x0054;
		}
		else {
			DrpVal = 0x03DF;
		}
		/* Write new DRP register value for TXPI_CFG. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xFF, DrpVal);

		/* TXPI_CFG3 */
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x9C, &DrpVal);
		DrpVal &= ~(0x0040);
		if (PllxClkOutMHz < 7500 && PllxClkOutMHz >= 5500) {
			DrpVal |= 1 << 6;
		}
		/* Write new DRP register value for TXPI_CFG3. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x9C, DrpVal);

		/* TX_PI_BIASSET */
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0xFB, &DrpVal);
		DrpVal &= ~(0x0006);
		if (PllxClkOutMHz >= 7500) {
			DrpVal |= 3 << 1;
		}
		else if (PllxClkOutMHz >= 5500) {
			DrpVal |= 2 << 1;
		}
		else if (PllxClkOutMHz >= 3500) {
			DrpVal |= 1 << 1;
		}
		/* Write new DRP register value for TX_PI_BIASSET. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xFB, DrpVal);

		/* CH_HSPMUX_TX */
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x116, &DrpVal);
		DrpVal &= ~(0xFF00);
		if (PllxClkOutMHz >= 7500) {
			DrpVal |= 0x68 << 8;
		}
		else if (PllxClkOutMHz >= 5500) {
			DrpVal |= 0x44 << 8;
		}
		else if (PllxClkOutMHz >= 3500) {
			DrpVal |= 0x24 << 8;
		}
		else {
			DrpVal |= 0x3C << 8;
		}
		/* Write new DRP register value for CH_HSPMUX_TX. */
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x116, DrpVal);
	}
	return Status;
}
/*****************************************************************************/
/**
* This function will configure the channel's TX settings.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
*
* @return
*		- XST_SUCCESS if the configuration was successful.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function will configure the channel's TX settings.
This function will configure the channel ' s TX settings .
u32 XVphy_Gthe4TxChReconfig(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
{
	XVphy_Channel *ChPtr;
	u32 ReturnVal;
	u16 DrpVal;
	u16 WriteVal;
	XVphy_ChannelId ChIdPll;
	XVphy_PllType PllType;
	u32 PllxVcoRateMHz;
	u32 PllxClkOutMHz;
	u32 PllxClkOutDiv;
    u32 Status = XST_SUCCESS;
	ReturnVal = XVphy_Gthe4TxPllRefClkDiv1Reconfig(InstancePtr, QuadId, ChId);
	if (!XVphy_IsHDMI(InstancePtr, XVPHY_DIR_TX)) {
		return ReturnVal;
	}
	PllType = XVphy_GetPllType(InstancePtr, QuadId, XVPHY_DIR_TX, ChId);
	switch (PllType) {
		case XVPHY_PLL_TYPE_QPLL:
		case XVPHY_PLL_TYPE_QPLL0:
		case XVPHY_PLL_TYPE_PLL0:
			ChIdPll = XVPHY_CHANNEL_ID_CMN0;
			PllxClkOutDiv = 2;
			break;
		case XVPHY_PLL_TYPE_QPLL1:
		case XVPHY_PLL_TYPE_PLL1:
			ChIdPll = XVPHY_CHANNEL_ID_CMN1;
			PllxClkOutDiv = 2;
			break;
		default:
			ChIdPll = ChId;
			PllxClkOutDiv = 1;
			break;
	}
	if (XVphy_IsHDMI(InstancePtr, XVPHY_DIR_TX)) {
		ChPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(ChId)];
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x85, &DrpVal);
		DrpVal &= ~(0x3 << 10);
		WriteVal = ((Xvphy_DrpEncodeIntDataWidth(ChPtr->
						TxIntDataWidth) & 0x3) << 10);
		DrpVal |= WriteVal;
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x85, DrpVal);
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x7A, &DrpVal);
		DrpVal &= ~(0xF);
		WriteVal = (Xvphy_DrpEncodeDataWidth(ChPtr->TxDataWidth) & 0xF);
		DrpVal |= WriteVal;
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x7A, DrpVal);
		PllxVcoRateMHz = XVphy_GetPllVcoFreqHz(InstancePtr, QuadId, ChIdPll,
				XVPHY_DIR_TX) / 1000000;
		PllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv;
		if (PllxClkOutMHz >= 5500) {
			DrpVal = 0x0000;
		}
		else if (PllxClkOutMHz >= 3500) {
			DrpVal = 0x0054;
		}
		else {
			DrpVal = 0x03DF;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xFF, DrpVal);
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x9C, &DrpVal);
		DrpVal &= ~(0x0040);
		if (PllxClkOutMHz < 7500 && PllxClkOutMHz >= 5500) {
			DrpVal |= 1 << 6;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x9C, DrpVal);
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0xFB, &DrpVal);
		DrpVal &= ~(0x0006);
		if (PllxClkOutMHz >= 7500) {
			DrpVal |= 3 << 1;
		}
		else if (PllxClkOutMHz >= 5500) {
			DrpVal |= 2 << 1;
		}
		else if (PllxClkOutMHz >= 3500) {
			DrpVal |= 1 << 1;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0xFB, DrpVal);
		Status |= XVphy_DrpRd(InstancePtr, QuadId, ChId, 0x116, &DrpVal);
		DrpVal &= ~(0xFF00);
		if (PllxClkOutMHz >= 7500) {
			DrpVal |= 0x68 << 8;
		}
		else if (PllxClkOutMHz >= 5500) {
			DrpVal |= 0x44 << 8;
		}
		else if (PllxClkOutMHz >= 3500) {
			DrpVal |= 0x24 << 8;
		}
		else {
			DrpVal |= 0x3C << 8;
		}
		Status |= XVphy_DrpWr(InstancePtr, QuadId, ChId, 0x116, DrpVal);
	}
	return Status;
}
u32 XVphy_Gthe4TxChReconfig ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId ChId ) { XVphy_Channel * ChPtr ; u32 ReturnVal ; u16 DrpVal ; u16 WriteVal ; XVphy_ChannelId ChIdPll ; XVphy_PllType PllType ; u32 PllxVcoRateMHz ; u32 PllxClkOutMHz ; u32 PllxClkOutDiv ; u32 Status = XST_SUCCESS ; ReturnVal = XVphy_Gthe4TxPllRefClkDiv1Reconfig ( InstancePtr , QuadId , ChId ) ; if ( ! XVphy_IsHDMI ( InstancePtr , XVPHY_DIR_TX ) ) { return ReturnVal ; } PllType = XVphy_GetPllType ( InstancePtr , QuadId , XVPHY_DIR_TX , ChId ) ; switch ( PllType ) { case XVPHY_PLL_TYPE_QPLL : case XVPHY_PLL_TYPE_QPLL0 : case XVPHY_PLL_TYPE_PLL0 : ChIdPll = XVPHY_CHANNEL_ID_CMN0 ; PllxClkOutDiv = 2 ; break ; case XVPHY_PLL_TYPE_QPLL1 : case XVPHY_PLL_TYPE_PLL1 : ChIdPll = XVPHY_CHANNEL_ID_CMN1 ; PllxClkOutDiv = 2 ; break ; default : ChIdPll = ChId ; PllxClkOutDiv = 1 ; break ; } if ( XVphy_IsHDMI ( InstancePtr , XVPHY_DIR_TX ) ) { ChPtr = & InstancePtr -> Quads [ QuadId ] . Plls [ XVPHY_CH2IDX ( ChId ) ] ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0x85 , & DrpVal ) ; DrpVal &= ~ ( 0x3 << 10 ) ; WriteVal = ( ( Xvphy_DrpEncodeIntDataWidth ( ChPtr -> TxIntDataWidth ) & 0x3 ) << 10 ) ; DrpVal |= WriteVal ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x85 , DrpVal ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0x7A , & DrpVal ) ; DrpVal &= ~ ( 0xF ) ; WriteVal = ( Xvphy_DrpEncodeDataWidth ( ChPtr -> TxDataWidth ) & 0xF ) ; DrpVal |= WriteVal ; Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x7A , DrpVal ) ; PllxVcoRateMHz = XVphy_GetPllVcoFreqHz ( InstancePtr , QuadId , ChIdPll , XVPHY_DIR_TX ) / 1000000 ; PllxClkOutMHz = PllxVcoRateMHz / PllxClkOutDiv ; if ( PllxClkOutMHz >= 5500 ) { DrpVal = 0x0000 ; } else if ( PllxClkOutMHz >= 3500 ) { DrpVal = 0x0054 ; } else { DrpVal = 0x03DF ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0xFF , DrpVal ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0x9C , & DrpVal ) ; DrpVal &= ~ ( 0x0040 ) ; if ( PllxClkOutMHz < 7500 && PllxClkOutMHz >= 5500 ) { DrpVal |= 1 << 6 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x9C , DrpVal ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0xFB , & DrpVal ) ; DrpVal &= ~ ( 0x0006 ) ; if ( PllxClkOutMHz >= 7500 ) { DrpVal |= 3 << 1 ; } else if ( PllxClkOutMHz >= 5500 ) { DrpVal |= 2 << 1 ; } else if ( PllxClkOutMHz >= 3500 ) { DrpVal |= 1 << 1 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0xFB , DrpVal ) ; Status |= XVphy_DrpRd ( InstancePtr , QuadId , ChId , 0x116 , & DrpVal ) ; DrpVal &= ~ ( 0xFF00 ) ; if ( PllxClkOutMHz >= 7500 ) { DrpVal |= 0x68 << 8 ; } else if ( PllxClkOutMHz >= 5500 ) { DrpVal |= 0x44 << 8 ; } else if ( PllxClkOutMHz >= 3500 ) { DrpVal |= 0x24 << 8 ; } else { DrpVal |= 0x3C << 8 ; } Status |= XVphy_DrpWr ( InstancePtr , QuadId , ChId , 0x116 , DrpVal ) ; } return Status ; }
This function will configure the channel's TX settings.
This function will configure the channel ' s TX settings .
/* Determine PLL type. */ /* Determine which channel(s) to operate on. */ /* TX_INT_DATAWIDTH */ /* TX_DATA_WIDTH */ /* TXPI_CFG */ /* Write new DRP register value for TXPI_CFG. */ /* TXPI_CFG3 */ /* Write new DRP register value for TXPI_CFG3. */ /* TX_PI_BIASSET */ /* Write new DRP register value for TX_PI_BIASSET. */ /* CH_HSPMUX_TX */ /* Write new DRP register value for CH_HSPMUX_TX. */