XilinxProcessorIPLib/drivers/v_sdirxss/examples/xuhdsdi_example/xuhdsdi_example.c
void XSdiEnableAESAudioPlayback(XSdiAud_SampRate SampleRate)
{
	XSdiVid_TransMode RxTransMode;
	u8 IsFractional;

	/* Enable SDI Audio Extract to SPDIF TX path */
	Xil_Out32((UINTPTR)(AXIS_SWITCH_RX + 0x40), (u32)(0x0));
	Xil_Out32((UINTPTR)(AXIS_SWITCH_RX + 0x44), (u32)(0x80000000));
	Xil_Out32((UINTPTR)(AXIS_SWITCH_RX), (u32)(0x2));

	/* Configure ACR to generate FS rate clock */
	RxTransMode =  XV_SdiRxSs_GetTransportMode(&SdiRxSs);
	IsFractional = XV_SdiRxSs_GetTransportBitRate(&SdiRxSs);
	ConfigNandCTS(IsFractional, RxTransMode, SampleRate);

	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x30), (u32)(0x00000100));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x34), (u32)(0x0000003C));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x38), (u32)(0x00000014));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x3C), (u32)(0x00000C00));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x40), (u32)(0x00000006));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x20), (u32)(0x00000001));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x70), (u32)(0x00000020));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x8),  (u32)(0x00000001));

	/* Wait for clock generated by ACR to be stable */
	sleep(1);

	/* Program SI5319 to generate FS*512 clock (AES TX Clock) */
	if (SampleRate == XSDIAUD_SMPLRATE_48) {
		I2cClk_SI5319(48000, 48000*512);
	} else if (SampleRate == XSDIAUD_SMPLRATE_44) {
		I2cClk_SI5319(44100, 44100*512);
	} else if (SampleRate == XSDIAUD_SMPLRATE_32) {
		I2cClk_SI5319(32000, 32000*512);
	}

	/* Wait for SI5319 to Lock */
	sleep(1);

	/* Enable SPDIF TX */
	XSpdif_ResetFifo(&SpdifTx);
	XSpdif_SetClkConfig(&SpdifTx, XSPDIF_CLK_8);
	XSpdif_Enable(&SpdifTx, TRUE);

	/* Enable 2-Channel SDI Audio Extract */
	XSdiAud_SetCh(&SdiExtract, 0x3);
	XSdiAud_Enable(&SdiExtract, 1);

	/* Enable loop control in ACR after the whole pipe is up & running */
	sleep(1);
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x20), (u32)(0x00000005));
}
/*****************************************************************************/
/**
 *
 * This function enables the AES Audio Playback Path (Audio extracted from SDI RX
 *  is played back on SPDIF TX)
 *
 * @return	None.
 *
 * @note	None.
 *
 ******************************************************************************/
This function enables the AES Audio Playback Path (Audio extracted from SDI RX
is played back on SPDIF TX)

@return      None.

@note        None.
This function enables the AES Audio Playback Path ( Audio extracted from SDI RX is played back on SPDIF TX ) @return None . @note None .
void XSdiEnableAESAudioPlayback(XSdiAud_SampRate SampleRate)
{
	XSdiVid_TransMode RxTransMode;
	u8 IsFractional;
	Xil_Out32((UINTPTR)(AXIS_SWITCH_RX + 0x40), (u32)(0x0));
	Xil_Out32((UINTPTR)(AXIS_SWITCH_RX + 0x44), (u32)(0x80000000));
	Xil_Out32((UINTPTR)(AXIS_SWITCH_RX), (u32)(0x2));
	RxTransMode =  XV_SdiRxSs_GetTransportMode(&SdiRxSs);
	IsFractional = XV_SdiRxSs_GetTransportBitRate(&SdiRxSs);
	ConfigNandCTS(IsFractional, RxTransMode, SampleRate);
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x30), (u32)(0x00000100));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x34), (u32)(0x0000003C));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x38), (u32)(0x00000014));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x3C), (u32)(0x00000C00));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x40), (u32)(0x00000006));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x20), (u32)(0x00000001));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x70), (u32)(0x00000020));
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x8),  (u32)(0x00000001));
	sleep(1);
	if (SampleRate == XSDIAUD_SMPLRATE_48) {
		I2cClk_SI5319(48000, 48000*512);
	} else if (SampleRate == XSDIAUD_SMPLRATE_44) {
		I2cClk_SI5319(44100, 44100*512);
	} else if (SampleRate == XSDIAUD_SMPLRATE_32) {
		I2cClk_SI5319(32000, 32000*512);
	}
	sleep(1);
	XSpdif_ResetFifo(&SpdifTx);
	XSpdif_SetClkConfig(&SpdifTx, XSPDIF_CLK_8);
	XSpdif_Enable(&SpdifTx, TRUE);
	XSdiAud_SetCh(&SdiExtract, 0x3);
	XSdiAud_Enable(&SdiExtract, 1);
	sleep(1);
	Xil_Out32((UINTPTR)(ACR_BASEADDR + 0x20), (u32)(0x00000005));
}
void XSdiEnableAESAudioPlayback ( XSdiAud_SampRate SampleRate ) { XSdiVid_TransMode RxTransMode ; u8 IsFractional ; Xil_Out32 ( ( UINTPTR ) ( AXIS_SWITCH_RX + 0x40 ) , ( u32 ) ( 0x0 ) ) ; Xil_Out32 ( ( UINTPTR ) ( AXIS_SWITCH_RX + 0x44 ) , ( u32 ) ( 0x80000000 ) ) ; Xil_Out32 ( ( UINTPTR ) ( AXIS_SWITCH_RX ) , ( u32 ) ( 0x2 ) ) ; RxTransMode = XV_SdiRxSs_GetTransportMode ( & SdiRxSs ) ; IsFractional = XV_SdiRxSs_GetTransportBitRate ( & SdiRxSs ) ; ConfigNandCTS ( IsFractional , RxTransMode , SampleRate ) ; Xil_Out32 ( ( UINTPTR ) ( ACR_BASEADDR + 0x30 ) , ( u32 ) ( 0x00000100 ) ) ; Xil_Out32 ( ( UINTPTR ) ( ACR_BASEADDR + 0x34 ) , ( u32 ) ( 0x0000003C ) ) ; Xil_Out32 ( ( UINTPTR ) ( ACR_BASEADDR + 0x38 ) , ( u32 ) ( 0x00000014 ) ) ; Xil_Out32 ( ( UINTPTR ) ( ACR_BASEADDR + 0x3C ) , ( u32 ) ( 0x00000C00 ) ) ; Xil_Out32 ( ( UINTPTR ) ( ACR_BASEADDR + 0x40 ) , ( u32 ) ( 0x00000006 ) ) ; Xil_Out32 ( ( UINTPTR ) ( ACR_BASEADDR + 0x20 ) , ( u32 ) ( 0x00000001 ) ) ; Xil_Out32 ( ( UINTPTR ) ( ACR_BASEADDR + 0x70 ) , ( u32 ) ( 0x00000020 ) ) ; Xil_Out32 ( ( UINTPTR ) ( ACR_BASEADDR + 0x8 ) , ( u32 ) ( 0x00000001 ) ) ; sleep ( 1 ) ; if ( SampleRate == XSDIAUD_SMPLRATE_48 ) { I2cClk_SI5319 ( 48000 , 48000 * 512 ) ; } else if ( SampleRate == XSDIAUD_SMPLRATE_44 ) { I2cClk_SI5319 ( 44100 , 44100 * 512 ) ; } else if ( SampleRate == XSDIAUD_SMPLRATE_32 ) { I2cClk_SI5319 ( 32000 , 32000 * 512 ) ; } sleep ( 1 ) ; XSpdif_ResetFifo ( & SpdifTx ) ; XSpdif_SetClkConfig ( & SpdifTx , XSPDIF_CLK_8 ) ; XSpdif_Enable ( & SpdifTx , TRUE ) ; XSdiAud_SetCh ( & SdiExtract , 0x3 ) ; XSdiAud_Enable ( & SdiExtract , 1 ) ; sleep ( 1 ) ; Xil_Out32 ( ( UINTPTR ) ( ACR_BASEADDR + 0x20 ) , ( u32 ) ( 0x00000005 ) ) ; }
This function enables the AES Audio Playback Path (Audio extracted from SDI RX
  is played back on SPDIF TX)
This function enables the AES Audio Playback Path ( Audio extracted from SDI RX is played back on SPDIF TX )
/* Enable SDI Audio Extract to SPDIF TX path */ /* Configure ACR to generate FS rate clock */ /* Wait for clock generated by ACR to be stable */ /* Program SI5319 to generate FS*512 clock (AES TX Clock) */ /* Wait for SI5319 to Lock */ /* Enable SPDIF TX */ /* Enable 2-Channel SDI Audio Extract */ /* Enable loop control in ACR after the whole pipe is up & running */