XilinxProcessorIPLib/drivers/intc/src/xintc.c
int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId)
{
	u8 Id;
	XIntc_Config *CfgPtr;
	u32 NextBitMask = 1;

	Xil_AssertNonvoid(InstancePtr != NULL);

	/*
	 * If the device is started, disallow the initialize and return a status
	 * indicating it is started.  This allows the user to stop the device
	 * and reinitialize, but prevents a user from inadvertently initializing
	 */
	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
		return XST_DEVICE_IS_STARTED;
	}

	/*
	 * Lookup the device configuration in the CROM table. Use this
	 * configuration info down below when initializing this component.
	 */
	CfgPtr = XIntc_LookupConfig(DeviceId);
	if (CfgPtr == NULL) {
		return XST_DEVICE_NOT_FOUND;
	}

	/*
	 * Set some default values
	 */
	InstancePtr->IsReady = 0;
	InstancePtr->IsStarted = 0;	/* not started */
	InstancePtr->CfgPtr = CfgPtr;

	InstancePtr->CfgPtr->Options = XIN_SVC_SGL_ISR_OPTION;
	InstancePtr->CfgPtr->IntcType = CfgPtr->IntcType;

	/*
	 * Save the base address pointer such that the registers of the
	 * interrupt can be accessed
	 */
#if (XPAR_XINTC_USE_DCR_BRIDGE != 0)
	InstancePtr->BaseAddress = ((CfgPtr->BaseAddress >> 2)) & 0xFFF;
#else
	InstancePtr->BaseAddress = CfgPtr->BaseAddress;
#endif

	/*
	 * Initialize all the data needed to perform interrupt processing for
	 * each interrupt ID up to the maximum used
	 */
	for (Id = 0; Id < (CfgPtr->NumberofIntrs + CfgPtr->NumberofSwIntrs) ; Id++) {

		/*
		 * Initialize the handler to point to a stub to handle an
		 * interrupt which has not been connected to a handler. Only
		 * initialize it if the handler is 0 or XNullHandler, which
		 * means it was not initialized statically by the tools/user.
		 * Set the callback reference to this instance so that
		 * unhandled interrupts can be tracked.
		 */
		if ((InstancePtr->CfgPtr->HandlerTable[Id].Handler == 0) ||
		    (InstancePtr->CfgPtr->HandlerTable[Id].Handler ==
		     XNullHandler)) {
			InstancePtr->CfgPtr->HandlerTable[Id].Handler =
				StubHandler;
		}
		InstancePtr->CfgPtr->HandlerTable[Id].CallBackRef = InstancePtr;

		/*
		 * Initialize the bit position mask table such that bit
		 * positions are lookups only for each interrupt id, with 0
		 * being a special case
		 * (XIntc_BitPosMask[] = { 1, 2, 4, 8, ... })
		 */
		XIntc_BitPosMask[Id] = NextBitMask;
		NextBitMask *= 2;
	}

	/*
	 * Disable IRQ output signal
	 * Disable all interrupt sources
	 * Acknowledge all sources
	 */
	XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, 0);
	XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET, 0);
	XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, 0xFFFFFFFF);

	/*
	 * If the fast Interrupt mode is enabled then set all the
	 * interrupts as normal mode.
	 */
	if(InstancePtr->CfgPtr->FastIntr == TRUE) {
		XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET, 0);

#ifdef XPAR_MICROBLAZE_BASE_VECTORS
		if (InstancePtr->CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			for (Id = 0; Id < 32 ; Id++) {
				XIntc_Out64(InstancePtr->BaseAddress + XIN_IVEAR_OFFSET
				+ (Id * 8), XPAR_MICROBLAZE_BASE_VECTORS
				+ 0x10);
			}
		} else {
			for (Id = 0; Id < 32 ; Id++) {
				XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
					+ (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS
					+ 0x10);
			}
		}
#else
		if (InstancePtr->CfgPtr->VectorAddrWidth >
			XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			for (Id = 0; Id < 32 ; Id++) {
				XIntc_Out64(InstancePtr->BaseAddress + XIN_IVEAR_OFFSET
				+ (Id * 8), 0x10);
			}
		} else {
			for (Id = 0; Id < 32 ; Id++) {
				XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
								+ (Id * 4), 0x10);
			}
		}
#endif
	}

	/* Initialize slaves in Cascade mode*/
	if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
		XIntc_InitializeSlaves(InstancePtr);
	}

	/*
	 * Indicate the instance is now ready to use, successfully initialized
	 */
	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;

	return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* Initialize a specific interrupt controller instance/driver. The
* initialization entails:
*
*	- Initialize fields of the XIntc structure
*	- Initial vector table with stub function calls
*	- All interrupt sources are disabled
*	- Interrupt output is disabled
*
* @param	InstancePtr is a pointer to the XIntc instance to be worked on.
* @param	DeviceId is the unique id of the device controlled by this XIntc
*		instance.  Passing in a device id associates the generic XIntc
*		instance to a specific device, as chosen by the caller or
*		application developer.
*
* @return
*		- XST_SUCCESS if initialization was successful
*		- XST_DEVICE_IS_STARTED if the device has already been started
*		- XST_DEVICE_NOT_FOUND if device configuration information was
*		not found for a device with the supplied device ID.
*
* @note		In Cascade mode this function calls XIntc_InitializeSlaves to
*	        initialize Slave Interrupt controllers.
*
******************************************************************************/
Initialize a specific interrupt controller instance/driver. The
initialization entails.

Initialize fields of the XIntc structure
Initial vector table with stub function calls
All interrupt sources are disabled
Interrupt output is disabled
Initialize a specific interrupt controller instance / driver . The initialization entails . Initialize fields of the XIntc structure Initial vector table with stub function calls All interrupt sources are disabled Interrupt output is disabled
int XIntc_Initialize(XIntc * InstancePtr, u16 DeviceId)
{
	u8 Id;
	XIntc_Config *CfgPtr;
	u32 NextBitMask = 1;
	Xil_AssertNonvoid(InstancePtr != NULL);
	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
		return XST_DEVICE_IS_STARTED;
	}
	CfgPtr = XIntc_LookupConfig(DeviceId);
	if (CfgPtr == NULL) {
		return XST_DEVICE_NOT_FOUND;
	}
	InstancePtr->IsReady = 0;
	InstancePtr->IsStarted = 0;	
	InstancePtr->CfgPtr = CfgPtr;
	InstancePtr->CfgPtr->Options = XIN_SVC_SGL_ISR_OPTION;
	InstancePtr->CfgPtr->IntcType = CfgPtr->IntcType;
#if (XPAR_XINTC_USE_DCR_BRIDGE != 0)
	InstancePtr->BaseAddress = ((CfgPtr->BaseAddress >> 2)) & 0xFFF;
#else
	InstancePtr->BaseAddress = CfgPtr->BaseAddress;
#endif
	for (Id = 0; Id < (CfgPtr->NumberofIntrs + CfgPtr->NumberofSwIntrs) ; Id++) {
		if ((InstancePtr->CfgPtr->HandlerTable[Id].Handler == 0) ||
		    (InstancePtr->CfgPtr->HandlerTable[Id].Handler ==
		     XNullHandler)) {
			InstancePtr->CfgPtr->HandlerTable[Id].Handler =
				StubHandler;
		}
		InstancePtr->CfgPtr->HandlerTable[Id].CallBackRef = InstancePtr;
		XIntc_BitPosMask[Id] = NextBitMask;
		NextBitMask *= 2;
	}
	XIntc_Out32(InstancePtr->BaseAddress + XIN_MER_OFFSET, 0);
	XIntc_Out32(InstancePtr->BaseAddress + XIN_IER_OFFSET, 0);
	XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, 0xFFFFFFFF);
	if(InstancePtr->CfgPtr->FastIntr == TRUE) {
		XIntc_Out32(InstancePtr->BaseAddress + XIN_IMR_OFFSET, 0);
#ifdef XPAR_MICROBLAZE_BASE_VECTORS
		if (InstancePtr->CfgPtr->VectorAddrWidth >
				XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			for (Id = 0; Id < 32 ; Id++) {
				XIntc_Out64(InstancePtr->BaseAddress + XIN_IVEAR_OFFSET
				+ (Id * 8), XPAR_MICROBLAZE_BASE_VECTORS
				+ 0x10);
			}
		} else {
			for (Id = 0; Id < 32 ; Id++) {
				XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
					+ (Id * 4), XPAR_MICROBLAZE_BASE_VECTORS
					+ 0x10);
			}
		}
#else
		if (InstancePtr->CfgPtr->VectorAddrWidth >
			XINTC_STANDARD_VECTOR_ADDRESS_WIDTH) {
			for (Id = 0; Id < 32 ; Id++) {
				XIntc_Out64(InstancePtr->BaseAddress + XIN_IVEAR_OFFSET
				+ (Id * 8), 0x10);
			}
		} else {
			for (Id = 0; Id < 32 ; Id++) {
				XIntc_Out32(InstancePtr->BaseAddress + XIN_IVAR_OFFSET
								+ (Id * 4), 0x10);
			}
		}
#endif
	}
	if (InstancePtr->CfgPtr->IntcType != XIN_INTC_NOCASCADE) {
		XIntc_InitializeSlaves(InstancePtr);
	}
	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
	return XST_SUCCESS;
}
int XIntc_Initialize ( XIntc * InstancePtr , u16 DeviceId ) { u8 Id ; XIntc_Config * CfgPtr ; u32 NextBitMask = 1 ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; if ( InstancePtr -> IsStarted == XIL_COMPONENT_IS_STARTED ) { return XST_DEVICE_IS_STARTED ; } CfgPtr = XIntc_LookupConfig ( DeviceId ) ; if ( CfgPtr == NULL ) { return XST_DEVICE_NOT_FOUND ; } InstancePtr -> IsReady = 0 ; InstancePtr -> IsStarted = 0 ; InstancePtr -> CfgPtr = CfgPtr ; InstancePtr -> CfgPtr -> Options = XIN_SVC_SGL_ISR_OPTION ; InstancePtr -> CfgPtr -> IntcType = CfgPtr -> IntcType ; #if ( XPAR_XINTC_USE_DCR_BRIDGE != 0 ) InstancePtr -> BaseAddress = ( ( CfgPtr -> BaseAddress >> 2 ) ) & 0xFFF ; #else InstancePtr -> BaseAddress = CfgPtr -> BaseAddress ; #endif for ( Id = 0 ; Id < ( CfgPtr -> NumberofIntrs + CfgPtr -> NumberofSwIntrs ) ; Id ++ ) { if ( ( InstancePtr -> CfgPtr -> HandlerTable [ Id ] . Handler == 0 ) || ( InstancePtr -> CfgPtr -> HandlerTable [ Id ] . Handler == XNullHandler ) ) { InstancePtr -> CfgPtr -> HandlerTable [ Id ] . Handler = StubHandler ; } InstancePtr -> CfgPtr -> HandlerTable [ Id ] . CallBackRef = InstancePtr ; XIntc_BitPosMask [ Id ] = NextBitMask ; NextBitMask *= 2 ; } XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_MER_OFFSET , 0 ) ; XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_IER_OFFSET , 0 ) ; XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_IAR_OFFSET , 0xFFFFFFFF ) ; if ( InstancePtr -> CfgPtr -> FastIntr == TRUE ) { XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_IMR_OFFSET , 0 ) ; #ifdef XPAR_MICROBLAZE_BASE_VECTORS if ( InstancePtr -> CfgPtr -> VectorAddrWidth > XINTC_STANDARD_VECTOR_ADDRESS_WIDTH ) { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out64 ( InstancePtr -> BaseAddress + XIN_IVEAR_OFFSET + ( Id * 8 ) , XPAR_MICROBLAZE_BASE_VECTORS + 0x10 ) ; } } else { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_IVAR_OFFSET + ( Id * 4 ) , XPAR_MICROBLAZE_BASE_VECTORS + 0x10 ) ; } } #else if ( InstancePtr -> CfgPtr -> VectorAddrWidth > XINTC_STANDARD_VECTOR_ADDRESS_WIDTH ) { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out64 ( InstancePtr -> BaseAddress + XIN_IVEAR_OFFSET + ( Id * 8 ) , 0x10 ) ; } } else { for ( Id = 0 ; Id < 32 ; Id ++ ) { XIntc_Out32 ( InstancePtr -> BaseAddress + XIN_IVAR_OFFSET + ( Id * 4 ) , 0x10 ) ; } } #endif } if ( InstancePtr -> CfgPtr -> IntcType != XIN_INTC_NOCASCADE ) { XIntc_InitializeSlaves ( InstancePtr ) ; } InstancePtr -> IsReady = XIL_COMPONENT_IS_READY ; return XST_SUCCESS ; }
Initialize a specific interrupt controller instance/driver.
Initialize a specific interrupt controller instance / driver .
/*
	 * If the device is started, disallow the initialize and return a status
	 * indicating it is started.  This allows the user to stop the device
	 * and reinitialize, but prevents a user from inadvertently initializing
	 */ /*
	 * Lookup the device configuration in the CROM table. Use this
	 * configuration info down below when initializing this component.
	 */ /*
	 * Set some default values
	 */ /* not started */ /*
	 * Save the base address pointer such that the registers of the
	 * interrupt can be accessed
	 */ /*
	 * Initialize all the data needed to perform interrupt processing for
	 * each interrupt ID up to the maximum used
	 */ /*
		 * Initialize the handler to point to a stub to handle an
		 * interrupt which has not been connected to a handler. Only
		 * initialize it if the handler is 0 or XNullHandler, which
		 * means it was not initialized statically by the tools/user.
		 * Set the callback reference to this instance so that
		 * unhandled interrupts can be tracked.
		 */ /*
		 * Initialize the bit position mask table such that bit
		 * positions are lookups only for each interrupt id, with 0
		 * being a special case
		 * (XIntc_BitPosMask[] = { 1, 2, 4, 8, ... })
		 */ /*
	 * Disable IRQ output signal
	 * Disable all interrupt sources
	 * Acknowledge all sources
	 */ /*
	 * If the fast Interrupt mode is enabled then set all the
	 * interrupts as normal mode.
	 */ /* Initialize slaves in Cascade mode*/ /*
	 * Indicate the instance is now ready to use, successfully initialized
	 */