STM/STM32_LIBRARIES/tm_stm32_qspiflash.c
uint8_t BSP_QSPI_GetStatus(void)
{
  QSPI_CommandTypeDef s_command;
  uint8_t reg;

  /* Initialize the read flag status register command */
  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
  s_command.Instruction       = READ_FLAG_STATUS_REG_CMD;
  s_command.AddressMode       = QSPI_ADDRESS_NONE;
  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
  s_command.DataMode          = QSPI_DATA_1_LINE;
  s_command.DummyCycles       = 0;
  s_command.NbData            = 1;
  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;

  /* Configure the command */
  if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
  {
    return QSPI_ERROR;
  }

  /* Reception of the data */
  if (HAL_QSPI_Receive(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
  {
    return QSPI_ERROR;
  }
  
  /* Check the value of the register */
  if ((reg & (N25Q128A_FSR_PRERR | N25Q128A_FSR_VPPERR | N25Q128A_FSR_PGERR | N25Q128A_FSR_ERERR)) != 0)
  {
    return QSPI_ERROR;
  }
  else if ((reg & (N25Q128A_FSR_PGSUS | N25Q128A_FSR_ERSUS)) != 0)
  {
    return QSPI_SUSPENDED;
  }
  else if ((reg & N25Q128A_FSR_READY) != 0)
  {
    return QSPI_OK;
  }
  else
  {
    return QSPI_BUSY;
  }
}
/**
  * @brief  Reads current status of the QSPI memory.
  * @retval QSPI memory status
  */
@brief  Reads current status of the QSPI memory.
@retval QSPI memory status
@brief Reads current status of the QSPI memory . @retval QSPI memory status
uint8_t BSP_QSPI_GetStatus(void)
{
  QSPI_CommandTypeDef s_command;
  uint8_t reg;
  s_command.InstructionMode   = QSPI_INSTRUCTION_1_LINE;
  s_command.Instruction       = READ_FLAG_STATUS_REG_CMD;
  s_command.AddressMode       = QSPI_ADDRESS_NONE;
  s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
  s_command.DataMode          = QSPI_DATA_1_LINE;
  s_command.DummyCycles       = 0;
  s_command.NbData            = 1;
  s_command.DdrMode           = QSPI_DDR_MODE_DISABLE;
  s_command.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;
  s_command.SIOOMode          = QSPI_SIOO_INST_EVERY_CMD;
  if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
  {
    return QSPI_ERROR;
  }
  if (HAL_QSPI_Receive(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
  {
    return QSPI_ERROR;
  }
  if ((reg & (N25Q128A_FSR_PRERR | N25Q128A_FSR_VPPERR | N25Q128A_FSR_PGERR | N25Q128A_FSR_ERERR)) != 0)
  {
    return QSPI_ERROR;
  }
  else if ((reg & (N25Q128A_FSR_PGSUS | N25Q128A_FSR_ERSUS)) != 0)
  {
    return QSPI_SUSPENDED;
  }
  else if ((reg & N25Q128A_FSR_READY) != 0)
  {
    return QSPI_OK;
  }
  else
  {
    return QSPI_BUSY;
  }
}
uint8_t BSP_QSPI_GetStatus ( void ) { QSPI_CommandTypeDef s_command ; uint8_t reg ; s_command . InstructionMode = QSPI_INSTRUCTION_1_LINE ; s_command . Instruction = READ_FLAG_STATUS_REG_CMD ; s_command . AddressMode = QSPI_ADDRESS_NONE ; s_command . AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE ; s_command . DataMode = QSPI_DATA_1_LINE ; s_command . DummyCycles = 0 ; s_command . NbData = 1 ; s_command . DdrMode = QSPI_DDR_MODE_DISABLE ; s_command . DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY ; s_command . SIOOMode = QSPI_SIOO_INST_EVERY_CMD ; if ( HAL_QSPI_Command ( & QSPIHandle , & s_command , HAL_QPSI_TIMEOUT_DEFAULT_VALUE ) != HAL_OK ) { return QSPI_ERROR ; } if ( HAL_QSPI_Receive ( & QSPIHandle , & reg , HAL_QPSI_TIMEOUT_DEFAULT_VALUE ) != HAL_OK ) { return QSPI_ERROR ; } if ( ( reg & ( N25Q128A_FSR_PRERR | N25Q128A_FSR_VPPERR | N25Q128A_FSR_PGERR | N25Q128A_FSR_ERERR ) ) != 0 ) { return QSPI_ERROR ; } else if ( ( reg & ( N25Q128A_FSR_PGSUS | N25Q128A_FSR_ERSUS ) ) != 0 ) { return QSPI_SUSPENDED ; } else if ( ( reg & N25Q128A_FSR_READY ) != 0 ) { return QSPI_OK ; } else { return QSPI_BUSY ; } }
@brief  Reads current status of the QSPI memory.
@brief Reads current status of the QSPI memory .
/* Initialize the read flag status register command */ /* Configure the command */ /* Reception of the data */ /* Check the value of the register */