src/dpdk/drivers/net/qede/base/ecore_dcbx.c
enum _ecore_status_t
ecore_dcbx_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
			    enum ecore_mib_read_type type)
{
	enum _ecore_status_t rc = ECORE_SUCCESS;

	rc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type);
	if (rc)
		return rc;

	if (type == ECORE_DCBX_OPERATIONAL_MIB) {
		ecore_dcbx_get_dscp_params(p_hwfn, &p_hwfn->p_dcbx_info->get);

		rc = ecore_dcbx_process_mib_info(p_hwfn, p_ptt);
		if (!rc) {
			/* reconfigure tcs of QM queues according
			 * to negotiation results
			 */
			ecore_qm_reconf(p_hwfn, p_ptt);

			/* update storm FW with negotiation results */
			ecore_sp_pf_update_dcbx(p_hwfn);
		}
	}

	ecore_dcbx_get_params(p_hwfn, &p_hwfn->p_dcbx_info->get, type);

	/* Update the DSCP to TC mapping enable bit if required */
	if ((type == ECORE_DCBX_OPERATIONAL_MIB) &&
	    p_hwfn->p_dcbx_info->dscp_nig_update) {
		u8 val = !!p_hwfn->p_dcbx_info->get.dscp.enabled;
		u32 addr = NIG_REG_DSCP_TO_TC_MAP_ENABLE;

		rc = ecore_all_ppfids_wr(p_hwfn, p_ptt, addr, val);
		if (rc != ECORE_SUCCESS) {
			DP_NOTICE(p_hwfn, false,
				  "Failed to update the DSCP to TC mapping enable bit\n");
			return rc;
		}

		p_hwfn->p_dcbx_info->dscp_nig_update = false;
	}

	OSAL_DCBX_AEN(p_hwfn, type);

	return rc;
}
/*
 * Read updated MIB.
 * Reconfigure QM and invoke PF update ramrod command if operational MIB
 * change is detected.
 */
Read updated MIB.
Reconfigure QM and invoke PF update ramrod command if operational MIB
change is detected.
Read updated MIB . Reconfigure QM and invoke PF update ramrod command if operational MIB change is detected .
enum _ecore_status_t
ecore_dcbx_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
			    enum ecore_mib_read_type type)
{
	enum _ecore_status_t rc = ECORE_SUCCESS;
	rc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type);
	if (rc)
		return rc;
	if (type == ECORE_DCBX_OPERATIONAL_MIB) {
		ecore_dcbx_get_dscp_params(p_hwfn, &p_hwfn->p_dcbx_info->get);
		rc = ecore_dcbx_process_mib_info(p_hwfn, p_ptt);
		if (!rc) {
			ecore_qm_reconf(p_hwfn, p_ptt);
			ecore_sp_pf_update_dcbx(p_hwfn);
		}
	}
	ecore_dcbx_get_params(p_hwfn, &p_hwfn->p_dcbx_info->get, type);
	if ((type == ECORE_DCBX_OPERATIONAL_MIB) &&
	    p_hwfn->p_dcbx_info->dscp_nig_update) {
		u8 val = !!p_hwfn->p_dcbx_info->get.dscp.enabled;
		u32 addr = NIG_REG_DSCP_TO_TC_MAP_ENABLE;
		rc = ecore_all_ppfids_wr(p_hwfn, p_ptt, addr, val);
		if (rc != ECORE_SUCCESS) {
			DP_NOTICE(p_hwfn, false,
				  "Failed to update the DSCP to TC mapping enable bit\n");
			return rc;
		}
		p_hwfn->p_dcbx_info->dscp_nig_update = false;
	}
	OSAL_DCBX_AEN(p_hwfn, type);
	return rc;
}
enum _ecore_status_t ecore_dcbx_mib_update_event ( struct ecore_hwfn * p_hwfn , struct ecore_ptt * p_ptt , enum ecore_mib_read_type type ) { enum _ecore_status_t rc = ECORE_SUCCESS ; rc = ecore_dcbx_read_mib ( p_hwfn , p_ptt , type ) ; if ( rc ) return rc ; if ( type == ECORE_DCBX_OPERATIONAL_MIB ) { ecore_dcbx_get_dscp_params ( p_hwfn , & p_hwfn -> p_dcbx_info -> get ) ; rc = ecore_dcbx_process_mib_info ( p_hwfn , p_ptt ) ; if ( ! rc ) { ecore_qm_reconf ( p_hwfn , p_ptt ) ; ecore_sp_pf_update_dcbx ( p_hwfn ) ; } } ecore_dcbx_get_params ( p_hwfn , & p_hwfn -> p_dcbx_info -> get , type ) ; if ( ( type == ECORE_DCBX_OPERATIONAL_MIB ) && p_hwfn -> p_dcbx_info -> dscp_nig_update ) { u8 val = ! ! p_hwfn -> p_dcbx_info -> get . dscp . enabled ; u32 addr = NIG_REG_DSCP_TO_TC_MAP_ENABLE ; rc = ecore_all_ppfids_wr ( p_hwfn , p_ptt , addr , val ) ; if ( rc != ECORE_SUCCESS ) { DP_NOTICE ( p_hwfn , false , " \n " ) ; return rc ; } p_hwfn -> p_dcbx_info -> dscp_nig_update = false ; } OSAL_DCBX_AEN ( p_hwfn , type ) ; return rc ; }
Read updated MIB.
Read updated MIB .
/* reconfigure tcs of QM queues according
			 * to negotiation results
			 */ /* update storm FW with negotiation results */ /* Update the DSCP to TC mapping enable bit if required */