XilinxProcessorIPLib/drivers/hdcp1x/src/xhdcp1x_cipher.c
int XHdcp1x_CipherDisableEncryption(XHdcp1x *InstancePtr, u64 StreamMap)
{
	u32 Val = 0;
	int DisableXor = TRUE;

	/* Verify arguments. */
	Xil_AssertNonvoid(InstancePtr != NULL);

	/* Check that it is not disabled */
	if (!XHdcp1x_CipherIsEnabled(InstancePtr)) {
		return (XST_NOT_ENABLED);
	}

	/* Check that it is not a receiver */
	if (XHdcp1x_IsRX(InstancePtr)) {
		return (XST_FAILURE);
	}

	/* Check for nothing to do */
	if (StreamMap == 0) {
		return (XST_SUCCESS);
	}

	/* Clear the register update bit */
	Val = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Val &= ~XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Val);

	/* Update the LS 32-bits */
	Val = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L);
	Val &= ~((u32) (StreamMap & 0xFFFFFFFFul));
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L, Val);
	if (Val != 0) {
		DisableXor = FALSE;
	}

	/* Write the MS 32-bits */
	Val = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H);
	Val &= ~((u32) ((StreamMap >> 32) & 0xFFFFFFFFul));
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H, Val);
	if (Val != 0) {
		DisableXor = FALSE;
	}

	/* Check HDMI special case */
	if (XHdcp1x_IsHDMI(InstancePtr)) {
		DisableXor = TRUE;
	}

	/* Check for XOR disable */
	if (DisableXor) {
		Val = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CIPHER_CONTROL);
		Val &= ~XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_XOR_ENABLE;
		XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CIPHER_CONTROL, Val);
	}

	/* Set the register update bit */
	Val = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Val |= XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Val);

	return (XST_SUCCESS);
}
/*****************************************************************************/
/**
* This function disables encryption on a set of streams.
*
* @param	InstancePtr is the device to configure.
* @param	StreamMap is the bit map of streams to disable encryption on.
*
* @return
*		- XST_SUCCESS if successful.
*		- XST_NOT_ENABLE if the core is not enabled.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function disables encryption on a set of streams.
This function disables encryption on a set of streams .
int XHdcp1x_CipherDisableEncryption(XHdcp1x *InstancePtr, u64 StreamMap)
{
	u32 Val = 0;
	int DisableXor = TRUE;
	Xil_AssertNonvoid(InstancePtr != NULL);
	if (!XHdcp1x_CipherIsEnabled(InstancePtr)) {
		return (XST_NOT_ENABLED);
	}
	if (XHdcp1x_IsRX(InstancePtr)) {
		return (XST_FAILURE);
	}
	if (StreamMap == 0) {
		return (XST_SUCCESS);
	}
	Val = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Val &= ~XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Val);
	Val = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L);
	Val &= ~((u32) (StreamMap & 0xFFFFFFFFul));
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L, Val);
	if (Val != 0) {
		DisableXor = FALSE;
	}
	Val = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H);
	Val &= ~((u32) ((StreamMap >> 32) & 0xFFFFFFFFul));
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H, Val);
	if (Val != 0) {
		DisableXor = FALSE;
	}
	if (XHdcp1x_IsHDMI(InstancePtr)) {
		DisableXor = TRUE;
	}
	if (DisableXor) {
		Val = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CIPHER_CONTROL);
		Val &= ~XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_XOR_ENABLE;
		XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CIPHER_CONTROL, Val);
	}
	Val = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Val |= XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Val);
	return (XST_SUCCESS);
}
int XHdcp1x_CipherDisableEncryption ( XHdcp1x * InstancePtr , u64 StreamMap ) { u32 Val = 0 ; int DisableXor = TRUE ; Xil_AssertNonvoid ( InstancePtr != NULL ) ; if ( ! XHdcp1x_CipherIsEnabled ( InstancePtr ) ) { return ( XST_NOT_ENABLED ) ; } if ( XHdcp1x_IsRX ( InstancePtr ) ) { return ( XST_FAILURE ) ; } if ( StreamMap == 0 ) { return ( XST_SUCCESS ) ; } Val = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL ) ; Val &= ~ XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL , Val ) ; Val = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L ) ; Val &= ~ ( ( u32 ) ( StreamMap & 0xFFFFFFFFul ) ) ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_L , Val ) ; if ( Val != 0 ) { DisableXor = FALSE ; } Val = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H ) ; Val &= ~ ( ( u32 ) ( ( StreamMap >> 32 ) & 0xFFFFFFFFul ) ) ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_ENCRYPT_ENABLE_H , Val ) ; if ( Val != 0 ) { DisableXor = FALSE ; } if ( XHdcp1x_IsHDMI ( InstancePtr ) ) { DisableXor = TRUE ; } if ( DisableXor ) { Val = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CIPHER_CONTROL ) ; Val &= ~ XHDCP1X_CIPHER_BITMASK_CIPHER_CONTROL_XOR_ENABLE ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CIPHER_CONTROL , Val ) ; } Val = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL ) ; Val |= XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL , Val ) ; return ( XST_SUCCESS ) ; }
This function disables encryption on a set of streams.
This function disables encryption on a set of streams .
/* Verify arguments. */ /* Check that it is not disabled */ /* Check that it is not a receiver */ /* Check for nothing to do */ /* Clear the register update bit */ /* Update the LS 32-bits */ /* Write the MS 32-bits */ /* Check HDMI special case */ /* Check for XOR disable */ /* Set the register update bit */