XilinxProcessorIPLib/drivers/aienginev2/src/dma/xaie_dma_aieml.c
static AieRC _XAieMl_DmaMemTileCheckPaddingConfig(XAie_DmaDesc *DmaDesc)
{
	XAie_AieMlDimDesc *DDesc = DmaDesc->MultiDimDesc.AieMlMultiDimDesc.DimDesc;
	XAie_PadDesc *PDesc = DmaDesc->PadDesc;

	for(u8 Dim = 0U; Dim < XAIEML_DMA_PAD_NUM_DIMS; Dim++) {
		if(DDesc[Dim].Wrap == 0U) {

			if(PDesc[Dim].After != 0U) {
				XAIE_ERROR("Padding after for dimension %u must"
						" be 0 when wrap is 1\n", Dim);
				return XAIE_INVALID_DMA_DESC;
			}

			for(u8 PadDim = Dim + 1U;
					PadDim < XAIEML_DMA_PAD_NUM_DIMS;
					PadDim++) {
				if((PDesc[PadDim].After != 0U) ||
						(PDesc[PadDim].Before != 0U)) {
					XAIE_ERROR("After and Before pading "
							"for dimension %u must "
							"be 0 when wrap for "
							"dimension %u is 0\n",
							PadDim, Dim);
					return XAIE_ERR;
				}
			}
		}
	}

	XAIE_DBG("Zero padding and wrap configuration is correct\n");
	return XAIE_OK;
}
/*****************************************************************************/
/**
*
* This API checks the validity of wrap and padding before and after fields of
* the Dma descriptor.
*
* @param	DmaDesc: Dma Descriptor
*
* @return	XAIE_OK on success, XAIE_INVALID_DMA_DESC on failure
*
* @note		Internal Only.
*		If D0_wrap == 0:
*			D1/D2 padding after/before must be 0
*			D0 padding after must be 0
*		If D1_wrap == 0:
*			D2 padding after/before must be 0
*			D1 padding after must be 0
*		If D2_wrap == 0:
*			D2 padding after must be 0
*
******************************************************************************/
This API checks the validity of wrap and padding before and after fields of
the Dma descriptor.
This API checks the validity of wrap and padding before and after fields of the Dma descriptor .
static AieRC _XAieMl_DmaMemTileCheckPaddingConfig(XAie_DmaDesc *DmaDesc)
{
	XAie_AieMlDimDesc *DDesc = DmaDesc->MultiDimDesc.AieMlMultiDimDesc.DimDesc;
	XAie_PadDesc *PDesc = DmaDesc->PadDesc;
	for(u8 Dim = 0U; Dim < XAIEML_DMA_PAD_NUM_DIMS; Dim++) {
		if(DDesc[Dim].Wrap == 0U) {
			if(PDesc[Dim].After != 0U) {
				XAIE_ERROR("Padding after for dimension %u must"
						" be 0 when wrap is 1\n", Dim);
				return XAIE_INVALID_DMA_DESC;
			}
			for(u8 PadDim = Dim + 1U;
					PadDim < XAIEML_DMA_PAD_NUM_DIMS;
					PadDim++) {
				if((PDesc[PadDim].After != 0U) ||
						(PDesc[PadDim].Before != 0U)) {
					XAIE_ERROR("After and Before pading "
							"for dimension %u must "
							"be 0 when wrap for "
							"dimension %u is 0\n",
							PadDim, Dim);
					return XAIE_ERR;
				}
			}
		}
	}
	XAIE_DBG("Zero padding and wrap configuration is correct\n");
	return XAIE_OK;
}
static AieRC _XAieMl_DmaMemTileCheckPaddingConfig ( XAie_DmaDesc * DmaDesc ) { XAie_AieMlDimDesc * DDesc = DmaDesc -> MultiDimDesc . AieMlMultiDimDesc . DimDesc ; XAie_PadDesc * PDesc = DmaDesc -> PadDesc ; for ( u8 Dim = 0U ; Dim < XAIEML_DMA_PAD_NUM_DIMS ; Dim ++ ) { if ( DDesc [ Dim ] . Wrap == 0U ) { if ( PDesc [ Dim ] . After != 0U ) { XAIE_ERROR ( " " " \n " , Dim ) ; return XAIE_INVALID_DMA_DESC ; } for ( u8 PadDim = Dim + 1U ; PadDim < XAIEML_DMA_PAD_NUM_DIMS ; PadDim ++ ) { if ( ( PDesc [ PadDim ] . After != 0U ) || ( PDesc [ PadDim ] . Before != 0U ) ) { XAIE_ERROR ( " " " " " " " \n " , PadDim , Dim ) ; return XAIE_ERR ; } } } } XAIE_DBG ( " \n " ) ; return XAIE_OK ; }
This API checks the validity of wrap and padding before and after fields of
the Dma descriptor.
This API checks the validity of wrap and padding before and after fields of the Dma descriptor .