src/dpdk/drivers/net/igc/base/igc_nvm.c
static s32 igc_ready_nvm_eeprom(struct igc_hw *hw)
{
	struct igc_nvm_info *nvm = &hw->nvm;
	u32 eecd = IGC_READ_REG(hw, IGC_EECD);
	u8 spi_stat_reg;

	DEBUGFUNC("igc_ready_nvm_eeprom");

	if (nvm->type == igc_nvm_eeprom_microwire) {
		/* Clear SK and DI */
		eecd &= ~(IGC_EECD_DI | IGC_EECD_SK);
		IGC_WRITE_REG(hw, IGC_EECD, eecd);
		/* Set CS */
		eecd |= IGC_EECD_CS;
		IGC_WRITE_REG(hw, IGC_EECD, eecd);
	} else if (nvm->type == igc_nvm_eeprom_spi) {
		u16 timeout = NVM_MAX_RETRY_SPI;

		/* Clear SK and CS */
		eecd &= ~(IGC_EECD_CS | IGC_EECD_SK);
		IGC_WRITE_REG(hw, IGC_EECD, eecd);
		IGC_WRITE_FLUSH(hw);
		usec_delay(1);

		/* Read "Status Register" repeatedly until the LSB is cleared.
		 * The EEPROM will signal that the command has been completed
		 * by clearing bit 0 of the internal status register.  If it's
		 * not cleared within 'timeout', then error out.
		 */
		while (timeout) {
			igc_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
						 hw->nvm.opcode_bits);
			spi_stat_reg = (u8)igc_shift_in_eec_bits(hw, 8);
			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
				break;

			usec_delay(5);
			igc_standby_nvm(hw);
			timeout--;
		}

		if (!timeout) {
			DEBUGOUT("SPI NVM Status error\n");
			return -IGC_ERR_NVM;
		}
	}

	return IGC_SUCCESS;
}
/**
 *  igc_ready_nvm_eeprom - Prepares EEPROM for read/write
 *  @hw: pointer to the HW structure
 *
 *  Setups the EEPROM for reading and writing.
 **/
Prepares EEPROM for read/write
@hw: pointer to the HW structure

Setups the EEPROM for reading and writing.
Prepares EEPROM for read / write @hw : pointer to the HW structure Setups the EEPROM for reading and writing .
static s32 igc_ready_nvm_eeprom(struct igc_hw *hw)
{
	struct igc_nvm_info *nvm = &hw->nvm;
	u32 eecd = IGC_READ_REG(hw, IGC_EECD);
	u8 spi_stat_reg;
	DEBUGFUNC("igc_ready_nvm_eeprom");
	if (nvm->type == igc_nvm_eeprom_microwire) {
		eecd &= ~(IGC_EECD_DI | IGC_EECD_SK);
		IGC_WRITE_REG(hw, IGC_EECD, eecd);
		eecd |= IGC_EECD_CS;
		IGC_WRITE_REG(hw, IGC_EECD, eecd);
	} else if (nvm->type == igc_nvm_eeprom_spi) {
		u16 timeout = NVM_MAX_RETRY_SPI;
		eecd &= ~(IGC_EECD_CS | IGC_EECD_SK);
		IGC_WRITE_REG(hw, IGC_EECD, eecd);
		IGC_WRITE_FLUSH(hw);
		usec_delay(1);
		while (timeout) {
			igc_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
						 hw->nvm.opcode_bits);
			spi_stat_reg = (u8)igc_shift_in_eec_bits(hw, 8);
			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
				break;
			usec_delay(5);
			igc_standby_nvm(hw);
			timeout--;
		}
		if (!timeout) {
			DEBUGOUT("SPI NVM Status error\n");
			return -IGC_ERR_NVM;
		}
	}
	return IGC_SUCCESS;
}
static s32 igc_ready_nvm_eeprom ( struct igc_hw * hw ) { struct igc_nvm_info * nvm = & hw -> nvm ; u32 eecd = IGC_READ_REG ( hw , IGC_EECD ) ; u8 spi_stat_reg ; DEBUGFUNC ( " " ) ; if ( nvm -> type == igc_nvm_eeprom_microwire ) { eecd &= ~ ( IGC_EECD_DI | IGC_EECD_SK ) ; IGC_WRITE_REG ( hw , IGC_EECD , eecd ) ; eecd |= IGC_EECD_CS ; IGC_WRITE_REG ( hw , IGC_EECD , eecd ) ; } else if ( nvm -> type == igc_nvm_eeprom_spi ) { u16 timeout = NVM_MAX_RETRY_SPI ; eecd &= ~ ( IGC_EECD_CS | IGC_EECD_SK ) ; IGC_WRITE_REG ( hw , IGC_EECD , eecd ) ; IGC_WRITE_FLUSH ( hw ) ; usec_delay ( 1 ) ; while ( timeout ) { igc_shift_out_eec_bits ( hw , NVM_RDSR_OPCODE_SPI , hw -> nvm . opcode_bits ) ; spi_stat_reg = ( u8 ) igc_shift_in_eec_bits ( hw , 8 ) ; if ( ! ( spi_stat_reg & NVM_STATUS_RDY_SPI ) ) break ; usec_delay ( 5 ) ; igc_standby_nvm ( hw ) ; timeout -- ; } if ( ! timeout ) { DEBUGOUT ( " \n " ) ; return - IGC_ERR_NVM ; } } return IGC_SUCCESS ; }
igc_ready_nvm_eeprom - Prepares EEPROM for read/write
  @hw: pointer to the HW structure
igc_ready_nvm_eeprom - Prepares EEPROM for read / write @hw : pointer to the HW structure
/* Clear SK and DI */ /* Set CS */ /* Clear SK and CS */ /* Read "Status Register" repeatedly until the LSB is cleared.
		 * The EEPROM will signal that the command has been completed
		 * by clearing bit 0 of the internal status register.  If it's
		 * not cleared within 'timeout', then error out.
		 */