gen/genacorn.c
static void shift_down(void)
{
    int extra = -1;

    // LFSR7: s7_l ^= (f << 4), state->s7 = (f >> 4)
    alloc_high_reg(&extra);
    check_high_reg(&f);
    insn_printf("swap r%d", f);
    insn_printf("mov r%d,r%d", extra, f);
    insn_printf("andi r%d,0xF0", extra);    // Assumes extra is a high reg.
    insn_printf("eor r%d,r%d", s7_l, extra);
    insn_printf("andi r%d,0x0F", f);        // Assumes f is a high reg.
    insn_printf("std Z+%d,r%d", get_lfsr(6)->offsetl, f);
    release_reg(&f);
    release_reg(&extra);

    // LFSR6 down to LFSR1
    shift_down_lfsr(get_lfsr(5), s7_l);
    release_reg(&s7_l);
    shift_down_lfsr(get_lfsr(4), s6_l);
    release_reg(&s6_l);
    shift_down_lfsr(get_lfsr(3), s5_l);
    release_reg(&s5_l);
    shift_down_lfsr(get_lfsr(2), s4_l);
    release_reg(&s4_l);
    shift_down_lfsr(get_lfsr(1), s3_l);
    release_reg(&s3_l);
    shift_down_lfsr(get_lfsr(0), s2_l);
    release_reg(&s2_l);
}
// Shift the state downwards by 8 bits.
Shift the state downwards by 8 bits.
Shift the state downwards by 8 bits .
static void shift_down(void)
{
    int extra = -1;
    alloc_high_reg(&extra);
    check_high_reg(&f);
    insn_printf("swap r%d", f);
    insn_printf("mov r%d,r%d", extra, f);
    insn_printf("andi r%d,0xF0", extra);    
    insn_printf("eor r%d,r%d", s7_l, extra);
    insn_printf("andi r%d,0x0F", f);        
    insn_printf("std Z+%d,r%d", get_lfsr(6)->offsetl, f);
    release_reg(&f);
    release_reg(&extra);
    shift_down_lfsr(get_lfsr(5), s7_l);
    release_reg(&s7_l);
    shift_down_lfsr(get_lfsr(4), s6_l);
    release_reg(&s6_l);
    shift_down_lfsr(get_lfsr(3), s5_l);
    release_reg(&s5_l);
    shift_down_lfsr(get_lfsr(2), s4_l);
    release_reg(&s4_l);
    shift_down_lfsr(get_lfsr(1), s3_l);
    release_reg(&s3_l);
    shift_down_lfsr(get_lfsr(0), s2_l);
    release_reg(&s2_l);
}
static void shift_down ( void ) { int extra = -1 ; alloc_high_reg ( & extra ) ; check_high_reg ( & f ) ; insn_printf ( " " , f ) ; insn_printf ( " " , extra , f ) ; insn_printf ( " " , extra ) ; insn_printf ( " " , s7_l , extra ) ; insn_printf ( " " , f ) ; insn_printf ( " " , get_lfsr ( 6 ) -> offsetl , f ) ; release_reg ( & f ) ; release_reg ( & extra ) ; shift_down_lfsr ( get_lfsr ( 5 ) , s7_l ) ; release_reg ( & s7_l ) ; shift_down_lfsr ( get_lfsr ( 4 ) , s6_l ) ; release_reg ( & s6_l ) ; shift_down_lfsr ( get_lfsr ( 3 ) , s5_l ) ; release_reg ( & s5_l ) ; shift_down_lfsr ( get_lfsr ( 2 ) , s4_l ) ; release_reg ( & s4_l ) ; shift_down_lfsr ( get_lfsr ( 1 ) , s3_l ) ; release_reg ( & s3_l ) ; shift_down_lfsr ( get_lfsr ( 0 ) , s2_l ) ; release_reg ( & s2_l ) ; }
Shift the state downwards by 8 bits.
Shift the state downwards by 8 bits .
// LFSR7: s7_l ^= (f << 4), state->s7 = (f >> 4) // Assumes extra is a high reg. // Assumes f is a high reg. // LFSR6 down to LFSR1