XilinxProcessorIPLib/drivers/vphy/src/xvphy_gthe4.c
u32 XVphy_Gthe4CfgSetCdr(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
{
	XVphy_Channel *ChPtr;
	u32 Status = XST_SUCCESS;
	u64 LineRateHz;

	/* Set CDR values only for CPLLs. */
	if ((ChId < XVPHY_CHANNEL_ID_CH1) || (ChId > XVPHY_CHANNEL_ID_CH4)) {
		return XST_FAILURE;
	}

	/* This is DP specific. */
	ChPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(ChId)];

	ChPtr->PllParams.Cdr[0] = 0x0000;
	ChPtr->PllParams.Cdr[1] = 0x0000;
	ChPtr->PllParams.Cdr[3] = 0x0000;
	ChPtr->PllParams.Cdr[4] = 0x0000;
	if (InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_DP) {

		LineRateHz = XVphy_GetLineRateHz(InstancePtr, QuadId, ChId);

		if(LineRateHz==XVPHY_DP_LINK_RATE_HZ_810GBPS) {
		  ChPtr->PllParams.Cdr[2] = 0x01C4;
		} else if(LineRateHz==XVPHY_DP_LINK_RATE_HZ_540GBPS) {
			ChPtr->PllParams.Cdr[2] = 0x01C4;
		} else if(LineRateHz==XVPHY_DP_LINK_RATE_HZ_270GBPS) {
			ChPtr->PllParams.Cdr[2] = 0x01B4;
		} else {
			ChPtr->PllParams.Cdr[2] = 0x01A3;
		}
	}
	else if (XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX)) {
		/* RxOutDiv = 1  => Cdr[2] = 0x0269
		 * RxOutDiv = 2  => Cdr[2] = 0x0259
		 * RxOutDiv = 4  => Cdr[2] = 0x0249
		 * RxOutDiv = 8  => Cdr[2] = 0x0239
		 * RxOutDiv = 16 => Cdr[2] = 0x0229 */
		ChPtr->PllParams.Cdr[2] = 0x0269;
		while (ChPtr->RxOutDiv >>= 1) {
			ChPtr->PllParams.Cdr[2] -= 0x10;
		}
		/* Restore RxOutDiv. */
		ChPtr->RxOutDiv = 1 << ((0x0269 - ChPtr->PllParams.Cdr[2]) >> 4);
	}
	else {
		Status = XST_FAILURE;
	}

	return Status;
}
/*****************************************************************************/
/**
* This function will set the clock and data recovery (CDR) values for a given
* channel.
*
* @param	InstancePtr is a pointer to the XVphy core instance.
* @param	QuadId is the GT quad ID to operate on.
* @param	ChId is the channel ID to operate on.
*
* @return
*		- XST_SUCCESS if the configuration was successful.
*		- XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
This function will set the clock and data recovery (CDR) values for a given
channel.
This function will set the clock and data recovery ( CDR ) values for a given channel .
u32 XVphy_Gthe4CfgSetCdr(XVphy *InstancePtr, u8 QuadId, XVphy_ChannelId ChId)
{
	XVphy_Channel *ChPtr;
	u32 Status = XST_SUCCESS;
	u64 LineRateHz;
	if ((ChId < XVPHY_CHANNEL_ID_CH1) || (ChId > XVPHY_CHANNEL_ID_CH4)) {
		return XST_FAILURE;
	}
	ChPtr = &InstancePtr->Quads[QuadId].Plls[XVPHY_CH2IDX(ChId)];
	ChPtr->PllParams.Cdr[0] = 0x0000;
	ChPtr->PllParams.Cdr[1] = 0x0000;
	ChPtr->PllParams.Cdr[3] = 0x0000;
	ChPtr->PllParams.Cdr[4] = 0x0000;
	if (InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_DP) {
		LineRateHz = XVphy_GetLineRateHz(InstancePtr, QuadId, ChId);
		if(LineRateHz==XVPHY_DP_LINK_RATE_HZ_810GBPS) {
		  ChPtr->PllParams.Cdr[2] = 0x01C4;
		} else if(LineRateHz==XVPHY_DP_LINK_RATE_HZ_540GBPS) {
			ChPtr->PllParams.Cdr[2] = 0x01C4;
		} else if(LineRateHz==XVPHY_DP_LINK_RATE_HZ_270GBPS) {
			ChPtr->PllParams.Cdr[2] = 0x01B4;
		} else {
			ChPtr->PllParams.Cdr[2] = 0x01A3;
		}
	}
	else if (XVphy_IsHDMI(InstancePtr, XVPHY_DIR_RX)) {
		ChPtr->PllParams.Cdr[2] = 0x0269;
		while (ChPtr->RxOutDiv >>= 1) {
			ChPtr->PllParams.Cdr[2] -= 0x10;
		}
		ChPtr->RxOutDiv = 1 << ((0x0269 - ChPtr->PllParams.Cdr[2]) >> 4);
	}
	else {
		Status = XST_FAILURE;
	}
	return Status;
}
u32 XVphy_Gthe4CfgSetCdr ( XVphy * InstancePtr , u8 QuadId , XVphy_ChannelId ChId ) { XVphy_Channel * ChPtr ; u32 Status = XST_SUCCESS ; u64 LineRateHz ; if ( ( ChId < XVPHY_CHANNEL_ID_CH1 ) || ( ChId > XVPHY_CHANNEL_ID_CH4 ) ) { return XST_FAILURE ; } ChPtr = & InstancePtr -> Quads [ QuadId ] . Plls [ XVPHY_CH2IDX ( ChId ) ] ; ChPtr -> PllParams . Cdr [ 0 ] = 0x0000 ; ChPtr -> PllParams . Cdr [ 1 ] = 0x0000 ; ChPtr -> PllParams . Cdr [ 3 ] = 0x0000 ; ChPtr -> PllParams . Cdr [ 4 ] = 0x0000 ; if ( InstancePtr -> Config . RxProtocol == XVPHY_PROTOCOL_DP ) { LineRateHz = XVphy_GetLineRateHz ( InstancePtr , QuadId , ChId ) ; if ( LineRateHz == XVPHY_DP_LINK_RATE_HZ_810GBPS ) { ChPtr -> PllParams . Cdr [ 2 ] = 0x01C4 ; } else if ( LineRateHz == XVPHY_DP_LINK_RATE_HZ_540GBPS ) { ChPtr -> PllParams . Cdr [ 2 ] = 0x01C4 ; } else if ( LineRateHz == XVPHY_DP_LINK_RATE_HZ_270GBPS ) { ChPtr -> PllParams . Cdr [ 2 ] = 0x01B4 ; } else { ChPtr -> PllParams . Cdr [ 2 ] = 0x01A3 ; } } else if ( XVphy_IsHDMI ( InstancePtr , XVPHY_DIR_RX ) ) { ChPtr -> PllParams . Cdr [ 2 ] = 0x0269 ; while ( ChPtr -> RxOutDiv >>= 1 ) { ChPtr -> PllParams . Cdr [ 2 ] -= 0x10 ; } ChPtr -> RxOutDiv = 1 << ( ( 0x0269 - ChPtr -> PllParams . Cdr [ 2 ] ) >> 4 ) ; } else { Status = XST_FAILURE ; } return Status ; }
This function will set the clock and data recovery (CDR) values for a given
channel.
This function will set the clock and data recovery ( CDR ) values for a given channel .
/* Set CDR values only for CPLLs. */ /* This is DP specific. */ /* RxOutDiv = 1  => Cdr[2] = 0x0269
		 * RxOutDiv = 2  => Cdr[2] = 0x0259
		 * RxOutDiv = 4  => Cdr[2] = 0x0249
		 * RxOutDiv = 8  => Cdr[2] = 0x0239
		 * RxOutDiv = 16 => Cdr[2] = 0x0229 */ /* Restore RxOutDiv. */