src/dpdk/drivers/net/ixgbe/ixgbe_ethdev.c
static void
ixgbe_configure_msix(struct rte_eth_dev *dev)
{
	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
	struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
	struct ixgbe_hw *hw =
		IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
	uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
	uint32_t vec = IXGBE_MISC_VEC_ID;
	uint32_t mask;
	uint32_t gpie;

	/* won't configure msix register if no mapping is done
	 * between intr vector and event fd
	 * but if misx has been enabled already, need to configure
	 * auto clean, auto mask and throttling.
	 */
	gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
	if (!rte_intr_dp_is_en(intr_handle) &&
	    !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
		return;

	if (rte_intr_allow_others(intr_handle))
		vec = base = IXGBE_RX_VEC_START;

	/* setup GPIE for MSI-x mode */
	gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
	gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
		IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
	/* auto clearing and auto setting corresponding bits in EIMS
	 * when MSI-X interrupt is triggered
	 */
	if (hw->mac.type == ixgbe_mac_82598EB) {
		IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
	} else {
		IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
		IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
	}
	IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);

	/* Populate the IVAR table and set the ITR values to the
	 * corresponding register.
	 */
	if (rte_intr_dp_is_en(intr_handle)) {
		for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
			queue_id++) {
			/* by default, 1:1 mapping */
			ixgbe_set_ivar_map(hw, 0, queue_id, vec);
			intr_handle->intr_vec[queue_id] = vec;
			if (vec < base + intr_handle->nb_efd - 1)
				vec++;
		}

		switch (hw->mac.type) {
		case ixgbe_mac_82598EB:
			ixgbe_set_ivar_map(hw, -1,
					   IXGBE_IVAR_OTHER_CAUSES_INDEX,
					   IXGBE_MISC_VEC_ID);
			break;
		case ixgbe_mac_82599EB:
		case ixgbe_mac_X540:
		case ixgbe_mac_X550:
		case ixgbe_mac_X550EM_x:
			ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
			break;
		default:
			break;
		}
	}
	IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
			IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
			| IXGBE_EITR_CNT_WDIS);

	/* set up to autoclear timer, and the vectors */
	mask = IXGBE_EIMS_ENABLE_MASK;
	mask &= ~(IXGBE_EIMS_OTHER |
		  IXGBE_EIMS_MAILBOX |
		  IXGBE_EIMS_LSC);

	IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
}
/**
 * Sets up the hardware to properly generate MSI-X interrupts
 * @hw
 *  board private structure
 */
Sets up the hardware to properly generate MSI-X interrupts
@hw
board private structure
Sets up the hardware to properly generate MSI - X interrupts @hw board private structure
static void
ixgbe_configure_msix(struct rte_eth_dev *dev)
{
	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
	struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
	struct ixgbe_hw *hw =
		IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
	uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
	uint32_t vec = IXGBE_MISC_VEC_ID;
	uint32_t mask;
	uint32_t gpie;
	gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
	if (!rte_intr_dp_is_en(intr_handle) &&
	    !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
		return;
	if (rte_intr_allow_others(intr_handle))
		vec = base = IXGBE_RX_VEC_START;
	gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
	gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
		IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
	if (hw->mac.type == ixgbe_mac_82598EB) {
		IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
	} else {
		IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
		IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
	}
	IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
	if (rte_intr_dp_is_en(intr_handle)) {
		for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
			queue_id++) {
			ixgbe_set_ivar_map(hw, 0, queue_id, vec);
			intr_handle->intr_vec[queue_id] = vec;
			if (vec < base + intr_handle->nb_efd - 1)
				vec++;
		}
		switch (hw->mac.type) {
		case ixgbe_mac_82598EB:
			ixgbe_set_ivar_map(hw, -1,
					   IXGBE_IVAR_OTHER_CAUSES_INDEX,
					   IXGBE_MISC_VEC_ID);
			break;
		case ixgbe_mac_82599EB:
		case ixgbe_mac_X540:
		case ixgbe_mac_X550:
		case ixgbe_mac_X550EM_x:
			ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
			break;
		default:
			break;
		}
	}
	IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
			IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
			| IXGBE_EITR_CNT_WDIS);
	mask = IXGBE_EIMS_ENABLE_MASK;
	mask &= ~(IXGBE_EIMS_OTHER |
		  IXGBE_EIMS_MAILBOX |
		  IXGBE_EIMS_LSC);
	IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
}
static void ixgbe_configure_msix ( struct rte_eth_dev * dev ) { struct rte_pci_device * pci_dev = RTE_ETH_DEV_TO_PCI ( dev ) ; struct rte_intr_handle * intr_handle = & pci_dev -> intr_handle ; struct ixgbe_hw * hw = IXGBE_DEV_PRIVATE_TO_HW ( dev -> data -> dev_private ) ; uint32_t queue_id , base = IXGBE_MISC_VEC_ID ; uint32_t vec = IXGBE_MISC_VEC_ID ; uint32_t mask ; uint32_t gpie ; gpie = IXGBE_READ_REG ( hw , IXGBE_GPIE ) ; if ( ! rte_intr_dp_is_en ( intr_handle ) && ! ( gpie & ( IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT ) ) ) return ; if ( rte_intr_allow_others ( intr_handle ) ) vec = base = IXGBE_RX_VEC_START ; gpie = IXGBE_READ_REG ( hw , IXGBE_GPIE ) ; gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME ; if ( hw -> mac . type == ixgbe_mac_82598EB ) { IXGBE_WRITE_REG ( hw , IXGBE_EIAM , IXGBE_EICS_RTX_QUEUE ) ; } else { IXGBE_WRITE_REG ( hw , IXGBE_EIAM_EX ( 0 ) , 0xFFFFFFFF ) ; IXGBE_WRITE_REG ( hw , IXGBE_EIAM_EX ( 1 ) , 0xFFFFFFFF ) ; } IXGBE_WRITE_REG ( hw , IXGBE_GPIE , gpie ) ; if ( rte_intr_dp_is_en ( intr_handle ) ) { for ( queue_id = 0 ; queue_id < dev -> data -> nb_rx_queues ; queue_id ++ ) { ixgbe_set_ivar_map ( hw , 0 , queue_id , vec ) ; intr_handle -> intr_vec [ queue_id ] = vec ; if ( vec < base + intr_handle -> nb_efd - 1 ) vec ++ ; } switch ( hw -> mac . type ) { case ixgbe_mac_82598EB : ixgbe_set_ivar_map ( hw , -1 , IXGBE_IVAR_OTHER_CAUSES_INDEX , IXGBE_MISC_VEC_ID ) ; break ; case ixgbe_mac_82599EB : case ixgbe_mac_X540 : case ixgbe_mac_X550 : case ixgbe_mac_X550EM_x : ixgbe_set_ivar_map ( hw , -1 , 1 , IXGBE_MISC_VEC_ID ) ; break ; default : break ; } } IXGBE_WRITE_REG ( hw , IXGBE_EITR ( IXGBE_MISC_VEC_ID ) , IXGBE_EITR_INTERVAL_US ( IXGBE_QUEUE_ITR_INTERVAL_DEFAULT ) | IXGBE_EITR_CNT_WDIS ) ; mask = IXGBE_EIMS_ENABLE_MASK ; mask &= ~ ( IXGBE_EIMS_OTHER | IXGBE_EIMS_MAILBOX | IXGBE_EIMS_LSC ) ; IXGBE_WRITE_REG ( hw , IXGBE_EIAC , mask ) ; }
Sets up the hardware to properly generate MSI-X interrupts
 @hw
  board private structure
Sets up the hardware to properly generate MSI - X interrupts @hw board private structure
/* won't configure msix register if no mapping is done
	 * between intr vector and event fd
	 * but if misx has been enabled already, need to configure
	 * auto clean, auto mask and throttling.
	 */ /* setup GPIE for MSI-x mode */ /* auto clearing and auto setting corresponding bits in EIMS
	 * when MSI-X interrupt is triggered
	 */ /* Populate the IVAR table and set the ITR values to the
	 * corresponding register.
	 */ /* by default, 1:1 mapping */ /* set up to autoclear timer, and the vectors */