XilinxProcessorIPLib/drivers/hdcp1x/src/xhdcp1x_cipher.c
void XHdcp1x_CipherInit(XHdcp1x *InstancePtr)
{
	u32 Value = 0;

	/* Reset it */
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Value |= XHDCP1X_CIPHER_BITMASK_CONTROL_RESET;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Value);
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Value &= ~XHDCP1X_CIPHER_BITMASK_CONTROL_RESET;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Value);

	/* Ensure all interrupts are disabled and cleared */
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_INTERRUPT_MASK, (u32)(-1));
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_INTERRUPT_STATUS, (u32)(-1));

	/* Check for DP */
	if (XHdcp1x_IsDP(InstancePtr)) {
		/* Configure for four lanes SST */
		Value  = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CONTROL);
		Value &= ~XHDCP1X_CIPHER_BITMASK_CONTROL_NUM_LANES;
		Value |= (4u << 4);
		XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CONTROL, Value);
	}

	/* Ensure that the register update bit is set */
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Value |= XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Value);
}
/*****************************************************************************/
/**
* This function initializes an HDCP cipher.
*
* @param	InstancePtr is the device to initialize.
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
This function initializes an HDCP cipher.
This function initializes an HDCP cipher .
void XHdcp1x_CipherInit(XHdcp1x *InstancePtr)
{
	u32 Value = 0;
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Value |= XHDCP1X_CIPHER_BITMASK_CONTROL_RESET;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Value);
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Value &= ~XHDCP1X_CIPHER_BITMASK_CONTROL_RESET;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Value);
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_INTERRUPT_MASK, (u32)(-1));
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_INTERRUPT_STATUS, (u32)(-1));
	if (XHdcp1x_IsDP(InstancePtr)) {
		Value  = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CONTROL);
		Value &= ~XHDCP1X_CIPHER_BITMASK_CONTROL_NUM_LANES;
		Value |= (4u << 4);
		XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
			XHDCP1X_CIPHER_REG_CONTROL, Value);
	}
	Value = XHdcp1x_ReadReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL);
	Value |= XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE;
	XHdcp1x_WriteReg(InstancePtr->Config.BaseAddress,
		XHDCP1X_CIPHER_REG_CONTROL, Value);
}
void XHdcp1x_CipherInit ( XHdcp1x * InstancePtr ) { u32 Value = 0 ; Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL ) ; Value |= XHDCP1X_CIPHER_BITMASK_CONTROL_RESET ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL , Value ) ; Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL ) ; Value &= ~ XHDCP1X_CIPHER_BITMASK_CONTROL_RESET ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL , Value ) ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_INTERRUPT_MASK , ( u32 ) ( -1 ) ) ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_INTERRUPT_STATUS , ( u32 ) ( -1 ) ) ; if ( XHdcp1x_IsDP ( InstancePtr ) ) { Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL ) ; Value &= ~ XHDCP1X_CIPHER_BITMASK_CONTROL_NUM_LANES ; Value |= ( 4u << 4 ) ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL , Value ) ; } Value = XHdcp1x_ReadReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL ) ; Value |= XHDCP1X_CIPHER_BITMASK_CONTROL_UPDATE ; XHdcp1x_WriteReg ( InstancePtr -> Config . BaseAddress , XHDCP1X_CIPHER_REG_CONTROL , Value ) ; }
This function initializes an HDCP cipher.
This function initializes an HDCP cipher .
/* Reset it */ /* Ensure all interrupts are disabled and cleared */ /* Check for DP */ /* Configure for four lanes SST */ /* Ensure that the register update bit is set */