src/drivers/trex_i40e_fdir.c
static void
i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
		enum i40e_filter_pctype pctype,
		const struct trex_rte_eth_fdir_flex_mask *mask_cfg)
{
	struct i40e_hw *hw = I40E_PF_TO_HW(pf);
	struct i40e_fdir_flex_mask *flex_mask;
	uint32_t flxinset, fd_mask;
	uint16_t mask_tmp;
	uint8_t i, nb_bitmask = 0;

	flex_mask = &pf->fdir.flex_mask[pctype];
	memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
	for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
		mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
		if (mask_tmp != 0x0) {
			flex_mask->word_mask |=
				I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
			if (mask_tmp != UINT16_MAX) {
				/* set bit mask */
				flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
				flex_mask->bitmask[nb_bitmask].offset =
					i / sizeof(uint16_t);
				nb_bitmask++;
			}
		}
	}
	/* write mask to hw */
	flxinset = (flex_mask->word_mask <<
		I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
		I40E_PRTQF_FD_FLXINSET_INSET_MASK;
	i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);

	for (i = 0; i < nb_bitmask; i++) {
		fd_mask = (flex_mask->bitmask[i].mask <<
			I40E_PRTQF_FD_MSK_MASK_SHIFT) &
			I40E_PRTQF_FD_MSK_MASK_MASK;
		fd_mask |= ((flex_mask->bitmask[i].offset +
			I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
			I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
			I40E_PRTQF_FD_MSK_OFFSET_MASK;
		i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
	}
}
/*
 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 * @pf: board private structure
 * @pctype: packet classify type
 * @flex_masks: mask for flexible payload
 */
configure the mask on flexible payload
@pf: board private structure
@pctype: packet classify type
@flex_masks: mask for flexible payload
configure the mask on flexible payload @pf : board private structure @pctype : packet classify type @flex_masks : mask for flexible payload
static void
i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
		enum i40e_filter_pctype pctype,
		const struct trex_rte_eth_fdir_flex_mask *mask_cfg)
{
	struct i40e_hw *hw = I40E_PF_TO_HW(pf);
	struct i40e_fdir_flex_mask *flex_mask;
	uint32_t flxinset, fd_mask;
	uint16_t mask_tmp;
	uint8_t i, nb_bitmask = 0;
	flex_mask = &pf->fdir.flex_mask[pctype];
	memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
	for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
		mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
		if (mask_tmp != 0x0) {
			flex_mask->word_mask |=
				I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
			if (mask_tmp != UINT16_MAX) {
				flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
				flex_mask->bitmask[nb_bitmask].offset =
					i / sizeof(uint16_t);
				nb_bitmask++;
			}
		}
	}
	flxinset = (flex_mask->word_mask <<
		I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
		I40E_PRTQF_FD_FLXINSET_INSET_MASK;
	i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
	for (i = 0; i < nb_bitmask; i++) {
		fd_mask = (flex_mask->bitmask[i].mask <<
			I40E_PRTQF_FD_MSK_MASK_SHIFT) &
			I40E_PRTQF_FD_MSK_MASK_MASK;
		fd_mask |= ((flex_mask->bitmask[i].offset +
			I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
			I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
			I40E_PRTQF_FD_MSK_OFFSET_MASK;
		i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
	}
}
static void i40e_set_flex_mask_on_pctype ( struct i40e_pf * pf , enum i40e_filter_pctype pctype , const struct trex_rte_eth_fdir_flex_mask * mask_cfg ) { struct i40e_hw * hw = I40E_PF_TO_HW ( pf ) ; struct i40e_fdir_flex_mask * flex_mask ; uint32_t flxinset , fd_mask ; uint16_t mask_tmp ; uint8_t i , nb_bitmask = 0 ; flex_mask = & pf -> fdir . flex_mask [ pctype ] ; memset ( flex_mask , 0 , sizeof ( struct i40e_fdir_flex_mask ) ) ; for ( i = 0 ; i < I40E_FDIR_MAX_FLEX_LEN ; i += sizeof ( uint16_t ) ) { mask_tmp = I40E_WORD ( mask_cfg -> mask [ i ] , mask_cfg -> mask [ i + 1 ] ) ; if ( mask_tmp != 0x0 ) { flex_mask -> word_mask |= I40E_FLEX_WORD_MASK ( i / sizeof ( uint16_t ) ) ; if ( mask_tmp != UINT16_MAX ) { flex_mask -> bitmask [ nb_bitmask ] . mask = ~ mask_tmp ; flex_mask -> bitmask [ nb_bitmask ] . offset = i / sizeof ( uint16_t ) ; nb_bitmask ++ ; } } } flxinset = ( flex_mask -> word_mask << I40E_PRTQF_FD_FLXINSET_INSET_SHIFT ) & I40E_PRTQF_FD_FLXINSET_INSET_MASK ; i40e_write_rx_ctl ( hw , I40E_PRTQF_FD_FLXINSET ( pctype ) , flxinset ) ; for ( i = 0 ; i < nb_bitmask ; i ++ ) { fd_mask = ( flex_mask -> bitmask [ i ] . mask << I40E_PRTQF_FD_MSK_MASK_SHIFT ) & I40E_PRTQF_FD_MSK_MASK_MASK ; fd_mask |= ( ( flex_mask -> bitmask [ i ] . offset + I40E_FLX_OFFSET_IN_FIELD_VECTOR ) << I40E_PRTQF_FD_MSK_OFFSET_SHIFT ) & I40E_PRTQF_FD_MSK_OFFSET_MASK ; i40e_write_rx_ctl ( hw , I40E_PRTQF_FD_MSK ( pctype , i ) , fd_mask ) ; } }
i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 @pf: board private structure
 @pctype: packet classify type
 @flex_masks: mask for flexible payload
i40e_set_flex_mask_on_pctype - configure the mask on flexible payload @pf : board private structure @pctype : packet classify type @flex_masks : mask for flexible payload
/* set bit mask */ /* write mask to hw */