src/dpdk/drivers/net/cxgbe/base/t4_hw.c
int t4_init_tp_params(struct adapter *adap)
{
	int chan, ret;
	u32 param, v;

	v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
	adap->params.tp.tre = G_TIMERRESOLUTION(v);
	adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);

	/* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
	for (chan = 0; chan < NCHAN; chan++)
		adap->params.tp.tx_modq[chan] = chan;

	/*
	 * Cache the adapter's Compressed Filter Mode/Mask and global Ingress
	 * Configuration.
	 */
	param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
		 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
		 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK));

	/* Read current value */
	ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
			      1, &param, &v);
	if (!ret) {
		dev_info(adap, "Current filter mode/mask 0x%x:0x%x\n",
			 G_FW_PARAMS_PARAM_FILTER_MODE(v),
			 G_FW_PARAMS_PARAM_FILTER_MASK(v));
		adap->params.tp.vlan_pri_map =
			G_FW_PARAMS_PARAM_FILTER_MODE(v);
		adap->params.tp.filter_mask =
			G_FW_PARAMS_PARAM_FILTER_MASK(v);
	} else {
		dev_info(adap,
			 "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");

		/* In case of older-fw (which doesn't expose the api
		 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
		 * the fw api) combination, fall-back to older method of reading
		 * the filter mode from indirect-register
		 */
		t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
				 &adap->params.tp.vlan_pri_map, 1,
				 A_TP_VLAN_PRI_MAP);

		/* With the older-fw and newer-driver combination we might run
		 * into an issue when user wants to use hash filter region but
		 * the filter_mask is zero, in this case filter_mask validation
		 * is tough. To avoid that we set the filter_mask same as filter
		 * mode, which will behave exactly as the older way of ignoring
		 * the filter mask validation.
		 */
		adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
	}

	t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
			 &adap->params.tp.ingress_config, 1,
			 A_TP_INGRESS_CONFIG);

	/* For T6, cache the adapter's compressed error vector
	 * and passing outer header info for encapsulated packets.
	 */
	if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
		v = t4_read_reg(adap, A_TP_OUT_CONFIG);
		adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
	}

	/*
	 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
	 * shift positions of several elements of the Compressed Filter Tuple
	 * for this adapter which we need frequently ...
	 */
	adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
	adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
	adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
	adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
							       F_PROTOCOL);
	adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
								F_ETHERTYPE);
	adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
							       F_MACMATCH);
	adap->params.tp.tos_shift = t4_filter_field_shift(adap, F_TOS);

	v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
	adap->params.tp.hash_filter_mask = v;
	v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
	adap->params.tp.hash_filter_mask |= ((u64)v << 32);

	return 0;
}
/**
 * t4_init_tp_params - initialize adap->params.tp
 * @adap: the adapter
 *
 * Initialize various fields of the adapter's TP Parameters structure.
 */
initialize adap->params.tp
@adap: the adapter

Initialize various fields of the adapter's TP Parameters structure.
initialize adap - > params . tp @adap : the adapter Initialize various fields of the adapter ' s TP Parameters structure .
int t4_init_tp_params(struct adapter *adap)
{
	int chan, ret;
	u32 param, v;
	v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
	adap->params.tp.tre = G_TIMERRESOLUTION(v);
	adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
	for (chan = 0; chan < NCHAN; chan++)
		adap->params.tp.tx_modq[chan] = chan;
	param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
		 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
		 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK));
	ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
			      1, &param, &v);
	if (!ret) {
		dev_info(adap, "Current filter mode/mask 0x%x:0x%x\n",
			 G_FW_PARAMS_PARAM_FILTER_MODE(v),
			 G_FW_PARAMS_PARAM_FILTER_MASK(v));
		adap->params.tp.vlan_pri_map =
			G_FW_PARAMS_PARAM_FILTER_MODE(v);
		adap->params.tp.filter_mask =
			G_FW_PARAMS_PARAM_FILTER_MASK(v);
	} else {
		dev_info(adap,
			 "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");
		t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
				 &adap->params.tp.vlan_pri_map, 1,
				 A_TP_VLAN_PRI_MAP);
		adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
	}
	t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
			 &adap->params.tp.ingress_config, 1,
			 A_TP_INGRESS_CONFIG);
	if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
		v = t4_read_reg(adap, A_TP_OUT_CONFIG);
		adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
	}
	adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
	adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
	adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
	adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
							       F_PROTOCOL);
	adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
								F_ETHERTYPE);
	adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
							       F_MACMATCH);
	adap->params.tp.tos_shift = t4_filter_field_shift(adap, F_TOS);
	v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
	adap->params.tp.hash_filter_mask = v;
	v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
	adap->params.tp.hash_filter_mask |= ((u64)v << 32);
	return 0;
}
int t4_init_tp_params ( struct adapter * adap ) { int chan , ret ; u32 param , v ; v = t4_read_reg ( adap , A_TP_TIMER_RESOLUTION ) ; adap -> params . tp . tre = G_TIMERRESOLUTION ( v ) ; adap -> params . tp . dack_re = G_DELAYEDACKRESOLUTION ( v ) ; for ( chan = 0 ; chan < NCHAN ; chan ++ ) adap -> params . tp . tx_modq [ chan ] = chan ; param = ( V_FW_PARAMS_MNEM ( FW_PARAMS_MNEM_DEV ) | V_FW_PARAMS_PARAM_X ( FW_PARAMS_PARAM_DEV_FILTER ) | V_FW_PARAMS_PARAM_Y ( FW_PARAM_DEV_FILTER_MODE_MASK ) ) ; ret = t4_query_params ( adap , adap -> mbox , adap -> pf , 0 , 1 , & param , & v ) ; if ( ! ret ) { dev_info ( adap , " \n " , G_FW_PARAMS_PARAM_FILTER_MODE ( v ) , G_FW_PARAMS_PARAM_FILTER_MASK ( v ) ) ; adap -> params . tp . vlan_pri_map = G_FW_PARAMS_PARAM_FILTER_MODE ( v ) ; adap -> params . tp . filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK ( v ) ; } else { dev_info ( adap , " \n " ) ; t4_read_indirect ( adap , A_TP_PIO_ADDR , A_TP_PIO_DATA , & adap -> params . tp . vlan_pri_map , 1 , A_TP_VLAN_PRI_MAP ) ; adap -> params . tp . filter_mask = adap -> params . tp . vlan_pri_map ; } t4_read_indirect ( adap , A_TP_PIO_ADDR , A_TP_PIO_DATA , & adap -> params . tp . ingress_config , 1 , A_TP_INGRESS_CONFIG ) ; if ( CHELSIO_CHIP_VERSION ( adap -> params . chip ) > CHELSIO_T5 ) { v = t4_read_reg ( adap , A_TP_OUT_CONFIG ) ; adap -> params . tp . rx_pkt_encap = ( v & F_CRXPKTENC ) ? 1 : 0 ; } adap -> params . tp . vlan_shift = t4_filter_field_shift ( adap , F_VLAN ) ; adap -> params . tp . vnic_shift = t4_filter_field_shift ( adap , F_VNIC_ID ) ; adap -> params . tp . port_shift = t4_filter_field_shift ( adap , F_PORT ) ; adap -> params . tp . protocol_shift = t4_filter_field_shift ( adap , F_PROTOCOL ) ; adap -> params . tp . ethertype_shift = t4_filter_field_shift ( adap , F_ETHERTYPE ) ; adap -> params . tp . macmatch_shift = t4_filter_field_shift ( adap , F_MACMATCH ) ; adap -> params . tp . tos_shift = t4_filter_field_shift ( adap , F_TOS ) ; v = t4_read_reg ( adap , LE_3_DB_HASH_MASK_GEN_IPV4_T6_A ) ; adap -> params . tp . hash_filter_mask = v ; v = t4_read_reg ( adap , LE_4_DB_HASH_MASK_GEN_IPV4_T6_A ) ; adap -> params . tp . hash_filter_mask |= ( ( u64 ) v << 32 ) ; return 0 ; }
t4_init_tp_params - initialize adap->params.tp
 @adap: the adapter
t4_init_tp_params - initialize adap - > params . tp @adap : the adapter
/* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ /*
	 * Cache the adapter's Compressed Filter Mode/Mask and global Ingress
	 * Configuration.
	 */ /* Read current value */ /* In case of older-fw (which doesn't expose the api
		 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
		 * the fw api) combination, fall-back to older method of reading
		 * the filter mode from indirect-register
		 */ /* With the older-fw and newer-driver combination we might run
		 * into an issue when user wants to use hash filter region but
		 * the filter_mask is zero, in this case filter_mask validation
		 * is tough. To avoid that we set the filter_mask same as filter
		 * mode, which will behave exactly as the older way of ignoring
		 * the filter mask validation.
		 */ /* For T6, cache the adapter's compressed error vector
	 * and passing outer header info for encapsulated packets.
	 */ /*
	 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
	 * shift positions of several elements of the Compressed Filter Tuple
	 * for this adapter which we need frequently ...
	 */