String[] verilogWords = {"module", "endmodule", "assign", "always", "initial", "wire", "reg", "event", "input", "output", "inout", "time", "if", "else", "for", "while", "case", "endcase", "function", "endfunction", "task", "endtask", "begin", "end", "parameter", "fork", "join", "integer", "posedge", "negedge", "forever", "repeat"};  String[] vhdlWords = {"begin", "end", "if", "else", "for", "while", "case", "library", "use", "entity", "architecture", "is", "of", "generic", "port", "process", "constant", "procedure", "signal", "shared", "variable", "type", "subtype", "file", "alias", "attribute", "component", "disconnect", "group", "block", "assert", "generate", "with", "elsif", "in", "out", "inout", "buffer", "linkage", "return", "when", "then", "and", "or", "to", "downto", "map"};
	private HdlScanner(ColorManager manager, boolean isVerilog)	{		IToken keyword = new Token(HdlTextAttribute.KEY_WORD				.getTextAttribute(manager));		IToken other = new Token(HdlTextAttribute.DEFAULT				.getTextAttribute(manager));		List rules = new ArrayList();		WordRule wordRule = new WordRule(new IWordDetector()		{			public boolean isWordPart(char character)			{				return Character.isJavaIdentifierPart(character);			}			public boolean isWordStart(char character)			{				return Character.isJavaIdentifierStart(character);			}		}, other);		String[] verilogWords = {"module", "endmodule", "assign", "always",				"initial", "wire", "reg", "event", "input", "output", "inout",				"time", "if", "else", "for", "while", "case", "endcase",				"function", "endfunction", "task", "endtask", "begin", "end",				"parameter", "fork", "join", "integer", "posedge", "negedge",				"forever", "repeat"};		String[] vhdlWords = {"begin", "end", "if", "else", "for", "while",				"case", "library", "use", "entity", "architecture", "is", "of",				"generic", "port", "process", "constant", "procedure",				"signal", "shared", "variable", "type", "subtype", "file",				"alias", "attribute", "component", "disconnect", "group",				"block", "assert", "generate", "with", "elsif", "in", "out",				"inout", "buffer", "linkage", "return", "when", "then", "and",				"or", "to", "downto", "map"};		if (isVerilog)		{			for (int i = 0; i < verilogWords.length; i++)				wordRule.addWord(verilogWords[i], keyword);		}		else		{			for (int i = 0; i < vhdlWords.length; i++)				wordRule.addWord(vhdlWords[i], keyword);			// it is possible to use upper case in VHDL			for (int i = 0; i < vhdlWords.length; i++)				wordRule.addWord(vhdlWords[i].toUpperCase(), keyword);		}		rules.add(wordRule);		IRule[] result = new IRule[rules.size()];		rules.toArray(result);		setRules(result);	}