if (VM.VerifyAssertions) VM._assert(false);
  protected final void USHR_SHL(OPT_Instruction s,                                 OPT_RegisterOperand def,                                 OPT_RegisterOperand left,                                 OPT_IntConstantOperand shift1,                                 OPT_IntConstantOperand shift2) {    int x = shift1.value;    int y = shift2.value;    if (x <= y) {      //-#if RVM_FOR_64_ADDR      EMIT(MIR_RotateAndMask.create(PPC64_RLDICR, def, left,                                     IC(y - x), IC(0), IC(63 - y)));       //-#elif RVM_FOR_32_ADDR      EMIT(MIR_RotateAndMask.create(PPC_RLWINM, def, left,                                     IC(y - x), IC(0), IC(31 - y)));       //-#endif    } else {      //-#if RVM_FOR_64_ADDR      if (VM.VerifyAssertions) VM._assert(false);      //-#elif RVM_FOR_32_ADDR      EMIT(MIR_RotateAndMask.create(PPC_RLWINM, def, left,                                     IC((32 - (x - y)) & 0x1f),                                     IC(x - y), IC(31 - y)));      //-#endif    }  }