EMIT(MIR_Binary.create(operator, L(defReg), L(leftReg), L(rightReg)));
  protected final void LONG_LOG(OPT_Instruction s,                                 OPT_Operator operator,                                 OPT_RegisterOperand def,                                 OPT_RegisterOperand left,                                 OPT_RegisterOperand right) {    OPT_Register defReg = def.register;    OPT_Register leftReg = left.register;    OPT_Register rightReg = right.register;    EMIT(MIR_Binary.create(operator, R(defReg),                            R(leftReg), R(rightReg)));    EMIT(MIR_Binary.create(operator,                            R(regpool.getSecondReg(defReg)),                            R(regpool.getSecondReg(leftReg)),                            R(regpool.getSecondReg(rightReg))));  }