OPT_RegisterOperand op = MIR_Unary.getResult(s).asRegister();
  void addArchRestrictions(OPT_BasicBlock bb, ArrayList symbolics) {    // If there are any registers used in catch blocks, we want to ensure    // that these registers are not used or evicted from scratch registers    // at a relevant PEI, so that the assumptions of register homes in the    // catch block remain valid.  For now, we do this by forcing any    // register used in such a PEI as not spilled.  TODO: relax this    // restriction for better code.    for (OPT_InstructionEnumeration ie = bb.forwardInstrEnumerator();         ie.hasMoreElements(); ) {      OPT_Instruction s = ie.next();      if (s.isPEI() && s.operator != IR_PROLOGUE) {        if (bb.hasApplicableExceptionalOut(s) || !SCRATCH_IN_PEI) {          for (Enumeration e = s.getOperands(); e.hasMoreElements(); ) {            OPT_Operand op = (OPT_Operand)e.nextElement();            if (op != null && op.isRegister()) {              noteMustNotSpill(op.asRegister().register);              handle8BitRestrictions(s);            }          }        }      }      // handle special cases       switch (s.getOpcode()) {        case MIR_LOWTABLESWITCH_opcode:          {            OPT_RegisterOperand op = MIR_LowTableSwitch.getIndex(s);            noteMustNotSpill(op.register);          }          break;        case IA32_MOVZX__B_opcode: case IA32_MOVSX__B_opcode:          {            OPT_RegisterOperand op = MIR_Unary.getResult(s).asRegister();            if (MIR_Unary.getVal(s).isRegister()) {              OPT_RegisterOperand val = MIR_Unary.getVal(s).asRegister();              restrictTo8Bits(val.register);            }          }          break;        case IA32_SET__B_opcode:          {             if (MIR_Set.getResult(s).isRegister()) {              OPT_RegisterOperand op = MIR_Set.getResult(s).asRegister();              restrictTo8Bits(op.register);            }          }          break;        default:          handle8BitRestrictions(s);          break;      }    }    for (OPT_InstructionEnumeration ie = bb.forwardInstrEnumerator();         ie.hasMoreElements(); ) {      OPT_Instruction s = ie.next();      if (s.operator == IA32_FNINIT) {        // No floating point register survives across an FNINIT        for (Iterator sym = symbolics.iterator(); sym.hasNext(); ) {          OPT_LiveIntervalElement symb = (OPT_LiveIntervalElement) sym.next();          if (symb.getRegister().isFloatingPoint()) {            if (contains(symb,s.scratch)) {              addRestrictions(symb.getRegister(),phys.getFPRs());            }          }        }      } else if (s.operator == IA32_FCLEAR) {        // Only some FPRs survive across an FCLEAR        for (Iterator sym = symbolics.iterator(); sym.hasNext(); ) {          OPT_LiveIntervalElement symb = (OPT_LiveIntervalElement) sym.next();          if (symb.getRegister().isFloatingPoint()) {            if (contains(symb,s.scratch)) {              int nSave = MIR_UnaryNoRes.getVal(s).asIntConstant().value;              for (int i = nSave; i < NUM_FPRS; i++) {                addRestriction(symb.getRegister(), phys.getFPR(i));              }            }          }        }      }    }  }