EMIT(CPOS(s,MIR_CondMove.create(IA32_CMOV, R(lval),R(hval), OPT_IA32ConditionOperand.NE()))); EMIT(MIR_CondMove.mutate(s,IA32_CMOV, R(hval), bit63.copyRO(), OPT_IA32ConditionOperand.NE()));
EMIT(CPOS(s,MIR_CondMove.create(IA32_CMOV, new OPT_RegisterOperand(lval, VM_TypeReference.Int), new OPT_RegisterOperand(hval, VM_TypeReference.Int), OPT_IA32ConditionOperand.NE()))); EMIT(MIR_CondMove.mutate(s,IA32_CMOV, new OPT_RegisterOperand(hval, VM_TypeReference.Int), bit63.copyRO(), OPT_IA32ConditionOperand.NE()));
  protected final void LONG_SHR(OPT_Instruction s) {    OPT_Register hval = BinaryAcc.getResult(s).register;    OPT_Register lval = burs.ir.regpool.getSecondReg(hval);    OPT_Operand shiftOp = BinaryAcc.getClearValue(s);        if (shiftOp instanceof OPT_IntConstantOperand) {      int shift = ((OPT_IntConstantOperand)shiftOp).value;      shift = shift & 0x3F; // only bottom six bits matter;      if (shift == 0) {        s.remove(); // operation is a nop.		} else if (shift == 1) {        EMIT(CPOS(s,MIR_BinaryAcc.create(IA32_SAR, R(hval), IC(1))));        EMIT(MIR_BinaryAcc.mutate(s,IA32_RCR, R(lval), IC(1)));		} else if (shift == 32) {        EMIT(CPOS(s,MIR_Move.create(IA32_MOV, R(lval), R(hval))));        EMIT(MIR_BinaryAcc.mutate(s, IA32_SAR, R(hval), IC(31)));      } else if (shift > 32) {        EMIT(CPOS(s,MIR_Move.create(IA32_MOV, R(lval), R(hval))));        EMIT(CPOS(s,MIR_BinaryAcc.create(IA32_SAR, R(lval), IC(shift-32))));        EMIT(MIR_BinaryAcc.mutate(s, IA32_SAR, R(hval), IC(31)));      } else {        EMIT(CPOS(s,MIR_DoubleShift.create(IA32_SHRD, R(lval), R(hval), IC(shift))));        EMIT(MIR_BinaryAcc.mutate(s, IA32_SAR, R(hval), IC(shift)));      }    } else {      OPT_RegisterOperand bit63 = burs.ir.regpool.makeTempInt();      OPT_Register ecx = getECX();		// Set up ecx and bit63      EMIT(CPOS(s,MIR_Move.create(IA32_MOV, R(ecx), shiftOp)));      EMIT(CPOS(s,MIR_Move.create(IA32_MOV, bit63, R(hval))));      EMIT(CPOS(s,MIR_BinaryAcc.create(IA32_SAR, bit63.copyRO(), IC(31))));		// Perform shift      EMIT(CPOS(s,MIR_DoubleShift.create(IA32_SHRD, R(lval), R(hval), R(ecx))));      EMIT(CPOS(s,MIR_BinaryAcc.create(IA32_SAR, R(hval), R(ecx))));		// Check for > 32bit shift		EMIT(CPOS(s,MIR_Test.create(IA32_TEST, R(ecx), IC(32)))); // ZF = ((ecx & 32) != 0)		// if (shift > 32) {lval = hval; hval = bit63}		EMIT(CPOS(s,MIR_CondMove.create(IA32_CMOV, R(lval),R(hval), OPT_IA32ConditionOperand.NE()))); // ZF == 0		EMIT(MIR_CondMove.mutate(s,IA32_CMOV, R(hval), bit63.copyRO(), OPT_IA32ConditionOperand.NE())); // ZF == 0    }  }