OPT_RegisterOperand op = LowTableSwitch.getIndex(s);
OPT_RegisterOperand op = MIR_LowTableSwitch.getIndex(s);
  protected void processBlock(OPT_BasicBlock bb) {    // first process the default register restrictions    super.processBlock(bb);        // If there are any registers used in catch blocks, we want to ensure    // that these registers are not used or evicted from scratch registers    // at a relevant PEI, so that the assumptions of register homes in the    // catch block remain valid.  For now, we do this by forcing any    // register used in such a PEI as not spilled.  TODO: relax this    // restriction for better code.    for (OPT_InstructionEnumeration ie = bb.forwardInstrEnumerator();         ie.hasMoreElements(); ) {      OPT_Instruction s = ie.next();      if (s.isPEI() && s.operator != IR_PROLOGUE) {        if (bb.hasApplicableExceptionalOut(s) || !SCRATCH_IN_PEI) {          for (Enumeration e = s.getOperands(); e.hasMoreElements(); ) {            OPT_Operand op = (OPT_Operand)e.nextElement();            if (op != null && op.isRegister()) {              noteMustNotSpill(op.asRegister().register);            }          }        }      }      // handle special cases for IA32      // These fall into two classes:      //  (1) Some operands must be in registers      //  (2) Some register operands must be in eax,ebx,ecx,or edx      //      because they are really 8 bit registers (al,bl,cl,dl).      //      This happens in a few special cases (MOVZX/MOZSX/SET)      //      and in any other operator that has an 8 bit memory operand.      switch (s.getOpcode()) {      case IA32_SHRD_opcode: case IA32_SHLD_opcode:	{	  OPT_RegisterOperand op = MIR_DoubleShift.getSource(s);	  noteMustNotSpill(op.register);	}	break;      case IA32_FCOMI_opcode: case IA32_FCOMIP_opcode:	{	  OPT_Operand op = MIR_Compare.getVal2(s);	  if (!(op instanceof OPT_BURSManagedFPROperand)) {	    noteMustNotSpill(op.asRegister().register);	  }	}	break;      case IA32_IMUL2_opcode:	{ 	  OPT_RegisterOperand op = MIR_BinaryAcc.getResult(s).asRegister();	  noteMustNotSpill(op.register);	}	break;      case IA32_LOWTABLESWITCH_opcode:	{	  OPT_RegisterOperand op = LowTableSwitch.getIndex(s);	  noteMustNotSpill(op.register);	}	break;      case IA32_CMOV_opcode: case IA32_FCMOV_opcode:	{	  OPT_RegisterOperand op = MIR_CondMove.getResult(s).asRegister();	  noteMustNotSpill(op.register);	}	break;      case IA32_MOVZX$B_opcode: case IA32_MOVSX$B_opcode:	{	  OPT_RegisterOperand op = MIR_Unary.getResult(s).asRegister();	  noteMustNotSpill(op.register);	  if (MIR_Unary.getVal(s).isRegister()) {	    OPT_RegisterOperand val = MIR_Unary.getVal(s).asRegister();	    restrictTo8Bits(val.register);	  }	}	break;      case IA32_MOVZX$W_opcode: case IA32_MOVSX$W_opcode:	{ 	  OPT_RegisterOperand op = MIR_Unary.getResult(s).asRegister();	  noteMustNotSpill(op.register);	}	break;      case IA32_SET$B_opcode:	{ 	  if (MIR_Set.getResult(s).isRegister()) {	    OPT_RegisterOperand op = MIR_Set.getResult(s).asRegister();	    restrictTo8Bits(op.register);	  }	}	break;      default:	{	  for (OPT_OperandEnumeration me = s.getMemoryOperands(); 	       me.hasMoreElements(); ) {	    OPT_MemoryOperand mop = (OPT_MemoryOperand)me.next();	    if (mop.size == 1) {	      for (OPT_OperandEnumeration e2 = s.getRootOperands(); 		   e2.hasMoreElements(); ) {		OPT_Operand rootOp = e2.next();		if (rootOp.isRegister()) {		  restrictTo8Bits(rootOp.asRegister().register);		}	      }	    }	  }	}	break;      }    }  }