if (VM.VerifyAssertions) VM.assert(imm < (0x8000 - 4));
if (VM.VerifyAssertions) VM._assert(imm < (0x8000 - 4));
  void LONG_LOAD_addi(OPT_BURS burs, OPT_Instruction s, 		      OPT_RegisterOperand def, 		      OPT_RegisterOperand left, 		      OPT_IntConstantOperand right, 		      OPT_LocationOperand loc, 		      OPT_Operand guard) {    OPT_Register defHigh = def.register;    OPT_Register defLow = burs.ir.regpool.getSecondReg(defHigh);    int imm = right.value;    if (VM.VerifyAssertions) VM.assert(imm < (0x8000 - 4));    OPT_Instruction inst = OPT_IRTools.nonPEIGC (MIR_Load.create						    (PPC_LWZ, 						     R(defHigh), 						     left, I(imm), loc, 						     guard));    inst.copyPosition(s);    burs.append(inst);    if (loc != null) {      loc = (OPT_LocationOperand)loc.copy();    }    inst = OPT_IRTools.nonPEIGC (MIR_Load.create(PPC_LWZ, 						    R(defLow), 						    left.copyU2U(), 						    I(imm + 4), loc, 						    guard));    inst.copyPosition(s);    burs.append(inst);  }