if (VM.VerifyAssertions) VM._assert(false);
  protected final void SHL_USHR(OPT_Instruction s,                                 OPT_RegisterOperand def,                                 OPT_RegisterOperand left,                                 OPT_IntConstantOperand shift1,                                 OPT_IntConstantOperand shift2) {    int x = shift1.value;    int y = shift2.value;    if (x <= y) {      //-#if RVM_FOR_64_ADDR      EMIT(MIR_RotateAndMask.create(PPC64_RLDICL, def, left,                                     IC(64 - (y - x)), IC(y), IC(63)));       //-#elif RVM_FOR_32_ADDR      EMIT(MIR_RotateAndMask.create(PPC_RLWINM, def, left,                                     IC((32 - (y - x)) & 0x1f),                                     IC(y), IC(31)));       //-#endif    } else {      //-#if RVM_FOR_64_ADDR      if (VM.VerifyAssertions) VM._assert(false);      //-#elif RVM_FOR_32_ADDR      EMIT(MIR_RotateAndMask.create(PPC_RLWINM, def, left,                                     IC(x - y), IC(y), IC(31 - (x - y))));      //-#endif    }  }