what are the different layers of layered architecture in sv?
['signal layer: This layer connects the TestBench to the RTL design. ... ', 'command layer: This layer contains lower-level driver and monitor components, as well as the assertions. ... ', 'functional layer: ... ', 'scenario layer: ... ', 'test layer: ... ', 'VMM Standard Library.', 'VMM Register Abstraction Layer (RAL)', 'VMM Hardware Abstraction Layer (HAL)']