data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n             data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:10: Define or directive not defined: \'`MemAddrWidth\'\n  input wire[`MemAddrWidth-1:0] inst_addr,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:11: Define or directive not defined: \'`MemAddrWidth\'\n  input wire[`MemAddrWidth-1:0] data_addr,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:12: Define or directive not defined: \'`RegDataBytes\'\n  input wire[`RegDataBytes-1:0] write_data_mask,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:13: Define or directive not defined: \'`RegDataWidth\'\n  input wire[`RegDataWidth-1:0] write_data_value,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:15: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] inst_value,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:16: Define or directive not defined: \'`RegDataWidth\'\n  output reg[`RegDataWidth-1:0] read_data_value,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:83: Define or directive not defined: \'`MemRead\'\n     if(data_optype == `MemRead) begin\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:83: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     if(data_optype == `MemRead) begin\n                               ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:89: syntax error, unexpected begin, expecting assert or assume or cover or restrict\n    CS_DATA_VALUE: begin\n                   ^~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:90: Define or directive not defined: \'`MemWrite\'\n     if(data_optype == `MemWrite) begin\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:110: Define or directive not defined: \'`No\'\n   busy <= `No;\n           ^~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:117: Define or directive not defined: \'`Yes\'\n    busy <= `Yes;\n            ^~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:119: Define or directive not defined: \'`No\'\n    busy <= `No;\n            ^~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:135: Define or directive not defined: \'`SendDisable\'\n   uart_send_flag <= `SendDisable;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:135: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   uart_send_flag <= `SendDisable;\n                                 ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:136: Define or directive not defined: \'`RecvDisable\'\n   uart_recv_flag <= `RecvDisable;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:136: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   uart_recv_flag <= `RecvDisable;\n                                 ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:144: Define or directive not defined: \'`SendDisable\'\n      uart_send_flag <= `SendDisable;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:144: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      uart_send_flag <= `SendDisable;\n                                    ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:145: Define or directive not defined: \'`RecvDisable\'\n   uart_recv_flag <= `RecvDisable;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:145: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   uart_recv_flag <= `RecvDisable;\n                                 ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:161: Define or directive not defined: \'`SendEnable\'\n      uart_send_flag <= `SendEnable;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:161: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      uart_send_flag <= `SendEnable;\n                                   ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:190: Define or directive not defined: \'`MemRead\'\n     if (data_optype == `MemRead) begin\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:190: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     if (data_optype == `MemRead) begin\n                                ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:192: Define or directive not defined: \'`RecvEnable\'\n       uart_recv_flag <= `RecvEnable;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:216: syntax error, unexpected else, expecting endcase\n      end else begin\n          ^~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:220: syntax error, unexpected else\n     end else begin\n         ^~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:222: Define or directive not defined: \'`SendEnable\'\n       uart_send_flag <= `SendEnable;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:228: syntax error, unexpected <=, expecting IDENTIFIER\n                              uart_send_data <= write_data_value[7:0];\n                                             ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:230: syntax error, unexpected <=, expecting IDENTIFIER\n                              uart_send_data <= write_data_value[15:8];\n                                             ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:232: syntax error, unexpected <=, expecting IDENTIFIER\n                              uart_send_data <= write_data_value[23:16];\n                                             ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:234: syntax error, unexpected <=, expecting IDENTIFIER\n                              uart_send_data <= write_data_value[31:24];\n                                             ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:236: syntax error, unexpected <=, expecting IDENTIFIER\n        next_disp <= 0;\n                  ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:238: syntax error, unexpected <=, expecting IDENTIFIER\n         next_status <= CS_INST_HEAD;\n                     ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:240: syntax error, unexpected <=, expecting IDENTIFIER\n         next_status <= CS_OUTPUT;\n                     ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:244: syntax error, unexpected <=, expecting IDENTIFIER\n        next_status <= cur_status;\n                    ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:255: Define or directive not defined: \'`SendEnable\'\n      uart_send_flag <= `SendEnable;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:261: syntax error, unexpected <=, expecting IDENTIFIER\n        uart_send_data <= cur_head[7:0];\n                       ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:263: syntax error, unexpected <=, expecting IDENTIFIER\n        uart_send_data <= cur_head[15:8];\n                       ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:265: syntax error, unexpected <=, expecting IDENTIFIER\n        uart_send_data <= cur_head[23:16];\n                       ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:267: syntax error, unexpected <=, expecting IDENTIFIER\n        uart_send_data <= cur_head[31:24];\n                       ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:269: syntax error, unexpected <=, expecting IDENTIFIER\n        uart_send_data <= cur_head[39:32];\n                       ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:271: syntax error, unexpected <=, expecting IDENTIFIER\n       next_status <= CS_INST_VALUE;\n                   ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:275: syntax error, unexpected <=, expecting IDENTIFIER\n       next_status <= cur_status;\n                   ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:285: Define or directive not defined: \'`RecvEnable\'\n      uart_recv_flag <= `RecvEnable;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:291: syntax error, unexpected \'[\', expecting IDENTIFIER\n        inst_value[7:0] <= uart_recv_data;\n                  ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:293: syntax error, unexpected \'[\', expecting IDENTIFIER\n        inst_value[15:8] <= uart_recv_data;\n                  ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:295: syntax error, unexpected \'[\', expecting IDENTIFIER\n        inst_value[23:16] <= uart_recv_data;\n                  ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module cache(
		input wire clk,
		input wire rst,

		input wire inst_ce, data_ce,
		input wire data_optype,
		input wire[`MemAddrWidth-1:0] inst_addr,
		input wire[`MemAddrWidth-1:0] data_addr,
		input wire[`RegDataBytes-1:0] write_data_mask,
		input wire[`RegDataWidth-1:0] write_data_value,

		output reg[`RegDataWidth-1:0] inst_value,
		output reg[`RegDataWidth-1:0] read_data_value,

		output reg busy,

		output wire Tx,
		input wire Rx
	);


	reg uart_send_flag, uart_recv_flag;
	reg[7:0] uart_send_data;
	wire[7:0] uart_recv_data;
	wire uart_receivable, uart_sendable;



    uart_comm uart0( 
            .CLK(clk),
            .RST(rst),
            .send_flag(uart_send_flag),
            .send_data(uart_send_data),
            .recv_flag(uart_recv_flag),
            .recv_data(uart_recv_data),
            .sendable(uart_sendable),
            .receivable(uart_receivable), 
            .Tx(Tx), 
            .Rx(Rx) );

	reg[39:0] cur_head;
	reg[31:0] cur_data;


	localparam CS_READY			=	4'd0;
	localparam CS_DATA_HEAD		=	4'd1;
	localparam CS_DATA_VALUE	=	4'd2;
	localparam CS_INST_HEAD		=	4'd3;
	localparam CS_INST_VALUE	=	4'd4;
	localparam CS_OUTPUT		=	4'd5;
	reg[3:0] cur_status;
	reg[2:0] cur_disp;
	reg[2:0] next_disp;
	reg[3:0] next_status;










	localparam READ_BIT		=	1'b0;
	localparam WRITE_BIT	=	1'b1;
	always @ (*) begin
		if (rst) begin
			cur_head <= 0;
			cur_data <= 0;
		end else begin
			cur_head <= 0;
			cur_data <= 0;
			case (cur_status) 
				CS_READY: begin
					cur_head <= 0;
					cur_data <= 0;
				end
				CS_DATA_HEAD: begin
					if(data_optype == `MemRead) begin
						cur_head <= {{4{READ_BIT}}, {4{1'b0}}, data_addr};
					end else begin
						cur_head <= {{4{WRITE_BIT}}, write_data_mask, data_addr};
					end
				end
				CS_DATA_VALUE: begin
					if(data_optype == `MemWrite) begin
						cur_data <= write_data_value;
					end 
				end
				CS_INST_HEAD: begin
					cur_head <= {{4{READ_BIT}}, {4{1'b0}}, inst_addr};
				end
			endcase
		end
	end








	always @ (*) begin
		if(rst) begin
			busy <= `No;
		end else begin
			if(		cur_status == CS_INST_HEAD 
				||	cur_status == CS_INST_VALUE
				||	cur_status == CS_DATA_HEAD
				||	cur_status == CS_DATA_VALUE
				||	(cur_status == CS_READY && (inst_ce || data_ce))) begin
				busy <= `Yes;
			end else begin
				busy <= `No;
			end
		end
	end




	integer index;
	localparam HeadFullDisp	=	3'b100;
	localparam DataFullDisp =	3'b011;

	always @ (*) begin
		if (rst) begin
			next_status <= CS_READY;
			next_disp	<= 0;
			uart_send_flag <= `SendDisable;
			uart_recv_flag <= `RecvDisable;
			uart_send_data <= 0;
			inst_value <= 0;
			read_data_value <= 0;
		end else begin
		    next_status <= cur_status;
		    next_disp   <= 0;
		    uart_send_data <= 0;
		    uart_send_flag <= `SendDisable;
			uart_recv_flag <= `RecvDisable;
			case (cur_status) 
				CS_READY: begin
					if (data_ce) begin
						next_status <= CS_DATA_HEAD;
						next_disp <= 0;
					end else if (inst_ce) begin
						next_status <= CS_INST_HEAD;
						next_disp <= 0;
					end else begin
						next_status <= CS_READY;
						next_disp <= 0;
					end
				end
				CS_DATA_HEAD: begin
					if (uart_sendable) begin
						uart_send_flag <= `SendEnable;

                        if(cur_disp == 3'b000) 
                          uart_send_data <= cur_head[7:0];
                        else if(cur_disp == 3'b001)
                          uart_send_data <= cur_head[15:8];
                        else if(cur_disp == 3'b010)
                          uart_send_data <= cur_head[23:16];
                        else if(cur_disp == 3'b011)
                          uart_send_data <= cur_head[31:24];
                        else
                          uart_send_data <= cur_head[39:32];
						if(cur_disp == HeadFullDisp) begin
							next_status <= CS_DATA_VALUE;
							next_disp <= 0;
							$display("[cache] send data head [%x]", cur_head);
						end else begin
							next_status <= cur_status;
							next_disp <= cur_disp + 1;
						end
					end else begin
						next_status <= cur_status;
						next_disp <= cur_disp;
					end
				end
				CS_DATA_VALUE: begin
					if (data_optype == `MemRead) begin
						if (uart_receivable) begin
							uart_recv_flag <= `RecvEnable;

                            if(cur_disp == 3'b000) 
                              read_data_value[7:0] <= uart_recv_data;
                            else if(cur_disp == 3'b001)
                              read_data_value[15:8] <= uart_recv_data;
                            else if(cur_disp == 3'b010)
                              read_data_value[23:16] <= uart_recv_data;
                            else
                              read_data_value[31:24] <= uart_recv_data;
							if(cur_disp == DataFullDisp) begin
								next_disp <= 0;
								if(inst_ce)
									next_status <= CS_INST_HEAD;
								else
									next_status <= CS_OUTPUT;
								$display("[cache] recv data value [%x]", {uart_recv_data,read_data_value[23:0]});
							end else begin
								next_status <= cur_status;
								next_disp <= cur_disp + 1;
							end
						end else begin
							next_status <= cur_status;
							next_disp <= cur_disp;
						end
					end else begin
						if (uart_sendable) begin
							uart_send_flag <= `SendEnable;

							if(cur_disp == 3'b000) 
                              uart_send_data <= write_data_value[7:0];
                            else if(cur_disp == 3'b001)
                              uart_send_data <= write_data_value[15:8];
                            else if(cur_disp == 3'b010)
                              uart_send_data <= write_data_value[23:16];
                            else 
                              uart_send_data <= write_data_value[31:24];
							if(cur_disp == DataFullDisp) begin
								next_disp <= 0;
								if(inst_ce) begin
									next_status <= CS_INST_HEAD;
								end else begin
									next_status <= CS_OUTPUT;
								end
								$display("[cache] send data value [%x]", write_data_value);
							end else begin
								next_status <= cur_status;
								next_disp <= cur_disp + 1;
							end
						end else begin
							next_status <= cur_status;
							next_disp <= cur_disp;
						end
					end
				end
				CS_INST_HEAD: begin
					if (uart_sendable) begin
						uart_send_flag <= `SendEnable;

						if(cur_disp == 3'b000) 
						  uart_send_data <= cur_head[7:0];
						else if(cur_disp == 3'b001)
						  uart_send_data <= cur_head[15:8];
						else if(cur_disp == 3'b010)
						  uart_send_data <= cur_head[23:16];
						else if(cur_disp == 3'b011)
						  uart_send_data <= cur_head[31:24];
						else
						  uart_send_data <= cur_head[39:32];
						if(cur_disp == HeadFullDisp) begin
							next_status <= CS_INST_VALUE;
							next_disp <= 0;
							$display("[cache] send inst head [%x]", cur_head);
						end else begin
							next_status <= cur_status;
							next_disp <= cur_disp + 1;
						end
					end else begin
						next_status <= cur_status;
						next_disp <= cur_disp;
					end
				end
				CS_INST_VALUE: begin
					if (uart_receivable) begin
						uart_recv_flag <= `RecvEnable;

						if(cur_disp == 3'b000) 
						  inst_value[7:0] <= uart_recv_data;
						else if(cur_disp == 3'b001)
						  inst_value[15:8] <= uart_recv_data;
						else if(cur_disp == 3'b010)
						  inst_value[23:16] <= uart_recv_data;
						else
						  inst_value[31:24] <= uart_recv_data;
						if(cur_disp == DataFullDisp) begin
							next_disp <= 0;
							next_status <= CS_OUTPUT;
							$display("[cache] recv inst value [%x]", {uart_recv_data,inst_value[23:0]});
						end else begin
							next_status <= cur_status;
							next_disp <= cur_disp + 1;
						end
					end else begin
						next_status <= cur_status;
						next_disp <= cur_disp;
					end
				end
				CS_OUTPUT: begin
					$display("[cache] cur_status: CS_OUTPUT");
					next_status <= CS_READY;
					next_disp <= 0;
				end
			endcase
		end
	end





	always @ (posedge clk) begin
		if(rst) begin
			cur_status <= CS_READY;
			cur_disp <= 0;
		end else begin
			cur_status <= next_status;
			cur_disp <= next_disp;
		end
	end
endmodule
module cache(
		input wire clk,
		input wire rst,

		input wire inst_ce, data_ce,
		input wire data_optype,
		input wire[`MemAddrWidth-1:0] inst_addr,
		input wire[`MemAddrWidth-1:0] data_addr,
		input wire[`RegDataBytes-1:0] write_data_mask,
		input wire[`RegDataWidth-1:0] write_data_value,

		output reg[`RegDataWidth-1:0] inst_value,
		output reg[`RegDataWidth-1:0] read_data_value,

		output reg busy,

		output wire Tx,
		input wire Rx
	);



	reg uart_send_flag, uart_recv_flag;
	reg[7:0] uart_send_data;
	wire[7:0] uart_recv_data;
	wire uart_receivable, uart_sendable;



    uart_comm uart0( 
            .CLK(clk),
            .RST(rst),
            .send_flag(uart_send_flag),
            .send_data(uart_send_data),
            .recv_flag(uart_recv_flag),
            .recv_data(uart_recv_data),
            .sendable(uart_sendable),
            .receivable(uart_receivable), 
            .Tx(Tx), 
            .Rx(Rx) );

	reg[39:0] cur_head;
	reg[31:0] cur_data;


	localparam CS_READY			=	4'd0;
	localparam CS_DATA_HEAD		=	4'd1;
	localparam CS_DATA_VALUE	=	4'd2;
	localparam CS_INST_HEAD		=	4'd3;
	localparam CS_INST_VALUE	=	4'd4;
	localparam CS_OUTPUT		=	4'd5;
	reg[3:0] cur_status;
	reg[2:0] cur_disp;
	reg[2:0] next_disp;
	reg[3:0] next_status;










	localparam READ_BIT		=	1'b0;
	localparam WRITE_BIT	=	1'b1;
	always @ (*) begin
		if (rst) begin
			cur_head <= 0;
			cur_data <= 0;
		end else begin
			cur_head <= 0;
			cur_data <= 0;
			case (cur_status) 
				CS_READY: begin
					cur_head <= 0;
					cur_data <= 0;
				end
				CS_DATA_HEAD: begin
					if(data_optype == `MemRead) begin
						cur_head <= {{4{READ_BIT}}, {4{1'b0}}, data_addr};
					end else begin
						cur_head <= {{4{WRITE_BIT}}, write_data_mask, data_addr};
					end
				end
				CS_DATA_VALUE: begin
					if(data_optype == `MemWrite) begin
						cur_data <= write_data_value;
					end 
				end
				CS_INST_HEAD: begin
					cur_head <= {{4{READ_BIT}}, {4{1'b0}}, inst_addr};
				end
			endcase
		end
	end








	always @ (*) begin
		if(rst) begin
			busy <= `No;
		end else begin
			if(		cur_status == CS_INST_HEAD 
				||	cur_status == CS_INST_VALUE
				||	cur_status == CS_DATA_HEAD
				||	cur_status == CS_DATA_VALUE
				||	(cur_status == CS_READY && (inst_ce || data_ce))) begin
				busy <= `Yes;
			end else begin
				busy <= `No;
			end
		end
	end




	integer index;
	localparam HeadFullDisp	=	3'b100;
	localparam DataFullDisp =	3'b011;

	always @ (*) begin
		if (rst) begin
			next_status <= CS_READY;
			next_disp	<= 0;
			uart_send_flag <= `SendDisable;
			uart_recv_flag <= `RecvDisable;
			uart_send_data <= 0;
			inst_value <= 0;
			read_data_value <= 0;
		end else begin
		    next_status <= cur_status;
		    next_disp   <= 0;
		    uart_send_data <= 0;
		    uart_send_flag <= `SendDisable;
			uart_recv_flag <= `RecvDisable;
			case (cur_status) 
				CS_READY: begin
					if (data_ce) begin
						next_status <= CS_DATA_HEAD;
						next_disp <= 0;
					end else if (inst_ce) begin
						next_status <= CS_INST_HEAD;
						next_disp <= 0;
					end else begin
						next_status <= CS_READY;
						next_disp <= 0;
					end
				end
				CS_DATA_HEAD: begin
					if (uart_sendable) begin
						uart_send_flag <= `SendEnable;

                        if(cur_disp == 3'b000) 
                          uart_send_data <= cur_head[7:0];
                        else if(cur_disp == 3'b001)
                          uart_send_data <= cur_head[15:8];
                        else if(cur_disp == 3'b010)
                          uart_send_data <= cur_head[23:16];
                        else if(cur_disp == 3'b011)
                          uart_send_data <= cur_head[31:24];
                        else
                          uart_send_data <= cur_head[39:32];
						if(cur_disp == HeadFullDisp) begin
							next_status <= CS_DATA_VALUE;
							next_disp <= 0;
							$display("[cache] send data head [%x]", cur_head);
						end else begin
							next_status <= cur_status;
							next_disp <= cur_disp + 1;
						end
					end else begin
						next_status <= cur_status;
						next_disp <= cur_disp;
					end
				end
				CS_DATA_VALUE: begin
					if (data_optype == `MemRead) begin
						if (uart_receivable) begin
							uart_recv_flag <= `RecvEnable;

                            if(cur_disp == 3'b000) 
                              read_data_value[7:0] <= uart_recv_data;
                            else if(cur_disp == 3'b001)
                              read_data_value[15:8] <= uart_recv_data;
                            else if(cur_disp == 3'b010)
                              read_data_value[23:16] <= uart_recv_data;
                            else
                              read_data_value[31:24] <= uart_recv_data;
							if(cur_disp == DataFullDisp) begin
								next_disp <= 0;
								if(inst_ce)
									next_status <= CS_INST_HEAD;
								else
									next_status <= CS_OUTPUT;
								$display("[cache] recv data value [%x]", {uart_recv_data,read_data_value[23:0]});
							end else begin
								next_status <= cur_status;
								next_disp <= cur_disp + 1;
							end
						end else begin
							next_status <= cur_status;
							next_disp <= cur_disp;
						end
					end else begin
						if (uart_sendable) begin
							uart_send_flag <= `SendEnable;

							if(cur_disp == 3'b000) 
                              uart_send_data <= write_data_value[7:0];
                            else if(cur_disp == 3'b001)
                              uart_send_data <= write_data_value[15:8];
                            else if(cur_disp == 3'b010)
                              uart_send_data <= write_data_value[23:16];
                            else 
                              uart_send_data <= write_data_value[31:24];
							if(cur_disp == DataFullDisp) begin
								next_disp <= 0;
								if(inst_ce) begin
									next_status <= CS_INST_HEAD;
								end else begin
									next_status <= CS_OUTPUT;
								end
								$display("[cache] send data value [%x]", write_data_value);
							end else begin
								next_status <= cur_status;
								next_disp <= cur_disp + 1;
							end
						end else begin
							next_status <= cur_status;
							next_disp <= cur_disp;
						end
					end
				end
				CS_INST_HEAD: begin
					if (uart_sendable) begin
						uart_send_flag <= `SendEnable;

						if(cur_disp == 3'b000) 
						  uart_send_data <= cur_head[7:0];
						else if(cur_disp == 3'b001)
						  uart_send_data <= cur_head[15:8];
						else if(cur_disp == 3'b010)
						  uart_send_data <= cur_head[23:16];
						else if(cur_disp == 3'b011)
						  uart_send_data <= cur_head[31:24];
						else
						  uart_send_data <= cur_head[39:32];
						if(cur_disp == HeadFullDisp) begin
							next_status <= CS_INST_VALUE;
							next_disp <= 0;
							$display("[cache] send inst head [%x]", cur_head);
						end else begin
							next_status <= cur_status;
							next_disp <= cur_disp + 1;
						end
					end else begin
						next_status <= cur_status;
						next_disp <= cur_disp;
					end
				end
				CS_INST_VALUE: begin
					if (uart_receivable) begin
						uart_recv_flag <= `RecvEnable;

						if(cur_disp == 3'b000) 
						  inst_value[7:0] <= uart_recv_data;
						else if(cur_disp == 3'b001)
						  inst_value[15:8] <= uart_recv_data;
						else if(cur_disp == 3'b010)
						  inst_value[23:16] <= uart_recv_data;
						else
						  inst_value[31:24] <= uart_recv_data;
						if(cur_disp == DataFullDisp) begin
							next_disp <= 0;
							next_status <= CS_OUTPUT;
							$display("[cache] recv inst value [%x]", {uart_recv_data,inst_value[23:0]});
						end else begin
							next_status <= cur_status;
							next_disp <= cur_disp + 1;
						end
					end else begin
						next_status <= cur_status;
						next_disp <= cur_disp;
					end
				end
				CS_OUTPUT: begin
					$display("[cache] cur_status: CS_OUTPUT");
					next_status <= CS_READY;
					next_disp <= 0;
				end
			endcase
		end
	end





	always @ (posedge clk) begin
		if(rst) begin
			cur_status <= CS_READY;
			cur_disp <= 0;
		end else begin
			cur_status <= next_status;
			cur_disp <= next_disp;
		end
	end
endmodule