data/full_repos/permissive/172705897/verilog/dataMem_mask_gen.v
data/verilator_xmls/823d291e-46c3-4b19-b27d-eb47f51ddf56.xml
module sign_mask_gen(func3, sign_mask);
	input [2:0]	func3;
	output [3:0]	sign_mask;

	reg [2:0]	mask;



	always @(*) begin
		case(func3[1:0])
			2'b00: mask = 3'b001;
			2'b01: mask = 3'b011;
			2'b10: mask = 3'b111;
			default: mask = 3'b000;
		endcase
	end

	assign sign_mask = {(~func3[2]), mask};
endmodule
module sign_mask_gen(func3, sign_mask);

	input [2:0]	func3;
	output [3:0]	sign_mask;

	reg [2:0]	mask;



	always @(*) begin
		case(func3[1:0])
			2'b00: mask = 3'b001;
			2'b01: mask = 3'b011;
			2'b10: mask = 3'b111;
			default: mask = 3'b000;
		endcase
	end

	assign sign_mask = {(~func3[2]), mask};
endmodule