data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/fifo_1clk_regs.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/fifo_1clk_regs.v:24: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module fifo_1clk_regs (clk, rst, wr_en, wr_data, full, rd_en, rd_data, empty, used);
`include "util.vh"
  parameter                 Width    = 8;
  parameter                 Depth    = 4;

  localparam                UsedBits = clog2(Depth+1);

  input                     clk;
  input                     rst;

  input                     wr_en;
  input [Width-1:0]         wr_data;
  output                    full;

  input                     rd_en;
  output [Width-1:0]        rd_data;
  output                    empty;

  output reg [UsedBits-1:0] used;


  reg [Depth*Width-1:0] data;


  always @(posedge clk) begin:fifo_regs
    reg [UsedBits-1:0] used_i;
    integer            i;

    used_i = used;


    if (rd_en) begin
      data   <= data >> Width;
      used_i  = used_i - 1;
    end


    if (wr_en) begin
      for (i=0; i < Depth; i=i+1) begin
        if (i == used_i)
          data[i*Width +: Width] <= wr_data;
      end
      used_i = used_i + 1;
    end

    used <= used_i;

    if (rst) begin
      used <= 0;
    end
  end

  assign rd_data  = data[Width-1:0];
  assign full     = (used == Depth);
  assign empty    = (used == 0);

endmodule
module fifo_1clk_regs (clk, rst, wr_en, wr_data, full, rd_en, rd_data, empty, used);

`include "util.vh"
  parameter                 Width    = 8;
  parameter                 Depth    = 4;

  localparam                UsedBits = clog2(Depth+1);

  input                     clk;
  input                     rst;

  input                     wr_en;
  input [Width-1:0]         wr_data;
  output                    full;

  input                     rd_en;
  output [Width-1:0]        rd_data;
  output                    empty;

  output reg [UsedBits-1:0] used;


  reg [Depth*Width-1:0] data;


  always @(posedge clk) begin:fifo_regs
    reg [UsedBits-1:0] used_i;
    integer            i;

    used_i = used;


    if (rd_en) begin
      data   <= data >> Width;
      used_i  = used_i - 1;
    end


    if (wr_en) begin
      for (i=0; i < Depth; i=i+1) begin
        if (i == used_i)
          data[i*Width +: Width] <= wr_data;
      end
      used_i = used_i + 1;
    end

    used <= used_i;

    if (rst) begin
      used <= 0;
    end
  end

  assign rd_data  = data[Width-1:0];
  assign full     = (used == Depth);
  assign empty    = (used == 0);

endmodule