data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/txd.v
None: at end of input
1: b'%Error: data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src/txd.v:14: Cannot find include file: .\\\\src\\\\head_uart.v\n`include    ".\\\\src\\\\head_uart.v" \n            ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src,data/full_repos/permissive/166661632/.\\\\src\\\\head_uart.v\n             data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src,data/full_repos/permissive/166661632/.\\\\src\\\\head_uart.v.v\n             data/full_repos/permissive/166661632/p8/MiniUART_src/MiniUART_src/src,data/full_repos/permissive/166661632/.\\\\src\\\\head_uart.v.sv\n             .\\\\src\\\\head_uart.v\n             .\\\\src\\\\head_uart.v.v\n             .\\\\src\\\\head_uart.v.sv\n             obj_dir/.\\\\src\\\\head_uart.v\n             obj_dir/.\\\\src\\\\head_uart.v.v\n             obj_dir/.\\\\src\\\\head_uart.v.sv\n%Error: Exiting due to 1 error(s)\n'
module  ctrl_shift( en_tx, load, shift, ts, clk, rst ) ;
    input                           en_tx ;
    input                           load ;
    output                          shift ;
    output                          ts ;
    input                           clk ;
    input                           rst ;


    reg     [3:0]                   cnt_tx ;
    wire                            en_cnt_tx ;
    wire                            rst_cnt_tx ;
    parameter   IDLE=0, SHIFT=1 ;
    reg                             fsm ;
    

    assign  shift   = (fsm==SHIFT) && en_tx ;

    assign  ts      = (fsm==IDLE) ;


    always  @( posedge clk or posedge rst )
        if ( rst )
            fsm <= IDLE ;
        else
            case ( fsm )
                IDLE    :   if ( load ) 
                                fsm <= SHIFT ;
                SHIFT   :   if ( cnt_tx == 0 )
                                fsm <= IDLE ;
            endcase


    assign  rst_cnt_tx  = (fsm==IDLE) ;
    assign  en_cnt_tx   = (fsm==SHIFT) && en_tx ;
    always  @( posedge clk or posedge rst_cnt_tx )
        if ( rst_cnt_tx )
            cnt_tx <= 10 ;
        else
            if ( en_cnt_tx )
                cnt_tx <= cnt_tx - 1 ;
endmodule
module  ctrl_shift( en_tx, load, shift, ts, clk, rst ) ;

    input                           en_tx ;
    input                           load ;
    output                          shift ;
    output                          ts ;
    input                           clk ;
    input                           rst ;


    reg     [3:0]                   cnt_tx ;
    wire                            en_cnt_tx ;
    wire                            rst_cnt_tx ;
    parameter   IDLE=0, SHIFT=1 ;
    reg                             fsm ;
    

    assign  shift   = (fsm==SHIFT) && en_tx ;

    assign  ts      = (fsm==IDLE) ;


    always  @( posedge clk or posedge rst )
        if ( rst )
            fsm <= IDLE ;
        else
            case ( fsm )
                IDLE    :   if ( load ) 
                                fsm <= SHIFT ;
                SHIFT   :   if ( cnt_tx == 0 )
                                fsm <= IDLE ;
            endcase


    assign  rst_cnt_tx  = (fsm==IDLE) ;
    assign  en_cnt_tx   = (fsm==SHIFT) && en_tx ;
    always  @( posedge clk or posedge rst_cnt_tx )
        if ( rst_cnt_tx )
            cnt_tx <= 10 ;
        else
            if ( en_cnt_tx )
                cnt_tx <= cnt_tx - 1 ;
endmodule