data/full_repos/permissive/157588658/sw/targets/bx-smitest.v
 line:26: before: ")"
1: b'%Error: data/full_repos/permissive/157588658/sw/targets/bx-smitest.v:5: Cannot find include file: ../src/smi.v\n`include "../src/smi.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/157588658/sw/targets,data/full_repos/permissive/157588658/../src/smi.v\n             data/full_repos/permissive/157588658/sw/targets,data/full_repos/permissive/157588658/../src/smi.v.v\n             data/full_repos/permissive/157588658/sw/targets,data/full_repos/permissive/157588658/../src/smi.v.sv\n             ../src/smi.v\n             ../src/smi.v.v\n             ../src/smi.v.sv\n             obj_dir/../src/smi.v\n             obj_dir/../src/smi.v.v\n             obj_dir/../src/smi.v.sv\n%Error: data/full_repos/permissive/157588658/sw/targets/bx-smitest.v:6: Cannot find include file: ../src/pll.v\n`include "../src/pll.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/157588658/sw/targets/bx-smitest.v:21: syntax error, unexpected \')\', expecting \'[\'\n   );\n   ^\n%Error: data/full_repos/permissive/157588658/sw/targets/bx-smitest.v:27: syntax error, unexpected IDENTIFIER\n   pll quad(CLK, clk_64mhz, locked);\n   ^~~\n%Error: data/full_repos/permissive/157588658/sw/targets/bx-smitest.v:35: syntax error, unexpected initial\n   initial reset = 0;\n   ^~~~~~~\n%Error: data/full_repos/permissive/157588658/sw/targets/bx-smitest.v:42: syntax error, unexpected IDENTIFIER\n   smi smi(clk_64mhz, reset, smi_data, smi_oe, smi_we, smi_in, smi_out, read, write);\n   ^~~\n%Error: data/full_repos/permissive/157588658/sw/targets/bx-smitest.v:46: syntax error, unexpected initial\n   initial first = 1\'b1;\n   ^~~~~~~\n%Error: data/full_repos/permissive/157588658/sw/targets/bx-smitest.v:49: syntax error, unexpected initial\n   initial data = 1\'b0;\n   ^~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module smitest
  (
   input CLK,
   inout PIN_1,
   inout PIN_2,
   input PIN_3,
   input PIN_4,
   inout PIN_5,
   inout PIN_6,
   inout PIN_7,
   inout PIN_8,
   inout PIN_9,
   inout PIN_10,
   );


   wire  clk_64mhz;
   wire  locked;

   pll quad(CLK, clk_64mhz, locked);


   wire  smi_oe = PIN_3;
   wire  smi_we = PIN_4;
   wire [7:0] smi_data = {PIN_9, PIN_10, PIN_1, PIN_2, PIN_6, PIN_8, PIN_7, PIN_5};

   reg      reset;
   initial reset = 0;

   wire [7:0] smi_in;
   wire [7:0] smi_out;
   wire       read;
   wire       write;

   smi smi(clk_64mhz, reset, smi_data, smi_oe, smi_we, smi_in, smi_out, read, write);


   reg        first;
   initial first = 1'b1;

   reg [7:0]  data;
   initial data = 1'b0;

   assign smi_in = data;

   always @(posedge clk_64mhz) begin
      if (write) begin

      end else if (read) begin

         if (first) begin
            data <= 7'b1000101;
            first <= 1'b0;
         end else begin
            data <= data ^ 7'b0100000;
         end
      end
   end
endmodule
module smitest
  (
   input CLK,
   inout PIN_1,
   inout PIN_2,
   input PIN_3,
   input PIN_4,
   inout PIN_5,
   inout PIN_6,
   inout PIN_7,
   inout PIN_8,
   inout PIN_9,
   inout PIN_10,
   );



   wire  clk_64mhz;
   wire  locked;

   pll quad(CLK, clk_64mhz, locked);


   wire  smi_oe = PIN_3;
   wire  smi_we = PIN_4;
   wire [7:0] smi_data = {PIN_9, PIN_10, PIN_1, PIN_2, PIN_6, PIN_8, PIN_7, PIN_5};

   reg      reset;
   initial reset = 0;

   wire [7:0] smi_in;
   wire [7:0] smi_out;
   wire       read;
   wire       write;

   smi smi(clk_64mhz, reset, smi_data, smi_oe, smi_we, smi_in, smi_out, read, write);


   reg        first;
   initial first = 1'b1;

   reg [7:0]  data;
   initial data = 1'b0;

   assign smi_in = data;

   always @(posedge clk_64mhz) begin
      if (write) begin

      end else if (read) begin

         if (first) begin
            data <= 7'b1000101;
            first <= 1'b0;
         end else begin
            data <= data ^ 7'b0100000;
         end
      end
   end
endmodule