data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-2_7segmentos/bcd-7.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/111433415/verilog/04_subsistemas_comb/04-2_7segmentos/bcd-7.v:20: Little bit endian vector: MSB < LSB of bit range: 1:7\n    output reg [1:7] y   \n               ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module bcd7 (
    input wire e,
    input wire [3:0] x,
    output reg [1:7] y
    );



endmodule
module bcd7 (
    input wire e,
    input wire [3:0] x,
    output reg [1:7] y
    );




endmodule