data/full_repos/permissive/184916587/OLD/ALU.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'add_rs1\'\n ALU_sched schedule(\n           ^~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'add_rs2\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'A_add_rd\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'sub_rs1\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'sub_rs2\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'S_sub_rd\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'sll_rs1\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'sll_rs2\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'SLL_sll_rd\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'slt_rs1\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'slt_rs2\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'SLT_slt_rd\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'sltu_rs1\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'sltu_rs2\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'SLTU_sltu_rd\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'xor_rs1\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'xor_rs2\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'X_xor_rd\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'srl_rs1\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'srl_rs2\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'SRL_srl_rd\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'sra_rs1\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'sra_rs2\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'SRA_sra_rd\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'or_rs1\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'or_rs2\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'O_or_rd\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'and_rs1\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'and_rs2\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/184916587/OLD/ALU.v:16: Cell has missing pin: \'AND_and_rd\'\n ALU_sched schedule(\n           ^~~~~~~~\n%Error: Exiting due to 30 warning(s)\n'
module ALU_sched(
	input[31:0] rs1_num,
	input[31:0] rs2_num,
	input[9:0] alu_op,

	output[31:0] rd_num,

	input[31:0] add_rs1,
	input[31:0] add_rs2,
	output[31:0] A_add_rd,

	input[31:0] sub_rs1,
	input[31:0] sub_rs2,
	output[31:0] S_sub_rd,

	input[31:0] sll_rs1,
	input[31:0] sll_rs2,
	output[31:0] SLL_sll_rd,

	input[31:0] slt_rs1,
	input[31:0] slt_rs2,
	output[31:0] SLT_slt_rd,

	input[31:0] sltu_rs1,
	input[31:0] sltu_rs2,
	output[31:0] SLTU_sltu_rd,

	input[31:0] xor_rs1,
	input[31:0] xor_rs2,
	output[31:0] X_xor_rd,

	input[31:0] srl_rs1,
	input[31:0] srl_rs2,
	output[31:0] SRL_srl_rd,

	input[31:0] sra_rs1,
	input[31:0] sra_rs2,
	output[31:0] SRA_sra_rd,

	input[31:0] or_rs1,
	input[31:0] or_rs2,
	output[31:0] O_or_rd,

	input[31:0] and_rs1,
	input[31:0] and_rs2,
	output[31:0] AND_and_rd
);

	add_32 add_add(
		.add_rs1(rs1_num),
		.add_rs2(rs2_num),
		.add_rd(A_add_rd)
	);
	sub_32 sub_sub(
		.sub_rs1(rs1_num),
		.sub_rs2(rs2_num),
		.sub_rd(S_sub_rd)
	);
	sll_32 sll_sll(
		.sll_rs1(rs1_num),
		.sll_rs2(rs2_num),
		.sll_rd(SLL_sll_rd)
	);
	slt_32 slt_slt(
		.slt_rs1(rs1_num),
		.slt_rs2(rs2_num),
		.slt_rd(SLT_slt_rd)
	);
	sltu_32 sltu_sltu(
		.sltu_rs1(rs1_num),
		.sltu_rs2(rs2_num),
		.sltu_rd(SLTU_sltu_rd)
	);
	xor_32 xor_xor(
		.xor_rs1(rs1_num),
		.xor_rs2(rs2_num),
		.xor_rd(X_xor_rd)
	);
	srl_32 srl_srl(
		.srl_rs1(rs1_num),
		.srl_rs2(rs2_num),
		.srl_rd(SRL_srl_rd)
	);
	sra_32 sra_sra(
		.sra_rs1(rs1_num),
		.sra_rs2(rs2_num),
		.sra_rd(SRA_sra_rd)
	);
	or_32 or_or(
		.or_rs1(rs1_num),
		.or_rs2(rs2_num),
		.or_rd(O_or_rd)
	);
	and_32 and_and(
		.and_rs1(rs1_num),
		.and_rs2(rs2_num),
		.and_rd(AND_and_rd)
	);

	reg[31:0] rd_num_temp;


	always @(*)
	begin
		if(alu_op===10'b0000000001)
			rd_num_temp=A_add_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000000010)
			rd_num_temp=S_sub_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000000011)
			rd_num_temp=SLL_sll_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000000101)
			rd_num_temp=SLT_slt_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000000110)
			rd_num_temp=SLTU_sltu_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000000111)
			rd_num_temp=X_xor_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000001000)
			rd_num_temp=SRL_srl_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000001001)
			rd_num_temp=SRA_sra_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000001010)
			rd_num_temp=O_or_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000001011)
			rd_num_temp=AND_and_rd;
	end

	assign rd_num=rd_num_temp;
endmodule
module ALU_sched(
	input[31:0] rs1_num,
	input[31:0] rs2_num,
	input[9:0] alu_op,

	output[31:0] rd_num,

	input[31:0] add_rs1,
	input[31:0] add_rs2,
	output[31:0] A_add_rd,

	input[31:0] sub_rs1,
	input[31:0] sub_rs2,
	output[31:0] S_sub_rd,

	input[31:0] sll_rs1,
	input[31:0] sll_rs2,
	output[31:0] SLL_sll_rd,

	input[31:0] slt_rs1,
	input[31:0] slt_rs2,
	output[31:0] SLT_slt_rd,

	input[31:0] sltu_rs1,
	input[31:0] sltu_rs2,
	output[31:0] SLTU_sltu_rd,

	input[31:0] xor_rs1,
	input[31:0] xor_rs2,
	output[31:0] X_xor_rd,

	input[31:0] srl_rs1,
	input[31:0] srl_rs2,
	output[31:0] SRL_srl_rd,

	input[31:0] sra_rs1,
	input[31:0] sra_rs2,
	output[31:0] SRA_sra_rd,

	input[31:0] or_rs1,
	input[31:0] or_rs2,
	output[31:0] O_or_rd,

	input[31:0] and_rs1,
	input[31:0] and_rs2,
	output[31:0] AND_and_rd
);


	add_32 add_add(
		.add_rs1(rs1_num),
		.add_rs2(rs2_num),
		.add_rd(A_add_rd)
	);
	sub_32 sub_sub(
		.sub_rs1(rs1_num),
		.sub_rs2(rs2_num),
		.sub_rd(S_sub_rd)
	);
	sll_32 sll_sll(
		.sll_rs1(rs1_num),
		.sll_rs2(rs2_num),
		.sll_rd(SLL_sll_rd)
	);
	slt_32 slt_slt(
		.slt_rs1(rs1_num),
		.slt_rs2(rs2_num),
		.slt_rd(SLT_slt_rd)
	);
	sltu_32 sltu_sltu(
		.sltu_rs1(rs1_num),
		.sltu_rs2(rs2_num),
		.sltu_rd(SLTU_sltu_rd)
	);
	xor_32 xor_xor(
		.xor_rs1(rs1_num),
		.xor_rs2(rs2_num),
		.xor_rd(X_xor_rd)
	);
	srl_32 srl_srl(
		.srl_rs1(rs1_num),
		.srl_rs2(rs2_num),
		.srl_rd(SRL_srl_rd)
	);
	sra_32 sra_sra(
		.sra_rs1(rs1_num),
		.sra_rs2(rs2_num),
		.sra_rd(SRA_sra_rd)
	);
	or_32 or_or(
		.or_rs1(rs1_num),
		.or_rs2(rs2_num),
		.or_rd(O_or_rd)
	);
	and_32 and_and(
		.and_rs1(rs1_num),
		.and_rs2(rs2_num),
		.and_rd(AND_and_rd)
	);

	reg[31:0] rd_num_temp;


	always @(*)
	begin
		if(alu_op===10'b0000000001)
			rd_num_temp=A_add_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000000010)
			rd_num_temp=S_sub_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000000011)
			rd_num_temp=SLL_sll_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000000101)
			rd_num_temp=SLT_slt_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000000110)
			rd_num_temp=SLTU_sltu_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000000111)
			rd_num_temp=X_xor_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000001000)
			rd_num_temp=SRL_srl_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000001001)
			rd_num_temp=SRA_sra_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000001010)
			rd_num_temp=O_or_rd;
	end

	always @(*)
	begin
		if(alu_op===10'b0000001011)
			rd_num_temp=AND_and_rd;
	end

	assign rd_num=rd_num_temp;
endmodule