data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v
 line:102: before: ";"
1: b'%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:121: Cannot find include file: clogb2.vh\n`include "clogb2.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming,data/full_repos/permissive/197252258/clogb2.vh\n             data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming,data/full_repos/permissive/197252258/clogb2.vh.v\n             data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming,data/full_repos/permissive/197252258/clogb2.vh.sv\n             clogb2.vh\n             clogb2.vh.v\n             clogb2.vh.sv\n             obj_dir/clogb2.vh\n             obj_dir/clogb2.vh.v\n             obj_dir/clogb2.vh.sv\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:5: Define or directive not defined: \'`PKT_TYPE_W\'\n    input   [`PKT_TYPE_W-1:0]       pkt_type_in,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:6: Define or directive not defined: \'`PKT_DATA_W\'\n    input   [`PKT_DATA_W-1:0]       pkt_data_in,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:7: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   cumulative_ack_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:8: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   selective_ack_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:9: Define or directive not defined: \'`TX_CNT_W\'\n    input   [`TX_CNT_W-1:0]         sack_tx_id_in,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:11: Define or directive not defined: \'`TIME_W\'\n    input   [`TIME_W-1:0]           now,\n             ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:13: Define or directive not defined: \'`FLAG_W\'\n    input   [`FLAG_W-1:0]           valid_selective_ack,\n             ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:14: Define or directive not defined: \'`FLOW_WIN_IND_W\'\n    input   [`FLOW_WIN_IND_W-1:0]   new_c_acks_cnt,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:15: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   old_wnd_start_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:17: Define or directive not defined: \'`FLOW_WIN_SIZE\'\n    input   [`FLOW_WIN_SIZE-1:0]    acked_wnd_in,\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:18: Define or directive not defined: \'`FLOW_WIN_SIZE\'\n    input   [`FLOW_WIN_SIZE-1:0]    rtx_wnd_in,\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:19: Define or directive not defined: \'`TX_CNT_WIN_SIZE\'\n    input   [`TX_CNT_WIN_SIZE-1:0]  tx_cnt_wnd_in,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:20: Define or directive not defined: \'`FLOW_WIN_IND_W\'\n    input   [`FLOW_WIN_IND_W-1:0]   wnd_start_ind_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:21: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   wnd_start_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:22: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\n    input   [`FLOW_WIN_SIZE_W-1:0]  wnd_size_in,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:23: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   next_new_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:24: Define or directive not defined: \'`TIMER_W\'\n    input   [`TIMER_W-1:0]          rtx_timer_amnt_in,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:25: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   total_tx_cnt_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:26: Define or directive not defined: \'`USER_CONTEXT_W\'\n    input   [`USER_CONTEXT_W-1:0]   user_cntxt_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:29: Define or directive not defined: \'`FLOW_WIN_SIZE\'\n    output  [`FLOW_WIN_SIZE-1:0]    rtx_wnd_out,\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:30: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\n    output  [`FLOW_WIN_SIZE_W-1:0]  wnd_size_out,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:31: Define or directive not defined: \'`FLAG_W\'\n    output  [`FLAG_W-1:0]           reset_rtx_timer,\n             ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:32: Define or directive not defined: \'`TIMER_W\'\n    output  [`TIMER_W-1:0]          rtx_timer_amnt_out, \n             ^~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:33: Define or directive not defined: \'`USER_CONTEXT_W\'\n    output  [`USER_CONTEXT_W-1:0]   user_cntxt_out\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:36: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nlocalparam  R_FLOW_WIN_IND_W = `FLOW_WIN_IND_W - 1;\n                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:44: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\nwire    [`FLOW_SEQ_NUM_W-1:0]                       rtx_start_ind_tmp;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:45: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       rtx_start_ind;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:47: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\nwire    [`FLOW_SEQ_NUM_W-1:0]                       rtx_end_ind_tmp;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:48: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       rtx_end_ind;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:51: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       rtx_range_start_1;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:52: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       rtx_range_end_1;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:55: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       rtx_range_start_2;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:56: Define or directive not defined: \'`FLOW_WIN_IND_W\'\nwire    [`FLOW_WIN_IND_W-1:0]                       rtx_range_end_2;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:58: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\nwire    [`FLOW_SEQ_NUM_W-1:0]                       rtx_start;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:59: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\nwire    [`FLOW_SEQ_NUM_W-1:0]                       rtx_end;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:102: Define or directive not defined: \'`FLOW_WIN_SIZE\'\nassign rtx_range_end_1 = (rtx_end_ind >= rtx_start_ind) ? rtx_end_ind : `FLOW_WIN_SIZE;\n                                                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:102: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign rtx_range_end_1 = (rtx_end_ind >= rtx_start_ind) ? rtx_end_ind : `FLOW_WIN_SIZE;\n                                                                                      ^\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:111: Define or directive not defined: \'`FLOW_WIN_SIZE\'\nfor (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_rtx\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/dd_engine/event_processors/dd_incoming/dd_incoming_1.v:111: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nfor (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_rtx\n                              ^\n%Error: Cannot continue\n'
module dd_incoming_1 (

    input   [`PKT_TYPE_W-1:0]       pkt_type_in,
    input   [`PKT_DATA_W-1:0]       pkt_data_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   cumulative_ack_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   selective_ack_in,
    input   [`TX_CNT_W-1:0]         sack_tx_id_in,

    input   [`TIME_W-1:0]           now,

    input   [`FLAG_W-1:0]           valid_selective_ack,
    input   [`FLOW_WIN_IND_W-1:0]   new_c_acks_cnt,
    input   [`FLOW_SEQ_NUM_W-1:0]   old_wnd_start_in,
    
    input   [`FLOW_WIN_SIZE-1:0]    acked_wnd_in,
    input   [`FLOW_WIN_SIZE-1:0]    rtx_wnd_in,
    input   [`TX_CNT_WIN_SIZE-1:0]  tx_cnt_wnd_in,
    input   [`FLOW_WIN_IND_W-1:0]   wnd_start_ind_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   wnd_start_in,
    input   [`FLOW_WIN_SIZE_W-1:0]  wnd_size_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   next_new_in,
    input   [`TIMER_W-1:0]          rtx_timer_amnt_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   total_tx_cnt_in,
    input   [`USER_CONTEXT_W-1:0]   user_cntxt_in,
    

    output  [`FLOW_WIN_SIZE-1:0]    rtx_wnd_out,
    output  [`FLOW_WIN_SIZE_W-1:0]  wnd_size_out,
    output  [`FLAG_W-1:0]           reset_rtx_timer,
    output  [`TIMER_W-1:0]          rtx_timer_amnt_out, 
    output  [`USER_CONTEXT_W-1:0]   user_cntxt_out
);

localparam  R_FLOW_WIN_IND_W = `FLOW_WIN_IND_W - 1;





wire                                                mark_rtx;

wire    [`FLOW_SEQ_NUM_W-1:0]                       rtx_start_ind_tmp;
wire    [`FLOW_WIN_IND_W-1:0]                       rtx_start_ind;

wire    [`FLOW_SEQ_NUM_W-1:0]                       rtx_end_ind_tmp;
wire    [`FLOW_WIN_IND_W-1:0]                       rtx_end_ind;

wire                                                rtx_range_val_1;
wire    [`FLOW_WIN_IND_W-1:0]                       rtx_range_start_1;
wire    [`FLOW_WIN_IND_W-1:0]                       rtx_range_end_1;

wire                                                rtx_range_val_2;
wire    [`FLOW_WIN_IND_W-1:0]                       rtx_range_start_2;
wire    [`FLOW_WIN_IND_W-1:0]                       rtx_range_end_2;

wire    [`FLOW_SEQ_NUM_W-1:0]                       rtx_start;
wire    [`FLOW_SEQ_NUM_W-1:0]                       rtx_end;





user_defined_incoming ud_inc (.pkt_type_in          (pkt_type_in          ),
                              .pkt_data_in          (pkt_data_in          ),
                              .cumulative_ack_in    (cumulative_ack_in    ),
                              .selective_ack_in     (selective_ack_in     ),
                              .sack_tx_id_in        (sack_tx_id_in        ),
                              .now                  (now                  ),

                              .valid_selective_ack  (valid_selective_ack  ),
                              .new_c_acks_cnt       (new_c_acks_cnt       ),
                              .old_wnd_start_in     (old_wnd_start_in     ),
    
                              .acked_wnd_in         (acked_wnd_in         ),
                              .rtx_wnd_in           (rtx_wnd_in           ),
                              .tx_cnt_wnd_in        (tx_cnt_wnd_in        ),
                              .wnd_start_in         (wnd_start_in         ),
                              .wnd_size_in          (wnd_size_in          ),
                              .next_new_in          (next_new_in          ),
                              .rtx_timer_amnt_in    (rtx_timer_amnt_in    ),
                              .total_tx_cnt_in      (total_tx_cnt_in      ),
                              .user_cntxt_in        (user_cntxt_in        ),

                              .mark_rtx             (mark_rtx             ),
                              .rtx_start            (rtx_start            ),
                              .rtx_end              (rtx_end              ),
                              .wnd_size_out         (wnd_size_out         ),
                              .reset_rtx_timer      (reset_rtx_timer      ),
                              .rtx_timer_amnt_out   (rtx_timer_amnt_out   ),
                              .user_cntxt_out       (user_cntxt_out       ));

assign rtx_start_ind_tmp = rtx_start - wnd_start_in + wnd_start_ind_in;
assign rtx_start_ind = {1'b0, rtx_start_ind_tmp[R_FLOW_WIN_IND_W-1:0]};

assign rtx_end_ind_tmp = rtx_end - wnd_start_in + wnd_start_ind_in;
assign rtx_end_ind     = {1'b0, rtx_end_ind_tmp[R_FLOW_WIN_IND_W-1:0]};

assign rtx_range_val_1 = 1'b1;
assign rtx_range_start_1 = rtx_start_ind;
assign rtx_range_end_1 = (rtx_end_ind >= rtx_start_ind) ? rtx_end_ind : `FLOW_WIN_SIZE;

assign rtx_range_val_2 = rtx_end_ind < rtx_start_ind;
assign rtx_range_start_2 = {(R_FLOW_WIN_IND_W+1){1'b0}};
assign rtx_range_end_2 = rtx_end_ind;

genvar i;

generate
for (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_rtx
    assign rtx_wnd_out[i] = ~acked_wnd_in[i] & 
                            ((mark_rtx &
                             ((rtx_range_val_1 & i >= rtx_range_start_1 & i < rtx_range_end_1) |
                              (rtx_range_val_2 & i >= rtx_range_start_2 & i < rtx_range_end_2))) 
                            ? 1'b1 : rtx_wnd_in[i]);
end
endgenerate


`include "clogb2.vh"
endmodule
module dd_incoming_1 (

    input   [`PKT_TYPE_W-1:0]       pkt_type_in,
    input   [`PKT_DATA_W-1:0]       pkt_data_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   cumulative_ack_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   selective_ack_in,
    input   [`TX_CNT_W-1:0]         sack_tx_id_in,

    input   [`TIME_W-1:0]           now,

    input   [`FLAG_W-1:0]           valid_selective_ack,
    input   [`FLOW_WIN_IND_W-1:0]   new_c_acks_cnt,
    input   [`FLOW_SEQ_NUM_W-1:0]   old_wnd_start_in,
    
    input   [`FLOW_WIN_SIZE-1:0]    acked_wnd_in,
    input   [`FLOW_WIN_SIZE-1:0]    rtx_wnd_in,
    input   [`TX_CNT_WIN_SIZE-1:0]  tx_cnt_wnd_in,
    input   [`FLOW_WIN_IND_W-1:0]   wnd_start_ind_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   wnd_start_in,
    input   [`FLOW_WIN_SIZE_W-1:0]  wnd_size_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   next_new_in,
    input   [`TIMER_W-1:0]          rtx_timer_amnt_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   total_tx_cnt_in,
    input   [`USER_CONTEXT_W-1:0]   user_cntxt_in,
    

    output  [`FLOW_WIN_SIZE-1:0]    rtx_wnd_out,
    output  [`FLOW_WIN_SIZE_W-1:0]  wnd_size_out,
    output  [`FLAG_W-1:0]           reset_rtx_timer,
    output  [`TIMER_W-1:0]          rtx_timer_amnt_out, 
    output  [`USER_CONTEXT_W-1:0]   user_cntxt_out
);


localparam  R_FLOW_WIN_IND_W = `FLOW_WIN_IND_W - 1;





wire                                                mark_rtx;

wire    [`FLOW_SEQ_NUM_W-1:0]                       rtx_start_ind_tmp;
wire    [`FLOW_WIN_IND_W-1:0]                       rtx_start_ind;

wire    [`FLOW_SEQ_NUM_W-1:0]                       rtx_end_ind_tmp;
wire    [`FLOW_WIN_IND_W-1:0]                       rtx_end_ind;

wire                                                rtx_range_val_1;
wire    [`FLOW_WIN_IND_W-1:0]                       rtx_range_start_1;
wire    [`FLOW_WIN_IND_W-1:0]                       rtx_range_end_1;

wire                                                rtx_range_val_2;
wire    [`FLOW_WIN_IND_W-1:0]                       rtx_range_start_2;
wire    [`FLOW_WIN_IND_W-1:0]                       rtx_range_end_2;

wire    [`FLOW_SEQ_NUM_W-1:0]                       rtx_start;
wire    [`FLOW_SEQ_NUM_W-1:0]                       rtx_end;





user_defined_incoming ud_inc (.pkt_type_in          (pkt_type_in          ),
                              .pkt_data_in          (pkt_data_in          ),
                              .cumulative_ack_in    (cumulative_ack_in    ),
                              .selective_ack_in     (selective_ack_in     ),
                              .sack_tx_id_in        (sack_tx_id_in        ),
                              .now                  (now                  ),

                              .valid_selective_ack  (valid_selective_ack  ),
                              .new_c_acks_cnt       (new_c_acks_cnt       ),
                              .old_wnd_start_in     (old_wnd_start_in     ),
    
                              .acked_wnd_in         (acked_wnd_in         ),
                              .rtx_wnd_in           (rtx_wnd_in           ),
                              .tx_cnt_wnd_in        (tx_cnt_wnd_in        ),
                              .wnd_start_in         (wnd_start_in         ),
                              .wnd_size_in          (wnd_size_in          ),
                              .next_new_in          (next_new_in          ),
                              .rtx_timer_amnt_in    (rtx_timer_amnt_in    ),
                              .total_tx_cnt_in      (total_tx_cnt_in      ),
                              .user_cntxt_in        (user_cntxt_in        ),

                              .mark_rtx             (mark_rtx             ),
                              .rtx_start            (rtx_start            ),
                              .rtx_end              (rtx_end              ),
                              .wnd_size_out         (wnd_size_out         ),
                              .reset_rtx_timer      (reset_rtx_timer      ),
                              .rtx_timer_amnt_out   (rtx_timer_amnt_out   ),
                              .user_cntxt_out       (user_cntxt_out       ));

assign rtx_start_ind_tmp = rtx_start - wnd_start_in + wnd_start_ind_in;
assign rtx_start_ind = {1'b0, rtx_start_ind_tmp[R_FLOW_WIN_IND_W-1:0]};

assign rtx_end_ind_tmp = rtx_end - wnd_start_in + wnd_start_ind_in;
assign rtx_end_ind     = {1'b0, rtx_end_ind_tmp[R_FLOW_WIN_IND_W-1:0]};

assign rtx_range_val_1 = 1'b1;
assign rtx_range_start_1 = rtx_start_ind;
assign rtx_range_end_1 = (rtx_end_ind >= rtx_start_ind) ? rtx_end_ind : `FLOW_WIN_SIZE;

assign rtx_range_val_2 = rtx_end_ind < rtx_start_ind;
assign rtx_range_start_2 = {(R_FLOW_WIN_IND_W+1){1'b0}};
assign rtx_range_end_2 = rtx_end_ind;

genvar i;

generate
for (i = 0; i < `FLOW_WIN_SIZE; i = i + 1) begin: gen_rtx
    assign rtx_wnd_out[i] = ~acked_wnd_in[i] & 
                            ((mark_rtx &
                             ((rtx_range_val_1 & i >= rtx_range_start_1 & i < rtx_range_end_1) |
                              (rtx_range_val_2 & i >= rtx_range_start_2 & i < rtx_range_end_2))) 
                            ? 1'b1 : rtx_wnd_in[i]);
end
endgenerate


`include "clogb2.vh"
endmodule