data/full_repos/permissive/161033574/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161033574/top.v:27: Operator GTE expects 16 bits on the RHS, but RHS\'s CONST \'8\'ha\' generates 8 bits.\n                                                             : ... In instance top\n        if (clkdiv >= 8\'d10)\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/161033574/top.v:50: Cannot find file containing module: \'framebuffer\'\n   framebuffer fb (.rst_n(rst_n),\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161033574,data/full_repos/permissive/161033574/framebuffer\n             data/full_repos/permissive/161033574,data/full_repos/permissive/161033574/framebuffer.v\n             data/full_repos/permissive/161033574,data/full_repos/permissive/161033574/framebuffer.sv\n             framebuffer\n             framebuffer.v\n             framebuffer.sv\n             obj_dir/framebuffer\n             obj_dir/framebuffer.v\n             obj_dir/framebuffer.sv\n%Error: data/full_repos/permissive/161033574/top.v:59: Cannot find file containing module: \'lcd\'\n   lcd lcd1 (.clk(clk_lcd),\n   ^~~\n%Error: data/full_repos/permissive/161033574/top.v:71: Cannot find file containing module: \'spi_slave\'\n   spi_slave spi1 (.rst_n(rst_n),\n   ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module top(
           input        clk,
           output       clk_en,
           input        rst_n,
           output [7:0] led,
           output       lcd_flm,
           output       lcd_cl1,
           output       lcd_cl2,
           output       lcd_m,
           output [3:0] lcd_data,
           input        cs_n,
           input        sclk,
           input        mosi,
           output       miso,
           input uart_rx,
           output uart_tx
           );

   assign clk_en = 1;

   reg [15:0]    clkdiv;
   reg           clk_1mhz;
   reg           clk_lcd;

   always @ (negedge clk)
     begin
        if (clkdiv >= 8'd10)
          begin
             clkdiv <= 0;
             clk_lcd <= ~clk_lcd;
          end
        else
          begin
             clkdiv <= clkdiv + 1;
          end
     end

   wire [7:0]  rxbuf;
   wire        dr;

   wire        fb_clk;
   wire [31:0] fb_addr;
   wire [7:0]  fb_data;

   wire        fb_wclk;
   reg [31:0]  fb_waddr;
   reg [7:0]   fb_wdata;
   wire        fb_switch;

   framebuffer fb (.rst_n(rst_n),
                   .rclk(fb_clk),
                   .wclk(fb_wclk),
                   .rad(fb_addr),
                   .wad(fb_waddr - 1),
                   .switch(fb_switch),
                   .din(fb_wdata),
                   .dout(fb_data));

   lcd lcd1 (.clk(clk_lcd),
             .rst_n(rst_n),
             .fb_clk(fb_clk),
             .fb_data(fb_data),
             .fb_addr(fb_addr),
             .data(lcd_data),
             .flm(lcd_flm),
             .lp(lcd_cl1),
             .dclk(lcd_cl2),
             .m(lcd_m));


   spi_slave spi1 (.rst_n(rst_n),
                   .cs_n(cs_n),
                   .sclk(sclk),
                   .mosi(mosi),
                   .miso(miso),
                   .dr(dr),
                   .rxbuf(rxbuf));







   reg         flag;

   reg [31:0]  clkdivcnt;















   assign fb_switch = cs_n;
   assign fb_wclk = !dr;
endmodule
module top(
           input        clk,
           output       clk_en,
           input        rst_n,
           output [7:0] led,
           output       lcd_flm,
           output       lcd_cl1,
           output       lcd_cl2,
           output       lcd_m,
           output [3:0] lcd_data,
           input        cs_n,
           input        sclk,
           input        mosi,
           output       miso,
           input uart_rx,
           output uart_tx
           );


   assign clk_en = 1;

   reg [15:0]    clkdiv;
   reg           clk_1mhz;
   reg           clk_lcd;

   always @ (negedge clk)
     begin
        if (clkdiv >= 8'd10)
          begin
             clkdiv <= 0;
             clk_lcd <= ~clk_lcd;
          end
        else
          begin
             clkdiv <= clkdiv + 1;
          end
     end

   wire [7:0]  rxbuf;
   wire        dr;

   wire        fb_clk;
   wire [31:0] fb_addr;
   wire [7:0]  fb_data;

   wire        fb_wclk;
   reg [31:0]  fb_waddr;
   reg [7:0]   fb_wdata;
   wire        fb_switch;

   framebuffer fb (.rst_n(rst_n),
                   .rclk(fb_clk),
                   .wclk(fb_wclk),
                   .rad(fb_addr),
                   .wad(fb_waddr - 1),
                   .switch(fb_switch),
                   .din(fb_wdata),
                   .dout(fb_data));

   lcd lcd1 (.clk(clk_lcd),
             .rst_n(rst_n),
             .fb_clk(fb_clk),
             .fb_data(fb_data),
             .fb_addr(fb_addr),
             .data(lcd_data),
             .flm(lcd_flm),
             .lp(lcd_cl1),
             .dclk(lcd_cl2),
             .m(lcd_m));


   spi_slave spi1 (.rst_n(rst_n),
                   .cs_n(cs_n),
                   .sclk(sclk),
                   .mosi(mosi),
                   .miso(miso),
                   .dr(dr),
                   .rxbuf(rxbuf));







   reg         flag;

   reg [31:0]  clkdivcnt;















   assign fb_switch = cs_n;
   assign fb_wclk = !dr;
endmodule