data/full_repos/permissive/125927162/PWM/pwm_tb.v
 line:39: before: "$"
1: b'%Error: data/full_repos/permissive/125927162/PWM/pwm_tb.v:31: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("pwm_test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/PWM/pwm_tb.v:32: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, DUT);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PWM/pwm_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PWM/pwm_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #50000\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PWM/pwm_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk = ~clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/PWM/pwm_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n   always #1000 in = in + 1;\n          ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pwm_tb();
   localparam WIDTH = 8;
   reg clk;
   reg rst;
   reg [WIDTH-1:0] in;
   wire      out;

   pwm #(.WIDTH(WIDTH)) DUT(
			.clk(clk),
			.rst(rst),
			.in(in),
			.out(out)
			);
   initial begin
      $dumpfile("pwm_test.vcd");
      $dumpvars(0, DUT);
      clk = 0;
      in = 0;
      rst = 1;
      #10
	rst = 0;
      #50000
	$finish;
      
   end

   always #1 clk = ~clk;
   always #1000 in = in + 1;
endmodule
module pwm_tb();

   localparam WIDTH = 8;
   reg clk;
   reg rst;
   reg [WIDTH-1:0] in;
   wire      out;

   pwm #(.WIDTH(WIDTH)) DUT(
			.clk(clk),
			.rst(rst),
			.in(in),
			.out(out)
			);
   initial begin
      $dumpfile("pwm_test.vcd");
      $dumpvars(0, DUT);
      clk = 0;
      in = 0;
      rst = 1;
      #10
	rst = 0;
      #50000
	$finish;
      
   end

   always #1 clk = ~clk;
   always #1000 in = in + 1;
endmodule