data/full_repos/permissive/202776140/memory.v
data/verilator_xmls/d2049ac8-4827-4192-bfcf-eeda209f1edc.xml
module memory
(
    address,
    clk,
    load,
    out_en,
    reset,
    data_in,
    data_out
);


parameter address_size = 16;
parameter memory_size = 2 ** address_size;


input wire [address_size-1:0] address;                 
input wire clk, load, out_en, reset;
input wire [15:0] data_in;


output reg [15:0] data_out;


reg [15:0] memory_registers [memory_size-1:0];
integer k;


always @ (posedge clk)
begin 
    if (out_en) 
    begin 
        data_out <= memory_registers[address];
    end     
    else begin
        data_out <= {16{1'bz}};
    end

    if (load) 
    begin
        memory_registers[address] <= data_in;
    end
end

endmodule
module memory
(
    address,
    clk,
    load,
    out_en,
    reset,
    data_in,
    data_out
);



parameter address_size = 16;
parameter memory_size = 2 ** address_size;


input wire [address_size-1:0] address;                 
input wire clk, load, out_en, reset;
input wire [15:0] data_in;


output reg [15:0] data_out;


reg [15:0] memory_registers [memory_size-1:0];
integer k;


always @ (posedge clk)
begin 
    if (out_en) 
    begin 
        data_out <= memory_registers[address];
    end     
    else begin
        data_out <= {16{1'bz}};
    end

    if (load) 
    begin
        memory_registers[address] <= data_in;
    end
end

endmodule