data/full_repos/permissive/193790231/lab04/lab04part02.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/193790231/lab04/lab04part02.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/193790231/lab04/lab04part02.v:6: Cannot find file containing module: \'counter16x_add\'\n counter16x_add altcounter(count[15:0], SW[0], SW[1], SW[2]);\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193790231/lab04,data/full_repos/permissive/193790231/counter16x_add\n             data/full_repos/permissive/193790231/lab04,data/full_repos/permissive/193790231/counter16x_add.v\n             data/full_repos/permissive/193790231/lab04,data/full_repos/permissive/193790231/counter16x_add.sv\n             counter16x_add\n             counter16x_add.v\n             counter16x_add.sv\n             obj_dir/counter16x_add\n             obj_dir/counter16x_add.v\n             obj_dir/counter16x_add.sv\n%Error: data/full_repos/permissive/193790231/lab04/lab04part02.v:7: Cannot find file containing module: \'hexDisplay4digit\'\n hexDisplay4digit disp(HEX3, HEX2, HEX1, HEX0, count);\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tbl4p2;
	reg  [2:0]sw;
	wire [15:0]ct;
	wire [6:0]h3, h2, h1, h0;
	integer i;
	lab04part02 testl4p2(ct, h3, h2, h1, h0, sw);
	initial begin
		sw[1]=1'b0;
		sw[0]=1'b1;
		for(i=0; i<100; i=i+1) begin
		#100;
			if(i==0)
				sw[2] = 0;
			if(i==2)
				sw[2] = 1;
			sw[1] = ~sw[1];
		end

	end
endmodule
module tbl4p2;

	reg  [2:0]sw;
	wire [15:0]ct;
	wire [6:0]h3, h2, h1, h0;
	integer i;
	lab04part02 testl4p2(ct, h3, h2, h1, h0, sw);
	initial begin
		sw[1]=1'b0;
		sw[0]=1'b1;
		for(i=0; i<100; i=i+1) begin
		#100;
			if(i==0)
				sw[2] = 0;
			if(i==2)
				sw[2] = 1;
			sw[1] = ~sw[1];
		end

	end
endmodule