data/full_repos/permissive/170402453/RISC_DIVIDER/RISC_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #300;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/170402453/RISC_DIVIDER/RISC_tb.v:31: Cannot find file containing module: \'RISC\'\n RISC uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/170402453/RISC_DIVIDER,data/full_repos/permissive/170402453/RISC\n             data/full_repos/permissive/170402453/RISC_DIVIDER,data/full_repos/permissive/170402453/RISC.v\n             data/full_repos/permissive/170402453/RISC_DIVIDER,data/full_repos/permissive/170402453/RISC.sv\n             RISC\n             RISC.v\n             RISC.sv\n             obj_dir/RISC\n             obj_dir/RISC.v\n             obj_dir/RISC.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RISC_tb;


	reg clk;


	RISC uut (
		.clk(clk)
	);

	initial begin

		clk = 1;


		#300;
        


	end
	
	always #10 clk = ~clk;
      
endmodule
module RISC_tb;



	reg clk;


	RISC uut (
		.clk(clk)
	);

	initial begin

		clk = 1;


		#300;
        


	end
	
	always #10 clk = ~clk;
      
endmodule