data/full_repos/permissive/205055389/test/verga/bitselect1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/205055389/test/verga/bitselect1.v:26: Operator ASSIGN expects 65 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h123456789abcdef1\' generates 64 bits.\n                                                                               : ... In instance top\n      b = 64\'h123456789abcdef1;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top;
  reg [63:0] a;
  reg [64:0] b;
  reg [62:0] c;
  reg [7:0] q;
  integer i;

  initial
    begin
      a = 64'h123456789abcdef1;
      for (i = 0;i <= 56;i = i + 4)
	begin
	  q = a[i +: 8];
	  $display("q=%h",q);
	end

      q = 8'hff;
      for (i = 0;i <= 56;i = i + 4)
	begin
	  a = 0;
	  a[i +: 8] = q;
	  $display("i=%2d  a=%016h",i,a);
	end
      $display("  ----   ");

      b = 64'h123456789abcdef1;
      for (i = 0;i <= 56;i = i + 4)
	begin
	  q = b[i +: 8];
	  $display("q=%h",q);
	end

      q = 8'hff;
      for (i = 0;i <= 56;i = i + 4)
	begin
	  b = 0;
	  b[i +: 8] = q;
	  $display("i=%2d  b=%016h",i,b);
	end

      $display("  ----   ");

      c = 63'h123456789abcdef1;
      for (i = 0;i < 56;i = i + 4)
	begin
	  q = c[i +: 8];
	  $display("q=%h",q);
	end

      q = 8'hff;
      for (i = 0;i < 56;i = i + 4)
	begin
	  c = 0;
	  c[i +: 8] = q;
	  $display("i=%2d  c=%016h",i,c);
	end
    end

endmodule
module top;

  reg [63:0] a;
  reg [64:0] b;
  reg [62:0] c;
  reg [7:0] q;
  integer i;

  initial
    begin
      a = 64'h123456789abcdef1;
      for (i = 0;i <= 56;i = i + 4)
	begin
	  q = a[i +: 8];
	  $display("q=%h",q);
	end

      q = 8'hff;
      for (i = 0;i <= 56;i = i + 4)
	begin
	  a = 0;
	  a[i +: 8] = q;
	  $display("i=%2d  a=%016h",i,a);
	end
      $display("  ----   ");

      b = 64'h123456789abcdef1;
      for (i = 0;i <= 56;i = i + 4)
	begin
	  q = b[i +: 8];
	  $display("q=%h",q);
	end

      q = 8'hff;
      for (i = 0;i <= 56;i = i + 4)
	begin
	  b = 0;
	  b[i +: 8] = q;
	  $display("i=%2d  b=%016h",i,b);
	end

      $display("  ----   ");

      c = 63'h123456789abcdef1;
      for (i = 0;i < 56;i = i + 4)
	begin
	  q = c[i +: 8];
	  $display("q=%h",q);
	end

      q = 8'hff;
      for (i = 0;i < 56;i = i + 4)
	begin
	  c = 0;
	  c[i +: 8] = q;
	  $display("i=%2d  c=%016h",i,c);
	end
    end

endmodule