data/full_repos/permissive/188795755/elec_design/beta4/src/pwm.v
'utf-8' codec can't decode byte 0xbf in position 247: invalid start byte
1: b'%Warning-WIDTH: data/full_repos/permissive/188795755/elec_design/beta4/src/pwm.v:109: Operator LTE expects 16 bits on the RHS, but RHS\'s VARREF \'cnt_n\' generates 10 bits.\n                                                                                    : ... In instance pwm\n        else if(cnt_2ms <= cnt_n)\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module  pwm(

        input                   sclk                    ,
        input                   s_rst_n                 ,

        input                   enable                  ,
        input                   direct                  ,
        input           [ 2:0]  cnt                     ,


        output          [ 1:0]  MA
);




parameter       CLK_DIV_CYCLE   =       'd14            ;
parameter       LED_PERIOD      =       'd999           ;

reg     [ 1:0]                  MA_r                    ;
reg     [ 5:0]                  cnt_clk                 ;
reg                             div100_clk              ;
reg     [15:0]                  cnt_2ms                 ;
reg     [ 9:0]                  cnt_n                   ;
reg                             flag_1s                 ;
reg                             pulseout                ;




assign  MA      =       MA_r;


always  @(posedge div100_clk or negedge s_rst_n ) begin  
        if (!s_rst_n)
                MA_r    <=      2'b00;
        else if (!enable)
                MA_r    <=      2'b00;
        else if(direct)      
                MA_r    <=      {~pulseout,1'b1};
        else
                MA_r    <=      {1'b1,~pulseout};
end




always  @(posedge sclk or negedge s_rst_n) begin
        if(!s_rst_n)
                cnt_clk     <=      6'b0000_00;
        else if(cnt_clk >= CLK_DIV_CYCLE)
                cnt_clk     <=      6'b0000_00;
        else
                cnt_clk     <=      cnt_clk + 1'b1;
end

always  @(posedge sclk or negedge s_rst_n) begin
        if(!s_rst_n)
                div100_clk      <=      1'b0;
        else if(cnt_clk == 0)
                div100_clk      <=       ~div100_clk;
end


always  @(posedge div100_clk or negedge s_rst_n) begin
        if(!s_rst_n)
                cnt_2ms <=      'd0;
        else if(cnt_2ms >= LED_PERIOD)
                cnt_2ms <=      'd0;
        else if(enable)
                cnt_2ms <=      cnt_2ms + 1'b1;
end


always  @(posedge div100_clk or negedge s_rst_n) begin
        if(!s_rst_n)
                cnt_n   <=      'd0;

        else begin
                if(cnt_2ms >= LED_PERIOD && flag_1s == 1'b0)
                        cnt_n   <=      cnt_n + 1'b1;
                if(cnt_2ms >= LED_PERIOD && flag_1s == 1'b1)
                        cnt_n   <=      cnt_n - 1'b1;
        end
end


always  @(posedge div100_clk or negedge s_rst_n) begin
        if(!s_rst_n)
                flag_1s    <=      1'b0;
        else if(cnt_n == 0)
                flag_1s    <=      1'b0;
        else if(cnt_n >= LED_PERIOD)
                flag_1s    <=      1'b1;
end


always  @(posedge div100_clk or negedge s_rst_n) begin
        if(!s_rst_n)
                pulseout     <=      1'b0;
        else if(cnt_2ms <= cnt_n)
                pulseout     <=      1'b1;
        else
                pulseout     <=      1'b0;
end  
             
endmodule
module  pwm(

        input                   sclk                    ,
        input                   s_rst_n                 ,

        input                   enable                  ,
        input                   direct                  ,
        input           [ 2:0]  cnt                     ,


        output          [ 1:0]  MA
);





parameter       CLK_DIV_CYCLE   =       'd14            ;
parameter       LED_PERIOD      =       'd999           ;

reg     [ 1:0]                  MA_r                    ;
reg     [ 5:0]                  cnt_clk                 ;
reg                             div100_clk              ;
reg     [15:0]                  cnt_2ms                 ;
reg     [ 9:0]                  cnt_n                   ;
reg                             flag_1s                 ;
reg                             pulseout                ;




assign  MA      =       MA_r;


always  @(posedge div100_clk or negedge s_rst_n ) begin  
        if (!s_rst_n)
                MA_r    <=      2'b00;
        else if (!enable)
                MA_r    <=      2'b00;
        else if(direct)      
                MA_r    <=      {~pulseout,1'b1};
        else
                MA_r    <=      {1'b1,~pulseout};
end




always  @(posedge sclk or negedge s_rst_n) begin
        if(!s_rst_n)
                cnt_clk     <=      6'b0000_00;
        else if(cnt_clk >= CLK_DIV_CYCLE)
                cnt_clk     <=      6'b0000_00;
        else
                cnt_clk     <=      cnt_clk + 1'b1;
end

always  @(posedge sclk or negedge s_rst_n) begin
        if(!s_rst_n)
                div100_clk      <=      1'b0;
        else if(cnt_clk == 0)
                div100_clk      <=       ~div100_clk;
end


always  @(posedge div100_clk or negedge s_rst_n) begin
        if(!s_rst_n)
                cnt_2ms <=      'd0;
        else if(cnt_2ms >= LED_PERIOD)
                cnt_2ms <=      'd0;
        else if(enable)
                cnt_2ms <=      cnt_2ms + 1'b1;
end


always  @(posedge div100_clk or negedge s_rst_n) begin
        if(!s_rst_n)
                cnt_n   <=      'd0;

        else begin
                if(cnt_2ms >= LED_PERIOD && flag_1s == 1'b0)
                        cnt_n   <=      cnt_n + 1'b1;
                if(cnt_2ms >= LED_PERIOD && flag_1s == 1'b1)
                        cnt_n   <=      cnt_n - 1'b1;
        end
end


always  @(posedge div100_clk or negedge s_rst_n) begin
        if(!s_rst_n)
                flag_1s    <=      1'b0;
        else if(cnt_n == 0)
                flag_1s    <=      1'b0;
        else if(cnt_n >= LED_PERIOD)
                flag_1s    <=      1'b1;
end


always  @(posedge div100_clk or negedge s_rst_n) begin
        if(!s_rst_n)
                pulseout     <=      1'b0;
        else if(cnt_2ms <= cnt_n)
                pulseout     <=      1'b1;
        else
                pulseout     <=      1'b0;
end  
             
endmodule