data/full_repos/permissive/190680822/core/cordic.v
1: b'%Warning-WIDTH: data/full_repos/permissive/190680822/core/cordic.v:69: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s VARREF \'x_start\' generates 32 bits.\n                                                                     : ... In instance CORDIC\n        x[0] <= x_start;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/190680822/core/cordic.v:70: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s VARREF \'y_start\' generates 32 bits.\n                                                                     : ... In instance CORDIC\n        y[0] <= y_start;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/190680822/core/cordic.v:76: Operator NEGATE expects 33 bits on the LHS, but LHS\'s VARREF \'y_start\' generates 32 bits.\n                                                                     : ... In instance CORDIC\n        x[0] <= -y_start;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/190680822/core/cordic.v:77: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s VARREF \'x_start\' generates 32 bits.\n                                                                     : ... In instance CORDIC\n        y[0] <= x_start;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/190680822/core/cordic.v:83: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s VARREF \'y_start\' generates 32 bits.\n                                                                     : ... In instance CORDIC\n        x[0] <= y_start;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/190680822/core/cordic.v:84: Operator NEGATE expects 33 bits on the LHS, but LHS\'s VARREF \'x_start\' generates 32 bits.\n                                                                     : ... In instance CORDIC\n        y[0] <= -x_start;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/190680822/core/cordic.v:117: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 33 bits.\n                                                                      : ... In instance CORDIC\n  assign cosine = x[width-1];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/190680822/core/cordic.v:118: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 33 bits.\n                                                                      : ... In instance CORDIC\n  assign sine = y[width-1];\n              ^\n%Error: Exiting due to 8 warning(s)\n'
module CORDIC(clock, cosine, sine, x_start, y_start, angle);

  parameter width = 32;


  input clock;
  input signed [width-1:0] x_start,y_start; 
  input signed [31:0] angle;


  output signed  [width-1:0] sine, cosine;


  wire signed [31:0] atan_table [0:30];
                          
  assign atan_table[00] = 'b00100000000000000000000000000000;
  assign atan_table[01] = 'b00010010111001000000010100011101;
  assign atan_table[02] = 'b00001001111110110011100001011011;
  assign atan_table[03] = 'b00000101000100010001000111010100;
  assign atan_table[04] = 'b00000010100010110000110101000011;
  assign atan_table[05] = 'b00000001010001011101011111100001;
  assign atan_table[06] = 'b00000000101000101111011000011110;
  assign atan_table[07] = 'b00000000010100010111110001010101;
  assign atan_table[08] = 'b00000000001010001011111001010011;
  assign atan_table[09] = 'b00000000000101000101111100101110;
  assign atan_table[10] = 'b00000000000010100010111110011000;
  assign atan_table[11] = 'b00000000000001010001011111001100;
  assign atan_table[12] = 'b00000000000000101000101111100110;
  assign atan_table[13] = 'b00000000000000010100010111110011;
  assign atan_table[14] = 'b00000000000000001010001011111001;
  assign atan_table[15] = 'b00000000000000000101000101111100;
  assign atan_table[16] = 'b00000000000000000010100010111110;
  assign atan_table[17] = 'b00000000000000000001010001011111;
  assign atan_table[18] = 'b00000000000000000000101000101111;
  assign atan_table[19] = 'b00000000000000000000010100010111;
  assign atan_table[20] = 'b00000000000000000000001010001011;
  assign atan_table[21] = 'b00000000000000000000000101000101;
  assign atan_table[22] = 'b00000000000000000000000010100010;
  assign atan_table[23] = 'b00000000000000000000000001010001;
  assign atan_table[24] = 'b00000000000000000000000000101000;
  assign atan_table[25] = 'b00000000000000000000000000010100;
  assign atan_table[26] = 'b00000000000000000000000000001010;
  assign atan_table[27] = 'b00000000000000000000000000000101;
  assign atan_table[28] = 'b00000000000000000000000000000010;
  assign atan_table[29] = 'b00000000000000000000000000000001;
  assign atan_table[30] = 'b00000000000000000000000000000000;

  reg signed [width:0] x [0:width-1];
  reg signed [width:0] y [0:width-1];
  reg signed    [31:0] z [0:width-1];



  wire [1:0] quadrant;
  assign quadrant = angle[31:30];

  always @(posedge clock)
  begin
    case(quadrant)
      2'b00,
      2'b11:
      begin
        x[0] <= x_start;
        y[0] <= y_start;
        z[0] <= angle;
      end

      2'b01:
      begin
        x[0] <= -y_start;
        y[0] <= x_start;
        z[0] <= {2'b00,angle[29:0]};
      end

      2'b10:
      begin
        x[0] <= y_start;
        y[0] <= -x_start;
        z[0] <= {2'b11,angle[29:0]};
      end
    endcase
  end



  genvar i;

  generate
  for (i=0; i < (width-1); i=i+1)
  begin: xyz
    wire z_sign;
    wire signed [width:0] x_shr, y_shr;

    assign x_shr = x[i] >>> i;
    assign y_shr = y[i] >>> i;


    assign z_sign = z[i][31];

    always @(posedge clock)
    begin

      x[i+1] <= z_sign ? x[i] + y_shr : x[i] - y_shr;
      y[i+1] <= z_sign ? y[i] - x_shr : y[i] + x_shr;
      z[i+1] <= z_sign ? z[i] + atan_table[i] : z[i] - atan_table[i];
    end
  end
  endgenerate


  assign cosine = x[width-1];
  assign sine = y[width-1];

endmodule
module CORDIC(clock, cosine, sine, x_start, y_start, angle);


  parameter width = 32;


  input clock;
  input signed [width-1:0] x_start,y_start; 
  input signed [31:0] angle;


  output signed  [width-1:0] sine, cosine;


  wire signed [31:0] atan_table [0:30];
                          
  assign atan_table[00] = 'b00100000000000000000000000000000;
  assign atan_table[01] = 'b00010010111001000000010100011101;
  assign atan_table[02] = 'b00001001111110110011100001011011;
  assign atan_table[03] = 'b00000101000100010001000111010100;
  assign atan_table[04] = 'b00000010100010110000110101000011;
  assign atan_table[05] = 'b00000001010001011101011111100001;
  assign atan_table[06] = 'b00000000101000101111011000011110;
  assign atan_table[07] = 'b00000000010100010111110001010101;
  assign atan_table[08] = 'b00000000001010001011111001010011;
  assign atan_table[09] = 'b00000000000101000101111100101110;
  assign atan_table[10] = 'b00000000000010100010111110011000;
  assign atan_table[11] = 'b00000000000001010001011111001100;
  assign atan_table[12] = 'b00000000000000101000101111100110;
  assign atan_table[13] = 'b00000000000000010100010111110011;
  assign atan_table[14] = 'b00000000000000001010001011111001;
  assign atan_table[15] = 'b00000000000000000101000101111100;
  assign atan_table[16] = 'b00000000000000000010100010111110;
  assign atan_table[17] = 'b00000000000000000001010001011111;
  assign atan_table[18] = 'b00000000000000000000101000101111;
  assign atan_table[19] = 'b00000000000000000000010100010111;
  assign atan_table[20] = 'b00000000000000000000001010001011;
  assign atan_table[21] = 'b00000000000000000000000101000101;
  assign atan_table[22] = 'b00000000000000000000000010100010;
  assign atan_table[23] = 'b00000000000000000000000001010001;
  assign atan_table[24] = 'b00000000000000000000000000101000;
  assign atan_table[25] = 'b00000000000000000000000000010100;
  assign atan_table[26] = 'b00000000000000000000000000001010;
  assign atan_table[27] = 'b00000000000000000000000000000101;
  assign atan_table[28] = 'b00000000000000000000000000000010;
  assign atan_table[29] = 'b00000000000000000000000000000001;
  assign atan_table[30] = 'b00000000000000000000000000000000;

  reg signed [width:0] x [0:width-1];
  reg signed [width:0] y [0:width-1];
  reg signed    [31:0] z [0:width-1];



  wire [1:0] quadrant;
  assign quadrant = angle[31:30];

  always @(posedge clock)
  begin
    case(quadrant)
      2'b00,
      2'b11:
      begin
        x[0] <= x_start;
        y[0] <= y_start;
        z[0] <= angle;
      end

      2'b01:
      begin
        x[0] <= -y_start;
        y[0] <= x_start;
        z[0] <= {2'b00,angle[29:0]};
      end

      2'b10:
      begin
        x[0] <= y_start;
        y[0] <= -x_start;
        z[0] <= {2'b11,angle[29:0]};
      end
    endcase
  end



  genvar i;

  generate
  for (i=0; i < (width-1); i=i+1)
  begin: xyz
    wire z_sign;
    wire signed [width:0] x_shr, y_shr;

    assign x_shr = x[i] >>> i;
    assign y_shr = y[i] >>> i;


    assign z_sign = z[i][31];

    always @(posedge clock)
    begin

      x[i+1] <= z_sign ? x[i] + y_shr : x[i] - y_shr;
      y[i+1] <= z_sign ? y[i] - x_shr : y[i] + x_shr;
      z[i+1] <= z_sign ? z[i] + atan_table[i] : z[i] - atan_table[i];
    end
  end
  endgenerate


  assign cosine = x[width-1];
  assign sine = y[width-1];

endmodule