data/full_repos/permissive/19591557/modules/spinnaker_link/spio_spinnaker_link_sync2.v
data/verilator_xmls/9afde88c-177a-4d67-b05b-c30f9ec4baf7.xml
module spio_spinnaker_link_sync2 #
(
  parameter SIZE = 1
)
(
  input                   CLK0_IN,
  input                   CLK1_IN,
  input      [SIZE - 1:0] IN,
  output reg [SIZE - 1:0] OUT
);




  reg  [SIZE - 1:0] sync;

   




  always @ (posedge CLK0_IN)
       sync <= IN;

  always @ (posedge CLK1_IN)
       OUT  <= sync;

endmodule
module spio_spinnaker_link_sync2 #
(
  parameter SIZE = 1
)
(
  input                   CLK0_IN,
  input                   CLK1_IN,
  input      [SIZE - 1:0] IN,
  output reg [SIZE - 1:0] OUT
);





  reg  [SIZE - 1:0] sync;

   




  always @ (posedge CLK0_IN)
       sync <= IN;

  always @ (posedge CLK1_IN)
       OUT  <= sync;

endmodule