data/full_repos/permissive/127519632/cpu_tb.sv
 line:72: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/127519632/cpu_tb.sv:65: Unsupported: Ignoring delay on this delayed statement.\n #11\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/127519632/cpu_tb.sv:67: Unsupported: Ignoring delay on this delayed statement.\n #22\n ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/cpu_tb.sv:71: Unsupported: Ignoring delay on this delayed statement.\n #10000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/cpu_tb.sv:76: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/cpu_tb.sv:78: Unsupported: Ignoring delay on this delayed statement.\nalways #1 instruction_bus[3:0] = random_out;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/cpu_tb.sv:79: Unsupported: Ignoring delay on this delayed statement.\nalways #1 instruction_bus[7:4] = random_out_1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/cpu_tb.sv:80: Unsupported: Ignoring delay on this delayed statement.\nalways #1 instruction_bus[11:8] = random_out_2;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/cpu_tb.sv:81: Unsupported: Ignoring delay on this delayed statement.\nalways #1 enable_n_1 = carry;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/127519632/cpu_tb.sv:82: Unsupported: Ignoring delay on this delayed statement.\nalways #1 enable_n_2 = carry_1;\n       ^\n%Error: data/full_repos/permissive/127519632/cpu_tb.sv:15: Cannot find file containing module: \'cpu\'\ncpu U1(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/cpu\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/cpu.v\n             data/full_repos/permissive/127519632,data/full_repos/permissive/127519632/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: data/full_repos/permissive/127519632/cpu_tb.sv:32: Cannot find file containing module: \'lfsr\'\nlfsr U2(\n^~~~\n%Error: data/full_repos/permissive/127519632/cpu_tb.sv:40: Cannot find file containing module: \'lfsr\'\nlfsr U3(\n^~~~\n%Error: data/full_repos/permissive/127519632/cpu_tb.sv:48: Cannot find file containing module: \'lfsr\'\nlfsr U4(\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/127519632/cpu_tb.sv:64: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                 : ... In instance cpu_tb\n reset_in = 2\'b0001;\n          ^\n%Error: Exiting due to 4 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_tb;


wire ram_RW, ram_EN;
wire [7:0]ram_address_bus;
wire [3:0]ram_data_bus_out;
wire [3:0]ram_data_bus_in;

reg clk, rst_n;
reg [11:0]instruction_bus;


cpu U1(
	ram_RW,
	ram_EN,
	ram_address_bus,
	ram_data_bus_out,
	ram_data_bus_in,
	instruction_bus,
	rst_n,
	clk);


wire carry, carry_1, carry_2;
wire [3:0]random_out, random_out_1, random_out_2;
reg [3:0]reset_in;
reg enable_n, enable_n_1, enable_n_2;


lfsr U2(
	carry,
	random_out,
	reset_in,
	enable_n,
	rst_n,
	clk);

lfsr U3(
	carry_1,
	random_out_1,
	reset_in,
	enable_n_1,
	rst_n,
	clk);

lfsr U4(
	carry_2,
	random_out_2,
	reset_in,
	enable_n_2,
	rst_n,
	clk);

integer file_cut;



initial begin
	rst_n = 0;
	clk = 0;
	enable_n = 0;
	reset_in = 2'b0001;
	#11
	rst_n = 1;
	#22
	rst_n = 1;
	enable_n = 1;
	rst_n = 1;
	#10000
	$stop;
end


always #5 clk = ~clk;

always #1 instruction_bus[3:0] = random_out;
always #1 instruction_bus[7:4] = random_out_1;
always #1 instruction_bus[11:8] = random_out_2;
always #1 enable_n_1 = carry;
always #1 enable_n_2 = carry_1;


always @(posedge clk) begin
	$display(random_out);
end

initial file_cut = $fopen("./qqqwwwqqq.txt", "w");

always @(posedge clk) begin
	$fwrite(file_cut, "clk = %d", clk);
end

endmodule
module cpu_tb;



wire ram_RW, ram_EN;
wire [7:0]ram_address_bus;
wire [3:0]ram_data_bus_out;
wire [3:0]ram_data_bus_in;

reg clk, rst_n;
reg [11:0]instruction_bus;


cpu U1(
	ram_RW,
	ram_EN,
	ram_address_bus,
	ram_data_bus_out,
	ram_data_bus_in,
	instruction_bus,
	rst_n,
	clk);


wire carry, carry_1, carry_2;
wire [3:0]random_out, random_out_1, random_out_2;
reg [3:0]reset_in;
reg enable_n, enable_n_1, enable_n_2;


lfsr U2(
	carry,
	random_out,
	reset_in,
	enable_n,
	rst_n,
	clk);

lfsr U3(
	carry_1,
	random_out_1,
	reset_in,
	enable_n_1,
	rst_n,
	clk);

lfsr U4(
	carry_2,
	random_out_2,
	reset_in,
	enable_n_2,
	rst_n,
	clk);

integer file_cut;



initial begin
	rst_n = 0;
	clk = 0;
	enable_n = 0;
	reset_in = 2'b0001;
	#11
	rst_n = 1;
	#22
	rst_n = 1;
	enable_n = 1;
	rst_n = 1;
	#10000
	$stop;
end


always #5 clk = ~clk;

always #1 instruction_bus[3:0] = random_out;
always #1 instruction_bus[7:4] = random_out_1;
always #1 instruction_bus[11:8] = random_out_2;
always #1 enable_n_1 = carry;
always #1 enable_n_2 = carry_1;


always @(posedge clk) begin
	$display(random_out);
end

initial file_cut = $fopen("./qqqwwwqqq.txt", "w");

always @(posedge clk) begin
	$fwrite(file_cut, "clk = %d", clk);
end

endmodule