data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v
 line:64: before: "("
1: b"%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v:65: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v:70: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v:72: Unsupported: wait statements\n    wait (mst_pready);\n    ^~~~\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v:73: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v:84: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v:88: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v:90: Unsupported: wait statements\n    wait (mst_pready);\n    ^~~~\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v:91: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v:134: syntax error, unexpected '@'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v:145: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v:147: syntax error, unexpected '@'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/apb/sim/apb_master_sim.v:195: syntax error, unexpected '@'\n    @(negedge rst);\n    ^\n%Error: Exiting due to 12 error(s)\n"
module apb_master_sim #(
  parameter Filename = "undefined",
  parameter Verbose  = 1)
(
  input             clk,
  input             rst,
  output reg [31:0] mst_paddr,
  output reg        mst_pwrite,
  output reg [31:0] mst_pwdata,
  output reg        mst_psel,
  output reg        mst_penable,
  input             mst_pready,
  input [31:0]      mst_prdata,
  input             mst_pslverr,
  input [31:0]      irq,
  output reg        done,
  output reg        err
);





  task do_write(input [31:0] addr, input [31:0] data); begin
    @(posedge clk);
    mst_paddr   <= addr;
    mst_pwdata  <= data;
    mst_pwrite  <= 1;
    mst_psel    <= 1;
    @(posedge clk);
    mst_penable <= 1;
    wait (mst_pready);
    @(posedge clk);
    mst_psel    <= 0;
    mst_penable <= 0;
    if (Verbose) begin
      $display("@%0t %0s: wrote 0x%08x to address 0x%08x",
                   $time, Filename, data, addr);
    end
  end endtask


  task do_read(input [31:0] addr); begin
    @(posedge clk);
    mst_paddr  <= addr;
    mst_pwrite <= 0;
    mst_psel   <= 1;
    @(posedge clk);
    mst_penable <= 1;
    wait (mst_pready);
    @(posedge clk);
    mst_psel       <= 0;
    mst_penable    <= 0;
  end endtask


  task do_read_check(input [31:0] addr, input [31:0] expected); begin
    do_read(addr);
    if (mst_prdata !== expected) begin
      $display("@%0t %0s: Error, read 0x%x from address 0x%x, expected 0x%x",
               $time, Filename, mst_prdata, addr, expected);
      err <= 1;
    end else if (Verbose) begin
      $display("@%0t %0s: read 0x%08x from address 0x%08x",
               $time, Filename, mst_prdata, addr);
    end
  end endtask


  task do_read_poll(input [31:0] addr, input [31:0] value); begin
    if (Verbose) begin
      $display("@%0t %0s: polling address 0x%08x until it equals 0x%08x",
               $time, Filename, addr, value);
    end
    do_read(addr);
    while (mst_prdata !== value) begin
      do_read(addr);
    end
    if (Verbose) begin
      $display("@%0t %0s: read 0x%08x from address 0x%08x, done polling",
               $time, Filename, mst_prdata, addr);
    end
  end endtask


  task do_stall(input integer cycles);
    integer i;
    begin
      if (Verbose) begin
        $display("@%0t %0s: stalling for %0d cycles", $time, Filename, cycles);
      end
      i  = 0;
      while (i < cycles) begin
        @(posedge clk);
        i = i + 1;
      end
    end
  endtask


  task do_wait(input integer irq_num); begin
    if (Verbose) begin
      $display("@%0t %0s: waiting for interrupt[%0d]", $time, Filename, irq_num);
    end
    @(posedge clk);
    while (!irq[irq_num]) begin
      @(posedge clk);
    end
    if (Verbose) begin
      $display("@%0t %0s: received interrupt[%0d]", $time, Filename, irq_num);
    end
  end endtask

  task fail(); begin
    $display("***SIMULATION FAILED***");
    $finish;
  end endtask

  task format_error(input integer line_num); begin
    $display("%0s: invalid format on line %0d", Filename, line_num);
    fail();
  end endtask




  localparam [2*8-1:0] ReadInstr   = "RD",
                       PollInstr   = "RP",
                       WriteInstr  = "WR",
                       WaitInstr   = "WT",
                       StallInstr  = "ST";

  integer         fp, r;
  integer         stall_cycles, irq_num, line_count;
  reg [31:0]      addr, data, expected;
  reg [256*8-1:0] junk;
  reg [2*8-1:0]   instr;

  initial begin


    fp = $fopen(Filename, "r");
    if (!fp) begin
      $display("Error: unable to open file \"%0s\"", Filename);
      fail();
    end


    err          = 0;
    done         = 0;
    line_count   = 0;
    mst_psel     = 0;
    mst_pwrite   = 0;
    mst_penable  = 0;
    @(negedge rst);


    while (!done) begin
      r = $fscanf(fp, "%0s", instr);

      line_count = line_count + 1;


      if (r >= 1 && instr[7:0] != "#") begin

        case (instr)
          ReadInstr:
            begin
              r  = $fscanf(fp, "%x %x", addr, expected);
              if (r != 2) format_error(line_count);
              do_read_check(addr, expected);
            end

          PollInstr:
            begin
              r  = $fscanf(fp, "%x %x", addr, expected);
              if (r != 2) format_error(line_count);
              do_read_poll(addr, expected);
            end

          WriteInstr:
            begin
              r  = $fscanf(fp, "%x %x", addr, data);
              if (r != 2) format_error(line_count);
              do_write(addr, data);
            end

          WaitInstr:
            begin
              r  = $fscanf(fp, "%d", irq_num);
              if (r != 1) format_error(line_count);
              do_wait(irq_num);
            end

          StallInstr:
            begin
              r  = $fscanf(fp, "%d", stall_cycles);
              if (r != 1) format_error(line_count);
              do_stall(stall_cycles);
            end

          default:
            format_error(line_count);

        endcase
      end


      r = $fgets(junk, fp);
      if ($feof(fp)) begin
        done = 1;
        $fclose(fp);
      end
    end

    $display ("%0s: reached end of file", Filename);

  end

endmodule
module apb_master_sim #(
  parameter Filename = "undefined",
  parameter Verbose  = 1)
(
  input             clk,
  input             rst,
  output reg [31:0] mst_paddr,
  output reg        mst_pwrite,
  output reg [31:0] mst_pwdata,
  output reg        mst_psel,
  output reg        mst_penable,
  input             mst_pready,
  input [31:0]      mst_prdata,
  input             mst_pslverr,
  input [31:0]      irq,
  output reg        done,
  output reg        err
);






  task do_write(input [31:0] addr, input [31:0] data); begin
    @(posedge clk);
    mst_paddr   <= addr;
    mst_pwdata  <= data;
    mst_pwrite  <= 1;
    mst_psel    <= 1;
    @(posedge clk);
    mst_penable <= 1;
    wait (mst_pready);
    @(posedge clk);
    mst_psel    <= 0;
    mst_penable <= 0;
    if (Verbose) begin
      $display("@%0t %0s: wrote 0x%08x to address 0x%08x",
                   $time, Filename, data, addr);
    end
  end endtask


  task do_read(input [31:0] addr); begin
    @(posedge clk);
    mst_paddr  <= addr;
    mst_pwrite <= 0;
    mst_psel   <= 1;
    @(posedge clk);
    mst_penable <= 1;
    wait (mst_pready);
    @(posedge clk);
    mst_psel       <= 0;
    mst_penable    <= 0;
  end endtask


  task do_read_check(input [31:0] addr, input [31:0] expected); begin
    do_read(addr);
    if (mst_prdata !== expected) begin
      $display("@%0t %0s: Error, read 0x%x from address 0x%x, expected 0x%x",
               $time, Filename, mst_prdata, addr, expected);
      err <= 1;
    end else if (Verbose) begin
      $display("@%0t %0s: read 0x%08x from address 0x%08x",
               $time, Filename, mst_prdata, addr);
    end
  end endtask


  task do_read_poll(input [31:0] addr, input [31:0] value); begin
    if (Verbose) begin
      $display("@%0t %0s: polling address 0x%08x until it equals 0x%08x",
               $time, Filename, addr, value);
    end
    do_read(addr);
    while (mst_prdata !== value) begin
      do_read(addr);
    end
    if (Verbose) begin
      $display("@%0t %0s: read 0x%08x from address 0x%08x, done polling",
               $time, Filename, mst_prdata, addr);
    end
  end endtask


  task do_stall(input integer cycles);
    integer i;
    begin
      if (Verbose) begin
        $display("@%0t %0s: stalling for %0d cycles", $time, Filename, cycles);
      end
      i  = 0;
      while (i < cycles) begin
        @(posedge clk);
        i = i + 1;
      end
    end
  endtask


  task do_wait(input integer irq_num); begin
    if (Verbose) begin
      $display("@%0t %0s: waiting for interrupt[%0d]", $time, Filename, irq_num);
    end
    @(posedge clk);
    while (!irq[irq_num]) begin
      @(posedge clk);
    end
    if (Verbose) begin
      $display("@%0t %0s: received interrupt[%0d]", $time, Filename, irq_num);
    end
  end endtask

  task fail(); begin
    $display("***SIMULATION FAILED***");
    $finish;
  end endtask

  task format_error(input integer line_num); begin
    $display("%0s: invalid format on line %0d", Filename, line_num);
    fail();
  end endtask




  localparam [2*8-1:0] ReadInstr   = "RD",
                       PollInstr   = "RP",
                       WriteInstr  = "WR",
                       WaitInstr   = "WT",
                       StallInstr  = "ST";

  integer         fp, r;
  integer         stall_cycles, irq_num, line_count;
  reg [31:0]      addr, data, expected;
  reg [256*8-1:0] junk;
  reg [2*8-1:0]   instr;

  initial begin


    fp = $fopen(Filename, "r");
    if (!fp) begin
      $display("Error: unable to open file \"%0s\"", Filename);
      fail();
    end


    err          = 0;
    done         = 0;
    line_count   = 0;
    mst_psel     = 0;
    mst_pwrite   = 0;
    mst_penable  = 0;
    @(negedge rst);


    while (!done) begin
      r = $fscanf(fp, "%0s", instr);

      line_count = line_count + 1;


      if (r >= 1 && instr[7:0] != "#") begin

        case (instr)
          ReadInstr:
            begin
              r  = $fscanf(fp, "%x %x", addr, expected);
              if (r != 2) format_error(line_count);
              do_read_check(addr, expected);
            end

          PollInstr:
            begin
              r  = $fscanf(fp, "%x %x", addr, expected);
              if (r != 2) format_error(line_count);
              do_read_poll(addr, expected);
            end

          WriteInstr:
            begin
              r  = $fscanf(fp, "%x %x", addr, data);
              if (r != 2) format_error(line_count);
              do_write(addr, data);
            end

          WaitInstr:
            begin
              r  = $fscanf(fp, "%d", irq_num);
              if (r != 1) format_error(line_count);
              do_wait(irq_num);
            end

          StallInstr:
            begin
              r  = $fscanf(fp, "%d", stall_cycles);
              if (r != 1) format_error(line_count);
              do_stall(stall_cycles);
            end

          default:
            format_error(line_count);

        endcase
      end


      r = $fgets(junk, fp);
      if ($feof(fp)) begin
        done = 1;
        $fclose(fp);
      end
    end

    $display ("%0s: reached end of file", Filename);

  end

endmodule