data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v
1: b'%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:55: Cannot find file containing module: \'PC\'\n    PC #(32) pcreg(clk, reset, pcnext, pc);\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/PC\n             data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/PC.v\n             data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new,data/full_repos/permissive/169258653/PC.sv\n             PC\n             PC.v\n             PC.sv\n             obj_dir/PC\n             obj_dir/PC.v\n             obj_dir/PC.sv\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:56: Cannot find file containing module: \'adder\'\n    adder pcadd1(pc, 32\'b100, pcplus4);\n    ^~~~~\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:57: Cannot find file containing module: \'sl2\'\n    sl2 immsh(signimm,signimmsh);\n    ^~~\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:58: Cannot find file containing module: \'adder\'\n    adder pcadd2(pcplus4,signimmsh,pcbranch);\n    ^~~~~\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:59: Cannot find file containing module: \'MUX2\'\n    MUX2 #(32) pcbrmux(pcplus4, pcbranch, pcsrc, pcnextbr);\n    ^~~~\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:60: Cannot find file containing module: \'MUX2\'\n    MUX2 #(32) pcmux(pcnextbr, {pcplus4[31:28], instr[25:0], 2\'b00}, jump, pcnext);\n    ^~~~\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:65: Cannot find file containing module: \'regfile\'\n    regfile rf(clk, regwrite, instr[25:21], instr[20:16], writereg,instr[10:6], result, srca, writedata,alusrca,pc,swt,tx,disopx);\n    ^~~~~~~\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:66: Cannot find file containing module: \'MUX4\'\n    MUX4 #(5) wrmux(instr[20:16], instr[15:11],5\'b11111,5\'b00000, regdst, writereg);\n    ^~~~\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:67: Cannot find file containing module: \'MUX2\'\n    MUX2 #(32) resmux(aluout, readdata, mem2reg, result);\n    ^~~~\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:68: Cannot find file containing module: \'sign_extend\'\n    sign_extend se(instr[15:0], extend, signimm);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:72: Cannot find file containing module: \'MUX4\'\n    MUX4 #(32) srcbmux(writedata, signimm, 32\'b100,32\'b1000,alusrcb, srcb);\n    ^~~~\n%Error: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:73: Cannot find file containing module: \'ALU\'\n    ALU alu0(srca, srcb, alucontrol, aluout, zero);\n    ^~~\n%Warning-WIDTH: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:93: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'pcsrc\' generates 1 bits.\n                                                                                                                                               : ... In instance datapath\n            6\'b000111:begin t<=pcsrc;disop<=ONE; end\n                             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:99: Unsized numbers/parameters not allowed in replications.\n                                                                                                                                                     : ... In instance datapath\n            6\'b000000:begin t<={{27{0}},writereg};disop<=TWO; end\n                                    ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:99: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                                                                     : ... In instance datapath\n            6\'b000000:begin t<={{27{0}},writereg};disop<=TWO; end\n                                   ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:99: Unsized numbers/parameters not allowed in replications.\n                                                                                                                                                     : ... In instance datapath\n            6\'b000000:begin t<={{27{0}},writereg};disop<=TWO; end\n                                       ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:114: Unsized numbers/parameters not allowed in replications.\n                                                                                                                                                      : ... In instance datapath\n            6\'b000011:begin t<={{31{0}},zero};disop<=ONE; end\n                                    ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:114: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                                                                      : ... In instance datapath\n            6\'b000011:begin t<={{31{0}},zero};disop<=ONE; end\n                                   ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/169258653/monocycle/MIPS_single_cycle_32bit/MIPS_single_cycle_32bit.srcs/sources_1/new/datapath.v:114: Unsized numbers/parameters not allowed in replications.\n                                                                                                                                                      : ... In instance datapath\n            6\'b000011:begin t<={{31{0}},zero};disop<=ONE; end\n                                       ^\n%Error: Exiting due to 12 error(s), 7 warning(s)\n'
module datapath(
    input clk,reset,
    input mem2reg,pcsrc,
    input [1:0] alusrca,
    input [1:0] alusrcb,
    input [1:0] regdst,
    input regwrite, jump,
    input [3:0] alucontrol,
    output zero,
    output [31:0] pc,
    input [31:0] instr,
    output [31:0] aluout,writedata,
    input [31:0] readdata,
    input extend,
    input [9:0] swt,
    output reg [31:0] t,
    output reg [7:0] disop
    );
    
    wire [4:0] writereg;
    wire [31:0] pcnext,pcnextbr,pcplus4,pcbranch;
    wire [31:0] signimm,signimmsh;
    wire [31:0] srca,srcb;
    wire [31:0] result;
    

    wire [31:0] tx;
    wire [7:0] disopx;
    



    PC #(32) pcreg(clk, reset, pcnext, pc);
    adder pcadd1(pc, 32'b100, pcplus4);
    sl2 immsh(signimm,signimmsh);
    adder pcadd2(pcplus4,signimmsh,pcbranch);
    MUX2 #(32) pcbrmux(pcplus4, pcbranch, pcsrc, pcnextbr);
    MUX2 #(32) pcmux(pcnextbr, {pcplus4[31:28], instr[25:0], 2'b00}, jump, pcnext);
    



    regfile rf(clk, regwrite, instr[25:21], instr[20:16], writereg,instr[10:6], result, srca, writedata,alusrca,pc,swt,tx,disopx);
    MUX4 #(5) wrmux(instr[20:16], instr[15:11],5'b11111,5'b00000, regdst, writereg);
    MUX2 #(32) resmux(aluout, readdata, mem2reg, result);
    sign_extend se(instr[15:0], extend, signimm);
    


    MUX4 #(32) srcbmux(writedata, signimm, 32'b100,32'b1000,alusrcb, srcb);
    ALU alu0(srca, srcb, alucontrol, aluout, zero);
    

    parameter EIGHT=8'b11111111;
    parameter ZERO=8'b00000000;
    parameter TWO=8'b00000011;
    parameter ONE=8'b1;
    always@(*)
    begin
        case(swt[9:6])

        4'b0000:
            case(swt[5:0])
            6'b000000:begin t<=pc;disop<=EIGHT; end
            6'b000001:begin t<=pcnext;disop<=EIGHT; end
            6'b000010:begin t<=pcplus4;disop<=EIGHT; end
            6'b000011:begin t<=signimm;disop<=EIGHT; end
            6'b000100:begin t<=signimmsh;disop<=EIGHT; end
            6'b000101:begin t<=pcbranch;disop<=EIGHT; end
            6'b000110:begin t<=pcnextbr;disop<=EIGHT; end
            6'b000111:begin t<=pcsrc;disop<=ONE; end
            default:begin t<=0;disop<=ZERO; end
            endcase

        4'b0001:
            case(swt[5:0])
            6'b000000:begin t<={{27{0}},writereg};disop<=TWO; end
            6'b000001:begin t<=result;disop<=EIGHT; end
            6'b000010:begin t<=srca;disop<=EIGHT; end
            6'b000011:begin t<=writedata;disop<=EIGHT; end
            default:begin t<=0;disop<=ZERO; end
            endcase

        4'b0010:
            begin t<=tx;disop<=disopx; end

        4'b0011:
            case(swt[5:0])
            6'b000000:begin t<=srca;disop<=EIGHT; end
            6'b000001:begin t<=srcb;disop<=EIGHT; end
            6'b000010:begin t<=aluout;disop<=EIGHT; end
            6'b000011:begin t<={{31{0}},zero};disop<=ONE; end
            default:begin t<=0;disop<=ZERO; end
            endcase
        default:
            begin t<=0;disop<=ZERO; end
        endcase
    end
    
endmodule
module datapath(
    input clk,reset,
    input mem2reg,pcsrc,
    input [1:0] alusrca,
    input [1:0] alusrcb,
    input [1:0] regdst,
    input regwrite, jump,
    input [3:0] alucontrol,
    output zero,
    output [31:0] pc,
    input [31:0] instr,
    output [31:0] aluout,writedata,
    input [31:0] readdata,
    input extend,
    input [9:0] swt,
    output reg [31:0] t,
    output reg [7:0] disop
    );

    
    wire [4:0] writereg;
    wire [31:0] pcnext,pcnextbr,pcplus4,pcbranch;
    wire [31:0] signimm,signimmsh;
    wire [31:0] srca,srcb;
    wire [31:0] result;
    

    wire [31:0] tx;
    wire [7:0] disopx;
    



    PC #(32) pcreg(clk, reset, pcnext, pc);
    adder pcadd1(pc, 32'b100, pcplus4);
    sl2 immsh(signimm,signimmsh);
    adder pcadd2(pcplus4,signimmsh,pcbranch);
    MUX2 #(32) pcbrmux(pcplus4, pcbranch, pcsrc, pcnextbr);
    MUX2 #(32) pcmux(pcnextbr, {pcplus4[31:28], instr[25:0], 2'b00}, jump, pcnext);
    



    regfile rf(clk, regwrite, instr[25:21], instr[20:16], writereg,instr[10:6], result, srca, writedata,alusrca,pc,swt,tx,disopx);
    MUX4 #(5) wrmux(instr[20:16], instr[15:11],5'b11111,5'b00000, regdst, writereg);
    MUX2 #(32) resmux(aluout, readdata, mem2reg, result);
    sign_extend se(instr[15:0], extend, signimm);
    


    MUX4 #(32) srcbmux(writedata, signimm, 32'b100,32'b1000,alusrcb, srcb);
    ALU alu0(srca, srcb, alucontrol, aluout, zero);
    

    parameter EIGHT=8'b11111111;
    parameter ZERO=8'b00000000;
    parameter TWO=8'b00000011;
    parameter ONE=8'b1;
    always@(*)
    begin
        case(swt[9:6])

        4'b0000:
            case(swt[5:0])
            6'b000000:begin t<=pc;disop<=EIGHT; end
            6'b000001:begin t<=pcnext;disop<=EIGHT; end
            6'b000010:begin t<=pcplus4;disop<=EIGHT; end
            6'b000011:begin t<=signimm;disop<=EIGHT; end
            6'b000100:begin t<=signimmsh;disop<=EIGHT; end
            6'b000101:begin t<=pcbranch;disop<=EIGHT; end
            6'b000110:begin t<=pcnextbr;disop<=EIGHT; end
            6'b000111:begin t<=pcsrc;disop<=ONE; end
            default:begin t<=0;disop<=ZERO; end
            endcase

        4'b0001:
            case(swt[5:0])
            6'b000000:begin t<={{27{0}},writereg};disop<=TWO; end
            6'b000001:begin t<=result;disop<=EIGHT; end
            6'b000010:begin t<=srca;disop<=EIGHT; end
            6'b000011:begin t<=writedata;disop<=EIGHT; end
            default:begin t<=0;disop<=ZERO; end
            endcase

        4'b0010:
            begin t<=tx;disop<=disopx; end

        4'b0011:
            case(swt[5:0])
            6'b000000:begin t<=srca;disop<=EIGHT; end
            6'b000001:begin t<=srcb;disop<=EIGHT; end
            6'b000010:begin t<=aluout;disop<=EIGHT; end
            6'b000011:begin t<={{31{0}},zero};disop<=ONE; end
            default:begin t<=0;disop<=ZERO; end
            endcase
        default:
            begin t<=0;disop<=ZERO; end
        endcase
    end
    
endmodule