data/full_repos/permissive/113454857/lock_in+pid/fpga/rtl/lock/debounce.v
data/verilator_xmls/e322494c-72b2-49fb-a085-a170c2d7df41.xml
module debounce #(parameter N0=7 , N1=4)
   (
    input wire clk, reset,
    input wire in,
    output reg db_level, db_tick
   );
   

   

   localparam  [1:0]
               zero  = 2'b00,
               wait0 = 2'b01,
               one   = 2'b10,
               wait1 = 2'b11;
   

   reg [N0-1:0] q_reg, q_next;
   reg [1:0] state_reg, state_next;



    always @(posedge clk, posedge reset)
       if (reset)
          begin
             state_reg <= zero;
             q_reg <= 0;
          end
       else
          begin
             state_reg <= state_next;
             q_reg <= q_next;
          end


   always @*
   begin
      state_next = state_reg;
      q_next = q_reg;
      db_tick = 1'b0;
      case (state_reg)
         zero:
            begin
               db_level = 1'b0;
               if (in)
                  begin
                     state_next = wait1;
                     q_next = {N0{1'b1}};
                  end
            end
         wait1:
            begin
               db_level = 1'b0;
               if (in)
                  begin
                     q_next = q_reg - 1;
                     if (q_next==0)
                        begin
                           state_next = one;
                           db_tick = 1'b1;
                        end
                  end
               else
                  state_next = zero;
            end
         one:
            begin
               db_level = 1'b1;
               if (~in)
                  begin
                     state_next = wait0;
                     q_next = { {N0-N1{1'b0}}  , {N1{1'b1}}  };
                  end
            end
         wait0:
            begin
               db_level = 1'b1;
               if (~in)
                  begin
                     q_next = q_reg - 1;
                     if (q_next==0)
                        state_next = zero;
                  end
               else
                  state_next = one;

            end
         default: state_next = zero;
      endcase
   end

endmodule
module debounce #(parameter N0=7 , N1=4)
   (
    input wire clk, reset,
    input wire in,
    output reg db_level, db_tick
   );

   

   

   localparam  [1:0]
               zero  = 2'b00,
               wait0 = 2'b01,
               one   = 2'b10,
               wait1 = 2'b11;
   

   reg [N0-1:0] q_reg, q_next;
   reg [1:0] state_reg, state_next;



    always @(posedge clk, posedge reset)
       if (reset)
          begin
             state_reg <= zero;
             q_reg <= 0;
          end
       else
          begin
             state_reg <= state_next;
             q_reg <= q_next;
          end


   always @*
   begin
      state_next = state_reg;
      q_next = q_reg;
      db_tick = 1'b0;
      case (state_reg)
         zero:
            begin
               db_level = 1'b0;
               if (in)
                  begin
                     state_next = wait1;
                     q_next = {N0{1'b1}};
                  end
            end
         wait1:
            begin
               db_level = 1'b0;
               if (in)
                  begin
                     q_next = q_reg - 1;
                     if (q_next==0)
                        begin
                           state_next = one;
                           db_tick = 1'b1;
                        end
                  end
               else
                  state_next = zero;
            end
         one:
            begin
               db_level = 1'b1;
               if (~in)
                  begin
                     state_next = wait0;
                     q_next = { {N0-N1{1'b0}}  , {N1{1'b1}}  };
                  end
            end
         wait0:
            begin
               db_level = 1'b1;
               if (~in)
                  begin
                     q_next = q_reg - 1;
                     if (q_next==0)
                        state_next = zero;
                  end
               else
                  state_next = one;

            end
         default: state_next = zero;
      endcase
   end

endmodule