data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v
 line:105: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:121: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'INIT_CTL_TARGET\' generates 1 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n            reg_ctl_target  <= INIT_CTL_TARGET;\n                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:169: Operator ADD expects 48 bits on the RHS, but RHS\'s VARREF \'reg_v\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                reg_cur_x <= reg_cur_x + reg_v;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:179: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_ctl_enable\' generates 1 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_CTL_ENABLE:  reg_ctl_enable  <= reg_mask(reg_ctl_enable,  s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:179: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_CTL_ENABLE:  reg_ctl_enable  <= reg_mask(reg_ctl_enable,  s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:180: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_ctl_target\' generates 3 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_CTL_TARGET:  reg_ctl_target  <= reg_mask(reg_ctl_target,  s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:180: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_CTL_TARGET:  reg_ctl_target  <= reg_mask(reg_ctl_target,  s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:181: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_ctl_pwm\' generates 2 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_CTL_PWM:     reg_ctl_pwm     <= reg_mask(reg_ctl_pwm,     s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:181: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_CTL_PWM:     reg_ctl_pwm     <= reg_mask(reg_ctl_pwm,     s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:182: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_target_x\' generates 48 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_TARGET_X:    reg_target_x    <= reg_mask(reg_target_x,    s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:182: Operator ASSIGNDLY expects 48 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_TARGET_X:    reg_target_x    <= reg_mask(reg_target_x,    s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:183: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_target_v\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_TARGET_V:    reg_target_v    <= reg_mask(reg_target_v,    s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:183: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_TARGET_V:    reg_target_v    <= reg_mask(reg_target_v,    s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:184: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_target_a\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_TARGET_A:    reg_target_a    <= reg_mask(reg_target_a,    s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:184: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_TARGET_A:    reg_target_a    <= reg_mask(reg_target_a,    s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:185: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_max_v\' generates 24 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_MAX_V:       reg_max_v       <= reg_mask(reg_max_v,       s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:185: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_MAX_V:       reg_max_v       <= reg_mask(reg_max_v,       s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:186: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_max_a\' generates 24 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_MAX_A:       reg_max_a       <= reg_mask(reg_max_a,       s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:186: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_MAX_A:       reg_max_a       <= reg_mask(reg_max_a,       s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:187: Operator FUNCREF \'reg_mask\' expects 64 bits on the Function Argument, but Function Argument\'s VARREF \'reg_max_a_near\' generates 24 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_MAX_A_NEAR:  reg_max_a_near  <= reg_mask(reg_max_a_near,  s_wb_dat_i, s_wb_sel_i);\n                                                    ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:187: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 64 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                ADR_MAX_A_NEAR:  reg_max_a_near  <= reg_mask(reg_max_a_near,  s_wb_dat_i, s_wb_sel_i);\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:178: Operator CASE expects 8 bits on the Case expression, but Case expression\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                case ( s_wb_adr_i )\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:193: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n    assign s_wb_dat_o = (s_wb_adr_i == ADR_CORE_ID)     ? CORE_ID                 :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:194: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CTL_ENABLE)  ? reg_ctl_enable          :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:195: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CTL_TARGET)  ? reg_ctl_target          :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:196: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CTL_PWM)     ? reg_ctl_pwm             :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:197: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TARGET_X)    ? reg_target_x            :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:198: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TARGET_V)    ? reg_target_v            :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:199: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TARGET_A)    ? reg_target_a            :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:200: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_MAX_V)       ? reg_max_v               :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:201: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_MAX_A)       ? reg_max_a               :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:202: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_MAX_A_NEAR)  ? reg_max_a_near          :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:203: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CUR_X)       ? (reg_cur_x >>> X_SHIFT) :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:204: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CUR_V)       ? reg_cur_v               :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:205: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CUR_A)       ? reg_cur_a               :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:206: Operator EQ expects 8 bits on the LHS, but LHS\'s VARREF \'s_wb_adr_i\' generates 6 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TIME)        ? reg_time                :\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:193: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'CORE_ID\' generates 32 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n    assign s_wb_dat_o = (s_wb_adr_i == ADR_CORE_ID)     ? CORE_ID                 :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:194: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_ctl_enable\' generates 1 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CTL_ENABLE)  ? reg_ctl_enable          :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:195: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_ctl_target\' generates 3 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CTL_TARGET)  ? reg_ctl_target          :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:196: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_ctl_pwm\' generates 2 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CTL_PWM)     ? reg_ctl_pwm             :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:197: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_target_x\' generates 48 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TARGET_X)    ? reg_target_x            :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:198: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_target_v\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TARGET_V)    ? reg_target_v            :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:199: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_target_a\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TARGET_A)    ? reg_target_a            :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:200: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_max_v\' generates 24 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_MAX_V)       ? reg_max_v               :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:201: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_max_a\' generates 24 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_MAX_A)       ? reg_max_a               :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:202: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_max_a_near\' generates 24 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_MAX_A_NEAR)  ? reg_max_a_near          :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:203: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'reg_cur_x\' generates 48 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CUR_X)       ? (reg_cur_x >>> X_SHIFT) :\n                                                                     ^~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:204: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_cur_v\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CUR_V)       ? reg_cur_v               :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:205: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_cur_a\' generates 25 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_CUR_A)       ? reg_cur_a               :\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:206: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'reg_time\' generates 32 bits.\n                                                                                                                 : ... In instance stepper_motor_control\n                        (s_wb_adr_i == ADR_TIME)        ? reg_time                :\n                                                        ^\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:212: Cannot find file containing module: \'stepper_motor_control_calc\'\n    stepper_motor_control_calc\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl,data/full_repos/permissive/2084115/stepper_motor_control_calc\n             data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl,data/full_repos/permissive/2084115/stepper_motor_control_calc.v\n             data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl,data/full_repos/permissive/2084115/stepper_motor_control_calc.sv\n             stepper_motor_control_calc\n             stepper_motor_control_calc.v\n             stepper_motor_control_calc.sv\n             obj_dir/stepper_motor_control_calc\n             obj_dir/stepper_motor_control_calc.v\n             obj_dir/stepper_motor_control_calc.sv\n%Error: data/full_repos/permissive/2084115/projects/zybo_z7_stepper_motor/rtl/stepper_motor_control.v:237: Cannot find file containing module: \'bipolar_stepper_motor_drive\'\n    bipolar_stepper_motor_drive\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 49 warning(s)\n'
module stepper_motor_control
        #(
            parameter   CORE_ID          = 32'h5a5a_5a5a,
            
            parameter   WB_ADR_WIDTH     = 6,
            parameter   WB_DAT_SIZE      = 3,
            parameter   WB_DAT_WIDTH     = (8 << WB_DAT_SIZE),
            parameter   WB_SEL_WIDTH     = (1 << WB_DAT_SIZE),
            
            parameter   MICROSTEP_WIDTH  = 12,
            parameter   Q_WIDTH          = 24,
            parameter   X_WIDTH          = 24 + Q_WIDTH,
            parameter   X_SHIFT          = Q_WIDTH - 8,
            parameter   V_WIDTH          = Q_WIDTH,
            parameter   A_WIDTH          = Q_WIDTH,
            
            parameter   INIT_CTL_ENABLE  = 1'b0,
            parameter   INIT_CTL_TARGET  = 1'b0,
            parameter   INIT_CTL_PWM     = 2'b11,
            parameter   INIT_TARGET_X    = 0,
            parameter   INIT_TARGET_V    = 0,
            parameter   INIT_TARGET_A    = 0,
            parameter   INIT_MAX_V       = 1000,
            parameter   INIT_MAX_A       = 100,
            parameter   INIT_MAX_A_NEAR  = 120
        )
        (
            input   wire                        reset,
            input   wire                        clk,
            
            input   wire    [WB_ADR_WIDTH-1:0]  s_wb_adr_i,
            input   wire    [WB_DAT_WIDTH-1:0]  s_wb_dat_i,
            output  wire    [WB_DAT_WIDTH-1:0]  s_wb_dat_o,
            input   wire                        s_wb_we_i,
            input   wire    [WB_SEL_WIDTH-1:0]  s_wb_sel_i,
            input   wire                        s_wb_stb_i,
            output  wire                        s_wb_ack_o,
            
            output  wire                        motor_en,
            output  wire                        motor_a,
            output  wire                        motor_b
        );
    
    
    localparam  ADR_CORE_ID     = 8'h00;
    localparam  ADR_CTL_ENABLE  = 8'h01;
    localparam  ADR_CTL_TARGET  = 8'h02;
    localparam  ADR_CTL_PWM     = 8'h03;
    localparam  ADR_TARGET_X    = 8'h04;
    localparam  ADR_TARGET_V    = 8'h06;
    localparam  ADR_TARGET_A    = 8'h07;
    localparam  ADR_MAX_V       = 8'h09;
    localparam  ADR_MAX_A       = 8'h0a;
    localparam  ADR_MAX_A_NEAR  = 8'h0f;
    localparam  ADR_CUR_X       = 8'h10;
    localparam  ADR_CUR_V       = 8'h12;
    localparam  ADR_CUR_A       = 8'h13;
    localparam  ADR_TIME        = 8'h20;
    
    
    wire                                update;
    
    reg             [0:0]               reg_ctl_enable;
    reg             [2:0]               reg_ctl_target;
    reg             [1:0]               reg_ctl_pwm;
    reg     signed  [X_WIDTH-1:0]       reg_target_x;
    reg     signed  [V_WIDTH:0]         reg_target_v;
    reg     signed  [A_WIDTH:0]         reg_target_a;
    reg             [V_WIDTH-1:0]       reg_max_v;
    reg             [A_WIDTH-1:0]       reg_max_a;
    reg             [A_WIDTH-1:0]       reg_max_a_near;
    reg     signed  [X_WIDTH-1:0]       reg_cur_x;
    reg     signed  [V_WIDTH:0]         reg_cur_v;
    reg     signed  [A_WIDTH:0]         reg_cur_a;
    reg             [31:0]              reg_time;
    
    wire    signed  [V_WIDTH:0]         max_v = {1'b0, reg_max_v};
    wire    signed  [A_WIDTH:0]         max_a = {1'b0, reg_max_a};
    wire    signed  [V_WIDTH:0]         min_v = -max_v;
    wire    signed  [A_WIDTH:0]         min_a = -max_a;
    
    reg                                 reg_start;
    reg     signed  [A_WIDTH:0]         reg_a_tmp;
    reg     signed  [A_WIDTH:0]         reg_a;
    reg     signed  [V_WIDTH:0]         reg_v_tmp;
    reg     signed  [V_WIDTH:0]         reg_v;
    
    wire    signed  [A_WIDTH:0]         calc_a;
    wire                                calc_valid;
    
    function [WB_DAT_WIDTH-1:0] reg_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );
    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            reg_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction
    
    always @(posedge clk) begin
        if ( reset ) begin
            reg_ctl_enable  <= INIT_CTL_ENABLE;
            reg_ctl_target  <= INIT_CTL_TARGET;
            reg_ctl_pwm     <= INIT_CTL_PWM;
            reg_target_x    <= INIT_TARGET_X;
            reg_target_v    <= INIT_TARGET_V;
            reg_target_a    <= INIT_TARGET_A;
            reg_max_v       <= INIT_MAX_V;
            reg_max_a       <= INIT_MAX_A;
            reg_max_a_near  <= INIT_MAX_A_NEAR;
            reg_cur_x       <= 0;
            reg_cur_v       <= 0;
            reg_cur_a       <= 0;
            reg_time        <= 0;
            
            reg_start       <= 1'b0;
            reg_a_tmp       <= 0;
            reg_a           <= 0;
            reg_v_tmp       <= 0;
            reg_v           <= 0;
        end
        else begin

            reg_start <= update;
            

            reg_a_tmp <= 0;
            if ( reg_ctl_target[2] ) begin
                reg_a_tmp <= reg_target_a;
            end
            else if ( reg_ctl_target[1] ) begin
                reg_a_tmp <= reg_target_v - reg_cur_v;
            end
            if ( reg_ctl_target[0] ) begin
                reg_a <= calc_a;
            end
            else begin
                reg_a <= reg_a_tmp;
                if ( reg_a_tmp > +max_a ) begin reg_a <= +max_a; end
                if ( reg_a_tmp < -max_a ) begin reg_a <= -max_a; end
            end
            

            reg_v_tmp <= reg_cur_v + reg_a;
            reg_v <= reg_v_tmp;
            if ( reg_v_tmp > +max_v ) begin reg_v <= +max_v; end
            if ( reg_v_tmp < -max_v ) begin reg_v <= -max_v; end
            

            if ( update && reg_ctl_enable ) begin
                reg_cur_x <= reg_cur_x + reg_v;
                reg_cur_v <= reg_v;
                reg_cur_a <= reg_a;
                reg_time  <= reg_time + 1;
            end
            
            

            if ( s_wb_stb_i && s_wb_we_i ) begin
                case ( s_wb_adr_i )
                ADR_CTL_ENABLE:  reg_ctl_enable  <= reg_mask(reg_ctl_enable,  s_wb_dat_i, s_wb_sel_i);
                ADR_CTL_TARGET:  reg_ctl_target  <= reg_mask(reg_ctl_target,  s_wb_dat_i, s_wb_sel_i);
                ADR_CTL_PWM:     reg_ctl_pwm     <= reg_mask(reg_ctl_pwm,     s_wb_dat_i, s_wb_sel_i);
                ADR_TARGET_X:    reg_target_x    <= reg_mask(reg_target_x,    s_wb_dat_i, s_wb_sel_i);
                ADR_TARGET_V:    reg_target_v    <= reg_mask(reg_target_v,    s_wb_dat_i, s_wb_sel_i);
                ADR_TARGET_A:    reg_target_a    <= reg_mask(reg_target_a,    s_wb_dat_i, s_wb_sel_i);
                ADR_MAX_V:       reg_max_v       <= reg_mask(reg_max_v,       s_wb_dat_i, s_wb_sel_i);
                ADR_MAX_A:       reg_max_a       <= reg_mask(reg_max_a,       s_wb_dat_i, s_wb_sel_i);
                ADR_MAX_A_NEAR:  reg_max_a_near  <= reg_mask(reg_max_a_near,  s_wb_dat_i, s_wb_sel_i);
                endcase
            end
        end
    end
    
    assign s_wb_dat_o = (s_wb_adr_i == ADR_CORE_ID)     ? CORE_ID                 :
                        (s_wb_adr_i == ADR_CTL_ENABLE)  ? reg_ctl_enable          :
                        (s_wb_adr_i == ADR_CTL_TARGET)  ? reg_ctl_target          :
                        (s_wb_adr_i == ADR_CTL_PWM)     ? reg_ctl_pwm             :
                        (s_wb_adr_i == ADR_TARGET_X)    ? reg_target_x            :
                        (s_wb_adr_i == ADR_TARGET_V)    ? reg_target_v            :
                        (s_wb_adr_i == ADR_TARGET_A)    ? reg_target_a            :
                        (s_wb_adr_i == ADR_MAX_V)       ? reg_max_v               :
                        (s_wb_adr_i == ADR_MAX_A)       ? reg_max_a               :
                        (s_wb_adr_i == ADR_MAX_A_NEAR)  ? reg_max_a_near          :
                        (s_wb_adr_i == ADR_CUR_X)       ? (reg_cur_x >>> X_SHIFT) :
                        (s_wb_adr_i == ADR_CUR_V)       ? reg_cur_v               :
                        (s_wb_adr_i == ADR_CUR_A)       ? reg_cur_a               :
                        (s_wb_adr_i == ADR_TIME)        ? reg_time                :
                        0;
    assign s_wb_ack_o = s_wb_stb_i;
    
    

    stepper_motor_control_calc
            #(
                .X_WIDTH            (X_WIDTH),
                .V_WIDTH            (V_WIDTH),
                .A_WIDTH            (A_WIDTH)
            )
        i_stepper_motor_control_calc
            (
                .reset              (reset),
                .clk                (clk),
                .cke                (1'b1),
                
                .start              (reg_start),
                
                .target_x           (reg_target_x <<< X_SHIFT),
                .cur_x              (reg_cur_x),
                .cur_v              (reg_cur_v),
                .max_a              (reg_max_a),
                .max_a_near         (reg_max_a_near),
                
                .out_a              (calc_a),
                .out_valid          (calc_valid)
            );
    

    bipolar_stepper_motor_drive
            #(
                .Q_WIDTH            (Q_WIDTH),
                .MICROSTEP_WIDTH    (MICROSTEP_WIDTH)
            )
        i_bipolar_stepper_motor_drive
            (
                .reset              (reset),
                .clk                (clk),
                
                .microstep_en       (reg_ctl_pwm[0]),
                .nanostep_en        (reg_ctl_pwm[1]),
                .asyc_update_en     (1'b0),
                
                .phase              (reg_cur_x[Q_WIDTH+1:0]),
                .update             (update),
                
                .out_a              (motor_a),
                .out_b              (motor_b)
            );
    
    assign motor_en = reg_ctl_enable;
    
endmodule
module stepper_motor_control
        #(
            parameter   CORE_ID          = 32'h5a5a_5a5a,
            
            parameter   WB_ADR_WIDTH     = 6,
            parameter   WB_DAT_SIZE      = 3,
            parameter   WB_DAT_WIDTH     = (8 << WB_DAT_SIZE),
            parameter   WB_SEL_WIDTH     = (1 << WB_DAT_SIZE),
            
            parameter   MICROSTEP_WIDTH  = 12,
            parameter   Q_WIDTH          = 24,
            parameter   X_WIDTH          = 24 + Q_WIDTH,
            parameter   X_SHIFT          = Q_WIDTH - 8,
            parameter   V_WIDTH          = Q_WIDTH,
            parameter   A_WIDTH          = Q_WIDTH,
            
            parameter   INIT_CTL_ENABLE  = 1'b0,
            parameter   INIT_CTL_TARGET  = 1'b0,
            parameter   INIT_CTL_PWM     = 2'b11,
            parameter   INIT_TARGET_X    = 0,
            parameter   INIT_TARGET_V    = 0,
            parameter   INIT_TARGET_A    = 0,
            parameter   INIT_MAX_V       = 1000,
            parameter   INIT_MAX_A       = 100,
            parameter   INIT_MAX_A_NEAR  = 120
        )
        (
            input   wire                        reset,
            input   wire                        clk,
            
            input   wire    [WB_ADR_WIDTH-1:0]  s_wb_adr_i,
            input   wire    [WB_DAT_WIDTH-1:0]  s_wb_dat_i,
            output  wire    [WB_DAT_WIDTH-1:0]  s_wb_dat_o,
            input   wire                        s_wb_we_i,
            input   wire    [WB_SEL_WIDTH-1:0]  s_wb_sel_i,
            input   wire                        s_wb_stb_i,
            output  wire                        s_wb_ack_o,
            
            output  wire                        motor_en,
            output  wire                        motor_a,
            output  wire                        motor_b
        );

    
    
    localparam  ADR_CORE_ID     = 8'h00;
    localparam  ADR_CTL_ENABLE  = 8'h01;
    localparam  ADR_CTL_TARGET  = 8'h02;
    localparam  ADR_CTL_PWM     = 8'h03;
    localparam  ADR_TARGET_X    = 8'h04;
    localparam  ADR_TARGET_V    = 8'h06;
    localparam  ADR_TARGET_A    = 8'h07;
    localparam  ADR_MAX_V       = 8'h09;
    localparam  ADR_MAX_A       = 8'h0a;
    localparam  ADR_MAX_A_NEAR  = 8'h0f;
    localparam  ADR_CUR_X       = 8'h10;
    localparam  ADR_CUR_V       = 8'h12;
    localparam  ADR_CUR_A       = 8'h13;
    localparam  ADR_TIME        = 8'h20;
    
    
    wire                                update;
    
    reg             [0:0]               reg_ctl_enable;
    reg             [2:0]               reg_ctl_target;
    reg             [1:0]               reg_ctl_pwm;
    reg     signed  [X_WIDTH-1:0]       reg_target_x;
    reg     signed  [V_WIDTH:0]         reg_target_v;
    reg     signed  [A_WIDTH:0]         reg_target_a;
    reg             [V_WIDTH-1:0]       reg_max_v;
    reg             [A_WIDTH-1:0]       reg_max_a;
    reg             [A_WIDTH-1:0]       reg_max_a_near;
    reg     signed  [X_WIDTH-1:0]       reg_cur_x;
    reg     signed  [V_WIDTH:0]         reg_cur_v;
    reg     signed  [A_WIDTH:0]         reg_cur_a;
    reg             [31:0]              reg_time;
    
    wire    signed  [V_WIDTH:0]         max_v = {1'b0, reg_max_v};
    wire    signed  [A_WIDTH:0]         max_a = {1'b0, reg_max_a};
    wire    signed  [V_WIDTH:0]         min_v = -max_v;
    wire    signed  [A_WIDTH:0]         min_a = -max_a;
    
    reg                                 reg_start;
    reg     signed  [A_WIDTH:0]         reg_a_tmp;
    reg     signed  [A_WIDTH:0]         reg_a;
    reg     signed  [V_WIDTH:0]         reg_v_tmp;
    reg     signed  [V_WIDTH:0]         reg_v;
    
    wire    signed  [A_WIDTH:0]         calc_a;
    wire                                calc_valid;
    
    function [WB_DAT_WIDTH-1:0] reg_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );
    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            reg_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction
    
    always @(posedge clk) begin
        if ( reset ) begin
            reg_ctl_enable  <= INIT_CTL_ENABLE;
            reg_ctl_target  <= INIT_CTL_TARGET;
            reg_ctl_pwm     <= INIT_CTL_PWM;
            reg_target_x    <= INIT_TARGET_X;
            reg_target_v    <= INIT_TARGET_V;
            reg_target_a    <= INIT_TARGET_A;
            reg_max_v       <= INIT_MAX_V;
            reg_max_a       <= INIT_MAX_A;
            reg_max_a_near  <= INIT_MAX_A_NEAR;
            reg_cur_x       <= 0;
            reg_cur_v       <= 0;
            reg_cur_a       <= 0;
            reg_time        <= 0;
            
            reg_start       <= 1'b0;
            reg_a_tmp       <= 0;
            reg_a           <= 0;
            reg_v_tmp       <= 0;
            reg_v           <= 0;
        end
        else begin

            reg_start <= update;
            

            reg_a_tmp <= 0;
            if ( reg_ctl_target[2] ) begin
                reg_a_tmp <= reg_target_a;
            end
            else if ( reg_ctl_target[1] ) begin
                reg_a_tmp <= reg_target_v - reg_cur_v;
            end
            if ( reg_ctl_target[0] ) begin
                reg_a <= calc_a;
            end
            else begin
                reg_a <= reg_a_tmp;
                if ( reg_a_tmp > +max_a ) begin reg_a <= +max_a; end
                if ( reg_a_tmp < -max_a ) begin reg_a <= -max_a; end
            end
            

            reg_v_tmp <= reg_cur_v + reg_a;
            reg_v <= reg_v_tmp;
            if ( reg_v_tmp > +max_v ) begin reg_v <= +max_v; end
            if ( reg_v_tmp < -max_v ) begin reg_v <= -max_v; end
            

            if ( update && reg_ctl_enable ) begin
                reg_cur_x <= reg_cur_x + reg_v;
                reg_cur_v <= reg_v;
                reg_cur_a <= reg_a;
                reg_time  <= reg_time + 1;
            end
            
            

            if ( s_wb_stb_i && s_wb_we_i ) begin
                case ( s_wb_adr_i )
                ADR_CTL_ENABLE:  reg_ctl_enable  <= reg_mask(reg_ctl_enable,  s_wb_dat_i, s_wb_sel_i);
                ADR_CTL_TARGET:  reg_ctl_target  <= reg_mask(reg_ctl_target,  s_wb_dat_i, s_wb_sel_i);
                ADR_CTL_PWM:     reg_ctl_pwm     <= reg_mask(reg_ctl_pwm,     s_wb_dat_i, s_wb_sel_i);
                ADR_TARGET_X:    reg_target_x    <= reg_mask(reg_target_x,    s_wb_dat_i, s_wb_sel_i);
                ADR_TARGET_V:    reg_target_v    <= reg_mask(reg_target_v,    s_wb_dat_i, s_wb_sel_i);
                ADR_TARGET_A:    reg_target_a    <= reg_mask(reg_target_a,    s_wb_dat_i, s_wb_sel_i);
                ADR_MAX_V:       reg_max_v       <= reg_mask(reg_max_v,       s_wb_dat_i, s_wb_sel_i);
                ADR_MAX_A:       reg_max_a       <= reg_mask(reg_max_a,       s_wb_dat_i, s_wb_sel_i);
                ADR_MAX_A_NEAR:  reg_max_a_near  <= reg_mask(reg_max_a_near,  s_wb_dat_i, s_wb_sel_i);
                endcase
            end
        end
    end
    
    assign s_wb_dat_o = (s_wb_adr_i == ADR_CORE_ID)     ? CORE_ID                 :
                        (s_wb_adr_i == ADR_CTL_ENABLE)  ? reg_ctl_enable          :
                        (s_wb_adr_i == ADR_CTL_TARGET)  ? reg_ctl_target          :
                        (s_wb_adr_i == ADR_CTL_PWM)     ? reg_ctl_pwm             :
                        (s_wb_adr_i == ADR_TARGET_X)    ? reg_target_x            :
                        (s_wb_adr_i == ADR_TARGET_V)    ? reg_target_v            :
                        (s_wb_adr_i == ADR_TARGET_A)    ? reg_target_a            :
                        (s_wb_adr_i == ADR_MAX_V)       ? reg_max_v               :
                        (s_wb_adr_i == ADR_MAX_A)       ? reg_max_a               :
                        (s_wb_adr_i == ADR_MAX_A_NEAR)  ? reg_max_a_near          :
                        (s_wb_adr_i == ADR_CUR_X)       ? (reg_cur_x >>> X_SHIFT) :
                        (s_wb_adr_i == ADR_CUR_V)       ? reg_cur_v               :
                        (s_wb_adr_i == ADR_CUR_A)       ? reg_cur_a               :
                        (s_wb_adr_i == ADR_TIME)        ? reg_time                :
                        0;
    assign s_wb_ack_o = s_wb_stb_i;
    
    

    stepper_motor_control_calc
            #(
                .X_WIDTH            (X_WIDTH),
                .V_WIDTH            (V_WIDTH),
                .A_WIDTH            (A_WIDTH)
            )
        i_stepper_motor_control_calc
            (
                .reset              (reset),
                .clk                (clk),
                .cke                (1'b1),
                
                .start              (reg_start),
                
                .target_x           (reg_target_x <<< X_SHIFT),
                .cur_x              (reg_cur_x),
                .cur_v              (reg_cur_v),
                .max_a              (reg_max_a),
                .max_a_near         (reg_max_a_near),
                
                .out_a              (calc_a),
                .out_valid          (calc_valid)
            );
    

    bipolar_stepper_motor_drive
            #(
                .Q_WIDTH            (Q_WIDTH),
                .MICROSTEP_WIDTH    (MICROSTEP_WIDTH)
            )
        i_bipolar_stepper_motor_drive
            (
                .reset              (reset),
                .clk                (clk),
                
                .microstep_en       (reg_ctl_pwm[0]),
                .nanostep_en        (reg_ctl_pwm[1]),
                .asyc_update_en     (1'b0),
                
                .phase              (reg_cur_x[Q_WIDTH+1:0]),
                .update             (update),
                
                .out_a              (motor_a),
                .out_b              (motor_b)
            );
    
    assign motor_en = reg_ctl_enable;
    
endmodule