data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v
 line:42: before: "("
1: b'%Error: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:1: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/110151336/alt_boards/a_c4e6e10,data/full_repos/permissive/110151336/config.vh\n             data/full_repos/permissive/110151336/alt_boards/a_c4e6e10,data/full_repos/permissive/110151336/config.vh.v\n             data/full_repos/permissive/110151336/alt_boards/a_c4e6e10,data/full_repos/permissive/110151336/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n            # 10 clk = ! clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:40: syntax error, unexpected \'@\'\n        repeat (2) @ (posedge clk);\n                   ^\n%Error: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:42: syntax error, unexpected \'@\'\n        repeat (2) @ (posedge clk);\n                   ^\n%Error: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:49: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #0\n        ^\n%Error: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:51: syntax error, unexpected \'@\'\n        @ (posedge rst_n);\n        ^\n%Error: data/full_repos/permissive/110151336/alt_boards/a_c4e6e10/testbench.v:55: syntax error, unexpected \'@\'\n            @ (posedge clk);\n            ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n'
module testbench;

    reg         clk;
    reg  [ 3:0] key;
    reg  [ 7:0] sw;
    wire [11:0] led;
    wire [ 7:0] abcdefgh;
    wire [ 7:0] digit;
    wire        buzzer;

    top i_top
    (
        .clk      ( clk      ),
        .key      ( key      ),
        .sw       ( sw       ),
        .led      ( led      ),
        .abcdefgh ( abcdefgh ),
        .digit    ( digit    ),
        .buzzer   ( buzzer   )
    );


    initial
    begin
        clk = 0;

        forever
            # 10 clk = ! clk;
    end

    reg rst_n;
    
    always @*
        key [3] = rst_n;

    initial
    begin
        repeat (2) @ (posedge clk);
        rst_n <= 0;
        repeat (2) @ (posedge clk);
        rst_n <= 1;
    end

    initial
    begin
        #0
        $dumpvars;

        @ (posedge rst_n);

        repeat (10000)
        begin
            @ (posedge clk);

            key <= $random;
            sw  <= $random;
        end

        $stop;
    end

endmodule
module testbench;


    reg         clk;
    reg  [ 3:0] key;
    reg  [ 7:0] sw;
    wire [11:0] led;
    wire [ 7:0] abcdefgh;
    wire [ 7:0] digit;
    wire        buzzer;

    top i_top
    (
        .clk      ( clk      ),
        .key      ( key      ),
        .sw       ( sw       ),
        .led      ( led      ),
        .abcdefgh ( abcdefgh ),
        .digit    ( digit    ),
        .buzzer   ( buzzer   )
    );


    initial
    begin
        clk = 0;

        forever
            # 10 clk = ! clk;
    end

    reg rst_n;
    
    always @*
        key [3] = rst_n;

    initial
    begin
        repeat (2) @ (posedge clk);
        rst_n <= 0;
        repeat (2) @ (posedge clk);
        rst_n <= 1;
    end

    initial
    begin
        #0
        $dumpvars;

        @ (posedge rst_n);

        repeat (10000)
        begin
            @ (posedge clk);

            key <= $random;
            sw  <= $random;
        end

        $stop;
    end

endmodule