data/full_repos/permissive/143278/ivltests/udp_sched.v
 line:11: before: "primitive"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/udp_sched.v:39: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/udp_sched.v:48: syntax error, unexpected \'@\'\n @(dclk)\n ^\n%Error: data/full_repos/permissive/143278/ivltests/udp_sched.v:55: syntax error, unexpected $display\n $display("q4=%b", q4);\n ^~~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

reg rclk, dclk;
wire clk = rclk;
wire q0,q1,q2,q3,q4;

u_dff ff0(q0, 1'b1, clk),
      ff1(q1, 1'b1, q0),
      ff2(q2, 1'b1, q1),
      ff3(q3, 1'b1, q2),
      ff4(q4, 1'b1, q3);

initial
begin
	#1


	rclk = 1;




	dclk <= 1;
	@(dclk)

	if (q4 !== 1'b1) begin
	   $display("FAILED -- q4 did not propagate in time (q4=%b)", q4);
	   $finish;
	end

	$display("q4=%b", q4);
        $display("PASSED");
end

endmodule
module top;


reg rclk, dclk;
wire clk = rclk;
wire q0,q1,q2,q3,q4;

u_dff ff0(q0, 1'b1, clk),
      ff1(q1, 1'b1, q0),
      ff2(q2, 1'b1, q1),
      ff3(q3, 1'b1, q2),
      ff4(q4, 1'b1, q3);

initial
begin
	#1


	rclk = 1;




	dclk <= 1;
	@(dclk)

	if (q4 !== 1'b1) begin
	   $display("FAILED -- q4 did not propagate in time (q4=%b)", q4);
	   $finish;
	end

	$display("q4=%b", q4);
        $display("PASSED");
end

endmodule