data/full_repos/permissive/181738725/wavetrace/verilog/lib/shift/shift_ram.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/shift/shift_ram.v:32: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/shift,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/shift,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/shift,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module shift_ram #(
  parameter Width = 8,
  parameter Depth = 32)
(
  input              clk,
  input              rst,
  input [Width-1:0]  din_data,
  input              en,
  output [Width-1:0] dout_data
);

`include "util.vh"

  reg  [clog2(Depth)-1:0] wr_addr;
  wire [clog2(Depth)-1:0] wr_addr_next, rd_addr;

  assign wr_addr_next = (wr_addr == Depth-1) ? 0 : wr_addr + 1;

  always @(posedge clk) begin
    if (en) begin
      wr_addr <= wr_addr_next;
    end
    if (rst) begin
      wr_addr <= 0;
    end
  end

  assign rd_addr = (en) ? wr_addr_next : wr_addr;

  ram_1c_1r_1w #(
    .Width (Width),
    .Depth (Depth))
  ram (
    .clk     (clk),
    .wr_en   (en),
    .wr_addr (wr_addr),
    .wr_data (din_data),
    .rd_addr (rd_addr),
    .rd_data (dout_data));

endmodule
module shift_ram #(
  parameter Width = 8,
  parameter Depth = 32)
(
  input              clk,
  input              rst,
  input [Width-1:0]  din_data,
  input              en,
  output [Width-1:0] dout_data
);


`include "util.vh"

  reg  [clog2(Depth)-1:0] wr_addr;
  wire [clog2(Depth)-1:0] wr_addr_next, rd_addr;

  assign wr_addr_next = (wr_addr == Depth-1) ? 0 : wr_addr + 1;

  always @(posedge clk) begin
    if (en) begin
      wr_addr <= wr_addr_next;
    end
    if (rst) begin
      wr_addr <= 0;
    end
  end

  assign rd_addr = (en) ? wr_addr_next : wr_addr;

  ram_1c_1r_1w #(
    .Width (Width),
    .Depth (Depth))
  ram (
    .clk     (clk),
    .wr_en   (en),
    .wr_addr (wr_addr),
    .wr_data (din_data),
    .rd_addr (rd_addr),
    .rd_data (dout_data));

endmodule