data/full_repos/permissive/143597583/rtl/verilog/sym_map.v
data/verilator_xmls/70c3d359-1578-4ee8-8163-e6d54cb23609.xml
module sym_map (
  input wire clk,
  input wire rst,

  input wire [7:0] x_i,
  input wire x_valid_i,
  output wire x_ready_o,

  output wire [15:0] y_a_o,
  output wire [15:0] y_b_o,
  output wire y_valid_o,
  input wire y_ready_i
);
	parameter S_READY    = 1 << 0,
	          S_SYM_0    = 1 << 1,
	          S_SYM_1    = 1 << 1,
	          S_SYM_2    = 1 << 1,
	          S_SYM_3    = 1 << 1;

	reg [7:0] curr_state, next_state;

	always @(posedge clk) begin
		if (rst) begin
			curr_state <= S_READY;
		end
		else begin
			curr_state <= next_state;
		end
	end

	always @(*) begin
		next_state = curr_state;
		case (curr_state)
			S_READY: begin
				if (x_valid_i) begin
					next_state = S_SYM_0;
				end
			end
			S_SYM_0: begin
				if (y_ready_i) begin
					next_state = S_SYM_1;
				end
			end
			S_SYM_1: begin
				if (y_ready_i) begin
					next_state = S_SYM_2;
				end
			end
			S_SYM_2: begin
				if (y_ready_i) begin
					next_state = S_SYM_3;
				end
			end
			S_SYM_3: begin
				if (y_ready_i) begin
					next_state = S_READY;
				end
			end
		endcase
	end

	reg [1:0] sym_bits;
	always @(*) begin
		case (curr_state)
			default: sym_bits = octet[1:0];
			S_SYM_1: sym_bits = octet[3:2];
			S_SYM_2: sym_bits = octet[5:4];
			S_SYM_3: sym_bits = octet[7:6];
		endcase
	end

	wire [15:0] sym_I;
	wire [15:0] sym_Q;


	wire [15:0] pos_one;
	wire [15:0] neg_one;
	assign pos_one = 16'b0_01_0000_0000_0000_0;
	assign neg_one = 16'b1_11_0000_0000_0000_0;

	assign sym_I = sym_bits[0] ? pos_one : neg_one;
	assign sym_Q = sym_bits[1] ? pos_one : neg_one;

	assign x_ready_o = (curr_state == S_READY);
	reg [7:0] octet;
	always @(posedge clk) begin
		if (rst) begin
			octet <= 0;
		end
		else if (curr_state == S_READY && x_valid_i) begin
			octet <= x_i;
		end
	end

endmodule
module sym_map (
  input wire clk,
  input wire rst,

  input wire [7:0] x_i,
  input wire x_valid_i,
  output wire x_ready_o,

  output wire [15:0] y_a_o,
  output wire [15:0] y_b_o,
  output wire y_valid_o,
  input wire y_ready_i
);

	parameter S_READY    = 1 << 0,
	          S_SYM_0    = 1 << 1,
	          S_SYM_1    = 1 << 1,
	          S_SYM_2    = 1 << 1,
	          S_SYM_3    = 1 << 1;

	reg [7:0] curr_state, next_state;

	always @(posedge clk) begin
		if (rst) begin
			curr_state <= S_READY;
		end
		else begin
			curr_state <= next_state;
		end
	end

	always @(*) begin
		next_state = curr_state;
		case (curr_state)
			S_READY: begin
				if (x_valid_i) begin
					next_state = S_SYM_0;
				end
			end
			S_SYM_0: begin
				if (y_ready_i) begin
					next_state = S_SYM_1;
				end
			end
			S_SYM_1: begin
				if (y_ready_i) begin
					next_state = S_SYM_2;
				end
			end
			S_SYM_2: begin
				if (y_ready_i) begin
					next_state = S_SYM_3;
				end
			end
			S_SYM_3: begin
				if (y_ready_i) begin
					next_state = S_READY;
				end
			end
		endcase
	end

	reg [1:0] sym_bits;
	always @(*) begin
		case (curr_state)
			default: sym_bits = octet[1:0];
			S_SYM_1: sym_bits = octet[3:2];
			S_SYM_2: sym_bits = octet[5:4];
			S_SYM_3: sym_bits = octet[7:6];
		endcase
	end

	wire [15:0] sym_I;
	wire [15:0] sym_Q;


	wire [15:0] pos_one;
	wire [15:0] neg_one;
	assign pos_one = 16'b0_01_0000_0000_0000_0;
	assign neg_one = 16'b1_11_0000_0000_0000_0;

	assign sym_I = sym_bits[0] ? pos_one : neg_one;
	assign sym_Q = sym_bits[1] ? pos_one : neg_one;

	assign x_ready_o = (curr_state == S_READY);
	reg [7:0] octet;
	always @(posedge clk) begin
		if (rst) begin
			octet <= 0;
		end
		else if (curr_state == S_READY && x_valid_i) begin
			octet <= x_i;
		end
	end

endmodule