data/full_repos/permissive/172908596/Load and store Instruction/load.v
1: b'%Error: Cannot find file containing module: and\n        ... Looked in:\n             data/full_repos/permissive/172908596/Load/and\n             data/full_repos/permissive/172908596/Load/and.v\n             data/full_repos/permissive/172908596/Load/and.sv\n             and\n             and.v\n             and.sv\n             obj_dir/and\n             obj_dir/and.v\n             obj_dir/and.sv\n%Error: Cannot find file containing module: store\n%Error: Cannot find file containing module: Instruction,data/full_repos/permissive/172908596\n%Error: Cannot find file containing module: data/full_repos/permissive/172908596/Load\n%Error: Cannot find file containing module: Instruction/load.v\n%Error: Exiting due to 5 error(s)\n'
module load(r1,r2,offset,clk,a,rd,readdata);
input [4:0] r1;
input [4:0] r2;
input clk;
input [11:0] offset;
reg [63:0] regFile[0:31];
output wire [63:0] a;
output wire [63:0] rd;
output reg [63:0] readdata;
wire cout, zero, overflow;
integer i;
reg [63:0] x;
reg [63:0] MEMO[0:10000];

initial
begin
	for(i=0;i<32;i=i+1)
	begin
		regFile[i] <= i;
	end
end
initial
	begin
 
	for (i = 0; i < 80; i = i + 1)
	begin
	    MEMO[i] <= i;
	end
end

	always@(*)
	begin
		x[11:0]= offset[11:0];
		x[63:12]={52{offset[11]}};
	end

	
	assign a=regFile[r1];
	ALU m1(a,x,4'b0000,2'b10,rd,cout,zero,overflow);
	always@(posedge clk)
	begin	
	
	regFile[r2] = MEMO[rd];
	readdata = regFile[r2];
	end
	 

endmodule
module load(r1,r2,offset,clk,a,rd,readdata);

input [4:0] r1;
input [4:0] r2;
input clk;
input [11:0] offset;
reg [63:0] regFile[0:31];
output wire [63:0] a;
output wire [63:0] rd;
output reg [63:0] readdata;
wire cout, zero, overflow;
integer i;
reg [63:0] x;
reg [63:0] MEMO[0:10000];

initial
begin
	for(i=0;i<32;i=i+1)
	begin
		regFile[i] <= i;
	end
end
initial
	begin
 
	for (i = 0; i < 80; i = i + 1)
	begin
	    MEMO[i] <= i;
	end
end

	always@(*)
	begin
		x[11:0]= offset[11:0];
		x[63:12]={52{offset[11]}};
	end

	
	assign a=regFile[r1];
	ALU m1(a,x,4'b0000,2'b10,rd,cout,zero,overflow);
	always@(posedge clk)
	begin	
	
	regFile[r2] = MEMO[rd];
	readdata = regFile[r2];
	end
	 

endmodule