data/full_repos/permissive/115403704/src/PC.v
data/verilator_xmls/d9287cda-43d4-4343-a81b-95f74e60833d.xml
module PCUnit(in,PC,clk,sig);
    output reg [31:0] PC;
    input [31:0] in;
    input clk;
    input sig;

    initial
    begin
        PC = 32'h0000_3000;
        $display("PC: %h",PC);
    end
    always@(negedge clk)
	begin
		if (sig)
            begin
                PC = in;
                $display("PC: %h",PC);
            end
	end

endmodule
module PCUnit(in,PC,clk,sig);

    output reg [31:0] PC;
    input [31:0] in;
    input clk;
    input sig;

    initial
    begin
        PC = 32'h0000_3000;
        $display("PC: %h",PC);
    end
    always@(negedge clk)
	begin
		if (sig)
            begin
                PC = in;
                $display("PC: %h",PC);
            end
	end

endmodule