data/full_repos/permissive/196851857/datapath/dm.v
None: at end of input
1: b'%Error: data/full_repos/permissive/196851857/datapath/dm.v:1: Cannot find include file: ..\\\\control\\\\ctrl_signals_def.v\n`include "..\\\\control\\\\ctrl_signals_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/196851857/datapath,data/full_repos/permissive/196851857/..\\\\control\\\\ctrl_signals_def.v\n             data/full_repos/permissive/196851857/datapath,data/full_repos/permissive/196851857/..\\\\control\\\\ctrl_signals_def.v.v\n             data/full_repos/permissive/196851857/datapath,data/full_repos/permissive/196851857/..\\\\control\\\\ctrl_signals_def.v.sv\n             ..\\\\control\\\\ctrl_signals_def.v\n             ..\\\\control\\\\ctrl_signals_def.v.v\n             ..\\\\control\\\\ctrl_signals_def.v.sv\n             obj_dir/..\\\\control\\\\ctrl_signals_def.v\n             obj_dir/..\\\\control\\\\ctrl_signals_def.v.v\n             obj_dir/..\\\\control\\\\ctrl_signals_def.v.sv\n%Error: data/full_repos/permissive/196851857/datapath/dm.v:17: syntax error, unexpected byte, expecting IDENTIFIER or do or final\n  wire [7:0] byte, be_to_wr_byte;\n             ^~~~\n%Error: data/full_repos/permissive/196851857/datapath/dm.v:35: syntax error, unexpected \')\', expecting "\'{"\n    .out(byte)\n             ^\n%Error: data/full_repos/permissive/196851857/datapath/dm.v:39: syntax error, unexpected \')\', expecting "\'{"\n    .in(byte),\n            ^\n%Error: data/full_repos/permissive/196851857/datapath/dm.v:56: Define or directive not defined: \'`MemByByte\'\n      if (MemOpType == `MemByByte)\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/196851857/datapath/dm.v:56: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (MemOpType == `MemByByte)\n                                 ^\n%Error: Cannot continue\n'
module dm_4k(
  addr, d_in,
  wr_en, d_out,
  MemOpType, MemDataExtType, 
  ByteOff,
  clk
);
  input [11:2] addr;
  input MemOpType, MemDataExtType;
  input [1:0] ByteOff;
  input [31:0] d_in;
  input wr_en;
  input clk;
  output [31:0]d_out;
  reg [31:0] dm[1023:0];
  wire [7:0] byte, be_to_wr_byte;
  wire [31:0] word_buffer, byte_ext_word;
  integer i;
  initial
  begin
    for(i = 0;i < 1024;i = i + 1)
    dm[i] = 32'b0;
  end
  assign word_buffer = dm[addr[11:2]];



  mux4 #(.WIDTH(8)) byte_mux(
    .i00(word_buffer[7:0]),
    .i01(word_buffer[15:8]),
    .i10(word_buffer[23:16]),
    .i11(word_buffer[31:24]),
    .sel(ByteOff),
    .out(byte)
  );
  
  ext #(.WIDTH(8), .BIGWIDTH(32)) ext_byte_ext_word(
    .in(byte),
    .ExtType(MemDataExtType),
    .out(byte_ext_word)
  );
  
  mux sel_memOpType(
    .i0(byte_ext_word),
    .i1(word_buffer),
    .sel(MemOpType),
    .out(d_out)
  );
  
  assign be_to_wr_byte = d_in[7:0];
  
  always@(posedge clk)
  begin
    if (wr_en)
      if (MemOpType == `MemByByte)
      begin

        case (ByteOff)
         2'b00: dm[addr[11:2]][7:0] <= be_to_wr_byte;
         2'b01: dm[addr[11:2]][15:8] <= be_to_wr_byte;
         2'b10: dm[addr[11:2]][23:16] <= be_to_wr_byte;
         2'b11: dm[addr[11:2]][31:24] <= be_to_wr_byte;
        endcase
      end else 
      begin
        dm[addr[11:2]][31:0] <= d_in;
      end
  end
endmodule
module dm_4k(
  addr, d_in,
  wr_en, d_out,
  MemOpType, MemDataExtType, 
  ByteOff,
  clk
);

  input [11:2] addr;
  input MemOpType, MemDataExtType;
  input [1:0] ByteOff;
  input [31:0] d_in;
  input wr_en;
  input clk;
  output [31:0]d_out;
  reg [31:0] dm[1023:0];
  wire [7:0] byte, be_to_wr_byte;
  wire [31:0] word_buffer, byte_ext_word;
  integer i;
  initial
  begin
    for(i = 0;i < 1024;i = i + 1)
    dm[i] = 32'b0;
  end
  assign word_buffer = dm[addr[11:2]];



  mux4 #(.WIDTH(8)) byte_mux(
    .i00(word_buffer[7:0]),
    .i01(word_buffer[15:8]),
    .i10(word_buffer[23:16]),
    .i11(word_buffer[31:24]),
    .sel(ByteOff),
    .out(byte)
  );
  
  ext #(.WIDTH(8), .BIGWIDTH(32)) ext_byte_ext_word(
    .in(byte),
    .ExtType(MemDataExtType),
    .out(byte_ext_word)
  );
  
  mux sel_memOpType(
    .i0(byte_ext_word),
    .i1(word_buffer),
    .sel(MemOpType),
    .out(d_out)
  );
  
  assign be_to_wr_byte = d_in[7:0];
  
  always@(posedge clk)
  begin
    if (wr_en)
      if (MemOpType == `MemByByte)
      begin

        case (ByteOff)
         2'b00: dm[addr[11:2]][7:0] <= be_to_wr_byte;
         2'b01: dm[addr[11:2]][15:8] <= be_to_wr_byte;
         2'b10: dm[addr[11:2]][23:16] <= be_to_wr_byte;
         2'b11: dm[addr[11:2]][31:24] <= be_to_wr_byte;
        endcase
      end else 
      begin
        dm[addr[11:2]][31:0] <= d_in;
      end
  end
endmodule