data/full_repos/permissive/206301883/DVS_MODEL.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/206301883/DVS_MODEL.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DVS_MODEL(
input clk,
input ACK,
output REQ,
output [9:0]AER
    );
    
reg req = 1'b1;
reg [9:0]aer1 = 10'b0000000000;

assign REQ = req;
assign AER = aer1; 


always @(posedge clk)
begin
    if (ACK == 1'b1) begin
        req = 1'b0;
        #30;
        aer1 = 10'b1111111111;
    end
    else begin
       req <= 1'b1;
       aer1 = 10'b0000000000;
    end
        
end
endmodule
module DVS_MODEL(
input clk,
input ACK,
output REQ,
output [9:0]AER
    );

    
reg req = 1'b1;
reg [9:0]aer1 = 10'b0000000000;

assign REQ = req;
assign AER = aer1; 


always @(posedge clk)
begin
    if (ACK == 1'b1) begin
        req = 1'b0;
        #30;
        aer1 = 10'b1111111111;
    end
    else begin
       req <= 1'b1;
       aer1 = 10'b0000000000;
    end
        
end
endmodule