data/full_repos/permissive/159001439/src/rgmii_if.v
1: b"%Error: data/full_repos/permissive/159001439/src/rgmii_if.v:44: Cannot find file containing module: 'rgmii_rx'\nrgmii_rx #(.MODE(RX_MODE)) rx_i(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159001439/src,data/full_repos/permissive/159001439/rgmii_rx\n             data/full_repos/permissive/159001439/src,data/full_repos/permissive/159001439/rgmii_rx.v\n             data/full_repos/permissive/159001439/src,data/full_repos/permissive/159001439/rgmii_rx.sv\n             rgmii_rx\n             rgmii_rx.v\n             rgmii_rx.sv\n             obj_dir/rgmii_rx\n             obj_dir/rgmii_rx.v\n             obj_dir/rgmii_rx.sv\n%Error: data/full_repos/permissive/159001439/src/rgmii_if.v:61: Cannot find file containing module: 'rgmii_tx'\nrgmii_tx #(.MODE(TX_MODE)) tx_i(\n^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module rgmii_if(
	input reset,
	input speed,





	output ibs_up,
	output [1:0] ibs_spd,
	output ibs_dplx,
    output interrupt,


	input rgmii_rxclk,
	input [3:0] rgmii_rxdat,
	input rgmii_rxctl,
	output rgmii_gtxclk,
	output [3:0] rgmii_txdat,
	output rgmii_txctl,


	input txclk_x2,
	input txclk,
	input [7:0] txd,
	input txen,
	input txer,
	output rxclk_x2,
	output rxclk,
	output [7:0] rxd,
	output rxdv,
	output rxer,
	output crs,
	output col
);





parameter RX_MODE = "DELAYED";
parameter TX_MODE = "DELAYED";

rgmii_rx #(.MODE(RX_MODE)) rx_i(
	.reset(reset),
	.speed(speed),
	.ibs_up(ibs_up),
	.ibs_spd(ibs_spd),
	.ibs_dplx(ibs_dplx),
	.rgmii_rxclk(rgmii_rxclk),
	.rgmii_rxdat(rgmii_rxdat),
	.rgmii_rxctl(rgmii_rxctl),
	.rxclk_x2(rxclk_x2),
	.rxclk(rxclk),
	.rxd(rxd),
	.rxdv(rxdv),
	.rxer(rxer),
	.crs(crs)
);

rgmii_tx #(.MODE(TX_MODE)) tx_i(
	.reset(reset),
	.speed(speed),
	.txclk_x2(txclk_x2),
	.txclk(txclk),
	.txd(txd),
	.txen(txen),
	.txer(txer),
	.rgmii_gtxclk(rgmii_gtxclk),
	.rgmii_txdat(rgmii_txdat),
	.rgmii_txctl(rgmii_txctl)
);


assign col = txen && (crs || rxdv);


wire [3:0] ibs_new = {ibs_dplx, ibs_spd, ibs_up};
reg [3:0] ibs_prev;
always @(posedge rxclk)
begin
    ibs_prev <= ibs_new;
end
assign interrupt = ibs_new != ibs_prev;

endmodule
module rgmii_if(
	input reset,
	input speed,





	output ibs_up,
	output [1:0] ibs_spd,
	output ibs_dplx,
    output interrupt,


	input rgmii_rxclk,
	input [3:0] rgmii_rxdat,
	input rgmii_rxctl,
	output rgmii_gtxclk,
	output [3:0] rgmii_txdat,
	output rgmii_txctl,


	input txclk_x2,
	input txclk,
	input [7:0] txd,
	input txen,
	input txer,
	output rxclk_x2,
	output rxclk,
	output [7:0] rxd,
	output rxdv,
	output rxer,
	output crs,
	output col
);






parameter RX_MODE = "DELAYED";
parameter TX_MODE = "DELAYED";

rgmii_rx #(.MODE(RX_MODE)) rx_i(
	.reset(reset),
	.speed(speed),
	.ibs_up(ibs_up),
	.ibs_spd(ibs_spd),
	.ibs_dplx(ibs_dplx),
	.rgmii_rxclk(rgmii_rxclk),
	.rgmii_rxdat(rgmii_rxdat),
	.rgmii_rxctl(rgmii_rxctl),
	.rxclk_x2(rxclk_x2),
	.rxclk(rxclk),
	.rxd(rxd),
	.rxdv(rxdv),
	.rxer(rxer),
	.crs(crs)
);

rgmii_tx #(.MODE(TX_MODE)) tx_i(
	.reset(reset),
	.speed(speed),
	.txclk_x2(txclk_x2),
	.txclk(txclk),
	.txd(txd),
	.txen(txen),
	.txer(txer),
	.rgmii_gtxclk(rgmii_gtxclk),
	.rgmii_txdat(rgmii_txdat),
	.rgmii_txctl(rgmii_txctl)
);


assign col = txen && (crs || rxdv);


wire [3:0] ibs_new = {ibs_dplx, ibs_spd, ibs_up};
reg [3:0] ibs_prev;
always @(posedge rxclk)
begin
    ibs_prev <= ibs_new;
end
assign interrupt = ibs_new != ibs_prev;

endmodule