data/full_repos/permissive/211866113/RAM.v
data/verilator_xmls/6e3c4e20-70b1-4f44-9f3f-ed06faab2d51.xml
module RAM_module (ADDRESS, DATA, OUT, CS, WE, OE);


    parameter Address_size = 2;
    parameter Word_size = 3;

    input [Address_size-1:0] ADDRESS;
    input [Word_size-1:0]    DATA;
    output [Word_size-1:0]   OUT;

    input 		     CS, WE, OE;



    reg [Word_size-1:0]      Mem [0:(1<<Address_size)-1];


    reg [Address_size-1:0]   addr_reg;


    assign OUT = (CS && OE) ?  Mem[addr_reg] : {Word_size{1'bz}};

    always @(CS) begin
	if (WE) begin
            Mem[ADDRESS] = DATA;
            $display("%b, address: %b", Mem[ADDRESS], ADDRESS);
	end
	addr_reg = ADDRESS;
    end

    always @(WE or OE)
      if (WE && OE) $display("Notice: OE and WE both HIGH");

endmodule
module RAM_module (ADDRESS, DATA, OUT, CS, WE, OE);



    parameter Address_size = 2;
    parameter Word_size = 3;

    input [Address_size-1:0] ADDRESS;
    input [Word_size-1:0]    DATA;
    output [Word_size-1:0]   OUT;

    input 		     CS, WE, OE;



    reg [Word_size-1:0]      Mem [0:(1<<Address_size)-1];


    reg [Address_size-1:0]   addr_reg;


    assign OUT = (CS && OE) ?  Mem[addr_reg] : {Word_size{1'bz}};

    always @(CS) begin
	if (WE) begin
            Mem[ADDRESS] = DATA;
            $display("%b, address: %b", Mem[ADDRESS], ADDRESS);
	end
	addr_reg = ADDRESS;
    end

    always @(WE or OE)
      if (WE && OE) $display("Notice: OE and WE both HIGH");

endmodule