data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v
1: b'%Error: data/full_repos/permissive/129155059/proyecto-01/p2s_s2p/p2s_s2p_synth.v:1: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.v\n             data/full_repos/permissive/129155059/proyecto-01/p2s_s2p,data/full_repos/permissive/129155059/cmos_cells.v.sv\n             cmos_cells.v\n             cmos_cells.v.v\n             cmos_cells.v.sv\n             obj_dir/cmos_cells.v\n             obj_dir/cmos_cells.v.v\n             obj_dir/cmos_cells.v.sv\n%Error: Exiting due to 1 error(s)\n'
module mux_ctr_synth(valid_count, CLK, reset, CTR);
  wire [2:0] _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  input CLK;
  output [2:0] CTR;
  reg [2:0] CTR;
  input reset;
  input valid_count;
  NAND _15_ (
    .A(valid_count),
    .B(CTR[0]),
    .Y(_14_)
  );
  NOT _16_ (
    .A(CTR[0]),
    .Y(_01_)
  );
  NOT _17_ (
    .A(valid_count),
    .Y(_02_)
  );
  NAND _18_ (
    .A(_02_),
    .B(_01_),
    .Y(_03_)
  );
  NAND _19_ (
    .A(_03_),
    .B(_14_),
    .Y(_04_)
  );
  NAND _20_ (
    .A(_04_),
    .B(reset),
    .Y(_00_[0])
  );
  NOR _21_ (
    .A(_02_),
    .B(_01_),
    .Y(_05_)
  );
  NAND _22_ (
    .A(_05_),
    .B(CTR[1]),
    .Y(_06_)
  );
  NOT _23_ (
    .A(CTR[1]),
    .Y(_07_)
  );
  NAND _24_ (
    .A(_14_),
    .B(_07_),
    .Y(_08_)
  );
  NAND _25_ (
    .A(_08_),
    .B(_06_),
    .Y(_09_)
  );
  NAND _26_ (
    .A(_09_),
    .B(reset),
    .Y(_00_[1])
  );
  NAND _27_ (
    .A(_06_),
    .B(CTR[2]),
    .Y(_10_)
  );
  NOT _28_ (
    .A(reset),
    .Y(_11_)
  );
  NOR _29_ (
    .A(_06_),
    .B(CTR[2]),
    .Y(_12_)
  );
  NOR _30_ (
    .A(_12_),
    .B(_11_),
    .Y(_13_)
  );
  NAND _31_ (
    .A(_13_),
    .B(_10_),
    .Y(_00_[2])
  );
  always @(posedge CLK)
      CTR[0] <= _00_[0];
  always @(posedge CLK)
      CTR[1] <= _00_[1];
  always @(posedge CLK)
      CTR[2] <= _00_[2];
endmodule
module mux_ctr_synth(valid_count, CLK, reset, CTR);

  wire [2:0] _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  input CLK;
  output [2:0] CTR;
  reg [2:0] CTR;
  input reset;
  input valid_count;
  NAND _15_ (
    .A(valid_count),
    .B(CTR[0]),
    .Y(_14_)
  );
  NOT _16_ (
    .A(CTR[0]),
    .Y(_01_)
  );
  NOT _17_ (
    .A(valid_count),
    .Y(_02_)
  );
  NAND _18_ (
    .A(_02_),
    .B(_01_),
    .Y(_03_)
  );
  NAND _19_ (
    .A(_03_),
    .B(_14_),
    .Y(_04_)
  );
  NAND _20_ (
    .A(_04_),
    .B(reset),
    .Y(_00_[0])
  );
  NOR _21_ (
    .A(_02_),
    .B(_01_),
    .Y(_05_)
  );
  NAND _22_ (
    .A(_05_),
    .B(CTR[1]),
    .Y(_06_)
  );
  NOT _23_ (
    .A(CTR[1]),
    .Y(_07_)
  );
  NAND _24_ (
    .A(_14_),
    .B(_07_),
    .Y(_08_)
  );
  NAND _25_ (
    .A(_08_),
    .B(_06_),
    .Y(_09_)
  );
  NAND _26_ (
    .A(_09_),
    .B(reset),
    .Y(_00_[1])
  );
  NAND _27_ (
    .A(_06_),
    .B(CTR[2]),
    .Y(_10_)
  );
  NOT _28_ (
    .A(reset),
    .Y(_11_)
  );
  NOR _29_ (
    .A(_06_),
    .B(CTR[2]),
    .Y(_12_)
  );
  NOR _30_ (
    .A(_12_),
    .B(_11_),
    .Y(_13_)
  );
  NAND _31_ (
    .A(_13_),
    .B(_10_),
    .Y(_00_[2])
  );
  always @(posedge CLK)
      CTR[0] <= _00_[0];
  always @(posedge CLK)
      CTR[1] <= _00_[1];
  always @(posedge CLK)
      CTR[2] <= _00_[2];
endmodule