data/full_repos/permissive/143278/ivltests/always3.1.3B.v
 line:35: before: "assign"
1: b'%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/always3.1.3B.v:35: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s LOGAND generates 1 bits.\n                                                                            : ... In instance main\nalways assign value1 = 1\'b1 && 1\'b1 ;\n       ^~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module main ;

reg [3:0] value1 ;

initial
    if(value1 != 4'h1)
	$display("FAILED - 3.1.3B always assign reg_lvalue = boolean_expr\n");
    else
	begin
           $display("PASSED\n");
	   $finish;
        end

always assign value1 = 1'b1 && 1'b1 ;

endmodule
module main ;


reg [3:0] value1 ;

initial
    if(value1 != 4'h1)
	$display("FAILED - 3.1.3B always assign reg_lvalue = boolean_expr\n");
    else
	begin
           $display("PASSED\n");
	   $finish;
        end

always assign value1 = 1'b1 && 1'b1 ;

endmodule