data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v
None: at end of input
1: b'%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:1: Cannot find include file: cypress.v\n`include "cypress.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in,data/full_repos/permissive/193054270/cypress.v\n             data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in,data/full_repos/permissive/193054270/cypress.v.v\n             data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in,data/full_repos/permissive/193054270/cypress.v.sv\n             cypress.v\n             cypress.v.v\n             cypress.v.sv\n             obj_dir/cypress.v\n             obj_dir/cypress.v.v\n             obj_dir/cypress.v.sv\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:54: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:54: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                   ^\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:54: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:54: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:55: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:55: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:55: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:56: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:56: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:56: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:57: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:58: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:58: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:58: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:59: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:59: Define or directive not defined: \'`CS_A0_SRC__ALU\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:59: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:60: Define or directive not defined: \'`CS_FEEDBACK_ENBL\'\n    `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:60: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:60: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:61: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:62: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:62: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:62: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:63: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:63: Define or directive not defined: \'`CS_A0_SRC__ALU\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:63: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:64: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:64: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:64: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:65: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:66: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:66: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:66: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:67: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:67: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:67: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:68: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:68: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:68: Define or directive not defined: \'`CS_SI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:69: Define or directive not defined: \'`CS_CMP_SEL_CFGA\'\n    `CS_CMP_SEL_CFGA,  \n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:70: Define or directive not defined: \'`CS_ALU_OP_PASS\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:70: Define or directive not defined: \'`CS_SRCA_A0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:70: Define or directive not defined: \'`CS_SRCB_D0\'\n    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:71: Define or directive not defined: \'`CS_SHFT_OP_PASS\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:71: Define or directive not defined: \'`CS_A0_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:71: Define or directive not defined: \'`CS_A1_SRC_NONE\'\n    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:72: Define or directive not defined: \'`CS_FEEDBACK_DSBL\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/193054270/pa_in_dma/pa_in_dma.cydsn/pa_in/pa_in.v:72: Define or directive not defined: \'`CS_CI_SEL_CFGA\'\n    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\n                       ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module pa_in (
	input   clock,
    output  dma
);

localparam RG_IDLE = 3'b000;
localparam RG_COPY = 3'b001;
reg [2:0]rg_state;

reg[7:0] pa_in_reg;
reg[1:0] val_type;
reg load_fifo;

always @(posedge clock)
begin
case(rg_state)
    RG_IDLE:
    begin
        load_fifo = 1'b0;
        rg_state = RG_COPY;
    end
    
    RG_COPY:
    begin
        case(val_type)
        2'b00:
        begin
            pa_in_reg = 8'b11111111;
        end
        2'b01:
        begin
            pa_in_reg = 8'b11110000;
        end
        2'b10:
        begin
            pa_in_reg = 8'b11001100;
        end
        2'b11:
        begin
            pa_in_reg = 8'b10101010;
        end
        endcase
        val_type = val_type + 1'b1;
        load_fifo = 1'b1;
        rg_state = RG_IDLE;
    end
endcase
end

cy_psoc3_dp #(.cy_dpconfig(
{
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    8'hFF, 8'h00,
    8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
    `SC_SI_A_DEFSI,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, `SC_PI_DYN_EN,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
    `SC_CMP0_NOCHN,
    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}
)) dp(
    .clk(clock),
    .cs_addr(rg_state),
    .f0_load(load_fifo),
    .f0_bus_stat(dma),
    .pi(pa_in_reg)
);

endmodule
module pa_in (
	input   clock,
    output  dma
);


localparam RG_IDLE = 3'b000;
localparam RG_COPY = 3'b001;
reg [2:0]rg_state;

reg[7:0] pa_in_reg;
reg[1:0] val_type;
reg load_fifo;

always @(posedge clock)
begin
case(rg_state)
    RG_IDLE:
    begin
        load_fifo = 1'b0;
        rg_state = RG_COPY;
    end
    
    RG_COPY:
    begin
        case(val_type)
        2'b00:
        begin
            pa_in_reg = 8'b11111111;
        end
        2'b01:
        begin
            pa_in_reg = 8'b11110000;
        end
        2'b10:
        begin
            pa_in_reg = 8'b11001100;
        end
        2'b11:
        begin
            pa_in_reg = 8'b10101010;
        end
        endcase
        val_type = val_type + 1'b1;
        load_fifo = 1'b1;
        rg_state = RG_IDLE;
    end
endcase
end

cy_psoc3_dp #(.cy_dpconfig(
{
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
    `CS_CMP_SEL_CFGA,
    8'hFF, 8'h00,
    8'hFF, 8'hFF,
    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
    `SC_SI_A_DEFSI,
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, `SC_PI_DYN_EN,
    1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
    `SC_CMP0_NOCHN,
    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
    `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
    `SC_WRK16CAT_DSBL
}
)) dp(
    .clk(clock),
    .cs_addr(rg_state),
    .f0_load(load_fifo),
    .f0_bus_stat(dma),
    .pi(pa_in_reg)
);

endmodule