data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v
1: b'%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:48: Cannot find include file: e203_defines.v\n`include "e203_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v.v\n             data/full_repos/permissive/160924877/analysis/rtl/e203/core,data/full_repos/permissive/160924877/e203_defines.v.sv\n             e203_defines.v\n             e203_defines.v.v\n             e203_defines.v.sv\n             obj_dir/e203_defines.v\n             obj_dir/e203_defines.v.v\n             obj_dir/e203_defines.v.sv\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:54: Define or directive not defined: \'`E203_PC_SIZE\'\n input  [`E203_PC_SIZE-1:0] pc_rtvec,  \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:65: Define or directive not defined: \'`E203_PC_SIZE\'\noutput [`E203_PC_SIZE-1:0] ifu_req_pc,  \n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:79: Define or directive not defined: \'`E203_INSTR_SIZE\'\ninput  [`E203_INSTR_SIZE-1:0] ifu_rsp_instr,  \n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:84: Define or directive not defined: \'`E203_INSTR_SIZE\'\n output [`E203_INSTR_SIZE-1:0] ifu_o_ir, \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:85: Define or directive not defined: \'`E203_PC_SIZE\'\n output [`E203_PC_SIZE-1:0] ifu_o_pc,    \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:87: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:88: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:99: Define or directive not defined: \'`E203_PC_SIZE\'\n input   [`E203_PC_SIZE-1:0] pipe_flush_add_op1,  \n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:100: Define or directive not defined: \'`E203_PC_SIZE\'\n input   [`E203_PC_SIZE-1:0] pipe_flush_add_op2,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:116: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0] rf2ifu_x1,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:117: Define or directive not defined: \'`E203_XLEN\'\n input  [`E203_XLEN-1:0] rf2ifu_rs1,\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:120: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n input  [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:265: Define or directive not defined: \'`E203_INSTR_SIZE\'\n wire [`E203_INSTR_SIZE-1:0] ifu_ir_nxt = ifu_rsp_instr;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:279: Define or directive not defined: \'`E203_INSTR_SIZE\'\n wire [`E203_INSTR_SIZE-1:0] ifu_ir_r; \n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:283: Define or directive not defined: \'`E203_INSTR_SIZE\'\n sirv_gnrl_dfflr #(`E203_INSTR_SIZE/2) ifu_hi_ir_dfflr (ir_hi_ena, ifu_ir_nxt[31:16], ifu_ir_r[31:16], clk, rst_n);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:283: syntax error, unexpected \'/\', expecting \')\'\n sirv_gnrl_dfflr #(`E203_INSTR_SIZE/2) ifu_hi_ir_dfflr (ir_hi_ena, ifu_ir_nxt[31:16], ifu_ir_r[31:16], clk, rst_n);\n                                   ^\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:284: Define or directive not defined: \'`E203_INSTR_SIZE\'\n sirv_gnrl_dfflr #(`E203_INSTR_SIZE/2) ifu_lo_ir_dfflr (ir_lo_ena, ifu_ir_nxt[15: 0], ifu_ir_r[15: 0], clk, rst_n);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:284: syntax error, unexpected \'/\', expecting \')\'\n sirv_gnrl_dfflr #(`E203_INSTR_SIZE/2) ifu_lo_ir_dfflr (ir_lo_ena, ifu_ir_nxt[15: 0], ifu_ir_r[15: 0], clk, rst_n);\n                                   ^\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:288: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n wire [`E203_RFIDX_WIDTH-1:0] minidec_rs1idx;\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:289: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n wire [`E203_RFIDX_WIDTH-1:0] minidec_rs2idx;\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:303: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n wire [`E203_RFIDX_WIDTH-1:0] ir_rs1idx_r;\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:304: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n wire [`E203_RFIDX_WIDTH-1:0] ir_rs2idx_r;\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:309: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n wire [`E203_RFIDX_WIDTH-1:0] ir_rs1idx_nxt = minidec_rs1idx;\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:310: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n wire [`E203_RFIDX_WIDTH-1:0] ir_rs2idx_nxt = minidec_rs2idx;\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:311: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n sirv_gnrl_dfflr #(`E203_RFIDX_WIDTH) ir_rs1idx_dfflr (ir_rs1idx_ena, ir_rs1idx_nxt, ir_rs1idx_r, clk, rst_n);\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:312: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n sirv_gnrl_dfflr #(`E203_RFIDX_WIDTH) ir_rs2idx_dfflr (ir_rs2idx_ena, ir_rs2idx_nxt, ir_rs2idx_r, clk, rst_n);\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:314: Define or directive not defined: \'`E203_PC_SIZE\'\n wire [`E203_PC_SIZE-1:0] pc_r;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:315: Define or directive not defined: \'`E203_PC_SIZE\'\n wire [`E203_PC_SIZE-1:0] ifu_pc_nxt = pc_r;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:316: Define or directive not defined: \'`E203_PC_SIZE\'\n wire [`E203_PC_SIZE-1:0] ifu_pc_r;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:317: Define or directive not defined: \'`E203_PC_SIZE\'\n sirv_gnrl_dfflr #(`E203_PC_SIZE) ifu_pc_dfflr (ir_pc_vld_set, ifu_pc_nxt,  ifu_pc_r, clk, rst_n);\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:341: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n wire [`E203_RFIDX_WIDTH-1:0] ir_rdidx = dec2ifu_rdidx;\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:342: Define or directive not defined: \'`E203_RFIDX_WIDTH\'\n wire [`E203_RFIDX_WIDTH-1:0] minidec_jalr_rs1idx;\n       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:387: Define or directive not defined: \'`E203_XLEN\'\n wire [`E203_XLEN-1:0] minidec_bjp_imm;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:419: Define or directive not defined: \'`E203_PC_SIZE\'\n wire [`E203_PC_SIZE-1:0] prdt_pc_add_op1;  \n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:420: Define or directive not defined: \'`E203_PC_SIZE\'\n wire [`E203_PC_SIZE-1:0] prdt_pc_add_op2;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:456: Define or directive not defined: \'`E203_PC_SIZE\'\n wire [`E203_PC_SIZE-1:0] pc_nxt_pre;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:457: Define or directive not defined: \'`E203_PC_SIZE\'\n wire [`E203_PC_SIZE-1:0] pc_nxt;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:461: Define or directive not defined: \'`E203_PC_SIZE\'\n wire [`E203_PC_SIZE-1:0] pc_add_op1 = \n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:466: Define or directive not defined: \'`E203_PC_SIZE\'\n wire [`E203_PC_SIZE-1:0] pc_add_op2 =  \n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:468: Define or directive not defined: \'`E203_PC_SIZE\'\n    reset_req_r   ? `E203_PC_SIZE\'b0 :\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:479: Define or directive not defined: \'`E203_PC_SIZE\'\n   pipe_flush_req ? {pipe_flush_pc[`E203_PC_SIZE-1:1],1\'b0} :\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:480: Define or directive not defined: \'`E203_PC_SIZE\'\n   dly_flush_r ? {pc_r[`E203_PC_SIZE-1:1],1\'b0} :\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:481: Define or directive not defined: \'`E203_PC_SIZE\'\n   {pc_nxt_pre[`E203_PC_SIZE-1:1],1\'b0};\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/160924877/analysis/rtl/e203/core/e203_ifu_ifetch.v:516: Define or directive not defined: \'`E203_PC_SIZE\'\n sirv_gnrl_dfflr #(`E203_PC_SIZE) pc_dfflr (pc_ena, pc_nxt, pc_r, clk, rst_n);\n                   ^~~~~~~~~~~~~\n%Error: Exiting due to 45 error(s)\n'
module e203_ifu_ifetch(



	input  [`E203_PC_SIZE-1:0] pc_rtvec,  




output ifu_req_valid,
input  ifu_req_ready,




output [`E203_PC_SIZE-1:0] ifu_req_pc,





input  ifu_rsp_valid,
output ifu_rsp_ready,






input  [`E203_INSTR_SIZE-1:0] ifu_rsp_instr,




	output [`E203_INSTR_SIZE-1:0] ifu_o_ir,
	output [`E203_PC_SIZE-1:0] ifu_o_pc,
	output ifu_o_pc_vld,
	output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,
	output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,
	output ifu_o_prdt_taken,


	output ifu_o_muldiv_b2b,
	output ifu_o_valid,
	
	input  ifu_o_ready,


	input   pipe_flush_req,
	input   [`E203_PC_SIZE-1:0] pipe_flush_add_op1,  
	input   [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
	`ifdef E203_TIMING_BOOST
	input   [`E203_PC_SIZE-1:0] pipe_flush_pc,  
	`endif

			





	input  ifu_halt_req,
	output ifu_halt_ack,


	input  oitf_empty,
	input  [`E203_XLEN-1:0] rf2ifu_x1,
	input  [`E203_XLEN-1:0] rf2ifu_rs1,
	input  dec2ifu_rs1en,
	input  dec2ifu_rden,
	input  [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,
	input  dec2ifu_mulhsu,
	input  dec2ifu_div   ,
	input  dec2ifu_rem   ,
	input  dec2ifu_divu  ,
	input  dec2ifu_remu  ,

	input  clk,
	input  rst_n
	);

	wire ifu_req_hsked  = (ifu_req_valid & ifu_req_ready) ;
	wire ifu_rsp_hsked  = (ifu_rsp_valid & ifu_rsp_ready) ;
	wire ifu_ir_o_hsked = (ifu_o_valid & ifu_o_ready) ;


	




	wire reset_flag_r;
	sirv_gnrl_dffrs #(1) reset_flag_dffrs (1'b0, reset_flag_r, clk, rst_n);






	wire reset_req_r;
	wire reset_req_set = (~reset_req_r) & reset_flag_r;
	wire reset_req_clr = reset_req_r & ifu_req_hsked;
	wire reset_req_ena = reset_req_set | reset_req_clr;
	wire reset_req_nxt = reset_req_set | (~reset_req_clr);

	sirv_gnrl_dfflr #(1) reset_req_dfflr (reset_req_ena, reset_req_nxt, reset_req_r, clk, rst_n);










	wire halt_ack_set;
	wire halt_ack_clr;
	wire halt_ack_ena;
	wire halt_ack_r;
	wire halt_ack_nxt;






	wire ifu_no_outs;
	assign halt_ack_set = ifu_halt_req & (~halt_ack_r) & ifu_no_outs;



	assign halt_ack_clr = halt_ack_r & (~ifu_halt_req);

	assign halt_ack_ena = halt_ack_set | halt_ack_clr;
	assign halt_ack_nxt = halt_ack_set | (~halt_ack_clr);

	sirv_gnrl_dfflr #(1) halt_ack_dfflr (halt_ack_ena, halt_ack_nxt, halt_ack_r, clk, rst_n);

	assign ifu_halt_ack = halt_ack_r;















	wire dly_flush_set;
	wire dly_flush_clr;
	wire dly_flush_ena;
	wire dly_flush_nxt;




	wire dly_flush_r;
	assign dly_flush_set = pipe_flush_req & (~ifu_req_hsked);


	assign dly_flush_clr = dly_flush_r & ifu_req_hsked;
	assign dly_flush_ena = dly_flush_set | dly_flush_clr;
	assign dly_flush_nxt = dly_flush_set | (~dly_flush_clr);

	sirv_gnrl_dfflr #(1) dly_flush_dfflr (dly_flush_ena, dly_flush_nxt, dly_flush_r, clk, rst_n);


	wire pipe_flush_req_real = pipe_flush_req | dly_flush_r;






	wire ir_valid_set;
	wire ir_valid_clr;
	wire ir_valid_ena;
	wire ir_valid_r;
	wire ir_valid_nxt;

	wire ir_pc_vld_set;

	wire ir_pc_vld_ena;
	wire ir_pc_vld_r;
	wire ir_pc_vld_nxt;





	wire pc_newpend_r;
	wire ifu_ir_i_ready;
	assign ir_valid_set  = ifu_rsp_hsked & (~pipe_flush_req_real) ;
	assign ir_pc_vld_set = pc_newpend_r & ifu_ir_i_ready & (~pipe_flush_req_real);


	assign ir_valid_clr  = ifu_ir_o_hsked | (pipe_flush_req & ir_valid_r);


	assign ir_valid_ena  = ir_valid_set  | ir_valid_clr;
	assign ir_valid_nxt  = ir_valid_set  | (~ir_valid_clr);
	assign ir_pc_vld_ena = ir_pc_vld_set | ir_valid_clr;
	assign ir_pc_vld_nxt = ir_pc_vld_set | (~ir_valid_clr);

	sirv_gnrl_dfflr #(1) ir_valid_dfflr (ir_valid_ena, ir_valid_nxt, ir_valid_r, clk, rst_n);
	sirv_gnrl_dfflr #(1) ir_pc_vld_dfflr (ir_pc_vld_ena, ir_pc_vld_nxt, ir_pc_vld_r, clk, rst_n);


	wire [`E203_INSTR_SIZE-1:0] ifu_ir_nxt = ifu_rsp_instr;






	wire prdt_taken;  
	wire ifu_prdt_taken_r;
	sirv_gnrl_dfflr #(1) ifu_prdt_taken_dfflr (ir_valid_set, prdt_taken, ifu_prdt_taken_r, clk, rst_n);
	wire ifu_muldiv_b2b_nxt;
	wire ifu_muldiv_b2b_r;
	sirv_gnrl_dfflr #(1) ir_muldiv_b2b_dfflr (ir_valid_set, ifu_muldiv_b2b_nxt, ifu_muldiv_b2b_r, clk, rst_n);

	wire [`E203_INSTR_SIZE-1:0] ifu_ir_r;

	wire ir_hi_ena = ir_valid_set;
	wire ir_lo_ena = ir_valid_set;
	sirv_gnrl_dfflr #(`E203_INSTR_SIZE/2) ifu_hi_ir_dfflr (ir_hi_ena, ifu_ir_nxt[31:16], ifu_ir_r[31:16], clk, rst_n);
	sirv_gnrl_dfflr #(`E203_INSTR_SIZE/2) ifu_lo_ir_dfflr (ir_lo_ena, ifu_ir_nxt[15: 0], ifu_ir_r[15: 0], clk, rst_n);

	wire minidec_rs1en;
	wire minidec_rs2en;
	wire [`E203_RFIDX_WIDTH-1:0] minidec_rs1idx;
	wire [`E203_RFIDX_WIDTH-1:0] minidec_rs2idx;













	wire [`E203_RFIDX_WIDTH-1:0] ir_rs1idx_r;
	wire [`E203_RFIDX_WIDTH-1:0] ir_rs2idx_r;
	wire bpu2rf_rs1_ena;

	wire ir_rs1idx_ena = (ir_valid_set & minidec_rs1en) | bpu2rf_rs1_ena;
	wire ir_rs2idx_ena = (ir_valid_set & minidec_rs2en);
	wire [`E203_RFIDX_WIDTH-1:0] ir_rs1idx_nxt = minidec_rs1idx;
	wire [`E203_RFIDX_WIDTH-1:0] ir_rs2idx_nxt = minidec_rs2idx;
	sirv_gnrl_dfflr #(`E203_RFIDX_WIDTH) ir_rs1idx_dfflr (ir_rs1idx_ena, ir_rs1idx_nxt, ir_rs1idx_r, clk, rst_n);
	sirv_gnrl_dfflr #(`E203_RFIDX_WIDTH) ir_rs2idx_dfflr (ir_rs2idx_ena, ir_rs2idx_nxt, ir_rs2idx_r, clk, rst_n);

	wire [`E203_PC_SIZE-1:0] pc_r;
	wire [`E203_PC_SIZE-1:0] ifu_pc_nxt = pc_r;
	wire [`E203_PC_SIZE-1:0] ifu_pc_r;
	sirv_gnrl_dfflr #(`E203_PC_SIZE) ifu_pc_dfflr (ir_pc_vld_set, ifu_pc_nxt,  ifu_pc_r, clk, rst_n);

	assign ifu_o_ir  = ifu_ir_r;
	assign ifu_o_pc  = ifu_pc_r;



	assign ifu_o_rs1idx = ir_rs1idx_r;
	assign ifu_o_rs2idx = ir_rs2idx_r;
	assign ifu_o_prdt_taken = ifu_prdt_taken_r;
	assign ifu_o_muldiv_b2b = ifu_muldiv_b2b_r;

	assign ifu_o_valid  = ir_valid_r;
	assign ifu_o_pc_vld = ir_pc_vld_r;


	assign ifu_ir_i_ready   = (~ir_valid_r) | ir_valid_clr;




	wire ir_empty = ~ir_valid_r;
	wire ir_rs1en = dec2ifu_rs1en;
	wire ir_rden = dec2ifu_rden;
	wire [`E203_RFIDX_WIDTH-1:0] ir_rdidx = dec2ifu_rdidx;
	wire [`E203_RFIDX_WIDTH-1:0] minidec_jalr_rs1idx;
	wire jalr_rs1idx_cam_irrdidx = ir_rden & (minidec_jalr_rs1idx == ir_rdidx) & ir_valid_r;






	wire minidec_mul ;
	wire minidec_div ;
	wire minidec_rem ;
	wire minidec_divu;
	wire minidec_remu;
	assign ifu_muldiv_b2b_nxt = 
	(


		( 
			minidec_mul & dec2ifu_mulhsu)






			| ( minidec_div  & dec2ifu_rem)
			| ( minidec_rem  & dec2ifu_div)
			| ( minidec_divu & dec2ifu_remu)
			| ( minidec_remu & dec2ifu_divu)
		)

		& (ir_rs1idx_r == ir_rs1idx_nxt)
		& (ir_rs2idx_r == ir_rs2idx_nxt)

		& (~(ir_rs1idx_r == ir_rdidx))
		& (~(ir_rs2idx_r == ir_rdidx))
	;




	wire minidec_bjp;
	wire minidec_jal;
	wire minidec_jalr;
	wire minidec_bxx;
	wire [`E203_XLEN-1:0] minidec_bjp_imm;


	e203_ifu_minidec u_e203_ifu_minidec (
		.instr       (ifu_ir_nxt         ),

		.dec_rs1en   (minidec_rs1en      ),
		.dec_rs2en   (minidec_rs2en      ),
		.dec_rs1idx  (minidec_rs1idx     ),
		.dec_rs2idx  (minidec_rs2idx     ),


		.dec_bjp     (minidec_bjp        ),
		.dec_jal     (minidec_jal        ),
		.dec_jalr    (minidec_jalr       ),
		.dec_bxx     (minidec_bxx        ),


		.dec_mul     (minidec_mul ),
		.dec_div     (minidec_div ),
		.dec_rem     (minidec_rem ),
		.dec_divu    (minidec_divu),
		.dec_remu    (minidec_remu),



		.dec_jalr_rs1idx (minidec_jalr_rs1idx),
		.dec_bjp_imm (minidec_bjp_imm    )

	);

	wire bpu_wait;
	wire [`E203_PC_SIZE-1:0] prdt_pc_add_op1;  
	wire [`E203_PC_SIZE-1:0] prdt_pc_add_op2;

	e203_ifu_litebpu u_e203_ifu_litebpu(

		.pc                       (pc_r),
															
		.dec_jal                  (minidec_jal  ),
		.dec_jalr                 (minidec_jalr ),
		.dec_bxx                  (minidec_bxx  ),
		.dec_bjp_imm              (minidec_bjp_imm  ),
		.dec_jalr_rs1idx          (minidec_jalr_rs1idx  ),

		.dec_i_valid              (ifu_rsp_valid),
		.ir_valid_clr             (ir_valid_clr),
								
		.oitf_empty               (oitf_empty),
		.ir_empty                 (ir_empty  ),
		.ir_rs1en                 (ir_rs1en  ),

		.jalr_rs1idx_cam_irrdidx  (jalr_rs1idx_cam_irrdidx),
	
		.bpu_wait                 (bpu_wait       ),  
		.prdt_taken               (prdt_taken     ),  
		.prdt_pc_add_op1          (prdt_pc_add_op1),  
		.prdt_pc_add_op2          (prdt_pc_add_op2),

		.bpu2rf_rs1_ena           (bpu2rf_rs1_ena),
		.rf2bpu_x1                (rf2ifu_x1    ),
		.rf2bpu_rs1               (rf2ifu_rs1   ),

		.clk                      (clk  ) ,
		.rst_n                    (rst_n )                 
	);

	wire [2:0] pc_incr_ofst =  3'd4;

	wire [`E203_PC_SIZE-1:0] pc_nxt_pre;
	wire [`E203_PC_SIZE-1:0] pc_nxt;

	wire bjp_req = minidec_bjp & prdt_taken;

	wire [`E203_PC_SIZE-1:0] pc_add_op1 = 
				bjp_req ? prdt_pc_add_op1    :
				reset_req_r   ? pc_rtvec :
				pc_r;

	wire [`E203_PC_SIZE-1:0] pc_add_op2 =  
				bjp_req ? prdt_pc_add_op2    :
				reset_req_r   ? `E203_PC_SIZE'b0 :
				pc_incr_ofst ;






	assign pc_nxt_pre = pc_add_op1 + pc_add_op2;

	assign pc_nxt = 
			pipe_flush_req ? {pipe_flush_pc[`E203_PC_SIZE-1:1],1'b0} :
			dly_flush_r ? {pc_r[`E203_PC_SIZE-1:1],1'b0} :
			{pc_nxt_pre[`E203_PC_SIZE-1:1],1'b0};





	wire ifu_new_req = (~bpu_wait) & (~ifu_halt_req) & (~reset_flag_r);




	wire ifu_req_valid_pre = ifu_new_req | reset_req_r | pipe_flush_req_real;



	wire out_flag_clr;
	wire out_flag_r;
	wire new_req_condi = (~out_flag_r) | out_flag_clr;
	assign ifu_no_outs = (~out_flag_r) | ifu_rsp_valid;




	assign ifu_req_valid = ifu_req_valid_pre & new_req_condi;


	wire ifu_rsp2ir_ready = (pipe_flush_req_real) ? 1'b1 : (ifu_ir_i_ready & ifu_req_ready & (~bpu_wait));



	assign ifu_rsp_ready = ifu_rsp2ir_ready;


	wire pc_ena = ifu_req_hsked | pipe_flush_req;

	sirv_gnrl_dfflr #(`E203_PC_SIZE) pc_dfflr (pc_ena, pc_nxt, pc_r, clk, rst_n);


	assign ifu_req_pc    = pc_nxt;


	wire out_flag_set = ifu_req_hsked;

	assign out_flag_clr = ifu_rsp_hsked;
	wire out_flag_ena = out_flag_set | out_flag_clr;

	wire out_flag_nxt = out_flag_set | (~out_flag_clr);

	sirv_gnrl_dfflr #(1) out_flag_dfflr (out_flag_ena, out_flag_nxt, out_flag_r, clk, rst_n);


	wire pc_newpend_set = pc_ena;

	wire pc_newpend_clr = ir_pc_vld_set;
	wire pc_newpend_ena = pc_newpend_set | pc_newpend_clr;

	wire pc_newpend_nxt = pc_newpend_set | (~pc_newpend_clr);

	sirv_gnrl_dfflr #(1) pc_newpend_dfflr (pc_newpend_ena, pc_newpend_nxt, pc_newpend_r, clk, rst_n);



	`ifndef FPGA_SOURCE
	`ifndef DISABLE_SV_ASSERTION


CHECK_IFU_REQ_VALID_NO_X:
	assert property (@(posedge clk) disable iff (~rst_n)
										 (ifu_req_valid !== 1'bx)
									)
	else $fatal ("\n Error: Oops, detected X value for ifu_req_valid !!! This should never happen. \n");


`endif
`endif

endmodule
module e203_ifu_ifetch(



	input  [`E203_PC_SIZE-1:0] pc_rtvec,  




output ifu_req_valid,
input  ifu_req_ready,




output [`E203_PC_SIZE-1:0] ifu_req_pc,





input  ifu_rsp_valid,
output ifu_rsp_ready,






input  [`E203_INSTR_SIZE-1:0] ifu_rsp_instr,




	output [`E203_INSTR_SIZE-1:0] ifu_o_ir,
	output [`E203_PC_SIZE-1:0] ifu_o_pc,
	output ifu_o_pc_vld,
	output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,
	output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,
	output ifu_o_prdt_taken,


	output ifu_o_muldiv_b2b,
	output ifu_o_valid,
	
	input  ifu_o_ready,


	input   pipe_flush_req,
	input   [`E203_PC_SIZE-1:0] pipe_flush_add_op1,  
	input   [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
	`ifdef E203_TIMING_BOOST
	input   [`E203_PC_SIZE-1:0] pipe_flush_pc,  
	`endif

			





	input  ifu_halt_req,
	output ifu_halt_ack,


	input  oitf_empty,
	input  [`E203_XLEN-1:0] rf2ifu_x1,
	input  [`E203_XLEN-1:0] rf2ifu_rs1,
	input  dec2ifu_rs1en,
	input  dec2ifu_rden,
	input  [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,
	input  dec2ifu_mulhsu,
	input  dec2ifu_div   ,
	input  dec2ifu_rem   ,
	input  dec2ifu_divu  ,
	input  dec2ifu_remu  ,

	input  clk,
	input  rst_n
	);


	wire ifu_req_hsked  = (ifu_req_valid & ifu_req_ready) ;
	wire ifu_rsp_hsked  = (ifu_rsp_valid & ifu_rsp_ready) ;
	wire ifu_ir_o_hsked = (ifu_o_valid & ifu_o_ready) ;


	




	wire reset_flag_r;
	sirv_gnrl_dffrs #(1) reset_flag_dffrs (1'b0, reset_flag_r, clk, rst_n);






	wire reset_req_r;
	wire reset_req_set = (~reset_req_r) & reset_flag_r;
	wire reset_req_clr = reset_req_r & ifu_req_hsked;
	wire reset_req_ena = reset_req_set | reset_req_clr;
	wire reset_req_nxt = reset_req_set | (~reset_req_clr);

	sirv_gnrl_dfflr #(1) reset_req_dfflr (reset_req_ena, reset_req_nxt, reset_req_r, clk, rst_n);










	wire halt_ack_set;
	wire halt_ack_clr;
	wire halt_ack_ena;
	wire halt_ack_r;
	wire halt_ack_nxt;






	wire ifu_no_outs;
	assign halt_ack_set = ifu_halt_req & (~halt_ack_r) & ifu_no_outs;



	assign halt_ack_clr = halt_ack_r & (~ifu_halt_req);

	assign halt_ack_ena = halt_ack_set | halt_ack_clr;
	assign halt_ack_nxt = halt_ack_set | (~halt_ack_clr);

	sirv_gnrl_dfflr #(1) halt_ack_dfflr (halt_ack_ena, halt_ack_nxt, halt_ack_r, clk, rst_n);

	assign ifu_halt_ack = halt_ack_r;















	wire dly_flush_set;
	wire dly_flush_clr;
	wire dly_flush_ena;
	wire dly_flush_nxt;




	wire dly_flush_r;
	assign dly_flush_set = pipe_flush_req & (~ifu_req_hsked);


	assign dly_flush_clr = dly_flush_r & ifu_req_hsked;
	assign dly_flush_ena = dly_flush_set | dly_flush_clr;
	assign dly_flush_nxt = dly_flush_set | (~dly_flush_clr);

	sirv_gnrl_dfflr #(1) dly_flush_dfflr (dly_flush_ena, dly_flush_nxt, dly_flush_r, clk, rst_n);


	wire pipe_flush_req_real = pipe_flush_req | dly_flush_r;






	wire ir_valid_set;
	wire ir_valid_clr;
	wire ir_valid_ena;
	wire ir_valid_r;
	wire ir_valid_nxt;

	wire ir_pc_vld_set;

	wire ir_pc_vld_ena;
	wire ir_pc_vld_r;
	wire ir_pc_vld_nxt;





	wire pc_newpend_r;
	wire ifu_ir_i_ready;
	assign ir_valid_set  = ifu_rsp_hsked & (~pipe_flush_req_real) ;
	assign ir_pc_vld_set = pc_newpend_r & ifu_ir_i_ready & (~pipe_flush_req_real);


	assign ir_valid_clr  = ifu_ir_o_hsked | (pipe_flush_req & ir_valid_r);


	assign ir_valid_ena  = ir_valid_set  | ir_valid_clr;
	assign ir_valid_nxt  = ir_valid_set  | (~ir_valid_clr);
	assign ir_pc_vld_ena = ir_pc_vld_set | ir_valid_clr;
	assign ir_pc_vld_nxt = ir_pc_vld_set | (~ir_valid_clr);

	sirv_gnrl_dfflr #(1) ir_valid_dfflr (ir_valid_ena, ir_valid_nxt, ir_valid_r, clk, rst_n);
	sirv_gnrl_dfflr #(1) ir_pc_vld_dfflr (ir_pc_vld_ena, ir_pc_vld_nxt, ir_pc_vld_r, clk, rst_n);


	wire [`E203_INSTR_SIZE-1:0] ifu_ir_nxt = ifu_rsp_instr;






	wire prdt_taken;  
	wire ifu_prdt_taken_r;
	sirv_gnrl_dfflr #(1) ifu_prdt_taken_dfflr (ir_valid_set, prdt_taken, ifu_prdt_taken_r, clk, rst_n);
	wire ifu_muldiv_b2b_nxt;
	wire ifu_muldiv_b2b_r;
	sirv_gnrl_dfflr #(1) ir_muldiv_b2b_dfflr (ir_valid_set, ifu_muldiv_b2b_nxt, ifu_muldiv_b2b_r, clk, rst_n);

	wire [`E203_INSTR_SIZE-1:0] ifu_ir_r;

	wire ir_hi_ena = ir_valid_set;
	wire ir_lo_ena = ir_valid_set;
	sirv_gnrl_dfflr #(`E203_INSTR_SIZE/2) ifu_hi_ir_dfflr (ir_hi_ena, ifu_ir_nxt[31:16], ifu_ir_r[31:16], clk, rst_n);
	sirv_gnrl_dfflr #(`E203_INSTR_SIZE/2) ifu_lo_ir_dfflr (ir_lo_ena, ifu_ir_nxt[15: 0], ifu_ir_r[15: 0], clk, rst_n);

	wire minidec_rs1en;
	wire minidec_rs2en;
	wire [`E203_RFIDX_WIDTH-1:0] minidec_rs1idx;
	wire [`E203_RFIDX_WIDTH-1:0] minidec_rs2idx;













	wire [`E203_RFIDX_WIDTH-1:0] ir_rs1idx_r;
	wire [`E203_RFIDX_WIDTH-1:0] ir_rs2idx_r;
	wire bpu2rf_rs1_ena;

	wire ir_rs1idx_ena = (ir_valid_set & minidec_rs1en) | bpu2rf_rs1_ena;
	wire ir_rs2idx_ena = (ir_valid_set & minidec_rs2en);
	wire [`E203_RFIDX_WIDTH-1:0] ir_rs1idx_nxt = minidec_rs1idx;
	wire [`E203_RFIDX_WIDTH-1:0] ir_rs2idx_nxt = minidec_rs2idx;
	sirv_gnrl_dfflr #(`E203_RFIDX_WIDTH) ir_rs1idx_dfflr (ir_rs1idx_ena, ir_rs1idx_nxt, ir_rs1idx_r, clk, rst_n);
	sirv_gnrl_dfflr #(`E203_RFIDX_WIDTH) ir_rs2idx_dfflr (ir_rs2idx_ena, ir_rs2idx_nxt, ir_rs2idx_r, clk, rst_n);

	wire [`E203_PC_SIZE-1:0] pc_r;
	wire [`E203_PC_SIZE-1:0] ifu_pc_nxt = pc_r;
	wire [`E203_PC_SIZE-1:0] ifu_pc_r;
	sirv_gnrl_dfflr #(`E203_PC_SIZE) ifu_pc_dfflr (ir_pc_vld_set, ifu_pc_nxt,  ifu_pc_r, clk, rst_n);

	assign ifu_o_ir  = ifu_ir_r;
	assign ifu_o_pc  = ifu_pc_r;



	assign ifu_o_rs1idx = ir_rs1idx_r;
	assign ifu_o_rs2idx = ir_rs2idx_r;
	assign ifu_o_prdt_taken = ifu_prdt_taken_r;
	assign ifu_o_muldiv_b2b = ifu_muldiv_b2b_r;

	assign ifu_o_valid  = ir_valid_r;
	assign ifu_o_pc_vld = ir_pc_vld_r;


	assign ifu_ir_i_ready   = (~ir_valid_r) | ir_valid_clr;




	wire ir_empty = ~ir_valid_r;
	wire ir_rs1en = dec2ifu_rs1en;
	wire ir_rden = dec2ifu_rden;
	wire [`E203_RFIDX_WIDTH-1:0] ir_rdidx = dec2ifu_rdidx;
	wire [`E203_RFIDX_WIDTH-1:0] minidec_jalr_rs1idx;
	wire jalr_rs1idx_cam_irrdidx = ir_rden & (minidec_jalr_rs1idx == ir_rdidx) & ir_valid_r;






	wire minidec_mul ;
	wire minidec_div ;
	wire minidec_rem ;
	wire minidec_divu;
	wire minidec_remu;
	assign ifu_muldiv_b2b_nxt = 
	(


		( 
			minidec_mul & dec2ifu_mulhsu)






			| ( minidec_div  & dec2ifu_rem)
			| ( minidec_rem  & dec2ifu_div)
			| ( minidec_divu & dec2ifu_remu)
			| ( minidec_remu & dec2ifu_divu)
		)

		& (ir_rs1idx_r == ir_rs1idx_nxt)
		& (ir_rs2idx_r == ir_rs2idx_nxt)

		& (~(ir_rs1idx_r == ir_rdidx))
		& (~(ir_rs2idx_r == ir_rdidx))
	;




	wire minidec_bjp;
	wire minidec_jal;
	wire minidec_jalr;
	wire minidec_bxx;
	wire [`E203_XLEN-1:0] minidec_bjp_imm;


	e203_ifu_minidec u_e203_ifu_minidec (
		.instr       (ifu_ir_nxt         ),

		.dec_rs1en   (minidec_rs1en      ),
		.dec_rs2en   (minidec_rs2en      ),
		.dec_rs1idx  (minidec_rs1idx     ),
		.dec_rs2idx  (minidec_rs2idx     ),


		.dec_bjp     (minidec_bjp        ),
		.dec_jal     (minidec_jal        ),
		.dec_jalr    (minidec_jalr       ),
		.dec_bxx     (minidec_bxx        ),


		.dec_mul     (minidec_mul ),
		.dec_div     (minidec_div ),
		.dec_rem     (minidec_rem ),
		.dec_divu    (minidec_divu),
		.dec_remu    (minidec_remu),



		.dec_jalr_rs1idx (minidec_jalr_rs1idx),
		.dec_bjp_imm (minidec_bjp_imm    )

	);

	wire bpu_wait;
	wire [`E203_PC_SIZE-1:0] prdt_pc_add_op1;  
	wire [`E203_PC_SIZE-1:0] prdt_pc_add_op2;

	e203_ifu_litebpu u_e203_ifu_litebpu(

		.pc                       (pc_r),
															
		.dec_jal                  (minidec_jal  ),
		.dec_jalr                 (minidec_jalr ),
		.dec_bxx                  (minidec_bxx  ),
		.dec_bjp_imm              (minidec_bjp_imm  ),
		.dec_jalr_rs1idx          (minidec_jalr_rs1idx  ),

		.dec_i_valid              (ifu_rsp_valid),
		.ir_valid_clr             (ir_valid_clr),
								
		.oitf_empty               (oitf_empty),
		.ir_empty                 (ir_empty  ),
		.ir_rs1en                 (ir_rs1en  ),

		.jalr_rs1idx_cam_irrdidx  (jalr_rs1idx_cam_irrdidx),
	
		.bpu_wait                 (bpu_wait       ),  
		.prdt_taken               (prdt_taken     ),  
		.prdt_pc_add_op1          (prdt_pc_add_op1),  
		.prdt_pc_add_op2          (prdt_pc_add_op2),

		.bpu2rf_rs1_ena           (bpu2rf_rs1_ena),
		.rf2bpu_x1                (rf2ifu_x1    ),
		.rf2bpu_rs1               (rf2ifu_rs1   ),

		.clk                      (clk  ) ,
		.rst_n                    (rst_n )                 
	);

	wire [2:0] pc_incr_ofst =  3'd4;

	wire [`E203_PC_SIZE-1:0] pc_nxt_pre;
	wire [`E203_PC_SIZE-1:0] pc_nxt;

	wire bjp_req = minidec_bjp & prdt_taken;

	wire [`E203_PC_SIZE-1:0] pc_add_op1 = 
				bjp_req ? prdt_pc_add_op1    :
				reset_req_r   ? pc_rtvec :
				pc_r;

	wire [`E203_PC_SIZE-1:0] pc_add_op2 =  
				bjp_req ? prdt_pc_add_op2    :
				reset_req_r   ? `E203_PC_SIZE'b0 :
				pc_incr_ofst ;






	assign pc_nxt_pre = pc_add_op1 + pc_add_op2;

	assign pc_nxt = 
			pipe_flush_req ? {pipe_flush_pc[`E203_PC_SIZE-1:1],1'b0} :
			dly_flush_r ? {pc_r[`E203_PC_SIZE-1:1],1'b0} :
			{pc_nxt_pre[`E203_PC_SIZE-1:1],1'b0};





	wire ifu_new_req = (~bpu_wait) & (~ifu_halt_req) & (~reset_flag_r);




	wire ifu_req_valid_pre = ifu_new_req | reset_req_r | pipe_flush_req_real;



	wire out_flag_clr;
	wire out_flag_r;
	wire new_req_condi = (~out_flag_r) | out_flag_clr;
	assign ifu_no_outs = (~out_flag_r) | ifu_rsp_valid;




	assign ifu_req_valid = ifu_req_valid_pre & new_req_condi;


	wire ifu_rsp2ir_ready = (pipe_flush_req_real) ? 1'b1 : (ifu_ir_i_ready & ifu_req_ready & (~bpu_wait));



	assign ifu_rsp_ready = ifu_rsp2ir_ready;


	wire pc_ena = ifu_req_hsked | pipe_flush_req;

	sirv_gnrl_dfflr #(`E203_PC_SIZE) pc_dfflr (pc_ena, pc_nxt, pc_r, clk, rst_n);


	assign ifu_req_pc    = pc_nxt;


	wire out_flag_set = ifu_req_hsked;

	assign out_flag_clr = ifu_rsp_hsked;
	wire out_flag_ena = out_flag_set | out_flag_clr;

	wire out_flag_nxt = out_flag_set | (~out_flag_clr);

	sirv_gnrl_dfflr #(1) out_flag_dfflr (out_flag_ena, out_flag_nxt, out_flag_r, clk, rst_n);


	wire pc_newpend_set = pc_ena;

	wire pc_newpend_clr = ir_pc_vld_set;
	wire pc_newpend_ena = pc_newpend_set | pc_newpend_clr;

	wire pc_newpend_nxt = pc_newpend_set | (~pc_newpend_clr);

	sirv_gnrl_dfflr #(1) pc_newpend_dfflr (pc_newpend_ena, pc_newpend_nxt, pc_newpend_r, clk, rst_n);



	`ifndef FPGA_SOURCE
	`ifndef DISABLE_SV_ASSERTION


CHECK_IFU_REQ_VALID_NO_X:
	assert property (@(posedge clk) disable iff (~rst_n)
										 (ifu_req_valid !== 1'bx)
									)
	else $fatal ("\n Error: Oops, detected X value for ifu_req_valid !!! This should never happen. \n");


`endif
`endif

endmodule