data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/top/b200/sim/b200_tb.v
1: b"%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/top/b200/sim/b200_tb.v:107: Cannot find file containing module: 'b200'\n   b200 b200_i1(\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/top/b200/sim,data/full_repos/permissive/214858095/b200\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/top/b200/sim,data/full_repos/permissive/214858095/b200.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/top/b200/sim,data/full_repos/permissive/214858095/b200.sv\n             b200\n             b200.v\n             b200.sv\n             obj_dir/b200\n             obj_dir/b200.v\n             obj_dir/b200.sv\n%Error: Exiting due to 1 error(s)\n"
module b200_tb ();

   wire cat_ce;
   wire cat_miso;
   wire cat_mosi;
   wire cat_sclk;

   wire fx3_ce;
   wire fx3_miso;
   wire fx3_mosi;
   wire fx3_sclk;

   wire pll_ce;
   wire pll_mosi;
   wire pll_sclk;


   wire FPGA_RXD0;
   wire FPGA_TXD0;


   wire codec_enable;
   wire codec_en_agc;
   wire codec_reset;
   wire codec_sync;
   wire codec_txrx;
   wire [3:0] codec_ctrl_in;
   wire [7:0] codec_ctrl_out;


   wire       codec_data_clk_p;
   wire       codec_fb_clk_p;
   wire [11:0] rx_codec_d;
   wire [11:0] tx_codec_d;
   wire        rx_frame_p;
   wire        tx_frame_p;

   wire        cat_clkout_fpga;


   wire        codec_main_clk_p;
   wire        codec_main_clk_n;


   wire [31:0] debug;
   wire [1:0]  debug_clk;


   wire        IFCLK;
   wire        FX3_EXTINT;
   wire        GPIF_CTL0;
   wire        GPIF_CTL1;
   wire        GPIF_CTL2;
   wire        GPIF_CTL3;
   wire        GPIF_CTL7;
   wire        GPIF_CTL4;
   wire        GPIF_CTL5;
   wire        GPIF_CTL6;
   wire        GPIF_CTL8;
   wire        GPIF_CTL11;
   wire        GPIF_CTL12;
   wire [31:0] GPIF_D;
   wire        GPIF_CTL9;


   wire        gps_lock;
   wire        gps_rxd;
   wire        gps_txd;
   wire        gps_txd_nmea;


   wire        LED_RX1;
   wire        LED_RX2;
   wire        LED_TXRX1_RX;
   wire        LED_TXRX1_TX;
   wire        LED_TXRX2_RX;
   wire        LED_TXRX2_TX;


   wire        ref_sel;
   wire        pll_lock;
   wire        FPGA_CFG_CS;
   wire        AUX_PWR_ON;


   wire        PPS_IN_EXT;
   wire        PPS_IN_INT;


   wire        SFDX1_RX;
   wire        SFDX1_TX;
   wire        SFDX2_RX;
   wire        SFDX2_TX;
   wire        SRX1_RX;
   wire        SRX1_TX;
   wire        SRX2_RX;
   wire        SRX2_TX;
   wire        tx_bandsel_a;
   wire        tx_bandsel_b;
   wire        tx_enable1;
   wire        tx_enable2;
   wire        rx_bandsel_a;
   wire        rx_bandsel_b;
   wire        rx_bandsel_c;


   b200 b200_i1(

		.cat_ce(),
		.cat_miso(),
		.cat_mosi(),
		.cat_sclk(),

		.fx3_ce(),
		.fx3_miso(),
		.fx3_mosi(),
		.fx3_sclk(),

		.pll_ce(),
		.pll_mosi(),
		.pll_sclk(),


		.FPGA_RXD0(),
		.FPGA_TXD0(),


		.codec_enable(),
		.codec_en_agc(),
		.codec_reset(),
		.codec_sync(),
		.codec_txrx(),
		.codec_ctrl_in(),
		.codec_ctrl_out(),


		.codec_data_clk_p(),
		.codec_fb_clk_p(),
		.rx_codec_d(),
		.tx_codec_d(),
		.rx_frame_p(),
		.tx_frame_p(),

		.cat_clkout_fpga(),


		.codec_main_clk_p(),
		.codec_main_clk_n(),


		.debug(),
		.debug_clk(),


		.IFCLK(),
		.FX3_EXTINT(),
		.GPIF_CTL0(),
		.GPIF_CTL1(),
		.GPIF_CTL2(),
		.GPIF_CTL3(),
		.GPIF_CTL7(),
		.GPIF_CTL4(),
		.GPIF_CTL5(),
		.GPIF_CTL6(),
		.GPIF_CTL8(),
		.GPIF_CTL11(),
		.GPIF_CTL12(),
		.GPIF_D(),
		.GPIF_CTL9(),


		.gps_lock(),
		.gps_rxd(),
		.gps_txd(),
		.gps_txd_nmea(),


		.LED_RX1(),
		.LED_RX2(),
		.LED_TXRX1_RX(),
		.LED_TXRX1_TX(),
		.LED_TXRX2_RX(),
		.LED_TXRX2_TX(),


		.ref_sel(),
		.pll_lock(),
		.FPGA_CFG_CS(),
		.AUX_PWR_ON(),


		.PPS_IN_EXT(),
		.PPS_IN_INT(),


		.SFDX1_RX(),
		.SFDX1_TX(),
		.SFDX2_RX(),
		.SFDX2_TX(),
		.SRX1_RX(),
		.SRX1_TX(),
		.SRX2_RX(),
		.SRX2_TX(),
		.tx_bandsel_a(),
		.tx_bandsel_b(),
		.tx_enable1(),
		.tx_enable2(),
		.rx_bandsel_a(),
		.rx_bandsel_b(),
		.rx_bandsel_c()
		);

endmodule
module b200_tb ();


   wire cat_ce;
   wire cat_miso;
   wire cat_mosi;
   wire cat_sclk;

   wire fx3_ce;
   wire fx3_miso;
   wire fx3_mosi;
   wire fx3_sclk;

   wire pll_ce;
   wire pll_mosi;
   wire pll_sclk;


   wire FPGA_RXD0;
   wire FPGA_TXD0;


   wire codec_enable;
   wire codec_en_agc;
   wire codec_reset;
   wire codec_sync;
   wire codec_txrx;
   wire [3:0] codec_ctrl_in;
   wire [7:0] codec_ctrl_out;


   wire       codec_data_clk_p;
   wire       codec_fb_clk_p;
   wire [11:0] rx_codec_d;
   wire [11:0] tx_codec_d;
   wire        rx_frame_p;
   wire        tx_frame_p;

   wire        cat_clkout_fpga;


   wire        codec_main_clk_p;
   wire        codec_main_clk_n;


   wire [31:0] debug;
   wire [1:0]  debug_clk;


   wire        IFCLK;
   wire        FX3_EXTINT;
   wire        GPIF_CTL0;
   wire        GPIF_CTL1;
   wire        GPIF_CTL2;
   wire        GPIF_CTL3;
   wire        GPIF_CTL7;
   wire        GPIF_CTL4;
   wire        GPIF_CTL5;
   wire        GPIF_CTL6;
   wire        GPIF_CTL8;
   wire        GPIF_CTL11;
   wire        GPIF_CTL12;
   wire [31:0] GPIF_D;
   wire        GPIF_CTL9;


   wire        gps_lock;
   wire        gps_rxd;
   wire        gps_txd;
   wire        gps_txd_nmea;


   wire        LED_RX1;
   wire        LED_RX2;
   wire        LED_TXRX1_RX;
   wire        LED_TXRX1_TX;
   wire        LED_TXRX2_RX;
   wire        LED_TXRX2_TX;


   wire        ref_sel;
   wire        pll_lock;
   wire        FPGA_CFG_CS;
   wire        AUX_PWR_ON;


   wire        PPS_IN_EXT;
   wire        PPS_IN_INT;


   wire        SFDX1_RX;
   wire        SFDX1_TX;
   wire        SFDX2_RX;
   wire        SFDX2_TX;
   wire        SRX1_RX;
   wire        SRX1_TX;
   wire        SRX2_RX;
   wire        SRX2_TX;
   wire        tx_bandsel_a;
   wire        tx_bandsel_b;
   wire        tx_enable1;
   wire        tx_enable2;
   wire        rx_bandsel_a;
   wire        rx_bandsel_b;
   wire        rx_bandsel_c;


   b200 b200_i1(

		.cat_ce(),
		.cat_miso(),
		.cat_mosi(),
		.cat_sclk(),

		.fx3_ce(),
		.fx3_miso(),
		.fx3_mosi(),
		.fx3_sclk(),

		.pll_ce(),
		.pll_mosi(),
		.pll_sclk(),


		.FPGA_RXD0(),
		.FPGA_TXD0(),


		.codec_enable(),
		.codec_en_agc(),
		.codec_reset(),
		.codec_sync(),
		.codec_txrx(),
		.codec_ctrl_in(),
		.codec_ctrl_out(),


		.codec_data_clk_p(),
		.codec_fb_clk_p(),
		.rx_codec_d(),
		.tx_codec_d(),
		.rx_frame_p(),
		.tx_frame_p(),

		.cat_clkout_fpga(),


		.codec_main_clk_p(),
		.codec_main_clk_n(),


		.debug(),
		.debug_clk(),


		.IFCLK(),
		.FX3_EXTINT(),
		.GPIF_CTL0(),
		.GPIF_CTL1(),
		.GPIF_CTL2(),
		.GPIF_CTL3(),
		.GPIF_CTL7(),
		.GPIF_CTL4(),
		.GPIF_CTL5(),
		.GPIF_CTL6(),
		.GPIF_CTL8(),
		.GPIF_CTL11(),
		.GPIF_CTL12(),
		.GPIF_D(),
		.GPIF_CTL9(),


		.gps_lock(),
		.gps_rxd(),
		.gps_txd(),
		.gps_txd_nmea(),


		.LED_RX1(),
		.LED_RX2(),
		.LED_TXRX1_RX(),
		.LED_TXRX1_TX(),
		.LED_TXRX2_RX(),
		.LED_TXRX2_TX(),


		.ref_sel(),
		.pll_lock(),
		.FPGA_CFG_CS(),
		.AUX_PWR_ON(),


		.PPS_IN_EXT(),
		.PPS_IN_INT(),


		.SFDX1_RX(),
		.SFDX1_TX(),
		.SFDX2_RX(),
		.SFDX2_TX(),
		.SRX1_RX(),
		.SRX1_TX(),
		.SRX2_RX(),
		.SRX2_TX(),
		.tx_bandsel_a(),
		.tx_bandsel_b(),
		.tx_enable1(),
		.tx_enable2(),
		.rx_bandsel_a(),
		.rx_bandsel_b(),
		.rx_bandsel_c()
		);

endmodule