data/full_repos/permissive/136009613/accelerator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/136009613/accelerator.v:39: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_state_dec\' generates 16 bits.\n                                                                     : ... In instance accelerator\n assign instruction_in = data_state_dec;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/136009613/accelerator.v:44: Cannot find file containing module: \'rom\'\n rom r(.address(adr_rom_state), .data(data_rom_state));\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/136009613,data/full_repos/permissive/136009613/rom\n             data/full_repos/permissive/136009613,data/full_repos/permissive/136009613/rom.v\n             data/full_repos/permissive/136009613,data/full_repos/permissive/136009613/rom.sv\n             rom\n             rom.v\n             rom.sv\n             obj_dir/rom\n             obj_dir/rom.v\n             obj_dir/rom.sv\n%Error: data/full_repos/permissive/136009613/accelerator.v:46: Cannot find file containing module: \'state_machine\'\n state_machine s(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136009613/accelerator.v:51: Cannot find file containing module: \'decoder\'\n decoder d(\n ^~~~~~~\n%Error: data/full_repos/permissive/136009613/accelerator.v:56: Cannot find file containing module: \'memory\'\n memory m(\n ^~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module accelerator(
	clk,
	reset,
	rwn,
	data,
	address_test,
	
	rom_address,
	data_from_rom,
	instruction_in,
	instruction_out
);

	parameter address_size = 16;
	
	input clk, reset, rwn;
	input [address_size - 1:0] address_test;
	output [31:0] data;
	
	wire [7:0] adr_rom_state;
	wire [7:0] data_rom_state;
	
	wire ready_state_dec;
	wire start_state_dec;
	wire [15:0] data_state_dec;

	wire start_dec_mem;
	wire [31:0] data_dec_mem;
	wire [15:0] adr_dec_mem;

	
	output [7:0] rom_address;
	assign rom_address = adr_rom_state;
	
	output [7:0] data_from_rom;
	assign data_from_rom = data_rom_state;
	
	output [31:0] instruction_in;
	assign instruction_in = data_state_dec;
	
	output [31:0] instruction_out;
	assign instruction_out = data_dec_mem;
	
	rom r(.address(adr_rom_state), .data(data_rom_state));

	state_machine s(
		.clk(clk), .reset(reset), .ready_from_decoder(ready_state_dec), 
		.start_for_decoder(start_state_dec), .data_from_rom(data_rom_state), 
		.data_for_decoder(data_state_dec), .rom_address(adr_rom_state));

	decoder d(
		.clk(clk), .reset(reset), .start(start_state_dec), .ready(ready_state_dec),
		.instruction_in(data_state_dec), .instruction_out(data_dec_mem),
		.start_for_memory(start_dec_mem), .address_for_memory(adr_dec_mem));

	memory m(
		.clk(clk), .reset(reset), .address_dec(adr_dec_mem), .address_test(address_test), .data_in(data_dec_mem), 
		.data_out(data), .rwn(rwn), .start(start_dec_mem));

endmodule
module accelerator(
	clk,
	reset,
	rwn,
	data,
	address_test,
	
	rom_address,
	data_from_rom,
	instruction_in,
	instruction_out
);


	parameter address_size = 16;
	
	input clk, reset, rwn;
	input [address_size - 1:0] address_test;
	output [31:0] data;
	
	wire [7:0] adr_rom_state;
	wire [7:0] data_rom_state;
	
	wire ready_state_dec;
	wire start_state_dec;
	wire [15:0] data_state_dec;

	wire start_dec_mem;
	wire [31:0] data_dec_mem;
	wire [15:0] adr_dec_mem;

	
	output [7:0] rom_address;
	assign rom_address = adr_rom_state;
	
	output [7:0] data_from_rom;
	assign data_from_rom = data_rom_state;
	
	output [31:0] instruction_in;
	assign instruction_in = data_state_dec;
	
	output [31:0] instruction_out;
	assign instruction_out = data_dec_mem;
	
	rom r(.address(adr_rom_state), .data(data_rom_state));

	state_machine s(
		.clk(clk), .reset(reset), .ready_from_decoder(ready_state_dec), 
		.start_for_decoder(start_state_dec), .data_from_rom(data_rom_state), 
		.data_for_decoder(data_state_dec), .rom_address(adr_rom_state));

	decoder d(
		.clk(clk), .reset(reset), .start(start_state_dec), .ready(ready_state_dec),
		.instruction_in(data_state_dec), .instruction_out(data_dec_mem),
		.start_for_memory(start_dec_mem), .address_for_memory(adr_dec_mem));

	memory m(
		.clk(clk), .reset(reset), .address_dec(adr_dec_mem), .address_test(address_test), .data_in(data_dec_mem), 
		.data_out(data), .rwn(rwn), .start(start_dec_mem));

endmodule