data/full_repos/permissive/108908995/test_cells.v
 line:27: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/108908995/test_cells.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1 $display("y  = %h", y);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/108908995/test_cells.v:4: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'64\'h1234567\' generates 64 bits.\n                                                                   : ... In instance top\nwire [31:0]k = 64\'h01234567;\n             ^\n%Error: data/full_repos/permissive/108908995/test_cells.v:7: Cannot find file containing module: \'fcell\'\nfcell fc (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fcell\n             data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fcell.v\n             data/full_repos/permissive/108908995,data/full_repos/permissive/108908995/fcell.sv\n             fcell\n             fcell.v\n             fcell.sv\n             obj_dir/fcell\n             obj_dir/fcell.v\n             obj_dir/fcell.sv\n%Error: data/full_repos/permissive/108908995/test_cells.v:20: Cannot find file containing module: \'ifcell\'\nifcell ifc (\n^~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

wire [63:0]x = 64'hDEADBEEFBAADF00D;
wire [31:0]k = 64'h01234567;
wire [63:0]y;

fcell fc (
    .IN(x),
    .KEY(k),
    .OUT(y)
);

initial begin
    $display("x  = %h", x);
    $display("k  = %h", k);
end

wire [63:0]x_dec;

ifcell ifc (
    .IN(y),
    .KEY(k),
    .OUT(x_dec)
);

initial begin
    #1 $display("y  = %h", y);
    $display("x' = %h", x_dec);
    
    if (x == x_dec)
        $display("[PASSED]");
    else 
        $display("[FAILED]");
    
    $finish;
end

endmodule
module top;


wire [63:0]x = 64'hDEADBEEFBAADF00D;
wire [31:0]k = 64'h01234567;
wire [63:0]y;

fcell fc (
    .IN(x),
    .KEY(k),
    .OUT(y)
);

initial begin
    $display("x  = %h", x);
    $display("k  = %h", k);
end

wire [63:0]x_dec;

ifcell ifc (
    .IN(y),
    .KEY(k),
    .OUT(x_dec)
);

initial begin
    #1 $display("y  = %h", y);
    $display("x' = %h", x_dec);
    
    if (x == x_dec)
        $display("[PASSED]");
    else 
        $display("[FAILED]");
    
    $finish;
end

endmodule