data/full_repos/permissive/137045072/execution.v
1: b'%Error: data/full_repos/permissive/137045072/execution.v:21: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.v\n             data/full_repos/permissive/137045072,data/full_repos/permissive/137045072/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/137045072/execution.v:28: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] raw_inst,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`DATA_BUS] raw_inst,\n                    ^\n%Error: data/full_repos/permissive/137045072/execution.v:29: Define or directive not defined: \'`INST_BUS\'\n    input [`INST_BUS] inst,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:31: Define or directive not defined: \'`EX_SRC_BUS\'\n    input [`EX_SRC_BUS] exec_src,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:33: Define or directive not defined: \'`ALU_OP_WIDTH\'\n    input [`ALU_OP_WIDTH-1:0] alu_op,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:34: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] alu_rs,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:35: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] alu_rt,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:39: Define or directive not defined: \'`EXCEPT_MASK_BUS\'\n    input [`EXCEPT_MASK_BUS] dec_exception_mask,\n           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:44: Define or directive not defined: \'`CP0_REG_BUS\'\n    output [`CP0_REG_BUS] cp0_reg_read_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:45: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] cp0_reg_read,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:46: Define or directive not defined: \'`CP0_REG_BUS\'\n    output [`CP0_REG_BUS] cp0_reg_write_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:47: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] cp0_reg_write,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:50: Define or directive not defined: \'`CP0_REG_BUS\'\n    input [`CP0_REG_BUS] mem_cp0_write_addr,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:51: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] mem_cp0_write,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:54: Define or directive not defined: \'`CP0_REG_BUS\'\n    input [`CP0_REG_BUS] wb_cp0_write_addr,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:55: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] wb_cp0_write,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:59: Define or directive not defined: \'`DATA_BUS\'\n    output reg [`DATA_BUS] res,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:62: Define or directive not defined: \'`EXCEPT_MASK_BUS\'\n    output [`EXCEPT_MASK_BUS] exception_mask\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:64: Define or directive not defined: \'`DATA_BUS\'\n    wire [`DATA_BUS] alu_rd, move_res;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:64: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`DATA_BUS] alu_rd, move_res;\n                   ^\n%Error: data/full_repos/permissive/137045072/execution.v:65: Define or directive not defined: \'`DATA_BUS\'\n    reg [`DATA_BUS] cp0_reg_override;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`DATA_BUS] cp0_reg_override;\n                  ^\n%Error: data/full_repos/permissive/137045072/execution.v:67: Define or directive not defined: \'`EX_ALU\'\n    assign take_branch = exec_src == `EX_ALU && branch && alu_rd;\n                                     ^~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:68: Define or directive not defined: \'`EX_ALU\'\n    assign take_trap = exec_src == `EX_ALU && trap && alu_rd;\n                                   ^~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:70: Define or directive not defined: \'`EXCEPT_TRAP\'\n    assign exception_mask = take_trap ? dec_exception_mask | (1 << `EXCEPT_TRAP) : dec_exception_mask;\n                                                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:76: Define or directive not defined: \'`EX_NOP\'\n            `EX_NOP: res <= 0;\n            ^~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:77: Define or directive not defined: \'`EX_ALU\'\n            `EX_ALU: res <= alu_rd;\n            ^~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:78: Define or directive not defined: \'`EX_MOV\'\n            `EX_MOV: res <= move_res;\n            ^~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:86: Define or directive not defined: \'`INST_TEST_DONE\'\n            `INST_TEST_DONE:\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:88: Define or directive not defined: \'`INST_TEST_PASS\'\n            `INST_TEST_PASS:\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:90: Define or directive not defined: \'`INST_TEST_FAIL\'\n            `INST_TEST_FAIL:\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:100: Define or directive not defined: \'`REG_WB\'\n        if (mem_wb_cp0 == `REG_WB && mem_cp0_write_addr == cp0_reg_read_addr)\n                          ^~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:102: Define or directive not defined: \'`REG_WB\'\n        else if (wb_wb_cp0 == `REG_WB && wb_cp0_write_addr == cp0_reg_read_addr)\n                              ^~~~~~~\n%Error: data/full_repos/permissive/137045072/execution.v:127: Define or directive not defined: \'`EX_ALU\'\n        .en(exec_src == `EX_ALU),\n                        ^~~~~~~\n%Error: Exiting due to 35 error(s)\n'
module execution#(parameter DATA_WIDTH = 32)(
    input clk,
    input rst_n,
    input stall,

    input [`DATA_BUS] raw_inst,
    input [`INST_BUS] inst,

    input [`EX_SRC_BUS] exec_src,

    input [`ALU_OP_WIDTH-1:0] alu_op,
    input [`DATA_BUS] alu_rs,
    input [`DATA_BUS] alu_rt,

    input branch,
    input trap,
    input [`EXCEPT_MASK_BUS] dec_exception_mask,



    output cp0_reg_rw,
    output [`CP0_REG_BUS] cp0_reg_read_addr,
    input [`DATA_BUS] cp0_reg_read,
    output [`CP0_REG_BUS] cp0_reg_write_addr,
    output [`DATA_BUS] cp0_reg_write,

    input mem_wb_cp0,
    input [`CP0_REG_BUS] mem_cp0_write_addr,
    input [`DATA_BUS] mem_cp0_write,

    input wb_wb_cp0,
    input [`CP0_REG_BUS] wb_cp0_write_addr,
    input [`DATA_BUS] wb_cp0_write,
    


    output reg [`DATA_BUS] res,
    output take_branch,
    output take_trap,
    output [`EXCEPT_MASK_BUS] exception_mask
);
    wire [`DATA_BUS] alu_rd, move_res;
    reg [`DATA_BUS] cp0_reg_override;

    assign take_branch = exec_src == `EX_ALU && branch && alu_rd;
    assign take_trap = exec_src == `EX_ALU && trap && alu_rd;
    
    assign exception_mask = take_trap ? dec_exception_mask | (1 << `EXCEPT_TRAP) : dec_exception_mask;


    always @*
    begin
        case (exec_src)
            `EX_NOP: res <= 0;
            `EX_ALU: res <= alu_rd;
            `EX_MOV: res <= move_res;
            default: res <= 0;
        endcase
    end
    
    always @*
    begin
        case (inst)
            `INST_TEST_DONE:
                $display("Test done");
            `INST_TEST_PASS:
                $display("Test pass");
            `INST_TEST_FAIL:
                $display("Test fail");
        endcase    
    end



    always @*
    begin
        cp0_reg_override <= cp0_reg_read;
        if (mem_wb_cp0 == `REG_WB && mem_cp0_write_addr == cp0_reg_read_addr)
            cp0_reg_override <= mem_cp0_write;
        else if (wb_wb_cp0 == `REG_WB && wb_cp0_write_addr == cp0_reg_read_addr)
            cp0_reg_override <= wb_cp0_write;
    end
    
    move #(.DATA_WIDTH(DATA_WIDTH)) mov(
        .clk(clk),
        .rst_n(rst_n),

        .raw_inst(raw_inst),
        .inst(inst),
        .exec_src(exec_src),
        
        .cp0_reg_rw(cp0_reg_rw),
        .cp0_reg_read_addr(cp0_reg_read_addr),
        .cp0_reg_read(cp0_reg_override),
        .cp0_reg_write_addr(cp0_reg_write_addr),
        .cp0_reg_write(cp0_reg_write),

        .data(alu_rs),

        .res(move_res)
    );
    
    arithmetic_logic_unit #(.DATA_WIDTH(DATA_WIDTH)) alu(
        .stall(stall),
        .en(exec_src == `EX_ALU),
        .op(alu_op),
        .rs(alu_rs),
        .rt(alu_rt),
        .rd(alu_rd)
    );
endmodule
module execution#(parameter DATA_WIDTH = 32)(
    input clk,
    input rst_n,
    input stall,

    input [`DATA_BUS] raw_inst,
    input [`INST_BUS] inst,

    input [`EX_SRC_BUS] exec_src,

    input [`ALU_OP_WIDTH-1:0] alu_op,
    input [`DATA_BUS] alu_rs,
    input [`DATA_BUS] alu_rt,

    input branch,
    input trap,
    input [`EXCEPT_MASK_BUS] dec_exception_mask,



    output cp0_reg_rw,
    output [`CP0_REG_BUS] cp0_reg_read_addr,
    input [`DATA_BUS] cp0_reg_read,
    output [`CP0_REG_BUS] cp0_reg_write_addr,
    output [`DATA_BUS] cp0_reg_write,

    input mem_wb_cp0,
    input [`CP0_REG_BUS] mem_cp0_write_addr,
    input [`DATA_BUS] mem_cp0_write,

    input wb_wb_cp0,
    input [`CP0_REG_BUS] wb_cp0_write_addr,
    input [`DATA_BUS] wb_cp0_write,
    


    output reg [`DATA_BUS] res,
    output take_branch,
    output take_trap,
    output [`EXCEPT_MASK_BUS] exception_mask
);

    wire [`DATA_BUS] alu_rd, move_res;
    reg [`DATA_BUS] cp0_reg_override;

    assign take_branch = exec_src == `EX_ALU && branch && alu_rd;
    assign take_trap = exec_src == `EX_ALU && trap && alu_rd;
    
    assign exception_mask = take_trap ? dec_exception_mask | (1 << `EXCEPT_TRAP) : dec_exception_mask;


    always @*
    begin
        case (exec_src)
            `EX_NOP: res <= 0;
            `EX_ALU: res <= alu_rd;
            `EX_MOV: res <= move_res;
            default: res <= 0;
        endcase
    end
    
    always @*
    begin
        case (inst)
            `INST_TEST_DONE:
                $display("Test done");
            `INST_TEST_PASS:
                $display("Test pass");
            `INST_TEST_FAIL:
                $display("Test fail");
        endcase    
    end



    always @*
    begin
        cp0_reg_override <= cp0_reg_read;
        if (mem_wb_cp0 == `REG_WB && mem_cp0_write_addr == cp0_reg_read_addr)
            cp0_reg_override <= mem_cp0_write;
        else if (wb_wb_cp0 == `REG_WB && wb_cp0_write_addr == cp0_reg_read_addr)
            cp0_reg_override <= wb_cp0_write;
    end
    
    move #(.DATA_WIDTH(DATA_WIDTH)) mov(
        .clk(clk),
        .rst_n(rst_n),

        .raw_inst(raw_inst),
        .inst(inst),
        .exec_src(exec_src),
        
        .cp0_reg_rw(cp0_reg_rw),
        .cp0_reg_read_addr(cp0_reg_read_addr),
        .cp0_reg_read(cp0_reg_override),
        .cp0_reg_write_addr(cp0_reg_write_addr),
        .cp0_reg_write(cp0_reg_write),

        .data(alu_rs),

        .res(move_res)
    );
    
    arithmetic_logic_unit #(.DATA_WIDTH(DATA_WIDTH)) alu(
        .stall(stall),
        .en(exec_src == `EX_ALU),
        .op(alu_op),
        .rs(alu_rs),
        .rt(alu_rt),
        .rd(alu_rd)
    );
endmodule