data/full_repos/permissive/16591284/fifo_design_collection/test/tb_fifo.v
None: at end of input
1: b'%Error: data/full_repos/permissive/16591284/fifo_design_collection/test/tb_fifo.v:7: Cannot find include file: fifo.v\n`include "fifo.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/16591284/fifo_design_collection/test,data/full_repos/permissive/16591284/fifo.v\n             data/full_repos/permissive/16591284/fifo_design_collection/test,data/full_repos/permissive/16591284/fifo.v.v\n             data/full_repos/permissive/16591284/fifo_design_collection/test,data/full_repos/permissive/16591284/fifo.v.sv\n             fifo.v\n             fifo.v.v\n             fifo.v.sv\n             obj_dir/fifo.v\n             obj_dir/fifo.v.v\n             obj_dir/fifo.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/16591284/fifo_design_collection/test/tb_fifo.v:14: Unsupported: Ignoring delay on this delayed statement.\n  reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end\n                                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/16591284/fifo_design_collection/test/tb_fifo.v:15: Unsupported: Ignoring delay on this delayed statement.\n  reg RST; initial begin RST=1; #400 RST=0; end\n                                ^\n%Error: data/full_repos/permissive/16591284/fifo_design_collection/test/tb_fifo.v:70: Unsupported: $fflush of all handles does not map to C++.\n      $fflush();\n      ^~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module tb_FIFO();
  reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end
  reg RST; initial begin RST=1; #400 RST=0; end

  wire                   fifo_enq;
  wire                   fifo_deq;
  reg  [`FIFO_WIDTH-1:0] fifo_din;
  wire [`FIFO_WIDTH-1:0] fifo_dot;
  wire                   fifo_emp;
  wire                   fifo_ful;
  wire [`FIFO_SIZE:0]    fifo_cnt;

  assign fifo_enq = ~fifo_ful;
  assign fifo_deq = ~fifo_emp;

  DFIFO #(`FIFO_SIZE, `FIFO_WIDTH)

  fifo(CLK, RST, fifo_enq, fifo_deq, fifo_din, 
       fifo_dot, fifo_emp, fifo_ful, fifo_cnt);

  always @(posedge CLK) begin
    if      (RST)      fifo_din <= 1;
    else if (fifo_enq) fifo_din <= fifo_din + 1;
  end


  reg [`FIFO_WIDTH-1:0] chk_data;
  always @(posedge CLK) begin
    if (RST) begin
      chk_data <= 1;
    end else begin
      if (fifo_deq) begin
        chk_data <= chk_data + 1;
        if (fifo_dot != chk_data) begin
          $write("\nError!\n");
          $write("%d %d\n", fifo_dot, chk_data);
          $finish();
        end
      end
    end
  end
  

  reg [31:0] cycle;
  always @(posedge CLK) begin
    if (RST) begin
      cycle <= 0;
    end else begin
      cycle <= cycle + 1;
      if (cycle >= 100) $finish();
    end
  end

  always @(posedge CLK) begin
    if (fifo_deq) begin
      $write("%d | %d", cycle, fifo_dot);
      $write("\n");
      $fflush();
    end
  end
  
endmodule
module tb_FIFO();

  reg CLK; initial begin CLK=0; forever #50 CLK=~CLK; end
  reg RST; initial begin RST=1; #400 RST=0; end

  wire                   fifo_enq;
  wire                   fifo_deq;
  reg  [`FIFO_WIDTH-1:0] fifo_din;
  wire [`FIFO_WIDTH-1:0] fifo_dot;
  wire                   fifo_emp;
  wire                   fifo_ful;
  wire [`FIFO_SIZE:0]    fifo_cnt;

  assign fifo_enq = ~fifo_ful;
  assign fifo_deq = ~fifo_emp;

  DFIFO #(`FIFO_SIZE, `FIFO_WIDTH)

  fifo(CLK, RST, fifo_enq, fifo_deq, fifo_din, 
       fifo_dot, fifo_emp, fifo_ful, fifo_cnt);

  always @(posedge CLK) begin
    if      (RST)      fifo_din <= 1;
    else if (fifo_enq) fifo_din <= fifo_din + 1;
  end


  reg [`FIFO_WIDTH-1:0] chk_data;
  always @(posedge CLK) begin
    if (RST) begin
      chk_data <= 1;
    end else begin
      if (fifo_deq) begin
        chk_data <= chk_data + 1;
        if (fifo_dot != chk_data) begin
          $write("\nError!\n");
          $write("%d %d\n", fifo_dot, chk_data);
          $finish();
        end
      end
    end
  end
  

  reg [31:0] cycle;
  always @(posedge CLK) begin
    if (RST) begin
      cycle <= 0;
    end else begin
      cycle <= cycle + 1;
      if (cycle >= 100) $finish();
    end
  end

  always @(posedge CLK) begin
    if (fifo_deq) begin
      $write("%d | %d", cycle, fifo_dot);
      $write("\n");
      $fflush();
    end
  end
  
endmodule