data/full_repos/permissive/189714993/Stoper.srcs/sources_1/new/Stoper/ms_clock.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/189714993/Stoper.srcs/sources_1/new/Stoper/ms_clock.v:6: Little bit endian vector: MSB < LSB of bit range: 0:17\n reg [0:17] count;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/189714993/Stoper.srcs/sources_1/new/Stoper/ms_clock.v:19: Operator EQ expects 32 or 19 bits on the LHS, but LHS\'s VARREF \'count\' generates 18 bits.\n                                                                                                   : ... In instance ms_clock\n   if (count == speed_up)\n             ^~\n%Error: Exiting due to 2 warning(s)\n'
module ms_clock(clock, ms_clock);

	input clock;
	output ms_clock;
	reg ms_clock;
	reg [0:17] count;
	
	parameter speed_up = 500000;
	

	always @ (posedge clock)
		begin
		  if (count[0:0] === 1'bx)
		      begin
		          count = 0;
		          ms_clock = 1'b0;
		      end 
			count <= count + 1;
			if (count == speed_up)
				begin
					ms_clock <= ~ms_clock;
					count <= 0;
				end
		end
endmodule
module ms_clock(clock, ms_clock);


	input clock;
	output ms_clock;
	reg ms_clock;
	reg [0:17] count;
	
	parameter speed_up = 500000;
	

	always @ (posedge clock)
		begin
		  if (count[0:0] === 1'bx)
		      begin
		          count = 0;
		          ms_clock = 1'b0;
		      end 
			count <= count + 1;
			if (count == speed_up)
				begin
					ms_clock <= ~ms_clock;
					count <= 0;
				end
		end
endmodule