data/full_repos/permissive/203526788/GoBoard/TX_RX/top.v
 line:361: before: ")"
1: b'%Error: data/full_repos/permissive/203526788/GoBoard/TX_RX/top.v:3: Cannot find include file: Display.v\n`include "Display.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/203526788/GoBoard/TX_RX,data/full_repos/permissive/203526788/Display.v\n             data/full_repos/permissive/203526788/GoBoard/TX_RX,data/full_repos/permissive/203526788/Display.v.v\n             data/full_repos/permissive/203526788/GoBoard/TX_RX,data/full_repos/permissive/203526788/Display.v.sv\n             Display.v\n             Display.v.v\n             Display.v.sv\n             obj_dir/Display.v\n             obj_dir/Display.v.v\n             obj_dir/Display.v.sv\n%Error: data/full_repos/permissive/203526788/GoBoard/TX_RX/top.v:4: Cannot find include file: UART_TX.v\n`include "UART_TX.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/203526788/GoBoard/TX_RX/top.v:5: Cannot find include file: UART_RX.v\n`include "UART_RX.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/203526788/GoBoard/TX_RX/top.v:15: syntax error, unexpected \')\', expecting \'[\'\n);\n^\n%Error: data/full_repos/permissive/203526788/GoBoard/TX_RX/top.v:27: syntax error, unexpected IDENTIFIER\n  UART_TX #(.CLKS_PER_BIT(217)) UART_TX_Inst\n  ^~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module top(
  	  input CLK,
	    output [6:0] SEG1,
	    output [6:0] SEG2,
	    output [3:0] LED, 
		  output wire UARTTX,
		  input wire UARTRX,
);

	parameter ClkFrequency = 25000000;
	parameter Baud = 9600;

  wire active;
  wire done;
  reg [7:0] data = 7'd99;
  wire [7:0] dataRx;
  reg enable = 1'b0;
  wire rxDiv;

  UART_TX #(.CLKS_PER_BIT(217)) UART_TX_Inst
  (
     .i_Rst_L(enable),
     .i_Clock(CLK),
     .i_TX_DV(1'b1),
     .i_TX_Byte(data),
     .o_TX_Active(active),
     .o_TX_Serial(UARTTX),
     .o_TX_Done(done)
  );

  UART_RX #(.CLKS_PER_BIT(217)) UART_RX_Inst
  (
   .i_Rst_L(1'b1),
   .i_Clock(CLK),
   .i_RX_Serial(UARTRX),
   .o_RX_DV(rxDiv),
   .o_RX_Byte(dataRx)
  );

  always @(posedge CLK)
  begin
    if (done)
      enable <= 1'b0;
    
    if (rxDiv)
    begin
      data <= dataRx;
      enable <= 1'b1;
    end

  end
  
  
  assign LED = 4'b0;

  DisplayNumber ns (CLK, SEG1, SEG2, data);

endmodule
module top(
  	  input CLK,
	    output [6:0] SEG1,
	    output [6:0] SEG2,
	    output [3:0] LED, 
		  output wire UARTTX,
		  input wire UARTRX,
);


	parameter ClkFrequency = 25000000;
	parameter Baud = 9600;

  wire active;
  wire done;
  reg [7:0] data = 7'd99;
  wire [7:0] dataRx;
  reg enable = 1'b0;
  wire rxDiv;

  UART_TX #(.CLKS_PER_BIT(217)) UART_TX_Inst
  (
     .i_Rst_L(enable),
     .i_Clock(CLK),
     .i_TX_DV(1'b1),
     .i_TX_Byte(data),
     .o_TX_Active(active),
     .o_TX_Serial(UARTTX),
     .o_TX_Done(done)
  );

  UART_RX #(.CLKS_PER_BIT(217)) UART_RX_Inst
  (
   .i_Rst_L(1'b1),
   .i_Clock(CLK),
   .i_RX_Serial(UARTRX),
   .o_RX_DV(rxDiv),
   .o_RX_Byte(dataRx)
  );

  always @(posedge CLK)
  begin
    if (done)
      enable <= 1'b0;
    
    if (rxDiv)
    begin
      data <= dataRx;
      enable <= 1'b1;
    end

  end
  
  
  assign LED = 4'b0;

  DisplayNumber ns (CLK, SEG1, SEG2, data);

endmodule