data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v
None: at end of input
1: b'%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:21: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128566293/TBench/verilog,data/full_repos/permissive/128566293/timescale.v\n             data/full_repos/permissive/128566293/TBench/verilog,data/full_repos/permissive/128566293/timescale.v.v\n             data/full_repos/permissive/128566293/TBench/verilog,data/full_repos/permissive/128566293/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:91: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:92: syntax error, unexpected \'@\'\n    @ (negedge rst_tb);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #((0.8 * 10));\n    ^\n%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:102: syntax error, unexpected \'@\'\n        @ (posedge clk_tb);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #((0.8 * 10));\n        ^\n%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:112: syntax error, unexpected \'@\'\n    @ (posedge clk_tb);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:113: Unsupported: Ignoring delay on this delayed statement.\n    #((0.8 * 10));\n    ^\n%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:120: syntax error, unexpected \'@\'\n    @ (posedge clk_tb);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:121: Unsupported: Ignoring delay on this delayed statement.\n    #((0.8 * 10));\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:136: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:148: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile(`DUMPFILE);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:148: Define or directive not defined: \'`DUMPFILE\'\n    $dumpfile(`DUMPFILE);\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:149: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/128566293/TBench/verilog/tc_counter.v:151: Unsupported: Ignoring delay on this delayed statement.\n    #(10_000);\n    ^\n%Error: Exiting due to 8 error(s), 8 warning(s)\n'
module tc_counter (

);



    reg                 clk_tb = ~0;

always @ (clk_tb)
begin
    clk_tb <= #(`CLK_PERIOD/2) ~clk_tb;
end

    reg                 rst_tb = 0;

initial
begin
    #1;

    rst_tb <= ~0;
    rst_tb <= #(`RST_PERIOD) 0;
end



    localparam          c_width =5;

    reg                 r_enable = 0;
    wire [c_width-1:0]  w_result;



VfD_counter dut (
    .i_enable           (r_enable),
    .o_result           (w_result),

    .clk                (clk_tb),
    .rst                (rst_tb)
);



    reg [c_width-1:0]   r_expectation = 0;

always @ (posedge clk_tb)
begin
    if (r_enable)
        r_expectation = r_expectation +1;
end



    integer             failed = 0;

task t_initialize;
begin
    #1;
    @ (negedge rst_tb);
    @ (posedge clk_tb);
    #(`STROBE);
end
endtask

task t_run;
    input integer reps;
begin
    repeat(reps) begin
        @ (posedge clk_tb);
        #(`STROBE);
        failed = (r_expectation == w_result)? failed: failed+1;
    end
end
endtask

task t_enable;
begin
    r_enable <= ~0;
    @ (posedge clk_tb);
    #(`STROBE);
end
endtask

task t_disable;
begin
    r_enable <= 0;
    @ (posedge clk_tb);
    #(`STROBE);
end
endtask

initial
begin
    t_initialize;


    t_enable;
    t_run(15);


    t_disable;

    #1;
    if (failed)
        $display("\t%m: *failed* %0d times", failed);
    else
        $display("\t%m: *well done*");
    $finish;
end



initial
begin
    $dumpfile(`DUMPFILE);
    $dumpvars;

    #(`TIMELIMIT);
    $display("\t%m: *time limit (%t) reached*", $time);
    $finish;
end

endmodule
module tc_counter (

);




    reg                 clk_tb = ~0;

always @ (clk_tb)
begin
    clk_tb <= #(`CLK_PERIOD/2) ~clk_tb;
end

    reg                 rst_tb = 0;

initial
begin
    #1;

    rst_tb <= ~0;
    rst_tb <= #(`RST_PERIOD) 0;
end



    localparam          c_width =5;

    reg                 r_enable = 0;
    wire [c_width-1:0]  w_result;



VfD_counter dut (
    .i_enable           (r_enable),
    .o_result           (w_result),

    .clk                (clk_tb),
    .rst                (rst_tb)
);



    reg [c_width-1:0]   r_expectation = 0;

always @ (posedge clk_tb)
begin
    if (r_enable)
        r_expectation = r_expectation +1;
end



    integer             failed = 0;

task t_initialize;
begin
    #1;
    @ (negedge rst_tb);
    @ (posedge clk_tb);
    #(`STROBE);
end
endtask

task t_run;
    input integer reps;
begin
    repeat(reps) begin
        @ (posedge clk_tb);
        #(`STROBE);
        failed = (r_expectation == w_result)? failed: failed+1;
    end
end
endtask

task t_enable;
begin
    r_enable <= ~0;
    @ (posedge clk_tb);
    #(`STROBE);
end
endtask

task t_disable;
begin
    r_enable <= 0;
    @ (posedge clk_tb);
    #(`STROBE);
end
endtask

initial
begin
    t_initialize;


    t_enable;
    t_run(15);


    t_disable;

    #1;
    if (failed)
        $display("\t%m: *failed* %0d times", failed);
    else
        $display("\t%m: *well done*");
    $finish;
end



initial
begin
    $dumpfile(`DUMPFILE);
    $dumpvars;

    #(`TIMELIMIT);
    $display("\t%m: *time limit (%t) reached*", $time);
    $finish;
end

endmodule