data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/erase_keys.v
1: b"%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/erase_keys.v:192: Cannot find file containing module: 'erase_ram'\n    erase_ram #(\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src,data/full_repos/permissive/13196823/erase_ram\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src,data/full_repos/permissive/13196823/erase_ram.v\n             data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src,data/full_repos/permissive/13196823/erase_ram.sv\n             erase_ram\n             erase_ram.v\n             erase_ram.sv\n             obj_dir/erase_ram\n             obj_dir/erase_ram.v\n             obj_dir/erase_ram.sv\n%Error: data/full_repos/permissive/13196823/fpga/DE4_Ethernet_0/src/erase_keys.v:205: Cannot find file containing module: 'decoder'\n    decoder #(\n    ^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module erase_keys (
                reset,
                wr_clk,
                wr_en,
                wr_key,
                wr_index,
                wr_erase_n,
                key_addr,
                index_reg,
                cam_full,
                multi_index
                );
                


`define     RANDOM_INTERNAL




parameter   FAMILY      = "Stratix IV";


parameter   S_KEY       = 8;


parameter   ENTRIES     = 416;              
localparam  INDEX       = log2(ENTRIES);
localparam  ADJ_ENTRY   = 2**INDEX;

input                   reset;
input                   wr_clk, wr_en;
input   [S_KEY-1:0]     wr_key;
input   [INDEX-1:0]     wr_index;
input                   wr_erase_n;

output  [S_KEY-1:0]     key_addr;
output  [ADJ_ENTRY-1:0] index_reg;
output                  cam_full, multi_index;

reg                     rst_reg1, rst_reg2;


always @(posedge wr_clk or posedge reset)
begin
    if (reset)
    begin
        rst_reg2    <= 1'b1;
        rst_reg1    <= 1'b1;
    end
    else
    begin
        rst_reg2    <= rst_reg1;
        rst_reg1    <= 1'b0;
    end
end

wire  wr_rst    = rst_reg2;


`ifdef RANDOM_INTERNAL

    reg     [ADJ_ENTRY-1:0] index_reg;
    reg                     multi_index;
    reg     [S_KEY-1:0]     lat_erase_key;
    reg                     reg_wr_erase_n;
    reg     [S_KEY-1:0]     reg_wr_key;

    wire    [S_KEY-1:0]     erase_key;
    wire    [ADJ_ENTRY-1:0] wr_index_decode;

    wire    [S_KEY-1:0]     key_addr = reg_wr_erase_n ? reg_wr_key : lat_erase_key;
    wire                    cam_full = &index_reg;
    
    always @(posedge wr_clk or posedge wr_rst)
    begin
        if (wr_rst)
        begin: reset_keys
            index_reg       <= {ADJ_ENTRY{1'b0}};
            multi_index     <= 1'b0;
            reg_wr_erase_n  <= 1'b0;
            reg_wr_key      <= {S_KEY{1'b0}};
        end
        else if (wr_en && wr_erase_n)
        begin: write_key
            index_reg       <= index_reg | wr_index_decode;
            reg_wr_erase_n  <= wr_erase_n;
            reg_wr_key      <= wr_key;
            if ((index_reg & wr_index_decode) != 0)
                multi_index <= 1'b1;
            else
                multi_index <= 1'b0;
        end
        else if (wr_en && !wr_erase_n)
        begin: remove_key
            index_reg   <= index_reg & ~wr_index_decode;
            multi_index <= 1'b0;
            reg_wr_erase_n  <= wr_erase_n;
            reg_wr_key      <= wr_key;
        end
        else
        begin
            index_reg   <= index_reg;
            multi_index <= 1'b0;
            reg_wr_erase_n  <= reg_wr_erase_n;
            reg_wr_key      <= reg_wr_key;
        end
    end
    

    always @(erase_key or wr_clk)
    begin
        if (wr_clk)
        begin
            lat_erase_key <= erase_key;
        end
    end
    





    erase_ram #(
        .FAMILY     ( FAMILY ),
        .S_KEY      ( S_KEY ),
        .ENTRIES    ( ADJ_ENTRY )
        ) erase_ram_inst (
        .address    ( wr_index ),
        .clock      ( wr_clk ),
        .data       ( wr_key ),
        .wren       ( wr_en ),
        .q          ( erase_key )
        );
        

    decoder #(
        .WIDTH      ( ADJ_ENTRY )
        ) decoder_inst (
        .encode_in  ( wr_index ),
        .data_out   ( wr_index_decode )
        );

`else   `ifdef FIFO_INTERAL



        `else   `ifdef FIFO_AUTO


    
                `else


                    wire    [ADJ_ENTRY-1:0] index_reg = ADJ_ENTRY'b0;
                    wire                    multi_index = 0;
                    wire                    cam_full = 0;


                    wire    [S_KEY-1:0]     key_addr = wr_key;
                    
                `endif
        `endif
`endif

function integer log2;
input [31:0] bits;
integer k;
begin
    log2 = 1;
    for (k=0; 2**k < bits; k=k+1)
        log2 = k + 1;
end
endfunction

endmodule
module erase_keys (
                reset,
                wr_clk,
                wr_en,
                wr_key,
                wr_index,
                wr_erase_n,
                key_addr,
                index_reg,
                cam_full,
                multi_index
                );

                


`define     RANDOM_INTERNAL




parameter   FAMILY      = "Stratix IV";


parameter   S_KEY       = 8;


parameter   ENTRIES     = 416;              
localparam  INDEX       = log2(ENTRIES);
localparam  ADJ_ENTRY   = 2**INDEX;

input                   reset;
input                   wr_clk, wr_en;
input   [S_KEY-1:0]     wr_key;
input   [INDEX-1:0]     wr_index;
input                   wr_erase_n;

output  [S_KEY-1:0]     key_addr;
output  [ADJ_ENTRY-1:0] index_reg;
output                  cam_full, multi_index;

reg                     rst_reg1, rst_reg2;


always @(posedge wr_clk or posedge reset)
begin
    if (reset)
    begin
        rst_reg2    <= 1'b1;
        rst_reg1    <= 1'b1;
    end
    else
    begin
        rst_reg2    <= rst_reg1;
        rst_reg1    <= 1'b0;
    end
end

wire  wr_rst    = rst_reg2;


`ifdef RANDOM_INTERNAL

    reg     [ADJ_ENTRY-1:0] index_reg;
    reg                     multi_index;
    reg     [S_KEY-1:0]     lat_erase_key;
    reg                     reg_wr_erase_n;
    reg     [S_KEY-1:0]     reg_wr_key;

    wire    [S_KEY-1:0]     erase_key;
    wire    [ADJ_ENTRY-1:0] wr_index_decode;

    wire    [S_KEY-1:0]     key_addr = reg_wr_erase_n ? reg_wr_key : lat_erase_key;
    wire                    cam_full = &index_reg;
    
    always @(posedge wr_clk or posedge wr_rst)
    begin
        if (wr_rst)
        begin: reset_keys
            index_reg       <= {ADJ_ENTRY{1'b0}};
            multi_index     <= 1'b0;
            reg_wr_erase_n  <= 1'b0;
            reg_wr_key      <= {S_KEY{1'b0}};
        end
        else if (wr_en && wr_erase_n)
        begin: write_key
            index_reg       <= index_reg | wr_index_decode;
            reg_wr_erase_n  <= wr_erase_n;
            reg_wr_key      <= wr_key;
            if ((index_reg & wr_index_decode) != 0)
                multi_index <= 1'b1;
            else
                multi_index <= 1'b0;
        end
        else if (wr_en && !wr_erase_n)
        begin: remove_key
            index_reg   <= index_reg & ~wr_index_decode;
            multi_index <= 1'b0;
            reg_wr_erase_n  <= wr_erase_n;
            reg_wr_key      <= wr_key;
        end
        else
        begin
            index_reg   <= index_reg;
            multi_index <= 1'b0;
            reg_wr_erase_n  <= reg_wr_erase_n;
            reg_wr_key      <= reg_wr_key;
        end
    end
    

    always @(erase_key or wr_clk)
    begin
        if (wr_clk)
        begin
            lat_erase_key <= erase_key;
        end
    end
    





    erase_ram #(
        .FAMILY     ( FAMILY ),
        .S_KEY      ( S_KEY ),
        .ENTRIES    ( ADJ_ENTRY )
        ) erase_ram_inst (
        .address    ( wr_index ),
        .clock      ( wr_clk ),
        .data       ( wr_key ),
        .wren       ( wr_en ),
        .q          ( erase_key )
        );
        

    decoder #(
        .WIDTH      ( ADJ_ENTRY )
        ) decoder_inst (
        .encode_in  ( wr_index ),
        .data_out   ( wr_index_decode )
        );

`else   `ifdef FIFO_INTERAL



        `else   `ifdef FIFO_AUTO


    
                `else


                    wire    [ADJ_ENTRY-1:0] index_reg = ADJ_ENTRY'b0;
                    wire                    multi_index = 0;
                    wire                    cam_full = 0;


                    wire    [S_KEY-1:0]     key_addr = wr_key;
                    
                `endif
        `endif
`endif

function integer log2;
input [31:0] bits;
integer k;
begin
    log2 = 1;
    for (k=0; 2**k < bits; k=k+1)
        log2 = k + 1;
end
endfunction

endmodule