data/full_repos/permissive/160991228/src/hdl/GACTX/mux_1OfN.v
1: b'%Warning-WIDTH: data/full_repos/permissive/160991228/src/hdl/GACTX/mux_1OfN.v:39: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'select\' generates 2 bits.\n                                                                                : ... In instance mux_1OfN\n    data_out <= data_in[(select+1)*DATA_WIDTH-1-:DATA_WIDTH];\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mux_1OfN #(
    parameter NUM_PORTS_WIDTH = 2,
    parameter DATA_WIDTH = 32

)(
    input clk,
    input [NUM_PORTS_WIDTH-1:0] select,
    input [(2 ** NUM_PORTS_WIDTH)*DATA_WIDTH-1:0] data_in,
    output reg [DATA_WIDTH-1:0] data_out
);

localparam NUM_PORTS = 2**NUM_PORTS_WIDTH;

always @(posedge clk) begin
    data_out <= data_in[(select+1)*DATA_WIDTH-1-:DATA_WIDTH];
end

endmodule
module mux_1OfN #(
    parameter NUM_PORTS_WIDTH = 2,
    parameter DATA_WIDTH = 32

)(
    input clk,
    input [NUM_PORTS_WIDTH-1:0] select,
    input [(2 ** NUM_PORTS_WIDTH)*DATA_WIDTH-1:0] data_in,
    output reg [DATA_WIDTH-1:0] data_out
);


localparam NUM_PORTS = 2**NUM_PORTS_WIDTH;

always @(posedge clk) begin
    data_out <= data_in[(select+1)*DATA_WIDTH-1-:DATA_WIDTH];
end

endmodule