data/full_repos/permissive/140464302/lbp_all_ddr_vga/sd_ddr_vga/remote_sources/_/rtl/sd_top.v
'utf-8' codec can't decode byte 0xd0 in position 1550: invalid continuation byte
1: b"%Error: data/full_repos/permissive/140464302/lbp_all_ddr_vga/sd_ddr_vga/remote_sources/_/rtl/sd_top.v:27: Duplicate declaration of signal: 'init_o'\n                                                                                                        : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire init_o;\n     ^~~~~~\n        data/full_repos/permissive/140464302/lbp_all_ddr_vga/sd_ddr_vga/remote_sources/_/rtl/sd_top.v:16: ... Location of original declaration\n     output             init_o,\n                        ^~~~~~\n%Error: Exiting due to 1 error(s)\n"
module sd_top(
					input              sd_rstn,

					input              SD_clk,					
					output  reg        SD_cs,
					output  reg        SD_datain,
					input              SD_dataout,
					
	
					output             myvalid_o,
					output   [7:0]     mydata_o,
					output             init_o,
               output             pic_read_done					
   
					
    );


wire [3:0] state_initial;
wire [3:0] state_read;

wire [7:0]rx_o;
wire init_o;
wire read_o;

wire SD_cs_i;
wire SD_cs_r;
wire SD_datain_i;
wire SD_datain_r;




sd_initial	sd_initial_inst(

			.rst_n         (sd_rstn),				 
			.SD_clk        (SD_clk),
			.SD_cs         (SD_cs_i),
			.SD_datain     (SD_datain_i),
			.SD_dataout    (SD_dataout),
			.rx            (),
			.init_o        (init_o),
			.state         (state_initial)
);



sd_read	sd_read_inst(   
			.SD_clk        (SD_clk),
			.SD_cs         (SD_cs_r),
			.SD_datain     (SD_datain_r),
			.SD_dataout    (SD_dataout),
				
			.mydata_o      (mydata_o),
			.myvalid_o     (myvalid_o),
		
			
			.data_come     (),
			
			.init          (init_o),
					
			.mystate       (state_read),
			
			.read_o        (pic_read_done)
						
						
    );

						



always @(*)
begin
	if(!init_o)	begin
	      SD_cs<=SD_cs_i;
			SD_datain<=SD_datain_i;
	end
	else begin
	      SD_cs<=SD_cs_r;
			SD_datain<=SD_datain_r;
	end
end

	 
endmodule
module sd_top(
					input              sd_rstn,

					input              SD_clk,					
					output  reg        SD_cs,
					output  reg        SD_datain,
					input              SD_dataout,
					
	
					output             myvalid_o,
					output   [7:0]     mydata_o,
					output             init_o,
               output             pic_read_done					
   
					
    );



wire [3:0] state_initial;
wire [3:0] state_read;

wire [7:0]rx_o;
wire init_o;
wire read_o;

wire SD_cs_i;
wire SD_cs_r;
wire SD_datain_i;
wire SD_datain_r;




sd_initial	sd_initial_inst(

			.rst_n         (sd_rstn),				 
			.SD_clk        (SD_clk),
			.SD_cs         (SD_cs_i),
			.SD_datain     (SD_datain_i),
			.SD_dataout    (SD_dataout),
			.rx            (),
			.init_o        (init_o),
			.state         (state_initial)
);



sd_read	sd_read_inst(   
			.SD_clk        (SD_clk),
			.SD_cs         (SD_cs_r),
			.SD_datain     (SD_datain_r),
			.SD_dataout    (SD_dataout),
				
			.mydata_o      (mydata_o),
			.myvalid_o     (myvalid_o),
		
			
			.data_come     (),
			
			.init          (init_o),
					
			.mystate       (state_read),
			
			.read_o        (pic_read_done)
						
						
    );

						



always @(*)
begin
	if(!init_o)	begin
	      SD_cs<=SD_cs_i;
			SD_datain<=SD_datain_i;
	end
	else begin
	      SD_cs<=SD_cs_r;
			SD_datain<=SD_datain_r;
	end
end

	 
endmodule