data/full_repos/permissive/136660017/tut-03-dff.v
1: b'%Error: data/full_repos/permissive/136660017/tut-03-dff.v:36: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,bench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/136660017/tut-03-dff.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/136660017/tut-03-dff.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/136660017/tut-03-dff.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/136660017/tut-03-dff.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/136660017/tut-03-dff.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/136660017/tut-03-dff.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dff2(output q, input d, input clk);
  reg q_reg;
  assign q = q_reg;
  always@(posedge clk)
  begin
    q_reg=d;
  end
endmodule
module dff2(output q, input d, input clk);

  reg q_reg;
  assign q = q_reg;
  always@(posedge clk)
  begin
    q_reg=d;
  end
endmodule