data/full_repos/permissive/201488448/2_circuits/2_sequential/xx_srlatch.v
data/verilator_xmls/7a156f5a-0ec0-424b-a7b1-7d1c990bba3a.xml
module top_module (
	input set,
	input reset,
	output reg q
);






	assign q = set ? 1'b1 : (reset ? 1'b0 : q);
	



	



	
endmodule
module top_module (
	input set,
	input reset,
	output reg q
);







	assign q = set ? 1'b1 : (reset ? 1'b0 : q);
	



	



	
endmodule