data/full_repos/permissive/466009483/HDL/PROJECT_FILES/decoder.v
data/verilator_xmls/8754289b-ed7a-4fc0-a34a-bc36ebb7c81a.xml
module decoder#(parameter DEC_WIDTH = 2)
                (x_in  , out_dec);
input [DEC_WIDTH-1:0] x_in ;
output reg [2:0] out_dec ;


always @(*)
   begin
     case(x_in)
     0: out_dec = 3'b110;
     1: out_dec = 3'b101;
     2: out_dec = 3'b011;
     3: out_dec = 3'b111;
     default : out_dec = 3'bzzz ;
     endcase
     end
endmodule
module decoder#(parameter DEC_WIDTH = 2)
                (x_in  , out_dec);

input [DEC_WIDTH-1:0] x_in ;
output reg [2:0] out_dec ;


always @(*)
   begin
     case(x_in)
     0: out_dec = 3'b110;
     1: out_dec = 3'b101;
     2: out_dec = 3'b011;
     3: out_dec = 3'b111;
     default : out_dec = 3'bzzz ;
     endcase
     end
endmodule