data/full_repos/permissive/217937330/simu_coder_test.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/217937330/simu_coder_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/217937330/simu_coder_test.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #100 rst=~rst;\n        ^\n%Error: data/full_repos/permissive/217937330/simu_coder_test.v:41: Cannot find file containing module: \'bch_encoder\'\n    bch_encoder out(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/217937330,data/full_repos/permissive/217937330/bch_encoder\n             data/full_repos/permissive/217937330,data/full_repos/permissive/217937330/bch_encoder.v\n             data/full_repos/permissive/217937330,data/full_repos/permissive/217937330/bch_encoder.sv\n             bch_encoder\n             bch_encoder.v\n             bch_encoder.sv\n             obj_dir/bch_encoder\n             obj_dir/bch_encoder.v\n             obj_dir/bch_encoder.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simu_coder_test(


    );
    parameter k=191;
    reg clk;
    reg rst;
    reg [k-1:0]msg;
    wire [254:0]bch_dataout;
    always #5 clk = ~clk;
    
    initial
    begin
        msg[k-1:0]=191'b10000111110110111110000100000010011000010110000010010110100111001100101110001010101111010011011111100100011100100101110111110010000110010110001000000110100110101111100100111000101100000100100;
        clk=1;
        rst=1;
        #100 rst=~rst;
    end    
    bch_encoder out(
        .rst(rst),
        .clk(clk),
        .msg(msg),
        .bch_dataout(bch_dataout)
        );
    
endmodule
module simu_coder_test(


    );

    parameter k=191;
    reg clk;
    reg rst;
    reg [k-1:0]msg;
    wire [254:0]bch_dataout;
    always #5 clk = ~clk;
    
    initial
    begin
        msg[k-1:0]=191'b10000111110110111110000100000010011000010110000010010110100111001100101110001010101111010011011111100100011100100101110111110010000110010110001000000110100110101111100100111000101100000100100;
        clk=1;
        rst=1;
        #100 rst=~rst;
    end    
    bch_encoder out(
        .rst(rst),
        .clk(clk),
        .msg(msg),
        .bch_dataout(bch_dataout)
        );
    
endmodule