data/full_repos/permissive/152229899/sync_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152229899/sync_fifo.v:45: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                   : ... In instance sync_fifo.ram_top\n   data_out<=ram[rd_addr];\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/152229899/sync_fifo.v:53: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                   : ... In instance sync_fifo.ram_top\n  ram[wr_addr]<=data_in;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/152229899/sync_fifo.v:215: Operator GTE expects 8 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                    : ... In instance sync_fifo\n   else if (data_in >= 5\'d0 && data_in < 5\'d31)\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/152229899/sync_fifo.v:215: Operator LT expects 8 bits on the RHS, but RHS\'s CONST \'5\'h1f\' generates 5 bits.\n                                                                    : ... In instance sync_fifo\n   else if (data_in >= 5\'d0 && data_in < 5\'d31)\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/152229899/sync_fifo.v:213: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'5\'h1f\' generates 5 bits.\n                                                                    : ... In instance sync_fifo\n   else if (data_in == 5\'d31)\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/152229899/sync_fifo.v:219: Operator GTE expects 5 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                    : ... In instance sync_fifo\nassign wr_en = (time_cnt >= 1\'b0 && time_cnt <= 5\'d15) ? 1\'b1:1\'b0;\n                         ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152229899/sync_fifo.v:205: Comparison is constant due to unsigned arithmetic\n                                                                       : ... In instance sync_fifo\n else if (data_in >= 8\'d0 && data_in < 8\'d15)\n                  ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152229899/sync_fifo.v:215: Comparison is constant due to unsigned arithmetic\n                                                                       : ... In instance sync_fifo\n   else if (data_in >= 5\'d0 && data_in < 5\'d31)\n                    ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152229899/sync_fifo.v:219: Comparison is constant due to unsigned arithmetic\n                                                                       : ... In instance sync_fifo\nassign wr_en = (time_cnt >= 1\'b0 && time_cnt <= 5\'d15) ? 1\'b1:1\'b0;\n                         ^~\n%Warning-CMPCONST: data/full_repos/permissive/152229899/sync_fifo.v:220: Comparison is constant due to limited range\n                                                                       : ... In instance sync_fifo\nassign rd_en = (time_cnt >= 5\'d16 && time_cnt <= 5\'d31) ? 1\'b1:1\'b0;\n                                              ^~\n%Error: Exiting due to 10 warning(s)\n'
module sync_fifo(input clk,
					input rst,
					output [7:0]data_out,
					output full,
					output empty,
					output reg  [4:0]time_cnt);

wire wr_en;
wire rd_en;
wire [3:0]rd_addr;
wire [3:0]wr_addr;
reg [7:0]data_in;


ram ram_top(.clk(clk),
				.rst(rst),
				.wr_en(wr_en),
				.rd_en(rd_en),
				.wr_addr(wr_addr),
				.rd_addr(rd_addr),
				.data_in(data_in),
				.full(full),
				.empty(empty),
				.data_out(data_out));
				
rd_addr_gen rd_addr_gen_top(.clk(clk),
									.rst(rst),
									.rd_en(rd_en),
									.empty(empty),
									.rd_addr(rd_addr));
									
wr_addr_gen wr_addr_gen_top(.clk(clk),
									.rst(rst),
									.wr_en(wr_en),
									.full(full),
									.wr_addr(wr_addr));
									
flag_gen flag_gen_top(.clk(clk),
							.rst(rst),
							.wr_en(wr_en),
							.rd_en(rd_en),
							.full(full),
							.empty(empty));
							
							
always @(posedge clk or negedge rst)
begin
   if (rst == 1'b0)
      data_in <= 8'd0;
   else if (data_in == 8'd15)
      data_in <= 8'd0;
	else if (data_in >= 8'd0 && data_in < 8'd15)
      data_in <= data_in + 8'd1;
end

always @(posedge clk or negedge rst)
begin 
	if (!rst)
	      time_cnt <=5'b0;
			else if (data_in == 5'd31)
			time_cnt <=5'b0;
			else if (data_in >= 5'd0 && data_in < 5'd31)
			time_cnt <= time_cnt + 5'd1;
	end

assign wr_en = (time_cnt >= 1'b0 && time_cnt <= 5'd15) ? 1'b1:1'b0;
assign rd_en = (time_cnt >= 5'd16 && time_cnt <= 5'd31) ? 1'b1:1'b0;


endmodule
module sync_fifo(input clk,
					input rst,
					output [7:0]data_out,
					output full,
					output empty,
					output reg  [4:0]time_cnt);


wire wr_en;
wire rd_en;
wire [3:0]rd_addr;
wire [3:0]wr_addr;
reg [7:0]data_in;


ram ram_top(.clk(clk),
				.rst(rst),
				.wr_en(wr_en),
				.rd_en(rd_en),
				.wr_addr(wr_addr),
				.rd_addr(rd_addr),
				.data_in(data_in),
				.full(full),
				.empty(empty),
				.data_out(data_out));
				
rd_addr_gen rd_addr_gen_top(.clk(clk),
									.rst(rst),
									.rd_en(rd_en),
									.empty(empty),
									.rd_addr(rd_addr));
									
wr_addr_gen wr_addr_gen_top(.clk(clk),
									.rst(rst),
									.wr_en(wr_en),
									.full(full),
									.wr_addr(wr_addr));
									
flag_gen flag_gen_top(.clk(clk),
							.rst(rst),
							.wr_en(wr_en),
							.rd_en(rd_en),
							.full(full),
							.empty(empty));
							
							
always @(posedge clk or negedge rst)
begin
   if (rst == 1'b0)
      data_in <= 8'd0;
   else if (data_in == 8'd15)
      data_in <= 8'd0;
	else if (data_in >= 8'd0 && data_in < 8'd15)
      data_in <= data_in + 8'd1;
end

always @(posedge clk or negedge rst)
begin 
	if (!rst)
	      time_cnt <=5'b0;
			else if (data_in == 5'd31)
			time_cnt <=5'b0;
			else if (data_in >= 5'd0 && data_in < 5'd31)
			time_cnt <= time_cnt + 5'd1;
	end

assign wr_en = (time_cnt >= 1'b0 && time_cnt <= 5'd15) ? 1'b1:1'b0;
assign rd_en = (time_cnt >= 5'd16 && time_cnt <= 5'd31) ? 1'b1:1'b0;


endmodule