data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:39: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk <= ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:44: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clk);\n             ^\n%Error: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:47: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clk);\n             ^\n%Error: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:53: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:55: Too many digits for 32 bit number: \'hdeadbeefdeadbeef\n  mem_readdata <= \'hdeadbeefdeadbeef;\n                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:58: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:62: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:66: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clk);\n             ^\n%Error: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:71: Too many digits for 32 bit number: \'h8000fffffff00000\n  next_addr <= \'h8000fffffff00000;\n               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:74: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:76: Too many digits for 32 bit number: \'hcafecafecafecafe\n  mem_readdata <= \'hcafecafecafecafe;\n                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:79: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/117436613/testbench/fetch_unit_test.sv:83: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: Exiting due to 12 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fetch_unit_test();

	logic			clk = 0;
	logic			reset_n = 0;
	logic			enable = 0;
	logic			ctl_change = 0;
	logic[63:0]	next_addr;
	logic			fetch_done;
	logic[63:0]	loc;
	logic[31:0]	inst;
	logic[18:0]	interrupt;	
	
	logic [63:0]	mem_address;
	logic [1:0]	mem_datasize;
	logic			mem_read;
	 logic [63:0]	mem_readdata;
	 logic			mem_done = 0;

   fetch_unit u0 (
		.clk,
		.reset_n,
		.enable,
		.ctl_change,
		.next_addr,
		.fetch_done,
		.loc,
		.inst,
		.interrupt,	
		
		.mem_address,
		.mem_datasize,
		.mem_read,
		.mem_readdata,
		.mem_done
  );

	always #10 clk <= ~clk;

	initial begin
		reset_n <= 0;
		
		repeat (2) @(posedge clk);
		reset_n <= 1;
		
		repeat (2) @(posedge clk);
		

		enable <= 1;
		
		while (!mem_read)
			@(posedge clk);
		
		mem_readdata <= 'hdeadbeefdeadbeef;
		mem_done <= 1;
		
		@(posedge clk);
		mem_done <= 0;
		
		while (!fetch_done)
			@(posedge clk);
		
		enable <= 0;
		
		repeat (2) @(posedge clk);
		

		enable <= 1;
		ctl_change <= 1;
		next_addr <= 'h8000fffffff00000;

		while (!mem_read)
			@(posedge clk);
		
		mem_readdata <= 'hcafecafecafecafe;
		mem_done <= 1;
		
		@(posedge clk);
		mem_done <= 0;
		
		while (!fetch_done)
			@(posedge clk);
		
		enable <= 0;

		end

endmodule
module fetch_unit_test();


	logic			clk = 0;
	logic			reset_n = 0;
	logic			enable = 0;
	logic			ctl_change = 0;
	logic[63:0]	next_addr;
	logic			fetch_done;
	logic[63:0]	loc;
	logic[31:0]	inst;
	logic[18:0]	interrupt;	
	
	logic [63:0]	mem_address;
	logic [1:0]	mem_datasize;
	logic			mem_read;
	 logic [63:0]	mem_readdata;
	 logic			mem_done = 0;

   fetch_unit u0 (
		.clk,
		.reset_n,
		.enable,
		.ctl_change,
		.next_addr,
		.fetch_done,
		.loc,
		.inst,
		.interrupt,	
		
		.mem_address,
		.mem_datasize,
		.mem_read,
		.mem_readdata,
		.mem_done
  );

	always #10 clk <= ~clk;

	initial begin
		reset_n <= 0;
		
		repeat (2) @(posedge clk);
		reset_n <= 1;
		
		repeat (2) @(posedge clk);
		

		enable <= 1;
		
		while (!mem_read)
			@(posedge clk);
		
		mem_readdata <= 'hdeadbeefdeadbeef;
		mem_done <= 1;
		
		@(posedge clk);
		mem_done <= 0;
		
		while (!fetch_done)
			@(posedge clk);
		
		enable <= 0;
		
		repeat (2) @(posedge clk);
		

		enable <= 1;
		ctl_change <= 1;
		next_addr <= 'h8000fffffff00000;

		while (!mem_read)
			@(posedge clk);
		
		mem_readdata <= 'hcafecafecafecafe;
		mem_done <= 1;
		
		@(posedge clk);
		mem_done <= 0;
		
		while (!fetch_done)
			@(posedge clk);
		
		enable <= 0;

		end

endmodule