data/full_repos/permissive/169522605/hw3_1/nand2.v
data/verilator_xmls/4ff8ea05-7e8b-412f-8c7a-d7af1fea524c.xml
module nand2 (in1,in2,out);
    input in1,in2;
    output out;
    assign out = ~(in1 & in2);
endmodule
module nand2 (in1,in2,out);

    input in1,in2;
    output out;
    assign out = ~(in1 & in2);
endmodule