data/full_repos/permissive/120518070/main/source/tb_RC4_gen_pseudo_rand_module.sv
Syntax Error
1: b'%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_pseudo_rand_module.sv:15: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_pseudo_rand_module.sv:17: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_pseudo_rand_module.sv:41: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_pseudo_rand_module.sv:43: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_pseudo_rand_module.sv:45: syntax error, unexpected \'@\'\n @(negedge tb_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_pseudo_rand_module.sv:46: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_pseudo_rand_module.sv:48: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Error: data/full_repos/permissive/120518070/main/source/tb_RC4_gen_pseudo_rand_module.sv:60: syntax error, unexpected \'@\'\n  @(negedge tb_clk);\n  ^\n%Error: Exiting due to 4 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_RC4_gen_pseudo_rand_module();
	localparam CLK_PERIOD = 35;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	reg tb_n_rst;
	reg tb_genStateArr_i;
	reg tb_genVal_i;
	reg [31:0] tb_rc4_key_i;
	reg [7:0] tb_outputToXor_o;
	reg tb_sarrGenerated_o;
	reg tb_valReady_o;

	RC4_gen_pseudo_rand_module DUT (.clk(tb_clk),.n_rst(tb_n_rst),.genStateArr_i(tb_genStateArr_i),.genVal_i(tb_genVal_i),
					.rc4_key_i_(tb_rc4_key_i),.outputToXor_o(tb_outputToXor_o),.sarrGenerated_o_(tb_sarrGenerated_o),.valReady_o_(tb_valReady_o));

	logic flag = 0;
initial
begin
	tb_n_rst = 0;
	tb_genStateArr_i = 0;
	tb_genVal_i = 0;
	tb_rc4_key_i = "DR.J";
	tb_outputToXor_o = 0;
	tb_sarrGenerated_o = 0;
	tb_valReady_o = 0;
	@(negedge tb_clk);
	tb_n_rst = 1;
	@(negedge tb_clk);
	tb_genStateArr_i = 1;
	@(negedge tb_clk);
	#(CLK_PERIOD);
	flag = 1;
	#(CLK_PERIOD);
	flag = 0;







	tb_genVal_i = 1;
	if (flag == 1)
	begin
		@(negedge tb_clk);
		@(negedge tb_clk);
		@(negedge tb_clk);
		@(negedge tb_clk);
		@(negedge tb_clk);
		@(negedge tb_clk);
		@(negedge tb_clk);
		@(negedge tb_clk);
		tb_genVal_i = 1;
		flag = 0;
	end
	else
	begin
		tb_genVal_i = 1;
	end
end
endmodule
module tb_RC4_gen_pseudo_rand_module();

	localparam CLK_PERIOD = 35;
	reg tb_clk;
	always
	begin
		tb_clk = 1'b0;
		#(CLK_PERIOD/2);
		tb_clk = 1'b1;
		#(CLK_PERIOD/2);
	end

	reg tb_n_rst;
	reg tb_genStateArr_i;
	reg tb_genVal_i;
	reg [31:0] tb_rc4_key_i;
	reg [7:0] tb_outputToXor_o;
	reg tb_sarrGenerated_o;
	reg tb_valReady_o;

	RC4_gen_pseudo_rand_module DUT (.clk(tb_clk),.n_rst(tb_n_rst),.genStateArr_i(tb_genStateArr_i),.genVal_i(tb_genVal_i),
					.rc4_key_i_(tb_rc4_key_i),.outputToXor_o(tb_outputToXor_o),.sarrGenerated_o_(tb_sarrGenerated_o),.valReady_o_(tb_valReady_o));

	logic flag = 0;
initial
begin
	tb_n_rst = 0;
	tb_genStateArr_i = 0;
	tb_genVal_i = 0;
	tb_rc4_key_i = "DR.J";
	tb_outputToXor_o = 0;
	tb_sarrGenerated_o = 0;
	tb_valReady_o = 0;
	@(negedge tb_clk);
	tb_n_rst = 1;
	@(negedge tb_clk);
	tb_genStateArr_i = 1;
	@(negedge tb_clk);
	#(CLK_PERIOD);
	flag = 1;
	#(CLK_PERIOD);
	flag = 0;







	tb_genVal_i = 1;
	if (flag == 1)
	begin
		@(negedge tb_clk);
		@(negedge tb_clk);
		@(negedge tb_clk);
		@(negedge tb_clk);
		@(negedge tb_clk);
		@(negedge tb_clk);
		@(negedge tb_clk);
		@(negedge tb_clk);
		tb_genVal_i = 1;
		flag = 0;
	end
	else
	begin
		tb_genVal_i = 1;
	end
end
endmodule