data/full_repos/permissive/206169433/pipeline/forward.v
data/verilator_xmls/facaa410-7c48-42e6-8b31-2708564d4410.xml
module forward(


        output reg  [1:0]forwardA,
        output reg  [1:0]forwardB,
        output reg  forwardC,
        output reg  forwardD,


        input       [4:0]reg_rs_ID,
        input       [4:0]reg_rt_ID,
        input       [4:0]reg_rs_EX,
        input       [4:0]reg_rt_EX,


        input       [4:0]reg_rd_MEM,
        input       [4:0]reg_rd_WB,
        input       regwrite_MEM,
        input       regwrite_WB
    );
    always @(*)
    begin

        if          (regwrite_MEM && reg_rd_MEM!=0 && reg_rd_MEM==reg_rs_EX)    forwardA = 2'b10;
        else if    (regwrite_WB  && reg_rd_WB!=0  && reg_rd_WB==reg_rs_EX)     forwardA = 2'b01;
        else        forwardA = 2'b00;

        if          (regwrite_MEM && reg_rd_MEM!=0 && reg_rd_MEM==reg_rt_EX)    forwardB = 2'b10;
        else if    (regwrite_WB  && reg_rd_WB!=0  && reg_rd_WB==reg_rt_EX)     forwardB = 2'b01;
        else        forwardB = 2'b00;

        if          (regwrite_MEM && reg_rd_MEM!=0 && reg_rd_MEM==reg_rs_ID)    forwardC = 1'b1;
        else        forwardC = 1'b0;

        if          (regwrite_MEM && reg_rd_MEM!=0 && reg_rd_MEM==reg_rt_ID)    forwardD = 1'b1;
        else        forwardD = 1'b0;
    end
    initial begin forwardA = 2'b00; forwardB = 2'b00; forwardC = 1'b0; forwardD = 1'b0; end
    
endmodule
module forward(


        output reg  [1:0]forwardA,
        output reg  [1:0]forwardB,
        output reg  forwardC,
        output reg  forwardD,


        input       [4:0]reg_rs_ID,
        input       [4:0]reg_rt_ID,
        input       [4:0]reg_rs_EX,
        input       [4:0]reg_rt_EX,


        input       [4:0]reg_rd_MEM,
        input       [4:0]reg_rd_WB,
        input       regwrite_MEM,
        input       regwrite_WB
    );

    always @(*)
    begin

        if          (regwrite_MEM && reg_rd_MEM!=0 && reg_rd_MEM==reg_rs_EX)    forwardA = 2'b10;
        else if    (regwrite_WB  && reg_rd_WB!=0  && reg_rd_WB==reg_rs_EX)     forwardA = 2'b01;
        else        forwardA = 2'b00;

        if          (regwrite_MEM && reg_rd_MEM!=0 && reg_rd_MEM==reg_rt_EX)    forwardB = 2'b10;
        else if    (regwrite_WB  && reg_rd_WB!=0  && reg_rd_WB==reg_rt_EX)     forwardB = 2'b01;
        else        forwardB = 2'b00;

        if          (regwrite_MEM && reg_rd_MEM!=0 && reg_rd_MEM==reg_rs_ID)    forwardC = 1'b1;
        else        forwardC = 1'b0;

        if          (regwrite_MEM && reg_rd_MEM!=0 && reg_rd_MEM==reg_rt_ID)    forwardD = 1'b1;
        else        forwardD = 1'b0;
    end
    initial begin forwardA = 2'b00; forwardB = 2'b00; forwardC = 1'b0; forwardD = 1'b0; end
    
endmodule