data/full_repos/permissive/143278/vhdl_tests/pr2911213.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/pr2911213.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/vhdl_tests/pr2911213.v:10: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n                                                                           : ... In instance top\n    a = 3\'b101;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/vhdl_tests/pr2911213.v:11: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                                           : ... In instance top\n    b = 4\'b0101;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/vhdl_tests/pr2911213.v:13: Operator EQ expects 9 bits on the RHS, but RHS\'s CONST \'8\'ha5\' generates 8 bits.\n                                                                           : ... In instance top\n    if (y == 8\'b10100101)\n          ^~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top();

  reg [3:0] a;
  reg [4:0] b;
  wire [8:0] y;

  functest uut(a, b, y);

  initial begin
    a = 3'b101;
    b = 4'b0101;
    #1;
    if (y == 8'b10100101)
      $display("PASSED");
    else
      $display("FAILED y = %b", y);
  end

endmodule
module top();


  reg [3:0] a;
  reg [4:0] b;
  wire [8:0] y;

  functest uut(a, b, y);

  initial begin
    a = 3'b101;
    b = 4'b0101;
    #1;
    if (y == 8'b10100101)
      $display("PASSED");
    else
      $display("FAILED y = %b", y);
  end

endmodule