data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_gate.v
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_gate.v:52: Cannot find include file: ../core/ctrlport.vh\n  `include "../core/ctrlport.vh" \n           ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils,data/full_repos/permissive/214858095/../core/ctrlport.vh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils,data/full_repos/permissive/214858095/../core/ctrlport.vh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils,data/full_repos/permissive/214858095/../core/ctrlport.vh.sv\n             ../core/ctrlport.vh\n             ../core/ctrlport.vh.v\n             ../core/ctrlport.vh.sv\n             obj_dir/../core/ctrlport.vh\n             obj_dir/../core/ctrlport.vh.v\n             obj_dir/../core/ctrlport.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module ctrlport_gate (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire enable,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [ 9:0] s_ctrlport_req_portid,
  input  wire [15:0] s_ctrlport_req_rem_epid,
  input  wire [ 9:0] s_ctrlport_req_rem_portid,
  input  wire [31:0] s_ctrlport_req_data,
  input  wire [ 3:0] s_ctrlport_req_byte_en,
  input  wire        s_ctrlport_req_has_time,
  input  wire [63:0] s_ctrlport_req_time,
  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  output reg         m_ctrlport_req_wr,
  output reg         m_ctrlport_req_rd,
  output reg  [19:0] m_ctrlport_req_addr,
  output reg  [ 9:0] m_ctrlport_req_portid,
  output reg  [15:0] m_ctrlport_req_rem_epid,
  output reg  [ 9:0] m_ctrlport_req_rem_portid,
  output reg  [31:0] m_ctrlport_req_data,
  output reg  [ 3:0] m_ctrlport_req_byte_en,
  output reg         m_ctrlport_req_has_time,
  output reg  [63:0] m_ctrlport_req_time,
  input  wire        m_ctrlport_resp_ack,
  input  wire [ 1:0] m_ctrlport_resp_status,
  input  wire [31:0] m_ctrlport_resp_data
);

  `include "../core/ctrlport.vh"

  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      m_ctrlport_req_wr   <= 1'b0;
      m_ctrlport_req_rd   <= 1'b0;
      s_ctrlport_resp_ack <= 1'b0;
    end else begin

      m_ctrlport_req_wr         <= s_ctrlport_req_wr;
      m_ctrlport_req_rd         <= s_ctrlport_req_rd;
      m_ctrlport_req_addr       <= s_ctrlport_req_addr;
      m_ctrlport_req_portid     <= s_ctrlport_req_portid;
      m_ctrlport_req_rem_epid   <= s_ctrlport_req_rem_epid;
      m_ctrlport_req_rem_portid <= s_ctrlport_req_rem_portid;
      m_ctrlport_req_data       <= s_ctrlport_req_data;
      m_ctrlport_req_byte_en    <= s_ctrlport_req_byte_en;
      m_ctrlport_req_has_time   <= s_ctrlport_req_has_time;
      m_ctrlport_req_time       <= s_ctrlport_req_time;

      s_ctrlport_resp_ack    <= m_ctrlport_resp_ack;
      s_ctrlport_resp_status <= m_ctrlport_resp_status;
      s_ctrlport_resp_data   <= m_ctrlport_resp_data;


      if (m_ctrlport_req_rd || m_ctrlport_req_wr) begin
        if (~enable) begin

          m_ctrlport_req_wr <= 1'b0;
          m_ctrlport_req_rd <= 1'b0;


          s_ctrlport_resp_ack    <= 1'b1;
          s_ctrlport_resp_status <= CTRL_STS_CMDERR;
        end
      end
    end
  end

endmodule
module ctrlport_gate (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire enable,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [ 9:0] s_ctrlport_req_portid,
  input  wire [15:0] s_ctrlport_req_rem_epid,
  input  wire [ 9:0] s_ctrlport_req_rem_portid,
  input  wire [31:0] s_ctrlport_req_data,
  input  wire [ 3:0] s_ctrlport_req_byte_en,
  input  wire        s_ctrlport_req_has_time,
  input  wire [63:0] s_ctrlport_req_time,
  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  output reg         m_ctrlport_req_wr,
  output reg         m_ctrlport_req_rd,
  output reg  [19:0] m_ctrlport_req_addr,
  output reg  [ 9:0] m_ctrlport_req_portid,
  output reg  [15:0] m_ctrlport_req_rem_epid,
  output reg  [ 9:0] m_ctrlport_req_rem_portid,
  output reg  [31:0] m_ctrlport_req_data,
  output reg  [ 3:0] m_ctrlport_req_byte_en,
  output reg         m_ctrlport_req_has_time,
  output reg  [63:0] m_ctrlport_req_time,
  input  wire        m_ctrlport_resp_ack,
  input  wire [ 1:0] m_ctrlport_resp_status,
  input  wire [31:0] m_ctrlport_resp_data
);


  `include "../core/ctrlport.vh"

  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      m_ctrlport_req_wr   <= 1'b0;
      m_ctrlport_req_rd   <= 1'b0;
      s_ctrlport_resp_ack <= 1'b0;
    end else begin

      m_ctrlport_req_wr         <= s_ctrlport_req_wr;
      m_ctrlport_req_rd         <= s_ctrlport_req_rd;
      m_ctrlport_req_addr       <= s_ctrlport_req_addr;
      m_ctrlport_req_portid     <= s_ctrlport_req_portid;
      m_ctrlport_req_rem_epid   <= s_ctrlport_req_rem_epid;
      m_ctrlport_req_rem_portid <= s_ctrlport_req_rem_portid;
      m_ctrlport_req_data       <= s_ctrlport_req_data;
      m_ctrlport_req_byte_en    <= s_ctrlport_req_byte_en;
      m_ctrlport_req_has_time   <= s_ctrlport_req_has_time;
      m_ctrlport_req_time       <= s_ctrlport_req_time;

      s_ctrlport_resp_ack    <= m_ctrlport_resp_ack;
      s_ctrlport_resp_status <= m_ctrlport_resp_status;
      s_ctrlport_resp_data   <= m_ctrlport_resp_data;


      if (m_ctrlport_req_rd || m_ctrlport_req_wr) begin
        if (~enable) begin

          m_ctrlport_req_wr <= 1'b0;
          m_ctrlport_req_rd <= 1'b0;


          s_ctrlport_resp_ack    <= 1'b1;
          s_ctrlport_resp_status <= CTRL_STS_CMDERR;
        end
      end
    end
  end

endmodule