data/full_repos/permissive/143278/ivltests/vhdl_report.v
None: at end of input
1: b'%Error: data/full_repos/permissive/143278/ivltests/vhdl_report.v:30: syntax error, unexpected ::, expecting \';\'\n    a = vhdl_report_pkg::test_asserts(0);\n                       ^~\n                                                                   : ... Perhaps \'vhdl_report_pkg\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_report.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #1 start_test = 1\'b1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module vhdl_report_test;

logic start_test;
vhdl_report dut(start_test);
int a;

initial begin

    a = vhdl_report_pkg::test_asserts(0);

    start_test = 1'b0;
    #1 start_test = 1'b1;
end
endmodule
module vhdl_report_test;


logic start_test;
vhdl_report dut(start_test);
int a;

initial begin

    a = vhdl_report_pkg::test_asserts(0);

    start_test = 1'b0;
    #1 start_test = 1'b1;
end
endmodule