data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v
 line:82: before: "case"
1: b'%Warning-MULTITOP: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:205: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'$__QLF_FACTOR_BRAM36_TDP\'\nmodule \\$__QLF_FACTOR_BRAM36_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, D1ADDR, D1DATA, D1EN);\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$__QLF_FACTOR_BRAM18_TDP\'\nmodule \\$__QLF_FACTOR_BRAM18_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, CLK3, CLK4, D1ADDR, D1DATA, D1EN);\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$__QLF_FACTOR_BRAM18_SDP\'\nmodule \\$__QLF_FACTOR_BRAM18_SDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, CLK1, CLK2);\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$__QLF_FACTOR_BRAM36_SDP\'\nmodule \\$__QLF_FACTOR_BRAM36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$__QLF_FACTOR_BRAM36_SDP_ASYMMETRIC\'\nmodule \\$__QLF_FACTOR_BRAM36_SDP_ASYMMETRIC (RD_ADDR, RD_ARST, RD_CLK, RD_DATA, RD_EN, RD_SRST, WR_ADDR, WR_CLK, WR_DATA, WR_EN);\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:951: Operator ASSIGNDLY expects 36 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 18 bits.\n                                                                                             : ... In instance __024___05FQLF_FACTOR_BRAM36_SDP_ASYMMETRIC\n   {RD_DATA_CMPL, RD_DATA} <= {PORT_A2_RDATA[17 - (READ_DATA_BITS_TO_SKIP / 2):17 - (READ_DATA_BITS_TO_SKIP / 2)], PORT_A1_RDATA[17 - (READ_DATA_BITS_TO_SKIP / 2):17 - (READ_DATA_BITS_TO_SKIP / 2)],PORT_A2_RDATA[17 - (READ_DATA_BITS_TO_SKIP / 2):0], PORT_A1_RDATA[17 - (READ_DATA_BITS_TO_SKIP / 2):0]};\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:953: Operator ASSIGNDLY expects 36 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n                                                                                             : ... In instance __024___05FQLF_FACTOR_BRAM36_SDP_ASYMMETRIC\n   {RD_DATA_CMPL, RD_DATA} <= {PORT_A1_RDATA[17 - (READ_DATA_BITS_TO_SKIP-18):17 - (READ_DATA_BITS_TO_SKIP-18)], PORT_A1_RDATA[17 - (READ_DATA_BITS_TO_SKIP-18):0]};\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:956: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                                             : ... In instance __024___05FQLF_FACTOR_BRAM36_SDP_ASYMMETRIC\n wire [17:0] PORT_A1_WDATA = {WR_DATA_CMPL, WR_DATA[15:0]};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:957: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                                             : ... In instance __024___05FQLF_FACTOR_BRAM36_SDP_ASYMMETRIC\n wire [17:0] PORT_A2_WDATA = {WR_DATA_CMPL, WR_DATA[31:16]};\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:964: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'WR_EN\' generates 4 bits.\n                                                                                             : ... In instance __024___05FQLF_FACTOR_BRAM36_SDP_ASYMMETRIC\n wire PORT_A1_WEN = WR_EN;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:968: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'WR_EN\' generates 4 bits.\n                                                                                             : ... In instance __024___05FQLF_FACTOR_BRAM36_SDP_ASYMMETRIC\n wire PORT_A2_WEN = WR_EN;\n                  ^\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:971: Cannot find file containing module: \'TDP36K\'\n TDP36K _TECHMAP_REPLACE_ (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f,data/full_repos/permissive/220229160/TDP36K\n             data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f,data/full_repos/permissive/220229160/TDP36K.v\n             data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f,data/full_repos/permissive/220229160/TDP36K.sv\n             TDP36K\n             TDP36K.v\n             TDP36K.sv\n             obj_dir/TDP36K\n             obj_dir/TDP36K.v\n             obj_dir/TDP36K.sv\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:353: Little bit endian vector: MSB < LSB of bit range: 35:36\n wire [35:CFG_DBITS] A1DATA_CMPL;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:354: Little bit endian vector: MSB < LSB of bit range: 35:36\n wire [35:CFG_DBITS] B1DATA_CMPL;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:379: Operator ASSIGNW expects 36 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 38 bits.\n                                                                                             : ... In instance __024___05FQLF_FACTOR_BRAM36_SDP\n   assign B1DATA_TOTAL = {B1DATA_CMPL, B1DATA};\n                       ^\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:449: Cannot find file containing module: \'TDP36K\'\n TDP36K _TECHMAP_REPLACE_ (\n ^~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:299: Cannot find file containing module: \'BRAM2x18_SDP\'\n BRAM2x18_SDP #(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:236: Cannot find file containing module: \'BRAM2x18_TDP\'\n BRAM2x18_TDP #(\n ^~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:67: Little bit endian vector: MSB < LSB of bit range: 35:36\n wire [35:CFG_DBITS] A1DATA_CMPL;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:68: Little bit endian vector: MSB < LSB of bit range: 35:36\n wire [35:CFG_DBITS] B1DATA_CMPL;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:69: Little bit endian vector: MSB < LSB of bit range: 35:36\n wire [35:CFG_DBITS] C1DATA_CMPL;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:70: Little bit endian vector: MSB < LSB of bit range: 35:36\n wire [35:CFG_DBITS] D1DATA_CMPL;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:92: Operator ASSIGNW expects 36 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 38 bits.\n                                                                                            : ... In instance __024___05FQLF_FACTOR_BRAM36_TDP\n   assign B1DATA_TOTAL = {B1DATA_CMPL, B1DATA};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:93: Operator ASSIGNW expects 36 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 38 bits.\n                                                                                            : ... In instance __024___05FQLF_FACTOR_BRAM36_TDP\n   assign D1DATA_TOTAL = {D1DATA_CMPL, D1DATA};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:144: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'B1EN\' generates 4 bits.\n                                                                                             : ... In instance __024___05FQLF_FACTOR_BRAM36_TDP\n   assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 5) : (B1EN ? (B1ADDR_TOTAL << 5) : 15\'d0);\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:145: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'D1EN\' generates 4 bits.\n                                                                                             : ... In instance __024___05FQLF_FACTOR_BRAM36_TDP\n   assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 5) : (D1EN ? (D1ADDR_TOTAL << 5) : 15\'d0);\n                                                           ^\n%Error: data/full_repos/permissive/220229160/ql-qlf-plugin/qlf_k6n10f/brams_map.v:166: Cannot find file containing module: \'TDP36K\'\n TDP36K _TECHMAP_REPLACE_ (\n ^~~~~~\n%Error: Exiting due to 5 error(s), 18 warning(s)\n'
module \$__QLF_FACTOR_BRAM36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CFG_ABITS = 10;
	parameter CFG_DBITS = 36;
	parameter CFG_ENABLE_B = 4;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [36863:0] INIT = 36864'bx;

	localparam MODE_36  = 3'b111;
	localparam MODE_18  = 3'b110;
	localparam MODE_9   = 3'b101;
	localparam MODE_4   = 3'b100;
	localparam MODE_2   = 3'b010;
	localparam MODE_1   = 3'b001;

	input CLK2;
	input CLK3;

	input [CFG_ABITS-1:0] A1ADDR;
	output [CFG_DBITS-1:0] A1DATA;
	input A1EN;

	input [CFG_ABITS-1:0] B1ADDR;
	input [CFG_DBITS-1:0] B1DATA;
	input [CFG_ENABLE_B-1:0] B1EN;

	wire [14:0] A1ADDR_15;
	wire [14:0] B1ADDR_15;

	wire [35:0] DOBDO;

	wire [14:CFG_ABITS] A1ADDR_CMPL;
	wire [14:CFG_ABITS] B1ADDR_CMPL;
	wire [35:CFG_DBITS] A1DATA_CMPL;
	wire [35:CFG_DBITS] B1DATA_CMPL;

	wire [14:0] A1ADDR_TOTAL;
	wire [14:0] B1ADDR_TOTAL;
	wire [35:0] A1DATA_TOTAL;
	wire [35:0] B1DATA_TOTAL;

	wire FLUSH1;
	wire FLUSH2;

	assign A1ADDR_CMPL = {15-CFG_ABITS{1'b0}};
	assign B1ADDR_CMPL = {15-CFG_ABITS{1'b0}};

	assign A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR};
	assign B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR};



	case (CFG_DBITS)
		9: begin
			assign A1DATA = {A1DATA_TOTAL[16], A1DATA_TOTAL[7:0]};
			assign B1DATA_TOTAL = {B1DATA_CMPL[35:17], B1DATA[8], B1DATA_CMPL[16:9], B1DATA[7:0]};
		end
		default: begin
			assign A1DATA = A1DATA_TOTAL[CFG_DBITS-1:0];
			assign B1DATA_TOTAL = {B1DATA_CMPL, B1DATA};
		end
	endcase

	case (CFG_DBITS)
		1: begin
			assign A1ADDR_15 = A1ADDR_TOTAL;
			assign B1ADDR_15 = B1ADDR_TOTAL;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0
            };
		end

		2: begin
			assign A1ADDR_15 = A1ADDR_TOTAL << 1;
			assign B1ADDR_15 = B1ADDR_TOTAL << 1;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_2, `MODE_2, `MODE_2, `MODE_2, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_2, `MODE_2, `MODE_2, `MODE_2, 1'd0
            };
		end

		4: begin
			assign A1ADDR_15 = A1ADDR_TOTAL << 2;
			assign B1ADDR_15 = B1ADDR_TOTAL << 2;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_4, `MODE_4, `MODE_4, `MODE_4, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_4, `MODE_4, `MODE_4, `MODE_4, 1'd0
            };
		end
		8, 9: begin
			assign A1ADDR_15 = A1ADDR_TOTAL << 3;
			assign B1ADDR_15 = B1ADDR_TOTAL << 3;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0
            };
		end

		16, 18: begin
			assign A1ADDR_15 = A1ADDR_TOTAL << 4;
			assign B1ADDR_15 = B1ADDR_TOTAL << 4;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0
            };
		end
		32, 36: begin
			assign A1ADDR_15 = A1ADDR_TOTAL << 5;
			assign B1ADDR_15 = B1ADDR_TOTAL << 5;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0
            };
		end
		default: begin
			assign A1ADDR_15 = A1ADDR_TOTAL;
			assign B1ADDR_15 = B1ADDR_TOTAL;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0
            };
		end
	endcase


	assign FLUSH1 = 1'b0;
	assign FLUSH2 = 1'b0;

	TDP36K _TECHMAP_REPLACE_ (
		.RESET_ni(1'b1),
		.WDATA_A1_i(18'h3FFFF),
		.WDATA_A2_i(18'h3FFFF),
		.RDATA_A1_o(A1DATA_TOTAL[17:0]),
		.RDATA_A2_o(A1DATA_TOTAL[35:18]),
		.ADDR_A1_i(A1ADDR_15),
		.ADDR_A2_i(A1ADDR_15),
		.CLK_A1_i(CLK2),
		.CLK_A2_i(CLK2),
		.REN_A1_i(A1EN),
		.REN_A2_i(A1EN),
		.WEN_A1_i(1'b0),
		.WEN_A2_i(1'b0),
		.BE_A1_i({A1EN, A1EN}),
		.BE_A2_i({A1EN, A1EN}),

		.WDATA_B1_i(B1DATA_TOTAL[17:0]),
		.WDATA_B2_i(B1DATA_TOTAL[35:18]),
		.RDATA_B1_o(DOBDO[17:0]),
		.RDATA_B2_o(DOBDO[35:18]),
		.ADDR_B1_i(B1ADDR_15),
		.ADDR_B2_i(B1ADDR_15),
		.CLK_B1_i(CLK3),
		.CLK_B2_i(CLK3),
		.REN_B1_i(1'b0),
		.REN_B2_i(1'b0),
		.WEN_B1_i(B1EN[0]),
		.WEN_B2_i(B1EN[0]),
		.BE_B1_i(B1EN[1:0]),
		.BE_B2_i(B1EN[3:2]),

		.FLUSH1_i(FLUSH1),
		.FLUSH2_i(FLUSH2)
	);
endmodule
module \$__QLF_FACTOR_BRAM36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);

	parameter CFG_ABITS = 10;
	parameter CFG_DBITS = 36;
	parameter CFG_ENABLE_B = 4;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [36863:0] INIT = 36864'bx;

	localparam MODE_36  = 3'b111;
	localparam MODE_18  = 3'b110;
	localparam MODE_9   = 3'b101;
	localparam MODE_4   = 3'b100;
	localparam MODE_2   = 3'b010;
	localparam MODE_1   = 3'b001;

	input CLK2;
	input CLK3;

	input [CFG_ABITS-1:0] A1ADDR;
	output [CFG_DBITS-1:0] A1DATA;
	input A1EN;

	input [CFG_ABITS-1:0] B1ADDR;
	input [CFG_DBITS-1:0] B1DATA;
	input [CFG_ENABLE_B-1:0] B1EN;

	wire [14:0] A1ADDR_15;
	wire [14:0] B1ADDR_15;

	wire [35:0] DOBDO;

	wire [14:CFG_ABITS] A1ADDR_CMPL;
	wire [14:CFG_ABITS] B1ADDR_CMPL;
	wire [35:CFG_DBITS] A1DATA_CMPL;
	wire [35:CFG_DBITS] B1DATA_CMPL;

	wire [14:0] A1ADDR_TOTAL;
	wire [14:0] B1ADDR_TOTAL;
	wire [35:0] A1DATA_TOTAL;
	wire [35:0] B1DATA_TOTAL;

	wire FLUSH1;
	wire FLUSH2;

	assign A1ADDR_CMPL = {15-CFG_ABITS{1'b0}};
	assign B1ADDR_CMPL = {15-CFG_ABITS{1'b0}};

	assign A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR};
	assign B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR};



	case (CFG_DBITS)
		9: begin
			assign A1DATA = {A1DATA_TOTAL[16], A1DATA_TOTAL[7:0]};
			assign B1DATA_TOTAL = {B1DATA_CMPL[35:17], B1DATA[8], B1DATA_CMPL[16:9], B1DATA[7:0]};
		end
		default: begin
			assign A1DATA = A1DATA_TOTAL[CFG_DBITS-1:0];
			assign B1DATA_TOTAL = {B1DATA_CMPL, B1DATA};
		end
	endcase

	case (CFG_DBITS)
		1: begin
			assign A1ADDR_15 = A1ADDR_TOTAL;
			assign B1ADDR_15 = B1ADDR_TOTAL;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_1, `MODE_1, `MODE_1, `MODE_1, 1'd0
            };
		end

		2: begin
			assign A1ADDR_15 = A1ADDR_TOTAL << 1;
			assign B1ADDR_15 = B1ADDR_TOTAL << 1;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_2, `MODE_2, `MODE_2, `MODE_2, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_2, `MODE_2, `MODE_2, `MODE_2, 1'd0
            };
		end

		4: begin
			assign A1ADDR_15 = A1ADDR_TOTAL << 2;
			assign B1ADDR_15 = B1ADDR_TOTAL << 2;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_4, `MODE_4, `MODE_4, `MODE_4, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_4, `MODE_4, `MODE_4, `MODE_4, 1'd0
            };
		end
		8, 9: begin
			assign A1ADDR_15 = A1ADDR_TOTAL << 3;
			assign B1ADDR_15 = B1ADDR_TOTAL << 3;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_9, `MODE_9, `MODE_9, `MODE_9, 1'd0
            };
		end

		16, 18: begin
			assign A1ADDR_15 = A1ADDR_TOTAL << 4;
			assign B1ADDR_15 = B1ADDR_TOTAL << 4;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_18, `MODE_18, `MODE_18, `MODE_18, 1'd0
            };
		end
		32, 36: begin
			assign A1ADDR_15 = A1ADDR_TOTAL << 5;
			assign B1ADDR_15 = B1ADDR_TOTAL << 5;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0
            };
		end
		default: begin
			assign A1ADDR_15 = A1ADDR_TOTAL;
			assign B1ADDR_15 = B1ADDR_TOTAL;
            defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
                11'd10, 11'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0,
                12'd10, 12'd10, 4'd0, `MODE_36, `MODE_36, `MODE_36, `MODE_36, 1'd0
            };
		end
	endcase


	assign FLUSH1 = 1'b0;
	assign FLUSH2 = 1'b0;

	TDP36K _TECHMAP_REPLACE_ (
		.RESET_ni(1'b1),
		.WDATA_A1_i(18'h3FFFF),
		.WDATA_A2_i(18'h3FFFF),
		.RDATA_A1_o(A1DATA_TOTAL[17:0]),
		.RDATA_A2_o(A1DATA_TOTAL[35:18]),
		.ADDR_A1_i(A1ADDR_15),
		.ADDR_A2_i(A1ADDR_15),
		.CLK_A1_i(CLK2),
		.CLK_A2_i(CLK2),
		.REN_A1_i(A1EN),
		.REN_A2_i(A1EN),
		.WEN_A1_i(1'b0),
		.WEN_A2_i(1'b0),
		.BE_A1_i({A1EN, A1EN}),
		.BE_A2_i({A1EN, A1EN}),

		.WDATA_B1_i(B1DATA_TOTAL[17:0]),
		.WDATA_B2_i(B1DATA_TOTAL[35:18]),
		.RDATA_B1_o(DOBDO[17:0]),
		.RDATA_B2_o(DOBDO[35:18]),
		.ADDR_B1_i(B1ADDR_15),
		.ADDR_B2_i(B1ADDR_15),
		.CLK_B1_i(CLK3),
		.CLK_B2_i(CLK3),
		.REN_B1_i(1'b0),
		.REN_B2_i(1'b0),
		.WEN_B1_i(B1EN[0]),
		.WEN_B2_i(B1EN[0]),
		.BE_B1_i(B1EN[1:0]),
		.BE_B2_i(B1EN[3:2]),

		.FLUSH1_i(FLUSH1),
		.FLUSH2_i(FLUSH2)
	);
endmodule