data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/dsp/mult_add_clip.v
 line:77: before: "["
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/dsp/mult_add_clip.v:91: [-2:0] Range extract has backward bit ordering, perhaps you wanted [0:-2]\n                                                                                                                      : ... In instance mult_add_clip\n          align_c[C_BOT-1:0] = {C_BOT{1\'b0}};\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/dsp/mult_add_clip.v:91: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates -1 bits.\n                                                                                                                              : ... In instance mult_add_clip\n          align_c[C_BOT-1:0] = {C_BOT{1\'b0}};\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/dsp/mult_add_clip.v:194: Cannot find file containing module: \'DSP48E1\'\n  DSP48E1 #(\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/dsp,data/full_repos/permissive/214858095/DSP48E1\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/dsp,data/full_repos/permissive/214858095/DSP48E1.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/dsp,data/full_repos/permissive/214858095/DSP48E1.sv\n             DSP48E1\n             DSP48E1.v\n             DSP48E1.sv\n             obj_dir/DSP48E1\n             obj_dir/DSP48E1.v\n             obj_dir/DSP48E1.sv\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
function automatic [47:0] align_c;
    input [WIDTH_C-1:0] c;
    begin

      if (C_EXT > 0) begin
        align_c[47 -: C_EXT] = {C_EXT{c[WIDTH_C-1]}};
      end
      if (C_BOT < 0) begin

        align_c[C_TOP:0] = c[WIDTH_C-1:(-C_BOT)];
      end else begin

        align_c[C_TOP:C_BOT] = c;
        if (C_BOT > 0) begin
          align_c[C_BOT-1:0] = {C_BOT{1'b0}};
        end
      end
    end
  endfunction
function automatic [47:0] align_c;

    input [WIDTH_C-1:0] c;
    begin

      if (C_EXT > 0) begin
        align_c[47 -: C_EXT] = {C_EXT{c[WIDTH_C-1]}};
      end
      if (C_BOT < 0) begin

        align_c[C_TOP:0] = c[WIDTH_C-1:(-C_BOT)];
      end else begin

        align_c[C_TOP:C_BOT] = c;
        if (C_BOT > 0) begin
          align_c[C_BOT-1:0] = {C_BOT{1'b0}};
        end
      end
    end
  endfunction