data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v
 line:100: before: "begin"
1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n             ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n            ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.extend\n    Imm={{16{0}},halfImm[15:0]};\n                ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n                                                                                                    : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n                                                                                              : ... In instance multicpu.alu\n   zero = ALUResult ? 0 : 1;\n                    ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multicpu(
    input clk,rst
    );
    wire PCWre,InsMemRW,IRWre,WrRegDSrc,ExtSel,RegWre,ALUSrcA,ALUSrcB,RD,WR,ALUM2Reg,zero;
        wire [1:0] RegDst,PCSrc;
        wire [2:0] ALUOp,state;
        wire [4:0] rs,rt,rd,sa;
        wire [5:0] op;
        wire [15:0] halfImmediate;
        wire [25:0] addr26;
        wire [31:0] IAddr,IR_in,instruction,immediate,RegData1,RegData2,AData,BData,DataIn,DAddr,DataOut,result,ALUM2DR_in,ALUM2DR_out,PC4,WriteData,alu_a,alu_b,addr32;
        
        assign PC4=IAddr+4;
        assign op=instruction[31:26];
        assign rs=instruction[25:21];
        assign rt=instruction[20:16];
        assign rd=instruction[15:11];
        assign sa=instruction[15:11];
        assign addr26=instruction[25:0];
        assign halfImmediate=instruction[15:0];
        assign WriteData=WrRegDSrc ? ALUM2DR_out:PC4;
        assign ALUM2DR_in=ALUM2Reg? DataOut:result;
        assign DataIn=BData;
        
        pc pc(clk,rst,PCWre,PCSrc,immediate,RegData1,addr32,IAddr);
        alu alu(AData,BData,immediate,sa,ALUOp,ALUSrcA,ALUSrcB,zero,result);
        extend extend(ExtSel,halfImmediate,immediate);
        IR ir(IRWre,clk,IR_in,instruction);
        DataLate ADR(RegData1,clk,AData);
        DataLate BDR(RegData2,clk,BData);
        DataLate ALUM2DR(ALUM2DR_in,clk,ALUM2DR_out);
        DataLate ALUout(result,clk,DAddr);
        DataMemory DataMemory(DAddr,DataIn,RD,WR,DataOut);
        InstructionMemory InsMemory(IAddr,InsMemRW,IR_in);
        RegisterFile register(rs,rt,rd,WriteData,RegDst,clk,RegWre,RegData1,RegData2);
        pcaddr pcaddr(addr26,IAddr,addr32);
        ControlUnit ControlUnit(clk,zero,rst,op,WrRegDSrc, ExtSel, RegWre, ALUSrcB, ALUSrcA, InsMemRW, IRWre, RD, WR, ALUM2Reg, PCWre,ALUOp,RegDst, PCSrc);

endmodule
module multicpu(
    input clk,rst
    );

    wire PCWre,InsMemRW,IRWre,WrRegDSrc,ExtSel,RegWre,ALUSrcA,ALUSrcB,RD,WR,ALUM2Reg,zero;
        wire [1:0] RegDst,PCSrc;
        wire [2:0] ALUOp,state;
        wire [4:0] rs,rt,rd,sa;
        wire [5:0] op;
        wire [15:0] halfImmediate;
        wire [25:0] addr26;
        wire [31:0] IAddr,IR_in,instruction,immediate,RegData1,RegData2,AData,BData,DataIn,DAddr,DataOut,result,ALUM2DR_in,ALUM2DR_out,PC4,WriteData,alu_a,alu_b,addr32;
        
        assign PC4=IAddr+4;
        assign op=instruction[31:26];
        assign rs=instruction[25:21];
        assign rt=instruction[20:16];
        assign rd=instruction[15:11];
        assign sa=instruction[15:11];
        assign addr26=instruction[25:0];
        assign halfImmediate=instruction[15:0];
        assign WriteData=WrRegDSrc ? ALUM2DR_out:PC4;
        assign ALUM2DR_in=ALUM2Reg? DataOut:result;
        assign DataIn=BData;
        
        pc pc(clk,rst,PCWre,PCSrc,immediate,RegData1,addr32,IAddr);
        alu alu(AData,BData,immediate,sa,ALUOp,ALUSrcA,ALUSrcB,zero,result);
        extend extend(ExtSel,halfImmediate,immediate);
        IR ir(IRWre,clk,IR_in,instruction);
        DataLate ADR(RegData1,clk,AData);
        DataLate BDR(RegData2,clk,BData);
        DataLate ALUM2DR(ALUM2DR_in,clk,ALUM2DR_out);
        DataLate ALUout(result,clk,DAddr);
        DataMemory DataMemory(DAddr,DataIn,RD,WR,DataOut);
        InstructionMemory InsMemory(IAddr,InsMemRW,IR_in);
        RegisterFile register(rs,rt,rd,WriteData,RegDst,clk,RegWre,RegData1,RegData2);
        pcaddr pcaddr(addr26,IAddr,addr32);
        ControlUnit ControlUnit(clk,zero,rst,op,WrRegDSrc, ExtSel, RegWre, ALUSrcB, ALUSrcA, InsMemRW, IRWre, RD, WR, ALUM2Reg, PCWre,ALUOp,RegDst, PCSrc);

endmodule