data/full_repos/permissive/106408053/verilog/async_fifo.v
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1: b'%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:175: Cannot find include file: gray.v\n`include "gray.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.v\n             data/full_repos/permissive/106408053/verilog,data/full_repos/permissive/106408053/gray.v.sv\n             gray.v\n             gray.v.v\n             gray.v.sv\n             obj_dir/gray.v\n             obj_dir/gray.v.v\n             obj_dir/gray.v.sv\n%Error: data/full_repos/permissive/106408053/verilog/async_fifo.v:306: Cannot find include file: gray.v\n`include "gray.v" \n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:225: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:253: Unsupported: Ignoring delay on this delayed statement.\n          #1; \n          ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:266: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:353: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/106408053/verilog/async_fifo.v:387: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n'
module async_fifo_rdpath (
  clk, reset, 
  read_req, data_avail, 
  data_valid, data_out,
  ram_rdenb, ram_rdaddr, ram_rddata,
  stable_wrptr, stable_rdptr);

parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;

input clk, reset;


input read_req;
output data_avail, data_valid;
output [ASYNC_FIFO_MAXDATA:0] data_out;


output ram_rdenb;
output [ASYNC_FIFO_MAXINDEX:0] ram_rdaddr;
input [ASYNC_FIFO_MAXDATA:0] ram_rddata;


input [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr;
output [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr;

localparam WIDTH = ASYNC_FIFO_MAXINDEX+2;
`include "gray.v"





reg [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr, next_stable_rdptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] wrptr, next_wrptr;

reg data_avail, next_data_avail;
reg data_valid, next_data_valid;
reg [ASYNC_FIFO_MAXINDEX+1:0] rdptr, next_rdptr;
reg [ASYNC_FIFO_MAXDATA:0] data_out, next_data_out;

wire ram_rdenb = data_avail;
reg [ASYNC_FIFO_MAXINDEX:0] ram_rdaddr;

wire [ASYNC_FIFO_MAXINDEX+1:0] rdptr_plus1 = rdptr+1'b1;

wire [ASYNC_FIFO_MAXINDEX+1:0] gray_wrptr;
full_synchronizer #(WIDTH) sync_gray_wrptr (clk, reset, stable_wrptr, gray_wrptr);





initial
begin
  stable_rdptr = 0;
  wrptr = 0;
end
always @ (posedge clk or posedge reset)
begin
  if (reset)
    begin
      stable_rdptr = 0;
      wrptr = 0;
    end
  else
    begin
      stable_rdptr = next_stable_rdptr;
      wrptr = next_wrptr;
    end
end

always @(*)
begin
  #1;
  next_stable_rdptr = bin2gray(rdptr);
  next_wrptr = gray2bin(gray_wrptr);
end





initial 
begin
  rdptr = 0;
  data_avail = 1'b0;
  data_valid = 1'b0;
end
always @ (posedge clk or posedge reset)
begin
  if (reset) 
    begin
      rdptr = 0;
      data_avail = 1'b0;
      data_valid = 1'b0;
    end
  else
    begin
      rdptr = next_rdptr;
      data_avail = next_data_avail;
      data_valid = next_data_valid;
    end
end
always @ (posedge clk) data_out = next_data_out;

always @(*)
begin
  #1;
  next_rdptr = rdptr;
  next_data_out = {(ASYNC_FIFO_MAXDATA+1){data_avail}} & ram_rddata;
  next_data_valid = 1'b0;

  if (read_req && data_avail)
    begin
      next_data_valid = 1'b1;
      next_rdptr = rdptr_plus1;
    end

  next_data_avail = (next_wrptr != next_rdptr);
  ram_rdaddr = next_rdptr[ASYNC_FIFO_MAXINDEX:0];
end
endmodule
module async_fifo_rdpath (
  clk, reset, 
  read_req, data_avail, 
  data_valid, data_out,
  ram_rdenb, ram_rdaddr, ram_rddata,
  stable_wrptr, stable_rdptr);


parameter ASYNC_FIFO_MAXINDEX = 3;
parameter ASYNC_FIFO_MAXDATA = 31;

input clk, reset;


input read_req;
output data_avail, data_valid;
output [ASYNC_FIFO_MAXDATA:0] data_out;


output ram_rdenb;
output [ASYNC_FIFO_MAXINDEX:0] ram_rdaddr;
input [ASYNC_FIFO_MAXDATA:0] ram_rddata;


input [ASYNC_FIFO_MAXINDEX+1:0] stable_wrptr;
output [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr;

localparam WIDTH = ASYNC_FIFO_MAXINDEX+2;
`include "gray.v"





reg [ASYNC_FIFO_MAXINDEX+1:0] stable_rdptr, next_stable_rdptr;
reg [ASYNC_FIFO_MAXINDEX+1:0] wrptr, next_wrptr;

reg data_avail, next_data_avail;
reg data_valid, next_data_valid;
reg [ASYNC_FIFO_MAXINDEX+1:0] rdptr, next_rdptr;
reg [ASYNC_FIFO_MAXDATA:0] data_out, next_data_out;

wire ram_rdenb = data_avail;
reg [ASYNC_FIFO_MAXINDEX:0] ram_rdaddr;

wire [ASYNC_FIFO_MAXINDEX+1:0] rdptr_plus1 = rdptr+1'b1;

wire [ASYNC_FIFO_MAXINDEX+1:0] gray_wrptr;
full_synchronizer #(WIDTH) sync_gray_wrptr (clk, reset, stable_wrptr, gray_wrptr);





initial
begin
  stable_rdptr = 0;
  wrptr = 0;
end
always @ (posedge clk or posedge reset)
begin
  if (reset)
    begin
      stable_rdptr = 0;
      wrptr = 0;
    end
  else
    begin
      stable_rdptr = next_stable_rdptr;
      wrptr = next_wrptr;
    end
end

always @(*)
begin
  #1;
  next_stable_rdptr = bin2gray(rdptr);
  next_wrptr = gray2bin(gray_wrptr);
end





initial 
begin
  rdptr = 0;
  data_avail = 1'b0;
  data_valid = 1'b0;
end
always @ (posedge clk or posedge reset)
begin
  if (reset) 
    begin
      rdptr = 0;
      data_avail = 1'b0;
      data_valid = 1'b0;
    end
  else
    begin
      rdptr = next_rdptr;
      data_avail = next_data_avail;
      data_valid = next_data_valid;
    end
end
always @ (posedge clk) data_out = next_data_out;

always @(*)
begin
  #1;
  next_rdptr = rdptr;
  next_data_out = {(ASYNC_FIFO_MAXDATA+1){data_avail}} & ram_rddata;
  next_data_valid = 1'b0;

  if (read_req && data_avail)
    begin
      next_data_valid = 1'b1;
      next_rdptr = rdptr_plus1;
    end

  next_data_avail = (next_wrptr != next_rdptr);
  ram_rdaddr = next_rdptr[ASYNC_FIFO_MAXINDEX:0];
end
endmodule