data/full_repos/permissive/112823543/Avalon_LedPanel _Client_Server/LedMemoryServer_Avalon.v
1: b'%Error: Cannot find file containing module: _Client_Server,data/full_repos/permissive/112823543\n        ... Looked in:\n             data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543\n             data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.v\n             data/full_repos/permissive/112823543/Avalon_LedPanel/_Client_Server,data/full_repos/permissive/112823543.sv\n             _Client_Server,data/full_repos/permissive/112823543\n             _Client_Server,data/full_repos/permissive/112823543.v\n             _Client_Server,data/full_repos/permissive/112823543.sv\n             obj_dir/_Client_Server,data/full_repos/permissive/112823543\n             obj_dir/_Client_Server,data/full_repos/permissive/112823543.v\n             obj_dir/_Client_Server,data/full_repos/permissive/112823543.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/112823543/Avalon_LedPanel\n%Error: Cannot find file containing module: _Client_Server/LedMemoryServer_Avalon.v\n%Error: Exiting due to 3 error(s)\n'
module LedPanelServer_Avalon #(

		parameter	DISPLAY_ROWS_LINES = 4,
		parameter	DISPLAY_COLS_LINES = 6,
		parameter	COLOR_BITS		   = 8
	) (

		input 	wire				clock,
		input	wire				reset,


		input	wire	[1:0]		s0_address,
		input	wire				s0_write,
		input	wire	[31:0]		s0_writedata,
		input	wire				s0_read,
		output	reg		[31:0]		s0_readdata,
		
		output	wire				irq,
		

		input 	wire				ext_clock200,


		output	wire [DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES-1:0]				memAddrMst,
		output	wire [2:0]			bitplaneMst,
		output 	wire 				backbufferMst,

		output	wire [3:0] 			ADDR_MST,
		output  wire				LATCH_MST,
		output  wire				CLK_LED_MST,
		output 	wire				BLANK_MST
	);

	localparam			major_version = 1;
	localparam			minor_version = 5;

	



























	reg								backbuffer;
	reg								flip_backbuffer;
	wire							v_sync;
	reg								v_sync_q;
	wire	[7:0]					reg_stat = {flip_backbuffer, 5'b00000, backbuffer, v_sync_q};
	

	reg		[7:0]					reg_irq;
	wire							irq_ena		= reg_irq[7];
	wire							irq_latch	= reg_irq[0];


	reg		[1:0]					v_sync_edge_detect;
	reg 							req_backbuffer_flip;
	
	assign 	irq = irq_ena && irq_latch;


	assign 	backbufferMst = backbuffer;



	always @(posedge clock)
		begin
			if (reset) begin
				backbuffer <= 1'b0;
				flip_backbuffer <= 1'b0;
				reg_irq  <= 8'h00;
			end else begin

				if (s0_address == 2'b01) begin
					if (s0_read) begin
						s0_readdata <= {24'b0, reg_irq};
					end else if (s0_write) begin
						reg_irq[7] 	 <= s0_writedata[7];
						reg_irq[0] <= 1'b0;
					end
				end else if (s0_address == 2'b00) begin

					if (s0_read) begin
						s0_readdata <= {24'b0, reg_stat};
					end else if (s0_write) begin
						flip_backbuffer <= s0_writedata[7];
					end
				end else if (s0_address == 2'b10) begin

					if (s0_read) begin
						s0_readdata[7:0] <= 2**DISPLAY_COLS_LINES;
						s0_readdata[15:8]<= 2**DISPLAY_ROWS_LINES;
						s0_readdata[31:16]<= 2**COLOR_BITS;
					end
				end else begin
					if (s0_read) begin
						s0_readdata[31:24] <= major_version;
						s0_readdata[23:16] <= minor_version;
					end
				end

				if (v_sync_edge_detect == 2'b01) begin
					reg_irq[0] <= 1'b1;
				end

				if (req_backbuffer_flip) begin
					backbuffer <= ~backbuffer;
					flip_backbuffer <= 0;
				end
			end
		end
	

		always @(posedge ext_clock200)
			begin
				if (reset) begin
					req_backbuffer_flip <= 1'b0;
					v_sync_q <= 1'b0;
					v_sync_edge_detect <= 2'b00;
				end else begin
					v_sync_q <= v_sync;

					v_sync_edge_detect <= {v_sync_edge_detect[0], v_sync_q};
					if ((v_sync_edge_detect == 2'b01) && (flip_backbuffer) ) begin
							req_backbuffer_flip <= 1'b1;
					end else if (req_backbuffer_flip && !flip_backbuffer) begin
						req_backbuffer_flip <= 1'b0;
					end
				end
			end
	
		LedPanelServer #(
			.COLOR_BITS(COLOR_BITS),
			.DISPLAY_ROWS_LINES(DISPLAY_ROWS_LINES),
			.DISPLAY_COLS_LINES(DISPLAY_COLS_LINES)
		)		panel(
		.CLK(ext_clock200),
		.RST(reset),
	
		.ADDR_MST(ADDR_MST),
		.CLK_LED_MST(CLK_LED_MST),
		.BLANK_MST(BLANK_MST),
		.LATCH_MST(LATCH_MST),
		
		.v_sync(v_sync),
		.memAddrMst(memAddrMst),
		.bitplaneMst(bitplaneMst)
	);



endmodule
module LedPanelServer_Avalon #(

		parameter	DISPLAY_ROWS_LINES = 4,
		parameter	DISPLAY_COLS_LINES = 6,
		parameter	COLOR_BITS		   = 8
	) (

		input 	wire				clock,
		input	wire				reset,


		input	wire	[1:0]		s0_address,
		input	wire				s0_write,
		input	wire	[31:0]		s0_writedata,
		input	wire				s0_read,
		output	reg		[31:0]		s0_readdata,
		
		output	wire				irq,
		

		input 	wire				ext_clock200,


		output	wire [DISPLAY_COLS_LINES+DISPLAY_ROWS_LINES-1:0]				memAddrMst,
		output	wire [2:0]			bitplaneMst,
		output 	wire 				backbufferMst,

		output	wire [3:0] 			ADDR_MST,
		output  wire				LATCH_MST,
		output  wire				CLK_LED_MST,
		output 	wire				BLANK_MST
	);


	localparam			major_version = 1;
	localparam			minor_version = 5;

	



























	reg								backbuffer;
	reg								flip_backbuffer;
	wire							v_sync;
	reg								v_sync_q;
	wire	[7:0]					reg_stat = {flip_backbuffer, 5'b00000, backbuffer, v_sync_q};
	

	reg		[7:0]					reg_irq;
	wire							irq_ena		= reg_irq[7];
	wire							irq_latch	= reg_irq[0];


	reg		[1:0]					v_sync_edge_detect;
	reg 							req_backbuffer_flip;
	
	assign 	irq = irq_ena && irq_latch;


	assign 	backbufferMst = backbuffer;



	always @(posedge clock)
		begin
			if (reset) begin
				backbuffer <= 1'b0;
				flip_backbuffer <= 1'b0;
				reg_irq  <= 8'h00;
			end else begin

				if (s0_address == 2'b01) begin
					if (s0_read) begin
						s0_readdata <= {24'b0, reg_irq};
					end else if (s0_write) begin
						reg_irq[7] 	 <= s0_writedata[7];
						reg_irq[0] <= 1'b0;
					end
				end else if (s0_address == 2'b00) begin

					if (s0_read) begin
						s0_readdata <= {24'b0, reg_stat};
					end else if (s0_write) begin
						flip_backbuffer <= s0_writedata[7];
					end
				end else if (s0_address == 2'b10) begin

					if (s0_read) begin
						s0_readdata[7:0] <= 2**DISPLAY_COLS_LINES;
						s0_readdata[15:8]<= 2**DISPLAY_ROWS_LINES;
						s0_readdata[31:16]<= 2**COLOR_BITS;
					end
				end else begin
					if (s0_read) begin
						s0_readdata[31:24] <= major_version;
						s0_readdata[23:16] <= minor_version;
					end
				end

				if (v_sync_edge_detect == 2'b01) begin
					reg_irq[0] <= 1'b1;
				end

				if (req_backbuffer_flip) begin
					backbuffer <= ~backbuffer;
					flip_backbuffer <= 0;
				end
			end
		end
	

		always @(posedge ext_clock200)
			begin
				if (reset) begin
					req_backbuffer_flip <= 1'b0;
					v_sync_q <= 1'b0;
					v_sync_edge_detect <= 2'b00;
				end else begin
					v_sync_q <= v_sync;

					v_sync_edge_detect <= {v_sync_edge_detect[0], v_sync_q};
					if ((v_sync_edge_detect == 2'b01) && (flip_backbuffer) ) begin
							req_backbuffer_flip <= 1'b1;
					end else if (req_backbuffer_flip && !flip_backbuffer) begin
						req_backbuffer_flip <= 1'b0;
					end
				end
			end
	
		LedPanelServer #(
			.COLOR_BITS(COLOR_BITS),
			.DISPLAY_ROWS_LINES(DISPLAY_ROWS_LINES),
			.DISPLAY_COLS_LINES(DISPLAY_COLS_LINES)
		)		panel(
		.CLK(ext_clock200),
		.RST(reset),
	
		.ADDR_MST(ADDR_MST),
		.CLK_LED_MST(CLK_LED_MST),
		.BLANK_MST(BLANK_MST),
		.LATCH_MST(LATCH_MST),
		
		.v_sync(v_sync),
		.memAddrMst(memAddrMst),
		.bitplaneMst(bitplaneMst)
	);



endmodule