data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #(T/2);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #(T/2);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #(1.5*T);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #(T);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #(19.4*T);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #(100*T);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #(100*T);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #(100*T);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #(100*T);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #(500*T);\n    ^\n%Error: data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new/testbench.v:34: Cannot find file containing module: \'Traffic_lights_ce\'\nTraffic_lights_ce #(.DVSR(5))\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new,data/full_repos/permissive/116473298/Traffic_lights_ce\n             data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new,data/full_repos/permissive/116473298/Traffic_lights_ce.v\n             data/full_repos/permissive/116473298/Traffic_lights_comprehensive_experiment.srcs/sim_1/new,data/full_repos/permissive/116473298/Traffic_lights_ce.sv\n             Traffic_lights_ce\n             Traffic_lights_ce.v\n             Traffic_lights_ce.sv\n             obj_dir/Traffic_lights_ce\n             obj_dir/Traffic_lights_ce.v\n             obj_dir/Traffic_lights_ce.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
reg clk;
reg reset;
reg go;
reg emergency;
wire [7:0] sseg;
wire [3:0] an;
wire redout_2,yellowout_2,greenout_2;
wire redout_1,yellowout_1,greenout_1;
wire s_tick;

Traffic_lights_ce #(.DVSR(5))
U_Traffic_lights_ce
(
.clk(clk),
.reset(reset),
.go(go),
.emergency(emergency),
.sseg(sseg),
.an(an),
.redout_2(redout_2),
.yellowout_2(yellowout_2),
.greenout_2(greenout_2),
.redout_1(redout_1),
.yellowout_1(yellowout_1),
.greenout_1(greenout_1)
);

parameter T = 4;

always begin
    clk = 1'b1;
    #(T/2);
    clk = 1'b0;
    #(T/2);
end

initial begin
    reset = 1'b1;
    emergency = 1'b0;
    go = 1'b0;
    #(1.5*T);
    reset = 1'b0;
    #(T);
    go = 1'b1;
    #(19.4*T);
    emergency = 1'b0;
    #(100*T);
    emergency = 1'b0;
    #(100*T);
    go = 1'b0;
    #(100*T);
    go = 1'b1;
    #(100*T);
    emergency = 1'b1;
    #(500*T);
    emergency = 1'b0;
    
end

endmodule
module testbench();

reg clk;
reg reset;
reg go;
reg emergency;
wire [7:0] sseg;
wire [3:0] an;
wire redout_2,yellowout_2,greenout_2;
wire redout_1,yellowout_1,greenout_1;
wire s_tick;

Traffic_lights_ce #(.DVSR(5))
U_Traffic_lights_ce
(
.clk(clk),
.reset(reset),
.go(go),
.emergency(emergency),
.sseg(sseg),
.an(an),
.redout_2(redout_2),
.yellowout_2(yellowout_2),
.greenout_2(greenout_2),
.redout_1(redout_1),
.yellowout_1(yellowout_1),
.greenout_1(greenout_1)
);

parameter T = 4;

always begin
    clk = 1'b1;
    #(T/2);
    clk = 1'b0;
    #(T/2);
end

initial begin
    reset = 1'b1;
    emergency = 1'b0;
    go = 1'b0;
    #(1.5*T);
    reset = 1'b0;
    #(T);
    go = 1'b1;
    #(19.4*T);
    emergency = 1'b0;
    #(100*T);
    emergency = 1'b0;
    #(100*T);
    go = 1'b0;
    #(100*T);
    go = 1'b1;
    #(100*T);
    emergency = 1'b1;
    #(500*T);
    emergency = 1'b0;
    
end

endmodule