data/full_repos/permissive/117026779/src/ServoModule.v
1: b'%Warning-WIDTH: data/full_repos/permissive/117026779/src/ServoModule.v:64: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'data\' generates 16 bits.\n                                                                         : ... In instance ServoModule\n        tmp_compare_value = data;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ServoModule(
	input wire clk,
	input wire rst,
	input wire load,
	input wire [15:0] data,
	output reg signal
);



parameter MAX_COUNT    = 20000*100;

parameter COUNT_WIDTH  = 32;



reg  [COUNT_WIDTH-1:0] counter;
reg  [COUNT_WIDTH-1:0] compare_value;
reg  [COUNT_WIDTH-1:0] tmp_compare_value;














always @(posedge clk or
		 posedge rst) begin
    if (rst) begin
        counter = 0;
        compare_value = 0;
        tmp_compare_value = 0;
    end
    else if(load) begin
        tmp_compare_value = data;
    end
    else begin
        if(counter > MAX_COUNT) begin
        	compare_value = tmp_compare_value;
	        counter = 0;
        	signal = 1;
        end
        if(counter >= compare_value*100) begin
        	signal = 0;
        end
	    counter = counter + 1;
    end
end

endmodule
module ServoModule(
	input wire clk,
	input wire rst,
	input wire load,
	input wire [15:0] data,
	output reg signal
);




parameter MAX_COUNT    = 20000*100;

parameter COUNT_WIDTH  = 32;



reg  [COUNT_WIDTH-1:0] counter;
reg  [COUNT_WIDTH-1:0] compare_value;
reg  [COUNT_WIDTH-1:0] tmp_compare_value;














always @(posedge clk or
		 posedge rst) begin
    if (rst) begin
        counter = 0;
        compare_value = 0;
        tmp_compare_value = 0;
    end
    else if(load) begin
        tmp_compare_value = data;
    end
    else begin
        if(counter > MAX_COUNT) begin
        	compare_value = tmp_compare_value;
	        counter = 0;
        	signal = 1;
        end
        if(counter >= compare_value*100) begin
        	signal = 0;
        end
	    counter = counter + 1;
    end
end

endmodule