data/full_repos/permissive/168395472/labs/04_devboard/top.v
data/verilator_xmls/ab1deee1-c819-4e11-a1f0-ca0279198227.xml
module top(
    input CLK,

    output DS_C,
	 output DS_EN1, DS_EN2, DS_EN3, DS_EN4
);

assign {DS_EN1, DS_EN2, DS_EN3, DS_EN4} = 4'b1111;

blink_gen blink_gen(.clk(CLK), .clk2(DS_C));

endmodule
module top(
    input CLK,

    output DS_C,
	 output DS_EN1, DS_EN2, DS_EN3, DS_EN4
);


assign {DS_EN1, DS_EN2, DS_EN3, DS_EN4} = 4'b1111;

blink_gen blink_gen(.clk(CLK), .clk2(DS_C));

endmodule