data/full_repos/permissive/211316121/lab8_2_nexys4/Display.v
data/verilator_xmls/6768e043-c1d4-4bd6-ae9b-77158dc57bba.xml
module RAM(
    input clk,
    input wr,
    input clr,
    input [3:0] din,
    input [3:0] addr,
    output [3:0] qout
);
reg [3:0] mem [15:0];
always@(posedge clk)
    if(clr)
    begin
        mem[0]<='b0000;mem[1]<='b0000;mem[2]<='b0000;mem[3]<='b0000;
        mem[4]<='b0000;mem[5]<='b0000;mem[6]<='b0000;mem[7]<='b0000;
        mem[8]<='b0000;mem[9]<='b0000;mem[10]<='b0000;mem[11]<='b0000;
        mem[12]<='b0000;mem[13]<='b0000;mem[14]<='b0000;mem[15]<='b0000;
    end
    else 
    begin
        if(wr)
            mem[addr]<=din;
    end
assign qout=mem[addr];
endmodule
module RAM(
    input clk,
    input wr,
    input clr,
    input [3:0] din,
    input [3:0] addr,
    output [3:0] qout
);

reg [3:0] mem [15:0];
always@(posedge clk)
    if(clr)
    begin
        mem[0]<='b0000;mem[1]<='b0000;mem[2]<='b0000;mem[3]<='b0000;
        mem[4]<='b0000;mem[5]<='b0000;mem[6]<='b0000;mem[7]<='b0000;
        mem[8]<='b0000;mem[9]<='b0000;mem[10]<='b0000;mem[11]<='b0000;
        mem[12]<='b0000;mem[13]<='b0000;mem[14]<='b0000;mem[15]<='b0000;
    end
    else 
    begin
        if(wr)
            mem[addr]<=din;
    end
assign qout=mem[addr];
endmodule