data/full_repos/permissive/159830616/YJ431_PL.srcs/sources_1/new/FB_QEI.v
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1: b'%Warning-MULTITOP: data/full_repos/permissive/159830616/YJ431_PL.srcs/sources_1/new/FB_QEI.v:119: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'FB_QEIREG\'\nmodule FB_QEIREG(\n       ^~~~~~~~~\n                                                                                                : ... Top module \'QEI\'\nmodule QEI(\n       ^~~\n%Error: Exiting due to 1 warning(s)\n'
module FB_QEIREG(
 	RST_n,
	BUS_ADDR,
	BUS_DATA,
	BUS_CS,

	BUS_read,
	BUS_write,

	QEI_BASE,


	QEI_CLEAR_Reg,
	QEI_CH0_Read,
	QEI_CH1_Read,
	QEI_CH2_Read,
	QEI_CH3_Read

    );


input RST_n;
input [31:0] BUS_ADDR;
inout [31:0] BUS_DATA;
input BUS_CS;

input BUS_read;
input BUS_write;

input [9:0] QEI_BASE;

output reg [31:0] QEI_CLEAR_Reg = 32'd0;
input [31:0] QEI_CH0_Read;
input [31:0] QEI_CH1_Read;
input [31:0] QEI_CH2_Read;
input [31:0] QEI_CH3_Read;

wire AD_TRI_n;
wire ADD_COMF;

reg [31:0] BUS_DATA_REG = 32'b0;

assign ADD_COMF = ( BUS_ADDR[31:22] == QEI_BASE[9:0] ) ? 1'b1:1'b0;
assign AD_TRI_n = ADD_COMF & ~BUS_CS & BUS_read ;



assign BUS_DATA = AD_TRI_n ? BUS_DATA_REG : 32'bz;



always@( posedge BUS_CS or negedge RST_n )
if ( !RST_n ) begin
	QEI_CLEAR_Reg <= 32'd0;
end

else begin
	if ( ADD_COMF && BUS_write == 1'b1) begin
        case(BUS_ADDR[21:0])
            22'b00000: begin
                QEI_CLEAR_Reg [31:0] <= BUS_DATA [31:0];
            end
        endcase
	end
end



always@( negedge BUS_CS or negedge RST_n )
if ( !RST_n ) begin

end

else begin
	if ( ADD_COMF && BUS_write == 1'b0) begin
        case(BUS_ADDR[21:0])
            22'b00000:
                BUS_DATA_REG[31:0] <= QEI_CLEAR_Reg[31:0];
            22'b00100:
                BUS_DATA_REG[31:0] <= QEI_CH0_Read[31:0];
            22'b01000:
                BUS_DATA_REG[31:0] <= QEI_CH1_Read[31:0];
            22'b01100:
                BUS_DATA_REG[31:0] <= QEI_CH2_Read[31:0];
            22'b10000:
                BUS_DATA_REG[31:0] <= QEI_CH3_Read[31:0];
            default:
                BUS_DATA_REG[31:0] <=32'hffffffff;
        endcase
	end
end


endmodule
module FB_QEIREG(
 	RST_n,
	BUS_ADDR,
	BUS_DATA,
	BUS_CS,

	BUS_read,
	BUS_write,

	QEI_BASE,


	QEI_CLEAR_Reg,
	QEI_CH0_Read,
	QEI_CH1_Read,
	QEI_CH2_Read,
	QEI_CH3_Read

    );



input RST_n;
input [31:0] BUS_ADDR;
inout [31:0] BUS_DATA;
input BUS_CS;

input BUS_read;
input BUS_write;

input [9:0] QEI_BASE;

output reg [31:0] QEI_CLEAR_Reg = 32'd0;
input [31:0] QEI_CH0_Read;
input [31:0] QEI_CH1_Read;
input [31:0] QEI_CH2_Read;
input [31:0] QEI_CH3_Read;

wire AD_TRI_n;
wire ADD_COMF;

reg [31:0] BUS_DATA_REG = 32'b0;

assign ADD_COMF = ( BUS_ADDR[31:22] == QEI_BASE[9:0] ) ? 1'b1:1'b0;
assign AD_TRI_n = ADD_COMF & ~BUS_CS & BUS_read ;



assign BUS_DATA = AD_TRI_n ? BUS_DATA_REG : 32'bz;



always@( posedge BUS_CS or negedge RST_n )
if ( !RST_n ) begin
	QEI_CLEAR_Reg <= 32'd0;
end

else begin
	if ( ADD_COMF && BUS_write == 1'b1) begin
        case(BUS_ADDR[21:0])
            22'b00000: begin
                QEI_CLEAR_Reg [31:0] <= BUS_DATA [31:0];
            end
        endcase
	end
end



always@( negedge BUS_CS or negedge RST_n )
if ( !RST_n ) begin

end

else begin
	if ( ADD_COMF && BUS_write == 1'b0) begin
        case(BUS_ADDR[21:0])
            22'b00000:
                BUS_DATA_REG[31:0] <= QEI_CLEAR_Reg[31:0];
            22'b00100:
                BUS_DATA_REG[31:0] <= QEI_CH0_Read[31:0];
            22'b01000:
                BUS_DATA_REG[31:0] <= QEI_CH1_Read[31:0];
            22'b01100:
                BUS_DATA_REG[31:0] <= QEI_CH2_Read[31:0];
            22'b10000:
                BUS_DATA_REG[31:0] <= QEI_CH3_Read[31:0];
            default:
                BUS_DATA_REG[31:0] <=32'hffffffff;
        endcase
	end
end


endmodule