data/full_repos/permissive/109209652/verilog/convolve_census/sp_census.v
1: b'%Warning-WIDTH: data/full_repos/permissive/109209652/verilog/convolve_census/sp_census.v:61: Operator OR expects 1600 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                           : ... In instance sp_census\n    is_buf_val <= (is_buf_val << 1) |  1\'b1;\n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/109209652/verilog/convolve_census/sp_census.v:88: Cannot find file containing module: \'shift_reg\'\n          shift_reg #(8, ROW_SZ-CEN_SZ) row_shift_buf(\n          ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109209652/verilog/convolve_census,data/full_repos/permissive/109209652/shift_reg\n             data/full_repos/permissive/109209652/verilog/convolve_census,data/full_repos/permissive/109209652/shift_reg.v\n             data/full_repos/permissive/109209652/verilog/convolve_census,data/full_repos/permissive/109209652/shift_reg.sv\n             shift_reg\n             shift_reg.v\n             shift_reg.sv\n             obj_dir/shift_reg\n             obj_dir/shift_reg.v\n             obj_dir/shift_reg.sv\n%Error: data/full_repos/permissive/109209652/verilog/convolve_census/sp_census.v:78: Cannot find file containing module: \'shift_reg\'\n          shift_reg #(8, ROW_SZ-CEN_SZ) row_shift_buf(\n          ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module sp_census #(parameter ROW_SZ = 320, parameter COL_SZ = 240)(
	input		clk,
	input		reset,
	input		[7:0]	thresh,

	input		[7:0]	in_val,
	input		[9:0]	in_x,
	input		[9:0]	in_y,
	input				is_in_val,

	output		[7:0]	out_val,
	output		[9:0]	out_x,
	output		[9:0]	out_y,
	output				is_out_val
);

	localparam CEN_SZ = 5;



	reg		[7:0] conv_r [(CEN_SZ*CEN_SZ)-1 : 0];



	wire	[7:0] carry_over_wires [CEN_SZ-2 : 0];



	reg		[(ROW_SZ*CEN_SZ)-1 : 0] is_buf_val;



	reg		[9:0] in_x_reg;
	reg		[9:0] in_y_reg;

	always@ (posedge clk) begin
		if (is_in_val) begin
			in_x_reg <= in_x;
			in_y_reg <= in_y;
		end
	end


	reg		[7:0] threshold;
	always @(posedge clk) begin
		threshold <= thresh;
	end


	assign out_x = in_x_reg < (ROW_SZ-(CEN_SZ/2)-1) ? (in_x_reg + ROW_SZ) - (ROW_SZ-(CEN_SZ/2)-1) : in_x_reg - (ROW_SZ-(CEN_SZ/2)-1);
	assign out_y = out_x <= (CEN_SZ/2) ? (in_y_reg < 1 ? COL_SZ-1 : in_y_reg-1) : (in_y_reg < 2 ? COL_SZ-2+in_y_reg : in_y_reg-2);


	always@ (posedge clk) begin
		if (reset) begin
			is_buf_val <= 0;
		end
		else begin
			if (is_in_val) begin
				is_buf_val <= (is_buf_val << 1) |  1'b1;
			end
		end
	end


	assign is_out_val = is_in_val & is_buf_val[ROW_SZ*(CEN_SZ/2) + (ROW_SZ-CEN_SZ) + (CEN_SZ/2)];


	genvar i, j;
	generate
	    for (i = 0; i < CEN_SZ; i = i + 1) begin: SHIFT_BUF
	    	wire [7:0] row_buf_sr_out;


	        if (i == CEN_SZ-1) begin

	        	shift_reg #(8, ROW_SZ-CEN_SZ) row_shift_buf(
					.clk(clk), 
					.shift(is_in_val),
					.sr_in(in_val),
					.sr_out(row_buf_sr_out)
				);
				
	        end
	        else begin
	        	
	        	shift_reg #(8, ROW_SZ-CEN_SZ) row_shift_buf(
					.clk(clk), 
					.shift(is_in_val),
					.sr_in(carry_over_wires[i]),
					.sr_out(row_buf_sr_out)
				);

	        end


	        for (j = 0; j < CEN_SZ; j = j + 1) begin: CONV_REGS

				if (j == 0) begin
					if(i != 0) begin
						assign carry_over_wires[i-1] = conv_r[CEN_SZ*i + j];
					end

					always@ (posedge clk) begin
						if (is_in_val) begin
							conv_r[CEN_SZ*i + j] <= conv_r[CEN_SZ*i + (j+1)];
						end
					end

				end

				else if (j == CEN_SZ-1) begin

					always@ (posedge clk) begin
						if (is_in_val) begin
							conv_r[CEN_SZ*i + j] <= row_buf_sr_out;
						end
					end

				end
				else begin

					always@ (posedge clk) begin
						if (is_in_val) begin
							conv_r[CEN_SZ*i + j] <= conv_r[CEN_SZ*i + (j+1)];
						end
					end

				end
			end
	        
	    end
	endgenerate


	assign out_val[0] = (conv_r[CEN_SZ*0 + 0] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[1] = (conv_r[CEN_SZ*0 + 2] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[2] = (conv_r[CEN_SZ*0 + 4] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[3] = (conv_r[CEN_SZ*2 + 0] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[4] = (conv_r[CEN_SZ*2 + 4] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[5] = (conv_r[CEN_SZ*4 + 0] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[6] = (conv_r[CEN_SZ*4 + 2] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[7] = (conv_r[CEN_SZ*4 + 4] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;

endmodule
module sp_census #(parameter ROW_SZ = 320, parameter COL_SZ = 240)(
	input		clk,
	input		reset,
	input		[7:0]	thresh,

	input		[7:0]	in_val,
	input		[9:0]	in_x,
	input		[9:0]	in_y,
	input				is_in_val,

	output		[7:0]	out_val,
	output		[9:0]	out_x,
	output		[9:0]	out_y,
	output				is_out_val
);


	localparam CEN_SZ = 5;



	reg		[7:0] conv_r [(CEN_SZ*CEN_SZ)-1 : 0];



	wire	[7:0] carry_over_wires [CEN_SZ-2 : 0];



	reg		[(ROW_SZ*CEN_SZ)-1 : 0] is_buf_val;



	reg		[9:0] in_x_reg;
	reg		[9:0] in_y_reg;

	always@ (posedge clk) begin
		if (is_in_val) begin
			in_x_reg <= in_x;
			in_y_reg <= in_y;
		end
	end


	reg		[7:0] threshold;
	always @(posedge clk) begin
		threshold <= thresh;
	end


	assign out_x = in_x_reg < (ROW_SZ-(CEN_SZ/2)-1) ? (in_x_reg + ROW_SZ) - (ROW_SZ-(CEN_SZ/2)-1) : in_x_reg - (ROW_SZ-(CEN_SZ/2)-1);
	assign out_y = out_x <= (CEN_SZ/2) ? (in_y_reg < 1 ? COL_SZ-1 : in_y_reg-1) : (in_y_reg < 2 ? COL_SZ-2+in_y_reg : in_y_reg-2);


	always@ (posedge clk) begin
		if (reset) begin
			is_buf_val <= 0;
		end
		else begin
			if (is_in_val) begin
				is_buf_val <= (is_buf_val << 1) |  1'b1;
			end
		end
	end


	assign is_out_val = is_in_val & is_buf_val[ROW_SZ*(CEN_SZ/2) + (ROW_SZ-CEN_SZ) + (CEN_SZ/2)];


	genvar i, j;
	generate
	    for (i = 0; i < CEN_SZ; i = i + 1) begin: SHIFT_BUF
	    	wire [7:0] row_buf_sr_out;


	        if (i == CEN_SZ-1) begin

	        	shift_reg #(8, ROW_SZ-CEN_SZ) row_shift_buf(
					.clk(clk), 
					.shift(is_in_val),
					.sr_in(in_val),
					.sr_out(row_buf_sr_out)
				);
				
	        end
	        else begin
	        	
	        	shift_reg #(8, ROW_SZ-CEN_SZ) row_shift_buf(
					.clk(clk), 
					.shift(is_in_val),
					.sr_in(carry_over_wires[i]),
					.sr_out(row_buf_sr_out)
				);

	        end


	        for (j = 0; j < CEN_SZ; j = j + 1) begin: CONV_REGS

				if (j == 0) begin
					if(i != 0) begin
						assign carry_over_wires[i-1] = conv_r[CEN_SZ*i + j];
					end

					always@ (posedge clk) begin
						if (is_in_val) begin
							conv_r[CEN_SZ*i + j] <= conv_r[CEN_SZ*i + (j+1)];
						end
					end

				end

				else if (j == CEN_SZ-1) begin

					always@ (posedge clk) begin
						if (is_in_val) begin
							conv_r[CEN_SZ*i + j] <= row_buf_sr_out;
						end
					end

				end
				else begin

					always@ (posedge clk) begin
						if (is_in_val) begin
							conv_r[CEN_SZ*i + j] <= conv_r[CEN_SZ*i + (j+1)];
						end
					end

				end
			end
	        
	    end
	endgenerate


	assign out_val[0] = (conv_r[CEN_SZ*0 + 0] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[1] = (conv_r[CEN_SZ*0 + 2] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[2] = (conv_r[CEN_SZ*0 + 4] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[3] = (conv_r[CEN_SZ*2 + 0] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[4] = (conv_r[CEN_SZ*2 + 4] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[5] = (conv_r[CEN_SZ*4 + 0] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[6] = (conv_r[CEN_SZ*4 + 2] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;
	assign out_val[7] = (conv_r[CEN_SZ*4 + 4] < conv_r[CEN_SZ*2 + 2] - threshold) ? 1'b1 : 1'b0;

endmodule