data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_rx_tb.v
 line:76: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_rx_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD/2) clk_p = 1\'b1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_rx_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD/2);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_rx_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD*128);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_rx_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD*128);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_rx_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #(PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_rx_tb.v:39: Cannot find file containing module: \'adc_rx\'\n   adc_rx adc_rx(.data_i_p(data_i_p[7:0]),\n   ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports,data/full_repos/permissive/17242406/adc_rx\n             data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports,data/full_repos/permissive/17242406/adc_rx.v\n             data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports,data/full_repos/permissive/17242406/adc_rx.sv\n             adc_rx\n             adc_rx.v\n             adc_rx.sv\n             obj_dir/adc_rx\n             obj_dir/adc_rx.v\n             obj_dir/adc_rx.sv\n%Warning-WIDTH: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_rx_tb.v:77: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                                               : ... In instance adc_rx_tb\n  data_i_p[7:0] = ({$random} % 256);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/17242406/novena-afe-hs.srcs/sources_1/imports/imports/adc_rx_tb.v:78: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                                               : ... In instance adc_rx_tb\n  data_q_p[7:0] = ({$random} % 256);\n                ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adc_rx_tb;

   reg clk_p;
   wire clk_n;
   
   reg [7:0] data_i_p;
   wire [7:0] data_i_n;

   reg [7:0]  data_q_p;
   wire [7:0] data_q_n;

   wire [63:0] adc_i;
   wire [63:0] adc_q;
   wire        oclk;

   reg 	       reset;
   
   adc_rx adc_rx(.data_i_p(data_i_p[7:0]),
		 .data_i_n(data_i_n[7:0]),
		 .data_q_p(data_q_p[7:0]),
		 .data_q_n(data_q_n[7:0]),

		 .clk_p(clk_p),
		 .clk_n(clk_n),

		 .adc_i(adc_i[63:0]),
		 .adc_q(adc_q[63:0]),
		 .oclk(oclk),

		 .reset(reset)
		 );
   
   parameter PERIOD = 16'd2;
   always begin
      clk_p = 1'b0;
      #(PERIOD/2) clk_p = 1'b1;
      #(PERIOD/2);
   end
   
   assign clk_n = !clk_p;
   assign data_i_n = ~data_i_p;
   assign data_q_n = ~data_q_p;

   initial begin
      reset = 1'b1;
      data_i_p[7:0] = 8'b0;
      data_q_p[7:0] = 8'b0;

      $stop;
      #(PERIOD*128);
      reset = 1'b0;
      #(PERIOD*128);


      repeat(1000) begin
	 data_i_p[7:0] = ({$random} % 256);
	 data_q_p[7:0] = ({$random} % 256);
	 #(PERIOD/2);
      end

      $stop;
   end
   
endmodule
module adc_rx_tb;


   reg clk_p;
   wire clk_n;
   
   reg [7:0] data_i_p;
   wire [7:0] data_i_n;

   reg [7:0]  data_q_p;
   wire [7:0] data_q_n;

   wire [63:0] adc_i;
   wire [63:0] adc_q;
   wire        oclk;

   reg 	       reset;
   
   adc_rx adc_rx(.data_i_p(data_i_p[7:0]),
		 .data_i_n(data_i_n[7:0]),
		 .data_q_p(data_q_p[7:0]),
		 .data_q_n(data_q_n[7:0]),

		 .clk_p(clk_p),
		 .clk_n(clk_n),

		 .adc_i(adc_i[63:0]),
		 .adc_q(adc_q[63:0]),
		 .oclk(oclk),

		 .reset(reset)
		 );
   
   parameter PERIOD = 16'd2;
   always begin
      clk_p = 1'b0;
      #(PERIOD/2) clk_p = 1'b1;
      #(PERIOD/2);
   end
   
   assign clk_n = !clk_p;
   assign data_i_n = ~data_i_p;
   assign data_q_n = ~data_q_p;

   initial begin
      reset = 1'b1;
      data_i_p[7:0] = 8'b0;
      data_q_p[7:0] = 8'b0;

      $stop;
      #(PERIOD*128);
      reset = 1'b0;
      #(PERIOD*128);


      repeat(1000) begin
	 data_i_p[7:0] = ({$random} % 256);
	 data_q_p[7:0] = ({$random} % 256);
	 #(PERIOD/2);
      end

      $stop;
   end
   
endmodule