data/full_repos/permissive/110151336/lab_06/src/01_counter_simple/simple_counter.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/077298fa-acf7-4834-94f3-2f0718f9cd31.xml
module simple_counter
#(
  parameter WIDTH=8
)
(
 input                  clk,
 input                  rst_n,
 output reg [WIDTH-1:0] cnt
 );
          
   always@(posedge clk or negedge rst_n)
     begin
        if(!rst_n)
          cnt <= {WIDTH{1'b0}};
        else
          cnt <= cnt + 1'b1;
     end
   
endmodule
module simple_counter
#(
  parameter WIDTH=8
)
(
 input                  clk,
 input                  rst_n,
 output reg [WIDTH-1:0] cnt
 );

          
   always@(posedge clk or negedge rst_n)
     begin
        if(!rst_n)
          cnt <= {WIDTH{1'b0}};
        else
          cnt <= cnt + 1'b1;
     end
   
endmodule