data/full_repos/permissive/157979234/Semester III/Digital Design and Computer Organization/Session 05/reg_alu.v
1: b'%Error: Cannot find file containing module: III/Digital\n        ... Looked in:\n             data/full_repos/permissive/157979234/Semester/III/Digital\n             data/full_repos/permissive/157979234/Semester/III/Digital.v\n             data/full_repos/permissive/157979234/Semester/III/Digital.sv\n             III/Digital\n             III/Digital.v\n             III/Digital.sv\n             obj_dir/III/Digital\n             obj_dir/III/Digital.v\n             obj_dir/III/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Organization/Session\n%Error: Cannot find file containing module: 05,data/full_repos/permissive/157979234\n%Error: Cannot find file containing module: data/full_repos/permissive/157979234/Semester\n%Error: Cannot find file containing module: 05/reg_alu.v\n%Error: Exiting due to 8 error(s)\n'
module reg_file (input wire clk, reset, wr, input wire [2:0] rd_addr_a, rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b);

wire [7:0] load;
wire [15:0] q0, q1, q2, q3, q4, q5, q6, q7;

demux8 dmx(wr, wr_addr[2], wr_addr[1], wr_addr[0], load);
reg16_8 rm16(clk, reset, load, d_in, q0, q1, q2, q3, q4, q5, q6, q7);
mux8_16 mx0(q0, q1, q2, q3, q4, q5, q6, q7, {rd_addr_a[2], rd_addr_a[1], rd_addr_a[0]}, d_out_a);
mux8_16 mx1(q0, q1, q2, q3, q4, q5, q6, q7, {rd_addr_b[2], rd_addr_b[1], rd_addr_b[0]}, d_out_b);

endmodule
module reg_file (input wire clk, reset, wr, input wire [2:0] rd_addr_a, rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b);


wire [7:0] load;
wire [15:0] q0, q1, q2, q3, q4, q5, q6, q7;

demux8 dmx(wr, wr_addr[2], wr_addr[1], wr_addr[0], load);
reg16_8 rm16(clk, reset, load, d_in, q0, q1, q2, q3, q4, q5, q6, q7);
mux8_16 mx0(q0, q1, q2, q3, q4, q5, q6, q7, {rd_addr_a[2], rd_addr_a[1], rd_addr_a[0]}, d_out_a);
mux8_16 mx1(q0, q1, q2, q3, q4, q5, q6, q7, {rd_addr_b[2], rd_addr_b[1], rd_addr_b[0]}, d_out_b);

endmodule