data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/tart_clk_generator.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/tart_clk_generator.v:31: Cannot find file containing module: 'IBUFG'\n   IBUFG #(\n   ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog,data/full_repos/permissive/20430511/IBUFG\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog,data/full_repos/permissive/20430511/IBUFG.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog,data/full_repos/permissive/20430511/IBUFG.sv\n             IBUFG\n             IBUFG.v\n             IBUFG.sv\n             obj_dir/IBUFG\n             obj_dir/IBUFG.v\n             obj_dir/IBUFG.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/tart_clk_generator.v:38: Cannot find file containing module: 'BUFIO2'\n   BUFIO2 #(\n   ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/tart_clk_generator.v:51: Cannot find file containing module: 'DCM_SP'\n   DCM_SP #(\n   ^~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/tart_clk_generator.v:93: Cannot find file containing module: 'BUFG'\n   BUFG BUFG_inst0 (\n   ^~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/tart_clk_generator.v:98: Cannot find file containing module: 'BUFG'\n   BUFG BUFG_inst1 (\n   ^~~~\n%Error: Exiting due to 5 error(s)\n"
module tart_clk_generator(
      input wire  CLKIN,
      output wire CLKOUT0,
      output wire CLKOUT1,
      output      reset_n
    );

   wire GND_PIN; assign GND_PIN = 0;
   wire CLK0;
   
   IBUFG #(
         .IOSTANDARD("DEFAULT")
      ) IBUFG_inst (
         .O(IBUFG_OUT),
         .I(CLKIN)
      );

   BUFIO2 #(
      .DIVIDE(1),
      .DIVIDE_BYPASS("TRUE"),
      .I_INVERT("FALSE"),
      .USE_DOUBLER("FALSE")
   )
   BUFIO2_inst (
      .DIVCLK(DIVCLK),


      .I(IBUFG_OUT)
   );

   DCM_SP #(
      .CLKDV_DIVIDE(2.0),

      .CLKFX_DIVIDE(1),
      .CLKFX_MULTIPLY(6),
      .CLKIN_DIVIDE_BY_2("FALSE"),
      .CLKIN_PERIOD(61.095),
      .CLKOUT_PHASE_SHIFT("NONE"),
      .CLK_FEEDBACK("1X"),
      .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
      .DFS_FREQUENCY_MODE("LOW"),
      .DLL_FREQUENCY_MODE("LOW"),
      .DSS_MODE("NONE"),
      .DUTY_CYCLE_CORRECTION("TRUE"),
      .FACTORY_JF(16'hc080),
      .PHASE_SHIFT(0),
      .STARTUP_WAIT("FALSE")
   )
   DCM_SP_inst (
      .CLK0(CLK0),






      .CLKFX(CLKFX),

      .LOCKED(reset_n),


      .CLKFB(CLK0),
      .CLKIN(DIVCLK),
      .DSSEN(GND_PIN),
      .PSCLK(GND_PIN),
      .PSEN(GND_PIN),
      .PSINCDEC(GND_PIN),
      .RST(GND_PIN)
   );



   BUFG BUFG_inst0 (
      .O(CLKOUT0),
      .I(DIVCLK)
   );
   
   BUFG BUFG_inst1 (
      .O(CLKOUT1),
      .I(CLKFX)
   );


endmodule
module tart_clk_generator(
      input wire  CLKIN,
      output wire CLKOUT0,
      output wire CLKOUT1,
      output      reset_n
    );


   wire GND_PIN; assign GND_PIN = 0;
   wire CLK0;
   
   IBUFG #(
         .IOSTANDARD("DEFAULT")
      ) IBUFG_inst (
         .O(IBUFG_OUT),
         .I(CLKIN)
      );

   BUFIO2 #(
      .DIVIDE(1),
      .DIVIDE_BYPASS("TRUE"),
      .I_INVERT("FALSE"),
      .USE_DOUBLER("FALSE")
   )
   BUFIO2_inst (
      .DIVCLK(DIVCLK),


      .I(IBUFG_OUT)
   );

   DCM_SP #(
      .CLKDV_DIVIDE(2.0),

      .CLKFX_DIVIDE(1),
      .CLKFX_MULTIPLY(6),
      .CLKIN_DIVIDE_BY_2("FALSE"),
      .CLKIN_PERIOD(61.095),
      .CLKOUT_PHASE_SHIFT("NONE"),
      .CLK_FEEDBACK("1X"),
      .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
      .DFS_FREQUENCY_MODE("LOW"),
      .DLL_FREQUENCY_MODE("LOW"),
      .DSS_MODE("NONE"),
      .DUTY_CYCLE_CORRECTION("TRUE"),
      .FACTORY_JF(16'hc080),
      .PHASE_SHIFT(0),
      .STARTUP_WAIT("FALSE")
   )
   DCM_SP_inst (
      .CLK0(CLK0),






      .CLKFX(CLKFX),

      .LOCKED(reset_n),


      .CLKFB(CLK0),
      .CLKIN(DIVCLK),
      .DSSEN(GND_PIN),
      .PSCLK(GND_PIN),
      .PSEN(GND_PIN),
      .PSINCDEC(GND_PIN),
      .RST(GND_PIN)
   );



   BUFG BUFG_inst0 (
      .O(CLKOUT0),
      .I(DIVCLK)
   );
   
   BUFG BUFG_inst1 (
      .O(CLKOUT1),
      .I(CLKFX)
   );


endmodule