data/full_repos/permissive/121864698/Datapath.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/121864698/Datapath.v:16: Signal definition not found, creating implicitly: \'zero\'\nand (sel4,branch,zero);\n                 ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/121864698/Datapath.v:16: Signal definition not found, creating implicitly: \'sel4\'\n                                                                     : ... Suggested alternative: \'sel1\'\nand (sel4,branch,zero);\n     ^~~~\n%Error: data/full_repos/permissive/121864698/Datapath.v:24: Cannot find file containing module: \'Mux2\'\nMux2 alu(dataA,8\'bx,sel5,aluMux);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/121864698,data/full_repos/permissive/121864698/Mux2\n             data/full_repos/permissive/121864698,data/full_repos/permissive/121864698/Mux2.v\n             data/full_repos/permissive/121864698,data/full_repos/permissive/121864698/Mux2.sv\n             Mux2\n             Mux2.v\n             Mux2.sv\n             obj_dir/Mux2\n             obj_dir/Mux2.v\n             obj_dir/Mux2.sv\n%Error: data/full_repos/permissive/121864698/Datapath.v:25: Cannot find file containing module: \'PC\'\nPC programcounter(op3,clk,pc_out,pc_sel,reset);\n^~\n%Error: data/full_repos/permissive/121864698/Datapath.v:26: Cannot find file containing module: \'instruction\'\ninstruction im(pc_out,clk,opcode,jump,addA,addB,write_add,iformat,pc_sel);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/121864698/Datapath.v:27: Cannot find file containing module: \'Mux1\'\nMux1 multi1(addB,write_add,sel1,out1);\n^~~~\n%Error: data/full_repos/permissive/121864698/Datapath.v:28: Cannot find file containing module: \'Register\'\nRegister regfile(reg_wrt,addA,clk,addB,out1,regData,dataA,dataB);\n^~~~~~~~\n%Error: data/full_repos/permissive/121864698/Datapath.v:29: Cannot find file containing module: \'sign\'\nsign xtend(iformat,xtended);\n^~~~\n%Error: data/full_repos/permissive/121864698/Datapath.v:30: Cannot find file containing module: \'lat\'\nlat latch(xtended,latchout,clk);\n^~~\n%Error: data/full_repos/permissive/121864698/Datapath.v:31: Cannot find file containing module: \'Mux2\'\nMux2 multi2(dataB,latchout,sel2,out2);\n^~~~\n%Error: data/full_repos/permissive/121864698/Datapath.v:32: Cannot find file containing module: \'ALU\'\nALU alux(aluMux,out2,alu_op,result,zero);\n^~~\n%Error: data/full_repos/permissive/121864698/Datapath.v:33: Cannot find file containing module: \'RAM\'\nRAM datamemory(result,clk,dataB,data_out,re,wr);\n^~~\n%Error: data/full_repos/permissive/121864698/Datapath.v:34: Cannot find file containing module: \'Mux2\'\nMux2 multi3(result,data_out,sel3,regData);\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/121864698/Datapath.v:36: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'latchout\' generates 8 bits.\n                                                                  : ... In instance datapath\nassign next_alu_out = latchout + pc_out;\n                               ^\n%Error: data/full_repos/permissive/121864698/Datapath.v:38: Cannot find file containing module: \'Mux3\'\nMux3 multi4(pc_out,next_alu_out,sel4,out);\n^~~~\n%Error: data/full_repos/permissive/121864698/Datapath.v:39: Cannot find file containing module: \'Mux3\'\nMux3 multi5(jump_add,out,sel6,op3);\n^~~~\n%Error: Exiting due to 13 error(s), 3 warning(s)\n'
module datapath(alu_op,opcode,clk,carry,sel1,sel2,sel3,sel5,sel6,re,wr,reg_wrt,reset,pc_sel,im_select,branch);
input clk;
output carry;
input [1:0]sel2;
input sel1,sel3,sel5,sel6,re,wr;
input reg_wrt;
input reset;
output [3:0]opcode;
input [3:0]alu_op;
input im_select;
input branch,pc_sel;
wire [7:0] shift;
wire [15:0] next_pc;
wire [15:0] next_alu_out,jump_add;
wire [11:0] jump;
and (sel4,branch,zero);
wire [15:0]op3,out;
wire [15:0]pc_out;
wire [3:0]iformat,addA,addB,write_add,out1;
wire [7:0]data_out;
wire [7:0]result;
wire [7:0]regData,aluMux;
wire [7:0] dataA,dataB,xtended,out2,latchout;
Mux2 alu(dataA,8'bx,sel5,aluMux);
PC programcounter(op3,clk,pc_out,pc_sel,reset);
instruction im(pc_out,clk,opcode,jump,addA,addB,write_add,iformat,pc_sel);
Mux1 multi1(addB,write_add,sel1,out1);
Register regfile(reg_wrt,addA,clk,addB,out1,regData,dataA,dataB);
sign xtend(iformat,xtended);
lat latch(xtended,latchout,clk);
Mux2 multi2(dataB,latchout,sel2,out2);
ALU alux(aluMux,out2,alu_op,result,zero);
RAM datamemory(result,clk,dataB,data_out,re,wr);
Mux2 multi3(result,data_out,sel3,regData);

assign next_alu_out = latchout + pc_out;
assign jump_add = {pc_out[15:12],jump}; 
Mux3 multi4(pc_out,next_alu_out,sel4,out);
Mux3 multi5(jump_add,out,sel6,op3);
endmodule
module datapath(alu_op,opcode,clk,carry,sel1,sel2,sel3,sel5,sel6,re,wr,reg_wrt,reset,pc_sel,im_select,branch);

input clk;
output carry;
input [1:0]sel2;
input sel1,sel3,sel5,sel6,re,wr;
input reg_wrt;
input reset;
output [3:0]opcode;
input [3:0]alu_op;
input im_select;
input branch,pc_sel;
wire [7:0] shift;
wire [15:0] next_pc;
wire [15:0] next_alu_out,jump_add;
wire [11:0] jump;
and (sel4,branch,zero);
wire [15:0]op3,out;
wire [15:0]pc_out;
wire [3:0]iformat,addA,addB,write_add,out1;
wire [7:0]data_out;
wire [7:0]result;
wire [7:0]regData,aluMux;
wire [7:0] dataA,dataB,xtended,out2,latchout;
Mux2 alu(dataA,8'bx,sel5,aluMux);
PC programcounter(op3,clk,pc_out,pc_sel,reset);
instruction im(pc_out,clk,opcode,jump,addA,addB,write_add,iformat,pc_sel);
Mux1 multi1(addB,write_add,sel1,out1);
Register regfile(reg_wrt,addA,clk,addB,out1,regData,dataA,dataB);
sign xtend(iformat,xtended);
lat latch(xtended,latchout,clk);
Mux2 multi2(dataB,latchout,sel2,out2);
ALU alux(aluMux,out2,alu_op,result,zero);
RAM datamemory(result,clk,dataB,data_out,re,wr);
Mux2 multi3(result,data_out,sel3,regData);

assign next_alu_out = latchout + pc_out;
assign jump_add = {pc_out[15:12],jump}; 
Mux3 multi4(pc_out,next_alu_out,sel4,out);
Mux3 multi5(jump_add,out,sel6,op3);
endmodule