data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v
None: at end of input
1: b'%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:15: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_1, net_2, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:16: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_1, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:17: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(gnd, y, net_2);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:18: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_2, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:19: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_2, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:20: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, vdd, net_2);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:32: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_3, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:33: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_4, ab);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:34: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_3, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:35: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(net_4, y, bb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:36: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(gnd, bb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:37: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, ab, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:38: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, net_7, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:39: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_7, vdd, ab);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:40: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, net_8, bb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:41: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_8, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:42: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(bb, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:43: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(ab, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:70: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_1, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:71: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_1, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:72: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_1, coutb, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:73: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(gnd, net_11, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:74: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, coutb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:75: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, net_23, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:76: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_23, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:77: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_7(gnd, net_23, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:78: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_8(net_23, sb, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:79: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_9(gnd, net_33, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:80: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_10(net_33, net_32, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:81: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_11(net_32, sb, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:82: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_12(gnd, cout, coutb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:83: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_13(gnd, s, sb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:84: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(sb, net_92, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:85: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(net_92, net_90, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:86: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_90, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:87: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(sb, net_94, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:88: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(net_94, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:89: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_6(net_94, vdd, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:90: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_7(net_94, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:91: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_8(cout, vdd, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:92: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_9(net_95, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:93: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_10(coutb, net_95, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:94: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_11(net_111, vdd, a);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:95: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_12(net_111, vdd, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:96: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_13(coutb, net_111, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:97: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_14(s, vdd, sb);\n          ^~~~~~~\n%Error: Exiting due to 46 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module muddlib07__and2_1x(a, b, y);
  input a;
  input b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_1, net_2;

  tranif1 nmos_0(net_1, net_2, b);
  tranif1 nmos_1(gnd, net_1, a);
  tranif1 nmos_2(gnd, y, net_2);
  tranif0 pmos_0(net_2, vdd, b);
  tranif0 pmos_1(net_2, vdd, a);
  tranif0 pmos_2(y, vdd, net_2);
endmodule
module muddlib07__and2_1x(a, b, y);

  input a;
  input b;
  output y;

  supply1 vdd;
  supply0 gnd;
  wire net_1, net_2;

  tranif1 nmos_0(net_1, net_2, b);
  tranif1 nmos_1(gnd, net_1, a);
  tranif1 nmos_2(gnd, y, net_2);
  tranif0 pmos_0(net_2, vdd, b);
  tranif0 pmos_1(net_2, vdd, a);
  tranif0 pmos_2(y, vdd, net_2);
endmodule