data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v
None: at end of input
1: b'%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:12: Cannot find include file: nettype.h\n`include "nettype.h" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169597129/bus/rtl,data/full_repos/permissive/169597129/nettype.h\n             data/full_repos/permissive/169597129/bus/rtl,data/full_repos/permissive/169597129/nettype.h.v\n             data/full_repos/permissive/169597129/bus/rtl,data/full_repos/permissive/169597129/nettype.h.sv\n             nettype.h\n             nettype.h.v\n             nettype.h.sv\n             obj_dir/nettype.h\n             obj_dir/nettype.h.v\n             obj_dir/nettype.h.sv\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:13: Cannot find include file: stddef.h\n`include "stddef.h" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:14: Cannot find include file: global_config.h\n`include "global_config.h" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:17: Cannot find include file: bus.h\n`include "bus.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:23: Define or directive not defined: \'`WordAddrBus\'\n input  wire [`WordAddrBus] m0_addr,     \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input  wire [`WordAddrBus] m0_addr,     \n                          ^\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire       m0_rw,     \n ^~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire [`WordDataBus] m0_wr_data,  \n ^~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:26: Define or directive not defined: \'`WordDataBus\'\n input  wire [`WordDataBus] m0_wr_data,  \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:29: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire [`WordAddrBus] m1_addr,     \n ^~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:29: Define or directive not defined: \'`WordAddrBus\'\n input  wire [`WordAddrBus] m1_addr,     \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:31: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire       m1_rw,     \n ^~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire [`WordDataBus] m1_wr_data,  \n ^~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:32: Define or directive not defined: \'`WordDataBus\'\n input  wire [`WordDataBus] m1_wr_data,  \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:35: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire [`WordAddrBus] m2_addr,     \n ^~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:35: Define or directive not defined: \'`WordAddrBus\'\n input  wire [`WordAddrBus] m2_addr,     \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:37: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire       m2_rw,     \n ^~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:38: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire [`WordDataBus] m2_wr_data,  \n ^~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:38: Define or directive not defined: \'`WordDataBus\'\n input  wire [`WordDataBus] m2_wr_data,  \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:41: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire [`WordAddrBus] m3_addr,     \n ^~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:41: Define or directive not defined: \'`WordAddrBus\'\n input  wire [`WordAddrBus] m3_addr,     \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:43: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire       m3_rw,     \n ^~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:44: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input  wire [`WordDataBus] m3_wr_data,  \n ^~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:44: Define or directive not defined: \'`WordDataBus\'\n input  wire [`WordDataBus] m3_wr_data,  \n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:47: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg [`WordAddrBus] s_addr,     \n ^~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:47: Define or directive not defined: \'`WordAddrBus\'\n output reg [`WordAddrBus] s_addr,     \n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:49: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg       s_rw,     \n ^~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:50: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [`WordDataBus] s_wr_data    \n ^~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:50: Define or directive not defined: \'`WordDataBus\'\n output reg [`WordDataBus] s_wr_data    \n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:56: Define or directive not defined: \'`ENABLE_\'\n  if (m0_grnt_ == `ENABLE_) begin     \n                  ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:61: Define or directive not defined: \'`ENABLE_\'\n  end else if (m1_grnt_ == `ENABLE_) begin  \n                           ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:66: Define or directive not defined: \'`ENABLE_\'\n  end else if (m2_grnt_ == `ENABLE_) begin  \n                           ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:71: Define or directive not defined: \'`ENABLE_\'\n  end else if (m3_grnt_ == `ENABLE_) begin  \n                           ^~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:77: Define or directive not defined: \'`WORD_ADDR_W\'\n   s_addr   = `WORD_ADDR_W\'h0;\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:78: Define or directive not defined: \'`DISABLE_\'\n   s_as_   = `DISABLE_;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:79: Define or directive not defined: \'`READ\'\n   s_rw   = `READ;\n            ^~~~~\n%Error: data/full_repos/permissive/169597129/bus/rtl/bus_master_mux.v:80: Define or directive not defined: \'`WORD_DATA_W\'\n   s_wr_data = `WORD_DATA_W\'h0;\n               ^~~~~~~~~~~~\n%Error: Exiting due to 37 error(s)\n'
module bus_master_mux (


	input  wire [`WordAddrBus] m0_addr,
	input  wire				   m0_as_,
	input  wire				   m0_rw,
	input  wire [`WordDataBus] m0_wr_data,
	input  wire				   m0_grnt_,

	input  wire [`WordAddrBus] m1_addr,
	input  wire				   m1_as_,
	input  wire				   m1_rw,
	input  wire [`WordDataBus] m1_wr_data,
	input  wire				   m1_grnt_,

	input  wire [`WordAddrBus] m2_addr,
	input  wire				   m2_as_,
	input  wire				   m2_rw,
	input  wire [`WordDataBus] m2_wr_data,
	input  wire				   m2_grnt_,

	input  wire [`WordAddrBus] m3_addr,
	input  wire				   m3_as_,
	input  wire				   m3_rw,
	input  wire [`WordDataBus] m3_wr_data,
	input  wire				   m3_grnt_,

	output reg	[`WordAddrBus] s_addr,
	output reg				   s_as_,
	output reg				   s_rw,
	output reg	[`WordDataBus] s_wr_data
);


	always @(*) begin

		if (m0_grnt_ == `ENABLE_) begin
			s_addr	  = m0_addr;
			s_as_	  = m0_as_;
			s_rw	  = m0_rw;
			s_wr_data = m0_wr_data;
		end else if (m1_grnt_ == `ENABLE_) begin
			s_addr	  = m1_addr;
			s_as_	  = m1_as_;
			s_rw	  = m1_rw;
			s_wr_data = m1_wr_data;
		end else if (m2_grnt_ == `ENABLE_) begin
			s_addr	  = m2_addr;
			s_as_	  = m2_as_;
			s_rw	  = m2_rw;
			s_wr_data = m2_wr_data;
		end else if (m3_grnt_ == `ENABLE_) begin
			s_addr	  = m3_addr;
			s_as_	  = m3_as_;
			s_rw	  = m3_rw;
			s_wr_data = m3_wr_data;
		end else begin
			s_addr	  = `WORD_ADDR_W'h0;
			s_as_	  = `DISABLE_;
			s_rw	  = `READ;
			s_wr_data = `WORD_DATA_W'h0;
		end
	end

endmodule
module bus_master_mux (


	input  wire [`WordAddrBus] m0_addr,
	input  wire				   m0_as_,
	input  wire				   m0_rw,
	input  wire [`WordDataBus] m0_wr_data,
	input  wire				   m0_grnt_,

	input  wire [`WordAddrBus] m1_addr,
	input  wire				   m1_as_,
	input  wire				   m1_rw,
	input  wire [`WordDataBus] m1_wr_data,
	input  wire				   m1_grnt_,

	input  wire [`WordAddrBus] m2_addr,
	input  wire				   m2_as_,
	input  wire				   m2_rw,
	input  wire [`WordDataBus] m2_wr_data,
	input  wire				   m2_grnt_,

	input  wire [`WordAddrBus] m3_addr,
	input  wire				   m3_as_,
	input  wire				   m3_rw,
	input  wire [`WordDataBus] m3_wr_data,
	input  wire				   m3_grnt_,

	output reg	[`WordAddrBus] s_addr,
	output reg				   s_as_,
	output reg				   s_rw,
	output reg	[`WordDataBus] s_wr_data
);



	always @(*) begin

		if (m0_grnt_ == `ENABLE_) begin
			s_addr	  = m0_addr;
			s_as_	  = m0_as_;
			s_rw	  = m0_rw;
			s_wr_data = m0_wr_data;
		end else if (m1_grnt_ == `ENABLE_) begin
			s_addr	  = m1_addr;
			s_as_	  = m1_as_;
			s_rw	  = m1_rw;
			s_wr_data = m1_wr_data;
		end else if (m2_grnt_ == `ENABLE_) begin
			s_addr	  = m2_addr;
			s_as_	  = m2_as_;
			s_rw	  = m2_rw;
			s_wr_data = m2_wr_data;
		end else if (m3_grnt_ == `ENABLE_) begin
			s_addr	  = m3_addr;
			s_as_	  = m3_as_;
			s_rw	  = m3_rw;
			s_wr_data = m3_wr_data;
		end else begin
			s_addr	  = `WORD_ADDR_W'h0;
			s_as_	  = `DISABLE_;
			s_rw	  = `READ;
			s_wr_data = `WORD_DATA_W'h0;
		end
	end

endmodule