data/full_repos/permissive/114643454/src/id_ex.v
 line:5: before: "]"
1: b"%Error: data/full_repos/permissive/114643454/src/id_ex.v:5: Define or directive not defined: '`AluOpBus'\n    input   wire[`AluOpBus]     id_aluop,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:5: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n    input   wire[`AluOpBus]     id_aluop,\n                          ^\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:6: Define or directive not defined: '`AluSelBus'\n    input   wire[`AluSelBus]    id_alusel,\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:7: Define or directive not defined: '`RegBus'\n    input   wire[`RegBus]       id_reg1,\n                 ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:8: Define or directive not defined: '`RegBus'\n    input   wire[`RegBus]       id_reg2,\n                 ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:9: Define or directive not defined: '`RegAddrBus'\n    input   wire[`RegAddrBus]   id_wd,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[5 : 0]         stall,\n    ^~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegBus]       id_link_address,\n    ^~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:13: Define or directive not defined: '`RegBus'\n    input   wire[`RegBus]       id_link_address,\n                 ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:15: Define or directive not defined: '`RegBus'\n    input   wire[`RegBus]       id_inst,\n                 ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:17: Define or directive not defined: '`AluOpBus'\n    output  reg[`AluOpBus]      ex_aluop,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:18: Define or directive not defined: '`AluSelBus'\n    output  reg[`AluSelBus]     ex_alusel,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:19: Define or directive not defined: '`RegBus'\n    output  reg[`RegBus]        ex_reg1,\n                ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:20: Define or directive not defined: '`RegBus'\n    output  reg[`RegBus]        ex_reg2,\n                ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:21: Define or directive not defined: '`RegAddrBus'\n    output  reg[`RegAddrBus]    ex_wd,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:24: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output  reg[`RegBus]        ex_link_address,\n    ^~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:24: Define or directive not defined: '`RegBus'\n    output  reg[`RegBus]        ex_link_address,\n                ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:26: Define or directive not defined: '`RegBus'\n    output  reg[`RegBus]        ex_inst\n                ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:32: Define or directive not defined: '`RstEnable'\n        if (rst == `RstEnable) begin\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:33: Define or directive not defined: '`EXE_NOP_OP'\n            ex_aluop <= `EXE_NOP_OP;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:34: Define or directive not defined: '`EXE_RES_NOP'\n            ex_alusel <= `EXE_RES_NOP;\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:35: Define or directive not defined: '`ZeroWord'\n            ex_reg1 <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:36: Define or directive not defined: '`ZeroWord'\n            ex_reg2 <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:37: Define or directive not defined: '`NOPRegAddr'\n            ex_wd <= `NOPRegAddr;\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:38: Define or directive not defined: '`WriteDisable'\n            ex_wreg <= `WriteDisable;\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:39: Define or directive not defined: '`Stop'\n        end else if (stall[2] == `Stop && stall[3] == `NoStop) begin\n                                 ^~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:39: Define or directive not defined: '`NoStop'\n        end else if (stall[2] == `Stop && stall[3] == `NoStop) begin\n                                                      ^~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:40: Define or directive not defined: '`EXE_NOP_OP'\n            ex_aluop <= `EXE_NOP_OP;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:41: Define or directive not defined: '`EXE_RES_NOP'\n            ex_alusel <= `EXE_RES_NOP;\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:42: Define or directive not defined: '`ZeroWord'\n            ex_reg1 <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:43: Define or directive not defined: '`ZeroWord'\n            ex_reg2 <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:44: Define or directive not defined: '`NOPRegAddr'\n            ex_wd <= `NOPRegAddr;\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:45: Define or directive not defined: '`WriteDisable'\n            ex_wreg <= `WriteDisable;\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:46: Define or directive not defined: '`ZeroWord'\n            ex_link_address <= `ZeroWord;\n                               ^~~~~~~~~\n%Error: data/full_repos/permissive/114643454/src/id_ex.v:47: Define or directive not defined: '`NoStop'\n        end else if (stall[2] == `NoStop) begin\n                                 ^~~~~~~\n%Error: Exiting due to 35 error(s)\n"
module id_ex (

    input   wire                clk,
    input   wire                rst,
    input   wire[`AluOpBus]     id_aluop,
    input   wire[`AluSelBus]    id_alusel,
    input   wire[`RegBus]       id_reg1,
    input   wire[`RegBus]       id_reg2,
    input   wire[`RegAddrBus]   id_wd,
    input   wire                id_wreg,
    input   wire[5 : 0]         stall,

    input   wire[`RegBus]       id_link_address,

    input   wire[`RegBus]       id_inst,

    output  reg[`AluOpBus]      ex_aluop,
    output  reg[`AluSelBus]     ex_alusel,
    output  reg[`RegBus]        ex_reg1,
    output  reg[`RegBus]        ex_reg2,
    output  reg[`RegAddrBus]    ex_wd,
    output  reg                 ex_wreg,

    output  reg[`RegBus]        ex_link_address,

    output  reg[`RegBus]        ex_inst


);

    always @ ( posedge clk ) begin
        if (rst == `RstEnable) begin
            ex_aluop <= `EXE_NOP_OP;
            ex_alusel <= `EXE_RES_NOP;
            ex_reg1 <= `ZeroWord;
            ex_reg2 <= `ZeroWord;
            ex_wd <= `NOPRegAddr;
            ex_wreg <= `WriteDisable;
        end else if (stall[2] == `Stop && stall[3] == `NoStop) begin
            ex_aluop <= `EXE_NOP_OP;
            ex_alusel <= `EXE_RES_NOP;
            ex_reg1 <= `ZeroWord;
            ex_reg2 <= `ZeroWord;
            ex_wd <= `NOPRegAddr;
            ex_wreg <= `WriteDisable;
            ex_link_address <= `ZeroWord;
        end else if (stall[2] == `NoStop) begin
            ex_aluop <= id_aluop;
            ex_alusel <= id_alusel;
            ex_reg1 <= id_reg1;
            ex_reg2 <= id_reg2;
            ex_wd <= id_wd;
            ex_wreg <= id_wreg;
            ex_link_address <= id_link_address;

            ex_inst <= id_inst;
        end
    end

endmodule
module id_ex (

    input   wire                clk,
    input   wire                rst,
    input   wire[`AluOpBus]     id_aluop,
    input   wire[`AluSelBus]    id_alusel,
    input   wire[`RegBus]       id_reg1,
    input   wire[`RegBus]       id_reg2,
    input   wire[`RegAddrBus]   id_wd,
    input   wire                id_wreg,
    input   wire[5 : 0]         stall,

    input   wire[`RegBus]       id_link_address,

    input   wire[`RegBus]       id_inst,

    output  reg[`AluOpBus]      ex_aluop,
    output  reg[`AluSelBus]     ex_alusel,
    output  reg[`RegBus]        ex_reg1,
    output  reg[`RegBus]        ex_reg2,
    output  reg[`RegAddrBus]    ex_wd,
    output  reg                 ex_wreg,

    output  reg[`RegBus]        ex_link_address,

    output  reg[`RegBus]        ex_inst


);


    always @ ( posedge clk ) begin
        if (rst == `RstEnable) begin
            ex_aluop <= `EXE_NOP_OP;
            ex_alusel <= `EXE_RES_NOP;
            ex_reg1 <= `ZeroWord;
            ex_reg2 <= `ZeroWord;
            ex_wd <= `NOPRegAddr;
            ex_wreg <= `WriteDisable;
        end else if (stall[2] == `Stop && stall[3] == `NoStop) begin
            ex_aluop <= `EXE_NOP_OP;
            ex_alusel <= `EXE_RES_NOP;
            ex_reg1 <= `ZeroWord;
            ex_reg2 <= `ZeroWord;
            ex_wd <= `NOPRegAddr;
            ex_wreg <= `WriteDisable;
            ex_link_address <= `ZeroWord;
        end else if (stall[2] == `NoStop) begin
            ex_aluop <= id_aluop;
            ex_alusel <= id_alusel;
            ex_reg1 <= id_reg1;
            ex_reg2 <= id_reg2;
            ex_wd <= id_wd;
            ex_wreg <= id_wreg;
            ex_link_address <= id_link_address;

            ex_inst <= id_inst;
        end
    end

endmodule