data/full_repos/permissive/160976968/adder.v
1: b"%Error: data/full_repos/permissive/160976968/adder.v:10: syntax error, unexpected '(', expecting IDENTIFIER\n comparator(SW[3:0], 0, X_EC);\n            ^~\n%Error: Exiting due to 1 error(s)\n"
module to_hex(in, disp);
	input [3:0]in;
	output [0:6]disp;

	assign disp[0] = (~in[3] & ~in[2] & ~in[1] & in[0])
						| (~in[3] & in[2] & ~in[1] & ~in[0]);
	assign disp[1] = (~in[3] & in[2] & ~in[1] & in[0])
						| (~in[3] & in[2] & in[1] & ~in[0]);
	assign disp[2] = (~in[3] & ~in[2] & in[1] & ~in[0]);
	assign disp[3] = (~in[3] & ~in[2] & ~in[1] & in[0])
						| (~in[3] & in[2] & ~in[1] & ~in[0])
						| (~in[3] & in[2] & in[1] & in[0])
						| (in[3] & ~in[2] & ~in[1] & in[0]);
	assign disp[4] = ~((~in[3] & ~in[2] & ~in[1] & ~in[0])
						| (~in[3] & ~in[2] & in[1] & ~in[0])
						| (~in[3] & in[2] & in[1] & ~in[0])
						| (in[3] & ~in[2] & ~in[1] & ~in[0]));
	assign disp[5] = (~in[3] & ~in[2] & ~in[1] & in[0])
						| (~in[3] & ~in[2] & in[1] & ~in[0])
						| (~in[3] & ~in[2] & in[1] & in[0])
						| (~in[3] & in[2] & in[1] & in[0]);
	assign disp[6] = (~in[3] & ~in[2] & ~in[1] & ~in[0])
						| (~in[3] & ~in[2] & ~in[1] & in[0])
						| (~in[3] & in[2] & in[1] & in[0]);
endmodule
module to_hex(in, disp);

	input [3:0]in;
	output [0:6]disp;

	assign disp[0] = (~in[3] & ~in[2] & ~in[1] & in[0])
						| (~in[3] & in[2] & ~in[1] & ~in[0]);
	assign disp[1] = (~in[3] & in[2] & ~in[1] & in[0])
						| (~in[3] & in[2] & in[1] & ~in[0]);
	assign disp[2] = (~in[3] & ~in[2] & in[1] & ~in[0]);
	assign disp[3] = (~in[3] & ~in[2] & ~in[1] & in[0])
						| (~in[3] & in[2] & ~in[1] & ~in[0])
						| (~in[3] & in[2] & in[1] & in[0])
						| (in[3] & ~in[2] & ~in[1] & in[0]);
	assign disp[4] = ~((~in[3] & ~in[2] & ~in[1] & ~in[0])
						| (~in[3] & ~in[2] & in[1] & ~in[0])
						| (~in[3] & in[2] & in[1] & ~in[0])
						| (in[3] & ~in[2] & ~in[1] & ~in[0]));
	assign disp[5] = (~in[3] & ~in[2] & ~in[1] & in[0])
						| (~in[3] & ~in[2] & in[1] & ~in[0])
						| (~in[3] & ~in[2] & in[1] & in[0])
						| (~in[3] & in[2] & in[1] & in[0]);
	assign disp[6] = (~in[3] & ~in[2] & ~in[1] & ~in[0])
						| (~in[3] & ~in[2] & ~in[1] & in[0])
						| (~in[3] & in[2] & in[1] & in[0]);
endmodule