data/full_repos/permissive/156650213/gmii_mirror_xgmii.srcs/sim_1/new/sim_gap.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/156650213/gmii_mirror_xgmii.srcs/sim_1/new/sim_gap.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/156650213/gmii_mirror_xgmii.srcs/sim_1/new/sim_gap.v:44: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                                  : ... In instance sim_gap\n                packet_len = $unsigned($random) % 32 + 8;  \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/156650213/gmii_mirror_xgmii.srcs/sim_1/new/sim_gap.v:46: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'packet_len\' generates 16 bits.\n                                                                                                  : ... In instance sim_gap\n                tdata <= packet_len + tuser;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/156650213/gmii_mirror_xgmii.srcs/sim_1/new/sim_gap.v:46: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'tuser\' generates 4 bits.\n                                                                                                  : ... In instance sim_gap\n                tdata <= packet_len + tuser;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/156650213/gmii_mirror_xgmii.srcs/sim_1/new/sim_gap.v:50: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 16 bits.\n                                                                                                  : ... In instance sim_gap\n                tuser <= (packet_len >= 8) ? 8 : packet_len;\n                      ^~\n%Error: data/full_repos/permissive/156650213/gmii_mirror_xgmii.srcs/sim_1/new/sim_gap.v:58: Cannot find file containing module: \'axis_fifo\'\naxis_fifo #(.WIDTH_DATA(64), .WIDTH_USER(4), .WIDTH_LAST(1), .FIFO_SIZE_L2(0)) axis_fifo_0(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156650213/gmii_mirror_xgmii.srcs/sim_1/new,data/full_repos/permissive/156650213/axis_fifo\n             data/full_repos/permissive/156650213/gmii_mirror_xgmii.srcs/sim_1/new,data/full_repos/permissive/156650213/axis_fifo.v\n             data/full_repos/permissive/156650213/gmii_mirror_xgmii.srcs/sim_1/new,data/full_repos/permissive/156650213/axis_fifo.sv\n             axis_fifo\n             axis_fifo.v\n             axis_fifo.sv\n             obj_dir/axis_fifo\n             obj_dir/axis_fifo.v\n             obj_dir/axis_fifo.sv\n%Error: data/full_repos/permissive/156650213/gmii_mirror_xgmii.srcs/sim_1/new/sim_gap.v:67: Cannot find file containing module: \'xgmii_make_contiguous\'\nxgmii_make_contiguous xgmii_make_contiguous_0(\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/156650213/gmii_mirror_xgmii.srcs/sim_1/new/sim_gap.v:75: Cannot find file containing module: \'xgmii_tx_nofcs\'\nxgmii_tx_nofcs xg_tx_nofcs_0(\n^~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_gap();

reg clk;
reg resetn;

initial begin
    clk = 0;
    forever clk = #1 !clk;
end
initial begin
    resetn = 0;
    #10;
    resetn = 1;
end

reg [15:0] packet_len;
reg [63:0] tdata;
reg [3:0] tuser;
reg tlast;
reg tvalid;
reg found_packet_end;

wire tready;
wire [63:0] tdata_f;
wire [3:0] tuser_f;
wire tlast_f;
wire tvalid_f;
wire tready_f;

always @(posedge clk) begin
    if (!resetn) begin
        packet_len <= 0;
        tdata <= 0;
        tuser <= 0;
        tlast <= 0;
        tvalid <= 0;
        found_packet_end <= 0;
    end else begin
        tvalid <= 1;
        found_packet_end <= 0;
        if (tready) begin
            if (packet_len == 0) begin
                packet_len = $unsigned($random) % 32 + 8;
                tuser = 8;
                tdata <= packet_len + tuser;
                tlast <= 0;
                found_packet_end <= 1;
            end else begin
                tuser <= (packet_len >= 8) ? 8 : packet_len;
                tlast <= (packet_len <= 8);
                packet_len <= (packet_len <= 8) ? 0 : (packet_len - 8);
            end
        end
    end
end

axis_fifo #(.WIDTH_DATA(64), .WIDTH_USER(4), .WIDTH_LAST(1), .FIFO_SIZE_L2(0)) axis_fifo_0(
    .CLK(clk), .RESETN(resetn),
    .IV_TDATA(tdata), .IV_TUSER(tuser), .IV_TLAST(tlast), .IV_TVALID(tvalid), .IV_TREADY(tready),
    .OV_TDATA(tdata_f), .OV_TUSER(tuser_f), .OV_TLAST(tlast_f), .OV_TVALID(tvalid_f), .OV_TREADY(tready_f));

wire [63:0] txd_c;
wire [3:0] txlen_c;
wire txhd_c;

xgmii_make_contiguous xgmii_make_contiguous_0(
    .CLK(clk), .RESETN(resetn), .PACKET_END(found_packet_end),
    .IVAL_TDATA(tdata_f), .IVAL_TUSER(tuser_f), .IVAL_TLAST(tlast_f), .IVAL_TVALID(tvalid_f), .IVAL_TREADY(tready_f),
    .OVAL_XGMII_D(txd_c), .OVAL_XGMII_LEN(txlen_c), .OVAL_XGMII_HALFDELAY(txhd_c));

wire [63:0] txd_o;
wire [7:0] txc_o;

xgmii_tx_nofcs xg_tx_nofcs_0(
    .CLK(clk), .RESET(!resetn), .TXLEN_IN(txlen_c), .TXD_IN(txd_c), .TXHD_IN(txhd_c),
    .TXC_OUT(txc_o), .TXD_OUT(txd_o));

endmodule
module sim_gap();


reg clk;
reg resetn;

initial begin
    clk = 0;
    forever clk = #1 !clk;
end
initial begin
    resetn = 0;
    #10;
    resetn = 1;
end

reg [15:0] packet_len;
reg [63:0] tdata;
reg [3:0] tuser;
reg tlast;
reg tvalid;
reg found_packet_end;

wire tready;
wire [63:0] tdata_f;
wire [3:0] tuser_f;
wire tlast_f;
wire tvalid_f;
wire tready_f;

always @(posedge clk) begin
    if (!resetn) begin
        packet_len <= 0;
        tdata <= 0;
        tuser <= 0;
        tlast <= 0;
        tvalid <= 0;
        found_packet_end <= 0;
    end else begin
        tvalid <= 1;
        found_packet_end <= 0;
        if (tready) begin
            if (packet_len == 0) begin
                packet_len = $unsigned($random) % 32 + 8;
                tuser = 8;
                tdata <= packet_len + tuser;
                tlast <= 0;
                found_packet_end <= 1;
            end else begin
                tuser <= (packet_len >= 8) ? 8 : packet_len;
                tlast <= (packet_len <= 8);
                packet_len <= (packet_len <= 8) ? 0 : (packet_len - 8);
            end
        end
    end
end

axis_fifo #(.WIDTH_DATA(64), .WIDTH_USER(4), .WIDTH_LAST(1), .FIFO_SIZE_L2(0)) axis_fifo_0(
    .CLK(clk), .RESETN(resetn),
    .IV_TDATA(tdata), .IV_TUSER(tuser), .IV_TLAST(tlast), .IV_TVALID(tvalid), .IV_TREADY(tready),
    .OV_TDATA(tdata_f), .OV_TUSER(tuser_f), .OV_TLAST(tlast_f), .OV_TVALID(tvalid_f), .OV_TREADY(tready_f));

wire [63:0] txd_c;
wire [3:0] txlen_c;
wire txhd_c;

xgmii_make_contiguous xgmii_make_contiguous_0(
    .CLK(clk), .RESETN(resetn), .PACKET_END(found_packet_end),
    .IVAL_TDATA(tdata_f), .IVAL_TUSER(tuser_f), .IVAL_TLAST(tlast_f), .IVAL_TVALID(tvalid_f), .IVAL_TREADY(tready_f),
    .OVAL_XGMII_D(txd_c), .OVAL_XGMII_LEN(txlen_c), .OVAL_XGMII_HALFDELAY(txhd_c));

wire [63:0] txd_o;
wire [7:0] txc_o;

xgmii_tx_nofcs xg_tx_nofcs_0(
    .CLK(clk), .RESET(!resetn), .TXLEN_IN(txlen_c), .TXD_IN(txd_c), .TXHD_IN(txhd_c),
    .TXC_OUT(txc_o), .TXD_OUT(txd_o));

endmodule