data/full_repos/permissive/135475029/lab_5/src/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/135475029/lab_5/src/ALU.v:61: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                       : ... In instance ALU\n            sum = A + BB + AluOp[1];\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ALU(
    input   [3:0] AluOp,
    input   [31:0] A,
    input   [31:0] B,
    output  reg [31:0] result,
    output  reg zero
    );
    
    wire [31:0] AandB;
    wire [31:0] AxorB;
    wire [31:0] AnorB;
    wire [31:0] AorB;
    reg [31:0] logicOut;
    reg [31:0] BB;
    reg [31:0] sum;
    reg [31:0] arithmeticOut;
    
    assign AandB = A & B;
    assign AxorB = A ^ B;
    assign AorB = A | B;
    assign AnorB = ~(A|B);
    

    always@(*)
        case(AluOp[1:0])
            2'b00: logicOut = AandB;
            2'b01: logicOut = AorB;
            2'b10: logicOut = AxorB;
            2'b11: logicOut = AnorB;
        endcase 
        

    always@(*)
        begin
            case(AluOp[1])
                1'b0: BB = B;
                1'b1: BB = ~B;
            endcase
            sum = A + BB + AluOp[1];
        end
    always@(*)
        case(AluOp[3])
            1'b0: arithmeticOut = sum;
            1'b1: arithmeticOut = sum >> 31;    
        endcase
        
    always@(*)
        begin
            case(AluOp[2])
                1'b0: result = arithmeticOut;
                1'b1: result = logicOut;
            endcase
            zero = ~(|result);
        end
endmodule
module ALU(
    input   [3:0] AluOp,
    input   [31:0] A,
    input   [31:0] B,
    output  reg [31:0] result,
    output  reg zero
    );

    
    wire [31:0] AandB;
    wire [31:0] AxorB;
    wire [31:0] AnorB;
    wire [31:0] AorB;
    reg [31:0] logicOut;
    reg [31:0] BB;
    reg [31:0] sum;
    reg [31:0] arithmeticOut;
    
    assign AandB = A & B;
    assign AxorB = A ^ B;
    assign AorB = A | B;
    assign AnorB = ~(A|B);
    

    always@(*)
        case(AluOp[1:0])
            2'b00: logicOut = AandB;
            2'b01: logicOut = AorB;
            2'b10: logicOut = AxorB;
            2'b11: logicOut = AnorB;
        endcase 
        

    always@(*)
        begin
            case(AluOp[1])
                1'b0: BB = B;
                1'b1: BB = ~B;
            endcase
            sum = A + BB + AluOp[1];
        end
    always@(*)
        case(AluOp[3])
            1'b0: arithmeticOut = sum;
            1'b1: arithmeticOut = sum >> 31;    
        endcase
        
    always@(*)
        begin
            case(AluOp[2])
                1'b0: result = arithmeticOut;
                1'b1: result = logicOut;
            endcase
            zero = ~(|result);
        end
endmodule