data/full_repos/permissive/165663914/firmware/Polyphase_FIR/CicInterpM5.v
1: b'%Warning-WIDTH: data/full_repos/permissive/165663914/firmware/Polyphase_FIR/CicInterpM5.v:54: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                            : ... In instance CicInterpM5\n assign y_real = y5[CBITS-1 -:OBITS] + y5[(CBITS-1)-OBITS];   \n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/165663914/firmware/Polyphase_FIR/CicInterpM5.v:55: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                            : ... In instance CicInterpM5\n assign y_imag = s5[CBITS-1 -:OBITS] + s5[(CBITS-1)-OBITS];\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/165663914/firmware/Polyphase_FIR/CicInterpM5.v:70: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                            : ... In instance CicInterpM5\n    counter <= 1\'d0;\n            ^~\n%Error: Exiting due to 3 warning(s)\n'
module CicInterpM5(
	input clock,
	input clock_en,
	output reg req,
	input signed [IBITS-1:0] x_real,
	input signed [IBITS-1:0] x_imag,
	output signed [OBITS-1:0] y_real,
	output signed [OBITS-1:0] y_imag
	);
	
	parameter RRRR = 320;
	parameter IBITS = 20;
	parameter OBITS = 16;
	parameter GBITS = 34;

	localparam CBITS = IBITS + GBITS;

	reg [8:0] counter;

	reg signed [CBITS-1:0] x0, x1, x2, x3, x4, x5, dx0, dx1, dx2, dx3, dx4;
	reg signed [CBITS-1:0] y1, y2, y3, y4, y5;
	reg signed [CBITS-1:0] q0, q1, q2, q3, q4, q5, dq0, dq1, dq2, dq3, dq4;
	reg signed [CBITS-1:0] s1, s2, s3, s4, s5;

	wire signed [CBITS-1:0] sxtxr, sxtxi;
	assign sxtxr = {{(CBITS - IBITS){x_real[IBITS-1]}}, x_real};
	assign sxtxi = {{(CBITS - IBITS){x_imag[IBITS-1]}}, x_imag};
	assign y_real = y5[CBITS-1 -:OBITS] + y5[(CBITS-1)-OBITS];
	assign y_imag = s5[CBITS-1 -:OBITS] + s5[(CBITS-1)-OBITS];
	
	initial
	begin
		counter = 0;
		req = 0;
	end

	always @(posedge clock)
	begin
		if (clock_en)
		begin

			if (counter == RRRR - 1)
			begin
				counter <= 1'd0;
				x0 <= sxtxr;
				q0 <= sxtxi;
				req <= 1'd1;

				x1 <= x0 - dx0;
				x2 <= x1 - dx1;			
				x3 <= x2 - dx2;				
				x4 <= x3 - dx3;				
				x5 <= x4 - dx4;			
				dx0 <= x0;
				dx1 <= x1;
				dx2 <= x2;
				dx3 <= x3;
				dx4 <= x4;

				q1 <= q0 - dq0;
				q2 <= q1 - dq1;
				q3 <= q2 - dq2;
				q4 <= q3 - dq3;
				q5 <= q4 - dq4;
				dq0 <= q0;
				dq1 <= q1;
				dq2 <= q2;
				dq3 <= q3;
				dq4 <= q4;
			end
			else
			begin
				counter <= counter + 1'd1;
				x5 <= 0;
				q5 <= 0;
				req <= 1'd0;
			end


			y1 <= y1 + x5;
			y2 <= y2 + y1;
			y3 <= y3 + y2;
			y4 <= y4 + y3;
			y5 <= y5 + y4;

			s1 <= s1 + q5;
			s2 <= s2 + s1;
			s3 <= s3 + s2;
			s4 <= s4 + s3;
			s5 <= s5 + s4;
		end
		else
		begin
			req <= 1'd0;
		end
	end
endmodule
module CicInterpM5(
	input clock,
	input clock_en,
	output reg req,
	input signed [IBITS-1:0] x_real,
	input signed [IBITS-1:0] x_imag,
	output signed [OBITS-1:0] y_real,
	output signed [OBITS-1:0] y_imag
	);

	
	parameter RRRR = 320;
	parameter IBITS = 20;
	parameter OBITS = 16;
	parameter GBITS = 34;

	localparam CBITS = IBITS + GBITS;

	reg [8:0] counter;

	reg signed [CBITS-1:0] x0, x1, x2, x3, x4, x5, dx0, dx1, dx2, dx3, dx4;
	reg signed [CBITS-1:0] y1, y2, y3, y4, y5;
	reg signed [CBITS-1:0] q0, q1, q2, q3, q4, q5, dq0, dq1, dq2, dq3, dq4;
	reg signed [CBITS-1:0] s1, s2, s3, s4, s5;

	wire signed [CBITS-1:0] sxtxr, sxtxi;
	assign sxtxr = {{(CBITS - IBITS){x_real[IBITS-1]}}, x_real};
	assign sxtxi = {{(CBITS - IBITS){x_imag[IBITS-1]}}, x_imag};
	assign y_real = y5[CBITS-1 -:OBITS] + y5[(CBITS-1)-OBITS];
	assign y_imag = s5[CBITS-1 -:OBITS] + s5[(CBITS-1)-OBITS];
	
	initial
	begin
		counter = 0;
		req = 0;
	end

	always @(posedge clock)
	begin
		if (clock_en)
		begin

			if (counter == RRRR - 1)
			begin
				counter <= 1'd0;
				x0 <= sxtxr;
				q0 <= sxtxi;
				req <= 1'd1;

				x1 <= x0 - dx0;
				x2 <= x1 - dx1;			
				x3 <= x2 - dx2;				
				x4 <= x3 - dx3;				
				x5 <= x4 - dx4;			
				dx0 <= x0;
				dx1 <= x1;
				dx2 <= x2;
				dx3 <= x3;
				dx4 <= x4;

				q1 <= q0 - dq0;
				q2 <= q1 - dq1;
				q3 <= q2 - dq2;
				q4 <= q3 - dq3;
				q5 <= q4 - dq4;
				dq0 <= q0;
				dq1 <= q1;
				dq2 <= q2;
				dq3 <= q3;
				dq4 <= q4;
			end
			else
			begin
				counter <= counter + 1'd1;
				x5 <= 0;
				q5 <= 0;
				req <= 1'd0;
			end


			y1 <= y1 + x5;
			y2 <= y2 + y1;
			y3 <= y3 + y2;
			y4 <= y4 + y3;
			y5 <= y5 + y4;

			s1 <= s1 + q5;
			s2 <= s2 + s1;
			s3 <= s3 + s2;
			s4 <= s4 + s3;
			s5 <= s5 + s4;
		end
		else
		begin
			req <= 1'd0;
		end
	end
endmodule