data/full_repos/permissive/154123726/3rdParty/simd/SIMD_comp.v
1: b'%Error: data/full_repos/permissive/154123726/3rdParty/simd/SIMD_comp.v:84: Cannot find file containing module: \'FFT_128\'\n  FFT_128 myFFT128(.clk(clk),\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/FFT_128\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/FFT_128.v\n             data/full_repos/permissive/154123726/3rdParty/simd,data/full_repos/permissive/154123726/FFT_128.sv\n             FFT_128\n             FFT_128.v\n             FFT_128.sv\n             obj_dir/FFT_128\n             obj_dir/FFT_128.v\n             obj_dir/FFT_128.sv\n%Error: data/full_repos/permissive/154123726/3rdParty/simd/SIMD_comp.v:92: Cannot find file containing module: \'Round\'\n Round myRound(.clk(clk),\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/SIMD_comp.v:153: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                                                  : ... In instance SIMD_Compress\n  else if(state == step1 && counter==4\'d5)\n                                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/154123726/3rdParty/simd/SIMD_comp.v:210: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                                                  : ... In instance SIMD_Compress\n  else if(state == step1 && counter==4\'d5)\n                                   ^~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module SIMD_Compress(clk,
					rst_n,
					init,
					enable,
					Final,
					M, 
					IA, 
					IB, 
					IC, 
					ID, 
					OA, 
					OB, 
					OC, 
					OD
					);
	

	input          clk;
	input          rst_n;
	input          init;
	input          enable;
	input          Final;	
	input  [511:0] M;	
	input  [127:0] IA;
	input  [127:0] IB;
	input  [127:0] IC;
	input  [127:0] ID;
	

	output [127:0] OA;
	output [127:0] OB;
	output [127:0] OC;
	output [127:0] OD;

	parameter idle = 4'd0;
	parameter step1 = 4'd1;
	parameter rounds = 4'd2;
	

	wire   [127:0] ORA;
	wire   [127:0] ORB;
	wire   [127:0] ORC;
	wire   [127:0] ORD;
	

	wire   [128*10-1:0] yw;
	

	reg    [  3:0] state;
	

	reg    [  5:0] counter;
	

	reg    [128*10-1:0] y;
    
	
	

	reg    [127:0] SA;
	reg    [127:0] SB;
	reg    [127:0] SC;
	reg    [127:0] SD;
	reg            enableRound;
	
  FFT_128 myFFT128(.clk(clk),
				   .rst_n(rst_n),				   
				   .init(enable),
				   .Final(Final),
				   .yi(M),
				   .yo(yw)
					
				   );
	Round myRound(.clk(clk),
				  .rst_n(rst_n),				  
				  .init(enableRound),
				  .IA(SA),
				  .IB(SB),
				  .IC(SC),
				  .ID(SD),
				  .y(y), 
				  .IV0(IA), 
				  .IV1(IB), 
				  .IV2(IC), 
				  .IV3(ID),
				  .OA(ORA),
				  .OB(ORB),
				  .OC(ORC),
				  .OD(ORD)				  
				  );

	assign OA = SA;
	assign OB = SB;
	assign OC = SC;
	assign OD = SD;

	

	always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			state <= idle;
		else if(init == 1'b1)
			state <= idle;
		else if(enable == 1'b1)
			state <= step1;
		else if(state == step1 && counter == 6'd6)
			state <= rounds;
		else if(state == rounds && counter == 6'h23)
			state <= idle;
		else
			state <= state;
	end	
	

	always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			counter <= 6'd0;
		else if(init == 1'b1)
			counter <= 6'd0;
		else if(state == idle || enable == 1'b1)
			counter <= 6'd0;
		else if(state == step1 && counter == 6'd6) 
			counter <= 6'd0;
		else
			counter <= counter + 1;
	end
	

	always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			enableRound <= 1'd0;
		else if(state == step1 && counter==4'd5)
			enableRound <= 1'd1;
		else
			enableRound <= 1'd0;
	end


	always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
		begin
			SA <= 128'd0;
			SB <= 128'd0;
			SC <= 128'd0;
			SD <= 128'd0;		
		end
		else if(enable)
		begin
			SA <= IA ^ M[127:0];
			SB <= IB ^ M[255:128];
			SC <= IC ^ M[383:256];
			SD <= ID ^ M[511:384];

			
		end
		else if(state == rounds)
		begin
			SA <= ORA;
			SB <= ORB;
			SC <= ORC;
			SD <= ORD;
		end
		else
		begin
			SA <= SA;
			SB <= SB;
			SC <= SC;
			SD <= SD;		
		end
	end
	

	wire [9:0] y_wire_vector [127:0];
	genvar g;
	generate 
	for(g=0; g<128;g=g+1)
	begin:gen_g
		assign y_wire_vector [g] = yw[(g+1)*10-1:g*10];
		
	end
	endgenerate 	
	

	always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			y <= 0;
		else if(state == step1 && counter==4'd5)
			y <=yw;

		else
			y <= y;
	end
	

endmodule
module SIMD_Compress(clk,
					rst_n,
					init,
					enable,
					Final,
					M, 
					IA, 
					IB, 
					IC, 
					ID, 
					OA, 
					OB, 
					OC, 
					OD
					);

	

	input          clk;
	input          rst_n;
	input          init;
	input          enable;
	input          Final;	
	input  [511:0] M;	
	input  [127:0] IA;
	input  [127:0] IB;
	input  [127:0] IC;
	input  [127:0] ID;
	

	output [127:0] OA;
	output [127:0] OB;
	output [127:0] OC;
	output [127:0] OD;

	parameter idle = 4'd0;
	parameter step1 = 4'd1;
	parameter rounds = 4'd2;
	

	wire   [127:0] ORA;
	wire   [127:0] ORB;
	wire   [127:0] ORC;
	wire   [127:0] ORD;
	

	wire   [128*10-1:0] yw;
	

	reg    [  3:0] state;
	

	reg    [  5:0] counter;
	

	reg    [128*10-1:0] y;
    
	
	

	reg    [127:0] SA;
	reg    [127:0] SB;
	reg    [127:0] SC;
	reg    [127:0] SD;
	reg            enableRound;
	
  FFT_128 myFFT128(.clk(clk),
				   .rst_n(rst_n),				   
				   .init(enable),
				   .Final(Final),
				   .yi(M),
				   .yo(yw)
					
				   );
	Round myRound(.clk(clk),
				  .rst_n(rst_n),				  
				  .init(enableRound),
				  .IA(SA),
				  .IB(SB),
				  .IC(SC),
				  .ID(SD),
				  .y(y), 
				  .IV0(IA), 
				  .IV1(IB), 
				  .IV2(IC), 
				  .IV3(ID),
				  .OA(ORA),
				  .OB(ORB),
				  .OC(ORC),
				  .OD(ORD)				  
				  );

	assign OA = SA;
	assign OB = SB;
	assign OC = SC;
	assign OD = SD;

	

	always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			state <= idle;
		else if(init == 1'b1)
			state <= idle;
		else if(enable == 1'b1)
			state <= step1;
		else if(state == step1 && counter == 6'd6)
			state <= rounds;
		else if(state == rounds && counter == 6'h23)
			state <= idle;
		else
			state <= state;
	end	
	

	always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			counter <= 6'd0;
		else if(init == 1'b1)
			counter <= 6'd0;
		else if(state == idle || enable == 1'b1)
			counter <= 6'd0;
		else if(state == step1 && counter == 6'd6) 
			counter <= 6'd0;
		else
			counter <= counter + 1;
	end
	

	always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			enableRound <= 1'd0;
		else if(state == step1 && counter==4'd5)
			enableRound <= 1'd1;
		else
			enableRound <= 1'd0;
	end


	always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
		begin
			SA <= 128'd0;
			SB <= 128'd0;
			SC <= 128'd0;
			SD <= 128'd0;		
		end
		else if(enable)
		begin
			SA <= IA ^ M[127:0];
			SB <= IB ^ M[255:128];
			SC <= IC ^ M[383:256];
			SD <= ID ^ M[511:384];

			
		end
		else if(state == rounds)
		begin
			SA <= ORA;
			SB <= ORB;
			SC <= ORC;
			SD <= ORD;
		end
		else
		begin
			SA <= SA;
			SB <= SB;
			SC <= SC;
			SD <= SD;		
		end
	end
	

	wire [9:0] y_wire_vector [127:0];
	genvar g;
	generate 
	for(g=0; g<128;g=g+1)
	begin:gen_g
		assign y_wire_vector [g] = yw[(g+1)*10-1:g*10];
		
	end
	endgenerate 	
	

	always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			y <= 0;
		else if(state == step1 && counter==4'd5)
			y <=yw;

		else
			y <= y;
	end
	

endmodule