data/full_repos/permissive/20289584/CountUP_TB.v
 line:39 column:2: Illegal character '\x00'
1: b'%Warning-STMTDLY: data/full_repos/permissive/20289584/CountUP_TB.v:35: Unsupported: Ignoring delay on this delayed statement.\nalways #20 clk  = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20289584/CountUP_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\nalways #10  rst = 1;\n       ^\n%Error: data/full_repos/permissive/20289584/CountUP_TB.v:22: Cannot find file containing module: \'Block1\'\nBlock1  test(.df(df),.df_0(df_0),.pin_name3(clk),.pin_name9(rst),.pa(CountOut),.pb(CountOut1),.pb_s(pb_s),.pb_d(pb_d),.pb_h(pb_h),.pin_name59(pin_name59),.pin_name544(pin_name544),.ssel(ssel),.dd(dd),.cc(aa),.nn(nn),.gg(cc));\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20289584,data/full_repos/permissive/20289584/Block1\n             data/full_repos/permissive/20289584,data/full_repos/permissive/20289584/Block1.v\n             data/full_repos/permissive/20289584,data/full_repos/permissive/20289584/Block1.sv\n             Block1\n             Block1.v\n             Block1.sv\n             obj_dir/Block1\n             obj_dir/Block1.v\n             obj_dir/Block1.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CountUP_TB;



parameter Bitwidth = 4;



reg clk,rst;
reg pb_s,pb_d,pb_h;
reg df,df_0,ed;
wire [1:0]ssel;
wire  pc,pd,pe,pf,q,pin_nameaaa;
wire [3:0] pin_name59,pin_name544,dd,aa,nn,cc;
wire [Bitwidth-1:0] CountOut;
wire [Bitwidth-1:0] CountOut1;
wire Carry;


Block1  test(.df(df),.df_0(df_0),.pin_name3(clk),.pin_name9(rst),.pa(CountOut),.pb(CountOut1),.pb_s(pb_s),.pb_d(pb_d),.pb_h(pb_h),.pin_name59(pin_name59),.pin_name544(pin_name544),.ssel(ssel),.dd(dd),.cc(aa),.nn(nn),.gg(cc));


initial
begin
	pb_h=1;
	pb_d=1;
	pb_s=1;
	df = 0;
	df_0 = 0;
	clk = 0;
	rst = 0;
end
always #20 clk  = ~clk;
always #10  rst = 1;

endmodule
module CountUP_TB;




parameter Bitwidth = 4;



reg clk,rst;
reg pb_s,pb_d,pb_h;
reg df,df_0,ed;
wire [1:0]ssel;
wire  pc,pd,pe,pf,q,pin_nameaaa;
wire [3:0] pin_name59,pin_name544,dd,aa,nn,cc;
wire [Bitwidth-1:0] CountOut;
wire [Bitwidth-1:0] CountOut1;
wire Carry;


Block1  test(.df(df),.df_0(df_0),.pin_name3(clk),.pin_name9(rst),.pa(CountOut),.pb(CountOut1),.pb_s(pb_s),.pb_d(pb_d),.pb_h(pb_h),.pin_name59(pin_name59),.pin_name544(pin_name544),.ssel(ssel),.dd(dd),.cc(aa),.nn(nn),.gg(cc));


initial
begin
	pb_h=1;
	pb_d=1;
	pb_s=1;
	df = 0;
	df_0 = 0;
	clk = 0;
	rst = 0;
end
always #20 clk  = ~clk;
always #10  rst = 1;

endmodule