data/full_repos/permissive/157436936/ex4/D_FF.v
data/verilator_xmls/b66e3e12-8f3a-4564-86d5-21ad224ab43b.xml
module D_FF(q, clk, d, rst_n);
	output reg q;
	input clk;
	input d;
	input rst_n;
	
	always @(posedge clk or negedge rst_n)
		if (!rst_n)
			q <= 1'b0;
		else
			q <= d;
	
endmodule
module D_FF(q, clk, d, rst_n);

	output reg q;
	input clk;
	input d;
	input rst_n;
	
	always @(posedge clk or negedge rst_n)
		if (!rst_n)
			q <= 1'b0;
		else
			q <= d;
	
endmodule