data/full_repos/permissive/102394571/fsmtest_sim.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #10 speed = 4\'b0001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #10 btnr = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #1 btnr = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 1;speed = 4\'b0001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 0;speed = 4\'b0001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 1;speed = 4\'b0001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 0;speed = 4\'b0001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 1;speed = 4\'b0001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #10 t_expired = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/102394571/fsmtest_sim.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #1  clk =  ! clk;\n  ^\n%Error: data/full_repos/permissive/102394571/fsmtest_sim.v:72: Can\'t find definition of variable: \'t_expired\'\n  #10 t_expired = 1;speed = 4\'b0001;\n      ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fsmtest_sim;


	reg clk;
	reg btnl;
	reg btnd;
	reg btnr;
	reg btnp;
	reg btnu;
	reg [3:0] speed;


	wire [7:2] led;
	wire [6:0] seg;
	wire [3:0] an;


	FSMTest uut (
		.clk(clk), 
		.btnl(btnl), 
		.btnd(btnd), 
		.btnr(btnr), 
		.btnp(btnp), 
		.btnu(btnu), 
		.speed(speed), 
		.led(led), 
		.seg(seg), 
		.an(an)
	);

	initial begin

		clk = 0;
		btnl = 0;
		btnd = 0;
		btnr = 0;
		btnp = 0;
		btnu = 0;
		speed = 0;


		#100;
        

		#10 speed = 4'b0001;
		#10 btnr = 1;
		#1 btnr = 0;
		#10 t_expired = 1;speed = 4'b0001;
		#10 t_expired = 0;speed = 4'b0001;
		#10 t_expired = 1;speed = 4'b0001;
		#10 t_expired = 0;speed = 4'b0001;
		#10 t_expired = 1;speed = 4'b0001;
		#10 t_expired = 0;
	end
   always 
		#1  clk =  ! clk;
endmodule
module fsmtest_sim;



	reg clk;
	reg btnl;
	reg btnd;
	reg btnr;
	reg btnp;
	reg btnu;
	reg [3:0] speed;


	wire [7:2] led;
	wire [6:0] seg;
	wire [3:0] an;


	FSMTest uut (
		.clk(clk), 
		.btnl(btnl), 
		.btnd(btnd), 
		.btnr(btnr), 
		.btnp(btnp), 
		.btnu(btnu), 
		.speed(speed), 
		.led(led), 
		.seg(seg), 
		.an(an)
	);

	initial begin

		clk = 0;
		btnl = 0;
		btnd = 0;
		btnr = 0;
		btnp = 0;
		btnu = 0;
		speed = 0;


		#100;
        

		#10 speed = 4'b0001;
		#10 btnr = 1;
		#1 btnr = 0;
		#10 t_expired = 1;speed = 4'b0001;
		#10 t_expired = 0;speed = 4'b0001;
		#10 t_expired = 1;speed = 4'b0001;
		#10 t_expired = 0;speed = 4'b0001;
		#10 t_expired = 1;speed = 4'b0001;
		#10 t_expired = 0;
	end
   always 
		#1  clk =  ! clk;
endmodule