data/full_repos/permissive/158845296/add.v
data/verilator_xmls/24530233-f299-4cb1-8a97-45c5af7e7e0e.xml
module add
(
    input  [31:0] A, B,
    output [31:0] C
);

    assign C = A + B;

endmodule
module add
(
    input  [31:0] A, B,
    output [31:0] C
);


    assign C = A + B;

endmodule