data/full_repos/permissive/202448421/rtl/audio/I2C_AUD_Config.v
1: b'%Warning-WIDTH: data/full_repos/permissive/202448421/rtl/audio/I2C_AUD_Config.v:55: Operator LT expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'mI2C_CLK_DIV\' generates 16 bits.\n                                                                                  : ... In instance I2C_AUD_Config\n  if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/202448421/rtl/audio/I2C_AUD_Config.v:65: Cannot find file containing module: \'I2C_Controller\'\nI2C_Controller  u0 ( .CLOCK(mI2C_CTRL_CLK),   \n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202448421/rtl/audio,data/full_repos/permissive/202448421/I2C_Controller\n             data/full_repos/permissive/202448421/rtl/audio,data/full_repos/permissive/202448421/I2C_Controller.v\n             data/full_repos/permissive/202448421/rtl/audio,data/full_repos/permissive/202448421/I2C_Controller.sv\n             I2C_Controller\n             I2C_Controller.v\n             I2C_Controller.sv\n             obj_dir/I2C_Controller\n             obj_dir/I2C_Controller.v\n             obj_dir/I2C_Controller.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module I2C_AUD_Config (
						o_I2C_END,
						iCLK,
						iRST_N,

						I2C_SCLK,
						I2C_SDAT	);

input		iCLK;
input		iRST_N;

output		I2C_SCLK;
inout		I2C_SDAT;
output      o_I2C_END ;

reg	[15:0]	mI2C_CLK_DIV;
reg	[23:0]	mI2C_DATA;
reg			mI2C_CTRL_CLK;
reg			mI2C_GO;
wire		mI2C_END;
wire		mI2C_ACK;
reg	[15:0]	LUT_DATA;
reg	[3:0]	LUT_INDEX;
reg	[1:0]	mSetup_ST;
reg         o_I2C_END;

parameter	CLK_Freq	=	50000000;
parameter	I2C_Freq	=	20000;

parameter	LUT_SIZE	=	12;

parameter	Dummy_DATA	=	0;
parameter	REG_REST	=	1;
parameter	SET_LIN_L	=	2;
parameter	SET_LIN_R	=	3;
parameter	SET_HEAD_L	=	4;
parameter	SET_HEAD_R	=	5;
parameter	A_PATH_CTRL	=	6;
parameter	D_PATH_CTRL	=	7;
parameter	POWER_ON	=	8;
parameter	SET_FORMAT	=	9;
parameter	SAMPLE_CTRL	=	10;
parameter	SET_ACTIVE	=	11;


always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		mI2C_CTRL_CLK	<=	0;
		mI2C_CLK_DIV	<=	0;
	end
	else
	begin
		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
		else
		begin
			mI2C_CLK_DIV	<=	0;
			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
		end
	end
end

I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),
						.I2C_SCLK(I2C_SCLK),
 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),
						.I2C_DATA(mI2C_DATA),
						.GO(mI2C_GO),
						.END(mI2C_END),
						.ACK(mI2C_ACK),
						.RESET(iRST_N)	);


always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		LUT_INDEX	<=	0;
		mSetup_ST	<=	0;
		mI2C_GO		<=	0;
	end
	else
	begin
		if(LUT_INDEX<LUT_SIZE)
		begin
				 o_I2C_END <= 0 ;
			case(mSetup_ST)
			0:	begin
					mI2C_DATA	<=	{8'h34,LUT_DATA};
					mI2C_GO		<=	1;
					mSetup_ST	<=	1;
				end
			1:	begin
					if(mI2C_END)
					begin
						if(!mI2C_ACK)
						mSetup_ST	<=	2;
						else
						mSetup_ST	<=	0;							
						mI2C_GO		<=	0;
					end
				end
			2:	begin
					LUT_INDEX	<=	LUT_INDEX+1;
					mSetup_ST	<=	0;
				end
			endcase
		end
				else begin
				o_I2C_END <= 1 ;end
	end
end


always
begin
	case(LUT_INDEX)

	Dummy_DATA	:	LUT_DATA	<=	16'h0000;
	REG_REST	:	LUT_DATA	<=	16'h1E00;
	SET_LIN_L	:	LUT_DATA	<=	16'h001A;
	SET_LIN_R	:	LUT_DATA	<=	16'h021A;
	SET_HEAD_L	:	LUT_DATA	<=	16'h047B;
	SET_HEAD_R	:	LUT_DATA	<=	16'h067B;


	A_PATH_CTRL	:	LUT_DATA	<=	16'h0812;
	D_PATH_CTRL	:	LUT_DATA	<=	16'h0A06;
	POWER_ON	:	LUT_DATA	<=	16'h0C00;
	SET_FORMAT	:	LUT_DATA	<=	16'h0E01;
	SAMPLE_CTRL	:	LUT_DATA	<=	16'h1002;
	SET_ACTIVE	:	LUT_DATA	<=	16'h1201;
	default		:	LUT_DATA	<=	16'h0000;
	endcase
end

endmodule
module I2C_AUD_Config (
						o_I2C_END,
						iCLK,
						iRST_N,

						I2C_SCLK,
						I2C_SDAT	);


input		iCLK;
input		iRST_N;

output		I2C_SCLK;
inout		I2C_SDAT;
output      o_I2C_END ;

reg	[15:0]	mI2C_CLK_DIV;
reg	[23:0]	mI2C_DATA;
reg			mI2C_CTRL_CLK;
reg			mI2C_GO;
wire		mI2C_END;
wire		mI2C_ACK;
reg	[15:0]	LUT_DATA;
reg	[3:0]	LUT_INDEX;
reg	[1:0]	mSetup_ST;
reg         o_I2C_END;

parameter	CLK_Freq	=	50000000;
parameter	I2C_Freq	=	20000;

parameter	LUT_SIZE	=	12;

parameter	Dummy_DATA	=	0;
parameter	REG_REST	=	1;
parameter	SET_LIN_L	=	2;
parameter	SET_LIN_R	=	3;
parameter	SET_HEAD_L	=	4;
parameter	SET_HEAD_R	=	5;
parameter	A_PATH_CTRL	=	6;
parameter	D_PATH_CTRL	=	7;
parameter	POWER_ON	=	8;
parameter	SET_FORMAT	=	9;
parameter	SAMPLE_CTRL	=	10;
parameter	SET_ACTIVE	=	11;


always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		mI2C_CTRL_CLK	<=	0;
		mI2C_CLK_DIV	<=	0;
	end
	else
	begin
		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
		else
		begin
			mI2C_CLK_DIV	<=	0;
			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
		end
	end
end

I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),
						.I2C_SCLK(I2C_SCLK),
 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),
						.I2C_DATA(mI2C_DATA),
						.GO(mI2C_GO),
						.END(mI2C_END),
						.ACK(mI2C_ACK),
						.RESET(iRST_N)	);


always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		LUT_INDEX	<=	0;
		mSetup_ST	<=	0;
		mI2C_GO		<=	0;
	end
	else
	begin
		if(LUT_INDEX<LUT_SIZE)
		begin
				 o_I2C_END <= 0 ;
			case(mSetup_ST)
			0:	begin
					mI2C_DATA	<=	{8'h34,LUT_DATA};
					mI2C_GO		<=	1;
					mSetup_ST	<=	1;
				end
			1:	begin
					if(mI2C_END)
					begin
						if(!mI2C_ACK)
						mSetup_ST	<=	2;
						else
						mSetup_ST	<=	0;							
						mI2C_GO		<=	0;
					end
				end
			2:	begin
					LUT_INDEX	<=	LUT_INDEX+1;
					mSetup_ST	<=	0;
				end
			endcase
		end
				else begin
				o_I2C_END <= 1 ;end
	end
end


always
begin
	case(LUT_INDEX)

	Dummy_DATA	:	LUT_DATA	<=	16'h0000;
	REG_REST	:	LUT_DATA	<=	16'h1E00;
	SET_LIN_L	:	LUT_DATA	<=	16'h001A;
	SET_LIN_R	:	LUT_DATA	<=	16'h021A;
	SET_HEAD_L	:	LUT_DATA	<=	16'h047B;
	SET_HEAD_R	:	LUT_DATA	<=	16'h067B;


	A_PATH_CTRL	:	LUT_DATA	<=	16'h0812;
	D_PATH_CTRL	:	LUT_DATA	<=	16'h0A06;
	POWER_ON	:	LUT_DATA	<=	16'h0C00;
	SET_FORMAT	:	LUT_DATA	<=	16'h0E01;
	SAMPLE_CTRL	:	LUT_DATA	<=	16'h1002;
	SET_ACTIVE	:	LUT_DATA	<=	16'h1201;
	default		:	LUT_DATA	<=	16'h0000;
	endcase
end

endmodule