data/full_repos/permissive/143278/vhdl_tests/pr2541625.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/vhdl_tests/pr2541625.v:8: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top();
  wire out1, out2;

  child c1(1, 0, out1);
  child c2(1, 1, out2);

  initial begin
    #1;
    if (out1 !== 0)
      $display("FAILED -- out1 !== 0");
    else if (out2 !== 1)
      $display("FAILED -- out2 !== 1");
    else
      $display("PASSED");
  end

endmodule
module top();

  wire out1, out2;

  child c1(1, 0, out1);
  child c2(1, 1, out2);

  initial begin
    #1;
    if (out1 !== 0)
      $display("FAILED -- out1 !== 0");
    else if (out2 !== 1)
      $display("FAILED -- out2 !== 1");
    else
      $display("PASSED");
  end

endmodule