data/full_repos/permissive/211316121/lab5_3/74LS175.v
data/verilator_xmls/93f50b06-d055-44ed-bd4b-14b8d3f620cf.xml
module CLKDIV(
    input clkstd,
    output clk
);
reg [28:0] q;

always@(posedge clkstd)
    q<=q+1;

assign clk=q[26];

endmodule
module CLKDIV(
    input clkstd,
    output clk
);

reg [28:0] q;

always@(posedge clkstd)
    q<=q+1;

assign clk=q[26];

endmodule