data/full_repos/permissive/123690745/EqualBranch.v
'utf-8' codec can't decode byte 0xb7 in position 1938: invalid start byte
1: b'%Warning-MULTITOP: data/full_repos/permissive/123690745/EqualBranch.v:72: Multiple top level modules\n                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                        : ... Top module \'BranchControl\'\nmodule BranchControl(\n       ^~~~~~~~~~~~~\n                                                                        : ... Top module \'beqALU\'\nmodule beqALU(\n       ^~~~~~\n%Error: data/full_repos/permissive/123690745/EqualBranch.v:80: Cannot find file containing module: \'bitExtender18to32\'\n bitExtender18to32 bitExtender18to32(.In(ImmediateM4),.Out(ImmediateExt),.sign(1\'b1));\n ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/bitExtender18to32\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/bitExtender18to32.v\n             data/full_repos/permissive/123690745,data/full_repos/permissive/123690745/bitExtender18to32.sv\n             bitExtender18to32\n             bitExtender18to32.v\n             bitExtender18to32.sv\n             obj_dir/bitExtender18to32\n             obj_dir/bitExtender18to32.v\n             obj_dir/bitExtender18to32.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module BranchControl(
	 input [31:0] PCD,
	 input FlushE,
		
	 input signed [1:0] EqualZeroD,
    input signed [1:0] EqualD,
    input jal,
	 input jalr,
    input jr,
	 input j,
	 
	 input beq,
	 input bne,
	 input blez,
	 input bgtz,
	 input bltz,
	 input bgez,
	 input bltzall, 
	 
	 input eret,
	 
    output reg [2:0] BranchSelect = 0,
	 output reg Nullify = 0,
	 output reg AtDelaySlotF = 0
    );
	 always @(*) begin
		AtDelaySlotF = 0;
		BranchSelect = 0;
		Nullify = 0;
		if (jal || j) BranchSelect = 2;
		if (jr || jalr) BranchSelect = 3;
		if (beq && EqualD == 0) BranchSelect = 1;
		if (bne && EqualD != 0) BranchSelect = 1;
		if (blez && EqualZeroD <= 0) BranchSelect = 1;
		if (bgtz && EqualZeroD > 0) BranchSelect = 1;
		if (bltz && EqualZeroD < 0) BranchSelect = 1;
		if (bgez && EqualZeroD >= 0) BranchSelect = 1;
		
		if (bltzall && EqualZeroD == -1) BranchSelect = 1;
		if (bltzall && EqualZeroD != -1) Nullify = 1;
		
		if (eret) BranchSelect = 4;
		
		if (BranchSelect != 0) AtDelaySlotF = 1;
		

		
	 end

endmodule
module BranchControl(
	 input [31:0] PCD,
	 input FlushE,
		
	 input signed [1:0] EqualZeroD,
    input signed [1:0] EqualD,
    input jal,
	 input jalr,
    input jr,
	 input j,
	 
	 input beq,
	 input bne,
	 input blez,
	 input bgtz,
	 input bltz,
	 input bgez,
	 input bltzall, 
	 
	 input eret,
	 
    output reg [2:0] BranchSelect = 0,
	 output reg Nullify = 0,
	 output reg AtDelaySlotF = 0
    );

	 always @(*) begin
		AtDelaySlotF = 0;
		BranchSelect = 0;
		Nullify = 0;
		if (jal || j) BranchSelect = 2;
		if (jr || jalr) BranchSelect = 3;
		if (beq && EqualD == 0) BranchSelect = 1;
		if (bne && EqualD != 0) BranchSelect = 1;
		if (blez && EqualZeroD <= 0) BranchSelect = 1;
		if (bgtz && EqualZeroD > 0) BranchSelect = 1;
		if (bltz && EqualZeroD < 0) BranchSelect = 1;
		if (bgez && EqualZeroD >= 0) BranchSelect = 1;
		
		if (bltzall && EqualZeroD == -1) BranchSelect = 1;
		if (bltzall && EqualZeroD != -1) Nullify = 1;
		
		if (eret) BranchSelect = 4;
		
		if (BranchSelect != 0) AtDelaySlotF = 1;
		

		
	 end

endmodule