data/full_repos/permissive/188868339/src/CPU_6502_Top.v
 line:52: before: ","
1: b"%Error: data/full_repos/permissive/188868339/src/CPU_6502_Top.v:29: Cannot find file containing module: 'REG_FILE'\n REG_FILE REG_FILE(CLKOUT_1, CLKOUT_2, RDY, rst, ACC_EN, IDX_EN, IDY_EN, SP_EN, PC_EN,\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188868339/src,data/full_repos/permissive/188868339/REG_FILE\n             data/full_repos/permissive/188868339/src,data/full_repos/permissive/188868339/REG_FILE.v\n             data/full_repos/permissive/188868339/src,data/full_repos/permissive/188868339/REG_FILE.sv\n             REG_FILE\n             REG_FILE.v\n             REG_FILE.sv\n             obj_dir/REG_FILE\n             obj_dir/REG_FILE.v\n             obj_dir/REG_FILE.sv\n%Error: data/full_repos/permissive/188868339/src/CPU_6502_Top.v:52: Cannot find file containing module: 'REG_EN_8bit'\n REG_EN_8bit ADH(clk, res,  ,  , A[7:0]); \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/188868339/src/CPU_6502_Top.v:53: Cannot find file containing module: 'REG_EN_8bit'\n REG_EN_8bit ADL(clk, res,  ,  , A[15:8]); \n ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module CPU_6502_Top(
    input clk,
    input res,
    input RDY,
    input IRQ,
    input NMI,
    output SYNC,
    output SO,
    output CLKOUT_2,
    output CLKOUT_1,
    output RW,
    output [15:0]ADDR_BUS,
    inout [7:0]DATA_BUS
);
	

	assign CLKOUT_2 = clk;
	assign CLKOUT_1 = ~clk;
	

	REG_FILE REG_FILE(CLKOUT_1, CLKOUT_2, RDY, rst, ACC_EN, IDX_EN, IDY_EN, SP_EN, PC_EN,
	SR_EN, ACC_D, IDX_D, IDY_D, SP_D, PC_D, SR_D, ACC_Q, IDX_Q, IDY_Q, SP_Q, PC_Q, SR_Q);
	
	wire ACC_EN;
	wire IDX_EN;
	wire IDY_EN;
	wire SP_EN;
	wire PC_EN;
	wire SR_EN;
	wire [7:0] ACC_D;
	wire [7:0] IDX_D;
	wire [7:0] IDY_D;
	wire [7:0] SP_D;
	wire [7:0] PC_D;
	wire [7:0] SR_D;
	wire [7:0] ACC_Q;
	wire [7:0] IDX_Q;
	wire [7:0] IDY_Q;
	wire [15:0] SP_Q;
	wire [7:0] PC_Q;
	wire [7:0] SR_Q;
	

	REG_EN_8bit ADH(clk, res,,, A[7:0]); 
	REG_EN_8bit ADL(clk, res,,, A[15:8]); 
	

	
	


endmodule
module CPU_6502_Top(
    input clk,
    input res,
    input RDY,
    input IRQ,
    input NMI,
    output SYNC,
    output SO,
    output CLKOUT_2,
    output CLKOUT_1,
    output RW,
    output [15:0]ADDR_BUS,
    inout [7:0]DATA_BUS
);

	

	assign CLKOUT_2 = clk;
	assign CLKOUT_1 = ~clk;
	

	REG_FILE REG_FILE(CLKOUT_1, CLKOUT_2, RDY, rst, ACC_EN, IDX_EN, IDY_EN, SP_EN, PC_EN,
	SR_EN, ACC_D, IDX_D, IDY_D, SP_D, PC_D, SR_D, ACC_Q, IDX_Q, IDY_Q, SP_Q, PC_Q, SR_Q);
	
	wire ACC_EN;
	wire IDX_EN;
	wire IDY_EN;
	wire SP_EN;
	wire PC_EN;
	wire SR_EN;
	wire [7:0] ACC_D;
	wire [7:0] IDX_D;
	wire [7:0] IDY_D;
	wire [7:0] SP_D;
	wire [7:0] PC_D;
	wire [7:0] SR_D;
	wire [7:0] ACC_Q;
	wire [7:0] IDX_Q;
	wire [7:0] IDY_Q;
	wire [15:0] SP_Q;
	wire [7:0] PC_Q;
	wire [7:0] SR_Q;
	

	REG_EN_8bit ADH(clk, res,,, A[7:0]); 
	REG_EN_8bit ADL(clk, res,,, A[15:8]); 
	

	
	


endmodule