data/full_repos/permissive/137416811/openfpga_flow/benchmarks/quicklogic_tests/io_reg/io_reg.v
data/verilator_xmls/19bdb5b4-0a6b-485a-b5fb-027e32ed0f1f.xml
module io_reg(clk, in, out);

    input clk;
    input in;
    output out;
    reg out;



    always @(posedge clk)
    begin
        out <= in;
    end
    

    
endmodule
module io_reg(clk, in, out);


    input clk;
    input in;
    output out;
    reg out;



    always @(posedge clk)
    begin
        out <= in;
    end
    

    
endmodule