data/full_repos/permissive/152249767/src/mem_test_mpu/src/mem_mpu_old.v
1: b"%Error: data/full_repos/permissive/152249767/src/mem_test_mpu/src/mem_mpu_old.v:95: Duplicate declaration of signal: 'is_legal_accces'\n    reg is_legal_accces;                             \n        ^~~~~~~~~~~~~~~\n        data/full_repos/permissive/152249767/src/mem_test_mpu/src/mem_mpu_old.v:40: ... Location of original declaration\n        output reg is_legal_accces,      \n                   ^~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module mem_mpu #(
        parameter integer MEM_WORDS      = 1024,
        parameter integer DATA_WIDTH     = 32,
        
        parameter integer MPU_START_ADDR = 768,
        parameter integer MPU_ITEM_NUM   = 16,
        parameter integer MPU_ITEM_LEN   = 5
    )(
        input wire clk,
        input wire resetn,
        

        input wire is_inst,
        output reg inform_cpu_wait,
        

        input wire [31:0] pc_addr,
        

        output reg interrupt,
        output reg is_legal_accces,
        

        input wire        cpu_valid,
        output reg        cpu_ready,
        input wire [21:0] cpu_addr,
        input wire [31:0] cpu_wdata,
        input wire [ 3:0] cpu_wstrb,
        output reg [31:0] cpu_rdata,
		


		output reg [3:0]  mem_wen,
        output reg [21:0] mem_addr,
        output reg [31:0] mem_wdata,
        input wire [31:0] mem_rdata
	);


    wire [3:0]  mpu_mem_wen;
    assign mpu_mem_wen = (cpu_valid && !cpu_ready && cpu_addr < 4*MEM_WORDS) ? cpu_wstrb : 4'b0;
    

    wire [31:0] pc_word_addr;
    assign pc_word_addr = pc_addr/4;
    

    reg do_read_inst;
    reg do_read_data;
    reg do_write_data;
    
    reg do_read_inst_ok;
    reg do_read_data_ok;
    reg do_write_data_ok;
    
    reg [2:0] temp_reg;
    
    wire is_data_op;
    assign is_data_op = do_read_data || do_write_data;
    

    reg [3:0]  mpu2mem_wen;
    reg [21:0] mpu2mem_addr;
    reg [31:0] mpu2mem_wdata;
    reg [31:0] mpu2mem_rdata;
    

    reg [3:0]  cache2mem_wen;
    reg [21:0] cache2mem_addr;
    reg [1:0]  temp_count;
    


	reg [DATA_WIDTH-1:0] mpu_cache[MPU_ITEM_NUM*MPU_ITEM_LEN:0];  
	reg cache_need_mod;
    reg is_legal_accces;
    reg access_control_ok;
    reg [21:0] item_count;
    integer i;
    integer fine_item;
    

	always @(posedge clk) begin 
        if (!resetn) begin
            cache_need_mod <= 1'b1;
            is_legal_accces <= 1'b1;
            fine_item <= MPU_ITEM_NUM+1;
            access_control_ok <= 1;
            
            inform_cpu_wait <=0;
            cpu_ready <=0;
            temp_reg <= 0;
            
            do_read_inst <=0;
            do_read_data <=0;
            do_write_data<=0;
            
            interrupt <= 0;
           
            cache2mem_wen <= 4'b0000;
            cache2mem_addr <= MPU_START_ADDR;
            
            item_count<= 0;
            temp_count<= 0;
        end
	end
    

    always @(posedge clk) begin
        if (!cpu_valid) begin
            cpu_ready <= 0;  
        end
        if (do_read_inst_ok || do_read_data_ok || do_write_data_ok) begin
            cpu_ready <= 1;             
            inform_cpu_wait<=0;
            do_read_inst <=0;
            do_read_data <= 0;
            do_write_data <=0;
            
            do_read_inst_ok <=0;
            do_read_data_ok <=0;
            do_write_data_ok <=0;
            
            is_legal_accces <= 1;
            fine_item <= MPU_ITEM_NUM+1;
            
            temp_reg <= 0;
            temp_count<= 0;
        end
    end
    

    always @(posedge clk) begin
        if(cpu_ready) begin
            temp_reg <= temp_reg+1;
            if (temp_reg[1:0] == 2'b11) begin
                cpu_ready <= 0;
                temp_reg <= 0;
            end
        end
    end
	

	always @(posedge clk) begin
        if (resetn) begin
            if (!is_data_op && !interrupt && is_inst && do_read_inst==0 && !cpu_ready && cpu_valid) begin
                do_read_inst <= 1;
                inform_cpu_wait <=1;

                mem_wen  <= mpu_mem_wen;
                mem_addr <= cpu_addr;
                temp_reg <= 0;
            end
        end
    end
    

    always @(posedge clk) begin
        if (!is_data_op && !interrupt && do_read_inst) begin
            temp_reg <= temp_reg+1;
            if (temp_reg[0:0]==1) begin
                do_read_inst_ok <= 1;
                cpu_rdata <= mem_rdata;
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn) begin
            if (!is_inst) begin
                if(!is_data_op && cpu_valid && !cpu_ready) begin

                    if (mpu_mem_wen==4'b0000) begin

                        do_read_data <= 1;
                        inform_cpu_wait <=1;
                        
                        mpu2mem_wen <= mpu_mem_wen;
                        mpu2mem_addr <= cpu_addr;
                        mpu2mem_rdata <= mem_rdata;
                    end
                    else begin

                        do_write_data <= 1;
                        inform_cpu_wait <=1;
                        
                        mpu2mem_wen <= mpu_mem_wen;
                        mpu2mem_addr <= cpu_addr;
                        mpu2mem_wdata <= cpu_wdata;
                    end
                end
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn && is_data_op) begin
            if (cache_need_mod && item_count<= MPU_ITEM_NUM * MPU_ITEM_LEN) begin
                mem_wen <= cache2mem_wen;
                mem_addr <= cache2mem_addr+item_count;
                temp_count <= temp_count+1;
                if (temp_count[0:0] == 1) begin

                    mpu_cache[item_count] <= mem_rdata;
                    item_count <= item_count+1;
                end
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn && is_data_op) begin
            if (cache_need_mod && item_count> MPU_ITEM_NUM * MPU_ITEM_LEN) begin
                cache_need_mod <= 0;
                item_count <= 0;
                temp_count <= 0;
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn && is_data_op) begin
            if (!cache_need_mod) begin

                for(i=0;i<MPU_ITEM_NUM;i=i+1) begin

                    if(pc_word_addr>=mpu_cache[i*MPU_ITEM_LEN+1] && pc_word_addr<=mpu_cache[i*MPU_ITEM_LEN+2]) begin

                        if(mpu2mem_addr>=mpu_cache[i*MPU_ITEM_LEN+3] && mpu2mem_addr<=mpu_cache[i*MPU_ITEM_LEN+4]) begin

                            fine_item = i;   
                        end
                    end
                end

                if(fine_item<MPU_ITEM_NUM) begin
                    if (do_read_data && mpu_cache[fine_item*MPU_ITEM_LEN+5][2:2]!=1'b1)
                        is_legal_accces <= 0;
                    if (do_write_data && mpu_cache[fine_item*MPU_ITEM_LEN+5][1:1]!=1'b1)
                        is_legal_accces <= 0;
                end
                else begin
                    is_legal_accces <= 0;
                end
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn && is_data_op) begin
            if(is_data_op && !is_legal_accces) begin

                interrupt <= 1;
                inform_cpu_wait <= 0;
                cpu_ready <= 1;
            end
        end
    end
    

    always @(posedge clk) begin
        if (interrupt) begin

            do_read_data <=0;
            do_write_data <=0;
            if(!is_data_op) begin
                interrupt<=0;
                is_legal_accces <=1;
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn && is_data_op) begin
            if(do_read_data && is_legal_accces && !cache_need_mod) begin
                mem_wen <= mpu2mem_wen;
                mem_addr <= mpu2mem_addr;
                

                cpu_rdata <= mem_rdata;
                
                temp_count <= temp_count+1;
                if(temp_count[0:0] == 1) begin
                    if(mpu2mem_wen == 4'b0000) begin
                        do_read_data_ok <= 1;
                    end
                end
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn && is_data_op) begin
            if(do_write_data && is_legal_accces && !cache_need_mod) begin

                mem_wen <= mpu2mem_wen;
                mem_addr <= mpu2mem_addr;

                temp_count <= temp_count+1;
                if(temp_count[0:0] == 1) begin
                    if(mpu2mem_wen != 4'b0000) begin
                        do_write_data_ok <= 1;
                        mem_wdata <= mpu2mem_wdata;
                    end
                end

                if (MPU_START_ADDR<=mpu2mem_addr && mpu2mem_addr<= MPU_START_ADDR+MPU_ITEM_NUM*MPU_ITEM_LEN) begin
                    mpu_cache[mpu2mem_addr-MPU_START_ADDR] <= mpu2mem_wdata;
                end
            end
        end
    end
    
endmodule
module mem_mpu #(
        parameter integer MEM_WORDS      = 1024,
        parameter integer DATA_WIDTH     = 32,
        
        parameter integer MPU_START_ADDR = 768,
        parameter integer MPU_ITEM_NUM   = 16,
        parameter integer MPU_ITEM_LEN   = 5
    )(
        input wire clk,
        input wire resetn,
        

        input wire is_inst,
        output reg inform_cpu_wait,
        

        input wire [31:0] pc_addr,
        

        output reg interrupt,
        output reg is_legal_accces,
        

        input wire        cpu_valid,
        output reg        cpu_ready,
        input wire [21:0] cpu_addr,
        input wire [31:0] cpu_wdata,
        input wire [ 3:0] cpu_wstrb,
        output reg [31:0] cpu_rdata,
		


		output reg [3:0]  mem_wen,
        output reg [21:0] mem_addr,
        output reg [31:0] mem_wdata,
        input wire [31:0] mem_rdata
	);



    wire [3:0]  mpu_mem_wen;
    assign mpu_mem_wen = (cpu_valid && !cpu_ready && cpu_addr < 4*MEM_WORDS) ? cpu_wstrb : 4'b0;
    

    wire [31:0] pc_word_addr;
    assign pc_word_addr = pc_addr/4;
    

    reg do_read_inst;
    reg do_read_data;
    reg do_write_data;
    
    reg do_read_inst_ok;
    reg do_read_data_ok;
    reg do_write_data_ok;
    
    reg [2:0] temp_reg;
    
    wire is_data_op;
    assign is_data_op = do_read_data || do_write_data;
    

    reg [3:0]  mpu2mem_wen;
    reg [21:0] mpu2mem_addr;
    reg [31:0] mpu2mem_wdata;
    reg [31:0] mpu2mem_rdata;
    

    reg [3:0]  cache2mem_wen;
    reg [21:0] cache2mem_addr;
    reg [1:0]  temp_count;
    


	reg [DATA_WIDTH-1:0] mpu_cache[MPU_ITEM_NUM*MPU_ITEM_LEN:0];  
	reg cache_need_mod;
    reg is_legal_accces;
    reg access_control_ok;
    reg [21:0] item_count;
    integer i;
    integer fine_item;
    

	always @(posedge clk) begin 
        if (!resetn) begin
            cache_need_mod <= 1'b1;
            is_legal_accces <= 1'b1;
            fine_item <= MPU_ITEM_NUM+1;
            access_control_ok <= 1;
            
            inform_cpu_wait <=0;
            cpu_ready <=0;
            temp_reg <= 0;
            
            do_read_inst <=0;
            do_read_data <=0;
            do_write_data<=0;
            
            interrupt <= 0;
           
            cache2mem_wen <= 4'b0000;
            cache2mem_addr <= MPU_START_ADDR;
            
            item_count<= 0;
            temp_count<= 0;
        end
	end
    

    always @(posedge clk) begin
        if (!cpu_valid) begin
            cpu_ready <= 0;  
        end
        if (do_read_inst_ok || do_read_data_ok || do_write_data_ok) begin
            cpu_ready <= 1;             
            inform_cpu_wait<=0;
            do_read_inst <=0;
            do_read_data <= 0;
            do_write_data <=0;
            
            do_read_inst_ok <=0;
            do_read_data_ok <=0;
            do_write_data_ok <=0;
            
            is_legal_accces <= 1;
            fine_item <= MPU_ITEM_NUM+1;
            
            temp_reg <= 0;
            temp_count<= 0;
        end
    end
    

    always @(posedge clk) begin
        if(cpu_ready) begin
            temp_reg <= temp_reg+1;
            if (temp_reg[1:0] == 2'b11) begin
                cpu_ready <= 0;
                temp_reg <= 0;
            end
        end
    end
	

	always @(posedge clk) begin
        if (resetn) begin
            if (!is_data_op && !interrupt && is_inst && do_read_inst==0 && !cpu_ready && cpu_valid) begin
                do_read_inst <= 1;
                inform_cpu_wait <=1;

                mem_wen  <= mpu_mem_wen;
                mem_addr <= cpu_addr;
                temp_reg <= 0;
            end
        end
    end
    

    always @(posedge clk) begin
        if (!is_data_op && !interrupt && do_read_inst) begin
            temp_reg <= temp_reg+1;
            if (temp_reg[0:0]==1) begin
                do_read_inst_ok <= 1;
                cpu_rdata <= mem_rdata;
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn) begin
            if (!is_inst) begin
                if(!is_data_op && cpu_valid && !cpu_ready) begin

                    if (mpu_mem_wen==4'b0000) begin

                        do_read_data <= 1;
                        inform_cpu_wait <=1;
                        
                        mpu2mem_wen <= mpu_mem_wen;
                        mpu2mem_addr <= cpu_addr;
                        mpu2mem_rdata <= mem_rdata;
                    end
                    else begin

                        do_write_data <= 1;
                        inform_cpu_wait <=1;
                        
                        mpu2mem_wen <= mpu_mem_wen;
                        mpu2mem_addr <= cpu_addr;
                        mpu2mem_wdata <= cpu_wdata;
                    end
                end
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn && is_data_op) begin
            if (cache_need_mod && item_count<= MPU_ITEM_NUM * MPU_ITEM_LEN) begin
                mem_wen <= cache2mem_wen;
                mem_addr <= cache2mem_addr+item_count;
                temp_count <= temp_count+1;
                if (temp_count[0:0] == 1) begin

                    mpu_cache[item_count] <= mem_rdata;
                    item_count <= item_count+1;
                end
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn && is_data_op) begin
            if (cache_need_mod && item_count> MPU_ITEM_NUM * MPU_ITEM_LEN) begin
                cache_need_mod <= 0;
                item_count <= 0;
                temp_count <= 0;
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn && is_data_op) begin
            if (!cache_need_mod) begin

                for(i=0;i<MPU_ITEM_NUM;i=i+1) begin

                    if(pc_word_addr>=mpu_cache[i*MPU_ITEM_LEN+1] && pc_word_addr<=mpu_cache[i*MPU_ITEM_LEN+2]) begin

                        if(mpu2mem_addr>=mpu_cache[i*MPU_ITEM_LEN+3] && mpu2mem_addr<=mpu_cache[i*MPU_ITEM_LEN+4]) begin

                            fine_item = i;   
                        end
                    end
                end

                if(fine_item<MPU_ITEM_NUM) begin
                    if (do_read_data && mpu_cache[fine_item*MPU_ITEM_LEN+5][2:2]!=1'b1)
                        is_legal_accces <= 0;
                    if (do_write_data && mpu_cache[fine_item*MPU_ITEM_LEN+5][1:1]!=1'b1)
                        is_legal_accces <= 0;
                end
                else begin
                    is_legal_accces <= 0;
                end
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn && is_data_op) begin
            if(is_data_op && !is_legal_accces) begin

                interrupt <= 1;
                inform_cpu_wait <= 0;
                cpu_ready <= 1;
            end
        end
    end
    

    always @(posedge clk) begin
        if (interrupt) begin

            do_read_data <=0;
            do_write_data <=0;
            if(!is_data_op) begin
                interrupt<=0;
                is_legal_accces <=1;
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn && is_data_op) begin
            if(do_read_data && is_legal_accces && !cache_need_mod) begin
                mem_wen <= mpu2mem_wen;
                mem_addr <= mpu2mem_addr;
                

                cpu_rdata <= mem_rdata;
                
                temp_count <= temp_count+1;
                if(temp_count[0:0] == 1) begin
                    if(mpu2mem_wen == 4'b0000) begin
                        do_read_data_ok <= 1;
                    end
                end
            end
        end
    end
    

    always @(posedge clk) begin
        if (resetn && is_data_op) begin
            if(do_write_data && is_legal_accces && !cache_need_mod) begin

                mem_wen <= mpu2mem_wen;
                mem_addr <= mpu2mem_addr;

                temp_count <= temp_count+1;
                if(temp_count[0:0] == 1) begin
                    if(mpu2mem_wen != 4'b0000) begin
                        do_write_data_ok <= 1;
                        mem_wdata <= mpu2mem_wdata;
                    end
                end

                if (MPU_START_ADDR<=mpu2mem_addr && mpu2mem_addr<= MPU_START_ADDR+MPU_ITEM_NUM*MPU_ITEM_LEN) begin
                    mpu_cache[mpu2mem_addr-MPU_START_ADDR] <= mpu2mem_wdata;
                end
            end
        end
    end
    
endmodule