data/full_repos/permissive/161356276/hdl/rtl/hpdmc/hpdmc_datactl.v
1: b"%Error: data/full_repos/permissive/161356276/hdl/rtl/hpdmc/hpdmc_datactl.v:108: Cannot find file containing module: 'hpdmc_banktimer'\nhpdmc_banktimer banktimer0(\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161356276/hdl/rtl/hpdmc,data/full_repos/permissive/161356276/hpdmc_banktimer\n             data/full_repos/permissive/161356276/hdl/rtl/hpdmc,data/full_repos/permissive/161356276/hpdmc_banktimer.v\n             data/full_repos/permissive/161356276/hdl/rtl/hpdmc,data/full_repos/permissive/161356276/hpdmc_banktimer.sv\n             hpdmc_banktimer\n             hpdmc_banktimer.v\n             hpdmc_banktimer.sv\n             obj_dir/hpdmc_banktimer\n             obj_dir/hpdmc_banktimer.v\n             obj_dir/hpdmc_banktimer.sv\n%Error: data/full_repos/permissive/161356276/hdl/rtl/hpdmc/hpdmc_datactl.v:119: Cannot find file containing module: 'hpdmc_banktimer'\nhpdmc_banktimer banktimer1(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/rtl/hpdmc/hpdmc_datactl.v:130: Cannot find file containing module: 'hpdmc_banktimer'\nhpdmc_banktimer banktimer2(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161356276/hdl/rtl/hpdmc/hpdmc_datactl.v:140: Cannot find file containing module: 'hpdmc_banktimer'\nhpdmc_banktimer banktimer3(\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module hpdmc_datactl(
	input sys_clk,
	input sdram_rst,

	input read,
	input write,
	input [3:0] concerned_bank,
	output reg read_safe,
	output reg write_safe,
	output [3:0] precharge_safe,

	output reg direction,
	output direction_r,

	input tim_cas,
	input [1:0] tim_wr
);



reg [2:0] read_safe_counter;
always @(posedge sys_clk) begin
	if(sdram_rst) begin
		read_safe_counter <= 3'd0;
		read_safe <= 1'b1;
	end else begin
		if(read) begin
			read_safe_counter <= 3'd3;
			read_safe <= 1'b0;
		end else if(write) begin

			read_safe_counter <= 3'd5;
			read_safe <= 1'b0;
		end else begin
			if(read_safe_counter == 3'd1)
				read_safe <= 1'b1;
			if(~read_safe)
				read_safe_counter <= read_safe_counter - 3'd1;
		end
	end
end



reg [2:0] write_safe_counter;
always @(posedge sys_clk) begin
	if(sdram_rst) begin
		write_safe_counter <= 3'd0;
		write_safe <= 1'b1;
	end else begin
		if(read) begin
			write_safe_counter <= {1'b1, tim_cas, ~tim_cas};
			write_safe <= 1'b0;
		end else if(write) begin
			write_safe_counter <= 3'd4;
			write_safe <= 1'b0;
		end else begin
			if(write_safe_counter == 3'd1)
				write_safe <= 1'b1;
			if(~write_safe)
				write_safe_counter <= write_safe_counter - 3'd1;
		end
	end
end

reg [1:0] counter_writedirection;
always @(posedge sys_clk) begin
	if(sdram_rst) begin
		counter_writedirection <= 2'd0;
	end else begin
		if(write)
			counter_writedirection <= 2'd3;
		else if(|counter_writedirection)
			counter_writedirection <= counter_writedirection - 2'd1;
	end
end

reg direction0;
always @(posedge sys_clk) begin
	direction <= ~(write | (|counter_writedirection));

end


hpdmc_banktimer banktimer0(
	.sys_clk(sys_clk),
	.sdram_rst(sdram_rst),

	.tim_cas(tim_cas),
	.tim_wr(tim_wr),

	.read(read & concerned_bank[0]),
	.write(write & concerned_bank[0]),
	.precharge_safe(precharge_safe[0])
);
hpdmc_banktimer banktimer1(
	.sys_clk(sys_clk),
	.sdram_rst(sdram_rst),

	.tim_cas(tim_cas),
	.tim_wr(tim_wr),

	.read(read & concerned_bank[1]),
	.write(write & concerned_bank[1]),
	.precharge_safe(precharge_safe[1])
);
hpdmc_banktimer banktimer2(
	.sys_clk(sys_clk),
	.sdram_rst(sdram_rst),

	.tim_cas(tim_cas),
	.tim_wr(tim_wr),

	.read(read & concerned_bank[2]),
	.write(write & concerned_bank[2]),	.precharge_safe(precharge_safe[2])
);
hpdmc_banktimer banktimer3(
	.sys_clk(sys_clk),
	.sdram_rst(sdram_rst),

	.tim_cas(tim_cas),
	.tim_wr(tim_wr),

	.read(read & concerned_bank[3]),
	.write(write & concerned_bank[3]),
	.precharge_safe(precharge_safe[3])
);

endmodule
module hpdmc_datactl(
	input sys_clk,
	input sdram_rst,

	input read,
	input write,
	input [3:0] concerned_bank,
	output reg read_safe,
	output reg write_safe,
	output [3:0] precharge_safe,

	output reg direction,
	output direction_r,

	input tim_cas,
	input [1:0] tim_wr
);




reg [2:0] read_safe_counter;
always @(posedge sys_clk) begin
	if(sdram_rst) begin
		read_safe_counter <= 3'd0;
		read_safe <= 1'b1;
	end else begin
		if(read) begin
			read_safe_counter <= 3'd3;
			read_safe <= 1'b0;
		end else if(write) begin

			read_safe_counter <= 3'd5;
			read_safe <= 1'b0;
		end else begin
			if(read_safe_counter == 3'd1)
				read_safe <= 1'b1;
			if(~read_safe)
				read_safe_counter <= read_safe_counter - 3'd1;
		end
	end
end



reg [2:0] write_safe_counter;
always @(posedge sys_clk) begin
	if(sdram_rst) begin
		write_safe_counter <= 3'd0;
		write_safe <= 1'b1;
	end else begin
		if(read) begin
			write_safe_counter <= {1'b1, tim_cas, ~tim_cas};
			write_safe <= 1'b0;
		end else if(write) begin
			write_safe_counter <= 3'd4;
			write_safe <= 1'b0;
		end else begin
			if(write_safe_counter == 3'd1)
				write_safe <= 1'b1;
			if(~write_safe)
				write_safe_counter <= write_safe_counter - 3'd1;
		end
	end
end

reg [1:0] counter_writedirection;
always @(posedge sys_clk) begin
	if(sdram_rst) begin
		counter_writedirection <= 2'd0;
	end else begin
		if(write)
			counter_writedirection <= 2'd3;
		else if(|counter_writedirection)
			counter_writedirection <= counter_writedirection - 2'd1;
	end
end

reg direction0;
always @(posedge sys_clk) begin
	direction <= ~(write | (|counter_writedirection));

end


hpdmc_banktimer banktimer0(
	.sys_clk(sys_clk),
	.sdram_rst(sdram_rst),

	.tim_cas(tim_cas),
	.tim_wr(tim_wr),

	.read(read & concerned_bank[0]),
	.write(write & concerned_bank[0]),
	.precharge_safe(precharge_safe[0])
);
hpdmc_banktimer banktimer1(
	.sys_clk(sys_clk),
	.sdram_rst(sdram_rst),

	.tim_cas(tim_cas),
	.tim_wr(tim_wr),

	.read(read & concerned_bank[1]),
	.write(write & concerned_bank[1]),
	.precharge_safe(precharge_safe[1])
);
hpdmc_banktimer banktimer2(
	.sys_clk(sys_clk),
	.sdram_rst(sdram_rst),

	.tim_cas(tim_cas),
	.tim_wr(tim_wr),

	.read(read & concerned_bank[2]),
	.write(write & concerned_bank[2]),	.precharge_safe(precharge_safe[2])
);
hpdmc_banktimer banktimer3(
	.sys_clk(sys_clk),
	.sdram_rst(sdram_rst),

	.tim_cas(tim_cas),
	.tim_wr(tim_wr),

	.read(read & concerned_bank[3]),
	.write(write & concerned_bank[3]),
	.precharge_safe(precharge_safe[3])
);

endmodule