data/full_repos/permissive/137454634/count.v
None: at end of input
1: b'%Warning-MULTITOP: data/full_repos/permissive/137454634/count.v:40: Multiple top level modules\n                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                  : ... Top module \'counter_run\'\nmodule counter_run(endRun,CP,CP_H,StRun);\n       ^~~~~~~~~~~\n                                                                  : ... Top module \'counter_open\'\nmodule counter_open(endOpen,dispStage,CP,StOpen,pause,close);\n       ^~~~~~~~~~~~\n                                                                  : ... Top module \'delaybutton\'\nmodule delaybutton(pause,CP,delay);\n       ^~~~~~~~~~~\n                                                                  : ... Top module \'divideclk\'\nmodule divideclk(clk4hz,clk32hz,StRun,StOpen);\n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module divideclk(clk4hz,clk32hz,StRun,StOpen);

input clk32hz,StRun,StOpen;
output reg clk4hz;
reg[2:0] count=3'b000;

always @(posedge clk32hz)
	begin
		if (!StRun && !StOpen) clk4hz<=1'b1;
		else if (count==3'b111) begin clk4hz<=1'b1;count<=3'b000;end
		else begin clk4hz<=1'b0 ;count<=count+1'b1;end
	end

endmodule
module divideclk(clk4hz,clk32hz,StRun,StOpen);


input clk32hz,StRun,StOpen;
output reg clk4hz;
reg[2:0] count=3'b000;

always @(posedge clk32hz)
	begin
		if (!StRun && !StOpen) clk4hz<=1'b1;
		else if (count==3'b111) begin clk4hz<=1'b1;count<=3'b000;end
		else begin clk4hz<=1'b0 ;count<=count+1'b1;end
	end

endmodule