data/full_repos/permissive/125927162/PISO/piso.v
data/verilator_xmls/21626cab-4931-40c4-a356-6c0e4b1f6da0.xml
module piso (clk, latch, din, ser, dout, rst);
   parameter WIDTH = 8;
   input clk;
   input latch;
   input rst;
   input ser;
   input [WIDTH-1:0] din;
   output reg 	     dout;

   reg [WIDTH-1:0]   data;
   
   always @ (posedge clk) begin
      if (rst) begin
	 data <= 0;
	 dout <= 0;
      end
      else if (latch)
	data <= din;
      else begin
	 dout <= data[0];
	 data[WIDTH-2:0] <= data[WIDTH-1:1];
	 data[WIDTH-1] <= ser;
      end
   end

endmodule
module piso (clk, latch, din, ser, dout, rst);

   parameter WIDTH = 8;
   input clk;
   input latch;
   input rst;
   input ser;
   input [WIDTH-1:0] din;
   output reg 	     dout;

   reg [WIDTH-1:0]   data;
   
   always @ (posedge clk) begin
      if (rst) begin
	 data <= 0;
	 dout <= 0;
      end
      else if (latch)
	data <= din;
      else begin
	 dout <= data[0];
	 data[WIDTH-2:0] <= data[WIDTH-1:1];
	 data[WIDTH-1] <= ser;
      end
   end

endmodule