data/full_repos/permissive/137454634/state_control.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/cc081652-c86e-4fcc-b502-d475dd1c6ec5.xml
module state_control(opendoor,mv2nxt,position,clk,switch,eff_req,ud_mode,endRun,endOpen,upReq,downReq);

input clk,switch,endRun,endOpen;
input [3:0] eff_req,upReq,downReq;
input [1:0] ud_mode;
output reg [3:0] position;
output reg opendoor,mv2nxt;
reg [2:0] state;

always @(posedge clk)
    begin
		if (switch==1'b0)
		begin
			state[2:0]=3'b000;
			opendoor=1'b0;
            mv2nxt=1'b0;
			position=4'b0001;
        end
        else
        begin
            case (state)
            3'b000:state[2:0]=3'b001;
            3'b001:
            begin


                if((|(position & (upReq|downReq))==1)||(|(eff_req & position)==1))
                begin
                    opendoor=1'b1;
                end
                else if ((|ud_mode)==1 && opendoor!=1'b1)
                begin
                    mv2nxt=1;
                    state=3'b010;
                end
    			else state[2:0]=3'b001;
                if (endOpen==1)
                begin
                    opendoor=0;
                    mv2nxt=1;
                    if (ud_mode!=2'b00) state=3'b010;
					else mv2nxt=0;
                end
            end
            3'b010:
            begin
                if(endRun==1)
                begin
                    mv2nxt=0;
                    if(ud_mode==2'b01)
        			begin 
	       			    position=position<<1;
					    state=3'b001;
					end
                    else
                    begin 
					    position=position>>1;
					    state=3'b001;
    				end
                end
            end
            endcase
        end
    end

endmodule
module state_control(opendoor,mv2nxt,position,clk,switch,eff_req,ud_mode,endRun,endOpen,upReq,downReq);


input clk,switch,endRun,endOpen;
input [3:0] eff_req,upReq,downReq;
input [1:0] ud_mode;
output reg [3:0] position;
output reg opendoor,mv2nxt;
reg [2:0] state;

always @(posedge clk)
    begin
		if (switch==1'b0)
		begin
			state[2:0]=3'b000;
			opendoor=1'b0;
            mv2nxt=1'b0;
			position=4'b0001;
        end
        else
        begin
            case (state)
            3'b000:state[2:0]=3'b001;
            3'b001:
            begin


                if((|(position & (upReq|downReq))==1)||(|(eff_req & position)==1))
                begin
                    opendoor=1'b1;
                end
                else if ((|ud_mode)==1 && opendoor!=1'b1)
                begin
                    mv2nxt=1;
                    state=3'b010;
                end
    			else state[2:0]=3'b001;
                if (endOpen==1)
                begin
                    opendoor=0;
                    mv2nxt=1;
                    if (ud_mode!=2'b00) state=3'b010;
					else mv2nxt=0;
                end
            end
            3'b010:
            begin
                if(endRun==1)
                begin
                    mv2nxt=0;
                    if(ud_mode==2'b01)
        			begin 
	       			    position=position<<1;
					    state=3'b001;
					end
                    else
                    begin 
					    position=position>>1;
					    state=3'b001;
    				end
                end
            end
            endcase
        end
    end

endmodule