data/full_repos/permissive/212495825/src/roms.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-MULTITOP: data/full_repos/permissive/212495825/src/roms.v:52: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'MAIN_ROM\'\nmodule MAIN_ROM\n       ^~~~~~~~\n                                                                     : ... Top module \'SUB_ROM\'\nmodule SUB_ROM\n       ^~~~~~~\n                                                                     : ... Top module \'BGCH_ROM\'\nmodule BGCH_ROM\n       ^~~~~~~~\n                                                                     : ... Top module \'SPCH_ROM\'\nmodule SPCH_ROM\n       ^~~~~~~~\n                                                                     : ... Top module \'CLUT1_ROM\'\nmodule CLUT1_ROM\n       ^~~~~~~~~\n                                                                     : ... Top module \'PALET_ROM\'\nmodule PALET_ROM\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/roms.v:20: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                  : ... In instance MAIN_ROM.mrom0\nalways @(posedge CL0) DO0 <= core[AD0];\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/roms.v:21: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'DI1\' generates 8 bits.\n                                                                  : ... In instance MAIN_ROM.mrom0\nalways @(posedge CL1) if (WE1) core[AD1] <= DI1;\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/roms.v:20: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 5 bits.\n                                                                  : ... In instance CLUT1_ROM.clut1l\nalways @(posedge CL0) DO0 <= core[AD0];\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/212495825/src/roms.v:21: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'DI1\' generates 4 bits.\n                                                                  : ... In instance CLUT1_ROM.clut1l\nalways @(posedge CL1) if (WE1) core[AD1] <= DI1;\n                                         ^~\n%Error: Exiting due to 5 warning(s)\n'
module MAIN_ROM
(
	input				clk,
	input  [15:0]	ad,
	output  [7:0]	dt,

	input				ROMCL,
	input	 [17:0]	ROMAD,
	input	  [7:0]	ROMDT,
	input				ROMEN
);

wire [7:0] dt0, dt1, dt2;

DLROM #(13,8) mrom0( clk, ad[12:0], dt0, ROMCL,ROMAD[12:0],ROMDT,ROMEN & (ROMAD[17:13]==5'b00_000) );
DLROM #(13,8) mrom1( clk, ad[12:0], dt1, ROMCL,ROMAD[12:0],ROMDT,ROMEN & (ROMAD[17:13]==5'b00_001) );
DLROM #(13,8) mrom2( clk, ad[12:0], dt2, ROMCL,ROMAD[12:0],ROMDT,ROMEN & (ROMAD[17:13]==5'b00_010) );

assign dt = ( ad[15:13] == 3'b101 ) ? dt0 :
				( ad[15:13] == 3'b110 ) ? dt1 :
				( ad[15:13] == 3'b111 ) ? dt2 :
				8'h00;

endmodule
module MAIN_ROM
(
	input				clk,
	input  [15:0]	ad,
	output  [7:0]	dt,

	input				ROMCL,
	input	 [17:0]	ROMAD,
	input	  [7:0]	ROMDT,
	input				ROMEN
);


wire [7:0] dt0, dt1, dt2;

DLROM #(13,8) mrom0( clk, ad[12:0], dt0, ROMCL,ROMAD[12:0],ROMDT,ROMEN & (ROMAD[17:13]==5'b00_000) );
DLROM #(13,8) mrom1( clk, ad[12:0], dt1, ROMCL,ROMAD[12:0],ROMDT,ROMEN & (ROMAD[17:13]==5'b00_001) );
DLROM #(13,8) mrom2( clk, ad[12:0], dt2, ROMCL,ROMAD[12:0],ROMDT,ROMEN & (ROMAD[17:13]==5'b00_010) );

assign dt = ( ad[15:13] == 3'b101 ) ? dt0 :
				( ad[15:13] == 3'b110 ) ? dt1 :
				( ad[15:13] == 3'b111 ) ? dt2 :
				8'h00;

endmodule