data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v
 line:54: before: ","
1: b'%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n   always #CLKE clk_e <= ~clk_e;  \n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n   always #CLKB b_clk <= ~b_clk;  \n          ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n   always #CLKX clk_x <= ~clk_x;  \n          ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:82: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile ("../vcd/sig_tb.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:83: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n      #DELAY reset = 1; #DE; #DE reset = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n      #DELAY reset = 1; #DE; #DE reset = 0;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n      #DELAY reset = 1; #DE; #DE reset = 0;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n      #DE cycle = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n      #720;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n      #720;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n      #720;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_capture_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n      #720 $finish;\n      ^\n%Error: Exiting due to 2 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module signal_capture_tb;

   parameter DELAY = 3;
   parameter CLKX  = 2.5;
   parameter CLKB  = 5;
   parameter CLKE  = 30;

   parameter DE    = CLKE*2;
   parameter DB    = CLKB*2;
   parameter DX    = CLKX*2;





   reg clk_x = 1'b1, clk_e = 1'b1, b_clk = 1'b1, reset = 1'b0;
   wire n_clk = ~b_clk;

   always #CLKE clk_e <= ~clk_e;
   always #CLKB b_clk <= ~b_clk;
   always #CLKX clk_x <= ~clk_x;





   reg ce = 1'b0, x_ = 1'b0, x = 1'b0;



   reg align = 1'b0, cycle = 1'b0, drift = 1'b0, retry = 1'b0;
   wire d, q, ready, locked, invalid;
   wire error, valid, start;
   wire [3:0] phase;
   wire [3:0] delta;







   initial begin : SIGNAL_TB
      $dumpfile ("../vcd/sig_tb.vcd");
      $dumpvars;

      $display("%12t: Issuing reset.", $time);
      #DELAY reset = 1; #DE; #DE reset = 0;

      $display("%12t: Beginning clock-recovery.", $time);
      #DE cycle = 1;


      #720;
      #720;
      #720;
      #720 $finish;
   end





   always @(posedge clk_e)
     if (reset)
       ce <= #DELAY 1'b0;
     else begin
        x  <= #DELAY $random;
        ce <= #DELAY 1'b1;
     end



   wire p = x_ ^ d;

   always @(negedge clk_e)
     x_ <= #DELAY x;





   signal_stagger
     #( .PHASE_JITTER(1),
        .PHASE_OFFSET(2),
        .CYCLE_JITTER(0)
        ) STAG
       (
        .clk(clk_x),
        .rst(reset),
        .ce (ce),
        .d  (x),
        .q  (d)
        );







   signal_capture
     #( .RATIO    (12),
        .RBITS    (4),
        .RESET    (1),
        .DRIFT    (1),
        .CYCLE    (1),
        .NOISY    (1),
        .DELAY    (DELAY)
        ) SIGCAP
       (
        .clock_i  (clk_x),
        .reset_i  (reset),
        .align_i  (align),
        .cycle_i  (cycle),
        .drift_i  (drift),
        .ready_o  (ready),
        .locked_o (locked),
        .invalid_o(invalid),
        .retry_i  (retry),

        .signal_i(d),
        .signal_o(q)
        );



`ifdef __DO_NOT_USE_YODUT





   wire start, valid, error;
   wire [3:0] phase;
   wire [4:0] delta;

   signal_phase
     #( .RATIO  (12),
        .RBITS  (4),
        .RESET  (1),
        .DRIFT  (1),
        .CYCLE  (1),
        .NOISY  (1),
        .DELAY  (DELAY)
        ) PHASE
       (
        .clk_x_i(clk_x),
        .rst_x_i(reset),

        .clk_e_i(clk_e),
        .sig_e_i(d),

        .align_i(align),
        .cycle_i(cycle),
        .drift_i(drift),
        .start_o(start),
        .phase_o(phase),
        .delta_o(delta),
        .valid_o(valid),
        .error_o(error),
        .retry_i(retry)
        );



`else





   reg        dat_p, dat_n;
   reg        sig_p, sig_n;

   always @(posedge b_clk)
     dat_p <= #DELAY d;

   always @(posedge n_clk)
     dat_n <= #DELAY d;

   always @(posedge b_clk)
     {sig_n, sig_p} <= #DELAY {dat_n, d};


   signal_phase_DDR
     #( .RATIO  (6),
        .RBITS  (3),
        .TICKS  (2),
        .RESET  (1),
        .POLAR  (0),
        .NOISY  (1),
        .DELAY  (DELAY)
        ) PHASE
       (
        .clk_e_i(clk_e),
        .clk_s_i(b_clk),
        .clk_n_i(n_clk),
        .reset_i(reset),

        .enable_i(align),
        .invert_i(1'b0),
        .strobe_o(start),
        .sig_p_i (sig_p),
        .sig_n_i (sig_n),

        .phase_o (phase),
        .delta_o (delta),
        .locked_o(valid),
        .error_o (error),
        .retry_i (retry)
        );
`endif


   
endmodule
module signal_capture_tb;


   parameter DELAY = 3;
   parameter CLKX  = 2.5;
   parameter CLKB  = 5;
   parameter CLKE  = 30;

   parameter DE    = CLKE*2;
   parameter DB    = CLKB*2;
   parameter DX    = CLKX*2;





   reg clk_x = 1'b1, clk_e = 1'b1, b_clk = 1'b1, reset = 1'b0;
   wire n_clk = ~b_clk;

   always #CLKE clk_e <= ~clk_e;
   always #CLKB b_clk <= ~b_clk;
   always #CLKX clk_x <= ~clk_x;





   reg ce = 1'b0, x_ = 1'b0, x = 1'b0;



   reg align = 1'b0, cycle = 1'b0, drift = 1'b0, retry = 1'b0;
   wire d, q, ready, locked, invalid;
   wire error, valid, start;
   wire [3:0] phase;
   wire [3:0] delta;







   initial begin : SIGNAL_TB
      $dumpfile ("../vcd/sig_tb.vcd");
      $dumpvars;

      $display("%12t: Issuing reset.", $time);
      #DELAY reset = 1; #DE; #DE reset = 0;

      $display("%12t: Beginning clock-recovery.", $time);
      #DE cycle = 1;


      #720;
      #720;
      #720;
      #720 $finish;
   end





   always @(posedge clk_e)
     if (reset)
       ce <= #DELAY 1'b0;
     else begin
        x  <= #DELAY $random;
        ce <= #DELAY 1'b1;
     end



   wire p = x_ ^ d;

   always @(negedge clk_e)
     x_ <= #DELAY x;





   signal_stagger
     #( .PHASE_JITTER(1),
        .PHASE_OFFSET(2),
        .CYCLE_JITTER(0)
        ) STAG
       (
        .clk(clk_x),
        .rst(reset),
        .ce (ce),
        .d  (x),
        .q  (d)
        );







   signal_capture
     #( .RATIO    (12),
        .RBITS    (4),
        .RESET    (1),
        .DRIFT    (1),
        .CYCLE    (1),
        .NOISY    (1),
        .DELAY    (DELAY)
        ) SIGCAP
       (
        .clock_i  (clk_x),
        .reset_i  (reset),
        .align_i  (align),
        .cycle_i  (cycle),
        .drift_i  (drift),
        .ready_o  (ready),
        .locked_o (locked),
        .invalid_o(invalid),
        .retry_i  (retry),

        .signal_i(d),
        .signal_o(q)
        );



`ifdef __DO_NOT_USE_YODUT





   wire start, valid, error;
   wire [3:0] phase;
   wire [4:0] delta;

   signal_phase
     #( .RATIO  (12),
        .RBITS  (4),
        .RESET  (1),
        .DRIFT  (1),
        .CYCLE  (1),
        .NOISY  (1),
        .DELAY  (DELAY)
        ) PHASE
       (
        .clk_x_i(clk_x),
        .rst_x_i(reset),

        .clk_e_i(clk_e),
        .sig_e_i(d),

        .align_i(align),
        .cycle_i(cycle),
        .drift_i(drift),
        .start_o(start),
        .phase_o(phase),
        .delta_o(delta),
        .valid_o(valid),
        .error_o(error),
        .retry_i(retry)
        );



`else





   reg        dat_p, dat_n;
   reg        sig_p, sig_n;

   always @(posedge b_clk)
     dat_p <= #DELAY d;

   always @(posedge n_clk)
     dat_n <= #DELAY d;

   always @(posedge b_clk)
     {sig_n, sig_p} <= #DELAY {dat_n, d};


   signal_phase_DDR
     #( .RATIO  (6),
        .RBITS  (3),
        .TICKS  (2),
        .RESET  (1),
        .POLAR  (0),
        .NOISY  (1),
        .DELAY  (DELAY)
        ) PHASE
       (
        .clk_e_i(clk_e),
        .clk_s_i(b_clk),
        .clk_n_i(n_clk),
        .reset_i(reset),

        .enable_i(align),
        .invert_i(1'b0),
        .strobe_o(start),
        .sig_p_i (sig_p),
        .sig_n_i (sig_n),

        .phase_o (phase),
        .delta_o (delta),
        .locked_o(valid),
        .error_o (error),
        .retry_i (retry)
        );
`endif


   
endmodule