data/full_repos/permissive/184916587/ALU_RECV.v
data/verilator_xmls/11c131a4-5f02-45c9-b967-521eab3318de.xml
module sll_32(
	input[31:0] sll_rs1,
	input[31:0] sll_rs2,
	output[31:0] sll_rd
);
	assign sll_rd=sll_rs1<<sll_rs2[4:0];
endmodule
module sll_32(
	input[31:0] sll_rs1,
	input[31:0] sll_rs2,
	output[31:0] sll_rd
);

	assign sll_rd=sll_rs1<<sll_rs2[4:0];
endmodule