data/full_repos/permissive/113756623/Max7219Counter/work/verilog/multi_base_ctr_6.v
1: b"%Error: data/full_repos/permissive/113756623/Max7219Counter/work/verilog/multi_base_ctr_6.v:30: Cannot find file containing module: 'base_ctr_11'\n    base_ctr_11 dctr (\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/base_ctr_11\n             data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/base_ctr_11.v\n             data/full_repos/permissive/113756623/Max7219Counter/work/verilog,data/full_repos/permissive/113756623/base_ctr_11.sv\n             base_ctr_11\n             base_ctr_11.v\n             base_ctr_11.sv\n             obj_dir/base_ctr_11\n             obj_dir/base_ctr_11.v\n             obj_dir/base_ctr_11.sv\n%Error: Exiting due to 1 error(s)\n"
module multi_base_ctr_6 (
    input clk,
    input rst,
    input inc,
    output reg [39:0] digits
  );
  
  localparam DIGITS = 4'h8;
  localparam BASE = 5'h10;
  
  
  wire [(4'h8+0)-1:0] M_dctr_ovf;
  wire [(4'h8+0)*5-1:0] M_dctr_value;
  reg [(4'h8+0)-1:0] M_dctr_inc;
  
  genvar GEN_dctr0;
  generate
  for (GEN_dctr0=0;GEN_dctr0<4'h8;GEN_dctr0=GEN_dctr0+1) begin: dctr_gen_0
    base_ctr_11 dctr (
      .clk(clk),
      .rst(rst),
      .inc(M_dctr_inc[GEN_dctr0*(1)+(1)-1-:(1)]),
      .ovf(M_dctr_ovf[GEN_dctr0*(1)+(1)-1-:(1)]),
      .value(M_dctr_value[GEN_dctr0*(3'h5)+(3'h5)-1-:(3'h5)])
    );
  end
  endgenerate
  
  always @* begin
    M_dctr_inc[0+0-:1] = inc;
    digits = M_dctr_value;
    M_dctr_inc[1+6-:7] = M_dctr_ovf[0+6-:7];
  end
endmodule
module multi_base_ctr_6 (
    input clk,
    input rst,
    input inc,
    output reg [39:0] digits
  );

  
  localparam DIGITS = 4'h8;
  localparam BASE = 5'h10;
  
  
  wire [(4'h8+0)-1:0] M_dctr_ovf;
  wire [(4'h8+0)*5-1:0] M_dctr_value;
  reg [(4'h8+0)-1:0] M_dctr_inc;
  
  genvar GEN_dctr0;
  generate
  for (GEN_dctr0=0;GEN_dctr0<4'h8;GEN_dctr0=GEN_dctr0+1) begin: dctr_gen_0
    base_ctr_11 dctr (
      .clk(clk),
      .rst(rst),
      .inc(M_dctr_inc[GEN_dctr0*(1)+(1)-1-:(1)]),
      .ovf(M_dctr_ovf[GEN_dctr0*(1)+(1)-1-:(1)]),
      .value(M_dctr_value[GEN_dctr0*(3'h5)+(3'h5)-1-:(3'h5)])
    );
  end
  endgenerate
  
  always @* begin
    M_dctr_inc[0+0-:1] = inc;
    digits = M_dctr_value;
    M_dctr_inc[1+6-:7] = M_dctr_ovf[0+6-:7];
  end
endmodule