data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v
1: b'%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:2: Cannot find include file: instr_head.v\n`include "instr_head.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new,data/full_repos/permissive/206017343/instr_head.v\n             data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new,data/full_repos/permissive/206017343/instr_head.v.v\n             data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new,data/full_repos/permissive/206017343/instr_head.v.sv\n             instr_head.v\n             instr_head.v.v\n             instr_head.v.sv\n             obj_dir/instr_head.v\n             obj_dir/instr_head.v.v\n             obj_dir/instr_head.v.sv\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:26: Define or directive not defined: \'`INSTR_TYPE_R\'\n    assign is_add = (opcode == `INSTR_TYPE_R && funct == `INSTR_ADD) ? 1 : 0;\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:26: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n    assign is_add = (opcode == `INSTR_TYPE_R && funct == `INSTR_ADD) ? 1 : 0;\n                                             ^~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:26: Define or directive not defined: \'`INSTR_ADD\'\n    assign is_add = (opcode == `INSTR_TYPE_R && funct == `INSTR_ADD) ? 1 : 0;\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:29: Define or directive not defined: \'`INSTR_ADDIU\'\n    assign is_addiu = (opcode == `INSTR_ADDIU) ? 1 : 0;\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:29: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign is_addiu = (opcode == `INSTR_ADDIU) ? 1 : 0;\n                                             ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:30: Define or directive not defined: \'`INSTR_LUI\'\n    assign is_lui = (opcode == `INSTR_LUI) ? 1 : 0;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:30: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign is_lui = (opcode == `INSTR_LUI) ? 1 : 0;\n                                         ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:31: Define or directive not defined: \'`INSTR_LW\'\n    assign is_lw = (opcode == `INSTR_LW) ? 1 : 0;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:31: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign is_lw = (opcode == `INSTR_LW) ? 1 : 0;\n                                       ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:32: Define or directive not defined: \'`INSTR_SW\'\n    assign is_sw = (opcode == `INSTR_SW) ? 1 : 0;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:32: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign is_sw = (opcode == `INSTR_SW) ? 1 : 0;\n                                       ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:33: Define or directive not defined: \'`INSTR_BEQ\'\n    assign is_beq = (opcode == `INSTR_BEQ) ? 1 : 0;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:33: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign is_beq = (opcode == `INSTR_BEQ) ? 1 : 0;\n                                         ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:34: Define or directive not defined: \'`INSTR_SLTI\'\n    assign is_slti = (opcode == `INSTR_SLTI) ? 1 : 0;\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:34: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign is_slti = (opcode == `INSTR_SLTI) ? 1 : 0;\n                                           ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:37: Define or directive not defined: \'`INSTR_J\'\n    assign is_j = (opcode == `INSTR_J) ? 1 : 0;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:37: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign is_j = (opcode == `INSTR_J) ? 1 : 0;\n                                     ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:41: Define or directive not defined: \'`PCS_BEQ_GO\'\n    assign pcs_ctrl = (is_beq && zero) ? `PCS_BEQ_GO :\n                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:41: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign pcs_ctrl = (is_beq && zero) ? `PCS_BEQ_GO :\n                                                     ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:42: Define or directive not defined: \'`PCS_J\'\n                      (is_j) ? `PCS_J : `PCS_DEFAULT;\n                               ^~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:42: Define or directive not defined: \'`PCS_DEFAULT\'\n                      (is_j) ? `PCS_J : `PCS_DEFAULT;\n                                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:43: Define or directive not defined: \'`DM_WR_ENABLE\'\n    assign dm_we_ctrl = (is_sw) ? `DM_WR_ENABLE : `DM_WR_DISABLE;\n                                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:43: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign dm_we_ctrl = (is_sw) ? `DM_WR_ENABLE : `DM_WR_DISABLE;\n                                                ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:43: Define or directive not defined: \'`DM_WR_DISABLE\'\n    assign dm_we_ctrl = (is_sw) ? `DM_WR_ENABLE : `DM_WR_DISABLE;\n                                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:44: Define or directive not defined: \'`ALU_OP_ADD\'\n    assign alu_op_ctrl = (is_add || is_addiu || is_lw || is_sw) ? `ALU_OP_ADD :\n                                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:44: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign alu_op_ctrl = (is_add || is_addiu || is_lw || is_sw) ? `ALU_OP_ADD :\n                                                                              ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:45: Define or directive not defined: \'`ALU_OP_SUB\'\n                         (is_beq || is_slti) ? `ALU_OP_SUB : `ALU_OP_DEFALUT;\n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:45: Define or directive not defined: \'`ALU_OP_DEFALUT\'\n                         (is_beq || is_slti) ? `ALU_OP_SUB : `ALU_OP_DEFALUT;\n                                                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:46: Define or directive not defined: \'`ALU_SRC_B_RT\'\n    assign alu_src_b_ctrl = (is_add || is_beq || is_slti) ? `ALU_SRC_B_RT :\n                                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:46: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign alu_src_b_ctrl = (is_add || is_beq || is_slti) ? `ALU_SRC_B_RT :\n                                                                          ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:47: Define or directive not defined: \'`ALU_SRC_B_IMM16_SE\'\n                            (is_addiu || is_lw || is_sw) ? `ALU_SRC_B_IMM16_SE : `ALU_SRC_B_DEFALUT;\n                                                           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:47: Define or directive not defined: \'`ALU_SRC_B_DEFALUT\'\n                            (is_addiu || is_lw || is_sw) ? `ALU_SRC_B_IMM16_SE : `ALU_SRC_B_DEFALUT;\n                                                                                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:48: Define or directive not defined: \'`RF_WDATA_LUIM\'\n    assign rf_wdata_ctrl = (is_lui) ? `RF_WDATA_LUIM :\n                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:48: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign rf_wdata_ctrl = (is_lui) ? `RF_WDATA_LUIM :\n                                                     ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:49: Define or directive not defined: \'`RF_WDATA_SLTIM\'\n                           (is_slti) ? `RF_WDATA_SLTIM :\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:50: Define or directive not defined: \'`RF_WDATA_DM\'\n                           (is_lw) ? `RF_WDATA_DM : \n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:51: Define or directive not defined: \'`RF_WDATA_ALU\'\n                           (is_add || is_addiu) ? `RF_WDATA_ALU : `RF_WDATA_DEFALUT;\n                                                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:51: Define or directive not defined: \'`RF_WDATA_DEFALUT\'\n                           (is_add || is_addiu) ? `RF_WDATA_ALU : `RF_WDATA_DEFALUT;\n                                                                  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:52: Define or directive not defined: \'`SLTI_ONE\'\n    assign slti_ctrl = (less) ? `SLTI_ONE : `SLTI_ZERO;\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:52: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign slti_ctrl = (less) ? `SLTI_ONE : `SLTI_ZERO;\n                                          ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:52: Define or directive not defined: \'`SLTI_ZERO\'\n    assign slti_ctrl = (less) ? `SLTI_ONE : `SLTI_ZERO;\n                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:53: Define or directive not defined: \'`RF_WR_ENABLE\'\n    assign rf_we_ctrl = (is_lui || is_slti || is_lw || is_add || is_addiu) ?  `RF_WR_ENABLE : `RF_WR_DISABLE;\n                                                                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:53: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign rf_we_ctrl = (is_lui || is_slti || is_lw || is_add || is_addiu) ?  `RF_WR_ENABLE : `RF_WR_DISABLE;\n                                                                                            ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:53: Define or directive not defined: \'`RF_WR_DISABLE\'\n    assign rf_we_ctrl = (is_lui || is_slti || is_lw || is_add || is_addiu) ?  `RF_WR_ENABLE : `RF_WR_DISABLE;\n                                                                                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:54: Define or directive not defined: \'`RF_WAD_RD\'\n    assign rf_wad_ctrl = (is_add) ? `RF_WAD_RD :\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:54: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign rf_wad_ctrl = (is_add) ? `RF_WAD_RD :\n                                               ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:55: Define or directive not defined: \'`RF_WAD_RT\'\n                         (is_lui || is_slti || is_lw || is_addiu) ? `RF_WAD_RT : `RF_WAD_DEFAULT;\n                                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sources_1/new/cu.v:55: Define or directive not defined: \'`RF_WAD_DEFAULT\'\n                         (is_lui || is_slti || is_lw || is_addiu) ? `RF_WAD_RT : `RF_WAD_DEFAULT;\n                                                                                 ^~~~~~~~~~~~~~~\n%Error: Exiting due to 49 error(s)\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module cu(
    input wire[5:0] funct,
    input wire[5:0] opcode,
    input wire zero,
    input wire less, 

    output wire[1:0] pcs_ctrl,
    output wire dm_we_ctrl,
    output wire[1:0] alu_op_ctrl,
    output wire[1:0] alu_src_b_ctrl,
    output wire[2:0] rf_wdata_ctrl,
    output wire slti_ctrl,
    output wire rf_we_ctrl,
    output wire[1:0] rf_wad_ctrl
    );



    wire is_add, is_addiu, is_lui, is_lw, is_sw, is_j, is_beq, is_slti;
    

    assign is_add = (opcode == `INSTR_TYPE_R && funct == `INSTR_ADD) ? 1 : 0;


    assign is_addiu = (opcode == `INSTR_ADDIU) ? 1 : 0;
    assign is_lui = (opcode == `INSTR_LUI) ? 1 : 0;
    assign is_lw = (opcode == `INSTR_LW) ? 1 : 0;
    assign is_sw = (opcode == `INSTR_SW) ? 1 : 0;
    assign is_beq = (opcode == `INSTR_BEQ) ? 1 : 0;
    assign is_slti = (opcode == `INSTR_SLTI) ? 1 : 0;


    assign is_j = (opcode == `INSTR_J) ? 1 : 0;



    assign pcs_ctrl = (is_beq && zero) ? `PCS_BEQ_GO :
                      (is_j) ? `PCS_J : `PCS_DEFAULT;
    assign dm_we_ctrl = (is_sw) ? `DM_WR_ENABLE : `DM_WR_DISABLE;
    assign alu_op_ctrl = (is_add || is_addiu || is_lw || is_sw) ? `ALU_OP_ADD :
                         (is_beq || is_slti) ? `ALU_OP_SUB : `ALU_OP_DEFALUT;
    assign alu_src_b_ctrl = (is_add || is_beq || is_slti) ? `ALU_SRC_B_RT :
                            (is_addiu || is_lw || is_sw) ? `ALU_SRC_B_IMM16_SE : `ALU_SRC_B_DEFALUT;
    assign rf_wdata_ctrl = (is_lui) ? `RF_WDATA_LUIM :
                           (is_slti) ? `RF_WDATA_SLTIM :
                           (is_lw) ? `RF_WDATA_DM : 
                           (is_add || is_addiu) ? `RF_WDATA_ALU : `RF_WDATA_DEFALUT;
    assign slti_ctrl = (less) ? `SLTI_ONE : `SLTI_ZERO;
    assign rf_we_ctrl = (is_lui || is_slti || is_lw || is_add || is_addiu) ?  `RF_WR_ENABLE : `RF_WR_DISABLE;
    assign rf_wad_ctrl = (is_add) ? `RF_WAD_RD :
                         (is_lui || is_slti || is_lw || is_addiu) ? `RF_WAD_RT : `RF_WAD_DEFAULT;



endmodule
module cu(
    input wire[5:0] funct,
    input wire[5:0] opcode,
    input wire zero,
    input wire less, 

    output wire[1:0] pcs_ctrl,
    output wire dm_we_ctrl,
    output wire[1:0] alu_op_ctrl,
    output wire[1:0] alu_src_b_ctrl,
    output wire[2:0] rf_wdata_ctrl,
    output wire slti_ctrl,
    output wire rf_we_ctrl,
    output wire[1:0] rf_wad_ctrl
    );




    wire is_add, is_addiu, is_lui, is_lw, is_sw, is_j, is_beq, is_slti;
    

    assign is_add = (opcode == `INSTR_TYPE_R && funct == `INSTR_ADD) ? 1 : 0;


    assign is_addiu = (opcode == `INSTR_ADDIU) ? 1 : 0;
    assign is_lui = (opcode == `INSTR_LUI) ? 1 : 0;
    assign is_lw = (opcode == `INSTR_LW) ? 1 : 0;
    assign is_sw = (opcode == `INSTR_SW) ? 1 : 0;
    assign is_beq = (opcode == `INSTR_BEQ) ? 1 : 0;
    assign is_slti = (opcode == `INSTR_SLTI) ? 1 : 0;


    assign is_j = (opcode == `INSTR_J) ? 1 : 0;



    assign pcs_ctrl = (is_beq && zero) ? `PCS_BEQ_GO :
                      (is_j) ? `PCS_J : `PCS_DEFAULT;
    assign dm_we_ctrl = (is_sw) ? `DM_WR_ENABLE : `DM_WR_DISABLE;
    assign alu_op_ctrl = (is_add || is_addiu || is_lw || is_sw) ? `ALU_OP_ADD :
                         (is_beq || is_slti) ? `ALU_OP_SUB : `ALU_OP_DEFALUT;
    assign alu_src_b_ctrl = (is_add || is_beq || is_slti) ? `ALU_SRC_B_RT :
                            (is_addiu || is_lw || is_sw) ? `ALU_SRC_B_IMM16_SE : `ALU_SRC_B_DEFALUT;
    assign rf_wdata_ctrl = (is_lui) ? `RF_WDATA_LUIM :
                           (is_slti) ? `RF_WDATA_SLTIM :
                           (is_lw) ? `RF_WDATA_DM : 
                           (is_add || is_addiu) ? `RF_WDATA_ALU : `RF_WDATA_DEFALUT;
    assign slti_ctrl = (less) ? `SLTI_ONE : `SLTI_ZERO;
    assign rf_we_ctrl = (is_lui || is_slti || is_lw || is_add || is_addiu) ?  `RF_WR_ENABLE : `RF_WR_DISABLE;
    assign rf_wad_ctrl = (is_add) ? `RF_WAD_RD :
                         (is_lui || is_slti || is_lw || is_addiu) ? `RF_WAD_RT : `RF_WAD_DEFAULT;



endmodule