data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/ram.v
 line:62: before: "_user_irq_1_intr"
1: b'%Error: data/full_repos/permissive/172396252/WRAMPsys.srcs/sources_1/ram.v:40: Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above 1024\n                                                                             : ... In instance ram\n  for (i = 0; i < RAM_WIDTH; i = i + 1) begin\n  ^~~\n%Error: Exiting due to 1 error(s)\n'
module ram(
    input clk,
    input read_en,
    input write_en,
    inout [31:0] data_bus,
    input [19:0] address_bus
    );

	parameter RAM_WIDTH = 'h4000;

	reg [31:0] data;
	reg [31:0] ram[0:RAM_WIDTH-1];

	assign data_bus = read_en ? data : 32'hzzzzzzzz;


	genvar i;
	generate 
		for (i = 0; i < RAM_WIDTH; i = i + 1) begin
			initial ram[i] = 32'hffffffff;
		end
	endgenerate









	always @(posedge clk) begin
		if (write_en) begin
			ram[address_bus] <= data_bus;
		end
		else data <= ram[address_bus];
	end
    
endmodule
module ram(
    input clk,
    input read_en,
    input write_en,
    inout [31:0] data_bus,
    input [19:0] address_bus
    );


	parameter RAM_WIDTH = 'h4000;

	reg [31:0] data;
	reg [31:0] ram[0:RAM_WIDTH-1];

	assign data_bus = read_en ? data : 32'hzzzzzzzz;


	genvar i;
	generate 
		for (i = 0; i < RAM_WIDTH; i = i + 1) begin
			initial ram[i] = 32'hffffffff;
		end
	endgenerate









	always @(posedge clk) begin
		if (write_en) begin
			ram[address_bus] <= data_bus;
		end
		else data <= ram[address_bus];
	end
    
endmodule