data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v
None: at end of input
1: b'%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:3: Cannot find include file: bus.v\n`include "bus.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201275379/src/cpu/core/stage/id,data/full_repos/permissive/201275379/bus.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/id,data/full_repos/permissive/201275379/bus.v.v\n             data/full_repos/permissive/201275379/src/cpu/core/stage/id,data/full_repos/permissive/201275379/bus.v.sv\n             bus.v\n             bus.v.v\n             bus.v.sv\n             obj_dir/bus.v\n             obj_dir/bus.v.v\n             obj_dir/bus.v.sv\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:4: Cannot find include file: opcode.v\n`include "opcode.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:5: Cannot find include file: regimm.v\n`include "regimm.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:6: Cannot find include file: cp0.v\n`include "cp0.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:11: Define or directive not defined: \'`INST_OP_BUS\'\n  input   [`INST_OP_BUS]    op,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  input   [`INST_OP_BUS]    op,\n                       ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:12: Define or directive not defined: \'`REG_ADDR_BUS\'\n  input   [`REG_ADDR_BUS]   rs,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:13: Define or directive not defined: \'`REG_ADDR_BUS\'\n  input   [`REG_ADDR_BUS]   rt,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:14: Define or directive not defined: \'`REG_ADDR_BUS\'\n  input   [`REG_ADDR_BUS]   rd,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:15: Define or directive not defined: \'`HALF_DATA_BUS\'\n  input   [`HALF_DATA_BUS]  imm,\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:20: Define or directive not defined: \'`DATA_BUS\'\n  input   [`DATA_BUS]       reg_read_data_1,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:21: Define or directive not defined: \'`DATA_BUS\'\n  input   [`DATA_BUS]       reg_read_data_2,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:24: Define or directive not defined: \'`REG_ADDR_BUS\'\n  output  [`REG_ADDR_BUS]   reg_read_addr_1,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:25: Define or directive not defined: \'`REG_ADDR_BUS\'\n  output  [`REG_ADDR_BUS]   reg_read_addr_2,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:27: Define or directive not defined: \'`REG_ADDR_BUS\'\n  output  [`REG_ADDR_BUS]   reg_write_addr,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:31: Define or directive not defined: \'`DATA_BUS\'\n  output  [`DATA_BUS]       operand_data_1,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:32: Define or directive not defined: \'`DATA_BUS\'\n  output  [`DATA_BUS]       operand_data_2\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:36: Define or directive not defined: \'`REG_ADDR_BUS\'\n  reg[`REG_ADDR_BUS] reg_read_addr_1, reg_read_addr_2, reg_write_addr;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`REG_ADDR_BUS] reg_read_addr_1, reg_read_addr_2, reg_write_addr;\n                   ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:39: Define or directive not defined: \'`DATA_BUS\'\n  reg[`DATA_BUS] operand_data_1, operand_data_2;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg[`DATA_BUS] operand_data_1, operand_data_2;\n               ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:42: Define or directive not defined: \'`DATA_BUS\'\n  wire[`DATA_BUS] zero_extended_imm = {16\'b0, imm};\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`DATA_BUS] zero_extended_imm = {16\'b0, imm};\n                ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:43: Define or directive not defined: \'`DATA_BUS\'\n  wire[`DATA_BUS] zero_extended_imm_hi = {imm, 16\'b0};\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`DATA_BUS] zero_extended_imm_hi = {imm, 16\'b0};\n                ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:44: Define or directive not defined: \'`DATA_BUS\'\n  wire[`DATA_BUS] sign_extended_imm = {{16{imm[15]}}, imm};\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire[`DATA_BUS] sign_extended_imm = {{16{imm[15]}}, imm};\n                ^\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:57: Define or directive not defined: \'`OP_ADDI\'\n        `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,\n        ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:57: Define or directive not defined: \'`OP_ADDIU\'\n        `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:57: Define or directive not defined: \'`OP_SLTI\'\n        `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:57: Define or directive not defined: \'`OP_SLTIU\'\n        `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,\n                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:58: Define or directive not defined: \'`OP_ANDI\'\n        `OP_ANDI, `OP_ORI, `OP_XORI,\n        ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:58: Define or directive not defined: \'`OP_ORI\'\n        `OP_ANDI, `OP_ORI, `OP_XORI,\n                  ^~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:58: Define or directive not defined: \'`OP_XORI\'\n        `OP_ANDI, `OP_ORI, `OP_XORI,\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:60: Define or directive not defined: \'`OP_LB\'\n        `OP_LB, `OP_LH, `OP_LW, `OP_LBU, `OP_LHU: begin\n        ^~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:60: Define or directive not defined: \'`OP_LH\'\n        `OP_LB, `OP_LH, `OP_LW, `OP_LBU, `OP_LHU: begin\n                ^~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:60: Define or directive not defined: \'`OP_LW\'\n        `OP_LB, `OP_LH, `OP_LW, `OP_LBU, `OP_LHU: begin\n                        ^~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:60: Define or directive not defined: \'`OP_LBU\'\n        `OP_LB, `OP_LH, `OP_LW, `OP_LBU, `OP_LHU: begin\n                                ^~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:60: Define or directive not defined: \'`OP_LHU\'\n        `OP_LB, `OP_LH, `OP_LW, `OP_LBU, `OP_LHU: begin\n                                         ^~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:67: Define or directive not defined: \'`OP_BEQ\'\n        `OP_BEQ, `OP_BNE, `OP_BLEZ, `OP_BGTZ,\n        ^~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:67: Define or directive not defined: \'`OP_BNE\'\n        `OP_BEQ, `OP_BNE, `OP_BLEZ, `OP_BGTZ,\n                 ^~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:67: Define or directive not defined: \'`OP_BLEZ\'\n        `OP_BEQ, `OP_BNE, `OP_BLEZ, `OP_BGTZ,\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:67: Define or directive not defined: \'`OP_BGTZ\'\n        `OP_BEQ, `OP_BNE, `OP_BLEZ, `OP_BGTZ,\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:69: Define or directive not defined: \'`OP_SB\'\n        `OP_SB, `OP_SH, `OP_SW,\n        ^~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:69: Define or directive not defined: \'`OP_SH\'\n        `OP_SB, `OP_SH, `OP_SW,\n                ^~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:69: Define or directive not defined: \'`OP_SW\'\n        `OP_SB, `OP_SH, `OP_SW,\n                        ^~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:71: Define or directive not defined: \'`OP_SPECIAL\'\n        `OP_SPECIAL, `OP_SPECIAL2: begin\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:71: Define or directive not defined: \'`OP_SPECIAL2\'\n        `OP_SPECIAL, `OP_SPECIAL2: begin\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:78: Define or directive not defined: \'`OP_REGIMM\'\n        `OP_REGIMM: begin\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/201275379/src/cpu/core/stage/id/RegGen.v:80: Define or directive not defined: \'`REGIMM_BLTZ\'\n            `REGIMM_BLTZ, `REGIMM_BLTZAL,\n            ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module RegGen(
  input                     rst,

  input   [`INST_OP_BUS]    op,
  input   [`REG_ADDR_BUS]   rs,
  input   [`REG_ADDR_BUS]   rt,
  input   [`REG_ADDR_BUS]   rd,
  input   [`HALF_DATA_BUS]  imm,
  input                     is_cp0,

  input                     reg_read_is_ref_1,
  input                     reg_read_is_ref_2,
  input   [`DATA_BUS]       reg_read_data_1,
  input   [`DATA_BUS]       reg_read_data_2,
  output                    reg_read_en_1,
  output                    reg_read_en_2,
  output  [`REG_ADDR_BUS]   reg_read_addr_1,
  output  [`REG_ADDR_BUS]   reg_read_addr_2,
  output                    reg_write_en,
  output  [`REG_ADDR_BUS]   reg_write_addr,

  output                    operand_is_ref_1,
  output                    operand_is_ref_2,
  output  [`DATA_BUS]       operand_data_1,
  output  [`DATA_BUS]       operand_data_2
);

  reg reg_read_en_1, reg_read_en_2, reg_write_en;
  reg[`REG_ADDR_BUS] reg_read_addr_1, reg_read_addr_2, reg_write_addr;

  reg operand_is_ref_1, operand_is_ref_2;
  reg[`DATA_BUS] operand_data_1, operand_data_2;


  wire[`DATA_BUS] zero_extended_imm = {16'b0, imm};
  wire[`DATA_BUS] zero_extended_imm_hi = {imm, 16'b0};
  wire[`DATA_BUS] sign_extended_imm = {{16{imm[15]}}, imm};


  always @(*) begin
    if (!rst) begin
      reg_read_en_1 <= 0;
      reg_read_en_2 <= 0;
      reg_read_addr_1 <= 0;
      reg_read_addr_2 <= 0;
    end
    else begin
      case (op)

        `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,
        `OP_ANDI, `OP_ORI, `OP_XORI,

        `OP_LB, `OP_LH, `OP_LW, `OP_LBU, `OP_LHU: begin
          reg_read_en_1 <= 1;
          reg_read_en_2 <= 0;
          reg_read_addr_1 <= rs;
          reg_read_addr_2 <= 0;
        end

        `OP_BEQ, `OP_BNE, `OP_BLEZ, `OP_BGTZ,

        `OP_SB, `OP_SH, `OP_SW,

        `OP_SPECIAL, `OP_SPECIAL2: begin
          reg_read_en_1 <= 1;
          reg_read_en_2 <= 1;
          reg_read_addr_1 <= rs;
          reg_read_addr_2 <= rt;
        end

        `OP_REGIMM: begin
          case (rt)
            `REGIMM_BLTZ, `REGIMM_BLTZAL,
            `REGIMM_BGEZ, `REGIMM_BGEZAL: begin
              reg_read_en_1 <= 1;
              reg_read_en_2 <= 0;
              reg_read_addr_1 <= rs;
              reg_read_addr_2 <= 0;
            end
            default: begin
              reg_read_en_1 <= 0;
              reg_read_en_2 <= 0;
              reg_read_addr_1 <= 0;
              reg_read_addr_2 <= 0;
            end
          endcase
        end

        `OP_CP0: begin
          reg_read_en_1 <= 1;
          reg_read_en_2 <= 0;
          reg_read_addr_1 <= rt;
          reg_read_addr_2 <= 0;
        end
        default: begin
          reg_read_en_1 <= 0;
          reg_read_en_2 <= 0;
          reg_read_addr_1 <= 0;
          reg_read_addr_2 <= 0;
        end
      endcase
    end
  end


  always @(*) begin
    if (!rst) begin
      operand_is_ref_1 <= 0;
      operand_data_1 <= 0;
    end
    else begin
      case (op)

        `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,
        `OP_ANDI, `OP_ORI, `OP_XORI, `OP_LUI,

        `OP_LB, `OP_LH, `OP_LW, `OP_LBU, `OP_LHU, `OP_SB, `OP_SH, `OP_SW,
        `OP_SPECIAL, `OP_SPECIAL2, `OP_REGIMM, `OP_CP0: begin
          operand_is_ref_1 <= reg_read_is_ref_1;
          operand_data_1 <= reg_read_data_1;
        end
        default: begin
          operand_is_ref_1 <= 0;
          operand_data_1 <= 0;
        end
    endcase
    end
  end


  always @(*) begin
    if (!rst) begin
      operand_is_ref_2 <= 0;
      operand_data_2 <= 0;
    end
    else begin
      case (op)
        `OP_ORI, `OP_ANDI, `OP_XORI: begin
          operand_is_ref_2 <= 0;
          operand_data_2 <= zero_extended_imm;
        end 
        `OP_LUI: begin
          operand_is_ref_2 <= 0;
          operand_data_2 <= zero_extended_imm_hi;
        end
        `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU: begin
          operand_is_ref_2 <= 0;
          operand_data_2 <= sign_extended_imm;
        end

        `OP_SB, `OP_SH, `OP_SW,

        `OP_SPECIAL, `OP_SPECIAL2: begin
          operand_is_ref_2 <= reg_read_is_ref_2;
          operand_data_2 <= reg_read_data_2;
        end
        default: begin
          operand_is_ref_2 <= 0;
          operand_data_2 <= 0;
        end
      endcase
    end
  end


  always @(*) begin
    if (!rst) begin
      reg_write_en <= 0;
      reg_write_addr <= 0;
    end
    else begin
      case (op)

        `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,
        `OP_ANDI, `OP_ORI, `OP_XORI, `OP_LUI: begin
          reg_write_en <= 1;
          reg_write_addr <= rt;
        end
        `OP_SPECIAL, `OP_SPECIAL2: begin
          reg_write_en <= 1;
          reg_write_addr <= rd;
        end
        `OP_JAL: begin
          reg_write_en <= 1;
          reg_write_addr <= 31;
        end
        `OP_REGIMM: begin
          case (rt)
            `REGIMM_BGEZAL, `REGIMM_BLTZAL: begin
              reg_write_en <= 1;
              reg_write_addr <= 31;
            end
            default: begin
              reg_write_en <= 0;
              reg_write_addr <= 0;
            end
          endcase
        end
        `OP_LB, `OP_LBU, `OP_LH, `OP_LHU, `OP_LW: begin
          reg_write_en <= 1;
          reg_write_addr <= rt;
        end
        `OP_CP0: begin
          if (rs == `CP0_MFC0 && is_cp0) begin
            reg_write_en <= 1;
            reg_write_addr <= rt;
          end
          else begin
            reg_write_en <= 0;
            reg_write_addr <= 0;
          end
        end
        default: begin
          reg_write_en <= 0;
          reg_write_addr <= 0;
        end
      endcase
    end
  end

endmodule
module RegGen(
  input                     rst,

  input   [`INST_OP_BUS]    op,
  input   [`REG_ADDR_BUS]   rs,
  input   [`REG_ADDR_BUS]   rt,
  input   [`REG_ADDR_BUS]   rd,
  input   [`HALF_DATA_BUS]  imm,
  input                     is_cp0,

  input                     reg_read_is_ref_1,
  input                     reg_read_is_ref_2,
  input   [`DATA_BUS]       reg_read_data_1,
  input   [`DATA_BUS]       reg_read_data_2,
  output                    reg_read_en_1,
  output                    reg_read_en_2,
  output  [`REG_ADDR_BUS]   reg_read_addr_1,
  output  [`REG_ADDR_BUS]   reg_read_addr_2,
  output                    reg_write_en,
  output  [`REG_ADDR_BUS]   reg_write_addr,

  output                    operand_is_ref_1,
  output                    operand_is_ref_2,
  output  [`DATA_BUS]       operand_data_1,
  output  [`DATA_BUS]       operand_data_2
);


  reg reg_read_en_1, reg_read_en_2, reg_write_en;
  reg[`REG_ADDR_BUS] reg_read_addr_1, reg_read_addr_2, reg_write_addr;

  reg operand_is_ref_1, operand_is_ref_2;
  reg[`DATA_BUS] operand_data_1, operand_data_2;


  wire[`DATA_BUS] zero_extended_imm = {16'b0, imm};
  wire[`DATA_BUS] zero_extended_imm_hi = {imm, 16'b0};
  wire[`DATA_BUS] sign_extended_imm = {{16{imm[15]}}, imm};


  always @(*) begin
    if (!rst) begin
      reg_read_en_1 <= 0;
      reg_read_en_2 <= 0;
      reg_read_addr_1 <= 0;
      reg_read_addr_2 <= 0;
    end
    else begin
      case (op)

        `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,
        `OP_ANDI, `OP_ORI, `OP_XORI,

        `OP_LB, `OP_LH, `OP_LW, `OP_LBU, `OP_LHU: begin
          reg_read_en_1 <= 1;
          reg_read_en_2 <= 0;
          reg_read_addr_1 <= rs;
          reg_read_addr_2 <= 0;
        end

        `OP_BEQ, `OP_BNE, `OP_BLEZ, `OP_BGTZ,

        `OP_SB, `OP_SH, `OP_SW,

        `OP_SPECIAL, `OP_SPECIAL2: begin
          reg_read_en_1 <= 1;
          reg_read_en_2 <= 1;
          reg_read_addr_1 <= rs;
          reg_read_addr_2 <= rt;
        end

        `OP_REGIMM: begin
          case (rt)
            `REGIMM_BLTZ, `REGIMM_BLTZAL,
            `REGIMM_BGEZ, `REGIMM_BGEZAL: begin
              reg_read_en_1 <= 1;
              reg_read_en_2 <= 0;
              reg_read_addr_1 <= rs;
              reg_read_addr_2 <= 0;
            end
            default: begin
              reg_read_en_1 <= 0;
              reg_read_en_2 <= 0;
              reg_read_addr_1 <= 0;
              reg_read_addr_2 <= 0;
            end
          endcase
        end

        `OP_CP0: begin
          reg_read_en_1 <= 1;
          reg_read_en_2 <= 0;
          reg_read_addr_1 <= rt;
          reg_read_addr_2 <= 0;
        end
        default: begin
          reg_read_en_1 <= 0;
          reg_read_en_2 <= 0;
          reg_read_addr_1 <= 0;
          reg_read_addr_2 <= 0;
        end
      endcase
    end
  end


  always @(*) begin
    if (!rst) begin
      operand_is_ref_1 <= 0;
      operand_data_1 <= 0;
    end
    else begin
      case (op)

        `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,
        `OP_ANDI, `OP_ORI, `OP_XORI, `OP_LUI,

        `OP_LB, `OP_LH, `OP_LW, `OP_LBU, `OP_LHU, `OP_SB, `OP_SH, `OP_SW,
        `OP_SPECIAL, `OP_SPECIAL2, `OP_REGIMM, `OP_CP0: begin
          operand_is_ref_1 <= reg_read_is_ref_1;
          operand_data_1 <= reg_read_data_1;
        end
        default: begin
          operand_is_ref_1 <= 0;
          operand_data_1 <= 0;
        end
    endcase
    end
  end


  always @(*) begin
    if (!rst) begin
      operand_is_ref_2 <= 0;
      operand_data_2 <= 0;
    end
    else begin
      case (op)
        `OP_ORI, `OP_ANDI, `OP_XORI: begin
          operand_is_ref_2 <= 0;
          operand_data_2 <= zero_extended_imm;
        end 
        `OP_LUI: begin
          operand_is_ref_2 <= 0;
          operand_data_2 <= zero_extended_imm_hi;
        end
        `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU: begin
          operand_is_ref_2 <= 0;
          operand_data_2 <= sign_extended_imm;
        end

        `OP_SB, `OP_SH, `OP_SW,

        `OP_SPECIAL, `OP_SPECIAL2: begin
          operand_is_ref_2 <= reg_read_is_ref_2;
          operand_data_2 <= reg_read_data_2;
        end
        default: begin
          operand_is_ref_2 <= 0;
          operand_data_2 <= 0;
        end
      endcase
    end
  end


  always @(*) begin
    if (!rst) begin
      reg_write_en <= 0;
      reg_write_addr <= 0;
    end
    else begin
      case (op)

        `OP_ADDI, `OP_ADDIU, `OP_SLTI, `OP_SLTIU,
        `OP_ANDI, `OP_ORI, `OP_XORI, `OP_LUI: begin
          reg_write_en <= 1;
          reg_write_addr <= rt;
        end
        `OP_SPECIAL, `OP_SPECIAL2: begin
          reg_write_en <= 1;
          reg_write_addr <= rd;
        end
        `OP_JAL: begin
          reg_write_en <= 1;
          reg_write_addr <= 31;
        end
        `OP_REGIMM: begin
          case (rt)
            `REGIMM_BGEZAL, `REGIMM_BLTZAL: begin
              reg_write_en <= 1;
              reg_write_addr <= 31;
            end
            default: begin
              reg_write_en <= 0;
              reg_write_addr <= 0;
            end
          endcase
        end
        `OP_LB, `OP_LBU, `OP_LH, `OP_LHU, `OP_LW: begin
          reg_write_en <= 1;
          reg_write_addr <= rt;
        end
        `OP_CP0: begin
          if (rs == `CP0_MFC0 && is_cp0) begin
            reg_write_en <= 1;
            reg_write_addr <= rt;
          end
          else begin
            reg_write_en <= 0;
            reg_write_addr <= 0;
          end
        end
        default: begin
          reg_write_en <= 0;
          reg_write_addr <= 0;
        end
      endcase
    end
  end

endmodule