data/full_repos/permissive/199399537/sdram_wr_data.v
'utf-8' codec can't decode byte 0xca in position 100: invalid continuation byte
1: b'%Error: data/full_repos/permissive/199399537/sdram_wr_data.v:30: Cannot find include file: sdr_para.v\n`include "sdr_para.v"  //     SDRAM             \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/sdr_para.v\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/sdr_para.v.v\n             data/full_repos/permissive/199399537,data/full_repos/permissive/199399537/sdr_para.v.sv\n             sdr_para.v\n             sdr_para.v.v\n             sdr_para.v.sv\n             obj_dir/sdr_para.v\n             obj_dir/sdr_para.v.v\n             obj_dir/sdr_para.v.sv\n%Error: data/full_repos/permissive/199399537/sdram_wr_data.v:47: Define or directive not defined: \'`W_WRITE\'\n else if((work_state == `W_WRITE) | (work_state == `W_WD)) \n                        ^~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_wr_data.v:47: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n else if((work_state == `W_WRITE) | (work_state == `W_WD)) \n                                ^\n%Error: data/full_repos/permissive/199399537/sdram_wr_data.v:47: Define or directive not defined: \'`W_WD\'\n else if((work_state == `W_WRITE) | (work_state == `W_WD)) \n                                                   ^~~~~\n%Error: data/full_repos/permissive/199399537/sdram_wr_data.v:57: Define or directive not defined: \'`W_WRITE\'\n   else if((work_state == `W_WRITE) | (work_state == `W_WD)) \n                          ^~~~~~~~\n%Error: data/full_repos/permissive/199399537/sdram_wr_data.v:57: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   else if((work_state == `W_WRITE) | (work_state == `W_WD)) \n                                  ^\n%Error: data/full_repos/permissive/199399537/sdram_wr_data.v:57: Define or directive not defined: \'`W_WD\'\n   else if((work_state == `W_WRITE) | (work_state == `W_WD)) \n                                                     ^~~~~\n%Error: data/full_repos/permissive/199399537/sdram_wr_data.v:75: Define or directive not defined: \'`W_RD\'\n  else if((work_state == `W_RD) & (cnt_clk >= 9\'d0) & (cnt_clk < 9\'d9)) \n                         ^~~~~\n%Error: data/full_repos/permissive/199399537/sdram_wr_data.v:75: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  else if((work_state == `W_RD) & (cnt_clk >= 9\'d0) & (cnt_clk < 9\'d9)) \n                              ^\n%Error: Exiting due to 9 error(s)\n'
module sdram_wr_data(
					clk,rst_n,

					sdram_data,
					sys_data_in,sys_data_out,
					work_state,cnt_clk
				);

				
input clk;
input rst_n;



inout[15:0] 		sdram_data;


input	[15:0] 	sys_data_in;
output[15:0] 	sys_data_out;


input[3:0] work_state;
input[8:0] cnt_clk;

`include "sdr_para.v"







reg[15:0] 	sdr_din;
reg 				sdr_dlink;


always @ (posedge clk or negedge rst_n) 
	if(!rst_n) 
			sdr_din <= 16'd0;
	else if((work_state == `W_WRITE) | (work_state == `W_WD)) 
			sdr_din	<=	sys_data_in;



always @ (posedge clk or negedge rst_n) 
	if(!rst_n) 
			sdr_dlink <= 1'b0;
   else if((work_state == `W_WRITE) | (work_state == `W_WD)) 
			sdr_dlink <= 1'b1;
	else 
			sdr_dlink <= 1'b0;

assign sdram_data = sdr_dlink ? sdr_din:16'hzzzz;


reg[15:0] sdr_dout;


always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
			sdr_dout <= 16'd0;


		else if((work_state == `W_RD) & (cnt_clk >= 9'd0) & (cnt_clk < 9'd9)) 
			sdr_dout <= sdram_data;

assign sys_data_out = sdr_dout;



endmodule
module sdram_wr_data(
					clk,rst_n,

					sdram_data,
					sys_data_in,sys_data_out,
					work_state,cnt_clk
				);


				
input clk;
input rst_n;



inout[15:0] 		sdram_data;


input	[15:0] 	sys_data_in;
output[15:0] 	sys_data_out;


input[3:0] work_state;
input[8:0] cnt_clk;

`include "sdr_para.v"







reg[15:0] 	sdr_din;
reg 				sdr_dlink;


always @ (posedge clk or negedge rst_n) 
	if(!rst_n) 
			sdr_din <= 16'd0;
	else if((work_state == `W_WRITE) | (work_state == `W_WD)) 
			sdr_din	<=	sys_data_in;



always @ (posedge clk or negedge rst_n) 
	if(!rst_n) 
			sdr_dlink <= 1'b0;
   else if((work_state == `W_WRITE) | (work_state == `W_WD)) 
			sdr_dlink <= 1'b1;
	else 
			sdr_dlink <= 1'b0;

assign sdram_data = sdr_dlink ? sdr_din:16'hzzzz;


reg[15:0] sdr_dout;


always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
			sdr_dout <= 16'd0;


		else if((work_state == `W_RD) & (cnt_clk >= 9'd0) & (cnt_clk < 9'd9)) 
			sdr_dout <= sdram_data;

assign sys_data_out = sdr_dout;



endmodule