data/full_repos/permissive/139299103/OneCycleCPU.srcs/sources_1/new/selector5.v
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data/verilator_xmls/0dee1852-6178-4295-a8ed-06a827c14f33.xml
module selector5(
	 control,
	 data1,
	 data2,
	 result
);
    
	input  control;
	input wire [4:0] data1;   
	input wire [4:0] data2;
	output wire [4:0] result;
	assign result = (control == 0)? data1:data2;
	
endmodule
module selector5(
	 control,
	 data1,
	 data2,
	 result
);

    
	input  control;
	input wire [4:0] data1;   
	input wire [4:0] data2;
	output wire [4:0] result;
	assign result = (control == 0)? data1:data2;
	
endmodule