data/full_repos/permissive/161263445/Sword_FSM.v
data/verilator_xmls/0a3bf7d2-9a25-4caf-a053-e11823bda493.xml
module Sword_FSM (
	clk, in, state
);

input clk;
input [2:0] in;
output reg state;

initial
	state <= 0;

always @ (posedge clk) 
	if (in == 3'b011)
		state <= 1;
		
endmodule
module Sword_FSM (
	clk, in, state
);


input clk;
input [2:0] in;
output reg state;

initial
	state <= 0;

always @ (posedge clk) 
	if (in == 3'b011)
		state <= 1;
		
endmodule