data/full_repos/permissive/109846502/StateMachine.v
Syntax Error
1: b'%Error: data/full_repos/permissive/109846502/StateMachine.v:1: Cannot find include file: defines.vh\n`include "defines.vh"  \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.v\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/109846502/StateMachine.v:43: Define or directive not defined: \'`S_WPR\'\n  ST <= `S_WPR;\n        ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  ST <= `S_WPR;\n              ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:44: Define or directive not defined: \'`SL_A\'\n  ST_L <= `SL_A;\n          ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:44: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  ST_L <= `SL_A;\n               ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:49: Define or directive not defined: \'`S_GON\'\n  `S_GON: begin\n  ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:49: syntax error, unexpected \':\', expecting endcase\n  `S_GON: begin\n        ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:52: Define or directive not defined: \'`KEY_NONE\'\n    ST <= key == `KEY_NONE ? `S_WPR : `S_GON;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:52: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n    ST <= key == `KEY_NONE ? `S_WPR : `S_GON;\n                           ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:52: Define or directive not defined: \'`S_WPR\'\n    ST <= key == `KEY_NONE ? `S_WPR : `S_GON;\n                             ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:52: Define or directive not defined: \'`S_GON\'\n    ST <= key == `KEY_NONE ? `S_WPR : `S_GON;\n                                      ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:55: Define or directive not defined: \'`S_WPR\'\n  `S_WPR:\n  ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:56: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   begin\n   ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:57: Define or directive not defined: \'`KEY_A\'\n    if(key == `KEY_A)\n              ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:59: Define or directive not defined: \'`S_GON\'\n     ST <= `S_GON;\n           ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:60: Define or directive not defined: \'`SL_A\'\n     ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;\n                     ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:60: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n     ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;\n                           ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:60: Define or directive not defined: \'`SL_B\'\n     ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;\n                             ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:60: Define or directive not defined: \'`SL_A\'\n     ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;\n                                     ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:63: syntax error, unexpected else\n    else if(key >= `KEY_0 && key <= `KEY_9)\n    ^~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:63: Define or directive not defined: \'`KEY_0\'\n    else if(key >= `KEY_0 && key <= `KEY_9)\n                   ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:63: Define or directive not defined: \'`KEY_9\'\n    else if(key >= `KEY_0 && key <= `KEY_9)\n                                    ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:65: Define or directive not defined: \'`S_GON\'\n     ST <= `S_GON;\n           ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:68: syntax error, unexpected else\n    else if(key != `KEY_NONE)\n    ^~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:68: Define or directive not defined: \'`KEY_NONE\'\n    else if(key != `KEY_NONE)\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:70: Define or directive not defined: \'`S_OP\'\n    ST <= `S_OP;\n          ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:73: Define or directive not defined: \'`KEY_B\'\n      `KEY_B:\n      ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:73: syntax error, unexpected \':\', expecting endcase\n      `KEY_B:\n            ^\n%Error: data/full_repos/permissive/109846502/StateMachine.v:74: Define or directive not defined: \'`SL_ADD\'\n       ST_L <= `SL_ADD;\n               ^~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:75: Define or directive not defined: \'`KEY_C\'\n      `KEY_C:\n      ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:76: Define or directive not defined: \'`SL_SUB\'\n       ST_L <= `SL_SUB;\n               ^~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:77: Define or directive not defined: \'`KEY_D\'\n      `KEY_D:\n      ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:78: Define or directive not defined: \'`SL_AND\'\n       ST_L <= `SL_AND;\n               ^~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:79: Define or directive not defined: \'`KEY_E\'\n      `KEY_E:\n      ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:80: Define or directive not defined: \'`SL_OR\'\n       ST_L <= `SL_OR;\n               ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:81: Define or directive not defined: \'`KEY_F\'\n      `KEY_F:\n      ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:82: Define or directive not defined: \'`SL_XOR\'\n       ST_L <= `SL_XOR;\n               ^~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:86: Define or directive not defined: \'`S_OP\'\n  `S_OP: begin\n  ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:89: syntax error, unexpected <=, expecting IDENTIFIER\n   ST <= key == `KEY_NONE ? `S_OBL : `S_OP;\n      ^~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:89: Define or directive not defined: \'`KEY_NONE\'\n   ST <= key == `KEY_NONE ? `S_OBL : `S_OP;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:89: Define or directive not defined: \'`S_OBL\'\n   ST <= key == `KEY_NONE ? `S_OBL : `S_OP;\n                            ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:89: Define or directive not defined: \'`S_OP\'\n   ST <= key == `KEY_NONE ? `S_OBL : `S_OP;\n                                     ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:92: Define or directive not defined: \'`S_OBL\'\n  `S_OBL:\n  ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:93: Define or directive not defined: \'`KEY_NONE\'\n   if(key == `KEY_NONE && end_obl) begin\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:94: Define or directive not defined: \'`S_WPR\'\n    ST <= `S_WPR;\n          ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:95: Define or directive not defined: \'`SL_A\'\n    ST_L <= `SL_A;\n            ^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:98: Define or directive not defined: \'`S_OBL\'\n   ST <= `S_OBL;\n         ^~~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:105: syntax error, unexpected begin\nbegin\n^~~~~\n%Error: data/full_repos/permissive/109846502/StateMachine.v:108: syntax error, unexpected \'=\', expecting IDENTIFIER\n val = val >> 1;\n     ^\n%Error: Cannot continue\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module StateMachine
#(parameter waiter = 10000)
(
			input [4:0] key,
			input clk,
			input rst,
			input end_obl,
			output reg [1:0] ST,
			output reg [1:0] index,
			output reg [2:0] ST_L
    );
	 
localparam nbits = clog2b(waiter) + 1;
reg [nbits - 1:0] cnt;

assign comp = (cnt >= (waiter - 1));	 
 
always @(posedge clk, posedge rst)
begin
	if(rst) begin
		ST <= `S_WPR;
		ST_L <= `SL_A;
		index <= 2'd0;
	end
	else begin		
	case(ST)
		`S_GON: begin
			cnt <= cnt + 1;
			if(comp) begin
				ST <= key == `KEY_NONE ? `S_WPR : `S_GON;
				cnt  <= cnt <= {nbits{1'b0}};
			end end
		`S_WPR:
			begin
				if(key == `KEY_A)
				begin
					ST <= `S_GON;
					ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;
					index <= 2'd0;
				end
				else if(key >= `KEY_0 && key <= `KEY_9)
				begin
					ST <= `S_GON;
					index <= index + 1;
				end
				else if(key != `KEY_NONE)
				begin
				ST <= `S_OP;
				index <= 2'd0;
					case(key)
						`KEY_B:
							ST_L <= `SL_ADD;
						`KEY_C:
							ST_L <= `SL_SUB;
						`KEY_D:
							ST_L <= `SL_AND;
						`KEY_E:
							ST_L <= `SL_OR;
						`KEY_F:
							ST_L <= `SL_XOR;
					endcase
				end	
			end
		`S_OP: begin
			cnt <= cnt + 1;
			if(comp) begin
			ST <= key == `KEY_NONE ? `S_OBL : `S_OP;
			cnt <= cnt <= {nbits{1'b0}};
			end end
		`S_OBL:
			if(key == `KEY_NONE && end_obl) begin
				ST <= `S_WPR;
				ST_L <= `SL_A;
			end
			else
			ST <= `S_OBL;
	endcase
	end
end

function integer clog2b;
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
	val = val >> 1;
end
endfunction


endmodule
module StateMachine
#(parameter waiter = 10000)
(
			input [4:0] key,
			input clk,
			input rst,
			input end_obl,
			output reg [1:0] ST,
			output reg [1:0] index,
			output reg [2:0] ST_L
    );

	 
localparam nbits = clog2b(waiter) + 1;
reg [nbits - 1:0] cnt;

assign comp = (cnt >= (waiter - 1));	 
 
always @(posedge clk, posedge rst)
begin
	if(rst) begin
		ST <= `S_WPR;
		ST_L <= `SL_A;
		index <= 2'd0;
	end
	else begin		
	case(ST)
		`S_GON: begin
			cnt <= cnt + 1;
			if(comp) begin
				ST <= key == `KEY_NONE ? `S_WPR : `S_GON;
				cnt  <= cnt <= {nbits{1'b0}};
			end end
		`S_WPR:
			begin
				if(key == `KEY_A)
				begin
					ST <= `S_GON;
					ST_L <= ST_L == `SL_A ? `SL_B : `SL_A;
					index <= 2'd0;
				end
				else if(key >= `KEY_0 && key <= `KEY_9)
				begin
					ST <= `S_GON;
					index <= index + 1;
				end
				else if(key != `KEY_NONE)
				begin
				ST <= `S_OP;
				index <= 2'd0;
					case(key)
						`KEY_B:
							ST_L <= `SL_ADD;
						`KEY_C:
							ST_L <= `SL_SUB;
						`KEY_D:
							ST_L <= `SL_AND;
						`KEY_E:
							ST_L <= `SL_OR;
						`KEY_F:
							ST_L <= `SL_XOR;
					endcase
				end	
			end
		`S_OP: begin
			cnt <= cnt + 1;
			if(comp) begin
			ST <= key == `KEY_NONE ? `S_OBL : `S_OP;
			cnt <= cnt <= {nbits{1'b0}};
			end end
		`S_OBL:
			if(key == `KEY_NONE && end_obl) begin
				ST <= `S_WPR;
				ST_L <= `SL_A;
			end
			else
			ST <= `S_OBL;
	endcase
	end
end

function integer clog2b;
input reg[31:0] val;
begin
val = val - 1;
for(clog2b=0; val > 0; clog2b = clog2b + 1)
	val = val >> 1;
end
endfunction


endmodule