data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:158: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'block_ram_sp\'\nmodule  block_ram_sp(\n        ^~~~~~~~~~~~\n                                                                                             : ... Top module \'block_ram_dp\'\nmodule  block_ram_dp(\n        ^~~~~~~~~~~~\n                                                                                             : ... Top module \'dist_ram_dp\'\nmodule  dist_ram_dp(\n        ^~~~~~~~~~~\n                                                                                             : ... Top module \'per_dp2_0_r\'\nmodule per_dp2_0_r(\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/109231608/bitrev_files/per_n64_p2_w8_idx0.v:670: Output port connection \'counter_out\' expects 6 bits on the pin connection, but pin connection\'s VARREF \'counter_out_w\' generates 5 bits.\n                                                                                          : ... In instance per_dp2_0_r\n  counter_64 ctrl_unit(.in_start(in_start), .counter_out(counter_out_w), .clk(clk), .rst(rst));\n                                             ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n'
module  mem_addr_gen_dp2_mem0_per0(
counter_in,                              
clk,                             
rst,                             
addr_out                            
);                               
  input clk, rst;                           
  input [4:0] counter_in;      
  output [4:0] addr_out;      

  wire [3:0] word_counter_w [0:0];      
  wire [0:0] addr_a0;      
  assign addr_out[3:0] = {word_counter_w[0][0],word_counter_w[0][1],word_counter_w[0][2],word_counter_w[0][3]};    
  assign addr_out[4:4] = addr_a0[0:0];   
  
  assign word_counter_w[0] = counter_in[3:0];  
  assign addr_a0 = counter_in[4:4]; 
  
endmodule
module  mem_addr_gen_dp2_mem0_per0(
counter_in,                              
clk,                             
rst,                             
addr_out                            
);
                               
  input clk, rst;                           
  input [4:0] counter_in;      
  output [4:0] addr_out;      

  wire [3:0] word_counter_w [0:0];      
  wire [0:0] addr_a0;      
  assign addr_out[3:0] = {word_counter_w[0][0],word_counter_w[0][1],word_counter_w[0][2],word_counter_w[0][3]};    
  assign addr_out[4:4] = addr_a0[0:0];   
  
  assign word_counter_w[0] = counter_in[3:0];  
  assign addr_a0 = counter_in[4:4]; 
  
endmodule