data/full_repos/permissive/150266237/pratica_maq_venda/main.v
 line:54: before: "+"
1: b'%Warning-WIDTH: data/full_repos/permissive/150266237/pratica_maq_venda/main.v:47: Value too large for 2 bit number: 40\nassign vendeu = (estado >= 2\'d40);\n                           ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/150266237/pratica_maq_venda/main.v:13: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                   : ... Top module \'ff\'\nmodule ff ( input data, input c, input r, output q);\n       ^~\n                                                                                   : ... Top module \'moeda\'\nmodule moeda(input clk, input res, input next);\n       ^~~~~\n                                                                                   : ... Top module \'maq_pedido\'\nmodule maq_pedido(input clk,input res,input vendeu, input next, input [1:0] moeda ,output m5, output m10, output m20);\n       ^~~~~~~~~~\n                                                                                   : ... Top module \'maq_venda\'\nmodule maq_venda(input clk, input res, input m5, input m10, input m20, output next, output vendeu);\n       ^~~~~~~~~\n                                                                                   : ... Top module \'main\'\nmodule main;\n       ^~~~\n%Error: data/full_repos/permissive/150266237/pratica_maq_venda/main.v:3: Duplicate declaration of signal: \'q\'\n                                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nreg q;\n    ^\n        data/full_repos/permissive/150266237/pratica_maq_venda/main.v:2: ... Location of original declaration\nmodule ff ( input data, input c, input r, output q);\n                                                 ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module maq_venda(input clk, input res, input m5, input m10, input m20, output next, output vendeu);
reg [2:0] estado;
reg [6:0] saldo;

parameter init = 3'b000, pedido = 3'b001, soma= 3'b010, vende = 3'b011, proximo = 3'b100;

assign vendeu = (estado >= 2'd40);
assign next = ~vendeu;

always @(posedge clk or  negedge res) 
    begin
        if(res == 0) estado = init;
        else
            estado += m5*5 + m10*10 + m20*20;
    end
endmodule
module maq_venda(input clk, input res, input m5, input m10, input m20, output next, output vendeu);

reg [2:0] estado;
reg [6:0] saldo;

parameter init = 3'b000, pedido = 3'b001, soma= 3'b010, vende = 3'b011, proximo = 3'b100;

assign vendeu = (estado >= 2'd40);
assign next = ~vendeu;

always @(posedge clk or  negedge res) 
    begin
        if(res == 0) estado = init;
        else
            estado += m5*5 + m10*10 + m20*20;
    end
endmodule