data/full_repos/permissive/170267528/state1/tclProject/impSRAM/ip_SRAM.v
1: b"%Error: data/full_repos/permissive/170267528/state1/tclProject/impSRAM/ip_SRAM.v:56: Cannot find file containing module: 'yj_basic_reg_clk_p'\nyj_basic_reg_clk_p # (\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170267528/state1/tclProject/impSRAM,data/full_repos/permissive/170267528/yj_basic_reg_clk_p\n             data/full_repos/permissive/170267528/state1/tclProject/impSRAM,data/full_repos/permissive/170267528/yj_basic_reg_clk_p.v\n             data/full_repos/permissive/170267528/state1/tclProject/impSRAM,data/full_repos/permissive/170267528/yj_basic_reg_clk_p.sv\n             yj_basic_reg_clk_p\n             yj_basic_reg_clk_p.v\n             yj_basic_reg_clk_p.sv\n             obj_dir/yj_basic_reg_clk_p\n             obj_dir/yj_basic_reg_clk_p.v\n             obj_dir/yj_basic_reg_clk_p.sv\n%Error: data/full_repos/permissive/170267528/state1/tclProject/impSRAM/ip_SRAM.v:78: Cannot find file containing module: 'yj_basic_reg_clk_p'\nyj_basic_reg_clk_p # (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/170267528/state1/tclProject/impSRAM/ip_SRAM.v:98: Cannot find file containing module: 'yj_basic_reg_clk_p'\nyj_basic_reg_clk_p # (\n^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module perip_SRAM # (
		parameter ADDRW = 20,
		parameter DATAW = 16
	)
	( 
		input CLK,
		input RSTn,

		input mode_R1_W0,
		input [ADDRW-1:0] SRAM_ADDR_Stream,
		input [DATAW-1:0] SRAM_DATA_IN_Stream,
		output [DATAW-1:0] SRAM_DATA_OUT_Stream,



		output SRAM_OE_Pin,
		output SRAM_WR_Pin,
		output SRAM_CS_Pin,

		output [ADDRW-1:0] SRAM_ADDR_Pin,
		output [DATAW-1:0] SRAM_DATA_IN_Pin,
		input [DATAW-1:0] SRAM_DATA_OUT_Pin
);
	

wire [ADDRW-1:0] address_Din;
wire [ADDRW-1:0] address_Qout;


yj_basic_reg_clk_p # (
		.DW(ADDRW),
		.RSTVAL(1'b0)
	)
	address_reg
	(
		.CLK(CLK),
		.RSTn(RSTn),

		.din(address_Din),
		.qout(address_Qout)
);

assign address_Din = SRAM_ADDR_Stream;
assign SRAM_ADDR_Pin = address_Qout;




wire [DATAW-1:0] dataRead_Din;
wire [DATAW-1:0] dataRead_Qout;

yj_basic_reg_clk_p # (
		.DW(DATAW),
		.RSTVAL(1'b0)
	)
	dataRead_reg
	(
		.CLK(CLK),
		.RSTn(RSTn),

		.din(dataRead_Din),
		.qout(dataRead_Qout)
);

assign dataRead_Din = (mode_R1_W0 == 1'b1) ? SRAM_DATA_OUT_Pin : dataRead_Qout;
assign SRAM_DATA_OUT_Stream = dataRead_Qout;


wire [DATAW-1:0] dataWrite_Din;
wire [DATAW-1:0] dataWrite_Qout;

yj_basic_reg_clk_p # (
		.DW(DATAW),
		.RSTVAL(1'b0)
	)
	dataWrite_reg
	(
		.CLK(CLK),
		.RSTn(RSTn),

		.din(dataWrite_Din),
		.qout(dataWrite_Qout)
);

assign dataWrite_Din = (mode_R1_W0 == 1'b0) ? SRAM_DATA_IN_Stream : dataWrite_Qout;
assign SRAM_DATA_IN_Pin = dataWrite_Qout;

assign SRAM_WR_Pin = mode_R1_W0;
assign SRAM_OE_Pin = 1'b0;
assign SRAM_CS_Pin = 1'b0;













endmodule
module perip_SRAM # (
		parameter ADDRW = 20,
		parameter DATAW = 16
	)
	( 
		input CLK,
		input RSTn,

		input mode_R1_W0,
		input [ADDRW-1:0] SRAM_ADDR_Stream,
		input [DATAW-1:0] SRAM_DATA_IN_Stream,
		output [DATAW-1:0] SRAM_DATA_OUT_Stream,



		output SRAM_OE_Pin,
		output SRAM_WR_Pin,
		output SRAM_CS_Pin,

		output [ADDRW-1:0] SRAM_ADDR_Pin,
		output [DATAW-1:0] SRAM_DATA_IN_Pin,
		input [DATAW-1:0] SRAM_DATA_OUT_Pin
);

	

wire [ADDRW-1:0] address_Din;
wire [ADDRW-1:0] address_Qout;


yj_basic_reg_clk_p # (
		.DW(ADDRW),
		.RSTVAL(1'b0)
	)
	address_reg
	(
		.CLK(CLK),
		.RSTn(RSTn),

		.din(address_Din),
		.qout(address_Qout)
);

assign address_Din = SRAM_ADDR_Stream;
assign SRAM_ADDR_Pin = address_Qout;




wire [DATAW-1:0] dataRead_Din;
wire [DATAW-1:0] dataRead_Qout;

yj_basic_reg_clk_p # (
		.DW(DATAW),
		.RSTVAL(1'b0)
	)
	dataRead_reg
	(
		.CLK(CLK),
		.RSTn(RSTn),

		.din(dataRead_Din),
		.qout(dataRead_Qout)
);

assign dataRead_Din = (mode_R1_W0 == 1'b1) ? SRAM_DATA_OUT_Pin : dataRead_Qout;
assign SRAM_DATA_OUT_Stream = dataRead_Qout;


wire [DATAW-1:0] dataWrite_Din;
wire [DATAW-1:0] dataWrite_Qout;

yj_basic_reg_clk_p # (
		.DW(DATAW),
		.RSTVAL(1'b0)
	)
	dataWrite_reg
	(
		.CLK(CLK),
		.RSTn(RSTn),

		.din(dataWrite_Din),
		.qout(dataWrite_Qout)
);

assign dataWrite_Din = (mode_R1_W0 == 1'b0) ? SRAM_DATA_IN_Stream : dataWrite_Qout;
assign SRAM_DATA_IN_Pin = dataWrite_Qout;

assign SRAM_WR_Pin = mode_R1_W0;
assign SRAM_OE_Pin = 1'b0;
assign SRAM_CS_Pin = 1'b0;













endmodule