data/full_repos/permissive/132220215/shiftReg.v
 line:13: before: "clr"
1: b'%Error: data/full_repos/permissive/132220215/shiftReg.v:2: Cannot find include file: d_ff_asyn_clr.v\n`include "d_ff_asyn_clr.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/132220215,data/full_repos/permissive/132220215/d_ff_asyn_clr.v\n             data/full_repos/permissive/132220215,data/full_repos/permissive/132220215/d_ff_asyn_clr.v.v\n             data/full_repos/permissive/132220215,data/full_repos/permissive/132220215/d_ff_asyn_clr.v.sv\n             d_ff_asyn_clr.v\n             d_ff_asyn_clr.v.v\n             d_ff_asyn_clr.v.sv\n             obj_dir/d_ff_asyn_clr.v\n             obj_dir/d_ff_asyn_clr.v.v\n             obj_dir/d_ff_asyn_clr.v.sv\n%Error: Exiting due to 1 error(s)\n'
module shiftReg #(parameter N = 8) (
	input Din,
	input asyn_clr,
        input clk,
	output Dout);

 wire [N:0] w;
 assign w[0] = Din;
 assign Dout = w[N];

 genvar i;
 generate
	 for(i=0;i<N;i=i+1)
		 D_FF DF(.D(w[i]),.clk(clk),.Q(w[i+1]),.clr(asyn_clr));
 endgenerate
endmodule
module shiftReg #(parameter N = 8) (
	input Din,
	input asyn_clr,
        input clk,
	output Dout);


 wire [N:0] w;
 assign w[0] = Din;
 assign Dout = w[N];

 genvar i;
 generate
	 for(i=0;i<N;i=i+1)
		 D_FF DF(.D(w[i]),.clk(clk),.Q(w[i+1]),.clr(asyn_clr));
 endgenerate
endmodule