data/full_repos/permissive/125927162/digital_comparitor/comp_tb.v
 line:42: before: "$"
1: b'%Error: data/full_repos/permissive/125927162/digital_comparitor/comp_tb.v:33: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("comp.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/digital_comparitor/comp_tb.v:34: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, DUT);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/digital_comparitor/comp_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/digital_comparitor/comp_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/digital_comparitor/comp_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #1\n      ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module comp_tb ();
   localparam WIDTH = 4;
   reg [WIDTH-1:0] a;
   reg [WIDTH-1:0] b;
   wire 	   gt;
   wire 	   eq;
   wire 	   lt;

   comp #(.WIDTH(WIDTH)) DUT (
			      .a(a),
			      .b(b),
			      .gt(gt),
			      .eq(eq),
			      .lt(lt)
			      );

   initial begin
      $dumpfile("comp.vcd");
      $dumpvars(0, DUT);
      a = 4'b1010;
      b = 4'b1111;
      #1
	b = a;
      #1
	b = 4'b0000;
      #1
	$finish;
   end
   
endmodule
module comp_tb ();

   localparam WIDTH = 4;
   reg [WIDTH-1:0] a;
   reg [WIDTH-1:0] b;
   wire 	   gt;
   wire 	   eq;
   wire 	   lt;

   comp #(.WIDTH(WIDTH)) DUT (
			      .a(a),
			      .b(b),
			      .gt(gt),
			      .eq(eq),
			      .lt(lt)
			      );

   initial begin
      $dumpfile("comp.vcd");
      $dumpvars(0, DUT);
      a = 4'b1010;
      b = 4'b1111;
      #1
	b = a;
      #1
	b = 4'b0000;
      #1
	$finish;
   end
   
endmodule