data/full_repos/permissive/140572461/hdl/clk_div.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/140572461/hdl/clk_div.v:55: Unsupported: Ignoring delay on this delayed statement.\nalways #1\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/140572461/hdl/clk_div.v:24: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'counter\' generates 5 bits.\n                                                                     : ... In instance clk_div_tb.DUT\n        if (counter == COUNTER_MAX - 1) begin\n                    ^~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clk_div(
    input           clk,
    input           enable,
    output  reg     clk_out
);


parameter SYS_CLK = 50000000;
parameter CLK_OUT = 1000000;
parameter COUNTER_MAX = SYS_CLK / (2 * CLK_OUT);

reg [4:0] counter;

initial begin
    counter = 0;
    clk_out = 0;
end

always @(posedge clk) begin
    if (enable) begin
        if (counter == COUNTER_MAX - 1) begin
            counter <= 0;
            clk_out <= ~clk_out;
        end
        else begin
            counter <= counter + 1'd1;
        end
    end
end

endmodule
module clk_div(
    input           clk,
    input           enable,
    output  reg     clk_out
);



parameter SYS_CLK = 50000000;
parameter CLK_OUT = 1000000;
parameter COUNTER_MAX = SYS_CLK / (2 * CLK_OUT);

reg [4:0] counter;

initial begin
    counter = 0;
    clk_out = 0;
end

always @(posedge clk) begin
    if (enable) begin
        if (counter == COUNTER_MAX - 1) begin
            counter <= 0;
            clk_out <= ~clk_out;
        end
        else begin
            counter <= counter + 1'd1;
        end
    end
end

endmodule