data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/rmw_address_unit.v
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/rmw_address_unit.v:149: Cannot find file containing module: 'FD'\n   FD #(.INIT(INIT0)) FD0[MSB:0] (.D(d), .Q(r), .C(clk));\n   ^~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/FD\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/FD.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator,data/full_repos/permissive/20430511/FD.sv\n             FD\n             FD.v\n             FD.sv\n             obj_dir/FD\n             obj_dir/FD.v\n             obj_dir/FD.sv\n%Error: Internal Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/correlator/rmw_address_unit.v:149: ../V3Width.cpp:3377: Visit function missing? Widthed expectation for this node: PARSEREF 0x5603e8a11280 <e790> {c149}  MSB [TEXT]\n                                                                                                                            : ... In instance rmw_address_unit.DBL_FD0\n   FD #(.INIT(INIT0)) FD0[MSB:0] (.D(d), .Q(r), .C(clk));\n                          ^~~\n"
module rmw_address_unit
  #( parameter ABITS = 4,
     parameter ASB   = ABITS-1,
     parameter LOWER = 0,
     parameter UPPER = 11,
     parameter TICKS = 3,
     parameter DELAY = 3)
   (
    input          clk_i,
    input          rst_i,
    input          ce_i,

    output [ASB:0] rd_adr_o,
    output         rd_wrap_o,
    output [ASB:0] wr_adr_o,
    output         wr_wrap_o
    );

   wire [ASB:0]    next_rd_adr, next_adr;
   wire [ASB:0]    wr_adr_w;
   reg [ASB:0]     wr_adr_r = LOWER;

   assign rd_wrap_o = rd_adr_o == UPPER;
   assign wr_wrap_o = wr_adr_o == UPPER;

   assign next_adr[0] = ~rd_adr_o[0];
   assign next_adr[1] = rd_adr_o  [0] == 1'b1   ? ~rd_adr_o[1] : rd_adr_o[1];
   assign next_adr[2] = rd_adr_o[1:0] == 2'b11  ? ~rd_adr_o[2] : rd_adr_o[2];
   assign next_adr[3] = rd_adr_o[2:0] == 3'b111 ? ~rd_adr_o[3] : rd_adr_o[3];
   assign next_rd_adr = rd_wrap_o ? LOWER : next_adr;





   assign wr_adr_o = TICKS == 4 ? wr_adr_r : TICKS == 3 ? wr_adr_w : {ABITS{1'bx}};

   always @(posedge clk_i)
     if (rst_i)
       wr_adr_r <= #DELAY LOWER;
     else
       wr_adr_r <= #DELAY wr_adr_w;





`ifdef __icarus
   reg [ASB:0]         rd_adr_r = LOWER;

   assign rd_adr_o = rd_adr_r;

   always @(posedge clk_i)
     if (rst_i)     rd_adr_r <= #DELAY LOWER;
     else if (ce_i) rd_adr_r <= #DELAY next_rd_adr;
     else           rd_adr_r <= #DELAY rd_adr_o;
`else

   FDRE
     #(.INIT(LOWER))
   FD0 [ASB:0]
     ( .C(clk_i),
       .R(rst_i),
       .CE(ce_i),
       .D(next_rd_adr),
       .Q(rd_adr_o)
       );
`endif

   dbl_fd
     #(.WIDTH(ABITS),
       .INIT0(LOWER),
       .INIT1(LOWER),
       .DELAY(DELAY))
   DBL_FD0
     ( .clk(clk_i),
       .d(rd_adr_o),
       .q(wr_adr_w)
       );


endmodule
module rmw_address_unit
  #( parameter ABITS = 4,
     parameter ASB   = ABITS-1,
     parameter LOWER = 0,
     parameter UPPER = 11,
     parameter TICKS = 3,
     parameter DELAY = 3)
   (
    input          clk_i,
    input          rst_i,
    input          ce_i,

    output [ASB:0] rd_adr_o,
    output         rd_wrap_o,
    output [ASB:0] wr_adr_o,
    output         wr_wrap_o
    );


   wire [ASB:0]    next_rd_adr, next_adr;
   wire [ASB:0]    wr_adr_w;
   reg [ASB:0]     wr_adr_r = LOWER;

   assign rd_wrap_o = rd_adr_o == UPPER;
   assign wr_wrap_o = wr_adr_o == UPPER;

   assign next_adr[0] = ~rd_adr_o[0];
   assign next_adr[1] = rd_adr_o  [0] == 1'b1   ? ~rd_adr_o[1] : rd_adr_o[1];
   assign next_adr[2] = rd_adr_o[1:0] == 2'b11  ? ~rd_adr_o[2] : rd_adr_o[2];
   assign next_adr[3] = rd_adr_o[2:0] == 3'b111 ? ~rd_adr_o[3] : rd_adr_o[3];
   assign next_rd_adr = rd_wrap_o ? LOWER : next_adr;





   assign wr_adr_o = TICKS == 4 ? wr_adr_r : TICKS == 3 ? wr_adr_w : {ABITS{1'bx}};

   always @(posedge clk_i)
     if (rst_i)
       wr_adr_r <= #DELAY LOWER;
     else
       wr_adr_r <= #DELAY wr_adr_w;





`ifdef __icarus
   reg [ASB:0]         rd_adr_r = LOWER;

   assign rd_adr_o = rd_adr_r;

   always @(posedge clk_i)
     if (rst_i)     rd_adr_r <= #DELAY LOWER;
     else if (ce_i) rd_adr_r <= #DELAY next_rd_adr;
     else           rd_adr_r <= #DELAY rd_adr_o;
`else

   FDRE
     #(.INIT(LOWER))
   FD0 [ASB:0]
     ( .C(clk_i),
       .R(rst_i),
       .CE(ce_i),
       .D(next_rd_adr),
       .Q(rd_adr_o)
       );
`endif

   dbl_fd
     #(.WIDTH(ABITS),
       .INIT0(LOWER),
       .INIT1(LOWER),
       .DELAY(DELAY))
   DBL_FD0
     ( .clk(clk_i),
       .d(rd_adr_o),
       .q(wr_adr_w)
       );


endmodule