data/full_repos/permissive/169574047/ripple_carry_counter/ripple_carry_counter.srcs/sim_1/new/testbench.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/169574047/ripple_carry_counter/ripple_carry_counter.srcs/sim_1/new/testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;   \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/169574047/ripple_carry_counter/ripple_carry_counter.srcs/sim_1/new/testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #15 reset = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/ripple_carry_counter/ripple_carry_counter.srcs/sim_1/new/testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #180 reset = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/ripple_carry_counter/ripple_carry_counter.srcs/sim_1/new/testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/ripple_carry_counter/ripple_carry_counter.srcs/sim_1/new/testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #20 $finish;         \n        ^\n%Error: data/full_repos/permissive/169574047/ripple_carry_counter/ripple_carry_counter.srcs/sim_1/new/testbench.v:52: Unsupported or unknown PLI call: $monitor\n    $monitor($time, " Output q = %d", q);\n    ^~~~~~~~\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench(

    );
    
    reg clk;
    reg reset;
    wire[3:0] q;
    

    ripple_carry_counter r1(q,clk,reset);
    

    initial
        clk = 1'b0;
    always
        #5 clk = ~clk;
    

    initial
    begin
        reset = 1'b1;
        #15 reset = 1'b0;
        #180 reset = 1'b1;
        #10 reset = 1'b0;
        #20 $finish;
    end
    

    initial
    $monitor($time, " Output q = %d", q);
    
endmodule
module testbench(

    );

    
    reg clk;
    reg reset;
    wire[3:0] q;
    

    ripple_carry_counter r1(q,clk,reset);
    

    initial
        clk = 1'b0;
    always
        #5 clk = ~clk;
    

    initial
    begin
        reset = 1'b1;
        #15 reset = 1'b0;
        #180 reset = 1'b1;
        #10 reset = 1'b0;
        #20 $finish;
    end
    

    initial
    $monitor($time, " Output q = %d", q);
    
endmodule