data/full_repos/permissive/159479522/Show_now.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/159479522/Show_now.v:77: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'wash_time\' generates 5 bits.\n                                                                  : ... In instance Show_time\n            time_now=wash_time?wash_time:(rinse_time?rinse_time:dry_time);     \n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/159479522/Show_now.v:77: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'rinse_time\' generates 5 bits.\n                                                                  : ... In instance Show_time\n            time_now=wash_time?wash_time:(rinse_time?rinse_time:dry_time);     \n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/159479522/Show_now.v:77: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'wash_time\' generates 5 bits.\n                                                                  : ... In instance Show_time\n            time_now=wash_time?wash_time:(rinse_time?rinse_time:dry_time);     \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/159479522/Show_now.v:77: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'rinse_time\' generates 5 bits.\n                                                                  : ... In instance Show_time\n            time_now=wash_time?wash_time:(rinse_time?rinse_time:dry_time);     \n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/159479522/Show_now.v:77: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'dry_time\' generates 5 bits.\n                                                                  : ... In instance Show_time\n            time_now=wash_time?wash_time:(rinse_time?rinse_time:dry_time);     \n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/159479522/Show_now.v:88: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'wash_time\' generates 5 bits.\n                                                                  : ... In instance Show_time\n            time_now=wash_time;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/159479522/Show_now.v:96: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'rinse_time\' generates 5 bits.\n                                                                  : ... In instance Show_time\n              time_now=rinse_time;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/159479522/Show_now.v:104: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'dry_time\' generates 5 bits.\n                                                                   : ... In instance Show_time\n                time_now=dry_time;\n                        ^\n%Error: Exiting due to 8 warning(s)\n'
module Show_time(reset,clk,clk_sec,power_led,module_select,water_select,model_now,start_led,if_finish,water_level,time_now,time_all);
  input wire reset,clk,clk_sec,module_select,water_select,power_led,start_led,if_finish;
 input wire [2:0] model_now;
 input wire [3:0] water_level;
 output reg [5:0] time_now,time_all;
       reg [4:0] wash_time,rinse_time,dry_time;
       reg    time1_ind,time2_ind,time3_ind;
 initial begin
        time1_ind=0;
        time2_ind=0;
        time3_ind=0;
        time_now=11;
        time_all=29;
  end
  always @(module_select or water_select )
    begin
   case(model_now)
      3'b000:   begin
         wash_time=9+water_level;
         rinse_time=9+water_level*2;
         dry_time=3+water_level;
         end
       3'b001:  begin
        wash_time=9+water_level;
        rinse_time=0;
        dry_time=0;
        end
       3'b010:   begin
        wash_time=9+water_level;
        rinse_time=9+water_level*2;
        dry_time=0;
        end
       3'b011:   begin
        wash_time=0;
        rinse_time=9+water_level*2;
        dry_time=0;
        end
       3'b100:   begin
        wash_time=0;
        rinse_time=9+water_level*2;
        dry_time=3+water_level;
        end
       3'b101:  begin
        wash_time=0;
        rinse_time=0;
        dry_time=3+water_level;
        end
    endcase
 end
 
  always@(posedge clk_sec )
      begin    
          if(module_select || if_finish||water_select)
           begin
            if(power_led&&~start_led)   begin
            time_now=wash_time?wash_time:(rinse_time?rinse_time:dry_time);
            time1_ind=0;                                      
            time2_ind=0;            
            time3_ind=0; 
           end
          end
          else  begin
          if(power_led&&start_led)
          begin
            if(time1_ind==0)
            begin
            time_now=wash_time;
            time1_ind=1;
            end
            if(time_now>0)
            time_now=time_now-1;
            else  begin
              if(time2_ind==0)
              begin
              time_now=rinse_time;
              time2_ind=1;
              end
              if(time_now>0)
              time_now=time_now-1;
              else   begin
                if(time3_ind==0)
                begin
                time_now=dry_time;
                time3_ind=1;
                end
                if(time_now>0)
                time_now=time_now-1;
                else   time_now=11;
                end
               end
              end
             end
            end
            
      always@(posedge clk_sec )
      begin
        if(module_select||water_select||if_finish)
        begin
        if(power_led && ~start_led)
       time_all=wash_time+rinse_time+dry_time;
        end
      else  begin
      if(power_led  &&  start_led)
      begin
         if(time_all>0)
         time_all=time_all-1;
         else  begin
         time_all=29;
         end
       end
      end
     end       
endmodule
module Show_time(reset,clk,clk_sec,power_led,module_select,water_select,model_now,start_led,if_finish,water_level,time_now,time_all);

  input wire reset,clk,clk_sec,module_select,water_select,power_led,start_led,if_finish;
 input wire [2:0] model_now;
 input wire [3:0] water_level;
 output reg [5:0] time_now,time_all;
       reg [4:0] wash_time,rinse_time,dry_time;
       reg    time1_ind,time2_ind,time3_ind;
 initial begin
        time1_ind=0;
        time2_ind=0;
        time3_ind=0;
        time_now=11;
        time_all=29;
  end
  always @(module_select or water_select )
    begin
   case(model_now)
      3'b000:   begin
         wash_time=9+water_level;
         rinse_time=9+water_level*2;
         dry_time=3+water_level;
         end
       3'b001:  begin
        wash_time=9+water_level;
        rinse_time=0;
        dry_time=0;
        end
       3'b010:   begin
        wash_time=9+water_level;
        rinse_time=9+water_level*2;
        dry_time=0;
        end
       3'b011:   begin
        wash_time=0;
        rinse_time=9+water_level*2;
        dry_time=0;
        end
       3'b100:   begin
        wash_time=0;
        rinse_time=9+water_level*2;
        dry_time=3+water_level;
        end
       3'b101:  begin
        wash_time=0;
        rinse_time=0;
        dry_time=3+water_level;
        end
    endcase
 end
 
  always@(posedge clk_sec )
      begin    
          if(module_select || if_finish||water_select)
           begin
            if(power_led&&~start_led)   begin
            time_now=wash_time?wash_time:(rinse_time?rinse_time:dry_time);
            time1_ind=0;                                      
            time2_ind=0;            
            time3_ind=0; 
           end
          end
          else  begin
          if(power_led&&start_led)
          begin
            if(time1_ind==0)
            begin
            time_now=wash_time;
            time1_ind=1;
            end
            if(time_now>0)
            time_now=time_now-1;
            else  begin
              if(time2_ind==0)
              begin
              time_now=rinse_time;
              time2_ind=1;
              end
              if(time_now>0)
              time_now=time_now-1;
              else   begin
                if(time3_ind==0)
                begin
                time_now=dry_time;
                time3_ind=1;
                end
                if(time_now>0)
                time_now=time_now-1;
                else   time_now=11;
                end
               end
              end
             end
            end
            
      always@(posedge clk_sec )
      begin
        if(module_select||water_select||if_finish)
        begin
        if(power_led && ~start_led)
       time_all=wash_time+rinse_time+dry_time;
        end
      else  begin
      if(power_led  &&  start_led)
      begin
         if(time_all>0)
         time_all=time_all-1;
         else  begin
         time_all=29;
         end
       end
      end
     end       
endmodule