data/full_repos/permissive/111499712/fw/src/video_hack_1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/111499712/fw/src/video_hack_1.v:43: Operator ADD expects 11 bits on the LHS, but LHS\'s VARREF \'y\' generates 6 bits.\n                                                                             : ... In instance video_hack_1\nwire [6:0] t_sum = y + (t >> 4);\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/111499712/fw/src/video_hack_1.v:43: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s ADD generates 11 bits.\n                                                                             : ... In instance video_hack_1\nwire [6:0] t_sum = y + (t >> 4);\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/111499712/fw/src/video_hack_1.v:44: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s ADD generates 7 bits.\n                                                                             : ... In instance video_hack_1\nwire [5:0] a_sum = t_sum + x;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/111499712/fw/src/video_hack_1.v:45: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 7 bits.\n                                                                             : ... In instance video_hack_1\nwire [5:0] b_sum = t_sum - x;\n                 ^\n%Error: Exiting due to 4 warning(s)\n'
module video_hack_1(clk, reset, frame_begin, x, y, pixel_data);
parameter Width = 96;
parameter Height = 64;
input clk, reset, frame_begin;
input [$clog2(Width-1)-1:0] x;
input [$clog2(Height-1)-1:0] y;
output [15:0] pixel_data;

reg [10:0] t;

wire [6:0] t_sum = y + (t >> 4);
wire [5:0] a_sum = t_sum + x;
wire [5:0] b_sum = t_sum - x;

wire [4:0] r = a_sum[5] ? a_sum[4:0] : ~a_sum[4:0];
wire [5:0] g = t_sum[6] ? t_sum[5:0] : ~t_sum[5:0];
wire [4:0] b = b_sum[5] ? b_sum[4:0] : ~b_sum[4:0];

assign pixel_data = {r, g, b};

always @(negedge clk) begin
  if (reset)
    t <= 0;
  else if (frame_begin)
    t <= t + 1;
end

endmodule
module video_hack_1(clk, reset, frame_begin, x, y, pixel_data);

parameter Width = 96;
parameter Height = 64;
input clk, reset, frame_begin;
input [$clog2(Width-1)-1:0] x;
input [$clog2(Height-1)-1:0] y;
output [15:0] pixel_data;

reg [10:0] t;

wire [6:0] t_sum = y + (t >> 4);
wire [5:0] a_sum = t_sum + x;
wire [5:0] b_sum = t_sum - x;

wire [4:0] r = a_sum[5] ? a_sum[4:0] : ~a_sum[4:0];
wire [5:0] g = t_sum[6] ? t_sum[5:0] : ~t_sum[5:0];
wire [4:0] b = b_sum[5] ? b_sum[4:0] : ~b_sum[4:0];

assign pixel_data = {r, g, b};

always @(negedge clk) begin
  if (reset)
    t <= 0;
  else if (frame_begin)
    t <= t + 1;
end

endmodule