data/full_repos/permissive/143278/ivltests/shift4.v
data/verilator_xmls/75800b67-bbb7-4271-9ddb-7ff294052ef8.xml
module main;
   reg signed [7:0] a;
   reg [7:0] b;
   initial begin

      $display("simple arithmetic right shift");
      a = 8'b11001001;
      $display("before:  a = %b", a);
      a = a>>>1;
      $display("after:   a = %b", a);
      if (a !== 8'b11100100) begin
	 $display("FAILED");
	 $finish;
      end



      $display("concatenated arithmetic right shift");
      a = 8'b11001001;
      b = 0;
      $display("before:  a = %b", a);
      {a,b} = {a,b}>>>1;
      $display("after:   a = %b", a);
      if (a !== 8'b01100100) begin
	 $display("FAILED");
	 $finish;
      end




      $display("concatenated arithmetic right shift with $signed");
      a = 8'b11001001;
      b = 0;
      $display("before:  a = %b", a);
      {a,b} = $signed({a,b})>>>1;
      $display("after:   a = %b", a);
      if (a !== 8'b11100100) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module main;

   reg signed [7:0] a;
   reg [7:0] b;
   initial begin

      $display("simple arithmetic right shift");
      a = 8'b11001001;
      $display("before:  a = %b", a);
      a = a>>>1;
      $display("after:   a = %b", a);
      if (a !== 8'b11100100) begin
	 $display("FAILED");
	 $finish;
      end



      $display("concatenated arithmetic right shift");
      a = 8'b11001001;
      b = 0;
      $display("before:  a = %b", a);
      {a,b} = {a,b}>>>1;
      $display("after:   a = %b", a);
      if (a !== 8'b01100100) begin
	 $display("FAILED");
	 $finish;
      end




      $display("concatenated arithmetic right shift with $signed");
      a = 8'b11001001;
      b = 0;
      $display("before:  a = %b", a);
      {a,b} = $signed({a,b})>>>1;
      $display("after:   a = %b", a);
      if (a !== 8'b11100100) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
   end
endmodule