data/full_repos/permissive/149231262/Verilog_pingpong/robeimodel/verilog/count.v
data/verilator_xmls/c224acff-71c3-4a86-943c-e1f8607cef09.xml
module count(
	clk,
	countmax);


	input clk;
	output countmax;

	wire clk;
	wire countmax;


	reg [18:0] count;
	
	assign countmax = (count == 200000);
	assign count =0;
	
	always @(posedge clk)
	begin
	if(countmax)
	count <= 0;
	else
	count <= count + 1;
	end
endmodule
module count(
	clk,
	countmax);



	input clk;
	output countmax;

	wire clk;
	wire countmax;


	reg [18:0] count;
	
	assign countmax = (count == 200000);
	assign count =0;
	
	always @(posedge clk)
	begin
	if(countmax)
	count <= 0;
	else
	count <= count + 1;
	end
endmodule