data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/sixteen_bit_adder.v
1: b"%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/sixteen_bit_adder.v:13: Cannot find file containing module: 'four_bit_adder'\nfour_bit_adder add1(.x(x[3:0]), .y(y[3:0]), .c_in(c_in), .sum(sum[3:0]), .c_out(co_1));\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new,data/full_repos/permissive/133458123/four_bit_adder\n             data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new,data/full_repos/permissive/133458123/four_bit_adder.v\n             data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new,data/full_repos/permissive/133458123/four_bit_adder.sv\n             four_bit_adder\n             four_bit_adder.v\n             four_bit_adder.sv\n             obj_dir/four_bit_adder\n             obj_dir/four_bit_adder.v\n             obj_dir/four_bit_adder.sv\n%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/sixteen_bit_adder.v:14: Cannot find file containing module: 'four_bit_adder'\nfour_bit_adder add2(.x(x[7:4]), .y(y[7:4]), .c_in(co_1), .sum(sum[7:4]), .c_out(co_2));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/sixteen_bit_adder.v:15: Cannot find file containing module: 'four_bit_adder'\nfour_bit_adder add3(.x(x[11:8]), .y(y[11:8]), .c_in(co_2), .sum(sum[11:8]), .c_out(co_3));\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/133458123/mips_processor/mips_processor.srcs/sources_1/new/sixteen_bit_adder.v:16: Cannot find file containing module: 'four_bit_adder'\nfour_bit_adder add4(.x(x[15:12]), .y(y[15:12]), .c_in(co_3), .sum(sum[15:12]), .c_out(c_out));\n^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module sixteen_bit_adder(input wire [15:0] x, input wire [15:0] y, input wire c_in, output wire [15:0] sum, output wire c_out);







wire co_1, co_2, co_3;

four_bit_adder add1(.x(x[3:0]), .y(y[3:0]), .c_in(c_in), .sum(sum[3:0]), .c_out(co_1));
four_bit_adder add2(.x(x[7:4]), .y(y[7:4]), .c_in(co_1), .sum(sum[7:4]), .c_out(co_2));
four_bit_adder add3(.x(x[11:8]), .y(y[11:8]), .c_in(co_2), .sum(sum[11:8]), .c_out(co_3));
four_bit_adder add4(.x(x[15:12]), .y(y[15:12]), .c_in(co_3), .sum(sum[15:12]), .c_out(c_out));

endmodule
module sixteen_bit_adder(input wire [15:0] x, input wire [15:0] y, input wire c_in, output wire [15:0] sum, output wire c_out);








wire co_1, co_2, co_3;

four_bit_adder add1(.x(x[3:0]), .y(y[3:0]), .c_in(c_in), .sum(sum[3:0]), .c_out(co_1));
four_bit_adder add2(.x(x[7:4]), .y(y[7:4]), .c_in(co_1), .sum(sum[7:4]), .c_out(co_2));
four_bit_adder add3(.x(x[11:8]), .y(y[11:8]), .c_in(co_2), .sum(sum[11:8]), .c_out(co_3));
four_bit_adder add4(.x(x[15:12]), .y(y[15:12]), .c_in(co_3), .sum(sum[15:12]), .c_out(c_out));

endmodule