data/full_repos/permissive/102394571/Debouncer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/102394571/Debouncer.v:48: Operator ADD expects 20 bits on the RHS, but RHS\'s CONST \'16\'h1\' generates 16 bits.\n                                                                   : ... In instance Debouncer\n    signal_cnt <= signal_cnt + 16\'d1;   \n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Debouncer(
    input clk,
    input signal,


    output reg signal_state,
    output signal_up
);


reg signal_sync_0;  always @(posedge clk) signal_sync_0 <= signal;
reg signal_sync_1;  always @(posedge clk) signal_sync_1 <= signal_sync_0;


reg [19:0] signal_cnt;




wire signal_idle = (signal_state==signal_sync_1);
wire signal_cnt_max = &signal_cnt;

always @(posedge clk)
if(signal_idle)
    signal_cnt <= 0;
else
begin
    signal_cnt <= signal_cnt + 16'd1;
    if(signal_cnt_max) signal_state <= ~signal_state;
end

assign signal_up   = ~signal_idle & signal_cnt_max &  signal_state;
endmodule
module Debouncer(
    input clk,
    input signal,


    output reg signal_state,
    output signal_up
);



reg signal_sync_0;  always @(posedge clk) signal_sync_0 <= signal;
reg signal_sync_1;  always @(posedge clk) signal_sync_1 <= signal_sync_0;


reg [19:0] signal_cnt;




wire signal_idle = (signal_state==signal_sync_1);
wire signal_cnt_max = &signal_cnt;

always @(posedge clk)
if(signal_idle)
    signal_cnt <= 0;
else
begin
    signal_cnt <= signal_cnt + 16'd1;
    if(signal_cnt_max) signal_state <= ~signal_state;
end

assign signal_up   = ~signal_idle & signal_cnt_max &  signal_state;
endmodule