data/full_repos/permissive/120024308/src/cpu/cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/120024308/src/cpu/cpu.v:170: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'inmediate_rf\' generates 16 bits.\n                                                                      : ... In instance CPU\n   assign inmediate_addr_gl = (from_register_ex)? operand0_rf : inmediate_rf;\n                                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/120024308/src/cpu/cpu.v:172: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'inmediate_wb\' generates 16 bits.\n                                                                      : ... In instance CPU\n   assign hard_ip_gl = (branch_taken_wb)? inmediate_wb : inmediate_addr_gl;\n                                        ^\n%Error: data/full_repos/permissive/120024308/src/cpu/cpu.v:185: Cannot find file containing module: \'UPCOUNTER_POSEDGE\'\n   UPCOUNTER_POSEDGE #(32) IP\n   ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120024308/src/cpu,data/full_repos/permissive/120024308/UPCOUNTER_POSEDGE\n             data/full_repos/permissive/120024308/src/cpu,data/full_repos/permissive/120024308/UPCOUNTER_POSEDGE.v\n             data/full_repos/permissive/120024308/src/cpu,data/full_repos/permissive/120024308/UPCOUNTER_POSEDGE.sv\n             UPCOUNTER_POSEDGE\n             UPCOUNTER_POSEDGE.v\n             UPCOUNTER_POSEDGE.sv\n             obj_dir/UPCOUNTER_POSEDGE\n             obj_dir/UPCOUNTER_POSEDGE.v\n             obj_dir/UPCOUNTER_POSEDGE.sv\n%Error: data/full_repos/permissive/120024308/src/cpu/cpu.v:195: Cannot find file containing module: \'FFD_POSEDGE_SYNCHRONOUS_RESET\'\n   FFD_POSEDGE_SYNCHRONOUS_RESET #(32) FF_ip\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/cpu.v:205: Cannot find file containing module: \'FFD_POSEDGE_SYNCHRONOUS_RESET\'\n   FFD_POSEDGE_SYNCHRONOUS_RESET #(32) FF_return\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/cpu.v:216: Cannot find file containing module: \'ROM\'\n   ROM InstructionRom\n   ^~~\n%Error: data/full_repos/permissive/120024308/src/cpu/cpu.v:223: Cannot find file containing module: \'Decoder\'\n   Decoder Ins_decod\n   ^~~~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/cpu.v:239: Cannot find file containing module: \'Bubbler\'\n      Bubbler Bubbler\n      ^~~~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/cpu.v:310: Cannot find file containing module: \'Register_file\'\n   Register_file Register_file\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/cpu.v:326: Cannot find file containing module: \'FFD_POSEDGE_SYNCHRONOUS_RESET\'\n   FFD_POSEDGE_SYNCHRONOUS_RESET #(6+5+32+32+32+16+1+1+1) FF_rf\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/cpu.v:338: Cannot find file containing module: \'Alu\'\n   Alu Alu\n   ^~~\n%Error: data/full_repos/permissive/120024308/src/cpu/cpu.v:350: Cannot find file containing module: \'Output\'\n   Output Output\n   ^~~~~~\n%Error: data/full_repos/permissive/120024308/src/cpu/cpu.v:362: Cannot find file containing module: \'FFD_POSEDGE_SYNCHRONOUS_RESET\'\n   FFD_POSEDGE_SYNCHRONOUS_RESET #(6+5+32+32+32+32+16+1+1+1+1) FF_ex\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/120024308/src/cpu/cpu.v:376: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'inmediate_me\' generates 16 bits.\n                                                                      : ... In instance CPU\n   assign ram_address      = operand1_ex+inmediate_me;  \n                                        ^\n%Error: data/full_repos/permissive/120024308/src/cpu/cpu.v:382: Cannot find file containing module: \'FFD_POSEDGE_SYNCHRONOUS_RESET\'\n   FFD_POSEDGE_SYNCHRONOUS_RESET #(5+32+32+16+1+1+1+32) FF_me\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s), 3 warning(s)\n'
module CPU(
	   input wire 	      clk,
	   input wire 	      reset,
	   output wire [7:0]  data,





	   output wire 	      ram_enable_read,
	   output wire 	      ram_enable_write,
	   output wire [31:0] ram_data_write,
	   input wire [31:0]  ram_data_read,
	   output wire [31:0] ram_address
	    );



   wire                  	      branch_taken_gl;
   wire [`WORD_SIZE-1:0] 	      inmediate_addr_gl;
   wire 			      return_branch_gl;
   wire [`WORD_SIZE-1:0] 	      return_addr_gl;
   wire [`WORD_SIZE-1:0] 	      hard_ip_gl;
   wire [`WORD_SIZE-1:0] 	      bub_hard_ip_gl;
   wire [`WORD_SIZE-1:0] 	      next_ip_gl;
   wire [`WORD_SIZE-1:0] 	      current_ip_gl;
   wire [`WORD_SIZE-1:0] 	      bub_current_ip_gl;
   wire 			      write_enable_gl;
   wire [`REGISTER_SIZE-1:0] 	      destination_gl;
   wire [`WORD_SIZE-1:0] 	      register_data_in_gl;
   wire 			      stall_gl;
   
   
   


   wire [`WORD_SIZE-1:0] 	      instruction_fd;
   wire 			      branch_taken_fd;
   wire 			      from_register_fd;
   wire 			      sto_ip_fd;
   wire [`OP_CODE_SIZE-1:0] 	      operation_fd;
   wire [`INMEDIATE_SIZE-1:0] 	      inmediate_fd;
   wire [`REGISTER_SIZE-1:0] 	      destination_fd;
   wire [`REGISTER_SIZE-1:0] 	      read0_fd;
   wire [`REGISTER_SIZE-1:0] 	      read1_fd;
   wire [`REGISTER_SIZE-1:0] 	      read2_fd;
   wire 			      ram_enable_write_fd;
   wire 			      ram_enable_read_fd;

   wire 			      bub_branch_taken_fd;
   wire 			      bub_from_register_fd;
   wire 			      bub_sto_ip_fd;
   wire [`OP_CODE_SIZE-1:0] 	      bub_operation_fd;
   wire [`INMEDIATE_SIZE-1:0] 	      bub_inmediate_fd;
   wire [`REGISTER_SIZE-1:0] 	      bub_destination_fd;
   wire [`REGISTER_SIZE-1:0] 	      bub_read0_fd;
   wire [`REGISTER_SIZE-1:0] 	      bub_read1_fd;
   wire [`REGISTER_SIZE-1:0] 	      bub_read2_fd;
   wire 			      bub_ram_enable_write_fd;
   wire 			      bub_ram_enable_read_fd;

   


   wire 			      branch_taken_rf;
   wire 			      from_register_rf;
   wire 			      sto_ip_rf;
   wire [`REGISTER_SIZE-1:0] 	      read0_rf;
   wire [`REGISTER_SIZE-1:0] 	      read1_rf;
   wire [`REGISTER_SIZE-1:0] 	      read2_rf;
   wire [`WORD_SIZE-1:0] 	      operand0_rf;
   wire [`WORD_SIZE-1:0] 	      operand1_rf;
   wire [`WORD_SIZE-1:0] 	      operand2_rf;
   wire [`OP_CODE_SIZE-1:0] 	      operation_rf;
   wire [`REGISTER_SIZE-1:0] 	      destination_rf;
   wire [`INMEDIATE_SIZE-1:0] 	      inmediate_rf;
   wire 			      ram_enable_write_rf;
   wire 			      ram_enable_read_rf;


   wire [`OP_CODE_SIZE-1:0] 	      operation_ex;
   wire [`WORD_SIZE-1:0] 	      operand0_ex;
   wire [`WORD_SIZE-1:0] 	      operand1_ex;
   wire [`WORD_SIZE-1:0] 	      operand2_ex;
   wire [`WORD_SIZE-1:0] 	      result_ex;
   wire 			      write_enable_ex;
   wire 			      branch_taken_ex;
   wire [`REGISTER_SIZE-1:0] 	      destination_ex;
   wire [`INMEDIATE_SIZE-1:0] 	      inmediate_ex;
   wire 			      ram_enable_write_ex;
   wire 			      ram_enable_read_ex;
   wire 			      from_register_ex;
			      


   wire [`OP_CODE_SIZE-1:0] 	      operation_me;
   wire [`WORD_SIZE-1:0] 	      ram_data_write_me;
   wire [`WORD_SIZE-1:0] 	      ram_data_read_me;
   wire [`REGISTER_SIZE-1:0] 	      destination_me;
   wire [`WORD_SIZE-1:0] 	      result_me;
   wire [`WORD_SIZE-1:0] 	      operand0_me;
   wire [`WORD_SIZE-1:0] 	      operand1_me;
   wire [`WORD_SIZE-1:0] 	      operand2_me;
   wire [`INMEDIATE_SIZE-1:0] 	      inmediate_me;
   wire 			      write_enable_me;
   wire 			      branch_taken_me;
   wire 			      ram_enable_write_me;
   wire 			      ram_enable_read_me;


   wire [`REGISTER_SIZE-1:0] 	      destination_wb;
   wire [`WORD_SIZE-1:0] 	      result_wb;
   wire [`WORD_SIZE-1:0] 	      operand2_wb;
   wire [`INMEDIATE_SIZE-1:0] 	      inmediate_wb;
   wire 			      write_enable_wb;
   wire 			      branch_taken_wb;
   wire [`WORD_SIZE-1:0] 	      mem_wb;
   wire [`WORD_SIZE-1:0] 	      data_wb;
   wire 			      ram_enable_read_wb;
   



   assign branch_taken_gl = ((branch_taken_rf || branch_taken_wb) && 
			     !(from_register_rf)) || from_register_ex;
   

   assign inmediate_addr_gl = (from_register_ex)? operand0_rf : inmediate_rf;

   assign hard_ip_gl = (branch_taken_wb)? inmediate_wb : inmediate_addr_gl;

   assign bub_hard_ip_gl = (stall_gl && !branch_taken_gl)? bub_current_ip_gl : hard_ip_gl;
   


   assign write_enable_gl = sto_ip_rf | write_enable_wb | ram_enable_read_wb;
   assign destination_gl = (sto_ip_rf)? `RA : destination_wb;
   assign data_wb = (ram_enable_read_wb)? ram_data_read: result_wb;   
   assign register_data_in_gl = (sto_ip_rf)? return_addr_gl: data_wb;
   


   UPCOUNTER_POSEDGE #(32) IP
     (
      .Clock(clk),
      .Reset(reset | branch_taken_gl | stall_gl),
      .Initial(bub_hard_ip_gl),
      .Enable(1'b1 && !stall_gl || branch_taken_gl),
      .Q(next_ip_gl)

      );

   FFD_POSEDGE_SYNCHRONOUS_RESET #(32) FF_ip
     (
      .Clock(clk),
      .Reset(reset),
      .Enable(1'b1),
      .D(next_ip_gl),
      .Q(current_ip_gl)
      );


   FFD_POSEDGE_SYNCHRONOUS_RESET #(32) FF_return
     (
      .Clock(clk),
      .Reset(reset),
      .Enable(sto_ip_fd),
      .D(bub_current_ip_gl+1),
      .Q(return_addr_gl)
      );



   ROM InstructionRom
     (
      .iAddress (bub_current_ip_gl),
      .oInstruction(instruction_fd)
      );


   Decoder Ins_decod
     (
      .instruction(instruction_fd),
      .branch_taken(branch_taken_fd),
      .link(sto_ip_fd),
      .from_register(from_register_fd),
      .operation(operation_fd),
      .inmediate(inmediate_fd),
      .destination(destination_fd),
      .read0(read0_fd),
      .read1(read1_fd),
      .read2(read2_fd),
      .ram_enable_write(ram_enable_write_fd),
      .ram_enable_read(ram_enable_read_fd)
      );

      Bubbler Bubbler
     (
      .Clock(clk),
      .Reset(reset | branch_taken_gl ),
      .current_address(next_ip_gl),
      .global_branch_taken(branch_taken_gl),
      .operation(operation_fd),
      .inmediate(inmediate_fd),
      .destination(destination_fd),
      .link(sto_ip_fd),
      .read0(read0_fd),
      .read1(read1_fd),
      .read2(read2_fd),
      .branch_taken(branch_taken_fd),
      .from_register(from_register_fd),
      .ram_enable_write(ram_enable_write_fd),
      .ram_enable_read(ram_enable_read_fd),

      .past_operation0(operation_rf),
      .past_operation1(operation_ex),
      .past_operation2(operation_me),

      .past_destination0(destination_rf),
      .past_destination1(destination_ex),
      .past_destination2(destination_me),

      .stall(stall_gl),
      .overwrite_address(bub_current_ip_gl),

      .out_operation(operation_rf),
      .out_inmediate(inmediate_rf),
      .out_destination(destination_rf),
      .out_read0(read0_rf),
      .out_read1(read1_rf),
      .out_read2(read2_rf),
      .out_branch_taken(branch_taken_rf),
      .out_link(sto_ip_rf),
      .out_from_register(from_register_rf),
      .out_ram_enable_write(ram_enable_write_rf),
      .out_ram_enable_read(ram_enable_read_rf)
      );

   






   Register_file Register_file
     (
      .Clock(clk),
      .iWriteEnable(write_enable_gl),
      .iReadAddress0(read0_rf),
      .iReadAddress1(read1_rf),
      .iReadAddress2(read2_rf),
      .iWriteAddress(destination_gl),
      .iDataIn(register_data_in_gl),
      .oDataOut0(operand0_rf),
      .oDataOut1(operand1_rf),
      .oDataOut2(operand2_rf)
      );
   


   FFD_POSEDGE_SYNCHRONOUS_RESET #(6+5+32+32+32+16+1+1+1) FF_rf
     (
      .Clock(clk),
      .Reset(reset | branch_taken_gl),
      .Enable(1'b1),
      .D({operation_rf, destination_rf, operand2_rf, operand1_rf, operand0_rf, inmediate_rf, ram_enable_write_rf, ram_enable_read_rf, from_register_rf}),
      .Q({operation_ex, destination_ex, operand2_ex, operand1_ex, operand0_ex, inmediate_ex, ram_enable_write_ex, ram_enable_read_ex, from_register_ex})
      );




   Alu Alu
     (
      .operation(operation_ex),
      .operand0(operand0_rf),
      .operand1(operand1_rf),
      .operand2(operand2_rf),
      .inmediate(inmediate_ex),
      .result(result_ex),
      .write_enable(write_enable_ex),
      .branch_taken(branch_taken_ex)
      );

   Output Output
		(
		 .clk(clk),
		 .reset(reset),
		 .operation(operation_ex),
		 .out(data),
		 .in(result_ex)
		 );
   



   FFD_POSEDGE_SYNCHRONOUS_RESET #(6+5+32+32+32+32+16+1+1+1+1) FF_ex
     (
      .Clock(clk),

      .Reset(reset),
      .Enable(1'b1),
      .D({operation_ex, destination_ex, result_ex, operand2_ex, operand1_ex, operand0_ex, inmediate_ex, write_enable_ex, branch_taken_ex, ram_enable_write_ex, ram_enable_read_ex}),
      .Q({operation_me, destination_me, result_me, operand2_me, operand1_me, operand0_me, inmediate_me, write_enable_me, branch_taken_me, ram_enable_write_me, ram_enable_read_me})
      );



   assign ram_enable_write = ram_enable_write_me;
   assign ram_data_write   = operand2_ex;
   assign ram_address      = operand1_ex+inmediate_me;
   assign ram_enable_read  = ram_enable_read_ex;

   


   FFD_POSEDGE_SYNCHRONOUS_RESET #(5+32+32+16+1+1+1+32) FF_me
     (
      .Clock(clk),

      .Reset(reset),
      .Enable(1'b1),

      .D({destination_me, operand2_me, result_me, inmediate_me, write_enable_me, ram_enable_read_me, branch_taken_me, ram_data_read}),
      .Q({destination_wb, operand2_wb, result_wb, inmediate_wb, write_enable_wb, ram_enable_read_wb, branch_taken_wb, mem_wb})
      );


endmodule
module CPU(
	   input wire 	      clk,
	   input wire 	      reset,
	   output wire [7:0]  data,





	   output wire 	      ram_enable_read,
	   output wire 	      ram_enable_write,
	   output wire [31:0] ram_data_write,
	   input wire [31:0]  ram_data_read,
	   output wire [31:0] ram_address
	    );




   wire                  	      branch_taken_gl;
   wire [`WORD_SIZE-1:0] 	      inmediate_addr_gl;
   wire 			      return_branch_gl;
   wire [`WORD_SIZE-1:0] 	      return_addr_gl;
   wire [`WORD_SIZE-1:0] 	      hard_ip_gl;
   wire [`WORD_SIZE-1:0] 	      bub_hard_ip_gl;
   wire [`WORD_SIZE-1:0] 	      next_ip_gl;
   wire [`WORD_SIZE-1:0] 	      current_ip_gl;
   wire [`WORD_SIZE-1:0] 	      bub_current_ip_gl;
   wire 			      write_enable_gl;
   wire [`REGISTER_SIZE-1:0] 	      destination_gl;
   wire [`WORD_SIZE-1:0] 	      register_data_in_gl;
   wire 			      stall_gl;
   
   
   


   wire [`WORD_SIZE-1:0] 	      instruction_fd;
   wire 			      branch_taken_fd;
   wire 			      from_register_fd;
   wire 			      sto_ip_fd;
   wire [`OP_CODE_SIZE-1:0] 	      operation_fd;
   wire [`INMEDIATE_SIZE-1:0] 	      inmediate_fd;
   wire [`REGISTER_SIZE-1:0] 	      destination_fd;
   wire [`REGISTER_SIZE-1:0] 	      read0_fd;
   wire [`REGISTER_SIZE-1:0] 	      read1_fd;
   wire [`REGISTER_SIZE-1:0] 	      read2_fd;
   wire 			      ram_enable_write_fd;
   wire 			      ram_enable_read_fd;

   wire 			      bub_branch_taken_fd;
   wire 			      bub_from_register_fd;
   wire 			      bub_sto_ip_fd;
   wire [`OP_CODE_SIZE-1:0] 	      bub_operation_fd;
   wire [`INMEDIATE_SIZE-1:0] 	      bub_inmediate_fd;
   wire [`REGISTER_SIZE-1:0] 	      bub_destination_fd;
   wire [`REGISTER_SIZE-1:0] 	      bub_read0_fd;
   wire [`REGISTER_SIZE-1:0] 	      bub_read1_fd;
   wire [`REGISTER_SIZE-1:0] 	      bub_read2_fd;
   wire 			      bub_ram_enable_write_fd;
   wire 			      bub_ram_enable_read_fd;

   


   wire 			      branch_taken_rf;
   wire 			      from_register_rf;
   wire 			      sto_ip_rf;
   wire [`REGISTER_SIZE-1:0] 	      read0_rf;
   wire [`REGISTER_SIZE-1:0] 	      read1_rf;
   wire [`REGISTER_SIZE-1:0] 	      read2_rf;
   wire [`WORD_SIZE-1:0] 	      operand0_rf;
   wire [`WORD_SIZE-1:0] 	      operand1_rf;
   wire [`WORD_SIZE-1:0] 	      operand2_rf;
   wire [`OP_CODE_SIZE-1:0] 	      operation_rf;
   wire [`REGISTER_SIZE-1:0] 	      destination_rf;
   wire [`INMEDIATE_SIZE-1:0] 	      inmediate_rf;
   wire 			      ram_enable_write_rf;
   wire 			      ram_enable_read_rf;


   wire [`OP_CODE_SIZE-1:0] 	      operation_ex;
   wire [`WORD_SIZE-1:0] 	      operand0_ex;
   wire [`WORD_SIZE-1:0] 	      operand1_ex;
   wire [`WORD_SIZE-1:0] 	      operand2_ex;
   wire [`WORD_SIZE-1:0] 	      result_ex;
   wire 			      write_enable_ex;
   wire 			      branch_taken_ex;
   wire [`REGISTER_SIZE-1:0] 	      destination_ex;
   wire [`INMEDIATE_SIZE-1:0] 	      inmediate_ex;
   wire 			      ram_enable_write_ex;
   wire 			      ram_enable_read_ex;
   wire 			      from_register_ex;
			      


   wire [`OP_CODE_SIZE-1:0] 	      operation_me;
   wire [`WORD_SIZE-1:0] 	      ram_data_write_me;
   wire [`WORD_SIZE-1:0] 	      ram_data_read_me;
   wire [`REGISTER_SIZE-1:0] 	      destination_me;
   wire [`WORD_SIZE-1:0] 	      result_me;
   wire [`WORD_SIZE-1:0] 	      operand0_me;
   wire [`WORD_SIZE-1:0] 	      operand1_me;
   wire [`WORD_SIZE-1:0] 	      operand2_me;
   wire [`INMEDIATE_SIZE-1:0] 	      inmediate_me;
   wire 			      write_enable_me;
   wire 			      branch_taken_me;
   wire 			      ram_enable_write_me;
   wire 			      ram_enable_read_me;


   wire [`REGISTER_SIZE-1:0] 	      destination_wb;
   wire [`WORD_SIZE-1:0] 	      result_wb;
   wire [`WORD_SIZE-1:0] 	      operand2_wb;
   wire [`INMEDIATE_SIZE-1:0] 	      inmediate_wb;
   wire 			      write_enable_wb;
   wire 			      branch_taken_wb;
   wire [`WORD_SIZE-1:0] 	      mem_wb;
   wire [`WORD_SIZE-1:0] 	      data_wb;
   wire 			      ram_enable_read_wb;
   



   assign branch_taken_gl = ((branch_taken_rf || branch_taken_wb) && 
			     !(from_register_rf)) || from_register_ex;
   

   assign inmediate_addr_gl = (from_register_ex)? operand0_rf : inmediate_rf;

   assign hard_ip_gl = (branch_taken_wb)? inmediate_wb : inmediate_addr_gl;

   assign bub_hard_ip_gl = (stall_gl && !branch_taken_gl)? bub_current_ip_gl : hard_ip_gl;
   


   assign write_enable_gl = sto_ip_rf | write_enable_wb | ram_enable_read_wb;
   assign destination_gl = (sto_ip_rf)? `RA : destination_wb;
   assign data_wb = (ram_enable_read_wb)? ram_data_read: result_wb;   
   assign register_data_in_gl = (sto_ip_rf)? return_addr_gl: data_wb;
   


   UPCOUNTER_POSEDGE #(32) IP
     (
      .Clock(clk),
      .Reset(reset | branch_taken_gl | stall_gl),
      .Initial(bub_hard_ip_gl),
      .Enable(1'b1 && !stall_gl || branch_taken_gl),
      .Q(next_ip_gl)

      );

   FFD_POSEDGE_SYNCHRONOUS_RESET #(32) FF_ip
     (
      .Clock(clk),
      .Reset(reset),
      .Enable(1'b1),
      .D(next_ip_gl),
      .Q(current_ip_gl)
      );


   FFD_POSEDGE_SYNCHRONOUS_RESET #(32) FF_return
     (
      .Clock(clk),
      .Reset(reset),
      .Enable(sto_ip_fd),
      .D(bub_current_ip_gl+1),
      .Q(return_addr_gl)
      );



   ROM InstructionRom
     (
      .iAddress (bub_current_ip_gl),
      .oInstruction(instruction_fd)
      );


   Decoder Ins_decod
     (
      .instruction(instruction_fd),
      .branch_taken(branch_taken_fd),
      .link(sto_ip_fd),
      .from_register(from_register_fd),
      .operation(operation_fd),
      .inmediate(inmediate_fd),
      .destination(destination_fd),
      .read0(read0_fd),
      .read1(read1_fd),
      .read2(read2_fd),
      .ram_enable_write(ram_enable_write_fd),
      .ram_enable_read(ram_enable_read_fd)
      );

      Bubbler Bubbler
     (
      .Clock(clk),
      .Reset(reset | branch_taken_gl ),
      .current_address(next_ip_gl),
      .global_branch_taken(branch_taken_gl),
      .operation(operation_fd),
      .inmediate(inmediate_fd),
      .destination(destination_fd),
      .link(sto_ip_fd),
      .read0(read0_fd),
      .read1(read1_fd),
      .read2(read2_fd),
      .branch_taken(branch_taken_fd),
      .from_register(from_register_fd),
      .ram_enable_write(ram_enable_write_fd),
      .ram_enable_read(ram_enable_read_fd),

      .past_operation0(operation_rf),
      .past_operation1(operation_ex),
      .past_operation2(operation_me),

      .past_destination0(destination_rf),
      .past_destination1(destination_ex),
      .past_destination2(destination_me),

      .stall(stall_gl),
      .overwrite_address(bub_current_ip_gl),

      .out_operation(operation_rf),
      .out_inmediate(inmediate_rf),
      .out_destination(destination_rf),
      .out_read0(read0_rf),
      .out_read1(read1_rf),
      .out_read2(read2_rf),
      .out_branch_taken(branch_taken_rf),
      .out_link(sto_ip_rf),
      .out_from_register(from_register_rf),
      .out_ram_enable_write(ram_enable_write_rf),
      .out_ram_enable_read(ram_enable_read_rf)
      );

   






   Register_file Register_file
     (
      .Clock(clk),
      .iWriteEnable(write_enable_gl),
      .iReadAddress0(read0_rf),
      .iReadAddress1(read1_rf),
      .iReadAddress2(read2_rf),
      .iWriteAddress(destination_gl),
      .iDataIn(register_data_in_gl),
      .oDataOut0(operand0_rf),
      .oDataOut1(operand1_rf),
      .oDataOut2(operand2_rf)
      );
   


   FFD_POSEDGE_SYNCHRONOUS_RESET #(6+5+32+32+32+16+1+1+1) FF_rf
     (
      .Clock(clk),
      .Reset(reset | branch_taken_gl),
      .Enable(1'b1),
      .D({operation_rf, destination_rf, operand2_rf, operand1_rf, operand0_rf, inmediate_rf, ram_enable_write_rf, ram_enable_read_rf, from_register_rf}),
      .Q({operation_ex, destination_ex, operand2_ex, operand1_ex, operand0_ex, inmediate_ex, ram_enable_write_ex, ram_enable_read_ex, from_register_ex})
      );




   Alu Alu
     (
      .operation(operation_ex),
      .operand0(operand0_rf),
      .operand1(operand1_rf),
      .operand2(operand2_rf),
      .inmediate(inmediate_ex),
      .result(result_ex),
      .write_enable(write_enable_ex),
      .branch_taken(branch_taken_ex)
      );

   Output Output
		(
		 .clk(clk),
		 .reset(reset),
		 .operation(operation_ex),
		 .out(data),
		 .in(result_ex)
		 );
   



   FFD_POSEDGE_SYNCHRONOUS_RESET #(6+5+32+32+32+32+16+1+1+1+1) FF_ex
     (
      .Clock(clk),

      .Reset(reset),
      .Enable(1'b1),
      .D({operation_ex, destination_ex, result_ex, operand2_ex, operand1_ex, operand0_ex, inmediate_ex, write_enable_ex, branch_taken_ex, ram_enable_write_ex, ram_enable_read_ex}),
      .Q({operation_me, destination_me, result_me, operand2_me, operand1_me, operand0_me, inmediate_me, write_enable_me, branch_taken_me, ram_enable_write_me, ram_enable_read_me})
      );



   assign ram_enable_write = ram_enable_write_me;
   assign ram_data_write   = operand2_ex;
   assign ram_address      = operand1_ex+inmediate_me;
   assign ram_enable_read  = ram_enable_read_ex;

   


   FFD_POSEDGE_SYNCHRONOUS_RESET #(5+32+32+16+1+1+1+32) FF_me
     (
      .Clock(clk),

      .Reset(reset),
      .Enable(1'b1),

      .D({destination_me, operand2_me, result_me, inmediate_me, write_enable_me, ram_enable_read_me, branch_taken_me, ram_data_read}),
      .Q({destination_wb, operand2_wb, result_wb, inmediate_wb, write_enable_wb, ram_enable_read_wb, branch_taken_wb, mem_wb})
      );


endmodule