data/full_repos/permissive/113268705/FPGA_UART/UART.v
data/verilator_xmls/1832aebe-b61b-4b71-b628-31a9b0f1f7eb.xml
module UART(CLK,TX,RX);


input CLK;

input RX;
output reg TX;

reg[7:0] RXD,TXD;

parameter DATA_BIT = 8;
parameter PARITY_BIT = 0;
parameter STOP_BIT = 1;

parameter BAUDRATE = 2604;	

reg[3:0] TX_Status,RX_Status;
integer TX_Count,RX_Count;

reg TX_Start;

reg TX_Transaction, RX_Transaction;

reg BUFF;

integer timer;

initial begin
	BUFF = 0;
	timer = 0;
	
	TX_Count = 0;
	RX_Count = 0;

	TX_Start = 1;
	
	TX_Transaction = 1;
	RX_Transaction = 1;
	
	TX = 1;
	
	TX_Status = 0;
	RX_Status = 0;
	
	TXD = 8'h00;
	RXD = 8'h00;	
end


always @(posedge CLK) begin
	if(RX_Transaction) TXD <= RXD;
	else begin
		BUFF = 1;
	end
	
	if(RX_Transaction && BUFF) begin	
		TX_Start = 0;
		BUFF = 0;
	end else if(!BUFF) begin
		TX_Start = 1;
	end
end



always @(posedge CLK) begin
	if(TX_Transaction && !TX_Start) begin
		TX_Transaction = 0;
		TX = 0;
		TX_Status = 1;
		TX_Count = 0;
	end else if(!TX_Transaction) begin
		if(TX_Count == BAUDRATE) begin	
			if(TX_Status > 0 && TX_Status < 1 + DATA_BIT) begin
				TX = TXD[TX_Status -1];
			end else if(TX_Status < 1 + DATA_BIT + PARITY_BIT) begin
			end else if(TX_Status < 1 + DATA_BIT + PARITY_BIT + STOP_BIT) begin
				TX = 1;
			end else begin
				TX = 1;
				TX_Transaction = 1;
			end
			TX_Count = 0;
			TX_Status = TX_Status + 1;
		end
		TX_Count = TX_Count + 1;
	end
end

always @(posedge CLK) begin
	if(RX_Transaction && !RX) begin
		RX_Transaction = 0;
		RX_Status = 1;
		RX_Count = 0;
	end else if(!RX_Transaction) begin								
		if(RX_Count == BAUDRATE) begin
			if(RX_Status > 0 && RX_Status < 1 + DATA_BIT) begin
				RXD[RX_Status - 1] = RX;
				RX_Status = RX_Status + 1;
			end else if(RX_Status < 1 + DATA_BIT + PARITY_BIT) begin
			end else if(RX_Status < 1 + DATA_BIT + PARITY_BIT + STOP_BIT) begin
				if(RX) begin
					RX_Status = RX_Status + 1;
				end else begin
					RX_Transaction = 1;															
					RX_Count = 0;
				end
			end else begin
				RX_Transaction = 1;
				RX_Count = 0;
			end
			RX_Count = 0;
		end
		RX_Count = RX_Count + 1;
	end
end

endmodule
module UART(CLK,TX,RX);



input CLK;

input RX;
output reg TX;

reg[7:0] RXD,TXD;

parameter DATA_BIT = 8;
parameter PARITY_BIT = 0;
parameter STOP_BIT = 1;

parameter BAUDRATE = 2604;	

reg[3:0] TX_Status,RX_Status;
integer TX_Count,RX_Count;

reg TX_Start;

reg TX_Transaction, RX_Transaction;

reg BUFF;

integer timer;

initial begin
	BUFF = 0;
	timer = 0;
	
	TX_Count = 0;
	RX_Count = 0;

	TX_Start = 1;
	
	TX_Transaction = 1;
	RX_Transaction = 1;
	
	TX = 1;
	
	TX_Status = 0;
	RX_Status = 0;
	
	TXD = 8'h00;
	RXD = 8'h00;	
end


always @(posedge CLK) begin
	if(RX_Transaction) TXD <= RXD;
	else begin
		BUFF = 1;
	end
	
	if(RX_Transaction && BUFF) begin	
		TX_Start = 0;
		BUFF = 0;
	end else if(!BUFF) begin
		TX_Start = 1;
	end
end



always @(posedge CLK) begin
	if(TX_Transaction && !TX_Start) begin
		TX_Transaction = 0;
		TX = 0;
		TX_Status = 1;
		TX_Count = 0;
	end else if(!TX_Transaction) begin
		if(TX_Count == BAUDRATE) begin	
			if(TX_Status > 0 && TX_Status < 1 + DATA_BIT) begin
				TX = TXD[TX_Status -1];
			end else if(TX_Status < 1 + DATA_BIT + PARITY_BIT) begin
			end else if(TX_Status < 1 + DATA_BIT + PARITY_BIT + STOP_BIT) begin
				TX = 1;
			end else begin
				TX = 1;
				TX_Transaction = 1;
			end
			TX_Count = 0;
			TX_Status = TX_Status + 1;
		end
		TX_Count = TX_Count + 1;
	end
end

always @(posedge CLK) begin
	if(RX_Transaction && !RX) begin
		RX_Transaction = 0;
		RX_Status = 1;
		RX_Count = 0;
	end else if(!RX_Transaction) begin								
		if(RX_Count == BAUDRATE) begin
			if(RX_Status > 0 && RX_Status < 1 + DATA_BIT) begin
				RXD[RX_Status - 1] = RX;
				RX_Status = RX_Status + 1;
			end else if(RX_Status < 1 + DATA_BIT + PARITY_BIT) begin
			end else if(RX_Status < 1 + DATA_BIT + PARITY_BIT + STOP_BIT) begin
				if(RX) begin
					RX_Status = RX_Status + 1;
				end else begin
					RX_Transaction = 1;															
					RX_Count = 0;
				end
			end else begin
				RX_Transaction = 1;
				RX_Count = 0;
			end
			RX_Count = 0;
		end
		RX_Count = RX_Count + 1;
	end
end

endmodule