data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/hdl/5932_74HC161.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/hdl/5932_74HC161.v:3: Little bit endian vector: MSB < LSB of bit range: 0:3\ninput MR,CP,CEP,CET,PE;input[0:3]D;\n                            ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/hdl/5932_74HC161.v:4: Little bit endian vector: MSB < LSB of bit range: 0:3\noutput[0:3]Q;output TC;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/165160692/04.FPGA/5932_74HC161/hdl/5932_74HC161.v:5: Little bit endian vector: MSB < LSB of bit range: 0:3\nreg [0:3]QAUX;reg TC;\n    ^\n%Error: Exiting due to 3 warning(s)\n'
module HC161(MR,CP,CEP,CET,PE,D,Q,TC);
input MR,CP,CEP,CET,PE;input[0:3]D;
output[0:3]Q;output TC;
reg [0:3]QAUX;reg TC;

always@(posedge CP)
 begin
  if(!MR)
   begin QAUX<=0;TC=0;end
  else if(!PE)
   begin QAUX<=D;TC=CET&Q[3]&Q[2]&Q[1]&Q[0];end
  else if(!CEP)
   begin QAUX<=QAUX;TC=CET&Q[3]&Q[2]&Q[1]&Q[0];end
  else if(!CET)
   begin QAUX<=QAUX;TC=0;end
  else begin QAUX<=QAUX+1;TC=CET&Q[3]&Q[2]&Q[1]&Q[0];end
  if(QAUX==4'b1111)TC=1'b1;
 end
assign Q=QAUX;
endmodule
module HC161(MR,CP,CEP,CET,PE,D,Q,TC);

input MR,CP,CEP,CET,PE;input[0:3]D;
output[0:3]Q;output TC;
reg [0:3]QAUX;reg TC;

always@(posedge CP)
 begin
  if(!MR)
   begin QAUX<=0;TC=0;end
  else if(!PE)
   begin QAUX<=D;TC=CET&Q[3]&Q[2]&Q[1]&Q[0];end
  else if(!CEP)
   begin QAUX<=QAUX;TC=CET&Q[3]&Q[2]&Q[1]&Q[0];end
  else if(!CET)
   begin QAUX<=QAUX;TC=0;end
  else begin QAUX<=QAUX+1;TC=CET&Q[3]&Q[2]&Q[1]&Q[0];end
  if(QAUX==4'b1111)TC=1'b1;
 end
assign Q=QAUX;
endmodule