data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:1: Cannot find include file: Util/Math.v\n`include "Util/Math.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Util/Math.v\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Util/Math.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Stage,data/full_repos/permissive/131921633/Util/Math.v.sv\n             Util/Math.v\n             Util/Math.v.v\n             Util/Math.v.sv\n             obj_dir/Util/Math.v\n             obj_dir/Util/Math.v.v\n             obj_dir/Util/Math.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:2: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:3: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:5: Cannot find include file: Mips/Pipeline/Ex/Mem.v\n`include "Mips/Pipeline/Ex/Mem.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:6: Cannot find include file: Mips/Pipeline/Mem/Reg.v\n`include "Mips/Pipeline/Mem/Reg.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:7: Cannot find include file: Mips/Pipeline/Mem/Fwd.v\n`include "Mips/Pipeline/Mem/Fwd.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:9: Cannot find include file: Mips/Datapath/Memory/datapath.v\n`include "Mips/Datapath/Memory/datapath.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:17: Define or directive not defined: \'`Data_Control_Control_T\'\n ( `Data_Control_Control_T (input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:17: syntax error, unexpected \'(\', expecting \'[\'\n ( `Data_Control_Control_T (input) ctrl\n                            ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:18: Define or directive not defined: \'`Mips_Pipeline_ExMem_T\'\n , `Mips_Pipeline_ExMem_T (input) pipeExMem\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:19: Define or directive not defined: \'`Mips_Pipeline_MemReg_T\'\n , `Mips_Pipeline_MemReg_T (output) pipeMemReg\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:20: Define or directive not defined: \'`Mips_Pipeline_MemFwd_T\'\n , `Mips_Pipeline_MemFwd_T (output) pipeMemFwd\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:23: Define or directive not defined: \'`Util_Math_log2_expr\'\n`Util_Math_log2_expr\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:25: Define or directive not defined: \'`Mips_Pipeline_ExMem_Decl_Defaults\'\n`Mips_Pipeline_ExMem_Decl_Defaults\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:36: Define or directive not defined: \'`Mips_Type_RegPorts_T\'\n`Mips_Type_RegPorts_T (reg) regPorts$;\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:37: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways @(posedge `Data_Control_Control_Clock(ctrl))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:40: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (reg) aluResult$;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:41: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways @(posedge `Data_Control_Control_Clock(ctrl))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:44: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (reg) memData;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:47: Define or directive not defined: \'`Mips_Type_RegPorts_WriteAddr\'\n  `Mips_Type_RegPorts_WriteAddr(regPorts$) ==\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:48: Define or directive not defined: \'`Mips_Type_RegPorts_Read2Addr\'\n  `Mips_Type_RegPorts_Read2Addr(regPorts)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:55: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) memOut;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:68: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (reg) memOutD;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:69: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways @(posedge `Data_Control_Control_Clock(ctrl))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:72: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (reg) regPort2$;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:73: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways @(posedge `Data_Control_Control_Clock(ctrl))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Stage/mem.v:76: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (reg) memOut$;\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 27 error(s)\n'
module Mips_Stage_mem #
	( parameter DELAYED = 1
	, parameter ADDR_L = 64
	, parameter ADDR_W = Util_Math_log2(ADDR_L)
	, parameter INVERT_CTRL = 0
	)
	( `Data_Control_Control_T (input) ctrl
	, `Mips_Pipeline_ExMem_T (input) pipeExMem
	, `Mips_Pipeline_MemReg_T (output) pipeMemReg
	, `Mips_Pipeline_MemFwd_T (output) pipeMemFwd
	);

`Util_Math_log2_expr

`Mips_Pipeline_ExMem_Decl_Defaults
Mips_Pipeline_ExMem_unpack EXMEM
	( .in (pipeExMem)
	, .instruction (instruction)
	, .pcAddr      (pcAddr)
	, .control     (control)
	, .regPort2    (regPort2)
	, .regPorts    (regPorts)
	, .aluResult   (aluResult)
	);

`Mips_Type_RegPorts_T (reg) regPorts$;
always @(posedge `Data_Control_Control_Clock(ctrl))
	regPorts$ <= regPorts;

`Mips_Type_Word_T (reg) aluResult$;
always @(posedge `Data_Control_Control_Clock(ctrl))
	aluResult$ <= aluResult;

`Mips_Type_Word_T (reg) memData;
always @(*)
	if(
		`Mips_Type_RegPorts_WriteAddr(regPorts$) ==
		`Mips_Type_RegPorts_Read2Addr(regPorts)
	)
		memData = aluResult$;
	else
		memData = regPort2;


`Mips_Type_Word_T (wire) memOut;
Mips_Datapath_Memory_datapath #
	( .ADDR_L (64)
	, .ADDR_W (Util_Math_log2(ADDR_L))
	, .INVERT_CTRL (INVERT_CTRL)
	) MEM
	( .ctrl (ctrl)
	, .aluResult (aluResult)
	, .regPort2  (memData)
	, .control   (control)
	, .out       (memOut)
	);

`Mips_Type_Word_T (reg) memOutD;
always @(posedge `Data_Control_Control_Clock(ctrl))
	memOutD <= memOut;

`Mips_Type_Word_T (reg) regPort2$;
always @(posedge `Data_Control_Control_Clock(ctrl))
	regPort2$ <= regPort2;

`Mips_Type_Word_T (reg) memOut$;
always @(*)
	if(
		aluResult == aluResult$
	)
		memOut$ = regPort2$;
	else
		memOut$ = memOut;


Mips_Pipeline_MemReg_generate #
	( .DELAYED (DELAYED)
	) MEMREG
	( .ctrl (ctrl)
	, .instruction (instruction)
	, .pcAddr      (pcAddr)
	, .memOut      (memOut$)
	, .aluResult   (aluResult)
	, .regPorts    (regPorts)
	, .out         (pipeMemReg)
	);

Mips_Pipeline_MemFwd_pack MEMFWD
	( .out (pipeMemFwd)
	, .pcAddr    (pcAddr)
	, .aluResult (aluResult)
	, .regPorts  (regPorts)
	);

endmodule
module Mips_Stage_mem #
	( parameter DELAYED = 1
	, parameter ADDR_L = 64
	, parameter ADDR_W = Util_Math_log2(ADDR_L)
	, parameter INVERT_CTRL = 0
	)
	( `Data_Control_Control_T (input) ctrl
	, `Mips_Pipeline_ExMem_T (input) pipeExMem
	, `Mips_Pipeline_MemReg_T (output) pipeMemReg
	, `Mips_Pipeline_MemFwd_T (output) pipeMemFwd
	);


`Util_Math_log2_expr

`Mips_Pipeline_ExMem_Decl_Defaults
Mips_Pipeline_ExMem_unpack EXMEM
	( .in (pipeExMem)
	, .instruction (instruction)
	, .pcAddr      (pcAddr)
	, .control     (control)
	, .regPort2    (regPort2)
	, .regPorts    (regPorts)
	, .aluResult   (aluResult)
	);

`Mips_Type_RegPorts_T (reg) regPorts$;
always @(posedge `Data_Control_Control_Clock(ctrl))
	regPorts$ <= regPorts;

`Mips_Type_Word_T (reg) aluResult$;
always @(posedge `Data_Control_Control_Clock(ctrl))
	aluResult$ <= aluResult;

`Mips_Type_Word_T (reg) memData;
always @(*)
	if(
		`Mips_Type_RegPorts_WriteAddr(regPorts$) ==
		`Mips_Type_RegPorts_Read2Addr(regPorts)
	)
		memData = aluResult$;
	else
		memData = regPort2;


`Mips_Type_Word_T (wire) memOut;
Mips_Datapath_Memory_datapath #
	( .ADDR_L (64)
	, .ADDR_W (Util_Math_log2(ADDR_L))
	, .INVERT_CTRL (INVERT_CTRL)
	) MEM
	( .ctrl (ctrl)
	, .aluResult (aluResult)
	, .regPort2  (memData)
	, .control   (control)
	, .out       (memOut)
	);

`Mips_Type_Word_T (reg) memOutD;
always @(posedge `Data_Control_Control_Clock(ctrl))
	memOutD <= memOut;

`Mips_Type_Word_T (reg) regPort2$;
always @(posedge `Data_Control_Control_Clock(ctrl))
	regPort2$ <= regPort2;

`Mips_Type_Word_T (reg) memOut$;
always @(*)
	if(
		aluResult == aluResult$
	)
		memOut$ = regPort2$;
	else
		memOut$ = memOut;


Mips_Pipeline_MemReg_generate #
	( .DELAYED (DELAYED)
	) MEMREG
	( .ctrl (ctrl)
	, .instruction (instruction)
	, .pcAddr      (pcAddr)
	, .memOut      (memOut$)
	, .aluResult   (aluResult)
	, .regPorts    (regPorts)
	, .out         (pipeMemReg)
	);

Mips_Pipeline_MemFwd_pack MEMFWD
	( .out (pipeMemFwd)
	, .pcAddr    (pcAddr)
	, .aluResult (aluResult)
	, .regPorts  (regPorts)
	);

endmodule