data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v
1: b'%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:45: Cannot find include file: openMSP430_defines.v\n`include "openMSP430_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/152581089/Verilog/MSP430,data/full_repos/permissive/152581089/openMSP430_defines.v\n             data/full_repos/permissive/152581089/Verilog/MSP430,data/full_repos/permissive/152581089/openMSP430_defines.v.v\n             data/full_repos/permissive/152581089/Verilog/MSP430,data/full_repos/permissive/152581089/openMSP430_defines.v.sv\n             openMSP430_defines.v\n             openMSP430_defines.v.v\n             openMSP430_defines.v.sv\n             obj_dir/openMSP430_defines.v\n             obj_dir/openMSP430_defines.v.v\n             obj_dir/openMSP430_defines.v.sv\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:257: Cannot find include file: openMSP430_undefines.v\n`include "openMSP430_undefines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:151: Define or directive not defined: \'`ALU_SRC_INV\'\nwire        op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]);\n                                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:151: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire        op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]);\n                                                                ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:161: Define or directive not defined: \'`JL\'\nwire        jmp_not_taken  = (inst_jmp[`JL]  & ~(status[3]^status[2])) |\n                                       ^~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:161: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire        jmp_not_taken  = (inst_jmp[`JL]  & ~(status[3]^status[2])) |\n                                          ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:162: Define or directive not defined: \'`JGE\'\n                             (inst_jmp[`JGE] &  (status[3]^status[2])) |\n                                       ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:163: Define or directive not defined: \'`JN\'\n                             (inst_jmp[`JN]  &  ~status[2])            |\n                                       ^~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:164: Define or directive not defined: \'`JC\'\n                             (inst_jmp[`JC]  &  ~status[0])            |\n                                       ^~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:165: Define or directive not defined: \'`JNC\'\n                             (inst_jmp[`JNC] &   status[0])            |\n                                       ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:166: Define or directive not defined: \'`JEQ\'\n                             (inst_jmp[`JEQ] &  ~status[1])            |\n                                       ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:167: Define or directive not defined: \'`JNE\'\n                             (inst_jmp[`JNE] &   status[1]);\n                                       ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:178: Define or directive not defined: \'`ALU_INC_C\'\nwire        alu_inc         = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) |\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:178: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire        alu_inc         = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) |\n                                                                ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:179: Define or directive not defined: \'`ALU_INC\'\n                                             inst_alu[`ALU_INC]);\n                                                      ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:193: Define or directive not defined: \'`RRC\'\nwire        alu_shift_msb  = inst_so[`RRC] ? status[0]     :\n                                     ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:193: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire        alu_shift_msb  = inst_so[`RRC] ? status[0]     :\n                                         ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:205: Define or directive not defined: \'`ALU_AND\'\nwire        alu_short_thro = ~(inst_alu[`ALU_AND]   |\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:205: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire        alu_short_thro = ~(inst_alu[`ALU_AND]   |\n                                                ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:206: Define or directive not defined: \'`ALU_OR\'\n                               inst_alu[`ALU_OR]    |\n                                        ^~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:207: Define or directive not defined: \'`ALU_XOR\'\n                               inst_alu[`ALU_XOR]   |\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:208: Define or directive not defined: \'`ALU_SHIFT\'\n                               inst_alu[`ALU_SHIFT] |\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:209: Define or directive not defined: \'`SWPB\'\n                               inst_so[`SWPB]       |\n                                       ^~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:210: Define or directive not defined: \'`SXT\'\n                               inst_so[`SXT]);\n                                       ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:212: Define or directive not defined: \'`ALU_AND\'\nwire [16:0] alu_short      = ({17{inst_alu[`ALU_AND]}}   & alu_and)   |\n                                           ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:212: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [16:0] alu_short      = ({17{inst_alu[`ALU_AND]}}   & alu_and)   |\n                                                   ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:213: Define or directive not defined: \'`ALU_OR\'\n                             ({17{inst_alu[`ALU_OR]}}    & alu_or)    |\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:214: Define or directive not defined: \'`ALU_XOR\'\n                             ({17{inst_alu[`ALU_XOR]}}   & alu_xor)   |\n                                           ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:215: Define or directive not defined: \'`ALU_SHIFT\'\n                             ({17{inst_alu[`ALU_SHIFT]}} & alu_shift) |\n                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:216: Define or directive not defined: \'`SWPB\'\n                             ({17{inst_so[`SWPB]}}       & alu_swpb)  |\n                                          ^~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:217: Define or directive not defined: \'`SXT\'\n                             ({17{inst_so[`SXT]}}        & alu_sxt)   |\n                                          ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:222: Define or directive not defined: \'`IRQ\'\nwire [16:0] alu_out_nxt    = (inst_so[`IRQ] | dbg_halt_st |\n                                      ^~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:222: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [16:0] alu_out_nxt    = (inst_so[`IRQ] | dbg_halt_st |\n                                          ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:223: Define or directive not defined: \'`ALU_ADD\'\n                              inst_alu[`ALU_ADD]) ? alu_add_inc :\n                                       ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:224: Define or directive not defined: \'`ALU_DADD\'\n                              inst_alu[`ALU_DADD] ? alu_dadd    : alu_short;\n                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:246: Define or directive not defined: \'`ALU_SHIFT\'\nassign  alu_stat    = inst_alu[`ALU_SHIFT]  ? {1\'b0, N,Z,op_src_in[0]} :\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:246: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign  alu_stat    = inst_alu[`ALU_SHIFT]  ? {1\'b0, N,Z,op_src_in[0]} :\n                                         ^\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:247: Define or directive not defined: \'`ALU_STAT_7\'\n                      inst_alu[`ALU_STAT_7] ? {1\'b0, N,Z,~Z}           :\n                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:248: Define or directive not defined: \'`ALU_XOR\'\n                      inst_alu[`ALU_XOR]    ? {V_xor,N,Z,~Z}           : {V,N,Z,C};\n                               ^~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:250: Define or directive not defined: \'`ALU_STAT_F\'\nassign  alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4\'b1111 : 4\'b0000;\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/152581089/Verilog/MSP430/omsp_alu.v:250: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign  alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4\'b1111 : 4\'b0000;\n                                           ^\n%Error: Exiting due to 41 error(s)\n'
module  omsp_alu (


    alu_out,
    alu_out_add,
    alu_stat,
    alu_stat_wr,


    dbg_halt_st,
    exec_cycle,
    inst_alu,
    inst_bw,
    inst_jmp,
    inst_so,
    op_dst,
    op_src,
    status
);



output       [15:0] alu_out;
output       [15:0] alu_out_add;
output        [3:0] alu_stat;
output        [3:0] alu_stat_wr;



input               dbg_halt_st;
input               exec_cycle;
input        [11:0] inst_alu;
input               inst_bw;
input         [7:0] inst_jmp;
input         [7:0] inst_so;
input        [15:0] op_dst;
input        [15:0] op_src;
input         [3:0] status;






function [4:0] bcd_add;

   input [3:0] X;
   input [3:0] Y;
   input       C_;

   reg   [4:0] Z_;
   begin
      Z_ = {1'b0,X}+{1'b0,Y}+{4'b0000,C_};
      if (Z_<5'd10) bcd_add = Z_;
      else          bcd_add = Z_+5'd6;
   end

endfunction













































wire        op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]);
wire [15:0] op_src_inv     = {16{op_src_inv_cmd}} ^ op_src;



wire        op_bit8_msk     = ~exec_cycle | ~inst_bw;
wire [16:0] op_src_in       = {1'b0, {op_src_inv[15:8] & {8{op_bit8_msk}}}, op_src_inv[7:0]};
wire [16:0] op_dst_in       = {1'b0, {op_dst[15:8]     & {8{op_bit8_msk}}}, op_dst[7:0]};


wire        jmp_not_taken  = (inst_jmp[`JL]  & ~(status[3]^status[2])) |
                             (inst_jmp[`JGE] &  (status[3]^status[2])) |
                             (inst_jmp[`JN]  &  ~status[2])            |
                             (inst_jmp[`JC]  &  ~status[0])            |
                             (inst_jmp[`JNC] &   status[0])            |
                             (inst_jmp[`JEQ] &  ~status[1])            |
                             (inst_jmp[`JNE] &   status[1]);
wire [16:0] op_src_in_jmp  = op_src_in & {17{~jmp_not_taken}};


wire [16:0] alu_add        = op_src_in_jmp + op_dst_in;
wire [16:0] alu_and        = op_src_in     & op_dst_in;
wire [16:0] alu_or         = op_src_in     | op_dst_in;
wire [16:0] alu_xor        = op_src_in     ^ op_dst_in;



wire        alu_inc         = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) |
                                             inst_alu[`ALU_INC]);
wire [16:0] alu_add_inc    = alu_add + {16'h0000, alu_inc};




wire  [4:0] alu_dadd0      = bcd_add(op_src_in[3:0],   op_dst_in[3:0],  status[0]);
wire  [4:0] alu_dadd1      = bcd_add(op_src_in[7:4],   op_dst_in[7:4],  alu_dadd0[4]);
wire  [4:0] alu_dadd2      = bcd_add(op_src_in[11:8],  op_dst_in[11:8], alu_dadd1[4]);
wire  [4:0] alu_dadd3      = bcd_add(op_src_in[15:12], op_dst_in[15:12],alu_dadd2[4]);
wire [16:0] alu_dadd       = {alu_dadd3, alu_dadd2[3:0], alu_dadd1[3:0], alu_dadd0[3:0]};



wire        alu_shift_msb  = inst_so[`RRC] ? status[0]     :
	                     inst_bw       ? op_src[7]     : op_src[15];
wire        alu_shift_7    = inst_bw       ? alu_shift_msb : op_src[8];
wire [16:0] alu_shift      = {1'b0, alu_shift_msb, op_src[15:9], alu_shift_7, op_src[7:1]};



wire [16:0] alu_swpb       = {1'b0, op_src[7:0],op_src[15:8]};
wire [16:0] alu_sxt        = {1'b0, {8{op_src[7]}},op_src[7:0]};



wire        alu_short_thro = ~(inst_alu[`ALU_AND]   |
                               inst_alu[`ALU_OR]    |
                               inst_alu[`ALU_XOR]   |
                               inst_alu[`ALU_SHIFT] |
                               inst_so[`SWPB]       |
                               inst_so[`SXT]);

wire [16:0] alu_short      = ({17{inst_alu[`ALU_AND]}}   & alu_and)   |
                             ({17{inst_alu[`ALU_OR]}}    & alu_or)    |
                             ({17{inst_alu[`ALU_XOR]}}   & alu_xor)   |
                             ({17{inst_alu[`ALU_SHIFT]}} & alu_shift) |
                             ({17{inst_so[`SWPB]}}       & alu_swpb)  |
                             ({17{inst_so[`SXT]}}        & alu_sxt)   |
                             ({17{alu_short_thro}}       & op_src_in);



wire [16:0] alu_out_nxt    = (inst_so[`IRQ] | dbg_halt_st |
                              inst_alu[`ALU_ADD]) ? alu_add_inc :
                              inst_alu[`ALU_DADD] ? alu_dadd    : alu_short;

assign      alu_out        =  alu_out_nxt[15:0];
assign      alu_out_add    =  alu_add[15:0];






wire    V_xor       = inst_bw ? (op_src_in[7]  & op_dst_in[7])  :
                                (op_src_in[15] & op_dst_in[15]);

wire    V           = inst_bw ? ((~op_src_in[7]  & ~op_dst_in[7]  &  alu_out[7])  |
                                 ( op_src_in[7]  &  op_dst_in[7]  & ~alu_out[7])) :
                                ((~op_src_in[15] & ~op_dst_in[15] &  alu_out[15]) |
                                 ( op_src_in[15] &  op_dst_in[15] & ~alu_out[15]));

wire    N           = inst_bw ?  alu_out[7]       : alu_out[15];
wire    Z           = inst_bw ? (alu_out[7:0]==0) : (alu_out==0);
wire    C           = inst_bw ?  alu_out[8]       : alu_out_nxt[16];

assign  alu_stat    = inst_alu[`ALU_SHIFT]  ? {1'b0, N,Z,op_src_in[0]} :
                      inst_alu[`ALU_STAT_7] ? {1'b0, N,Z,~Z}           :
                      inst_alu[`ALU_XOR]    ? {V_xor,N,Z,~Z}           : {V,N,Z,C};

assign  alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4'b1111 : 4'b0000;


endmodule
module  omsp_alu (


    alu_out,
    alu_out_add,
    alu_stat,
    alu_stat_wr,


    dbg_halt_st,
    exec_cycle,
    inst_alu,
    inst_bw,
    inst_jmp,
    inst_so,
    op_dst,
    op_src,
    status
);




output       [15:0] alu_out;
output       [15:0] alu_out_add;
output        [3:0] alu_stat;
output        [3:0] alu_stat_wr;



input               dbg_halt_st;
input               exec_cycle;
input        [11:0] inst_alu;
input               inst_bw;
input         [7:0] inst_jmp;
input         [7:0] inst_so;
input        [15:0] op_dst;
input        [15:0] op_src;
input         [3:0] status;






function [4:0] bcd_add;

   input [3:0] X;
   input [3:0] Y;
   input       C_;

   reg   [4:0] Z_;
   begin
      Z_ = {1'b0,X}+{1'b0,Y}+{4'b0000,C_};
      if (Z_<5'd10) bcd_add = Z_;
      else          bcd_add = Z_+5'd6;
   end

endfunction













































wire        op_src_inv_cmd = exec_cycle & (inst_alu[`ALU_SRC_INV]);
wire [15:0] op_src_inv     = {16{op_src_inv_cmd}} ^ op_src;



wire        op_bit8_msk     = ~exec_cycle | ~inst_bw;
wire [16:0] op_src_in       = {1'b0, {op_src_inv[15:8] & {8{op_bit8_msk}}}, op_src_inv[7:0]};
wire [16:0] op_dst_in       = {1'b0, {op_dst[15:8]     & {8{op_bit8_msk}}}, op_dst[7:0]};


wire        jmp_not_taken  = (inst_jmp[`JL]  & ~(status[3]^status[2])) |
                             (inst_jmp[`JGE] &  (status[3]^status[2])) |
                             (inst_jmp[`JN]  &  ~status[2])            |
                             (inst_jmp[`JC]  &  ~status[0])            |
                             (inst_jmp[`JNC] &   status[0])            |
                             (inst_jmp[`JEQ] &  ~status[1])            |
                             (inst_jmp[`JNE] &   status[1]);
wire [16:0] op_src_in_jmp  = op_src_in & {17{~jmp_not_taken}};


wire [16:0] alu_add        = op_src_in_jmp + op_dst_in;
wire [16:0] alu_and        = op_src_in     & op_dst_in;
wire [16:0] alu_or         = op_src_in     | op_dst_in;
wire [16:0] alu_xor        = op_src_in     ^ op_dst_in;



wire        alu_inc         = exec_cycle & ((inst_alu[`ALU_INC_C] & status[0]) |
                                             inst_alu[`ALU_INC]);
wire [16:0] alu_add_inc    = alu_add + {16'h0000, alu_inc};




wire  [4:0] alu_dadd0      = bcd_add(op_src_in[3:0],   op_dst_in[3:0],  status[0]);
wire  [4:0] alu_dadd1      = bcd_add(op_src_in[7:4],   op_dst_in[7:4],  alu_dadd0[4]);
wire  [4:0] alu_dadd2      = bcd_add(op_src_in[11:8],  op_dst_in[11:8], alu_dadd1[4]);
wire  [4:0] alu_dadd3      = bcd_add(op_src_in[15:12], op_dst_in[15:12],alu_dadd2[4]);
wire [16:0] alu_dadd       = {alu_dadd3, alu_dadd2[3:0], alu_dadd1[3:0], alu_dadd0[3:0]};



wire        alu_shift_msb  = inst_so[`RRC] ? status[0]     :
	                     inst_bw       ? op_src[7]     : op_src[15];
wire        alu_shift_7    = inst_bw       ? alu_shift_msb : op_src[8];
wire [16:0] alu_shift      = {1'b0, alu_shift_msb, op_src[15:9], alu_shift_7, op_src[7:1]};



wire [16:0] alu_swpb       = {1'b0, op_src[7:0],op_src[15:8]};
wire [16:0] alu_sxt        = {1'b0, {8{op_src[7]}},op_src[7:0]};



wire        alu_short_thro = ~(inst_alu[`ALU_AND]   |
                               inst_alu[`ALU_OR]    |
                               inst_alu[`ALU_XOR]   |
                               inst_alu[`ALU_SHIFT] |
                               inst_so[`SWPB]       |
                               inst_so[`SXT]);

wire [16:0] alu_short      = ({17{inst_alu[`ALU_AND]}}   & alu_and)   |
                             ({17{inst_alu[`ALU_OR]}}    & alu_or)    |
                             ({17{inst_alu[`ALU_XOR]}}   & alu_xor)   |
                             ({17{inst_alu[`ALU_SHIFT]}} & alu_shift) |
                             ({17{inst_so[`SWPB]}}       & alu_swpb)  |
                             ({17{inst_so[`SXT]}}        & alu_sxt)   |
                             ({17{alu_short_thro}}       & op_src_in);



wire [16:0] alu_out_nxt    = (inst_so[`IRQ] | dbg_halt_st |
                              inst_alu[`ALU_ADD]) ? alu_add_inc :
                              inst_alu[`ALU_DADD] ? alu_dadd    : alu_short;

assign      alu_out        =  alu_out_nxt[15:0];
assign      alu_out_add    =  alu_add[15:0];






wire    V_xor       = inst_bw ? (op_src_in[7]  & op_dst_in[7])  :
                                (op_src_in[15] & op_dst_in[15]);

wire    V           = inst_bw ? ((~op_src_in[7]  & ~op_dst_in[7]  &  alu_out[7])  |
                                 ( op_src_in[7]  &  op_dst_in[7]  & ~alu_out[7])) :
                                ((~op_src_in[15] & ~op_dst_in[15] &  alu_out[15]) |
                                 ( op_src_in[15] &  op_dst_in[15] & ~alu_out[15]));

wire    N           = inst_bw ?  alu_out[7]       : alu_out[15];
wire    Z           = inst_bw ? (alu_out[7:0]==0) : (alu_out==0);
wire    C           = inst_bw ?  alu_out[8]       : alu_out_nxt[16];

assign  alu_stat    = inst_alu[`ALU_SHIFT]  ? {1'b0, N,Z,op_src_in[0]} :
                      inst_alu[`ALU_STAT_7] ? {1'b0, N,Z,~Z}           :
                      inst_alu[`ALU_XOR]    ? {V_xor,N,Z,~Z}           : {V,N,Z,C};

assign  alu_stat_wr = (inst_alu[`ALU_STAT_F] & exec_cycle) ? 4'b1111 : 4'b0000;


endmodule