data/full_repos/permissive/132157042/src/pixram.v
1: b"%Error-ASSIGNIN: data/full_repos/permissive/132157042/src/pixram.v:47: Assigning to input/const variable: 'data_out'\n   bram #(12, 8) bram_a(clk, read, write_a, raddr, waddr[11:0], data_out[31:24], data_in);\n                                                                ^~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/132157042/src/pixram.v:48: Assigning to input/const variable: 'data_out'\n   bram #(12, 8) bram_b(clk, read, write_b, raddr, waddr[11:0], data_out[23:16], data_in);\n                                                                ^~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/132157042/src/pixram.v:49: Assigning to input/const variable: 'data_out'\n   bram #(12, 8) bram_c(clk, read, write_c, raddr, waddr[11:0], data_out[15:8], data_in);\n                                                                ^~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/132157042/src/pixram.v:50: Assigning to input/const variable: 'data_out'\n   bram #(12, 8) bram_d(clk, read, write_d, raddr, waddr[11:0], data_out[7:0], data_in);\n                                                                ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module pixram
  (
   input wire        clk,
   input wire        read,
   input wire        write,
   input wire [11:0] raddr,
   input wire [13:0] waddr,
   input wire [31:0] data_out,
   input wire [7:0]  data_in);


   wire              write_a = write && waddr[13:12] == 2'b00 ;
   wire              write_b = write && waddr[13:12] == 2'b01;
   wire              write_c = write && waddr[13:12] == 2'b10 ;
   wire              write_d = write && waddr[13:12] == 2'b11;

   bram #(12, 8) bram_a(clk, read, write_a, raddr, waddr[11:0], data_out[31:24], data_in);
   bram #(12, 8) bram_b(clk, read, write_b, raddr, waddr[11:0], data_out[23:16], data_in);
   bram #(12, 8) bram_c(clk, read, write_c, raddr, waddr[11:0], data_out[15:8], data_in);
   bram #(12, 8) bram_d(clk, read, write_d, raddr, waddr[11:0], data_out[7:0], data_in);
endmodule
module pixram
  (
   input wire        clk,
   input wire        read,
   input wire        write,
   input wire [11:0] raddr,
   input wire [13:0] waddr,
   input wire [31:0] data_out,
   input wire [7:0]  data_in);



   wire              write_a = write && waddr[13:12] == 2'b00 ;
   wire              write_b = write && waddr[13:12] == 2'b01;
   wire              write_c = write && waddr[13:12] == 2'b10 ;
   wire              write_d = write && waddr[13:12] == 2'b11;

   bram #(12, 8) bram_a(clk, read, write_a, raddr, waddr[11:0], data_out[31:24], data_in);
   bram #(12, 8) bram_b(clk, read, write_b, raddr, waddr[11:0], data_out[23:16], data_in);
   bram #(12, 8) bram_c(clk, read, write_c, raddr, waddr[11:0], data_out[15:8], data_in);
   bram #(12, 8) bram_d(clk, read, write_d, raddr, waddr[11:0], data_out[7:0], data_in);
endmodule