data/full_repos/permissive/208113388/afu/afp/mcp3_arb004.v
data/verilator_xmls/d8296cc9-9b67-4f2e-bdee-ef42a3b2f305.xml
module mcp3_arb004 (


    input                 clock
  , input                 reset


  , input                 req_taken
  , input           [3:0] req_bus
  , input           [3:0] req_bus_2pending


  , output                winner_valid
  , output          [1:0] winner
  , output reg      [3:0] req_clear

  );

  reg       [3:0] decoded_winner;
  reg       [3:0] current_winner;
  wire      [3:0] new_winner_gt;
  wire            pick_new_winner;                                                                                                 
  wire      [3:0] new_winner;
  reg       [1:0] new_winner_encoded;                                                                                              
  wire            any_new_winner;                                                                                                  

  reg       [1:0] winner_d;                                                                                                        
  reg       [1:0] winner_q;
  wire            winner_valid_d;                                                                                                          
  reg             winner_valid_q;                                                                                                          


  always @*
    begin

      case ( winner_q[1:0] )
        2'b00 :  decoded_winner[3:0] = 4'b0001;
        2'b01 :  decoded_winner[3:0] = 4'b0010;
        2'b10 :  decoded_winner[3:0] = 4'b0100;
        2'b11 :  decoded_winner[3:0] = 4'b1000;
      endcase


      if ( winner_valid_q )
        current_winner[3:0] =  decoded_winner[3:0];
      else
        current_winner[3:0] =  4'b0;

    end





  assign  new_winner_gt[3] =  current_winner[3] && ~req_bus_2pending[3];
  assign  new_winner_gt[2] =  current_winner[2] && ~req_bus_2pending[2];
  assign  new_winner_gt[1] =  current_winner[1] && ~req_bus_2pending[1];
  assign  new_winner_gt[0] =  current_winner[0] && ~req_bus_2pending[0];



  assign  new_winner[0] =  ( req_bus[0] && ~new_winner_gt[0] &&
                          (( decoded_winner[0] && ~req_bus[3] && ~req_bus[2] && ~req_bus[1] ) ||
                           ( decoded_winner[1] && ~req_bus[3] && ~req_bus[2]                ) ||
                           ( decoded_winner[2] && ~req_bus[3]                               ) ||
                           ( decoded_winner[3]                                              )));

  assign  new_winner[1] =  ( req_bus[1] && ~new_winner_gt[1] &&
                          (( decoded_winner[0]                                              ) ||
                           ( decoded_winner[1] && ~req_bus[3] && ~req_bus[2] && ~req_bus[0] ) ||
                           ( decoded_winner[2] && ~req_bus[3]                && ~req_bus[0] ) ||
                           ( decoded_winner[3]                               && ~req_bus[0] )));
                                                            
  assign  new_winner[2] =  ( req_bus[2] && ~new_winner_gt[2] &&
                          (( decoded_winner[0]                && ~req_bus[1]                ) ||
                           ( decoded_winner[1]                                              ) ||
                           ( decoded_winner[2] && ~req_bus[3] && ~req_bus[1] && ~req_bus[0] ) ||
                           ( decoded_winner[3]                && ~req_bus[1] && ~req_bus[0] )));

  assign  new_winner[3] =  ( req_bus[3] && ~new_winner_gt[3] &&
                          (( decoded_winner[0] && ~req_bus[2] && ~req_bus[1]                ) ||
                           ( decoded_winner[1] && ~req_bus[2]                               ) ||
                           ( decoded_winner[2]                                              ) ||
                           ( decoded_winner[3] && ~req_bus[2] && ~req_bus[1] && ~req_bus[0] )));



  always @*
    begin
      new_winner_encoded[1:0] = 2'b00;
      if ( new_winner[3] )  new_winner_encoded[1:0] = 2'b11;
      if ( new_winner[2] )  new_winner_encoded[1:0] = 2'b10;
      if ( new_winner[1] )  new_winner_encoded[1:0] = 2'b01;
      if ( new_winner[0] )  new_winner_encoded[1:0] = 2'b00;
    end

  assign  any_new_winner =  ( new_winner[3:0] != 4'b0 );





  assign  pick_new_winner =  ( req_taken || ~winner_valid_q || ( | ( current_winner[3:0] & ~req_bus[3:0] )));



  assign  winner_valid_d =  (( any_new_winner || ( winner_valid_q && ~pick_new_winner )) && ~reset );



  always @*
    begin
      if ( reset )
        winner_d[1:0] =  2'b11;
      else if ( pick_new_winner )
        winner_d[1:0] =  new_winner_encoded[1:0];
      else
        winner_d[1:0] =  winner_q[1:0];
    end



  always @*
    begin
      if ( req_taken )
        req_clear[3:0] =  current_winner[3:0];
      else
        req_clear[3:0] =  4'b0;
    end



  assign  winner_valid =  winner_valid_q;
  assign  winner[1:0]  =  winner_q[1:0];






  always @ ( posedge clock )
    begin
      winner_q[1:0]     <= winner_d[1:0];
      winner_valid_q    <= winner_valid_d;               
    end

endmodule
module mcp3_arb004 (


    input                 clock
  , input                 reset


  , input                 req_taken
  , input           [3:0] req_bus
  , input           [3:0] req_bus_2pending


  , output                winner_valid
  , output          [1:0] winner
  , output reg      [3:0] req_clear

  );


  reg       [3:0] decoded_winner;
  reg       [3:0] current_winner;
  wire      [3:0] new_winner_gt;
  wire            pick_new_winner;                                                                                                 
  wire      [3:0] new_winner;
  reg       [1:0] new_winner_encoded;                                                                                              
  wire            any_new_winner;                                                                                                  

  reg       [1:0] winner_d;                                                                                                        
  reg       [1:0] winner_q;
  wire            winner_valid_d;                                                                                                          
  reg             winner_valid_q;                                                                                                          


  always @*
    begin

      case ( winner_q[1:0] )
        2'b00 :  decoded_winner[3:0] = 4'b0001;
        2'b01 :  decoded_winner[3:0] = 4'b0010;
        2'b10 :  decoded_winner[3:0] = 4'b0100;
        2'b11 :  decoded_winner[3:0] = 4'b1000;
      endcase


      if ( winner_valid_q )
        current_winner[3:0] =  decoded_winner[3:0];
      else
        current_winner[3:0] =  4'b0;

    end





  assign  new_winner_gt[3] =  current_winner[3] && ~req_bus_2pending[3];
  assign  new_winner_gt[2] =  current_winner[2] && ~req_bus_2pending[2];
  assign  new_winner_gt[1] =  current_winner[1] && ~req_bus_2pending[1];
  assign  new_winner_gt[0] =  current_winner[0] && ~req_bus_2pending[0];



  assign  new_winner[0] =  ( req_bus[0] && ~new_winner_gt[0] &&
                          (( decoded_winner[0] && ~req_bus[3] && ~req_bus[2] && ~req_bus[1] ) ||
                           ( decoded_winner[1] && ~req_bus[3] && ~req_bus[2]                ) ||
                           ( decoded_winner[2] && ~req_bus[3]                               ) ||
                           ( decoded_winner[3]                                              )));

  assign  new_winner[1] =  ( req_bus[1] && ~new_winner_gt[1] &&
                          (( decoded_winner[0]                                              ) ||
                           ( decoded_winner[1] && ~req_bus[3] && ~req_bus[2] && ~req_bus[0] ) ||
                           ( decoded_winner[2] && ~req_bus[3]                && ~req_bus[0] ) ||
                           ( decoded_winner[3]                               && ~req_bus[0] )));
                                                            
  assign  new_winner[2] =  ( req_bus[2] && ~new_winner_gt[2] &&
                          (( decoded_winner[0]                && ~req_bus[1]                ) ||
                           ( decoded_winner[1]                                              ) ||
                           ( decoded_winner[2] && ~req_bus[3] && ~req_bus[1] && ~req_bus[0] ) ||
                           ( decoded_winner[3]                && ~req_bus[1] && ~req_bus[0] )));

  assign  new_winner[3] =  ( req_bus[3] && ~new_winner_gt[3] &&
                          (( decoded_winner[0] && ~req_bus[2] && ~req_bus[1]                ) ||
                           ( decoded_winner[1] && ~req_bus[2]                               ) ||
                           ( decoded_winner[2]                                              ) ||
                           ( decoded_winner[3] && ~req_bus[2] && ~req_bus[1] && ~req_bus[0] )));



  always @*
    begin
      new_winner_encoded[1:0] = 2'b00;
      if ( new_winner[3] )  new_winner_encoded[1:0] = 2'b11;
      if ( new_winner[2] )  new_winner_encoded[1:0] = 2'b10;
      if ( new_winner[1] )  new_winner_encoded[1:0] = 2'b01;
      if ( new_winner[0] )  new_winner_encoded[1:0] = 2'b00;
    end

  assign  any_new_winner =  ( new_winner[3:0] != 4'b0 );





  assign  pick_new_winner =  ( req_taken || ~winner_valid_q || ( | ( current_winner[3:0] & ~req_bus[3:0] )));



  assign  winner_valid_d =  (( any_new_winner || ( winner_valid_q && ~pick_new_winner )) && ~reset );



  always @*
    begin
      if ( reset )
        winner_d[1:0] =  2'b11;
      else if ( pick_new_winner )
        winner_d[1:0] =  new_winner_encoded[1:0];
      else
        winner_d[1:0] =  winner_q[1:0];
    end



  always @*
    begin
      if ( req_taken )
        req_clear[3:0] =  current_winner[3:0];
      else
        req_clear[3:0] =  4'b0;
    end



  assign  winner_valid =  winner_valid_q;
  assign  winner[1:0]  =  winner_q[1:0];






  always @ ( posedge clock )
    begin
      winner_q[1:0]     <= winner_d[1:0];
      winner_valid_q    <= winner_valid_d;               
    end

endmodule