data/full_repos/permissive/205055389/test/verga/adder3.v
1: b'%Error: data/full_repos/permissive/205055389/test/verga/adder3.v:11: Unsupported or unknown PLI call: $monitor\n $monitor("%d: %h = %h + %h + %h",$time,{co,s},a,b,ci);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/adder3.v:13: Unsupported: Ignoring delay on this delayed statement.\n #2 a = 4\'b0; b = 4\'b0; ci = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/adder3.v:14: Unsupported: Ignoring delay on this delayed statement.\n #2 a = 4\'h2; b = 4\'h7; ci = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/adder3.v:15: Unsupported: Ignoring delay on this delayed statement.\n #2 a = 4\'h2; b = 4\'h7; ci = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/adder3.v:16: Unsupported: Ignoring delay on this delayed statement.\n #2 a = 4\'h9; b = 4\'h3; ci = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/adder3.v:17: Unsupported: Ignoring delay on this delayed statement.\n #2 a = 4\'hf; b = 4\'h3; ci = 1\'b0;\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder(s,co,a,b,ci);
  output [3:0] s;
  output co;
  input [3:0] a,b;
  input ci;
  wire [2:0] c;
  wire [3:0] x1,w1,w2,w3;

  xor g1[3:0] (x1,a,b);
  xor g1[3:0] (s,x1,{c[2:0],ci});

  and g1[3:0] (w1,a,b);
  and g1[3:0] (w2,a,{c[2:0],ci});
  and g1[3:0] (w3,b,{c[2:0],ci});

  or  g1[3:0] ({co,c}, w1, w2, w3);

endmodule
module adder(s,co,a,b,ci);

  output [3:0] s;
  output co;
  input [3:0] a,b;
  input ci;
  wire [2:0] c;
  wire [3:0] x1,w1,w2,w3;

  xor g1[3:0] (x1,a,b);
  xor g1[3:0] (s,x1,{c[2:0],ci});

  and g1[3:0] (w1,a,b);
  and g1[3:0] (w2,a,{c[2:0],ci});
  and g1[3:0] (w3,b,{c[2:0],ci});

  or  g1[3:0] ({co,c}, w1, w2, w3);

endmodule