data/full_repos/permissive/113002755/verilog/Letter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Letter.v:51: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n                                                                        : ... In instance Letter\nassign col = iVGA_X - iPosX;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Letter.v:53: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n                                                                        : ... In instance Letter\nassign row = iVGA_Y - iPosY;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/113002755/verilog/Letter.v:56: Operator ADD expects 32 or 7 bits on the RHS, but RHS\'s VARREF \'row\' generates 4 bits.\n                                                                        : ... In instance Letter\nassign dAddr = (iLetter * 16) + row;\n                              ^\n%Error: data/full_repos/permissive/113002755/verilog/Letter.v:71: Cannot find file containing module: \'letter_bitmap\'\nletter_bitmap map(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/letter_bitmap\n             data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/letter_bitmap.v\n             data/full_repos/permissive/113002755/verilog,data/full_repos/permissive/113002755/letter_bitmap.sv\n             letter_bitmap\n             letter_bitmap.v\n             letter_bitmap.sv\n             obj_dir/letter_bitmap\n             obj_dir/letter_bitmap.v\n             obj_dir/letter_bitmap.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module Letter (
	iClk,

	iPosX,
	iPosY,

	iVGA_X,
	iVGA_Y,

	iLetter,

	oDrawLet,

	iBlank
);


input iClk;
input [10:0]	iPosX;
input [10:0]	iPosY;
input [10:0]	iVGA_X;
input [10:0]	iVGA_Y;
input 			iBlank;
input [3:0]		iLetter;


output oDrawLet;
wire oDrawLet;


wire [15:0] rowBits;
wire [3:0] col;
wire [3:0] row;
wire [6:0] dAddr;
wire inPosition;
wire drawNum;


assign col = iVGA_X - iPosX;

assign row = iVGA_Y - iPosY;


assign dAddr = (iLetter * 16) + row;



assign inPosition = ((iVGA_X - iPosX)) < 16 && ((iVGA_Y - iPosY) < 16);


assign drawNum = inPosition && iBlank;


assign oDrawLet = (drawNum) ? rowBits[15-col] : 0 ;




letter_bitmap map(
	.address(dAddr),
	.clock(iClk),
	.q(rowBits)
);



endmodule
module Letter (
	iClk,

	iPosX,
	iPosY,

	iVGA_X,
	iVGA_Y,

	iLetter,

	oDrawLet,

	iBlank
);



input iClk;
input [10:0]	iPosX;
input [10:0]	iPosY;
input [10:0]	iVGA_X;
input [10:0]	iVGA_Y;
input 			iBlank;
input [3:0]		iLetter;


output oDrawLet;
wire oDrawLet;


wire [15:0] rowBits;
wire [3:0] col;
wire [3:0] row;
wire [6:0] dAddr;
wire inPosition;
wire drawNum;


assign col = iVGA_X - iPosX;

assign row = iVGA_Y - iPosY;


assign dAddr = (iLetter * 16) + row;



assign inPosition = ((iVGA_X - iPosX)) < 16 && ((iVGA_Y - iPosY) < 16);


assign drawNum = inPosition && iBlank;


assign oDrawLet = (drawNum) ? rowBits[15-col] : 0 ;




letter_bitmap map(
	.address(dAddr),
	.clock(iClk),
	.q(rowBits)
);



endmodule