data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps/testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk = ~clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n #20 resetest = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 {left, right, reset, y_exp} = vector[i];\n ^\n%Error: data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps/testbench.v:11: Cannot find file containing module: \'ford_thunderbird\'\n   ford_thunderbird uut(reset, left, right, clk, y);\n   ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps,data/full_repos/permissive/116563702/ford_thunderbird\n             data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps,data/full_repos/permissive/116563702/ford_thunderbird.v\n             data/full_repos/permissive/116563702/fsm/ford_thunderbird_tail_lamps,data/full_repos/permissive/116563702/ford_thunderbird.sv\n             ford_thunderbird\n             ford_thunderbird.v\n             ford_thunderbird.sv\n             obj_dir/ford_thunderbird\n             obj_dir/ford_thunderbird.v\n             obj_dir/ford_thunderbird.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
   reg left, right, resetest, reset, clk;
   reg [5:0] y_exp;
   wire [5:0] y;

   reg [10:0] i, error;
   reg [8:0]  vector[100:1];

   ford_thunderbird uut(reset, left, right, clk, y);

   always begin
      #5 clk = ~clk;
   end

   initial
     begin
	clk = 0;
	i = 1;
	error = 0;
	$readmemb("/media/nipun/789CB1599CB1131C/Nipun Pruthi/Study/IITR/vivado/files/understanding/fsm/ford_thunderbird_tail_lamps/test_data.tv",vector);
	resetest = 1;
	#20 resetest = 0;
     end

   always @(negedge clk)
     begin
	#2 {left, right, reset, y_exp} = vector[i];
     end

   always @(negedge clk)
     begin
	if(~resetest)
	  begin
	     if (y_exp !== y)
	       begin
		  $display ("Error : input = %b",{left, right, reset});
		  $display ("Output : %b ( %b expected)",y, y_exp);
		  error = error + 1;
	       end
	     else
	       begin
                  $display("Passed : Input = %b", {left,right,reset});
	          $display("Output : %b (%b expected)",y, y_exp);
	       end
	i = i + 1;
	if (vector[i] === 9'bx)
	  begin
	     $display("%d test complete with %d errors", i-1, error);
	     $finish;
	  end
	  end
     end
endmodule
module testbench;

   reg left, right, resetest, reset, clk;
   reg [5:0] y_exp;
   wire [5:0] y;

   reg [10:0] i, error;
   reg [8:0]  vector[100:1];

   ford_thunderbird uut(reset, left, right, clk, y);

   always begin
      #5 clk = ~clk;
   end

   initial
     begin
	clk = 0;
	i = 1;
	error = 0;
	$readmemb("/media/nipun/789CB1599CB1131C/Nipun Pruthi/Study/IITR/vivado/files/understanding/fsm/ford_thunderbird_tail_lamps/test_data.tv",vector);
	resetest = 1;
	#20 resetest = 0;
     end

   always @(negedge clk)
     begin
	#2 {left, right, reset, y_exp} = vector[i];
     end

   always @(negedge clk)
     begin
	if(~resetest)
	  begin
	     if (y_exp !== y)
	       begin
		  $display ("Error : input = %b",{left, right, reset});
		  $display ("Output : %b ( %b expected)",y, y_exp);
		  error = error + 1;
	       end
	     else
	       begin
                  $display("Passed : Input = %b", {left,right,reset});
	          $display("Output : %b (%b expected)",y, y_exp);
	       end
	i = i + 1;
	if (vector[i] === 9'bx)
	  begin
	     $display("%d test complete with %d errors", i-1, error);
	     $finish;
	  end
	  end
     end
endmodule