data/full_repos/permissive/206842334/src/addr_generator.v
1: b'%Error: data/full_repos/permissive/206842334/src/addr_generator.v:1: Cannot find include file: parameters.v\n`include "parameters.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/206842334/src,data/full_repos/permissive/206842334/parameters.v\n             data/full_repos/permissive/206842334/src,data/full_repos/permissive/206842334/parameters.v.v\n             data/full_repos/permissive/206842334/src,data/full_repos/permissive/206842334/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:20: Define or directive not defined: \'`BYTE\'\n    parameter [`BYTE-1:0] CONV_DIM_IMG    = 32;\n               ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:21: Define or directive not defined: \'`BYTE\'\n parameter [`BYTE-1:0] CONV_DIM_KERNEL = 5;\n            ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:22: Define or directive not defined: \'`BYTE\'\n parameter [`BYTE-1:0] CONV_DIM_CH     = 3;\n            ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:23: Define or directive not defined: \'`BYTE\'\n    parameter [`BYTE-1:0] CONV_OUT_CH     = 32;\n               ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:24: Define or directive not defined: \'`BYTE\'\n    parameter [`BYTE-1:0] CONV_DIM_OUT    = 32;\n               ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:25: Define or directive not defined: \'`BYTE\'\n    parameter [`BYTE-1:0] STRIDE          = 1;\n               ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:26: Define or directive not defined: \'`BYTE\'\n    parameter [`BYTE-1:0] PADDING         = 2;\n               ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:27: Define or directive not defined: \'`BYTE\'\n    parameter [`BYTE-1:0] KSIZE           = 4;\n               ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:33: Define or directive not defined: \'`BYTE\'\n    input [`BYTE-1:0] i;\n           ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:34: Define or directive not defined: \'`BYTE\'\n    input [`BYTE-1:0] j;\n           ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:35: Define or directive not defined: \'`BYTE\'\n    input [`BYTE-1:0] k;\n           ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:36: Define or directive not defined: \'`BYTE\'\n    input [`BYTE-1:0] m;\n           ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:37: Define or directive not defined: \'`BYTE\'\n    input [`BYTE-1:0] n;\n           ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:38: Define or directive not defined: \'`BYTE\'\n    input [`BYTE-1:0] l;\n           ^~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:39: Define or directive not defined: \'`HALF_WORD\'\n    output reg [`HALF_WORD-1:0] s_addr;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:40: Define or directive not defined: \'`HALF_WORD\'\n    output reg [`HALF_WORD-1:0] w_addr;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:41: Define or directive not defined: \'`HALF_WORD\'\n    output reg [`HALF_WORD-1:0] save_addr;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/206842334/src/addr_generator.v:42: Define or directive not defined: \'`HALF_WORD\'\n    output reg [`HALF_WORD-1:0] b_addr;\n                ^~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n'
module addr_generator(
    clk,
    reset,
    enable,
    en_save,
    i,
    j,
    k,
    l,
    m,
    n,
    s_addr,
    w_addr,
    b_addr,
    save_addr
);

    parameter [`BYTE-1:0] CONV_DIM_IMG    = 32;
	parameter [`BYTE-1:0] CONV_DIM_KERNEL = 5;
	parameter [`BYTE-1:0] CONV_DIM_CH     = 3;
    parameter [`BYTE-1:0] CONV_OUT_CH     = 32;
    parameter [`BYTE-1:0] CONV_DIM_OUT    = 32;
    parameter [`BYTE-1:0] STRIDE          = 1;
    parameter [`BYTE-1:0] PADDING         = 2;
    parameter [`BYTE-1:0] KSIZE           = 4;

    input clk;
    input reset;
    input enable;
    input en_save;
    input [`BYTE-1:0] i;
    input [`BYTE-1:0] j;
    input [`BYTE-1:0] k;
    input [`BYTE-1:0] m;
    input [`BYTE-1:0] n;
    input [`BYTE-1:0] l;
    output reg [`HALF_WORD-1:0] s_addr;
    output reg [`HALF_WORD-1:0] w_addr;
    output reg [`HALF_WORD-1:0] save_addr;
    output reg [`HALF_WORD-1:0] b_addr;

    always @(posedge clk) begin
        if(reset) begin
            s_addr <= 0;
            w_addr <= 0;
            b_addr <= 0;
        end else if(enable) begin
            s_addr <= (((((STRIDE * j) + m - PADDING) * CONV_DIM_IMG) + ((STRIDE * k) + n - PADDING)) * CONV_DIM_CH) + l;
            w_addr <= (i * CONV_DIM_CH * CONV_DIM_KERNEL * CONV_DIM_KERNEL) + (((m * CONV_DIM_KERNEL) + (n)) * CONV_DIM_CH) + l;
            b_addr <= i;
        end
    end

    reg [7:0] i_r, j_r, k_r;
    reg [7:0] i_r1, j_r1, k_r1;

    always @(posedge clk) begin
        if (reset) begin
            i_r <= 0;
            j_r <= 0;
            k_r <= 0;
            i_r1 <= 0;
            j_r1 <= 0;
            k_r1 <= 0;
        end else begin
            i_r  <= i;
            i_r1 <= i_r;
            j_r <= j;
            j_r1 <= j_r;
            k_r <= k;
            k_r1 <= k_r;
        end
    end

    always @(posedge clk) begin
        if (reset) begin
            save_addr <= 0;
        end else if(en_save) begin
            if (j == 0 && k == 0) begin
                save_addr <= i_r1 + (((j_r1 * CONV_DIM_OUT) + (k_r1)) * CONV_OUT_CH);
            end else begin
                save_addr <= i + (((j * CONV_DIM_OUT) + (k[KSIZE:0]-1'b1)) * CONV_OUT_CH);
            end
        end
    end
endmodule
module addr_generator(
    clk,
    reset,
    enable,
    en_save,
    i,
    j,
    k,
    l,
    m,
    n,
    s_addr,
    w_addr,
    b_addr,
    save_addr
);


    parameter [`BYTE-1:0] CONV_DIM_IMG    = 32;
	parameter [`BYTE-1:0] CONV_DIM_KERNEL = 5;
	parameter [`BYTE-1:0] CONV_DIM_CH     = 3;
    parameter [`BYTE-1:0] CONV_OUT_CH     = 32;
    parameter [`BYTE-1:0] CONV_DIM_OUT    = 32;
    parameter [`BYTE-1:0] STRIDE          = 1;
    parameter [`BYTE-1:0] PADDING         = 2;
    parameter [`BYTE-1:0] KSIZE           = 4;

    input clk;
    input reset;
    input enable;
    input en_save;
    input [`BYTE-1:0] i;
    input [`BYTE-1:0] j;
    input [`BYTE-1:0] k;
    input [`BYTE-1:0] m;
    input [`BYTE-1:0] n;
    input [`BYTE-1:0] l;
    output reg [`HALF_WORD-1:0] s_addr;
    output reg [`HALF_WORD-1:0] w_addr;
    output reg [`HALF_WORD-1:0] save_addr;
    output reg [`HALF_WORD-1:0] b_addr;

    always @(posedge clk) begin
        if(reset) begin
            s_addr <= 0;
            w_addr <= 0;
            b_addr <= 0;
        end else if(enable) begin
            s_addr <= (((((STRIDE * j) + m - PADDING) * CONV_DIM_IMG) + ((STRIDE * k) + n - PADDING)) * CONV_DIM_CH) + l;
            w_addr <= (i * CONV_DIM_CH * CONV_DIM_KERNEL * CONV_DIM_KERNEL) + (((m * CONV_DIM_KERNEL) + (n)) * CONV_DIM_CH) + l;
            b_addr <= i;
        end
    end

    reg [7:0] i_r, j_r, k_r;
    reg [7:0] i_r1, j_r1, k_r1;

    always @(posedge clk) begin
        if (reset) begin
            i_r <= 0;
            j_r <= 0;
            k_r <= 0;
            i_r1 <= 0;
            j_r1 <= 0;
            k_r1 <= 0;
        end else begin
            i_r  <= i;
            i_r1 <= i_r;
            j_r <= j;
            j_r1 <= j_r;
            k_r <= k;
            k_r1 <= k_r;
        end
    end

    always @(posedge clk) begin
        if (reset) begin
            save_addr <= 0;
        end else if(en_save) begin
            if (j == 0 && k == 0) begin
                save_addr <= i_r1 + (((j_r1 * CONV_DIM_OUT) + (k_r1)) * CONV_OUT_CH);
            end else begin
                save_addr <= i + (((j * CONV_DIM_OUT) + (k[KSIZE:0]-1'b1)) * CONV_OUT_CH);
            end
        end
    end
endmodule