data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/EXSegReg.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/EXSegReg.v:50: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                                : ... In instance EXSegReg\n            RdE<=32\'b0;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/EXSegReg.v:56: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance EXSegReg\n            RegWriteE<=1\'b0;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/EXSegReg.v:58: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance EXSegReg\n            MemWriteE<=1\'b0;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/EXSegReg.v:70: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                                : ... In instance EXSegReg\n                RdE<=32\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/EXSegReg.v:76: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance EXSegReg\n                RegWriteE<=1\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/175780824/3_CacheLab/CPUSrcCode/Verilog/EXSegReg.v:78: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                : ... In instance EXSegReg\n                MemWriteE<=1\'b0;\n                         ^~\n%Error: Exiting due to 6 warning(s)\n'
module EXSegReg(
    input wire clk,
    input wire rst,
    input wire en,
    input wire clear,

    input wire [31:0] PCD,
    output reg [31:0] PCE, 
    input wire [31:0] BrPCD,
    output reg [31:0] BrPCE, 
    input wire [31:0] ImmD,
    output reg [31:0] ImmE,
    input wire [4:0] RdD,
    output reg [4:0] RdE,
    input wire [4:0] Rs1D,
    output reg [4:0] Rs1E,
    input wire [4:0] Rs2D,
    output reg [4:0] Rs2E,
    input wire [31:0] RegOut1D,
    output reg [31:0] RegOut1E,
    input wire [31:0] RegOut2D,
    output reg [31:0] RegOut2E,

    input wire JalrD,
    output reg JalrE,
    input wire [2:0] RegWriteD,
    output reg [2:0] RegWriteE,
    input wire MemToRegD,
    output reg MemToRegE,
    input wire [3:0] MemWriteD,
    output reg [3:0] MemWriteE,
    input wire LoadNpcD,
    output reg LoadNpcE,
    input wire [4:0] AluContrlD,
    output reg [4:0] AluContrlE,
    input wire AluSrc1D,
    output reg AluSrc1E,
    input wire [1:0] AluSrc2D,
    output reg [1:0] AluSrc2E
    );

    always@(posedge clk or posedge rst)
    begin
        if(rst)
            begin
            PCE<=32'b0; 
            BrPCE<=32'b0; 
            ImmE<=32'b0;
            RdE<=32'b0;
            Rs1E<=5'b0;
            Rs2E<=5'b0;
            RegOut1E<=32'b0;
            RegOut2E<=32'b0;
            JalrE<=1'b0;
            RegWriteE<=1'b0;
            MemToRegE<=1'b0;
            MemWriteE<=1'b0;
            LoadNpcE<=1'b0;
            AluContrlE<=5'b0;
            AluSrc1E<=1'b0; 
            AluSrc2E<=2'b0; 
            end
        else if(en)
            if(clear)
                begin
                PCE<=32'b0; 
                BrPCE<=32'b0; 
                ImmE<=32'b0;
                RdE<=32'b0;
                Rs1E<=5'b0;
                Rs2E<=5'b0;
                RegOut1E<=32'b0;
                RegOut2E<=32'b0;
                JalrE<=1'b0;
                RegWriteE<=1'b0;
                MemToRegE<=1'b0;
                MemWriteE<=1'b0;
                LoadNpcE<=1'b0;
                AluContrlE<=5'b0;
                AluSrc1E<=1'b0; 
                AluSrc2E<=2'b0;     
                end
            else
                begin
                PCE<=PCD; 
                BrPCE<=BrPCD; 
                ImmE<=ImmD;
                RdE<=RdD;
                Rs1E<=Rs1D;
                Rs2E<=Rs2D;
                RegOut1E<=RegOut1D;
                RegOut2E<=RegOut2D;
                JalrE<=JalrD;
                RegWriteE=RegWriteD;
                MemToRegE<=MemToRegD;
                MemWriteE<=MemWriteD;
                LoadNpcE<=LoadNpcD;
                AluContrlE<=AluContrlD;
                AluSrc1E<=AluSrc1D;
                AluSrc2E<=AluSrc2D;         
                end                
    end
    
endmodule
module EXSegReg(
    input wire clk,
    input wire rst,
    input wire en,
    input wire clear,

    input wire [31:0] PCD,
    output reg [31:0] PCE, 
    input wire [31:0] BrPCD,
    output reg [31:0] BrPCE, 
    input wire [31:0] ImmD,
    output reg [31:0] ImmE,
    input wire [4:0] RdD,
    output reg [4:0] RdE,
    input wire [4:0] Rs1D,
    output reg [4:0] Rs1E,
    input wire [4:0] Rs2D,
    output reg [4:0] Rs2E,
    input wire [31:0] RegOut1D,
    output reg [31:0] RegOut1E,
    input wire [31:0] RegOut2D,
    output reg [31:0] RegOut2E,

    input wire JalrD,
    output reg JalrE,
    input wire [2:0] RegWriteD,
    output reg [2:0] RegWriteE,
    input wire MemToRegD,
    output reg MemToRegE,
    input wire [3:0] MemWriteD,
    output reg [3:0] MemWriteE,
    input wire LoadNpcD,
    output reg LoadNpcE,
    input wire [4:0] AluContrlD,
    output reg [4:0] AluContrlE,
    input wire AluSrc1D,
    output reg AluSrc1E,
    input wire [1:0] AluSrc2D,
    output reg [1:0] AluSrc2E
    );


    always@(posedge clk or posedge rst)
    begin
        if(rst)
            begin
            PCE<=32'b0; 
            BrPCE<=32'b0; 
            ImmE<=32'b0;
            RdE<=32'b0;
            Rs1E<=5'b0;
            Rs2E<=5'b0;
            RegOut1E<=32'b0;
            RegOut2E<=32'b0;
            JalrE<=1'b0;
            RegWriteE<=1'b0;
            MemToRegE<=1'b0;
            MemWriteE<=1'b0;
            LoadNpcE<=1'b0;
            AluContrlE<=5'b0;
            AluSrc1E<=1'b0; 
            AluSrc2E<=2'b0; 
            end
        else if(en)
            if(clear)
                begin
                PCE<=32'b0; 
                BrPCE<=32'b0; 
                ImmE<=32'b0;
                RdE<=32'b0;
                Rs1E<=5'b0;
                Rs2E<=5'b0;
                RegOut1E<=32'b0;
                RegOut2E<=32'b0;
                JalrE<=1'b0;
                RegWriteE<=1'b0;
                MemToRegE<=1'b0;
                MemWriteE<=1'b0;
                LoadNpcE<=1'b0;
                AluContrlE<=5'b0;
                AluSrc1E<=1'b0; 
                AluSrc2E<=2'b0;     
                end
            else
                begin
                PCE<=PCD; 
                BrPCE<=BrPCD; 
                ImmE<=ImmD;
                RdE<=RdD;
                Rs1E<=Rs1D;
                Rs2E<=Rs2D;
                RegOut1E<=RegOut1D;
                RegOut2E<=RegOut2D;
                JalrE<=JalrD;
                RegWriteE=RegWriteD;
                MemToRegE<=MemToRegD;
                MemWriteE<=MemWriteD;
                LoadNpcE<=LoadNpcD;
                AluContrlE<=AluContrlD;
                AluSrc1E<=AluSrc1D;
                AluSrc2E<=AluSrc2D;         
                end                
    end
    
endmodule