data/full_repos/permissive/169526487/verilog-codes/sequence-detector-overlap.v
 line:45: before: "endmodule"
1: b'%Warning-STMTDLY: data/full_repos/permissive/169526487/verilog-codes/sequence-detector-overlap.v:40: Unsupported: Ignoring delay on this delayed statement.\n#10; next_state=D; end\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/169526487/verilog-codes/sequence-detector-overlap.v:45: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module melay_overlap(
input x,
input clk,rst, output reg y
);
reg [2:0] current_state,next_state;
parameter A=3'b000; parameter B=3'b001; parameter C=3'b010; parameter D=3'b011; parameter E=3'b100; always@(posedge clk)begin if(rst)begin
current_state=A;

end
else begin current_state=next_state; end
end
always@(current_state or x)begin case(current_state)
A: begin
if(x==1)begin y=0; next_state=B; end


else if(x==0)begin y=0;
next_state=A;
end end
B:begin
if(x==1)begin y=0; next_state=C; end
else if(x==0)begin y=0;
next_state=A;
end end
C:begin
if(x==1)begin y=0; next_state=D; end
else if (x==0) begin y=0;
next_state=A;
end end
D:begin
if(x==0)begin y=0; next_state=E; end
else if(x==1) begin y=0;
next_state=D;
end end
3'b100:begin
if(x==1)begin y=1;
#10; next_state=D; end
else if(x==0) begin y=0;
next_state=A;
end end endcase

endmodule
module melay_overlap(
input x,
input clk,rst, output reg y
);

reg [2:0] current_state,next_state;
parameter A=3'b000; parameter B=3'b001; parameter C=3'b010; parameter D=3'b011; parameter E=3'b100; always@(posedge clk)begin if(rst)begin
current_state=A;

end
else begin current_state=next_state; end
end
always@(current_state or x)begin case(current_state)
A: begin
if(x==1)begin y=0; next_state=B; end


else if(x==0)begin y=0;
next_state=A;
end end
B:begin
if(x==1)begin y=0; next_state=C; end
else if(x==0)begin y=0;
next_state=A;
end end
C:begin
if(x==1)begin y=0; next_state=D; end
else if (x==0) begin y=0;
next_state=A;
end end
D:begin
if(x==0)begin y=0; next_state=E; end
else if(x==1) begin y=0;
next_state=D;
end end
3'b100:begin
if(x==1)begin y=1;
#10; next_state=D; end
else if(x==0) begin y=0;
next_state=A;
end end endcase

endmodule