data/full_repos/permissive/143278/ivltests/assign_nb2.v
 line:40: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/assign_nb2.v:35: Unsupported: Ignoring delay on this delayed statement.\n   always #5 PCLK = !PCLK;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/assign_nb2.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #50 $display("done: x=%b", x);\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/assign_nb2.v:25: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h3f\' generates 6 bits.\n                                                                          : ... In instance main\n   reg [7:1] a  = 6\'b111111;\n                  ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/assign_nb2.v:26: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h2\' generates 6 bits.\n                                                                          : ... In instance main\n   reg [7:1] b = 6\'b000010;\n                 ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/assign_nb2.v:42: Operator NEQCASE expects 7 bits on the RHS, but RHS\'s CONST \'6\'h2\' generates 6 bits.\n                                                                          : ... In instance main\n      if (x !== 6\'b000010)\n            ^~~\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg [7:1] a  = 6'b111111;
   reg [7:1] b = 6'b000010;

   integer q;
   reg [7:1] x;
   reg	     PCLK = 1;
   always @(posedge PCLK)
     for (q=1; q<=7; q=q+1)
       x[q] <= #1 a[q] & b[q];

   always #5 PCLK = !PCLK;

   initial begin


      #50 $display("done: x=%b", x);

      if (x !== 6'b000010)
	$display("FAILED -- x = %b", x);
      else
	$display("PASSED");

      $finish;
   end


endmodule
module main;


   reg [7:1] a  = 6'b111111;
   reg [7:1] b = 6'b000010;

   integer q;
   reg [7:1] x;
   reg	     PCLK = 1;
   always @(posedge PCLK)
     for (q=1; q<=7; q=q+1)
       x[q] <= #1 a[q] & b[q];

   always #5 PCLK = !PCLK;

   initial begin


      #50 $display("done: x=%b", x);

      if (x !== 6'b000010)
	$display("FAILED -- x = %b", x);
      else
	$display("PASSED");

      $finish;
   end


endmodule