data/full_repos/permissive/118895561/Project 2/mdu.v
1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/118895561\n        ... Looked in:\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561.v\n             data/full_repos/permissive/118895561/Project/2,data/full_repos/permissive/118895561.sv\n             2,data/full_repos/permissive/118895561\n             2,data/full_repos/permissive/118895561.v\n             2,data/full_repos/permissive/118895561.sv\n             obj_dir/2,data/full_repos/permissive/118895561\n             obj_dir/2,data/full_repos/permissive/118895561.v\n             obj_dir/2,data/full_repos/permissive/118895561.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/118895561/Project\n%Error: Cannot find file containing module: 2/mdu.v\n%Error: Exiting due to 3 error(s)\n'
module mdu(
    input  [31:0] D1,
    input  [31:0] D2,
    input  HiLo,
    input  [1:0] Op,
    input  Start,
    input  WriteEnabled,	 
    output Busy,
	 input  madd,
    output   [31:0] HI,
    output   [31:0] LO,
    input clk,
    input rst,
	 input INT_REQ,
	 input [31:0] HI_M, LO_M
    );
	 
	 reg [63:0] temp1,temp2;
	 reg [63:0] temp;
	 
	 integer delay = 0;
	 
	 reg [31:0] MDu[1:0];
	 
	 initial begin 
		MDu[0]=0; 
		MDu[1]=0;
	 end
	 
	 assign Busy = (delay != 0 || Start);
	 always @(posedge clk) begin
		if(rst) begin
			MDu[0]=0; MDu[1]=0;
			delay=0;
			end
		else begin 
			if(INT_REQ) begin
				MDu[0] = HI_M;
				MDu[1] = LO_M;
				delay = 0;
			end
			else if(WriteEnabled) begin
				case(HiLo)
					1'b0 : MDu[0] = D1;
					1'b1 : MDu[1] = D1;
				endcase
				delay=1;
			end
			else if(Start)
				case (Op)
					2'b00 : 
					begin 
						{ MDu[0], MDu[1]} = D1*D2; delay=5; 
					end
					2'b01 : 
					begin 
						{ MDu[0], MDu[1]} = $signed(D1)*$signed(D2);  
						delay=5; 
					end
					2'b10 : 
					begin  
						if(D2==0) begin
							
						end
						else begin
							MDu[0] = D1%D2;  
							MDu[1]= D1/D2; 
							delay=10;  
						end
					end
					2'b11 : 
					begin  
					if(D2==0) begin
							
					end
					else begin
						MDu[0] = $signed(D1)%$signed(D2); 
						MDu[1] = $signed(D1)/$signed(D2); 
						delay=10; 
					end
					end
				endcase   
				if(madd) begin 
					temp1= $signed(D1)*$signed(D2);
					temp2={MDu[0], MDu[1]};
					temp=temp1+temp2;
					MDu[0] =temp[63:32];
					MDu[1] =temp[31:0];
											

											
					delay=5;
					end
				if(delay>0)
					delay = delay-1;						
				end
	 end
	 
	 assign HI=MDu[0];
	 assign LO=MDu[1];

endmodule
module mdu(
    input  [31:0] D1,
    input  [31:0] D2,
    input  HiLo,
    input  [1:0] Op,
    input  Start,
    input  WriteEnabled,	 
    output Busy,
	 input  madd,
    output   [31:0] HI,
    output   [31:0] LO,
    input clk,
    input rst,
	 input INT_REQ,
	 input [31:0] HI_M, LO_M
    );

	 
	 reg [63:0] temp1,temp2;
	 reg [63:0] temp;
	 
	 integer delay = 0;
	 
	 reg [31:0] MDu[1:0];
	 
	 initial begin 
		MDu[0]=0; 
		MDu[1]=0;
	 end
	 
	 assign Busy = (delay != 0 || Start);
	 always @(posedge clk) begin
		if(rst) begin
			MDu[0]=0; MDu[1]=0;
			delay=0;
			end
		else begin 
			if(INT_REQ) begin
				MDu[0] = HI_M;
				MDu[1] = LO_M;
				delay = 0;
			end
			else if(WriteEnabled) begin
				case(HiLo)
					1'b0 : MDu[0] = D1;
					1'b1 : MDu[1] = D1;
				endcase
				delay=1;
			end
			else if(Start)
				case (Op)
					2'b00 : 
					begin 
						{ MDu[0], MDu[1]} = D1*D2; delay=5; 
					end
					2'b01 : 
					begin 
						{ MDu[0], MDu[1]} = $signed(D1)*$signed(D2);  
						delay=5; 
					end
					2'b10 : 
					begin  
						if(D2==0) begin
							
						end
						else begin
							MDu[0] = D1%D2;  
							MDu[1]= D1/D2; 
							delay=10;  
						end
					end
					2'b11 : 
					begin  
					if(D2==0) begin
							
					end
					else begin
						MDu[0] = $signed(D1)%$signed(D2); 
						MDu[1] = $signed(D1)/$signed(D2); 
						delay=10; 
					end
					end
				endcase   
				if(madd) begin 
					temp1= $signed(D1)*$signed(D2);
					temp2={MDu[0], MDu[1]};
					temp=temp1+temp2;
					MDu[0] =temp[63:32];
					MDu[1] =temp[31:0];
											

											
					delay=5;
					end
				if(delay>0)
					delay = delay-1;						
				end
	 end
	 
	 assign HI=MDu[0];
	 assign LO=MDu[1];

endmodule