data/full_repos/permissive/114324064/src/cache_memory.v
1: b'%Error: data/full_repos/permissive/114324064/src/cache_memory.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.v\n             data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:22: Define or directive not defined: \'`DataAddrBus\'\n        input wire[`DataAddrBus]                ram_addr,\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        input wire[`DataAddrBus]                ram_addr,\n                               ^\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n        input wire[`DataBus]                    ram_data_i,\n        ^~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:24: Define or directive not defined: \'`DataBus\'\n        input wire[`DataBus]                    ram_data_i,\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:25: Define or directive not defined: \'`DataBus\'\n        output reg[`DataBus]                    ram_data_o\n                   ^~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:28: Define or directive not defined: \'`InstBus\'\n    reg[`InstBus] inst_mem[0:`InstMemNum-1];\n        ^~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`InstBus] inst_mem[0:`InstMemNum-1];\n                ^\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:28: Define or directive not defined: \'`InstMemNum\'\n    reg[`InstBus] inst_mem[0:`InstMemNum-1];\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:29: Define or directive not defined: \'`ByteWidth\'\n    reg[`ByteWidth]  data_mem0[0:`DataMemNum-1];  \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`ByteWidth]  data_mem0[0:`DataMemNum-1];  \n                  ^\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:29: Define or directive not defined: \'`DataMemNum\'\n    reg[`ByteWidth]  data_mem0[0:`DataMemNum-1];  \n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:30: Define or directive not defined: \'`ByteWidth\'\n    reg[`ByteWidth]  data_mem1[0:`DataMemNum-1];\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`ByteWidth]  data_mem1[0:`DataMemNum-1];\n                  ^\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:30: Define or directive not defined: \'`DataMemNum\'\n    reg[`ByteWidth]  data_mem1[0:`DataMemNum-1];\n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:31: Define or directive not defined: \'`ByteWidth\'\n    reg[`ByteWidth]  data_mem2[0:`DataMemNum-1];\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`ByteWidth]  data_mem2[0:`DataMemNum-1];\n                  ^\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:31: Define or directive not defined: \'`DataMemNum\'\n    reg[`ByteWidth]  data_mem2[0:`DataMemNum-1];\n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:32: Define or directive not defined: \'`ByteWidth\'\n    reg[`ByteWidth]  data_mem3[0:`DataMemNum-1];  \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`ByteWidth]  data_mem3[0:`DataMemNum-1];  \n                  ^\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:32: Define or directive not defined: \'`DataMemNum\'\n    reg[`ByteWidth]  data_mem3[0:`DataMemNum-1];  \n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:37: syntax error, unexpected initial\n    initial begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:39: Define or directive not defined: \'`InstMemNum\'\n        for (i = 0; i < `InstMemNum; i = i + 1) begin\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:66: Define or directive not defined: \'`ChipDisable\'\n        if (ram_ce == `ChipDisable) begin\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:68: Define or directive not defined: \'`WriteEnable\'\n        end else if(ram_we == `WriteEnable) begin\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:70: Define or directive not defined: \'`DataMemNumLog2\'\n                data_mem3[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[31:24];\n                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:76: Define or directive not defined: \'`DataMemNumLog2\'\n                data_mem2[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[23:16];\n                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:82: Define or directive not defined: \'`DataMemNumLog2\'\n                data_mem1[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[15:8];\n                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:88: Define or directive not defined: \'`DataMemNumLog2\'\n                data_mem0[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[7:0];\n                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:97: Define or directive not defined: \'`ChipDisable\'\n        if (ram_ce == `ChipDisable) begin\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:98: Define or directive not defined: \'`ZeroWord\'\n            ram_data_o <= `ZeroWord;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:99: Define or directive not defined: \'`WriteDisable\'\n        end else if(ram_we == `WriteDisable) begin\n                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:100: Define or directive not defined: \'`DataMemNumLog2\'\n            ram_data_o <= {data_mem3[ram_addr[`DataMemNumLog2+1:2]],\n                                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:101: Define or directive not defined: \'`DataMemNumLog2\'\n                           data_mem2[ram_addr[`DataMemNumLog2+1:2]],\n                                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:102: Define or directive not defined: \'`DataMemNumLog2\'\n                           data_mem1[ram_addr[`DataMemNumLog2+1:2]],\n                                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:103: Define or directive not defined: \'`DataMemNumLog2\'\n                           data_mem0[ram_addr[`DataMemNumLog2+1:2]]};\n                                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:105: Define or directive not defined: \'`ZeroWord\'\n            ram_data_o <= `ZeroWord;\n                          ^~~~~~~~~\n%Error: Exiting due to 37 error(s)\n'
module cache_memory
    #(
        parameter ADDR_WIDTH = 32,
        parameter SELECT_WIDTH = 4,
        parameter DATA_WIDTH = 32,
        parameter BENCH_WIDTH = DATA_WIDTH * (1 << (SELECT_WIDTH-2))
    )
    (
        input wire                              clk,


        input wire ic_read_i,
        input wire[ADDR_WIDTH-1:0] ic_addr_i,
        output reg[BENCH_WIDTH-1:0] ic_data_o,
        output reg ic_done_o,


        input wire                              ram_ce,
        input wire                              ram_we,
        input wire[`DataAddrBus]                ram_addr,
        input wire[3:0]                         ram_sel,
        input wire[`DataBus]                    ram_data_i,
        output reg[`DataBus]                    ram_data_o
    );

    reg[`InstBus] inst_mem[0:`InstMemNum-1];
    reg[`ByteWidth]  data_mem0[0:`DataMemNum-1];
    reg[`ByteWidth]  data_mem1[0:`DataMemNum-1];
    reg[`ByteWidth]  data_mem2[0:`DataMemNum-1];
    reg[`ByteWidth]  data_mem3[0:`DataMemNum-1];

    reg[3:0] cnt;
    
    integer i;
    initial begin
        $readmemh ("D:\\Users\\DELL\\Desktop\\inst_rom.data", inst_mem);
        for (i = 0; i < `InstMemNum; i = i + 1) begin
            data_mem3[i] <= inst_mem[i][7:0];
            data_mem2[i] <= inst_mem[i][15:8];
            data_mem1[i] <= inst_mem[i][23:16];
            data_mem0[i] <= inst_mem[i][31:24];
        end
        cnt <= 0;
    end
    
    always @ (posedge clk) begin
        cnt <= cnt + 1;
    end

    always @ (*) begin
        ic_data_o[31:0]   <= {data_mem3[(ic_addr_i>>2)+0], data_mem2[(ic_addr_i>>2)+0], data_mem1[(ic_addr_i>>2)+0], data_mem0[(ic_addr_i>>2)+0]}; 
        ic_data_o[63:32]  <= {data_mem3[(ic_addr_i>>2)+1], data_mem2[(ic_addr_i>>2)+1], data_mem1[(ic_addr_i>>2)+1], data_mem0[(ic_addr_i>>2)+1]};
        ic_data_o[95:64]  <= {data_mem3[(ic_addr_i>>2)+2], data_mem2[(ic_addr_i>>2)+2], data_mem1[(ic_addr_i>>2)+2], data_mem0[(ic_addr_i>>2)+2]};
        ic_data_o[127:96] <= {data_mem3[(ic_addr_i>>2)+3], data_mem2[(ic_addr_i>>2)+3], data_mem1[(ic_addr_i>>2)+3], data_mem0[(ic_addr_i>>2)+3]};
        if (cnt == 0) begin
            ic_done_o <= 1'b1;
            cnt <= cnt + 1;
        end else begin
            ic_done_o <= 1'b0;
        end
    end

    always @ (posedge clk) begin
        if (ram_ce == `ChipDisable) begin

        end else if(ram_we == `WriteEnable) begin
            if (ram_sel[3] == 1'b1) begin
                data_mem3[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[31:24];
                if (ram_addr == 32'h00000104) begin
  			       $write("%c", ram_data_i[31:24]);
      			end
            end
            if (ram_sel[2] == 1'b1) begin
                data_mem2[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[23:16];
                if (ram_addr == 32'h00000104) begin
  			       $write("%c", ram_data_i[23:16]);
      			end
            end
            if (ram_sel[1] == 1'b1) begin
                data_mem1[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[15:8];
                if (ram_addr == 32'h00000104) begin
  			       $write("%c", ram_data_i[15:8]);
      			end
            end
            if (ram_sel[0] == 1'b1) begin
                data_mem0[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[7:0];
                if (ram_addr == 32'h00000104) begin
  			       $write("%c", ram_data_i[7:0]);
      			end
            end
        end
    end

    always @ (*) begin
        if (ram_ce == `ChipDisable) begin
            ram_data_o <= `ZeroWord;
        end else if(ram_we == `WriteDisable) begin
            ram_data_o <= {data_mem3[ram_addr[`DataMemNumLog2+1:2]],
                           data_mem2[ram_addr[`DataMemNumLog2+1:2]],
                           data_mem1[ram_addr[`DataMemNumLog2+1:2]],
                           data_mem0[ram_addr[`DataMemNumLog2+1:2]]};
        end else begin
            ram_data_o <= `ZeroWord;
        end
    end

endmodule
module cache_memory
    #(
        parameter ADDR_WIDTH = 32,
        parameter SELECT_WIDTH = 4,
        parameter DATA_WIDTH = 32,
        parameter BENCH_WIDTH = DATA_WIDTH * (1 << (SELECT_WIDTH-2))
    )
    (
        input wire                              clk,


        input wire ic_read_i,
        input wire[ADDR_WIDTH-1:0] ic_addr_i,
        output reg[BENCH_WIDTH-1:0] ic_data_o,
        output reg ic_done_o,


        input wire                              ram_ce,
        input wire                              ram_we,
        input wire[`DataAddrBus]                ram_addr,
        input wire[3:0]                         ram_sel,
        input wire[`DataBus]                    ram_data_i,
        output reg[`DataBus]                    ram_data_o
    );


    reg[`InstBus] inst_mem[0:`InstMemNum-1];
    reg[`ByteWidth]  data_mem0[0:`DataMemNum-1];
    reg[`ByteWidth]  data_mem1[0:`DataMemNum-1];
    reg[`ByteWidth]  data_mem2[0:`DataMemNum-1];
    reg[`ByteWidth]  data_mem3[0:`DataMemNum-1];

    reg[3:0] cnt;
    
    integer i;
    initial begin
        $readmemh ("D:\\Users\\DELL\\Desktop\\inst_rom.data", inst_mem);
        for (i = 0; i < `InstMemNum; i = i + 1) begin
            data_mem3[i] <= inst_mem[i][7:0];
            data_mem2[i] <= inst_mem[i][15:8];
            data_mem1[i] <= inst_mem[i][23:16];
            data_mem0[i] <= inst_mem[i][31:24];
        end
        cnt <= 0;
    end
    
    always @ (posedge clk) begin
        cnt <= cnt + 1;
    end

    always @ (*) begin
        ic_data_o[31:0]   <= {data_mem3[(ic_addr_i>>2)+0], data_mem2[(ic_addr_i>>2)+0], data_mem1[(ic_addr_i>>2)+0], data_mem0[(ic_addr_i>>2)+0]}; 
        ic_data_o[63:32]  <= {data_mem3[(ic_addr_i>>2)+1], data_mem2[(ic_addr_i>>2)+1], data_mem1[(ic_addr_i>>2)+1], data_mem0[(ic_addr_i>>2)+1]};
        ic_data_o[95:64]  <= {data_mem3[(ic_addr_i>>2)+2], data_mem2[(ic_addr_i>>2)+2], data_mem1[(ic_addr_i>>2)+2], data_mem0[(ic_addr_i>>2)+2]};
        ic_data_o[127:96] <= {data_mem3[(ic_addr_i>>2)+3], data_mem2[(ic_addr_i>>2)+3], data_mem1[(ic_addr_i>>2)+3], data_mem0[(ic_addr_i>>2)+3]};
        if (cnt == 0) begin
            ic_done_o <= 1'b1;
            cnt <= cnt + 1;
        end else begin
            ic_done_o <= 1'b0;
        end
    end

    always @ (posedge clk) begin
        if (ram_ce == `ChipDisable) begin

        end else if(ram_we == `WriteEnable) begin
            if (ram_sel[3] == 1'b1) begin
                data_mem3[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[31:24];
                if (ram_addr == 32'h00000104) begin
  			       $write("%c", ram_data_i[31:24]);
      			end
            end
            if (ram_sel[2] == 1'b1) begin
                data_mem2[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[23:16];
                if (ram_addr == 32'h00000104) begin
  			       $write("%c", ram_data_i[23:16]);
      			end
            end
            if (ram_sel[1] == 1'b1) begin
                data_mem1[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[15:8];
                if (ram_addr == 32'h00000104) begin
  			       $write("%c", ram_data_i[15:8]);
      			end
            end
            if (ram_sel[0] == 1'b1) begin
                data_mem0[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[7:0];
                if (ram_addr == 32'h00000104) begin
  			       $write("%c", ram_data_i[7:0]);
      			end
            end
        end
    end

    always @ (*) begin
        if (ram_ce == `ChipDisable) begin
            ram_data_o <= `ZeroWord;
        end else if(ram_we == `WriteDisable) begin
            ram_data_o <= {data_mem3[ram_addr[`DataMemNumLog2+1:2]],
                           data_mem2[ram_addr[`DataMemNumLog2+1:2]],
                           data_mem1[ram_addr[`DataMemNumLog2+1:2]],
                           data_mem0[ram_addr[`DataMemNumLog2+1:2]]};
        end else begin
            ram_data_o <= `ZeroWord;
        end
    end

endmodule