data/full_repos/permissive/195227969/work/code/sb_sim_rtl/SB_DFFSR.v
data/verilator_xmls/6552e67e-1e23-4e8d-9457-53c7028c3183.xml
module SB_DFFSR
  ( input C,D,R,
    output reg Q
    );
   initial
     Q = 1'b0;
   always @(posedge C)
     Q <= R ? 1'b0 : D;
endmodule
module SB_DFFSR
  ( input C,D,R,
    output reg Q
    );

   initial
     Q = 1'b0;
   always @(posedge C)
     Q <= R ? 1'b0 : D;
endmodule