data/full_repos/permissive/168228981/edge_detect.v
data/verilator_xmls/0f94a02c-4d81-4cad-9731-c0dc1fcd3b40.xml
module edge_detect(clock, reset, in, edge_out);

input clock, reset, in;
output edge_out;
reg prev_in;
always @(posedge clock or posedge reset)
if (reset) prev_in = 0; 
else prev_in = in;
assign edge_out = in & !prev_in;

endmodule
module edge_detect(clock, reset, in, edge_out);


input clock, reset, in;
output edge_out;
reg prev_in;
always @(posedge clock or posedge reset)
if (reset) prev_in = 0; 
else prev_in = in;
assign edge_out = in & !prev_in;

endmodule