data/full_repos/permissive/188270170/verilog/sim/VGA_Sync_Pulses_TB.v
None: at end of input
1: b'%Error: data/full_repos/permissive/188270170/verilog/sim/VGA_Sync_Pulses_TB.v:2: Cannot find include file: VGA_Sync_Pulses.v\n`include "VGA_Sync_Pulses.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188270170/verilog/sim,data/full_repos/permissive/188270170/VGA_Sync_Pulses.v\n             data/full_repos/permissive/188270170/verilog/sim,data/full_repos/permissive/188270170/VGA_Sync_Pulses.v.v\n             data/full_repos/permissive/188270170/verilog/sim,data/full_repos/permissive/188270170/VGA_Sync_Pulses.v.sv\n             VGA_Sync_Pulses.v\n             VGA_Sync_Pulses.v.v\n             VGA_Sync_Pulses.v.sv\n             obj_dir/VGA_Sync_Pulses.v\n             obj_dir/VGA_Sync_Pulses.v.v\n             obj_dir/VGA_Sync_Pulses.v.sv\n%Error: data/full_repos/permissive/188270170/verilog/sim/VGA_Sync_Pulses_TB.v:3: Cannot find include file: Test_Pattern_Gen.v\n`include "Test_Pattern_Gen.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/188270170/verilog/sim/VGA_Sync_Pulses_TB.v:4: Cannot find include file: VGA_Sync_Porch.v\n`include "VGA_Sync_Porch.v" \n         ^~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/188270170/verilog/sim/VGA_Sync_Pulses_TB.v:20: Unsupported: Ignoring delay on this delayed statement.\n  always #20 r_Clk <= ~r_Clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/188270170/verilog/sim/VGA_Sync_Pulses_TB.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #5000;\n    ^\n%Error: data/full_repos/permissive/188270170/verilog/sim/VGA_Sync_Pulses_TB.v:60: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/188270170/verilog/sim/VGA_Sync_Pulses_TB.v:61: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0);\n    ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module VGA_TB;
  
  parameter c_VIDEO_WIDTH = 3;
  parameter c_TOTAL_COLS  = 10;
  parameter c_TOTAL_ROWS  = 6;
  parameter c_ACTIVE_COLS = 8;
  parameter c_ACTIVE_ROWS = 4;
  
  reg r_Clk = 1'b0;
  
  wire [c_VIDEO_WIDTH-1:0] w_Red_Video_TP;
  wire [c_VIDEO_WIDTH-1:0] w_Grn_Video_TP;
  wire [c_VIDEO_WIDTH-1:0] w_Blu_Video_TP;
    
  always #20 r_Clk <= ~r_Clk;
  

  VGA_Sync_Pulses #(.TOTAL_COLS(c_TOTAL_COLS),
                    .TOTAL_ROWS(c_TOTAL_ROWS),
                    .ACTIVE_COLS(c_ACTIVE_COLS),
                    .ACTIVE_ROWS(c_ACTIVE_ROWS)) VGA_Sync_Pulses_Inst 
  (.i_Clk(r_Clk),
   .o_HSync(w_HSync_Start),
   .o_VSync(w_VSync_Start),
   .o_Col_Count(),
   .o_Row_Count()
  );
  
  

  Test_Pattern_Gen  #(.VIDEO_WIDTH(c_VIDEO_WIDTH),
                      .TOTAL_COLS(c_TOTAL_COLS),
                      .TOTAL_ROWS(c_TOTAL_ROWS),
                      .ACTIVE_COLS(c_ACTIVE_COLS),
                      .ACTIVE_ROWS(c_ACTIVE_ROWS))
  Test_Pattern_Gen_Inst
   (.i_Clk(r_Clk),
    .i_Pattern(4'b0101),
    .i_HSync(w_HSync_Start),
    .i_VSync(w_VSync_Start),
    .o_HSync(w_HSync_TP),
    .o_VSync(w_VSync_TP),
    .o_Red_Video(w_Red_Video_TP),
    .o_Grn_Video(w_Grn_Video_TP),
    .o_Blu_Video(w_Blu_Video_TP));
  
  initial
  begin
    #5000;
    $finish();
  end
    
  initial 
  begin 
    $dumpfile("dump.vcd");
    $dumpvars(0);
  end
  
endmodule
module VGA_TB;

  
  parameter c_VIDEO_WIDTH = 3;
  parameter c_TOTAL_COLS  = 10;
  parameter c_TOTAL_ROWS  = 6;
  parameter c_ACTIVE_COLS = 8;
  parameter c_ACTIVE_ROWS = 4;
  
  reg r_Clk = 1'b0;
  
  wire [c_VIDEO_WIDTH-1:0] w_Red_Video_TP;
  wire [c_VIDEO_WIDTH-1:0] w_Grn_Video_TP;
  wire [c_VIDEO_WIDTH-1:0] w_Blu_Video_TP;
    
  always #20 r_Clk <= ~r_Clk;
  

  VGA_Sync_Pulses #(.TOTAL_COLS(c_TOTAL_COLS),
                    .TOTAL_ROWS(c_TOTAL_ROWS),
                    .ACTIVE_COLS(c_ACTIVE_COLS),
                    .ACTIVE_ROWS(c_ACTIVE_ROWS)) VGA_Sync_Pulses_Inst 
  (.i_Clk(r_Clk),
   .o_HSync(w_HSync_Start),
   .o_VSync(w_VSync_Start),
   .o_Col_Count(),
   .o_Row_Count()
  );
  
  

  Test_Pattern_Gen  #(.VIDEO_WIDTH(c_VIDEO_WIDTH),
                      .TOTAL_COLS(c_TOTAL_COLS),
                      .TOTAL_ROWS(c_TOTAL_ROWS),
                      .ACTIVE_COLS(c_ACTIVE_COLS),
                      .ACTIVE_ROWS(c_ACTIVE_ROWS))
  Test_Pattern_Gen_Inst
   (.i_Clk(r_Clk),
    .i_Pattern(4'b0101),
    .i_HSync(w_HSync_Start),
    .i_VSync(w_VSync_Start),
    .o_HSync(w_HSync_TP),
    .o_VSync(w_VSync_TP),
    .o_Red_Video(w_Red_Video_TP),
    .o_Grn_Video(w_Grn_Video_TP),
    .o_Blu_Video(w_Blu_Video_TP));
  
  initial
  begin
    #5000;
    $finish();
  end
    
  initial 
  begin 
    $dumpfile("dump.vcd");
    $dumpvars(0);
  end
  
endmodule