data/full_repos/permissive/209997170/6. time counter/work/planAhead/decimal selector/decimal selector.srcs/sources_1/imports/verilog/seven_seg_7.v
1: b'%Error: Cannot find file containing module: time\n        ... Looked in:\n             data/full_repos/permissive/209997170/6./time\n             data/full_repos/permissive/209997170/6./time.v\n             data/full_repos/permissive/209997170/6./time.sv\n             time\n             time.v\n             time.sv\n             obj_dir/time\n             obj_dir/time.v\n             obj_dir/time.sv\n%Error: Cannot find file containing module: counter/work/planAhead/decimal\n%Error: Cannot find file containing module: selector/decimal\n%Error: Cannot find file containing module: selector.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170\n%Error: Cannot find file containing module: data/full_repos/permissive/209997170/6.\n%Error: Cannot find file containing module: selector.srcs/sources_1/imports/verilog/seven_seg_7.v\n%Error: Exiting due to 6 error(s)\n'
module seven_seg_7 (
    input [3:0] char,
    output reg [6:0] segs
  );
  
  
  
  always @* begin
    
    case (char)
      1'h0: begin
        segs = 7'h3f;
      end
      1'h1: begin
        segs = 7'h06;
      end
      2'h2: begin
        segs = 7'h5b;
      end
      2'h3: begin
        segs = 7'h4f;
      end
      3'h4: begin
        segs = 7'h66;
      end
      3'h5: begin
        segs = 7'h6d;
      end
      3'h6: begin
        segs = 7'h7d;
      end
      3'h7: begin
        segs = 7'h07;
      end
      4'h8: begin
        segs = 7'h7f;
      end
      4'h9: begin
        segs = 7'h67;
      end
      default: begin
        segs = 7'h00;
      end
    endcase
  end
endmodule
module seven_seg_7 (
    input [3:0] char,
    output reg [6:0] segs
  );

  
  
  
  always @* begin
    
    case (char)
      1'h0: begin
        segs = 7'h3f;
      end
      1'h1: begin
        segs = 7'h06;
      end
      2'h2: begin
        segs = 7'h5b;
      end
      2'h3: begin
        segs = 7'h4f;
      end
      3'h4: begin
        segs = 7'h66;
      end
      3'h5: begin
        segs = 7'h6d;
      end
      3'h6: begin
        segs = 7'h7d;
      end
      3'h7: begin
        segs = 7'h07;
      end
      4'h8: begin
        segs = 7'h7f;
      end
      4'h9: begin
        segs = 7'h67;
      end
      default: begin
        segs = 7'h00;
      end
    endcase
  end
endmodule