data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v
1: b'%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:1: Cannot find include file: def.vh\n`include "def.vh" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.v\n             data/full_repos/permissive/111502990/cpu.srcs/sources_1/new,data/full_repos/permissive/111502990/def.vh.sv\n             def.vh\n             def.vh.v\n             def.vh.sv\n             obj_dir/def.vh\n             obj_dir/def.vh.v\n             obj_dir/def.vh.sv\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:6: Define or directive not defined: \'`ERRC_BITDEF\'\n input [`ERRC_BITDEF] in_errno,\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input [`ERRC_BITDEF] in_errno,\n                    ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:7: Define or directive not defined: \'`ERRC_BITDEF\'\n output [`ERRC_BITDEF] out_errno,\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:10: Define or directive not defined: \'`OPTYPE_BITDEF\'\n input [`OPTYPE_BITDEF] in_opt,\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:20: Define or directive not defined: \'`OPTYPE_BITDEF\'\n output [`OPTYPE_BITDEF] out_opt,\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:28: Define or directive not defined: \'`ERRC_BITDEF\'\n reg [`ERRC_BITDEF] Rerrno; assign out_errno = Rerrno;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`ERRC_BITDEF] Rerrno; assign out_errno = Rerrno;\n                  ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:29: syntax error, unexpected assign\n reg [31:0] Rnpc; assign out_npc = Rnpc;\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:30: syntax error, unexpected assign\n reg [5:0] Ropc; assign out_opc = Ropc;\n                 ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:31: Define or directive not defined: \'`OPTYPE_BITDEF\'\n reg [`OPTYPE_BITDEF] Ropt; assign out_opt = Ropt;\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`OPTYPE_BITDEF] Ropt; assign out_opt = Ropt;\n                    ^\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:32: syntax error, unexpected assign\n reg [31:0] Rrav; assign out_rav = Rrav;\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:33: syntax error, unexpected assign\n reg [31:0] Rrbv; assign out_rbv = Rrbv;\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:34: syntax error, unexpected assign\n reg [4:0] Rrout; assign out_rout = Rrout;\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:35: syntax error, unexpected assign\n reg [10:0] Raux; assign out_aux = Raux;\n                  ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:36: syntax error, unexpected assign\n reg [31:0] Rmem_read_addr; assign out_mem_read_addr = Rmem_read_addr;\n                            ^~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:40: Define or directive not defined: \'`PC_ILLEGAL\'\n   Rerrno <= 0; Rnpc <= `PC_ILLEGAL;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:47: Define or directive not defined: \'`OPCODE_LW\'\n   if (in_opc == `OPCODE_LW) begin\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:48: Define or directive not defined: \'`EXTSGN16to32\'\n    Rmem_read_addr <= in_rav + `EXTSGN16to32(in_imm); Rrav <= in_rav; Rrbv <= in_rbv;\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:49: Define or directive not defined: \'`OPCODE_SW\'\n   end else if (in_opc == `OPCODE_SW) begin\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:50: Define or directive not defined: \'`EXTSGN16to32\'\n    Rrbv <= in_rbv + `EXTSGN16to32(in_imm); Rrav <= in_rav; Rmem_read_addr <= 0;\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:51: Define or directive not defined: \'`OPTYPE_VJ\'\n   end else if (in_opt == `OPTYPE_VJ) begin\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:52: Define or directive not defined: \'`OPCODE_J\'\n    if (in_opc == `OPCODE_J) begin\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:58: Define or directive not defined: \'`OPCODE_BEQ\'\n      `OPCODE_BEQ: Rrav <= (in_rav == in_rbv);\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:59: Define or directive not defined: \'`OPCODE_BNE\'\n      `OPCODE_BNE: Rrav <= (in_rav != in_rbv);\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:60: Define or directive not defined: \'`OPCODE_BLT\'\n      `OPCODE_BLT: Rrav <= (in_rav < in_rbv);\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:61: Define or directive not defined: \'`OPCODE_BLE\'\n      `OPCODE_BLE: Rrav <= (in_rav <= in_rbv);\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:64: Define or directive not defined: \'`EXTSGN16to32\'\n     Rrbv <= in_npc + 4 + `EXTSGN16to32(in_imm); Rmem_read_addr <= 0;\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111502990/cpu.srcs/sources_1/new/decoder.v:66: Define or directive not defined: \'`OPCODE_JAL\'\n   end else if (in_opc == `OPCODE_JAL) begin\n                          ^~~~~~~~~~~\n%Error: Exiting due to 30 error(s)\n'
module decoder(
	input clk,
	input rst,
	input [`ERRC_BITDEF] in_errno,
	output [`ERRC_BITDEF] out_errno,
	input [31:0] in_npc,
	input [5:0] in_opc,
	input [`OPTYPE_BITDEF] in_opt,
	input [31:0] in_rav,
	input [31:0] in_rbv,
	input [4:0] in_rout,
	input [10:0] in_aux,
	input [15:0] in_imm,
	input [25:0] in_addr,
	input [31:0] in_mem_read_addr,
	output [31:0] out_npc,
	output [5:0] out_opc,
	output [`OPTYPE_BITDEF] out_opt,
	output [31:0] out_rav,
	output [31:0] out_rbv,
	output [4:0] out_rout,
	output [10:0] out_aux,
	output [31:0] out_mem_read_addr
	);

	reg [`ERRC_BITDEF] Rerrno; assign out_errno = Rerrno;
	reg [31:0] Rnpc; assign out_npc = Rnpc;
	reg [5:0] Ropc; assign out_opc = Ropc;
	reg [`OPTYPE_BITDEF] Ropt; assign out_opt = Ropt;
	reg [31:0] Rrav; assign out_rav = Rrav;
	reg [31:0] Rrbv; assign out_rbv = Rrbv;
	reg [4:0] Rrout; assign out_rout = Rrout;
	reg [10:0] Raux; assign out_aux = Raux;
	reg [31:0] Rmem_read_addr; assign out_mem_read_addr = Rmem_read_addr;

	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			Rerrno <= 0; Rnpc <= `PC_ILLEGAL;
			Ropc <= 0; Ropt <= 0; Rrav <= 0; Rrbv <= 0;
			Rrout <= 0; Raux <= 0; Rmem_read_addr <= 0;
		end else begin
			Rerrno <= in_errno; Rnpc <= in_npc;
			Ropc <= in_opc; Ropt <= in_opt;
			Rrout <= in_rout; Raux <= in_aux;
			if (in_opc == `OPCODE_LW) begin
				Rmem_read_addr <= in_rav + `EXTSGN16to32(in_imm); Rrav <= in_rav; Rrbv <= in_rbv;
			end else if (in_opc == `OPCODE_SW) begin
				Rrbv <= in_rbv + `EXTSGN16to32(in_imm); Rrav <= in_rav; Rmem_read_addr <= 0;
			end else if (in_opt == `OPTYPE_VJ) begin
				if (in_opc == `OPCODE_J) begin
					Rrav <= 1;
					Rrbv <= in_addr;
					Rmem_read_addr <= 0;
				end else begin
					case (in_opc)
						`OPCODE_BEQ: Rrav <= (in_rav == in_rbv);
						`OPCODE_BNE: Rrav <= (in_rav != in_rbv);
						`OPCODE_BLT: Rrav <= (in_rav < in_rbv);
						`OPCODE_BLE: Rrav <= (in_rav <= in_rbv);

					endcase
					Rrbv <= in_npc + 4 + `EXTSGN16to32(in_imm); Rmem_read_addr <= 0;
				end
			end else if (in_opc == `OPCODE_JAL) begin
				Rrav <= in_addr; Rrbv <= 0; Rmem_read_addr <= 0;
			end else begin
				Rmem_read_addr <= in_mem_read_addr; Rrav <= in_rav; Rrbv <= in_rbv;
			end
		end
	end
endmodule
module decoder(
	input clk,
	input rst,
	input [`ERRC_BITDEF] in_errno,
	output [`ERRC_BITDEF] out_errno,
	input [31:0] in_npc,
	input [5:0] in_opc,
	input [`OPTYPE_BITDEF] in_opt,
	input [31:0] in_rav,
	input [31:0] in_rbv,
	input [4:0] in_rout,
	input [10:0] in_aux,
	input [15:0] in_imm,
	input [25:0] in_addr,
	input [31:0] in_mem_read_addr,
	output [31:0] out_npc,
	output [5:0] out_opc,
	output [`OPTYPE_BITDEF] out_opt,
	output [31:0] out_rav,
	output [31:0] out_rbv,
	output [4:0] out_rout,
	output [10:0] out_aux,
	output [31:0] out_mem_read_addr
	);


	reg [`ERRC_BITDEF] Rerrno; assign out_errno = Rerrno;
	reg [31:0] Rnpc; assign out_npc = Rnpc;
	reg [5:0] Ropc; assign out_opc = Ropc;
	reg [`OPTYPE_BITDEF] Ropt; assign out_opt = Ropt;
	reg [31:0] Rrav; assign out_rav = Rrav;
	reg [31:0] Rrbv; assign out_rbv = Rrbv;
	reg [4:0] Rrout; assign out_rout = Rrout;
	reg [10:0] Raux; assign out_aux = Raux;
	reg [31:0] Rmem_read_addr; assign out_mem_read_addr = Rmem_read_addr;

	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			Rerrno <= 0; Rnpc <= `PC_ILLEGAL;
			Ropc <= 0; Ropt <= 0; Rrav <= 0; Rrbv <= 0;
			Rrout <= 0; Raux <= 0; Rmem_read_addr <= 0;
		end else begin
			Rerrno <= in_errno; Rnpc <= in_npc;
			Ropc <= in_opc; Ropt <= in_opt;
			Rrout <= in_rout; Raux <= in_aux;
			if (in_opc == `OPCODE_LW) begin
				Rmem_read_addr <= in_rav + `EXTSGN16to32(in_imm); Rrav <= in_rav; Rrbv <= in_rbv;
			end else if (in_opc == `OPCODE_SW) begin
				Rrbv <= in_rbv + `EXTSGN16to32(in_imm); Rrav <= in_rav; Rmem_read_addr <= 0;
			end else if (in_opt == `OPTYPE_VJ) begin
				if (in_opc == `OPCODE_J) begin
					Rrav <= 1;
					Rrbv <= in_addr;
					Rmem_read_addr <= 0;
				end else begin
					case (in_opc)
						`OPCODE_BEQ: Rrav <= (in_rav == in_rbv);
						`OPCODE_BNE: Rrav <= (in_rav != in_rbv);
						`OPCODE_BLT: Rrav <= (in_rav < in_rbv);
						`OPCODE_BLE: Rrav <= (in_rav <= in_rbv);

					endcase
					Rrbv <= in_npc + 4 + `EXTSGN16to32(in_imm); Rmem_read_addr <= 0;
				end
			end else if (in_opc == `OPCODE_JAL) begin
				Rrav <= in_addr; Rrbv <= 0; Rmem_read_addr <= 0;
			end else begin
				Rmem_read_addr <= in_mem_read_addr; Rrav <= in_rav; Rrbv <= in_rbv;
			end
		end
	end
endmodule