data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #50\n        ^\n%Error: data/full_repos/permissive/100975158/ProcessadorQuartus/TB_Controle.v:15: Cannot find file containing module: \'Controle\'\n    Controle teste_controle(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100975158/ProcessadorQuartus,data/full_repos/permissive/100975158/Controle\n             data/full_repos/permissive/100975158/ProcessadorQuartus,data/full_repos/permissive/100975158/Controle.v\n             data/full_repos/permissive/100975158/ProcessadorQuartus,data/full_repos/permissive/100975158/Controle.sv\n             Controle\n             Controle.v\n             Controle.sv\n             obj_dir/Controle\n             obj_dir/Controle.v\n             obj_dir/Controle.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_Controle ();

    reg[5:0] opcode;

    wire [1:0] c_ALUOp;
    wire c_fonte_ula;
    wire [2:0] c_desvio;
    wire [1:0] c_memoria;
    wire c_memtoreg;
    wire c_escrever_reg;
    wire c_reg_destino;


    Controle teste_controle(
		.opcode(opcode),
		.c_ALUOp(c_ALUOp),
		.c_fonte_ula(c_fonte_ula),
		.c_desvio(c_desvio),
		.c_memoria(c_memoria),
		.c_memtoreg(c_memtoreg),
		.c_escrever_reg(c_escrever_reg),
		.c_reg_destino(c_reg_destino)
	);

	initial begin
        opcode <= 6'b000000;
        #50
        opcode <= 6'b001000;
        #50
        opcode <= 6'b000011;
        #50
        opcode <= 6'b000010;
        #50
        opcode <= 6'b000101;
        #50
        opcode <= 6'b000100;
        #50
        opcode <= 6'b100011;
        #50
        opcode <= 6'b101011;
        #50
        opcode <= 6'b101011;
    end
endmodule
module TB_Controle ();


    reg[5:0] opcode;

    wire [1:0] c_ALUOp;
    wire c_fonte_ula;
    wire [2:0] c_desvio;
    wire [1:0] c_memoria;
    wire c_memtoreg;
    wire c_escrever_reg;
    wire c_reg_destino;


    Controle teste_controle(
		.opcode(opcode),
		.c_ALUOp(c_ALUOp),
		.c_fonte_ula(c_fonte_ula),
		.c_desvio(c_desvio),
		.c_memoria(c_memoria),
		.c_memtoreg(c_memtoreg),
		.c_escrever_reg(c_escrever_reg),
		.c_reg_destino(c_reg_destino)
	);

	initial begin
        opcode <= 6'b000000;
        #50
        opcode <= 6'b001000;
        #50
        opcode <= 6'b000011;
        #50
        opcode <= 6'b000010;
        #50
        opcode <= 6'b000101;
        #50
        opcode <= 6'b000100;
        #50
        opcode <= 6'b100011;
        #50
        opcode <= 6'b101011;
        #50
        opcode <= 6'b101011;
    end
endmodule