data/full_repos/permissive/143278/ivltests/pr2973532.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2973532.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pr2973532;

wire [15:0] a;
wire [7:0]  b;
wire [7:0]  c;

assign b[5:2] = 4'b1111;

assign c = 8'b00000000;

assign a = {b, c};

initial begin
  #1;
  $display("%b", a);
  if (a === 16'bzz1111zz00000000)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule
module pr2973532;


wire [15:0] a;
wire [7:0]  b;
wire [7:0]  c;

assign b[5:2] = 4'b1111;

assign c = 8'b00000000;

assign a = {b, c};

initial begin
  #1;
  $display("%b", a);
  if (a === 16'bzz1111zz00000000)
    $display("PASSED");
  else
    $display("FAILED");
end

endmodule