data/full_repos/permissive/205055389/test/verga/timing2.v
 line:5: before: "$"
1: b'%Error: data/full_repos/permissive/205055389/test/verga/timing2.v:10: Unsupported or unknown PLI call: $monitor\n    $monitor("%4d: ck=%b",$time,ck);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing2.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing2.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing2.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing2.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing2.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing2.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #80;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing2.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #90;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing2.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing2.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing2.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
   reg ck;

  specify
    $width(posedge ck, 30);
    $width(negedge ck, 25);
  endspecify

  initial
    $monitor("%4d: ck=%b",$time,ck);

  initial
    begin
        ck = 1'b1;
        #50;
	ck = 1'b0;
        $display("No violation expected at %d",$time);
        #50;

	ck = 1'b1;
        $display("No violation expected at %d",$time);
        #50;
	ck = 1'b0;
        $display("No violation expected at %d",$time);
        #50;

	ck = 1'b1;
        $display("No violation expected at %d",$time);
        #20;
	ck = 1'b0;
        $display("$width violation expected at %d on posedge",$time);
        #80;


	ck = 1'b1;
        $display("No violation expected at %d",$time);
        #90;
	ck = 1'b0;
        $display("No violation expected at %d",$time);
        #10;

	ck = 1'b1;
        $display("$width violation expected at %d on negedge",$time);
        #50;
	ck = 1'b0;
        $display("No violation expected at %d",$time);
        #50;

    end

endmodule
module top;

   reg ck;

  specify
    $width(posedge ck, 30);
    $width(negedge ck, 25);
  endspecify

  initial
    $monitor("%4d: ck=%b",$time,ck);

  initial
    begin
        ck = 1'b1;
        #50;
	ck = 1'b0;
        $display("No violation expected at %d",$time);
        #50;

	ck = 1'b1;
        $display("No violation expected at %d",$time);
        #50;
	ck = 1'b0;
        $display("No violation expected at %d",$time);
        #50;

	ck = 1'b1;
        $display("No violation expected at %d",$time);
        #20;
	ck = 1'b0;
        $display("$width violation expected at %d on posedge",$time);
        #80;


	ck = 1'b1;
        $display("No violation expected at %d",$time);
        #90;
	ck = 1'b0;
        $display("No violation expected at %d",$time);
        #10;

	ck = 1'b1;
        $display("$width violation expected at %d on negedge",$time);
        #50;
	ck = 1'b0;
        $display("No violation expected at %d",$time);
        #50;

    end

endmodule