data/full_repos/permissive/160976968/mc_adder.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/160976968/mc_adder.v:54: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6]disp;\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/160976968/mc_adder.v:28: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                  : ... In instance mc_adder.A\n assign {cout, O} = A + B + cin;\n                          ^\n%Warning-LITENDIAN: data/full_repos/permissive/160976968/mc_adder.v:3: Little bit endian vector: MSB < LSB of bit range: 0:6\n output [0:6]HEX0, HEX1, HEX3, HEX5;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/160976968/mc_adder.v:14: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 5 bits.\n                                                                  : ... In instance mc_adder\n  S0 = {Cout, O} - Z;\n     ^\n%Error: Exiting due to 4 warning(s)\n'
module mc_adder(SW, HEX0, HEX1, HEX3, HEX5);
	input [8:0]SW;
	output [0:6]HEX0, HEX1, HEX3, HEX5;
	wire Cout;
	wire[3:0] O;
	adder A(SW[3:0], SW[7:4], SW[8], Cout, O);
	wire[3:0] Z;
	wire C;
	greater_than_nine_if G({Cout, O}, Z, C);
	reg[3:0] S0;
	reg[3:0] S1;
	always @(Cout, O, Z, C)
	begin
		S0 = {Cout, O} - Z;
		S1 = {3'b000, C};
	end
	to_hex H1(S0, HEX0);
	to_hex H2(S1, HEX1);
	to_hex H3(SW[3:0], HEX3);
	to_hex H4(SW[7:4], HEX5);
endmodule
module mc_adder(SW, HEX0, HEX1, HEX3, HEX5);

	input [8:0]SW;
	output [0:6]HEX0, HEX1, HEX3, HEX5;
	wire Cout;
	wire[3:0] O;
	adder A(SW[3:0], SW[7:4], SW[8], Cout, O);
	wire[3:0] Z;
	wire C;
	greater_than_nine_if G({Cout, O}, Z, C);
	reg[3:0] S0;
	reg[3:0] S1;
	always @(Cout, O, Z, C)
	begin
		S0 = {Cout, O} - Z;
		S1 = {3'b000, C};
	end
	to_hex H1(S0, HEX0);
	to_hex H2(S1, HEX1);
	to_hex H3(SW[3:0], HEX3);
	to_hex H4(SW[7:4], HEX5);
endmodule