data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v
1: b'%Warning-WIDTH: data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v:147: Operator AND expects 32 bits on the LHS, but LHS\'s VARREF \'axi_awaddr\' generates 6 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n assign  aw_wrap_en = ((axi_awaddr & aw_wrap_size) == aw_wrap_size)? 1\'b1: 1\'b0;\n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v:148: Operator AND expects 32 bits on the LHS, but LHS\'s VARREF \'axi_araddr\' generates 6 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n assign  ar_wrap_en = ((axi_araddr & ar_wrap_size) == ar_wrap_size)? 1\'b1: 1\'b0;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v:282: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'axi_awaddr\' generates 6 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n                   axi_awaddr <= (axi_awaddr - aw_wrap_size); \n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v:282: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n                   axi_awaddr <= (axi_awaddr - aw_wrap_size); \n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v:291: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n                 axi_awaddr <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;\n                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v:473: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'axi_araddr\' generates 6 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n                   axi_araddr <= (axi_araddr - ar_wrap_size); \n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v:473: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n                   axi_araddr <= (axi_araddr - ar_wrap_size); \n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v:483: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n                 axi_araddr <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB]+1;\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v:601: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'axi_awaddr\' generates 6 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n          icb_cmd_addr = axi_awaddr;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v:658: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'axi_araddr\' generates 6 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n           icb_cmd_addr = axi_araddr;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v:727: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'axi_awaddr\' generates 6 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n         icb_cmd_addr_r <= axi_awaddr;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/214620165/rtl/fab/myip_v1_0_S00_AXI.v:738: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'axi_araddr\' generates 6 bits.\n                                                                                    : ... In instance myip_v1_0_S00_AXI\n         icb_cmd_addr_r <= axi_araddr;\n                        ^~\n%Error: Exiting due to 12 warning(s)\n'
module myip_v1_0_S00_AXI #
	(

		




		parameter integer C_S_AXI_ID_WIDTH	= 2,
		parameter integer C_S_AXI_DATA_WIDTH	= 32,
		parameter integer C_S_AXI_ADDR_WIDTH	= 6,
		parameter integer C_S_AXI_AWUSER_WIDTH	= 0,
		parameter integer C_S_AXI_ARUSER_WIDTH	= 0,
		parameter integer C_S_AXI_WUSER_WIDTH	= 0,
		parameter integer C_S_AXI_RUSER_WIDTH	= 0,
		parameter integer C_S_AXI_BUSER_WIDTH	= 0
	)
	(

		output	reg					icb_cmd_valid,
		input 						icb_cmd_ready,
		output	reg [31:0] 			icb_cmd_addr,
		output	reg 				icb_cmd_read,
		output	reg [31:0] 			icb_cmd_wdata,
		input 						icb_rsp_valid,
		input  	[31:0]				icb_rsp_rdata,
		output	reg 				icb_rsp_ready,



		input wire  S_AXI_ACLK,
		input wire  S_AXI_ARESETN,
		input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_AWID,
		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
		input wire [7 : 0] S_AXI_AWLEN,
		input wire [2 : 0] S_AXI_AWSIZE,
		input wire [1 : 0] S_AXI_AWBURST,
		input wire  S_AXI_AWLOCK,
		input wire [3 : 0] S_AXI_AWCACHE,
		input wire [2 : 0] S_AXI_AWPROT,
		input wire [3 : 0] S_AXI_AWQOS,
		input wire  S_AXI_AWVALID,
		output wire  S_AXI_AWREADY,
		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
		input wire  S_AXI_WLAST,
		input wire  S_AXI_WVALID,
		output wire  S_AXI_WREADY,
		output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_BID,
		output wire [1 : 0] S_AXI_BRESP,
		output wire  S_AXI_BVALID,
		input wire  S_AXI_BREADY,
		input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_ARID,
		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
		input wire [7 : 0] S_AXI_ARLEN,
		input wire [2 : 0] S_AXI_ARSIZE,
		input wire [1 : 0] S_AXI_ARBURST,
		input wire  S_AXI_ARLOCK,
		input wire [3 : 0] S_AXI_ARCACHE,
		input wire [2 : 0] S_AXI_ARPROT,
		input wire [3 : 0] S_AXI_ARQOS,
		input wire  S_AXI_ARVALID,
		output wire  S_AXI_ARREADY,
		output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_RID,
		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
		output wire [1 : 0] S_AXI_RRESP,
		output wire  S_AXI_RLAST,
		output wire  S_AXI_RVALID,
		input wire  S_AXI_RREADY
	);


	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  							axi_awready;
	wire  							axi_wready;
	reg [1 : 0] 					axi_bresp;
	reg  							axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  							axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 					axi_rresp;
	reg  							axi_rlast;
	wire  							axi_rvalid;

	wire aw_wrap_en;

	wire ar_wrap_en;



	wire [31:0]  aw_wrap_size ; 



	wire [31:0]  ar_wrap_size ; 

	reg axi_awv_awr_flag;

	reg axi_arv_arr_flag; 

	reg [7:0] axi_awlen_cntr;

	reg [7:0] axi_arlen_cntr;
	reg [1:0] axi_arburst;
	reg [1:0] axi_awburst;
	reg [7:0] axi_arlen;
	reg [7:0] axi_awlen;





	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32)+ 1;
	localparam integer OPT_MEM_ADDR_BITS = 3;
	localparam integer USER_NUM_MEM = 1;



	wire [OPT_MEM_ADDR_BITS:0] mem_address;
	wire [USER_NUM_MEM-1:0] mem_select;
	reg [C_S_AXI_DATA_WIDTH-1:0] mem_data_out[0 : USER_NUM_MEM-1];
	reg r_last;
	reg [C_S_AXI_ID_WIDTH-1:0]r_id;
	reg [C_S_AXI_ID_WIDTH-1:0]r_id_temp;
	genvar i;
	genvar j;
	genvar mem_byte_index;



	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RLAST	= r_last;
	assign S_AXI_RVALID	= axi_rvalid;
	assign S_AXI_BID = S_AXI_AWID;
	assign S_AXI_RID = r_id;
	assign  aw_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_awlen)); 
	assign  ar_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_arlen)); 
	assign  aw_wrap_en = ((axi_awaddr & aw_wrap_size) == aw_wrap_size)? 1'b1: 1'b0;
	assign  ar_wrap_en = ((axi_araddr & ar_wrap_size) == ar_wrap_size)? 1'b1: 1'b0;













		
		
		
		












		
	always @ (*)
	if(!S_AXI_ARESETN)
		r_id = 0;
	else if(icb_rsp_valid)
		r_id = r_id_temp;
	else
		r_id = r_id;
	
	always @ (posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
	if(!S_AXI_ARESETN)
		r_id_temp <= 0;
	else if(icb_cmd_valid)
		r_id_temp <= S_AXI_ARID;
		
	
		
		
		
	always @ (posedge S_AXI_ACLK)
	if(!S_AXI_ARESETN)
		r_last <= 0;
	else if(S_AXI_ARREADY & S_AXI_ARVALID)
		r_last <= 1;
	else if(S_AXI_RVALID & S_AXI_RREADY) 
		r_last <= 0;
	
	
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	      axi_awv_awr_flag <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && ~axi_awv_awr_flag && ~axi_arv_arr_flag)
	        begin

	          axi_awready <= 1'b1;
	          axi_awv_awr_flag  <= 1'b1; 

	        end
	      else if (S_AXI_WLAST && axi_wready)          

	        begin
	          axi_awv_awr_flag  <= 1'b0;
	        end
	      else        
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	      axi_awlen_cntr <= 0;
	      axi_awburst <= 0;
	      axi_awlen <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && ~axi_awv_awr_flag)
	        begin

	          axi_awaddr <= S_AXI_AWADDR[C_S_AXI_ADDR_WIDTH - 1:0];  
	           axi_awburst <= S_AXI_AWBURST; 
	           axi_awlen <= S_AXI_AWLEN;     

	          axi_awlen_cntr <= 0;
	        end   
	      else if((axi_awlen_cntr <= axi_awlen) && axi_wready && S_AXI_WVALID)        
	        begin

	          axi_awlen_cntr <= axi_awlen_cntr + 1;

	          case (axi_awburst)
	            2'b00:

	              begin
	                axi_awaddr <= axi_awaddr;          

	              end   
	            2'b01:

	              begin
	                axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;

	                axi_awaddr[ADDR_LSB-1:0]  <= {ADDR_LSB{1'b0}};   

	              end   
	            2'b10:

	              if (aw_wrap_en)
	                begin
	                  axi_awaddr <= (axi_awaddr - aw_wrap_size); 
	                end
	              else 
	                begin
	                  axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
	                  axi_awaddr[ADDR_LSB-1:0]  <= {ADDR_LSB{1'b0}}; 
	                end                      
	            default:
	              begin
	                axi_awaddr <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;

	              end
	          endcase              
	        end
	    end 
	end       





	reg axi_wready_temp;
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready_temp <= 1'b0;
	    end 
	  else
	    begin    
	      if ( ~axi_wready_temp && S_AXI_WVALID && axi_awv_awr_flag)
	        begin

	          axi_wready_temp <= 1'b1;
	        end

	      else if (S_AXI_WLAST && axi_wready)
	        begin
	          axi_wready_temp <= 1'b0;
	        end
	    end 
	end   
	assign axi_wready = axi_wready_temp && icb_cmd_ready;






	reg axi_bvalid_temp;
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid_temp <= 0;
	      axi_bresp <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awv_awr_flag && axi_wready && S_AXI_WVALID && ~axi_bvalid_temp && S_AXI_WLAST)
	        begin
	          axi_bvalid_temp <= 1'b1;
	          axi_bresp  <= 2'b0; 

	        end                   
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 


	            begin
	              axi_bvalid_temp <= 1'b0; 
	            end  
	        end
	    end
	 end
	 always @ (posedge S_AXI_ACLK)
	 if(axi_bvalid_temp && icb_rsp_valid)
		axi_bvalid = 1;
	else if(S_AXI_BREADY)
		axi_bvalid = 0;










	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_arv_arr_flag <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID && ~axi_awv_awr_flag && ~axi_arv_arr_flag)
	        begin
	          axi_arready <= 1'b1;
	          axi_arv_arr_flag <= 1'b1;
	        end
	      else if (axi_rvalid && S_AXI_RREADY && axi_arlen_cntr == axi_arlen)

	        begin
	          axi_arv_arr_flag  <= 1'b0;
	        end
	      else        
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       



	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_araddr <= 0;
	      axi_arlen_cntr <= 0;
	      axi_arburst <= 0;
	      axi_arlen <= 0;
	      axi_rlast <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID && ~axi_arv_arr_flag)
	        begin

	          axi_araddr <= S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH - 1:0]; 
	          axi_arburst <= S_AXI_ARBURST; 
	          axi_arlen <= S_AXI_ARLEN;     

	          axi_arlen_cntr <= 0;
	          axi_rlast <= 1'b0;
	        end   
	      else if((axi_arlen_cntr <= axi_arlen) && axi_rvalid && S_AXI_RREADY)        
	        begin
	         
	          axi_arlen_cntr <= axi_arlen_cntr + 1;
	          axi_rlast <= 1'b0;
	        
	          case (axi_arburst)
	            2'b00:

	              begin
	                axi_araddr       <= axi_araddr;        

	              end   
	            2'b01:

	              begin
	                axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1; 

	                axi_araddr[ADDR_LSB-1:0]  <= {ADDR_LSB{1'b0}};   

	              end   
	            2'b10:

	              if (ar_wrap_en) 
	                begin
	                  axi_araddr <= (axi_araddr - ar_wrap_size); 
	                end
	              else 
	                begin
	                axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1; 

	                axi_araddr[ADDR_LSB-1:0]  <= {ADDR_LSB{1'b0}};   
	                end                      
	            default:
	              begin
	                axi_araddr <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB]+1;

	              end
	          endcase              
	        end
	      else if((axi_arlen_cntr == axi_arlen) && ~axi_rlast && axi_arv_arr_flag )   
	        begin
	          axi_rlast <= 1'b1;
	        end          
	      else if (S_AXI_RREADY)   
	        begin
	          axi_rlast <= 1'b0;
	        end          
	    end 
	end       









	reg axi_rvalid_temp;
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid_temp <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arv_arr_flag && ~axi_rvalid_temp )
	        begin
	          axi_rvalid_temp <= 1'b1;
	          axi_rresp  <= 2'b0; 

	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin
	          axi_rvalid_temp <= 1'b0;
	        end            
	    end
	end    
	assign axi_rvalid = icb_rsp_valid & axi_rvalid_temp;
	

	reg [31:0] 	rdata_temp;
	reg 		[1:0] 	state_d, state_q;
	wire mem_rden;
	reg mem_wren;
	reg mem_wren_reg;
	
	always @ (* )
		if(!S_AXI_ARESETN)
			mem_wren = 0;
		else if(axi_wready_temp && S_AXI_WVALID )
			mem_wren = 1;
		else if(icb_rsp_valid)
			mem_wren = 0;
		else
			mem_wren = mem_wren_reg;
		
		always @ (posedge S_AXI_ACLK,negedge S_AXI_ARESETN)
		if(!S_AXI_ARESETN)
			mem_wren_reg <= 0;
		else if(axi_wready_temp && S_AXI_WVALID )
			mem_wren_reg <= 1;
		else if(icb_rsp_valid)
			mem_wren_reg <= 0;
		
		





	
	
	      assign mem_rden = axi_arv_arr_flag ;
	always @( rdata_temp, axi_rvalid, S_AXI_ARESETN)
	begin
		if(!S_AXI_ARESETN)
			axi_rdata = 32'h0000_0000;
		if (axi_rvalid) 
			axi_rdata = rdata_temp;  
	  else
			axi_rdata = 32'h0000_0000;      
	end    


		reg [1:0] w_state_d, w_state_q;
		reg [31:0]icb_cmd_addr_r;
		reg [31:0] icb_cmd_wdata_r;
		reg [31:0] rdata_temp_r;
	always @ (*)
		if(!S_AXI_ARESETN)
			begin
				icb_cmd_valid 	= 0;
				icb_cmd_addr 	= 0;
				icb_cmd_read 	= 0;
				icb_cmd_wdata 	= 0;
				icb_rsp_ready 	= 0;
				rdata_temp 		= 0;
				state_d			= 0;
				w_state_d		= 0;
			end
		else
			begin
				case(1)
					mem_wren 	:	begin
						rdata_temp 		= 0;
						state_d = 0;
						case(w_state_q)
							0	:	begin
										icb_cmd_valid = 1;
										icb_cmd_addr = axi_awaddr;
										icb_cmd_read = 0;
										icb_cmd_wdata = S_AXI_WDATA;
										icb_rsp_ready = 1;
										w_state_d = 1;
										
									end 
							1	:	begin
										icb_rsp_ready = 1;
										icb_cmd_read = 0;
										icb_cmd_addr = icb_cmd_addr_r;
										icb_cmd_wdata = icb_cmd_wdata_r;
										if(icb_cmd_ready)
											begin
												w_state_d = 2;
												icb_cmd_valid = 0;
											end		
										else	
											begin
												w_state_d = 1;
												icb_cmd_valid = 1;
											end
										
									end
							2	:	begin
										icb_cmd_valid = 0;
										icb_cmd_read = 0;
										icb_cmd_addr = icb_cmd_addr_r;
										icb_cmd_wdata = icb_cmd_wdata_r;
										if(icb_rsp_valid)
											begin
												w_state_d = 0;
												icb_rsp_ready = 0;
											end
										else
											begin
												w_state_d = 2;
												icb_rsp_ready = 1;
											end
									end
							default	:	begin
											icb_cmd_valid = 0;
											w_state_d = 0;
											icb_cmd_addr = 0;
											icb_cmd_wdata = 0;
											icb_cmd_read = 0;
											icb_rsp_ready = 0;
										end
						endcase
					end
					mem_rden : 
						begin
							w_state_d = 0;
							icb_cmd_wdata = 0;
							case (state_q)
								0	:	begin
											icb_cmd_valid = 1;
											icb_cmd_addr = axi_araddr;
											icb_cmd_read = 1;
											icb_rsp_ready = 1;
											rdata_temp 		= rdata_temp_r;
											if(icb_cmd_ready)
												state_d = 1;
											else	
												state_d = 0;
										end
								1	:	begin
											icb_cmd_valid 			= 0; 
											icb_cmd_read 			= 1;
											icb_cmd_addr 			= icb_cmd_addr_r;
											if(icb_rsp_valid)
												begin
													state_d 		= 2;
													rdata_temp 		= icb_rsp_rdata;
													icb_rsp_ready 	= 0;
												end
											else
												begin
													state_d 		= 1;
													rdata_temp 		= rdata_temp_r;
													icb_rsp_ready 	= 1;
												end
										end
								2	:	begin	
											state_d 		= 0;
											icb_cmd_valid 	= 0; 
											icb_rsp_ready 	= 0;
											icb_cmd_read 	= 1;
											icb_cmd_addr 	= icb_cmd_addr_r;
											rdata_temp 		= rdata_temp_r;
										end
							default	:	begin
											icb_cmd_valid 	= 0; 
											icb_rsp_ready	= 0;
											icb_cmd_addr 	= 0;
											icb_cmd_read 	= 1;
											state_d 		= 0;
											rdata_temp 		= 0;
										end
							endcase
						end
					default	:	begin
									icb_cmd_valid 	= 0;
									icb_cmd_addr 	= 0;
									icb_cmd_read 	= 0;
									icb_cmd_wdata 	= 0;
									icb_rsp_ready 	= 0;
									rdata_temp 		= 0;
									state_d			= 0;
									w_state_d 		= 0;
								end
				endcase
			end
		
		always @ (posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
		if(!S_AXI_ARESETN)
			begin
				icb_cmd_wdata_r <= 0;
				icb_cmd_addr_r <= 0;
				rdata_temp_r <= 0;
			end
		else
			case(1)
				mem_wren :
					case(w_state_q)
						0	:	begin
									icb_cmd_addr_r <= axi_awaddr;
									icb_cmd_wdata_r <= S_AXI_WDATA;
								end
						default :	begin
										icb_cmd_addr_r <= icb_cmd_addr_r;
										icb_cmd_wdata_r <= icb_cmd_wdata_r;
									end
					endcase
				mem_rden :
					case(state_q)
						0	:	begin
									icb_cmd_addr_r <= axi_araddr;
									
								end
						1	:	begin
									if(icb_rsp_valid)
										rdata_temp_r <= icb_rsp_rdata;
								end
						default :	begin
										icb_cmd_addr_r <= icb_cmd_addr_r;
										rdata_temp_r <= rdata_temp_r;
									end
					endcase
				default : 	begin
								icb_cmd_addr_r <= icb_cmd_addr_r;
								icb_cmd_wdata_r <= icb_cmd_wdata_r;
								rdata_temp_r <= rdata_temp_r;
							end
			endcase
		
		always @ (posedge S_AXI_ACLK)
			begin
				state_q <= state_d;
				w_state_q <= w_state_d;
			end
		


	endmodule
module myip_v1_0_S00_AXI #
	(

		




		parameter integer C_S_AXI_ID_WIDTH	= 2,
		parameter integer C_S_AXI_DATA_WIDTH	= 32,
		parameter integer C_S_AXI_ADDR_WIDTH	= 6,
		parameter integer C_S_AXI_AWUSER_WIDTH	= 0,
		parameter integer C_S_AXI_ARUSER_WIDTH	= 0,
		parameter integer C_S_AXI_WUSER_WIDTH	= 0,
		parameter integer C_S_AXI_RUSER_WIDTH	= 0,
		parameter integer C_S_AXI_BUSER_WIDTH	= 0
	)
	(

		output	reg					icb_cmd_valid,
		input 						icb_cmd_ready,
		output	reg [31:0] 			icb_cmd_addr,
		output	reg 				icb_cmd_read,
		output	reg [31:0] 			icb_cmd_wdata,
		input 						icb_rsp_valid,
		input  	[31:0]				icb_rsp_rdata,
		output	reg 				icb_rsp_ready,



		input wire  S_AXI_ACLK,
		input wire  S_AXI_ARESETN,
		input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_AWID,
		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
		input wire [7 : 0] S_AXI_AWLEN,
		input wire [2 : 0] S_AXI_AWSIZE,
		input wire [1 : 0] S_AXI_AWBURST,
		input wire  S_AXI_AWLOCK,
		input wire [3 : 0] S_AXI_AWCACHE,
		input wire [2 : 0] S_AXI_AWPROT,
		input wire [3 : 0] S_AXI_AWQOS,
		input wire  S_AXI_AWVALID,
		output wire  S_AXI_AWREADY,
		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
		input wire  S_AXI_WLAST,
		input wire  S_AXI_WVALID,
		output wire  S_AXI_WREADY,
		output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_BID,
		output wire [1 : 0] S_AXI_BRESP,
		output wire  S_AXI_BVALID,
		input wire  S_AXI_BREADY,
		input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_ARID,
		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
		input wire [7 : 0] S_AXI_ARLEN,
		input wire [2 : 0] S_AXI_ARSIZE,
		input wire [1 : 0] S_AXI_ARBURST,
		input wire  S_AXI_ARLOCK,
		input wire [3 : 0] S_AXI_ARCACHE,
		input wire [2 : 0] S_AXI_ARPROT,
		input wire [3 : 0] S_AXI_ARQOS,
		input wire  S_AXI_ARVALID,
		output wire  S_AXI_ARREADY,
		output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_RID,
		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
		output wire [1 : 0] S_AXI_RRESP,
		output wire  S_AXI_RLAST,
		output wire  S_AXI_RVALID,
		input wire  S_AXI_RREADY
	);



	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  							axi_awready;
	wire  							axi_wready;
	reg [1 : 0] 					axi_bresp;
	reg  							axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  							axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 					axi_rresp;
	reg  							axi_rlast;
	wire  							axi_rvalid;

	wire aw_wrap_en;

	wire ar_wrap_en;



	wire [31:0]  aw_wrap_size ; 



	wire [31:0]  ar_wrap_size ; 

	reg axi_awv_awr_flag;

	reg axi_arv_arr_flag; 

	reg [7:0] axi_awlen_cntr;

	reg [7:0] axi_arlen_cntr;
	reg [1:0] axi_arburst;
	reg [1:0] axi_awburst;
	reg [7:0] axi_arlen;
	reg [7:0] axi_awlen;





	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32)+ 1;
	localparam integer OPT_MEM_ADDR_BITS = 3;
	localparam integer USER_NUM_MEM = 1;



	wire [OPT_MEM_ADDR_BITS:0] mem_address;
	wire [USER_NUM_MEM-1:0] mem_select;
	reg [C_S_AXI_DATA_WIDTH-1:0] mem_data_out[0 : USER_NUM_MEM-1];
	reg r_last;
	reg [C_S_AXI_ID_WIDTH-1:0]r_id;
	reg [C_S_AXI_ID_WIDTH-1:0]r_id_temp;
	genvar i;
	genvar j;
	genvar mem_byte_index;



	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RLAST	= r_last;
	assign S_AXI_RVALID	= axi_rvalid;
	assign S_AXI_BID = S_AXI_AWID;
	assign S_AXI_RID = r_id;
	assign  aw_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_awlen)); 
	assign  ar_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_arlen)); 
	assign  aw_wrap_en = ((axi_awaddr & aw_wrap_size) == aw_wrap_size)? 1'b1: 1'b0;
	assign  ar_wrap_en = ((axi_araddr & ar_wrap_size) == ar_wrap_size)? 1'b1: 1'b0;













		
		
		
		












		
	always @ (*)
	if(!S_AXI_ARESETN)
		r_id = 0;
	else if(icb_rsp_valid)
		r_id = r_id_temp;
	else
		r_id = r_id;
	
	always @ (posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
	if(!S_AXI_ARESETN)
		r_id_temp <= 0;
	else if(icb_cmd_valid)
		r_id_temp <= S_AXI_ARID;
		
	
		
		
		
	always @ (posedge S_AXI_ACLK)
	if(!S_AXI_ARESETN)
		r_last <= 0;
	else if(S_AXI_ARREADY & S_AXI_ARVALID)
		r_last <= 1;
	else if(S_AXI_RVALID & S_AXI_RREADY) 
		r_last <= 0;
	
	
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	      axi_awv_awr_flag <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && ~axi_awv_awr_flag && ~axi_arv_arr_flag)
	        begin

	          axi_awready <= 1'b1;
	          axi_awv_awr_flag  <= 1'b1; 

	        end
	      else if (S_AXI_WLAST && axi_wready)          

	        begin
	          axi_awv_awr_flag  <= 1'b0;
	        end
	      else        
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	      axi_awlen_cntr <= 0;
	      axi_awburst <= 0;
	      axi_awlen <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && ~axi_awv_awr_flag)
	        begin

	          axi_awaddr <= S_AXI_AWADDR[C_S_AXI_ADDR_WIDTH - 1:0];  
	           axi_awburst <= S_AXI_AWBURST; 
	           axi_awlen <= S_AXI_AWLEN;     

	          axi_awlen_cntr <= 0;
	        end   
	      else if((axi_awlen_cntr <= axi_awlen) && axi_wready && S_AXI_WVALID)        
	        begin

	          axi_awlen_cntr <= axi_awlen_cntr + 1;

	          case (axi_awburst)
	            2'b00:

	              begin
	                axi_awaddr <= axi_awaddr;          

	              end   
	            2'b01:

	              begin
	                axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;

	                axi_awaddr[ADDR_LSB-1:0]  <= {ADDR_LSB{1'b0}};   

	              end   
	            2'b10:

	              if (aw_wrap_en)
	                begin
	                  axi_awaddr <= (axi_awaddr - aw_wrap_size); 
	                end
	              else 
	                begin
	                  axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
	                  axi_awaddr[ADDR_LSB-1:0]  <= {ADDR_LSB{1'b0}}; 
	                end                      
	            default:
	              begin
	                axi_awaddr <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;

	              end
	          endcase              
	        end
	    end 
	end       





	reg axi_wready_temp;
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready_temp <= 1'b0;
	    end 
	  else
	    begin    
	      if ( ~axi_wready_temp && S_AXI_WVALID && axi_awv_awr_flag)
	        begin

	          axi_wready_temp <= 1'b1;
	        end

	      else if (S_AXI_WLAST && axi_wready)
	        begin
	          axi_wready_temp <= 1'b0;
	        end
	    end 
	end   
	assign axi_wready = axi_wready_temp && icb_cmd_ready;






	reg axi_bvalid_temp;
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid_temp <= 0;
	      axi_bresp <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awv_awr_flag && axi_wready && S_AXI_WVALID && ~axi_bvalid_temp && S_AXI_WLAST)
	        begin
	          axi_bvalid_temp <= 1'b1;
	          axi_bresp  <= 2'b0; 

	        end                   
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 


	            begin
	              axi_bvalid_temp <= 1'b0; 
	            end  
	        end
	    end
	 end
	 always @ (posedge S_AXI_ACLK)
	 if(axi_bvalid_temp && icb_rsp_valid)
		axi_bvalid = 1;
	else if(S_AXI_BREADY)
		axi_bvalid = 0;










	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_arv_arr_flag <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID && ~axi_awv_awr_flag && ~axi_arv_arr_flag)
	        begin
	          axi_arready <= 1'b1;
	          axi_arv_arr_flag <= 1'b1;
	        end
	      else if (axi_rvalid && S_AXI_RREADY && axi_arlen_cntr == axi_arlen)

	        begin
	          axi_arv_arr_flag  <= 1'b0;
	        end
	      else        
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       



	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_araddr <= 0;
	      axi_arlen_cntr <= 0;
	      axi_arburst <= 0;
	      axi_arlen <= 0;
	      axi_rlast <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID && ~axi_arv_arr_flag)
	        begin

	          axi_araddr <= S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH - 1:0]; 
	          axi_arburst <= S_AXI_ARBURST; 
	          axi_arlen <= S_AXI_ARLEN;     

	          axi_arlen_cntr <= 0;
	          axi_rlast <= 1'b0;
	        end   
	      else if((axi_arlen_cntr <= axi_arlen) && axi_rvalid && S_AXI_RREADY)        
	        begin
	         
	          axi_arlen_cntr <= axi_arlen_cntr + 1;
	          axi_rlast <= 1'b0;
	        
	          case (axi_arburst)
	            2'b00:

	              begin
	                axi_araddr       <= axi_araddr;        

	              end   
	            2'b01:

	              begin
	                axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1; 

	                axi_araddr[ADDR_LSB-1:0]  <= {ADDR_LSB{1'b0}};   

	              end   
	            2'b10:

	              if (ar_wrap_en) 
	                begin
	                  axi_araddr <= (axi_araddr - ar_wrap_size); 
	                end
	              else 
	                begin
	                axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1; 

	                axi_araddr[ADDR_LSB-1:0]  <= {ADDR_LSB{1'b0}};   
	                end                      
	            default:
	              begin
	                axi_araddr <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB]+1;

	              end
	          endcase              
	        end
	      else if((axi_arlen_cntr == axi_arlen) && ~axi_rlast && axi_arv_arr_flag )   
	        begin
	          axi_rlast <= 1'b1;
	        end          
	      else if (S_AXI_RREADY)   
	        begin
	          axi_rlast <= 1'b0;
	        end          
	    end 
	end       









	reg axi_rvalid_temp;
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid_temp <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arv_arr_flag && ~axi_rvalid_temp )
	        begin
	          axi_rvalid_temp <= 1'b1;
	          axi_rresp  <= 2'b0; 

	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin
	          axi_rvalid_temp <= 1'b0;
	        end            
	    end
	end    
	assign axi_rvalid = icb_rsp_valid & axi_rvalid_temp;
	

	reg [31:0] 	rdata_temp;
	reg 		[1:0] 	state_d, state_q;
	wire mem_rden;
	reg mem_wren;
	reg mem_wren_reg;
	
	always @ (* )
		if(!S_AXI_ARESETN)
			mem_wren = 0;
		else if(axi_wready_temp && S_AXI_WVALID )
			mem_wren = 1;
		else if(icb_rsp_valid)
			mem_wren = 0;
		else
			mem_wren = mem_wren_reg;
		
		always @ (posedge S_AXI_ACLK,negedge S_AXI_ARESETN)
		if(!S_AXI_ARESETN)
			mem_wren_reg <= 0;
		else if(axi_wready_temp && S_AXI_WVALID )
			mem_wren_reg <= 1;
		else if(icb_rsp_valid)
			mem_wren_reg <= 0;
		
		





	
	
	      assign mem_rden = axi_arv_arr_flag ;
	always @( rdata_temp, axi_rvalid, S_AXI_ARESETN)
	begin
		if(!S_AXI_ARESETN)
			axi_rdata = 32'h0000_0000;
		if (axi_rvalid) 
			axi_rdata = rdata_temp;  
	  else
			axi_rdata = 32'h0000_0000;      
	end    


		reg [1:0] w_state_d, w_state_q;
		reg [31:0]icb_cmd_addr_r;
		reg [31:0] icb_cmd_wdata_r;
		reg [31:0] rdata_temp_r;
	always @ (*)
		if(!S_AXI_ARESETN)
			begin
				icb_cmd_valid 	= 0;
				icb_cmd_addr 	= 0;
				icb_cmd_read 	= 0;
				icb_cmd_wdata 	= 0;
				icb_rsp_ready 	= 0;
				rdata_temp 		= 0;
				state_d			= 0;
				w_state_d		= 0;
			end
		else
			begin
				case(1)
					mem_wren 	:	begin
						rdata_temp 		= 0;
						state_d = 0;
						case(w_state_q)
							0	:	begin
										icb_cmd_valid = 1;
										icb_cmd_addr = axi_awaddr;
										icb_cmd_read = 0;
										icb_cmd_wdata = S_AXI_WDATA;
										icb_rsp_ready = 1;
										w_state_d = 1;
										
									end 
							1	:	begin
										icb_rsp_ready = 1;
										icb_cmd_read = 0;
										icb_cmd_addr = icb_cmd_addr_r;
										icb_cmd_wdata = icb_cmd_wdata_r;
										if(icb_cmd_ready)
											begin
												w_state_d = 2;
												icb_cmd_valid = 0;
											end		
										else	
											begin
												w_state_d = 1;
												icb_cmd_valid = 1;
											end
										
									end
							2	:	begin
										icb_cmd_valid = 0;
										icb_cmd_read = 0;
										icb_cmd_addr = icb_cmd_addr_r;
										icb_cmd_wdata = icb_cmd_wdata_r;
										if(icb_rsp_valid)
											begin
												w_state_d = 0;
												icb_rsp_ready = 0;
											end
										else
											begin
												w_state_d = 2;
												icb_rsp_ready = 1;
											end
									end
							default	:	begin
											icb_cmd_valid = 0;
											w_state_d = 0;
											icb_cmd_addr = 0;
											icb_cmd_wdata = 0;
											icb_cmd_read = 0;
											icb_rsp_ready = 0;
										end
						endcase
					end
					mem_rden : 
						begin
							w_state_d = 0;
							icb_cmd_wdata = 0;
							case (state_q)
								0	:	begin
											icb_cmd_valid = 1;
											icb_cmd_addr = axi_araddr;
											icb_cmd_read = 1;
											icb_rsp_ready = 1;
											rdata_temp 		= rdata_temp_r;
											if(icb_cmd_ready)
												state_d = 1;
											else	
												state_d = 0;
										end
								1	:	begin
											icb_cmd_valid 			= 0; 
											icb_cmd_read 			= 1;
											icb_cmd_addr 			= icb_cmd_addr_r;
											if(icb_rsp_valid)
												begin
													state_d 		= 2;
													rdata_temp 		= icb_rsp_rdata;
													icb_rsp_ready 	= 0;
												end
											else
												begin
													state_d 		= 1;
													rdata_temp 		= rdata_temp_r;
													icb_rsp_ready 	= 1;
												end
										end
								2	:	begin	
											state_d 		= 0;
											icb_cmd_valid 	= 0; 
											icb_rsp_ready 	= 0;
											icb_cmd_read 	= 1;
											icb_cmd_addr 	= icb_cmd_addr_r;
											rdata_temp 		= rdata_temp_r;
										end
							default	:	begin
											icb_cmd_valid 	= 0; 
											icb_rsp_ready	= 0;
											icb_cmd_addr 	= 0;
											icb_cmd_read 	= 1;
											state_d 		= 0;
											rdata_temp 		= 0;
										end
							endcase
						end
					default	:	begin
									icb_cmd_valid 	= 0;
									icb_cmd_addr 	= 0;
									icb_cmd_read 	= 0;
									icb_cmd_wdata 	= 0;
									icb_rsp_ready 	= 0;
									rdata_temp 		= 0;
									state_d			= 0;
									w_state_d 		= 0;
								end
				endcase
			end
		
		always @ (posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
		if(!S_AXI_ARESETN)
			begin
				icb_cmd_wdata_r <= 0;
				icb_cmd_addr_r <= 0;
				rdata_temp_r <= 0;
			end
		else
			case(1)
				mem_wren :
					case(w_state_q)
						0	:	begin
									icb_cmd_addr_r <= axi_awaddr;
									icb_cmd_wdata_r <= S_AXI_WDATA;
								end
						default :	begin
										icb_cmd_addr_r <= icb_cmd_addr_r;
										icb_cmd_wdata_r <= icb_cmd_wdata_r;
									end
					endcase
				mem_rden :
					case(state_q)
						0	:	begin
									icb_cmd_addr_r <= axi_araddr;
									
								end
						1	:	begin
									if(icb_rsp_valid)
										rdata_temp_r <= icb_rsp_rdata;
								end
						default :	begin
										icb_cmd_addr_r <= icb_cmd_addr_r;
										rdata_temp_r <= rdata_temp_r;
									end
					endcase
				default : 	begin
								icb_cmd_addr_r <= icb_cmd_addr_r;
								icb_cmd_wdata_r <= icb_cmd_wdata_r;
								rdata_temp_r <= rdata_temp_r;
							end
			endcase
		
		always @ (posedge S_AXI_ACLK)
			begin
				state_q <= state_d;
				w_state_q <= w_state_d;
			end
		


	endmodule