data/full_repos/permissive/111258339/src/Control/ctrl.v
1: b'%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:1: Cannot find include file: src/Define/ctrl_encode_def.v\n`include "src/Define/ctrl_encode_def.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/111258339/src/Control,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v\n             data/full_repos/permissive/111258339/src/Control,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v.v\n             data/full_repos/permissive/111258339/src/Control,data/full_repos/permissive/111258339/src/Define/ctrl_encode_def.v.sv\n             src/Define/ctrl_encode_def.v\n             src/Define/ctrl_encode_def.v.v\n             src/Define/ctrl_encode_def.v.sv\n             obj_dir/src/Define/ctrl_encode_def.v\n             obj_dir/src/Define/ctrl_encode_def.v.v\n             obj_dir/src/Define/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:46: Define or directive not defined: \'`CTRL_OP_RTYPE\'\n            `CTRL_OP_RTYPE: begin\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:46: syntax error, unexpected \':\', expecting endcase\n            `CTRL_OP_RTYPE: begin\n                          ^\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:48: Define or directive not defined: \'`CTRL_FUNCT_ADDU\'\n                    `CTRL_FUNCT_ADDU: ALUOp = `ALUOP_ADDU;\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:48: Define or directive not defined: \'`ALUOP_ADDU\'\n                    `CTRL_FUNCT_ADDU: ALUOp = `ALUOP_ADDU;\n                                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:49: Define or directive not defined: \'`CTRL_FUNCT_SUBU\'\n                    `CTRL_FUNCT_SUBU: ALUOp = `ALUOP_SUBU;\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:49: Define or directive not defined: \'`ALUOP_SUBU\'\n                    `CTRL_FUNCT_SUBU: ALUOp = `ALUOP_SUBU;\n                                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:50: Define or directive not defined: \'`ALUOP_ADDU\'\n                    default: ALUOp = `ALUOP_ADDU;\n                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:63: Define or directive not defined: \'`CTRL_OP_ORI\'\n            `CTRL_OP_ORI: begin\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:63: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `CTRL_OP_ORI: begin\n                          ^~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:64: Define or directive not defined: \'`ALUOP_ORI\'\n                ALUOp = `ALUOP_ORI;\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:75: Define or directive not defined: \'`CTRL_OP_LW\'\n            `CTRL_OP_LW: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:75: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `CTRL_OP_LW: begin\n                         ^~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:86: Define or directive not defined: \'`CTRL_OP_SW\'\n            `CTRL_OP_SW: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:86: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `CTRL_OP_SW: begin\n                         ^~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:97: Define or directive not defined: \'`CTRL_OP_BEQ\'\n            `CTRL_OP_BEQ: begin\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:97: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `CTRL_OP_BEQ: begin\n                          ^~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:108: Define or directive not defined: \'`CTRL_OP_JAL\'\n            `CTRL_OP_JAL: begin\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:108: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `CTRL_OP_JAL: begin\n                          ^~~~~\n%Error: data/full_repos/permissive/111258339/src/Control/ctrl.v:120: syntax error, unexpected \':\', expecting clocking\n            default: begin\n                   ^\n%Error: Cannot continue\n'
module ctrl(
    input wire clk,
    input wire reset,

    input wire[5:0] OP,
    input wire[5:0] funct,

    input wire Zero,

    output reg RegWrite,

    output reg RegDst,

    output reg[1:0] EXTOp,

    output reg MemWrite,
    output reg MemRead,

    output reg ALUSrc,

    output reg[1:0] ALUOp,

    output reg Mem2Reg,

    output reg Branch,

    output reg Jump
);
  
    initial begin
        ALUSrc = 0;
        RegWrite = 0;
        RegDst = 0;
        MemWrite = 0;
        MemRead = 0;
        Mem2Reg = 0;
        Branch = 0;
        Jump = 1;
    end
  

    always @(*) begin
        case (OP)
            `CTRL_OP_RTYPE: begin
                case(funct)
                    `CTRL_FUNCT_ADDU: ALUOp = `ALUOP_ADDU;
                    `CTRL_FUNCT_SUBU: ALUOp = `ALUOP_SUBU;
                    default: ALUOp = `ALUOP_ADDU;
                endcase

                ALUSrc = 0;
                RegWrite = 1;
                RegDst = 1;
                MemWrite = 0;
                MemRead = 0;
                Mem2Reg = 0;
                Branch = 0;
                Jump = 1;
            end

            `CTRL_OP_ORI: begin
                ALUOp = `ALUOP_ORI;
                ALUSrc = 1;
                RegWrite = 1;
                RegDst = 0;
                MemWrite = 0;
                MemRead = 0;
                Mem2Reg = 0;
                Branch = 0;
                Jump = 1;
            end

            `CTRL_OP_LW: begin
                ALUSrc = 1;
                RegWrite = 1;
                RegDst = 0;
                MemWrite = 0;
                MemRead = 1;
                Mem2Reg = 1;
                Branch = 0;
                Jump = 1;
            end

            `CTRL_OP_SW: begin
                ALUSrc = 1;
                RegWrite = 0;
                RegDst = 0;
                MemWrite = 1;
                MemRead = 0;
                Mem2Reg = 0;
                Branch = 0;
                Jump = 1;
            end

            `CTRL_OP_BEQ: begin
                ALUSrc = 0;
                RegWrite = 0;
                RegDst = 0;
                MemWrite = 0;
                MemRead = 0;
                Mem2Reg = 0;
                Branch = 1;
                Jump   = 1;
            end

            `CTRL_OP_JAL: begin
                ALUSrc = 0;
                RegWrite = 1;
                RegDst = 0;
                MemWrite = 0;
                MemRead = 0;
                Mem2Reg = 0;
                Branch = 0;
                Jump = 0;
                $display("Jump!---------------");
            end

            default: begin
                ALUSrc = 0;
                RegWrite = 0;
                RegDst = 0;
                MemWrite = 0;
                MemRead = 0;
                Mem2Reg = 0;
                Branch = 0;
                Jump = 1;
            end
        endcase
    end
endmodule
module ctrl(
    input wire clk,
    input wire reset,

    input wire[5:0] OP,
    input wire[5:0] funct,

    input wire Zero,

    output reg RegWrite,

    output reg RegDst,

    output reg[1:0] EXTOp,

    output reg MemWrite,
    output reg MemRead,

    output reg ALUSrc,

    output reg[1:0] ALUOp,

    output reg Mem2Reg,

    output reg Branch,

    output reg Jump
);

  
    initial begin
        ALUSrc = 0;
        RegWrite = 0;
        RegDst = 0;
        MemWrite = 0;
        MemRead = 0;
        Mem2Reg = 0;
        Branch = 0;
        Jump = 1;
    end
  

    always @(*) begin
        case (OP)
            `CTRL_OP_RTYPE: begin
                case(funct)
                    `CTRL_FUNCT_ADDU: ALUOp = `ALUOP_ADDU;
                    `CTRL_FUNCT_SUBU: ALUOp = `ALUOP_SUBU;
                    default: ALUOp = `ALUOP_ADDU;
                endcase

                ALUSrc = 0;
                RegWrite = 1;
                RegDst = 1;
                MemWrite = 0;
                MemRead = 0;
                Mem2Reg = 0;
                Branch = 0;
                Jump = 1;
            end

            `CTRL_OP_ORI: begin
                ALUOp = `ALUOP_ORI;
                ALUSrc = 1;
                RegWrite = 1;
                RegDst = 0;
                MemWrite = 0;
                MemRead = 0;
                Mem2Reg = 0;
                Branch = 0;
                Jump = 1;
            end

            `CTRL_OP_LW: begin
                ALUSrc = 1;
                RegWrite = 1;
                RegDst = 0;
                MemWrite = 0;
                MemRead = 1;
                Mem2Reg = 1;
                Branch = 0;
                Jump = 1;
            end

            `CTRL_OP_SW: begin
                ALUSrc = 1;
                RegWrite = 0;
                RegDst = 0;
                MemWrite = 1;
                MemRead = 0;
                Mem2Reg = 0;
                Branch = 0;
                Jump = 1;
            end

            `CTRL_OP_BEQ: begin
                ALUSrc = 0;
                RegWrite = 0;
                RegDst = 0;
                MemWrite = 0;
                MemRead = 0;
                Mem2Reg = 0;
                Branch = 1;
                Jump   = 1;
            end

            `CTRL_OP_JAL: begin
                ALUSrc = 0;
                RegWrite = 1;
                RegDst = 0;
                MemWrite = 0;
                MemRead = 0;
                Mem2Reg = 0;
                Branch = 0;
                Jump = 0;
                $display("Jump!---------------");
            end

            default: begin
                ALUSrc = 0;
                RegWrite = 0;
                RegDst = 0;
                MemWrite = 0;
                MemRead = 0;
                Mem2Reg = 0;
                Branch = 0;
                Jump = 1;
            end
        endcase
    end
endmodule