data/full_repos/permissive/174642777/Experiments/Lab X8/1. Timer/Timer_test.v
1: b'%Error: Cannot find file containing module: X8/1.\n        ... Looked in:\n             data/full_repos/permissive/174642777/Experiments/Lab/X8/1.\n             data/full_repos/permissive/174642777/Experiments/Lab/X8/1..v\n             data/full_repos/permissive/174642777/Experiments/Lab/X8/1..sv\n             X8/1.\n             X8/1..v\n             X8/1..sv\n             obj_dir/X8/1.\n             obj_dir/X8/1..v\n             obj_dir/X8/1..sv\n%Error: Cannot find file containing module: Timer,data/full_repos/permissive/174642777\n%Error: Cannot find file containing module: data/full_repos/permissive/174642777/Experiments/Lab\n%Error: Cannot find file containing module: Timer/Timer_test.v\n%Error: Exiting due to 4 error(s)\n'
module Timer_test;


	reg CLK_100M;
	reg RST;
	reg START;
	reg STOP;
	reg INC;


	wire [7:0] SEG;
	wire [3:0] AN;
	wire RUN;
  

  reg[31:0] cclk;


	Timer uut (
		.CLK_100M(CLK_100M), 
		.RST(RST), 
		.START(START), 
		.STOP(STOP), 
		.INC(INC), 
		.SEG(SEG), 
		.AN(AN), 
		.RUN(RUN)
	);

	initial begin

		CLK_100M = 0;
		RST = 0;
		START = 0;
		STOP = 0;
		INC = 0;
    cclk = 0;


		#100;
        


	end
  
  always begin
    #1;
    CLK_100M <= !CLK_100M;
    cclk <= cclk + 1;
  end
  
  always@(posedge cclk[0], negedge cclk[0]) begin

    if(cclk == 110)   START = 1;
    if(cclk == 112)   START = 0;

    if(cclk == 200)  STOP = 1;
    if(cclk == 202)  STOP = 0;

    if(cclk == 300)  INC = 1;
    if(cclk == 400)  INC = 0;

    if(cclk == 500)   START = 1;
    if(cclk == 502)   START = 0;

    if(cclk == 600)  RST = 1;
    if(cclk == 602)  RST = 0;
  end
  
endmodule
module Timer_test;



	reg CLK_100M;
	reg RST;
	reg START;
	reg STOP;
	reg INC;


	wire [7:0] SEG;
	wire [3:0] AN;
	wire RUN;
  

  reg[31:0] cclk;


	Timer uut (
		.CLK_100M(CLK_100M), 
		.RST(RST), 
		.START(START), 
		.STOP(STOP), 
		.INC(INC), 
		.SEG(SEG), 
		.AN(AN), 
		.RUN(RUN)
	);

	initial begin

		CLK_100M = 0;
		RST = 0;
		START = 0;
		STOP = 0;
		INC = 0;
    cclk = 0;


		#100;
        


	end
  
  always begin
    #1;
    CLK_100M <= !CLK_100M;
    cclk <= cclk + 1;
  end
  
  always@(posedge cclk[0], negedge cclk[0]) begin

    if(cclk == 110)   START = 1;
    if(cclk == 112)   START = 0;

    if(cclk == 200)  STOP = 1;
    if(cclk == 202)  STOP = 0;

    if(cclk == 300)  INC = 1;
    if(cclk == 400)  INC = 0;

    if(cclk == 500)   START = 1;
    if(cclk == 502)   START = 0;

    if(cclk == 600)  RST = 1;
    if(cclk == 602)  RST = 0;
  end
  
endmodule