data/full_repos/permissive/135852214/Verilog/bus.v
1: b'%Warning-WIDTH: data/full_repos/permissive/135852214/Verilog/bus.v:27: Operator ASSIGNW expects 25 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 38 bits.\n                                                                     : ... In instance bus\nassign data_out = {rw,addr,data_out};\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/135852214/Verilog/bus.v:27: Wire inputs its own output, creating circular logic (wire x=x)\n                                                             : ... In instance bus\nassign data_out = {rw,addr,data_out};\n                ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module bus(
    input rw, 
    input [11:0] addr,
    input [11:0] data,
    output [24:0] data_out 
    );
assign data_out = {rw,addr,data_out};

endmodule
module bus(
    input rw, 
    input [11:0] addr,
    input [11:0] data,
    output [24:0] data_out 
    );

assign data_out = {rw,addr,data_out};

endmodule