data/full_repos/permissive/153866423/_magiccubeImageProcess.srcs/magiccubeImageProcess.srcs_18_12_07/sources_1/imports/MyScripts/magicalImageProcess/freq_divide.v
data/verilator_xmls/c971c20b-cec1-44e3-864b-a83881e16858.xml
module freq_divide(
        input clki,
        output clko_25MHz
    );

reg [27:0]state;
always@(posedge clki)
begin
  state <= state+1'b1;
end
assign clko_25MHz=state[1];

endmodule
module freq_divide(
        input clki,
        output clko_25MHz
    );


reg [27:0]state;
always@(posedge clki)
begin
  state <= state+1'b1;
end
assign clko_25MHz=state[1];

endmodule