data/full_repos/permissive/201025648/Verilog/3.11.v
 line:3 column:7: Illegal character '，'
1: b"%Error: data/full_repos/permissive/201025648/Verilog/3.11.v:3: syntax error, unexpected $end, expecting ',' or ';'\nreg x  y  a  b  m  \n     ^\n%Error: Cannot continue\n"
module stimulus;

reg x，y，a，b，m；

initial

	m=1'b0
initial
begin

	#5 a=1'b1;
	#25 y=1'b1;
end

initial

begin

	#10 x=1'b0;
	#25 y=1'b1;

end 

initial

	#50 $finish;
endmodule
module stimulus;


reg x，y，a，b，m；

initial

	m=1'b0
initial
begin

	#5 a=1'b1;
	#25 y=1'b1;
end

initial

begin

	#10 x=1'b0;
	#25 y=1'b1;

end 

initial

	#50 $finish;
endmodule