data/full_repos/permissive/201984065/src/tb/tb_prince_core.v
 line:115: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:98: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_HALF_PERIOD;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:112: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:175: Unsupported: Ignoring delay on this delayed statement.\n      #(2 * CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:214: Unsupported: Ignoring delay on this delayed statement.\n      #(2 * CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:217: Unsupported: Ignoring delay on this delayed statement.\n          #(CLK_PERIOD);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:271: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:293: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:131: Can\'t find definition of \'encdec\' in dotted variable: \'dut.encdec\'\n      $display("encdec = 0x%01x, next = 0x%01x", dut.encdec, dut.next);\n                                                     ^~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:131: Can\'t find definition of \'next\' in dotted variable: \'dut.next\'\n      $display("encdec = 0x%01x, next = 0x%01x", dut.encdec, dut.next);\n                                                                 ^~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:132: Can\'t find definition of \'key\' in dotted variable: \'dut.key\'\n      $display("key   = 0x%016x ", dut.key);\n                                       ^~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:133: Can\'t find definition of \'block\' in dotted variable: \'dut.block\'\n      $display("block = 0x%08x", dut.block);\n                                     ^~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:134: Can\'t find definition of \'ready\' in dotted variable: \'dut.ready\'\n      $display("ready  = 0x%01x", dut.ready);\n                                      ^~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:135: Can\'t find definition of \'result\' in dotted variable: \'dut.result\'\n      $display("result = 0x%08x", dut.result);\n                                      ^~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:139: Can\'t find definition of \'k0_reg\' in dotted variable: \'dut.k0_reg\'\n               dut.k0_reg, dut.k1_reg, dut.kp_reg);\n                   ^~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:139: Can\'t find definition of \'k1_reg\' in dotted variable: \'dut.k1_reg\'\n               dut.k0_reg, dut.k1_reg, dut.kp_reg);\n                               ^~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:139: Can\'t find definition of \'kp_reg\' in dotted variable: \'dut.kp_reg\'\n               dut.k0_reg, dut.k1_reg, dut.kp_reg);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:141: Can\'t find definition of \'prince_core_dp\' in dotted scope/variable: \'dut.prince_core_dp\'\n      $display("core_input: 0x%08x", dut.prince_core_dp.core_input);\n                                         ^~~~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:143: Can\'t find definition of \'prince_core_dp\' in dotted scope/variable: \'dut.prince_core_dp\'\n               dut.prince_core_dp.r0, dut.prince_core_dp.r1, dut.prince_core_dp.r2);\n                   ^~~~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:143: Can\'t find definition of \'prince_core_dp\' in dotted scope/variable: \'dut.prince_core_dp\'\n               dut.prince_core_dp.r0, dut.prince_core_dp.r1, dut.prince_core_dp.r2);\n                                          ^~~~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:143: Can\'t find definition of \'prince_core_dp\' in dotted scope/variable: \'dut.prince_core_dp\'\n               dut.prince_core_dp.r0, dut.prince_core_dp.r1, dut.prince_core_dp.r2);\n                                                                 ^~~~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:145: Can\'t find definition of \'r3_reg\' in dotted variable: \'dut.r3_reg\'\n               dut.r3_reg, dut.prince_core_dp.r4, dut.prince_core_dp.r5);\n                   ^~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:145: Can\'t find definition of \'prince_core_dp\' in dotted scope/variable: \'dut.prince_core_dp\'\n               dut.r3_reg, dut.prince_core_dp.r4, dut.prince_core_dp.r5);\n                               ^~~~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:145: Can\'t find definition of \'prince_core_dp\' in dotted scope/variable: \'dut.prince_core_dp\'\n               dut.r3_reg, dut.prince_core_dp.r4, dut.prince_core_dp.r5);\n                                                      ^~~~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:146: Can\'t find definition of \'mr_reg\' in dotted variable: \'dut.mr_reg\'\n      $display("mr: 0x%08x", dut.mr_reg);\n                                 ^~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:148: Can\'t find definition of \'prince_core_dp\' in dotted scope/variable: \'dut.prince_core_dp\'\n               dut.prince_core_dp.r6, dut.prince_core_dp.r7, dut.r8_reg);\n                   ^~~~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:148: Can\'t find definition of \'prince_core_dp\' in dotted scope/variable: \'dut.prince_core_dp\'\n               dut.prince_core_dp.r6, dut.prince_core_dp.r7, dut.r8_reg);\n                                          ^~~~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:148: Can\'t find definition of \'r8_reg\' in dotted variable: \'dut.r8_reg\'\n               dut.prince_core_dp.r6, dut.prince_core_dp.r7, dut.r8_reg);\n                                                                 ^~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:150: Can\'t find definition of \'prince_core_dp\' in dotted scope/variable: \'dut.prince_core_dp\'\n               dut.prince_core_dp.r9, dut.prince_core_dp.r10, dut.prince_core_dp.r11);\n                   ^~~~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:150: Can\'t find definition of \'prince_core_dp\' in dotted scope/variable: \'dut.prince_core_dp\'\n               dut.prince_core_dp.r9, dut.prince_core_dp.r10, dut.prince_core_dp.r11);\n                                          ^~~~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:150: Can\'t find definition of \'prince_core_dp\' in dotted scope/variable: \'dut.prince_core_dp\'\n               dut.prince_core_dp.r9, dut.prince_core_dp.r10, dut.prince_core_dp.r11);\n                                                                  ^~~~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:151: Can\'t find definition of \'prince_core_dp\' in dotted scope/variable: \'dut.prince_core_dp\'\n      $display("core_output: 0x%08x", dut.prince_core_dp.core_output);\n                                          ^~~~~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:153: Can\'t find definition of \'state_reg\' in dotted variable: \'dut.state_reg\'\n               dut.state_reg, dut.state_new, dut.state_we);\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:153: Can\'t find definition of \'state_new\' in dotted variable: \'dut.state_new\'\n               dut.state_reg, dut.state_new, dut.state_we);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:153: Can\'t find definition of \'state_we\' in dotted variable: \'dut.state_we\'\n               dut.state_reg, dut.state_new, dut.state_we);\n                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:156: Can\'t find definition of \'init_state\' in dotted variable: \'dut.init_state\'\n               dut.init_state, dut.update_state);\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:156: Can\'t find definition of \'update_state\' in dotted variable: \'dut.update_state\'\n               dut.init_state, dut.update_state);\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:158: Can\'t find definition of \'core_ctrl_reg\' in dotted variable: \'dut.core_ctrl_reg\'\n               dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:158: Can\'t find definition of \'core_ctrl_new\' in dotted variable: \'dut.core_ctrl_new\'\n               dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);\n                                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201984065/src/tb/tb_prince_core.v:158: Can\'t find definition of \'core_ctrl_we\' in dotted variable: \'dut.core_ctrl_we\'\n               dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);\n                                                         ^~~~~~~~~~~~\n%Error: Exiting due to 32 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_prince_core();




  parameter DEBUG     = 0;
  parameter DUMP_WAIT = 0;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;





  reg [31 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;
  reg          tb_monitor;

  reg           tb_clk;
  reg           tb_reset_n;
  reg           tb_encdec;
  reg           tb_init;
  reg           tb_next;
  wire          tb_ready;
  reg [127 : 0] tb_key;
  reg [63 : 0]  tb_block;
  wire [63 : 0] tb_result;





  prince_core dut(
                .clk(tb_clk),
                .reset_n(tb_reset_n),

                .encdec(tb_encdec),
                .next(tb_next),
                .ready(tb_ready),

                .key(tb_key),

                .block(tb_block),
                .result(tb_result)
               );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD;
      tb_clk = !tb_clk;
    end








  always
    begin : sys_monitor
      cycle_ctr = cycle_ctr + 1;
      #(CLK_PERIOD);
      if (tb_monitor)
        begin
          dump_dut_state();
        end
    end







  task dump_dut_state;
    begin
      $display("State of DUT");
      $display("------------");
      $display("Cycle: %08d", cycle_ctr);
      $display("Inputs and outputs:");
      $display("encdec = 0x%01x, next = 0x%01x", dut.encdec, dut.next);
      $display("key   = 0x%016x ", dut.key);
      $display("block = 0x%08x", dut.block);
      $display("ready  = 0x%01x", dut.ready);
      $display("result = 0x%08x", dut.result);
      $display("");
      $display("Internal states:");
      $display("k0: 0x%08x, k1: 0x%08x, kp: 0x%08x",
               dut.k0_reg, dut.k1_reg, dut.kp_reg);
      $display("");
      $display("core_input: 0x%08x", dut.prince_core_dp.core_input);
      $display("r0: 0x%08x, r1:  0x%08x, r2:  0x%08x",
               dut.prince_core_dp.r0, dut.prince_core_dp.r1, dut.prince_core_dp.r2);
      $display("r3: 0x%08x, r4:  0x%08x, r5:  0x%08x",
               dut.r3_reg, dut.prince_core_dp.r4, dut.prince_core_dp.r5);
      $display("mr: 0x%08x", dut.mr_reg);
      $display("r6: 0x%08x, r7:  0x%08x, r8:  0x%08x",
               dut.prince_core_dp.r6, dut.prince_core_dp.r7, dut.r8_reg);
      $display("r9: 0x%08x, r10: 0x%08x, r11: 0x%08x",
               dut.prince_core_dp.r9, dut.prince_core_dp.r10, dut.prince_core_dp.r11);
      $display("core_output: 0x%08x", dut.prince_core_dp.core_output);
      $display("state_reg: 0x%016x, state_new: 0x%016x, state_we: 0x%01x",
               dut.state_reg, dut.state_new, dut.state_we);
      $display("");
      $display("init_state: 0x%01x, update_state: 0x%01x",
               dut.init_state, dut.update_state);
      $display("core_ctrl_reg: 0x%02x, core_ctrl_new: 0x%02x, core_ctrl_we: 0x%01x",
               dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);
      $display("");
    end
  endtask







  task reset_dut;
    begin
      $display("*** DUT before reset:");
      dump_dut_state();
      $display("*** Toggling reset.");
      tb_reset_n = 0;
      #(2 * CLK_PERIOD);
      tb_reset_n = 1;
      $display("*** DUT after reset:");
      dump_dut_state();
    end
  endtask







  task display_test_result;
    begin
      if (error_ctr == 0)
        begin
          $display("*** All %02d test cases completed successfully", tc_ctr);
        end
      else
        begin
          $display("*** %02d tests completed - %02d test cases did not complete successfully.",
                   tc_ctr, error_ctr);
        end
    end
  endtask











  task wait_ready;
    begin
      #(2 * CLK_PERIOD);
      while (!tb_ready)
        begin
          #(CLK_PERIOD);
          if (DUMP_WAIT)
            begin
              dump_dut_state();
            end
        end
    end
  endtask








  task init_sim;
    begin
      cycle_ctr  = 0;
      error_ctr  = 0;
      tc_ctr     = 0;
      tb_monitor = 0;

      tb_clk     = 0;
      tb_reset_n = 1;
      tb_encdec  = 0;
      tb_next    = 0;
      tb_key     = 128'h0;
      tb_block   = 64'h0;
    end
  endtask









  task test(input integer tc, input reg [127 : 0] key,
            input reg [63 : 0] plaintext, input reg [63 : 0] ciphertext);
    begin
      tc_ctr = tc_ctr + 1;
      tb_monitor = 0;

      $display("*** TC%01d started.", tc);
      dump_dut_state();

      $display("*** TC%01d - encryption started.", tc);
      tb_key     = key;
      tb_encdec  = 1'h1;
      tb_block   = plaintext;
      tb_next    = 1'h1;
      #(CLK_PERIOD);
      tb_next    = 1'h0;
      wait_ready();
      $display("*** TC%01d - encryption completed.", tc);
      dump_dut_state();

      if (tb_result == ciphertext)
        $display("*** TC%01d correct ciphertext generated: 0x%016x",
                 tc, tb_result);
      else
        begin
          error_ctr = error_ctr + 1;
          $display("*** TC%01d incorrect ciphertext generated", tc);
          $display("*** TC%01d expected: 0x%016x", tc, ciphertext);
          $display("*** TC%01d got:      0x%016x", tc, tb_result);
        end

      $display("*** TC%01d - decryption started.", tc);
      tb_key    = key;
      tb_block  = ciphertext;
      tb_encdec = 1'h0;
      tb_next   = 1'h1;
      #(CLK_PERIOD);
      tb_next    = 1'h0;
      wait_ready();
      $display("*** TC%01d - decryption completed.", tc);

      if (tb_result == plaintext)
        $display("*** TC%01d correct plaintext generated: 0x%016x",
                 tc, tb_result);
      else
        begin
          error_ctr = error_ctr + 1;
          $display("*** TC%01d incorrect plaintext generated", tc);
          $display("*** TC%01d expected: 0x%016x", tc, plaintext);
          $display("*** TC%01d got:      0x%016x", tc, tb_result);
        end

      tb_monitor = 0;

      $display("*** TC%01d completed.", tc);
      $display("");
    end
  endtask







  initial
    begin : prince_core_test
      $display("*** Simulation of PRINCE core started.");
      $display("");

      init_sim();
      reset_dut();

      test(1, 128'h00000000_00000000_00000000_00000000,
           64'h00000000_00000000, 64'h818665aa_0d02dfda);

      test(2, 128'h00000000_00000000_00000000_00000000,
           64'hffffffff_ffffffff, 64'h604ae6ca_03c20ada);

      test(3, 128'hffffffff_ffffffff_00000000_00000000,
           64'h00000000_00000000, 64'h9fb51935_fc3df524);

      test(4, 128'h00000000_00000000_ffffffff_ffffffff,
           64'h00000000_00000000, 64'h78a54cbe_737bb7ef);

      test(5, 128'h00000000_00000000_fedcba98_76543210,
           64'h01234567_89abcdef, 64'hae25ad3c_a8fa9ccf);

      test(6, 128'h00112233_44556677_8899aabb_ccddeeff,
           64'h01234567_89abcdef, 64'hd6dcb597_8de756ee);

      test(7, 128'h01122334_45566778_899aabbc_cddeeff0,
           64'h01234567_89abcdef, 64'h392f599f_46761cd3);

      test(8, 128'h01122334_45566778_899aabbc_cddeeff0,
           64'hf0123456_789abcde, 64'h4fb5e332_b9b409bb);

      test(9, 128'hd8cdb780_70b4c55a_818665aa_0d02dfda,
           64'h69c4e0d8_6a7b0430, 64'h43c6b256_d79de7e8);

      display_test_result();
      $display("");
      $display("*** Simulation of PRINCE core completed.");
      $finish;
    end
endmodule
module tb_prince_core();





  parameter DEBUG     = 0;
  parameter DUMP_WAIT = 0;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;





  reg [31 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;
  reg          tb_monitor;

  reg           tb_clk;
  reg           tb_reset_n;
  reg           tb_encdec;
  reg           tb_init;
  reg           tb_next;
  wire          tb_ready;
  reg [127 : 0] tb_key;
  reg [63 : 0]  tb_block;
  wire [63 : 0] tb_result;





  prince_core dut(
                .clk(tb_clk),
                .reset_n(tb_reset_n),

                .encdec(tb_encdec),
                .next(tb_next),
                .ready(tb_ready),

                .key(tb_key),

                .block(tb_block),
                .result(tb_result)
               );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD;
      tb_clk = !tb_clk;
    end








  always
    begin : sys_monitor
      cycle_ctr = cycle_ctr + 1;
      #(CLK_PERIOD);
      if (tb_monitor)
        begin
          dump_dut_state();
        end
    end







  task dump_dut_state;
    begin
      $display("State of DUT");
      $display("------------");
      $display("Cycle: %08d", cycle_ctr);
      $display("Inputs and outputs:");
      $display("encdec = 0x%01x, next = 0x%01x", dut.encdec, dut.next);
      $display("key   = 0x%016x ", dut.key);
      $display("block = 0x%08x", dut.block);
      $display("ready  = 0x%01x", dut.ready);
      $display("result = 0x%08x", dut.result);
      $display("");
      $display("Internal states:");
      $display("k0: 0x%08x, k1: 0x%08x, kp: 0x%08x",
               dut.k0_reg, dut.k1_reg, dut.kp_reg);
      $display("");
      $display("core_input: 0x%08x", dut.prince_core_dp.core_input);
      $display("r0: 0x%08x, r1:  0x%08x, r2:  0x%08x",
               dut.prince_core_dp.r0, dut.prince_core_dp.r1, dut.prince_core_dp.r2);
      $display("r3: 0x%08x, r4:  0x%08x, r5:  0x%08x",
               dut.r3_reg, dut.prince_core_dp.r4, dut.prince_core_dp.r5);
      $display("mr: 0x%08x", dut.mr_reg);
      $display("r6: 0x%08x, r7:  0x%08x, r8:  0x%08x",
               dut.prince_core_dp.r6, dut.prince_core_dp.r7, dut.r8_reg);
      $display("r9: 0x%08x, r10: 0x%08x, r11: 0x%08x",
               dut.prince_core_dp.r9, dut.prince_core_dp.r10, dut.prince_core_dp.r11);
      $display("core_output: 0x%08x", dut.prince_core_dp.core_output);
      $display("state_reg: 0x%016x, state_new: 0x%016x, state_we: 0x%01x",
               dut.state_reg, dut.state_new, dut.state_we);
      $display("");
      $display("init_state: 0x%01x, update_state: 0x%01x",
               dut.init_state, dut.update_state);
      $display("core_ctrl_reg: 0x%02x, core_ctrl_new: 0x%02x, core_ctrl_we: 0x%01x",
               dut.core_ctrl_reg, dut.core_ctrl_new, dut.core_ctrl_we);
      $display("");
    end
  endtask







  task reset_dut;
    begin
      $display("*** DUT before reset:");
      dump_dut_state();
      $display("*** Toggling reset.");
      tb_reset_n = 0;
      #(2 * CLK_PERIOD);
      tb_reset_n = 1;
      $display("*** DUT after reset:");
      dump_dut_state();
    end
  endtask







  task display_test_result;
    begin
      if (error_ctr == 0)
        begin
          $display("*** All %02d test cases completed successfully", tc_ctr);
        end
      else
        begin
          $display("*** %02d tests completed - %02d test cases did not complete successfully.",
                   tc_ctr, error_ctr);
        end
    end
  endtask











  task wait_ready;
    begin
      #(2 * CLK_PERIOD);
      while (!tb_ready)
        begin
          #(CLK_PERIOD);
          if (DUMP_WAIT)
            begin
              dump_dut_state();
            end
        end
    end
  endtask








  task init_sim;
    begin
      cycle_ctr  = 0;
      error_ctr  = 0;
      tc_ctr     = 0;
      tb_monitor = 0;

      tb_clk     = 0;
      tb_reset_n = 1;
      tb_encdec  = 0;
      tb_next    = 0;
      tb_key     = 128'h0;
      tb_block   = 64'h0;
    end
  endtask









  task test(input integer tc, input reg [127 : 0] key,
            input reg [63 : 0] plaintext, input reg [63 : 0] ciphertext);
    begin
      tc_ctr = tc_ctr + 1;
      tb_monitor = 0;

      $display("*** TC%01d started.", tc);
      dump_dut_state();

      $display("*** TC%01d - encryption started.", tc);
      tb_key     = key;
      tb_encdec  = 1'h1;
      tb_block   = plaintext;
      tb_next    = 1'h1;
      #(CLK_PERIOD);
      tb_next    = 1'h0;
      wait_ready();
      $display("*** TC%01d - encryption completed.", tc);
      dump_dut_state();

      if (tb_result == ciphertext)
        $display("*** TC%01d correct ciphertext generated: 0x%016x",
                 tc, tb_result);
      else
        begin
          error_ctr = error_ctr + 1;
          $display("*** TC%01d incorrect ciphertext generated", tc);
          $display("*** TC%01d expected: 0x%016x", tc, ciphertext);
          $display("*** TC%01d got:      0x%016x", tc, tb_result);
        end

      $display("*** TC%01d - decryption started.", tc);
      tb_key    = key;
      tb_block  = ciphertext;
      tb_encdec = 1'h0;
      tb_next   = 1'h1;
      #(CLK_PERIOD);
      tb_next    = 1'h0;
      wait_ready();
      $display("*** TC%01d - decryption completed.", tc);

      if (tb_result == plaintext)
        $display("*** TC%01d correct plaintext generated: 0x%016x",
                 tc, tb_result);
      else
        begin
          error_ctr = error_ctr + 1;
          $display("*** TC%01d incorrect plaintext generated", tc);
          $display("*** TC%01d expected: 0x%016x", tc, plaintext);
          $display("*** TC%01d got:      0x%016x", tc, tb_result);
        end

      tb_monitor = 0;

      $display("*** TC%01d completed.", tc);
      $display("");
    end
  endtask







  initial
    begin : prince_core_test
      $display("*** Simulation of PRINCE core started.");
      $display("");

      init_sim();
      reset_dut();

      test(1, 128'h00000000_00000000_00000000_00000000,
           64'h00000000_00000000, 64'h818665aa_0d02dfda);

      test(2, 128'h00000000_00000000_00000000_00000000,
           64'hffffffff_ffffffff, 64'h604ae6ca_03c20ada);

      test(3, 128'hffffffff_ffffffff_00000000_00000000,
           64'h00000000_00000000, 64'h9fb51935_fc3df524);

      test(4, 128'h00000000_00000000_ffffffff_ffffffff,
           64'h00000000_00000000, 64'h78a54cbe_737bb7ef);

      test(5, 128'h00000000_00000000_fedcba98_76543210,
           64'h01234567_89abcdef, 64'hae25ad3c_a8fa9ccf);

      test(6, 128'h00112233_44556677_8899aabb_ccddeeff,
           64'h01234567_89abcdef, 64'hd6dcb597_8de756ee);

      test(7, 128'h01122334_45566778_899aabbc_cddeeff0,
           64'h01234567_89abcdef, 64'h392f599f_46761cd3);

      test(8, 128'h01122334_45566778_899aabbc_cddeeff0,
           64'hf0123456_789abcde, 64'h4fb5e332_b9b409bb);

      test(9, 128'hd8cdb780_70b4c55a_818665aa_0d02dfda,
           64'h69c4e0d8_6a7b0430, 64'h43c6b256_d79de7e8);

      display_test_result();
      $display("");
      $display("*** Simulation of PRINCE core completed.");
      $finish;
    end
endmodule