data/full_repos/permissive/147690299/lab/28_latch/rtl/lab_top.v
1: b"%Error: data/full_repos/permissive/147690299/lab/28_latch/rtl/lab_top.v:14: Cannot find file containing module: 'case_inferred_latch'\n    case_inferred_latch  case_inferred_latch (.d0(idata0), .d1(idata1), .d2(idata2), .sel(sel), .y(case_latch));\n    ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147690299/lab/28_latch/rtl,data/full_repos/permissive/147690299/case_inferred_latch\n             data/full_repos/permissive/147690299/lab/28_latch/rtl,data/full_repos/permissive/147690299/case_inferred_latch.v\n             data/full_repos/permissive/147690299/lab/28_latch/rtl,data/full_repos/permissive/147690299/case_inferred_latch.sv\n             case_inferred_latch\n             case_inferred_latch.v\n             case_inferred_latch.sv\n             obj_dir/case_inferred_latch\n             obj_dir/case_inferred_latch.v\n             obj_dir/case_inferred_latch.sv\n%Error: data/full_repos/permissive/147690299/lab/28_latch/rtl/lab_top.v:15: Cannot find file containing module: 'mux_case_correct'\n    mux_case_correct     mux_case_correct    (.d0(idata0), .d1(idata1), .d2(idata2), .sel(sel), .y(case_corrt));\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/147690299/lab/28_latch/rtl/lab_top.v:16: Cannot find file containing module: 'mod_latch'\n    mod_latch            mod_latch           (.d (idata0), .le(le ),                            .y(latch)     );\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module lab_top
(
    input        clk,
    input  [1:0] idata0,
    input  [1:0] idata1,
    input  [1:0] idata2,
    input  [1:0] sel,
    input        le,
    output [1:0] case_latch,
    output [1:0] case_corrt,
    output [1:0] latch
);
    case_inferred_latch  case_inferred_latch (.d0(idata0), .d1(idata1), .d2(idata2), .sel(sel), .y(case_latch));
    mux_case_correct     mux_case_correct    (.d0(idata0), .d1(idata1), .d2(idata2), .sel(sel), .y(case_corrt));
    mod_latch            mod_latch           (.d (idata0), .le(le ),                            .y(latch)     );

endmodule
module lab_top
(
    input        clk,
    input  [1:0] idata0,
    input  [1:0] idata1,
    input  [1:0] idata2,
    input  [1:0] sel,
    input        le,
    output [1:0] case_latch,
    output [1:0] case_corrt,
    output [1:0] latch
);

    case_inferred_latch  case_inferred_latch (.d0(idata0), .d1(idata1), .d2(idata2), .sel(sel), .y(case_latch));
    mux_case_correct     mux_case_correct    (.d0(idata0), .d1(idata1), .d2(idata2), .sel(sel), .y(case_corrt));
    mod_latch            mod_latch           (.d (idata0), .le(le ),                            .y(latch)     );

endmodule