data/full_repos/permissive/211878730/atlys/led/blink.v
1: b'%Warning-WIDTH: data/full_repos/permissive/211878730/atlys/led/blink.v:13: Operator EQ expects 27 bits on the LHS, but LHS\'s VARREF \'clk\' generates 1 bits.\n                                                                         : ... In instance blink\n  if (clk == 27\'d99999999) begin\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module blink(
	input  wire clk,
	output wire led
    );
	
	reg [26:0] cnt;
	assign led = cnt[26];
	
	always @(posedge clk) begin
		if (clk == 27'd99999999) begin
			cnt <= 0;
		end else begin
			cnt <= cnt + 1'b1;
		end
	end
endmodule
module blink(
	input  wire clk,
	output wire led
    );

	
	reg [26:0] cnt;
	assign led = cnt[26];
	
	always @(posedge clk) begin
		if (clk == 27'd99999999) begin
			cnt <= 0;
		end else begin
			cnt <= cnt + 1'b1;
		end
	end
endmodule