data/full_repos/permissive/125927162/VGA/vga.v
data/verilator_xmls/db30ef12-fdce-4ae8-922d-eb1092452566.xml
module vga (clk, rst, hs, vs, draw, x, y);
   localparam width = 800;
   localparam height = 525;
   
   input clk;
   input rst;
   output vs;
   output hs;
   output wire draw;
   output reg [$clog2(width + 1) - 1:0] x;
   output reg [$clog2(height + 1) - 1:0] y;

   always @ (posedge clk, posedge rst) begin
      if (rst) begin
	 x <= 0;
	 y <= 0;
      end
      else begin
	 if (x == width - 1) begin
	    x <= 0;
	    if (y == height - 1)
	      y <= 0;
	    else
	      y <= y + 1;
	 end
	 else
	   x <= x + 1;
      end
   end

   assign draw = (x < 640) && (y < 480);
   assign hs = ~((x >= 656) && (x < 752));
   assign vs = ~((y == 490) || (y == 491)); 
endmodule
module vga (clk, rst, hs, vs, draw, x, y);

   localparam width = 800;
   localparam height = 525;
   
   input clk;
   input rst;
   output vs;
   output hs;
   output wire draw;
   output reg [$clog2(width + 1) - 1:0] x;
   output reg [$clog2(height + 1) - 1:0] y;

   always @ (posedge clk, posedge rst) begin
      if (rst) begin
	 x <= 0;
	 y <= 0;
      end
      else begin
	 if (x == width - 1) begin
	    x <= 0;
	    if (y == height - 1)
	      y <= 0;
	    else
	      y <= y + 1;
	 end
	 else
	   x <= x + 1;
      end
   end

   assign draw = (x < 640) && (y < 480);
   assign hs = ~((x >= 656) && (x < 752));
   assign vs = ~((y == 490) || (y == 491)); 
endmodule