data/full_repos/permissive/205841227/verilog/include/mm_defines.vh
 line:6: before: "function"
data/verilator_xmls/ecb53301-4ffd-4f83-91e7-1da5475c3deb.xml
function integer log2;
input [31:0] value;
reg [31:0] i;
reg [31:0] t;
begin
   t = 1;
   for (i = 0; t < value; i = i + 1)  
	t = t << 1;
   log2 = i;
end
endfunction
function integer log2;

input [31:0] value;
reg [31:0] i;
reg [31:0] t;
begin
   t = 1;
   for (i = 0; t < value; i = i + 1)  
	t = t << 1;
   log2 = i;
end
endfunction