data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/sections/output-section.v
 line:39: before: "wire"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/sections/output-section.v:16: Signal definition not found, creating implicitly: \'to_j_and_k\'\nassign to_j_and_k = (feedback | ld);\n       ^~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/sections/output-section.v:18: Signal definition not found, creating implicitly: \'to_k\'\nassign to_j = ~(ld & to_k);\n                     ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/sections/output-section.v:18: Signal definition not found, creating implicitly: \'to_j\'\n                                                                                                                          : ... Suggested alternative: \'to_k\'\nassign to_j = ~(ld & to_k);\n       ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/sections/output-section.v:21: Signal definition not found, creating implicitly: \'j\'\nassign j = (to_j & to_j_and_k);\n       ^\n%Warning-IMPLICIT: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/sections/output-section.v:22: Signal definition not found, creating implicitly: \'k\'\nassign k = (to_k & to_j_and_k);\n       ^\n%Error: data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/sections/output-section.v:24: Cannot find file containing module: \'jk_flip_flop\'\njk_flip_flop JK (\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/sections,data/full_repos/permissive/174155074/jk_flip_flop\n             data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/sections,data/full_repos/permissive/174155074/jk_flip_flop.v\n             data/full_repos/permissive/174155074/sequential-logic/counters/jeff-74x161/sections,data/full_repos/permissive/174155074/jk_flip_flop.sv\n             jk_flip_flop\n             jk_flip_flop.v\n             jk_flip_flop.sv\n             obj_dir/jk_flip_flop\n             obj_dir/jk_flip_flop.v\n             obj_dir/jk_flip_flop.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module output_section (
    input  clr_bar,
    input  ld,
    input  feedback,
    input  clk,
    input  data,
    output q
);


wire NOTHING;

assign to_j_and_k = (feedback | ld);

assign to_j = ~(ld & to_k);
assign to_k = ~(data & ld);
 
assign j = (to_j & to_j_and_k);
assign k = (to_k & to_j_and_k);

jk_flip_flop JK (
    .clk(clk),       
    .clr_bar(clr_bar),   
    .j(j),        
    .k(k),        
    .q(q),    
    .q_bar(NOTHING)     
);

endmodule
module output_section (
    input  clr_bar,
    input  ld,
    input  feedback,
    input  clk,
    input  data,
    output q
);



wire NOTHING;

assign to_j_and_k = (feedback | ld);

assign to_j = ~(ld & to_k);
assign to_k = ~(data & ld);
 
assign j = (to_j & to_j_and_k);
assign k = (to_k & to_j_and_k);

jk_flip_flop JK (
    .clk(clk),       
    .clr_bar(clr_bar),   
    .j(j),        
    .k(k),        
    .q(q),    
    .q_bar(NOTHING)     
);

endmodule