data/full_repos/permissive/163534413/SerialIn.v
data/verilator_xmls/8f40d0bf-0eb0-457d-93d9-67af287c2ec1.xml
module SerialIn(SerialReady, SerialData, SerialClock, DataOut, DataWrite);
	
	input SerialReady, SerialData, SerialClock;
	output reg [7:0] DataOut;
	output reg DataWrite;
	
	reg [2:0] dataCounter;
	
	always @(negedge SerialClock or posedge SerialReady) begin
		if (SerialReady && !SerialClock) begin
			DataOut[dataCounter] = SerialData;
			dataCounter = dataCounter + 1;
			if (dataCounter == 0) DataWrite = 1;
		end
		if (SerialReady && SerialClock) DataWrite = 0;
	end

endmodule
module SerialIn(SerialReady, SerialData, SerialClock, DataOut, DataWrite);

	
	input SerialReady, SerialData, SerialClock;
	output reg [7:0] DataOut;
	output reg DataWrite;
	
	reg [2:0] dataCounter;
	
	always @(negedge SerialClock or posedge SerialReady) begin
		if (SerialReady && !SerialClock) begin
			DataOut[dataCounter] = SerialData;
			dataCounter = dataCounter + 1;
			if (dataCounter == 0) DataWrite = 1;
		end
		if (SerialReady && SerialClock) DataWrite = 0;
	end

endmodule