data/full_repos/permissive/143278/ivltests/pr1868991a.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1868991a.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 if (select_dcs_mpr !== idx) begin\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/pr1868991a.v:16: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s VARREF \'idx\' generates 32 bits.\n                                                                          : ... In instance test\n  dtlreq_addr = idx;\n              ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

   reg [31:0] mpr1[35-1:16];
   reg [29:0] dtlreq_addr;
   wire [7-1:0] select_mpr_inx = dtlreq_addr[7-1:0];
   wire [31:0]	select_dcs_mpr = mpr1[select_mpr_inx];

   integer	idx;
   initial begin
      for (idx = 16 ; idx < 35 ; idx = idx+1)
	mpr1[idx] = idx;

      for (idx = 16 ; idx < 35 ; idx = idx+1) begin
	 dtlreq_addr = idx;
	 #1 if (select_dcs_mpr !== idx) begin
	    $display("FAILED - select_dcs_mpr=%d, idx=%d", select_dcs_mpr, idx);
	    $finish;
	 end
      end

      $display("PASSED");
   end
endmodule
module test();


   reg [31:0] mpr1[35-1:16];
   reg [29:0] dtlreq_addr;
   wire [7-1:0] select_mpr_inx = dtlreq_addr[7-1:0];
   wire [31:0]	select_dcs_mpr = mpr1[select_mpr_inx];

   integer	idx;
   initial begin
      for (idx = 16 ; idx < 35 ; idx = idx+1)
	mpr1[idx] = idx;

      for (idx = 16 ; idx < 35 ; idx = idx+1) begin
	 dtlreq_addr = idx;
	 #1 if (select_dcs_mpr !== idx) begin
	    $display("FAILED - select_dcs_mpr=%d, idx=%d", select_dcs_mpr, idx);
	    $finish;
	 end
      end

      $display("PASSED");
   end
endmodule