data/full_repos/permissive/15946916/Lab6/lab6_6_test.v
 line:131: before: "$"
1: b'%Error: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:4: Cannot find include file: lab6_6.v\n`include "lab6_6.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/15946916/Lab6,data/full_repos/permissive/15946916/lab6_6.v\n             data/full_repos/permissive/15946916/Lab6,data/full_repos/permissive/15946916/lab6_6.v.v\n             data/full_repos/permissive/15946916/Lab6,data/full_repos/permissive/15946916/lab6_6.v.sv\n             lab6_6.v\n             lab6_6.v.v\n             lab6_6.v.sv\n             obj_dir/lab6_6.v\n             obj_dir/lab6_6.v.v\n             obj_dir/lab6_6.v.sv\n%Error: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:15: Unsupported or unknown PLI call: $monitor\n  $monitor($time, "\\tA=%d\\tB=%d\\tCin=%b\\tS=%d\\tCout=%b", A, B, C0, S, Cout);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/15946916/Lab6/lab6_6_test.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Error: Exiting due to 2 error(s), 18 warning(s)\n'
module ripple_carry_adder_test();
    reg  [31:0]    A, B;
	reg	   C0;
    wire  [31:0] S; 
	wire Cout;

    ripple_carry_adder_32bit test(S,Cout,A,B,C0);
initial begin
		$monitor($time, "\tA=%d\tB=%d\tCin=%b\tS=%d\tCout=%b", A, B, C0, S, Cout);
		
		A = 0;		B = 0;		C0 = 0;
		#1
		A = 0;		B = 0;		C0 = 1;
		#1
		A = 0;		B = 1;		C0 = 0;
		#1
		A = 1;		B = 0;		C0 = 0;
		#1
		A = 1;		B = 1;		C0 = 0;
		#1
		A = 1;		B = 1;		C0 = 1;
		#1
		A = 16777215;	B = 16777215;	C0 = 0;
		#1
		A = 16777215;	B = 16777215;	C0 = 1;
		#1
		A = 4294967295;	B = 0;		C0 = 0;
		#1
		A = 4294967295;	B = 0;		C0 = 1;
		#1
		A = 4294967295;	B = 1;		C0 = 0;
		#1
		A = 4294967295;	B = 1;		C0 = 1;
		#1
		A = 0;		B = 4294967295;	C0 = 0;
		#1
		A = 0;		B = 4294967295;	C0 = 1;
		#1
		A = 1;		B = 4294967295;	C0 = 0;
		#1
		A = 1;		B = 4294967295;	C0 = 1;
		#1
		A = 4294967295;	B = 4294967295;	C0 = 0;
		#1
		A = 4294967295;	B = 4294967295;	C0 = 1;
		#1
		$finish;
	end
endmodule
module ripple_carry_adder_test();

    reg  [31:0]    A, B;
	reg	   C0;
    wire  [31:0] S; 
	wire Cout;

    ripple_carry_adder_32bit test(S,Cout,A,B,C0);
initial begin
		$monitor($time, "\tA=%d\tB=%d\tCin=%b\tS=%d\tCout=%b", A, B, C0, S, Cout);
		
		A = 0;		B = 0;		C0 = 0;
		#1
		A = 0;		B = 0;		C0 = 1;
		#1
		A = 0;		B = 1;		C0 = 0;
		#1
		A = 1;		B = 0;		C0 = 0;
		#1
		A = 1;		B = 1;		C0 = 0;
		#1
		A = 1;		B = 1;		C0 = 1;
		#1
		A = 16777215;	B = 16777215;	C0 = 0;
		#1
		A = 16777215;	B = 16777215;	C0 = 1;
		#1
		A = 4294967295;	B = 0;		C0 = 0;
		#1
		A = 4294967295;	B = 0;		C0 = 1;
		#1
		A = 4294967295;	B = 1;		C0 = 0;
		#1
		A = 4294967295;	B = 1;		C0 = 1;
		#1
		A = 0;		B = 4294967295;	C0 = 0;
		#1
		A = 0;		B = 4294967295;	C0 = 1;
		#1
		A = 1;		B = 4294967295;	C0 = 0;
		#1
		A = 1;		B = 4294967295;	C0 = 1;
		#1
		A = 4294967295;	B = 4294967295;	C0 = 0;
		#1
		A = 4294967295;	B = 4294967295;	C0 = 1;
		#1
		$finish;
	end
endmodule