data/full_repos/permissive/169574047/bahavior/bahavior.srcs/sources_1/new/loop_statement.v
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1: b'%Error: data/full_repos/permissive/169574047/bahavior/bahavior.srcs/sources_1/new/loop_statement.v:43: syntax error, unexpected continue, expecting IDENTIFIER or \'=\' or do or final\nreg continue;\n    ^~~~~~~~\n%Error: data/full_repos/permissive/169574047/bahavior/bahavior.srcs/sources_1/new/loop_statement.v:49: syntax error, unexpected \'=\', expecting \';\'\n    continue = 1\'b1;\n             ^\n%Error: data/full_repos/permissive/169574047/bahavior/bahavior.srcs/sources_1/new/loop_statement.v:51: syntax error, unexpected continue, expecting TYPE-IDENTIFIER\n    while((i<16) && continue)    \n                    ^~~~~~~~\n%Error: data/full_repos/permissive/169574047/bahavior/bahavior.srcs/sources_1/new/loop_statement.v:58: syntax error, unexpected \'=\', expecting IDENTIFIER\n         i = i +1;\n           ^\n%Error: data/full_repos/permissive/169574047/bahavior/bahavior.srcs/sources_1/new/loop_statement.v:112: syntax error, unexpected \'@\'\n            @(posedge clock)buffer[i] = data;    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/169574047/bahavior/bahavior.srcs/sources_1/new/loop_statement.v:123: Unsupported: Ignoring delay on this delayed statement.\n    forever #10 clock = ~clock;  \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/169574047/bahavior/bahavior.srcs/sources_1/new/loop_statement.v:130: syntax error, unexpected \'@\'\n    forever @(posedge clock) data = data >> 2;\n            ^\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module loop_statement;



integer count;
initial
begin
    count = 0;
    while (count < 128)
    begin
        $display("Count = %d", count);
        count = count + 1;
    end
end


`define TRUE 1'b1
`define FALSE 1'b0
reg [15:0] flag;
integer i;
reg continue;

initial
begin
    flag = 16'b0010_0000_0000_0000;
    i = 0;
    continue = `TRUE;
    
    while((i<16) && continue)
    begin
        if(flag[i])
        begin
            $display("Encounterd a TURE bit at element number %d",i);
            continue = `FALSE;
        end
         i = i +1;
    end
end


integer count2;
initial
begin
    for(count2=0 ; count2<128 ; count2=count2+1)
        $display("Count2 = %d",count2);
end


`define MAX_STATES 32
integer state [0:`MAX_STATES-1];

initial
begin
    for(i=0 ; i<32 ; i=i+2)
        state[i] = 0;
    for(i=1 ; i<32 ; i=i+2)
        state[i] = 1;
end



integer count3;
initial
begin
    count3 = 0;
    repeat(128)
    begin
        $display("Count3 = %d", count3);
        count3 = count3 + 1;
    end
end




parameter cycles = 8;

reg data_start = 1;
reg [15:0] data;
reg clock;
reg [15:0] buffer [0:7];

always @(posedge clock)
begin
    if(data_start)
    begin
        i = 0;
        repeat(cycles)
        begin
            @(posedge clock)buffer[i] = data;
            i = i + 1;
        end
    end
end



initial
begin
    clock = 1'b0;
    forever #10 clock = ~clock;
end


initial
begin
    data = 16'b1111_0111_0011_0001;
    forever @(posedge clock) data = data >> 2;
end

endmodule
module loop_statement;




integer count;
initial
begin
    count = 0;
    while (count < 128)
    begin
        $display("Count = %d", count);
        count = count + 1;
    end
end


`define TRUE 1'b1
`define FALSE 1'b0
reg [15:0] flag;
integer i;
reg continue;

initial
begin
    flag = 16'b0010_0000_0000_0000;
    i = 0;
    continue = `TRUE;
    
    while((i<16) && continue)
    begin
        if(flag[i])
        begin
            $display("Encounterd a TURE bit at element number %d",i);
            continue = `FALSE;
        end
         i = i +1;
    end
end


integer count2;
initial
begin
    for(count2=0 ; count2<128 ; count2=count2+1)
        $display("Count2 = %d",count2);
end


`define MAX_STATES 32
integer state [0:`MAX_STATES-1];

initial
begin
    for(i=0 ; i<32 ; i=i+2)
        state[i] = 0;
    for(i=1 ; i<32 ; i=i+2)
        state[i] = 1;
end



integer count3;
initial
begin
    count3 = 0;
    repeat(128)
    begin
        $display("Count3 = %d", count3);
        count3 = count3 + 1;
    end
end




parameter cycles = 8;

reg data_start = 1;
reg [15:0] data;
reg clock;
reg [15:0] buffer [0:7];

always @(posedge clock)
begin
    if(data_start)
    begin
        i = 0;
        repeat(cycles)
        begin
            @(posedge clock)buffer[i] = data;
            i = i + 1;
        end
    end
end



initial
begin
    clock = 1'b0;
    forever #10 clock = ~clock;
end


initial
begin
    data = 16'b1111_0111_0011_0001;
    forever @(posedge clock) data = data >> 2;
end

endmodule