data/full_repos/permissive/122774145/vga_input/top.v
1: b'%Error: data/full_repos/permissive/122774145/vga_input/top.v:84: Cannot find file containing module: \'ddr2_idelay_ctrl_mod\'\n    ddr2_idelay_ctrl_mod #(\n    ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/122774145/vga_input,data/full_repos/permissive/122774145/ddr2_idelay_ctrl_mod\n             data/full_repos/permissive/122774145/vga_input,data/full_repos/permissive/122774145/ddr2_idelay_ctrl_mod.v\n             data/full_repos/permissive/122774145/vga_input,data/full_repos/permissive/122774145/ddr2_idelay_ctrl_mod.sv\n             ddr2_idelay_ctrl_mod\n             ddr2_idelay_ctrl_mod.v\n             ddr2_idelay_ctrl_mod.sv\n             obj_dir/ddr2_idelay_ctrl_mod\n             obj_dir/ddr2_idelay_ctrl_mod.v\n             obj_dir/ddr2_idelay_ctrl_mod.sv\n%Error: data/full_repos/permissive/122774145/vga_input/top.v:92: Cannot find file containing module: \'pll\'\n    pll pll (\n    ^~~\n%Error: data/full_repos/permissive/122774145/vga_input/top.v:99: Cannot find file containing module: \'debounce_rst\'\n    debounce_rst debounce_rst(\n    ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:141: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 11 bits.\n                                                                        : ... In instance top\n    wire [6:0] avg_addr = (x_position / 8);\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:168: Operator COND expects 15 bits on the Conditional True, but Conditional True\'s CONST \'14\'h0\' generates 14 bits.\n                                                                        : ... In instance top\n                    avg_r_a[avg_addr] <= ((avg_clear) ? (14\'b0) : (avg_r_a[avg_addr])) + r_in;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:168: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'r_in\' generates 8 bits.\n                                                                        : ... In instance top\n                    avg_r_a[avg_addr] <= ((avg_clear) ? (14\'b0) : (avg_r_a[avg_addr])) + r_in;\n                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:169: Operator COND expects 15 bits on the Conditional True, but Conditional True\'s CONST \'14\'h0\' generates 14 bits.\n                                                                        : ... In instance top\n                    avg_g_a[avg_addr] <= ((avg_clear) ? (14\'b0) : (avg_g_a[avg_addr])) + g_in;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:169: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'g_in\' generates 8 bits.\n                                                                        : ... In instance top\n                    avg_g_a[avg_addr] <= ((avg_clear) ? (14\'b0) : (avg_g_a[avg_addr])) + g_in;\n                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:170: Operator COND expects 15 bits on the Conditional True, but Conditional True\'s CONST \'14\'h0\' generates 14 bits.\n                                                                        : ... In instance top\n                    avg_b_a[avg_addr] <= ((avg_clear) ? (14\'b0) : (avg_b_a[avg_addr])) + b_in;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:170: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'b_in\' generates 8 bits.\n                                                                        : ... In instance top\n                    avg_b_a[avg_addr] <= ((avg_clear) ? (14\'b0) : (avg_b_a[avg_addr])) + b_in;\n                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:173: Operator COND expects 15 bits on the Conditional True, but Conditional True\'s CONST \'14\'h0\' generates 14 bits.\n                                                                        : ... In instance top\n                    avg_r_b[avg_addr] <= ((avg_clear) ? (14\'b0) : (avg_r_b[avg_addr])) + r_in;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:173: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'r_in\' generates 8 bits.\n                                                                        : ... In instance top\n                    avg_r_b[avg_addr] <= ((avg_clear) ? (14\'b0) : (avg_r_b[avg_addr])) + r_in;\n                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:174: Operator COND expects 15 bits on the Conditional True, but Conditional True\'s CONST \'14\'h0\' generates 14 bits.\n                                                                        : ... In instance top\n                    avg_g_b[avg_addr] <= ((avg_clear) ? (14\'b0) : (avg_g_b[avg_addr])) + g_in;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:174: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'g_in\' generates 8 bits.\n                                                                        : ... In instance top\n                    avg_g_b[avg_addr] <= ((avg_clear) ? (14\'b0) : (avg_g_b[avg_addr])) + g_in;\n                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:175: Operator COND expects 15 bits on the Conditional True, but Conditional True\'s CONST \'14\'h0\' generates 14 bits.\n                                                                        : ... In instance top\n                    avg_b_b[avg_addr] <= ((avg_clear) ? (14\'b0) : (avg_b_b[avg_addr])) + b_in;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:175: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'b_in\' generates 8 bits.\n                                                                        : ... In instance top\n                    avg_b_b[avg_addr] <= ((avg_clear) ? (14\'b0) : (avg_b_b[avg_addr])) + b_in;\n                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/122774145/vga_input/top.v:186: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 or 8 bits.\n                                                                        : ... In instance top\n    wire [5:0] char_sel = (avg_r_out + avg_g_out + avg_b_out) / 16; \n                        ^\n%Error: data/full_repos/permissive/122774145/vga_input/top.v:190: Cannot find file containing module: \'ascii_lut\'\n    ascii_lut ascii_lut(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/122774145/vga_input/top.v:195: Cannot find file containing module: \'vga_font\'\n    vga_font vga_font(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/122774145/vga_input/top.v:218: Cannot find file containing module: \'dvi_module\'\n    dvi_module dvi_module(  \n    ^~~~~~~~~~\n%Error: Exiting due to 6 error(s), 14 warning(s)\n'
module top(  

  inout          IIC_SCL_VIDEO,
  inout          IIC_SDA_VIDEO,
  

  input          VGA_IN_DATA_CLK,
  input  [7:0]   VGA_IN_BLUE,
  input  [7:0]   VGA_IN_GREEN,
  input  [7:0]   VGA_IN_RED,
  input          VGA_IN_HSOUT,
  input          VGA_IN_ODD_EVEN_B,
  input          VGA_IN_VSOUT,
  input          VGA_IN_SOGOUT,
  

  input          GPIO_SW_C,
  input          GPIO_SW_W,
  input          GPIO_SW_E,
  input          GPIO_SW_S,
  input          GPIO_SW_N,
  input  [7:0]   GPIO_DIP_SW,


  output [7:0]   GPIO_LED,
  output         GPIO_LED_C,
  output         GPIO_LED_W,
  output         GPIO_LED_E,
  output         GPIO_LED_S,
  output         GPIO_LED_N,
  

  output [11:0]  DVI_D,
  output         DVI_DE,
  output         DVI_H,
  output         DVI_RESET_B,
  output         DVI_V,
  output         DVI_XCLK_N,
  output         DVI_XCLK_P,
  input          DVI_GPIO1,
  

  input          FPGA_CPU_RESET_B,
  input          CLK_33MHZ_FPGA,
  input          CLK_27MHZ_FPGA
    );


    wire clk_33;
    wire clk_100;

    wire reset_in;
    wire reset_pll;
    wire reset;
    wire locked_pll;

    assign clk_33 = CLK_33MHZ_FPGA;
    assign reset_in = ~FPGA_CPU_RESET_B;
    

    localparam IODELAY_GRP = "IODELAY_MIG";
    localparam RST_SYNC_NUM = 25;
    ddr2_idelay_ctrl_mod #(
      .IODELAY_GRP(IODELAY_GRP),
      .RST_SYNC_NUM(RST_SYNC_NUM)
    ) ddr2_idelay_ctrl_mod (
      .clk_100MHz(clk_100),
      .rst(reset)
    );

    pll pll (
        .CLKIN1_IN(clk_33), 
        .RST_IN(reset_pll), 
        .CLKOUT0_OUT(clk_100),
        .LOCKED_OUT(locked_pll)
    );

    debounce_rst debounce_rst(
        .clk(clk_33),
        .noisy_rst(reset_in),
        .pll_locked(locked_pll),
        .clean_pll_rst(reset_pll),
        .clean_async_rst(reset)
    );

    
    wire iic_done;
    
    wire vs_in = VGA_IN_VSOUT;
    wire hs_in = VGA_IN_HSOUT;
    wire [7:0] r_in = VGA_IN_RED;
    wire [7:0] g_in = VGA_IN_GREEN;
    wire [7:0] b_in = VGA_IN_BLUE;
    wire pclk_in = VGA_IN_DATA_CLK;
    

    reg [14:0] avg_r_a [0:99]; 
    reg [14:0] avg_g_a [0:99];
    reg [14:0] avg_b_a [0:99];
    reg [14:0] avg_r_b [0:99]; 
    reg [14:0] avg_g_b [0:99];
    reg [14:0] avg_b_b [0:99];
    reg disp_buffer;
    reg [10:0] x_counter;
    reg [10:0] y_counter; 
    reg hs_last;
    reg vs_last;
    
    localparam x_offset = 11'd220;
    localparam y_offset = 11'd28;
    localparam x_size = 11'd800;
    localparam y_size = 11'd600;
    
    wire x_valid = ((x_counter >= x_offset)&&(x_counter < (x_offset + x_size))) ? 1 : 0;
    wire y_valid = ((y_counter >= y_offset)&&(y_counter < (y_offset + y_size))) ? 1 : 0;
    wire y_valid_output = ((y_counter >= (y_offset + 11'd16))&&(y_counter < (y_offset + y_size + 11'd16))) ? 1 : 0;
    wire [10:0] x_position = (x_valid) ? (x_counter - x_offset) : 11'd0;
    wire [10:0] y_position = (y_valid) ? (y_counter - y_offset) : 11'd0;
    
    wire [6:0] avg_addr = (x_position / 8);
    wire avg_clear = ((y_position[3:0] == 4'b0000)&&(x_position[2:0] == 3'b000)) ? 1 : 0;
    
    always@(posedge pclk_in)
    begin
        if (reset) begin
            vs_last <= 0;
            hs_last <= 0;
            x_counter <= 0;
            y_counter <= 0;
            disp_buffer <= 0;
        end
        else begin
            hs_last <= hs_in;
            vs_last <= vs_in;
            if ((hs_last == 1'b0)&&(hs_in == 1'b1)) begin
                x_counter <= 0;
                y_counter <= y_counter + 1;
                if (y_position[3:0] == 4'b1111)
                    disp_buffer <= ~disp_buffer;
            end else
                x_counter <= x_counter + 1;
            if ((vs_last == 1'b0)&&(vs_in == 1'b1)) begin
                y_counter <= 0;
            end
            if (x_valid && y_valid) begin
                if (disp_buffer) begin
                    avg_r_a[avg_addr] <= ((avg_clear) ? (14'b0) : (avg_r_a[avg_addr])) + r_in;
                    avg_g_a[avg_addr] <= ((avg_clear) ? (14'b0) : (avg_g_a[avg_addr])) + g_in;
                    avg_b_a[avg_addr] <= ((avg_clear) ? (14'b0) : (avg_b_a[avg_addr])) + b_in;
                end
                else begin
                    avg_r_b[avg_addr] <= ((avg_clear) ? (14'b0) : (avg_r_b[avg_addr])) + r_in;
                    avg_g_b[avg_addr] <= ((avg_clear) ? (14'b0) : (avg_g_b[avg_addr])) + g_in;
                    avg_b_b[avg_addr] <= ((avg_clear) ? (14'b0) : (avg_b_b[avg_addr])) + b_in;
                end
            end
        end
    end
    
    wire out_en = (x_valid & y_valid_output);
    
    wire [7:0] avg_r_out = disp_buffer ? avg_r_b[avg_addr][14:7] : avg_r_a[avg_addr][14:7];
    wire [7:0] avg_g_out = disp_buffer ? avg_g_b[avg_addr][14:7] : avg_g_a[avg_addr][14:7];
    wire [7:0] avg_b_out = disp_buffer ? avg_b_b[avg_addr][14:7] : avg_b_a[avg_addr][14:7];
    wire [5:0] char_sel = (avg_r_out + avg_g_out + avg_b_out) / 16; 
    wire [7:0] char;
    wire char_out;
    
    ascii_lut ascii_lut(
        .id(char_sel),
        .char(char)
    );
    
    vga_font vga_font(
        .clk(VGA_IN_DATA_CLK),
        .ascii_code(char),
        .row(y_position[3:0]),
        .col(x_position[2:0]),
        .pixel(char_out)
    );
    
    reg [7:0] char_r_out;
    reg [7:0] char_g_out;
    reg [7:0] char_b_out;
    
    always@(negedge VGA_IN_DATA_CLK)
    begin
        char_r_out <= (char_out) ? ((GPIO_DIP_SW[0]) ? (avg_r_out) : (8'hFF)) : (8'h00);
        char_g_out <= (char_out) ? ((GPIO_DIP_SW[0]) ? (avg_g_out) : (8'hFF)) : (8'h00);
        char_b_out <= (char_out) ? ((GPIO_DIP_SW[0]) ? (avg_b_out) : (8'hFF)) : (8'h00);
    end
    
    wire [7:0] r_out = (out_en) ? ((GPIO_DIP_SW[1]) ? (char_r_out) : (r_in)) : 8'h00;
    wire [7:0] g_out = (out_en) ? ((GPIO_DIP_SW[1]) ? (char_g_out) : (g_in)) : 8'h00;
    wire [7:0] b_out = (out_en) ? ((GPIO_DIP_SW[1]) ? (char_b_out) : (b_in)) : 8'h00;
    
    dvi_module dvi_module(  

        .dvi_vs(DVI_V),        
        .dvi_hs(DVI_H), 
        .dvi_d(DVI_D), 
        .dvi_xclk_p(DVI_XCLK_P), 
        .dvi_xclk_n(DVI_XCLK_N),
        .dvi_de(DVI_DE), 
        .dvi_reset_b(DVI_RESET_B),  
        .iic_done(iic_done), 
      

        .dvi_sda(IIC_SDA_VIDEO),
        .dvi_scl(IIC_SCL_VIDEO),
      

        .pixel_clk(VGA_IN_DATA_CLK), 
        .gpuclk_rst(reset), 
        .hsync(~VGA_IN_HSOUT),
        .vsync(~VGA_IN_VSOUT),
        .blank_b(out_en),
        .pixel_r(r_out),
        .pixel_b(b_out),
        .pixel_g(g_out)
    );


    assign GPIO_LED[7:0] = {char};
    assign GPIO_LED_C = iic_done;
    assign GPIO_LED_S = char_out;
    assign GPIO_LED_W = 0;
    assign GPIO_LED_N = 0;
    assign GPIO_LED_E = 0;
    
    
endmodule
module top(  

  inout          IIC_SCL_VIDEO,
  inout          IIC_SDA_VIDEO,
  

  input          VGA_IN_DATA_CLK,
  input  [7:0]   VGA_IN_BLUE,
  input  [7:0]   VGA_IN_GREEN,
  input  [7:0]   VGA_IN_RED,
  input          VGA_IN_HSOUT,
  input          VGA_IN_ODD_EVEN_B,
  input          VGA_IN_VSOUT,
  input          VGA_IN_SOGOUT,
  

  input          GPIO_SW_C,
  input          GPIO_SW_W,
  input          GPIO_SW_E,
  input          GPIO_SW_S,
  input          GPIO_SW_N,
  input  [7:0]   GPIO_DIP_SW,


  output [7:0]   GPIO_LED,
  output         GPIO_LED_C,
  output         GPIO_LED_W,
  output         GPIO_LED_E,
  output         GPIO_LED_S,
  output         GPIO_LED_N,
  

  output [11:0]  DVI_D,
  output         DVI_DE,
  output         DVI_H,
  output         DVI_RESET_B,
  output         DVI_V,
  output         DVI_XCLK_N,
  output         DVI_XCLK_P,
  input          DVI_GPIO1,
  

  input          FPGA_CPU_RESET_B,
  input          CLK_33MHZ_FPGA,
  input          CLK_27MHZ_FPGA
    );



    wire clk_33;
    wire clk_100;

    wire reset_in;
    wire reset_pll;
    wire reset;
    wire locked_pll;

    assign clk_33 = CLK_33MHZ_FPGA;
    assign reset_in = ~FPGA_CPU_RESET_B;
    

    localparam IODELAY_GRP = "IODELAY_MIG";
    localparam RST_SYNC_NUM = 25;
    ddr2_idelay_ctrl_mod #(
      .IODELAY_GRP(IODELAY_GRP),
      .RST_SYNC_NUM(RST_SYNC_NUM)
    ) ddr2_idelay_ctrl_mod (
      .clk_100MHz(clk_100),
      .rst(reset)
    );

    pll pll (
        .CLKIN1_IN(clk_33), 
        .RST_IN(reset_pll), 
        .CLKOUT0_OUT(clk_100),
        .LOCKED_OUT(locked_pll)
    );

    debounce_rst debounce_rst(
        .clk(clk_33),
        .noisy_rst(reset_in),
        .pll_locked(locked_pll),
        .clean_pll_rst(reset_pll),
        .clean_async_rst(reset)
    );

    
    wire iic_done;
    
    wire vs_in = VGA_IN_VSOUT;
    wire hs_in = VGA_IN_HSOUT;
    wire [7:0] r_in = VGA_IN_RED;
    wire [7:0] g_in = VGA_IN_GREEN;
    wire [7:0] b_in = VGA_IN_BLUE;
    wire pclk_in = VGA_IN_DATA_CLK;
    

    reg [14:0] avg_r_a [0:99]; 
    reg [14:0] avg_g_a [0:99];
    reg [14:0] avg_b_a [0:99];
    reg [14:0] avg_r_b [0:99]; 
    reg [14:0] avg_g_b [0:99];
    reg [14:0] avg_b_b [0:99];
    reg disp_buffer;
    reg [10:0] x_counter;
    reg [10:0] y_counter; 
    reg hs_last;
    reg vs_last;
    
    localparam x_offset = 11'd220;
    localparam y_offset = 11'd28;
    localparam x_size = 11'd800;
    localparam y_size = 11'd600;
    
    wire x_valid = ((x_counter >= x_offset)&&(x_counter < (x_offset + x_size))) ? 1 : 0;
    wire y_valid = ((y_counter >= y_offset)&&(y_counter < (y_offset + y_size))) ? 1 : 0;
    wire y_valid_output = ((y_counter >= (y_offset + 11'd16))&&(y_counter < (y_offset + y_size + 11'd16))) ? 1 : 0;
    wire [10:0] x_position = (x_valid) ? (x_counter - x_offset) : 11'd0;
    wire [10:0] y_position = (y_valid) ? (y_counter - y_offset) : 11'd0;
    
    wire [6:0] avg_addr = (x_position / 8);
    wire avg_clear = ((y_position[3:0] == 4'b0000)&&(x_position[2:0] == 3'b000)) ? 1 : 0;
    
    always@(posedge pclk_in)
    begin
        if (reset) begin
            vs_last <= 0;
            hs_last <= 0;
            x_counter <= 0;
            y_counter <= 0;
            disp_buffer <= 0;
        end
        else begin
            hs_last <= hs_in;
            vs_last <= vs_in;
            if ((hs_last == 1'b0)&&(hs_in == 1'b1)) begin
                x_counter <= 0;
                y_counter <= y_counter + 1;
                if (y_position[3:0] == 4'b1111)
                    disp_buffer <= ~disp_buffer;
            end else
                x_counter <= x_counter + 1;
            if ((vs_last == 1'b0)&&(vs_in == 1'b1)) begin
                y_counter <= 0;
            end
            if (x_valid && y_valid) begin
                if (disp_buffer) begin
                    avg_r_a[avg_addr] <= ((avg_clear) ? (14'b0) : (avg_r_a[avg_addr])) + r_in;
                    avg_g_a[avg_addr] <= ((avg_clear) ? (14'b0) : (avg_g_a[avg_addr])) + g_in;
                    avg_b_a[avg_addr] <= ((avg_clear) ? (14'b0) : (avg_b_a[avg_addr])) + b_in;
                end
                else begin
                    avg_r_b[avg_addr] <= ((avg_clear) ? (14'b0) : (avg_r_b[avg_addr])) + r_in;
                    avg_g_b[avg_addr] <= ((avg_clear) ? (14'b0) : (avg_g_b[avg_addr])) + g_in;
                    avg_b_b[avg_addr] <= ((avg_clear) ? (14'b0) : (avg_b_b[avg_addr])) + b_in;
                end
            end
        end
    end
    
    wire out_en = (x_valid & y_valid_output);
    
    wire [7:0] avg_r_out = disp_buffer ? avg_r_b[avg_addr][14:7] : avg_r_a[avg_addr][14:7];
    wire [7:0] avg_g_out = disp_buffer ? avg_g_b[avg_addr][14:7] : avg_g_a[avg_addr][14:7];
    wire [7:0] avg_b_out = disp_buffer ? avg_b_b[avg_addr][14:7] : avg_b_a[avg_addr][14:7];
    wire [5:0] char_sel = (avg_r_out + avg_g_out + avg_b_out) / 16; 
    wire [7:0] char;
    wire char_out;
    
    ascii_lut ascii_lut(
        .id(char_sel),
        .char(char)
    );
    
    vga_font vga_font(
        .clk(VGA_IN_DATA_CLK),
        .ascii_code(char),
        .row(y_position[3:0]),
        .col(x_position[2:0]),
        .pixel(char_out)
    );
    
    reg [7:0] char_r_out;
    reg [7:0] char_g_out;
    reg [7:0] char_b_out;
    
    always@(negedge VGA_IN_DATA_CLK)
    begin
        char_r_out <= (char_out) ? ((GPIO_DIP_SW[0]) ? (avg_r_out) : (8'hFF)) : (8'h00);
        char_g_out <= (char_out) ? ((GPIO_DIP_SW[0]) ? (avg_g_out) : (8'hFF)) : (8'h00);
        char_b_out <= (char_out) ? ((GPIO_DIP_SW[0]) ? (avg_b_out) : (8'hFF)) : (8'h00);
    end
    
    wire [7:0] r_out = (out_en) ? ((GPIO_DIP_SW[1]) ? (char_r_out) : (r_in)) : 8'h00;
    wire [7:0] g_out = (out_en) ? ((GPIO_DIP_SW[1]) ? (char_g_out) : (g_in)) : 8'h00;
    wire [7:0] b_out = (out_en) ? ((GPIO_DIP_SW[1]) ? (char_b_out) : (b_in)) : 8'h00;
    
    dvi_module dvi_module(  

        .dvi_vs(DVI_V),        
        .dvi_hs(DVI_H), 
        .dvi_d(DVI_D), 
        .dvi_xclk_p(DVI_XCLK_P), 
        .dvi_xclk_n(DVI_XCLK_N),
        .dvi_de(DVI_DE), 
        .dvi_reset_b(DVI_RESET_B),  
        .iic_done(iic_done), 
      

        .dvi_sda(IIC_SDA_VIDEO),
        .dvi_scl(IIC_SCL_VIDEO),
      

        .pixel_clk(VGA_IN_DATA_CLK), 
        .gpuclk_rst(reset), 
        .hsync(~VGA_IN_HSOUT),
        .vsync(~VGA_IN_VSOUT),
        .blank_b(out_en),
        .pixel_r(r_out),
        .pixel_b(b_out),
        .pixel_g(g_out)
    );


    assign GPIO_LED[7:0] = {char};
    assign GPIO_LED_C = iic_done;
    assign GPIO_LED_S = char_out;
    assign GPIO_LED_W = 0;
    assign GPIO_LED_N = 0;
    assign GPIO_LED_E = 0;
    
    
endmodule