data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:1: Cannot find include file: Data/Arith/extend.v\n`include "Data/Arith/extend.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Data/Arith,data/full_repos/permissive/131921633/Data/Arith/extend.v\n             data/full_repos/permissive/131921633/tv/Data/Arith,data/full_repos/permissive/131921633/Data/Arith/extend.v.v\n             data/full_repos/permissive/131921633/tv/Data/Arith,data/full_repos/permissive/131921633/Data/Arith/extend.v.sv\n             Data/Arith/extend.v\n             Data/Arith/extend.v.v\n             Data/Arith/extend.v.sv\n             obj_dir/Data/Arith/extend.v\n             obj_dir/Data/Arith/extend.v.v\n             obj_dir/Data/Arith/extend.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:2: Cannot find include file: Data/Arith/SignedUnsigned.v\n`include "Data/Arith/SignedUnsigned.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:3: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:9: Define or directive not defined: \'`Data_Arith_SignedUnsigned_T\'\n`Data_Arith_SignedUnsigned_T(logic) sign;\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:9: syntax error, unexpected \'(\'\n`Data_Arith_SignedUnsigned_T(logic) sign;\n                             ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:10: Define or directive not defined: \'`Data_Control_Control_T\'\n`Data_Control_Control_T(logic) ctrl;\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:23: Define or directive not defined: \'`Data_Arith_SignedUnsigned_Signed\'\nassign sign = `Data_Arith_SignedUnsigned_Signed;\n              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:23: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign sign = `Data_Arith_SignedUnsigned_Signed;\n                                               ^\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:25: Define or directive not defined: \'`Data_Control_Control_Clock\'\ninitial `Data_Control_Control_Clock(ctrl) = 0;\n        ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:25: syntax error, unexpected \'=\'\ninitial `Data_Control_Control_Clock(ctrl) = 0;\n                                          ^\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:26: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways #1 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:26: syntax error, unexpected \'=\'\nalways #1 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n                                            ^\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:26: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways #1 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n                                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:26: Unsupported: Ignoring delay on this delayed statement.\nalways #1 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:29: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:30: Define or directive not defined: \'`Data_Control_Control_Reset\'\n `Data_Control_Control_Reset(ctrl) = 1;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:30: syntax error, unexpected \'=\'\n `Data_Control_Control_Reset(ctrl) = 1;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:34: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:35: Define or directive not defined: \'`Data_Control_Control_Reset\'\n `Data_Control_Control_Reset(ctrl) = 0;\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:35: syntax error, unexpected \'=\'\n `Data_Control_Control_Reset(ctrl) = 0;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:37: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:41: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/131921633/tv/Data/Arith/extend.sv:45: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Error: Exiting due to 17 error(s), 6 warning(s)\n'
module Data_Arith_extend_tb;

logic [3:0] in  [1:0];
logic [7:0] out [1:0];
`Data_Arith_SignedUnsigned_T(logic) sign;
`Data_Control_Control_T(logic) ctrl;

Data_Arith_extend #
	( .IN_W  (4)
	, .OUT_W (8)
	, .DEPTH (2)
	) DUT
	( .in   (in)
	, .out  (out)
	, .sign (sign)
	, .ctrl (ctrl)
	);

assign sign = `Data_Arith_SignedUnsigned_Signed;

initial `Data_Control_Control_Clock(ctrl) = 0;
always #1 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);

initial begin
	#0;
	`Data_Control_Control_Reset(ctrl) = 1;
	in[0] = 4'h0;
	in[1] = 4'h0;

	#2;
	`Data_Control_Control_Reset(ctrl) = 0;

	#2;
	in[0] = 4'ha;
	in[1] = 4'h5;

	#2;
	in[0] = 4'h0;
	in[1] = 4'h0;

	#4;
	$finish;
end

endmodule
module Data_Arith_extend_tb;


logic [3:0] in  [1:0];
logic [7:0] out [1:0];
`Data_Arith_SignedUnsigned_T(logic) sign;
`Data_Control_Control_T(logic) ctrl;

Data_Arith_extend #
	( .IN_W  (4)
	, .OUT_W (8)
	, .DEPTH (2)
	) DUT
	( .in   (in)
	, .out  (out)
	, .sign (sign)
	, .ctrl (ctrl)
	);

assign sign = `Data_Arith_SignedUnsigned_Signed;

initial `Data_Control_Control_Clock(ctrl) = 0;
always #1 `Data_Control_Control_Clock(ctrl) = !`Data_Control_Control_Clock(ctrl);

initial begin
	#0;
	`Data_Control_Control_Reset(ctrl) = 1;
	in[0] = 4'h0;
	in[1] = 4'h0;

	#2;
	`Data_Control_Control_Reset(ctrl) = 0;

	#2;
	in[0] = 4'ha;
	in[1] = 4'h5;

	#2;
	in[0] = 4'h0;
	in[1] = 4'h0;

	#4;
	$finish;
end

endmodule