data/full_repos/permissive/104269513/generic_sw_regs.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/104269513/generic_sw_regs.v:64: Little bit endian vector: MSB < LSB of bit range: -2:0\n   wire [4-REG_ADDR_WIDTH-1:0] tag_addr;\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_sw_regs.v:74: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'reg_addr_in\' generates 4 bits.\n                                                                         : ... In instance generic_sw_regs\n   assign addr = reg_addr_in;\n               ^\n%Error: data/full_repos/permissive/104269513/generic_sw_regs.v:75: [3:5] Range extract has backward bit ordering, perhaps you wanted [5:3]\n                                                                 : ... In instance generic_sw_regs\n   assign tag_addr = reg_addr_in[4 - 1:REG_ADDR_WIDTH];\n                                ^\n%Warning-SELRANGE: data/full_repos/permissive/104269513/generic_sw_regs.v:75: Selection index out of range: 7:5 outside 3:0\n                                                                            : ... In instance generic_sw_regs\n   assign tag_addr = reg_addr_in[4 - 1:REG_ADDR_WIDTH];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_sw_regs.v:110: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n                                                                          : ... In instance generic_sw_regs\n               reg_data_out       <= reg_file[addr];\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/104269513/generic_sw_regs.v:115: Bit extraction of array[7:0] requires 3 bit index, not 5 bits.\n                                                                          : ... In instance generic_sw_regs\n               reg_file[addr]     <= reg_data_in;\n                       ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module generic_sw_regs
   #(
      parameter UDP_REG_SRC_WIDTH     = 2,
      parameter TAG                   = 0,
      parameter REG_ADDR_WIDTH        = 5,
      parameter NUM_REGS_USED         = 8,
      parameter REG_START_ADDR        = 0,



      parameter REG_END_ADDR = REG_START_ADDR + NUM_REGS_USED,
      parameter INPUT_START  = REG_START_ADDR * `CPCI_NF2_DATA_WIDTH,
      parameter INPUT_END    = REG_END_ADDR * `CPCI_NF2_DATA_WIDTH
   )
   (
      input                                  reg_req_in,
      input                                  reg_ack_in,
      input                                  reg_rd_wr_L_in,
      input  [`UDP_REG_ADDR_WIDTH-1:0]       reg_addr_in,
      input  [`CPCI_NF2_DATA_WIDTH-1:0]      reg_data_in,
      input  [UDP_REG_SRC_WIDTH-1:0]         reg_src_in,

      output reg                             reg_req_out,
      output reg                             reg_ack_out,
      output reg                             reg_rd_wr_L_out,
      output reg [`UDP_REG_ADDR_WIDTH-1:0]   reg_addr_out,
      output reg [`CPCI_NF2_DATA_WIDTH-1:0]  reg_data_out,
      output reg [UDP_REG_SRC_WIDTH-1:0]     reg_src_out,


      output [INPUT_END - 1 : INPUT_START]   software_regs,

      input                                clk,
      input                                reset
    );


   






   wire [REG_ADDR_WIDTH-1:0]              addr;
   wire [`UDP_REG_ADDR_WIDTH-REG_ADDR_WIDTH-1:0] tag_addr;

   wire                                   addr_good;
   wire                                   tag_hit;

   reg [`CPCI_NF2_DATA_WIDTH-1:0]         reg_file[REG_START_ADDR:REG_END_ADDR - 1];

   integer                                ii;


   assign addr = reg_addr_in;
   assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:REG_ADDR_WIDTH];

   assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;
   assign tag_hit = tag_addr == TAG;

   generate
   genvar i;
   for (i=REG_START_ADDR; i<REG_END_ADDR; i=i+1) begin:reg_file_assigns
      assign software_regs[`CPCI_NF2_DATA_WIDTH*(i+1)-1:`CPCI_NF2_DATA_WIDTH*i]
                                       = reg_file[i];
   end
   endgenerate

   always @(posedge clk) begin
      if(reset) begin
         for(ii=REG_START_ADDR; ii<REG_END_ADDR; ii=ii+1) begin
            reg_file[ii] <= 0;
         end
         reg_req_out        <= 0;
         reg_ack_out        <= 0;
         reg_rd_wr_L_out    <= 0;
         reg_addr_out       <= 0;
         reg_src_out        <= 0;
         reg_data_out       <= 0;
      end
      else begin

         if(addr_good && tag_hit && reg_req_in) begin
            reg_req_out        <= reg_req_in;
            reg_ack_out        <= 1'b1;
            reg_rd_wr_L_out    <= reg_rd_wr_L_in;
            reg_addr_out       <= reg_addr_in;
            reg_src_out        <= reg_src_in;

            if(reg_rd_wr_L_in) begin
               reg_data_out       <= reg_file[addr];
            end

            else begin
               reg_data_out       <= reg_data_in;
               reg_file[addr]     <= reg_data_in;
            end
         end
         else begin
            reg_req_out        <= reg_req_in;
            reg_ack_out        <= reg_ack_in;
            reg_rd_wr_L_out    <= reg_rd_wr_L_in;
            reg_addr_out       <= reg_addr_in;
            reg_src_out        <= reg_src_in;
            reg_data_out       <= reg_data_in;
         end
      end
   end

endmodule
module generic_sw_regs
   #(
      parameter UDP_REG_SRC_WIDTH     = 2,
      parameter TAG                   = 0,
      parameter REG_ADDR_WIDTH        = 5,
      parameter NUM_REGS_USED         = 8,
      parameter REG_START_ADDR        = 0,



      parameter REG_END_ADDR = REG_START_ADDR + NUM_REGS_USED,
      parameter INPUT_START  = REG_START_ADDR * `CPCI_NF2_DATA_WIDTH,
      parameter INPUT_END    = REG_END_ADDR * `CPCI_NF2_DATA_WIDTH
   )
   (
      input                                  reg_req_in,
      input                                  reg_ack_in,
      input                                  reg_rd_wr_L_in,
      input  [`UDP_REG_ADDR_WIDTH-1:0]       reg_addr_in,
      input  [`CPCI_NF2_DATA_WIDTH-1:0]      reg_data_in,
      input  [UDP_REG_SRC_WIDTH-1:0]         reg_src_in,

      output reg                             reg_req_out,
      output reg                             reg_ack_out,
      output reg                             reg_rd_wr_L_out,
      output reg [`UDP_REG_ADDR_WIDTH-1:0]   reg_addr_out,
      output reg [`CPCI_NF2_DATA_WIDTH-1:0]  reg_data_out,
      output reg [UDP_REG_SRC_WIDTH-1:0]     reg_src_out,


      output [INPUT_END - 1 : INPUT_START]   software_regs,

      input                                clk,
      input                                reset
    );



   






   wire [REG_ADDR_WIDTH-1:0]              addr;
   wire [`UDP_REG_ADDR_WIDTH-REG_ADDR_WIDTH-1:0] tag_addr;

   wire                                   addr_good;
   wire                                   tag_hit;

   reg [`CPCI_NF2_DATA_WIDTH-1:0]         reg_file[REG_START_ADDR:REG_END_ADDR - 1];

   integer                                ii;


   assign addr = reg_addr_in;
   assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:REG_ADDR_WIDTH];

   assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;
   assign tag_hit = tag_addr == TAG;

   generate
   genvar i;
   for (i=REG_START_ADDR; i<REG_END_ADDR; i=i+1) begin:reg_file_assigns
      assign software_regs[`CPCI_NF2_DATA_WIDTH*(i+1)-1:`CPCI_NF2_DATA_WIDTH*i]
                                       = reg_file[i];
   end
   endgenerate

   always @(posedge clk) begin
      if(reset) begin
         for(ii=REG_START_ADDR; ii<REG_END_ADDR; ii=ii+1) begin
            reg_file[ii] <= 0;
         end
         reg_req_out        <= 0;
         reg_ack_out        <= 0;
         reg_rd_wr_L_out    <= 0;
         reg_addr_out       <= 0;
         reg_src_out        <= 0;
         reg_data_out       <= 0;
      end
      else begin

         if(addr_good && tag_hit && reg_req_in) begin
            reg_req_out        <= reg_req_in;
            reg_ack_out        <= 1'b1;
            reg_rd_wr_L_out    <= reg_rd_wr_L_in;
            reg_addr_out       <= reg_addr_in;
            reg_src_out        <= reg_src_in;

            if(reg_rd_wr_L_in) begin
               reg_data_out       <= reg_file[addr];
            end

            else begin
               reg_data_out       <= reg_data_in;
               reg_file[addr]     <= reg_data_in;
            end
         end
         else begin
            reg_req_out        <= reg_req_in;
            reg_ack_out        <= reg_ack_in;
            reg_rd_wr_L_out    <= reg_rd_wr_L_in;
            reg_addr_out       <= reg_addr_in;
            reg_src_out        <= reg_src_in;
            reg_data_out       <= reg_data_in;
         end
      end
   end

endmodule