data/full_repos/permissive/173670949/blink.v
 line:13: before: ")"
1: b"%Error: data/full_repos/permissive/173670949/blink.v:13: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/173670949/blink.v:28: syntax error, unexpected always\n    always @(posedge ICE_CLK) begin\n    ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Blink(
    input ICE_CLK,
    output GLED5,
    output RLED1,
    output RLED2,
    output RLED3,
    output RLED4,
    output J3_10,
    output J3_9,
);


    localparam WIDTH = 24;
    reg [WIDTH-1:0] counter;


    reg [7:0] pwm_level;
    wire pwm_out;

    localparam UP   = 1'b0;
    localparam DOWN = 1'b1;
    reg state = UP;


    always @(posedge ICE_CLK) begin
        counter <= counter + 1;

        if (counter[15:0] == 0) begin
            if (state == UP) begin
                if (pwm_level == 8'hFF) begin
                    state <= DOWN;
                    pwm_level <= pwm_level - 1;
                end else
                    pwm_level <= pwm_level + 1;
            end else begin
                if (pwm_level == 8'h00) begin
                    state <= UP;
                    pwm_level <= pwm_level + 1;
                end else
                    pwm_level <= pwm_level - 1;
            end
        end
    end

    PWM pwm(ICE_CLK, pwm_level, pwm_out);

    assign RLED1 = pwm_out;
    assign RLED2 = pwm_out;
    assign RLED3 = pwm_out;
    assign RLED4 = pwm_out;
    assign GLED5 = ~pwm_out;

    assign J3_10 = pwm_out;
    assign J3_9  = ~pwm_out;






endmodule
module Blink(
    input ICE_CLK,
    output GLED5,
    output RLED1,
    output RLED2,
    output RLED3,
    output RLED4,
    output J3_10,
    output J3_9,
);



    localparam WIDTH = 24;
    reg [WIDTH-1:0] counter;


    reg [7:0] pwm_level;
    wire pwm_out;

    localparam UP   = 1'b0;
    localparam DOWN = 1'b1;
    reg state = UP;


    always @(posedge ICE_CLK) begin
        counter <= counter + 1;

        if (counter[15:0] == 0) begin
            if (state == UP) begin
                if (pwm_level == 8'hFF) begin
                    state <= DOWN;
                    pwm_level <= pwm_level - 1;
                end else
                    pwm_level <= pwm_level + 1;
            end else begin
                if (pwm_level == 8'h00) begin
                    state <= UP;
                    pwm_level <= pwm_level + 1;
                end else
                    pwm_level <= pwm_level - 1;
            end
        end
    end

    PWM pwm(ICE_CLK, pwm_level, pwm_out);

    assign RLED1 = pwm_out;
    assign RLED2 = pwm_out;
    assign RLED3 = pwm_out;
    assign RLED4 = pwm_out;
    assign GLED5 = ~pwm_out;

    assign J3_10 = pwm_out;
    assign J3_9  = ~pwm_out;






endmodule