data/full_repos/permissive/146975244/Temp.v
data/verilator_xmls/97886de4-2e52-45c0-96bb-78bade59658f.xml
module Temp(clk_in,clockO);

input clk_in;
output wire clockO;

parameter n =25;
reg [n:0] cont;

always@(posedge clk_in)
   begin
     cont <= cont + 1 ;
   end
	
	assign clockO = cont[n];

endmodule
module Temp(clk_in,clockO);


input clk_in;
output wire clockO;

parameter n =25;
reg [n:0] cont;

always@(posedge clk_in)
   begin
     cont <= cont + 1 ;
   end
	
	assign clockO = cont[n];

endmodule