data/full_repos/permissive/165846232/components/SignAddSub/SignAddSub.v
data/verilator_xmls/31b7ffbe-4976-4953-bcd3-6338ed93a3dd.xml
module SignAddSub
#(
	parameter INPUT_BIT_WIDTH = 8
)
(
    input Clk,
    input [INPUT_BIT_WIDTH-1:0] InputA,
	input [INPUT_BIT_WIDTH-1:0] InputB,
	input wire AddSubMode,
	output reg [INPUT_BIT_WIDTH-1:0] Result,
    output reg [INPUT_BIT_WIDTH-1:0] ResultB
);

    always @(posedge Clk)
	begin
		if(AddSubMode)
            begin
                Result <= InputA + InputB;
                ResultB <= InputA - InputB;
            end
		else
            begin
                Result <= InputA - InputB;
                ResultB <= InputA + InputB;
            end
	end

endmodule
module SignAddSub
#(
	parameter INPUT_BIT_WIDTH = 8
)
(
    input Clk,
    input [INPUT_BIT_WIDTH-1:0] InputA,
	input [INPUT_BIT_WIDTH-1:0] InputB,
	input wire AddSubMode,
	output reg [INPUT_BIT_WIDTH-1:0] Result,
    output reg [INPUT_BIT_WIDTH-1:0] ResultB
);


    always @(posedge Clk)
	begin
		if(AddSubMode)
            begin
                Result <= InputA + InputB;
                ResultB <= InputA - InputB;
            end
		else
            begin
                Result <= InputA - InputB;
                ResultB <= InputA + InputB;
            end
	end

endmodule