data/full_repos/permissive/21310161/hdl/sequencer.v
 line:67: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/21310161/hdl/sequencer.v:81: Operator ASSIGN expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'hdeadbeef\' generates 32 bits.\n                                                                      : ... In instance sequencer\n   reg [CBITS-1:0]    count = 32\'hDEADBEEF;\n                              ^~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/21310161/hdl/sequencer.v:95: Operator ADD expects 16 bits on the RHS, but RHS\'s LOGAND generates 1 bits.\n                                                                      : ... In instance sequencer\n     address + (inc && (rvalid || wvalid));\n             ^\n%Warning-WIDTH: data/full_repos/permissive/21310161/hdl/sequencer.v:101: Operator SUB expects 24 bits on the RHS, but RHS\'s VARREF \'wvalid_next\' generates 1 bits.\n                                                                       : ... In instance sequencer\n   2: count <= count - wvalid_next;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/21310161/hdl/sequencer.v:102: Operator SUB expects 24 bits on the RHS, but RHS\'s VARREF \'rvalid_next\' generates 1 bits.\n                                                                       : ... In instance sequencer\n   3: count <= count - rvalid_next;\n                     ^\n%Error: Exiting due to 4 warning(s)\n'
module delay_n
  (
   input  clock,
   input  in,
   output out
   );

   parameter N = 2;

   reg [N-1:0] sreg = 0;

   assign out = sreg[N-1];

   always @ (posedge clock)
     sreg <= {sreg[N-2:0],in};

endmodule
module delay_n
  (
   input  clock,
   input  in,
   output out
   );


   parameter N = 2;

   reg [N-1:0] sreg = 0;

   assign out = sreg[N-1];

   always @ (posedge clock)
     sreg <= {sreg[N-2:0],in};

endmodule