data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-dac/syzygy-dds-fp.v
1: b'%Error: data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-dac/syzygy-dds-fp.v:66: Cannot find file containing module: \'cordic_0\'\ncordic_0 cordic_0_inst(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-dac,data/full_repos/permissive/141490569/cordic_0\n             data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-dac,data/full_repos/permissive/141490569/cordic_0.v\n             data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-dac,data/full_repos/permissive/141490569/cordic_0.sv\n             cordic_0\n             cordic_0.v\n             cordic_0.sv\n             obj_dir/cordic_0\n             obj_dir/cordic_0.v\n             obj_dir/cordic_0.sv\n%Warning-WIDTH: data/full_repos/permissive/141490569/SignalGenerator/HDL/szg-dac/syzygy-dds-fp.v:91: Operator SHIFTL expects 70 bits on the LHS, but LHS\'s VARREF \'freq_r\' generates 32 bits.\n                                                                                                   : ... In instance syzygy_dds_fp\n  delta                 <= freq_r << shift_factor;\n                                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module syzygy_dds_fp(
	input  wire        clk,
	input  wire        reset,

	input  wire        dis_out,

	input  wire [31:0] freq,
	input  wire [31:0] phase,
	input  wire [27:0] inc_delta,

	output reg  [11:0] data
);


reg  [69:0]    delta;
reg  [31:0]    counter;
reg  [31:0]    freq_r, phase_r;
reg  [11:0]    cordic_out_shifted_up;

wire [31:0]    inc_delta_signed;
wire [11:0]    cordic_out;
wire           data_valid;

assign inc_delta_signed         = (inc_delta[27]) ? {4'hF, inc_delta} : {4'h0, inc_delta};


localparam     max_val          = 32'h40000000;

localparam     sub_val          = 32'hE0000000;

localparam     shift_factor     = 6'd37;


cordic_0 cordic_0_inst(
	.aclk                (clk),
	.s_axis_phase_tdata  (counter + phase_r + sub_val),
	.s_axis_phase_tvalid (1'b1),
	.m_axis_dout_tdata   (cordic_out),
	.m_axis_dout_tvalid  (data_valid)
);

always @(posedge clk) begin
	if (reset) begin
		delta                 <= 70'd0;
		delta                <= 70'd0;

		counter               <= 32'd0;

		freq_r                <= 32'd0;
		phase_r               <= 32'd0;

		cordic_out_shifted_up <= 12'd0;
	end else if (dis_out)
		data                  <= 12'd0;
	else begin

		freq_r                <= freq + inc_delta_signed;
		phase_r               <= phase;
		delta                 <= freq_r << shift_factor;

		data                  <= cordic_out_shifted_up;

		counter               <= counter + delta[65:34];

		if (counter >= max_val - delta[65:34])
			counter <= counter - max_val + delta[65:34];


		cordic_out_shifted_up <= cordic_out + 12'h400;
	end
end

endmodule
module syzygy_dds_fp(
	input  wire        clk,
	input  wire        reset,

	input  wire        dis_out,

	input  wire [31:0] freq,
	input  wire [31:0] phase,
	input  wire [27:0] inc_delta,

	output reg  [11:0] data
);



reg  [69:0]    delta;
reg  [31:0]    counter;
reg  [31:0]    freq_r, phase_r;
reg  [11:0]    cordic_out_shifted_up;

wire [31:0]    inc_delta_signed;
wire [11:0]    cordic_out;
wire           data_valid;

assign inc_delta_signed         = (inc_delta[27]) ? {4'hF, inc_delta} : {4'h0, inc_delta};


localparam     max_val          = 32'h40000000;

localparam     sub_val          = 32'hE0000000;

localparam     shift_factor     = 6'd37;


cordic_0 cordic_0_inst(
	.aclk                (clk),
	.s_axis_phase_tdata  (counter + phase_r + sub_val),
	.s_axis_phase_tvalid (1'b1),
	.m_axis_dout_tdata   (cordic_out),
	.m_axis_dout_tvalid  (data_valid)
);

always @(posedge clk) begin
	if (reset) begin
		delta                 <= 70'd0;
		delta                <= 70'd0;

		counter               <= 32'd0;

		freq_r                <= 32'd0;
		phase_r               <= 32'd0;

		cordic_out_shifted_up <= 12'd0;
	end else if (dis_out)
		data                  <= 12'd0;
	else begin

		freq_r                <= freq + inc_delta_signed;
		phase_r               <= phase;
		delta                 <= freq_r << shift_factor;

		data                  <= cordic_out_shifted_up;

		counter               <= counter + delta[65:34];

		if (counter >= max_val - delta[65:34])
			counter <= counter - max_val + delta[65:34];


		cordic_out_shifted_up <= cordic_out + 12'h400;
	end
end

endmodule