data/full_repos/permissive/211316121/lab3_3/sources_1/new/fourAdder.v
data/verilator_xmls/2995717f-cd1a-42ea-ac9c-5deeb623ad3d.xml
module fourAdder(
    input [3:0] a,
    input [3:0] b,
    output [3:0] s,
    output c4
    );
    wire c0,c1,c2,c3;
    wire [3:0] p;
    wire [3:0] g;
    
    xor
        P0(p[0],a[0],b[0]),
        P1(p[1],a[1],b[1]),
        P2(p[2],a[2],b[2]),
        P3(p[3],a[3],b[3]);
    
    and
        G0(g[0],a[0],b[0]),
        G1(g[1],a[1],b[1]),
        G2(g[2],a[2],b[2]),
        G3(g[3],a[3],b[3]);
        
    xor
        S0(s[0],p[0],c0),
        S1(s[1],p[1],c1),
        S2(s[2],p[2],c2),
        S3(s[3],p[3],c3);
        
    assign c0=0;
    assign c1=g[0]|p[0]&c0;
    assign c2=g[1]|p[1]&g[0]|p[1]&p[0]&c0;
    assign c3=g[2]|p[2]&g[1]|p[2]&p[1]&g[0]|p[2]&p[1]&p[0]&c0;
    assign c4=g[3]|p[3]&g[2]|p[3]&p[2]&g[1]|p[3]&p[2]&p[1]&g[0]|p[3]&p[2]&p[1]&p[0]&c0;
endmodule
module fourAdder(
    input [3:0] a,
    input [3:0] b,
    output [3:0] s,
    output c4
    );

    wire c0,c1,c2,c3;
    wire [3:0] p;
    wire [3:0] g;
    
    xor
        P0(p[0],a[0],b[0]),
        P1(p[1],a[1],b[1]),
        P2(p[2],a[2],b[2]),
        P3(p[3],a[3],b[3]);
    
    and
        G0(g[0],a[0],b[0]),
        G1(g[1],a[1],b[1]),
        G2(g[2],a[2],b[2]),
        G3(g[3],a[3],b[3]);
        
    xor
        S0(s[0],p[0],c0),
        S1(s[1],p[1],c1),
        S2(s[2],p[2],c2),
        S3(s[3],p[3],c3);
        
    assign c0=0;
    assign c1=g[0]|p[0]&c0;
    assign c2=g[1]|p[1]&g[0]|p[1]&p[0]&c0;
    assign c3=g[2]|p[2]&g[1]|p[2]&p[1]&g[0]|p[2]&p[1]&p[0]&c0;
    assign c4=g[3]|p[3]&g[2]|p[3]&p[2]&g[1]|p[3]&p[2]&p[1]&g[0]|p[3]&p[2]&p[1]&p[0]&c0;
endmodule