data/full_repos/permissive/142505464/modules/wb_bfm_mod/rtl/verilog/wb_bfm_mod_transactor.v
None: at end of input
1: b'%Error: data/full_repos/permissive/142505464/modules/wb_bfm_mod/rtl/verilog/wb_bfm_mod_transactor.v:61: Cannot find include file: wb_common_params.v\n  `include "wb_common_params.v" \n           ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/142505464/modules/wb_bfm_mod/rtl/verilog,data/full_repos/permissive/142505464/wb_common_params.v\n             data/full_repos/permissive/142505464/modules/wb_bfm_mod/rtl/verilog,data/full_repos/permissive/142505464/wb_common_params.v.v\n             data/full_repos/permissive/142505464/modules/wb_bfm_mod/rtl/verilog,data/full_repos/permissive/142505464/wb_common_params.v.sv\n             wb_common_params.v\n             wb_common_params.v.v\n             wb_common_params.v.sv\n             obj_dir/wb_common_params.v\n             obj_dir/wb_common_params.v.v\n             obj_dir/wb_common_params.v.sv\n%Error: data/full_repos/permissive/142505464/modules/wb_bfm_mod/rtl/verilog/wb_bfm_mod_transactor.v:122: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n          gen_adr = (low + ({$random(SEED)} % (high-low))) &  {{aw-ADR_LSB{1\'b1}},{ADR_LSB{1\'b0}}};\n                             ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/142505464/modules/wb_bfm_mod/rtl/verilog/wb_bfm_mod_transactor.v:122: ../V3Ast.cpp:358: Null item passed to setOp1p\n          gen_adr = (low + ({$random(SEED)} % (high-low))) &  {{aw-ADR_LSB{1\'b1}},{ADR_LSB{1\'b0}}};\n                            ^\n'
function [2:0] gen_cycle_type;
      input integer cycle_type_prob;
      begin
         if (cycle_type_prob <= CLASSIC_PROB) begin
            gen_cycle_type                = 3'b000;
         end else if (cycle_type_prob <= (CLASSIC_PROB + CONST_BURST_PROB)) begin
            gen_cycle_type                = CTI_CONST_BURST;
         end else begin
            gen_cycle_type                = CTI_INC_BURST;
         end
      end
   endfunction
function [2:0] gen_cycle_type;

      input integer cycle_type_prob;
      begin
         if (cycle_type_prob <= CLASSIC_PROB) begin
            gen_cycle_type                = 3'b000;
         end else if (cycle_type_prob <= (CLASSIC_PROB + CONST_BURST_PROB)) begin
            gen_cycle_type                = CTI_CONST_BURST;
         end else begin
            gen_cycle_type                = CTI_INC_BURST;
         end
      end
   endfunction