data/full_repos/permissive/152087828/testbench_pcpi.v
 line:17: before: "("
1: b'%Error: data/full_repos/permissive/152087828/testbench_pcpi.v:247: Unsupported: $fflush of all handles does not map to C++.\n    $fflush();\n    ^~~~~~~\n%Error: data/full_repos/permissive/152087828/testbench_pcpi.v:280: Unsupported: $fflush of all handles does not map to C++.\n     $fflush();\n     ^~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench ();
	reg clk = 1;
	reg resetn = 0;
	wire trap;

	always #5 clk = ~clk;

	initial begin
		repeat (100) @(posedge clk);
		resetn <= 1;
	end

	initial begin
		if ($test$plusargs("fsdb")) begin
			$fsdbDumpfile(`FSDB_FILE);
			$fsdbDumpvars(0, testbench);
		end
		repeat (1000000000) @(posedge clk);
		$display("TIMEOUT");
		$finish;
	end

	wire trace_valid;
	wire [35:0] trace_data;
	integer trace_file;

	initial begin
		if ($test$plusargs("trace")) begin
			trace_file = $fopen("testbench.trace", "w");
			repeat (10) @(posedge clk);
			while (!trap) begin
				@(posedge clk);
				if (trace_valid)
					$fwrite(trace_file, "%x\n", trace_data);
			end
			$fclose(trace_file);
			$display("Finished writing testbench.trace.");
		end
	end
	
	integer knn_in;
	integer i, j, cc, num, re;
	integer debug;                
	
	reg [7:0] data [0:5000];
	
	initial begin
		$readmemh("firmware/firmware.hex", top.memory, 0, `IMG_OFFSET-1);
	
		if ($value$plusargs("debug=%d", debug)) begin
			$display(">> Debug level = %d", debug);
		end else begin
			debug = 0;
		end
		
		knn_in = $fopen("input.txt", "r");
		re = $fscanf(knn_in, "%d", num);
		$display("num = %d", num);
		for(i=0;i<num;i=i+1)begin
			for(j=0;j<num;j=j+1)begin
			re = $fscanf(knn_in, "%d", data[num*i+j]);
			end
		end
		top.memory[`IMG_OFFSET] = {24'b0, num};
		for(i = 1; i <= num*num; i = i + 1) begin
			top.memory[`IMG_OFFSET + i] = {24'b0, data[i-1]};
		end  

		
		$fclose(knn_in);
	end
	
	picorv32_wrapper top (
		.clk(clk),
		.resetn(resetn),
		.trap(trap),
		.trace_valid(trace_valid),
		.trace_data(trace_data)
	);
endmodule
module testbench ();

	reg clk = 1;
	reg resetn = 0;
	wire trap;

	always #5 clk = ~clk;

	initial begin
		repeat (100) @(posedge clk);
		resetn <= 1;
	end

	initial begin
		if ($test$plusargs("fsdb")) begin
			$fsdbDumpfile(`FSDB_FILE);
			$fsdbDumpvars(0, testbench);
		end
		repeat (1000000000) @(posedge clk);
		$display("TIMEOUT");
		$finish;
	end

	wire trace_valid;
	wire [35:0] trace_data;
	integer trace_file;

	initial begin
		if ($test$plusargs("trace")) begin
			trace_file = $fopen("testbench.trace", "w");
			repeat (10) @(posedge clk);
			while (!trap) begin
				@(posedge clk);
				if (trace_valid)
					$fwrite(trace_file, "%x\n", trace_data);
			end
			$fclose(trace_file);
			$display("Finished writing testbench.trace.");
		end
	end
	
	integer knn_in;
	integer i, j, cc, num, re;
	integer debug;                
	
	reg [7:0] data [0:5000];
	
	initial begin
		$readmemh("firmware/firmware.hex", top.memory, 0, `IMG_OFFSET-1);
	
		if ($value$plusargs("debug=%d", debug)) begin
			$display(">> Debug level = %d", debug);
		end else begin
			debug = 0;
		end
		
		knn_in = $fopen("input.txt", "r");
		re = $fscanf(knn_in, "%d", num);
		$display("num = %d", num);
		for(i=0;i<num;i=i+1)begin
			for(j=0;j<num;j=j+1)begin
			re = $fscanf(knn_in, "%d", data[num*i+j]);
			end
		end
		top.memory[`IMG_OFFSET] = {24'b0, num};
		for(i = 1; i <= num*num; i = i + 1) begin
			top.memory[`IMG_OFFSET + i] = {24'b0, data[i-1]};
		end  

		
		$fclose(knn_in);
	end
	
	picorv32_wrapper top (
		.clk(clk),
		.resetn(resetn),
		.trap(trap),
		.trace_valid(trace_valid),
		.trace_data(trace_data)
	);
endmodule