data/full_repos/permissive/201708219/hdmi_driver.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/201708219/hdmi_driver.v:31: Cannot find file containing module: \'i2c_master_top\'\ni2c_master_top I2C_0 (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201708219,data/full_repos/permissive/201708219/i2c_master_top\n             data/full_repos/permissive/201708219,data/full_repos/permissive/201708219/i2c_master_top.v\n             data/full_repos/permissive/201708219,data/full_repos/permissive/201708219/i2c_master_top.sv\n             i2c_master_top\n             i2c_master_top.v\n             i2c_master_top.sv\n             obj_dir/i2c_master_top\n             obj_dir/i2c_master_top.v\n             obj_dir/i2c_master_top.sv\n%Error: data/full_repos/permissive/201708219/hdmi_driver.v:45: Cannot find file containing module: \'reg_lut\'\nreg_lut LUT0 (\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/201708219/hdmi_driver.v:65: Operator LT expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'mI2C_CLK_DIV\' generates 16 bits.\n                                                                     : ... In instance hdmi_driver\n  if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module hdmi_driver (
	input clk_50, reset_al,
	output 	wire H_sync, V_sync,
	output 	reg [9:0] CountX, CountY,
	output 	wire [7:0] RED, GREEN, BLUE,
	output 	reg Draw_enable,
	output 	wire scl,
	output 	wire sda,
	output 	wire fail,
	output	reg rst,
	output 	reg clk_25,
	input 	wire HDMI_INT,
	output 	reg mI2C_CTRL_CLK
);


assign H_sync = (CountX>=656) && (CountX<752);
assign V_sync = (CountY>=490) && (CountY<492);

wire 	[6:0] 	slave_address;
wire 	[7:0] 	data;
reg 	[2:0] 	byte_num = 2;
reg 	[7:0] 	byte_lut, byte_lut_next;
reg 	[9:0] 	clk_divide;
wire 			read_write = 0;
wire 			start;
reg 			clk_50k;
wire 			reset;
wire 			done;
	
i2c_master_top I2C_0 (
	.clk_50k		(mI2C_CTRL_CLK),
	.reset			(reset),
	.start			(start),
	.sda			(sda),
	.scl			(scl),
	.slave_address	(slave_address),
	.read_write		(read_write),
	.data			(data),
	.byte_num		(byte_num),
	.fail			(fail),
	.done			(done)
	);
	
reg_lut LUT0 (
	.byte_lut		(byte_lut),
	.data_byte		(data)
);


reg	[15:0]	mI2C_CLK_DIV;

parameter	CLK_Freq	=	50000000;
parameter	I2C_Freq	=	20000;

always@(posedge clk_50)
begin
	if(reset)
	begin
		mI2C_CTRL_CLK	<=	0;
		mI2C_CLK_DIV	<=	0;
	end
	else
	begin
		if( mI2C_CLK_DIV	<	(CLK_Freq/I2C_Freq) )
			mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1'b1;
		else
		begin
			mI2C_CLK_DIV	<=	0;
			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
		end
	end
end

assign GREEN = CountX[7:0];
assign BLUE = CountY[7:0];
assign RED = CountY[7:0]/2;
assign reset = ~reset_al;

assign start = 1;
assign slave_address = 7'h72;

always @ (posedge clk_50) begin
	clk_25 <= (rst) ? 0 : ~clk_25;
end

always @ (posedge done) begin
byte_lut_next <= byte_lut + 1;
end
	
always @ (posedge clk_50) begin

	rst <= reset;
	
	if (reset) begin
		clk_50k <= 0;
		clk_divide <= 0;
	end

	if (clk_divide == 500) begin
		clk_50k <= ~clk_50k;
		clk_divide <= 0;
	end
	else
		clk_divide <= clk_divide + 1;

		byte_lut <= (byte_lut == 62) ? 0 : byte_lut_next;
		
end

always @ (posedge clk_25) begin
	
	if (reset) begin
		CountX <= 0;
		CountY <= 0;
	end
	else begin
		CountX <= (CountX == 799) ? 0 : CountX + 1;
		if (CountX == 799) CountY <= (CountY == 524) ? 0 : CountY + 1;
	end
end

always @ (*) begin
	if (CountX <= 640 && CountY <= 480)
		Draw_enable = 1;
	else
		Draw_enable = 0;
end

endmodule
module hdmi_driver (
	input clk_50, reset_al,
	output 	wire H_sync, V_sync,
	output 	reg [9:0] CountX, CountY,
	output 	wire [7:0] RED, GREEN, BLUE,
	output 	reg Draw_enable,
	output 	wire scl,
	output 	wire sda,
	output 	wire fail,
	output	reg rst,
	output 	reg clk_25,
	input 	wire HDMI_INT,
	output 	reg mI2C_CTRL_CLK
);



assign H_sync = (CountX>=656) && (CountX<752);
assign V_sync = (CountY>=490) && (CountY<492);

wire 	[6:0] 	slave_address;
wire 	[7:0] 	data;
reg 	[2:0] 	byte_num = 2;
reg 	[7:0] 	byte_lut, byte_lut_next;
reg 	[9:0] 	clk_divide;
wire 			read_write = 0;
wire 			start;
reg 			clk_50k;
wire 			reset;
wire 			done;
	
i2c_master_top I2C_0 (
	.clk_50k		(mI2C_CTRL_CLK),
	.reset			(reset),
	.start			(start),
	.sda			(sda),
	.scl			(scl),
	.slave_address	(slave_address),
	.read_write		(read_write),
	.data			(data),
	.byte_num		(byte_num),
	.fail			(fail),
	.done			(done)
	);
	
reg_lut LUT0 (
	.byte_lut		(byte_lut),
	.data_byte		(data)
);


reg	[15:0]	mI2C_CLK_DIV;

parameter	CLK_Freq	=	50000000;
parameter	I2C_Freq	=	20000;

always@(posedge clk_50)
begin
	if(reset)
	begin
		mI2C_CTRL_CLK	<=	0;
		mI2C_CLK_DIV	<=	0;
	end
	else
	begin
		if( mI2C_CLK_DIV	<	(CLK_Freq/I2C_Freq) )
			mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1'b1;
		else
		begin
			mI2C_CLK_DIV	<=	0;
			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
		end
	end
end

assign GREEN = CountX[7:0];
assign BLUE = CountY[7:0];
assign RED = CountY[7:0]/2;
assign reset = ~reset_al;

assign start = 1;
assign slave_address = 7'h72;

always @ (posedge clk_50) begin
	clk_25 <= (rst) ? 0 : ~clk_25;
end

always @ (posedge done) begin
byte_lut_next <= byte_lut + 1;
end
	
always @ (posedge clk_50) begin

	rst <= reset;
	
	if (reset) begin
		clk_50k <= 0;
		clk_divide <= 0;
	end

	if (clk_divide == 500) begin
		clk_50k <= ~clk_50k;
		clk_divide <= 0;
	end
	else
		clk_divide <= clk_divide + 1;

		byte_lut <= (byte_lut == 62) ? 0 : byte_lut_next;
		
end

always @ (posedge clk_25) begin
	
	if (reset) begin
		CountX <= 0;
		CountY <= 0;
	end
	else begin
		CountX <= (CountX == 799) ? 0 : CountX + 1;
		if (CountX == 799) CountY <= (CountY == 524) ? 0 : CountY + 1;
	end
end

always @ (*) begin
	if (CountX <= 640 && CountY <= 480)
		Draw_enable = 1;
	else
		Draw_enable = 0;
end

endmodule