data/full_repos/permissive/206783267/SPI/TB/spi_master_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/206783267/SPI/TB/spi_master_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n forever #(CLK_CYCLE/2) clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206783267/SPI/TB/spi_master_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_CYCLE*7/2) arstn = 1\'b1;\n ^\n%Error: data/full_repos/permissive/206783267/SPI/TB/spi_master_tb.v:52: syntax error, unexpected \'@\'\n @(posedge arstn)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/SPI/TB/spi_master_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE) spi_start <= 1\'b0;\n  ^\n%Error: data/full_repos/permissive/206783267/SPI/TB/spi_master_tb.v:55: syntax error, unexpected \'@\'\n @(negedge spi_done)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/206783267/SPI/TB/spi_master_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_CYCLE) spi_start <= 1\'b0;\n  ^\n%Error: data/full_repos/permissive/206783267/SPI/TB/spi_master_tb.v:65: syntax error, unexpected \'@\'\n @(posedge spi_start)\n ^\n%Error: data/full_repos/permissive/206783267/SPI/TB/spi_master_tb.v:91: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module spi_master_tb();

parameter	CLK_FREQ = 50_000_000,
			SPI_FREQ = 5_000_000,
			DATA_WIDTH = 8,
			CLK_CYCLE = 20,
			CPOL = 0,
			CPHA = 0;

reg	clk, arstn;
reg	[DATA_WIDTH-1:0]	data_send;
reg	spi_start;
wire	sclk, csn, mosi;
reg	miso;
wire	spi_done;
wire	[DATA_WIDTH-1:0]	data_recv;


initial begin
	clk = 0;
	forever	#(CLK_CYCLE/2)	clk = ~clk;
end


initial begin
	arstn = 1'b0;
	#(CLK_CYCLE*7/2)	arstn = 1'b1;
end


generate
	case(CPHA ^ CPOL)
		0:	begin
			always@(negedge sclk) begin
				miso = $random;
			end
		end
		1:	begin
			always@(posedge sclk) begin
				miso = $random;
			end
		end
	endcase
endgenerate


task gen_spi_start;
begin
	spi_start = 1'b0;
	@(posedge arstn)
		#(CLK_CYCLE*15)	spi_start <= 1'b1;
		#(CLK_CYCLE)	spi_start <= 1'b0;
	@(negedge spi_done)
		#(CLK_CYCLE*15)	spi_start <= 1'b1;
		#(CLK_CYCLE)	spi_start <= 1'b0;
end
endtask


task gen_data_send;
begin
	data_send = 'd0;
	@(posedge spi_start)
		data_send = 8'b10100101;
	@(posedge spi_start)
		data_send = 8'b10011010;
	@(negedge spi_done)
		#(CLK_CYCLE) $finish;
end
endtask


always@(posedge sclk) begin
	$display("TIME = %d: MOSI = %b", $time, mosi);
end
always@(posedge spi_start) begin
	$display("TIME = %d: DATA = %b", $time, data_send);
end










initial fork
	gen_data_send;
	gen_spi_start;

join

spi_master
#(
	.CLK_FREQ(CLK_FREQ),
	.SPI_FREQ(SPI_FREQ),
	.DATA_WIDTH(DATA_WIDTH),
	.CPOL(CPOL),
	.CPHA(CPHA)
)
DUT(
	.clk(clk),
	.arstn(arstn),
	.data_send(data_send),
	.spi_start(spi_start),
	.sclk(sclk),
	.csn(csn),
	.mosi(mosi),
	.miso(miso),
	.spi_done(spi_done),
	.data_recv(data_recv)
);

endmodule
module spi_master_tb();


parameter	CLK_FREQ = 50_000_000,
			SPI_FREQ = 5_000_000,
			DATA_WIDTH = 8,
			CLK_CYCLE = 20,
			CPOL = 0,
			CPHA = 0;

reg	clk, arstn;
reg	[DATA_WIDTH-1:0]	data_send;
reg	spi_start;
wire	sclk, csn, mosi;
reg	miso;
wire	spi_done;
wire	[DATA_WIDTH-1:0]	data_recv;


initial begin
	clk = 0;
	forever	#(CLK_CYCLE/2)	clk = ~clk;
end


initial begin
	arstn = 1'b0;
	#(CLK_CYCLE*7/2)	arstn = 1'b1;
end


generate
	case(CPHA ^ CPOL)
		0:	begin
			always@(negedge sclk) begin
				miso = $random;
			end
		end
		1:	begin
			always@(posedge sclk) begin
				miso = $random;
			end
		end
	endcase
endgenerate


task gen_spi_start;
begin
	spi_start = 1'b0;
	@(posedge arstn)
		#(CLK_CYCLE*15)	spi_start <= 1'b1;
		#(CLK_CYCLE)	spi_start <= 1'b0;
	@(negedge spi_done)
		#(CLK_CYCLE*15)	spi_start <= 1'b1;
		#(CLK_CYCLE)	spi_start <= 1'b0;
end
endtask


task gen_data_send;
begin
	data_send = 'd0;
	@(posedge spi_start)
		data_send = 8'b10100101;
	@(posedge spi_start)
		data_send = 8'b10011010;
	@(negedge spi_done)
		#(CLK_CYCLE) $finish;
end
endtask


always@(posedge sclk) begin
	$display("TIME = %d: MOSI = %b", $time, mosi);
end
always@(posedge spi_start) begin
	$display("TIME = %d: DATA = %b", $time, data_send);
end










initial fork
	gen_data_send;
	gen_spi_start;

join

spi_master
#(
	.CLK_FREQ(CLK_FREQ),
	.SPI_FREQ(SPI_FREQ),
	.DATA_WIDTH(DATA_WIDTH),
	.CPOL(CPOL),
	.CPHA(CPHA)
)
DUT(
	.clk(clk),
	.arstn(arstn),
	.data_send(data_send),
	.spi_start(spi_start),
	.sclk(sclk),
	.csn(csn),
	.mosi(mosi),
	.miso(miso),
	.spi_done(spi_done),
	.data_recv(data_recv)
);

endmodule