data/full_repos/permissive/161526648/SingleCycle.v
1: b'%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:300: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                      : ... In instance SingleCycle.alu\n    result = ALUsrc1 < ALUsrc2;  \n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/161526648/SingleCycle.v:227: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                      : ... In instance SingleCycle.ImExtend\n assign out = $signed(in);\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module ALU(ALUsrc1,ALUsrc2,ALUControl,result,ZERO);
	parameter N=32;
	input [N-1:0]ALUsrc1,ALUsrc2;
	input [3:0]ALUControl;
	output reg [N-1:0]result;
	output reg ZERO;
	
	always @(ALUsrc1,ALUsrc2,ALUControl) begin
		case (ALUControl)
			4'b0000: result = ALUsrc1 & ALUsrc2;
			4'b0001: result = ALUsrc1 | ALUsrc2;
			4'b0010: result = ALUsrc1 + ALUsrc2;
			4'b0110: begin 
				result = ALUsrc1 - ALUsrc2;
				if(result == 0) ZERO = 1;
				else ZERO = 0;
			end
			4'b0111: begin
				result = ALUsrc1 < ALUsrc2;
				if(result == 0) ZERO = 1;
				else ZERO =0;
			end
			4'b1100: result = ~(ALUsrc1 | ALUsrc2);
		endcase
	end
endmodule
module ALU(ALUsrc1,ALUsrc2,ALUControl,result,ZERO);

	parameter N=32;
	input [N-1:0]ALUsrc1,ALUsrc2;
	input [3:0]ALUControl;
	output reg [N-1:0]result;
	output reg ZERO;
	
	always @(ALUsrc1,ALUsrc2,ALUControl) begin
		case (ALUControl)
			4'b0000: result = ALUsrc1 & ALUsrc2;
			4'b0001: result = ALUsrc1 | ALUsrc2;
			4'b0010: result = ALUsrc1 + ALUsrc2;
			4'b0110: begin 
				result = ALUsrc1 - ALUsrc2;
				if(result == 0) ZERO = 1;
				else ZERO = 0;
			end
			4'b0111: begin
				result = ALUsrc1 < ALUsrc2;
				if(result == 0) ZERO = 1;
				else ZERO =0;
			end
			4'b1100: result = ~(ALUsrc1 | ALUsrc2);
		endcase
	end
endmodule