data/full_repos/permissive/173099254/lab2/cod.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10 C=1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #10 C=0; B=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10 C=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #10 C=0; B=0; A=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #10 C=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #10 C=0; B=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10 C=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #10 B=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #10 B=0; A=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #10 B=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #10 B=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #10 B=0; A=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #10 B=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:122: Unsupported: Ignoring delay on this delayed statement.\n    #10 E=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:123: Unsupported: Ignoring delay on this delayed statement.\n    #10 A=2\'b00; I=4\'b1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:124: Unsupported: Ignoring delay on this delayed statement.\n    #10 A=2\'b01; I=4\'b0100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:125: Unsupported: Ignoring delay on this delayed statement.\n    #10 A=2\'b10; I=4\'b0010;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/173099254/lab2/cod.v:126: Unsupported: Ignoring delay on this delayed statement.\n    #10 A=2\'b11; I=4\'b0001;\n    ^\n%Warning-MULTITOP: data/full_repos/permissive/173099254/lab2/cod.v:48: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                     : ... Top module \'test_ex_1\'\nmodule test_ex_1();\n       ^~~~~~~~~\n                                                                     : ... Top module \'test_ex_2\'\nmodule test_ex_2();\n       ^~~~~~~~~\n                                                                     : ... Top module \'test_ex_3\'\nmodule test_ex_3();\n       ^~~~~~~~~\n                                                                     : ... Top module \'test_ex_4\'\nmodule test_ex_4();\n       ^~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/173099254/lab2/cod.v:101: Little bit endian vector: MSB < LSB of bit range: 0:1\ninput [0:1]A;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/173099254/lab2/cod.v:102: Little bit endian vector: MSB < LSB of bit range: 0:3\ninput [0:3]I;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/173099254/lab2/cod.v:65: Little bit endian vector: MSB < LSB of bit range: 0:3\noutput [0:3]Y;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/173099254/lab2/cod.v:116: Little bit endian vector: MSB < LSB of bit range: 0:1\n  reg [0:1]A;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/173099254/lab2/cod.v:117: Little bit endian vector: MSB < LSB of bit range: 0:3\n  reg [0:3]I;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/173099254/lab2/cod.v:85: Little bit endian vector: MSB < LSB of bit range: 0:3\n  wire [0:3]Y;\n       ^\n%Error: Exiting due to 25 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_ex_1();
  reg A, B, C;
  wire out;
  initial begin
    A=0; B=0; C=0;
    #10 C=1;
    #10 C=0; B=1;
    #10 C=1;
    #10 C=0; B=0; A=1;
    #10 C=1;
    #10 C=0; B=1;
    #10 C=1;
    end
    exercitiu_1 instanta (out, A, B, C);
endmodule
module test_ex_1();

  reg A, B, C;
  wire out;
  initial begin
    A=0; B=0; C=0;
    #10 C=1;
    #10 C=0; B=1;
    #10 C=1;
    #10 C=0; B=0; A=1;
    #10 C=1;
    #10 C=0; B=1;
    #10 C=1;
    end
    exercitiu_1 instanta (out, A, B, C);
endmodule