data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/rtl/diff_calc.v
 line:82: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/rtl/diff_calc.v:104: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_enable\' generates 1 bits.\n                                                                                                              : ... In instance diff_calc\n                ADR_ENABLE: reg_enable <= reg_mask(reg_enable, s_wb_dat_i, s_wb_sel_i);\n                                          ^~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/rtl/diff_calc.v:104: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                                              : ... In instance diff_calc\n                ADR_ENABLE: reg_enable <= reg_mask(reg_enable, s_wb_dat_i, s_wb_sel_i);\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/rtl/diff_calc.v:106: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_gain\' generates 18 bits.\n                                                                                                              : ... In instance diff_calc\n                ADR_GAIN:   reg_gain   <= reg_mask(reg_gain,   s_wb_dat_i, s_wb_sel_i);\n                                          ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/rtl/diff_calc.v:106: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                                              : ... In instance diff_calc\n                ADR_GAIN:   reg_gain   <= reg_mask(reg_gain,   s_wb_dat_i, s_wb_sel_i);\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/rtl/diff_calc.v:112: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_enable\' generates 1 bits.\n                                                                                                              : ... In instance diff_calc\n    assign s_wb_dat_o = (s_wb_adr_i == ADR_ENABLE) ? reg_enable   :\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/rtl/diff_calc.v:114: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_gain\' generates 18 bits.\n                                                                                                              : ... In instance diff_calc\n                        (s_wb_adr_i == ADR_GAIN)   ? reg_gain     :\n                                                   ^\n%Error: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/rtl/diff_calc.v:130: Cannot find file containing module: \'jelly_data_async\'\n    jelly_data_async\n    ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/rtl,data/full_repos/permissive/2084115/jelly_data_async\n             data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/rtl,data/full_repos/permissive/2084115/jelly_data_async.v\n             data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/rtl,data/full_repos/permissive/2084115/jelly_data_async.sv\n             jelly_data_async\n             jelly_data_async.v\n             jelly_data_async.sv\n             obj_dir/jelly_data_async\n             obj_dir/jelly_data_async.v\n             obj_dir/jelly_data_async.sv\n%Warning-WIDTH: data/full_repos/permissive/2084115/projects/ultra96v2_imx219_stepper_motor/rtl/diff_calc.v:196: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 50 bits.\n                                                                                                              : ... In instance diff_calc\n                st3_data <= (st2_data >>> Q_WIDTH);\n                         ^~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n'
function [WB_DAT_WIDTH-1:0] reg_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );
    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            reg_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction
function [WB_DAT_WIDTH-1:0] reg_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );

    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            reg_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction