data/full_repos/permissive/19572582/Lab2/lab2_part4.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part4.v:108: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] SSD;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part4.v:71: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] SSD;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/19572582/Lab2/lab2_part4.v:21: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] HEX1, HEX0;\n         ^\n%Error: Exiting due to 3 warning(s)\n'
module circuitA (V, A);
  input [3:0] V;
  output [3:0] A;

  assign A[0] = V[0];
  assign A[1] = ~V[1];
  assign A[2] = (~V[3] & ~V[1]) | (V[2] & V[1]);
  assign A[3] = (~V[3] & V[1]);
endmodule
module circuitA (V, A);

  input [3:0] V;
  output [3:0] A;

  assign A[0] = V[0];
  assign A[1] = ~V[1];
  assign A[2] = (~V[3] & ~V[1]) | (V[2] & V[1]);
  assign A[3] = (~V[3] & V[1]);
endmodule