data/full_repos/permissive/150214807/lab4.v
 line:123: before: "$"
1: b'%Error: data/full_repos/permissive/150214807/lab4.v:114: Unsupported or unknown PLI call: $monitor\n$monitor(,$time,"a = %h, b =%h, bin = %b, op = %b, cin = %b, res = %h, cout = %b",a,b,Binvert,Operation,Carryin,Result,CarryOut);\n^~~~~~~~\n%Error: data/full_repos/permissive/150214807/lab4.v:114: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n$monitor(,$time,"a = %h, b =%h, bin = %b, op = %b, cin = %b, res = %h, cout = %b",a,b,Binvert,Operation,Carryin,Result,CarryOut);\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab4.v:120: Unsupported: Ignoring delay on this delayed statement.\n#100 Operation=2\'b01;  \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab4.v:121: Unsupported: Ignoring delay on this delayed statement.\n#100 Operation=2\'b10;  \n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab4.v:122: Unsupported: Ignoring delay on this delayed statement.\n#100 Binvert=1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/150214807/lab4.v:123: Unsupported: Ignoring delay on this delayed statement.\n#200 $finish;\n^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ANDarray (RegDst,ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite,Branch,ALUOp0,ALUOp1,Op);
input [5:0] Op;
output RegDst,ALUSrc,MemtoReg, RegWrite, MemRead, MemWrite,Branch,ALUOp1,ALUOp0;
wire Rformat, lw,sw,beq;
assign Rformat= (~Op[0])& (~Op[1])& (~Op[2])& (~Op[3])& (~Op[4])& (~Op[5]);
assign lw = (Op[0])& (Op[1])& (~Op[2])& (~Op[3])& (~Op[4])& (Op[5]);
assign sw = (Op[0])& (Op[1])& (~Op[2])& (Op[3])& (~Op[4])& (Op[5]);
assign beq = (~Op[0])& (~Op[1])& (Op[2])& (~Op[3])& (~Op[4])& (~Op[5]);

assign RegDst = Rformat;
assign ALUSrc = lw | sw;
assign MemtoReg = lw;
assign RegWrite = Rformat | lw;
assign MemRead = lw;
assign MemWrite = sw;
assign Branch = beq;
assign AluOp0 = Rformat;
assign AluOp1 = beq;
endmodule
module ANDarray (RegDst,ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite,Branch,ALUOp0,ALUOp1,Op);

input [5:0] Op;
output RegDst,ALUSrc,MemtoReg, RegWrite, MemRead, MemWrite,Branch,ALUOp1,ALUOp0;
wire Rformat, lw,sw,beq;
assign Rformat= (~Op[0])& (~Op[1])& (~Op[2])& (~Op[3])& (~Op[4])& (~Op[5]);
assign lw = (Op[0])& (Op[1])& (~Op[2])& (~Op[3])& (~Op[4])& (Op[5]);
assign sw = (Op[0])& (Op[1])& (~Op[2])& (Op[3])& (~Op[4])& (Op[5]);
assign beq = (~Op[0])& (~Op[1])& (Op[2])& (~Op[3])& (~Op[4])& (~Op[5]);

assign RegDst = Rformat;
assign ALUSrc = lw | sw;
assign MemtoReg = lw;
assign RegWrite = Rformat | lw;
assign MemRead = lw;
assign MemWrite = sw;
assign Branch = beq;
assign AluOp0 = Rformat;
assign AluOp1 = beq;
endmodule