data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v
1: b'%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:21: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:27: Define or directive not defined: \'`INST_BUS\'\n    input      [`INST_BUS] inst_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input      [`INST_BUS] inst_in,\n                         ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:28: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] alu_res_in,  \n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:29: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] mem_read_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:30: Define or directive not defined: \'`DATA_BUS\'\n    output     [`DATA_BUS] mem_read_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:31: Define or directive not defined: \'`DATA_BUS\'\n    input      [`DATA_BUS] mem_write_in,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:32: Define or directive not defined: \'`DATA_BUS\'\n    output     [`DATA_BUS] mem_write_out,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:37: Define or directive not defined: \'`DATA_BUS\'\n    reg [`DATA_BUS] mem_write_reg;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`DATA_BUS] mem_write_reg;\n                  ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:38: Define or directive not defined: \'`DATA_BUS\'\n    reg [`DATA_BUS] mem_read_reg;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`DATA_BUS] mem_read_reg;\n                  ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:46: Define or directive not defined: \'`MEM_READ\'\n        mem_rw_reg <= `MEM_READ;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:50: Define or directive not defined: \'`INST_LW\'\n            `INST_LW: begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:51: Define or directive not defined: \'`MEM_READ\'\n                mem_rw_reg <= `MEM_READ;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:54: Define or directive not defined: \'`INST_SW\'\n            `INST_SW: begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/memory_access.v:55: Define or directive not defined: \'`MEM_WRITE\'\n                mem_rw_reg <= `MEM_WRITE;\n                              ^~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n'
module memory_access#(parameter DATA_WIDTH = 32)(
    input clk,
    input rst_n,
    
    input      [`INST_BUS] inst_in,
    input      [`DATA_BUS] alu_res_in,
    input      [`DATA_BUS] mem_read_in,
    output     [`DATA_BUS] mem_read_out,
    input      [`DATA_BUS] mem_write_in,
    output     [`DATA_BUS] mem_write_out,
    
    output                 mem_rw_out
);
    reg             mem_rw_reg;
    reg [`DATA_BUS] mem_write_reg;
    reg [`DATA_BUS] mem_read_reg;
    
    assign mem_rw_out = mem_rw_reg;
    assign mem_read_out = mem_read_reg;
    assign mem_write_out = mem_write_reg;

    always @*
    begin
        mem_rw_reg <= `MEM_READ;
        mem_read_reg <= 0;
        mem_write_reg <= 0;
        case (inst_in)
            `INST_LW: begin
                mem_rw_reg <= `MEM_READ;
                mem_read_reg <= mem_read_in;
            end
            `INST_SW: begin
                mem_rw_reg <= `MEM_WRITE;
                mem_write_reg <= mem_write_in;
            end
        endcase
    end

endmodule
module memory_access#(parameter DATA_WIDTH = 32)(
    input clk,
    input rst_n,
    
    input      [`INST_BUS] inst_in,
    input      [`DATA_BUS] alu_res_in,
    input      [`DATA_BUS] mem_read_in,
    output     [`DATA_BUS] mem_read_out,
    input      [`DATA_BUS] mem_write_in,
    output     [`DATA_BUS] mem_write_out,
    
    output                 mem_rw_out
);

    reg             mem_rw_reg;
    reg [`DATA_BUS] mem_write_reg;
    reg [`DATA_BUS] mem_read_reg;
    
    assign mem_rw_out = mem_rw_reg;
    assign mem_read_out = mem_read_reg;
    assign mem_write_out = mem_write_reg;

    always @*
    begin
        mem_rw_reg <= `MEM_READ;
        mem_read_reg <= 0;
        mem_write_reg <= 0;
        case (inst_in)
            `INST_LW: begin
                mem_rw_reg <= `MEM_READ;
                mem_read_reg <= mem_read_in;
            end
            `INST_SW: begin
                mem_rw_reg <= `MEM_WRITE;
                mem_write_reg <= mem_write_in;
            end
        endcase
    end

endmodule