data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh
 line:13: before: "interface"
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:7: Cannot find include file: sim_axis_lib.svh\n`include "sim_axis_lib.svh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi,data/full_repos/permissive/214858095/sim_axis_lib.svh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi,data/full_repos/permissive/214858095/sim_axis_lib.svh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi,data/full_repos/permissive/214858095/sim_axis_lib.svh.sv\n             sim_axis_lib.svh\n             sim_axis_lib.svh.v\n             sim_axis_lib.svh.sv\n             obj_dir/sim_axis_lib.svh\n             obj_dir/sim_axis_lib.svh.v\n             obj_dir/sim_axis_lib.svh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:36: Unsupported: Initial values in struct/union members.\n  logic         eob = 1\'b0;\n                      ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:37: Unsupported: Initial values in struct/union members.\n  logic         has_time = 1\'b0;\n                           ^~~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:38: Unsupported: Initial values in struct/union members.\n  logic [63:0]  timestamp = \'d0;\n                            ^~~\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:140: syntax error, unexpected \'@\'\n      if (clk) @(negedge clk);                     \n               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:144: syntax error, unexpected \'@\'\n      @(posedge clk);                              \n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:145: syntax error, unexpected \'@\'\n      while(~axis.tready[stream]) @(posedge clk);  \n                                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:159: syntax error, unexpected \'@\'\n      @(negedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:185: syntax error, unexpected \'@\'\n      @(negedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:212: syntax error, unexpected \'@\'\n      @(negedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:286: syntax error, unexpected \'@\'\n      if (clk) @(negedge clk);\n               ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:288: syntax error, unexpected \'@\'\n      while(~axis.tvalid[stream]) @(posedge clk);\n                                  ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:291: syntax error, unexpected \'@\'\n      @(negedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:310: syntax error, unexpected \'@\'\n      while(~(axis.tready[stream]&axis.tvalid[stream])) @(posedge clk);   \n                                                        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:313: syntax error, unexpected \'@\'\n      @(negedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:324: syntax error, unexpected \'@\'\n      while(axis.tready[stream]&axis.tvalid[stream]) @(posedge clk);\n                                                     ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:336: syntax error, unexpected \'@\'\n      while(~(axis.tready[stream]&axis.tvalid[stream]&axis.tlast[stream])) @(posedge clk);\n                                                                           ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:408: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:413: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:428: syntax error, unexpected \'@\'\n          @(posedge clk);\n          ^\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/sim/axi/sim_cvita_lib.svh:431: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: Exiting due to 21 error(s)\n'
function logic chdr_compare(input cvita_hdr_t a, input cvita_hdr_t b);
  return ((a.pkt_type == b.pkt_type) && (a.has_time == b.has_time) && (a.eob == b.eob) &&
          (a.seqnum == b.seqnum) && (a.length == b.length) && (a.src_sid == b.src_sid) && (a.dst_sid == b.dst_sid));
endfunction
function logic chdr_compare(input cvita_hdr_t a, input cvita_hdr_t b);

  return ((a.pkt_type == b.pkt_type) && (a.has_time == b.has_time) && (a.eob == b.eob) &&
          (a.seqnum == b.seqnum) && (a.length == b.length) && (a.src_sid == b.src_sid) && (a.dst_sid == b.dst_sid));
endfunction