data/full_repos/permissive/200314387/verilog/74670/hct74670.v
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data/verilator_xmls/55a0872f-53eb-4b3b-bcf9-f2b0f353a643.xml
module hct74670 (input _wr_en,
                 input [1:0] wr_addr,
                 input [3:0] wr_data,
                 input _rd_en,
                 input [1:0] rd_addr,
                 output [3:0] rd_data);
    
    parameter LOG=0;

    localparam PD_RE_TO_Q=18;
    localparam PD_A_TO_Q=21;
    localparam PD_D_TO_Q=27;
    localparam PD_WE_TO_Q=28;



    reg [3:0] registers[3:0];
    reg [3:0] tmp_data;





    initial begin
        if (LOG) $display("INITIALISING EMPTY REGISTER %m FILE TO VALUES [0,1,2,3]");
        registers[0] = 0;
        registers[1] = 1;
        registers[2] = 2;
        registers[3] = 3;
    end
      
    reg [3:0] out_val;
    
    specify
        (_rd_en *> rd_data)  = PD_RE_TO_Q;
        (_wr_en *> rd_data)  = PD_WE_TO_Q;
        (rd_addr *> rd_data) = PD_A_TO_Q;
        (wr_data => rd_data) = PD_D_TO_Q;
    endspecify
    

    always @* begin
        if (!_wr_en) begin
            registers[wr_addr] = wr_data;
        end
    end

    always @(registers[0]) begin
            if (LOG) $display("%9t ", $time, ": 74670 setting reg[0]  <= ", registers[0], " : %m");
    end
    always @(registers[1]) begin
            if (LOG) $display("%9t ", $time, ": 74670 setting reg[1]  <= ", registers[1], " : %m");
    end
    always @(registers[2]) begin
            if (LOG) $display("%9t ", $time, ": 74670 setting reg[2]  <= ", registers[2], " : %m");
    end
    always @(registers[3]) begin
            if (LOG) $display("%9t ", $time, ": 74670 setting reg[3]  <= ", registers[3], " : %m");
    end
        
        

    always_comb

    begin
        out_val = registers[rd_addr];
    end
    
    assign rd_data = _rd_en ? 4'bz : out_val;
    
endmodule
module hct74670 (input _wr_en,
                 input [1:0] wr_addr,
                 input [3:0] wr_data,
                 input _rd_en,
                 input [1:0] rd_addr,
                 output [3:0] rd_data);

    
    parameter LOG=0;

    localparam PD_RE_TO_Q=18;
    localparam PD_A_TO_Q=21;
    localparam PD_D_TO_Q=27;
    localparam PD_WE_TO_Q=28;



    reg [3:0] registers[3:0];
    reg [3:0] tmp_data;





    initial begin
        if (LOG) $display("INITIALISING EMPTY REGISTER %m FILE TO VALUES [0,1,2,3]");
        registers[0] = 0;
        registers[1] = 1;
        registers[2] = 2;
        registers[3] = 3;
    end
      
    reg [3:0] out_val;
    
    specify
        (_rd_en *> rd_data)  = PD_RE_TO_Q;
        (_wr_en *> rd_data)  = PD_WE_TO_Q;
        (rd_addr *> rd_data) = PD_A_TO_Q;
        (wr_data => rd_data) = PD_D_TO_Q;
    endspecify
    

    always @* begin
        if (!_wr_en) begin
            registers[wr_addr] = wr_data;
        end
    end

    always @(registers[0]) begin
            if (LOG) $display("%9t ", $time, ": 74670 setting reg[0]  <= ", registers[0], " : %m");
    end
    always @(registers[1]) begin
            if (LOG) $display("%9t ", $time, ": 74670 setting reg[1]  <= ", registers[1], " : %m");
    end
    always @(registers[2]) begin
            if (LOG) $display("%9t ", $time, ": 74670 setting reg[2]  <= ", registers[2], " : %m");
    end
    always @(registers[3]) begin
            if (LOG) $display("%9t ", $time, ": 74670 setting reg[3]  <= ", registers[3], " : %m");
    end
        
        

    always_comb

    begin
        out_val = registers[rd_addr];
    end
    
    assign rd_data = _rd_en ? 4'bz : out_val;
    
endmodule