data/full_repos/permissive/143278/ivltests/pr2029336.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2029336.v:64: Unsupported: Ignoring delay on this delayed statement.\n always #1\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
	parameter WIDTH = 33;
	reg clk;
	reg [WIDTH-1:0] in;
	reg [WIDTH-1:0] test_val1;
	reg [WIDTH-1:0] test_val2;
	reg [WIDTH-1:0] test_val3;
	integer infile, outfile, count;

	initial begin
		clk = 0;
		in = 0;
		test_val1 = 1 << 30;
		test_val2 = 1 << 31;
		test_val3 = 1 << 32;
		infile = $fopen("ivltests/pr2029336.in", "r");
		outfile = $fopen("work/pr2029336.out", "w");
		$fwrite(outfile, "# x = %d\n", test_val1);
		$fwrite(outfile, "# x = %d\n", test_val2);
		$fwrite(outfile, "# x = %d\n", test_val3);
	end

	always @(negedge clk) begin
		$fwrite(outfile, "%d\n", in);
		count = $fscanf(infile, "%d\n", in);
		if (count != 1) begin
			$fclose(infile);
			$fclose(outfile);
			$finish;
		end
	end

	always #1
		clk = ~clk;

endmodule
module testbench;

	parameter WIDTH = 33;
	reg clk;
	reg [WIDTH-1:0] in;
	reg [WIDTH-1:0] test_val1;
	reg [WIDTH-1:0] test_val2;
	reg [WIDTH-1:0] test_val3;
	integer infile, outfile, count;

	initial begin
		clk = 0;
		in = 0;
		test_val1 = 1 << 30;
		test_val2 = 1 << 31;
		test_val3 = 1 << 32;
		infile = $fopen("ivltests/pr2029336.in", "r");
		outfile = $fopen("work/pr2029336.out", "w");
		$fwrite(outfile, "# x = %d\n", test_val1);
		$fwrite(outfile, "# x = %d\n", test_val2);
		$fwrite(outfile, "# x = %d\n", test_val3);
	end

	always @(negedge clk) begin
		$fwrite(outfile, "%d\n", in);
		count = $fscanf(infile, "%d\n", in);
		if (count != 1) begin
			$fclose(infile);
			$fclose(outfile);
			$finish;
		end
	end

	always #1
		clk = ~clk;

endmodule