data/full_repos/permissive/168395472/problems/03_led_blink/top.v
data/verilator_xmls/fc9d7803-be5e-4a72-b693-37f64a3bcbdc.xml
module top(
    input CLK,

    output DS_C,
    output DS_EN1, DS_EN2, DS_EN3, DS_EN4
);

assign {DS_EN1, DS_EN2, DS_EN3, DS_EN4} = 4'b1111;



endmodule
module top(
    input CLK,

    output DS_C,
    output DS_EN1, DS_EN2, DS_EN3, DS_EN4
);


assign {DS_EN1, DS_EN2, DS_EN3, DS_EN4} = 4'b1111;



endmodule