data/full_repos/permissive/212020337/read_only_memory_module.v
1: b'%Warning-WIDTH: data/full_repos/permissive/212020337/read_only_memory_module.v:34: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                 : ... In instance rom_module\n          data_register[write_pointer[3:0]] <= data_in;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212020337/read_only_memory_module.v:34: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_in\' generates 4 bits.\n                                                                                 : ... In instance rom_module\n          data_register[write_pointer[3:0]] <= data_in;\n                                            ^~\n%Error: Exiting due to 2 warning(s)\n'
module rom_module(
    output [3:0] data_out,
    input  [3:0] data_in,
    input  [3:0] write_pointer,
    input  [3:0] read_pointer,
    input        write_enable,
    input        read_enable,
    input        clk
    );


    reg  [7:0] data_register[7:0];


    wire [3:0] data_bus;


    always @(posedge clk)
    begin
        if (write_enable) begin
          data_register[write_pointer[3:0]] <= data_in;
        end
    end
endmodule
module rom_module(
    output [3:0] data_out,
    input  [3:0] data_in,
    input  [3:0] write_pointer,
    input  [3:0] read_pointer,
    input        write_enable,
    input        read_enable,
    input        clk
    );



    reg  [7:0] data_register[7:0];


    wire [3:0] data_bus;


    always @(posedge clk)
    begin
        if (write_enable) begin
          data_register[write_pointer[3:0]] <= data_in;
        end
    end
endmodule