data/full_repos/permissive/13953106/lib/LAG_pl_input_trunk.v
 line:28: before: "data_in"
1: b"%Error: data/full_repos/permissive/13953106/lib/LAG_pl_input_trunk.v:28: syntax error, unexpected IDENTIFIER, expecting ';'\n   input  flit_t data_in [num_pls-1:0];\n                 ^~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_pl_input_trunk.v:29: syntax error, unexpected IDENTIFIER, expecting ';'\n   output flit_t data_out [num_pls-1:0];\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/13953106/lib/LAG_pl_input_trunk.v:30: syntax error, unexpected IDENTIFIER, expecting ';'\n   output fifov_flags_t flags [num_pls-1:0];\n                        ^~~~~\n%Error: Exiting due to 3 error(s)\n"
module LAG_pl_input_trunk(push, pop, data_in, data_out, flags, 

			allocated_pl, allocated_pl_valid,

			pl_new, pl_new_valid, 
			clk, rst_n);


   parameter num_pls = 4;
   

   parameter buffer_length = 8;

   input  clk, rst_n;
   input  [num_pls-1:0] push;
   input  [num_pls-1:0] pop;
   input  flit_t data_in [num_pls-1:0];
   output flit_t data_out [num_pls-1:0];
   output fifov_flags_t flags [num_pls-1:0];
   output [num_pls-1:0] allocated_pl [num_pls-1:0];
   output [num_pls-1:0] allocated_pl_valid;
	 
   input [num_pls-1:0][num_pls-1:0] pl_new;
   input [num_pls-1:0] 	pl_new_valid;

   logic [num_pls-1:0] pl_reg [num_pls-1:0];
   logic [num_pls-1:0] allocated_pl_valid;

   flit_t buffer_data_out [num_pls-1:0];
   flit_t routed [num_pls-1:0];

   logic sel_allocated_pl_valid;
   logic [num_pls-1:0] sel_pl_reg, sel_pl_new;
   
   integer i;
   genvar pl;

   




   LAG_pl_buffers #(.size(buffer_length),
		   .n(num_pls)) pl_bufsi
     (.push(push), .pop(pop), .data_in(data_in),
      .data_out(buffer_data_out), 
      .flags(flags), .clk, .rst_n);

   generate
   for (pl=0; pl<num_pls; pl++) begin:eachpl
    




	   assign allocated_pl[pl] = pl_reg[pl];
	   assign data_out[pl] = buffer_data_out[pl];
	  
   end
   endgenerate

   always@(posedge clk) begin
      if (!rst_n) begin
	 for (i=0; i<num_pls; i++) begin

	    allocated_pl_valid[i]<=1'b0;
	 end
      end else begin
	 



	 
	 for (i=0; i<num_pls; i++) begin

	    if (buffer_data_out[i].control.tail && pop[i]) begin



	       allocated_pl_valid[i]<=1'b0;
	       pl_reg[i]<='0;
	    end else begin



	       
	       if (pl_new_valid[i]) begin




		  allocated_pl_valid[i]<=1'b1;
		  pl_reg[i]<=pl_new[i];

		  assert (pl_new[i]!='0) else begin
		     $display ("New PL id. is blank?"); $fatal;
		  end
	       end
	    end
	 end
      end
   end

endmodule
module LAG_pl_input_trunk(push, pop, data_in, data_out, flags, 

			allocated_pl, allocated_pl_valid,

			pl_new, pl_new_valid, 
			clk, rst_n);



   parameter num_pls = 4;
   

   parameter buffer_length = 8;

   input  clk, rst_n;
   input  [num_pls-1:0] push;
   input  [num_pls-1:0] pop;
   input  flit_t data_in [num_pls-1:0];
   output flit_t data_out [num_pls-1:0];
   output fifov_flags_t flags [num_pls-1:0];
   output [num_pls-1:0] allocated_pl [num_pls-1:0];
   output [num_pls-1:0] allocated_pl_valid;
	 
   input [num_pls-1:0][num_pls-1:0] pl_new;
   input [num_pls-1:0] 	pl_new_valid;

   logic [num_pls-1:0] pl_reg [num_pls-1:0];
   logic [num_pls-1:0] allocated_pl_valid;

   flit_t buffer_data_out [num_pls-1:0];
   flit_t routed [num_pls-1:0];

   logic sel_allocated_pl_valid;
   logic [num_pls-1:0] sel_pl_reg, sel_pl_new;
   
   integer i;
   genvar pl;

   




   LAG_pl_buffers #(.size(buffer_length),
		   .n(num_pls)) pl_bufsi
     (.push(push), .pop(pop), .data_in(data_in),
      .data_out(buffer_data_out), 
      .flags(flags), .clk, .rst_n);

   generate
   for (pl=0; pl<num_pls; pl++) begin:eachpl
    




	   assign allocated_pl[pl] = pl_reg[pl];
	   assign data_out[pl] = buffer_data_out[pl];
	  
   end
   endgenerate

   always@(posedge clk) begin
      if (!rst_n) begin
	 for (i=0; i<num_pls; i++) begin

	    allocated_pl_valid[i]<=1'b0;
	 end
      end else begin
	 



	 
	 for (i=0; i<num_pls; i++) begin

	    if (buffer_data_out[i].control.tail && pop[i]) begin



	       allocated_pl_valid[i]<=1'b0;
	       pl_reg[i]<='0;
	    end else begin



	       
	       if (pl_new_valid[i]) begin




		  allocated_pl_valid[i]<=1'b1;
		  pl_reg[i]<=pl_new[i];

		  assert (pl_new[i]!='0) else begin
		     $display ("New PL id. is blank?"); $fatal;
		  end
	       end
	    end
	 end
      end
   end

endmodule