data/full_repos/permissive/135077285/alu.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/135077285/alu.v:5: Little bit endian vector: MSB < LSB of bit range: 0:3\n  input wire [0:3] unidadeControle,\n             ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/135077285/alu.v:6: Little bit endian vector: MSB < LSB of bit range: 0:31\n  output reg [0:31] saida,\n             ^\n%Warning-WIDTH: data/full_repos/permissive/135077285/alu.v:22: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                             : ... In instance alu\n      4: saida <= (entrada1 < entrada2);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/135077285/alu.v:23: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s OR generates 32 bits.\n                                                             : ... In instance alu\n      5: saida <= !(entrada1 | entrada2);\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/135077285/alu.v:23: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s LOGNOT generates 1 bits.\n                                                             : ... In instance alu\n      5: saida <= !(entrada1 | entrada2);\n               ^~\n%Error: Exiting due to 5 warning(s)\n'
module alu (
  input wire [31:0] entrada1,
  input wire [31:0] entrada2,
  input wire [0:3] unidadeControle,
  output reg [0:31] saida,
  output reg zero
);







  always @(*) begin
    case (unidadeControle)
      0: saida <= entrada1 + entrada2;
      1: saida <= entrada1 - entrada2;
      2: saida <= entrada1 & entrada2;
      3: saida <= entrada1 | entrada2;
      4: saida <= (entrada1 < entrada2);
      5: saida <= !(entrada1 | entrada2);
      6: saida <= 0;
    endcase

    zero = (saida == 0);
  end
endmodule
module alu (
  input wire [31:0] entrada1,
  input wire [31:0] entrada2,
  input wire [0:3] unidadeControle,
  output reg [0:31] saida,
  output reg zero
);








  always @(*) begin
    case (unidadeControle)
      0: saida <= entrada1 + entrada2;
      1: saida <= entrada1 - entrada2;
      2: saida <= entrada1 & entrada2;
      3: saida <= entrada1 | entrada2;
      4: saida <= (entrada1 < entrada2);
      5: saida <= !(entrada1 | entrada2);
      6: saida <= 0;
    endcase

    zero = (saida == 0);
  end
endmodule