data/full_repos/permissive/156129873/verilog/regs.v
1: b'%Error: data/full_repos/permissive/156129873/verilog/regs.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/156129873/verilog/regs.v:31: Define or directive not defined: \'`RstEnable\'\n    if (rst == `RstEnable) begin\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/regs.v:31: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if (rst == `RstEnable) begin\n                         ^\n%Error: data/full_repos/permissive/156129873/verilog/regs.v:44: syntax error, unexpected else\n    end else begin\n        ^~~~\n%Error: data/full_repos/permissive/156129873/verilog/regs.v:46: Define or directive not defined: \'`Enable\'\n        if (we == `Enable) begin\n                  ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/regs.v:57: Define or directive not defined: \'`Enable\'\n    if (re1 == `Enable && we == `Enable && reg1Addr == regAddr) begin\n               ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/regs.v:57: Define or directive not defined: \'`Enable\'\n    if (re1 == `Enable && we == `Enable && reg1Addr == regAddr) begin\n                                ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/regs.v:59: Define or directive not defined: \'`Enable\'\n    end else if (re1 == `Enable) begin\n                        ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/regs.v:65: Define or directive not defined: \'`Enable\'\n    if (re2 == `Enable && we == `Enable && reg2Addr == regAddr) begin\n               ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/regs.v:65: Define or directive not defined: \'`Enable\'\n    if (re2 == `Enable && we == `Enable && reg2Addr == regAddr) begin\n                                ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/regs.v:67: Define or directive not defined: \'`Enable\'\n    end else if (re2 == `Enable) begin\n                        ^~~~~~~\n%Error: Cannot continue\n'
module regs (


    input wire clk,


    input wire rst,


    input wire re1,
    input wire re2,
    input wire[3:0] reg1Addr,
    input wire[3:0] reg2Addr,


    input wire[15:0] regData,
    input wire[3:0] regAddr,
    input wire we,


    output reg[15:0] reg1Data,
    output reg[15:0] reg2Data,
	 output reg[15:0] led
);

reg[15:0] registers[11:0];

always @(posedge clk) begin
    if (rst == `RstEnable) begin
        registers[0] <= 16'd0;
        registers[1] <= 16'd0;
        registers[2] <= 16'd0;
        registers[3] <= 16'd0;
        registers[4] <= 16'd0;
        registers[5] <= 16'd0;
        registers[6] <= 16'd0;
        registers[7] <= 16'd0;
        registers[8] <= 16'hfe00;
        registers[9] <= 16'd0;
        registers[10] <= 16'd0;
        registers[11] <= 16'd0;
    end else begin

        if (we == `Enable) begin
            registers[regAddr] <= regData;
        end
    end
end

always @(registers[0], registers[1], registers[2],
		registers[3], registers[4], registers[5], registers[6],
		registers[7], registers[8], registers[9], registers[10],
		registers[11], re1, re2, we, reg1Addr, reg2Addr, regAddr, regData) begin

    if (re1 == `Enable && we == `Enable && reg1Addr == regAddr) begin
        reg1Data = regData;
    end else if (re1 == `Enable) begin
        reg1Data = registers[reg1Addr];
    end else begin
        reg1Data = 16'd0;
    end

    if (re2 == `Enable && we == `Enable && reg2Addr == regAddr) begin
        reg2Data = regData;
    end else if (re2 == `Enable) begin
        reg2Data = registers[reg2Addr];
    end else begin
        reg2Data = 16'd0;
    end
	 
	 led = registers[2];
end

endmodule
module regs (


    input wire clk,


    input wire rst,


    input wire re1,
    input wire re2,
    input wire[3:0] reg1Addr,
    input wire[3:0] reg2Addr,


    input wire[15:0] regData,
    input wire[3:0] regAddr,
    input wire we,


    output reg[15:0] reg1Data,
    output reg[15:0] reg2Data,
	 output reg[15:0] led
);


reg[15:0] registers[11:0];

always @(posedge clk) begin
    if (rst == `RstEnable) begin
        registers[0] <= 16'd0;
        registers[1] <= 16'd0;
        registers[2] <= 16'd0;
        registers[3] <= 16'd0;
        registers[4] <= 16'd0;
        registers[5] <= 16'd0;
        registers[6] <= 16'd0;
        registers[7] <= 16'd0;
        registers[8] <= 16'hfe00;
        registers[9] <= 16'd0;
        registers[10] <= 16'd0;
        registers[11] <= 16'd0;
    end else begin

        if (we == `Enable) begin
            registers[regAddr] <= regData;
        end
    end
end

always @(registers[0], registers[1], registers[2],
		registers[3], registers[4], registers[5], registers[6],
		registers[7], registers[8], registers[9], registers[10],
		registers[11], re1, re2, we, reg1Addr, reg2Addr, regAddr, regData) begin

    if (re1 == `Enable && we == `Enable && reg1Addr == regAddr) begin
        reg1Data = regData;
    end else if (re1 == `Enable) begin
        reg1Data = registers[reg1Addr];
    end else begin
        reg1Data = 16'd0;
    end

    if (re2 == `Enable && we == `Enable && reg2Addr == regAddr) begin
        reg2Data = regData;
    end else if (re2 == `Enable) begin
        reg2Data = registers[reg2Addr];
    end else begin
        reg2Data = 16'd0;
    end
	 
	 led = registers[2];
end

endmodule