data/full_repos/permissive/166008742/src/syn_fifo.v
1: b"%Error: data/full_repos/permissive/166008742/src/syn_fifo.v:76: Cannot find file containing module: 'dp_ram'\ndp_ram #(DATA_WIDTH, ADDR_WIDTH, RAM_DEPTH) dp_ram_inst\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/dp_ram\n             data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/dp_ram.v\n             data/full_repos/permissive/166008742/src,data/full_repos/permissive/166008742/dp_ram.sv\n             dp_ram\n             dp_ram.v\n             dp_ram.sv\n             obj_dir/dp_ram\n             obj_dir/dp_ram.v\n             obj_dir/dp_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module syn_fifo (
    input                   clk,
    input                   rst,
    input                   wr,
    input                   rd,
    input  [DATA_WIDTH-1:0] data_in,
    output [DATA_WIDTH-1:0] data_out,
    output                  empty,
    output                  full
);    
 

parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = (1 << ADDR_WIDTH);


reg  [ADDR_WIDTH-1:0] wr_pointer;
reg  [ADDR_WIDTH-1:0] rd_pointer;
reg  [ADDR_WIDTH-1:0] status_cnt;
wire [DATA_WIDTH-1:0] data_ram;


assign full = (status_cnt == RAM_DEPTH);
assign empty = (status_cnt == 0);


always @ (posedge clk or posedge rst) begin
    if (rst) begin
        wr_pointer <= 0;
    end else if (wr) begin
        if (wr_pointer < RAM_DEPTH-1) begin
            wr_pointer <= wr_pointer + 1;
        end
        else begin
            wr_pointer <= 0;
        end
    end
end

always @ (posedge clk or posedge rst) begin
    if (rst) begin
        rd_pointer <= 0;
    end else if (rd) begin
        if (rd_pointer < RAM_DEPTH-1) begin
            rd_pointer <= rd_pointer + 1;
        end
        else begin
            rd_pointer <= 0;
        end
    end
end

assign data_out = data_ram;

always @ (posedge clk or posedge rst)
begin : STATUS_COUNTER
  if (rst) begin
    status_cnt <= 0;

  end else if (rd && !wr && (status_cnt != 0)) begin
    status_cnt <= status_cnt - 1;

  end else if (wr && !rd && (status_cnt != RAM_DEPTH)) begin
    status_cnt <= status_cnt + 1;
  end
end 

dp_ram #(DATA_WIDTH, ADDR_WIDTH, RAM_DEPTH) dp_ram_inst
(
    .clk     (clk)        ,
    .wr_addr (wr_pointer) ,
    .wr_data (data_in)    ,
    .wr      (wr)         ,
    .rd_addr (rd_pointer) ,
    .rd_data (data_ram)   ,
    .rd      (rd)
);     

endmodule
module syn_fifo (
    input                   clk,
    input                   rst,
    input                   wr,
    input                   rd,
    input  [DATA_WIDTH-1:0] data_in,
    output [DATA_WIDTH-1:0] data_out,
    output                  empty,
    output                  full
);
    
 

parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = (1 << ADDR_WIDTH);


reg  [ADDR_WIDTH-1:0] wr_pointer;
reg  [ADDR_WIDTH-1:0] rd_pointer;
reg  [ADDR_WIDTH-1:0] status_cnt;
wire [DATA_WIDTH-1:0] data_ram;


assign full = (status_cnt == RAM_DEPTH);
assign empty = (status_cnt == 0);


always @ (posedge clk or posedge rst) begin
    if (rst) begin
        wr_pointer <= 0;
    end else if (wr) begin
        if (wr_pointer < RAM_DEPTH-1) begin
            wr_pointer <= wr_pointer + 1;
        end
        else begin
            wr_pointer <= 0;
        end
    end
end

always @ (posedge clk or posedge rst) begin
    if (rst) begin
        rd_pointer <= 0;
    end else if (rd) begin
        if (rd_pointer < RAM_DEPTH-1) begin
            rd_pointer <= rd_pointer + 1;
        end
        else begin
            rd_pointer <= 0;
        end
    end
end

assign data_out = data_ram;

always @ (posedge clk or posedge rst)
begin : STATUS_COUNTER
  if (rst) begin
    status_cnt <= 0;

  end else if (rd && !wr && (status_cnt != 0)) begin
    status_cnt <= status_cnt - 1;

  end else if (wr && !rd && (status_cnt != RAM_DEPTH)) begin
    status_cnt <= status_cnt + 1;
  end
end 

dp_ram #(DATA_WIDTH, ADDR_WIDTH, RAM_DEPTH) dp_ram_inst
(
    .clk     (clk)        ,
    .wr_addr (wr_pointer) ,
    .wr_data (data_in)    ,
    .wr      (wr)         ,
    .rd_addr (rd_pointer) ,
    .rd_data (data_ram)   ,
    .rd      (rd)
);     

endmodule