data/full_repos/permissive/163534413/Abs16.v
data/verilator_xmls/70d06224-5e9b-4f97-8924-e68b331a315b.xml
module Abs16(X,Y,Neg);

	input [15:0] X;
	output [15:0] Y;
	output Neg;
	
	assign Neg = X[15];
	assign Y = Neg ? -X : X;

endmodule
module Abs16(X,Y,Neg);


	input [15:0] X;
	output [15:0] Y;
	output Neg;
	
	assign Neg = X[15];
	assign Y = Neg ? -X : X;

endmodule