data/full_repos/permissive/219219909/Complex_Multiplier/adder12.v
data/verilator_xmls/482ffe66-3114-425f-8c16-e22bd00f98c9.xml
module adder12(
    input [11:0] a,
    input [11:0] b,
    output [11:0] s
    );

assign s=a+b;
endmodule
module adder12(
    input [11:0] a,
    input [11:0] b,
    output [11:0] s
    );


assign s=a+b;
endmodule