data/full_repos/permissive/211878730/atlys/practice/halfadder.v
data/verilator_xmls/32d0c160-6d29-4797-bbcb-14af7cc700af.xml
module halfadder(a, b, c, s);
	input  wire a;
	input  wire b;
	output wire c;
	output wire s;
	


	

	


	
	reg [1:0] sum;
	
	always @(*) begin
		case({a, b})
			2'b00: sum = 2'b00;
			2'b01: sum = 2'b01;
			2'b10: sum = 2'b01;
			2'b11: sum = 2'b10;
		endcase
	end
	
	assign {c, s} = sum;
endmodule
module halfadder(a, b, c, s);

	input  wire a;
	input  wire b;
	output wire c;
	output wire s;
	


	

	


	
	reg [1:0] sum;
	
	always @(*) begin
		case({a, b})
			2'b00: sum = 2'b00;
			2'b01: sum = 2'b01;
			2'b10: sum = 2'b01;
			2'b11: sum = 2'b10;
		endcase
	end
	
	assign {c, s} = sum;
endmodule