data/full_repos/permissive/169496369/alu_big.v
Syntax Error
1: b'%Warning-WIDTH: data/full_repos/permissive/169496369/alu_big.v:85: Operator ASSIGN expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'23\'h0\' generates 23 bits.\n                                                                 : ... In instance alu_big\n                                    c = 23\'d0;\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module alu_big(a, b, asign, bsign, op, csign, c);
    input [23:0]a, b;
    input asign, bsign, op;
    output logic [24:0]c;
    output logic csign;
    
    logic overflow = 0;
            logic [24:0] am, bm = 25'd0;
            logic [24:0] cm = 25'd0;
            
            always_comb
                begin
                    case(op)
                        0:
                        begin
                            if(asign == bsign)
                            begin
                                c = a + b;
                                csign = asign;
                            end
                            else if(asign > bsign)
                                if(b >= a)
                                begin
                                    csign = bsign;
                                    c = b - a;
                                end
                                else
                                begin
                                    csign = asign;
                                    c = a - b;
                                end
                            else
                            begin
                                if(a >= b)
                                begin
                                    csign = asign;
                                    c = a - b;
                                end
                                else
                                begin
                                    csign = bsign;
                                    c = b - a;
                                end
                            end   
                        end
                        1:
                        begin
                            if(asign == bsign)
                            begin
                                if (a > b)
                                begin
                                    csign = asign;
                                    c = a - b;
                                end
                                else if(b > a)
                                begin
                                    csign = bsign;
                                    c = b - a;
                                end
                                else
                                begin
                                    csign = 0;
                                    c = 23'd0;
                                end
                            end
                            else
                            begin
                                csign = asign;
                                c = a + b;
                            end
                        end
                    endcase
                end

endmodule
module alu_big(a, b, asign, bsign, op, csign, c);

    input [23:0]a, b;
    input asign, bsign, op;
    output logic [24:0]c;
    output logic csign;
    
    logic overflow = 0;
            logic [24:0] am, bm = 25'd0;
            logic [24:0] cm = 25'd0;
            
            always_comb
                begin
                    case(op)
                        0:
                        begin
                            if(asign == bsign)
                            begin
                                c = a + b;
                                csign = asign;
                            end
                            else if(asign > bsign)
                                if(b >= a)
                                begin
                                    csign = bsign;
                                    c = b - a;
                                end
                                else
                                begin
                                    csign = asign;
                                    c = a - b;
                                end
                            else
                            begin
                                if(a >= b)
                                begin
                                    csign = asign;
                                    c = a - b;
                                end
                                else
                                begin
                                    csign = bsign;
                                    c = b - a;
                                end
                            end   
                        end
                        1:
                        begin
                            if(asign == bsign)
                            begin
                                if (a > b)
                                begin
                                    csign = asign;
                                    c = a - b;
                                end
                                else if(b > a)
                                begin
                                    csign = bsign;
                                    c = b - a;
                                end
                                else
                                begin
                                    csign = 0;
                                    c = 23'd0;
                                end
                            end
                            else
                            begin
                                csign = asign;
                                c = a + b;
                            end
                        end
                    endcase
                end

endmodule