data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v
None: at end of input
1: b'%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:3: Cannot find include file: user_constants.vh\n`include "user_constants.vh" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197252258/src/user_defined_logic/reno,data/full_repos/permissive/197252258/user_constants.vh\n             data/full_repos/permissive/197252258/src/user_defined_logic/reno,data/full_repos/permissive/197252258/user_constants.vh.v\n             data/full_repos/permissive/197252258/src/user_defined_logic/reno,data/full_repos/permissive/197252258/user_constants.vh.sv\n             user_constants.vh\n             user_constants.vh.v\n             user_constants.vh.sv\n             obj_dir/user_constants.vh\n             obj_dir/user_constants.vh.v\n             obj_dir/user_constants.vh.sv\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:133: Cannot find include file: clogb2.vh\n`include "clogb2.vh" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:7: Define or directive not defined: \'`PKT_TYPE_W\'\n    input   [`PKT_TYPE_W-1:0]       pkt_type_in,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:8: Define or directive not defined: \'`PKT_DATA_W\'\n    input   [`PKT_DATA_W-1:0]       pkt_data_in,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:9: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   cumulative_ack_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:10: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   selective_ack_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:11: Define or directive not defined: \'`TX_CNT_W\'\n    input   [`TX_CNT_W-1:0]         sack_tx_id_in,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:13: Define or directive not defined: \'`TIME_W\'\n    input   [`TIME_W-1:0]           now,\n             ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:14: Define or directive not defined: \'`FLAG_W\'\n    input   [`FLAG_W-1:0]           valid_selective_ack,\n             ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:15: Define or directive not defined: \'`FLOW_WIN_IND_W\'\n    input   [`FLOW_WIN_IND_W-1:0]   new_c_acks_cnt,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:16: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   old_wnd_start_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:18: Define or directive not defined: \'`FLOW_WIN_SIZE\'\n    input   [`FLOW_WIN_SIZE-1:0]    acked_wnd_in,\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:19: Define or directive not defined: \'`FLOW_WIN_SIZE\'\n    input   [`FLOW_WIN_SIZE-1:0]    rtx_wnd_in,\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:20: Define or directive not defined: \'`TX_CNT_WIN_SIZE\'\n    input   [`TX_CNT_WIN_SIZE-1:0]  tx_cnt_wnd_in,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:21: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   wnd_start_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:22: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\n    input   [`FLOW_WIN_SIZE_W-1:0]  wnd_size_in,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:23: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   next_new_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:24: Define or directive not defined: \'`TIMER_W\'\n    input   [`TIMER_W-1:0]          rtx_timer_amnt_in,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:25: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    input   [`FLOW_SEQ_NUM_W-1:0]   total_tx_cnt_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:26: Define or directive not defined: \'`USER_CONTEXT_W\'\n    input   [`USER_CONTEXT_W-1:0]   user_cntxt_in,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:29: Define or directive not defined: \'`FLAG_W\'\n    output  [`FLAG_W-1:0]           mark_rtx,\n             ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:30: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    output  [`FLOW_SEQ_NUM_W-1:0]   rtx_start,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:31: Define or directive not defined: \'`FLOW_SEQ_NUM_W\'\n    output  [`FLOW_SEQ_NUM_W-1:0]   rtx_end,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:32: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\n    output  [`FLOW_WIN_SIZE_W-1:0]  wnd_size_out,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:33: Define or directive not defined: \'`FLAG_W\'\n    output  [`FLAG_W-1:0]           reset_rtx_timer,\n             ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:34: Define or directive not defined: \'`TIMER_W\'\n    output  [`TIMER_W-1:0]          rtx_timer_amnt_out,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:35: Define or directive not defined: \'`USER_CONTEXT_W\'\n    output  [`USER_CONTEXT_W-1:0]   user_cntxt_out\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:42: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nreg     [`FLOW_WIN_SIZE_W-1:0]                      wnd_size_out_tmp;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:43: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nreg     [`FLOW_WIN_SIZE_W-1:0]                      wnd_inc_cntr_out_tmp;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:44: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire    [`FLOW_WIN_SIZE_W-1:0]                      half_ss_thresh;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:46: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_zero;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:47: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_one;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:48: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_two;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:52: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire    [`FLOW_WIN_SIZE_W-1:0]                      dup_acks_in;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:53: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire    [`FLOW_WIN_SIZE_W-1:0]                      ss_thresh_in;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:54: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_inc_cntr_in;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:55: Define or directive not defined: \'`FLAG_W\'\nwire    [`FLAG_W-1:0]                               in_timeout_in;\n         ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:57: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire    [`FLOW_WIN_SIZE_W-1:0]                      dup_acks_out;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:58: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire    [`FLOW_WIN_SIZE_W-1:0]                      ss_thresh_out;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:59: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nwire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_inc_cntr_out;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:60: Define or directive not defined: \'`FLAG_W\'\nwire    [`FLAG_W-1:0]                               in_timeout_out;\n         ^~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:71: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nassign  wnd_zero = {`FLOW_WIN_SIZE_W{1\'b0}};\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:72: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nassign  wnd_one = {{(`FLOW_WIN_SIZE_W-1){1\'b0}}, {1\'b1}};\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:73: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nassign  wnd_two = {{(`FLOW_WIN_SIZE_W-2){1\'b0}}, {2\'d2}};\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:81: Define or directive not defined: \'`DUP_ACKS_THRESH\'\nassign mark_rtx = ~in_timeout_in & dup_acks_out == `DUP_ACKS_THRESH;\n                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nassign mark_rtx = ~in_timeout_in & dup_acks_out == `DUP_ACKS_THRESH;\n                                                                   ^\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:85: Define or directive not defined: \'`MAX_FLOW_WIN_SIZE\'\nassign wnd_size_out         = wnd_size_out_tmp >= `MAX_FLOW_WIN_SIZE ? `MAX_FLOW_WIN_SIZE : wnd_size_out_tmp;\n                                                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:85: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\nassign wnd_size_out         = wnd_size_out_tmp >= `MAX_FLOW_WIN_SIZE ? `MAX_FLOW_WIN_SIZE : wnd_size_out_tmp;\n                                                                     ^\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:85: Define or directive not defined: \'`MAX_FLOW_WIN_SIZE\'\nassign wnd_size_out         = wnd_size_out_tmp >= `MAX_FLOW_WIN_SIZE ? `MAX_FLOW_WIN_SIZE : wnd_size_out_tmp;\n                                                                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/197252258/src/user_defined_logic/reno/user_defined_incoming.v:91: Define or directive not defined: \'`FLOW_WIN_SIZE_W\'\nassign half_ss_thresh = wnd_size_in > wnd_two ? {1\'b0, wnd_size_in[`FLOW_WIN_SIZE_W-1:1]} : wnd_two;\n                                                                   ^~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module user_defined_incoming (

    input   [`PKT_TYPE_W-1:0]       pkt_type_in,
    input   [`PKT_DATA_W-1:0]       pkt_data_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   cumulative_ack_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   selective_ack_in,
    input   [`TX_CNT_W-1:0]         sack_tx_id_in,

    input   [`TIME_W-1:0]           now,
    input   [`FLAG_W-1:0]           valid_selective_ack,
    input   [`FLOW_WIN_IND_W-1:0]   new_c_acks_cnt,
    input   [`FLOW_SEQ_NUM_W-1:0]   old_wnd_start_in,
    
    input   [`FLOW_WIN_SIZE-1:0]    acked_wnd_in,
    input   [`FLOW_WIN_SIZE-1:0]    rtx_wnd_in,
    input   [`TX_CNT_WIN_SIZE-1:0]  tx_cnt_wnd_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   wnd_start_in,
    input   [`FLOW_WIN_SIZE_W-1:0]  wnd_size_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   next_new_in,
    input   [`TIMER_W-1:0]          rtx_timer_amnt_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   total_tx_cnt_in,
    input   [`USER_CONTEXT_W-1:0]   user_cntxt_in,


    output  [`FLAG_W-1:0]           mark_rtx,
    output  [`FLOW_SEQ_NUM_W-1:0]   rtx_start,
    output  [`FLOW_SEQ_NUM_W-1:0]   rtx_end,
    output  [`FLOW_WIN_SIZE_W-1:0]  wnd_size_out,
    output  [`FLAG_W-1:0]           reset_rtx_timer,
    output  [`TIMER_W-1:0]          rtx_timer_amnt_out,
    output  [`USER_CONTEXT_W-1:0]   user_cntxt_out
);


wire                                                is_new_ack;
wire                                                is_dup_ack;

reg     [`FLOW_WIN_SIZE_W-1:0]                      wnd_size_out_tmp;
reg     [`FLOW_WIN_SIZE_W-1:0]                      wnd_inc_cntr_out_tmp;
wire    [`FLOW_WIN_SIZE_W-1:0]                      half_ss_thresh;

wire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_zero;
wire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_one;
wire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_two;



wire    [`FLOW_WIN_SIZE_W-1:0]                      dup_acks_in;
wire    [`FLOW_WIN_SIZE_W-1:0]                      ss_thresh_in;
wire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_inc_cntr_in;
wire    [`FLAG_W-1:0]                               in_timeout_in;

wire    [`FLOW_WIN_SIZE_W-1:0]                      dup_acks_out;
wire    [`FLOW_WIN_SIZE_W-1:0]                      ss_thresh_out;
wire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_inc_cntr_out;
wire    [`FLAG_W-1:0]                               in_timeout_out;




assign {in_timeout_in, wnd_inc_cntr_in, ss_thresh_in,
        dup_acks_in} = user_cntxt_in;

assign user_cntxt_out =  {in_timeout_out, wnd_inc_cntr_out, ss_thresh_out,
                          dup_acks_out};

assign  wnd_zero = {`FLOW_WIN_SIZE_W{1'b0}};
assign  wnd_one = {{(`FLOW_WIN_SIZE_W-1){1'b0}}, {1'b1}};
assign  wnd_two = {{(`FLOW_WIN_SIZE_W-2){1'b0}}, {2'd2}};

assign is_dup_ack = old_wnd_start_in == cumulative_ack_in;
assign is_new_ack = wnd_start_in > old_wnd_start_in;
assign dup_acks_out = is_new_ack ? wnd_zero:
                      is_dup_ack ? dup_acks_in + wnd_one : dup_acks_in;


assign mark_rtx = ~in_timeout_in & dup_acks_out == `DUP_ACKS_THRESH;
assign rtx_start = wnd_start_in;
assign rtx_end = wnd_start_in + 1;

assign wnd_size_out         = wnd_size_out_tmp >= `MAX_FLOW_WIN_SIZE ? `MAX_FLOW_WIN_SIZE : wnd_size_out_tmp;
assign wnd_inc_cntr_out     = wnd_inc_cntr_out_tmp;
assign rtx_timer_amnt_out   = rtx_timer_amnt_in;
assign reset_rtx_timer      = is_new_ack;
assign in_timeout_out       = (~is_new_ack) & in_timeout_in;

assign half_ss_thresh = wnd_size_in > wnd_two ? {1'b0, wnd_size_in[`FLOW_WIN_SIZE_W-1:1]} : wnd_two;
assign ss_thresh_out = ~in_timeout_in & dup_acks_out == `DUP_ACKS_THRESH ? half_ss_thresh : ss_thresh_in;


always @(*) begin
    if (is_new_ack) begin
        if (~in_timeout_in & dup_acks_in > 0 & dup_acks_in < `DUP_ACKS_THRESH) begin
            wnd_size_out_tmp = wnd_size_in - dup_acks_in;
        end
        else if(~in_timeout_in & dup_acks_in >= `DUP_ACKS_THRESH) begin
            wnd_size_out_tmp = ss_thresh_in;
        end
        else if(wnd_size_in < ss_thresh_in) begin
            wnd_size_out_tmp = wnd_size_in + wnd_one;
        end
        else begin
            wnd_size_out_tmp = wnd_inc_cntr_in == wnd_size_in ? wnd_size_in + wnd_one : wnd_size_in;
        end 
    end
    else if (~in_timeout_in & is_dup_ack & 
              dup_acks_out < `MAX_DUP_ACKS) begin
        wnd_size_out_tmp = wnd_size_in + wnd_one;
    end
    else begin
        wnd_size_out_tmp = wnd_size_in;
    end
end


always @(*) begin
    if (is_new_ack) begin
        wnd_inc_cntr_out_tmp = wnd_inc_cntr_in == wnd_size_in ? wnd_zero : wnd_inc_cntr_in + wnd_one;
    end
    else if (~in_timeout_in & is_dup_ack) begin
        wnd_inc_cntr_out_tmp = (dup_acks_out >= `DUP_ACKS_THRESH) ? wnd_zero : wnd_inc_cntr_in;
    end
    else begin
        wnd_inc_cntr_out_tmp = wnd_inc_cntr_in;
    end
end


`include "clogb2.vh"

endmodule
module user_defined_incoming (

    input   [`PKT_TYPE_W-1:0]       pkt_type_in,
    input   [`PKT_DATA_W-1:0]       pkt_data_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   cumulative_ack_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   selective_ack_in,
    input   [`TX_CNT_W-1:0]         sack_tx_id_in,

    input   [`TIME_W-1:0]           now,
    input   [`FLAG_W-1:0]           valid_selective_ack,
    input   [`FLOW_WIN_IND_W-1:0]   new_c_acks_cnt,
    input   [`FLOW_SEQ_NUM_W-1:0]   old_wnd_start_in,
    
    input   [`FLOW_WIN_SIZE-1:0]    acked_wnd_in,
    input   [`FLOW_WIN_SIZE-1:0]    rtx_wnd_in,
    input   [`TX_CNT_WIN_SIZE-1:0]  tx_cnt_wnd_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   wnd_start_in,
    input   [`FLOW_WIN_SIZE_W-1:0]  wnd_size_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   next_new_in,
    input   [`TIMER_W-1:0]          rtx_timer_amnt_in,
    input   [`FLOW_SEQ_NUM_W-1:0]   total_tx_cnt_in,
    input   [`USER_CONTEXT_W-1:0]   user_cntxt_in,


    output  [`FLAG_W-1:0]           mark_rtx,
    output  [`FLOW_SEQ_NUM_W-1:0]   rtx_start,
    output  [`FLOW_SEQ_NUM_W-1:0]   rtx_end,
    output  [`FLOW_WIN_SIZE_W-1:0]  wnd_size_out,
    output  [`FLAG_W-1:0]           reset_rtx_timer,
    output  [`TIMER_W-1:0]          rtx_timer_amnt_out,
    output  [`USER_CONTEXT_W-1:0]   user_cntxt_out
);



wire                                                is_new_ack;
wire                                                is_dup_ack;

reg     [`FLOW_WIN_SIZE_W-1:0]                      wnd_size_out_tmp;
reg     [`FLOW_WIN_SIZE_W-1:0]                      wnd_inc_cntr_out_tmp;
wire    [`FLOW_WIN_SIZE_W-1:0]                      half_ss_thresh;

wire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_zero;
wire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_one;
wire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_two;



wire    [`FLOW_WIN_SIZE_W-1:0]                      dup_acks_in;
wire    [`FLOW_WIN_SIZE_W-1:0]                      ss_thresh_in;
wire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_inc_cntr_in;
wire    [`FLAG_W-1:0]                               in_timeout_in;

wire    [`FLOW_WIN_SIZE_W-1:0]                      dup_acks_out;
wire    [`FLOW_WIN_SIZE_W-1:0]                      ss_thresh_out;
wire    [`FLOW_WIN_SIZE_W-1:0]                      wnd_inc_cntr_out;
wire    [`FLAG_W-1:0]                               in_timeout_out;




assign {in_timeout_in, wnd_inc_cntr_in, ss_thresh_in,
        dup_acks_in} = user_cntxt_in;

assign user_cntxt_out =  {in_timeout_out, wnd_inc_cntr_out, ss_thresh_out,
                          dup_acks_out};

assign  wnd_zero = {`FLOW_WIN_SIZE_W{1'b0}};
assign  wnd_one = {{(`FLOW_WIN_SIZE_W-1){1'b0}}, {1'b1}};
assign  wnd_two = {{(`FLOW_WIN_SIZE_W-2){1'b0}}, {2'd2}};

assign is_dup_ack = old_wnd_start_in == cumulative_ack_in;
assign is_new_ack = wnd_start_in > old_wnd_start_in;
assign dup_acks_out = is_new_ack ? wnd_zero:
                      is_dup_ack ? dup_acks_in + wnd_one : dup_acks_in;


assign mark_rtx = ~in_timeout_in & dup_acks_out == `DUP_ACKS_THRESH;
assign rtx_start = wnd_start_in;
assign rtx_end = wnd_start_in + 1;

assign wnd_size_out         = wnd_size_out_tmp >= `MAX_FLOW_WIN_SIZE ? `MAX_FLOW_WIN_SIZE : wnd_size_out_tmp;
assign wnd_inc_cntr_out     = wnd_inc_cntr_out_tmp;
assign rtx_timer_amnt_out   = rtx_timer_amnt_in;
assign reset_rtx_timer      = is_new_ack;
assign in_timeout_out       = (~is_new_ack) & in_timeout_in;

assign half_ss_thresh = wnd_size_in > wnd_two ? {1'b0, wnd_size_in[`FLOW_WIN_SIZE_W-1:1]} : wnd_two;
assign ss_thresh_out = ~in_timeout_in & dup_acks_out == `DUP_ACKS_THRESH ? half_ss_thresh : ss_thresh_in;


always @(*) begin
    if (is_new_ack) begin
        if (~in_timeout_in & dup_acks_in > 0 & dup_acks_in < `DUP_ACKS_THRESH) begin
            wnd_size_out_tmp = wnd_size_in - dup_acks_in;
        end
        else if(~in_timeout_in & dup_acks_in >= `DUP_ACKS_THRESH) begin
            wnd_size_out_tmp = ss_thresh_in;
        end
        else if(wnd_size_in < ss_thresh_in) begin
            wnd_size_out_tmp = wnd_size_in + wnd_one;
        end
        else begin
            wnd_size_out_tmp = wnd_inc_cntr_in == wnd_size_in ? wnd_size_in + wnd_one : wnd_size_in;
        end 
    end
    else if (~in_timeout_in & is_dup_ack & 
              dup_acks_out < `MAX_DUP_ACKS) begin
        wnd_size_out_tmp = wnd_size_in + wnd_one;
    end
    else begin
        wnd_size_out_tmp = wnd_size_in;
    end
end


always @(*) begin
    if (is_new_ack) begin
        wnd_inc_cntr_out_tmp = wnd_inc_cntr_in == wnd_size_in ? wnd_zero : wnd_inc_cntr_in + wnd_one;
    end
    else if (~in_timeout_in & is_dup_ack) begin
        wnd_inc_cntr_out_tmp = (dup_acks_out >= `DUP_ACKS_THRESH) ? wnd_zero : wnd_inc_cntr_in;
    end
    else begin
        wnd_inc_cntr_out_tmp = wnd_inc_cntr_in;
    end
end


`include "clogb2.vh"

endmodule