data/full_repos/permissive/17099167/system/hardware/cores/arbiter/arbiter_ibus.v
None: at end of input
1: b'%Error: data/full_repos/permissive/17099167/system/hardware/cores/arbiter/arbiter_ibus.v:37: Cannot find include file: orpsoc-defines.v\n`include "orpsoc-defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/17099167/system/hardware/cores/arbiter,data/full_repos/permissive/17099167/orpsoc-defines.v\n             data/full_repos/permissive/17099167/system/hardware/cores/arbiter,data/full_repos/permissive/17099167/orpsoc-defines.v.v\n             data/full_repos/permissive/17099167/system/hardware/cores/arbiter,data/full_repos/permissive/17099167/orpsoc-defines.v.sv\n             orpsoc-defines.v\n             orpsoc-defines.v.v\n             orpsoc-defines.v.sv\n             obj_dir/orpsoc-defines.v\n             obj_dir/orpsoc-defines.v.v\n             obj_dir/orpsoc-defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module arbiter_ibus
  (


   wbm_adr_o,
   wbm_dat_o,
   wbm_sel_o,
   wbm_we_o,
   wbm_cyc_o,
   wbm_stb_o,
   wbm_cti_o,
   wbm_bte_o,
  
   wbm_dat_i,
   wbm_ack_i,
   wbm_err_i,
   wbm_rty_i,




   wbs0_adr_i,
   wbs0_dat_i,
   wbs0_sel_i,
   wbs0_we_i,
   wbs0_cyc_i,
   wbs0_stb_i,
   wbs0_cti_i,
   wbs0_bte_i,
  
   wbs0_dat_o,
   wbs0_ack_o,
   wbs0_err_o,
   wbs0_rty_o,



   wbs1_adr_i,
   wbs1_dat_i,
   wbs1_sel_i,
   wbs1_we_i,
   wbs1_cyc_i,
   wbs1_stb_i,
   wbs1_cti_i,
   wbs1_bte_i,
  
   wbs1_dat_o,
   wbs1_ack_o,
   wbs1_err_o,
   wbs1_rty_o,

   wb_clk,
   wb_rst
   );


   parameter wb_dat_width = 32;
   parameter wb_adr_width = 32;

   parameter wb_addr_match_width = 8;

   parameter slave0_adr = 8'hf0;
   parameter slave1_adr = 8'h00;

`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
   
   input wb_clk;
   input wb_rst;

   

   input [wb_adr_width-1:0] wbm_adr_o;
   input [wb_dat_width-1:0] wbm_dat_o;
   input [3:0] 		    wbm_sel_o;   
   input 		    wbm_we_o;
   input 		    wbm_cyc_o;
   input 		    wbm_stb_o;
   input [2:0] 		    wbm_cti_o;
   input [1:0] 		    wbm_bte_o;
   output [wb_dat_width-1:0] wbm_dat_i;   
   output 		     wbm_ack_i;
   output 		     wbm_err_i;
   output 		     wbm_rty_i;   


   output [wb_adr_width-1:0] wbs0_adr_i;
   output [wb_dat_width-1:0] wbs0_dat_i;
   output [3:0] 	     wbs0_sel_i;
   output 		     wbs0_we_i;
   output 		     wbs0_cyc_i;
   output 		     wbs0_stb_i;
   output [2:0] 	     wbs0_cti_i;
   output [1:0] 	     wbs0_bte_i;
   input [wb_dat_width-1:0]  wbs0_dat_o;   
   input 		     wbs0_ack_o;
   input 		     wbs0_err_o;
   input 		     wbs0_rty_o;   


   output [wb_adr_width-1:0] wbs1_adr_i;
   output [wb_dat_width-1:0] wbs1_dat_i;
   output [3:0] 	     wbs1_sel_i;
   output 		     wbs1_we_i;
   output 		     wbs1_cyc_i;
   output 		     wbs1_stb_i;
   output [2:0] 	     wbs1_cti_i;
   output [1:0] 	     wbs1_bte_i;
   input [wb_dat_width-1:0]  wbs1_dat_o;   
   input 		     wbs1_ack_o;
   input 		     wbs1_err_o;
   input 		     wbs1_rty_o;   

   wire [1:0] 		     slave_sel;

   reg 			     watchdog_err;
   
`ifdef ARBITER_IBUS_WATCHDOG
   reg [`ARBITER_IBUS_WATCHDOG_TIMER_WIDTH:0]  watchdog_timer;
   reg 			     wbm_stb_r;
   wire 		     wbm_stb_edge;
   reg 			     wbm_stb_edge_r, wbm_ack_i_r;

   always @(posedge wb_clk)
     wbm_stb_r <= wbm_stb_o;

   assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);

   always @(posedge wb_clk)
     wbm_stb_edge_r <= wbm_stb_edge;
   
   always @(posedge wb_clk)
     wbm_ack_i_r <= wbm_ack_i;
   
   

   always @(posedge wb_clk)
     if (wb_rst) watchdog_timer <= 0;
     else if (wbm_ack_i_r)
       watchdog_timer <= 0;
     else if (wbm_stb_edge_r)
       watchdog_timer <= 1;
     else if (|watchdog_timer)
       watchdog_timer <= watchdog_timer + 1;

   always @(posedge wb_clk) 
     watchdog_err <= (&watchdog_timer);
   
`else
   
   always @(posedge wb_clk) 
     watchdog_err <= 0;

`endif
   
   

`ifdef ARBITER_IBUS_REGISTERING
   

   reg [wb_adr_width-1:0]    wbm_adr_o_r;
   reg [wb_dat_width-1:0]    wbm_dat_o_r;
   reg [3:0] 		     wbm_sel_o_r;   
   reg 			     wbm_we_o_r;
   reg 			     wbm_cyc_o_r;
   reg 			     wbm_stb_o_r;
   reg [2:0] 		     wbm_cti_o_r;
   reg [1:0] 		     wbm_bte_o_r;

   reg [wb_dat_width-1:0]    wbs0_dat_o_r;   
   reg 			     wbs0_ack_o_r;
   reg 			     wbs0_err_o_r;
   reg 			     wbs0_rty_o_r;
   reg [wb_dat_width-1:0]    wbs1_dat_o_r;   
   reg 			     wbs1_ack_o_r;
   reg 			     wbs1_err_o_r;
   reg 			     wbs1_rty_o_r;

   wire 		     wbm_ack_i_pre_reg;

   
   

   always @(posedge wb_clk)
     begin
	wbm_adr_o_r <= wbm_adr_o;
	wbm_dat_o_r <= wbm_dat_o;
	wbm_sel_o_r <= wbm_sel_o;
	wbm_we_o_r <= wbm_we_o;
	wbm_cyc_o_r <= wbm_cyc_o;
	wbm_stb_o_r <= wbm_stb_o & !wbm_ack_i_pre_reg & !wbm_ack_i;
	wbm_cti_o_r <= wbm_cti_o;
	wbm_bte_o_r <= wbm_bte_o;


	wbs0_dat_o_r <= wbs0_dat_o;
	wbs0_ack_o_r <= wbs0_ack_o;
	wbs0_err_o_r <= wbs0_err_o;
	wbs0_rty_o_r <= wbs0_rty_o;
	wbs1_dat_o_r <= wbs1_dat_o;
	wbs1_ack_o_r <= wbs1_ack_o;
	wbs1_err_o_r <= wbs1_err_o;
	wbs1_rty_o_r <= wbs1_rty_o;   
	
     end


   assign slave_sel[0] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
			 slave0_adr;

   assign slave_sel[1] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
			 slave1_adr;


   assign wbs0_adr_i = wbm_adr_o_r;
   assign wbs0_dat_i = wbm_dat_o_r;
   assign wbs0_we_i = wbm_dat_o_r;
   assign wbs0_sel_i = wbm_sel_o_r;
   assign wbs0_cti_i = wbm_cti_o_r;
   assign wbs0_bte_i = wbm_bte_o_r;
   assign wbs0_cyc_i = wbm_cyc_o_r & slave_sel[0];
   assign wbs0_stb_i = wbm_stb_o_r & slave_sel[0];

   assign wbs1_adr_i = wbm_adr_o_r;
   assign wbs1_dat_i = wbm_dat_o_r;
   assign wbs1_we_i = wbm_dat_o_r;
   assign wbs1_sel_i = wbm_sel_o_r;
   assign wbs1_cti_i = wbm_cti_o_r;
   assign wbs1_bte_i = wbm_bte_o_r;
   assign wbs1_cyc_i = wbm_cyc_o_r & slave_sel[1];
   assign wbs1_stb_i = wbm_stb_o_r & slave_sel[1];



   assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o_r :
		      wbs0_dat_o_r ;
   
   assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o_r) |
		      (slave_sel[1] & wbs1_ack_o_r)
     ;
   
   assign wbm_err_i = (slave_sel[0] & wbs0_err_o_r) |
		      (slave_sel[1] & wbs1_err_o_r) |
		      watchdog_err;
   
   assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o_r) |
		      (slave_sel[1] & wbs1_rty_o_r);


   assign wbm_ack_i_pre_reg = (slave_sel[0] & wbs0_ack_o) |
			      (slave_sel[1] & wbs1_ack_o);
   
`else


   assign slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
			 slave0_adr;

   assign slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
			 slave1_adr;


   assign wbs0_adr_i = wbm_adr_o;
   assign wbs0_dat_i = wbm_dat_o;
   assign wbs0_we_i  = wbm_we_o;
   assign wbs0_sel_i = wbm_sel_o;
   assign wbs0_cti_i = wbm_cti_o;
   assign wbs0_bte_i = wbm_bte_o;
   assign wbs0_cyc_i = wbm_cyc_o & slave_sel[0];
   assign wbs0_stb_i = wbm_stb_o & slave_sel[0];

   assign wbs1_adr_i = wbm_adr_o;
   assign wbs1_dat_i = wbm_dat_o;
   assign wbs1_we_i  = wbm_we_o;
   assign wbs1_sel_i = wbm_sel_o;
   assign wbs1_cti_i = wbm_cti_o;
   assign wbs1_bte_i = wbm_bte_o;
   assign wbs1_cyc_i = wbm_cyc_o & slave_sel[1];
   assign wbs1_stb_i = wbm_stb_o & slave_sel[1];



   assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o :
		      wbs0_dat_o ;
   
   assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o) |
		      (slave_sel[1] & wbs1_ack_o);
   
   
   assign wbm_err_i = (slave_sel[0] & wbs0_err_o) |
		      (slave_sel[1] & wbs1_err_o) |
		      watchdog_err;
   
   assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o) |
		      (slave_sel[1] & wbs1_rty_o);
   

`endif
endmodule
module arbiter_ibus
  (


   wbm_adr_o,
   wbm_dat_o,
   wbm_sel_o,
   wbm_we_o,
   wbm_cyc_o,
   wbm_stb_o,
   wbm_cti_o,
   wbm_bte_o,
  
   wbm_dat_i,
   wbm_ack_i,
   wbm_err_i,
   wbm_rty_i,




   wbs0_adr_i,
   wbs0_dat_i,
   wbs0_sel_i,
   wbs0_we_i,
   wbs0_cyc_i,
   wbs0_stb_i,
   wbs0_cti_i,
   wbs0_bte_i,
  
   wbs0_dat_o,
   wbs0_ack_o,
   wbs0_err_o,
   wbs0_rty_o,



   wbs1_adr_i,
   wbs1_dat_i,
   wbs1_sel_i,
   wbs1_we_i,
   wbs1_cyc_i,
   wbs1_stb_i,
   wbs1_cti_i,
   wbs1_bte_i,
  
   wbs1_dat_o,
   wbs1_ack_o,
   wbs1_err_o,
   wbs1_rty_o,

   wb_clk,
   wb_rst
   );



   parameter wb_dat_width = 32;
   parameter wb_adr_width = 32;

   parameter wb_addr_match_width = 8;

   parameter slave0_adr = 8'hf0;
   parameter slave1_adr = 8'h00;

`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
   
   input wb_clk;
   input wb_rst;

   

   input [wb_adr_width-1:0] wbm_adr_o;
   input [wb_dat_width-1:0] wbm_dat_o;
   input [3:0] 		    wbm_sel_o;   
   input 		    wbm_we_o;
   input 		    wbm_cyc_o;
   input 		    wbm_stb_o;
   input [2:0] 		    wbm_cti_o;
   input [1:0] 		    wbm_bte_o;
   output [wb_dat_width-1:0] wbm_dat_i;   
   output 		     wbm_ack_i;
   output 		     wbm_err_i;
   output 		     wbm_rty_i;   


   output [wb_adr_width-1:0] wbs0_adr_i;
   output [wb_dat_width-1:0] wbs0_dat_i;
   output [3:0] 	     wbs0_sel_i;
   output 		     wbs0_we_i;
   output 		     wbs0_cyc_i;
   output 		     wbs0_stb_i;
   output [2:0] 	     wbs0_cti_i;
   output [1:0] 	     wbs0_bte_i;
   input [wb_dat_width-1:0]  wbs0_dat_o;   
   input 		     wbs0_ack_o;
   input 		     wbs0_err_o;
   input 		     wbs0_rty_o;   


   output [wb_adr_width-1:0] wbs1_adr_i;
   output [wb_dat_width-1:0] wbs1_dat_i;
   output [3:0] 	     wbs1_sel_i;
   output 		     wbs1_we_i;
   output 		     wbs1_cyc_i;
   output 		     wbs1_stb_i;
   output [2:0] 	     wbs1_cti_i;
   output [1:0] 	     wbs1_bte_i;
   input [wb_dat_width-1:0]  wbs1_dat_o;   
   input 		     wbs1_ack_o;
   input 		     wbs1_err_o;
   input 		     wbs1_rty_o;   

   wire [1:0] 		     slave_sel;

   reg 			     watchdog_err;
   
`ifdef ARBITER_IBUS_WATCHDOG
   reg [`ARBITER_IBUS_WATCHDOG_TIMER_WIDTH:0]  watchdog_timer;
   reg 			     wbm_stb_r;
   wire 		     wbm_stb_edge;
   reg 			     wbm_stb_edge_r, wbm_ack_i_r;

   always @(posedge wb_clk)
     wbm_stb_r <= wbm_stb_o;

   assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);

   always @(posedge wb_clk)
     wbm_stb_edge_r <= wbm_stb_edge;
   
   always @(posedge wb_clk)
     wbm_ack_i_r <= wbm_ack_i;
   
   

   always @(posedge wb_clk)
     if (wb_rst) watchdog_timer <= 0;
     else if (wbm_ack_i_r)
       watchdog_timer <= 0;
     else if (wbm_stb_edge_r)
       watchdog_timer <= 1;
     else if (|watchdog_timer)
       watchdog_timer <= watchdog_timer + 1;

   always @(posedge wb_clk) 
     watchdog_err <= (&watchdog_timer);
   
`else
   
   always @(posedge wb_clk) 
     watchdog_err <= 0;

`endif
   
   

`ifdef ARBITER_IBUS_REGISTERING
   

   reg [wb_adr_width-1:0]    wbm_adr_o_r;
   reg [wb_dat_width-1:0]    wbm_dat_o_r;
   reg [3:0] 		     wbm_sel_o_r;   
   reg 			     wbm_we_o_r;
   reg 			     wbm_cyc_o_r;
   reg 			     wbm_stb_o_r;
   reg [2:0] 		     wbm_cti_o_r;
   reg [1:0] 		     wbm_bte_o_r;

   reg [wb_dat_width-1:0]    wbs0_dat_o_r;   
   reg 			     wbs0_ack_o_r;
   reg 			     wbs0_err_o_r;
   reg 			     wbs0_rty_o_r;
   reg [wb_dat_width-1:0]    wbs1_dat_o_r;   
   reg 			     wbs1_ack_o_r;
   reg 			     wbs1_err_o_r;
   reg 			     wbs1_rty_o_r;

   wire 		     wbm_ack_i_pre_reg;

   
   

   always @(posedge wb_clk)
     begin
	wbm_adr_o_r <= wbm_adr_o;
	wbm_dat_o_r <= wbm_dat_o;
	wbm_sel_o_r <= wbm_sel_o;
	wbm_we_o_r <= wbm_we_o;
	wbm_cyc_o_r <= wbm_cyc_o;
	wbm_stb_o_r <= wbm_stb_o & !wbm_ack_i_pre_reg & !wbm_ack_i;
	wbm_cti_o_r <= wbm_cti_o;
	wbm_bte_o_r <= wbm_bte_o;


	wbs0_dat_o_r <= wbs0_dat_o;
	wbs0_ack_o_r <= wbs0_ack_o;
	wbs0_err_o_r <= wbs0_err_o;
	wbs0_rty_o_r <= wbs0_rty_o;
	wbs1_dat_o_r <= wbs1_dat_o;
	wbs1_ack_o_r <= wbs1_ack_o;
	wbs1_err_o_r <= wbs1_err_o;
	wbs1_rty_o_r <= wbs1_rty_o;   
	
     end


   assign slave_sel[0] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
			 slave0_adr;

   assign slave_sel[1] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] ==
			 slave1_adr;


   assign wbs0_adr_i = wbm_adr_o_r;
   assign wbs0_dat_i = wbm_dat_o_r;
   assign wbs0_we_i = wbm_dat_o_r;
   assign wbs0_sel_i = wbm_sel_o_r;
   assign wbs0_cti_i = wbm_cti_o_r;
   assign wbs0_bte_i = wbm_bte_o_r;
   assign wbs0_cyc_i = wbm_cyc_o_r & slave_sel[0];
   assign wbs0_stb_i = wbm_stb_o_r & slave_sel[0];

   assign wbs1_adr_i = wbm_adr_o_r;
   assign wbs1_dat_i = wbm_dat_o_r;
   assign wbs1_we_i = wbm_dat_o_r;
   assign wbs1_sel_i = wbm_sel_o_r;
   assign wbs1_cti_i = wbm_cti_o_r;
   assign wbs1_bte_i = wbm_bte_o_r;
   assign wbs1_cyc_i = wbm_cyc_o_r & slave_sel[1];
   assign wbs1_stb_i = wbm_stb_o_r & slave_sel[1];



   assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o_r :
		      wbs0_dat_o_r ;
   
   assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o_r) |
		      (slave_sel[1] & wbs1_ack_o_r)
     ;
   
   assign wbm_err_i = (slave_sel[0] & wbs0_err_o_r) |
		      (slave_sel[1] & wbs1_err_o_r) |
		      watchdog_err;
   
   assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o_r) |
		      (slave_sel[1] & wbs1_rty_o_r);


   assign wbm_ack_i_pre_reg = (slave_sel[0] & wbs0_ack_o) |
			      (slave_sel[1] & wbs1_ack_o);
   
`else


   assign slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
			 slave0_adr;

   assign slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] ==
			 slave1_adr;


   assign wbs0_adr_i = wbm_adr_o;
   assign wbs0_dat_i = wbm_dat_o;
   assign wbs0_we_i  = wbm_we_o;
   assign wbs0_sel_i = wbm_sel_o;
   assign wbs0_cti_i = wbm_cti_o;
   assign wbs0_bte_i = wbm_bte_o;
   assign wbs0_cyc_i = wbm_cyc_o & slave_sel[0];
   assign wbs0_stb_i = wbm_stb_o & slave_sel[0];

   assign wbs1_adr_i = wbm_adr_o;
   assign wbs1_dat_i = wbm_dat_o;
   assign wbs1_we_i  = wbm_we_o;
   assign wbs1_sel_i = wbm_sel_o;
   assign wbs1_cti_i = wbm_cti_o;
   assign wbs1_bte_i = wbm_bte_o;
   assign wbs1_cyc_i = wbm_cyc_o & slave_sel[1];
   assign wbs1_stb_i = wbm_stb_o & slave_sel[1];



   assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o :
		      wbs0_dat_o ;
   
   assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o) |
		      (slave_sel[1] & wbs1_ack_o);
   
   
   assign wbm_err_i = (slave_sel[0] & wbs0_err_o) |
		      (slave_sel[1] & wbs1_err_o) |
		      watchdog_err;
   
   assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o) |
		      (slave_sel[1] & wbs1_rty_o);
   

`endif
endmodule