data/full_repos/permissive/185451826/2.cyclic_shift/cyclic_shift_tp.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/185451826/2.cyclic_shift/cyclic_shift_tp.v:13: Unsupported: Ignoring delay on this delayed statement.\n #1000.1 rst_n=1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/185451826/2.cyclic_shift/cyclic_shift_tp.v:14: Unsupported: Ignoring delay on this delayed statement.\n #10000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/185451826/2.cyclic_shift/cyclic_shift_tp.v:17: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk=~clk;\n          ^\n%Error: data/full_repos/permissive/185451826/2.cyclic_shift/cyclic_shift_tp.v:25: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("shift_tp.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/185451826/2.cyclic_shift/cyclic_shift_tp.v:26: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, shift);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
   reg clk;
   reg rst_n;

   wire [3:0] led_out;

   initial
     begin
	clk=0;
	rst_n=0;
	#1000.1 rst_n=1;
	#10000;
	$finish;
     end
   always #10 clk=~clk;
   cyclic_shift shift(
		.clk(clk),
		.rst_n(rst_n),
		.led_out(led_out)
		);
   initial
     begin
	$dumpfile("shift_tp.vcd");
	$dumpvars(0, shift);
     end
endmodule
module tb;

   reg clk;
   reg rst_n;

   wire [3:0] led_out;

   initial
     begin
	clk=0;
	rst_n=0;
	#1000.1 rst_n=1;
	#10000;
	$finish;
     end
   always #10 clk=~clk;
   cyclic_shift shift(
		.clk(clk),
		.rst_n(rst_n),
		.led_out(led_out)
		);
   initial
     begin
	$dumpfile("shift_tp.vcd");
	$dumpvars(0, shift);
     end
endmodule