data/full_repos/permissive/152883307/Project/SignTest.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152883307/Project/SignTest.v:12: Operator NEGATE expects 9 bits on the LHS, but LHS\'s VARREF \'B\' generates 3 bits.\n                                                                          : ... In instance Sign\n  Y3 <= A*-B;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Sign (
	A, 
	B, 
	Y3
);
 
input		signed		[2:0] 	A, B;
output	reg signed	[8:0]		Y3;

 
always @(A or B) begin
		Y3 <= A*-B;
	end

endmodule
module Sign (
	A, 
	B, 
	Y3
);

 
input		signed		[2:0] 	A, B;
output	reg signed	[8:0]		Y3;

 
always @(A or B) begin
		Y3 <= A*-B;
	end

endmodule