data/full_repos/permissive/128781882/FPGA_implementation/IPUF/src/veriolg/apuf/dflop.v
data/verilator_xmls/a52f5f40-5ea7-4764-8d66-4c9232119628.xml
module dflop(clk,din,dout);
	
	input clk;
	input din;
	output reg dout;
    
	always @(posedge clk) begin
		dout <= din;	
	end
	
endmodule
module dflop(clk,din,dout);

	
	input clk;
	input din;
	output reg dout;
    
	always @(posedge clk) begin
		dout <= din;	
	end
	
endmodule