data/full_repos/permissive/135475029/lab_4/src/FSM.v
1: b"%Error: data/full_repos/permissive/135475029/lab_4/src/FSM.v:36: Cannot find file containing module: 'clk_div'\n    clk_div dc (clk, reset, clk_en);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/135475029/lab_4/src,data/full_repos/permissive/135475029/clk_div\n             data/full_repos/permissive/135475029/lab_4/src,data/full_repos/permissive/135475029/clk_div.v\n             data/full_repos/permissive/135475029/lab_4/src,data/full_repos/permissive/135475029/clk_div.sv\n             clk_div\n             clk_div.v\n             clk_div.sv\n             obj_dir/clk_div\n             obj_dir/clk_div.v\n             obj_dir/clk_div.sv\n%Error: Exiting due to 1 error(s)\n"
module FSM(
    input clk,
    input left,
    input right,
    input reset,
    output reg [2:0] L,
    output reg [2:0] R
    );
    
    reg [2:0] state;
    reg [2:0] nextstate;
    
    wire clk_en;
    clk_div dc (clk, reset, clk_en);
    
    parameter S0 = 3'b000;
    parameter L1 = 3'b001;
    parameter L2 = 3'b011;
    parameter L3 = 3'b111;
    parameter R1 = 3'b100;
    parameter R2 = 3'b110;
    parameter R3 = 3'b010;
    
    always@(posedge clk_en, posedge reset)
        if(reset)
            state <= S0;
        else
            state <= nextstate;
            

    always@(*)
        case(state)
            S0:
                begin
                    if(left)
                        nextstate = L1;
                    else if(right)
                        nextstate = R1;
                    else
                        nextstate = S0;
                end
            L1: nextstate = L2;
            L2: nextstate = L3;
            L3: nextstate = S0;
            R1: nextstate = R2;
            R2: nextstate = R3;
            R3: nextstate = S0;
            default: nextstate = S0;
            
        endcase
        

    always@(posedge clk_en)
        case(state)
            S0:
                begin
                    L <= 3'b000;
                    R <= 3'b000;
                end
            L1: L <= 3'b001;
            L2: L <= 3'b011;
            L3: L <= 3'b111;
            R1: R <= 3'b100;
            R2: R <= 3'b110;
            R3: R <= 3'b111;
            
            default:
                begin
                    L <= 3'b000;
                    R <= 3'b000;
                end
        endcase
    
endmodule
module FSM(
    input clk,
    input left,
    input right,
    input reset,
    output reg [2:0] L,
    output reg [2:0] R
    );

    
    reg [2:0] state;
    reg [2:0] nextstate;
    
    wire clk_en;
    clk_div dc (clk, reset, clk_en);
    
    parameter S0 = 3'b000;
    parameter L1 = 3'b001;
    parameter L2 = 3'b011;
    parameter L3 = 3'b111;
    parameter R1 = 3'b100;
    parameter R2 = 3'b110;
    parameter R3 = 3'b010;
    
    always@(posedge clk_en, posedge reset)
        if(reset)
            state <= S0;
        else
            state <= nextstate;
            

    always@(*)
        case(state)
            S0:
                begin
                    if(left)
                        nextstate = L1;
                    else if(right)
                        nextstate = R1;
                    else
                        nextstate = S0;
                end
            L1: nextstate = L2;
            L2: nextstate = L3;
            L3: nextstate = S0;
            R1: nextstate = R2;
            R2: nextstate = R3;
            R3: nextstate = S0;
            default: nextstate = S0;
            
        endcase
        

    always@(posedge clk_en)
        case(state)
            S0:
                begin
                    L <= 3'b000;
                    R <= 3'b000;
                end
            L1: L <= 3'b001;
            L2: L <= 3'b011;
            L3: L <= 3'b111;
            R1: R <= 3'b100;
            R2: R <= 3'b110;
            R3: R <= 3'b111;
            
            default:
                begin
                    L <= 3'b000;
                    R <= 3'b000;
                end
        endcase
    
endmodule