data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v
 line:34: before: "resetb_tb"
1: b'%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:34: syntax error, unexpected \'@\'\n  @(posedge clk_tb)     resetb_tb = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n     #0;  \n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:54: syntax error, unexpected \'@\'\n     @(posedge clk_tb);\n     ^\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:76: syntax error, unexpected \'@\'\n  @(posedge clk_tb)     resetb_tb = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n     #0;  \n     ^\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:96: syntax error, unexpected \'@\'\n     @(posedge clk_tb);\n     ^\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:112: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_log/regfile_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:113: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,regfile_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:115: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: Exiting due to 7 error(s), 2 warning(s)\n'
module regfile_tb(clk);
   reg clk_tb, resetb_tb, we_rd_tb;
   reg [4:0] a_rs1_tb, a_rs2_tb, a_rd_tb;
   wire [31:0] d_rs1_tb, d_rs2_tb;
   reg [31:0] d_rd_tb;

   assign clk_tb = clk;
   







   task run_test1;
      integer 	    i;
      begin
	 $display("(TT) --------------------------------------------------");
	 $display("(TT) Test 1: Basic R/W ");
	 $display("(TT) 1. Writes 32, 31, ... to x0, x1, ... consecutively");
	 $display("(TT) 2. RS1 reads x31, x0, x1, ...");
	 $display("(TT) 3. RS2 reads x30, x31, x0, x1, ...");
	 $display("(TT) 4. RS1 should read X, 0, 31, 30, ...");
	 $display("(TT) 5. RS2 should read X, X, 0, 31, 30, ...");
	 $display("(TT) 6. No stray value should remain");
	 $display("(TT) --------------------------------------------------");
	 
	 resetb_tb = 1'b0;
	 we_rd_tb = 1'b0;
	 @(posedge clk_tb)	    resetb_tb = 1'b1;
	 for (i = 0; i < 40; i = i + 1) begin

	    a_rd_tb = i;

	    d_rd_tb = 32 - i%32;
	    we_rd_tb = 1'b1;

	    a_rs1_tb = i - 1;

	    a_rs2_tb = i - 2;
	    #0;

	    $display("(TT) a_rd = x%d, d_rd = %d, we_rd = %d",
		     a_rd_tb, d_rd_tb, we_rd_tb);
	    $display("(TT) a_rs1 = x%d, d_rs1 = %d",
		     a_rs1_tb, d_rs1_tb);
	    $display("(TT) a_rs2 = x%d, d_rs2 = %d",
		     a_rs2_tb, d_rs2_tb);
	    $display("");
	    @(posedge clk_tb);
	 end
      end
   endtask



   task run_test2;
      integer 	    i;
      begin
	 $display("(TT) --------------------------------------------------");
	 $display("(TT) Test 2: Forwarding R/W ");
	 $display("(TT) 1. Writes 32, 31, ... to x0, x1, ... consecutively");
	 $display("(TT) 2. RS1 reads x0, x1, ...");
	 $display("(TT) 3. RS2 reads x31, x0, x1, ...");
	 $display("(TT) 4. RS1 should read 0, 31, 30, ...");
	 $display("(TT) 5. RS2 should read X, 0, 31, 30, ...");
	 $display("(TT) 6. No stray value should remain");
	 $display("(TT) --------------------------------------------------");
	 
	 resetb_tb = 1'b0;
	 we_rd_tb = 1'b0;
	 @(posedge clk_tb)	    resetb_tb = 1'b1;
	 for (i = 0; i < 40; i = i + 1) begin

	    a_rd_tb = i;

	    d_rd_tb = 32 - i%32;
	    we_rd_tb = 1'b1;

	    a_rs1_tb = i;

	    a_rs2_tb = i - 1;
	    #0;

	    $display("(TT) a_rd = x%d, d_rd = %d, we_rd = %d",
		     a_rd_tb, d_rd_tb, we_rd_tb);
	    $display("(TT) a_rs1 = x%d, d_rs1 = %d",
		     a_rs1_tb, d_rs1_tb);
	    $display("(TT) a_rs2 = x%d, d_rs2 = %d",
		     a_rs2_tb, d_rs2_tb);
	    $display("");
	    @(posedge clk_tb);
	 end
      end
   endtask
   
   regfile UUT(
	       .clk(clk_tb), .resetb(resetb_tb),
	       .a_rs1(a_rs1_tb), .d_rs1(d_rs1_tb),
	       .a_rs2(a_rs2_tb), .d_rs2(d_rs2_tb),
	       .a_rd(a_rd_tb), .d_rd(d_rd_tb),
	       .we_rd(we_rd_tb)
	       );


   initial
     begin : RUN_ALL_TESTS
	$dumpfile("tb_log/regfile_tb.vcd");
	$dumpvars(0,regfile_tb);

	@(posedge clk_tb);

	run_test1();

	run_test2();

	$finish;
	
     end


endmodule
module regfile_tb(clk);

   reg clk_tb, resetb_tb, we_rd_tb;
   reg [4:0] a_rs1_tb, a_rs2_tb, a_rd_tb;
   wire [31:0] d_rs1_tb, d_rs2_tb;
   reg [31:0] d_rd_tb;

   assign clk_tb = clk;
   







   task run_test1;
      integer 	    i;
      begin
	 $display("(TT) --------------------------------------------------");
	 $display("(TT) Test 1: Basic R/W ");
	 $display("(TT) 1. Writes 32, 31, ... to x0, x1, ... consecutively");
	 $display("(TT) 2. RS1 reads x31, x0, x1, ...");
	 $display("(TT) 3. RS2 reads x30, x31, x0, x1, ...");
	 $display("(TT) 4. RS1 should read X, 0, 31, 30, ...");
	 $display("(TT) 5. RS2 should read X, X, 0, 31, 30, ...");
	 $display("(TT) 6. No stray value should remain");
	 $display("(TT) --------------------------------------------------");
	 
	 resetb_tb = 1'b0;
	 we_rd_tb = 1'b0;
	 @(posedge clk_tb)	    resetb_tb = 1'b1;
	 for (i = 0; i < 40; i = i + 1) begin

	    a_rd_tb = i;

	    d_rd_tb = 32 - i%32;
	    we_rd_tb = 1'b1;

	    a_rs1_tb = i - 1;

	    a_rs2_tb = i - 2;
	    #0;

	    $display("(TT) a_rd = x%d, d_rd = %d, we_rd = %d",
		     a_rd_tb, d_rd_tb, we_rd_tb);
	    $display("(TT) a_rs1 = x%d, d_rs1 = %d",
		     a_rs1_tb, d_rs1_tb);
	    $display("(TT) a_rs2 = x%d, d_rs2 = %d",
		     a_rs2_tb, d_rs2_tb);
	    $display("");
	    @(posedge clk_tb);
	 end
      end
   endtask



   task run_test2;
      integer 	    i;
      begin
	 $display("(TT) --------------------------------------------------");
	 $display("(TT) Test 2: Forwarding R/W ");
	 $display("(TT) 1. Writes 32, 31, ... to x0, x1, ... consecutively");
	 $display("(TT) 2. RS1 reads x0, x1, ...");
	 $display("(TT) 3. RS2 reads x31, x0, x1, ...");
	 $display("(TT) 4. RS1 should read 0, 31, 30, ...");
	 $display("(TT) 5. RS2 should read X, 0, 31, 30, ...");
	 $display("(TT) 6. No stray value should remain");
	 $display("(TT) --------------------------------------------------");
	 
	 resetb_tb = 1'b0;
	 we_rd_tb = 1'b0;
	 @(posedge clk_tb)	    resetb_tb = 1'b1;
	 for (i = 0; i < 40; i = i + 1) begin

	    a_rd_tb = i;

	    d_rd_tb = 32 - i%32;
	    we_rd_tb = 1'b1;

	    a_rs1_tb = i;

	    a_rs2_tb = i - 1;
	    #0;

	    $display("(TT) a_rd = x%d, d_rd = %d, we_rd = %d",
		     a_rd_tb, d_rd_tb, we_rd_tb);
	    $display("(TT) a_rs1 = x%d, d_rs1 = %d",
		     a_rs1_tb, d_rs1_tb);
	    $display("(TT) a_rs2 = x%d, d_rs2 = %d",
		     a_rs2_tb, d_rs2_tb);
	    $display("");
	    @(posedge clk_tb);
	 end
      end
   endtask
   
   regfile UUT(
	       .clk(clk_tb), .resetb(resetb_tb),
	       .a_rs1(a_rs1_tb), .d_rs1(d_rs1_tb),
	       .a_rs2(a_rs2_tb), .d_rs2(d_rs2_tb),
	       .a_rd(a_rd_tb), .d_rd(d_rd_tb),
	       .we_rd(we_rd_tb)
	       );


   initial
     begin : RUN_ALL_TESTS
	$dumpfile("tb_log/regfile_tb.vcd");
	$dumpvars(0,regfile_tb);

	@(posedge clk_tb);

	run_test1();

	run_test2();

	$finish;
	
     end


endmodule