data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v
1: b'%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:21: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.v\n             data/full_repos/permissive/161048197/project_1.srcs/sources_1/new,data/full_repos/permissive/161048197/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:28: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] pc,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input [`DATA_BUS] pc,\n                    ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:29: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] raw_inst,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:30: Define or directive not defined: \'`INST_BUS\'\n    input [`INST_BUS] inst,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:31: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] imm,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:33: Define or directive not defined: \'`ALU_OP_WIDTH\'\n    input [`ALU_OP_WIDTH-1:0] alu_op,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:34: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] alu_rs,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:35: Define or directive not defined: \'`DATA_BUS\'\n    input [`DATA_BUS] alu_rt,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:42: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] res,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:44: Define or directive not defined: \'`DATA_BUS\'\n    output [`DATA_BUS] branch_target\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:46: Define or directive not defined: \'`DATA_BUS\'\n    wire [`DATA_BUS] alu_rd, move_res;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`DATA_BUS] alu_rd, move_res;\n                   ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:52: Define or directive not defined: \'`DATA_BUS\'\n    reg [`DATA_BUS] raw_bt;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg [`DATA_BUS] raw_bt;\n                  ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:53: Define or directive not defined: \'`DATA_BUS\'\n    wire [`DATA_BUS] pc4 = pc + 4;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire [`DATA_BUS] pc4 = pc + 4;\n                   ^\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:62: Define or directive not defined: \'`INST_J\'\n                if (inst == `INST_J)\n                            ^~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:63: Define or directive not defined: \'`RAW_INST_ADDR_BUS\'\n                    raw_bt <= { pc4[DATA_WIDTH-1:28], raw_inst[`RAW_INST_ADDR_BUS], 2\'b00 };\n                                                               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/161048197/project_1.srcs/sources_1/new/execution.v:74: Define or directive not defined: \'`JUMP_REG\'\n    assign branch_target = jump == `JUMP_REG ? alu_rs : raw_bt;\n                                   ^~~~~~~~~\n%Error: Exiting due to 20 error(s)\n'
module execution#(parameter DATA_WIDTH = 32)(
    input clk,
    input rst_n,
    input stall,

    input [`DATA_BUS] pc,
    input [`DATA_BUS] raw_inst,
    input [`INST_BUS] inst,
    input [`DATA_BUS] imm,

    input [`ALU_OP_WIDTH-1:0] alu_op,
    input [`DATA_BUS] alu_rs,
    input [`DATA_BUS] alu_rt,

    input jump,
    input branch,
    


    output [`DATA_BUS] res,
    output take_branch,
    output [`DATA_BUS] branch_target
);
    wire [`DATA_BUS] alu_rd, move_res;

    assign take_branch = branch && alu_rd;
    
    assign res = alu_rd;
    
    reg [`DATA_BUS] raw_bt;
    wire [`DATA_BUS] pc4 = pc + 4;
    
    always @*
    begin
        raw_bt <= 0;
        if (branch)
        begin
            if (jump)
            begin
                if (inst == `INST_J)
                    raw_bt <= { pc4[DATA_WIDTH-1:28], raw_inst[`RAW_INST_ADDR_BUS], 2'b00 };
                else
                    raw_bt <= 0;
            end
            else
            begin
                raw_bt <= pc4 + {imm[DATA_WIDTH-3:0], 2'b00};
            end
        end
    end
    
    assign branch_target = jump == `JUMP_REG ? alu_rs : raw_bt;



    arithmetic_logic_unit #(.DATA_WIDTH(DATA_WIDTH)) alu(
        .stall(stall),
        .op(alu_op),
        .rs(alu_rs),
        .rt(alu_rt),
        .rd(alu_rd)
    );
endmodule
module execution#(parameter DATA_WIDTH = 32)(
    input clk,
    input rst_n,
    input stall,

    input [`DATA_BUS] pc,
    input [`DATA_BUS] raw_inst,
    input [`INST_BUS] inst,
    input [`DATA_BUS] imm,

    input [`ALU_OP_WIDTH-1:0] alu_op,
    input [`DATA_BUS] alu_rs,
    input [`DATA_BUS] alu_rt,

    input jump,
    input branch,
    


    output [`DATA_BUS] res,
    output take_branch,
    output [`DATA_BUS] branch_target
);

    wire [`DATA_BUS] alu_rd, move_res;

    assign take_branch = branch && alu_rd;
    
    assign res = alu_rd;
    
    reg [`DATA_BUS] raw_bt;
    wire [`DATA_BUS] pc4 = pc + 4;
    
    always @*
    begin
        raw_bt <= 0;
        if (branch)
        begin
            if (jump)
            begin
                if (inst == `INST_J)
                    raw_bt <= { pc4[DATA_WIDTH-1:28], raw_inst[`RAW_INST_ADDR_BUS], 2'b00 };
                else
                    raw_bt <= 0;
            end
            else
            begin
                raw_bt <= pc4 + {imm[DATA_WIDTH-3:0], 2'b00};
            end
        end
    end
    
    assign branch_target = jump == `JUMP_REG ? alu_rs : raw_bt;



    arithmetic_logic_unit #(.DATA_WIDTH(DATA_WIDTH)) alu(
        .stall(stall),
        .op(alu_op),
        .rs(alu_rs),
        .rt(alu_rt),
        .rd(alu_rd)
    );
endmodule