data/full_repos/permissive/195073547/verilog_source/add_2_1/wptr_full.v
1: b'%Warning-WIDTH: data/full_repos/permissive/195073547/verilog_source/add_2_1/wptr_full.v:46: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'winc\' generates 1 bits.\n                                                                                          : ... In instance wptr_full\n    assign wbnext = !wfull ? wbin + winc : wbin;\n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module wptr_full (wfull, wptr, afull_n, winc, wclk, wrst_n);
    parameter               ADDRSIZE = 8;
    output                  wfull;
    output  [ADDRSIZE-1:0]  wptr;
    input                   afull_n;
    input                   winc, wclk, wrst_n;
    reg     [ADDRSIZE-1:0]  wptr, wbin;
    reg                     wfull, wfull2;
    wire    [ADDRSIZE-1:0]  wgnext, wbnext;



    always @(posedge wclk or negedge wrst_n)
        if (!wrst_n) begin
            wbin <= 0;
            wptr <= 0;
        end
        else begin
            wbin <= wbnext;
            wptr <= wgnext;
        end



    assign wbnext = !wfull ? wbin + winc : wbin;
    assign wgnext = (wbnext>>1) ^ wbnext;
    
    always @(posedge wclk or negedge wrst_n or negedge afull_n)
        if      (!wrst_n )  {wfull,wfull2} <= 2'b00;
        else if (!afull_n)  {wfull,wfull2} <= 2'b11;
        else                {wfull,wfull2} <= {wfull2,~afull_n};
endmodule
module wptr_full (wfull, wptr, afull_n, winc, wclk, wrst_n);

    parameter               ADDRSIZE = 8;
    output                  wfull;
    output  [ADDRSIZE-1:0]  wptr;
    input                   afull_n;
    input                   winc, wclk, wrst_n;
    reg     [ADDRSIZE-1:0]  wptr, wbin;
    reg                     wfull, wfull2;
    wire    [ADDRSIZE-1:0]  wgnext, wbnext;



    always @(posedge wclk or negedge wrst_n)
        if (!wrst_n) begin
            wbin <= 0;
            wptr <= 0;
        end
        else begin
            wbin <= wbnext;
            wptr <= wgnext;
        end



    assign wbnext = !wfull ? wbin + winc : wbin;
    assign wgnext = (wbnext>>1) ^ wbnext;
    
    always @(posedge wclk or negedge wrst_n or negedge afull_n)
        if      (!wrst_n )  {wfull,wfull2} <= 2'b00;
        else if (!afull_n)  {wfull,wfull2} <= 2'b11;
        else                {wfull,wfull2} <= {wfull2,~afull_n};
endmodule