data/full_repos/permissive/102388603/rmii_tx.v
data/verilator_xmls/ae7a0491-2127-4ac3-bafe-79cc3d084be8.xml
module rmii_tx
(	input clk,
	input rst,
	input [7:0]dataIn,
	input [15:0]dataLen,
	input start,
	output reg getByte,
	output ready,
	output [1:0]dataOut,
	output reg TXEN,
	output [15:0]numByteSend);


reg clkDev2;
always @(posedge clk, posedge rst)
if(rst)
	clkDev2 <= 0;
else
	clkDev2 <= ~clkDev2;


reg [7:0]dataTransmit;


assign dataOut = dataTransmit[1:0];


reg [1:0]state;
parameter idle		= 2'b00;
parameter send		= 2'b01;

reg [4:0]countBitSend;
reg [15:0]countByteSend;
reg [15:0]lenByteSend;

assign numByteSend = countByteSend;



assign ready = (state == idle) ? 1:0;

always @(negedge clk, posedge rst)
if(rst)
begin
	dataTransmit <= 0;
	countBitSend <= 0;
	TXEN <= 0;
	state <= idle;
	countByteSend <= 0;
	lenByteSend <= 0;
	getByte <= 0;
end
else
begin
	if(clkDev2)
	begin
		case(state)
		idle:
		begin
			if(start)
			begin
				countByteSend <= 1;
				lenByteSend <= dataLen;
				dataTransmit <= dataIn;
				state <= send;
				TXEN <= 1;
				countBitSend <= 0;
			end
			else
				TXEN <= 0;
		end
		
		send:
		begin
			if(countBitSend == 2)
				getByte <= 1;
			else
				getByte <= 0;
				
			if(countBitSend < 3)
			begin
				dataTransmit <= dataTransmit >> 2;
				countBitSend <= countBitSend + 1;
			end
			else if(countBitSend == 3)
			begin
				dataTransmit <= dataIn;
				countBitSend <= 0;
				countByteSend <= countByteSend + 1;
				if(countByteSend >= lenByteSend)
				begin
					state <= idle;
					TXEN <= 0;
				end
			end
		end
		endcase
	end
end

endmodule
module rmii_tx
(	input clk,
	input rst,
	input [7:0]dataIn,
	input [15:0]dataLen,
	input start,
	output reg getByte,
	output ready,
	output [1:0]dataOut,
	output reg TXEN,
	output [15:0]numByteSend);



reg clkDev2;
always @(posedge clk, posedge rst)
if(rst)
	clkDev2 <= 0;
else
	clkDev2 <= ~clkDev2;


reg [7:0]dataTransmit;


assign dataOut = dataTransmit[1:0];


reg [1:0]state;
parameter idle		= 2'b00;
parameter send		= 2'b01;

reg [4:0]countBitSend;
reg [15:0]countByteSend;
reg [15:0]lenByteSend;

assign numByteSend = countByteSend;



assign ready = (state == idle) ? 1:0;

always @(negedge clk, posedge rst)
if(rst)
begin
	dataTransmit <= 0;
	countBitSend <= 0;
	TXEN <= 0;
	state <= idle;
	countByteSend <= 0;
	lenByteSend <= 0;
	getByte <= 0;
end
else
begin
	if(clkDev2)
	begin
		case(state)
		idle:
		begin
			if(start)
			begin
				countByteSend <= 1;
				lenByteSend <= dataLen;
				dataTransmit <= dataIn;
				state <= send;
				TXEN <= 1;
				countBitSend <= 0;
			end
			else
				TXEN <= 0;
		end
		
		send:
		begin
			if(countBitSend == 2)
				getByte <= 1;
			else
				getByte <= 0;
				
			if(countBitSend < 3)
			begin
				dataTransmit <= dataTransmit >> 2;
				countBitSend <= countBitSend + 1;
			end
			else if(countBitSend == 3)
			begin
				dataTransmit <= dataIn;
				countBitSend <= 0;
				countByteSend <= countByteSend + 1;
				if(countByteSend >= lenByteSend)
				begin
					state <= idle;
					TXEN <= 0;
				end
			end
		end
		endcase
	end
end

endmodule