data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/xilinx/RAMB8X32_SDP.v
1: b"%Error: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/xilinx/RAMB8X32_SDP.v:81: Cannot find file containing module: 'RAMB8BWER'\n   RAMB8BWER\n   ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/xilinx,data/full_repos/permissive/20430511/RAMB8BWER\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/xilinx,data/full_repos/permissive/20430511/RAMB8BWER.v\n             data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/verilog/xilinx,data/full_repos/permissive/20430511/RAMB8BWER.sv\n             RAMB8BWER\n             RAMB8BWER.v\n             RAMB8BWER.sv\n             obj_dir/RAMB8BWER\n             obj_dir/RAMB8BWER.v\n             obj_dir/RAMB8BWER.sv\n%Error: Exiting due to 1 error(s)\n"
module RAMB8X32_SDP #(parameter DELAY = 3)
   (
    input         WCLK,
    input         WE,
    input [7:0]   WADDR,
    input [31:0]  DI,
    input         RCLK,
    input         CE,
    input [7:0]   RADDR,
    output [31:0] DO
    );


`ifdef __icarus



   reg [31:0]     sram[0:255];
   reg [31:0]     reg_DO = 0;

   assign DO = reg_DO;

   always @(posedge WCLK)
     if (WE) sram[WADDR] <= #DELAY DI;

   always @(posedge RCLK)
     if (CE) reg_DO <= #DELAY sram[RADDR];


`else



   wire [12:0]   RADR = {RADDR, 5'b0};
   wire [12:0]   WADR = {WADDR, 5'b0};

   RAMB8BWER
     #(.DATA_WIDTH_A(36),
       .DATA_WIDTH_B(36),
       .DOA_REG(0),
       .DOB_REG(0),
       .EN_RSTRAM_A("FALSE"),
       .EN_RSTRAM_B("FALSE"),
       .INIT_A(18'h00000),
       .INIT_B(18'h00000),
       .INIT_FILE("NONE"),
       .RAM_MODE("SDP"),
       .RSTTYPE("SYNC"),
       .RST_PRIORITY_A("CE"),
       .RST_PRIORITY_B("CE"),
       .SIM_COLLISION_CHECK("NONE"),
       .SRVAL_A(18'h00000),
       .SRVAL_B(18'h00000),



       .WRITE_MODE_A("WRITE_FIRST"),
       .WRITE_MODE_B("WRITE_FIRST") 
   )
   SRAM0
     (
       .CLKAWRCLK(WCLK),
       .ENAWREN(WE),
       .ADDRAWRADDR(WADR),
       .DIADI(DI[15:0]),
       .DIPADIP(2'b00),
       .DIBDI(DI[31:16]),
       .DIPBDIP(2'b00),

       .CLKBRDCLK(RCLK),
       .ENBRDEN(CE),
       .ADDRBRDADDR(RADR),
       .DOADO(DO[15:0]),
       .DOPADOP(),
       .DOBDO(DO[31:16]),
       .DOPBDOP(),

       .REGCEA(1'b0),
       .RSTA(1'b0),
       .WEAWEL({WE, WE}),

       .REGCEBREGCE(1'b1),
       .RSTBRST(1'b0),
       .WEBWEU({WE, WE})

   );
`endif


endmodule
module RAMB8X32_SDP #(parameter DELAY = 3)
   (
    input         WCLK,
    input         WE,
    input [7:0]   WADDR,
    input [31:0]  DI,
    input         RCLK,
    input         CE,
    input [7:0]   RADDR,
    output [31:0] DO
    );



`ifdef __icarus



   reg [31:0]     sram[0:255];
   reg [31:0]     reg_DO = 0;

   assign DO = reg_DO;

   always @(posedge WCLK)
     if (WE) sram[WADDR] <= #DELAY DI;

   always @(posedge RCLK)
     if (CE) reg_DO <= #DELAY sram[RADDR];


`else



   wire [12:0]   RADR = {RADDR, 5'b0};
   wire [12:0]   WADR = {WADDR, 5'b0};

   RAMB8BWER
     #(.DATA_WIDTH_A(36),
       .DATA_WIDTH_B(36),
       .DOA_REG(0),
       .DOB_REG(0),
       .EN_RSTRAM_A("FALSE"),
       .EN_RSTRAM_B("FALSE"),
       .INIT_A(18'h00000),
       .INIT_B(18'h00000),
       .INIT_FILE("NONE"),
       .RAM_MODE("SDP"),
       .RSTTYPE("SYNC"),
       .RST_PRIORITY_A("CE"),
       .RST_PRIORITY_B("CE"),
       .SIM_COLLISION_CHECK("NONE"),
       .SRVAL_A(18'h00000),
       .SRVAL_B(18'h00000),



       .WRITE_MODE_A("WRITE_FIRST"),
       .WRITE_MODE_B("WRITE_FIRST") 
   )
   SRAM0
     (
       .CLKAWRCLK(WCLK),
       .ENAWREN(WE),
       .ADDRAWRADDR(WADR),
       .DIADI(DI[15:0]),
       .DIPADIP(2'b00),
       .DIBDI(DI[31:16]),
       .DIPBDIP(2'b00),

       .CLKBRDCLK(RCLK),
       .ENBRDEN(CE),
       .ADDRBRDADDR(RADR),
       .DOADO(DO[15:0]),
       .DOPADOP(),
       .DOBDO(DO[31:16]),
       .DOPBDOP(),

       .REGCEA(1'b0),
       .RSTA(1'b0),
       .WEAWEL({WE, WE}),

       .REGCEBREGCE(1'b1),
       .RSTBRST(1'b0),
       .WEBWEU({WE, WE})

   );
`endif


endmodule