data/full_repos/permissive/200650987/src/verilog/discarded/cod_mine/icache/streambuffer_control.v
 line:55: before: ")"
1: b"%Error: data/full_repos/permissive/200650987/src/verilog/discarded/cod_mine/icache/streambuffer_control.v:55: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: Exiting due to 1 error(s)\n"
module streambuffer_control
(
    input          clk,
    input          rst,
    input   [31:0] target_addr,
    input          target_req,
    output         target_addr_ok,
    output         target_data_ok,
    output  [31:0] target_data,
   


    output  [3 :0] arid   ,
    output  [31:0] araddr,
    output  [7 :0] arlen  ,
    output  [2 :0] arsize ,
    output  [1 :0] arburst,
    output  [1 :0] arlock ,
    output  [3 :0] arcache,
    output  [2 :0] arprot ,
    output         arvalid,
    input          arready,

    input [3 :0] rid    ,
    input [31:0] rdata  ,
    input [1 :0] rresp ,
    input        rlast ,
    input        rvalid ,
    output       rready ,

    output  [3 :0] awid   ,
    output  [31:0] awaddr ,
    output  [7 :0] awlen  ,
    output  [2 :0] awsize ,
    output  [1 :0] awburst,
    output  [1 :0] awlock ,
    output  [3 :0] awcache,
    output  [2 :0] awprot ,
    output         awvalid,
    input          awready,

    output  [3 :0] wid    ,
    output  [31:0] wdata  ,
    output  [3 :0] wstrb  ,
    output         wlast  ,
    output         wvalid ,
    input          wready ,

    input [3 :0] bid    ,
    input [1 :0] bresp  ,
    input        bvalid ,
    output       bready ,

);



streambuffer way_0 ();
streambuffer way_1 ();



endmodule
module streambuffer_control
(
    input          clk,
    input          rst,
    input   [31:0] target_addr,
    input          target_req,
    output         target_addr_ok,
    output         target_data_ok,
    output  [31:0] target_data,
   


    output  [3 :0] arid   ,
    output  [31:0] araddr,
    output  [7 :0] arlen  ,
    output  [2 :0] arsize ,
    output  [1 :0] arburst,
    output  [1 :0] arlock ,
    output  [3 :0] arcache,
    output  [2 :0] arprot ,
    output         arvalid,
    input          arready,

    input [3 :0] rid    ,
    input [31:0] rdata  ,
    input [1 :0] rresp ,
    input        rlast ,
    input        rvalid ,
    output       rready ,

    output  [3 :0] awid   ,
    output  [31:0] awaddr ,
    output  [7 :0] awlen  ,
    output  [2 :0] awsize ,
    output  [1 :0] awburst,
    output  [1 :0] awlock ,
    output  [3 :0] awcache,
    output  [2 :0] awprot ,
    output         awvalid,
    input          awready,

    output  [3 :0] wid    ,
    output  [31:0] wdata  ,
    output  [3 :0] wstrb  ,
    output         wlast  ,
    output         wvalid ,
    input          wready ,

    input [3 :0] bid    ,
    input [1 :0] bresp  ,
    input        bvalid ,
    output       bready ,

);




streambuffer way_0 ();
streambuffer way_1 ();



endmodule