data/full_repos/permissive/165846232/components/LUA/LUA.v
1: b'%Warning-WIDTHCONCAT: data/full_repos/permissive/165846232/components/LUA/LUA.v:48: Unsized numbers/parameters not allowed in concatenations.\n                                                                                  : ... In instance LUA\n                ShiftValue <= { {DATA_WIDTH{1\'d0}}, BLOCK_SIZE };\n                                                    ^~~~~~~~~~\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/165846232/components/LUA/LUA.v:48: Unsized numbers/parameters not allowed in replications.\n                                                                                  : ... In instance LUA\n                ShiftValue <= { {DATA_WIDTH{1\'d0}}, BLOCK_SIZE };\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/165846232/components/LUA/LUA.v:49: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'InputY\' generates 16 bits.\n                                                                            : ... In instance LUA\n                InputYCopy <= InputY;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/165846232/components/LUA/LUA.v:55: Operator ADD expects 34 bits on the LHS, but LHS\'s VARREF \'Address\' generates 32 bits.\n                                                                            : ... In instance LUA\n                    Address <= Address + ShiftValue;\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/165846232/components/LUA/LUA.v:55: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s ADD generates 34 bits.\n                                                                            : ... In instance LUA\n                    Address <= Address + ShiftValue;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/165846232/components/LUA/LUA.v:63: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'InputX\' generates 16 bits.\n                                                                            : ... In instance LUA\n                Address <= Address + InputX;\n                                   ^\n%Error: Exiting due to 6 warning(s)\n'
module LUA
#(
    parameter DATA_WIDTH = 16,
    parameter BLOCK_SIZE = 0
)
(
   input wire [DATA_WIDTH-1:0] InputX,
   input wire [DATA_WIDTH-1:0] InputY,
   input wire Start,
   input wire Clk,
   output reg [(2*DATA_WIDTH)-1:0] Address,
   output wire Ready
);

   reg [DATA_WIDTH:0] InputYCopy;
   reg [(2*DATA_WIDTH)+1:0] ShiftValue;
   
   reg [$clog2(DATA_WIDTH)+1:0] Bit; 
   assign Ready = (Bit == 0);
   
   initial Bit = 0;

   always @(posedge Clk)
   begin
        if(Ready && Start)
        begin
                Bit <= DATA_WIDTH+1;
                Address <= 0;
                ShiftValue <= { {DATA_WIDTH{1'd0}}, BLOCK_SIZE };
                InputYCopy <= InputY;
            end
        else if(Bit > 1)
            begin
                if(InputYCopy[0] == 1'b1)
                begin
                    Address <= Address + ShiftValue;
                end
                InputYCopy <= InputYCopy >> 1;
                ShiftValue <= ShiftValue << 1;
                Bit <= Bit - 1;
            end
        else if(Bit == 1)
            begin
                Address <= Address + InputX;
                Bit <= Bit - 1;
            end
   end
     
endmodule
module LUA
#(
    parameter DATA_WIDTH = 16,
    parameter BLOCK_SIZE = 0
)
(
   input wire [DATA_WIDTH-1:0] InputX,
   input wire [DATA_WIDTH-1:0] InputY,
   input wire Start,
   input wire Clk,
   output reg [(2*DATA_WIDTH)-1:0] Address,
   output wire Ready
);


   reg [DATA_WIDTH:0] InputYCopy;
   reg [(2*DATA_WIDTH)+1:0] ShiftValue;
   
   reg [$clog2(DATA_WIDTH)+1:0] Bit; 
   assign Ready = (Bit == 0);
   
   initial Bit = 0;

   always @(posedge Clk)
   begin
        if(Ready && Start)
        begin
                Bit <= DATA_WIDTH+1;
                Address <= 0;
                ShiftValue <= { {DATA_WIDTH{1'd0}}, BLOCK_SIZE };
                InputYCopy <= InputY;
            end
        else if(Bit > 1)
            begin
                if(InputYCopy[0] == 1'b1)
                begin
                    Address <= Address + ShiftValue;
                end
                InputYCopy <= InputYCopy >> 1;
                ShiftValue <= ShiftValue << 1;
                Bit <= Bit - 1;
            end
        else if(Bit == 1)
            begin
                Address <= Address + InputX;
                Bit <= Bit - 1;
            end
   end
     
endmodule