data/full_repos/permissive/167489907/Examples/Adder-Subtractor/addsub.v
data/verilator_xmls/6a453216-f1cb-44d3-9039-6fccfdfd8110.xml
module addsub(
	input [7:0] dataa,
	input [7:0] datab,
	input add_sub,
	input clk,
	output reg [8:0] result);
	
always @(posedge clk)
begin	
	if(add_sub)
		result <= dataa+datab;
	else
		result <= dataa-datab;
end
endmodule
module addsub(
	input [7:0] dataa,
	input [7:0] datab,
	input add_sub,
	input clk,
	output reg [8:0] result);

	
always @(posedge clk)
begin	
	if(add_sub)
		result <= dataa+datab;
	else
		result <= dataa-datab;
end
endmodule