data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/rom_caller_3.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/rom_caller_3.v:25: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                 : ... In instance rom_caller_3\n  reg [3:0] M_count_d, M_count_q = 1\'h0;\n                                   ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/rom_caller_3.v:29: Cannot find file containing module: \'rom_test_8\'\n  rom_test_8 rom (\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170/rom_test_8\n             data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170/rom_test_8.v\n             data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog,data/full_repos/permissive/209997170/rom_test_8.sv\n             rom_test_8\n             rom_test_8.v\n             rom_test_8.sv\n             obj_dir/rom_test_8\n             obj_dir/rom_test_8.v\n             obj_dir/rom_test_8.sv\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/rom_caller_3.v:44: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                 : ... In instance rom_caller_3\n        M_count_d = 1\'h0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/rom_caller_3.v:45: Operator EQ expects 8 bits on the RHS, but RHS\'s CONST \'7\'h68\' generates 7 bits.\n                                                                                                                                                                 : ... In instance rom_caller_3\n        if (new_rx && rx_data == 7\'h68) begin\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/209997170/Sound/rom_tutorial/work/planAhead/rom_tutorial/rom_tutorial.srcs/sources_1/imports/verilog/rom_caller_3.v:53: Operator EQ expects 5 bits on the LHS, but LHS\'s VARREF \'M_count_q\' generates 4 bits.\n                                                                                                                                                                 : ... In instance rom_caller_3\n          if (M_count_q == 5\'h0a) begin\n                        ^~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module rom_caller_3 (
    input clk,
    input rst,
    input new_rx,
    input [7:0] rx_data,
    output reg new_tx,
    output reg [7:0] tx_data,
    input tx_busy
  );
  
  
  
  localparam NUM_LETTERS = 4'hb;
  
  localparam IDLE_state = 1'd0;
  localparam GREET_state = 1'd1;
  
  reg M_state_d, M_state_q = IDLE_state;
  reg [3:0] M_count_d, M_count_q = 1'h0;
  
  wire [8-1:0] M_rom_letter;
  reg [4-1:0] M_rom_address;
  rom_test_8 rom (
    .address(M_rom_address),
    .letter(M_rom_letter)
  );
  
  always @* begin
    M_state_d = M_state_q;
    M_count_d = M_count_q;
    
    M_rom_address = M_count_q;
    tx_data = M_rom_letter;
    new_tx = 1'h0;
    
    case (M_state_q)
      IDLE_state: begin
        M_count_d = 1'h0;
        if (new_rx && rx_data == 7'h68) begin
          M_state_d = GREET_state;
        end
      end
      GREET_state: begin
        if (!tx_busy) begin
          M_count_d = M_count_q + 1'h1;
          new_tx = 1'h1;
          if (M_count_q == 5'h0a) begin
            M_state_d = IDLE_state;
          end
        end
      end
    endcase
  end
  
  always @(posedge clk) begin
    M_count_q <= M_count_d;
    
    if (rst == 1'b1) begin
      M_state_q <= 1'h0;
    end else begin
      M_state_q <= M_state_d;
    end
  end
  
endmodule
module rom_caller_3 (
    input clk,
    input rst,
    input new_rx,
    input [7:0] rx_data,
    output reg new_tx,
    output reg [7:0] tx_data,
    input tx_busy
  );

  
  
  
  localparam NUM_LETTERS = 4'hb;
  
  localparam IDLE_state = 1'd0;
  localparam GREET_state = 1'd1;
  
  reg M_state_d, M_state_q = IDLE_state;
  reg [3:0] M_count_d, M_count_q = 1'h0;
  
  wire [8-1:0] M_rom_letter;
  reg [4-1:0] M_rom_address;
  rom_test_8 rom (
    .address(M_rom_address),
    .letter(M_rom_letter)
  );
  
  always @* begin
    M_state_d = M_state_q;
    M_count_d = M_count_q;
    
    M_rom_address = M_count_q;
    tx_data = M_rom_letter;
    new_tx = 1'h0;
    
    case (M_state_q)
      IDLE_state: begin
        M_count_d = 1'h0;
        if (new_rx && rx_data == 7'h68) begin
          M_state_d = GREET_state;
        end
      end
      GREET_state: begin
        if (!tx_busy) begin
          M_count_d = M_count_q + 1'h1;
          new_tx = 1'h1;
          if (M_count_q == 5'h0a) begin
            M_state_d = IDLE_state;
          end
        end
      end
    endcase
  end
  
  always @(posedge clk) begin
    M_count_q <= M_count_d;
    
    if (rst == 1'b1) begin
      M_state_q <= 1'h0;
    end else begin
      M_state_q <= M_state_d;
    end
  end
  
endmodule