data/full_repos/permissive/159891569/duty_cycler.t.v
 line:67: before: "$"
1: b'%Error: data/full_repos/permissive/159891569/duty_cycler.t.v:1: Cannot find include file: duty_cycler.v\n`include "duty_cycler.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/duty_cycler.v\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/duty_cycler.v.v\n             data/full_repos/permissive/159891569,data/full_repos/permissive/159891569/duty_cycler.v.sv\n             duty_cycler.v\n             duty_cycler.v.v\n             duty_cycler.v.sv\n             obj_dir/duty_cycler.v\n             obj_dir/duty_cycler.v.v\n             obj_dir/duty_cycler.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/159891569/duty_cycler.t.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #4 clk <= ~clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/159891569/duty_cycler.t.v:22: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("duty_cycler.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/159891569/duty_cycler.t.v:23: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars();\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159891569/duty_cycler.t.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #300\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/duty_cycler.t.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #300\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/duty_cycler.t.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #300\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/159891569/duty_cycler.t.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #300\n      ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module test_duty_cycler();

   reg clk;
   wire cycler_out;
   reg[1:0] duty_cycle;


   duty_cycler cycler (.clk(clk),
      .duty_cycle(duty_cycle),
      .out(cycler_out));

   initial
      clk <= 1'b0;

   always
      #4 clk <= ~clk;

   initial begin

      $dumpfile("duty_cycler.vcd");
      $dumpvars();

      duty_cycle = 2'd0;
      #300
      duty_cycle = 2'd1;
      #300
      duty_cycle = 2'd2;
      #300
      duty_cycle = 2'd3;
      #300

      $finish();     

   end












endmodule
module test_duty_cycler();


   reg clk;
   wire cycler_out;
   reg[1:0] duty_cycle;


   duty_cycler cycler (.clk(clk),
      .duty_cycle(duty_cycle),
      .out(cycler_out));

   initial
      clk <= 1'b0;

   always
      #4 clk <= ~clk;

   initial begin

      $dumpfile("duty_cycler.vcd");
      $dumpvars();

      duty_cycle = 2'd0;
      #300
      duty_cycle = 2'd1;
      #300
      duty_cycle = 2'd2;
      #300
      duty_cycle = 2'd3;
      #300

      $finish();     

   end












endmodule