data/full_repos/permissive/195227969/work/code/sb_sim_rtl/SB_DFFSS.v
data/verilator_xmls/bd5af763-5589-42a8-95fc-ebdf83b248be.xml
module SB_DFFSS
  ( input C,D,S,
    output reg Q
    );
   initial
     Q = 1'b0;
   always @(posedge C)
       Q <= S ? 1'b1 : D;
endmodule
module SB_DFFSS
  ( input C,D,S,
    output reg Q
    );

   initial
     Q = 1'b0;
   always @(posedge C)
       Q <= S ? 1'b1 : D;
endmodule