data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v
 line:178: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:123: Operator VAR \'ADDR_MASK\' expects 32 bits on the Initial value, but Initial value\'s NOT generates 64 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n    localparam  [AXI4_ADDR_WIDTH-1:0]   ADDR_MASK = ~((64\'d1 << AXI4_DATA_SIZE) - 1);\n                                        ^~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:193: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'INIT_CTL_CONTROL\' generates 4 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n            reg_ctl_control  <= INIT_CTL_CONTROL;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:195: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n            reg_param_stride <= INIT_PARAM_STRIDE & ADDR_MASK;\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:207: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_ctl_control\' generates 3 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                ADR_CTL_CONTROL:  reg_ctl_control  <= reg_mask(reg_ctl_control,  s_wb_dat_i, s_wb_sel_i);\n                                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:207: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                ADR_CTL_CONTROL:  reg_ctl_control  <= reg_mask(reg_ctl_control,  s_wb_dat_i, s_wb_sel_i);\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:209: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_stride\' generates 16 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                ADR_PARAM_STRIDE: reg_param_stride <= reg_mask(reg_param_stride, s_wb_dat_i, s_wb_sel_i) & ADDR_MASK;\n                                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:209: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                ADR_PARAM_STRIDE: reg_param_stride <= reg_mask(reg_param_stride, s_wb_dat_i, s_wb_sel_i) & ADDR_MASK;\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:210: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_width\' generates 12 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                ADR_PARAM_WIDTH:  reg_param_width  <= reg_mask(reg_param_width,  s_wb_dat_i, s_wb_sel_i);\n                                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:210: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                ADR_PARAM_WIDTH:  reg_param_width  <= reg_mask(reg_param_width,  s_wb_dat_i, s_wb_sel_i);\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:211: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_height\' generates 12 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                ADR_PARAM_HEIGHT: reg_param_height <= reg_mask(reg_param_height, s_wb_dat_i, s_wb_sel_i);\n                                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:211: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                ADR_PARAM_HEIGHT: reg_param_height <= reg_mask(reg_param_height, s_wb_dat_i, s_wb_sel_i);\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:212: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_size\' generates 24 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                ADR_PARAM_SIZE:   reg_param_size   <= reg_mask(reg_param_size,   s_wb_dat_i, s_wb_sel_i);\n                                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:212: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                ADR_PARAM_SIZE:   reg_param_size   <= reg_mask(reg_param_size,   s_wb_dat_i, s_wb_sel_i);\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:213: Operator FUNCREF \'reg_mask\' expects 32 bits on the Function Argument, but Function Argument\'s VARREF \'reg_param_arlen\' generates 8 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                ADR_PARAM_ARLEN:  reg_param_arlen  <= reg_mask(reg_param_arlen,  s_wb_dat_i, s_wb_sel_i);\n                                                      ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:213: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'reg_mask\' generates 32 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                ADR_PARAM_ARLEN:  reg_param_arlen  <= reg_mask(reg_param_arlen,  s_wb_dat_i, s_wb_sel_i);\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:241: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_ctl_control\' generates 3 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_CTL_CONTROL)    ? reg_ctl_control    :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:242: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_ctl_status\' generates 1 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_CTL_STATUS)     ? sig_ctl_status     :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:243: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_ctl_index\' generates 8 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_CTL_INDEX)      ? sig_ctl_index      :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:245: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_param_stride\' generates 16 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_PARAM_STRIDE)   ? reg_param_stride   :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:246: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_param_width\' generates 12 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_PARAM_WIDTH)    ? reg_param_width    :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:247: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_param_height\' generates 12 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_PARAM_HEIGHT)   ? reg_param_height   :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:248: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_param_size\' generates 24 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_PARAM_SIZE)     ? reg_param_size     :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:249: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'reg_param_arlen\' generates 8 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_PARAM_ARLEN)    ? reg_param_arlen    :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:251: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_monitor_stride\' generates 16 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_MONITOR_STRIDE) ? sig_monitor_stride :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:252: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_monitor_width\' generates 12 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_MONITOR_WIDTH)  ? sig_monitor_width  :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:253: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_monitor_height\' generates 12 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_MONITOR_HEIGHT) ? sig_monitor_height :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:254: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_monitor_size\' generates 24 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_MONITOR_SIZE)   ? sig_monitor_size   :\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:255: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'sig_monitor_arlen\' generates 8 bits.\n                                                                                           : ... In instance jelly_vdma_axi4_to_axi4s\n                        (s_wb_adr_i == ADR_MONITOR_ARLEN)  ? sig_monitor_arlen  :\n                                                           ^\n%Error: data/full_repos/permissive/2084115/rtl/video/jelly_vdma_axi4_to_axi4s.v:299: Cannot find file containing module: \'jelly_vdma_axi4_to_axi4s_core\'\n    jelly_vdma_axi4_to_axi4s_core\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/2084115/rtl/video,data/full_repos/permissive/2084115/jelly_vdma_axi4_to_axi4s_core\n             data/full_repos/permissive/2084115/rtl/video,data/full_repos/permissive/2084115/jelly_vdma_axi4_to_axi4s_core.v\n             data/full_repos/permissive/2084115/rtl/video,data/full_repos/permissive/2084115/jelly_vdma_axi4_to_axi4s_core.sv\n             jelly_vdma_axi4_to_axi4s_core\n             jelly_vdma_axi4_to_axi4s_core.v\n             jelly_vdma_axi4_to_axi4s_core.sv\n             obj_dir/jelly_vdma_axi4_to_axi4s_core\n             obj_dir/jelly_vdma_axi4_to_axi4s_core.v\n             obj_dir/jelly_vdma_axi4_to_axi4s_core.sv\n%Error: Exiting due to 1 error(s), 28 warning(s)\n'
function [WB_DAT_WIDTH-1:0] reg_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );
    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            reg_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction
function [WB_DAT_WIDTH-1:0] reg_mask(
                                        input [WB_DAT_WIDTH-1:0] org,
                                        input [WB_DAT_WIDTH-1:0] wdat,
                                        input [WB_SEL_WIDTH-1:0] msk
                                    );

    integer i;
    begin
        for ( i = 0; i < WB_DAT_WIDTH; i = i+1 ) begin
            reg_mask[i] = msk[i/8] ? wdat[i] : org[i];
        end
    end
    endfunction