data/full_repos/permissive/199632300/HDLBits/Exam/srlatch.v
data/verilator_xmls/2ddf6bdb-b879-4e8d-b14a-8193f15cfa0e.xml
module top_module (
	input set,
	input reset,
	output reg q
);






	assign q = set ? 1'b1 : (reset ? 1'b0 : q);
	

	
	
endmodule
module top_module (
	input set,
	input reset,
	output reg q
);







	assign q = set ? 1'b1 : (reset ? 1'b0 : q);
	

	
	
endmodule