data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:47: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'Cout_\' generates 32 bits.\n                                                                          : ... In instance ALU\n  assign Cout= Cout_;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:55: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'A\' generates 32 bits.\n                                                                          : ... In instance ALU\n   5\'b00000:  {{Cout_}, {Out_}} = A;    \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:56: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                          : ... In instance ALU\n   5\'b00010:  {{Cout_}, {Out_}} = A+B;   \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:56: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                          : ... In instance ALU\n   5\'b00010:  {{Cout_}, {Out_}} = A+B;   \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:57: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                          : ... In instance ALU\n   5\'b00101:  {{Cout_}, {Out_}} = A+~B+1;  \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:57: Operator NOT expects 64 bits on the LHS, but LHS\'s VARREF \'B\' generates 32 bits.\n                                                                          : ... In instance ALU\n   5\'b00101:  {{Cout_}, {Out_}} = A+~B+1;  \n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:58: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                          : ... In instance ALU\n   5\'b00111:  {{Cout_}, {Out_}} = A+~B+1;  \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:58: Operator NOT expects 64 bits on the LHS, but LHS\'s VARREF \'B\' generates 32 bits.\n                                                                          : ... In instance ALU\n   5\'b00111:  {{Cout_}, {Out_}} = A+~B+1;  \n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:59: Operator AND expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                          : ... In instance ALU\n   5\'b01000:  {{Cout_}, {Out_}} = A&B;   \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:59: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                          : ... In instance ALU\n   5\'b01000:  {{Cout_}, {Out_}} = A&B;   \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:60: Operator OR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                          : ... In instance ALU\n   5\'b01010:  {{Cout_}, {Out_}} = A|B;   \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:60: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                          : ... In instance ALU\n   5\'b01010:  {{Cout_}, {Out_}} = A|B;   \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:61: Operator NOT expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                          : ... In instance ALU\n   5\'b01110:  {{Cout_}, {Out_}} = ~A;    \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:80: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                                          : ... In instance ALU\n  end else if(Select == 4\'b0101 && A<B) begin\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/170402453/RISC_DIVIDER/ALU.v:75: Operator LTE expects 4 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                          : ... In instance ALU\n  if(1 <= Select <= 4\'b0101) begin\n                 ^~\n%Error: Exiting due to 15 warning(s)\n'
module ALU(
    input [4:0] Select,
    input [BITS-1:0] A,
    input [BITS-1:0] B,
    output wire [BITS-1:0] Out,
	 output wire statV,
    output wire Cout,
	 output reg shift,
	 output reg LR
    );
	 
	 parameter BITS = 32;
	 
	 reg [BITS-1:0] Cout_;
	 reg [BITS-1:0] Out_;
	 reg statV_;
	 
	 initial begin
		Cout_ 	= 	0;
		Out_ 		= 	0;
		statV_	=	0;
		shift=0;
		LR=0;
	 end
	 
	 assign Out = Out_;
	 assign Cout= Cout_;
	 assign statV=statV_;
	 

	 
	 always @(*) begin
		shift=0;
		case(Select)
			5'b00000: 	{{Cout_}, {Out_}} = A;
			5'b00010: 	{{Cout_}, {Out_}} = A+B;
			5'b00101: 	{{Cout_}, {Out_}} = A+~B+1;
			5'b00111: 	{{Cout_}, {Out_}} = A+~B+1;
			5'b01000: 	{{Cout_}, {Out_}} = A&B;
			5'b01010: 	{{Cout_}, {Out_}} = A|B;
			5'b01110: 	{{Cout_}, {Out_}} = ~A;
			5'b10100:	begin shift=1; LR=1; end
			5'b11000:	begin shift=1; LR=0; end
		endcase
		







		

		if(1 <= Select <= 4'b0101) begin
			if(((A+B) > 1<<BITS) && A[BITS-1] == 0) begin

				statV_ = 1;
			end else statV_ = 0;
		end else if(Select == 4'b0101 && A<B) begin
			if((A-B)>0 && A[BITS-1] == 1) begin

				statV_ = 1;
			end else statV_ = 0;
		end else statV_ = 0;
	 end
endmodule
module ALU(
    input [4:0] Select,
    input [BITS-1:0] A,
    input [BITS-1:0] B,
    output wire [BITS-1:0] Out,
	 output wire statV,
    output wire Cout,
	 output reg shift,
	 output reg LR
    );

	 
	 parameter BITS = 32;
	 
	 reg [BITS-1:0] Cout_;
	 reg [BITS-1:0] Out_;
	 reg statV_;
	 
	 initial begin
		Cout_ 	= 	0;
		Out_ 		= 	0;
		statV_	=	0;
		shift=0;
		LR=0;
	 end
	 
	 assign Out = Out_;
	 assign Cout= Cout_;
	 assign statV=statV_;
	 

	 
	 always @(*) begin
		shift=0;
		case(Select)
			5'b00000: 	{{Cout_}, {Out_}} = A;
			5'b00010: 	{{Cout_}, {Out_}} = A+B;
			5'b00101: 	{{Cout_}, {Out_}} = A+~B+1;
			5'b00111: 	{{Cout_}, {Out_}} = A+~B+1;
			5'b01000: 	{{Cout_}, {Out_}} = A&B;
			5'b01010: 	{{Cout_}, {Out_}} = A|B;
			5'b01110: 	{{Cout_}, {Out_}} = ~A;
			5'b10100:	begin shift=1; LR=1; end
			5'b11000:	begin shift=1; LR=0; end
		endcase
		







		

		if(1 <= Select <= 4'b0101) begin
			if(((A+B) > 1<<BITS) && A[BITS-1] == 0) begin

				statV_ = 1;
			end else statV_ = 0;
		end else if(Select == 4'b0101 && A<B) begin
			if((A-B)>0 && A[BITS-1] == 1) begin

				statV_ = 1;
			end else statV_ = 0;
		end else statV_ = 0;
	 end
endmodule