data/full_repos/permissive/135822174/api/static/F721000/109_1/1/moore_machine.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/135822174/api/static/F721000/109_1/1/moore_machine.v:41: Cell has missing pin: \'div_clk\'\nclk_div myclk (clk,reset,div_clk);\n        ^~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/135822174/api/static/F721000/109_1/1/moore_machine.v:41: Signal definition not found, creating implicitly: \'div_clk\'\nclk_div myclk (clk,reset,div_clk);\n                         ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/135822174/api/static/F721000/109_1/1/moore_machine.v:41: Input port connection \'counter\' expects 32 bits on the pin connection, but pin connection\'s VARREF \'div_clk\' generates 1 bits.\n                                                                                                  : ... In instance moore_machine\nclk_div myclk (clk,reset,div_clk);\n                         ^~~~~~~\n%Error: Exiting due to 3 warning(s)\n'
module moore_machine (clk,reset,in,pause,out);
input clk,reset,pause,in;
output [6:0]out;
reg [2:0] state, nextstate;
reg [6:0]out;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010; 
parameter S3 = 3'b011; 
parameter S4 = 3'b100; 
parameter S5 = 3'b101;
clk_div myclk (clk,reset,div_clk);
always @ (posedge div_clk or negedge reset)
begin 
	if (!reset)
		state <= S0;
	else
		state <= nextstate;
end
always @ (in or pause or state)
begin 
	if (pause)
		nextstate <= state;
	else
		case (state)
		S0: begin 
			if (in==1)
				nextstate <= S1;
			else
				nextstate <= S0;
		end
		S1: begin 
			if (in==1)
				nextstate <= S2;
			else
				nextstate <= S0;
		end
		S2: begin 
			if (in==1)
				nextstate <= S4;
			else
				nextstate <= S3;
		end
		S3: begin 
			if (in==1)
				nextstate <= S3;
			else
				nextstate <= S4;
		end
		S4: begin 
			if (in==1)
				nextstate <= S5;
			else
				nextstate <= S1;
		end
		S5: begin 
			if (in==1)
				nextstate <= S5;
			else
				nextstate <= S2;
		end
		endcase

end
always @ (state)
begin 
	case (state)
	S0: out = 7'b1000000;
	S1: out = 7'b1111001;
	S2: out = 7'b0100100;
	S3: out = 7'b0110000;
	S4: out = 7'b0011001;
	S5: out = 7'b0010010;
	endcase
end 
endmodule
module moore_machine (clk,reset,in,pause,out);

input clk,reset,pause,in;
output [6:0]out;
reg [2:0] state, nextstate;
reg [6:0]out;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010; 
parameter S3 = 3'b011; 
parameter S4 = 3'b100; 
parameter S5 = 3'b101;
clk_div myclk (clk,reset,div_clk);
always @ (posedge div_clk or negedge reset)
begin 
	if (!reset)
		state <= S0;
	else
		state <= nextstate;
end
always @ (in or pause or state)
begin 
	if (pause)
		nextstate <= state;
	else
		case (state)
		S0: begin 
			if (in==1)
				nextstate <= S1;
			else
				nextstate <= S0;
		end
		S1: begin 
			if (in==1)
				nextstate <= S2;
			else
				nextstate <= S0;
		end
		S2: begin 
			if (in==1)
				nextstate <= S4;
			else
				nextstate <= S3;
		end
		S3: begin 
			if (in==1)
				nextstate <= S3;
			else
				nextstate <= S4;
		end
		S4: begin 
			if (in==1)
				nextstate <= S5;
			else
				nextstate <= S1;
		end
		S5: begin 
			if (in==1)
				nextstate <= S5;
			else
				nextstate <= S2;
		end
		endcase

end
always @ (state)
begin 
	case (state)
	S0: out = 7'b1000000;
	S1: out = 7'b1111001;
	S2: out = 7'b0100100;
	S3: out = 7'b0110000;
	S4: out = 7'b0011001;
	S5: out = 7'b0010010;
	endcase
end 
endmodule