data/full_repos/permissive/188595972/src/lib.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/188595972/src/lib.v:31: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'InputToASCII\'\nmodule InputToASCII(keyboard,ascii,e);\n       ^~~~~~~~~~~~\n                                                                    : ... Top module \'EightSegDisplayment\'\nmodule EightSegDisplayment(segmentSelect,bitSelect_m,data,clk,rst_n);\n       ^~~~~~~~~~~~~~~~~~~\n                                                                    : ... Top module \'KeyboardScaner\'\nmodule KeyboardScaner(Yin,clk,rst_n,Xout,data);\n       ^~~~~~~~~~~~~~\n                                                                    : ... Top module \'SerialClockModule\'\nmodule SerialClockModule(e,clk,rst_n,out,half);\n       ^~~~~~~~~~~~~~~~~\n                                                                    : ... Top module \'AShiftReg\'\nmodule AShiftReg(Di,D,e,set,clk,rst_n,Q);\n       ^~~~~~~~~\n                                                                    : ... Top module \'NegedgeDetector\'\nmodule NegedgeDetector(i,clk,rst_n,neg);\n       ^~~~~~~~~~~~~~~\n                                                                    : ... Top module \'JK_FF\'\nmodule JK_FF(J,K,clk,rst_n,Q);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/188595972/src/lib.v:182: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                  : ... In instance NegedgeDetector\n        if(!rst_n) negCache<=2\'d0;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/188595972/src/lib.v:187: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                  : ... In instance NegedgeDetector\n        Y={negCache[0],|antiVibrationQ};\n         ^\n%Warning-WIDTH: data/full_repos/permissive/188595972/src/lib.v:47: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'num\' generates 2 bits.\n                                                                 : ... In instance EightSegDisplayment\n        case(num)\n        ^~~~\n%Error: Exiting due to 4 warning(s)\n'
module PriorityEncoder(i,o,ex);
    input [15:0]i;
    output reg [3:0]o;
    output ex;
    wire ex1,ex2;
    wire [2:0]o1,o2;
    assign ex=ex1|ex2;
    always@(*)
        if(ex1)o={1'b1,o1};
        else o={1'b0,o2};
    PriorityEightToThree pett1(i[15:8],o1,ex1);
    PriorityEightToThree pett2(i[7:0],o2,ex2);
    endmodule
module PriorityEncoder(i,o,ex);

    input [15:0]i;
    output reg [3:0]o;
    output ex;
    wire ex1,ex2;
    wire [2:0]o1,o2;
    assign ex=ex1|ex2;
    always@(*)
        if(ex1)o={1'b1,o1};
        else o={1'b0,o2};
    PriorityEightToThree pett1(i[15:8],o1,ex1);
    PriorityEightToThree pett2(i[7:0],o2,ex2);
    endmodule