data/full_repos/permissive/158984095/Homework2/Question1_a/HW_2_1_c_tb.v
1: b'%Error: data/full_repos/permissive/158984095/Homework2/Question1_a/HW_2_1_c_tb.v:8: Unsupported or unknown PLI call: $monitor\n$monitor($time,"in1 = %b \\t in2 = %b \\t cin = %b \\t sum = %b \\t cout = %b \\n",in[1],in[0],cin,out[0],out[1]);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question1_a/HW_2_1_c_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n# 10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question1_a/HW_2_1_c_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n# 10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question1_a/HW_2_1_c_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n# 10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/158984095/Homework2/Question1_a/HW_2_1_c_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n# 10;\n^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder_3is2_type2_tb();
reg [1:0] in;
reg cin;
wire [1:0] out; 
adder_3is2_type2 testbench_instantiate(in[1:0],cin,out[1:0]);

initial begin
$monitor($time,"in1 = %b \t in2 = %b \t cin = %b \t sum = %b \t cout = %b \n",in[1],in[0],cin,out[0],out[1]);
# 10;
in[1:0] = 2'b00;
cin = 1'b0;
# 10;
in[1:0] = 2'b01;
cin = 1'b1;
# 10;
in[1:0] = 2'b11;
cin = 1'b1;
# 10;
in[1:0] = 2'b10;
cin = 1'b1;
end
endmodule
module adder_3is2_type2_tb();

reg [1:0] in;
reg cin;
wire [1:0] out; 
adder_3is2_type2 testbench_instantiate(in[1:0],cin,out[1:0]);

initial begin
$monitor($time,"in1 = %b \t in2 = %b \t cin = %b \t sum = %b \t cout = %b \n",in[1],in[0],cin,out[0],out[1]);
# 10;
in[1:0] = 2'b00;
cin = 1'b0;
# 10;
in[1:0] = 2'b01;
cin = 1'b1;
# 10;
in[1:0] = 2'b11;
cin = 1'b1;
# 10;
in[1:0] = 2'b10;
cin = 1'b1;
end
endmodule