data/full_repos/permissive/124803629/src/Pipeline_CPU/Pipeline_CPU_tb.v
1: b'%Error: data/full_repos/permissive/124803629/src/Pipeline_CPU/Pipeline_CPU_tb.v:56: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/124803629/src/Pipeline_CPU/Pipeline_CPU_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #13 reset <= 1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/124803629/src/Pipeline_CPU/Pipeline_CPU_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n forever #10 sysclk = ~sysclk;\n         ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPU_tb;
reg reset, sysclk;
reg [7:0] switch;
reg [36:0] tmprx;
wire UART_RX, UART_TX, brclk9600, brclk153600;
wire [7:0] led;
wire [6:0] digi_1;
wire [6:0] digi_2;
wire [6:0] digi_3;
wire [6:0] digi_4;

initial begin
	reset <= 0;
	sysclk <= 0;
	reset <= 0;
	switch <= 8'b01001010;
	tmprx <= 37'b11_0_0000_0101_1_0_0001_1001_1111_1111_1111_1111;
end
	
initial fork
	#13 reset <= 1;
	forever #10 sysclk = ~sysclk;
join

baudrate_generator baudrate_generator_1(.sysclk(sysclk), .reset(reset), .brclk(brclk9600), .brclk16(brclk153600));

always @(posedge brclk9600)
begin
	tmprx <= tmprx<<1;
end

assign UART_RX = tmprx[36];
	
PipelineCPU PipelineCPU_1(reset, sysclk, UART_RX, UART_TX, switch, led, digi_1, digi_2, digi_3, digi_4);

endmodule
module CPU_tb;

reg reset, sysclk;
reg [7:0] switch;
reg [36:0] tmprx;
wire UART_RX, UART_TX, brclk9600, brclk153600;
wire [7:0] led;
wire [6:0] digi_1;
wire [6:0] digi_2;
wire [6:0] digi_3;
wire [6:0] digi_4;

initial begin
	reset <= 0;
	sysclk <= 0;
	reset <= 0;
	switch <= 8'b01001010;
	tmprx <= 37'b11_0_0000_0101_1_0_0001_1001_1111_1111_1111_1111;
end
	
initial fork
	#13 reset <= 1;
	forever #10 sysclk = ~sysclk;
join

baudrate_generator baudrate_generator_1(.sysclk(sysclk), .reset(reset), .brclk(brclk9600), .brclk16(brclk153600));

always @(posedge brclk9600)
begin
	tmprx <= tmprx<<1;
end

assign UART_RX = tmprx[36];
	
PipelineCPU PipelineCPU_1(reset, sysclk, UART_RX, UART_TX, switch, led, digi_1, digi_2, digi_3, digi_4);

endmodule