data/full_repos/permissive/143278/ivltests/tern10.v
 line:12: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tern10.v:12: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("%b = %b? %b : %b", Q, flag, a, b);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tern10.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (Q !== 5\'b00101) begin\n      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/tern10.v:5: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s VARREF \'a\' generates 4 bits.\n                                                                     : ... In instance main\n   wire [4:0] Q = flag? a : b;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/tern10.v:5: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'b\' generates 4 bits.\n                                                                     : ... In instance main\n   wire [4:0] Q = flag? a : b;\n                      ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg flag;
   reg [3:0] a, b;
   wire [4:0] Q = flag? a : b;

   initial begin
      flag = 1;
      a = 4'b1010;
      b = 4'b0101;

      #1 $display("%b = %b? %b : %b", Q, flag, a, b);

      if (Q !== 5'b01010) begin
	 $display("FAILED -- Q=%b, flag=%b, a=%b", Q, flag, a);
	 $finish;
      end

      flag = 0;
      #1 if (Q !== 5'b00101) begin
	 $display("FAILED -- Q=%b, flag=%b, b=%b", Q, flag, b);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main;


   reg flag;
   reg [3:0] a, b;
   wire [4:0] Q = flag? a : b;

   initial begin
      flag = 1;
      a = 4'b1010;
      b = 4'b0101;

      #1 $display("%b = %b? %b : %b", Q, flag, a, b);

      if (Q !== 5'b01010) begin
	 $display("FAILED -- Q=%b, flag=%b, a=%b", Q, flag, a);
	 $finish;
      end

      flag = 0;
      #1 if (Q !== 5'b00101) begin
	 $display("FAILED -- Q=%b, flag=%b, b=%b", Q, flag, b);
	 $finish;
      end

      $display("PASSED");
   end

endmodule