data/full_repos/permissive/212947157/rtl/svga/PIXEL_GEN.v
1: b'%Warning-WIDTH: data/full_repos/permissive/212947157/rtl/svga/PIXEL_GEN.v:59: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n                                                                            : ... In instance PIXEL_GEN\n    if(graph_pixel[3:0]==3\'b110)\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/212947157/rtl/svga/PIXEL_GEN.v:95: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                            : ... In instance PIXEL_GEN\n   pixel_4p_1bit   <= 2\'b00;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/212947157/rtl/svga/PIXEL_GEN.v:152: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                             : ... In instance PIXEL_GEN\n    latched_2p_1bit_half_data <= pixel_code[3:0];  \n                              ^~\n%Error: Exiting due to 3 warning(s)\n'
module PIXEL_GEN(

	reset,

	pixel_code,
	graph_pixel,

	pixel_clock,

	pixel_8p_2bit,
	pixel_4p_2bit,
	pixel_4p_1bit,
	pixel_2p_1bit,
	pixel_2p_1bit_half
);


input				reset;

input	[7:0]		pixel_code;
input	[8:0]		graph_pixel;

input				pixel_clock;

output	reg	[1:0]	pixel_8p_2bit;
output	reg	[1:0]	pixel_4p_2bit;
output	reg			pixel_4p_1bit;
output	reg			pixel_2p_1bit;
output	reg			pixel_2p_1bit_half;

reg		[7:0]		latched_8p_2bit_data;
reg		[7:0]		latched_4p_2bit_data;
reg		[7:0]		latched_4p_1bit_data;
reg		[7:0]		latched_2p_1bit_data;


reg		[7:0]		latched_2p_1bit_half_data;










always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin
			pixel_8p_2bit			<=	2'b00;
			latched_8p_2bit_data	<=	8'h00;
		end
	else begin
		case(graph_pixel[4:0])
			5'b00101:
				latched_8p_2bit_data[7:0]	<=	pixel_code;
			default:
				if(graph_pixel[3:0]==3'b110)
					{pixel_8p_2bit,latched_8p_2bit_data[7:2]}	<=	latched_8p_2bit_data[7:0];
		endcase
		end

	end







always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin
			pixel_4p_2bit			<=	2'b00;
			latched_4p_2bit_data	<=	8'h00;
		end
	else begin
		case(graph_pixel[3:0])
			4'b0101:
				latched_4p_2bit_data[7:0]	<=	pixel_code;
			default:
				if(graph_pixel[1:0]==2'b10)
					{pixel_4p_2bit,latched_4p_2bit_data[7:2]}	<=	latched_4p_2bit_data[7:0];
		endcase
		end

	end



always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin
			pixel_4p_1bit			<=	2'b00;
			latched_4p_1bit_data	<=	8'h00;
		end
	else begin
		case(graph_pixel[4:0])
			5'b00101:
				latched_4p_1bit_data[7:0]	<=	pixel_code;
			default:
				if(graph_pixel[1:0]==2'b10)
					{pixel_4p_1bit,latched_4p_1bit_data[7:1]}	<=	latched_4p_1bit_data[7:0];
		endcase
		end

	end








always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
		begin
			pixel_2p_1bit			<=	1'b0;
			latched_2p_1bit_data	<=	8'h00;
		end
	else begin
		case(graph_pixel[3:0])
			4'b0101:
				latched_2p_1bit_data[7:0]	<=	pixel_code;
			default:
				if(graph_pixel[0]==1'b0)
					{pixel_2p_1bit,latched_2p_1bit_data[7:1]}	<=	latched_2p_1bit_data[7:0];
		endcase
		end

	end








always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
		begin
			pixel_2p_1bit_half			<=	1'b0;

			latched_2p_1bit_half_data	<=	8'h00;
		end
	else begin
		case(graph_pixel[2:0])
			3'b101:
				latched_2p_1bit_half_data	<=	pixel_code[3:0];
			default:


				if(graph_pixel[0]==1'b0)
					{pixel_2p_1bit_half,latched_2p_1bit_half_data[3:1]}	<=	latched_2p_1bit_half_data[3:0];
		endcase
		end

	end

endmodule
module PIXEL_GEN(

	reset,

	pixel_code,
	graph_pixel,

	pixel_clock,

	pixel_8p_2bit,
	pixel_4p_2bit,
	pixel_4p_1bit,
	pixel_2p_1bit,
	pixel_2p_1bit_half
);



input				reset;

input	[7:0]		pixel_code;
input	[8:0]		graph_pixel;

input				pixel_clock;

output	reg	[1:0]	pixel_8p_2bit;
output	reg	[1:0]	pixel_4p_2bit;
output	reg			pixel_4p_1bit;
output	reg			pixel_2p_1bit;
output	reg			pixel_2p_1bit_half;

reg		[7:0]		latched_8p_2bit_data;
reg		[7:0]		latched_4p_2bit_data;
reg		[7:0]		latched_4p_1bit_data;
reg		[7:0]		latched_2p_1bit_data;


reg		[7:0]		latched_2p_1bit_half_data;










always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin
			pixel_8p_2bit			<=	2'b00;
			latched_8p_2bit_data	<=	8'h00;
		end
	else begin
		case(graph_pixel[4:0])
			5'b00101:
				latched_8p_2bit_data[7:0]	<=	pixel_code;
			default:
				if(graph_pixel[3:0]==3'b110)
					{pixel_8p_2bit,latched_8p_2bit_data[7:2]}	<=	latched_8p_2bit_data[7:0];
		endcase
		end

	end







always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin
			pixel_4p_2bit			<=	2'b00;
			latched_4p_2bit_data	<=	8'h00;
		end
	else begin
		case(graph_pixel[3:0])
			4'b0101:
				latched_4p_2bit_data[7:0]	<=	pixel_code;
			default:
				if(graph_pixel[1:0]==2'b10)
					{pixel_4p_2bit,latched_4p_2bit_data[7:2]}	<=	latched_4p_2bit_data[7:0];
		endcase
		end

	end



always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
 		begin
			pixel_4p_1bit			<=	2'b00;
			latched_4p_1bit_data	<=	8'h00;
		end
	else begin
		case(graph_pixel[4:0])
			5'b00101:
				latched_4p_1bit_data[7:0]	<=	pixel_code;
			default:
				if(graph_pixel[1:0]==2'b10)
					{pixel_4p_1bit,latched_4p_1bit_data[7:1]}	<=	latched_4p_1bit_data[7:0];
		endcase
		end

	end








always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
		begin
			pixel_2p_1bit			<=	1'b0;
			latched_2p_1bit_data	<=	8'h00;
		end
	else begin
		case(graph_pixel[3:0])
			4'b0101:
				latched_2p_1bit_data[7:0]	<=	pixel_code;
			default:
				if(graph_pixel[0]==1'b0)
					{pixel_2p_1bit,latched_2p_1bit_data[7:1]}	<=	latched_2p_1bit_data[7:0];
		endcase
		end

	end








always @ (posedge pixel_clock or posedge reset) begin
	if (reset)
		begin
			pixel_2p_1bit_half			<=	1'b0;

			latched_2p_1bit_half_data	<=	8'h00;
		end
	else begin
		case(graph_pixel[2:0])
			3'b101:
				latched_2p_1bit_half_data	<=	pixel_code[3:0];
			default:


				if(graph_pixel[0]==1'b0)
					{pixel_2p_1bit_half,latched_2p_1bit_half_data[3:1]}	<=	latched_2p_1bit_half_data[3:0];
		endcase
		end

	end

endmodule