data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1/ccc1_0/ccc1_ccc1_0_FCCC.v
None: at end of input
1: b"%Error: data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1/ccc1_0/ccc1_ccc1_0_FCCC.v:16: Cannot find file containing module: 'VCC'\n    VCC vcc_inst (.Y(vcc_net));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1/ccc1_0,data/full_repos/permissive/153287529/VCC\n             data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1/ccc1_0,data/full_repos/permissive/153287529/VCC.v\n             data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1/ccc1_0,data/full_repos/permissive/153287529/VCC.sv\n             VCC\n             VCC.v\n             VCC.sv\n             obj_dir/VCC\n             obj_dir/VCC.v\n             obj_dir/VCC.sv\n%Error: data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1/ccc1_0/ccc1_ccc1_0_FCCC.v:17: Cannot find file containing module: 'GND'\n    GND gnd_inst (.Y(gnd_net));\n    ^~~\n%Error: data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1/ccc1_0/ccc1_ccc1_0_FCCC.v:18: Cannot find file containing module: 'CLKINT'\n    CLKINT GL0_INST (.A(GL0_net), .Y(GL0));\n    ^~~~~~\n%Error: data/full_repos/permissive/153287529/hardware/synthesis/igloo2PerfCreative/libero/component/work/ccc1/ccc1_0/ccc1_ccc1_0_FCCC.v:19: Cannot find file containing module: 'CCC'\n    CCC #( .INIT(210'h0000407F90000044D74000718C6318C2318C1DEC0404040403818)\n    ^~~\n%Error: Exiting due to 4 error(s)\n"
module ccc1_ccc1_0_FCCC(
       RCOSC_25_50MHZ,
       LOCK,
       GL0
    );
input  RCOSC_25_50MHZ;
output LOCK;
output GL0;

    wire gnd_net, vcc_net, GL0_net;
    
    VCC vcc_inst (.Y(vcc_net));
    GND gnd_inst (.Y(gnd_net));
    CLKINT GL0_INST (.A(GL0_net), .Y(GL0));
    CCC #( .INIT(210'h0000407F90000044D74000718C6318C2318C1DEC0404040403818)
        , .VCOFREQUENCY(912.000) )  CCC_INST (.Y0(), .Y1(), .Y2(), .Y3(
        ), .PRDATA({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .LOCK(
        LOCK), .BUSY(), .CLK0(vcc_net), .CLK1(vcc_net), .CLK2(vcc_net), 
        .CLK3(vcc_net), .NGMUX0_SEL(gnd_net), .NGMUX1_SEL(gnd_net), 
        .NGMUX2_SEL(gnd_net), .NGMUX3_SEL(gnd_net), .NGMUX0_HOLD_N(
        vcc_net), .NGMUX1_HOLD_N(vcc_net), .NGMUX2_HOLD_N(vcc_net), 
        .NGMUX3_HOLD_N(vcc_net), .NGMUX0_ARST_N(vcc_net), 
        .NGMUX1_ARST_N(vcc_net), .NGMUX2_ARST_N(vcc_net), 
        .NGMUX3_ARST_N(vcc_net), .PLL_BYPASS_N(vcc_net), .PLL_ARST_N(
        vcc_net), .PLL_POWERDOWN_N(vcc_net), .GPD0_ARST_N(vcc_net), 
        .GPD1_ARST_N(vcc_net), .GPD2_ARST_N(vcc_net), .GPD3_ARST_N(
        vcc_net), .PRESET_N(gnd_net), .PCLK(vcc_net), .PSEL(vcc_net), 
        .PENABLE(vcc_net), .PWRITE(vcc_net), .PADDR({vcc_net, vcc_net, 
        vcc_net, vcc_net, vcc_net, vcc_net}), .PWDATA({vcc_net, 
        vcc_net, vcc_net, vcc_net, vcc_net, vcc_net, vcc_net, vcc_net})
        , .CLK0_PAD(gnd_net), .CLK1_PAD(gnd_net), .CLK2_PAD(gnd_net), 
        .CLK3_PAD(gnd_net), .GL0(GL0_net), .GL1(), .GL2(), .GL3(), 
        .RCOSC_25_50MHZ(RCOSC_25_50MHZ), .RCOSC_1MHZ(gnd_net), .XTLOSC(
        gnd_net));
    
endmodule
module ccc1_ccc1_0_FCCC(
       RCOSC_25_50MHZ,
       LOCK,
       GL0
    );

input  RCOSC_25_50MHZ;
output LOCK;
output GL0;

    wire gnd_net, vcc_net, GL0_net;
    
    VCC vcc_inst (.Y(vcc_net));
    GND gnd_inst (.Y(gnd_net));
    CLKINT GL0_INST (.A(GL0_net), .Y(GL0));
    CCC #( .INIT(210'h0000407F90000044D74000718C6318C2318C1DEC0404040403818)
        , .VCOFREQUENCY(912.000) )  CCC_INST (.Y0(), .Y1(), .Y2(), .Y3(
        ), .PRDATA({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .LOCK(
        LOCK), .BUSY(), .CLK0(vcc_net), .CLK1(vcc_net), .CLK2(vcc_net), 
        .CLK3(vcc_net), .NGMUX0_SEL(gnd_net), .NGMUX1_SEL(gnd_net), 
        .NGMUX2_SEL(gnd_net), .NGMUX3_SEL(gnd_net), .NGMUX0_HOLD_N(
        vcc_net), .NGMUX1_HOLD_N(vcc_net), .NGMUX2_HOLD_N(vcc_net), 
        .NGMUX3_HOLD_N(vcc_net), .NGMUX0_ARST_N(vcc_net), 
        .NGMUX1_ARST_N(vcc_net), .NGMUX2_ARST_N(vcc_net), 
        .NGMUX3_ARST_N(vcc_net), .PLL_BYPASS_N(vcc_net), .PLL_ARST_N(
        vcc_net), .PLL_POWERDOWN_N(vcc_net), .GPD0_ARST_N(vcc_net), 
        .GPD1_ARST_N(vcc_net), .GPD2_ARST_N(vcc_net), .GPD3_ARST_N(
        vcc_net), .PRESET_N(gnd_net), .PCLK(vcc_net), .PSEL(vcc_net), 
        .PENABLE(vcc_net), .PWRITE(vcc_net), .PADDR({vcc_net, vcc_net, 
        vcc_net, vcc_net, vcc_net, vcc_net}), .PWDATA({vcc_net, 
        vcc_net, vcc_net, vcc_net, vcc_net, vcc_net, vcc_net, vcc_net})
        , .CLK0_PAD(gnd_net), .CLK1_PAD(gnd_net), .CLK2_PAD(gnd_net), 
        .CLK3_PAD(gnd_net), .GL0(GL0_net), .GL1(), .GL2(), .GL3(), 
        .RCOSC_25_50MHZ(RCOSC_25_50MHZ), .RCOSC_1MHZ(gnd_net), .XTLOSC(
        gnd_net));
    
endmodule