data/full_repos/permissive/210844779/lab2/2.5.1/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.5.1/tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.5.1/tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.5.1/tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.5.1/tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n#90\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.5.1/tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.5.1/tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n#90;\n^\n%Error: data/full_repos/permissive/210844779/lab2/2.5.1/tb.v:6: Cannot find file containing module: \'pipo\'\n  pipo u0(.d(d),.clk(clk),.load(load),.q(q));\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab2/2.5.1,data/full_repos/permissive/210844779/pipo\n             data/full_repos/permissive/210844779/lab2/2.5.1,data/full_repos/permissive/210844779/pipo.v\n             data/full_repos/permissive/210844779/lab2/2.5.1,data/full_repos/permissive/210844779/pipo.sv\n             pipo\n             pipo.v\n             pipo.sv\n             obj_dir/pipo\n             obj_dir/pipo.v\n             obj_dir/pipo.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  reg [7:0]d;
  reg clk,load;
  wire [7:0]q;
  
  pipo u0(.d(d),.clk(clk),.load(load),.q(q));
  
  always
begin
  clk=1'b0; 
  #5
  clk=1'b1; 
  #5;
end

initial
begin
load=1'b1;
d=8'b10011010;
#10

load=1'b0;
d=8'b10011010;
#90

load=1'b1;
d=8'b11010110;
#10

load=1'b0;
d=8'b10011010;
#90;

end

endmodule
module tb();

  reg [7:0]d;
  reg clk,load;
  wire [7:0]q;
  
  pipo u0(.d(d),.clk(clk),.load(load),.q(q));
  
  always
begin
  clk=1'b0; 
  #5
  clk=1'b1; 
  #5;
end

initial
begin
load=1'b1;
d=8'b10011010;
#10

load=1'b0;
d=8'b10011010;
#90

load=1'b1;
d=8'b11010110;
#10

load=1'b0;
d=8'b10011010;
#90;

end

endmodule