data/full_repos/permissive/177038316/project.v
1: b'%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:457: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'HUNDREDS\' generates 2 bits.\n                                                                  : ... In instance top.m3\n    case(HUNDREDS)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:344: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'data_y\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y - data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:344: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'data_x\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y - data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:349: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'data_y\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y + data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:349: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'data_x\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y + data_x;\n                  ^\n%Error: Exiting due to 5 warning(s)\n'
function [1:0] fsm_function;
		input [1:0] state;
		input [1:0] tn;
		case (state)
			hold: 
			if (tn == clear) begin
			fsm_function = clear;
			end else if (tn == load) begin 
			fsm_function = load;
			end else begin 
			fsm_function = hold;
			end
			load:
			if (tn == load) begin
			fsm_function = load;
			end else begin
			fsm_function = hold;
			end
			clear:
			if (tn == clear) begin
			fsm_function =  clear;
			end else begin
			fsm_function = hold;
			end
		endcase
	endfunction
function [1:0] fsm_function;

		input [1:0] state;
		input [1:0] tn;
		case (state)
			hold: 
			if (tn == clear) begin
			fsm_function = clear;
			end else if (tn == load) begin 
			fsm_function = load;
			end else begin 
			fsm_function = hold;
			end
			load:
			if (tn == load) begin
			fsm_function = load;
			end else begin
			fsm_function = hold;
			end
			clear:
			if (tn == clear) begin
			fsm_function =  clear;
			end else begin
			fsm_function = hold;
			end
		endcase
	endfunction