data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v
'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte
1: b'%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:2: Cannot find include file: const_defination.v\n`include "const_defination.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.v\n             data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new,data/full_repos/permissive/114882688/const_defination.v.sv\n             const_defination.v\n             const_defination.v.v\n             const_defination.v.sv\n             obj_dir/const_defination.v\n             obj_dir/const_defination.v.v\n             obj_dir/const_defination.v.sv\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:25: Define or directive not defined: \'`digitsBus\'\n    input wire [`digitsBus] ALUB,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`digitsBus] ALUB,\n                          ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:26: Define or directive not defined: \'`digitsBus\'\n    input wire[`digitsBus] ALUA,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[`digitsBus] valE,\n    ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:28: Define or directive not defined: \'`digitsBus\'\n    output reg[`digitsBus] valE,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:30: syntax error, unexpected \')\', expecting \',\' or \';\'\n    );\n    ^\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:34: syntax error, unexpected always\n    always@(*)\n    ^~~~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:38: Define or directive not defined: \'`ADD\'\n            `ADD:\n            ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:59: Define or directive not defined: \'`SUB\'\n            `SUB:\n            ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:88: Define or directive not defined: \'`AND\'\n            `AND:\n            ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:100: Define or directive not defined: \'`XOR\'\n            `XOR:\n            ^~~~\n%Error: data/full_repos/permissive/114882688/myY-86.srcs/sources_1/new/ALU.v:112: Define or directive not defined: \'`NO\'\n            `NO:\n            ^~~\n%Error: Exiting due to 13 error(s)\n'
module ALU(
    input wire [`digitsBus] ALUB,
    input wire[`digitsBus] ALUA,
    input wire[2:0] fun,
    output reg[`digitsBus] valE,
    output reg[2:0] cc
    );
    
    reg[64:0] temp;
    reg[64:0] tempin;
    always@(*)
    begin
    tempin=ALUB;
        case(fun)
            `ADD:
                begin
                    temp=ALUA+tempin;
                    valE=temp;
                    if(temp[64]==1)
                    begin
                        cc[1]=1'b1;
                    end
                    else
                    begin
                        cc[1]=1'b0;
                    end
					if(valE==0)
                    begin
                        cc[0]=1;
                    end
                    else
                    begin
                        cc[0]=0;
                    end
                end
            `SUB:
                begin
                    temp=tempin-ALUA;
                    valE=temp[63:0];
                    if(temp[64]==1)
                    begin
                        cc[1]=1'b1;
                    end
                    else
                    begin
                        cc[1]=1'b0;
                    end
                    if(temp[63]==1)
                    begin
                        cc[2]=1;
                    end
                    else
                    begin
                        cc[2]=0;
                    end
                    if(valE==0)
                    begin
                        cc[0]=1;
                    end
                    else
                    begin
                        cc[0]=0;
                    end
                end
            `AND:
                begin
                    valE=ALUA&ALUB;
					if(valE==0)
					begin
						cc[0]=1;
					end
					else
					begin
						cc[0]=0;
					end
                end 
            `XOR:
                begin
                    valE=ALUA^ALUB;
					if(valE==0)
					begin
						cc[0]=1;
					end
					else
					begin
						cc[0]=0;
					end
                end
            `NO:
                begin

                end
        endcase
    end
    
endmodule
module ALU(
    input wire [`digitsBus] ALUB,
    input wire[`digitsBus] ALUA,
    input wire[2:0] fun,
    output reg[`digitsBus] valE,
    output reg[2:0] cc
    );

    
    reg[64:0] temp;
    reg[64:0] tempin;
    always@(*)
    begin
    tempin=ALUB;
        case(fun)
            `ADD:
                begin
                    temp=ALUA+tempin;
                    valE=temp;
                    if(temp[64]==1)
                    begin
                        cc[1]=1'b1;
                    end
                    else
                    begin
                        cc[1]=1'b0;
                    end
					if(valE==0)
                    begin
                        cc[0]=1;
                    end
                    else
                    begin
                        cc[0]=0;
                    end
                end
            `SUB:
                begin
                    temp=tempin-ALUA;
                    valE=temp[63:0];
                    if(temp[64]==1)
                    begin
                        cc[1]=1'b1;
                    end
                    else
                    begin
                        cc[1]=1'b0;
                    end
                    if(temp[63]==1)
                    begin
                        cc[2]=1;
                    end
                    else
                    begin
                        cc[2]=0;
                    end
                    if(valE==0)
                    begin
                        cc[0]=1;
                    end
                    else
                    begin
                        cc[0]=0;
                    end
                end
            `AND:
                begin
                    valE=ALUA&ALUB;
					if(valE==0)
					begin
						cc[0]=1;
					end
					else
					begin
						cc[0]=0;
					end
                end 
            `XOR:
                begin
                    valE=ALUA^ALUB;
					if(valE==0)
					begin
						cc[0]=1;
					end
					else
					begin
						cc[0]=0;
					end
                end
            `NO:
                begin

                end
        endcase
    end
    
endmodule