data/full_repos/permissive/187705377/Camera Reduced/audio.v
1: b'%Error: Cannot find file containing module: Reduced,data/full_repos/permissive/187705377\n        ... Looked in:\n             data/full_repos/permissive/187705377/Camera/Reduced,data/full_repos/permissive/187705377\n             data/full_repos/permissive/187705377/Camera/Reduced,data/full_repos/permissive/187705377.v\n             data/full_repos/permissive/187705377/Camera/Reduced,data/full_repos/permissive/187705377.sv\n             Reduced,data/full_repos/permissive/187705377\n             Reduced,data/full_repos/permissive/187705377.v\n             Reduced,data/full_repos/permissive/187705377.sv\n             obj_dir/Reduced,data/full_repos/permissive/187705377\n             obj_dir/Reduced,data/full_repos/permissive/187705377.v\n             obj_dir/Reduced,data/full_repos/permissive/187705377.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/187705377/Camera\n%Error: Cannot find file containing module: Reduced/audio.v\n%Error: Exiting due to 3 error(s)\n'
module audio (CLOCK_50, CLOCK2_50, KEY, SW, FPGA_I2C_SCLK, FPGA_I2C_SDAT, AUD_XCK, 
		        AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK, AUD_ADCDAT, AUD_DACDAT);

	input CLOCK_50, CLOCK2_50;
	input [0:0] KEY;
	input [8:0] SW;

	output FPGA_I2C_SCLK;
	inout FPGA_I2C_SDAT;

	output AUD_XCK;
	input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK;
	input AUD_ADCDAT;
	output AUD_DACDAT;

	
	reg read_ready, write_ready, read, write;
	reg [23:0] readdata_left, readdata_right;
	wire [23:0] writedata_left, writedata_right;
	
	always begin 
		if(write_ready && read_ready) begin
			writedata_left = readdata_left;
			writedata_right = readdata_right;
			write = 1'b1;
			read  = 1'b1;
		end else begin
			writedata_left = 0;
			writedata_right = 0;
			write = 1'b0;
			read  = 1'b0;
		end
	end










































































	clock_generator my_clock_gen(

		CLOCK2_50,
		reset,


		AUD_XCK
	);

	audio_and_video_config cfg(

		CLOCK_50,
		reset,


		FPGA_I2C_SDAT,
		FPGA_I2C_SCLK
	);

	audio_codec codec(

		CLOCK_50,
		reset,

		read,	write,
		writedata_left, writedata_right,

		AUD_ADCDAT,


		AUD_BCLK,
		AUD_ADCLRCK,
		AUD_DACLRCK,


		read_ready, write_ready,
		readdata_left, readdata_right,
		AUD_DACDAT
	);

endmodule
module audio (CLOCK_50, CLOCK2_50, KEY, SW, FPGA_I2C_SCLK, FPGA_I2C_SDAT, AUD_XCK, 
		        AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK, AUD_ADCDAT, AUD_DACDAT);


	input CLOCK_50, CLOCK2_50;
	input [0:0] KEY;
	input [8:0] SW;

	output FPGA_I2C_SCLK;
	inout FPGA_I2C_SDAT;

	output AUD_XCK;
	input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK;
	input AUD_ADCDAT;
	output AUD_DACDAT;

	
	reg read_ready, write_ready, read, write;
	reg [23:0] readdata_left, readdata_right;
	wire [23:0] writedata_left, writedata_right;
	
	always begin 
		if(write_ready && read_ready) begin
			writedata_left = readdata_left;
			writedata_right = readdata_right;
			write = 1'b1;
			read  = 1'b1;
		end else begin
			writedata_left = 0;
			writedata_right = 0;
			write = 1'b0;
			read  = 1'b0;
		end
	end










































































	clock_generator my_clock_gen(

		CLOCK2_50,
		reset,


		AUD_XCK
	);

	audio_and_video_config cfg(

		CLOCK_50,
		reset,


		FPGA_I2C_SDAT,
		FPGA_I2C_SCLK
	);

	audio_codec codec(

		CLOCK_50,
		reset,

		read,	write,
		writedata_left, writedata_right,

		AUD_ADCDAT,


		AUD_BCLK,
		AUD_ADCLRCK,
		AUD_DACLRCK,


		read_ready, write_ready,
		readdata_left, readdata_right,
		AUD_DACDAT
	);

endmodule