data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v
None: at end of input
1: b'%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:1: Cannot find include file: vga_config.inc\n`include "vga_config.inc" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic,data/full_repos/permissive/130996185/vga_config.inc\n             data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic,data/full_repos/permissive/130996185/vga_config.inc.v\n             data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic,data/full_repos/permissive/130996185/vga_config.inc.sv\n             vga_config.inc\n             vga_config.inc.v\n             vga_config.inc.sv\n             obj_dir/vga_config.inc\n             obj_dir/vga_config.inc.v\n             obj_dir/vga_config.inc.sv\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:84: Define or directive not defined: \'`VGA_V_BIAS\'\n  ADV7513_DATA_REQ <= (ADV7513_VCnt>=(`VGA_V_BIAS) && ADV7513_VCnt<(`VGA_V_BIAS + `VGA_V_WIDTH) && ADV7513_HCnt>=(`VGA_H_BIAS) && ADV7513_HCnt<(`VGA_H_BIAS + `VGA_H_WIDTH ));\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  ADV7513_DATA_REQ <= (ADV7513_VCnt>=(`VGA_V_BIAS) && ADV7513_VCnt<(`VGA_V_BIAS + `VGA_V_WIDTH) && ADV7513_HCnt>=(`VGA_H_BIAS) && ADV7513_HCnt<(`VGA_H_BIAS + `VGA_H_WIDTH ));\n                                                 ^\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:84: Define or directive not defined: \'`VGA_V_BIAS\'\n  ADV7513_DATA_REQ <= (ADV7513_VCnt>=(`VGA_V_BIAS) && ADV7513_VCnt<(`VGA_V_BIAS + `VGA_V_WIDTH) && ADV7513_HCnt>=(`VGA_H_BIAS) && ADV7513_HCnt<(`VGA_H_BIAS + `VGA_H_WIDTH ));\n                                                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:84: Define or directive not defined: \'`VGA_V_WIDTH\'\n  ADV7513_DATA_REQ <= (ADV7513_VCnt>=(`VGA_V_BIAS) && ADV7513_VCnt<(`VGA_V_BIAS + `VGA_V_WIDTH) && ADV7513_HCnt>=(`VGA_H_BIAS) && ADV7513_HCnt<(`VGA_H_BIAS + `VGA_H_WIDTH ));\n                                                                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:84: Define or directive not defined: \'`VGA_H_BIAS\'\n  ADV7513_DATA_REQ <= (ADV7513_VCnt>=(`VGA_V_BIAS) && ADV7513_VCnt<(`VGA_V_BIAS + `VGA_V_WIDTH) && ADV7513_HCnt>=(`VGA_H_BIAS) && ADV7513_HCnt<(`VGA_H_BIAS + `VGA_H_WIDTH ));\n                                                                                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:84: Define or directive not defined: \'`VGA_H_BIAS\'\n  ADV7513_DATA_REQ <= (ADV7513_VCnt>=(`VGA_V_BIAS) && ADV7513_VCnt<(`VGA_V_BIAS + `VGA_V_WIDTH) && ADV7513_HCnt>=(`VGA_H_BIAS) && ADV7513_HCnt<(`VGA_H_BIAS + `VGA_H_WIDTH ));\n                                                                                                                                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:84: Define or directive not defined: \'`VGA_H_WIDTH\'\n  ADV7513_DATA_REQ <= (ADV7513_VCnt>=(`VGA_V_BIAS) && ADV7513_VCnt<(`VGA_V_BIAS + `VGA_V_WIDTH) && ADV7513_HCnt>=(`VGA_H_BIAS) && ADV7513_HCnt<(`VGA_H_BIAS + `VGA_H_WIDTH ));\n                                                                                                                                                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:90: Define or directive not defined: \'`VGA_V_BIAS\'\n wire  IN_ZONE_0 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && \n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:90: Define or directive not defined: \'`VGA_V_BORD\'\n wire  IN_ZONE_0 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && \n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:90: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire  IN_ZONE_0 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                          ^\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:90: Define or directive not defined: \'`VGA_V_BIAS\'\n wire  IN_ZONE_0 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:90: Define or directive not defined: \'`VGA_V_BORD\'\n wire  IN_ZONE_0 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:90: Define or directive not defined: \'`VGA_V_LENG\'\n wire  IN_ZONE_0 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:91: Define or directive not defined: \'`VGA_H_BIAS\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:91: Define or directive not defined: \'`VGA_H_BORD\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:91: Define or directive not defined: \'`VGA_H_BIAS\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))\n                                                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:91: Define or directive not defined: \'`VGA_H_BORD\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))\n                                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:91: Define or directive not defined: \'`VGA_H_LENG\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))\n                                                                                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:93: Define or directive not defined: \'`VGA_V_BIAS\'\n wire  IN_ZONE_1 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && \n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:93: Define or directive not defined: \'`VGA_V_BORD\'\n wire  IN_ZONE_1 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && \n                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:93: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire  IN_ZONE_1 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                          ^\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:93: Define or directive not defined: \'`VGA_V_BIAS\'\n wire  IN_ZONE_1 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:93: Define or directive not defined: \'`VGA_V_BORD\'\n wire  IN_ZONE_1 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:93: Define or directive not defined: \'`VGA_V_LENG\'\n wire  IN_ZONE_1 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:94: Define or directive not defined: \'`VGA_H_BIAS\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD+`VGA_H_LENG))\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:94: Define or directive not defined: \'`VGA_H_WIDTH\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD+`VGA_H_LENG))\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:94: Define or directive not defined: \'`VGA_H_BORD\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD+`VGA_H_LENG))\n                                                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:94: Define or directive not defined: \'`VGA_H_BIAS\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD+`VGA_H_LENG))\n                                                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:94: Define or directive not defined: \'`VGA_H_WIDTH\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD+`VGA_H_LENG))\n                                                                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:94: Define or directive not defined: \'`VGA_H_BORD\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD+`VGA_H_LENG))\n                                                                                                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:94: Define or directive not defined: \'`VGA_H_LENG\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD+`VGA_H_LENG))\n                                                                                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:96: Define or directive not defined: \'`VGA_V_BIAS\'\n wire  IN_ZONE_2 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:96: Define or directive not defined: \'`VGA_V_WIDTH\'\n wire  IN_ZONE_2 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:96: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\n wire  IN_ZONE_2 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                            ^~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:96: Define or directive not defined: \'`VGA_V_BORD\'\n wire  IN_ZONE_2 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:96: Define or directive not defined: \'`VGA_V_BIAS\'\n wire  IN_ZONE_2 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                                               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:96: Define or directive not defined: \'`VGA_V_WIDTH\'\n wire  IN_ZONE_2 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:96: Define or directive not defined: \'`VGA_V_BORD\'\n wire  IN_ZONE_2 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:96: Define or directive not defined: \'`VGA_V_LENG\'\n wire  IN_ZONE_2 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                                                                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:97: Define or directive not defined: \'`VGA_H_BIAS\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:97: Define or directive not defined: \'`VGA_H_BORD\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:97: Define or directive not defined: \'`VGA_H_BIAS\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))\n                                                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:97: Define or directive not defined: \'`VGA_H_BORD\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))\n                                                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:97: Define or directive not defined: \'`VGA_H_LENG\'\n       (ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))\n                                                                                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:99: Define or directive not defined: \'`VGA_V_BIAS\'\n wire  IN_ZONE_3 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:99: Define or directive not defined: \'`VGA_V_WIDTH\'\n wire  IN_ZONE_3 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:99: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\n wire  IN_ZONE_3 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                            ^~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:99: Define or directive not defined: \'`VGA_V_BORD\'\n wire  IN_ZONE_3 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/130996185/projects/zFPGA_DE10_NANO_SoC/00_user_logic/adv7513_controller.v:99: Define or directive not defined: \'`VGA_V_BIAS\'\n wire  IN_ZONE_3 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && \n                                                                                               ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module adv7513_controller(
	ADV7513_PCLK, RESETN,
	ADV7513_R, ADV7513_G, ADV7513_B, 
	ADV7513_HSYNC,
	ADV7513_VSYNC,
	ADV7513_BLANK_N,
	ADV7513_VCnt,
	ADV7513_HCnt,
	ADV7513_DATA,
	ADV7513_DATA_REQ,
	ADV7513_FRAME_NEW_EN,
	ADV7513_DE,
	ACTION_WORD,
	ACTION_TITLE,
	SW
	);
	
	input	ADV7513_PCLK,RESETN;
	output	reg	[4:0]	ADV7513_R;
	output	reg	[5:0]	ADV7513_G;
	output	reg	[4:0]	ADV7513_B;
	output	ADV7513_HSYNC,ADV7513_VSYNC;
	output	ADV7513_BLANK_N;
	input	[3:0]		SW;

	output	reg				ADV7513_DATA_REQ, ADV7513_DE;
	output	reg				ADV7513_FRAME_NEW_EN;
	
	output	reg		[10:0]	ADV7513_HCnt;
	output	reg		[10:0]	ADV7513_VCnt;
	input			[15:0]	ADV7513_DATA;
	input			[15:0]	ACTION_WORD;
	input			[15:0]	ACTION_TITLE;


	parameter 	HA = 11'D640;
	parameter 	HF = 11'D16;
	parameter	HS = 11'D96;
	parameter	HB = 11'D48;
	parameter 	HT = (HA+HF+HS+HB);
	parameter 	VA = 11'D480;
	parameter 	VF = 11'D1;
	parameter	VS = 11'D3;
	parameter	VB = 11'D16;
	parameter	VT = (VA+VF+VS+VB);

	always @(posedge ADV7513_PCLK)	
		if(!RESETN)
		begin
			ADV7513_HCnt <= 0;
			ADV7513_VCnt <= 0;
		end
		else if(ADV7513_HCnt>=(HT-1))
		begin
			ADV7513_HCnt <= 0;
			if(ADV7513_VCnt>=(VT-1))
			begin
				ADV7513_VCnt <= 0;
			end
			else
				ADV7513_VCnt <= ADV7513_VCnt + 1;
		end
		else
			ADV7513_HCnt <= ADV7513_HCnt + 1;

	assign	ADV7513_HSYNC = (ADV7513_HCnt>=(HA+HF) && (ADV7513_HCnt<(HA+HF+HS)));
	assign	ADV7513_VSYNC = (ADV7513_VCnt>=(VA+VF) && (ADV7513_VCnt<(VA+VF+VS)));
	assign	ADV7513_BLANK_N = ~(((ADV7513_HCnt>=HA)&&(ADV7513_HCnt<HT))||(ADV7513_VCnt>=VA)&&(ADV7513_VCnt<VT));


	always @(posedge ADV7513_PCLK)
	begin
		ADV7513_FRAME_NEW_EN <= (ADV7513_VCnt>=(VA+1)) && (ADV7513_HCnt==(HA+1));
		ADV7513_DATA_REQ <= (ADV7513_VCnt>=(`VGA_V_BIAS) && ADV7513_VCnt<(`VGA_V_BIAS + `VGA_V_WIDTH) && ADV7513_HCnt>=(`VGA_H_BIAS) && ADV7513_HCnt<(`VGA_H_BIAS + `VGA_H_WIDTH ));

		ADV7513_DE <= (ADV7513_VCnt<VA && ADV7513_HCnt<HA);
	end
	

	wire 	IN_ZONE_0 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && 
							(ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))
						);
	wire 	IN_ZONE_1 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && 
							(ADV7513_HCnt>(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD+`VGA_H_LENG))
						);
	wire 	IN_ZONE_2 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && 
							(ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))
						);
	wire 	IN_ZONE_3 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && 
							(ADV7513_HCnt>(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD+`VGA_H_LENG))
						);
	wire	IN_BORDER_ZONE = (!IN_ZONE_0 && !IN_ZONE_1 && !IN_ZONE_2 && !IN_ZONE_3);


	always @(posedge ADV7513_PCLK)

		if(SW[1])	
		begin
			if((ADV7513_VCnt<VA && ADV7513_HCnt<HA))
			begin

				if(ADV7513_HCnt<(HA >> 2))
					{ADV7513_R, ADV7513_G, ADV7513_B} <= {5'H1F, 6'H00, 5'H00};

				else if(ADV7513_HCnt>=(HA >> 2) && ADV7513_HCnt<(HA >> 1))
					{ADV7513_R, ADV7513_G, ADV7513_B} <= {5'H00, 6'H3F, 5'H00};

				else if(ADV7513_HCnt>=(HA >> 1) && ADV7513_HCnt<(HA >> 2)*3)
					{ADV7513_R, ADV7513_G, ADV7513_B} <= {5'H00, 6'H00, 5'H1F};

				else
					{ADV7513_R, ADV7513_G, ADV7513_B} <= 16'HFFFF;
			end
			else
				{ADV7513_R, ADV7513_G, ADV7513_B} <= 16'H0000;
		end		
		else
		begin
			{ADV7513_R, ADV7513_G, ADV7513_B} <= 	(ADV7513_VCnt>=`TITLE_V_BIAS && ADV7513_VCnt<(`TITLE_V_BIAS+`TITLE_V_WIDTH) && ADV7513_HCnt>=(`TITLE_H_BIAS) && ADV7513_HCnt<(`TITLE_H_BIAS + `TITLE_H_WIDTH ))? 
														ACTION_TITLE : 
													(ADV7513_VCnt>=`WORD_V_BIAS && ADV7513_VCnt<(`WORD_V_BIAS+`WORD_V_WIDTH) && ADV7513_HCnt>=(`WORD_H_BIAS) && ADV7513_HCnt<(`WORD_H_BIAS + `WORD_H_WIDTH ))? 
														ACTION_WORD : 
													(ADV7513_VCnt>=(`VGA_V_BIAS) && ADV7513_VCnt<(`VGA_V_BIAS + `VGA_V_WIDTH) && ADV7513_HCnt>=(`VGA_H_BIAS) && ADV7513_HCnt<(`VGA_H_BIAS + `VGA_H_WIDTH ))? 
														(IN_BORDER_ZONE? 16'HFFFF : ADV7513_DATA): 
													(ADV7513_VCnt<VA && ADV7513_HCnt<HA)? 16'HFFFF : 16'H0000;
		end
endmodule
module adv7513_controller(
	ADV7513_PCLK, RESETN,
	ADV7513_R, ADV7513_G, ADV7513_B, 
	ADV7513_HSYNC,
	ADV7513_VSYNC,
	ADV7513_BLANK_N,
	ADV7513_VCnt,
	ADV7513_HCnt,
	ADV7513_DATA,
	ADV7513_DATA_REQ,
	ADV7513_FRAME_NEW_EN,
	ADV7513_DE,
	ACTION_WORD,
	ACTION_TITLE,
	SW
	);

	
	input	ADV7513_PCLK,RESETN;
	output	reg	[4:0]	ADV7513_R;
	output	reg	[5:0]	ADV7513_G;
	output	reg	[4:0]	ADV7513_B;
	output	ADV7513_HSYNC,ADV7513_VSYNC;
	output	ADV7513_BLANK_N;
	input	[3:0]		SW;

	output	reg				ADV7513_DATA_REQ, ADV7513_DE;
	output	reg				ADV7513_FRAME_NEW_EN;
	
	output	reg		[10:0]	ADV7513_HCnt;
	output	reg		[10:0]	ADV7513_VCnt;
	input			[15:0]	ADV7513_DATA;
	input			[15:0]	ACTION_WORD;
	input			[15:0]	ACTION_TITLE;


	parameter 	HA = 11'D640;
	parameter 	HF = 11'D16;
	parameter	HS = 11'D96;
	parameter	HB = 11'D48;
	parameter 	HT = (HA+HF+HS+HB);
	parameter 	VA = 11'D480;
	parameter 	VF = 11'D1;
	parameter	VS = 11'D3;
	parameter	VB = 11'D16;
	parameter	VT = (VA+VF+VS+VB);

	always @(posedge ADV7513_PCLK)	
		if(!RESETN)
		begin
			ADV7513_HCnt <= 0;
			ADV7513_VCnt <= 0;
		end
		else if(ADV7513_HCnt>=(HT-1))
		begin
			ADV7513_HCnt <= 0;
			if(ADV7513_VCnt>=(VT-1))
			begin
				ADV7513_VCnt <= 0;
			end
			else
				ADV7513_VCnt <= ADV7513_VCnt + 1;
		end
		else
			ADV7513_HCnt <= ADV7513_HCnt + 1;

	assign	ADV7513_HSYNC = (ADV7513_HCnt>=(HA+HF) && (ADV7513_HCnt<(HA+HF+HS)));
	assign	ADV7513_VSYNC = (ADV7513_VCnt>=(VA+VF) && (ADV7513_VCnt<(VA+VF+VS)));
	assign	ADV7513_BLANK_N = ~(((ADV7513_HCnt>=HA)&&(ADV7513_HCnt<HT))||(ADV7513_VCnt>=VA)&&(ADV7513_VCnt<VT));


	always @(posedge ADV7513_PCLK)
	begin
		ADV7513_FRAME_NEW_EN <= (ADV7513_VCnt>=(VA+1)) && (ADV7513_HCnt==(HA+1));
		ADV7513_DATA_REQ <= (ADV7513_VCnt>=(`VGA_V_BIAS) && ADV7513_VCnt<(`VGA_V_BIAS + `VGA_V_WIDTH) && ADV7513_HCnt>=(`VGA_H_BIAS) && ADV7513_HCnt<(`VGA_H_BIAS + `VGA_H_WIDTH ));

		ADV7513_DE <= (ADV7513_VCnt<VA && ADV7513_HCnt<HA);
	end
	

	wire 	IN_ZONE_0 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && 
							(ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))
						);
	wire 	IN_ZONE_1 = ((ADV7513_VCnt>(`VGA_V_BIAS+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+`VGA_V_BORD+`VGA_V_LENG)) && 
							(ADV7513_HCnt>(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD+`VGA_H_LENG))
						);
	wire 	IN_ZONE_2 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && 
							(ADV7513_HCnt>(`VGA_H_BIAS+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+`VGA_H_BORD+`VGA_H_LENG))
						);
	wire 	IN_ZONE_3 = ((ADV7513_VCnt>(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD) && ADV7513_VCnt<(`VGA_V_BIAS+(`VGA_V_WIDTH>>1)+`VGA_V_BORD+`VGA_V_LENG)) && 
							(ADV7513_HCnt>(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD) && ADV7513_HCnt<(`VGA_H_BIAS+(`VGA_H_WIDTH>>1)+`VGA_H_BORD+`VGA_H_LENG))
						);
	wire	IN_BORDER_ZONE = (!IN_ZONE_0 && !IN_ZONE_1 && !IN_ZONE_2 && !IN_ZONE_3);


	always @(posedge ADV7513_PCLK)

		if(SW[1])	
		begin
			if((ADV7513_VCnt<VA && ADV7513_HCnt<HA))
			begin

				if(ADV7513_HCnt<(HA >> 2))
					{ADV7513_R, ADV7513_G, ADV7513_B} <= {5'H1F, 6'H00, 5'H00};

				else if(ADV7513_HCnt>=(HA >> 2) && ADV7513_HCnt<(HA >> 1))
					{ADV7513_R, ADV7513_G, ADV7513_B} <= {5'H00, 6'H3F, 5'H00};

				else if(ADV7513_HCnt>=(HA >> 1) && ADV7513_HCnt<(HA >> 2)*3)
					{ADV7513_R, ADV7513_G, ADV7513_B} <= {5'H00, 6'H00, 5'H1F};

				else
					{ADV7513_R, ADV7513_G, ADV7513_B} <= 16'HFFFF;
			end
			else
				{ADV7513_R, ADV7513_G, ADV7513_B} <= 16'H0000;
		end		
		else
		begin
			{ADV7513_R, ADV7513_G, ADV7513_B} <= 	(ADV7513_VCnt>=`TITLE_V_BIAS && ADV7513_VCnt<(`TITLE_V_BIAS+`TITLE_V_WIDTH) && ADV7513_HCnt>=(`TITLE_H_BIAS) && ADV7513_HCnt<(`TITLE_H_BIAS + `TITLE_H_WIDTH ))? 
														ACTION_TITLE : 
													(ADV7513_VCnt>=`WORD_V_BIAS && ADV7513_VCnt<(`WORD_V_BIAS+`WORD_V_WIDTH) && ADV7513_HCnt>=(`WORD_H_BIAS) && ADV7513_HCnt<(`WORD_H_BIAS + `WORD_H_WIDTH ))? 
														ACTION_WORD : 
													(ADV7513_VCnt>=(`VGA_V_BIAS) && ADV7513_VCnt<(`VGA_V_BIAS + `VGA_V_WIDTH) && ADV7513_HCnt>=(`VGA_H_BIAS) && ADV7513_HCnt<(`VGA_H_BIAS + `VGA_H_WIDTH ))? 
														(IN_BORDER_ZONE? 16'HFFFF : ADV7513_DATA): 
													(ADV7513_VCnt<VA && ADV7513_HCnt<HA)? 16'HFFFF : 16'H0000;
		end
endmodule