data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_mux.v
 line:44: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_mux.v:44: Unsupported: Ignoring delay on this delayed statement.\n#10000000 $stop;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_mux.v:47: Unsupported: Ignoring delay on this delayed statement.\n#n sel=~sel;\n^\n%Warning-STMTDLY: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_mux.v:52: Unsupported: Ignoring delay on this delayed statement.\n#(2*n)\n^\n%Warning-STMTDLY: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_mux.v:55: Unsupported: Ignoring delay on this delayed statement.\n#(2*n)\n^\n%Warning-STMTDLY: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_mux.v:58: Unsupported: Ignoring delay on this delayed statement.\n#(2*n)\n^\n%Error: data/full_repos/permissive/219219909/3-parallel_Data_Shuffler/test_mux.v:36: Cannot find file containing module: \'mux_2x1\'\n mux_2x1 uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/219219909/3-parallel_Data_Shuffler,data/full_repos/permissive/219219909/mux_2x1\n             data/full_repos/permissive/219219909/3-parallel_Data_Shuffler,data/full_repos/permissive/219219909/mux_2x1.v\n             data/full_repos/permissive/219219909/3-parallel_Data_Shuffler,data/full_repos/permissive/219219909/mux_2x1.sv\n             mux_2x1\n             mux_2x1.v\n             mux_2x1.sv\n             obj_dir/mux_2x1\n             obj_dir/mux_2x1.v\n             obj_dir/mux_2x1.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_mux;
parameter n=5;

	reg [31:0] data0;
	reg [31:0] data1;
	reg sel;


	wire [31:0] data_out;


	mux_2x1 uut (
		.data0(data0), 
		.data1(data1), 
		.sel(sel), 
		.data_out(data_out)
	);
initial begin
      sel=0;
#10000000 $stop;
end
always begin
#n sel=~sel;
end
	initial begin
			data0=32'h00000001;
data1=32'h00000002;		
#(2*n)
data0=32'h00000003;
data1=32'h00000004;
#(2*n)
data0=32'h00000005;
data1=32'h00000006;
#(2*n)
data0=32'h00000007;
data1=32'h00000008;

	end
      
endmodule
module test_mux;

parameter n=5;

	reg [31:0] data0;
	reg [31:0] data1;
	reg sel;


	wire [31:0] data_out;


	mux_2x1 uut (
		.data0(data0), 
		.data1(data1), 
		.sel(sel), 
		.data_out(data_out)
	);
initial begin
      sel=0;
#10000000 $stop;
end
always begin
#n sel=~sel;
end
	initial begin
			data0=32'h00000001;
data1=32'h00000002;		
#(2*n)
data0=32'h00000003;
data1=32'h00000004;
#(2*n)
data0=32'h00000005;
data1=32'h00000006;
#(2*n)
data0=32'h00000007;
data1=32'h00000008;

	end
      
endmodule