data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/RAMTester/XEM6010-Verilog/Simulation/test_okhi/test_tf.v
 line:152: before: ")"
1: b'%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/RAMTester/XEM6010-Verilog/Simulation/test_okhi/test_tf.v:272: Cannot find include file: ./oksim/okHostCalls.v\n `include "./oksim/okHostCalls.v" \n          ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/RAMTester/XEM6010-Verilog/Simulation/test_okhi,data/full_repos/permissive/120539939/./oksim/okHostCalls.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/RAMTester/XEM6010-Verilog/Simulation/test_okhi,data/full_repos/permissive/120539939/./oksim/okHostCalls.v.v\n             data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/RAMTester/XEM6010-Verilog/Simulation/test_okhi,data/full_repos/permissive/120539939/./oksim/okHostCalls.v.sv\n             ./oksim/okHostCalls.v\n             ./oksim/okHostCalls.v.v\n             ./oksim/okHostCalls.v.sv\n             obj_dir/./oksim/okHostCalls.v\n             obj_dir/./oksim/okHostCalls.v.v\n             obj_dir/./oksim/okHostCalls.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/RAMTester/XEM6010-Verilog/Simulation/test_okhi/test_tf.v:209: Unsupported: Ignoring delay on this delayed statement.\n always #(tCLK/2.0) clk1 = ~clk1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/RAMTester/XEM6010-Verilog/Simulation/test_okhi/test_tf.v:224: Unsupported: wait statements\n  wait (tf.dut.c3_calib_done == 1\'b1);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/120539939/FrontPanel/ubuntu16.04/Samples/RAMTester/XEM6010-Verilog/Simulation/test_okhi/test_tf.v:245: Unsupported: Ignoring delay on this delayed statement.\n  #10000;\n  ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module tf;



	parameter DEBUG_EN              = 0;                                                                     
	parameter C3_MEMCLK_PERIOD     = 3200;                                                                   
	parameter C3_RST_ACT_LOW        = 0;                                                                     
	parameter C3_INPUT_CLK_TYPE     = "DIFFERENTIAL";                                                        
	parameter C3_NUM_DQ_PINS        = 16;                                                                    
	parameter C3_MEM_ADDR_WIDTH     = 13;                                                                    
	parameter C3_MEM_BANKADDR_WIDTH = 3;                                                                     
	parameter C3_MEM_ADDR_ORDER     = "ROW_BANK_COLUMN";                                                     
	parameter C3_P0_MASK_SIZE       = 4;                                                                     
	parameter C3_P0_DATA_PORT_SIZE  = 32;                                                                    
	parameter C3_P1_MASK_SIZE       = 4;                                                                     
	parameter C3_P1_DATA_PORT_SIZE  = 32;                                                                    
	parameter C3_MEM_BURST_LEN	  = 4;                                                                       
	parameter C3_MEM_NUM_COL_BITS   = 10;                                                                    
	parameter C3_CALIB_SOFT_IP      = "FALSE";
	parameter C3_SIMULATION      = "TRUE";                                                                   
	parameter C3_HW_TESTING      = "FALSE";                                                                  
	localparam C3_p0_BEGIN_ADDRESS                   = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;
	localparam C3_p0_DATA_MODE                       = 4'b0010;                                              
	localparam C3_p0_END_ADDRESS                     = (C3_HW_TESTING == "TRUE") ? 32'h02ffffff:32'h000002ff;     
	localparam C3_p0_PRBS_EADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'hfc000000:32'hfffffc00;
	localparam C3_p0_PRBS_SADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;
	





	reg  [7:0]  hi_in;
	wire [1:0]  hi_out;
	wire [15:0] hi_inout;
	wire        hi_aa;
	
	wire        i2c_sda;
	wire        i2c_scl;
	wire        hi_muxsel;
	
	wire [7:0]  led;
	

	reg         clk1;
	

	wire [C3_NUM_DQ_PINS-1:0]           mcb3_dram_dq;
	wire [C3_MEM_ADDR_WIDTH-1:0]        mcb3_dram_a;
	wire [C3_MEM_BANKADDR_WIDTH-1:0]    mcb3_dram_ba;
	wire                                mcb3_dram_ras_n;
	wire                                mcb3_dram_cas_n;
	wire                                mcb3_dram_we_n;
	wire                                mcb3_dram_odt;
	wire                                mcb3_dram_cke;
	wire                                mcb3_dram_dm;
	wire                                mcb3_dram_udqs;
	wire                                mcb3_dram_udqs_n;
	wire                                mcb3_rzq;
	wire                                mcb3_zio;
	wire                                mcb3_dram_udm;
	wire                                mcb3_dram_dqs;
	wire                                mcb3_dram_dqs_n;
	wire                                mcb3_dram_ck;
	wire                                mcb3_dram_ck_n;
	wire                                mcb3_dram_cs_n;
	


	PULLDOWN zio_pulldown3 (.O(mcb3_zio));
	PULLDOWN rzq_pulldown3 (.O(mcb3_rzq));
	




	generate
	if(C3_NUM_DQ_PINS == 16) begin : MEM_INST3
		ddr2_model_c3 u_mem_c3(
		.ck         (mcb3_dram_ck),
		.ck_n       (mcb3_dram_ck_n),
		.cke        (mcb3_dram_cke),
		.cs_n       (1'b0),
		.ras_n      (mcb3_dram_ras_n),
		.cas_n      (mcb3_dram_cas_n),
		.we_n       (mcb3_dram_we_n),
		.dm_rdqs    ({mcb3_dram_udm,mcb3_dram_dm}),
		.ba         (mcb3_dram_ba),
		.addr       (mcb3_dram_a),
		.dq         (mcb3_dram_dq),
		.dqs        ({mcb3_dram_udqs,mcb3_dram_dqs}),
		.dqs_n      ({mcb3_dram_udqs_n,mcb3_dram_dqs_n}),
		.rdqs_n     (),
		.odt        (mcb3_dram_odt)
		);
	end else begin
		ddr2_model_c3 u_mem_c3(
		.ck         (mcb3_dram_ck),
		.ck_n       (mcb3_dram_ck_n),
		.cke        (mcb3_dram_cke),
		.cs_n       (1'b0),
		.ras_n      (mcb3_dram_ras_n),
		.cas_n      (mcb3_dram_cas_n),
		.we_n       (mcb3_dram_we_n),
		.dm_rdqs    (mcb3_dram_dm),
		.ba         (mcb3_dram_ba),
		.addr       (mcb3_dram_a),
		.dq         (mcb3_dram_dq),
		.dqs        (mcb3_dram_dqs),
		.dqs_n      (mcb3_dram_dqs_n),
		.rdqs_n     (),
		.odt        (mcb3_dram_odt)
		);
	end
	endgenerate





	ramtest #(
	.DEBUG_EN(DEBUG_EN),                                                                   
	.C3_MEMCLK_PERIOD(C3_MEMCLK_PERIOD),                                                                
	.C3_RST_ACT_LOW(C3_RST_ACT_LOW),                                                                   
	.C3_INPUT_CLK_TYPE(C3_INPUT_CLK_TYPE),                                                   
	.C3_NUM_DQ_PINS(C3_NUM_DQ_PINS),                                                            
	.C3_MEM_ADDR_WIDTH(C3_MEM_ADDR_WIDTH),                         
	.C3_MEM_BANKADDR_WIDTH(C3_MEM_BANKADDR_WIDTH),                                    
	.C3_MEM_ADDR_ORDER(C3_MEM_ADDR_ORDER),                                             
	.C3_P0_MASK_SIZE(C3_P0_MASK_SIZE),                                                        
	.C3_P0_DATA_PORT_SIZE(C3_P0_DATA_PORT_SIZE),                                                      
	.C3_P1_MASK_SIZE(C3_P1_MASK_SIZE),                                                            
	.C3_P1_DATA_PORT_SIZE(C3_P1_DATA_PORT_SIZE),                                                                                         
	.C3_CALIB_SOFT_IP(C3_CALIB_SOFT_IP),                                
	.C3_SIMULATION(C3_SIMULATION),                                                
	.C3_HW_TESTING(C3_HW_TESTING),                                         
	)
	 dut
		(
		.hi_in                  (hi_in),
		.hi_out                 (hi_out),
		.hi_inout               (hi_inout),
		.i2c_sda                (i2c_sda),
		.i2c_scl                (i2c_scl),
		.hi_aa                  (hi_aa),
		.hi_muxsel              (hi_muxsel),
	
		.led                    (led),
	
		.clk1                   (clk1),
				
		.mcb3_dram_dq           (mcb3_dram_dq),
		.mcb3_dram_a            (mcb3_dram_a),
		.mcb3_dram_ba           (mcb3_dram_ba),
		.mcb3_dram_ras_n        (mcb3_dram_ras_n),
		.mcb3_dram_cas_n        (mcb3_dram_cas_n),
		.mcb3_dram_we_n         (mcb3_dram_we_n),
		.mcb3_dram_odt          (mcb3_dram_odt),
		.mcb3_dram_cke          (mcb3_dram_cke),
		.mcb3_dram_dm           (mcb3_dram_dm),
		.mcb3_dram_udqs         (mcb3_dram_udqs),
		.mcb3_dram_udqs_n       (mcb3_dram_udqs_n),
		.mcb3_rzq               (mcb3_rzq),
		.mcb3_zio               (mcb3_zio),
		.mcb3_dram_udm          (mcb3_dram_udm),
		.mcb3_dram_dqs          (mcb3_dram_dqs),
		.mcb3_dram_dqs_n        (mcb3_dram_dqs_n),
		.mcb3_dram_ck           (mcb3_dram_ck),
		.mcb3_dram_ck_n         (mcb3_dram_ck_n),
		.mcb3_dram_cs_n         (mcb3_dram_cs_n)
		);





	parameter BlockDelayStates = 5;
	parameter ReadyCheckDelay = 5;

	parameter PostReadyDelay = 5;

	parameter pipeInSize = 1024;

	parameter pipeOutSize = 1024;

	integer k, e;
	reg	[7:0]	pipeIn  [0:(pipeInSize-1)];
	reg	[7:0]	pipeOut [0:(pipeOutSize-1)];
	reg [7:0] pipetmp [0:(pipeInSize-1)];
	

	parameter tCLK = 10.0;
	initial clk1 = 0;
	always #(tCLK/2.0) clk1 = ~clk1;
	

	integer i;
	initial begin
		
		FrontPanelReset;
		$display("//// Beginning Tests at:                           %dns   /////", $time);
		

		SetWireInValue(8'h00, 16'h0004, 16'hffff);
		UpdateWireIns;
		SetWireInValue(8'h00, 16'h0000, 16'hffff);
		UpdateWireIns;
	
		wait (tf.dut.c3_calib_done == 1'b1);
	
		$display("//// DDR2 PHY initialization complete at:          %dns   /////", $time);


		for (k=0; k<pipeInSize; k=k+1) pipeIn[k] = $random;

		for (k=0; k<pipeInSize; k=k+1) pipetmp[k] = pipeIn[k];

		for (k=0; k<pipeOutSize; k=k+1) pipeOut[k] = 8'h00;
		

		SetWireInValue(8'h00, 16'h0002, 16'hffff);
		UpdateWireIns;
		WriteToPipeIn(8'h80, pipeInSize);
		$display("//// Write to DDR2 complete at:                    %dns   /////", $time);
	

		SetWireInValue(8'h00, 16'h0001, 16'hffff);
		UpdateWireIns;
	
		#10000;
	

		ReadFromPipeOut(8'ha0, pipeInSize);
	$display("//// Read From DDR2 complete at:                   %dns   /////", $time);
	

		e=0;
		for (k=0; k<pipeInSize; k=k+1) begin 
			if (pipeOut[k] != pipetmp[k]) begin
				e=e+1;
				$display(" ");
				$display("Error! Data mismatch at byte %d:  Expected: 0x%08x Read: 0x%08x", k, pipetmp[k], pipeOut[k]);
			end
		end
		
		if (e == 0) begin
			$display(" ");
			$display("Success! All data passes readback.");
		end

	$display("Simulation done at: %dns", $time);
	$stop;
	
	end
	

	`include "./oksim/okHostCalls.v"

endmodule
module tf;




	parameter DEBUG_EN              = 0;                                                                     
	parameter C3_MEMCLK_PERIOD     = 3200;                                                                   
	parameter C3_RST_ACT_LOW        = 0;                                                                     
	parameter C3_INPUT_CLK_TYPE     = "DIFFERENTIAL";                                                        
	parameter C3_NUM_DQ_PINS        = 16;                                                                    
	parameter C3_MEM_ADDR_WIDTH     = 13;                                                                    
	parameter C3_MEM_BANKADDR_WIDTH = 3;                                                                     
	parameter C3_MEM_ADDR_ORDER     = "ROW_BANK_COLUMN";                                                     
	parameter C3_P0_MASK_SIZE       = 4;                                                                     
	parameter C3_P0_DATA_PORT_SIZE  = 32;                                                                    
	parameter C3_P1_MASK_SIZE       = 4;                                                                     
	parameter C3_P1_DATA_PORT_SIZE  = 32;                                                                    
	parameter C3_MEM_BURST_LEN	  = 4;                                                                       
	parameter C3_MEM_NUM_COL_BITS   = 10;                                                                    
	parameter C3_CALIB_SOFT_IP      = "FALSE";
	parameter C3_SIMULATION      = "TRUE";                                                                   
	parameter C3_HW_TESTING      = "FALSE";                                                                  
	localparam C3_p0_BEGIN_ADDRESS                   = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;
	localparam C3_p0_DATA_MODE                       = 4'b0010;                                              
	localparam C3_p0_END_ADDRESS                     = (C3_HW_TESTING == "TRUE") ? 32'h02ffffff:32'h000002ff;     
	localparam C3_p0_PRBS_EADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'hfc000000:32'hfffffc00;
	localparam C3_p0_PRBS_SADDR_MASK_POS             = (C3_HW_TESTING == "TRUE") ? 32'h01000000:32'h00000100;
	





	reg  [7:0]  hi_in;
	wire [1:0]  hi_out;
	wire [15:0] hi_inout;
	wire        hi_aa;
	
	wire        i2c_sda;
	wire        i2c_scl;
	wire        hi_muxsel;
	
	wire [7:0]  led;
	

	reg         clk1;
	

	wire [C3_NUM_DQ_PINS-1:0]           mcb3_dram_dq;
	wire [C3_MEM_ADDR_WIDTH-1:0]        mcb3_dram_a;
	wire [C3_MEM_BANKADDR_WIDTH-1:0]    mcb3_dram_ba;
	wire                                mcb3_dram_ras_n;
	wire                                mcb3_dram_cas_n;
	wire                                mcb3_dram_we_n;
	wire                                mcb3_dram_odt;
	wire                                mcb3_dram_cke;
	wire                                mcb3_dram_dm;
	wire                                mcb3_dram_udqs;
	wire                                mcb3_dram_udqs_n;
	wire                                mcb3_rzq;
	wire                                mcb3_zio;
	wire                                mcb3_dram_udm;
	wire                                mcb3_dram_dqs;
	wire                                mcb3_dram_dqs_n;
	wire                                mcb3_dram_ck;
	wire                                mcb3_dram_ck_n;
	wire                                mcb3_dram_cs_n;
	


	PULLDOWN zio_pulldown3 (.O(mcb3_zio));
	PULLDOWN rzq_pulldown3 (.O(mcb3_rzq));
	




	generate
	if(C3_NUM_DQ_PINS == 16) begin : MEM_INST3
		ddr2_model_c3 u_mem_c3(
		.ck         (mcb3_dram_ck),
		.ck_n       (mcb3_dram_ck_n),
		.cke        (mcb3_dram_cke),
		.cs_n       (1'b0),
		.ras_n      (mcb3_dram_ras_n),
		.cas_n      (mcb3_dram_cas_n),
		.we_n       (mcb3_dram_we_n),
		.dm_rdqs    ({mcb3_dram_udm,mcb3_dram_dm}),
		.ba         (mcb3_dram_ba),
		.addr       (mcb3_dram_a),
		.dq         (mcb3_dram_dq),
		.dqs        ({mcb3_dram_udqs,mcb3_dram_dqs}),
		.dqs_n      ({mcb3_dram_udqs_n,mcb3_dram_dqs_n}),
		.rdqs_n     (),
		.odt        (mcb3_dram_odt)
		);
	end else begin
		ddr2_model_c3 u_mem_c3(
		.ck         (mcb3_dram_ck),
		.ck_n       (mcb3_dram_ck_n),
		.cke        (mcb3_dram_cke),
		.cs_n       (1'b0),
		.ras_n      (mcb3_dram_ras_n),
		.cas_n      (mcb3_dram_cas_n),
		.we_n       (mcb3_dram_we_n),
		.dm_rdqs    (mcb3_dram_dm),
		.ba         (mcb3_dram_ba),
		.addr       (mcb3_dram_a),
		.dq         (mcb3_dram_dq),
		.dqs        (mcb3_dram_dqs),
		.dqs_n      (mcb3_dram_dqs_n),
		.rdqs_n     (),
		.odt        (mcb3_dram_odt)
		);
	end
	endgenerate





	ramtest #(
	.DEBUG_EN(DEBUG_EN),                                                                   
	.C3_MEMCLK_PERIOD(C3_MEMCLK_PERIOD),                                                                
	.C3_RST_ACT_LOW(C3_RST_ACT_LOW),                                                                   
	.C3_INPUT_CLK_TYPE(C3_INPUT_CLK_TYPE),                                                   
	.C3_NUM_DQ_PINS(C3_NUM_DQ_PINS),                                                            
	.C3_MEM_ADDR_WIDTH(C3_MEM_ADDR_WIDTH),                         
	.C3_MEM_BANKADDR_WIDTH(C3_MEM_BANKADDR_WIDTH),                                    
	.C3_MEM_ADDR_ORDER(C3_MEM_ADDR_ORDER),                                             
	.C3_P0_MASK_SIZE(C3_P0_MASK_SIZE),                                                        
	.C3_P0_DATA_PORT_SIZE(C3_P0_DATA_PORT_SIZE),                                                      
	.C3_P1_MASK_SIZE(C3_P1_MASK_SIZE),                                                            
	.C3_P1_DATA_PORT_SIZE(C3_P1_DATA_PORT_SIZE),                                                                                         
	.C3_CALIB_SOFT_IP(C3_CALIB_SOFT_IP),                                
	.C3_SIMULATION(C3_SIMULATION),                                                
	.C3_HW_TESTING(C3_HW_TESTING),                                         
	)
	 dut
		(
		.hi_in                  (hi_in),
		.hi_out                 (hi_out),
		.hi_inout               (hi_inout),
		.i2c_sda                (i2c_sda),
		.i2c_scl                (i2c_scl),
		.hi_aa                  (hi_aa),
		.hi_muxsel              (hi_muxsel),
	
		.led                    (led),
	
		.clk1                   (clk1),
				
		.mcb3_dram_dq           (mcb3_dram_dq),
		.mcb3_dram_a            (mcb3_dram_a),
		.mcb3_dram_ba           (mcb3_dram_ba),
		.mcb3_dram_ras_n        (mcb3_dram_ras_n),
		.mcb3_dram_cas_n        (mcb3_dram_cas_n),
		.mcb3_dram_we_n         (mcb3_dram_we_n),
		.mcb3_dram_odt          (mcb3_dram_odt),
		.mcb3_dram_cke          (mcb3_dram_cke),
		.mcb3_dram_dm           (mcb3_dram_dm),
		.mcb3_dram_udqs         (mcb3_dram_udqs),
		.mcb3_dram_udqs_n       (mcb3_dram_udqs_n),
		.mcb3_rzq               (mcb3_rzq),
		.mcb3_zio               (mcb3_zio),
		.mcb3_dram_udm          (mcb3_dram_udm),
		.mcb3_dram_dqs          (mcb3_dram_dqs),
		.mcb3_dram_dqs_n        (mcb3_dram_dqs_n),
		.mcb3_dram_ck           (mcb3_dram_ck),
		.mcb3_dram_ck_n         (mcb3_dram_ck_n),
		.mcb3_dram_cs_n         (mcb3_dram_cs_n)
		);





	parameter BlockDelayStates = 5;
	parameter ReadyCheckDelay = 5;

	parameter PostReadyDelay = 5;

	parameter pipeInSize = 1024;

	parameter pipeOutSize = 1024;

	integer k, e;
	reg	[7:0]	pipeIn  [0:(pipeInSize-1)];
	reg	[7:0]	pipeOut [0:(pipeOutSize-1)];
	reg [7:0] pipetmp [0:(pipeInSize-1)];
	

	parameter tCLK = 10.0;
	initial clk1 = 0;
	always #(tCLK/2.0) clk1 = ~clk1;
	

	integer i;
	initial begin
		
		FrontPanelReset;
		$display("//// Beginning Tests at:                           %dns   /////", $time);
		

		SetWireInValue(8'h00, 16'h0004, 16'hffff);
		UpdateWireIns;
		SetWireInValue(8'h00, 16'h0000, 16'hffff);
		UpdateWireIns;
	
		wait (tf.dut.c3_calib_done == 1'b1);
	
		$display("//// DDR2 PHY initialization complete at:          %dns   /////", $time);


		for (k=0; k<pipeInSize; k=k+1) pipeIn[k] = $random;

		for (k=0; k<pipeInSize; k=k+1) pipetmp[k] = pipeIn[k];

		for (k=0; k<pipeOutSize; k=k+1) pipeOut[k] = 8'h00;
		

		SetWireInValue(8'h00, 16'h0002, 16'hffff);
		UpdateWireIns;
		WriteToPipeIn(8'h80, pipeInSize);
		$display("//// Write to DDR2 complete at:                    %dns   /////", $time);
	

		SetWireInValue(8'h00, 16'h0001, 16'hffff);
		UpdateWireIns;
	
		#10000;
	

		ReadFromPipeOut(8'ha0, pipeInSize);
	$display("//// Read From DDR2 complete at:                   %dns   /////", $time);
	

		e=0;
		for (k=0; k<pipeInSize; k=k+1) begin 
			if (pipeOut[k] != pipetmp[k]) begin
				e=e+1;
				$display(" ");
				$display("Error! Data mismatch at byte %d:  Expected: 0x%08x Read: 0x%08x", k, pipetmp[k], pipeOut[k]);
			end
		end
		
		if (e == 0) begin
			$display(" ");
			$display("Success! All data passes readback.");
		end

	$display("Simulation done at: %dns", $time);
	$stop;
	
	end
	

	`include "./oksim/okHostCalls.v"

endmodule