data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/utils/ctrlport_decoder_param.v
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data/verilator_xmls/4a4ce006-814c-4b3a-af57-32e8ad1b12d9.xml
module ctrlport_decoder_param #(
  parameter NUM_SLAVES  = 4,
  parameter PORT_BASE   = { 20'h300, 20'h200, 20'h100, 20'h000 },
  parameter PORT_ADDR_W = {   32'd8,   32'd8,   32'd8,   32'd8 }
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,
  input  wire [ 3:0] s_ctrlport_req_byte_en,
  input  wire        s_ctrlport_req_has_time,
  input  wire [63:0] s_ctrlport_req_time,
  output reg         s_ctrlport_resp_ack = 1'b0,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  output reg  [   NUM_SLAVES-1:0] m_ctrlport_req_wr = 0,
  output reg  [   NUM_SLAVES-1:0] m_ctrlport_req_rd = 0,
  output reg  [20*NUM_SLAVES-1:0] m_ctrlport_req_addr = 0,
  output reg  [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
  output reg  [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
  output reg  [   NUM_SLAVES-1:0] m_ctrlport_req_has_time,
  output reg  [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
  input  wire [   NUM_SLAVES-1:0] m_ctrlport_resp_ack,
  input  wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
  input  wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
);










  wire [NUM_SLAVES-1:0] dec_mask;

  generate
    genvar i;

    for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_dec_mask
      localparam [19:0] BASE_ADDR = PORT_BASE  [i*20 +: 20];
      localparam [31:0] ADDR_W    = PORT_ADDR_W[i*32 +: 32];
      assign dec_mask[i] = ~|((s_ctrlport_req_addr ^ BASE_ADDR) & ((~0) << ADDR_W));
    end






    for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
      localparam [31:0] ADDR_W = PORT_ADDR_W[i*32 +: 32];

      always @(posedge ctrlport_clk) begin
        if (ctrlport_rst) begin
          m_ctrlport_req_wr[i] <= 1'b0;
          m_ctrlport_req_rd[i] <= 1'b0;
        end else begin

          m_ctrlport_req_wr[i] <= s_ctrlport_req_wr & dec_mask[i];
          m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & dec_mask[i];



          m_ctrlport_req_data    [32*i +: 32] <= s_ctrlport_req_data;
          m_ctrlport_req_byte_en [4*i +: 4]   <= s_ctrlport_req_byte_en;
          m_ctrlport_req_has_time[i]          <= s_ctrlport_req_has_time;
          m_ctrlport_req_time    [64*i +: 64] <= s_ctrlport_req_time;


          m_ctrlport_req_addr[20*i +: 20]     <= 20'b0;
          m_ctrlport_req_addr[20*i +: ADDR_W] <= s_ctrlport_req_addr[ADDR_W-1 : 0];
        end
      end
    end
  endgenerate





  reg [31:0] data;
  reg [ 1:0] status;
  reg        ack = 0;


  always @(*) begin : comb_decode
    integer s;
    data   = 0;
    status = 0;
    ack    = 0;
    for (s = 0; s < NUM_SLAVES; s = s+1) begin
      data   = data   | (m_ctrlport_resp_data  [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
      status = status | (m_ctrlport_resp_status[s* 2 +:  2] & { 2{m_ctrlport_resp_ack[s]}});
      ack    = ack    | m_ctrlport_resp_ack[s];
    end
  end


  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      s_ctrlport_resp_ack  <= 0;
    end else begin
      s_ctrlport_resp_data   <= data;
      s_ctrlport_resp_status <= status;
      s_ctrlport_resp_ack    <= ack;
    end
  end

endmodule
module ctrlport_decoder_param #(
  parameter NUM_SLAVES  = 4,
  parameter PORT_BASE   = { 20'h300, 20'h200, 20'h100, 20'h000 },
  parameter PORT_ADDR_W = {   32'd8,   32'd8,   32'd8,   32'd8 }
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,
  input  wire [ 3:0] s_ctrlport_req_byte_en,
  input  wire        s_ctrlport_req_has_time,
  input  wire [63:0] s_ctrlport_req_time,
  output reg         s_ctrlport_resp_ack = 1'b0,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  output reg  [   NUM_SLAVES-1:0] m_ctrlport_req_wr = 0,
  output reg  [   NUM_SLAVES-1:0] m_ctrlport_req_rd = 0,
  output reg  [20*NUM_SLAVES-1:0] m_ctrlport_req_addr = 0,
  output reg  [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
  output reg  [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
  output reg  [   NUM_SLAVES-1:0] m_ctrlport_req_has_time,
  output reg  [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
  input  wire [   NUM_SLAVES-1:0] m_ctrlport_resp_ack,
  input  wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
  input  wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
);











  wire [NUM_SLAVES-1:0] dec_mask;

  generate
    genvar i;

    for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_dec_mask
      localparam [19:0] BASE_ADDR = PORT_BASE  [i*20 +: 20];
      localparam [31:0] ADDR_W    = PORT_ADDR_W[i*32 +: 32];
      assign dec_mask[i] = ~|((s_ctrlport_req_addr ^ BASE_ADDR) & ((~0) << ADDR_W));
    end






    for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
      localparam [31:0] ADDR_W = PORT_ADDR_W[i*32 +: 32];

      always @(posedge ctrlport_clk) begin
        if (ctrlport_rst) begin
          m_ctrlport_req_wr[i] <= 1'b0;
          m_ctrlport_req_rd[i] <= 1'b0;
        end else begin

          m_ctrlport_req_wr[i] <= s_ctrlport_req_wr & dec_mask[i];
          m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & dec_mask[i];



          m_ctrlport_req_data    [32*i +: 32] <= s_ctrlport_req_data;
          m_ctrlport_req_byte_en [4*i +: 4]   <= s_ctrlport_req_byte_en;
          m_ctrlport_req_has_time[i]          <= s_ctrlport_req_has_time;
          m_ctrlport_req_time    [64*i +: 64] <= s_ctrlport_req_time;


          m_ctrlport_req_addr[20*i +: 20]     <= 20'b0;
          m_ctrlport_req_addr[20*i +: ADDR_W] <= s_ctrlport_req_addr[ADDR_W-1 : 0];
        end
      end
    end
  endgenerate





  reg [31:0] data;
  reg [ 1:0] status;
  reg        ack = 0;


  always @(*) begin : comb_decode
    integer s;
    data   = 0;
    status = 0;
    ack    = 0;
    for (s = 0; s < NUM_SLAVES; s = s+1) begin
      data   = data   | (m_ctrlport_resp_data  [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
      status = status | (m_ctrlport_resp_status[s* 2 +:  2] & { 2{m_ctrlport_resp_ack[s]}});
      ack    = ack    | m_ctrlport_resp_ack[s];
    end
  end


  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      s_ctrlport_resp_ack  <= 0;
    end else begin
      s_ctrlport_resp_data   <= data;
      s_ctrlport_resp_status <= status;
      s_ctrlport_resp_ack    <= ack;
    end
  end

endmodule