data/full_repos/permissive/100796583/test/MBScore_IR_tb.v
1: b'%Error: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:1: Cannot find include file: ../cpu/MBScore_const.v\n`include "../cpu/MBScore_const.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v\n             data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.v\n             data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.sv\n             ../cpu/MBScore_const.v\n             ../cpu/MBScore_const.v.v\n             ../cpu/MBScore_const.v.sv\n             obj_dir/../cpu/MBScore_const.v\n             obj_dir/../cpu/MBScore_const.v.v\n             obj_dir/../cpu/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:13: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] next_addr;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:14: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] inst_in;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:15: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] inst_out;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:16: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] pc_out;\n       ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clk = ~clk;  \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #40\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Error: Exiting due to 5 error(s), 8 warning(s)\n'
module MBScore_IR_vlg_tst();
	reg clk;
	reg rst_n;
	reg IR_ack;
	reg next;
	reg JAL_or_J;
	reg BEQ_or_BNE;
	reg JR;
	reg hlt;
	reg jump;
	reg	[`DATA_WIDTH-1:0]	next_addr;
	reg	[`DATA_WIDTH-1:0]	inst_in;
	wire [`DATA_WIDTH-1:0]	inst_out;
	wire [`DATA_WIDTH-1:0]	pc_out;
	wire mem_re;

    MBScore_IR i1(
        .clk(clk),
	    .rst_n(rst_n),
	    .IR_ack(IR_ack),
	    .next(next),
	    .JAL_or_J(JAL_or_J),
	    .BEQ_or_BNE(BEQ_or_BNE),
	    .JR(JR),
	    .hlt(hlt),
	    .jump(jump),
	    .next_addr(next_addr),
	    .inst_in(inst_in),
	    .inst_out(inst_out),
	    .pc_out(pc_out),
	    .mem_re(mem_re)
    );

    initial                                                
    begin
        JAL_or_J = 1'b0;
        BEQ_or_BNE = 1'b0;
        JR = 1'b0;
        hlt = 1'b0;
        next = 1'b0;

        IR_ack = 1'b0;                                                                
        rst_n = 1'b1;
        clk = 1'b0;
        #1
        rst_n = 1'b0;
        #5
        rst_n = 1'b1;                                                                                               
        $display("Running testbench");                       
    end

    always
    begin
        forever #10 clk = ~clk;  
    end

    always @(posedge mem_re)
    if(pc_out == 32'd0)
    inst_in = 32'b00010000001000100000000000000001;
    else
    if(pc_out == 32'd8)
    inst_in = 32'b00010000001000100000000000000010;
    else
    inst_in = 32'b00010000001000100000000000000011;

    initial
    begin
        #10
        IR_ack = 1'b1;
        #20
        IR_ack = 1'b0;  
        #40
        next = 1'b1;
        BEQ_or_BNE = 1'b1;
        jump = 1'b0;
        #20
        IR_ack = 1'b1;
        #20
        IR_ack = 1'b0;
    end

endmodule
module MBScore_IR_vlg_tst();

	reg clk;
	reg rst_n;
	reg IR_ack;
	reg next;
	reg JAL_or_J;
	reg BEQ_or_BNE;
	reg JR;
	reg hlt;
	reg jump;
	reg	[`DATA_WIDTH-1:0]	next_addr;
	reg	[`DATA_WIDTH-1:0]	inst_in;
	wire [`DATA_WIDTH-1:0]	inst_out;
	wire [`DATA_WIDTH-1:0]	pc_out;
	wire mem_re;

    MBScore_IR i1(
        .clk(clk),
	    .rst_n(rst_n),
	    .IR_ack(IR_ack),
	    .next(next),
	    .JAL_or_J(JAL_or_J),
	    .BEQ_or_BNE(BEQ_or_BNE),
	    .JR(JR),
	    .hlt(hlt),
	    .jump(jump),
	    .next_addr(next_addr),
	    .inst_in(inst_in),
	    .inst_out(inst_out),
	    .pc_out(pc_out),
	    .mem_re(mem_re)
    );

    initial                                                
    begin
        JAL_or_J = 1'b0;
        BEQ_or_BNE = 1'b0;
        JR = 1'b0;
        hlt = 1'b0;
        next = 1'b0;

        IR_ack = 1'b0;                                                                
        rst_n = 1'b1;
        clk = 1'b0;
        #1
        rst_n = 1'b0;
        #5
        rst_n = 1'b1;                                                                                               
        $display("Running testbench");                       
    end

    always
    begin
        forever #10 clk = ~clk;  
    end

    always @(posedge mem_re)
    if(pc_out == 32'd0)
    inst_in = 32'b00010000001000100000000000000001;
    else
    if(pc_out == 32'd8)
    inst_in = 32'b00010000001000100000000000000010;
    else
    inst_in = 32'b00010000001000100000000000000011;

    initial
    begin
        #10
        IR_ack = 1'b1;
        #20
        IR_ack = 1'b0;  
        #40
        next = 1'b1;
        BEQ_or_BNE = 1'b1;
        jump = 1'b0;
        #20
        IR_ack = 1'b1;
        #20
        IR_ack = 1'b0;
    end

endmodule