data/full_repos/permissive/117026779/src/Keyboard.v
1: b"%Error: data/full_repos/permissive/117026779/src/Keyboard.v:256: Cannot find file containing module: 'Syncronizer'\nSyncronizer #(.WIDTH(1)) sync_clk (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/Syncronizer\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/Syncronizer.v\n             data/full_repos/permissive/117026779/src,data/full_repos/permissive/117026779/Syncronizer.sv\n             Syncronizer\n             Syncronizer.v\n             Syncronizer.sv\n             obj_dir/Syncronizer\n             obj_dir/Syncronizer.v\n             obj_dir/Syncronizer.sv\n%Error: data/full_repos/permissive/117026779/src/Keyboard.v:264: Cannot find file containing module: 'Syncronizer'\nSyncronizer #(.WIDTH(1)) sync_data (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/117026779/src/Keyboard.v:272: Cannot find file containing module: 'SHIFTREGISTER'\nSHIFTREGISTER #(.WIDTH(11)) scan_code_register (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/117026779/src/Keyboard.v:292: Cannot find file containing module: 'COUNTER'\nCOUNTER #(.WIDTH(4)) counter_ps2_clks (\n^~~~~~~\n%Error: data/full_repos/permissive/117026779/src/Keyboard.v:302: Cannot find file containing module: 'XNOR'\nXNOR #(.WIDTH(8)) parity_checker (\n^~~~\n%Error: data/full_repos/permissive/117026779/src/Keyboard.v:307: Cannot find file containing module: 'XNOR'\nXNOR #(.WIDTH(2)) parity_matcher (\n^~~~\n%Error: data/full_repos/permissive/117026779/src/Keyboard.v:312: Cannot find file containing module: 'AND'\nAND #(.WIDTH(2)) new_signal (\n^~~\n%Error: data/full_repos/permissive/117026779/src/Keyboard.v:317: Cannot find file containing module: 'TRIBUFFER'\nTRIBUFFER #(.WIDTH(8)) scan_code_buffer (\n^~~~~~~~~\n%Error: data/full_repos/permissive/117026779/src/Keyboard.v:97: Cannot find file containing module: 'FIFO'\nFIFO #(\n^~~~\n%Error: data/full_repos/permissive/117026779/src/Keyboard.v:503: Cannot find file containing module: 'VGA_Terminal'\nVGA_Terminal vga_term(\n^~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module ASCII_Keyboard(
    input wire clk,
    input wire rst,
    input wire ps2_clk,
    input wire ps2_data,
    input wire oe,
    input wire next,
    output wire [`ASCII_WIDTH-1:0] ascii,
    output wire ready,
    output reg [`ASCII_WIDTH-1:0] scan_code_reg,
    output reg [31:0] extended_count,
    output wire command
);



parameter WAITING = 0;
parameter NEW_CODE = 1;
parameter TRANSLATE = 2;
parameter WRITE_TO_FIFO = 3;
parameter STATE_WIDTH = $clog2(WRITE_TO_FIFO+1);



wire [`ASCII_WIDTH-1:0] fifo_ascii;
wire [`ASCII_WIDTH-1:0] translated_to_ascii;
wire [`ASCII_WIDTH-1:0] scan_code;
wire full, empty;
wire key_ready;



assign ascii = (oe) ? fifo_ascii : 8'bZ;
assign ready = (!empty);
assign command = (fifo_ascii == `LEFT_ARROW_ASCII ||
                    fifo_ascii == `RIGHT_ARROW_ASCII ||
                    fifo_ascii == `UP_ARROW_ASCII ||
                    fifo_ascii == `DOWN_ARROW_ASCII);



Keyboard keyboard(
    .clk(clk),
    .rst(rst),
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),
    .clr(clr),
    .cs(1'b1),
    .data(scan_code),
    .ready(key_ready)
);

FIFO #(
    .LENGTH(16),
    .WIDTH(`ASCII_WIDTH)
) ascii_to_vga (
    .clk(clk),
    .rst(rst),
    .wr_cs(fifo_control),
    .wr_en(fifo_control),
    .rd_cs(next),
    .rd_en(next),
    .full(full),
    .empty(empty),
    .out(fifo_ascii),
    .in(translated_to_ascii)
);

KeyboardToASCIIROM rom(
    .scan_code(scan_code_reg),
    .shift(shift),
    .ascii(translated_to_ascii)
);



reg [STATE_WIDTH-1:0] state;
reg clr;
reg break_detected;
reg empty_reg;
reg previously_empty;
reg fifo_control;
reg shift;
reg extended;



always@(posedge clk or posedge rst)
begin
    if(rst)
    begin
        state           <= WAITING;
        clr             <= 0;
        fifo_control    <= 0;
        scan_code_reg   <= 0;
        break_detected  <= 0;
        shift           <= 0;
        extended        <= 0;
        extended_count  <= 0;
    end
    else
    begin
        case(state)
            WAITING: begin
                clr          = 0;
                fifo_control = 0;
                if(key_ready)
                begin
                    scan_code_reg = scan_code;
                    state = NEW_CODE;
                end
            end
            NEW_CODE: begin
                fifo_control = 0;
                clr          = 1;
                if(scan_code_reg == `EXTEND_CODE)
                begin
                    extended = 1;
                    extended_count = extended_count + 1;
                    state = WAITING;
                end
                else if(break_detected && (scan_code_reg == `SHIFT_CODE_LEFT || scan_code_reg == `SHIFT_CODE_RIGHT))
                begin
                    shift = 0;
                    break_detected = 0;
                    state = WAITING;
                end
                else if(break_detected)
                begin
                    extended = 0;
                    break_detected = 0;
                    state = WAITING;
                end
                else begin
                    state = TRANSLATE;
                end
            end
            TRANSLATE: begin
                fifo_control = 0;
                clr          = 0;
                if(scan_code_reg == `BREAK_CODE)
                begin
                    break_detected = 1;
                    state = WAITING;
                end
                else if(extended)
                begin
                    extended = 0;
                    scan_code_reg[7] = 1;
                    state = WRITE_TO_FIFO;
                end
                else if (scan_code_reg == `SHIFT_CODE_LEFT || scan_code_reg == `SHIFT_CODE_RIGHT)
                begin
                    shift = 1;
                    state = WAITING;
                end
                else begin
                    state = WRITE_TO_FIFO;
                end
            end
            WRITE_TO_FIFO: begin
                fifo_control = 1;
                clr          = 0;
                state = WAITING;
            end
            default: begin
                fifo_control = 0;
                clr = 1;
                state = WAITING;
            end
        endcase
    end
end

endmodule
module ASCII_Keyboard(
    input wire clk,
    input wire rst,
    input wire ps2_clk,
    input wire ps2_data,
    input wire oe,
    input wire next,
    output wire [`ASCII_WIDTH-1:0] ascii,
    output wire ready,
    output reg [`ASCII_WIDTH-1:0] scan_code_reg,
    output reg [31:0] extended_count,
    output wire command
);




parameter WAITING = 0;
parameter NEW_CODE = 1;
parameter TRANSLATE = 2;
parameter WRITE_TO_FIFO = 3;
parameter STATE_WIDTH = $clog2(WRITE_TO_FIFO+1);



wire [`ASCII_WIDTH-1:0] fifo_ascii;
wire [`ASCII_WIDTH-1:0] translated_to_ascii;
wire [`ASCII_WIDTH-1:0] scan_code;
wire full, empty;
wire key_ready;



assign ascii = (oe) ? fifo_ascii : 8'bZ;
assign ready = (!empty);
assign command = (fifo_ascii == `LEFT_ARROW_ASCII ||
                    fifo_ascii == `RIGHT_ARROW_ASCII ||
                    fifo_ascii == `UP_ARROW_ASCII ||
                    fifo_ascii == `DOWN_ARROW_ASCII);



Keyboard keyboard(
    .clk(clk),
    .rst(rst),
    .ps2_clk(ps2_clk),
    .ps2_data(ps2_data),
    .clr(clr),
    .cs(1'b1),
    .data(scan_code),
    .ready(key_ready)
);

FIFO #(
    .LENGTH(16),
    .WIDTH(`ASCII_WIDTH)
) ascii_to_vga (
    .clk(clk),
    .rst(rst),
    .wr_cs(fifo_control),
    .wr_en(fifo_control),
    .rd_cs(next),
    .rd_en(next),
    .full(full),
    .empty(empty),
    .out(fifo_ascii),
    .in(translated_to_ascii)
);

KeyboardToASCIIROM rom(
    .scan_code(scan_code_reg),
    .shift(shift),
    .ascii(translated_to_ascii)
);



reg [STATE_WIDTH-1:0] state;
reg clr;
reg break_detected;
reg empty_reg;
reg previously_empty;
reg fifo_control;
reg shift;
reg extended;



always@(posedge clk or posedge rst)
begin
    if(rst)
    begin
        state           <= WAITING;
        clr             <= 0;
        fifo_control    <= 0;
        scan_code_reg   <= 0;
        break_detected  <= 0;
        shift           <= 0;
        extended        <= 0;
        extended_count  <= 0;
    end
    else
    begin
        case(state)
            WAITING: begin
                clr          = 0;
                fifo_control = 0;
                if(key_ready)
                begin
                    scan_code_reg = scan_code;
                    state = NEW_CODE;
                end
            end
            NEW_CODE: begin
                fifo_control = 0;
                clr          = 1;
                if(scan_code_reg == `EXTEND_CODE)
                begin
                    extended = 1;
                    extended_count = extended_count + 1;
                    state = WAITING;
                end
                else if(break_detected && (scan_code_reg == `SHIFT_CODE_LEFT || scan_code_reg == `SHIFT_CODE_RIGHT))
                begin
                    shift = 0;
                    break_detected = 0;
                    state = WAITING;
                end
                else if(break_detected)
                begin
                    extended = 0;
                    break_detected = 0;
                    state = WAITING;
                end
                else begin
                    state = TRANSLATE;
                end
            end
            TRANSLATE: begin
                fifo_control = 0;
                clr          = 0;
                if(scan_code_reg == `BREAK_CODE)
                begin
                    break_detected = 1;
                    state = WAITING;
                end
                else if(extended)
                begin
                    extended = 0;
                    scan_code_reg[7] = 1;
                    state = WRITE_TO_FIFO;
                end
                else if (scan_code_reg == `SHIFT_CODE_LEFT || scan_code_reg == `SHIFT_CODE_RIGHT)
                begin
                    shift = 1;
                    state = WAITING;
                end
                else begin
                    state = WRITE_TO_FIFO;
                end
            end
            WRITE_TO_FIFO: begin
                fifo_control = 1;
                clr          = 0;
                state = WAITING;
            end
            default: begin
                fifo_control = 0;
                clr = 1;
                state = WAITING;
            end
        endcase
    end
end

endmodule