data/full_repos/permissive/158824477/submodules/PulseRain_MCU/memory/lattice/MXO2_4K/dual_port_ram_lattice.v
data/verilator_xmls/443f74e0-a3f7-4c22-b582-7ae4edfc1676.xml
module dual_port_ram_lattice #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) (
          input wire [ADDR_WIDTH - 1 : 0]       waddr, 
          input wire [ADDR_WIDTH - 1 : 0]       raddr,
          
          input wire [DATA_WIDTH - 1 : 0]       din,
          input wire                            write_en, 
          input wire                            wclk, 
          input wire                            rclk,
          output reg [DATA_WIDTH - 1 : 0]       dout
);

    reg [DATA_WIDTH - 1 : 0] mem [(1<<ADDR_WIDTH)-1:0];
    
    always @(posedge wclk)  begin
        if (write_en) begin
            mem[waddr] <= din;
        end
    end
   
    always @(posedge rclk) begin
        dout <= mem[raddr];
    end
endmodule
module dual_port_ram_lattice #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) (
          input wire [ADDR_WIDTH - 1 : 0]       waddr, 
          input wire [ADDR_WIDTH - 1 : 0]       raddr,
          
          input wire [DATA_WIDTH - 1 : 0]       din,
          input wire                            write_en, 
          input wire                            wclk, 
          input wire                            rclk,
          output reg [DATA_WIDTH - 1 : 0]       dout
);


    reg [DATA_WIDTH - 1 : 0] mem [(1<<ADDR_WIDTH)-1:0];
    
    always @(posedge wclk)  begin
        if (write_en) begin
            mem[waddr] <= din;
        end
    end
   
    always @(posedge rclk) begin
        dout <= mem[raddr];
    end
endmodule