data/full_repos/permissive/183345139/verilog_tutorial/1_Button_Led/button_led.v
data/verilator_xmls/3fee7311-1190-4cf8-88a6-0046081dfc2b.xml
module button_led
(
    input wire button0,
    input wire button1,
    output wire [7:0] led
);

assign led[0] = ~button0;
assign led[1] = ~button1;

assign led[7:2] = 0;

endmodule
module button_led
(
    input wire button0,
    input wire button1,
    output wire [7:0] led
);


assign led[0] = ~button0;
assign led[1] = ~button1;

assign led[7:2] = 0;

endmodule