data/full_repos/permissive/206301883/PIN_TEST.v
data/verilator_xmls/2fd1f034-2bc3-4b13-8175-9d9dcb0bde3f.xml
module PIN_TEST(
input clk,
output reg pin
    );
    
always @(posedge clk)
    begin
        pin <= 1'b1;
    end
endmodule
module PIN_TEST(
input clk,
output reg pin
    );

    
always @(posedge clk)
    begin
        pin <= 1'b1;
    end
endmodule