data/full_repos/permissive/143278/ivltests/pr2355304.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2355304.v:18: Unsupported: Ignoring delay on this delayed statement.\n #1 if (t_not !== 1) begin\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test ();
    parameter t=0;
    reg t_not, t_zero;

    generate
    if (!t) begin
        initial t_not = 1;
    end
    endgenerate

    generate
    if (t==0) begin
        initial t_zero = 1;
    end
    endgenerate

    initial begin
	#1 if (t_not !== 1) begin
		$display("FAILED -- t_not=%b", t_not);
		$finish;
	end
	if (t_zero !== 1) begin
		$display("FAILED -- t_zero=%b", t_zero);
		$finish;
	end
	$display("PASSED");
    end
endmodule
module test ();

    parameter t=0;
    reg t_not, t_zero;

    generate
    if (!t) begin
        initial t_not = 1;
    end
    endgenerate

    generate
    if (t==0) begin
        initial t_zero = 1;
    end
    endgenerate

    initial begin
	#1 if (t_not !== 1) begin
		$display("FAILED -- t_not=%b", t_not);
		$finish;
	end
	if (t_zero !== 1) begin
		$display("FAILED -- t_zero=%b", t_zero);
		$finish;
	end
	$display("PASSED");
    end
endmodule