data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/clk_divider.v
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data/verilator_xmls/042a3f43-38ee-47f8-8326-f4c98c39ea81.xml
module clk_divider
#(
	parameter O_CLK_FREQ = 1
)(
	input clk_in,
	input reset,
	output reg clk_out
);


	localparam COUNTER_MAX = 'd100_000_000/(2 * O_CLK_FREQ) - 1;

	reg [26:0] counter = 'd0;


	always @(posedge clk_in) begin
		if (reset == 1'b1) begin

			counter <= 'd0;
			clk_out <= 0;
		end else if (counter == COUNTER_MAX) begin

			counter <= 'd0;
			clk_out <= ~clk_out;
		end else begin

			counter <= counter + 'd1;
			clk_out <= clk_out;
		end
	end

endmodule
module clk_divider
#(
	parameter O_CLK_FREQ = 1
)(
	input clk_in,
	input reset,
	output reg clk_out
);



	localparam COUNTER_MAX = 'd100_000_000/(2 * O_CLK_FREQ) - 1;

	reg [26:0] counter = 'd0;


	always @(posedge clk_in) begin
		if (reset == 1'b1) begin

			counter <= 'd0;
			clk_out <= 0;
		end else if (counter == COUNTER_MAX) begin

			counter <= 'd0;
			clk_out <= ~clk_out;
		end else begin

			counter <= counter + 'd1;
			clk_out <= clk_out;
		end
	end

endmodule