data/full_repos/permissive/100597706/testing/testbench.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n   always # 5 clk = ~ clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #50;\n    ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[4] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[4] = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #300    INT[14] = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #20     INT[14] = 1\'b0;\n    ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module AHBLDEC #(parameter logHBank = 10, parameter ioN = 1) (
	input [31:0] HADDR,
	output reg [0:2+ioN] HSEL
);
    reg [0:1+ioN] HSEL_wo_def;
    integer i;
    always @ * begin
    	HSEL_wo_def[0] = (HADDR[31:logHBank+2] == 0);
		HSEL_wo_def[1] = (HADDR[31:28] == 4'hf);
    	for (i = 0; i < ioN; i = i + 1)
    	    HSEL_wo_def[i+2] = (HADDR == {28'h8000000, i[3:0]});
    	    
    	if (HSEL_wo_def == 0)
    	    HSEL = {1'b1, HSEL_wo_def};
    	else
    	    HSEL = {1'b0, HSEL_wo_def};
    end

endmodule
module AHBLDEC #(parameter logHBank = 10, parameter ioN = 1) (
	input [31:0] HADDR,
	output reg [0:2+ioN] HSEL
);

    reg [0:1+ioN] HSEL_wo_def;
    integer i;
    always @ * begin
    	HSEL_wo_def[0] = (HADDR[31:logHBank+2] == 0);
		HSEL_wo_def[1] = (HADDR[31:28] == 4'hf);
    	for (i = 0; i < ioN; i = i + 1)
    	    HSEL_wo_def[i+2] = (HADDR == {28'h8000000, i[3:0]});
    	    
    	if (HSEL_wo_def == 0)
    	    HSEL = {1'b1, HSEL_wo_def};
    	else
    	    HSEL = {1'b0, HSEL_wo_def};
    end

endmodule