data/full_repos/permissive/109936328/pipe_util/register_file.v
1: b'%Error: data/full_repos/permissive/109936328/pipe_util/register_file.v:52: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile(DUMP_FILE);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/109936328/pipe_util/register_file.v:54: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, registers[i]);\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register_file(
  clk,
  aresetn,
  
  rd_reg_a,
  rd_reg_b,
  
  rd_data_a,
  rd_data_b,
  
  wr_en,
  wr_reg,
  wr_data
);

  parameter REG_COUNT = 32;

  parameter REG_W = 32;

  parameter REG_IDX_W = $clog2(REG_COUNT);


  parameter DUMP_VARS = 0;
  parameter DUMP_FILE = "a.vcd";


  input clk;

  input aresetn;


  input [REG_IDX_W - 1:0] rd_reg_a;
  input [REG_IDX_W - 1:0] rd_reg_b;


  output reg [REG_W - 1:0] rd_data_a;
  output reg [REG_W - 1:0] rd_data_b;


  input wr_en;

  input [REG_IDX_W - 1:0] wr_reg;

  input [REG_W - 1:0] wr_data;

  reg [REG_W - 1:0] registers [0:REG_COUNT - 1];

  integer i;

  initial begin
    if(DUMP_VARS == 1) begin
      $dumpfile(DUMP_FILE);
      for(i = 0; i < REG_COUNT; i = i + 1) begin
        $dumpvars(0, registers[i]);
      end
    end
  end

  always@(posedge clk, negedge aresetn) begin

    if(aresetn == 0) begin
      for(i = 0; i < REG_COUNT; i = i + 1) begin
        registers[i] <= 0;
      end
      

    end else if(wr_en == 1 && wr_reg != 0) begin
      registers[wr_reg] <= wr_data;
    end
  end
  

  always@(negedge clk) begin
    if(aresetn == 1) begin
      rd_data_a <= registers[rd_reg_a];
      rd_data_b <= registers[rd_reg_b];
    end
  end
endmodule
module register_file(
  clk,
  aresetn,
  
  rd_reg_a,
  rd_reg_b,
  
  rd_data_a,
  rd_data_b,
  
  wr_en,
  wr_reg,
  wr_data
);


  parameter REG_COUNT = 32;

  parameter REG_W = 32;

  parameter REG_IDX_W = $clog2(REG_COUNT);


  parameter DUMP_VARS = 0;
  parameter DUMP_FILE = "a.vcd";


  input clk;

  input aresetn;


  input [REG_IDX_W - 1:0] rd_reg_a;
  input [REG_IDX_W - 1:0] rd_reg_b;


  output reg [REG_W - 1:0] rd_data_a;
  output reg [REG_W - 1:0] rd_data_b;


  input wr_en;

  input [REG_IDX_W - 1:0] wr_reg;

  input [REG_W - 1:0] wr_data;

  reg [REG_W - 1:0] registers [0:REG_COUNT - 1];

  integer i;

  initial begin
    if(DUMP_VARS == 1) begin
      $dumpfile(DUMP_FILE);
      for(i = 0; i < REG_COUNT; i = i + 1) begin
        $dumpvars(0, registers[i]);
      end
    end
  end

  always@(posedge clk, negedge aresetn) begin

    if(aresetn == 0) begin
      for(i = 0; i < REG_COUNT; i = i + 1) begin
        registers[i] <= 0;
      end
      

    end else if(wr_en == 1 && wr_reg != 0) begin
      registers[wr_reg] <= wr_data;
    end
  end
  

  always@(negedge clk) begin
    if(aresetn == 1) begin
      rd_data_a <= registers[rd_reg_a];
      rd_data_b <= registers[rd_reg_b];
    end
  end
endmodule