data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v
1: b"%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:48: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    .do({open_n18,open_n19,open_n20,led_pad[15]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:48: syntax error, unexpected '(', expecting ')'\n    .do({open_n18,open_n19,open_n20,led_pad[15]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:60: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n35,open_n36,open_n37,led_pad[14]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:60: syntax error, unexpected '(', expecting ')'\n    .do({open_n35,open_n36,open_n37,led_pad[14]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:72: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n52,open_n53,open_n54,led_pad[13]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:72: syntax error, unexpected '(', expecting ')'\n    .do({open_n52,open_n53,open_n54,led_pad[13]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:84: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n69,open_n70,open_n71,led_pad[12]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:84: syntax error, unexpected '(', expecting ')'\n    .do({open_n69,open_n70,open_n71,led_pad[12]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:96: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n86,open_n87,open_n88,led_pad[11]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:96: syntax error, unexpected '(', expecting ')'\n    .do({open_n86,open_n87,open_n88,led_pad[11]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:108: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n103,open_n104,open_n105,led_pad[10]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:108: syntax error, unexpected '(', expecting ')'\n    .do({open_n103,open_n104,open_n105,led_pad[10]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:120: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n120,open_n121,open_n122,led_pad[9]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:120: syntax error, unexpected '(', expecting ')'\n    .do({open_n120,open_n121,open_n122,led_pad[9]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:132: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n137,open_n138,open_n139,led_pad[8]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:132: syntax error, unexpected '(', expecting ')'\n    .do({open_n137,open_n138,open_n139,led_pad[8]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:144: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n154,open_n155,open_n156,led_pad[7]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:144: syntax error, unexpected '(', expecting ')'\n    .do({open_n154,open_n155,open_n156,led_pad[7]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:156: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n171,open_n172,open_n173,led_pad[6]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:156: syntax error, unexpected '(', expecting ')'\n    .do({open_n171,open_n172,open_n173,led_pad[6]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:168: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n188,open_n189,open_n190,led_pad[5]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:168: syntax error, unexpected '(', expecting ')'\n    .do({open_n188,open_n189,open_n190,led_pad[5]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:180: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n205,open_n206,open_n207,led_pad[4]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:180: syntax error, unexpected '(', expecting ')'\n    .do({open_n205,open_n206,open_n207,led_pad[4]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:192: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n222,open_n223,open_n224,led_pad[3]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:192: syntax error, unexpected '(', expecting ')'\n    .do({open_n222,open_n223,open_n224,led_pad[3]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:204: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n239,open_n240,open_n241,led_pad[2]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:204: syntax error, unexpected '(', expecting ')'\n    .do({open_n239,open_n240,open_n241,led_pad[2]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:216: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n256,open_n257,open_n258,led_pad[1]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:216: syntax error, unexpected '(', expecting ')'\n    .do({open_n256,open_n257,open_n258,led_pad[1]}),\n        ^\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:228: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n    .do({open_n273,open_n274,open_n275,led_pad[0]}),\n     ^~\n%Error: data/full_repos/permissive/194847941/demo/2_Buttons&LED/buttons_led_tdpack.v:228: syntax error, unexpected '(', expecting ')'\n    .do({open_n273,open_n274,open_n275,led_pad[0]}),\n        ^\n%Error: Exiting due to 32 error(s)\n"
module rst_n
  (
  clk,
  rst_n
  );

  input clk;
  output rst_n;

  wire [3:0] cnt;
  wire \add0/c1 ;
  wire \add0/c3 ;
  wire n0;

  EG_PHY_MSLICE #(


    .ALUTYPE("ADD_CARRY"),
    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0000000000001010),
    .INIT_LUT1(16'b0110011001101010),
    .MODE("RIPPLE"),
    .REG1_REGSET("SET"),
    .REG1_SD("F"),
    .SRMODE("SYNC"),
    .SRMUX("SR"))
    \reg0_b0|add0/ucin  (
    .a({cnt[0],1'b0}),
    .b({1'b1,open_n0}),
    .clk(clk),
    .sr(n0),
    .fco(\add0/c1 ),
    .q({cnt[0],open_n22}));
  EG_PHY_MSLICE #(


    .ALUTYPE("ADD"),
    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0110011001101010),
    .INIT_LUT1(16'b0110011001101010),
    .MODE("RIPPLE"),
    .REG0_REGSET("SET"),
    .REG0_SD("F"),
    .REG1_REGSET("SET"),
    .REG1_SD("F"),
    .SRMODE("SYNC"),
    .SRMUX("SR"))
    \reg0_b2|reg0_b1  (
    .a(cnt[2:1]),
    .b(2'b00),
    .clk(clk),
    .fci(\add0/c1 ),
    .sr(n0),
    .fco(\add0/c3 ),
    .q(cnt[2:1]));
  EG_PHY_MSLICE #(


    .ALUTYPE("ADD"),
    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0110011001101010),
    .INIT_LUT1(16'b0110011001101010),
    .MODE("RIPPLE"),
    .REG0_REGSET("SET"),
    .REG0_SD("F"),
    .SRMODE("SYNC"),
    .SRMUX("SR"))
    reg0_b3_al_u1 (
    .a({open_n43,cnt[3]}),
    .b({open_n44,1'b0}),
    .clk(clk),
    .fci(\add0/c3 ),
    .sr(n0),
    .q({open_n66,cnt[3]}));
  EG_PHY_LSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUTF0(16'b1000000000000000),
    .INIT_LUTG0(16'b1000000000000000),
    .LSFMUX0("FUNC5"),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("0"))
    rst_n_reg (
    .a({open_n67,cnt[0]}),
    .b({open_n68,cnt[1]}),
    .c({open_n69,cnt[2]}),
    .clk(clk),
    .d({open_n71,cnt[3]}),
    .f({open_n89,n0}),
    .q({open_n93,rst_n}));

endmodule
module rst_n
  (
  clk,
  rst_n
  );


  input clk;
  output rst_n;

  wire [3:0] cnt;
  wire \add0/c1 ;
  wire \add0/c3 ;
  wire n0;

  EG_PHY_MSLICE #(


    .ALUTYPE("ADD_CARRY"),
    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0000000000001010),
    .INIT_LUT1(16'b0110011001101010),
    .MODE("RIPPLE"),
    .REG1_REGSET("SET"),
    .REG1_SD("F"),
    .SRMODE("SYNC"),
    .SRMUX("SR"))
    \reg0_b0|add0/ucin  (
    .a({cnt[0],1'b0}),
    .b({1'b1,open_n0}),
    .clk(clk),
    .sr(n0),
    .fco(\add0/c1 ),
    .q({cnt[0],open_n22}));
  EG_PHY_MSLICE #(


    .ALUTYPE("ADD"),
    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0110011001101010),
    .INIT_LUT1(16'b0110011001101010),
    .MODE("RIPPLE"),
    .REG0_REGSET("SET"),
    .REG0_SD("F"),
    .REG1_REGSET("SET"),
    .REG1_SD("F"),
    .SRMODE("SYNC"),
    .SRMUX("SR"))
    \reg0_b2|reg0_b1  (
    .a(cnt[2:1]),
    .b(2'b00),
    .clk(clk),
    .fci(\add0/c1 ),
    .sr(n0),
    .fco(\add0/c3 ),
    .q(cnt[2:1]));
  EG_PHY_MSLICE #(


    .ALUTYPE("ADD"),
    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUT0(16'b0110011001101010),
    .INIT_LUT1(16'b0110011001101010),
    .MODE("RIPPLE"),
    .REG0_REGSET("SET"),
    .REG0_SD("F"),
    .SRMODE("SYNC"),
    .SRMUX("SR"))
    reg0_b3_al_u1 (
    .a({open_n43,cnt[3]}),
    .b({open_n44,1'b0}),
    .clk(clk),
    .fci(\add0/c3 ),
    .sr(n0),
    .q({open_n66,cnt[3]}));
  EG_PHY_LSLICE #(


    .CEMUX("1"),
    .CLKMUX("CLK"),
    .DFFMODE("FF"),
    .INIT_LUTF0(16'b1000000000000000),
    .INIT_LUTG0(16'b1000000000000000),
    .LSFMUX0("FUNC5"),
    .MODE("LOGIC"),
    .REG0_REGSET("RESET"),
    .REG0_SD("F"),
    .SRMODE("ASYNC"),
    .SRMUX("0"))
    rst_n_reg (
    .a({open_n67,cnt[0]}),
    .b({open_n68,cnt[1]}),
    .c({open_n69,cnt[2]}),
    .clk(clk),
    .d({open_n71,cnt[3]}),
    .f({open_n89,n0}),
    .q({open_n93,rst_n}));

endmodule