data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/fixed_mult.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new/fixed_mult.v:22: Cannot find include file: common.h\n`include "common.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h.v\n             data/full_repos/permissive/191476706/MemN2N.srcs/sources_1/new,data/full_repos/permissive/191476706/common.h.sv\n             common.h\n             common.h.v\n             common.h.sv\n             obj_dir/common.h\n             obj_dir/common.h.v\n             obj_dir/common.h.sv\n%Error: Exiting due to 1 error(s)\n'
module fixed_mult
(

    a,
    b,

    c,
    overflow,
    underflow
);

parameter WL = 32;
parameter IWL = 7;


input wire signed [WL-1:0] a;
input wire signed [WL-1:0] b;


output wire signed [WL-1:0] c;
output wire overflow;
output wire underflow;

assign overflow = 1'b0;
assign underflow = 1'b0;





wire signed [2*WL-1:0] result;








assign result = a*b;


assign c = {result[2*WL-1],result[IWL+2*(WL-IWL-1)-1-:(WL-1)]};

endmodule
module fixed_mult
(

    a,
    b,

    c,
    overflow,
    underflow
);


parameter WL = 32;
parameter IWL = 7;


input wire signed [WL-1:0] a;
input wire signed [WL-1:0] b;


output wire signed [WL-1:0] c;
output wire overflow;
output wire underflow;

assign overflow = 1'b0;
assign underflow = 1'b0;





wire signed [2*WL-1:0] result;








assign result = a*b;


assign c = {result[2*WL-1],result[IWL+2*(WL-IWL-1)-1-:(WL-1)]};

endmodule