data/full_repos/permissive/19818566/hardware/testcases/DCT4/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog/goc_wrapper.v
 line:7: before: ")"
1: b"%Error: data/full_repos/permissive/19818566/hardware/testcases/DCT4/fpga_sim/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog/goc_wrapper.v:7: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: Exiting due to 1 error(s)\n"
module golden_circuit (
clk,
rst,
testVector,
resultVector,
);
input clk;
input rst;
input[63:0] testVector;
output[22:0] resultVector;
dct4 toplevel_instance (
.CK(clk),
.inp(testVector [63:0]),
.outp(resultVector [19:0]),
.outi(resultVector [22:20]));
endmodule
module golden_circuit (
clk,
rst,
testVector,
resultVector,
);

input clk;
input rst;
input[63:0] testVector;
output[22:0] resultVector;
dct4 toplevel_instance (
.CK(clk),
.inp(testVector [63:0]),
.outp(resultVector [19:0]),
.outi(resultVector [22:20]));
endmodule