data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n         ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n                ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) GSR = GSR_int;\n            ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) GSR = GSR_int;\n                   ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) GTS = GTS_int;\n            ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) GTS = GTS_int;\n                   ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) PRLD = PRLD_int;\n            ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) PRLD = PRLD_int;\n                   ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_164
   (\slaveRegDo_mux_0_reg[2] ,
    \slaveRegDo_mux_0_reg[4] ,
    \slaveRegDo_mux_0_reg[1] ,
    Q,
    s_daddr_o,
    \xsdb_reg_reg[2]_0 ,
    \xsdb_reg_reg[4]_0 ,
    s_den_o,
    \captured_samples_reg[14] ,
    s_dclk_o);
  output \slaveRegDo_mux_0_reg[2] ;
  output \slaveRegDo_mux_0_reg[4] ;
  output \slaveRegDo_mux_0_reg[1] ;
  output [11:0]Q;
  input [3:0]s_daddr_o;
  input [1:0]\xsdb_reg_reg[2]_0 ;
  input \xsdb_reg_reg[4]_0 ;
  input s_den_o;
  input [14:0]\captured_samples_reg[14] ;
  input s_dclk_o;

  wire [11:0]Q;
  wire [14:0]\captured_samples_reg[14] ;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire \slaveRegDo_mux_0_reg[1] ;
  wire \slaveRegDo_mux_0_reg[2] ;
  wire \slaveRegDo_mux_0_reg[4] ;
  wire [1:0]\xsdb_reg_reg[2]_0 ;
  wire \xsdb_reg_reg[4]_0 ;
  wire \xsdb_reg_reg_n_0_[1] ;
  wire \xsdb_reg_reg_n_0_[2] ;
  wire \xsdb_reg_reg_n_0_[4] ;

  LUT5 #(
    .INIT(32'hFFFFBABF)) 
    \slaveRegDo_mux_0[1]_i_6 
       (.I0(s_daddr_o[2]),
        .I1(\xsdb_reg_reg_n_0_[1] ),
        .I2(s_daddr_o[0]),
        .I3(\xsdb_reg_reg[2]_0 [0]),
        .I4(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0_reg[1] ));
  LUT6 #(
    .INIT(64'h0000000040444000)) 
    \slaveRegDo_mux_0[2]_i_6 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[3]),
        .I2(\xsdb_reg_reg_n_0_[2] ),
        .I3(s_daddr_o[0]),
        .I4(\xsdb_reg_reg[2]_0 [1]),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0_reg[2] ));
  LUT6 #(
    .INIT(64'hFFBFFFFFFFBF0000)) 
    \slaveRegDo_mux_0[4]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[0]),
        .I2(\xsdb_reg_reg_n_0_[4] ),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[3]),
        .I5(\xsdb_reg_reg[4]_0 ),
        .O(\slaveRegDo_mux_0_reg[4] ));
  FDRE \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [10]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [11]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [12]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [13]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [14]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [1]),
        .Q(\xsdb_reg_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [2]),
        .Q(\xsdb_reg_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [3]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [4]),
        .Q(\xsdb_reg_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [5]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [6]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [7]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [8]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [9]),
        .Q(Q[6]),
        .R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_164
   (\slaveRegDo_mux_0_reg[2] ,
    \slaveRegDo_mux_0_reg[4] ,
    \slaveRegDo_mux_0_reg[1] ,
    Q,
    s_daddr_o,
    \xsdb_reg_reg[2]_0 ,
    \xsdb_reg_reg[4]_0 ,
    s_den_o,
    \captured_samples_reg[14] ,
    s_dclk_o);

  output \slaveRegDo_mux_0_reg[2] ;
  output \slaveRegDo_mux_0_reg[4] ;
  output \slaveRegDo_mux_0_reg[1] ;
  output [11:0]Q;
  input [3:0]s_daddr_o;
  input [1:0]\xsdb_reg_reg[2]_0 ;
  input \xsdb_reg_reg[4]_0 ;
  input s_den_o;
  input [14:0]\captured_samples_reg[14] ;
  input s_dclk_o;

  wire [11:0]Q;
  wire [14:0]\captured_samples_reg[14] ;
  wire [3:0]s_daddr_o;
  wire s_dclk_o;
  wire s_den_o;
  wire \slaveRegDo_mux_0_reg[1] ;
  wire \slaveRegDo_mux_0_reg[2] ;
  wire \slaveRegDo_mux_0_reg[4] ;
  wire [1:0]\xsdb_reg_reg[2]_0 ;
  wire \xsdb_reg_reg[4]_0 ;
  wire \xsdb_reg_reg_n_0_[1] ;
  wire \xsdb_reg_reg_n_0_[2] ;
  wire \xsdb_reg_reg_n_0_[4] ;

  LUT5 #(
    .INIT(32'hFFFFBABF)) 
    \slaveRegDo_mux_0[1]_i_6 
       (.I0(s_daddr_o[2]),
        .I1(\xsdb_reg_reg_n_0_[1] ),
        .I2(s_daddr_o[0]),
        .I3(\xsdb_reg_reg[2]_0 [0]),
        .I4(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0_reg[1] ));
  LUT6 #(
    .INIT(64'h0000000040444000)) 
    \slaveRegDo_mux_0[2]_i_6 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[3]),
        .I2(\xsdb_reg_reg_n_0_[2] ),
        .I3(s_daddr_o[0]),
        .I4(\xsdb_reg_reg[2]_0 [1]),
        .I5(s_daddr_o[1]),
        .O(\slaveRegDo_mux_0_reg[2] ));
  LUT6 #(
    .INIT(64'hFFBFFFFFFFBF0000)) 
    \slaveRegDo_mux_0[4]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[0]),
        .I2(\xsdb_reg_reg_n_0_[4] ),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[3]),
        .I5(\xsdb_reg_reg[4]_0 ),
        .O(\slaveRegDo_mux_0_reg[4] ));
  FDRE \xsdb_reg_reg[0] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[10] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [10]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[11] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [11]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[12] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [12]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[13] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [13]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[14] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [14]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[1] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [1]),
        .Q(\xsdb_reg_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[2] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [2]),
        .Q(\xsdb_reg_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[3] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [3]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[4] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [4]),
        .Q(\xsdb_reg_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \xsdb_reg_reg[5] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [5]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[6] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [6]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[7] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [7]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[8] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [8]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \xsdb_reg_reg[9] 
       (.C(s_dclk_o),
        .CE(s_den_o),
        .D(\captured_samples_reg[14] [9]),
        .Q(Q[6]),
        .R(1'b0));
endmodule