data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/fifo_1clk.v
None: at end of input
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo/fifo_1clk.v:25: Cannot find include file: util.vh\n`include "util.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/fifo,data/full_repos/permissive/181738725/util.vh.sv\n             util.vh\n             util.vh.v\n             util.vh.sv\n             obj_dir/util.vh\n             obj_dir/util.vh.v\n             obj_dir/util.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module fifo_1clk(clk, rst, wr_en, wr_data, full, rd_en, rd_data, empty, used);
`include "util.vh"
  parameter                 Width     = 8;
  parameter                 Depth     = 128;

  localparam                AddrBits  = clog2(Depth);
  localparam                UsedBits  = clog2(Depth+1);

  input                     clk;
  input                     rst;

  input                     wr_en;
  input  [Width-1:0]        wr_data;
  output                    full;

  input                     rd_en;
  output [Width-1:0]        rd_data;
  output reg                empty;

  output reg [UsedBits-1:0] used;



  function automatic [AddrBits:0] inc(input en, input phase,
                                      input [AddrBits-1:0] addr);
    reg [AddrBits-1:0] addr_n;
    reg                phase_n;
    begin
      addr_n  = addr;
      phase_n = phase;
      if (en) begin
        if (addr == Depth-1) begin
          addr_n  = 0;
          phase_n = ~phase;
        end else begin
          addr_n = addr + 1;
        end
      end
      inc = {phase_n, addr_n};
    end
  endfunction




  reg  [AddrBits-1:0]  rd_addr,     wr_addr;
  wire [AddrBits-1:0]  rd_addr_n,   wr_addr_n;
  reg                  rd_phase,    wr_phase;
  wire                 rd_phase_n,  wr_phase_n;

  assign {rd_phase_n, rd_addr_n} = inc(rd_en, rd_phase, rd_addr);
  assign {wr_phase_n, wr_addr_n} = inc(wr_en, wr_phase, wr_addr);

  always @(posedge clk) begin
    if (rst) begin
      {rd_phase, rd_addr} <= 0;
      {wr_phase, wr_addr} <= 0;
    end else begin
      {rd_phase, rd_addr} <= {rd_phase_n, rd_addr_n};
      {wr_phase, wr_addr} <= {wr_phase_n, wr_addr_n};
    end
  end




  ram_1c_1r_1w #(
    .Depth (Depth),
    .Width (Width),
    .ReportCollision(0))
  ram (
    .clk     (clk),
    .wr_en   (wr_en),
    .wr_addr (wr_addr),
    .wr_data (wr_data),
    .rd_addr (rd_addr_n),
    .rd_data (rd_data)
    );







  wire   empty_i  = (rd_addr_n == wr_addr && rd_phase_n == wr_phase);
  assign full     = (rd_addr   == wr_addr && rd_phase   != wr_phase);

  always @(posedge clk) begin
    if (rst) begin
      empty <= 1;
      used  <= 0;
    end else begin
      used  <= used + wr_en - rd_en;
      empty <= empty_i;
    end
  end

endmodule
module fifo_1clk(clk, rst, wr_en, wr_data, full, rd_en, rd_data, empty, used);

`include "util.vh"
  parameter                 Width     = 8;
  parameter                 Depth     = 128;

  localparam                AddrBits  = clog2(Depth);
  localparam                UsedBits  = clog2(Depth+1);

  input                     clk;
  input                     rst;

  input                     wr_en;
  input  [Width-1:0]        wr_data;
  output                    full;

  input                     rd_en;
  output [Width-1:0]        rd_data;
  output reg                empty;

  output reg [UsedBits-1:0] used;



  function automatic [AddrBits:0] inc(input en, input phase,
                                      input [AddrBits-1:0] addr);
    reg [AddrBits-1:0] addr_n;
    reg                phase_n;
    begin
      addr_n  = addr;
      phase_n = phase;
      if (en) begin
        if (addr == Depth-1) begin
          addr_n  = 0;
          phase_n = ~phase;
        end else begin
          addr_n = addr + 1;
        end
      end
      inc = {phase_n, addr_n};
    end
  endfunction




  reg  [AddrBits-1:0]  rd_addr,     wr_addr;
  wire [AddrBits-1:0]  rd_addr_n,   wr_addr_n;
  reg                  rd_phase,    wr_phase;
  wire                 rd_phase_n,  wr_phase_n;

  assign {rd_phase_n, rd_addr_n} = inc(rd_en, rd_phase, rd_addr);
  assign {wr_phase_n, wr_addr_n} = inc(wr_en, wr_phase, wr_addr);

  always @(posedge clk) begin
    if (rst) begin
      {rd_phase, rd_addr} <= 0;
      {wr_phase, wr_addr} <= 0;
    end else begin
      {rd_phase, rd_addr} <= {rd_phase_n, rd_addr_n};
      {wr_phase, wr_addr} <= {wr_phase_n, wr_addr_n};
    end
  end




  ram_1c_1r_1w #(
    .Depth (Depth),
    .Width (Width),
    .ReportCollision(0))
  ram (
    .clk     (clk),
    .wr_en   (wr_en),
    .wr_addr (wr_addr),
    .wr_data (wr_data),
    .rd_addr (rd_addr_n),
    .rd_data (rd_data)
    );







  wire   empty_i  = (rd_addr_n == wr_addr && rd_phase_n == wr_phase);
  assign full     = (rd_addr   == wr_addr && rd_phase   != wr_phase);

  always @(posedge clk) begin
    if (rst) begin
      empty <= 1;
      used  <= 0;
    end else begin
      used  <= used + wr_en - rd_en;
      empty <= empty_i;
    end
  end

endmodule