data/full_repos/permissive/152229899/FIFO/FIFO.v
 line:18: before: "wr_en"
1: b'%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:219: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk=~clk; \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:225: Unsupported: Ignoring delay on this delayed statement.\n    #100 rst=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:231: Unsupported: Ignoring delay on this delayed statement.\n    #20 data_in[7:0]=8\'b11001100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:232: Unsupported: Ignoring delay on this delayed statement.\n    #20 data_in[7:0]=8\'b11111111;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:234: Unsupported: Ignoring delay on this delayed statement.\n    #20 wr_en=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:236: Unsupported: Ignoring delay on this delayed statement.\n    #80 rd_en=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:239: Unsupported: Ignoring delay on this delayed statement.\n    #100 rst=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:246: Unsupported: Ignoring delay on this delayed statement.\n        #20 data_in[7:0]=8\'b00000000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:247: Unsupported: Ignoring delay on this delayed statement.\n        #20 data_in[7:0]=8\'b10101010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:248: Unsupported: Ignoring delay on this delayed statement.\n        #20 data_in[7:0]=8\'b11001100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:249: Unsupported: Ignoring delay on this delayed statement.\n        #20 data_in[7:0]=8\'b11111111; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:252: Unsupported: Ignoring delay on this delayed statement.\n    #1000 wr_en=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:253: Unsupported: Ignoring delay on this delayed statement.\n    #10 rd_en=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/152229899/FIFO/FIFO.v:255: Unsupported: Ignoring delay on this delayed statement.\n    #2000 rst=0; \n    ^\n%Error: data/full_repos/permissive/152229899/FIFO/FIFO.v:8: Input/output/inout does not appear in port list: \'wr_addr\'\n  input [5:0]wr_addr; \n             ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/152229899/FIFO/FIFO.v:186: Signal definition not found, creating implicitly: \'full\'\n                            .full(full), \n                                  ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/152229899/FIFO/FIFO.v:190: Signal definition not found, creating implicitly: \'empty\'\n                            .empty(empty), \n                                   ^~~~~\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifo_syn_ram(clk,wr_en,                   
                    rd_en, 
                    rd_addr, 
                    data_in, 
                    data_out);
  input clk,wr_en,rd_en; 
  input [5:0]wr_addr; 
  input [5:0]rd_addr; 
  input [7:0]data_in; 
  output [7:0]data_out; 
     
  reg [7:0]data_out; 
  reg [7:0]ram[63:0]; 
  wire clk,wr_en,rd_en; 
  wire [7:0]data_in; 
  
  always@(posedge clk or wr_en) 
    begin 
      if(wr_en)
        begin 
          ram[wr_addr]<=data_in; 
        end 
    end 
  always@(posedge clk or rd_en) 
    begin 
      if(rd_en)
        begin 
            data_out<=ram[rd_addr]; 
        end 
    end 
endmodule
module fifo_syn_ram(clk,wr_en,                   
                    rd_en, 
                    rd_addr, 
                    data_in, 
                    data_out);

  input clk,wr_en,rd_en; 
  input [5:0]wr_addr; 
  input [5:0]rd_addr; 
  input [7:0]data_in; 
  output [7:0]data_out; 
     
  reg [7:0]data_out; 
  reg [7:0]ram[63:0]; 
  wire clk,wr_en,rd_en; 
  wire [7:0]data_in; 
  
  always@(posedge clk or wr_en) 
    begin 
      if(wr_en)
        begin 
          ram[wr_addr]<=data_in; 
        end 
    end 
  always@(posedge clk or rd_en) 
    begin 
      if(rd_en)
        begin 
            data_out<=ram[rd_addr]; 
        end 
    end 
endmodule