data/full_repos/permissive/211471959/src/hdl/clock_divider.v
 line:26: before: "="
data/verilator_xmls/0ba57c72-d70e-4552-bd20-b7fb41f549da.xml
module clock_divider(
    input clk,
    input reset,
    output reg CLK_2_HZ = 0
    );
    integer count_2_HZ = 0;
    always @(posedge clk, posedge reset) begin
        if(reset) begin
            count_2_HZ <= 0;
            CLK_2_HZ <= 0;
        end
        else begin
            if(count_2_HZ == 2500000) begin
                count_2_HZ <= 0;
                CLK_2_HZ <= ~CLK_2_HZ;
            end
            else
                count_2_HZ <= count_2_HZ + 1;
        end
    end
endmodule
module clock_divider(
    input clk,
    input reset,
    output reg CLK_2_HZ = 0
    );

    integer count_2_HZ = 0;
    always @(posedge clk, posedge reset) begin
        if(reset) begin
            count_2_HZ <= 0;
            CLK_2_HZ <= 0;
        end
        else begin
            if(count_2_HZ == 2500000) begin
                count_2_HZ <= 0;
                CLK_2_HZ <= ~CLK_2_HZ;
            end
            else
                count_2_HZ <= count_2_HZ + 1;
        end
    end
endmodule