data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/axi/axi_fast_extract_tlast.v
data/verilator_xmls/a47cdff5-2641-4575-ab9c-82eba82f7b94.xml
module axi_fast_extract_tlast
  #(parameter WIDTH=64)
  (
   input clk,
   input reset,
   input clear,

   input [WIDTH-1:0] i_tdata,
   input i_tvalid,
   output reg i_tready,

   output [WIDTH-1:0] o_tdata,
   output o_tlast,
   output reg o_tvalid,
   input  o_tready
   );

   reg [WIDTH:0] data_reg1, data_reg2;

   reg [1:0] 	   fifo_state;
   
   localparam EMPTY = 0;
   localparam HALF = 1;
   localparam FULL = 2;

   reg [1:0]  extract_state;
   
   localparam IDLE = 0;
   localparam EXTRACT1 = 1;
   localparam EXTRACT2 = 2;
   localparam EXTRACT3 = 3;

   
   always @(posedge clk) 
     if (reset | clear) begin
	fifo_state <= EMPTY;
     end else begin
	case (fifo_state)



	  EMPTY: begin
	     if ((extract_state == IDLE) && (i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin

		extract_state <= EXTRACT1;
		i_tready <= 1'b1;
		o_tvalid <= 1'b0;
		fifo_state <= EMPTY;
	     end else if ((extract_state == EXTRACT1) && i_tvalid) begin

		i_tready <= 1'b1;
		o_tvalid <= 1'b0;
		fifo_state <= EMPTY;
		if (i_tdata[31:0] == 'h1) begin
		   extract_state <= EXTRACT2;
		end else begin
		   extract_state <= EXTRACT3;
		end
	     end else if ((extract_state == EXTRACT2) && i_tvalid) begin

		data_reg1 <= {1'b1,i_tdata};
		i_tready <= 1'b1;
		o_tvalid <= 1'b1;
		fifo_state <= HALF;
		extract_state <= IDLE;
	     end else if (i_tvalid) begin

		data_reg1 <= {1'b0,i_tdata};
		fifo_state <= HALF;
		extract_state <= IDLE;
		i_tready <= 1'b1;
		o_tvalid <= 1'b1;
	     end else begin

		fifo_state <= EMPTY;
		i_tready <= 1'b1;
		o_tvalid <= 1'b0;
	     end
	  end



	  HALF: begin
	     if ((extract_state == IDLE) && (i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin

		extract_state <= EXTRACT1;
		if (o_tready) begin

		   i_tready <= 1'b1;
		   o_tvalid <= 1'b0;
		   fifo_state <= EMPTY;
		end else begin

		   fifo_state <= HALF;
		   i_tready <= 1'b1;
		   o_tvalid <= 1'b1;
		end
	     end else if ((extract_state == EXTRACT1) && i_tvalid) begin

		if (i_tdata[31:0] == 'h1) begin
		   extract_state <= EXTRACT2;
		end else begin
		   extract_state <= EXTRACT3;
		end
		if (o_tready) begin

		   i_tready <= 1'b1;
		   o_tvalid <= 1'b0;
		   fifo_state <= EMPTY;
		end else begin

		   fifo_state <= HALF;
		   i_tready <= 1'b1;
		   o_tvalid <= 1'b1;
		end		
	     end else if ((extract_state == EXTRACT2) && i_tvalid) begin

		data_reg1 <= {1'b1,i_tdata};
		extract_state <= IDLE;
		if (o_tready) begin

		   i_tready <= 1'b1;
		   o_tvalid <= 1'b1;
		   fifo_state <= HALF;
		end else begin

		   data_reg2 <= data_reg1;
		   i_tready <= 1'b0;
		   o_tvalid <= 1'b1;
		   fifo_state <= FULL;
		end	
	     end else if (i_tvalid) begin

		data_reg1 <= {1'b0,i_tdata};
		extract_state <= IDLE;
		if (o_tready) begin

		   fifo_state <= HALF;
		   i_tready <= 1'b1;
		   o_tvalid <= 1'b1;
		end else begin

		   data_reg2 <= data_reg1;
		   i_tready <= 1'b0;
		   o_tvalid <= 1'b1;
		   fifo_state <= FULL;
		end	
	     end else if (o_tready) begin

		fifo_state <= EMPTY;
		i_tready <= 1'b1;
		o_tvalid <= 1'b0;
	     end else begin

		fifo_state <= HALF;
		i_tready <= 1'b1;
		o_tvalid <= 1'b1;
	     end
	  end



	  FULL: begin
	     if (o_tready) begin
		fifo_state <= HALF;
		i_tready <= 1'b1;
		o_tvalid <= 1'b1;
	     end
	     else begin
		fifo_state <= FULL;
		i_tready <= 1'b0;
		o_tvalid <= 1'b1;
	     end
	  end
	endcase
     end
   
   assign {o_tlast,o_tdata} = (fifo_state == FULL) ? data_reg2 : data_reg1;
   

endmodule
module axi_fast_extract_tlast
  #(parameter WIDTH=64)
  (
   input clk,
   input reset,
   input clear,

   input [WIDTH-1:0] i_tdata,
   input i_tvalid,
   output reg i_tready,

   output [WIDTH-1:0] o_tdata,
   output o_tlast,
   output reg o_tvalid,
   input  o_tready
   );


   reg [WIDTH:0] data_reg1, data_reg2;

   reg [1:0] 	   fifo_state;
   
   localparam EMPTY = 0;
   localparam HALF = 1;
   localparam FULL = 2;

   reg [1:0]  extract_state;
   
   localparam IDLE = 0;
   localparam EXTRACT1 = 1;
   localparam EXTRACT2 = 2;
   localparam EXTRACT3 = 3;

   
   always @(posedge clk) 
     if (reset | clear) begin
	fifo_state <= EMPTY;
     end else begin
	case (fifo_state)



	  EMPTY: begin
	     if ((extract_state == IDLE) && (i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin

		extract_state <= EXTRACT1;
		i_tready <= 1'b1;
		o_tvalid <= 1'b0;
		fifo_state <= EMPTY;
	     end else if ((extract_state == EXTRACT1) && i_tvalid) begin

		i_tready <= 1'b1;
		o_tvalid <= 1'b0;
		fifo_state <= EMPTY;
		if (i_tdata[31:0] == 'h1) begin
		   extract_state <= EXTRACT2;
		end else begin
		   extract_state <= EXTRACT3;
		end
	     end else if ((extract_state == EXTRACT2) && i_tvalid) begin

		data_reg1 <= {1'b1,i_tdata};
		i_tready <= 1'b1;
		o_tvalid <= 1'b1;
		fifo_state <= HALF;
		extract_state <= IDLE;
	     end else if (i_tvalid) begin

		data_reg1 <= {1'b0,i_tdata};
		fifo_state <= HALF;
		extract_state <= IDLE;
		i_tready <= 1'b1;
		o_tvalid <= 1'b1;
	     end else begin

		fifo_state <= EMPTY;
		i_tready <= 1'b1;
		o_tvalid <= 1'b0;
	     end
	  end



	  HALF: begin
	     if ((extract_state == IDLE) && (i_tdata == 64'hDEADBEEFFEEDCAFE) && i_tvalid) begin

		extract_state <= EXTRACT1;
		if (o_tready) begin

		   i_tready <= 1'b1;
		   o_tvalid <= 1'b0;
		   fifo_state <= EMPTY;
		end else begin

		   fifo_state <= HALF;
		   i_tready <= 1'b1;
		   o_tvalid <= 1'b1;
		end
	     end else if ((extract_state == EXTRACT1) && i_tvalid) begin

		if (i_tdata[31:0] == 'h1) begin
		   extract_state <= EXTRACT2;
		end else begin
		   extract_state <= EXTRACT3;
		end
		if (o_tready) begin

		   i_tready <= 1'b1;
		   o_tvalid <= 1'b0;
		   fifo_state <= EMPTY;
		end else begin

		   fifo_state <= HALF;
		   i_tready <= 1'b1;
		   o_tvalid <= 1'b1;
		end		
	     end else if ((extract_state == EXTRACT2) && i_tvalid) begin

		data_reg1 <= {1'b1,i_tdata};
		extract_state <= IDLE;
		if (o_tready) begin

		   i_tready <= 1'b1;
		   o_tvalid <= 1'b1;
		   fifo_state <= HALF;
		end else begin

		   data_reg2 <= data_reg1;
		   i_tready <= 1'b0;
		   o_tvalid <= 1'b1;
		   fifo_state <= FULL;
		end	
	     end else if (i_tvalid) begin

		data_reg1 <= {1'b0,i_tdata};
		extract_state <= IDLE;
		if (o_tready) begin

		   fifo_state <= HALF;
		   i_tready <= 1'b1;
		   o_tvalid <= 1'b1;
		end else begin

		   data_reg2 <= data_reg1;
		   i_tready <= 1'b0;
		   o_tvalid <= 1'b1;
		   fifo_state <= FULL;
		end	
	     end else if (o_tready) begin

		fifo_state <= EMPTY;
		i_tready <= 1'b1;
		o_tvalid <= 1'b0;
	     end else begin

		fifo_state <= HALF;
		i_tready <= 1'b1;
		o_tvalid <= 1'b1;
	     end
	  end



	  FULL: begin
	     if (o_tready) begin
		fifo_state <= HALF;
		i_tready <= 1'b1;
		o_tvalid <= 1'b1;
	     end
	     else begin
		fifo_state <= FULL;
		i_tready <= 1'b0;
		o_tvalid <= 1'b1;
	     end
	  end
	endcase
     end
   
   assign {o_tlast,o_tdata} = (fifo_state == FULL) ? data_reg2 : data_reg1;
   

endmodule