data/full_repos/permissive/104269513/pipeline_dualCF.v
 line:168: before: "integer"
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline_dualCF.v:691: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/pipeline_dualCF.v:696: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 0;\n ^\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:177: Cannot find file containing module: \'datapath\'\ndatapath dp  (   \n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.v\n             data/full_repos/permissive/104269513,data/full_repos/permissive/104269513/datapath.sv\n             datapath\n             datapath.v\n             datapath.sv\n             obj_dir/datapath\n             obj_dir/datapath.v\n             obj_dir/datapath.sv\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:223: Cannot find file containing module: \'ALU_ctrl\'\nALU_ctrl EX_ALU (\n^~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:231: Cannot find file containing module: \'control\'\ncontrol ctrl (\n^~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:294: Cannot find file containing module: \'convert_fifo\'\nconvert_fifo fifo_dm  ( \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104269513/pipeline_dualCF.v:674: Cannot find file containing module: \'regfile\'\nregfile op_reg(\n^~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pipeline_dualCF_tb();


reg clk, rst;




wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;


wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;


reg out_rdy, in_wr;
wire in_rdy, out_wr;
	

integer count,fq;
integer i, counter_restart;


reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;


reg[4:0] reg_wa;


pipeline_dualCF PL_2CF 	(

				.in_data(fifo_data_in),
				.in_ctrl(fifo_ctrl_in),
				.out_data(fifo_data_out),
				.out_ctrl(fifo_ctrl_out),


				.out_rdy(out_rdy),
				.in_wr(in_wr),
				.in_rdy(in_rdy),
				.out_wr(out_wr),
				

				.IorD(),
				.Addr_in(),
				.Data_In(),
				

				.Addr_DM(),
				.Addr_IM(),		
				.Data_out_IM(),
				.Data_out_DM(),
				.full(),
				.nearly_full(),			
				.nearly_empty(),			
				.empty(),			
				.fifo_busy(),			
				.packet_count(),			
				.FIFO_RD_addr(),
				.FIFO_WR_addr(),
				.fifo_state(),
				.DEPTH(),
				.PL_EN(),
				.SW_CTRL(),
				.fifo_rd_en(),
				.fifo_wr_en(),
				

				.Master_reg(),
				

				.clk(clk),
				.rst(rst)
				);
				
			
regfile op_reg(
				.clk(clk),
				.rst(rst),
				.r0addr(),
				.r1addr(),
				.waddr(reg_wa),
				.wdata(fifo_data_out),
				.wena(out_wr),
				.r0data(),
				.r1data()
			   );
			   
assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];

initial begin
	
	clk = 0;
	forever	#10	clk = ~clk;
end
	
initial begin
	rst = 1;
	#30	rst = 0;

end
	
initial begin

	count = 0;
	out_rdy = 1;
	in_wr = 0;
	counter_restart = 25;
	reg_wa = 0;
	reg_ra = 0;
	
	$readmemh ("ip_reg_init_var_pckt.txt", ip_reg);
end				

always @ (posedge clk)
	begin
		count <= count + 1;
		

		if (count > 2)
		begin
			if (in_rdy && fifo_ctrl_in != 'hab)
				begin
					in_wr <= 1;
					if (in_wr)
						reg_ra <= reg_ra + 1;
				end
			else 
				begin
					reg_ra <= reg_ra;
					in_wr <= 0;
				end
		end
		

			


		





		





		
		else if (count == 200 )
			begin
				out_rdy <= 0;
				in_wr <= 0;
			end
		

		if(out_wr)
			reg_wa <= reg_wa +1;
		else 
			reg_wa <= reg_wa;
	end

endmodule
module pipeline_dualCF_tb();



reg clk, rst;




wire [63:0] fifo_data_in;
wire [7:0] fifo_ctrl_in;


wire [63:0] fifo_data_out;
wire [7:0] fifo_ctrl_out;


reg out_rdy, in_wr;
wire in_rdy, out_wr;
	

integer count,fq;
integer i, counter_restart;


reg [71:0] ip_reg [255:0];
reg [7:0] reg_ra;


reg[4:0] reg_wa;


pipeline_dualCF PL_2CF 	(

				.in_data(fifo_data_in),
				.in_ctrl(fifo_ctrl_in),
				.out_data(fifo_data_out),
				.out_ctrl(fifo_ctrl_out),


				.out_rdy(out_rdy),
				.in_wr(in_wr),
				.in_rdy(in_rdy),
				.out_wr(out_wr),
				

				.IorD(),
				.Addr_in(),
				.Data_In(),
				

				.Addr_DM(),
				.Addr_IM(),		
				.Data_out_IM(),
				.Data_out_DM(),
				.full(),
				.nearly_full(),			
				.nearly_empty(),			
				.empty(),			
				.fifo_busy(),			
				.packet_count(),			
				.FIFO_RD_addr(),
				.FIFO_WR_addr(),
				.fifo_state(),
				.DEPTH(),
				.PL_EN(),
				.SW_CTRL(),
				.fifo_rd_en(),
				.fifo_wr_en(),
				

				.Master_reg(),
				

				.clk(clk),
				.rst(rst)
				);
				
			
regfile op_reg(
				.clk(clk),
				.rst(rst),
				.r0addr(),
				.r1addr(),
				.waddr(reg_wa),
				.wdata(fifo_data_out),
				.wena(out_wr),
				.r0data(),
				.r1data()
			   );
			   
assign {fifo_ctrl_in,fifo_data_in} = ip_reg[reg_ra];

initial begin
	
	clk = 0;
	forever	#10	clk = ~clk;
end
	
initial begin
	rst = 1;
	#30	rst = 0;

end
	
initial begin

	count = 0;
	out_rdy = 1;
	in_wr = 0;
	counter_restart = 25;
	reg_wa = 0;
	reg_ra = 0;
	
	$readmemh ("ip_reg_init_var_pckt.txt", ip_reg);
end				

always @ (posedge clk)
	begin
		count <= count + 1;
		

		if (count > 2)
		begin
			if (in_rdy && fifo_ctrl_in != 'hab)
				begin
					in_wr <= 1;
					if (in_wr)
						reg_ra <= reg_ra + 1;
				end
			else 
				begin
					reg_ra <= reg_ra;
					in_wr <= 0;
				end
		end
		

			


		





		





		
		else if (count == 200 )
			begin
				out_rdy <= 0;
				in_wr <= 0;
			end
		

		if(out_wr)
			reg_wa <= reg_wa +1;
		else 
			reg_wa <= reg_wa;
	end

endmodule