data/full_repos/permissive/163534413/Abs8.v
data/verilator_xmls/58a077c1-f46e-4a34-a385-b8bd8891d209.xml
module Abs8(X,Y,Neg);

	input [7:0] X;
	output [7:0] Y;
	output Neg;
	
	assign Neg = X[7];
	assign Y = Neg ? -X : X;

endmodule
module Abs8(X,Y,Neg);


	input [7:0] X;
	output [7:0] Y;
	output Neg;
	
	assign Neg = X[7];
	assign Y = Neg ? -X : X;

endmodule