data/full_repos/permissive/131921633/tv/top.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/top.v:1: Cannot find include file: Mips/mips_pipeline.v\n`include "Mips/mips_pipeline.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv,data/full_repos/permissive/131921633/Mips/mips_pipeline.v\n             data/full_repos/permissive/131921633/tv,data/full_repos/permissive/131921633/Mips/mips_pipeline.v.v\n             data/full_repos/permissive/131921633/tv,data/full_repos/permissive/131921633/Mips/mips_pipeline.v.sv\n             Mips/mips_pipeline.v\n             Mips/mips_pipeline.v.v\n             Mips/mips_pipeline.v.sv\n             obj_dir/Mips/mips_pipeline.v\n             obj_dir/Mips/mips_pipeline.v.v\n             obj_dir/Mips/mips_pipeline.v.sv\n%Error: data/full_repos/permissive/131921633/tv/top.v:2: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/top.v:3: Cannot find include file: Util/Math.v\n`include "Util/Math.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/top.v:10: Define or directive not defined: \'`Data_Control_Control_T\'\n ( `Data_Control_Control_T(input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/top.v:10: syntax error, unexpected \'(\', expecting \'[\'\n ( `Data_Control_Control_T(input) ctrl\n                           ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/top.v:11: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T(output) pcAddr\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/top.v:14: Define or directive not defined: \'`Util_Math_log2_expr\'\n`Util_Math_log2_expr\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module top #
	( parameter FILE = "asm/old/test0.mif"
	, parameter ADDR_L = 64
	, parameter ADDR_W = Util_Math_log2(ADDR_L)
	)
	( `Data_Control_Control_T(input) ctrl
	, `Mips_Type_Word_T(output) pcAddr
	);

`Util_Math_log2_expr

Mips_mips_pipeline #
	( .FILE   (FILE)
	, .ADDR_L (ADDR_L)
	, .ADDR_W (ADDR_W)
	) MIPS
	( .ctrl (ctrl)
	, .pcAddr (pcAddr)
	);

endmodule
module top #
	( parameter FILE = "asm/old/test0.mif"
	, parameter ADDR_L = 64
	, parameter ADDR_W = Util_Math_log2(ADDR_L)
	)
	( `Data_Control_Control_T(input) ctrl
	, `Mips_Type_Word_T(output) pcAddr
	);


`Util_Math_log2_expr

Mips_mips_pipeline #
	( .FILE   (FILE)
	, .ADDR_L (ADDR_L)
	, .ADDR_W (ADDR_W)
	) MIPS
	( .ctrl (ctrl)
	, .pcAddr (pcAddr)
	);

endmodule