data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/core/axis_ctrl_endpoint.v
 line:115: before: "("
1: b'%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/core/axis_ctrl_endpoint.v:54: Cannot find include file: rfnoc_chdr_utils.vh\n  `include "rfnoc_chdr_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/core,data/full_repos/permissive/214858095/rfnoc_chdr_utils.vh\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/core,data/full_repos/permissive/214858095/rfnoc_chdr_utils.vh.v\n             data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/core,data/full_repos/permissive/214858095/rfnoc_chdr_utils.vh.sv\n             rfnoc_chdr_utils.vh\n             rfnoc_chdr_utils.vh.v\n             rfnoc_chdr_utils.vh.sv\n             obj_dir/rfnoc_chdr_utils.vh\n             obj_dir/rfnoc_chdr_utils.vh.v\n             obj_dir/rfnoc_chdr_utils.vh.sv\n%Error: data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/rfnoc/core/axis_ctrl_endpoint.v:55: Cannot find include file: rfnoc_axis_ctrl_utils.vh\n  `include "rfnoc_axis_ctrl_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module axis_ctrl_endpoint #(
  parameter       SYNC_CLKS       = 0,
  parameter       SLAVE_FIFO_SIZE = 5
)(

  input  wire         rfnoc_ctrl_clk,
  input  wire         rfnoc_ctrl_rst,
  input  wire         axis_ctrl_clk,
  input  wire         axis_ctrl_rst,

  input  wire [31:0]  s_rfnoc_ctrl_tdata,
  input  wire         s_rfnoc_ctrl_tlast,
  input  wire         s_rfnoc_ctrl_tvalid,
  output wire         s_rfnoc_ctrl_tready,
  output wire [31:0]  m_rfnoc_ctrl_tdata,
  output wire         m_rfnoc_ctrl_tlast,
  output wire         m_rfnoc_ctrl_tvalid,
  input  wire         m_rfnoc_ctrl_tready,

  input  wire [31:0]  s_axis_ctrl_tdata,
  input  wire         s_axis_ctrl_tlast,
  input  wire         s_axis_ctrl_tvalid,
  output wire         s_axis_ctrl_tready,
  output wire [31:0]  m_axis_ctrl_tdata,
  output wire         m_axis_ctrl_tlast,
  output wire         m_axis_ctrl_tvalid,
  input  wire         m_axis_ctrl_tready
);




  `include "rfnoc_chdr_utils.vh"
  `include "rfnoc_axis_ctrl_utils.vh"





  wire [31:0] i_ctrl_tdata;
  wire        i_ctrl_tlast, i_ctrl_tvalid, i_ctrl_tready;

  generate
    if (SYNC_CLKS) begin
      axi_fifo #(.WIDTH(32+1), .SIZE(SLAVE_FIFO_SIZE)) in_fifo_i (
        .clk(axis_ctrl_clk), .reset(axis_ctrl_rst), .clear(1'b0),
        .i_tdata({s_rfnoc_ctrl_tlast, s_rfnoc_ctrl_tdata}),
        .i_tvalid(s_rfnoc_ctrl_tvalid), .i_tready(s_rfnoc_ctrl_tready),
        .o_tdata({i_ctrl_tlast, i_ctrl_tdata}),
        .o_tvalid(i_ctrl_tvalid), .o_tready(i_ctrl_tready),
        .space(), .occupied()
      );

      axi_fifo #(.WIDTH(32+1), .SIZE(1)) out_fifo_i (
        .clk(axis_ctrl_clk), .reset(axis_ctrl_rst), .clear(1'b0),
        .i_tdata({s_axis_ctrl_tlast, s_axis_ctrl_tdata}),
        .i_tvalid(s_axis_ctrl_tvalid), .i_tready(s_axis_ctrl_tready),
        .o_tdata({m_rfnoc_ctrl_tlast, m_rfnoc_ctrl_tdata}),
        .o_tvalid(m_rfnoc_ctrl_tvalid), .o_tready(m_rfnoc_ctrl_tready),
        .space(), .occupied()
      );
    end else begin
      axi_fifo_2clk #(.WIDTH(32+1), .SIZE(SLAVE_FIFO_SIZE), .PIPELINE("NONE")) in_fifo_i (
        .reset(rfnoc_ctrl_rst),
        .i_aclk(rfnoc_ctrl_clk),
        .i_tdata({s_rfnoc_ctrl_tlast, s_rfnoc_ctrl_tdata}),
        .i_tvalid(s_rfnoc_ctrl_tvalid), .i_tready(s_rfnoc_ctrl_tready),
        .o_aclk(axis_ctrl_clk),
        .o_tdata({i_ctrl_tlast, i_ctrl_tdata}),
        .o_tvalid(i_ctrl_tvalid), .o_tready(i_ctrl_tready)
      );

      axi_fifo_2clk #(.WIDTH(32+1), .SIZE(1), .PIPELINE("NONE")) out_fifo_i (
        .reset(axis_ctrl_rst),
        .i_aclk(axis_ctrl_clk),
        .i_tdata({s_axis_ctrl_tlast, s_axis_ctrl_tdata}),
        .i_tvalid(s_axis_ctrl_tvalid), .i_tready(s_axis_ctrl_tready),
        .o_aclk(rfnoc_ctrl_clk),
        .o_tdata({m_rfnoc_ctrl_tlast, m_rfnoc_ctrl_tdata}),
        .o_tvalid(m_rfnoc_ctrl_tvalid), .o_tready(m_rfnoc_ctrl_tready)
      );
    end
  endgenerate

  axi_fifo #(.WIDTH(32+1), .SIZE(1)) slv_pipe_i (
    .clk(axis_ctrl_clk), .reset(axis_ctrl_rst), .clear(1'b0),
    .i_tdata({i_ctrl_tlast, i_ctrl_tdata}),
    .i_tvalid(i_ctrl_tvalid), .i_tready(i_ctrl_tready),
    .o_tdata({m_axis_ctrl_tlast, m_axis_ctrl_tdata}),
    .o_tvalid(m_axis_ctrl_tvalid), .o_tready(m_axis_ctrl_tready),
    .space(), .occupied()
  );

endmodule
module axis_ctrl_endpoint #(
  parameter       SYNC_CLKS       = 0,
  parameter       SLAVE_FIFO_SIZE = 5
)(

  input  wire         rfnoc_ctrl_clk,
  input  wire         rfnoc_ctrl_rst,
  input  wire         axis_ctrl_clk,
  input  wire         axis_ctrl_rst,

  input  wire [31:0]  s_rfnoc_ctrl_tdata,
  input  wire         s_rfnoc_ctrl_tlast,
  input  wire         s_rfnoc_ctrl_tvalid,
  output wire         s_rfnoc_ctrl_tready,
  output wire [31:0]  m_rfnoc_ctrl_tdata,
  output wire         m_rfnoc_ctrl_tlast,
  output wire         m_rfnoc_ctrl_tvalid,
  input  wire         m_rfnoc_ctrl_tready,

  input  wire [31:0]  s_axis_ctrl_tdata,
  input  wire         s_axis_ctrl_tlast,
  input  wire         s_axis_ctrl_tvalid,
  output wire         s_axis_ctrl_tready,
  output wire [31:0]  m_axis_ctrl_tdata,
  output wire         m_axis_ctrl_tlast,
  output wire         m_axis_ctrl_tvalid,
  input  wire         m_axis_ctrl_tready
);





  `include "rfnoc_chdr_utils.vh"
  `include "rfnoc_axis_ctrl_utils.vh"





  wire [31:0] i_ctrl_tdata;
  wire        i_ctrl_tlast, i_ctrl_tvalid, i_ctrl_tready;

  generate
    if (SYNC_CLKS) begin
      axi_fifo #(.WIDTH(32+1), .SIZE(SLAVE_FIFO_SIZE)) in_fifo_i (
        .clk(axis_ctrl_clk), .reset(axis_ctrl_rst), .clear(1'b0),
        .i_tdata({s_rfnoc_ctrl_tlast, s_rfnoc_ctrl_tdata}),
        .i_tvalid(s_rfnoc_ctrl_tvalid), .i_tready(s_rfnoc_ctrl_tready),
        .o_tdata({i_ctrl_tlast, i_ctrl_tdata}),
        .o_tvalid(i_ctrl_tvalid), .o_tready(i_ctrl_tready),
        .space(), .occupied()
      );

      axi_fifo #(.WIDTH(32+1), .SIZE(1)) out_fifo_i (
        .clk(axis_ctrl_clk), .reset(axis_ctrl_rst), .clear(1'b0),
        .i_tdata({s_axis_ctrl_tlast, s_axis_ctrl_tdata}),
        .i_tvalid(s_axis_ctrl_tvalid), .i_tready(s_axis_ctrl_tready),
        .o_tdata({m_rfnoc_ctrl_tlast, m_rfnoc_ctrl_tdata}),
        .o_tvalid(m_rfnoc_ctrl_tvalid), .o_tready(m_rfnoc_ctrl_tready),
        .space(), .occupied()
      );
    end else begin
      axi_fifo_2clk #(.WIDTH(32+1), .SIZE(SLAVE_FIFO_SIZE), .PIPELINE("NONE")) in_fifo_i (
        .reset(rfnoc_ctrl_rst),
        .i_aclk(rfnoc_ctrl_clk),
        .i_tdata({s_rfnoc_ctrl_tlast, s_rfnoc_ctrl_tdata}),
        .i_tvalid(s_rfnoc_ctrl_tvalid), .i_tready(s_rfnoc_ctrl_tready),
        .o_aclk(axis_ctrl_clk),
        .o_tdata({i_ctrl_tlast, i_ctrl_tdata}),
        .o_tvalid(i_ctrl_tvalid), .o_tready(i_ctrl_tready)
      );

      axi_fifo_2clk #(.WIDTH(32+1), .SIZE(1), .PIPELINE("NONE")) out_fifo_i (
        .reset(axis_ctrl_rst),
        .i_aclk(axis_ctrl_clk),
        .i_tdata({s_axis_ctrl_tlast, s_axis_ctrl_tdata}),
        .i_tvalid(s_axis_ctrl_tvalid), .i_tready(s_axis_ctrl_tready),
        .o_aclk(rfnoc_ctrl_clk),
        .o_tdata({m_rfnoc_ctrl_tlast, m_rfnoc_ctrl_tdata}),
        .o_tvalid(m_rfnoc_ctrl_tvalid), .o_tready(m_rfnoc_ctrl_tready)
      );
    end
  endgenerate

  axi_fifo #(.WIDTH(32+1), .SIZE(1)) slv_pipe_i (
    .clk(axis_ctrl_clk), .reset(axis_ctrl_rst), .clear(1'b0),
    .i_tdata({i_ctrl_tlast, i_ctrl_tdata}),
    .i_tvalid(i_ctrl_tvalid), .i_tready(i_ctrl_tready),
    .o_tdata({m_axis_ctrl_tlast, m_axis_ctrl_tdata}),
    .o_tvalid(m_axis_ctrl_tvalid), .o_tready(m_axis_ctrl_tready),
    .space(), .occupied()
  );

endmodule