data/full_repos/permissive/205055389/test/verga/multedge.v
 line:28: before: "Dsetup"
1: b'%Error: data/full_repos/permissive/205055389/test/verga/multedge.v:10: Unsupported or unknown PLI call: $monitor\n $monitor("%2d: Q=%h  D=%h  EN=%h  CLR=%h",$time,Q,D,EN,CLR);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/multedge.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/multedge.v:17: Unsupported: Ignoring delay on this delayed statement.\n #1 CK = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/multedge.v:18: Unsupported: Ignoring delay on this delayed statement.\n #2 CK = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/multedge.v:21: Unsupported: Ignoring delay on this delayed statement.\n #1 CK = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/multedge.v:22: Unsupported: Ignoring delay on this delayed statement.\n #2 CK = 1\'b0;\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  wire [7:0] Q;
  reg [7:0] D;
  reg EN,CLR,CK;

  _GGREG8 g1(Q,D,EN,CLR,CK);
 
  initial
    begin
	$monitor("%2d: Q=%h  D=%h  EN=%h  CLR=%h",$time,Q,D,EN,CLR);

	CLR = 1'b1;
	EN = 1'b0;
	CK = 1'b0;
	D = 7'h42;
        #3;
	#1 CK = 1'b1;
	#2 CK = 1'b0;
	D = 7'h99;
	EN = 1'b1;
	#1 CK = 1'b1;
	#2 CK = 1'b0;
    end

endmodule
module top;

  wire [7:0] Q;
  reg [7:0] D;
  reg EN,CLR,CK;

  _GGREG8 g1(Q,D,EN,CLR,CK);
 
  initial
    begin
	$monitor("%2d: Q=%h  D=%h  EN=%h  CLR=%h",$time,Q,D,EN,CLR);

	CLR = 1'b1;
	EN = 1'b0;
	CK = 1'b0;
	D = 7'h42;
        #3;
	#1 CK = 1'b1;
	#2 CK = 1'b0;
	D = 7'h99;
	EN = 1'b1;
	#1 CK = 1'b1;
	#2 CK = 1'b0;
    end

endmodule