data/full_repos/permissive/148324174/CombLogic/CombLogic.v
data/verilator_xmls/43518bc8-f27d-4cd5-9ade-3374fb6f82d0.xml
module Comb_Logic_param
	#(parameter Dwidth=4)(
	input [Dwidth-1:0] X, Y,
	input [1:0] Inst,
	input Sel, 
	output reg [Dwidth-1:0] sum, Sel_out,
	output reg Cout, XEGY,
	output reg [2*Dwidth-1:0] Prod
	);

localparam Add = 2'b00;
localparam Mul = 2'b01;
localparam Comp = 2'b10;
localparam Mux = 2'b11;

always @(*)begin
	case (Inst)



		Add: {Cout, sum} = X+Y;

		Mul: Prod = X*Y;

		Comp:
		begin
			if (X >= Y) XEGY = 1'b1;
			else XEGY = 1'b0;
		end
		Mux:
			if (Sel == 1'b1) Sel_out = X;
			else Sel_out = Y;
	endcase
end

endmodule
module Comb_Logic_param
	#(parameter Dwidth=4)(
	input [Dwidth-1:0] X, Y,
	input [1:0] Inst,
	input Sel, 
	output reg [Dwidth-1:0] sum, Sel_out,
	output reg Cout, XEGY,
	output reg [2*Dwidth-1:0] Prod
	);


localparam Add = 2'b00;
localparam Mul = 2'b01;
localparam Comp = 2'b10;
localparam Mux = 2'b11;

always @(*)begin
	case (Inst)



		Add: {Cout, sum} = X+Y;

		Mul: Prod = X*Y;

		Comp:
		begin
			if (X >= Y) XEGY = 1'b1;
			else XEGY = 1'b0;
		end
		Mux:
			if (Sel == 1'b1) Sel_out = X;
			else Sel_out = Y;
	endcase
end

endmodule