data/full_repos/permissive/204736068/SoM/RTL/common/wb_spi_slave.sv
 line:122: before: "{"
1: b"%Error: data/full_repos/permissive/204736068/SoM/RTL/common/wb_spi_slave.sv:96: Cannot find file containing module: 'spi_slave_core'\n spi_slave_core u_spi_slave_core\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/204736068/SoM/RTL/common,data/full_repos/permissive/204736068/spi_slave_core\n             data/full_repos/permissive/204736068/SoM/RTL/common,data/full_repos/permissive/204736068/spi_slave_core.v\n             data/full_repos/permissive/204736068/SoM/RTL/common,data/full_repos/permissive/204736068/spi_slave_core.sv\n             spi_slave_core\n             spi_slave_core.v\n             spi_slave_core.sv\n             obj_dir/spi_slave_core\n             obj_dir/spi_slave_core.v\n             obj_dir/spi_slave_core.sv\n%Error: Exiting due to 1 error(s)\n"
module wb_spi_slave (
		input logic         clk,
		input logic         rst,
                  

		input logic         sck,
		input logic         ssn,
		input logic         mosi,
		output logic        miso,
                  

		output logic        o_wb_cyc,

		output logic        o_wb_stb,

		output logic [23:0] o_wb_adr,
		output logic [7:0]  o_wb_dat,
		output logic        o_wb_we,
                  
		input logic         i_wb_ack,
		input logic [7:0]   i_wb_dat,
		

		output logic reset_out,
		input logic [7:0] spi_id,
		input logic [7:0] spi_status                  
		);
   


	logic spi_busy, spi_rx_vld;
	logic [7:0] spi_tx_data;
	logic spi_tx_valid;

	spi_slave_core u_spi_slave_core
		(
			.sck                             (sck),
			.ssn                             (ssn),
			.mosi                            (mosi),
			.miso                            (miso),

			.clk (clk),
			.rst (rst),

			.address(o_wb_adr),
			.we(o_wb_we),
			.rx_data(o_wb_dat),
			.rx_valid(spi_rx_vld),

			.tx_data(spi_tx_data),
			.tx_valid(spi_tx_valid),
			
			.reset_out(reset_out),
			.spi_id(spi_id),
			.spi_status(spi_status),
			.busy(spi_busy)
		);



	enum {WB_IDLE='d0, WB_REQ='d1, WB_WAIT='d2, WB_XXX='d3} wb_curr, wb_next;
    

	always @* begin
		wb_next = WB_XXX;
		o_wb_cyc = '0;
		o_wb_stb = '0;

		case (wb_curr)
          
			WB_IDLE: begin
				if (spi_rx_vld) begin
					wb_next = WB_REQ;
					o_wb_cyc = '1;
					o_wb_stb = '1;
                  
				end
				else wb_next = WB_IDLE;
			end
          
			WB_REQ: begin
				o_wb_cyc = '1;
				o_wb_stb = '1;
				if (i_wb_ack) begin
					wb_next = WB_IDLE;
				end
				else begin
					wb_next = WB_WAIT;
				end
			end

			WB_WAIT: begin
				if (i_wb_ack) begin
					wb_next = WB_IDLE;
				end
				else begin
					o_wb_cyc = '1;
					wb_next = WB_WAIT;
				end
			end
          
		endcase
    

		if (rst) begin
			wb_next = WB_IDLE;
		end
	end


	always @(posedge clk, posedge rst) begin
		if (rst) wb_curr <= WB_IDLE;
		else  	 wb_curr <= wb_next;
	end


	always @(posedge clk) begin
		if (i_wb_ack && ~o_wb_we) begin
			spi_tx_data <= i_wb_dat; 
			spi_tx_valid <= '1;
		end else begin
			spi_tx_valid <= '0;
		end
	end

    
endmodule
module wb_spi_slave (
		input logic         clk,
		input logic         rst,
                  

		input logic         sck,
		input logic         ssn,
		input logic         mosi,
		output logic        miso,
                  

		output logic        o_wb_cyc,

		output logic        o_wb_stb,

		output logic [23:0] o_wb_adr,
		output logic [7:0]  o_wb_dat,
		output logic        o_wb_we,
                  
		input logic         i_wb_ack,
		input logic [7:0]   i_wb_dat,
		

		output logic reset_out,
		input logic [7:0] spi_id,
		input logic [7:0] spi_status                  
		);

   


	logic spi_busy, spi_rx_vld;
	logic [7:0] spi_tx_data;
	logic spi_tx_valid;

	spi_slave_core u_spi_slave_core
		(
			.sck                             (sck),
			.ssn                             (ssn),
			.mosi                            (mosi),
			.miso                            (miso),

			.clk (clk),
			.rst (rst),

			.address(o_wb_adr),
			.we(o_wb_we),
			.rx_data(o_wb_dat),
			.rx_valid(spi_rx_vld),

			.tx_data(spi_tx_data),
			.tx_valid(spi_tx_valid),
			
			.reset_out(reset_out),
			.spi_id(spi_id),
			.spi_status(spi_status),
			.busy(spi_busy)
		);



	enum {WB_IDLE='d0, WB_REQ='d1, WB_WAIT='d2, WB_XXX='d3} wb_curr, wb_next;
    

	always @* begin
		wb_next = WB_XXX;
		o_wb_cyc = '0;
		o_wb_stb = '0;

		case (wb_curr)
          
			WB_IDLE: begin
				if (spi_rx_vld) begin
					wb_next = WB_REQ;
					o_wb_cyc = '1;
					o_wb_stb = '1;
                  
				end
				else wb_next = WB_IDLE;
			end
          
			WB_REQ: begin
				o_wb_cyc = '1;
				o_wb_stb = '1;
				if (i_wb_ack) begin
					wb_next = WB_IDLE;
				end
				else begin
					wb_next = WB_WAIT;
				end
			end

			WB_WAIT: begin
				if (i_wb_ack) begin
					wb_next = WB_IDLE;
				end
				else begin
					o_wb_cyc = '1;
					wb_next = WB_WAIT;
				end
			end
          
		endcase
    

		if (rst) begin
			wb_next = WB_IDLE;
		end
	end


	always @(posedge clk, posedge rst) begin
		if (rst) wb_curr <= WB_IDLE;
		else  	 wb_curr <= wb_next;
	end


	always @(posedge clk) begin
		if (i_wb_ack && ~o_wb_we) begin
			spi_tx_data <= i_wb_dat; 
			spi_tx_valid <= '1;
		end else begin
			spi_tx_valid <= '0;
		end
	end

    
endmodule