data/full_repos/permissive/217756734/Verilog2001/Full AES Design And Data Communication/clock_signals.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: Cannot find file containing module: AES\n        ... Looked in:\n             data/full_repos/permissive/217756734/Verilog2001/Full/AES\n             data/full_repos/permissive/217756734/Verilog2001/Full/AES.v\n             data/full_repos/permissive/217756734/Verilog2001/Full/AES.sv\n             AES\n             AES.v\n             AES.sv\n             obj_dir/AES\n             obj_dir/AES.v\n             obj_dir/AES.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: And\n%Error: Cannot find file containing module: Data\n%Error: Cannot find file containing module: Communication,data/full_repos/permissive/217756734\n%Error: Cannot find file containing module: data/full_repos/permissive/217756734/Verilog2001/Full\n%Error: Cannot find file containing module: Communication/clock_signals.v\n%Error: Exiting due to 7 error(s)\n'
module clock_signals(
	input clock50MHz,
	output reg clock1MHz
);

reg [11:0] counter1MHz;

initial begin 
	clock1MHz = 0;
	counter1MHz = 12'd0;
end




always @(posedge clock50MHz) begin 
	if(counter1MHz == 12'd25) begin
		clock1MHz <= ~clock1MHz;
		counter1MHz <= 12'd0;
	end else begin
		counter1MHz <= counter1MHz + 12'd1;
	end

end

endmodule
module clock_signals(
	input clock50MHz,
	output reg clock1MHz
);


reg [11:0] counter1MHz;

initial begin 
	clock1MHz = 0;
	counter1MHz = 12'd0;
end




always @(posedge clock50MHz) begin 
	if(counter1MHz == 12'd25) begin
		clock1MHz <= ~clock1MHz;
		counter1MHz <= 12'd0;
	end else begin
		counter1MHz <= counter1MHz + 12'd1;
	end

end

endmodule