data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/MBE/testbench.sv
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/MBE/testbench.sv:20: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/MBE/testbench.sv:20: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mbe_4x
(
input [7:0] x,
output [3:0] single, double, neg
);

mbe_1x mbe3(x[7:5],single[3],double[3],neg[3]);
mbe_1x mbe2(x[5:3],single[2],double[2],neg[2]);
mbe_1x mbe1(x[3:1],single[1],double[1],neg[1]);
mbe_1x mbe0({x[1:0],1'b0},single[0],double[0],neg[0]);

endmodule
module mbe_4x
(
input [7:0] x,
output [3:0] single, double, neg
);


mbe_1x mbe3(x[7:5],single[3],double[3],neg[3]);
mbe_1x mbe2(x[5:3],single[2],double[2],neg[2]);
mbe_1x mbe1(x[3:1],single[1],double[1],neg[1]);
mbe_1x mbe0({x[1:0],1'b0},single[0],double[0],neg[0]);

endmodule