data/full_repos/permissive/124979458/HashTop_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/124979458/HashTop_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #5 rst = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/124979458/HashTop_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #100 rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/124979458/HashTop_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/124979458/HashTop_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #13 oRdHashClk <= ~oRdHashClk;\n  ^\n%Error: data/full_repos/permissive/124979458/HashTop_tb.v:59: Cannot find file containing module: \'HashTop\'\nHashTop HashTop(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/124979458,data/full_repos/permissive/124979458/HashTop\n             data/full_repos/permissive/124979458,data/full_repos/permissive/124979458/HashTop.v\n             data/full_repos/permissive/124979458,data/full_repos/permissive/124979458/HashTop.sv\n             HashTop\n             HashTop.v\n             HashTop.sv\n             obj_dir/HashTop\n             obj_dir/HashTop.v\n             obj_dir/HashTop.sv\n%Warning-WIDTH: data/full_repos/permissive/124979458/HashTop_tb.v:145: Bit extraction of array[3:0] requires 2 bit index, not 4 bits.\n                                                                     : ... In instance HashTop_tb\nassign oKeyLen = memKeyLen[i_keyLen];\n                          ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module HashTop_tb;



localparam	FIFOWIDTH 		= 8'd128;



localparam	KEYHASH_WIDTH 	= 8'd57;


reg 						clk;
reg 						rst;



wire 						iRdKeyClk;
wire 						iRdKeyFifo_en;
wire 						iRdKeyLenFifo_en;


wire 						iRdHashEmpty;
wire [KEYHASH_WIDTH-1:0]	iKeyHashFifo;



wire [FIFOWIDTH-1:0]		oKey;
wire [7:0]					oKeyLen;
reg 						oRdKeyEmpty;
reg 						oRdKeyLenEmpty;


wire 						oRdHashFifo_en;
reg 						oRdHashClk;


HashTop HashTop(
    .clk(clk),
	.rst(rst),


	.oRdKeyClk(iRdKeyClk),


	.iRdKeyEmpty(oRdKeyEmpty),
	.iRdKeyLenEmpty(oRdKeyLenEmpty),


	.oRdKeyFifo_en(iRdKeyFifo_en),
	.oRdKeyLenFifo_en(iRdKeyLenFifo_en),

	.iKey(oKey),
	.iKeyLen(oKeyLen),



	.iRdHashClk(oRdHashClk),

	.oRdHashEmpty(iRdHashEmpty),

	.iRdHashFifo_en(oRdHashFifo_en),


	.oKeyHashFifo(iKeyHashFifo)
	);



initial begin
    rst = 0;
    clk = 0;

    #5 rst = 1;
    #100 rst = 0;
    forever begin
		#10 clk <= ~clk;
    end
end

initial begin
  	oRdHashClk = 0;
    forever begin
		#13	oRdHashClk <= ~oRdHashClk;
    end
end

assign oRdHashFifo_en = !iRdHashEmpty;


reg [3:0]i_key;
reg [3:0]i_keyLen;
reg [7:0]			memKeyLen	[0:3];
reg [FIFOWIDTH-1:0]	memKey 		[0:9];
reg enable;
initial $readmemh("D:\\memKey.txt", memKey);
initial $readmemh("D:\\memKeyLen.txt", memKeyLen);

always @(posedge rst or posedge clk)begin
	if(rst)begin
		i_key <= 0;
		i_keyLen <= 0;
		oRdKeyEmpty <= 0;
		oRdKeyLenEmpty <= 0;
		enable <= 1;
	end
	else if(enable)begin
		if(iRdKeyFifo_en)begin
			i_key <= i_key+1;
		end
		if(iRdKeyLenFifo_en)begin
			i_keyLen <= i_keyLen+1;
		end
		if(i_keyLen == 3)begin
			enable <= 0;
			oRdKeyEmpty <= 1;
			oRdKeyLenEmpty <= 1;

		end
	end
end

assign oKey = memKey[i_key];
assign oKeyLen = memKeyLen[i_keyLen];

endmodule
module HashTop_tb;




localparam	FIFOWIDTH 		= 8'd128;



localparam	KEYHASH_WIDTH 	= 8'd57;


reg 						clk;
reg 						rst;



wire 						iRdKeyClk;
wire 						iRdKeyFifo_en;
wire 						iRdKeyLenFifo_en;


wire 						iRdHashEmpty;
wire [KEYHASH_WIDTH-1:0]	iKeyHashFifo;



wire [FIFOWIDTH-1:0]		oKey;
wire [7:0]					oKeyLen;
reg 						oRdKeyEmpty;
reg 						oRdKeyLenEmpty;


wire 						oRdHashFifo_en;
reg 						oRdHashClk;


HashTop HashTop(
    .clk(clk),
	.rst(rst),


	.oRdKeyClk(iRdKeyClk),


	.iRdKeyEmpty(oRdKeyEmpty),
	.iRdKeyLenEmpty(oRdKeyLenEmpty),


	.oRdKeyFifo_en(iRdKeyFifo_en),
	.oRdKeyLenFifo_en(iRdKeyLenFifo_en),

	.iKey(oKey),
	.iKeyLen(oKeyLen),



	.iRdHashClk(oRdHashClk),

	.oRdHashEmpty(iRdHashEmpty),

	.iRdHashFifo_en(oRdHashFifo_en),


	.oKeyHashFifo(iKeyHashFifo)
	);



initial begin
    rst = 0;
    clk = 0;

    #5 rst = 1;
    #100 rst = 0;
    forever begin
		#10 clk <= ~clk;
    end
end

initial begin
  	oRdHashClk = 0;
    forever begin
		#13	oRdHashClk <= ~oRdHashClk;
    end
end

assign oRdHashFifo_en = !iRdHashEmpty;


reg [3:0]i_key;
reg [3:0]i_keyLen;
reg [7:0]			memKeyLen	[0:3];
reg [FIFOWIDTH-1:0]	memKey 		[0:9];
reg enable;
initial $readmemh("D:\\memKey.txt", memKey);
initial $readmemh("D:\\memKeyLen.txt", memKeyLen);

always @(posedge rst or posedge clk)begin
	if(rst)begin
		i_key <= 0;
		i_keyLen <= 0;
		oRdKeyEmpty <= 0;
		oRdKeyLenEmpty <= 0;
		enable <= 1;
	end
	else if(enable)begin
		if(iRdKeyFifo_en)begin
			i_key <= i_key+1;
		end
		if(iRdKeyLenFifo_en)begin
			i_keyLen <= i_keyLen+1;
		end
		if(i_keyLen == 3)begin
			enable <= 0;
			oRdKeyEmpty <= 1;
			oRdKeyLenEmpty <= 1;

		end
	end
end

assign oKey = memKey[i_key];
assign oKeyLen = memKeyLen[i_keyLen];

endmodule