data/full_repos/permissive/200314387/verilog/7474/test.v
 line:40: before: "if"
1: b'%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:3: Cannot find include file: hct7474.v\n`include "hct7474.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/7474,data/full_repos/permissive/200314387/hct7474.v\n             data/full_repos/permissive/200314387/verilog/7474,data/full_repos/permissive/200314387/hct7474.v.v\n             data/full_repos/permissive/200314387/verilog/7474,data/full_repos/permissive/200314387/hct7474.v.sv\n             hct7474.v\n             hct7474.v.v\n             hct7474.v.sv\n             obj_dir/hct7474.v\n             obj_dir/hct7474.v.v\n             obj_dir/hct7474.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:4: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:29: Define or directive not defined: \'`Equals\'\n    `Equals(q, 1\'bx);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:29: syntax error, unexpected \',\'\n    `Equals(q, 1\'bx);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:30: Define or directive not defined: \'`Equals\'\n    `Equals(qb, 1\'bx);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:30: syntax error, unexpected \',\'\n    `Equals(qb, 1\'bx);\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:37: Define or directive not defined: \'`Equals\'\n    `Equals(q, 1\'b1);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:37: syntax error, unexpected \',\'\n    `Equals(q, 1\'b1);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:38: Define or directive not defined: \'`Equals\'\n    `Equals(qb, 1\'b1);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:38: syntax error, unexpected \',\'\n    `Equals(qb, 1\'b1);\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:45: Define or directive not defined: \'`Equals\'\n    `Equals(q, 1\'bx);  \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:45: syntax error, unexpected \',\'\n    `Equals(q, 1\'bx);  \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:46: Define or directive not defined: \'`Equals\'\n    `Equals(qb, 1\'bx);  \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:46: syntax error, unexpected \',\'\n    `Equals(qb, 1\'bx);  \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:54: Define or directive not defined: \'`Equals\'\n    `Equals(q, 1\'b0);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:54: syntax error, unexpected \',\'\n    `Equals(q, 1\'b0);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:55: Define or directive not defined: \'`Equals\'\n    `Equals(qb, 1\'b1); \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:55: syntax error, unexpected \',\'\n    `Equals(qb, 1\'b1); \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:63: Define or directive not defined: \'`Equals\'\n    `Equals(q, 1\'b0);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:63: syntax error, unexpected \',\'\n    `Equals(q, 1\'b0);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:64: Define or directive not defined: \'`Equals\'\n    `Equals(qb, 1\'b1); \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:64: syntax error, unexpected \',\'\n    `Equals(qb, 1\'b1); \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:72: Define or directive not defined: \'`Equals\'\n    `Equals(q, 1\'b1);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:72: syntax error, unexpected \',\'\n    `Equals(q, 1\'b1);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:73: Define or directive not defined: \'`Equals\'\n    `Equals(qb, 1\'b0); \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:73: syntax error, unexpected \',\'\n    `Equals(qb, 1\'b0); \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:81: Define or directive not defined: \'`Equals\'\n    `Equals(q, 1\'b1);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:81: syntax error, unexpected \',\'\n    `Equals(q, 1\'b1);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:82: Define or directive not defined: \'`Equals\'\n    `Equals(qb, 1\'b0); \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:82: syntax error, unexpected \',\'\n    `Equals(qb, 1\'b0); \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:89: Define or directive not defined: \'`Equals\'\n    `Equals(q, 1\'b1);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:89: syntax error, unexpected \',\'\n    `Equals(q, 1\'b1);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:90: Define or directive not defined: \'`Equals\'\n    `Equals(qb, 1\'b0); \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:90: syntax error, unexpected \',\'\n    `Equals(qb, 1\'b0); \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:99: Define or directive not defined: \'`Equals\'\n    `Equals(q, 1\'b1);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:99: syntax error, unexpected \',\'\n    `Equals(q, 1\'b1);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:98: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:100: Define or directive not defined: \'`Equals\'\n    `Equals(qb, 1\'b0); \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:100: syntax error, unexpected \',\'\n    `Equals(qb, 1\'b0); \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:113: Define or directive not defined: \'`Equals\'\n    `Equals(q, 1\'b0);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:113: syntax error, unexpected \',\'\n    `Equals(q, 1\'b0);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:112: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:114: Define or directive not defined: \'`Equals\'\n    `Equals(qb, 1\'b1); \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:114: syntax error, unexpected \',\'\n    `Equals(qb, 1\'b1); \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:122: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:126: Define or directive not defined: \'`Equals\'\n    `Equals(q, 1\'b1);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:126: syntax error, unexpected \',\'\n    `Equals(q, 1\'b1);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:125: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:127: Define or directive not defined: \'`Equals\'\n    `Equals(qb, 1\'b0); \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:127: syntax error, unexpected \',\'\n    `Equals(qb, 1\'b0); \n              ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:135: Define or directive not defined: \'`Equals\'\n    `Equals(q, 1\'b0);\n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:135: syntax error, unexpected \',\'\n    `Equals(q, 1\'b0);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/7474/test.v:134: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:136: Define or directive not defined: \'`Equals\'\n    `Equals(qb, 1\'b1); \n    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/7474/test.v:136: syntax error, unexpected \',\'\n    `Equals(qb, 1\'b1); \n              ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module tb();

logic cp, d, _sd, _rd;
wire q, qb;

localparam BLOCKS = 1;


hct7474 #(.BLOCKS(BLOCKS), .DELAY_RISE(9), .DELAY_FALL(9)) dut( ._SD(_sd), ._RD(_rd), .D(d), .CP(cp), .Q(q), ._Q(qb)); 

initial begin
`ifndef verilator
    $monitor("%9t ", $time, " : cp=%1b,d=%1b,_sd=%1b, _rd=%1b, q=%1b, qb=%1b", cp,d,_sd, _rd, q, qb);
`endif

    cp=0;
    d=1;

    #10
    _rd=1;
    _sd=1;

    #10
    `Equals(q, 1'bx);
    `Equals(qb, 1'bx);

    #10
    _rd=0;
    _sd=0;

    #10
    `Equals(q, 1'b1);
    `Equals(qb, 1'b1);

    #10
    _rd=1;
    _sd=1;

    #10
    `Equals(q, 1'bx);
    `Equals(qb, 1'bx);

    $display(" should reset async");
    #10
    _rd=0;
    _sd=1;

    #10
    `Equals(q, 1'b0);
    `Equals(qb, 1'b1); 

    $display(" should stay same");
    #10
    _rd=1;
    _sd=1;

    #10
    `Equals(q, 1'b0);
    `Equals(qb, 1'b1); 

    $display(" should set async");
    #10
    _rd=1;
    _sd=0;

    #10
    `Equals(q, 1'b1);
    `Equals(qb, 1'b0); 

    $display(" should stay same");
    #10
    _rd=1;
    _sd=1;

    #10
    `Equals(q, 1'b1);
    `Equals(qb, 1'b0); 

    $display(" should stay same even if d changes");
    #10
    d=0;

    #10
    `Equals(q, 1'b1);
    `Equals(qb, 1'b0); 

    $display(" should override clock +ve edge with set");
    #10
    _rd=1;
    _sd=0;
    cp=1;

    #10
    `Equals(q, 1'b1);
    `Equals(qb, 1'b0); 


    $display(" should clock in d");
    d=0;
    _rd=1;
    _sd=1;
    cp=0;

    #10
    cp=1;

    #10
    `Equals(q, 1'b0);
    `Equals(qb, 1'b1); 

    $display(" should clock in d");
    d=1;
    _rd=1;
    _sd=1;
    cp=0;

    #10
    cp=1;

    #10
    `Equals(q, 1'b1);
    `Equals(qb, 1'b0); 

    $display(" should clear async");
    d=1;
    _rd=0;
    _sd=1;

    #10
    `Equals(q, 1'b0);
    `Equals(qb, 1'b1); 
end

endmodule
module tb();


logic cp, d, _sd, _rd;
wire q, qb;

localparam BLOCKS = 1;


hct7474 #(.BLOCKS(BLOCKS), .DELAY_RISE(9), .DELAY_FALL(9)) dut( ._SD(_sd), ._RD(_rd), .D(d), .CP(cp), .Q(q), ._Q(qb)); 

initial begin
`ifndef verilator
    $monitor("%9t ", $time, " : cp=%1b,d=%1b,_sd=%1b, _rd=%1b, q=%1b, qb=%1b", cp,d,_sd, _rd, q, qb);
`endif

    cp=0;
    d=1;

    #10
    _rd=1;
    _sd=1;

    #10
    `Equals(q, 1'bx);
    `Equals(qb, 1'bx);

    #10
    _rd=0;
    _sd=0;

    #10
    `Equals(q, 1'b1);
    `Equals(qb, 1'b1);

    #10
    _rd=1;
    _sd=1;

    #10
    `Equals(q, 1'bx);
    `Equals(qb, 1'bx);

    $display(" should reset async");
    #10
    _rd=0;
    _sd=1;

    #10
    `Equals(q, 1'b0);
    `Equals(qb, 1'b1); 

    $display(" should stay same");
    #10
    _rd=1;
    _sd=1;

    #10
    `Equals(q, 1'b0);
    `Equals(qb, 1'b1); 

    $display(" should set async");
    #10
    _rd=1;
    _sd=0;

    #10
    `Equals(q, 1'b1);
    `Equals(qb, 1'b0); 

    $display(" should stay same");
    #10
    _rd=1;
    _sd=1;

    #10
    `Equals(q, 1'b1);
    `Equals(qb, 1'b0); 

    $display(" should stay same even if d changes");
    #10
    d=0;

    #10
    `Equals(q, 1'b1);
    `Equals(qb, 1'b0); 

    $display(" should override clock +ve edge with set");
    #10
    _rd=1;
    _sd=0;
    cp=1;

    #10
    `Equals(q, 1'b1);
    `Equals(qb, 1'b0); 


    $display(" should clock in d");
    d=0;
    _rd=1;
    _sd=1;
    cp=0;

    #10
    cp=1;

    #10
    `Equals(q, 1'b0);
    `Equals(qb, 1'b1); 

    $display(" should clock in d");
    d=1;
    _rd=1;
    _sd=1;
    cp=0;

    #10
    cp=1;

    #10
    `Equals(q, 1'b1);
    `Equals(qb, 1'b0); 

    $display(" should clear async");
    d=1;
    _rd=0;
    _sd=1;

    #10
    `Equals(q, 1'b0);
    `Equals(qb, 1'b1); 
end

endmodule