data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v
1: b'%Error: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:27: Cannot find file containing module: \'Divider\'\n    Divider #(10000)display_divider(.clk(clk), .clk_N(clk_N));\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources,data/full_repos/permissive/171720620/Divider\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources,data/full_repos/permissive/171720620/Divider.v\n             data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources,data/full_repos/permissive/171720620/Divider.sv\n             Divider\n             Divider.v\n             Divider.sv\n             obj_dir/Divider\n             obj_dir/Divider.v\n             obj_dir/Divider.sv\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:60: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s SEL generates 4 bits.\n                                                                                                  : ... In instance Display\n        displayData[3: 0] <= select != 2\'b00 ? (leddata % 10) : leddata[3: 0];\n                                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:60: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                  : ... In instance Display\n        displayData[3: 0] <= select != 2\'b00 ? (leddata % 10) : leddata[3: 0];\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:61: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s SEL generates 4 bits.\n                                                                                                  : ... In instance Display\n        displayData[7: 4] <= select != 2\'b00 ? (leddata / 10 % 10) : leddata[7: 4];\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:61: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                  : ... In instance Display\n        displayData[7: 4] <= select != 2\'b00 ? (leddata / 10 % 10) : leddata[7: 4];\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:62: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s SEL generates 4 bits.\n                                                                                                  : ... In instance Display\n        displayData[11: 8] <= select != 2\'b00 ? (leddata / 100 % 10) : leddata[11: 8];\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:62: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                  : ... In instance Display\n        displayData[11: 8] <= select != 2\'b00 ? (leddata / 100 % 10) : leddata[11: 8];\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:63: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s SEL generates 4 bits.\n                                                                                                  : ... In instance Display\n        displayData[15: 12] <= select != 2\'b00 ? (leddata / 1000 % 10) : leddata[15: 12];\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:63: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                  : ... In instance Display\n        displayData[15: 12] <= select != 2\'b00 ? (leddata / 1000 % 10) : leddata[15: 12];\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:64: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s SEL generates 4 bits.\n                                                                                                  : ... In instance Display\n        displayData[19: 16] <= select != 2\'b00 ? (leddata / 10000 % 10) : leddata[19: 16];\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:64: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                  : ... In instance Display\n        displayData[19: 16] <= select != 2\'b00 ? (leddata / 10000 % 10) : leddata[19: 16];\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:65: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s SEL generates 4 bits.\n                                                                                                  : ... In instance Display\n        displayData[23: 20] <= select != 2\'b00 ? (leddata / 100000 % 10) : leddata[23: 20];\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:65: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                  : ... In instance Display\n        displayData[23: 20] <= select != 2\'b00 ? (leddata / 100000 % 10) : leddata[23: 20];\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:66: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s SEL generates 4 bits.\n                                                                                                  : ... In instance Display\n        displayData[27: 24] <= select != 2\'b00 ? (leddata / 1000000 % 10) : leddata[27: 24];\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:66: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                  : ... In instance Display\n        displayData[27: 24] <= select != 2\'b00 ? (leddata / 1000000 % 10) : leddata[27: 24];\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:67: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s SEL generates 4 bits.\n                                                                                                  : ... In instance Display\n        displayData[31: 28] <= select != 2\'b00 ? (leddata / 10000000 % 10) : leddata[31: 28];\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/171720620/hardware/PipelineCPU/src/sources/Display.v:67: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                  : ... In instance Display\n        displayData[31: 28] <= select != 2\'b00 ? (leddata / 10000000 % 10) : leddata[31: 28];\n                            ^~\n%Error: Exiting due to 1 error(s), 16 warning(s)\n'
module Display(
        input [31:0] leddata,
        input [1:0] select,
        input clk,
        input rst,
        output reg [7:0] seg,
        output reg [7:0] an
    );
    wire clk_N;
    reg [31:0] displayData;
    reg [2:0] counter;

    Divider #(10000)display_divider(.clk(clk), .clk_N(clk_N));

    initial begin
        seg = 8'b11111111;
        an = 0;
        displayData = 0;
        counter = 0;
    end

    always @(posedge clk_N) begin
        an <= ~(8'h1 << counter);
        case (displayData[counter * 4+:4])
            4'b0000: seg <= 8'b11000000;
            4'b0001: seg <= 8'b11111001;
            4'b0010: seg <= 8'b10100100;
            4'b0011: seg <= 8'b10110000;
            4'b0100: seg <= 8'b10011001;
            4'b0101: seg <= 8'b10010010;
            4'b0110: seg <= 8'b10000010;
            4'b0111: seg <= 8'b11111000;
            4'b1000: seg <= 8'b10000000;
            4'b1001: seg <= 8'b10010000;
            4'b1010: seg <= 8'b10001000;
            4'b1011: seg <= 8'b10000011;
            4'b1100: seg <= 8'b11000110;
            4'b1101: seg <= 8'b10100001;
            4'b1110: seg <= 8'b10000110;
            4'b1111: seg <= 8'b10001110;
            default: seg <= 8'b11111111;
        endcase

        counter <= counter + 1;

        displayData[3: 0] <= select != 2'b00 ? (leddata % 10) : leddata[3: 0];
        displayData[7: 4] <= select != 2'b00 ? (leddata / 10 % 10) : leddata[7: 4];
        displayData[11: 8] <= select != 2'b00 ? (leddata / 100 % 10) : leddata[11: 8];
        displayData[15: 12] <= select != 2'b00 ? (leddata / 1000 % 10) : leddata[15: 12];
        displayData[19: 16] <= select != 2'b00 ? (leddata / 10000 % 10) : leddata[19: 16];
        displayData[23: 20] <= select != 2'b00 ? (leddata / 100000 % 10) : leddata[23: 20];
        displayData[27: 24] <= select != 2'b00 ? (leddata / 1000000 % 10) : leddata[27: 24];
        displayData[31: 28] <= select != 2'b00 ? (leddata / 10000000 % 10) : leddata[31: 28];

        if (rst) begin
            displayData <= 0;
            counter <= 0;
            seg <= 8'b11111111;
            an <= 0;
        end
    end

endmodule
module Display(
        input [31:0] leddata,
        input [1:0] select,
        input clk,
        input rst,
        output reg [7:0] seg,
        output reg [7:0] an
    );

    wire clk_N;
    reg [31:0] displayData;
    reg [2:0] counter;

    Divider #(10000)display_divider(.clk(clk), .clk_N(clk_N));

    initial begin
        seg = 8'b11111111;
        an = 0;
        displayData = 0;
        counter = 0;
    end

    always @(posedge clk_N) begin
        an <= ~(8'h1 << counter);
        case (displayData[counter * 4+:4])
            4'b0000: seg <= 8'b11000000;
            4'b0001: seg <= 8'b11111001;
            4'b0010: seg <= 8'b10100100;
            4'b0011: seg <= 8'b10110000;
            4'b0100: seg <= 8'b10011001;
            4'b0101: seg <= 8'b10010010;
            4'b0110: seg <= 8'b10000010;
            4'b0111: seg <= 8'b11111000;
            4'b1000: seg <= 8'b10000000;
            4'b1001: seg <= 8'b10010000;
            4'b1010: seg <= 8'b10001000;
            4'b1011: seg <= 8'b10000011;
            4'b1100: seg <= 8'b11000110;
            4'b1101: seg <= 8'b10100001;
            4'b1110: seg <= 8'b10000110;
            4'b1111: seg <= 8'b10001110;
            default: seg <= 8'b11111111;
        endcase

        counter <= counter + 1;

        displayData[3: 0] <= select != 2'b00 ? (leddata % 10) : leddata[3: 0];
        displayData[7: 4] <= select != 2'b00 ? (leddata / 10 % 10) : leddata[7: 4];
        displayData[11: 8] <= select != 2'b00 ? (leddata / 100 % 10) : leddata[11: 8];
        displayData[15: 12] <= select != 2'b00 ? (leddata / 1000 % 10) : leddata[15: 12];
        displayData[19: 16] <= select != 2'b00 ? (leddata / 10000 % 10) : leddata[19: 16];
        displayData[23: 20] <= select != 2'b00 ? (leddata / 100000 % 10) : leddata[23: 20];
        displayData[27: 24] <= select != 2'b00 ? (leddata / 1000000 % 10) : leddata[27: 24];
        displayData[31: 28] <= select != 2'b00 ? (leddata / 10000000 % 10) : leddata[31: 28];

        if (rst) begin
            displayData <= 0;
            counter <= 0;
            seg <= 8'b11111111;
            an <= 0;
        end
    end

endmodule