data/full_repos/permissive/160794640/example/axi_slave_connect_example.v
 line:19: before: ":"
1: b"%Error: data/full_repos/permissive/160794640/example/axi_slave_connect_example.v:19: syntax error, unexpected ::, expecting ')' or ','\n    output ariane_axi::req_t    dm_axi_s_req,\n                     ^~\n                                                                                   : ... Perhaps 'ariane_axi' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/160794640/example/axi_slave_connect_example.v:30: syntax error, unexpected IDENTIFIER\nAXI_BUS #(\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module axi_slave_connect_example (
    output ariane_axi::req_t    dm_axi_s_req,
    input  ariane_axi::resp_t   dm_axi_s_resp,		      
    input  ariane_axi::req_t    dm_axi_m_req,
    output ariane_axi::resp_t   dm_axi_m_resp
);
localparam AxiAddrWidth = 64;
localparam AxiDataWidth = 64;
localparam AxiIdWidthMaster = 4;
localparam AxiIdWidthSlaves = 4;
localparam AxiUserWidth = 1;

AXI_BUS #(
    .AXI_ADDR_WIDTH ( AxiAddrWidth     ),
    .AXI_DATA_WIDTH ( AxiDataWidth     ),
    .AXI_ID_WIDTH   ( AxiIdWidthMaster ),
    .AXI_USER_WIDTH ( AxiUserWidth     )
) slave();

AXI_BUS #(
    .AXI_ADDR_WIDTH ( AxiAddrWidth     ),
    .AXI_DATA_WIDTH ( AxiDataWidth     ),
    .AXI_ID_WIDTH   ( AxiIdWidthSlaves ),
    .AXI_USER_WIDTH ( AxiUserWidth     )
) master();

axi_master_connect i_axi_master_dm (.axi_req_i(dm_axi_m_req), .axi_resp_o(dm_axi_m_resp), .master(slave));
axi_slave_connect  i_axi_slave_dm  (.axi_req_o(dm_axi_s_req), .axi_resp_i(dm_axi_s_resp), .slave(master));

endmodule
module axi_slave_connect_example (
    output ariane_axi::req_t    dm_axi_s_req,
    input  ariane_axi::resp_t   dm_axi_s_resp,		      
    input  ariane_axi::req_t    dm_axi_m_req,
    output ariane_axi::resp_t   dm_axi_m_resp
);

localparam AxiAddrWidth = 64;
localparam AxiDataWidth = 64;
localparam AxiIdWidthMaster = 4;
localparam AxiIdWidthSlaves = 4;
localparam AxiUserWidth = 1;

AXI_BUS #(
    .AXI_ADDR_WIDTH ( AxiAddrWidth     ),
    .AXI_DATA_WIDTH ( AxiDataWidth     ),
    .AXI_ID_WIDTH   ( AxiIdWidthMaster ),
    .AXI_USER_WIDTH ( AxiUserWidth     )
) slave();

AXI_BUS #(
    .AXI_ADDR_WIDTH ( AxiAddrWidth     ),
    .AXI_DATA_WIDTH ( AxiDataWidth     ),
    .AXI_ID_WIDTH   ( AxiIdWidthSlaves ),
    .AXI_USER_WIDTH ( AxiUserWidth     )
) master();

axi_master_connect i_axi_master_dm (.axi_req_i(dm_axi_m_req), .axi_resp_o(dm_axi_m_resp), .master(slave));
axi_slave_connect  i_axi_slave_dm  (.axi_req_o(dm_axi_s_req), .axi_resp_i(dm_axi_s_resp), .slave(master));

endmodule