data/full_repos/permissive/216344104/theta_calculation.v
1: b'%Warning-WIDTH: data/full_repos/permissive/216344104/theta_calculation.v:14: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                           : ... In instance theta_calculation\nassign delta[15:0] = 8\'d0;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module theta_calculation(
	input clk,
	input rst_n,
	input signed [31:0] y_Global,
	input signed [31:0] x_Global,
	output reg signed[15:0] theta
);
parameter L = 50;

wire signed[31:0] delta_temp;
wire signed[31:0] delta;
assign delta_temp = y_Global - x_Global;
assign delta[31:16] = delta_temp[15:0];
assign delta[15:0] = 8'd0;

reg signed[31:0] theta_raw;
reg signed[63:0] theta_48;
reg signed[63:0] theta_48_pi;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		begin
			theta_raw <= 32'd0;
			theta_48 <= 64'd0;
			theta_48_pi <= 64'd0;
			theta <= 16'd0;
		end
	else
		begin
		theta_raw <= delta/L ;

		theta_48[63:32] <= theta_raw[31:0];
		theta_48[31:0] <= 32'd0;
		theta_48_pi <= theta_48/64'd26986075409;
		theta <= theta_48_pi[15:0];
		end
endmodule
module theta_calculation(
	input clk,
	input rst_n,
	input signed [31:0] y_Global,
	input signed [31:0] x_Global,
	output reg signed[15:0] theta
);

parameter L = 50;

wire signed[31:0] delta_temp;
wire signed[31:0] delta;
assign delta_temp = y_Global - x_Global;
assign delta[31:16] = delta_temp[15:0];
assign delta[15:0] = 8'd0;

reg signed[31:0] theta_raw;
reg signed[63:0] theta_48;
reg signed[63:0] theta_48_pi;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		begin
			theta_raw <= 32'd0;
			theta_48 <= 64'd0;
			theta_48_pi <= 64'd0;
			theta <= 16'd0;
		end
	else
		begin
		theta_raw <= delta/L ;

		theta_48[63:32] <= theta_raw[31:0];
		theta_48[31:0] <= 32'd0;
		theta_48_pi <= theta_48/64'd26986075409;
		theta <= theta_48_pi[15:0];
		end
endmodule