data/full_repos/permissive/161526648/mux3_1.v
data/verilator_xmls/131488c1-0de3-4f63-85c2-72db3ece0b40.xml
module mux3_1(src1,src2,src3,sel,result);
	parameter N = 32;
	input [N-1:0] src1,src2,src3;
	input[1:0] sel;
	output reg [N-1:0] result;
	
	always @(sel,src1,src2,src3) begin
		case (sel) 
			2'b00: result = src1;
			2'b01: result = src2;
			2'b10: result = src3;
		endcase
	end
endmodule
module mux3_1(src1,src2,src3,sel,result);

	parameter N = 32;
	input [N-1:0] src1,src2,src3;
	input[1:0] sel;
	output reg [N-1:0] result;
	
	always @(sel,src1,src2,src3) begin
		case (sel) 
			2'b00: result = src1;
			2'b01: result = src2;
			2'b10: result = src3;
		endcase
	end
endmodule