data/full_repos/permissive/121410129/7seg/7seg/CounterGenerator.v
data/verilator_xmls/9331669a-f8c5-4a71-9012-afb8e6f5c82c.xml
module CounterGenerator(clock, reset, counter);

input wire clock, reset;
output reg [2:0]counter;

always @ (posedge clock or posedge reset) begin
	if (reset == 1) begin
		counter <= 3'b000;
	end
	else begin
		counter <= counter + 3'b001;
	end
end

endmodule
module CounterGenerator(clock, reset, counter);


input wire clock, reset;
output reg [2:0]counter;

always @ (posedge clock or posedge reset) begin
	if (reset == 1) begin
		counter <= 3'b000;
	end
	else begin
		counter <= counter + 3'b001;
	end
end

endmodule