data/full_repos/permissive/201488448/1_verilog/00_start.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/954c11dd-b455-4564-b7c9-5955b5582d53.xml
module top_module( output one );
	
	assign one = 1'b1;
	
endmodule
module top_module( output one );

	
	assign one = 1'b1;
	
endmodule