data/full_repos/permissive/165846232/components/MinMax/MinMax.v
data/verilator_xmls/8cbede27-33f5-4fa4-bfad-496fa4f68caf.xml
module MinMax
#(
	parameter INPUT_BIT_WIDTH = 8
)
(
    input Clk,
    input [INPUT_BIT_WIDTH-1:0] InputA,
	input [INPUT_BIT_WIDTH-1:0] InputB,
	output reg [INPUT_BIT_WIDTH-1:0] Max,
    output reg [INPUT_BIT_WIDTH-1:0] Min
);

    always @(posedge Clk)
	begin
		if(InputA < InputB)
            begin
                Max <= InputB;
                Min <= InputA;
            end
        else
            begin
                Max <= InputA;
                Min <= InputB;
            end
	end

endmodule
module MinMax
#(
	parameter INPUT_BIT_WIDTH = 8
)
(
    input Clk,
    input [INPUT_BIT_WIDTH-1:0] InputA,
	input [INPUT_BIT_WIDTH-1:0] InputB,
	output reg [INPUT_BIT_WIDTH-1:0] Max,
    output reg [INPUT_BIT_WIDTH-1:0] Min
);


    always @(posedge Clk)
	begin
		if(InputA < InputB)
            begin
                Max <= InputB;
                Min <= InputA;
            end
        else
            begin
                Max <= InputA;
                Min <= InputB;
            end
	end

endmodule