data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv
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1: b'%Warning-STMTDLY: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:19: Unsupported: Ignoring delay on this delayed statement.\n            #(t/2) clk <= ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:40: syntax error, unexpected \'@\'\n            @(posedge clk); sel = 2\'b00; le = 1\'b1;\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:41: syntax error, unexpected \'@\'\n            @(posedge clk); sel = 2\'b01;\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:42: syntax error, unexpected \'@\'\n            @(posedge clk); sel = 2\'b10;\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:43: syntax error, unexpected \'@\'\n            @(posedge clk); $display("sel = incorrect value"); \n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:46: syntax error, unexpected \'@\'\n            @(posedge clk); data[0] = 2\'b00;\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:47: syntax error, unexpected \'@\'\n            @(posedge clk); data[0] = 2\'b01;\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:48: syntax error, unexpected \'@\'\n            @(posedge clk); $display("corrected:");\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:50: syntax error, unexpected \'@\'\n            @(posedge clk); $display("sel = incorrect value");\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:52: syntax error, unexpected \'@\'\n            @(posedge clk); $display("corrected:");\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:54: syntax error, unexpected \'@\'\n            @(posedge clk); data[0] = 2\'b11;\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:56: syntax error, unexpected \'@\'\n            @(posedge clk); $display("latch disable:");\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:58: syntax error, unexpected \'@\'\n            @(posedge clk); data[0] = 2\'b10;\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:59: syntax error, unexpected \'@\'\n            @(posedge clk); $display("latch enable:");\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:61: syntax error, unexpected \'@\'\n            @(posedge clk); data[0] = 2\'b01;\n            ^\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:67: Unsupported or unknown PLI call: $monitor\n        $monitor("data=%b sel=%b le=%b case_latch=%b case_corrt=%b latch=%b", \n        ^~~~~~~~\n%Error: data/full_repos/permissive/147690299/lab/28_latch/tb/testbench.sv:71: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: Exiting due to 16 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    
    localparam t = 20;

    reg  [2:0][1:0] data;
    reg       [1:0] sel;
    reg             le;
    wire      [1:0] case_latch;
    wire      [1:0] case_corrt;
    wire      [1:0] latch;
 
    reg  clk;
    initial begin
        clk <= 0;
        forever 
            #(t/2) clk <= ~clk;
    end


    lab_top dut
    (
        .clk        ( clk        ),
        .idata0     ( data[0]    ),
        .idata1     ( data[1]    ),
        .idata2     ( data[2]    ),
        .sel        ( sel        ),
        .le         ( le         ),
        .case_latch ( case_latch ),
        .case_corrt ( case_corrt ),
        .latch      ( latch      ) 
    );

    initial 
        begin
            data = 6'b111001;
            
            @(posedge clk); sel = 2'b00; le = 1'b1;
            @(posedge clk); sel = 2'b01;
            @(posedge clk); sel = 2'b10;
            @(posedge clk); $display("sel = incorrect value"); 
                            sel = 2'b11; 
            
            @(posedge clk); data[0] = 2'b00;
            @(posedge clk); data[0] = 2'b01;
            @(posedge clk); $display("corrected:");
                            sel = 2'b01;
            @(posedge clk); $display("sel = incorrect value");
                            sel = 2'b11;
            @(posedge clk); $display("corrected:");
                            sel = 2'b00;
            @(posedge clk); data[0] = 2'b11;

            @(posedge clk); $display("latch disable:");
                            le = 1'b0;
            @(posedge clk); data[0] = 2'b10;
            @(posedge clk); $display("latch enable:");
                            le = 1'b1;
            @(posedge clk); data[0] = 2'b01;

            $finish();
        end

    initial
        $monitor("data=%b sel=%b le=%b case_latch=%b case_corrt=%b latch=%b", 
                  data,   sel,   le,   case_latch,   case_corrt,   latch    );

    initial 
        $dumpvars;

endmodule
module testbench;

    
    localparam t = 20;

    reg  [2:0][1:0] data;
    reg       [1:0] sel;
    reg             le;
    wire      [1:0] case_latch;
    wire      [1:0] case_corrt;
    wire      [1:0] latch;
 
    reg  clk;
    initial begin
        clk <= 0;
        forever 
            #(t/2) clk <= ~clk;
    end


    lab_top dut
    (
        .clk        ( clk        ),
        .idata0     ( data[0]    ),
        .idata1     ( data[1]    ),
        .idata2     ( data[2]    ),
        .sel        ( sel        ),
        .le         ( le         ),
        .case_latch ( case_latch ),
        .case_corrt ( case_corrt ),
        .latch      ( latch      ) 
    );

    initial 
        begin
            data = 6'b111001;
            
            @(posedge clk); sel = 2'b00; le = 1'b1;
            @(posedge clk); sel = 2'b01;
            @(posedge clk); sel = 2'b10;
            @(posedge clk); $display("sel = incorrect value"); 
                            sel = 2'b11; 
            
            @(posedge clk); data[0] = 2'b00;
            @(posedge clk); data[0] = 2'b01;
            @(posedge clk); $display("corrected:");
                            sel = 2'b01;
            @(posedge clk); $display("sel = incorrect value");
                            sel = 2'b11;
            @(posedge clk); $display("corrected:");
                            sel = 2'b00;
            @(posedge clk); data[0] = 2'b11;

            @(posedge clk); $display("latch disable:");
                            le = 1'b0;
            @(posedge clk); data[0] = 2'b10;
            @(posedge clk); $display("latch enable:");
                            le = 1'b1;
            @(posedge clk); data[0] = 2'b01;

            $finish();
        end

    initial
        $monitor("data=%b sel=%b le=%b case_latch=%b case_corrt=%b latch=%b", 
                  data,   sel,   le,   case_latch,   case_corrt,   latch    );

    initial 
        $dumpvars;

endmodule