data/full_repos/permissive/123690745/IFID.v
 line:32: before: "="
data/verilator_xmls/c516eb77-35c1-4e67-a6c3-bf14b7d1addf.xml
module IFID(
	 input InterruptRequest,
    input [31:0] RD,
    input StallD,
    input CLR,
	 input reset,
	 input clk,
	 input [31:0] PCPlus4F,
	 input [31:0] PCF,
	 input AtDelaySlotF,
	 input CancelF,
	 output reg [31:0] PCD = 0,
    output reg [31:0] InstrD = 0,
    output reg [31:0] PCPlus4D = 0,
	 output reg AtDelaySlotD
    );
	always @(posedge clk) begin
		if (reset == 1 || ((InterruptRequest == 1 || CancelF) && StallD != 1)) begin
			InstrD <= 0;
			if (CancelF && !reset) begin
				PCPlus4D <= PCPlus4F;
				PCD <= PCF;
				AtDelaySlotD <= AtDelaySlotF;
			end
			else begin
				PCPlus4D <= 0;
				PCD <= 0;
				AtDelaySlotD <= 0;
			end
			
		end
		else if (StallD != 1) begin
			InstrD <= RD;
			PCPlus4D <= PCPlus4F;
			PCD <= PCF;
			AtDelaySlotD <= AtDelaySlotF;
		end
	end
endmodule
module IFID(
	 input InterruptRequest,
    input [31:0] RD,
    input StallD,
    input CLR,
	 input reset,
	 input clk,
	 input [31:0] PCPlus4F,
	 input [31:0] PCF,
	 input AtDelaySlotF,
	 input CancelF,
	 output reg [31:0] PCD = 0,
    output reg [31:0] InstrD = 0,
    output reg [31:0] PCPlus4D = 0,
	 output reg AtDelaySlotD
    );

	always @(posedge clk) begin
		if (reset == 1 || ((InterruptRequest == 1 || CancelF) && StallD != 1)) begin
			InstrD <= 0;
			if (CancelF && !reset) begin
				PCPlus4D <= PCPlus4F;
				PCD <= PCF;
				AtDelaySlotD <= AtDelaySlotF;
			end
			else begin
				PCPlus4D <= 0;
				PCD <= 0;
				AtDelaySlotD <= 0;
			end
			
		end
		else if (StallD != 1) begin
			InstrD <= RD;
			PCPlus4D <= PCPlus4F;
			PCD <= PCF;
			AtDelaySlotD <= AtDelaySlotF;
		end
	end
endmodule