data/full_repos/permissive/111433415/verilog/02_banco_pruebas/02-1_votador1/votador.v
data/verilator_xmls/78509003-d249-4c49-a2a7-b6ec2290711b.xml
module votador (
    output reg v,
    input wire a,
    input wire b,
    input wire c
    );


    always @(a, b, c)
        case(a)

        1:
            v = b | c;
        default:
            v = b & c;
        endcase

endmodule
module votador (
    output reg v,
    input wire a,
    input wire b,
    input wire c
    );



    always @(a, b, c)
        case(a)

        1:
            v = b | c;
        default:
            v = b & c;
        endcase

endmodule