data/full_repos/permissive/187199324/stannel/FetchStack.v
1: b'%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:1: Cannot find include file: defaults.vh\n`include "defaults.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.v\n             data/full_repos/permissive/187199324/stannel,data/full_repos/permissive/187199324/defaults.vh.sv\n             defaults.vh\n             defaults.vh.v\n             defaults.vh.sv\n             obj_dir/defaults.vh\n             obj_dir/defaults.vh.v\n             obj_dir/defaults.vh.sv\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:4: Define or directive not defined: \'`ADDRESS_BITS\'\nmodule FetchStack #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:4: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\nmodule FetchStack #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                      ^\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:4: Define or directive not defined: \'`DATA_BITS\'\nmodule FetchStack #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:4: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule FetchStack #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (\n                                                                                       ^\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:7: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                reset,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:8: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [dataBits-1:0] dataOut,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:9: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [addrBits-1:0] address,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:10: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                finished,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [addrBits-1:0] stackPointer,\n    ^~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:12: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [dataBits-1:0] topOfStack1,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [dataBits-1:0] topOfStack2,\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [dataBits-1:0] topOfStack3\n    ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:15: syntax error, unexpected \')\', expecting \',\' or \';\'\n  );\n  ^\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:21: syntax error, unexpected assign\n  assign topOfStack1 = rTop1;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:26: syntax error, unexpected assign\n  assign address = stackPointer + wOffset;\n  ^~~~~~\n%Error: data/full_repos/permissive/187199324/stannel/FetchStack.v:44: syntax error, unexpected always\n  always @(posedge clk)\n  ^~~~~~\n%Error: Exiting due to 17 error(s)\n'
module FetchStack #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    input  wire [dataBits-1:0] dataOut,
    output wire [addrBits-1:0] address,
    output wire                finished,
    input  wire [addrBits-1:0] stackPointer,
    output wire [dataBits-1:0] topOfStack1,
    output wire [dataBits-1:0] topOfStack2,
    output wire [dataBits-1:0] topOfStack3
  );



  reg [dataBits-1:0] rTop1, rTop2, rTop3;

  assign topOfStack1 = rTop1;
  assign topOfStack2 = rTop2;
  assign topOfStack3 = rTop3;

  reg [addrBits-1:0] wOffset;
  assign address = stackPointer + wOffset;

  assign finished = rState == FETCH_DONE;



  localparam FETCH_TOP1 = 2'd0;
  localparam FETCH_TOP2 = 2'd1;
  localparam FETCH_TOP3 = 2'd2;
  localparam FETCH_DONE = 2'd3;

  reg wUpdateTop1;
  reg wUpdateTop2;
  reg wUpdateTop3;

  reg [1:0] rState;
  reg       rMemoryCycle;

  always @(posedge clk)
    begin
      if (wUpdateTop1)
        rTop1 <= dataOut;
      if (wUpdateTop2)
        rTop2 <= dataOut;
      if (wUpdateTop3)
        rTop3 <= dataOut;

      if (!reset)
        rMemoryCycle <= 0;
      else
        rMemoryCycle <= rMemoryCycle + 1;

      if (!reset)
        rState <= 0;
      else if (rMemoryCycle)
        rState <= rState + 1;
    end

  always @(*)
    begin
      wUpdateTop1 = 0;
      wUpdateTop2 = 0;
      wUpdateTop3 = 0;
      wOffset     = 0;
      case (rState)
        FETCH_TOP1:
        begin
          wOffset     = 0;
          wUpdateTop1 = rMemoryCycle;
        end
        FETCH_TOP2:
        begin
          wOffset     = 1;
          wUpdateTop2 = rMemoryCycle;
        end
        FETCH_TOP3:
        begin
          wOffset     = 2;
          wUpdateTop3 = rMemoryCycle;
        end
        default:
        begin
          wOffset = 0;
        end
      endcase
    end

endmodule
module FetchStack #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (

    input  wire                clk,
    input  wire                reset,
    input  wire [dataBits-1:0] dataOut,
    output wire [addrBits-1:0] address,
    output wire                finished,
    input  wire [addrBits-1:0] stackPointer,
    output wire [dataBits-1:0] topOfStack1,
    output wire [dataBits-1:0] topOfStack2,
    output wire [dataBits-1:0] topOfStack3
  );




  reg [dataBits-1:0] rTop1, rTop2, rTop3;

  assign topOfStack1 = rTop1;
  assign topOfStack2 = rTop2;
  assign topOfStack3 = rTop3;

  reg [addrBits-1:0] wOffset;
  assign address = stackPointer + wOffset;

  assign finished = rState == FETCH_DONE;



  localparam FETCH_TOP1 = 2'd0;
  localparam FETCH_TOP2 = 2'd1;
  localparam FETCH_TOP3 = 2'd2;
  localparam FETCH_DONE = 2'd3;

  reg wUpdateTop1;
  reg wUpdateTop2;
  reg wUpdateTop3;

  reg [1:0] rState;
  reg       rMemoryCycle;

  always @(posedge clk)
    begin
      if (wUpdateTop1)
        rTop1 <= dataOut;
      if (wUpdateTop2)
        rTop2 <= dataOut;
      if (wUpdateTop3)
        rTop3 <= dataOut;

      if (!reset)
        rMemoryCycle <= 0;
      else
        rMemoryCycle <= rMemoryCycle + 1;

      if (!reset)
        rState <= 0;
      else if (rMemoryCycle)
        rState <= rState + 1;
    end

  always @(*)
    begin
      wUpdateTop1 = 0;
      wUpdateTop2 = 0;
      wUpdateTop3 = 0;
      wOffset     = 0;
      case (rState)
        FETCH_TOP1:
        begin
          wOffset     = 0;
          wUpdateTop1 = rMemoryCycle;
        end
        FETCH_TOP2:
        begin
          wOffset     = 1;
          wUpdateTop2 = rMemoryCycle;
        end
        FETCH_TOP3:
        begin
          wOffset     = 2;
          wUpdateTop3 = rMemoryCycle;
        end
        default:
        begin
          wOffset = 0;
        end
      endcase
    end

endmodule