data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n         ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n                ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) GSR = GSR_int;\n            ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) GSR = GSR_int;\n                   ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) GTS = GTS_int;\n            ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) GTS = GTS_int;\n                   ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) PRLD = PRLD_int;\n            ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n    assign (weak1, weak0) PRLD = PRLD_int;\n                   ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
   (s_rst_o,
    s_dclk_o,
    s_den_o,
    s_dwe_o,
    s_daddr_o,
    s_di_o,
    sl_oport_o,
    s_do_i,
    sl_iport_i,
    s_drdy_i);
  output s_rst_o;
  output s_dclk_o;
  output s_den_o;
  output s_dwe_o;
  output [16:0]s_daddr_o;
  output [15:0]s_di_o;
  output [16:0]sl_oport_o;
  input [15:0]s_do_i;
  input [36:0]sl_iport_i;
  input s_drdy_i;

  wire \G_1PIPE_IFACE.s_den_r_i_2_n_0 ;
  wire \G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ;
  wire [15:0]p_0_in;
  wire [10:0]reg_do;
  wire \reg_do[10]_i_2_n_0 ;
  wire \reg_do[15]_i_1_n_0 ;
  wire \reg_do[4]_i_2_n_0 ;
  wire \reg_do_reg_n_0_[0] ;
  wire \reg_do_reg_n_0_[10] ;
  wire \reg_do_reg_n_0_[11] ;
  wire \reg_do_reg_n_0_[12] ;
  wire \reg_do_reg_n_0_[13] ;
  wire \reg_do_reg_n_0_[14] ;
  wire \reg_do_reg_n_0_[15] ;
  wire \reg_do_reg_n_0_[1] ;
  wire \reg_do_reg_n_0_[2] ;
  wire \reg_do_reg_n_0_[3] ;
  wire \reg_do_reg_n_0_[4] ;
  wire \reg_do_reg_n_0_[5] ;
  wire \reg_do_reg_n_0_[6] ;
  wire \reg_do_reg_n_0_[7] ;
  wire \reg_do_reg_n_0_[8] ;
  wire \reg_do_reg_n_0_[9] ;
  wire reg_drdy;
  wire reg_drdy0;
  wire [15:0]reg_test;
  wire reg_test0;
  wire [16:0]s_daddr_o;
  wire s_den_o;
  wire s_den_r0;
  wire [15:0]s_di_o;
  wire [15:0]s_do_i;
  wire s_drdy_i;
  wire s_dwe_o;
  wire [36:0]sl_iport_i;
  wire [16:0]sl_oport_o;

  assign s_dclk_o = sl_iport_i[1];
  assign s_rst_o = sl_iport_i[0];
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[4]),
        .Q(s_daddr_o[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[14]),
        .Q(s_daddr_o[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[15]),
        .Q(s_daddr_o[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[16]),
        .Q(s_daddr_o[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[17]),
        .Q(s_daddr_o[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[18]),
        .Q(s_daddr_o[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[19]),
        .Q(s_daddr_o[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[16] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[20]),
        .Q(s_daddr_o[16]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[5]),
        .Q(s_daddr_o[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[6]),
        .Q(s_daddr_o[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[7]),
        .Q(s_daddr_o[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[8]),
        .Q(s_daddr_o[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[9]),
        .Q(s_daddr_o[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[10]),
        .Q(s_daddr_o[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[11]),
        .Q(s_daddr_o[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[12]),
        .Q(s_daddr_o[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[13]),
        .Q(s_daddr_o[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    \G_1PIPE_IFACE.s_den_r_i_1 
       (.I0(sl_iport_i[2]),
        .I1(sl_iport_i[14]),
        .I2(sl_iport_i[13]),
        .I3(sl_iport_i[12]),
        .I4(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ),
        .O(s_den_r0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \G_1PIPE_IFACE.s_den_r_i_2 
       (.I0(sl_iport_i[15]),
        .I1(sl_iport_i[16]),
        .I2(sl_iport_i[17]),
        .I3(sl_iport_i[18]),
        .I4(sl_iport_i[20]),
        .I5(sl_iport_i[19]),
        .O(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_den_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(s_den_r0),
        .Q(s_den_o),
        .R(sl_iport_i[0]));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[21]),
        .Q(s_di_o[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[31]),
        .Q(s_di_o[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[32]),
        .Q(s_di_o[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[33]),
        .Q(s_di_o[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[34]),
        .Q(s_di_o[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[35]),
        .Q(s_di_o[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[36]),
        .Q(s_di_o[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[22]),
        .Q(s_di_o[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[23]),
        .Q(s_di_o[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[24]),
        .Q(s_di_o[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[25]),
        .Q(s_di_o[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[26]),
        .Q(s_di_o[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[27]),
        .Q(s_di_o[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[28]),
        .Q(s_di_o[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[29]),
        .Q(s_di_o[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[30]),
        .Q(s_di_o[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[0]_i_1 
       (.I0(\reg_do_reg_n_0_[0] ),
        .I1(s_do_i[0]),
        .I2(reg_drdy),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[10]_i_1 
       (.I0(\reg_do_reg_n_0_[10] ),
        .I1(s_do_i[10]),
        .I2(reg_drdy),
        .O(p_0_in[10]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[11]_i_1 
       (.I0(\reg_do_reg_n_0_[11] ),
        .I1(s_do_i[11]),
        .I2(reg_drdy),
        .O(p_0_in[11]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[12]_i_1 
       (.I0(\reg_do_reg_n_0_[12] ),
        .I1(s_do_i[12]),
        .I2(reg_drdy),
        .O(p_0_in[12]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[13]_i_1 
       (.I0(\reg_do_reg_n_0_[13] ),
        .I1(s_do_i[13]),
        .I2(reg_drdy),
        .O(p_0_in[13]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[14]_i_1 
       (.I0(\reg_do_reg_n_0_[14] ),
        .I1(s_do_i[14]),
        .I2(reg_drdy),
        .O(p_0_in[14]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[15]_i_1 
       (.I0(\reg_do_reg_n_0_[15] ),
        .I1(s_do_i[15]),
        .I2(reg_drdy),
        .O(p_0_in[15]));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[1]_i_1 
       (.I0(\reg_do_reg_n_0_[1] ),
        .I1(s_do_i[1]),
        .I2(reg_drdy),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[2]_i_1 
       (.I0(\reg_do_reg_n_0_[2] ),
        .I1(s_do_i[2]),
        .I2(reg_drdy),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[3]_i_1 
       (.I0(\reg_do_reg_n_0_[3] ),
        .I1(s_do_i[3]),
        .I2(reg_drdy),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[4]_i_1 
       (.I0(\reg_do_reg_n_0_[4] ),
        .I1(s_do_i[4]),
        .I2(reg_drdy),
        .O(p_0_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[5]_i_1 
       (.I0(\reg_do_reg_n_0_[5] ),
        .I1(s_do_i[5]),
        .I2(reg_drdy),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[6]_i_1 
       (.I0(\reg_do_reg_n_0_[6] ),
        .I1(s_do_i[6]),
        .I2(reg_drdy),
        .O(p_0_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[7]_i_1 
       (.I0(\reg_do_reg_n_0_[7] ),
        .I1(s_do_i[7]),
        .I2(reg_drdy),
        .O(p_0_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[8]_i_1 
       (.I0(\reg_do_reg_n_0_[8] ),
        .I1(s_do_i[8]),
        .I2(reg_drdy),
        .O(p_0_in[8]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[9]_i_1 
       (.I0(\reg_do_reg_n_0_[9] ),
        .I1(s_do_i[9]),
        .I2(reg_drdy),
        .O(p_0_in[9]));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(sl_oport_o[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[10]),
        .Q(sl_oport_o[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[11]),
        .Q(sl_oport_o[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[12]),
        .Q(sl_oport_o[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[13]),
        .Q(sl_oport_o[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[14]),
        .Q(sl_oport_o[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[15]),
        .Q(sl_oport_o[16]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(sl_oport_o[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(sl_oport_o[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(sl_oport_o[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(sl_oport_o[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[5]),
        .Q(sl_oport_o[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[6]),
        .Q(sl_oport_o[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[7]),
        .Q(sl_oport_o[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[8]),
        .Q(sl_oport_o[9]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[9]),
        .Q(sl_oport_o[10]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \G_1PIPE_IFACE.s_drdy_r_i_1 
       (.I0(s_drdy_i),
        .I1(reg_drdy),
        .O(\G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_drdy_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ),
        .Q(sl_oport_o[0]),
        .R(sl_iport_i[0]));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_dwe_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[3]),
        .Q(s_dwe_o),
        .R(sl_iport_i[0]));
  LUT6 #(
    .INIT(64'hAAAAAAAAEAFFAAAA)) 
    \reg_do[0]_i_1 
       (.I0(\reg_do[4]_i_2_n_0 ),
        .I1(reg_test[0]),
        .I2(sl_iport_i[5]),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[8]),
        .I5(sl_iport_i[4]),
        .O(reg_do[0]));
  LUT5 #(
    .INIT(32'h20C0C000)) 
    \reg_do[10]_i_1 
       (.I0(reg_test[10]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[5]),
        .O(reg_do[10]));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \reg_do[10]_i_2 
       (.I0(sl_iport_i[8]),
        .I1(sl_iport_i[10]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[7]),
        .I4(sl_iport_i[9]),
        .O(\reg_do[10]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFF7F)) 
    \reg_do[15]_i_1 
       (.I0(sl_iport_i[5]),
        .I1(sl_iport_i[6]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[4]),
        .O(\reg_do[15]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h20C000C0)) 
    \reg_do[1]_i_1 
       (.I0(reg_test[1]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[5]),
        .O(reg_do[1]));
  LUT5 #(
    .INIT(32'h0000D000)) 
    \reg_do[2]_i_1 
       (.I0(sl_iport_i[5]),
        .I1(reg_test[2]),
        .I2(sl_iport_i[6]),
        .I3(\reg_do[10]_i_2_n_0 ),
        .I4(sl_iport_i[4]),
        .O(reg_do[2]));
  LUT6 #(
    .INIT(64'hAAEAAAAAAAAAAAFA)) 
    \reg_do[4]_i_1 
       (.I0(\reg_do[4]_i_2_n_0 ),
        .I1(reg_test[4]),
        .I2(sl_iport_i[8]),
        .I3(sl_iport_i[4]),
        .I4(sl_iport_i[5]),
        .I5(sl_iport_i[6]),
        .O(reg_do[4]));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT5 #(
    .INIT(32'hBFFFFFFC)) 
    \reg_do[4]_i_2 
       (.I0(sl_iport_i[7]),
        .I1(sl_iport_i[8]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[10]),
        .I4(sl_iport_i[9]),
        .O(\reg_do[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h2000C000)) 
    \reg_do[5]_i_1 
       (.I0(reg_test[5]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[5]),
        .O(reg_do[5]));
  LUT5 #(
    .INIT(32'h2000C000)) 
    \reg_do[6]_i_1 
       (.I0(reg_test[6]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[5]),
        .O(reg_do[6]));
  LUT5 #(
    .INIT(32'h2000C000)) 
    \reg_do[7]_i_1 
       (.I0(reg_test[7]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[5]),
        .O(reg_do[7]));
  LUT5 #(
    .INIT(32'h2F000000)) 
    \reg_do[8]_i_1 
       (.I0(reg_test[8]),
        .I1(sl_iport_i[4]),
        .I2(sl_iport_i[5]),
        .I3(\reg_do[10]_i_2_n_0 ),
        .I4(sl_iport_i[6]),
        .O(reg_do[8]));
  LUT5 #(
    .INIT(32'h20C0C000)) 
    \reg_do[9]_i_1 
       (.I0(reg_test[9]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[5]),
        .O(reg_do[9]));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[0]),
        .Q(\reg_do_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[10]),
        .Q(\reg_do_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[11]),
        .Q(\reg_do_reg_n_0_[11] ),
        .R(\reg_do[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[12]),
        .Q(\reg_do_reg_n_0_[12] ),
        .R(\reg_do[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[13]),
        .Q(\reg_do_reg_n_0_[13] ),
        .R(\reg_do[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[14]),
        .Q(\reg_do_reg_n_0_[14] ),
        .R(\reg_do[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[15]),
        .Q(\reg_do_reg_n_0_[15] ),
        .R(\reg_do[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[1]),
        .Q(\reg_do_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[2]),
        .Q(\reg_do_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[3]),
        .Q(\reg_do_reg_n_0_[3] ),
        .R(\reg_do[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[4]),
        .Q(\reg_do_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[5]),
        .Q(\reg_do_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[6]),
        .Q(\reg_do_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[7]),
        .Q(\reg_do_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[8]),
        .Q(\reg_do_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[9]),
        .Q(\reg_do_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    reg_drdy_i_1
       (.I0(sl_iport_i[14]),
        .I1(sl_iport_i[13]),
        .I2(sl_iport_i[12]),
        .I3(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ),
        .I4(sl_iport_i[2]),
        .O(reg_drdy0));
  FDRE #(
    .INIT(1'b0)) 
    reg_drdy_reg
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_drdy0),
        .Q(reg_drdy),
        .R(sl_iport_i[0]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \reg_test[15]_i_1 
       (.I0(sl_iport_i[3]),
        .I1(sl_iport_i[2]),
        .I2(sl_iport_i[14]),
        .I3(sl_iport_i[13]),
        .I4(sl_iport_i[12]),
        .I5(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ),
        .O(reg_test0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[21]),
        .Q(reg_test[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[31]),
        .Q(reg_test[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[32]),
        .Q(reg_test[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[33]),
        .Q(reg_test[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[34]),
        .Q(reg_test[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[35]),
        .Q(reg_test[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[36]),
        .Q(reg_test[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[22]),
        .Q(reg_test[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[23]),
        .Q(reg_test[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[24]),
        .Q(reg_test[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[25]),
        .Q(reg_test[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[26]),
        .Q(reg_test[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[27]),
        .Q(reg_test[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[28]),
        .Q(reg_test[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[29]),
        .Q(reg_test[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[30]),
        .Q(reg_test[9]),
        .R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
   (s_rst_o,
    s_dclk_o,
    s_den_o,
    s_dwe_o,
    s_daddr_o,
    s_di_o,
    sl_oport_o,
    s_do_i,
    sl_iport_i,
    s_drdy_i);

  output s_rst_o;
  output s_dclk_o;
  output s_den_o;
  output s_dwe_o;
  output [16:0]s_daddr_o;
  output [15:0]s_di_o;
  output [16:0]sl_oport_o;
  input [15:0]s_do_i;
  input [36:0]sl_iport_i;
  input s_drdy_i;

  wire \G_1PIPE_IFACE.s_den_r_i_2_n_0 ;
  wire \G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ;
  wire [15:0]p_0_in;
  wire [10:0]reg_do;
  wire \reg_do[10]_i_2_n_0 ;
  wire \reg_do[15]_i_1_n_0 ;
  wire \reg_do[4]_i_2_n_0 ;
  wire \reg_do_reg_n_0_[0] ;
  wire \reg_do_reg_n_0_[10] ;
  wire \reg_do_reg_n_0_[11] ;
  wire \reg_do_reg_n_0_[12] ;
  wire \reg_do_reg_n_0_[13] ;
  wire \reg_do_reg_n_0_[14] ;
  wire \reg_do_reg_n_0_[15] ;
  wire \reg_do_reg_n_0_[1] ;
  wire \reg_do_reg_n_0_[2] ;
  wire \reg_do_reg_n_0_[3] ;
  wire \reg_do_reg_n_0_[4] ;
  wire \reg_do_reg_n_0_[5] ;
  wire \reg_do_reg_n_0_[6] ;
  wire \reg_do_reg_n_0_[7] ;
  wire \reg_do_reg_n_0_[8] ;
  wire \reg_do_reg_n_0_[9] ;
  wire reg_drdy;
  wire reg_drdy0;
  wire [15:0]reg_test;
  wire reg_test0;
  wire [16:0]s_daddr_o;
  wire s_den_o;
  wire s_den_r0;
  wire [15:0]s_di_o;
  wire [15:0]s_do_i;
  wire s_drdy_i;
  wire s_dwe_o;
  wire [36:0]sl_iport_i;
  wire [16:0]sl_oport_o;

  assign s_dclk_o = sl_iport_i[1];
  assign s_rst_o = sl_iport_i[0];
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[4]),
        .Q(s_daddr_o[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[14]),
        .Q(s_daddr_o[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[15]),
        .Q(s_daddr_o[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[16]),
        .Q(s_daddr_o[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[17]),
        .Q(s_daddr_o[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[18]),
        .Q(s_daddr_o[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[19]),
        .Q(s_daddr_o[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[16] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[20]),
        .Q(s_daddr_o[16]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[5]),
        .Q(s_daddr_o[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[6]),
        .Q(s_daddr_o[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[7]),
        .Q(s_daddr_o[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[8]),
        .Q(s_daddr_o[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[9]),
        .Q(s_daddr_o[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[10]),
        .Q(s_daddr_o[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[11]),
        .Q(s_daddr_o[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[12]),
        .Q(s_daddr_o[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[13]),
        .Q(s_daddr_o[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    \G_1PIPE_IFACE.s_den_r_i_1 
       (.I0(sl_iport_i[2]),
        .I1(sl_iport_i[14]),
        .I2(sl_iport_i[13]),
        .I3(sl_iport_i[12]),
        .I4(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ),
        .O(s_den_r0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \G_1PIPE_IFACE.s_den_r_i_2 
       (.I0(sl_iport_i[15]),
        .I1(sl_iport_i[16]),
        .I2(sl_iport_i[17]),
        .I3(sl_iport_i[18]),
        .I4(sl_iport_i[20]),
        .I5(sl_iport_i[19]),
        .O(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_den_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(s_den_r0),
        .Q(s_den_o),
        .R(sl_iport_i[0]));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[21]),
        .Q(s_di_o[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[31]),
        .Q(s_di_o[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[32]),
        .Q(s_di_o[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[33]),
        .Q(s_di_o[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[34]),
        .Q(s_di_o[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[35]),
        .Q(s_di_o[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[36]),
        .Q(s_di_o[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[22]),
        .Q(s_di_o[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[23]),
        .Q(s_di_o[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[24]),
        .Q(s_di_o[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[25]),
        .Q(s_di_o[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[26]),
        .Q(s_di_o[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[27]),
        .Q(s_di_o[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[28]),
        .Q(s_di_o[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[29]),
        .Q(s_di_o[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[30]),
        .Q(s_di_o[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[0]_i_1 
       (.I0(\reg_do_reg_n_0_[0] ),
        .I1(s_do_i[0]),
        .I2(reg_drdy),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[10]_i_1 
       (.I0(\reg_do_reg_n_0_[10] ),
        .I1(s_do_i[10]),
        .I2(reg_drdy),
        .O(p_0_in[10]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[11]_i_1 
       (.I0(\reg_do_reg_n_0_[11] ),
        .I1(s_do_i[11]),
        .I2(reg_drdy),
        .O(p_0_in[11]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[12]_i_1 
       (.I0(\reg_do_reg_n_0_[12] ),
        .I1(s_do_i[12]),
        .I2(reg_drdy),
        .O(p_0_in[12]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[13]_i_1 
       (.I0(\reg_do_reg_n_0_[13] ),
        .I1(s_do_i[13]),
        .I2(reg_drdy),
        .O(p_0_in[13]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[14]_i_1 
       (.I0(\reg_do_reg_n_0_[14] ),
        .I1(s_do_i[14]),
        .I2(reg_drdy),
        .O(p_0_in[14]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[15]_i_1 
       (.I0(\reg_do_reg_n_0_[15] ),
        .I1(s_do_i[15]),
        .I2(reg_drdy),
        .O(p_0_in[15]));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[1]_i_1 
       (.I0(\reg_do_reg_n_0_[1] ),
        .I1(s_do_i[1]),
        .I2(reg_drdy),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[2]_i_1 
       (.I0(\reg_do_reg_n_0_[2] ),
        .I1(s_do_i[2]),
        .I2(reg_drdy),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[3]_i_1 
       (.I0(\reg_do_reg_n_0_[3] ),
        .I1(s_do_i[3]),
        .I2(reg_drdy),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[4]_i_1 
       (.I0(\reg_do_reg_n_0_[4] ),
        .I1(s_do_i[4]),
        .I2(reg_drdy),
        .O(p_0_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[5]_i_1 
       (.I0(\reg_do_reg_n_0_[5] ),
        .I1(s_do_i[5]),
        .I2(reg_drdy),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[6]_i_1 
       (.I0(\reg_do_reg_n_0_[6] ),
        .I1(s_do_i[6]),
        .I2(reg_drdy),
        .O(p_0_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[7]_i_1 
       (.I0(\reg_do_reg_n_0_[7] ),
        .I1(s_do_i[7]),
        .I2(reg_drdy),
        .O(p_0_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[8]_i_1 
       (.I0(\reg_do_reg_n_0_[8] ),
        .I1(s_do_i[8]),
        .I2(reg_drdy),
        .O(p_0_in[8]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[9]_i_1 
       (.I0(\reg_do_reg_n_0_[9] ),
        .I1(s_do_i[9]),
        .I2(reg_drdy),
        .O(p_0_in[9]));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(sl_oport_o[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[10]),
        .Q(sl_oport_o[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[11]),
        .Q(sl_oport_o[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[12]),
        .Q(sl_oport_o[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[13]),
        .Q(sl_oport_o[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[14]),
        .Q(sl_oport_o[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[15]),
        .Q(sl_oport_o[16]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(sl_oport_o[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(sl_oport_o[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(sl_oport_o[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(sl_oport_o[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[5]),
        .Q(sl_oport_o[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[6]),
        .Q(sl_oport_o[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[7]),
        .Q(sl_oport_o[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[8]),
        .Q(sl_oport_o[9]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[9]),
        .Q(sl_oport_o[10]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \G_1PIPE_IFACE.s_drdy_r_i_1 
       (.I0(s_drdy_i),
        .I1(reg_drdy),
        .O(\G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_drdy_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ),
        .Q(sl_oport_o[0]),
        .R(sl_iport_i[0]));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_dwe_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[3]),
        .Q(s_dwe_o),
        .R(sl_iport_i[0]));
  LUT6 #(
    .INIT(64'hAAAAAAAAEAFFAAAA)) 
    \reg_do[0]_i_1 
       (.I0(\reg_do[4]_i_2_n_0 ),
        .I1(reg_test[0]),
        .I2(sl_iport_i[5]),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[8]),
        .I5(sl_iport_i[4]),
        .O(reg_do[0]));
  LUT5 #(
    .INIT(32'h20C0C000)) 
    \reg_do[10]_i_1 
       (.I0(reg_test[10]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[5]),
        .O(reg_do[10]));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \reg_do[10]_i_2 
       (.I0(sl_iport_i[8]),
        .I1(sl_iport_i[10]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[7]),
        .I4(sl_iport_i[9]),
        .O(\reg_do[10]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFF7F)) 
    \reg_do[15]_i_1 
       (.I0(sl_iport_i[5]),
        .I1(sl_iport_i[6]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[4]),
        .O(\reg_do[15]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h20C000C0)) 
    \reg_do[1]_i_1 
       (.I0(reg_test[1]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[5]),
        .O(reg_do[1]));
  LUT5 #(
    .INIT(32'h0000D000)) 
    \reg_do[2]_i_1 
       (.I0(sl_iport_i[5]),
        .I1(reg_test[2]),
        .I2(sl_iport_i[6]),
        .I3(\reg_do[10]_i_2_n_0 ),
        .I4(sl_iport_i[4]),
        .O(reg_do[2]));
  LUT6 #(
    .INIT(64'hAAEAAAAAAAAAAAFA)) 
    \reg_do[4]_i_1 
       (.I0(\reg_do[4]_i_2_n_0 ),
        .I1(reg_test[4]),
        .I2(sl_iport_i[8]),
        .I3(sl_iport_i[4]),
        .I4(sl_iport_i[5]),
        .I5(sl_iport_i[6]),
        .O(reg_do[4]));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT5 #(
    .INIT(32'hBFFFFFFC)) 
    \reg_do[4]_i_2 
       (.I0(sl_iport_i[7]),
        .I1(sl_iport_i[8]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[10]),
        .I4(sl_iport_i[9]),
        .O(\reg_do[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h2000C000)) 
    \reg_do[5]_i_1 
       (.I0(reg_test[5]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[5]),
        .O(reg_do[5]));
  LUT5 #(
    .INIT(32'h2000C000)) 
    \reg_do[6]_i_1 
       (.I0(reg_test[6]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[5]),
        .O(reg_do[6]));
  LUT5 #(
    .INIT(32'h2000C000)) 
    \reg_do[7]_i_1 
       (.I0(reg_test[7]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[5]),
        .O(reg_do[7]));
  LUT5 #(
    .INIT(32'h2F000000)) 
    \reg_do[8]_i_1 
       (.I0(reg_test[8]),
        .I1(sl_iport_i[4]),
        .I2(sl_iport_i[5]),
        .I3(\reg_do[10]_i_2_n_0 ),
        .I4(sl_iport_i[6]),
        .O(reg_do[8]));
  LUT5 #(
    .INIT(32'h20C0C000)) 
    \reg_do[9]_i_1 
       (.I0(reg_test[9]),
        .I1(sl_iport_i[4]),
        .I2(\reg_do[10]_i_2_n_0 ),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[5]),
        .O(reg_do[9]));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[0]),
        .Q(\reg_do_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[10]),
        .Q(\reg_do_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[11]),
        .Q(\reg_do_reg_n_0_[11] ),
        .R(\reg_do[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[12]),
        .Q(\reg_do_reg_n_0_[12] ),
        .R(\reg_do[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[13]),
        .Q(\reg_do_reg_n_0_[13] ),
        .R(\reg_do[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[14]),
        .Q(\reg_do_reg_n_0_[14] ),
        .R(\reg_do[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[15]),
        .Q(\reg_do_reg_n_0_[15] ),
        .R(\reg_do[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[1]),
        .Q(\reg_do_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[2]),
        .Q(\reg_do_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[3]),
        .Q(\reg_do_reg_n_0_[3] ),
        .R(\reg_do[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[4]),
        .Q(\reg_do_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[5]),
        .Q(\reg_do_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[6]),
        .Q(\reg_do_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[7]),
        .Q(\reg_do_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[8]),
        .Q(\reg_do_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[9]),
        .Q(\reg_do_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    reg_drdy_i_1
       (.I0(sl_iport_i[14]),
        .I1(sl_iport_i[13]),
        .I2(sl_iport_i[12]),
        .I3(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ),
        .I4(sl_iport_i[2]),
        .O(reg_drdy0));
  FDRE #(
    .INIT(1'b0)) 
    reg_drdy_reg
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_drdy0),
        .Q(reg_drdy),
        .R(sl_iport_i[0]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \reg_test[15]_i_1 
       (.I0(sl_iport_i[3]),
        .I1(sl_iport_i[2]),
        .I2(sl_iport_i[14]),
        .I3(sl_iport_i[13]),
        .I4(sl_iport_i[12]),
        .I5(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ),
        .O(reg_test0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[21]),
        .Q(reg_test[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[31]),
        .Q(reg_test[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[32]),
        .Q(reg_test[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[33]),
        .Q(reg_test[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[34]),
        .Q(reg_test[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[35]),
        .Q(reg_test[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[36]),
        .Q(reg_test[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[22]),
        .Q(reg_test[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[23]),
        .Q(reg_test[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[24]),
        .Q(reg_test[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[25]),
        .Q(reg_test[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[26]),
        .Q(reg_test[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[27]),
        .Q(reg_test[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[28]),
        .Q(reg_test[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[29]),
        .Q(reg_test[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[30]),
        .Q(reg_test[9]),
        .R(1'b0));
endmodule