data/full_repos/permissive/170267528/state1/tclProject/impSRAM/sram_init.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/4e1c371b-5c4c-45be-b0e7-4284f9e8ed21.xml
module sram_init (
	input CLK,
	input RSTn,
	
	input enable,
	input [31:0] data,

	output reg [18:0] SRAM_ADDR_Stream,
	output reg [31:0] SRAM_DATA_IN_Stream
);

reg [1:0] selCnt;
reg [31:0] data_out;

always @(posedge CLK)begin

	if (!RSTn) begin
		SRAM_ADDR_Stream <= 19'b0;
		SRAM_DATA_IN_Stream  <= 32'b0;
		selCnt <= 2'b0;
		data_out <= 32'd0;
	end
	else begin
		if ( enable == 1'b0 ) begin 
			SRAM_ADDR_Stream <= 19'b0;
			SRAM_DATA_IN_Stream  <= 32'b0;
			selCnt <= 2'b0;
			data_out <= 32'd0;
		end

		else begin
			
			case (selCnt)
				2'b00:begin

					SRAM_ADDR_Stream <= SRAM_ADDR_Stream;
					SRAM_DATA_IN_Stream <= data_out;
					data_out <= data;
				end


















			endcase

		end
	end
end



endmodule
module sram_init (
	input CLK,
	input RSTn,
	
	input enable,
	input [31:0] data,

	output reg [18:0] SRAM_ADDR_Stream,
	output reg [31:0] SRAM_DATA_IN_Stream
);


reg [1:0] selCnt;
reg [31:0] data_out;

always @(posedge CLK)begin

	if (!RSTn) begin
		SRAM_ADDR_Stream <= 19'b0;
		SRAM_DATA_IN_Stream  <= 32'b0;
		selCnt <= 2'b0;
		data_out <= 32'd0;
	end
	else begin
		if ( enable == 1'b0 ) begin 
			SRAM_ADDR_Stream <= 19'b0;
			SRAM_DATA_IN_Stream  <= 32'b0;
			selCnt <= 2'b0;
			data_out <= 32'd0;
		end

		else begin
			
			case (selCnt)
				2'b00:begin

					SRAM_ADDR_Stream <= SRAM_ADDR_Stream;
					SRAM_DATA_IN_Stream <= data_out;
					data_out <= data;
				end


















			endcase

		end
	end
end



endmodule