data/full_repos/permissive/143278/fpga_tests/ge8_tb.v
 line:17: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/ge8_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #1 $display("%b >= %b: %b", A, B, out);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/fpga_tests/ge8_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n     #1 $write("%b >= %b: %b", A, B, out);\n     ^\n%Error: data/full_repos/permissive/143278/fpga_tests/ge8_tb.v:9: Cannot find file containing module: \'ge8\'\n   ge8 dut(.out(out), .A(A), .B(B));\n   ^~~\n        ... Looked in:\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/ge8\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/ge8.v\n             data/full_repos/permissive/143278/fpga_tests,data/full_repos/permissive/143278/ge8.sv\n             ge8\n             ge8.v\n             ge8.sv\n             obj_dir/ge8\n             obj_dir/ge8.v\n             obj_dir/ge8.sv\n%Warning-WIDTH: data/full_repos/permissive/143278/fpga_tests/ge8_tb.v:20: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'adx\' generates 32 bits.\n                                                                        : ... In instance main\n  A = adx;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/fpga_tests/ge8_tb.v:22: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'bdx\' generates 32 bits.\n                                                                        : ... In instance main\n     B = bdx;\n       ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   wire out;
   reg [7:0] A, B;

   ge8 dut(.out(out), .A(A), .B(B));

   reg	     error = 0;
   integer   adx, bdx;

   initial begin
      A = 0;
      B = 0;
      #1 $display("%b >= %b: %b", A, B, out);

      for (adx = 0 ;  adx < 256 ;  adx = adx + 1) begin
	 A = adx;
	 for (bdx = 0 ;  bdx < 256 ;  bdx = bdx + 1) begin
	    B = bdx;
	    #1 $write("%b >= %b: %b", A, B, out);
	    if (out === 1) begin
	       if (A < B) begin
		  $display(" ERROR");
		  error = 1;
	       end else begin
		  $display(" OK");
	       end

	    end else if (out === 0) begin
	       if (A < B) begin
		  $display(" OK");
	       end else begin
		  $display(" ERROR");
		  error = 1;
	       end

	    end else begin
	       $display(" ERROR");
	       error = 1;
	    end

	 end
      end

      if (error == 0)
	$display("PASSED");
      else
	$display("FAILED");

   end
endmodule
module main;


   wire out;
   reg [7:0] A, B;

   ge8 dut(.out(out), .A(A), .B(B));

   reg	     error = 0;
   integer   adx, bdx;

   initial begin
      A = 0;
      B = 0;
      #1 $display("%b >= %b: %b", A, B, out);

      for (adx = 0 ;  adx < 256 ;  adx = adx + 1) begin
	 A = adx;
	 for (bdx = 0 ;  bdx < 256 ;  bdx = bdx + 1) begin
	    B = bdx;
	    #1 $write("%b >= %b: %b", A, B, out);
	    if (out === 1) begin
	       if (A < B) begin
		  $display(" ERROR");
		  error = 1;
	       end else begin
		  $display(" OK");
	       end

	    end else if (out === 0) begin
	       if (A < B) begin
		  $display(" OK");
	       end else begin
		  $display(" ERROR");
		  error = 1;
	       end

	    end else begin
	       $display(" ERROR");
	       error = 1;
	    end

	 end
      end

      if (error == 0)
	$display("PASSED");
      else
	$display("FAILED");

   end
endmodule