data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v
None: at end of input
1: b'%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:24: Cannot find include file: raggedstone_spinn_aer_if_top.h\n`include "raggedstone_spinn_aer_if_top.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if,data/full_repos/permissive/156407853/raggedstone_spinn_aer_if_top.h\n             data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if,data/full_repos/permissive/156407853/raggedstone_spinn_aer_if_top.h.v\n             data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if,data/full_repos/permissive/156407853/raggedstone_spinn_aer_if_top.h.sv\n             raggedstone_spinn_aer_if_top.h\n             raggedstone_spinn_aer_if_top.h.v\n             raggedstone_spinn_aer_if_top.h.sv\n             obj_dir/raggedstone_spinn_aer_if_top.h\n             obj_dir/raggedstone_spinn_aer_if_top.h.v\n             obj_dir/raggedstone_spinn_aer_if_top.h.sv\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:37: Define or directive not defined: \'`MODE_BITS\'\n  output reg  [`MODE_BITS - 1:0] msel,\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:38: Define or directive not defined: \'`VKS_BITS\'\n  output reg   [`VKS_BITS - 1:0] vksel,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:126: Define or directive not defined: \'`LAST_MODE\'\n        if (msel == `LAST_MODE)\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        if (msel == `LAST_MODE)\n                              ^\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:136: Define or directive not defined: \'`LAST_MODE\'\n      if ((sel_state == 0) && (mode_sel == 1\'b0) && (msel == `LAST_MODE))\n                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:136: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if ((sel_state == 0) && (mode_sel == 1\'b0) && (msel == `LAST_MODE))\n                                                                       ^\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:138: Define or directive not defined: \'`LAST_VKS\'\n        if (vksel == `LAST_VKS)\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:194: Define or directive not defined: \'`VKS_ALT\'\n      `VKS_ALT: point <= 4\'b1110;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:194: syntax error, unexpected \':\', expecting endcase\n      `VKS_ALT: point <= 4\'b1110;\n              ^\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:206: Define or directive not defined: \'`RET_128\'\n      `RET_128:\n      ^~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:214: Define or directive not defined: \'`RET_64\'\n      `RET_64:\n      ^~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:222: Define or directive not defined: \'`RET_32\'\n      `RET_32:\n      ^~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:230: Define or directive not defined: \'`RET_16\'\n      `RET_16:\n      ^~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:238: Define or directive not defined: \'`COCHLEA\'\n      `COCHLEA:\n      ^~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/raggedstone_spinn_aer_if/raggedstone_spinn_aer_if_user_int.v:246: Define or directive not defined: \'`DIRECT\'\n      `DIRECT:\n      ^~~~~~~\n%Error: Exiting due to 16 error(s)\n'
function [6:0] bcd2sevenSeg;
    input [3:0] bcd;
    case (bcd)
            0: bcd2sevenSeg = 7'b000_0001;
            1: bcd2sevenSeg = 7'b100_1111;
            2: bcd2sevenSeg = 7'b001_0010;
            3: bcd2sevenSeg = 7'b000_0110;
            4: bcd2sevenSeg = 7'b100_1100;
            5: bcd2sevenSeg = 7'b010_0100;
            6: bcd2sevenSeg = 7'b110_0000;
            7: bcd2sevenSeg = 7'b000_1111;
            8: bcd2sevenSeg = 7'b000_0000;
            9: bcd2sevenSeg = 7'b000_1100;
           10: bcd2sevenSeg = 7'b111_1111;
           11: bcd2sevenSeg = 7'b111_0010;
           12: bcd2sevenSeg = 7'b110_0010;
           13: bcd2sevenSeg = 7'b110_1000;
      default: bcd2sevenSeg = 7'b111_1111;
    endcase
  endfunction
function [6:0] bcd2sevenSeg;

    input [3:0] bcd;
    case (bcd)
            0: bcd2sevenSeg = 7'b000_0001;
            1: bcd2sevenSeg = 7'b100_1111;
            2: bcd2sevenSeg = 7'b001_0010;
            3: bcd2sevenSeg = 7'b000_0110;
            4: bcd2sevenSeg = 7'b100_1100;
            5: bcd2sevenSeg = 7'b010_0100;
            6: bcd2sevenSeg = 7'b110_0000;
            7: bcd2sevenSeg = 7'b000_1111;
            8: bcd2sevenSeg = 7'b000_0000;
            9: bcd2sevenSeg = 7'b000_1100;
           10: bcd2sevenSeg = 7'b111_1111;
           11: bcd2sevenSeg = 7'b111_0010;
           12: bcd2sevenSeg = 7'b110_0010;
           13: bcd2sevenSeg = 7'b110_1000;
      default: bcd2sevenSeg = 7'b111_1111;
    endcase
  endfunction