data/full_repos/permissive/206301883/pass_next.v
1: b'%Warning-WIDTH: data/full_repos/permissive/206301883/pass_next.v:49: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'10\'h3fd\' generates 10 bits.\n                                                                   : ... In instance pass_next\n        if (counter == 10\'h3FD)  \n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pass_next(
input wire [31:0]data_in,
input wire [31:0]data_in_time,
input wire [31:0]data_in_tx,
output reg [31:0]data_out,
input wire r_next,
input wire new_tx,

input wire res
 );


reg switch = 0;
reg [31:0]counter = 0;
reg flag = 0;
reg r1, r2;

always @(posedge r_next) begin
    r1 <= new_tx;
    r2 <= r1;
end

always @(posedge r_next) 
begin       
            if (switch==0) begin
                    if (flag) begin
                        data_out <= data_in_tx;
                    end else begin
                        data_out <=data_in;
                    end
            end 
            else begin
                   if (flag) begin
                        data_out <= data_in_tx;
                   end else begin
                        data_out <=data_in_time;
                   end
            end
end

always @(negedge r_next or posedge new_tx)
begin
        switch <= ~switch;
        if (new_tx) begin
        counter <=0;
        flag <= 0;
        end else begin
        if (counter == 10'h3FD)
            begin
            counter <=0;
            flag <= 1;
            end
        else begin 
            counter <= counter + 1'h1; 
            flag <= 0;
            end
         end
end

endmodule
module pass_next(
input wire [31:0]data_in,
input wire [31:0]data_in_time,
input wire [31:0]data_in_tx,
output reg [31:0]data_out,
input wire r_next,
input wire new_tx,

input wire res
 );



reg switch = 0;
reg [31:0]counter = 0;
reg flag = 0;
reg r1, r2;

always @(posedge r_next) begin
    r1 <= new_tx;
    r2 <= r1;
end

always @(posedge r_next) 
begin       
            if (switch==0) begin
                    if (flag) begin
                        data_out <= data_in_tx;
                    end else begin
                        data_out <=data_in;
                    end
            end 
            else begin
                   if (flag) begin
                        data_out <= data_in_tx;
                   end else begin
                        data_out <=data_in_time;
                   end
            end
end

always @(negedge r_next or posedge new_tx)
begin
        switch <= ~switch;
        if (new_tx) begin
        counter <=0;
        flag <= 0;
        end else begin
        if (counter == 10'h3FD)
            begin
            counter <=0;
            flag <= 1;
            end
        else begin 
            counter <= counter + 1'h1; 
            flag <= 0;
            end
         end
end

endmodule