data/full_repos/permissive/201196900/Verilog_32BitPriorityEncoder/Verilog/PriorityEncoderWithLadnerFischer.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/201196900/Verilog_32BitPriorityEncoder/Verilog/PriorityEncoderWithLadnerFischer.v:78: Cell has missing pin: \'A32N\'\nAND_A_NOT_GATE  AND_A_NOT_GATE(.A1N(orOut16_0_Q15), .B1(orOut16_0_Q16), .A2N(orOut16_0_Q14), .B2(orOut16_0_Q15), .A3N(orOut16_0_Q13), .B3(orOut16_0_Q14), .A4N(orOut16_0_Q12), .B4(orOut16_0_Q13),\n                ^~~~~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module OR2GATE(input A, input B, output Q);
assign Q=A|B;
endmodule
module OR2GATE(input A, input B, output Q);

assign Q=A|B;
endmodule