data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer/user_logic.v
 line:1: before: "@"
1: b'%Error: data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer/user_logic.v:102: Cannot find file containing module: \'map_reducer\'\nmap_reducer #(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer,data/full_repos/permissive/15244593/map_reducer\n             data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer,data/full_repos/permissive/15244593/map_reducer.v\n             data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer,data/full_repos/permissive/15244593/map_reducer.sv\n             map_reducer\n             map_reducer.v\n             map_reducer.sv\n             obj_dir/map_reducer\n             obj_dir/map_reducer.v\n             obj_dir/map_reducer.sv\n%Error: data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer/user_logic.v:114: Cannot find file containing module: \'map_reducer\'\nmap_reducer #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer/user_logic.v:125: Cannot find file containing module: \'map_reducer\'\nmap_reducer #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer/user_logic.v:136: Cannot find file containing module: \'map_reducer\'\nmap_reducer #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer/user_logic.v:148: Cannot find file containing module: \'map_reducer\'\nmap_reducer #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer/user_logic.v:159: Cannot find file containing module: \'map_reducer\'\nmap_reducer #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer/user_logic.v:170: Cannot find file containing module: \'map_reducer\'\nmap_reducer #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer/user_logic.v:181: Cannot find file containing module: \'map_reducer\'\nmap_reducer #(\n^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/15244593/src/hw/fpga/source/userlogic/mapreducer/user_logic.v:192: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'o_pcie_str1_data\' generates 64 bits.\n                                                                                                            : ... In instance user_logic\nassign o_user_data = o_pcie_str1_data;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module user_logic(
    input              i_pcie_clk,
    input              i_ddr_clk,
    input              i_user_clk,
    input              i_rst,

    input    [31:0]    i_user_data,
    input    [19:0]    i_user_addr,
    input              i_user_wr_req,
    output      [31:0] o_user_data,
    output  reg        o_user_rd_ack,
    input              i_user_rd_req, 

    output   [255:0]   o_ddr_wr_data,
    output   [31:0]    o_ddr_wr_data_be_n,
    output             o_ddr_wr_data_valid,
    output   [26:0]    o_ddr_addr,
    output             o_ddr_rd,
    input    [255:0]   i_ddr_rd_data,
    input              i_ddr_rd_data_valid,
    input              i_ddr_wr_ack,
    input              i_ddr_rd_ack,

    input              i_ddr_str1_data_valid,
    output             o_ddr_str1_ack,
    input        [63:0]i_ddr_str1_data,
    output             o_ddr_str1_data_valid,
    input              i_ddr_str1_ack,
    output       [63:0]o_ddr_str1_data,

    input              i_ddr_str2_data_valid,
    output             o_ddr_str2_ack,
    input        [63:0]i_ddr_str2_data,
    output             o_ddr_str2_data_valid,
    input              i_ddr_str2_ack,
    output       [63:0]o_ddr_str2_data,

    input              i_ddr_str3_data_valid,
    output             o_ddr_str3_ack,
    input        [63:0]i_ddr_str3_data,
    output             o_ddr_str3_data_valid,
    input              i_ddr_str3_ack,
    output       [63:0]o_ddr_str3_data,	 

    input              i_ddr_str4_data_valid,
    output             o_ddr_str4_ack,
    input        [63:0]i_ddr_str4_data,
    output             o_ddr_str4_data_valid,
    input              i_ddr_str4_ack,
    output       [63:0]o_ddr_str4_data,

    input              i_pcie_str1_data_valid,
    output             o_pcie_str1_ack,
    input    [63:0]    i_pcie_str1_data,
    output             o_pcie_str1_data_valid,
    input              i_pcie_str1_ack,
    output   [63:0]    o_pcie_str1_data,

    input              i_pcie_str2_data_valid,
    output             o_pcie_str2_ack,
    input    [63:0]    i_pcie_str2_data,
    output             o_pcie_str2_data_valid,
    input              i_pcie_str2_ack,
    output   [63:0]    o_pcie_str2_data,

    input              i_pcie_str3_data_valid,
    output             o_pcie_str3_ack,
    input    [63:0]    i_pcie_str3_data,
    output             o_pcie_str3_data_valid,
    input              i_pcie_str3_ack,
    output   [63:0]    o_pcie_str3_data,

    input              i_pcie_str4_data_valid,
    output             o_pcie_str4_ack,
    input    [63:0]    i_pcie_str4_data,
    output             o_pcie_str4_data_valid,
    input              i_pcie_str4_ack,
    output   [63:0]    o_pcie_str4_data,

    output             o_intr_req,
    input              i_intr_ack
);

assign o_intr_req             = 1'b0;
assign o_pcie_str1_data_valid = 1'b1;
assign o_pcie_str2_data_valid = 1'b1;
assign o_pcie_str3_data_valid = 1'b1;
assign o_pcie_str4_data_valid = 1'b1;
assign o_ddr_str1_data_valid  = 1'b1;
assign o_ddr_str2_data_valid  = 1'b1;
assign o_ddr_str3_data_valid  = 1'b1;
assign o_ddr_str4_data_valid  = 1'b1;


always @(posedge i_user_clk)
begin
   o_user_rd_ack  <= i_user_rd_req;
end

map_reducer #(
    .NUM_MAPPERS(64)
    )
     mr1(
    .i_clk(i_pcie_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_pcie_str1_data), 
    .i_strm_data_valid(i_pcie_str1_data_valid), 
    .o_strm_data_rdy(o_pcie_str1_ack), 
    .o_data_count(o_pcie_str1_data)
    );
	 
map_reducer #(
    .NUM_MAPPERS(64)
    )mr2 (
    .i_clk(i_pcie_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_pcie_str2_data), 
    .i_strm_data_valid(i_pcie_str2_data_valid), 
    .o_strm_data_rdy(o_pcie_str2_ack), 
    .o_data_count(o_pcie_str2_data)
    );
	 
map_reducer #(
    .NUM_MAPPERS(64)
    )mr3 (
    .i_clk(i_pcie_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_pcie_str3_data), 
    .i_strm_data_valid(i_pcie_str3_data_valid), 
    .o_strm_data_rdy(o_pcie_str3_ack), 
    .o_data_count(o_pcie_str3_data)
    );
	 
map_reducer #(
    .NUM_MAPPERS(64)
    )mr4 (
    .i_clk(i_pcie_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_pcie_str4_data), 
    .i_strm_data_valid(i_pcie_str4_data_valid), 
    .o_strm_data_rdy(o_pcie_str4_ack), 
    .o_data_count(o_pcie_str4_data)
    );


map_reducer #(
    .NUM_MAPPERS(64)
    )mr5 (
    .i_clk(i_ddr_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_ddr_str1_data), 
    .i_strm_data_valid(i_ddr_str1_data_valid), 
    .o_strm_data_rdy(o_ddr_str1_ack), 
    .o_data_count(o_ddr_str1_data)
    );
	 
map_reducer #(
    .NUM_MAPPERS(64)
    )mr6 (
    .i_clk(i_ddr_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_ddr_str2_data), 
    .i_strm_data_valid(i_ddr_str2_data_valid), 
    .o_strm_data_rdy(o_ddr_str2_ack), 
    .o_data_count(o_ddr_str2_data)
    );
	 
map_reducer #(
    .NUM_MAPPERS(64)
    )mr7 (
    .i_clk(i_ddr_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_ddr_str3_data), 
    .i_strm_data_valid(i_ddr_str3_data_valid), 
    .o_strm_data_rdy(o_ddr_str3_ack), 
    .o_data_count(o_ddr_str3_data)
    );
	 
map_reducer #(
    .NUM_MAPPERS(64)
    )mr8 (
    .i_clk(i_ddr_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_ddr_str4_data), 
    .i_strm_data_valid(i_ddr_str4_data_valid), 
    .o_strm_data_rdy(o_ddr_str4_ack), 
    .o_data_count(o_ddr_str4_data)
    );

assign o_user_data = o_pcie_str1_data;

endmodule
module user_logic(
    input              i_pcie_clk,
    input              i_ddr_clk,
    input              i_user_clk,
    input              i_rst,

    input    [31:0]    i_user_data,
    input    [19:0]    i_user_addr,
    input              i_user_wr_req,
    output      [31:0] o_user_data,
    output  reg        o_user_rd_ack,
    input              i_user_rd_req, 

    output   [255:0]   o_ddr_wr_data,
    output   [31:0]    o_ddr_wr_data_be_n,
    output             o_ddr_wr_data_valid,
    output   [26:0]    o_ddr_addr,
    output             o_ddr_rd,
    input    [255:0]   i_ddr_rd_data,
    input              i_ddr_rd_data_valid,
    input              i_ddr_wr_ack,
    input              i_ddr_rd_ack,

    input              i_ddr_str1_data_valid,
    output             o_ddr_str1_ack,
    input        [63:0]i_ddr_str1_data,
    output             o_ddr_str1_data_valid,
    input              i_ddr_str1_ack,
    output       [63:0]o_ddr_str1_data,

    input              i_ddr_str2_data_valid,
    output             o_ddr_str2_ack,
    input        [63:0]i_ddr_str2_data,
    output             o_ddr_str2_data_valid,
    input              i_ddr_str2_ack,
    output       [63:0]o_ddr_str2_data,

    input              i_ddr_str3_data_valid,
    output             o_ddr_str3_ack,
    input        [63:0]i_ddr_str3_data,
    output             o_ddr_str3_data_valid,
    input              i_ddr_str3_ack,
    output       [63:0]o_ddr_str3_data,	 

    input              i_ddr_str4_data_valid,
    output             o_ddr_str4_ack,
    input        [63:0]i_ddr_str4_data,
    output             o_ddr_str4_data_valid,
    input              i_ddr_str4_ack,
    output       [63:0]o_ddr_str4_data,

    input              i_pcie_str1_data_valid,
    output             o_pcie_str1_ack,
    input    [63:0]    i_pcie_str1_data,
    output             o_pcie_str1_data_valid,
    input              i_pcie_str1_ack,
    output   [63:0]    o_pcie_str1_data,

    input              i_pcie_str2_data_valid,
    output             o_pcie_str2_ack,
    input    [63:0]    i_pcie_str2_data,
    output             o_pcie_str2_data_valid,
    input              i_pcie_str2_ack,
    output   [63:0]    o_pcie_str2_data,

    input              i_pcie_str3_data_valid,
    output             o_pcie_str3_ack,
    input    [63:0]    i_pcie_str3_data,
    output             o_pcie_str3_data_valid,
    input              i_pcie_str3_ack,
    output   [63:0]    o_pcie_str3_data,

    input              i_pcie_str4_data_valid,
    output             o_pcie_str4_ack,
    input    [63:0]    i_pcie_str4_data,
    output             o_pcie_str4_data_valid,
    input              i_pcie_str4_ack,
    output   [63:0]    o_pcie_str4_data,

    output             o_intr_req,
    input              i_intr_ack
);


assign o_intr_req             = 1'b0;
assign o_pcie_str1_data_valid = 1'b1;
assign o_pcie_str2_data_valid = 1'b1;
assign o_pcie_str3_data_valid = 1'b1;
assign o_pcie_str4_data_valid = 1'b1;
assign o_ddr_str1_data_valid  = 1'b1;
assign o_ddr_str2_data_valid  = 1'b1;
assign o_ddr_str3_data_valid  = 1'b1;
assign o_ddr_str4_data_valid  = 1'b1;


always @(posedge i_user_clk)
begin
   o_user_rd_ack  <= i_user_rd_req;
end

map_reducer #(
    .NUM_MAPPERS(64)
    )
     mr1(
    .i_clk(i_pcie_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_pcie_str1_data), 
    .i_strm_data_valid(i_pcie_str1_data_valid), 
    .o_strm_data_rdy(o_pcie_str1_ack), 
    .o_data_count(o_pcie_str1_data)
    );
	 
map_reducer #(
    .NUM_MAPPERS(64)
    )mr2 (
    .i_clk(i_pcie_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_pcie_str2_data), 
    .i_strm_data_valid(i_pcie_str2_data_valid), 
    .o_strm_data_rdy(o_pcie_str2_ack), 
    .o_data_count(o_pcie_str2_data)
    );
	 
map_reducer #(
    .NUM_MAPPERS(64)
    )mr3 (
    .i_clk(i_pcie_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_pcie_str3_data), 
    .i_strm_data_valid(i_pcie_str3_data_valid), 
    .o_strm_data_rdy(o_pcie_str3_ack), 
    .o_data_count(o_pcie_str3_data)
    );
	 
map_reducer #(
    .NUM_MAPPERS(64)
    )mr4 (
    .i_clk(i_pcie_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_pcie_str4_data), 
    .i_strm_data_valid(i_pcie_str4_data_valid), 
    .o_strm_data_rdy(o_pcie_str4_ack), 
    .o_data_count(o_pcie_str4_data)
    );


map_reducer #(
    .NUM_MAPPERS(64)
    )mr5 (
    .i_clk(i_ddr_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_ddr_str1_data), 
    .i_strm_data_valid(i_ddr_str1_data_valid), 
    .o_strm_data_rdy(o_ddr_str1_ack), 
    .o_data_count(o_ddr_str1_data)
    );
	 
map_reducer #(
    .NUM_MAPPERS(64)
    )mr6 (
    .i_clk(i_ddr_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_ddr_str2_data), 
    .i_strm_data_valid(i_ddr_str2_data_valid), 
    .o_strm_data_rdy(o_ddr_str2_ack), 
    .o_data_count(o_ddr_str2_data)
    );
	 
map_reducer #(
    .NUM_MAPPERS(64)
    )mr7 (
    .i_clk(i_ddr_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_ddr_str3_data), 
    .i_strm_data_valid(i_ddr_str3_data_valid), 
    .o_strm_data_rdy(o_ddr_str3_ack), 
    .o_data_count(o_ddr_str3_data)
    );
	 
map_reducer #(
    .NUM_MAPPERS(64)
    )mr8 (
    .i_clk(i_ddr_clk), 
    .i_rst(i_rst), 
    .i_strm_data(i_ddr_str4_data), 
    .i_strm_data_valid(i_ddr_str4_data_valid), 
    .o_strm_data_rdy(o_ddr_str4_ack), 
    .o_data_count(o_ddr_str4_data)
    );

assign o_user_data = o_pcie_str1_data;

endmodule