data/full_repos/permissive/146618947/pipeline_tarea9/tester.v
 line:29: before: "$"
1: b'%Error: data/full_repos/permissive/146618947/pipeline_tarea9/tester.v:14: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("sum.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/146618947/pipeline_tarea9/tester.v:15: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/146618947/pipeline_tarea9/tester.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #21;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/146618947/pipeline_tarea9/tester.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #41;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/pipeline_tarea9/tester.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #100 $finish;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/146618947/pipeline_tarea9/tester.v:42: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk <= ~clk;\n          ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester (
               input [3:0]      idx_dd_cond,
               input [3:0]      sum30_dd_cond,
               input [3:0]      idx_dd_est,
               input [3:0]      sum30_dd_est,
               output reg       clk,
               output reg       reset_L,
               output reg [3:0] idx,
               output reg [3:0] dataA,
               output reg [3:0] dataB
               );

   initial begin
      $dumpfile("sum.vcd");
      $dumpvars;


      reset_L <= 0;
      idx <= 0;
      dataA <= 0;
      dataB <= 0;

      #21;
      reset_L <= 1;
      #41;
      dataA <= 'b0101;
      dataB <= 'b1010;

      #100 $finish;

   end

   always @ (posedge clk) begin
      if (sum30_dd_est != sum30_dd_cond) begin
         $display("Diferencia en la salida en %t", $realtime);
      end
   end


   initial clk <= 1;

   always #10 clk <= ~clk;

endmodule
module tester (
               input [3:0]      idx_dd_cond,
               input [3:0]      sum30_dd_cond,
               input [3:0]      idx_dd_est,
               input [3:0]      sum30_dd_est,
               output reg       clk,
               output reg       reset_L,
               output reg [3:0] idx,
               output reg [3:0] dataA,
               output reg [3:0] dataB
               );


   initial begin
      $dumpfile("sum.vcd");
      $dumpvars;


      reset_L <= 0;
      idx <= 0;
      dataA <= 0;
      dataB <= 0;

      #21;
      reset_L <= 1;
      #41;
      dataA <= 'b0101;
      dataB <= 'b1010;

      #100 $finish;

   end

   always @ (posedge clk) begin
      if (sum30_dd_est != sum30_dd_cond) begin
         $display("Diferencia en la salida en %t", $realtime);
      end
   end


   initial clk <= 1;

   always #10 clk <= ~clk;

endmodule