data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v
1: b'%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:3: Cannot find include file: cpu.v\n`include "cpu.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/cpu,data/full_repos/permissive/200314387/cpu.v\n             data/full_repos/permissive/200314387/verilog/cpu,data/full_repos/permissive/200314387/cpu.v.v\n             data/full_repos/permissive/200314387/verilog/cpu,data/full_repos/permissive/200314387/cpu.v.sv\n             cpu.v\n             cpu.v.v\n             cpu.v.sv\n             obj_dir/cpu.v\n             obj_dir/cpu.v.v\n             obj_dir/cpu.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:4: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:5: Cannot find include file: psuedo_assembler.sv\n`include "psuedo_assembler.sv" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:17: Cannot find include file: ../lib/display_snippet.sv\n   `include "../lib/display_snippet.sv" \n            ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:15: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n    import alu_ops::*;\n           ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:27: Define or directive not defined: \'`DEFINE_CODE_VARS\'\n    `DEFINE_CODE_VARS(MAX_PC)\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:27: syntax error, unexpected \'(\'\n    `DEFINE_CODE_VARS(MAX_PC)\n                      ^~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:60: Define or directive not defined: \'`INSTRUCTION_N\'\n            `INSTRUCTION_N(pcAddress, pcAddress,  pcAddress, 7-pcAddress, pcAddress,        0,         `SET_FLAGS,  `CM_STD, `DIRECT  ,   pcAddress, pcAddress ); \n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:60: syntax error, unexpected \',\'\n            `INSTRUCTION_N(pcAddress, pcAddress,  pcAddress, 7-pcAddress, pcAddress,        0,         `SET_FLAGS,  `CM_STD, `DIRECT  ,   pcAddress, pcAddress ); \n                                    ^\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:60: Define or directive not defined: \'`SET_FLAGS\'\n            `INSTRUCTION_N(pcAddress, pcAddress,  pcAddress, 7-pcAddress, pcAddress,        0,         `SET_FLAGS,  `CM_STD, `DIRECT  ,   pcAddress, pcAddress ); \n                                                                                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:60: Define or directive not defined: \'`CM_STD\'\n            `INSTRUCTION_N(pcAddress, pcAddress,  pcAddress, 7-pcAddress, pcAddress,        0,         `SET_FLAGS,  `CM_STD, `DIRECT  ,   pcAddress, pcAddress ); \n                                                                                                                    ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:60: Define or directive not defined: \'`DIRECT\'\n            `INSTRUCTION_N(pcAddress, pcAddress,  pcAddress, 7-pcAddress, pcAddress,        0,         `SET_FLAGS,  `CM_STD, `DIRECT  ,   pcAddress, pcAddress ); \n                                                                                                                             ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:80: Define or directive not defined: \'`ROM\'\n            data = `ROM(addr);\n                   ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:81: Unsupported: Ignoring delay on this delayed statement.\n            #1000\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/200314387/verilog/cpu/test_pattern.v:97: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                );\n                ^\n%Error: Exiting due to 14 error(s), 1 warning(s)\n'
module test();

    import alu_ops::*;

   `include "../lib/display_snippet.sv"

    logic clk=0;
    cpu CPU(1'b0, clk);





    localparam MAX_PC=100;
    `DEFINE_CODE_VARS(MAX_PC)







    logic [47:0] data =0;
    int addr;
    string rom1 = "roms/pattern1.rom";
    string rom2 = "roms/pattern2.rom";
    string rom3 = "roms/pattern3.rom";
    string rom4 = "roms/pattern4.rom";
    string rom5 = "roms/pattern5.rom";
    string rom6 = "roms/pattern6.rom";
    int n_file1;
    int n_file2;
    int n_file3;
    int n_file4;
    int n_file5;
    int n_file6;

    integer counter=0;
    integer pcAddress=0;

    initial begin

        pcAddress=0;

        for (pcAddress=0; pcAddress < 256; pcAddress++) begin


            `INSTRUCTION_N(pcAddress, pcAddress,  pcAddress, 7-pcAddress, pcAddress,        0,         `SET_FLAGS,  `CM_STD, `DIRECT  ,   pcAddress, pcAddress ); 

            $display("CODE : %-s" , CODE_NUM[pcAddress]);
        end





        n_file1 = $fopen(rom1, "wb");
        n_file2 = $fopen(rom2, "wb");
        n_file3 = $fopen(rom3, "wb");
        n_file4 = $fopen(rom4, "wb");
        n_file5 = $fopen(rom5, "wb");
        n_file6 = $fopen(rom6, "wb");

        for (addr=0; addr < pcAddress; addr++) begin
            $display("CODE : %-s" , CODE_NUM[addr]);


            data = `ROM(addr);
            #1000

            $fwrite(n_file1, "%c", data[7:0]);
            $fwrite(n_file2, "%c", data[15:8]);
            $fwrite(n_file3, "%c", data[23:16]);
            $fwrite(n_file4, "%c", data[31:24]);
            $fwrite(n_file5, "%c", data[39:32]);
            $fwrite(n_file6, "%c", data[47:40]);

            $display("written %d", addr, " = %8b %8b %8b %8b %8b %8b", 
                data[47:40],
                data[39:32],
                data[31:24],
                data[23:16],
                data[15:8],
                data[7:0],
                );
            end    
        $fclose(n_file1);
        $fclose(n_file2);
        $fclose(n_file3);
        $fclose(n_file4);
        $fclose(n_file5);
        $fclose(n_file6);

        $display("DONE");
        $finish();
    end

endmodule
module test();


    import alu_ops::*;

   `include "../lib/display_snippet.sv"

    logic clk=0;
    cpu CPU(1'b0, clk);





    localparam MAX_PC=100;
    `DEFINE_CODE_VARS(MAX_PC)







    logic [47:0] data =0;
    int addr;
    string rom1 = "roms/pattern1.rom";
    string rom2 = "roms/pattern2.rom";
    string rom3 = "roms/pattern3.rom";
    string rom4 = "roms/pattern4.rom";
    string rom5 = "roms/pattern5.rom";
    string rom6 = "roms/pattern6.rom";
    int n_file1;
    int n_file2;
    int n_file3;
    int n_file4;
    int n_file5;
    int n_file6;

    integer counter=0;
    integer pcAddress=0;

    initial begin

        pcAddress=0;

        for (pcAddress=0; pcAddress < 256; pcAddress++) begin


            `INSTRUCTION_N(pcAddress, pcAddress,  pcAddress, 7-pcAddress, pcAddress,        0,         `SET_FLAGS,  `CM_STD, `DIRECT  ,   pcAddress, pcAddress ); 

            $display("CODE : %-s" , CODE_NUM[pcAddress]);
        end





        n_file1 = $fopen(rom1, "wb");
        n_file2 = $fopen(rom2, "wb");
        n_file3 = $fopen(rom3, "wb");
        n_file4 = $fopen(rom4, "wb");
        n_file5 = $fopen(rom5, "wb");
        n_file6 = $fopen(rom6, "wb");

        for (addr=0; addr < pcAddress; addr++) begin
            $display("CODE : %-s" , CODE_NUM[addr]);


            data = `ROM(addr);
            #1000

            $fwrite(n_file1, "%c", data[7:0]);
            $fwrite(n_file2, "%c", data[15:8]);
            $fwrite(n_file3, "%c", data[23:16]);
            $fwrite(n_file4, "%c", data[31:24]);
            $fwrite(n_file5, "%c", data[39:32]);
            $fwrite(n_file6, "%c", data[47:40]);

            $display("written %d", addr, " = %8b %8b %8b %8b %8b %8b", 
                data[47:40],
                data[39:32],
                data[31:24],
                data[23:16],
                data[15:8],
                data[7:0],
                );
            end    
        $fclose(n_file1);
        $fclose(n_file2);
        $fclose(n_file3);
        $fclose(n_file4);
        $fclose(n_file5);
        $fclose(n_file6);

        $display("DONE");
        $finish();
    end

endmodule