data/full_repos/permissive/119107706/Xilinx Project/SourceCode/Division/abs.v
1: b'%Error: Cannot find file containing module: Project/SourceCode/Division,data/full_repos/permissive/119107706\n        ... Looked in:\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             data/full_repos/permissive/119107706/Xilinx/Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n             Project/SourceCode/Division,data/full_repos/permissive/119107706\n             Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706.v\n             obj_dir/Project/SourceCode/Division,data/full_repos/permissive/119107706.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/119107706/Xilinx\n%Error: Cannot find file containing module: Project/SourceCode/Division/abs.v\n%Error: Exiting due to 3 error(s)\n'
module abs #(parameter WL = 4)
		(
			input signed [WL-1:0] in,
			output reg signed [WL-1:0] out
		);

always @ * begin

		out <= -in;				


end

endmodule
module abs #(parameter WL = 4)
		(
			input signed [WL-1:0] in,
			output reg signed [WL-1:0] out
		);


always @ * begin

		out <= -in;				


end

endmodule