data/full_repos/permissive/143278/ivltests/vhdl_const_record.v
 line:23: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_const_record.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_const_record.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_const_record.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_const_record.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_const_record.v:29: Can\'t find definition of \'sig\' in dotted variable: \'dut.sig\'\n  if(dut.sig !== 8\'h66)\n         ^~~\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_const_record.v:37: Can\'t find definition of \'sig2\' in dotted variable: \'dut.sig2\'\n  if(hex !== 8\'h14 || aval !== 8\'haa || dut.sig2 !== 8\'h00)\n                                            ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_const_record.v:45: Can\'t find definition of \'sig2\' in dotted variable: \'dut.sig2\'\n  if(hex !== 8\'h24 || aval !== 8\'hbb || dut.sig2 !== 8\'h11)\n                                            ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_const_record.v:53: Can\'t find definition of \'sig2\' in dotted variable: \'dut.sig2\'\n  if(hex !== 8\'h34 || aval !== 8\'hcc || dut.sig2 !== 8\'h22)\n                                            ^~~~\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_const_record.v:61: Can\'t find definition of \'sig2\' in dotted variable: \'dut.sig2\'\n  if(hex !== 8\'h56 || aval !== 8\'hdd || dut.sig2 !== 8\'h33)\n                                            ^~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vhdl_const_record_test;
int sel;
logic [7:0] hex;
logic [7:0] aval;
vhdl_const_record dut(sel, hex, aval);

initial begin
  if(dut.sig !== 8'h66)
  begin
    $display("FAILED 1");
    $finish();
  end

  sel = 0;
  #1;
  if(hex !== 8'h14 || aval !== 8'haa || dut.sig2 !== 8'h00)
  begin
    $display("FAILED 2");
    $finish();
  end

  sel = 1;
  #1;
  if(hex !== 8'h24 || aval !== 8'hbb || dut.sig2 !== 8'h11)
  begin
    $display("FAILED 3");
    $finish();
  end

  sel = 2;
  #1;
  if(hex !== 8'h34 || aval !== 8'hcc || dut.sig2 !== 8'h22)
  begin
    $display("FAILED 4");
    $finish();
  end

  sel = 3;
  #1;
  if(hex !== 8'h56 || aval !== 8'hdd || dut.sig2 !== 8'h33)
  begin
    $display("FAILED 5");
    $finish();
  end

  $display("PASSED");
end
endmodule
module vhdl_const_record_test;

int sel;
logic [7:0] hex;
logic [7:0] aval;
vhdl_const_record dut(sel, hex, aval);

initial begin
  if(dut.sig !== 8'h66)
  begin
    $display("FAILED 1");
    $finish();
  end

  sel = 0;
  #1;
  if(hex !== 8'h14 || aval !== 8'haa || dut.sig2 !== 8'h00)
  begin
    $display("FAILED 2");
    $finish();
  end

  sel = 1;
  #1;
  if(hex !== 8'h24 || aval !== 8'hbb || dut.sig2 !== 8'h11)
  begin
    $display("FAILED 3");
    $finish();
  end

  sel = 2;
  #1;
  if(hex !== 8'h34 || aval !== 8'hcc || dut.sig2 !== 8'h22)
  begin
    $display("FAILED 4");
    $finish();
  end

  sel = 3;
  #1;
  if(hex !== 8'h56 || aval !== 8'hdd || dut.sig2 !== 8'h33)
  begin
    $display("FAILED 5");
    $finish();
  end

  $display("PASSED");
end
endmodule