data/full_repos/permissive/20270692/labs/lab11/shift/shift_fifo_tb.v
1: b'%Error: data/full_repos/permissive/20270692/labs/lab11/shift/shift_fifo_tb.v:11: Cannot find include file: shift_fifo.v\n`include "shift_fifo.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20270692/labs/lab11/shift,data/full_repos/permissive/20270692/shift_fifo.v\n             data/full_repos/permissive/20270692/labs/lab11/shift,data/full_repos/permissive/20270692/shift_fifo.v.v\n             data/full_repos/permissive/20270692/labs/lab11/shift,data/full_repos/permissive/20270692/shift_fifo.v.sv\n             shift_fifo.v\n             shift_fifo.v.v\n             shift_fifo.v.sv\n             obj_dir/shift_fifo.v\n             obj_dir/shift_fifo.v.v\n             obj_dir/shift_fifo.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/shift/shift_fifo_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    forever #5 clk=~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/20270692/labs/lab11/shift/shift_fifo_tb.v:36: syntax error, unexpected \'@\'\n      @(posedge clk);  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/shift/shift_fifo_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #5 rst = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/shift/shift_fifo_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #5 rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/shift/shift_fifo_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #5 inputData = 1; writeMode = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/shift/shift_fifo_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #80 readMode = 1; writeMode = 0; inputData = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/20270692/labs/lab11/shift/shift_fifo_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #80 readMode = 0;\n    ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n'
module shift_fifo_tb (
    readMode,
    writeMode,
    inputData
  );

  output readMode, writeMode, inputData;
  reg readMode, writeMode, inputData;

  wire outputData;
  reg clk, rst;

  shift_fifo fifoInstance (readMode, writeMode,
                           inputData, outputData, clk, rst);
  initial
  begin
    clk=0;
    forever #5 clk=~clk;
  end

  initial
  begin
    forever begin
      @(posedge clk);
        $display("time=%04d RW=%b%b IO=%b%b clk=%b", $time,
            readMode, writeMode, inputData, outputData, clk);
    end
  end

  initial
  begin

    readMode = 0;
    writeMode = 0;
    inputData = 0;
    #5 rst = 1;
    #5 rst = 0;
    #5 inputData = 1; writeMode = 1;
    #80 readMode = 1; writeMode = 0; inputData = 0;
    #80 readMode = 0;
    if (1'b1 === outputData) begin
      $display("Pass");
    end else begin
      $display("Fail");
    end
    $finish;
  end

endmodule
module shift_fifo_tb (
    readMode,
    writeMode,
    inputData
  );


  output readMode, writeMode, inputData;
  reg readMode, writeMode, inputData;

  wire outputData;
  reg clk, rst;

  shift_fifo fifoInstance (readMode, writeMode,
                           inputData, outputData, clk, rst);
  initial
  begin
    clk=0;
    forever #5 clk=~clk;
  end

  initial
  begin
    forever begin
      @(posedge clk);
        $display("time=%04d RW=%b%b IO=%b%b clk=%b", $time,
            readMode, writeMode, inputData, outputData, clk);
    end
  end

  initial
  begin

    readMode = 0;
    writeMode = 0;
    inputData = 0;
    #5 rst = 1;
    #5 rst = 0;
    #5 inputData = 1; writeMode = 1;
    #80 readMode = 1; writeMode = 0; inputData = 0;
    #80 readMode = 0;
    if (1'b1 === outputData) begin
      $display("Pass");
    end else begin
      $display("Fail");
    end
    $finish;
  end

endmodule