data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v
 line:70: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:65: Unsupported: Ignoring delay on this delayed statement.\n #21;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:67: Unsupported: Ignoring delay on this delayed statement.\n #17;\n ^\n%Error: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:71: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:81: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:105: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:108: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:114: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:121: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:128: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:136: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:140: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:146: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:152: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:159: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:170: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:174: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:175: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:187: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/175063152/ip/sha_core_512_1.0/src/bench/test_sha256.v:192: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 12 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_sha;

reg clk,rst,cmd_w_i;
reg [31:0] text_i;

reg [2:0] cmd_i;

wire [31:0] text_o;
wire [3:0] cmd_o;

initial
begin


	clk = 1'b0;
	rst = 1'b0;
	cmd_w_i = 1'b0;
	cmd_i = 3'b0;
	
	#21;
	rst = 1'b1;
	#17;
	rst = 1'b0;
	
	test_SHA256;
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	
	$finish;
end


always #5 clk = ~clk;

sha256 sha_core(
	.clk_i(clk),
	.rst_i(rst),
	.text_i(text_i),
	.text_o(text_o),
	.cmd_i(cmd_i),
	.cmd_w_i(cmd_w_i),
	.cmd_o(cmd_o)
	);


task test_SHA256;
integer i;
reg [1023:0] all_message;
reg [511:0] tmp_i;
reg [255:0] tmp_o;
reg [31:0] tmp;
begin
	all_message = {`SHA256_TEST,`SHA256_TEST_PADDING};
	tmp_i = all_message[1023:512];
	tmp_o = `SHA256_TEST_RESULT;
	
	#100;
	
	
	@(posedge clk);
	cmd_i = 3'b010;
	cmd_w_i = 1'b1;
	
	for (i=0;i<16;i=i+1)
	begin
		@(posedge clk);
		cmd_w_i = 1'b0;
		text_i = tmp_i[16*32-1:15*32];
		tmp_i = tmp_i << 32;
	end

	
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);

	while (cmd_o[3])
		@(posedge clk);
	
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	
	#100;
	
	
	tmp_i = all_message[511:0];
	@(posedge clk);
	cmd_i = 3'b110;
	cmd_w_i = 1'b1;
	
	for (i=0;i<16;i=i+1)
	begin
		@(posedge clk);
		cmd_w_i = 1'b0;
		text_i = tmp_i[16*32-1:15*32];
		tmp_i = tmp_i << 32;
	end

	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);

	while (cmd_o[3])
		@(posedge clk);
	
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);

	cmd_i = 3'b001;
	cmd_w_i = 1'b1;
	
	@(posedge clk);
	cmd_w_i = 1'b0;
	for (i=0;i<8;i=i+1)
	begin
		@(posedge clk);
		#1;
		tmp = tmp_o[8*32-1:7*32];
		if (text_o !== tmp | (|text_o)===1'bx)
		begin
			$display("ERROR(SHA-256-%02d) Expected %x, Got %x", i,tmp, text_o);
		end
		else
		begin
			$display("OK(SHA-256-%02d),Expected %x, Got %x", i,tmp, text_o);
		end
		tmp_o = tmp_o << 32;
	end	
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	#100;
end
endtask

endmodule
module test_sha;


reg clk,rst,cmd_w_i;
reg [31:0] text_i;

reg [2:0] cmd_i;

wire [31:0] text_o;
wire [3:0] cmd_o;

initial
begin


	clk = 1'b0;
	rst = 1'b0;
	cmd_w_i = 1'b0;
	cmd_i = 3'b0;
	
	#21;
	rst = 1'b1;
	#17;
	rst = 1'b0;
	
	test_SHA256;
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	
	$finish;
end


always #5 clk = ~clk;

sha256 sha_core(
	.clk_i(clk),
	.rst_i(rst),
	.text_i(text_i),
	.text_o(text_o),
	.cmd_i(cmd_i),
	.cmd_w_i(cmd_w_i),
	.cmd_o(cmd_o)
	);


task test_SHA256;
integer i;
reg [1023:0] all_message;
reg [511:0] tmp_i;
reg [255:0] tmp_o;
reg [31:0] tmp;
begin
	all_message = {`SHA256_TEST,`SHA256_TEST_PADDING};
	tmp_i = all_message[1023:512];
	tmp_o = `SHA256_TEST_RESULT;
	
	#100;
	
	
	@(posedge clk);
	cmd_i = 3'b010;
	cmd_w_i = 1'b1;
	
	for (i=0;i<16;i=i+1)
	begin
		@(posedge clk);
		cmd_w_i = 1'b0;
		text_i = tmp_i[16*32-1:15*32];
		tmp_i = tmp_i << 32;
	end

	
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);

	while (cmd_o[3])
		@(posedge clk);
	
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	
	#100;
	
	
	tmp_i = all_message[511:0];
	@(posedge clk);
	cmd_i = 3'b110;
	cmd_w_i = 1'b1;
	
	for (i=0;i<16;i=i+1)
	begin
		@(posedge clk);
		cmd_w_i = 1'b0;
		text_i = tmp_i[16*32-1:15*32];
		tmp_i = tmp_i << 32;
	end

	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);

	while (cmd_o[3])
		@(posedge clk);
	
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);

	cmd_i = 3'b001;
	cmd_w_i = 1'b1;
	
	@(posedge clk);
	cmd_w_i = 1'b0;
	for (i=0;i<8;i=i+1)
	begin
		@(posedge clk);
		#1;
		tmp = tmp_o[8*32-1:7*32];
		if (text_o !== tmp | (|text_o)===1'bx)
		begin
			$display("ERROR(SHA-256-%02d) Expected %x, Got %x", i,tmp, text_o);
		end
		else
		begin
			$display("OK(SHA-256-%02d),Expected %x, Got %x", i,tmp, text_o);
		end
		tmp_o = tmp_o << 32;
	end	
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	#100;
end
endtask

endmodule