data/full_repos/permissive/136510272/projects/atmega/core.v
 line:41: before: "]"
1: b'%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:30: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance core\nassign DAT_O = 1\'b0;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:32: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                              : ... In instance core\nwire [15:0] test_reg = {r[27], r[26], r[17], r[16]};\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:91: Operator SUB expects 9 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                              : ... In instance core\nwire [8:0] c_sbc  = c_sub - f[0];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:92: Operator ADD expects 9 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                              : ... In instance core\nwire [8:0] c_adc  = c_add + f[0];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:94: Operator SUB expects 9 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                              : ... In instance core\nwire [8:0] c_sbci = Rd - K - f[0];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:121: Operator ASSIGN expects 22 bits on the Assign RHS, but Assign RHS\'s CONST \'14\'h0\' generates 14 bits.\n                                                                               : ... In instance core\n    ADR_O  = 14\'h0000;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:125: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n    cs     = 1\'b0;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:157: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd  = 1\'b0;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:170: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:183: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:196: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:209: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:222: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:235: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:245: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'c_and\' generates 8 bits.\n                                                                               : ... In instance core\n            R = c_and;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:248: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:258: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'c_eor\' generates 8 bits.\n                                                                               : ... In instance core\n            R = c_eor;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:261: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:271: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'c_or\' generates 8 bits.\n                                                                               : ... In instance core\n            R = c_or;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:274: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:284: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'Rr\' generates 8 bits.\n                                                                               : ... In instance core\n            R = Rr;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:287: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:300: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:313: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:326: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:336: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'c_ori\' generates 8 bits.\n                                                                               : ... In instance core\n            R = c_ori;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:339: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:349: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'c_andi\' generates 8 bits.\n                                                                               : ... In instance core\n            R = c_andi;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:352: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:362: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'K\' generates 8 bits.\n                                                                               : ... In instance core\n            R = K;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:365: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:373: Operator ASSIGN expects 22 bits on the Assign RHS, but Assign RHS\'s VARREF \'Xr\' generates 16 bits.\n                                                                               : ... In instance core\n        16\'b1001_000x_xxxx_1101: begin i_cmd = 3\'h1; i_alu = 1\'b0; ADR_O = Xr; end\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:374: Operator ASSIGN expects 22 bits on the Assign RHS, but Assign RHS\'s VARREF \'Yr\' generates 16 bits.\n                                                                               : ... In instance core\n        16\'b1001_000x_xxxx_1001: begin i_cmd = 3\'h2; i_alu = 1\'b0; ADR_O = Yr; end\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:375: Operator ASSIGN expects 22 bits on the Assign RHS, but Assign RHS\'s VARREF \'Zr\' generates 16 bits.\n                                                                               : ... In instance core\n        16\'b1001_000x_xxxx_0001: begin i_cmd = 3\'h3; i_alu = 1\'b0; ADR_O = Zr; end\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:376: Operator ASSIGN expects 22 bits on the Assign RHS, but Assign RHS\'s VARREF \'Xr\' generates 16 bits.\n                                                                               : ... In instance core\n        16\'b1001_000x_xxxx_1100: begin i_cmd = 3\'h4;       i_alu = 1\'b0; ADR_O = Xr; end\n                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:377: Operator ADD expects 22 bits on the LHS, but LHS\'s VARREF \'Yr\' generates 16 bits.\n                                                                               : ... In instance core\n        16\'b10x0_xx0x_xxxx_1xxx: begin i_cmd = 3\'h5;       i_alu = 1\'b0; ADR_O = Yr + {o[13],o[11:10],o[2:0]}; end\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:377: Operator ADD expects 22 bits on the RHS, but RHS\'s REPLICATE generates 6 bits.\n                                                                               : ... In instance core\n        16\'b10x0_xx0x_xxxx_1xxx: begin i_cmd = 3\'h5;       i_alu = 1\'b0; ADR_O = Yr + {o[13],o[11:10],o[2:0]}; end\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:378: Operator ADD expects 22 bits on the LHS, but LHS\'s VARREF \'Zr\' generates 16 bits.\n                                                                               : ... In instance core\n        16\'b10x0_xx0x_xxxx_0xxx: begin i_cmd = 3\'h6;       i_alu = 1\'b0; ADR_O = Zr + {o[13],o[11:10],o[2:0]}; end\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:378: Operator ADD expects 22 bits on the RHS, but RHS\'s REPLICATE generates 6 bits.\n                                                                               : ... In instance core\n        16\'b10x0_xx0x_xxxx_0xxx: begin i_cmd = 3\'h6;       i_alu = 1\'b0; ADR_O = Zr + {o[13],o[11:10],o[2:0]}; end\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:385: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            i_cmd = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:409: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'PC\' generates 14 bits.\n                                                                               : ... In instance core\n            begin PC <= PC + 1\'b1 + {{4{o[11]}}, o[11:0]}; end\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:409: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                               : ... In instance core\n            begin PC <= PC + 1\'b1 + {{4{o[11]}}, o[11:0]}; end\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:420: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                               : ... In instance core\n            begin PC <= PC + 1\'b1; cs <= 1\'b1; end\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:433: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n                cs <= 1\'b0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:435: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                               : ... In instance core\n                cs <= 2\'h2;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:449: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n            cs <= 1\'b0;  \n               ^~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:400: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance core\n    case (cs)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:400: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'1\'h1\' generates 1 bits.\n                                                                               : ... In instance core\n    case (cs)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/136510272/projects/atmega/core.v:400: Operator CASE expects 3 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n                                                                               : ... In instance core\n    case (cs)\n    ^~~~\n%Error: Exiting due to 49 warning(s)\n'
module core(

    input  wire        CLK_I,
    input  wire        RST_I,
    output wire [13:0] ROM_A,
    input  wire [15:0] ROM_I, 
    output reg  [21:0] ADR_O,
    input  wire [15:0] DAT_I, 
    output wire [15:0] DAT_O, 
    output reg         WE_O    
);


`define MAIN_LOOP   1'b0
`define STORE_LDREG 1'b1
`define INCR_INDEX  2'h2


`define CMD_NONE    3'h0
`define INC_POST_X  3'h1
`define INC_POST_Y  3'h2
`define INC_POST_Z  3'h3
`define LD_X        3'h4
`define LD_Y        3'h5
`define LD_Z        3'h6

assign ROM_A = PC;
assign DAT_O = 1'b0;

wire [15:0] test_reg = {r[27], r[26], r[17], r[16]};



reg [13:0] PC;
reg [13:0] SP;
reg  [8:0] R;
reg  [7:0] F;

reg  [7:0] r[32];
reg  [7:0] f;






reg [2:0]  cs;
reg [15:0] opcode;

reg        i_rjmp;     
reg [15:0] r_jmp;

reg       i_alu;
reg       i_save;
reg [2:0] i_cmd;


wire a_zero = (R[7:0] == 8'h00);
wire a_neg  =  R[7];


wire [15:0] o = cs > 0 ? opcode : ROM_I;


wire i_imm = (o[15:12] == 4'b0011 |
              o[15:12] == 4'b0100 |
              o[15:12] == 4'b0101 |
              o[15:12] == 4'b0110 |
              o[15:12] == 4'b1110 |
              o[15:12] == 4'b0111
             );


wire [4:0] Rn = { i_imm | o[9], o[3:0]};
wire [4:0] Dn = { i_imm | o[8], o[7:4]} ;


wire [7:0] Rr = r[ Rn ];
wire [7:0] Rd = r[ Dn ];





wire [7:0] K = {o[11:8], o[3:0]};

wire [8:0] c_add  = Rd + Rr;
wire [8:0] c_sub  = Rd - Rr;
wire [8:0] c_sbc  = c_sub - f[0];
wire [8:0] c_adc  = c_add + f[0];
wire [8:0] c_subi = Rd - K;
wire [8:0] c_sbci = Rd - K - f[0];

wire [7:0] c_and  = Rd & Rr;
wire [7:0] c_or   = Rd | Rr;
wire [7:0] c_eor  = Rd ^ Rr;
wire [7:0] c_andi = Rd & K;
wire [7:0] c_ori  = Rd | K;


wire [15:0] Xr = {r[27], r[26]};
wire [15:0] Xr_inc = Xr + 1'b1;

wire [15:0] Yr = {r[29], r[28]};
wire [15:0] Yr_inc = Yr + 1'b1;

wire [15:0] Zr = {r[31], r[30]};
wire [15:0] Zr_inc = Zr + 1'b1;


wire H_subi = (!Rd[3] & K[3]) | (K[3] & R[3]) | (R[3] & !Rd[3]);
wire V_subi = (Rd[7] & !K[7] & !R[7]) | (!Rd[7] & K[7] & R[7]);



initial begin

    PC     = 14'h0000;
    ADR_O  = 14'h0000;
    WE_O   = 1'b0;
    f      = 8'h00;
    F      = 8'h00;
    cs     = 1'b0;
        

    r[0]  = 8'h00; r[1]  = 8'h00; r[2]  = 8'h00;  r[3]  = 8'h00;
    r[4]  = 8'h00; r[5]  = 8'h00; r[6]  = 8'h00;  r[7]  = 8'h00;
    r[8]  = 8'h00; r[9]  = 8'h00; r[10] = 8'h00;  r[11] = 8'h00;
    r[12] = 8'h00; r[13] = 8'h00; r[14] = 8'h00;  r[15] = 8'h00;

    r[16] = 8'h00; r[17] = 8'h00; r[18] = 8'h00;  r[19] = 8'h00;
    r[20] = 8'h00; r[21] = 8'h00; r[22] = 8'h00;  r[23] = 8'h00;
    r[24] = 8'h00; r[25] = 8'h00; 
    

    r[26] = 8'h00; r[27] = 8'h00;
    r[28] = 8'h00; r[29] = 8'h00;
    r[30] = 8'h00; r[31] = 8'h00;

end



always @* begin

    casex (o)



        16'b000001_xx_xxxx_xxxx: begin
        
            R = c_sbc;
            F = f;
            
            i_cmd  = 1'b0;
            i_alu  = 1'b1;
            i_save = 1'b0;

        end



        16'b000010_xx_xxxx_xxxx: begin
        
            R = c_sbc;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end



        16'b000011_xx_xxxx_xxxx: begin
        
            R = c_add;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end



        16'b000100_xx_xxxx_xxxx: begin
        
            R = c_sub;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b0;
            i_save = 1'b0;
        
        end
    


        16'b000101_xx_xxxx_xxxx: begin
        
            R = c_sub;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b000110_xx_xxxx_xxxx: begin
        
            R = c_sub;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b000111_xx_xxxx_xxxx: begin
        
            R = c_adc;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end                       
        


        16'b001000_xx_xxxx_xxxx: begin
        
            R = c_and;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b001001_xx_xxxx_xxxx: begin
        
            R = c_eor;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b001010_xx_xxxx_xxxx: begin
        
            R = c_or;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b001011_xx_xxxx_xxxx: begin
        
            R = Rr;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b0011_xxxx_xxxx_xxxx: begin
        
            R = c_subi;
            F = {f[7:6], H_subi, H_subi ^ V_subi, V_subi, a_neg, a_zero, R[8]};
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b0;
        
        end
        


        16'b0100_xxxx_xxxx_xxxx: begin
        
            R = c_sbci;
            F = {f[7:6], H_subi, H_subi ^ V_subi, V_subi, a_neg, a_zero, R[8]};
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b0101_xxxx_xxxx_xxxx: begin
        
            R = c_subi;
            F = {f[7:6], H_subi, H_subi ^ V_subi, V_subi, a_neg, a_zero, R[8]};
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b0110_xxxx_xxxx_xxxx: begin
        
            R = c_ori;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;

        end
        


        16'b0111_xxxx_xxxx_xxxx: begin
        
            R = c_andi;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b1110_xxxx_xxxx_xxxx: begin
        
            R = K;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b1001_000x_xxxx_1101: begin i_cmd = `INC_POST_X; i_alu = 1'b0; ADR_O = Xr; end
        16'b1001_000x_xxxx_1001: begin i_cmd = `INC_POST_Y; i_alu = 1'b0; ADR_O = Yr; end
        16'b1001_000x_xxxx_0001: begin i_cmd = `INC_POST_Z; i_alu = 1'b0; ADR_O = Zr; end
        16'b1001_000x_xxxx_1100: begin i_cmd = `LD_X;       i_alu = 1'b0; ADR_O = Xr; end
        16'b10x0_xx0x_xxxx_1xxx: begin i_cmd = `LD_Y;       i_alu = 1'b0; ADR_O = Yr + {o[13],o[11:10],o[2:0]}; end
        16'b10x0_xx0x_xxxx_0xxx: begin i_cmd = `LD_Z;       i_alu = 1'b0; ADR_O = Zr + {o[13],o[11:10],o[2:0]}; end



        default: begin
        
            F = f; 
            i_cmd = 1'b0;
            i_alu = 1'b0;
            i_save = 1'b0;
            
        end

    endcase

end




always @(posedge CLK_I) begin

    case (cs)
    
        `MAIN_LOOP: begin     
        
            opcode <= ROM_I;
            


            if (o[15:12] == 4'b1100) 
            begin PC <= PC + 1'b1 + {{4{o[11]}}, o[11:0]}; end
            


            else if (i_alu) 
            begin PC <= PC + 1'b1; f <= F; if (i_save) r[ Dn ] <= R[7:0]; end



            else if (i_cmd == `INC_POST_X || i_cmd == `INC_POST_Y || i_cmd == `INC_POST_Z || 
                     i_cmd == `LD_X       || i_cmd == `LD_Y       || i_cmd == `LD_Z) 
            begin PC <= PC + 1'b1; cs <= `STORE_LDREG; end

        end
        



        `STORE_LDREG: begin

            r[ Dn ] <= ADR_O[0] ? DAT_I[15:8] : DAT_I[7:0];
            

            if (i_cmd == `LD_X || i_cmd == `LD_Y || i_cmd == `LD_Z)
                cs <= `MAIN_LOOP;
            else 
                cs <= `INCR_INDEX;
        
        end
        

        `INCR_INDEX: begin
        

                 if (i_cmd == `INC_POST_X) begin r[26] <= Xr_inc[7:0]; r[27] <= Xr_inc[15:8]; end

            else if (i_cmd == `INC_POST_Y) begin r[28] <= Yr_inc[7:0]; r[29] <= Yr_inc[15:8]; end

            else if (i_cmd == `INC_POST_Z) begin r[30] <= Zr_inc[7:0]; r[31] <= Zr_inc[15:8]; end

            cs <= `MAIN_LOOP;  

        end
    
    endcase

end

endmodule
module core(

    input  wire        CLK_I,
    input  wire        RST_I,
    output wire [13:0] ROM_A,
    input  wire [15:0] ROM_I, 
    output reg  [21:0] ADR_O,
    input  wire [15:0] DAT_I, 
    output wire [15:0] DAT_O, 
    output reg         WE_O    
);



`define MAIN_LOOP   1'b0
`define STORE_LDREG 1'b1
`define INCR_INDEX  2'h2


`define CMD_NONE    3'h0
`define INC_POST_X  3'h1
`define INC_POST_Y  3'h2
`define INC_POST_Z  3'h3
`define LD_X        3'h4
`define LD_Y        3'h5
`define LD_Z        3'h6

assign ROM_A = PC;
assign DAT_O = 1'b0;

wire [15:0] test_reg = {r[27], r[26], r[17], r[16]};



reg [13:0] PC;
reg [13:0] SP;
reg  [8:0] R;
reg  [7:0] F;

reg  [7:0] r[32];
reg  [7:0] f;






reg [2:0]  cs;
reg [15:0] opcode;

reg        i_rjmp;     
reg [15:0] r_jmp;

reg       i_alu;
reg       i_save;
reg [2:0] i_cmd;


wire a_zero = (R[7:0] == 8'h00);
wire a_neg  =  R[7];


wire [15:0] o = cs > 0 ? opcode : ROM_I;


wire i_imm = (o[15:12] == 4'b0011 |
              o[15:12] == 4'b0100 |
              o[15:12] == 4'b0101 |
              o[15:12] == 4'b0110 |
              o[15:12] == 4'b1110 |
              o[15:12] == 4'b0111
             );


wire [4:0] Rn = { i_imm | o[9], o[3:0]};
wire [4:0] Dn = { i_imm | o[8], o[7:4]} ;


wire [7:0] Rr = r[ Rn ];
wire [7:0] Rd = r[ Dn ];





wire [7:0] K = {o[11:8], o[3:0]};

wire [8:0] c_add  = Rd + Rr;
wire [8:0] c_sub  = Rd - Rr;
wire [8:0] c_sbc  = c_sub - f[0];
wire [8:0] c_adc  = c_add + f[0];
wire [8:0] c_subi = Rd - K;
wire [8:0] c_sbci = Rd - K - f[0];

wire [7:0] c_and  = Rd & Rr;
wire [7:0] c_or   = Rd | Rr;
wire [7:0] c_eor  = Rd ^ Rr;
wire [7:0] c_andi = Rd & K;
wire [7:0] c_ori  = Rd | K;


wire [15:0] Xr = {r[27], r[26]};
wire [15:0] Xr_inc = Xr + 1'b1;

wire [15:0] Yr = {r[29], r[28]};
wire [15:0] Yr_inc = Yr + 1'b1;

wire [15:0] Zr = {r[31], r[30]};
wire [15:0] Zr_inc = Zr + 1'b1;


wire H_subi = (!Rd[3] & K[3]) | (K[3] & R[3]) | (R[3] & !Rd[3]);
wire V_subi = (Rd[7] & !K[7] & !R[7]) | (!Rd[7] & K[7] & R[7]);



initial begin

    PC     = 14'h0000;
    ADR_O  = 14'h0000;
    WE_O   = 1'b0;
    f      = 8'h00;
    F      = 8'h00;
    cs     = 1'b0;
        

    r[0]  = 8'h00; r[1]  = 8'h00; r[2]  = 8'h00;  r[3]  = 8'h00;
    r[4]  = 8'h00; r[5]  = 8'h00; r[6]  = 8'h00;  r[7]  = 8'h00;
    r[8]  = 8'h00; r[9]  = 8'h00; r[10] = 8'h00;  r[11] = 8'h00;
    r[12] = 8'h00; r[13] = 8'h00; r[14] = 8'h00;  r[15] = 8'h00;

    r[16] = 8'h00; r[17] = 8'h00; r[18] = 8'h00;  r[19] = 8'h00;
    r[20] = 8'h00; r[21] = 8'h00; r[22] = 8'h00;  r[23] = 8'h00;
    r[24] = 8'h00; r[25] = 8'h00; 
    

    r[26] = 8'h00; r[27] = 8'h00;
    r[28] = 8'h00; r[29] = 8'h00;
    r[30] = 8'h00; r[31] = 8'h00;

end



always @* begin

    casex (o)



        16'b000001_xx_xxxx_xxxx: begin
        
            R = c_sbc;
            F = f;
            
            i_cmd  = 1'b0;
            i_alu  = 1'b1;
            i_save = 1'b0;

        end



        16'b000010_xx_xxxx_xxxx: begin
        
            R = c_sbc;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end



        16'b000011_xx_xxxx_xxxx: begin
        
            R = c_add;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end



        16'b000100_xx_xxxx_xxxx: begin
        
            R = c_sub;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b0;
            i_save = 1'b0;
        
        end
    


        16'b000101_xx_xxxx_xxxx: begin
        
            R = c_sub;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b000110_xx_xxxx_xxxx: begin
        
            R = c_sub;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b000111_xx_xxxx_xxxx: begin
        
            R = c_adc;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end                       
        


        16'b001000_xx_xxxx_xxxx: begin
        
            R = c_and;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b001001_xx_xxxx_xxxx: begin
        
            R = c_eor;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b001010_xx_xxxx_xxxx: begin
        
            R = c_or;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b001011_xx_xxxx_xxxx: begin
        
            R = Rr;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b0011_xxxx_xxxx_xxxx: begin
        
            R = c_subi;
            F = {f[7:6], H_subi, H_subi ^ V_subi, V_subi, a_neg, a_zero, R[8]};
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b0;
        
        end
        


        16'b0100_xxxx_xxxx_xxxx: begin
        
            R = c_sbci;
            F = {f[7:6], H_subi, H_subi ^ V_subi, V_subi, a_neg, a_zero, R[8]};
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b0101_xxxx_xxxx_xxxx: begin
        
            R = c_subi;
            F = {f[7:6], H_subi, H_subi ^ V_subi, V_subi, a_neg, a_zero, R[8]};
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b0110_xxxx_xxxx_xxxx: begin
        
            R = c_ori;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;

        end
        


        16'b0111_xxxx_xxxx_xxxx: begin
        
            R = c_andi;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b1110_xxxx_xxxx_xxxx: begin
        
            R = K;
            F = f;
            
            i_cmd = 1'b0;
            i_alu = 1'b1;
            i_save = 1'b1;
        
        end
        


        16'b1001_000x_xxxx_1101: begin i_cmd = `INC_POST_X; i_alu = 1'b0; ADR_O = Xr; end
        16'b1001_000x_xxxx_1001: begin i_cmd = `INC_POST_Y; i_alu = 1'b0; ADR_O = Yr; end
        16'b1001_000x_xxxx_0001: begin i_cmd = `INC_POST_Z; i_alu = 1'b0; ADR_O = Zr; end
        16'b1001_000x_xxxx_1100: begin i_cmd = `LD_X;       i_alu = 1'b0; ADR_O = Xr; end
        16'b10x0_xx0x_xxxx_1xxx: begin i_cmd = `LD_Y;       i_alu = 1'b0; ADR_O = Yr + {o[13],o[11:10],o[2:0]}; end
        16'b10x0_xx0x_xxxx_0xxx: begin i_cmd = `LD_Z;       i_alu = 1'b0; ADR_O = Zr + {o[13],o[11:10],o[2:0]}; end



        default: begin
        
            F = f; 
            i_cmd = 1'b0;
            i_alu = 1'b0;
            i_save = 1'b0;
            
        end

    endcase

end




always @(posedge CLK_I) begin

    case (cs)
    
        `MAIN_LOOP: begin     
        
            opcode <= ROM_I;
            


            if (o[15:12] == 4'b1100) 
            begin PC <= PC + 1'b1 + {{4{o[11]}}, o[11:0]}; end
            


            else if (i_alu) 
            begin PC <= PC + 1'b1; f <= F; if (i_save) r[ Dn ] <= R[7:0]; end



            else if (i_cmd == `INC_POST_X || i_cmd == `INC_POST_Y || i_cmd == `INC_POST_Z || 
                     i_cmd == `LD_X       || i_cmd == `LD_Y       || i_cmd == `LD_Z) 
            begin PC <= PC + 1'b1; cs <= `STORE_LDREG; end

        end
        



        `STORE_LDREG: begin

            r[ Dn ] <= ADR_O[0] ? DAT_I[15:8] : DAT_I[7:0];
            

            if (i_cmd == `LD_X || i_cmd == `LD_Y || i_cmd == `LD_Z)
                cs <= `MAIN_LOOP;
            else 
                cs <= `INCR_INDEX;
        
        end
        

        `INCR_INDEX: begin
        

                 if (i_cmd == `INC_POST_X) begin r[26] <= Xr_inc[7:0]; r[27] <= Xr_inc[15:8]; end

            else if (i_cmd == `INC_POST_Y) begin r[28] <= Yr_inc[7:0]; r[29] <= Yr_inc[15:8]; end

            else if (i_cmd == `INC_POST_Z) begin r[30] <= Zr_inc[7:0]; r[31] <= Zr_inc[15:8]; end

            cs <= `MAIN_LOOP;  

        end
    
    endcase

end

endmodule