data/full_repos/permissive/181415525/heart_beat.v
data/verilator_xmls/e7b21305-1f6b-4806-b0f3-f0928f65c6a9.xml
module heart_beat(
	clk,
	led
);

parameter DUR_BITS = 26;

input  clk;
output led;





reg [(DUR_BITS-1):0] cnt;
always @ (posedge clk)
begin
	cnt <= cnt + 1;
end

assign led = cnt[DUR_BITS-1];



endmodule
module heart_beat(
	clk,
	led
);


parameter DUR_BITS = 26;

input  clk;
output led;





reg [(DUR_BITS-1):0] cnt;
always @ (posedge clk)
begin
	cnt <= cnt + 1;
end

assign led = cnt[DUR_BITS-1];



endmodule