data/full_repos/permissive/160156794/counter.v
1: b"%Error: data/full_repos/permissive/160156794/counter.v:8: Duplicate declaration of signal: 'digit'\n                                                        : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  reg [BITS-1:0] digit = 0;\n                 ^~~~~\n        data/full_repos/permissive/160156794/counter.v:4: ... Location of original declaration\n  output [BITS-1:0] digit);\n                    ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module counter(
  input clk,
  input rst,
  output [BITS-1:0] digit);

  parameter BITS = 4;

  reg [BITS-1:0] digit = 0;

  always @ (posedge clk or posedge rst) begin
    if (rst)
      digit <= 0;
    else
      digit <= digit + 1;
  end

endmodule
module counter(
  input clk,
  input rst,
  output [BITS-1:0] digit);


  parameter BITS = 4;

  reg [BITS-1:0] digit = 0;

  always @ (posedge clk or posedge rst) begin
    if (rst)
      digit <= 0;
    else
      digit <= digit + 1;
  end

endmodule