data/full_repos/permissive/136684942/src/ALU.v
1: b'%Error: data/full_repos/permissive/136684942/src/ALU.v:69: Cannot find file containing module: \'adder_32bits\'\n adder_32bits adder_32bits_inst(.a(A),.b(B32),\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136684942/src,data/full_repos/permissive/136684942/adder_32bits\n             data/full_repos/permissive/136684942/src,data/full_repos/permissive/136684942/adder_32bits.v\n             data/full_repos/permissive/136684942/src,data/full_repos/permissive/136684942/adder_32bits.sv\n             adder_32bits\n             adder_32bits.v\n             adder_32bits.sv\n             obj_dir/adder_32bits\n             obj_dir/adder_32bits.v\n             obj_dir/adder_32bits.sv\n%Warning-WIDTH: data/full_repos/permissive/136684942/src/ALU.v:86: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s LOGOR generates 1 bits.\n                                                                 : ... In instance ALU\nalu_slt :Result<=(A[31]&&(~B[31]))||((A[31]^~B[31])&&sum[31]);\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/136684942/src/ALU.v:87: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s LOGOR generates 1 bits.\n                                                                 : ... In instance ALU\nalu_sltu :Result<=((~A[31])&&B[31])||((A[31]~^B[31])&&sum[31]);\n                ^~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module ALU (

	Result,overflow,

	ALUCode, A, B
);
	input [4:0]  ALUCode;
	input [31:0]  A, B;
	output [31:0] Result;
	output overflow;




	reg signed [31:0] B_reg;
	always @(B) begin
	B_reg = B;
	end

	parameter alu_add= 5'b00000;
	parameter alu_and= 5'b00001;
	parameter alu_xor= 5'b00010;
	parameter alu_or = 5'b00011;
	parameter alu_nor= 5'b00100;
	parameter alu_sub= 5'b00101;
	parameter alu_andi= 5'b00110;
	parameter alu_xori= 5'b00111;
	parameter alu_ori = 5'b01000;
	parameter alu_jr = 5'b01001;
	parameter alu_beq= 5'b01010;
	parameter alu_bne= 5'b01011;
	parameter alu_bgez= 5'b01100;
	parameter alu_bgtz= 5'b01101;
	parameter alu_blez= 5'b01110;
	parameter alu_bltz= 5'b01111;
	parameter alu_sll= 5'b10000;
	parameter alu_srl= 5'b10001;
	parameter alu_sra= 5'b10010; 
	parameter alu_slt= 5'b10011;
	parameter alu_sltu= 5'b10100;



	reg[31:0] Result;
	wire[31:0] sum,B32;
	wire Binvert;
	assign Binvert=~(ALUCode==alu_add);
	assign B32=B^{32{Binvert}};
	adder_32bits adder_32bits_inst(.a(A),.b(B32),
				.ci(Binvert),.s(sum),.co());
always@(*)
begin
case(ALUCode)
alu_add :Result<=sum;
alu_and :Result<=A&B;
alu_xor :Result<=A^B;
alu_or :Result<=A|B;
alu_nor :Result<=~(A|B);
alu_sub :Result<=sum;
alu_andi :Result<=A&{16'd0,B[15:0]};
alu_xori :Result<=A^{16'd0,B[15:0]};
alu_ori :Result<=A|{16'd0,B[15:0]};
alu_sll :Result<=B<<A;
alu_srl :Result<=B>>A;
alu_sra :Result<=B_reg>>>A;
alu_slt :Result<=(A[31]&&(~B[31]))||((A[31]^~B[31])&&sum[31]);
alu_sltu :Result<=((~A[31])&&B[31])||((A[31]~^B[31])&&sum[31]);
default :Result<=32'b0;
endcase
end
endmodule
module ALU (

	Result,overflow,

	ALUCode, A, B
);

	input [4:0]  ALUCode;
	input [31:0]  A, B;
	output [31:0] Result;
	output overflow;




	reg signed [31:0] B_reg;
	always @(B) begin
	B_reg = B;
	end

	parameter alu_add= 5'b00000;
	parameter alu_and= 5'b00001;
	parameter alu_xor= 5'b00010;
	parameter alu_or = 5'b00011;
	parameter alu_nor= 5'b00100;
	parameter alu_sub= 5'b00101;
	parameter alu_andi= 5'b00110;
	parameter alu_xori= 5'b00111;
	parameter alu_ori = 5'b01000;
	parameter alu_jr = 5'b01001;
	parameter alu_beq= 5'b01010;
	parameter alu_bne= 5'b01011;
	parameter alu_bgez= 5'b01100;
	parameter alu_bgtz= 5'b01101;
	parameter alu_blez= 5'b01110;
	parameter alu_bltz= 5'b01111;
	parameter alu_sll= 5'b10000;
	parameter alu_srl= 5'b10001;
	parameter alu_sra= 5'b10010; 
	parameter alu_slt= 5'b10011;
	parameter alu_sltu= 5'b10100;



	reg[31:0] Result;
	wire[31:0] sum,B32;
	wire Binvert;
	assign Binvert=~(ALUCode==alu_add);
	assign B32=B^{32{Binvert}};
	adder_32bits adder_32bits_inst(.a(A),.b(B32),
				.ci(Binvert),.s(sum),.co());
always@(*)
begin
case(ALUCode)
alu_add :Result<=sum;
alu_and :Result<=A&B;
alu_xor :Result<=A^B;
alu_or :Result<=A|B;
alu_nor :Result<=~(A|B);
alu_sub :Result<=sum;
alu_andi :Result<=A&{16'd0,B[15:0]};
alu_xori :Result<=A^{16'd0,B[15:0]};
alu_ori :Result<=A|{16'd0,B[15:0]};
alu_sll :Result<=B<<A;
alu_srl :Result<=B>>A;
alu_sra :Result<=B_reg>>>A;
alu_slt :Result<=(A[31]&&(~B[31]))||((A[31]^~B[31])&&sum[31]);
alu_sltu :Result<=((~A[31])&&B[31])||((A[31]~^B[31])&&sum[31]);
default :Result<=32'b0;
endcase
end
endmodule