data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16.v
 line:43: before: "="
1: b'%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16.v:97: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'rd_en_i\' generates 1 bits.\n                                                                                         : ... In instance afifo16\nassign #2 next_rd_ptr = !rempty_o ? bin_rd_ptr + rd_en_i : bin_rd_ptr;\n                                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16.v:115: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'wr_en_i\' generates 1 bits.\n                                                                                          : ... In instance afifo16\nassign #2 next_wr_ptr = !wfull_o ? bin_wr_ptr + wr_en_i : bin_wr_ptr;\n                                              ^\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16.v:207: Cannot find file containing module: \'bin2gray\'\nbin2gray B2G0 (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo/async,data/full_repos/permissive/20430511/bin2gray\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo/async,data/full_repos/permissive/20430511/bin2gray.v\n             data/full_repos/permissive/20430511/hardware/FPGA/fifo/async,data/full_repos/permissive/20430511/bin2gray.sv\n             bin2gray\n             bin2gray.v\n             bin2gray.sv\n             obj_dir/bin2gray\n             obj_dir/bin2gray.v\n             obj_dir/bin2gray.sv\n%Error: data/full_repos/permissive/20430511/hardware/FPGA/fifo/async/afifo16.v:214: Cannot find file containing module: \'bin2gray\'\nbin2gray B2G1 (\n^~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module afifo16 #(
	parameter	WIDTH	= 32,
	parameter	ADDRESS	= 4,
	parameter	MSB	= WIDTH - 1,
	parameter	ASB	= ADDRESS - 1
) (
	input		reset_ni,
	
	input		rd_clk_i,
	input		rd_en_i,
	output	[MSB:0]	rd_data_o,

	
	input		wr_clk_i,
	input		wr_en_i,
	input	[MSB:0]	wr_data_i,
	
	output	reg	rempty_o	= 1,
	output	reg	wfull_o		= 0,
	output	reg	rhalfish_o	= 0,
	output	reg	whalfish_o	= 0
);


reg	[ASB:0]	bin_rd_ptr	= 0;
reg	[ASB:0]	bin_wr_ptr	= 0;

wire	[ASB:0]	next_rd_ptr;
wire	[ASB:0]	next_wr_ptr;

wire	[ASB:0]	gray_rd_ptr_w;
wire	[ASB:0]	gray_wr_ptr_w;

reg	[ASB:0]	gray_rd_ptr_r	= 0;
reg	[ASB:0]	gray_wr_ptr_r	= 0;

wire	aempty_n;
wire	afull_n;
reg	rempty2	= 0;
reg	wfull2	= 0;


reg	ahalf_n	= 1;
reg	rhalf2	= 0;
reg	whalf2	= 0;









reg    [WIDTH-1:0]  mem [0:15];



always @ (posedge wr_clk_i)
begin
	if (wr_en_i && reset_ni)
		mem [gray_wr_ptr_r [ASB:0]]	<= #2 wr_data_i;
end

assign	#2 rd_data_o	= mem [gray_rd_ptr_r [ASB:0]];






assign	#2 next_rd_ptr	= !rempty_o ? bin_rd_ptr + rd_en_i : bin_rd_ptr;
always @(posedge rd_clk_i or negedge reset_ni)
begin
	if (!reset_ni)
	begin
		bin_rd_ptr	<= #2 0;
		gray_rd_ptr_r	<= #2 0;
	end
	else
	begin


		gray_rd_ptr_r	<= #2 gray_rd_ptr_w;
		bin_rd_ptr	<= #2 next_rd_ptr;
	end
end


assign	#2 next_wr_ptr	= !wfull_o ? bin_wr_ptr + wr_en_i : bin_wr_ptr;
always @(posedge wr_clk_i or negedge reset_ni)
begin
	if (!reset_ni)
	begin
		bin_wr_ptr	<= #2 0;
		gray_wr_ptr_r	<= #2 0;
	end
	else
	begin
		gray_wr_ptr_r	<= #2 gray_wr_ptr_w;
		bin_wr_ptr	<= #2 next_wr_ptr;
	end
end













reg	direction	= 0;
wire	#2 dirset_n	= ~((gray_wr_ptr_r [ASB] ^ gray_rd_ptr_r [ASB-1]) & ~(gray_wr_ptr_r [ASB-1] ^ gray_rd_ptr_r [ASB]));
wire	#2 dirclr_n	= ~((~(gray_wr_ptr_r [ASB] ^ gray_rd_ptr_r [ASB-1]) & (gray_wr_ptr_r [ASB-1] ^ gray_rd_ptr_r [ASB])) | ~reset_ni);

always @(negedge dirset_n or negedge dirclr_n)
	if	(!dirclr_n)	direction <= #2 1'b0;
	else			direction <= #2 1'b1;

assign	#2 aempty_n	= ~((gray_wr_ptr_r == gray_rd_ptr_r) && !direction);
assign	#2 afull_n	= ~((gray_wr_ptr_r == gray_rd_ptr_r) && direction);



always @(posedge rd_clk_i or negedge aempty_n)
	if (!aempty_n)	{rempty_o, rempty2}	<= #2 2'b11;
	else		{rempty_o, rempty2}	<= #2 {rempty2, ~aempty_n};



always @(posedge wr_clk_i or negedge reset_ni or negedge afull_n)
	if	(!reset_ni)	{wfull_o, wfull2}	<= #2 2'b00;
	else if	(!afull_n)	{wfull_o, wfull2}	<= #2 2'b11;
	else			{wfull_o, wfull2}	<= #2 {wfull2, ~afull_n};




wire	[1:0] qr	= gray_rd_ptr_r [ASB:ASB-1];
wire	[1:0] qw	= gray_wr_ptr_r [ASB:ASB-1];
always @(qr or qw)
	case ({qr, qw})
	4'b00_00:	ahalf_n	<= #2 1;
	4'b00_01:	ahalf_n	<= #2 1;
	4'b00_11:	ahalf_n	<= #2 0;
	4'b00_10:	ahalf_n	<= #2 0;
	
	4'b01_00:	ahalf_n	<= #2 0;
	4'b01_01:	ahalf_n	<= #2 1;
	4'b01_11:	ahalf_n	<= #2 1;
	4'b01_10:	ahalf_n	<= #2 0;
	
	4'b11_00:	ahalf_n	<= #2 0;
	4'b11_01:	ahalf_n	<= #2 0;
	4'b11_11:	ahalf_n	<= #2 1;
	4'b11_10:	ahalf_n	<= #2 1;
	
	4'b10_00:	ahalf_n	<= #2 1;
	4'b10_01:	ahalf_n	<= #2 0;
	4'b10_11:	ahalf_n	<= #2 0;
	4'b10_10:	ahalf_n	<= #2 1;
	endcase

always @(posedge rd_clk_i or negedge reset_ni or negedge ahalf_n)
	if (!reset_ni)		{rhalfish_o, rhalf2}	<= #2 2'b00;
	else if	(!ahalf_n)	{rhalfish_o, rhalf2}	<= #2 2'b11;
	else			{rhalfish_o, rhalf2}	<= #2 {rhalf2, ~ahalf_n};

always @(posedge wr_clk_i or negedge reset_ni or negedge ahalf_n)
	if (!reset_ni)		{whalfish_o, whalf2}	<= #2 2'b00;
	else if	(!ahalf_n)	{whalfish_o, whalf2}	<= #2 2'b11;
	else			{whalfish_o, whalf2}	<= #2 {whalf2, ~ahalf_n};



defparam	B2G0.WIDTH	= ADDRESS;
bin2gray B2G0 (
	.bin_i	(next_rd_ptr),
	.gray_o	(gray_rd_ptr_w)
);


defparam	B2G1.WIDTH	= ADDRESS;
bin2gray B2G1 (
	.bin_i	(next_wr_ptr),
	.gray_o	(gray_wr_ptr_w)
);


endmodule
module afifo16 #(
	parameter	WIDTH	= 32,
	parameter	ADDRESS	= 4,
	parameter	MSB	= WIDTH - 1,
	parameter	ASB	= ADDRESS - 1
) (
	input		reset_ni,
	
	input		rd_clk_i,
	input		rd_en_i,
	output	[MSB:0]	rd_data_o,

	
	input		wr_clk_i,
	input		wr_en_i,
	input	[MSB:0]	wr_data_i,
	
	output	reg	rempty_o	= 1,
	output	reg	wfull_o		= 0,
	output	reg	rhalfish_o	= 0,
	output	reg	whalfish_o	= 0
);



reg	[ASB:0]	bin_rd_ptr	= 0;
reg	[ASB:0]	bin_wr_ptr	= 0;

wire	[ASB:0]	next_rd_ptr;
wire	[ASB:0]	next_wr_ptr;

wire	[ASB:0]	gray_rd_ptr_w;
wire	[ASB:0]	gray_wr_ptr_w;

reg	[ASB:0]	gray_rd_ptr_r	= 0;
reg	[ASB:0]	gray_wr_ptr_r	= 0;

wire	aempty_n;
wire	afull_n;
reg	rempty2	= 0;
reg	wfull2	= 0;


reg	ahalf_n	= 1;
reg	rhalf2	= 0;
reg	whalf2	= 0;









reg    [WIDTH-1:0]  mem [0:15];



always @ (posedge wr_clk_i)
begin
	if (wr_en_i && reset_ni)
		mem [gray_wr_ptr_r [ASB:0]]	<= #2 wr_data_i;
end

assign	#2 rd_data_o	= mem [gray_rd_ptr_r [ASB:0]];






assign	#2 next_rd_ptr	= !rempty_o ? bin_rd_ptr + rd_en_i : bin_rd_ptr;
always @(posedge rd_clk_i or negedge reset_ni)
begin
	if (!reset_ni)
	begin
		bin_rd_ptr	<= #2 0;
		gray_rd_ptr_r	<= #2 0;
	end
	else
	begin


		gray_rd_ptr_r	<= #2 gray_rd_ptr_w;
		bin_rd_ptr	<= #2 next_rd_ptr;
	end
end


assign	#2 next_wr_ptr	= !wfull_o ? bin_wr_ptr + wr_en_i : bin_wr_ptr;
always @(posedge wr_clk_i or negedge reset_ni)
begin
	if (!reset_ni)
	begin
		bin_wr_ptr	<= #2 0;
		gray_wr_ptr_r	<= #2 0;
	end
	else
	begin
		gray_wr_ptr_r	<= #2 gray_wr_ptr_w;
		bin_wr_ptr	<= #2 next_wr_ptr;
	end
end













reg	direction	= 0;
wire	#2 dirset_n	= ~((gray_wr_ptr_r [ASB] ^ gray_rd_ptr_r [ASB-1]) & ~(gray_wr_ptr_r [ASB-1] ^ gray_rd_ptr_r [ASB]));
wire	#2 dirclr_n	= ~((~(gray_wr_ptr_r [ASB] ^ gray_rd_ptr_r [ASB-1]) & (gray_wr_ptr_r [ASB-1] ^ gray_rd_ptr_r [ASB])) | ~reset_ni);

always @(negedge dirset_n or negedge dirclr_n)
	if	(!dirclr_n)	direction <= #2 1'b0;
	else			direction <= #2 1'b1;

assign	#2 aempty_n	= ~((gray_wr_ptr_r == gray_rd_ptr_r) && !direction);
assign	#2 afull_n	= ~((gray_wr_ptr_r == gray_rd_ptr_r) && direction);



always @(posedge rd_clk_i or negedge aempty_n)
	if (!aempty_n)	{rempty_o, rempty2}	<= #2 2'b11;
	else		{rempty_o, rempty2}	<= #2 {rempty2, ~aempty_n};



always @(posedge wr_clk_i or negedge reset_ni or negedge afull_n)
	if	(!reset_ni)	{wfull_o, wfull2}	<= #2 2'b00;
	else if	(!afull_n)	{wfull_o, wfull2}	<= #2 2'b11;
	else			{wfull_o, wfull2}	<= #2 {wfull2, ~afull_n};




wire	[1:0] qr	= gray_rd_ptr_r [ASB:ASB-1];
wire	[1:0] qw	= gray_wr_ptr_r [ASB:ASB-1];
always @(qr or qw)
	case ({qr, qw})
	4'b00_00:	ahalf_n	<= #2 1;
	4'b00_01:	ahalf_n	<= #2 1;
	4'b00_11:	ahalf_n	<= #2 0;
	4'b00_10:	ahalf_n	<= #2 0;
	
	4'b01_00:	ahalf_n	<= #2 0;
	4'b01_01:	ahalf_n	<= #2 1;
	4'b01_11:	ahalf_n	<= #2 1;
	4'b01_10:	ahalf_n	<= #2 0;
	
	4'b11_00:	ahalf_n	<= #2 0;
	4'b11_01:	ahalf_n	<= #2 0;
	4'b11_11:	ahalf_n	<= #2 1;
	4'b11_10:	ahalf_n	<= #2 1;
	
	4'b10_00:	ahalf_n	<= #2 1;
	4'b10_01:	ahalf_n	<= #2 0;
	4'b10_11:	ahalf_n	<= #2 0;
	4'b10_10:	ahalf_n	<= #2 1;
	endcase

always @(posedge rd_clk_i or negedge reset_ni or negedge ahalf_n)
	if (!reset_ni)		{rhalfish_o, rhalf2}	<= #2 2'b00;
	else if	(!ahalf_n)	{rhalfish_o, rhalf2}	<= #2 2'b11;
	else			{rhalfish_o, rhalf2}	<= #2 {rhalf2, ~ahalf_n};

always @(posedge wr_clk_i or negedge reset_ni or negedge ahalf_n)
	if (!reset_ni)		{whalfish_o, whalf2}	<= #2 2'b00;
	else if	(!ahalf_n)	{whalfish_o, whalf2}	<= #2 2'b11;
	else			{whalfish_o, whalf2}	<= #2 {whalf2, ~ahalf_n};



defparam	B2G0.WIDTH	= ADDRESS;
bin2gray B2G0 (
	.bin_i	(next_rd_ptr),
	.gray_o	(gray_rd_ptr_w)
);


defparam	B2G1.WIDTH	= ADDRESS;
bin2gray B2G1 (
	.bin_i	(next_wr_ptr),
	.gray_o	(gray_wr_ptr_w)
);


endmodule