data/full_repos/permissive/214858095/FPGA_Exploration/spartan6/B205mini/ISE_Project/lib/fifo/axis_strm_monitor.v
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data/verilator_xmls/f596a3b2-a524-462d-bfa3-40a32a403d7f.xml
module axis_strm_monitor #(
  parameter WIDTH         = 64,
  parameter COUNT_W       = 32,
  parameter PKT_LENGTH_EN = 0,
  parameter PKT_CHKSUM_EN = 0,
  parameter PKT_COUNT_EN  = 0,
  parameter XFER_COUNT_EN = 0
)(

  input  wire               clk,
  input  wire               reset,

  input  wire [WIDTH-1:0]   axis_tdata,
  input  wire               axis_tlast,
  input  wire               axis_tvalid,
  input  wire               axis_tready,

  output wire               sop,
  output wire               eop,
  output reg  [15:0]        pkt_length = 16'd0,
  output wire [WIDTH-1:0]   pkt_chksum,

  output reg  [COUNT_W-1:0] pkt_count  = {COUNT_W{1'b0}},
  output reg  [COUNT_W-1:0] xfer_count = {COUNT_W{1'b0}}
);





  reg pkt_head = 1'b1;
  wire xfer = axis_tvalid & axis_tready;

  assign sop = pkt_head & xfer;
  assign eop = xfer & axis_tlast;

  always @(posedge clk) begin
    if (reset) begin
      pkt_head <= 1'b1;
    end else begin
      if (pkt_head) begin
        if (xfer)
          pkt_head <= ~eop;
      end else begin
        if (eop)
          pkt_head <= 1'b0;
      end
    end
  end

  generate if (PKT_LENGTH_EN) begin

    always @(posedge clk) begin
      if (reset | eop) begin
        pkt_length <= 16'd1;
      end else if (xfer) begin
        pkt_length <= pkt_length + 1'b1;
      end
    end
  end else begin

    always @(*) pkt_length <= 16'd0;
  end endgenerate

  generate if (PKT_CHKSUM_EN) begin

    reg [WIDTH-1:0] chksum_prev = {WIDTH{1'b0}};
    always @(posedge clk) begin
      if (reset) begin
        chksum_prev <= {WIDTH{1'b0}};
      end else if (xfer) begin
        chksum_prev <= pkt_chksum;
      end
    end
    assign pkt_chksum = chksum_prev ^ axis_tdata;
  end else begin

    assign pkt_chksum = {WIDTH{1'b0}};
  end endgenerate





  always @(posedge clk) begin
    if (reset | (PKT_COUNT_EN == 0)) begin
      pkt_count <= {COUNT_W{1'b0}};
    end else if (eop) begin
      pkt_count <= pkt_count + 1'b1;
    end
  end

  always @(posedge clk) begin
    if (reset | (XFER_COUNT_EN == 0)) begin
      xfer_count <= {COUNT_W{1'b0}};
    end else if (xfer) begin
      xfer_count <= xfer_count + 1'b1;
    end
  end

 endmodule
module axis_strm_monitor #(
  parameter WIDTH         = 64,
  parameter COUNT_W       = 32,
  parameter PKT_LENGTH_EN = 0,
  parameter PKT_CHKSUM_EN = 0,
  parameter PKT_COUNT_EN  = 0,
  parameter XFER_COUNT_EN = 0
)(

  input  wire               clk,
  input  wire               reset,

  input  wire [WIDTH-1:0]   axis_tdata,
  input  wire               axis_tlast,
  input  wire               axis_tvalid,
  input  wire               axis_tready,

  output wire               sop,
  output wire               eop,
  output reg  [15:0]        pkt_length = 16'd0,
  output wire [WIDTH-1:0]   pkt_chksum,

  output reg  [COUNT_W-1:0] pkt_count  = {COUNT_W{1'b0}},
  output reg  [COUNT_W-1:0] xfer_count = {COUNT_W{1'b0}}
);






  reg pkt_head = 1'b1;
  wire xfer = axis_tvalid & axis_tready;

  assign sop = pkt_head & xfer;
  assign eop = xfer & axis_tlast;

  always @(posedge clk) begin
    if (reset) begin
      pkt_head <= 1'b1;
    end else begin
      if (pkt_head) begin
        if (xfer)
          pkt_head <= ~eop;
      end else begin
        if (eop)
          pkt_head <= 1'b0;
      end
    end
  end

  generate if (PKT_LENGTH_EN) begin

    always @(posedge clk) begin
      if (reset | eop) begin
        pkt_length <= 16'd1;
      end else if (xfer) begin
        pkt_length <= pkt_length + 1'b1;
      end
    end
  end else begin

    always @(*) pkt_length <= 16'd0;
  end endgenerate

  generate if (PKT_CHKSUM_EN) begin

    reg [WIDTH-1:0] chksum_prev = {WIDTH{1'b0}};
    always @(posedge clk) begin
      if (reset) begin
        chksum_prev <= {WIDTH{1'b0}};
      end else if (xfer) begin
        chksum_prev <= pkt_chksum;
      end
    end
    assign pkt_chksum = chksum_prev ^ axis_tdata;
  end else begin

    assign pkt_chksum = {WIDTH{1'b0}};
  end endgenerate





  always @(posedge clk) begin
    if (reset | (PKT_COUNT_EN == 0)) begin
      pkt_count <= {COUNT_W{1'b0}};
    end else if (eop) begin
      pkt_count <= pkt_count + 1'b1;
    end
  end

  always @(posedge clk) begin
    if (reset | (XFER_COUNT_EN == 0)) begin
      xfer_count <= {COUNT_W{1'b0}};
    end else if (xfer) begin
      xfer_count <= xfer_count + 1'b1;
    end
  end

 endmodule