data/full_repos/permissive/174323821/hdl/ver/fast_pll.v
 line:33: before: "real"
1: b'%Error: data/full_repos/permissive/174323821/hdl/ver/fast_pll.v:33: Define or directive not defined: \'`JTFRAME_PLLSIM\'\n    localparam real BASE_CLK=`JTFRAME_PLLSIM;\n                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/174323821/hdl/ver/fast_pll.v:33: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam real BASE_CLK=`JTFRAME_PLLSIM;\n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/174323821/hdl/ver/fast_pll.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #30 locked = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module jtframe_pll0(
    input        inclk0,
    output   reg c0,
    output   reg c1,
    output       c2,
    output   reg c3,
    output   reg c4,
    output   reg locked
);
    localparam real BASE_CLK=`JTFRAME_PLLSIM;

    initial begin
        locked = 0;
        #30 locked = 1;
    end

    reg nc;

    initial begin
        {c0,c1,c3,c4,nc} = 0;
        forever c0 = #(BASE_CLK/2.0) ~c0;
    end

    always @(posedge c0) begin
        {c4,nc,c3,c1} <= {c4,nc,c3,c1} + 1'b1;
    end

    `ifdef SDRAM_DELAY
    real sdram_delay = `SDRAM_DELAY;
    initial $display("INFO: SDRAM_CLK delay set to %f ns",sdram_delay);
    assign #sdram_delay c2 = c1;
    `else
    initial $display("INFO: SDRAM_CLK delay set to 1 ns");
    assign #1 c2 = c1;
    `endif

endmodule
module jtframe_pll0(
    input        inclk0,
    output   reg c0,
    output   reg c1,
    output       c2,
    output   reg c3,
    output   reg c4,
    output   reg locked
);

    localparam real BASE_CLK=`JTFRAME_PLLSIM;

    initial begin
        locked = 0;
        #30 locked = 1;
    end

    reg nc;

    initial begin
        {c0,c1,c3,c4,nc} = 0;
        forever c0 = #(BASE_CLK/2.0) ~c0;
    end

    always @(posedge c0) begin
        {c4,nc,c3,c1} <= {c4,nc,c3,c1} + 1'b1;
    end

    `ifdef SDRAM_DELAY
    real sdram_delay = `SDRAM_DELAY;
    initial $display("INFO: SDRAM_CLK delay set to %f ns",sdram_delay);
    assign #sdram_delay c2 = c1;
    `else
    initial $display("INFO: SDRAM_CLK delay set to 1 ns");
    assign #1 c2 = c1;
    `endif

endmodule