data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot4_alm.sv
 line:32: before: "DATA_WIDTH"
1: b'%Error: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot4_alm.sv:78: Cannot find file containing module: \'dot2_alm\'\n   dot2_alm # ( DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot2_1 (clk, rst, ena, a1_in, a2_in, b1_in, b2_in, dot2_res[0]);\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl,data/full_repos/permissive/150152921/dot2_alm\n             data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl,data/full_repos/permissive/150152921/dot2_alm.v\n             data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl,data/full_repos/permissive/150152921/dot2_alm.sv\n             dot2_alm\n             dot2_alm.v\n             dot2_alm.sv\n             obj_dir/dot2_alm\n             obj_dir/dot2_alm.v\n             obj_dir/dot2_alm.sv\n%Error: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot4_alm.sv:80: Cannot find file containing module: \'dot2_alm\'\n   dot2_alm # ( DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot2_2 (clk, rst, ena, a3_in, a4_in, b3_in, b4_in, dot2_res[1]);\n   ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot4_alm.sv:85: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 17 bits.\n                                                                                                : ... In instance dot4_alm\n   assign dot2_res_e[0] = $signed(dot2_res[0]);\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot4_alm.sv:86: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 17 bits.\n                                                                                                : ... In instance dot4_alm\n   assign dot2_res_e[1] = $signed(dot2_res[1]);\n                        ^\n%Error: data/full_repos/permissive/150152921/apps/dotproduct/baseline/rtl/dot4_alm.sv:89: Cannot find file containing module: \'nBit_mLength_shiftRegister\'\n   nBit_mLength_shiftRegister # ( DATA_WIDTH*2+2, TREE_DELAY ) dot4_q (clk, rst, ena, dot2_res_e[0] + dot2_res_e[1], res_out);\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module dot4_alm # (
		   DATA_WIDTH = 8,
		   MULT_LATENCY = 4,
		   TREE_DELAY = 1
		   ) (
		      clk,
		      rst,
		      ena,

		      a1_in,
		      a2_in,
		      a3_in,
		      a4_in,

		      b1_in,
		      b2_in,
		      b3_in,
		      b4_in,

		      res_out
		      );



   input   wire                        clk;
   input   wire                        rst;
   input   wire                        ena;

   input   wire [DATA_WIDTH-1:0]       a1_in;
   input   wire [DATA_WIDTH-1:0]       a2_in;
   input   wire [DATA_WIDTH-1:0]       a3_in;
   input   wire [DATA_WIDTH-1:0]       a4_in;

   input   wire [DATA_WIDTH-1:0]       b1_in;
   input   wire [DATA_WIDTH-1:0]       b2_in;
   input   wire [DATA_WIDTH-1:0]       b3_in;
   input   wire [DATA_WIDTH-1:0]       b4_in;

   output  wire [DATA_WIDTH*2-1+2:0]   res_out;



   wire [DATA_WIDTH*2-1+1:0] 	       dot2_res [1:0];




   dot2_alm # ( DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot2_1 (clk, rst, ena, a1_in, a2_in, b1_in, b2_in, dot2_res[0]);

   dot2_alm # ( DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot2_2 (clk, rst, ena, a3_in, a4_in, b3_in, b4_in, dot2_res[1]);



   wire [DATA_WIDTH*2-1+2:0] 	       dot2_res_e [1:0];
   assign dot2_res_e[0] = $signed(dot2_res[0]);
   assign dot2_res_e[1] = $signed(dot2_res[1]);


   nBit_mLength_shiftRegister # ( DATA_WIDTH*2+2, TREE_DELAY ) dot4_q (clk, rst, ena, dot2_res_e[0] + dot2_res_e[1], res_out);

endmodule
module dot4_alm # (
		   DATA_WIDTH = 8,
		   MULT_LATENCY = 4,
		   TREE_DELAY = 1
		   ) (
		      clk,
		      rst,
		      ena,

		      a1_in,
		      a2_in,
		      a3_in,
		      a4_in,

		      b1_in,
		      b2_in,
		      b3_in,
		      b4_in,

		      res_out
		      );




   input   wire                        clk;
   input   wire                        rst;
   input   wire                        ena;

   input   wire [DATA_WIDTH-1:0]       a1_in;
   input   wire [DATA_WIDTH-1:0]       a2_in;
   input   wire [DATA_WIDTH-1:0]       a3_in;
   input   wire [DATA_WIDTH-1:0]       a4_in;

   input   wire [DATA_WIDTH-1:0]       b1_in;
   input   wire [DATA_WIDTH-1:0]       b2_in;
   input   wire [DATA_WIDTH-1:0]       b3_in;
   input   wire [DATA_WIDTH-1:0]       b4_in;

   output  wire [DATA_WIDTH*2-1+2:0]   res_out;



   wire [DATA_WIDTH*2-1+1:0] 	       dot2_res [1:0];




   dot2_alm # ( DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot2_1 (clk, rst, ena, a1_in, a2_in, b1_in, b2_in, dot2_res[0]);

   dot2_alm # ( DATA_WIDTH, MULT_LATENCY, TREE_DELAY) dot2_2 (clk, rst, ena, a3_in, a4_in, b3_in, b4_in, dot2_res[1]);



   wire [DATA_WIDTH*2-1+2:0] 	       dot2_res_e [1:0];
   assign dot2_res_e[0] = $signed(dot2_res[0]);
   assign dot2_res_e[1] = $signed(dot2_res[1]);


   nBit_mLength_shiftRegister # ( DATA_WIDTH*2+2, TREE_DELAY ) dot4_q (clk, rst, ena, dot2_res_e[0] + dot2_res_e[1], res_out);

endmodule