data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v
 line:29: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:149: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU_tb.v:13: Cannot find file containing module: \'ALU\'\nALU dut (\n^~~\n        ... Looked in:\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/ALU\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/ALU.v\n             data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles,data/full_repos/permissive/184366791/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 33 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_tb();
reg branch_op;
reg [5:0] ctrl;
reg [31:0] opA, opB;

wire [31:0] result;
wire branch;

ALU dut (
  .branch_op(branch_op),
  .ALU_Control(ctrl),
  .operand_A(opA),
  .operand_B(opB),
  .ALU_result(result),
  .branch(branch)
);

initial begin
  branch_op = 1'b0;
  ctrl = 6'b000000;
  opA = 4;
  opB = 5;

  #10
  $display("ALU Result 4 + 5: %d",result);
  #10
  ctrl = 6'b000010;
  #10
  $display("ALU Result 4 < 5: %d",result);
  #10
  opB = 32'hffffffff;
  #10
  $display("ALU Result 4 < -1: %d",result);
  #10
  branch_op = 1'b1;
  opB = 32'hffffffff;
  opA = 32'hffffffff;
  ctrl = 6'b010_000; 
  #10
  $display("ALU Result: -1==-1: %d",result);
  $display("branch: branch_op=1 and result: %b", branch);


  branch_op = 1'b0;
  opB = 32'h00000001;
  opA = 32'h00000001;
  ctrl = 6'b011_111;
  #10
  $display("ALU Result: JAL opA=1: %d",result);
  opB = 32'hffffffff;
  opA = 32'hffffffff;
  ctrl = 6'b111_111; 
  #10
  $display("ALU Result: JALR, opA=-1: (binary)%b",result);
  branch_op = 1'b1;
  opB = 32'hffffffff;
  opA = 32'hfffffffe;
  ctrl = 6'b010_000; 
  #10
  $display("ALU Result: -2==-1: %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'hffffffff;
  opA = 32'hfffffffe;
  ctrl = 6'b010_001; 
  #10
  $display("ALU Result: -2!=-1: %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'hffffffff;
  opA = 32'hfffffffe;
  ctrl = 6'b010_001;
  #10
  $display("ALU Result -2<-1: %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'hffffffff;
  opA = 32'hfffffffe;
  ctrl = 6'b010_101; 
  #10
  $display("ALU Result: -2>=-1 %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'hffffffff;
  opA = 32'hffffffff;
  ctrl = 6'b010_101;
  #10
  $display("ALU Result: -1>=-1 %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'hffffffff;
  opA = 32'h00000001;
  ctrl = 6'b010_110; 
  #10
  $display("ALU Result: 1 <UINT_MAX: %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'hffffffff;
  opA = 32'h00000001;
  ctrl = 6'b010_111;
  #10
  $display("ALU Result: 1>UINT_MAX %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'h00000001;
  opA = 32'h00000001;
  ctrl = 6'b010_111;
  #10
  $display("ALU Result: 1>=1: %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  branch_op = 1'b0;
  opB = 32'h00000001;
  opA = 32'h00000001;
  ctrl = 6'b000_010; 
  #10
  $display("ALU Result: 1<1: %d",result);
  opB = 32'hffffffff;
  opA = 32'h00000001;
  ctrl = 6'b000_011; 
  #10
  $display("ALU Result: 1<UINT_MAX: %d",result);
  opB = 32'h00000101;
  opA = 32'h00000001;
  ctrl = 6'b000_100; 
  #10
  $display("ALU Result: 0x00000001^0x00000101=0x00000100=256: %d",result);
  opB = 32'h00000101;
  opA = 32'h00000001;
  ctrl = 6'b000_110; 
  #10
  $display("ALU Result: 0x00000001|0x00000101=0x00000101=257: %d",result);
  opB = 32'h00010101;
  opA = 32'h00000001;
  ctrl = 6'b000_111; 
  #10
  $display("ALU Result: 0x00000001&0x00010101=1: %d",result);
  opB = 32'h00000001;
  opA = 32'h00000001;
  ctrl = 6'b000_001; 
  #10
  $display("ALU Result b01<<d1=b10=2: %d",result);
  opB = 32'h00000005;
  opA = 32'h00000011;
  ctrl = 6'b000_101; 
  #10
  $display("ALU Result: b10001>>d5=b00000=0: %d",result);
  opB = 32'h00000001;
  opA = 32'h00000011;
  ctrl = 6'b000_101; 
  #10
  $display("ALU Result: b010001>>d1=b1000=8: %d",result);
  opB = 32'h00000002;
  opA = 32'h00000011;
  ctrl = 6'b000_101; 
  #10
  $display("ALU Result: b10001>>d2=b00100=4: %d",result);
  opB = 32'h00000005;
  opA = 32'hfffffffc;
  ctrl = 6'b001_101;
  #10
  $display("ALU Result:  d-4>>>d5=-1: (binary) %b",result);
  opB = 32'h00000005;
  opA = 32'd4;
  ctrl = 6'b001_101;
  #10
  $display("ALU Result:  d4>>>d5=0: (binary) %b",result);
  opB = 32'hfffff010;
  opA = 32'b00000000000000010000000000000000; 
  ctrl = 6'b001_101;
  #10
  $display("ALU Result:  d2^16>>>d16=1: %d",result);
  opB = 32'h00000002;
  opA = 32'h00000011;
  ctrl = 6'b001_101; 
  #10
  $display("ALU Result: b10001>>>d2=b100=4: %d",result);
  opB = 32'h00000100;
  opA = 32'h00000101;
  ctrl = 6'b001_000; 
  #10
  $display("ALU Result: 0x00000101-0x00000100=1: %d",result);
  opB = 32'hffffffff;
  opA = 32'h00000001;
  ctrl = 6'b001_000; 
  #10
  $display("ALU Result: 1-(-1): %d",result);
  #10
  $stop();
end

endmodule
module ALU_tb();

reg branch_op;
reg [5:0] ctrl;
reg [31:0] opA, opB;

wire [31:0] result;
wire branch;

ALU dut (
  .branch_op(branch_op),
  .ALU_Control(ctrl),
  .operand_A(opA),
  .operand_B(opB),
  .ALU_result(result),
  .branch(branch)
);

initial begin
  branch_op = 1'b0;
  ctrl = 6'b000000;
  opA = 4;
  opB = 5;

  #10
  $display("ALU Result 4 + 5: %d",result);
  #10
  ctrl = 6'b000010;
  #10
  $display("ALU Result 4 < 5: %d",result);
  #10
  opB = 32'hffffffff;
  #10
  $display("ALU Result 4 < -1: %d",result);
  #10
  branch_op = 1'b1;
  opB = 32'hffffffff;
  opA = 32'hffffffff;
  ctrl = 6'b010_000; 
  #10
  $display("ALU Result: -1==-1: %d",result);
  $display("branch: branch_op=1 and result: %b", branch);


  branch_op = 1'b0;
  opB = 32'h00000001;
  opA = 32'h00000001;
  ctrl = 6'b011_111;
  #10
  $display("ALU Result: JAL opA=1: %d",result);
  opB = 32'hffffffff;
  opA = 32'hffffffff;
  ctrl = 6'b111_111; 
  #10
  $display("ALU Result: JALR, opA=-1: (binary)%b",result);
  branch_op = 1'b1;
  opB = 32'hffffffff;
  opA = 32'hfffffffe;
  ctrl = 6'b010_000; 
  #10
  $display("ALU Result: -2==-1: %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'hffffffff;
  opA = 32'hfffffffe;
  ctrl = 6'b010_001; 
  #10
  $display("ALU Result: -2!=-1: %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'hffffffff;
  opA = 32'hfffffffe;
  ctrl = 6'b010_001;
  #10
  $display("ALU Result -2<-1: %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'hffffffff;
  opA = 32'hfffffffe;
  ctrl = 6'b010_101; 
  #10
  $display("ALU Result: -2>=-1 %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'hffffffff;
  opA = 32'hffffffff;
  ctrl = 6'b010_101;
  #10
  $display("ALU Result: -1>=-1 %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'hffffffff;
  opA = 32'h00000001;
  ctrl = 6'b010_110; 
  #10
  $display("ALU Result: 1 <UINT_MAX: %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'hffffffff;
  opA = 32'h00000001;
  ctrl = 6'b010_111;
  #10
  $display("ALU Result: 1>UINT_MAX %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  opB = 32'h00000001;
  opA = 32'h00000001;
  ctrl = 6'b010_111;
  #10
  $display("ALU Result: 1>=1: %d",result);
  $display("branch: branch_op=1 and result: %b", branch);
  branch_op = 1'b0;
  opB = 32'h00000001;
  opA = 32'h00000001;
  ctrl = 6'b000_010; 
  #10
  $display("ALU Result: 1<1: %d",result);
  opB = 32'hffffffff;
  opA = 32'h00000001;
  ctrl = 6'b000_011; 
  #10
  $display("ALU Result: 1<UINT_MAX: %d",result);
  opB = 32'h00000101;
  opA = 32'h00000001;
  ctrl = 6'b000_100; 
  #10
  $display("ALU Result: 0x00000001^0x00000101=0x00000100=256: %d",result);
  opB = 32'h00000101;
  opA = 32'h00000001;
  ctrl = 6'b000_110; 
  #10
  $display("ALU Result: 0x00000001|0x00000101=0x00000101=257: %d",result);
  opB = 32'h00010101;
  opA = 32'h00000001;
  ctrl = 6'b000_111; 
  #10
  $display("ALU Result: 0x00000001&0x00010101=1: %d",result);
  opB = 32'h00000001;
  opA = 32'h00000001;
  ctrl = 6'b000_001; 
  #10
  $display("ALU Result b01<<d1=b10=2: %d",result);
  opB = 32'h00000005;
  opA = 32'h00000011;
  ctrl = 6'b000_101; 
  #10
  $display("ALU Result: b10001>>d5=b00000=0: %d",result);
  opB = 32'h00000001;
  opA = 32'h00000011;
  ctrl = 6'b000_101; 
  #10
  $display("ALU Result: b010001>>d1=b1000=8: %d",result);
  opB = 32'h00000002;
  opA = 32'h00000011;
  ctrl = 6'b000_101; 
  #10
  $display("ALU Result: b10001>>d2=b00100=4: %d",result);
  opB = 32'h00000005;
  opA = 32'hfffffffc;
  ctrl = 6'b001_101;
  #10
  $display("ALU Result:  d-4>>>d5=-1: (binary) %b",result);
  opB = 32'h00000005;
  opA = 32'd4;
  ctrl = 6'b001_101;
  #10
  $display("ALU Result:  d4>>>d5=0: (binary) %b",result);
  opB = 32'hfffff010;
  opA = 32'b00000000000000010000000000000000; 
  ctrl = 6'b001_101;
  #10
  $display("ALU Result:  d2^16>>>d16=1: %d",result);
  opB = 32'h00000002;
  opA = 32'h00000011;
  ctrl = 6'b001_101; 
  #10
  $display("ALU Result: b10001>>>d2=b100=4: %d",result);
  opB = 32'h00000100;
  opA = 32'h00000101;
  ctrl = 6'b001_000; 
  #10
  $display("ALU Result: 0x00000101-0x00000100=1: %d",result);
  opB = 32'hffffffff;
  opA = 32'h00000001;
  ctrl = 6'b001_000; 
  #10
  $display("ALU Result: 1-(-1): %d",result);
  #10
  $stop();
end

endmodule