data/full_repos/permissive/208741034/uart/rtl/uart_rx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/208741034/uart/rtl/uart_rx.v:52: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'clk_cnt\' generates 16 bits.\n                                                                          : ... In instance uart_rx\n      else if((rx_cnt == 4\'d9) && (clk_cnt == BPS_CNT/2))  \n                                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/208741034/uart/rtl/uart_rx.v:68: Operator LT expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'clk_cnt\' generates 16 bits.\n                                                                          : ... In instance uart_rx\n        if(clk_cnt < BPS_CNT - 1)begin\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/208741034/uart/rtl/uart_rx.v:89: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'clk_cnt\' generates 16 bits.\n                                                                          : ... In instance uart_rx\n      if(clk_cnt == BPS_CNT / 2)begin\n                 ^~\n%Error: Exiting due to 3 warning(s)\n'
module uart_rx(

    input               clk,
    input               rst_n,
    
    input               uart_rx_data,
    
    output  reg [7 : 0] uart_data,
    output  reg         uart_rx_done 
);

parameter   CLK_FREQ   = 50000000;
parameter   UART_BPS  = 115200;
localparam  BPS_CNT   = CLK_FREQ / UART_BPS;

reg [15 : 0] clk_cnt;
reg [3  : 0] rx_cnt;
reg [ 7 : 0] rxdata;

reg rx_flag;

reg uart_rx_d0;
reg uart_rx_d1;

wire       start_flag;
assign  start_flag = uart_rx_d1 & (~uart_rx_d0);  



always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
    uart_rx_d0 <= 1'b0;
    uart_rx_d1 <= 1'b0;
    end
    else begin
       uart_rx_d0 <= uart_rx_data;
       uart_rx_d1 <= uart_rx_d0;    
    end

end
  




always @(posedge clk or negedge rst_n)begin
   if(!rst_n)
     rx_flag <= 1'b0;
   else begin
     if(start_flag)
       rx_flag <= 1'b1;
      else if((rx_cnt == 4'd9) && (clk_cnt == BPS_CNT/2))
       rx_flag <= 1'b0;
      else
       rx_flag <= rx_flag;
   end

end



always @(posedge clk or negedge rst_n)begin
     if(!rst_n) begin
      clk_cnt <= 16'd0;
      rx_cnt  <= 4'd0 ;
     end 
     else if(rx_flag)begin
        if(clk_cnt < BPS_CNT - 1)begin
           clk_cnt <= clk_cnt + 1'd1;
           rx_cnt  <= rx_cnt;
        end
        else begin
          clk_cnt <= 16'd0;
          rx_cnt <= rx_cnt + 1'd1;
        end
     end
     else begin
        clk_cnt <= 16'd0;
        rx_cnt  <= 4'd0;
     end

end


always @(posedge clk or negedge rst_n)begin
  if(!rst_n)
  rxdata <= 8'd0;
  else if(rx_flag)begin
      if(clk_cnt == BPS_CNT / 2)begin

         case(rx_cnt)
         4'd1: rxdata[0] <= uart_rx_d1;
         4'd2: rxdata[1] <= uart_rx_d1;
         4'd3: rxdata[2] <= uart_rx_d1;
         4'd4: rxdata[3] <= uart_rx_d1;
         4'd5: rxdata[4] <= uart_rx_d1;
         4'd6: rxdata[5] <= uart_rx_d1;
         4'd7: rxdata[6] <= uart_rx_d1;
         4'd8: rxdata[7] <= uart_rx_d1;
         default: ;
         endcase
      
      end
      
      else 
      rxdata <= rxdata;
    end
    else 
      rxdata <= 8'd0;
end


always @(posedge clk or negedge rst_n)begin
    if(!rst_n )begin
    uart_data <= 8'd0;
    uart_rx_done <= 1'b0;
    end
    else if(rx_cnt == 4'd9)begin
       uart_data <= rxdata;
       uart_rx_done <= 1'b1;
    end
    else begin
       uart_data <= 8'd0;
       uart_rx_done <= 1'b0;
    end 
      

end
endmodule
module uart_rx(

    input               clk,
    input               rst_n,
    
    input               uart_rx_data,
    
    output  reg [7 : 0] uart_data,
    output  reg         uart_rx_done 
);


parameter   CLK_FREQ   = 50000000;
parameter   UART_BPS  = 115200;
localparam  BPS_CNT   = CLK_FREQ / UART_BPS;

reg [15 : 0] clk_cnt;
reg [3  : 0] rx_cnt;
reg [ 7 : 0] rxdata;

reg rx_flag;

reg uart_rx_d0;
reg uart_rx_d1;

wire       start_flag;
assign  start_flag = uart_rx_d1 & (~uart_rx_d0);  



always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
    uart_rx_d0 <= 1'b0;
    uart_rx_d1 <= 1'b0;
    end
    else begin
       uart_rx_d0 <= uart_rx_data;
       uart_rx_d1 <= uart_rx_d0;    
    end

end
  




always @(posedge clk or negedge rst_n)begin
   if(!rst_n)
     rx_flag <= 1'b0;
   else begin
     if(start_flag)
       rx_flag <= 1'b1;
      else if((rx_cnt == 4'd9) && (clk_cnt == BPS_CNT/2))
       rx_flag <= 1'b0;
      else
       rx_flag <= rx_flag;
   end

end



always @(posedge clk or negedge rst_n)begin
     if(!rst_n) begin
      clk_cnt <= 16'd0;
      rx_cnt  <= 4'd0 ;
     end 
     else if(rx_flag)begin
        if(clk_cnt < BPS_CNT - 1)begin
           clk_cnt <= clk_cnt + 1'd1;
           rx_cnt  <= rx_cnt;
        end
        else begin
          clk_cnt <= 16'd0;
          rx_cnt <= rx_cnt + 1'd1;
        end
     end
     else begin
        clk_cnt <= 16'd0;
        rx_cnt  <= 4'd0;
     end

end


always @(posedge clk or negedge rst_n)begin
  if(!rst_n)
  rxdata <= 8'd0;
  else if(rx_flag)begin
      if(clk_cnt == BPS_CNT / 2)begin

         case(rx_cnt)
         4'd1: rxdata[0] <= uart_rx_d1;
         4'd2: rxdata[1] <= uart_rx_d1;
         4'd3: rxdata[2] <= uart_rx_d1;
         4'd4: rxdata[3] <= uart_rx_d1;
         4'd5: rxdata[4] <= uart_rx_d1;
         4'd6: rxdata[5] <= uart_rx_d1;
         4'd7: rxdata[6] <= uart_rx_d1;
         4'd8: rxdata[7] <= uart_rx_d1;
         default: ;
         endcase
      
      end
      
      else 
      rxdata <= rxdata;
    end
    else 
      rxdata <= 8'd0;
end


always @(posedge clk or negedge rst_n)begin
    if(!rst_n )begin
    uart_data <= 8'd0;
    uart_rx_done <= 1'b0;
    end
    else if(rx_cnt == 4'd9)begin
       uart_data <= rxdata;
       uart_rx_done <= 1'b1;
    end
    else begin
       uart_data <= 8'd0;
       uart_rx_done <= 1'b0;
    end 
      

end
endmodule