data/full_repos/permissive/177038316/project.v
1: b'%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:457: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'HUNDREDS\' generates 2 bits.\n                                                                  : ... In instance top.m3\n    case(HUNDREDS)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:344: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'data_y\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y - data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:344: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'data_x\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y - data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:349: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'data_y\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y + data_x;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/177038316/project.v:349: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'data_x\' generates 8 bits.\n                                                                  : ... In instance top.m2\n    aux <= data_y + data_x;\n                  ^\n%Error: Exiting due to 5 warning(s)\n'
module controle(nova_instrucao, instrucao, clk, ready, tx, ty, tz, tula);
	input wire nova_instrucao, clk;
	input wire [2:0] instrucao;
	output reg ready, tula;
	output reg[1:0] tx, ty, tz;
	
	parameter IDLE = 3'b101, CLRLD = 3'b000, ADD = 3'b001, SUB = 3'b010, DISP = 3'b011, LOAD = 3'b100;
	parameter clear = 2'b00, load = 2'b01, hold = 2'b10;
	

	always @ (*)
	begin
	if (nova_instrucao == 0)
		begin
			tx <= hold;
			ty <= hold;
			tz <= hold;
		end
	else begin
		case(instrucao)		
		CLRLD:
		begin
			ready <= 1'b0;
			tx <=  2'b00; 
			ty <=  2'b00;
			tz <=  2'b00;
			ready <= 1'b1;
		end
		ADD:
		begin
			ready <= 1'b0;
			tula <= 1'b0;
			ty <= load;
			tx <= clear;
			tz <= hold;			
			ready <= 1'b1;
		end
		SUB:
		begin
			ready <= 1'b0;
			tula <= 1'b1;
			ty <= load;
			tx <= clear;
			tz <= hold;			
			ready <= 1'b1;
		end
		DISP:
		begin
			ready <= 1'b0;
			tx <= hold;
			ty <= hold;
			tz <= load;
			ready <= 1'b1;
		end
		LOAD:
		begin 
			ready <= 1'b0;
			tx <= load;
			ty <= hold;
			tz <= hold;
			ready <= 1'b1;
		end
		endcase
	end
	end
endmodule
module controle(nova_instrucao, instrucao, clk, ready, tx, ty, tz, tula);

	input wire nova_instrucao, clk;
	input wire [2:0] instrucao;
	output reg ready, tula;
	output reg[1:0] tx, ty, tz;
	
	parameter IDLE = 3'b101, CLRLD = 3'b000, ADD = 3'b001, SUB = 3'b010, DISP = 3'b011, LOAD = 3'b100;
	parameter clear = 2'b00, load = 2'b01, hold = 2'b10;
	

	always @ (*)
	begin
	if (nova_instrucao == 0)
		begin
			tx <= hold;
			ty <= hold;
			tz <= hold;
		end
	else begin
		case(instrucao)		
		CLRLD:
		begin
			ready <= 1'b0;
			tx <=  2'b00; 
			ty <=  2'b00;
			tz <=  2'b00;
			ready <= 1'b1;
		end
		ADD:
		begin
			ready <= 1'b0;
			tula <= 1'b0;
			ty <= load;
			tx <= clear;
			tz <= hold;			
			ready <= 1'b1;
		end
		SUB:
		begin
			ready <= 1'b0;
			tula <= 1'b1;
			ty <= load;
			tx <= clear;
			tz <= hold;			
			ready <= 1'b1;
		end
		DISP:
		begin
			ready <= 1'b0;
			tx <= hold;
			ty <= hold;
			tz <= load;
			ready <= 1'b1;
		end
		LOAD:
		begin 
			ready <= 1'b0;
			tx <= load;
			ty <= hold;
			tz <= hold;
			ready <= 1'b1;
		end
		endcase
	end
	end
endmodule