data/full_repos/permissive/186676986/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/186676986/test.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/186676986/test.v:65: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk=~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/186676986/test.v:66: Unsupported: Ignoring delay on this delayed statement.\n   always #20 X=~X;\n          ^\n%Error: data/full_repos/permissive/186676986/test.v:39: Cannot find file containing module: \'tlc\'\n tlc uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/186676986,data/full_repos/permissive/186676986/tlc\n             data/full_repos/permissive/186676986,data/full_repos/permissive/186676986/tlc.v\n             data/full_repos/permissive/186676986,data/full_repos/permissive/186676986/tlc.sv\n             tlc\n             tlc.v\n             tlc.sv\n             obj_dir/tlc\n             obj_dir/tlc.v\n             obj_dir/tlc.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_v;


	reg X;
	reg clk;
	reg clr;
	reg reset;


	wire [1:0] hwy;
	wire [1:0] cntry;
	wire slowclk;


	tlc uut (
		.X(X),  
		.clr(clr), 
		.hwy(hwy), 
		.slowclk(slowclk),
		.cntry(cntry)
	);

	initial begin

		X = 0;
		clk = 0;
		clr = 1;


		#100;
		
		clr=0;
		
		
		
        


	end
	
	always #5 clk=~clk;
			always #20 X=~X;

      
endmodule
module test_v;



	reg X;
	reg clk;
	reg clr;
	reg reset;


	wire [1:0] hwy;
	wire [1:0] cntry;
	wire slowclk;


	tlc uut (
		.X(X),  
		.clr(clr), 
		.hwy(hwy), 
		.slowclk(slowclk),
		.cntry(cntry)
	);

	initial begin

		X = 0;
		clk = 0;
		clr = 1;


		#100;
		
		clr=0;
		
		
		
        


	end
	
	always #5 clk=~clk;
			always #20 X=~X;

      
endmodule