data/full_repos/permissive/125927162/EM4100/EM4100_tb.v
 line:33: before: "$"
1: b'%Error: data/full_repos/permissive/125927162/EM4100/EM4100_tb.v:25: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("EM4100.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125927162/EM4100/EM4100_tb.v:26: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, DUT);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125927162/EM4100/EM4100_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #4\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/125927162/EM4100/EM4100_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #1000\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/125927162/EM4100/EM4100_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n   always #1 clk = !clk;\n          ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module EM4100_tb();
   reg clk;
   reg tx;
   reg [39:0] data;
   wire       q;

   EM4100 DUT(
	      .clk(clk),
	      .tx(tx),
	      .data(data),
	      .q(q));

   initial begin
      $dumpfile("EM4100.vcd");
      $dumpvars(0, DUT);
      clk = 0;
      tx = 0;
      data = {{20{1'b1}}, {20{1'b0}}};
      #4
      tx = 1;
      #1000
      $finish;
   end

   always #1 clk = !clk;
endmodule
module EM4100_tb();

   reg clk;
   reg tx;
   reg [39:0] data;
   wire       q;

   EM4100 DUT(
	      .clk(clk),
	      .tx(tx),
	      .data(data),
	      .q(q));

   initial begin
      $dumpfile("EM4100.vcd");
      $dumpvars(0, DUT);
      clk = 0;
      tx = 0;
      data = {{20{1'b1}}, {20{1'b0}}};
      #4
      tx = 1;
      #1000
      $finish;
   end

   always #1 clk = !clk;
endmodule