data/full_repos/permissive/210844779/lab2/2.6/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab2/2.6/tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/210844779/lab2/2.6/tb.v:7: Cannot find file containing module: \'mux16x1\'\nmux16x1 u0(I,S,Y);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab2/2.6,data/full_repos/permissive/210844779/mux16x1\n             data/full_repos/permissive/210844779/lab2/2.6,data/full_repos/permissive/210844779/mux16x1.v\n             data/full_repos/permissive/210844779/lab2/2.6,data/full_repos/permissive/210844779/mux16x1.sv\n             mux16x1\n             mux16x1.v\n             mux16x1.sv\n             obj_dir/mux16x1\n             obj_dir/mux16x1.v\n             obj_dir/mux16x1.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab2/2.6/tb.v:12: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\nI=$random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab2/2.6/tb.v:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                     : ... In instance tb\nS=$random;\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

reg [15:0]I;
reg [3:0]S;
wire Y;

mux16x1 u0(I,S,Y);

always
begin

I=$random;
S=$random;

#10;

end

endmodule
module tb();


reg [15:0]I;
reg [3:0]S;
wire Y;

mux16x1 u0(I,S,Y);

always
begin

I=$random;
S=$random;

#10;

end

endmodule