data/full_repos/permissive/169574047/fulladd4/fulladd4.srcs/sources_1/new/fulladd.v
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data/verilator_xmls/a21977d9-469e-4ddb-a05a-4fc48243e994.xml
module fulladd(output sum,c_out, input a,b,c_in);


wire s1, c1, c2;


xor (s1, a, b);
and (c1, a, b);

xor(sum, s1, c_in);
and(c2, s1, c_in);

xor(c_out, c2, c1);

endmodule
module fulladd(output sum,c_out, input a,b,c_in);



wire s1, c1, c2;


xor (s1, a, b);
and (c1, a, b);

xor(sum, s1, c_in);
and(c2, s1, c_in);

xor(c_out, c2, c1);

endmodule