data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v
None: at end of input
1: b'%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:28: Cannot find include file: spio_spinnaker_link.h\n`include "spio_spinnaker_link.h" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.v\n             data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link,data/full_repos/permissive/156407853/spio_spinnaker_link.h.sv\n             spio_spinnaker_link.h\n             spio_spinnaker_link.h.v\n             spio_spinnaker_link.h.sv\n             obj_dir/spio_spinnaker_link.h\n             obj_dir/spio_spinnaker_link.h.v\n             obj_dir/spio_spinnaker_link.h.sv\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:49: Define or directive not defined: \'`PKT_BITS\'\n  output wire [`PKT_BITS - 1:0] PKT_DATA_OUT,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:510: Define or directive not defined: \'`PKT_BITS\'\n  output reg  [`PKT_BITS - 1:0] PKT_DATA_OUT,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:538: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] bad_pkt;        \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:550: Define or directive not defined: \'`PKT_BITS\'\n  reg   [`PKT_BITS - 1:0] pkt_buf;    \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/156407853/Files/Verilog/spinnaker_link/spio_spinnaker_link_synchronous_receiver.v:650: Define or directive not defined: \'`PKT_BITS\'\n      pkt_buf <= {flt_data_bin, pkt_buf[`PKT_BITS - 1:4]};\n                                        ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module pkt_deserializer
(
  input                         CLK_IN,
  input                         RESET_IN,


  output reg                    FLT_ERR_OUT,
  output reg                    FRM_ERR_OUT,


  input                   [6:0] flt_data_bad,
  input                   [3:0] flt_data_bin,
  input                         flt_dat,
  input                         flt_bad,
  input                         flt_eop,
  output reg                    flt_cts,


  output reg  [`PKT_BITS - 1:0] PKT_DATA_OUT,
  output reg                    PKT_VLD_OUT,
  input                         PKT_RDY_IN
);





  localparam STATE_BITS = 2;
  localparam IDLE_ST    = 0;
  localparam TRAN_ST    = IDLE_ST + 1;
  localparam WAIT_ST    = TRAN_ST + 1;

  localparam SPKT_FLTS = 10;
  localparam LPKT_FLTS = 18;





  reg       exp_eop;

  reg [5:0] flit_cnt;

  reg       long_pkt;

  reg                     send_bad_pkt;
  reg   [`PKT_BITS - 1:0] bad_pkt;
  reg                     bad_pkt_pty;
  reg               [6:0] bad_flt_dat;
  reg               [5:0] bad_flt_cnt;
  reg               [7:0] bad_flt_cyc;

  reg               [6:0] dbg_flt_dat;
  reg               [5:0] dbg_flt_cnt;
  reg               [7:0] dbg_flt_cyc;

  reg               [7:0] cycle_cnt;

  reg   [`PKT_BITS - 1:0] pkt_buf;

  reg                     pkt_busy;

  reg                     send_pkt;

  reg                     pkt_out;

  reg  [STATE_BITS - 1:0] state;





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_cts <= 1'b0;
    else
      case (state)
        IDLE_ST,
	TRAN_ST: if (flt_eop && pkt_busy)
                   flt_cts <= 1'b0;
                 else
                   flt_cts <= 1'b1;

	WAIT_ST: if (!pkt_busy)
                   flt_cts <= 1'b1;

        default:   flt_cts <= 1'b1;
      endcase 





  always @(posedge CLK_IN)
    if ((state == IDLE_ST) && flt_dat)
      long_pkt <= flt_data_bin[1];





  always @ (*)
    exp_eop = (!long_pkt && (flit_cnt == SPKT_FLTS))
                || (flit_cnt == LPKT_FLTS);





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flit_cnt <= 0;
    else
      if (flt_dat || flt_bad)
        flit_cnt <= flit_cnt + 1;
      else if (pkt_out)
        flit_cnt <= 0;





  always @(posedge CLK_IN)
    if (pkt_out)
      if (!exp_eop  || send_bad_pkt)
        PKT_DATA_OUT <= bad_pkt;
      else if (long_pkt)
        PKT_DATA_OUT <= pkt_buf;
      else
        PKT_DATA_OUT <= pkt_buf >> 32;





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      PKT_VLD_OUT <= 1'b0;
    else
      if (!pkt_busy)
        if (send_pkt)
          PKT_VLD_OUT <= 1'b1;
        else
          PKT_VLD_OUT <= 1'b0;





  always @(*)
    pkt_busy = PKT_VLD_OUT && !PKT_RDY_IN;





  always @(posedge CLK_IN)
    if (flt_dat && flt_cts)
      pkt_buf <= {flt_data_bin, pkt_buf[`PKT_BITS - 1:4]};





  always @(*)
    case (state)
      IDLE_ST,
      TRAN_ST: if (flt_eop)
                 send_pkt = 1;
               else
                 send_pkt = 0;

      WAIT_ST:   send_pkt = 1;

      default:   send_pkt = 0;
    endcase 





  always @(*)
    pkt_out = send_pkt && !pkt_busy;





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      cycle_cnt <= 0;
    else
      if (pkt_out)
        cycle_cnt <= 0;
      else
        if (state == IDLE_ST)
          cycle_cnt <= 1;
        else if (state != WAIT_ST)
          cycle_cnt <= cycle_cnt + 1;





  wire pre_cycle = (!send_bad_pkt && (flt_dat || flt_eop));
  wire pos_cycle = (send_bad_pkt && (cycle_cnt == (bad_flt_cyc + 1)));

  wire dbg_cycle = pos_cycle;
   

  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      send_bad_pkt <= 1'b0;
    else
      if (flt_bad)
        send_bad_pkt <= 1'b1;
      else if (pkt_out)
        send_bad_pkt <= 1'b0;
        
  always @(posedge CLK_IN)
    if (flt_bad && !send_bad_pkt)
      bad_flt_dat <= flt_data_bad;
    else if (pkt_out)
      bad_flt_dat <= 0;
        
  always @(posedge CLK_IN)
    if (flt_bad && !send_bad_pkt)
      bad_flt_cnt <= flit_cnt;
    else if (pkt_out)
      bad_flt_cnt <= 0;
        
  always @(posedge CLK_IN)
    if (flt_bad && !send_bad_pkt)
      bad_flt_cyc <= cycle_cnt;
    else if (pkt_out)
      bad_flt_cyc <= 8'hcc;
        
  always @(posedge CLK_IN)
    if (dbg_cycle)
      dbg_flt_dat <= flt_data_bad;
    else if (pkt_out)
      dbg_flt_dat <= 0;
        
  always @(posedge CLK_IN)
    if (dbg_cycle)
      dbg_flt_cnt <= flit_cnt;
    else if (pkt_out)
      dbg_flt_cnt <= 0;
        
  always @(posedge CLK_IN)
    if (dbg_cycle)
      dbg_flt_cyc <= cycle_cnt;
    else if (pkt_out)
      dbg_flt_cyc <= 8'hcc;
        
  always @(*)
    bad_pkt_pty = ^(dbg_flt_cyc ^ dbg_flt_dat ^ dbg_flt_cnt
                     ^ bad_flt_cyc ^ exp_eop ^ send_bad_pkt
                     ^ flit_cnt ^ bad_flt_dat ^ bad_flt_cnt
                   );

  always @(*)
    bad_pkt = {bad_flt_cyc, dbg_flt_cyc,
                1'b0, dbg_flt_dat, 2'b00, dbg_flt_cnt,
                4'hb, 2'b00, exp_eop, send_bad_pkt,
                2'b00, flit_cnt,
                1'b0, bad_flt_dat,
                2'b00, bad_flt_cnt,
	        7'b0000001, bad_pkt_pty
              };





  reg flt_err_ext;
  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_err_ext <= 1'b0;
    else
      flt_err_ext <= FLT_ERR_OUT;

  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      FLT_ERR_OUT <= 1'b0;
    else
      if (flt_bad && !send_bad_pkt)
        FLT_ERR_OUT <= 1'b1;
      else if (flt_err_ext)
        FLT_ERR_OUT <= 1'b0;

  reg frm_err_ext;
  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      frm_err_ext <= 1'b0;
    else
      frm_err_ext <= FRM_ERR_OUT;

  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      FRM_ERR_OUT <= 1'b0;
    else
      if (flt_eop && !exp_eop)
        FRM_ERR_OUT <= 1'b1;
      else if (frm_err_ext)
        FRM_ERR_OUT <= 1'b0;






  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      state <= IDLE_ST;
    else
      case (state)
        IDLE_ST: casex ({flt_dat, flt_bad, flt_eop, pkt_busy})
                   4'b1xxx,
                   4'bx1xx: state <= TRAN_ST;
                   4'bxx11: state <= WAIT_ST;
                   default: state <= IDLE_ST;
                 endcase

        TRAN_ST: casex ({flt_eop, pkt_busy})
	           2'b10:
                     state <= IDLE_ST;

		   2'b11:
                     state <= WAIT_ST;

                   default:
                     state <= TRAN_ST;
                 endcase

        WAIT_ST: if (!pkt_busy)
                   state <= IDLE_ST;
      endcase
endmodule
module pkt_deserializer
(
  input                         CLK_IN,
  input                         RESET_IN,


  output reg                    FLT_ERR_OUT,
  output reg                    FRM_ERR_OUT,


  input                   [6:0] flt_data_bad,
  input                   [3:0] flt_data_bin,
  input                         flt_dat,
  input                         flt_bad,
  input                         flt_eop,
  output reg                    flt_cts,


  output reg  [`PKT_BITS - 1:0] PKT_DATA_OUT,
  output reg                    PKT_VLD_OUT,
  input                         PKT_RDY_IN
);






  localparam STATE_BITS = 2;
  localparam IDLE_ST    = 0;
  localparam TRAN_ST    = IDLE_ST + 1;
  localparam WAIT_ST    = TRAN_ST + 1;

  localparam SPKT_FLTS = 10;
  localparam LPKT_FLTS = 18;





  reg       exp_eop;

  reg [5:0] flit_cnt;

  reg       long_pkt;

  reg                     send_bad_pkt;
  reg   [`PKT_BITS - 1:0] bad_pkt;
  reg                     bad_pkt_pty;
  reg               [6:0] bad_flt_dat;
  reg               [5:0] bad_flt_cnt;
  reg               [7:0] bad_flt_cyc;

  reg               [6:0] dbg_flt_dat;
  reg               [5:0] dbg_flt_cnt;
  reg               [7:0] dbg_flt_cyc;

  reg               [7:0] cycle_cnt;

  reg   [`PKT_BITS - 1:0] pkt_buf;

  reg                     pkt_busy;

  reg                     send_pkt;

  reg                     pkt_out;

  reg  [STATE_BITS - 1:0] state;





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_cts <= 1'b0;
    else
      case (state)
        IDLE_ST,
	TRAN_ST: if (flt_eop && pkt_busy)
                   flt_cts <= 1'b0;
                 else
                   flt_cts <= 1'b1;

	WAIT_ST: if (!pkt_busy)
                   flt_cts <= 1'b1;

        default:   flt_cts <= 1'b1;
      endcase 





  always @(posedge CLK_IN)
    if ((state == IDLE_ST) && flt_dat)
      long_pkt <= flt_data_bin[1];





  always @ (*)
    exp_eop = (!long_pkt && (flit_cnt == SPKT_FLTS))
                || (flit_cnt == LPKT_FLTS);





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flit_cnt <= 0;
    else
      if (flt_dat || flt_bad)
        flit_cnt <= flit_cnt + 1;
      else if (pkt_out)
        flit_cnt <= 0;





  always @(posedge CLK_IN)
    if (pkt_out)
      if (!exp_eop  || send_bad_pkt)
        PKT_DATA_OUT <= bad_pkt;
      else if (long_pkt)
        PKT_DATA_OUT <= pkt_buf;
      else
        PKT_DATA_OUT <= pkt_buf >> 32;





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      PKT_VLD_OUT <= 1'b0;
    else
      if (!pkt_busy)
        if (send_pkt)
          PKT_VLD_OUT <= 1'b1;
        else
          PKT_VLD_OUT <= 1'b0;





  always @(*)
    pkt_busy = PKT_VLD_OUT && !PKT_RDY_IN;





  always @(posedge CLK_IN)
    if (flt_dat && flt_cts)
      pkt_buf <= {flt_data_bin, pkt_buf[`PKT_BITS - 1:4]};





  always @(*)
    case (state)
      IDLE_ST,
      TRAN_ST: if (flt_eop)
                 send_pkt = 1;
               else
                 send_pkt = 0;

      WAIT_ST:   send_pkt = 1;

      default:   send_pkt = 0;
    endcase 





  always @(*)
    pkt_out = send_pkt && !pkt_busy;





  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      cycle_cnt <= 0;
    else
      if (pkt_out)
        cycle_cnt <= 0;
      else
        if (state == IDLE_ST)
          cycle_cnt <= 1;
        else if (state != WAIT_ST)
          cycle_cnt <= cycle_cnt + 1;





  wire pre_cycle = (!send_bad_pkt && (flt_dat || flt_eop));
  wire pos_cycle = (send_bad_pkt && (cycle_cnt == (bad_flt_cyc + 1)));

  wire dbg_cycle = pos_cycle;
   

  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      send_bad_pkt <= 1'b0;
    else
      if (flt_bad)
        send_bad_pkt <= 1'b1;
      else if (pkt_out)
        send_bad_pkt <= 1'b0;
        
  always @(posedge CLK_IN)
    if (flt_bad && !send_bad_pkt)
      bad_flt_dat <= flt_data_bad;
    else if (pkt_out)
      bad_flt_dat <= 0;
        
  always @(posedge CLK_IN)
    if (flt_bad && !send_bad_pkt)
      bad_flt_cnt <= flit_cnt;
    else if (pkt_out)
      bad_flt_cnt <= 0;
        
  always @(posedge CLK_IN)
    if (flt_bad && !send_bad_pkt)
      bad_flt_cyc <= cycle_cnt;
    else if (pkt_out)
      bad_flt_cyc <= 8'hcc;
        
  always @(posedge CLK_IN)
    if (dbg_cycle)
      dbg_flt_dat <= flt_data_bad;
    else if (pkt_out)
      dbg_flt_dat <= 0;
        
  always @(posedge CLK_IN)
    if (dbg_cycle)
      dbg_flt_cnt <= flit_cnt;
    else if (pkt_out)
      dbg_flt_cnt <= 0;
        
  always @(posedge CLK_IN)
    if (dbg_cycle)
      dbg_flt_cyc <= cycle_cnt;
    else if (pkt_out)
      dbg_flt_cyc <= 8'hcc;
        
  always @(*)
    bad_pkt_pty = ^(dbg_flt_cyc ^ dbg_flt_dat ^ dbg_flt_cnt
                     ^ bad_flt_cyc ^ exp_eop ^ send_bad_pkt
                     ^ flit_cnt ^ bad_flt_dat ^ bad_flt_cnt
                   );

  always @(*)
    bad_pkt = {bad_flt_cyc, dbg_flt_cyc,
                1'b0, dbg_flt_dat, 2'b00, dbg_flt_cnt,
                4'hb, 2'b00, exp_eop, send_bad_pkt,
                2'b00, flit_cnt,
                1'b0, bad_flt_dat,
                2'b00, bad_flt_cnt,
	        7'b0000001, bad_pkt_pty
              };





  reg flt_err_ext;
  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      flt_err_ext <= 1'b0;
    else
      flt_err_ext <= FLT_ERR_OUT;

  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      FLT_ERR_OUT <= 1'b0;
    else
      if (flt_bad && !send_bad_pkt)
        FLT_ERR_OUT <= 1'b1;
      else if (flt_err_ext)
        FLT_ERR_OUT <= 1'b0;

  reg frm_err_ext;
  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      frm_err_ext <= 1'b0;
    else
      frm_err_ext <= FRM_ERR_OUT;

  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      FRM_ERR_OUT <= 1'b0;
    else
      if (flt_eop && !exp_eop)
        FRM_ERR_OUT <= 1'b1;
      else if (frm_err_ext)
        FRM_ERR_OUT <= 1'b0;






  always @(posedge CLK_IN or posedge RESET_IN)
    if (RESET_IN)
      state <= IDLE_ST;
    else
      case (state)
        IDLE_ST: casex ({flt_dat, flt_bad, flt_eop, pkt_busy})
                   4'b1xxx,
                   4'bx1xx: state <= TRAN_ST;
                   4'bxx11: state <= WAIT_ST;
                   default: state <= IDLE_ST;
                 endcase

        TRAN_ST: casex ({flt_eop, pkt_busy})
	           2'b10:
                     state <= IDLE_ST;

		   2'b11:
                     state <= WAIT_ST;

                   default:
                     state <= TRAN_ST;
                 endcase

        WAIT_ST: if (!pkt_busy)
                   state <= IDLE_ST;
      endcase
endmodule