data/full_repos/permissive/154123726/3rdParty/luffa/Luffa_Chaining.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/154123726/3rdParty/luffa/Luffa_Chaining.v:113: Multiple top level modules\n                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                           : ... Top module \'MESSAGE_INJECTION\'\nmodule MESSAGE_INJECTION(\n       ^~~~~~~~~~~~~~~~~\n                                                                                           : ... Top module \'PERMUTATION_Q\'\nmodule PERMUTATION_Q(\n       ^~~~~~~~~~~~~\n                                                                                           : ... Top module \'GEN_CONST\'\nmodule GEN_CONST(\n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module MESSAGE_INJECTION(
	                      msg,
	                      state_00, state_01, state_02, state_03, state_04, state_05, state_06, state_07,
	                      state_10, state_11, state_12, state_13, state_14, state_15, state_16, state_17,
	                      state_20, state_21, state_22, state_23, state_24, state_25, state_26, state_27,
	                      mi_00, mi_01, mi_02, mi_03, mi_04, mi_05, mi_06, mi_07,
	                      mi_10, mi_11, mi_12, mi_13, mi_14, mi_15, mi_16, mi_17,
	                      mi_20, mi_21, mi_22, mi_23, mi_24, mi_25, mi_26, mi_27
                        );

input  [255:0] msg;
input  [ 31:0] state_00, state_01, state_02, state_03, state_04, state_05, state_06, state_07;
input  [ 31:0] state_10, state_11, state_12, state_13, state_14, state_15, state_16, state_17;
input  [ 31:0] state_20, state_21, state_22, state_23, state_24, state_25, state_26, state_27;
output [ 31:0] mi_00, mi_01, mi_02, mi_03, mi_04, mi_05, mi_06, mi_07;
output [ 31:0] mi_10, mi_11, mi_12, mi_13, mi_14, mi_15, mi_16, mi_17;
output [ 31:0] mi_20, mi_21, mi_22, mi_23, mi_24, mi_25, mi_26, mi_27;

wire [31:0] xor_all_state0, xor_all_state1, xor_all_state2, xor_all_state3, xor_all_state4, xor_all_state5, xor_all_state6, xor_all_state7;
wire [31:0] mul_xas0, mul_xas1, mul_xas2, mul_xas3, mul_xas4, mul_xas5, mul_xas6, mul_xas7;
wire [31:0] mul_msg0, mul_msg1, mul_msg2, mul_msg3, mul_msg4, mul_msg5, mul_msg6, mul_msg7;
wire [31:0] mul2_msg0, mul2_msg1, mul2_msg2, mul2_msg3, mul2_msg4, mul2_msg5, mul2_msg6, mul2_msg7;
wire [31:0] mi_14_bt, mi_15_bt, mi_16_bt, mi_17_bt, mi_24_bt, mi_25_bt, mi_26_bt, mi_27_bt;

MULTIPLY_TWO multiply_two0(.in0(xor_all_state0), .in1(xor_all_state1), .in2(xor_all_state2), .in3(xor_all_state3), .in4(xor_all_state4), .in5(xor_all_state5), .in6(xor_all_state6), .in7(xor_all_state7), .out0(mul_xas0), .out1(mul_xas1), .out2(mul_xas2), .out3(mul_xas3), .out4(mul_xas4), .out5(mul_xas5), .out6(mul_xas6), .out7(mul_xas7));
MULTIPLY_TWO multiply_two1(.in0(msg[255:224]), .in1(msg[223:192]), .in2(msg[191:160]), .in3(msg[159:128]), .in4(msg[127:96]), .in5(msg[95:64]), .in6(msg[63:32]), .in7(msg[31:0]), .out0(mul_msg0), .out1(mul_msg1), .out2(mul_msg2), .out3(mul_msg3), .out4(mul_msg4), .out5(mul_msg5), .out6(mul_msg6), .out7(mul_msg7));
MULTIPLY_TWO multiply_two2(.in0(mul_msg0), .in1(mul_msg1), .in2(mul_msg2), .in3(mul_msg3), .in4(mul_msg4), .in5(mul_msg5), .in6(mul_msg6), .in7(mul_msg7), .out0(mul2_msg0), .out1(mul2_msg1), .out2(mul2_msg2), .out3(mul2_msg3), .out4(mul2_msg4), .out5(mul2_msg5), .out6(mul2_msg6), .out7(mul2_msg7));


assign xor_all_state0 = state_00 ^ state_10 ^ state_20;
assign xor_all_state1 = state_01 ^ state_11 ^ state_21;
assign xor_all_state2 = state_02 ^ state_12 ^ state_22;
assign xor_all_state3 = state_03 ^ state_13 ^ state_23;
assign xor_all_state4 = state_04 ^ state_14 ^ state_24;
assign xor_all_state5 = state_05 ^ state_15 ^ state_25;
assign xor_all_state6 = state_06 ^ state_16 ^ state_26;
assign xor_all_state7 = state_07 ^ state_17 ^ state_27;

assign mi_00 = state_00 ^ msg[255:224] ^ mul_xas0;
assign mi_01 = state_01 ^ msg[223:192] ^ mul_xas1;
assign mi_02 = state_02 ^ msg[191:160] ^ mul_xas2;
assign mi_03 = state_03 ^ msg[159:128] ^ mul_xas3;
assign mi_04 = state_04 ^ msg[127: 96] ^ mul_xas4;
assign mi_05 = state_05 ^ msg[ 95: 64] ^ mul_xas5;
assign mi_06 = state_06 ^ msg[ 63: 32] ^ mul_xas6;
assign mi_07 = state_07 ^ msg[ 31:  0] ^ mul_xas7;
assign mi_10 = state_10 ^ mul_msg0 ^ mul_xas0;
assign mi_11 = state_11 ^ mul_msg1 ^ mul_xas1;
assign mi_12 = state_12 ^ mul_msg2 ^ mul_xas2;
assign mi_13 = state_13 ^ mul_msg3 ^ mul_xas3;
assign mi_14_bt = state_14 ^ mul_msg4 ^ mul_xas4;
assign mi_15_bt = state_15 ^ mul_msg5 ^ mul_xas5;
assign mi_16_bt = state_16 ^ mul_msg6 ^ mul_xas6;
assign mi_17_bt = state_17 ^ mul_msg7 ^ mul_xas7;
assign mi_20 = state_20 ^ mul2_msg0 ^ mul_xas0;
assign mi_21 = state_21 ^ mul2_msg1 ^ mul_xas1;
assign mi_22 = state_22 ^ mul2_msg2 ^ mul_xas2;
assign mi_23 = state_23 ^ mul2_msg3 ^ mul_xas3;
assign mi_24_bt = state_24 ^ mul2_msg4 ^ mul_xas4;
assign mi_25_bt = state_25 ^ mul2_msg5 ^ mul_xas5;
assign mi_26_bt = state_26 ^ mul2_msg6 ^ mul_xas6;
assign mi_27_bt = state_27 ^ mul2_msg7 ^ mul_xas7;

assign mi_14 = {mi_14_bt[30:0],mi_14_bt[31]};
assign mi_15 = {mi_15_bt[30:0],mi_15_bt[31]};
assign mi_16 = {mi_16_bt[30:0],mi_16_bt[31]};
assign mi_17 = {mi_17_bt[30:0],mi_17_bt[31]};
assign mi_24 = {mi_24_bt[29:0],mi_24_bt[31:30]};
assign mi_25 = {mi_25_bt[29:0],mi_25_bt[31:30]};
assign mi_26 = {mi_26_bt[29:0],mi_26_bt[31:30]};
assign mi_27 = {mi_27_bt[29:0],mi_27_bt[31:30]};

endmodule
module MESSAGE_INJECTION(
	                      msg,
	                      state_00, state_01, state_02, state_03, state_04, state_05, state_06, state_07,
	                      state_10, state_11, state_12, state_13, state_14, state_15, state_16, state_17,
	                      state_20, state_21, state_22, state_23, state_24, state_25, state_26, state_27,
	                      mi_00, mi_01, mi_02, mi_03, mi_04, mi_05, mi_06, mi_07,
	                      mi_10, mi_11, mi_12, mi_13, mi_14, mi_15, mi_16, mi_17,
	                      mi_20, mi_21, mi_22, mi_23, mi_24, mi_25, mi_26, mi_27
                        );


input  [255:0] msg;
input  [ 31:0] state_00, state_01, state_02, state_03, state_04, state_05, state_06, state_07;
input  [ 31:0] state_10, state_11, state_12, state_13, state_14, state_15, state_16, state_17;
input  [ 31:0] state_20, state_21, state_22, state_23, state_24, state_25, state_26, state_27;
output [ 31:0] mi_00, mi_01, mi_02, mi_03, mi_04, mi_05, mi_06, mi_07;
output [ 31:0] mi_10, mi_11, mi_12, mi_13, mi_14, mi_15, mi_16, mi_17;
output [ 31:0] mi_20, mi_21, mi_22, mi_23, mi_24, mi_25, mi_26, mi_27;

wire [31:0] xor_all_state0, xor_all_state1, xor_all_state2, xor_all_state3, xor_all_state4, xor_all_state5, xor_all_state6, xor_all_state7;
wire [31:0] mul_xas0, mul_xas1, mul_xas2, mul_xas3, mul_xas4, mul_xas5, mul_xas6, mul_xas7;
wire [31:0] mul_msg0, mul_msg1, mul_msg2, mul_msg3, mul_msg4, mul_msg5, mul_msg6, mul_msg7;
wire [31:0] mul2_msg0, mul2_msg1, mul2_msg2, mul2_msg3, mul2_msg4, mul2_msg5, mul2_msg6, mul2_msg7;
wire [31:0] mi_14_bt, mi_15_bt, mi_16_bt, mi_17_bt, mi_24_bt, mi_25_bt, mi_26_bt, mi_27_bt;

MULTIPLY_TWO multiply_two0(.in0(xor_all_state0), .in1(xor_all_state1), .in2(xor_all_state2), .in3(xor_all_state3), .in4(xor_all_state4), .in5(xor_all_state5), .in6(xor_all_state6), .in7(xor_all_state7), .out0(mul_xas0), .out1(mul_xas1), .out2(mul_xas2), .out3(mul_xas3), .out4(mul_xas4), .out5(mul_xas5), .out6(mul_xas6), .out7(mul_xas7));
MULTIPLY_TWO multiply_two1(.in0(msg[255:224]), .in1(msg[223:192]), .in2(msg[191:160]), .in3(msg[159:128]), .in4(msg[127:96]), .in5(msg[95:64]), .in6(msg[63:32]), .in7(msg[31:0]), .out0(mul_msg0), .out1(mul_msg1), .out2(mul_msg2), .out3(mul_msg3), .out4(mul_msg4), .out5(mul_msg5), .out6(mul_msg6), .out7(mul_msg7));
MULTIPLY_TWO multiply_two2(.in0(mul_msg0), .in1(mul_msg1), .in2(mul_msg2), .in3(mul_msg3), .in4(mul_msg4), .in5(mul_msg5), .in6(mul_msg6), .in7(mul_msg7), .out0(mul2_msg0), .out1(mul2_msg1), .out2(mul2_msg2), .out3(mul2_msg3), .out4(mul2_msg4), .out5(mul2_msg5), .out6(mul2_msg6), .out7(mul2_msg7));


assign xor_all_state0 = state_00 ^ state_10 ^ state_20;
assign xor_all_state1 = state_01 ^ state_11 ^ state_21;
assign xor_all_state2 = state_02 ^ state_12 ^ state_22;
assign xor_all_state3 = state_03 ^ state_13 ^ state_23;
assign xor_all_state4 = state_04 ^ state_14 ^ state_24;
assign xor_all_state5 = state_05 ^ state_15 ^ state_25;
assign xor_all_state6 = state_06 ^ state_16 ^ state_26;
assign xor_all_state7 = state_07 ^ state_17 ^ state_27;

assign mi_00 = state_00 ^ msg[255:224] ^ mul_xas0;
assign mi_01 = state_01 ^ msg[223:192] ^ mul_xas1;
assign mi_02 = state_02 ^ msg[191:160] ^ mul_xas2;
assign mi_03 = state_03 ^ msg[159:128] ^ mul_xas3;
assign mi_04 = state_04 ^ msg[127: 96] ^ mul_xas4;
assign mi_05 = state_05 ^ msg[ 95: 64] ^ mul_xas5;
assign mi_06 = state_06 ^ msg[ 63: 32] ^ mul_xas6;
assign mi_07 = state_07 ^ msg[ 31:  0] ^ mul_xas7;
assign mi_10 = state_10 ^ mul_msg0 ^ mul_xas0;
assign mi_11 = state_11 ^ mul_msg1 ^ mul_xas1;
assign mi_12 = state_12 ^ mul_msg2 ^ mul_xas2;
assign mi_13 = state_13 ^ mul_msg3 ^ mul_xas3;
assign mi_14_bt = state_14 ^ mul_msg4 ^ mul_xas4;
assign mi_15_bt = state_15 ^ mul_msg5 ^ mul_xas5;
assign mi_16_bt = state_16 ^ mul_msg6 ^ mul_xas6;
assign mi_17_bt = state_17 ^ mul_msg7 ^ mul_xas7;
assign mi_20 = state_20 ^ mul2_msg0 ^ mul_xas0;
assign mi_21 = state_21 ^ mul2_msg1 ^ mul_xas1;
assign mi_22 = state_22 ^ mul2_msg2 ^ mul_xas2;
assign mi_23 = state_23 ^ mul2_msg3 ^ mul_xas3;
assign mi_24_bt = state_24 ^ mul2_msg4 ^ mul_xas4;
assign mi_25_bt = state_25 ^ mul2_msg5 ^ mul_xas5;
assign mi_26_bt = state_26 ^ mul2_msg6 ^ mul_xas6;
assign mi_27_bt = state_27 ^ mul2_msg7 ^ mul_xas7;

assign mi_14 = {mi_14_bt[30:0],mi_14_bt[31]};
assign mi_15 = {mi_15_bt[30:0],mi_15_bt[31]};
assign mi_16 = {mi_16_bt[30:0],mi_16_bt[31]};
assign mi_17 = {mi_17_bt[30:0],mi_17_bt[31]};
assign mi_24 = {mi_24_bt[29:0],mi_24_bt[31:30]};
assign mi_25 = {mi_25_bt[29:0],mi_25_bt[31:30]};
assign mi_26 = {mi_26_bt[29:0],mi_26_bt[31:30]};
assign mi_27 = {mi_27_bt[29:0],mi_27_bt[31:30]};

endmodule