data/full_repos/permissive/204608363/65536_8 floatpoint/all_float/pipeline.v
1: b'%Error: Cannot find file containing module: floatpoint/all_float,data/full_repos/permissive/204608363\n        ... Looked in:\n             data/full_repos/permissive/204608363/65536_8/floatpoint/all_float,data/full_repos/permissive/204608363\n             data/full_repos/permissive/204608363/65536_8/floatpoint/all_float,data/full_repos/permissive/204608363.v\n             data/full_repos/permissive/204608363/65536_8/floatpoint/all_float,data/full_repos/permissive/204608363.sv\n             floatpoint/all_float,data/full_repos/permissive/204608363\n             floatpoint/all_float,data/full_repos/permissive/204608363.v\n             floatpoint/all_float,data/full_repos/permissive/204608363.sv\n             obj_dir/floatpoint/all_float,data/full_repos/permissive/204608363\n             obj_dir/floatpoint/all_float,data/full_repos/permissive/204608363.v\n             obj_dir/floatpoint/all_float,data/full_repos/permissive/204608363.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/204608363/65536_8\n%Error: Cannot find file containing module: floatpoint/all_float/pipeline.v\n%Error: Exiting due to 3 error(s)\n'
module pipeline  #(parameter ADDR_Q_WIDTH = 19,parameter ADDR_Qmax_WIDTH = 16, DATA_WIDTH = 32) ( input clk,input rst, input[2:0] action, output wire[31:0] sum);


    reg[DATA_WIDTH-1:0] q;
    reg[DATA_WIDTH-1:0] r;
    reg[DATA_WIDTH-1:0] q1;
    reg[DATA_WIDTH-1:0] r1;
    reg[DATA_WIDTH-1:0] qmax;

    reg[ADDR_Qmax_WIDTH-1:0] s;
    reg[DATA_WIDTH-1:0] alpha;
    reg[DATA_WIDTH-1:0] gamma;
    reg[DATA_WIDTH-1:0] oneminusa;
    reg[DATA_WIDTH-1:0] ag;
    wire result_tvalid;
    wire result_tvalid2;
    wire result_tvalid3;
     wire result_tvalid12;
      wire result_tvalid123;
    

    reg[ADDR_Qmax_WIDTH-1:0] current_s ;
    reg[ADDR_Qmax_WIDTH-1:0] current_s1 ;
    reg[ADDR_Qmax_WIDTH-1:0] current_s2 ;
    reg[ADDR_Qmax_WIDTH-1:0] current_s3 ;
    reg[ADDR_Qmax_WIDTH-1:0] current_s4 ;        

    reg[2:0] current_a ;
    reg[2:0] current_a1 ;
    reg[2:0] current_a2 ;
    reg[2:0] current_a3 ;
    reg[2:0] current_a4 ;
        
    reg[7:0] sx ;
    reg[7:0] sy ;
    reg[ADDR_Qmax_WIDTH-1:0] nexts;





    reg [ADDR_Q_WIDTH-1:0] addrr_q;  
    reg [ADDR_Q_WIDTH-1:0] addrw_q;


    reg rflag_q;
    reg wflag_q;
    reg [DATA_WIDTH-1:0] data_in_q;
    wire [DATA_WIDTH-1:0] data_out_q;


    reg [ADDR_Qmax_WIDTH-1:0] addrr_qmax;
    reg [ADDR_Qmax_WIDTH-1:0] addrw_qmax;
    reg rflag_qmax;
    reg wflag_qmax;
    reg [DATA_WIDTH-1:0] data_in_qmax;
    wire [DATA_WIDTH-1:0] data_out_qmax;


    reg [ADDR_Q_WIDTH-1:0] addr_r;
    reg rflag_r;
    wire [DATA_WIDTH-1:0] data_out_r;
    localparam sf = 2.0**-4.0;

    always @(posedge clk) begin

        if (rst) begin
            s<= {16{1'b0}};
            current_s<={16{1'b0}};
            nexts<={16{1'b0}};
            alpha<=32'b00111111010011001100110011001101;
            gamma<=32'b00111111010011001100110011001101;

        end
 



        ag<=32'b01000111101011100001011;

        oneminusa<=32'b10011001100110011001100;
        

        sx<=s[15:8];sy<=s[7:0]; 
        if (sx=={8{1'b0}} && (action==3'b000)||(action==3'b001)||(action==3'b111)) begin
            nexts<=s;
        end
        else if (sy=={8{1'b0}} && (action==3'b001)||(action==3'b010)||(action==3'b011)) begin
            nexts<=s;      
        end
        else if (sx=={8{1'b1}} &&(action==3'b011)||(action==3'b100)||(action==3'b101)) begin
            nexts<=s;      
        end
        else if (sy=={8{1'b1}} && (action==3'b101)||(action==3'b110)||(action==3'b111)) begin
            nexts<=s;     
        end
        else begin
            case (action)
                3'b000: nexts<=s-16'b0000_0001_0000_0000;
                3'b001: nexts<=s-16'b0000_0001_0000_0001;
                3'b010: nexts<=s-16'b0000_0000_0000_0001;
                3'b011: nexts<=s-16'b0000_0000_0000_0001+16'b0000_0001_0000_0000;
                3'b100: nexts<=s+16'b0000_0001_0000_0000;
                3'b101: nexts<=s+16'b0000_0001_0000_0001;
                3'b110: nexts<=s+16'b0000_0000_0000_0001;
                3'b111: nexts<=s+16'b0000_0000_0000_0001-16'b0000_0001_0000_0000;

            endcase

        end
        

        addrr_q<={s,action}; 
        addr_r<={s,action};
        addrr_qmax<=nexts;



        

        current_s<=s;
        current_s1<=current_s;
        current_a<=action;
        current_a1<=current_a;
        s<=nexts;  
    end   
    
    
    

    always @(posedge clk) begin


        rflag_q<=1;
        q<=data_out_q;
        q1<=q;
        
        rflag_r<=1;
        r<=data_out_r;
        r1<=r;



        
        rflag_qmax<=1;
        qmax<=data_out_qmax;



        
        current_s2<=current_s1;
        current_a2<=current_a1;
        
    end
    


    
    wire [31:0] sum_part1;
    wire [31:0] sum_part2;
    wire [31:0] sum_part12;
    
    wire [31:0] sum_part3;
    reg [31:0] sum_part3a;
    
    
    wire [31:0] sum_part123;
    



    always@(posedge clk)
    begin







        sum_part3a<=sum_part3;


        
        current_s3<=current_s2;
        current_a3<=current_a2;
        current_s4<=current_s3;
        current_a4<=current_a3;

    end   



    always @(posedge clk) begin


        if (sum>q)begin
            wflag_qmax<=1;
            addrw_qmax<=current_s3;
            data_in_qmax<=sum;


        end

        wflag_q<=1;
        addrw_q<={current_s3,current_a3}; 
        data_in_q<=sum;







    end
        
    qtable qt0(
        .i_clk(clk),
        .i_rst(rst),
        .i_addr_r(addrr_q), 
        .i_addr_w(addrw_q),
        .i_read_en(rflag_q), 
        .i_write_en(wflag_q),
        .i_data(data_in_q),
        .o_data(data_out_q)); 

    qmaxtable qmaxt0(
        .i_clk(clk),
        .i_rst(rst),
        .i_addr_r(addrr_qmax), 
        .i_addr_w(addrw_qmax), 
        .i_read_en(rflag_qmax),
        .i_write_en(wflag_qmax),
        .i_data(data_in_qmax),
        .o_data(data_out_qmax)); 

    rtable rt0(
        .i_clk(clk),
        .i_addr(addr_r), 
        .i_read(rflag_r), 
        .o_data(data_out_r));
        
    floating_point_0 sum1 (
      .aclk(clk),
      .s_axis_a_tvalid(1'b1),
      .s_axis_a_tdata(alpha),
      .s_axis_b_tvalid(1'b1),
      .s_axis_b_tdata(r1),
      .m_axis_result_tvalid(result_tvalid),
      .m_axis_result_tdata(sum_part1)
    );
    
    floating_point_0 sum2 (
      .aclk(clk),
      .s_axis_a_tvalid(1'b1),
      .s_axis_a_tdata(oneminusa),
      .s_axis_b_tvalid(1'b1),
      .s_axis_b_tdata(q1),
      .m_axis_result_tvalid(result_tvalid2),
      .m_axis_result_tdata(sum_part2)
    );    
    
    floating_point_0 sum3 (
      .aclk(clk),
      .s_axis_a_tvalid(1'b1),
      .s_axis_a_tdata(ag),
      .s_axis_b_tvalid(1'b1),
      .s_axis_b_tdata(qmax),
      .m_axis_result_tvalid(result_tvalid3),
      .m_axis_result_tdata(sum_part3 )
    );
    
     floating_point_1 sum12 (
     .aclk(clk),
      .s_axis_a_tvalid(1'b1),
      .s_axis_a_tdata(sum_part1),
      .s_axis_b_tvalid(1'b1),
      .s_axis_b_tdata(sum_part2),
      .m_axis_result_tvalid(result_tvalid12),
      .m_axis_result_tdata(sum_part12)
    );

     floating_point_1 sum23 (
     .aclk(clk),
      .s_axis_a_tvalid(1'b1),
      .s_axis_a_tdata(sum_part12),
      .s_axis_b_tvalid(1'b1),
      .s_axis_b_tdata(sum_part3a),
      .m_axis_result_tvalid(result_tvalid123),
      .m_axis_result_tdata(sum)
    );

endmodule
module pipeline  #(parameter ADDR_Q_WIDTH = 19,parameter ADDR_Qmax_WIDTH = 16, DATA_WIDTH = 32) ( input clk,input rst, input[2:0] action, output wire[31:0] sum);



    reg[DATA_WIDTH-1:0] q;
    reg[DATA_WIDTH-1:0] r;
    reg[DATA_WIDTH-1:0] q1;
    reg[DATA_WIDTH-1:0] r1;
    reg[DATA_WIDTH-1:0] qmax;

    reg[ADDR_Qmax_WIDTH-1:0] s;
    reg[DATA_WIDTH-1:0] alpha;
    reg[DATA_WIDTH-1:0] gamma;
    reg[DATA_WIDTH-1:0] oneminusa;
    reg[DATA_WIDTH-1:0] ag;
    wire result_tvalid;
    wire result_tvalid2;
    wire result_tvalid3;
     wire result_tvalid12;
      wire result_tvalid123;
    

    reg[ADDR_Qmax_WIDTH-1:0] current_s ;
    reg[ADDR_Qmax_WIDTH-1:0] current_s1 ;
    reg[ADDR_Qmax_WIDTH-1:0] current_s2 ;
    reg[ADDR_Qmax_WIDTH-1:0] current_s3 ;
    reg[ADDR_Qmax_WIDTH-1:0] current_s4 ;        

    reg[2:0] current_a ;
    reg[2:0] current_a1 ;
    reg[2:0] current_a2 ;
    reg[2:0] current_a3 ;
    reg[2:0] current_a4 ;
        
    reg[7:0] sx ;
    reg[7:0] sy ;
    reg[ADDR_Qmax_WIDTH-1:0] nexts;





    reg [ADDR_Q_WIDTH-1:0] addrr_q;  
    reg [ADDR_Q_WIDTH-1:0] addrw_q;


    reg rflag_q;
    reg wflag_q;
    reg [DATA_WIDTH-1:0] data_in_q;
    wire [DATA_WIDTH-1:0] data_out_q;


    reg [ADDR_Qmax_WIDTH-1:0] addrr_qmax;
    reg [ADDR_Qmax_WIDTH-1:0] addrw_qmax;
    reg rflag_qmax;
    reg wflag_qmax;
    reg [DATA_WIDTH-1:0] data_in_qmax;
    wire [DATA_WIDTH-1:0] data_out_qmax;


    reg [ADDR_Q_WIDTH-1:0] addr_r;
    reg rflag_r;
    wire [DATA_WIDTH-1:0] data_out_r;
    localparam sf = 2.0**-4.0;

    always @(posedge clk) begin

        if (rst) begin
            s<= {16{1'b0}};
            current_s<={16{1'b0}};
            nexts<={16{1'b0}};
            alpha<=32'b00111111010011001100110011001101;
            gamma<=32'b00111111010011001100110011001101;

        end
 



        ag<=32'b01000111101011100001011;

        oneminusa<=32'b10011001100110011001100;
        

        sx<=s[15:8];sy<=s[7:0]; 
        if (sx=={8{1'b0}} && (action==3'b000)||(action==3'b001)||(action==3'b111)) begin
            nexts<=s;
        end
        else if (sy=={8{1'b0}} && (action==3'b001)||(action==3'b010)||(action==3'b011)) begin
            nexts<=s;      
        end
        else if (sx=={8{1'b1}} &&(action==3'b011)||(action==3'b100)||(action==3'b101)) begin
            nexts<=s;      
        end
        else if (sy=={8{1'b1}} && (action==3'b101)||(action==3'b110)||(action==3'b111)) begin
            nexts<=s;     
        end
        else begin
            case (action)
                3'b000: nexts<=s-16'b0000_0001_0000_0000;
                3'b001: nexts<=s-16'b0000_0001_0000_0001;
                3'b010: nexts<=s-16'b0000_0000_0000_0001;
                3'b011: nexts<=s-16'b0000_0000_0000_0001+16'b0000_0001_0000_0000;
                3'b100: nexts<=s+16'b0000_0001_0000_0000;
                3'b101: nexts<=s+16'b0000_0001_0000_0001;
                3'b110: nexts<=s+16'b0000_0000_0000_0001;
                3'b111: nexts<=s+16'b0000_0000_0000_0001-16'b0000_0001_0000_0000;

            endcase

        end
        

        addrr_q<={s,action}; 
        addr_r<={s,action};
        addrr_qmax<=nexts;



        

        current_s<=s;
        current_s1<=current_s;
        current_a<=action;
        current_a1<=current_a;
        s<=nexts;  
    end   
    
    
    

    always @(posedge clk) begin


        rflag_q<=1;
        q<=data_out_q;
        q1<=q;
        
        rflag_r<=1;
        r<=data_out_r;
        r1<=r;



        
        rflag_qmax<=1;
        qmax<=data_out_qmax;



        
        current_s2<=current_s1;
        current_a2<=current_a1;
        
    end
    


    
    wire [31:0] sum_part1;
    wire [31:0] sum_part2;
    wire [31:0] sum_part12;
    
    wire [31:0] sum_part3;
    reg [31:0] sum_part3a;
    
    
    wire [31:0] sum_part123;
    



    always@(posedge clk)
    begin







        sum_part3a<=sum_part3;


        
        current_s3<=current_s2;
        current_a3<=current_a2;
        current_s4<=current_s3;
        current_a4<=current_a3;

    end   



    always @(posedge clk) begin


        if (sum>q)begin
            wflag_qmax<=1;
            addrw_qmax<=current_s3;
            data_in_qmax<=sum;


        end

        wflag_q<=1;
        addrw_q<={current_s3,current_a3}; 
        data_in_q<=sum;







    end
        
    qtable qt0(
        .i_clk(clk),
        .i_rst(rst),
        .i_addr_r(addrr_q), 
        .i_addr_w(addrw_q),
        .i_read_en(rflag_q), 
        .i_write_en(wflag_q),
        .i_data(data_in_q),
        .o_data(data_out_q)); 

    qmaxtable qmaxt0(
        .i_clk(clk),
        .i_rst(rst),
        .i_addr_r(addrr_qmax), 
        .i_addr_w(addrw_qmax), 
        .i_read_en(rflag_qmax),
        .i_write_en(wflag_qmax),
        .i_data(data_in_qmax),
        .o_data(data_out_qmax)); 

    rtable rt0(
        .i_clk(clk),
        .i_addr(addr_r), 
        .i_read(rflag_r), 
        .o_data(data_out_r));
        
    floating_point_0 sum1 (
      .aclk(clk),
      .s_axis_a_tvalid(1'b1),
      .s_axis_a_tdata(alpha),
      .s_axis_b_tvalid(1'b1),
      .s_axis_b_tdata(r1),
      .m_axis_result_tvalid(result_tvalid),
      .m_axis_result_tdata(sum_part1)
    );
    
    floating_point_0 sum2 (
      .aclk(clk),
      .s_axis_a_tvalid(1'b1),
      .s_axis_a_tdata(oneminusa),
      .s_axis_b_tvalid(1'b1),
      .s_axis_b_tdata(q1),
      .m_axis_result_tvalid(result_tvalid2),
      .m_axis_result_tdata(sum_part2)
    );    
    
    floating_point_0 sum3 (
      .aclk(clk),
      .s_axis_a_tvalid(1'b1),
      .s_axis_a_tdata(ag),
      .s_axis_b_tvalid(1'b1),
      .s_axis_b_tdata(qmax),
      .m_axis_result_tvalid(result_tvalid3),
      .m_axis_result_tdata(sum_part3 )
    );
    
     floating_point_1 sum12 (
     .aclk(clk),
      .s_axis_a_tvalid(1'b1),
      .s_axis_a_tdata(sum_part1),
      .s_axis_b_tvalid(1'b1),
      .s_axis_b_tdata(sum_part2),
      .m_axis_result_tvalid(result_tvalid12),
      .m_axis_result_tdata(sum_part12)
    );

     floating_point_1 sum23 (
     .aclk(clk),
      .s_axis_a_tvalid(1'b1),
      .s_axis_a_tdata(sum_part12),
      .s_axis_b_tvalid(1'b1),
      .s_axis_b_tdata(sum_part3a),
      .m_axis_result_tvalid(result_tvalid123),
      .m_axis_result_tdata(sum)
    );

endmodule