data/full_repos/permissive/118895292/peripheral/keyboard/key_break_decoder.v
data/verilator_xmls/5e94193a-f32a-4462-b984-ff7b83de0372.xml
module key_break_decoder(
	global_clk,
	key_data_in,
	key_changed,
	key_out,
	key_break_out,
	key_changed_out);
	
input global_clk;
input [7:0] key_data_in;
input key_changed;
output reg [15:0] key_out = 0;
output reg key_break_out;
output reg key_changed_out;

reg [1:0] current_state = 0;
reg extended_seen = 0;

always @(key_changed)
begin
	if (key_changed)
	begin
		case (current_state)
		0: begin
			if (key_data_in == 8'he0)
			begin
				current_state <= 1;
				key_out[15:8] <= key_data_in;
				key_break_out <= 0;
			end
			else if (key_data_in == 8'hf0)
			begin
				key_out[15:8] <= 0;
				key_break_out <= 1;
				current_state <= 2;
			end
			else
			begin
				key_out <= {8'h00, key_data_in};
				key_changed_out <= 1;
				key_break_out <= 0;
				current_state <= 3;
			end
		end
		1: begin
			if (key_data_in == 8'hf0)
			begin
				key_break_out <= 1;
				current_state <= 2;
			end
			else
			begin
				key_out[7:0] <= key_data_in;
				key_changed_out <= 1;
				current_state <= 3;
			end
		end
		2: begin
			key_out[7:0] <= key_data_in;
			key_changed_out <= 1;
			current_state <= 3;
		end
		default: begin

			current_state <= 0;
		end
		endcase
	end
	else if (~key_changed && current_state == 3)
	begin


		key_changed_out <= 0;
		current_state <= 0;
	end
end

endmodule
module key_break_decoder(
	global_clk,
	key_data_in,
	key_changed,
	key_out,
	key_break_out,
	key_changed_out);

	
input global_clk;
input [7:0] key_data_in;
input key_changed;
output reg [15:0] key_out = 0;
output reg key_break_out;
output reg key_changed_out;

reg [1:0] current_state = 0;
reg extended_seen = 0;

always @(key_changed)
begin
	if (key_changed)
	begin
		case (current_state)
		0: begin
			if (key_data_in == 8'he0)
			begin
				current_state <= 1;
				key_out[15:8] <= key_data_in;
				key_break_out <= 0;
			end
			else if (key_data_in == 8'hf0)
			begin
				key_out[15:8] <= 0;
				key_break_out <= 1;
				current_state <= 2;
			end
			else
			begin
				key_out <= {8'h00, key_data_in};
				key_changed_out <= 1;
				key_break_out <= 0;
				current_state <= 3;
			end
		end
		1: begin
			if (key_data_in == 8'hf0)
			begin
				key_break_out <= 1;
				current_state <= 2;
			end
			else
			begin
				key_out[7:0] <= key_data_in;
				key_changed_out <= 1;
				current_state <= 3;
			end
		end
		2: begin
			key_out[7:0] <= key_data_in;
			key_changed_out <= 1;
			current_state <= 3;
		end
		default: begin

			current_state <= 0;
		end
		endcase
	end
	else if (~key_changed && current_state == 3)
	begin


		key_changed_out <= 0;
		current_state <= 0;
	end
end

endmodule