data/full_repos/permissive/167161024/ad9958_master_tb.v
 line:62: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/167161024/ad9958_master_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n   #10   clock = ~clock;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/167161024/ad9958_master_tb.v:46: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("ad9958_master.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/167161024/ad9958_master_tb.v:47: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0, ad9958_master_tb);\n   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/167161024/ad9958_master_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n   #100 reset_n <= 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/167161024/ad9958_master_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n   #1000000\n   ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ad9958_master_tb;

   wire cs;
   wire sclk;
   wire [3:0] sdio;
   wire 	  master_reset;
   wire 	  io_update;

   reg 		  clock;
   reg 		  reset_n;

   reg [32-1:0] ftw_ch0;
   reg [32-1:0] ftw_ch1;
   reg [10-1:0] asf_ch0;
   reg [10-1:0] asf_ch1;

   ad9958_master ad9958_master_inst(

									.cs					(cs),
									.sclk				(sclk),
									.sdio				(sdio[3:0]),
									.master_reset		(master_reset),
									.io_update			(io_update),

									.clock				(clock),
									.reset_n			(reset_n),
									.ftw_ch0			(ftw_ch0[32-1:0]),
									.ftw_ch1			(ftw_ch1[32-1:0]),
									.asf_ch0			(asf_ch0[10-1:0]),
									.asf_ch1			(asf_ch1[10-1:0]));

   always begin
	  #10 	 clock = ~clock;
   end

   always @(posedge clock) begin
	  ftw_ch0 <= ftw_ch0 + 32'd500;
	  ftw_ch1 <= ftw_ch1 + 32'd500;
	  asf_ch0 <= asf_ch0 + 32'd1000;
	  asf_ch1 <= asf_ch1 + 32'd1000;
   end

   initial begin
	  $dumpfile("ad9958_master.vcd");
	  $dumpvars(0, ad9958_master_tb);

	  $display("START");
	  clock <= 0;
	  reset_n <= 0;

	  ftw_ch0 <= 0;
	  ftw_ch1 <= 0;
	  asf_ch0 <= 0;
	  asf_ch1 <= 0;
	  
	  #100 reset_n <= 1;


	  #1000000
		$display("END");
	  $finish;	  
	  
   end

endmodule
module ad9958_master_tb;


   wire cs;
   wire sclk;
   wire [3:0] sdio;
   wire 	  master_reset;
   wire 	  io_update;

   reg 		  clock;
   reg 		  reset_n;

   reg [32-1:0] ftw_ch0;
   reg [32-1:0] ftw_ch1;
   reg [10-1:0] asf_ch0;
   reg [10-1:0] asf_ch1;

   ad9958_master ad9958_master_inst(

									.cs					(cs),
									.sclk				(sclk),
									.sdio				(sdio[3:0]),
									.master_reset		(master_reset),
									.io_update			(io_update),

									.clock				(clock),
									.reset_n			(reset_n),
									.ftw_ch0			(ftw_ch0[32-1:0]),
									.ftw_ch1			(ftw_ch1[32-1:0]),
									.asf_ch0			(asf_ch0[10-1:0]),
									.asf_ch1			(asf_ch1[10-1:0]));

   always begin
	  #10 	 clock = ~clock;
   end

   always @(posedge clock) begin
	  ftw_ch0 <= ftw_ch0 + 32'd500;
	  ftw_ch1 <= ftw_ch1 + 32'd500;
	  asf_ch0 <= asf_ch0 + 32'd1000;
	  asf_ch1 <= asf_ch1 + 32'd1000;
   end

   initial begin
	  $dumpfile("ad9958_master.vcd");
	  $dumpvars(0, ad9958_master_tb);

	  $display("START");
	  clock <= 0;
	  reset_n <= 0;

	  ftw_ch0 <= 0;
	  ftw_ch1 <= 0;
	  asf_ch0 <= 0;
	  asf_ch1 <= 0;
	  
	  #100 reset_n <= 1;


	  #1000000
		$display("END");
	  $finish;	  
	  
   end

endmodule