data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/address_request_decoder_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/address_request_decoder_testbench.v:59: Unsupported: Ignoring delay on this delayed statement.\n         #120 counter <= counter + 1;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests/address_request_decoder_testbench.v:41: Cannot find file containing module: \'address_request_decoder\'\n    address_request_decoder uut(.address(address), .ale(ale), .aen(aen), .ior(ior), .iow(iow), .interrupt_req(interrupt_req), .zk4(zk4),\n    ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/address_request_decoder\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/address_request_decoder.v\n             data/full_repos/permissive/160858992/ISA_Camac_Interface/sm2201_interface_board/tests,data/full_repos/permissive/160858992/address_request_decoder.sv\n             address_request_decoder\n             address_request_decoder.v\n             address_request_decoder.sv\n             obj_dir/address_request_decoder\n             obj_dir/address_request_decoder.v\n             obj_dir/address_request_decoder.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module address_request_decoder_testbench(

);

    reg [9:0] address;
    reg ale;
    reg aen;
    reg ior;
    reg iow;
    reg interrupt_req;
    reg zk4;
    wire sel;
    wire sel1;
    wire [1:0] internal_address;
    wire interrupt_en;
    
    reg [31:0] counter;
    reg [1:0] operation;
    
    address_request_decoder uut(.address(address), .ale(ale), .aen(aen), .ior(ior), .iow(iow), .interrupt_req(interrupt_req), .zk4(zk4),
                                .sel(sel), .sel1(sel1), .internal_address(internal_address), .interrupt_en(interrupt_en));

    initial
    begin
        address <= 40;
        ale <= 0;
        aen <= 0;
        ior <= 1;
        iow <= 1;
        interrupt_req <= 0;
        zk4 <= 1;
        counter <= 0;
        operation <= 0;
    end
    
    always @*
    begin
         #120 counter <= counter + 1;

        if (counter == 10) 
        begin
            ale <= 1;
            aen <= 1;
        end
        else if (counter == 20)
        begin
            if (operation == 0)
                ior <= 0;
            else
                iow <= 0;
        end
        else if (counter == 44)
        begin
            ale <= 0;
            aen <= 0;
        end
        else if (counter == 136)
        begin
            if (operation == 0)
                ior <= 1;
            else
                iow <= 1;
        end
        else if (counter == 146)
        begin
            counter <= 10;
            operation <= operation + 1;
            if (operation == 1)
            begin
                address <= address + 1;
                operation <= 0;
            end

            if (address == 318)
            begin
                address <= 256;
            end
        end
    end

endmodule
module address_request_decoder_testbench(

);


    reg [9:0] address;
    reg ale;
    reg aen;
    reg ior;
    reg iow;
    reg interrupt_req;
    reg zk4;
    wire sel;
    wire sel1;
    wire [1:0] internal_address;
    wire interrupt_en;
    
    reg [31:0] counter;
    reg [1:0] operation;
    
    address_request_decoder uut(.address(address), .ale(ale), .aen(aen), .ior(ior), .iow(iow), .interrupt_req(interrupt_req), .zk4(zk4),
                                .sel(sel), .sel1(sel1), .internal_address(internal_address), .interrupt_en(interrupt_en));

    initial
    begin
        address <= 40;
        ale <= 0;
        aen <= 0;
        ior <= 1;
        iow <= 1;
        interrupt_req <= 0;
        zk4 <= 1;
        counter <= 0;
        operation <= 0;
    end
    
    always @*
    begin
         #120 counter <= counter + 1;

        if (counter == 10) 
        begin
            ale <= 1;
            aen <= 1;
        end
        else if (counter == 20)
        begin
            if (operation == 0)
                ior <= 0;
            else
                iow <= 0;
        end
        else if (counter == 44)
        begin
            ale <= 0;
            aen <= 0;
        end
        else if (counter == 136)
        begin
            if (operation == 0)
                ior <= 1;
            else
                iow <= 1;
        end
        else if (counter == 146)
        begin
            counter <= 10;
            operation <= operation + 1;
            if (operation == 1)
            begin
                address <= address + 1;
                operation <= 0;
            end

            if (address == 318)
            begin
                address <= 256;
            end
        end
    end

endmodule