data/full_repos/permissive/197356760/FIFO/status_module.v
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/9f96e140-17f0-47e7-8486-f45281d4e095.xml
module sts_module (input clk, rst, rd_en, wr_en,
                   output f_empty, f_full);
  
  reg [2:0] count;
  
  always @(clk) begin
    if (rst)
      count <= 0;
    else
      case ({wr_en, rd_en})
        2'b01: count <= count -1;
        2'b10: count <= count +1;
        default: count <= count;
      endcase  
  end
        
  assign  f_full = count == 3'b111 ? 1:0;
  assign  f_empty = count== 0 ? 1:0;  
endmodule
module sts_module (input clk, rst, rd_en, wr_en,
                   output f_empty, f_full);

  
  reg [2:0] count;
  
  always @(clk) begin
    if (rst)
      count <= 0;
    else
      case ({wr_en, rd_en})
        2'b01: count <= count -1;
        2'b10: count <= count +1;
        default: count <= count;
      endcase  
  end
        
  assign  f_full = count == 3'b111 ? 1:0;
  assign  f_empty = count== 0 ? 1:0;  
endmodule