data/full_repos/permissive/155085421/encoder_xx6812.v
data/verilator_xmls/66cc19d7-37a6-4ede-b3bb-176922fe3b9f.xml
module encoder_xx6812(

    input clock_3mhz,


    input counter_reset,


    input[23:0] parallel_data_in,


    output reg serial_data_out,


    output reg done,


    output reg[4:0] bit_counter
    );


reg[1:0] state;

always @(posedge clock_3mhz or posedge counter_reset)
begin
    if (counter_reset)
    begin
        bit_counter <= 23;
        state <= 0;
        done <= 0;
        serial_data_out <= 0;
    end
    else begin
        if (~done)
        begin
            case (state)
                0:
                    serial_data_out <= 1;
                1:
                    serial_data_out <= parallel_data_in[bit_counter];
                2:
                    serial_data_out <= 0;
                3:  begin
                    serial_data_out <= 0;

                    if (bit_counter > 0)
                        bit_counter <= bit_counter - 1;
                    else
                        done <= 1;
                    end
            endcase
        end
        else begin
            serial_data_out <= 0;
        end
        state <= state + 1;
    end
end

endmodule
module encoder_xx6812(

    input clock_3mhz,


    input counter_reset,


    input[23:0] parallel_data_in,


    output reg serial_data_out,


    output reg done,


    output reg[4:0] bit_counter
    );



reg[1:0] state;

always @(posedge clock_3mhz or posedge counter_reset)
begin
    if (counter_reset)
    begin
        bit_counter <= 23;
        state <= 0;
        done <= 0;
        serial_data_out <= 0;
    end
    else begin
        if (~done)
        begin
            case (state)
                0:
                    serial_data_out <= 1;
                1:
                    serial_data_out <= parallel_data_in[bit_counter];
                2:
                    serial_data_out <= 0;
                3:  begin
                    serial_data_out <= 0;

                    if (bit_counter > 0)
                        bit_counter <= bit_counter - 1;
                    else
                        done <= 1;
                    end
            endcase
        end
        else begin
            serial_data_out <= 0;
        end
        state <= state + 1;
    end
end

endmodule