data/full_repos/permissive/21702465/source/system.v
 line:81: before: "("
1: b"%Error: data/full_repos/permissive/21702465/source/system.v:82: syntax error, unexpected '(', expecting IDENTIFIER\n    .clk_1(clk_1),  \n    ^\n%Error: Exiting due to 1 error(s)\n"
module system #(
	parameter INMEM_USER_BYTE_WIDTH = 1,
	parameter OUTMEM_USER_BYTE_WIDTH = 1,

	parameter INMEM_USER_ADDRESS_WIDTH = 17,
	parameter OUTMEM_USER_ADDRESS_WIDTH = 13,

	parameter INMEM_USER_REGISTER = 1,

	parameter MAC_ADDRESS = 48'hAAAAAAAAAAAA
)(	
	input		wire			CLK_200N,
	input		wire			CLK_200P,
	input		wire			RESET,
														

	output	wire	[7:0]	GMII_TXD_0,
	output	wire			GMII_TX_EN_0,
	output	wire			GMII_TX_ER_0,
	output	wire			GMII_GTX_CLK_0,
	input    wire	[7:0]	GMII_RXD_0,
	input		wire			GMII_RX_DV_0,
	input		wire			GMII_RX_ER_0,
	input		wire			GMII_RX_CLK_0,
	output	wire			GMII_RESET_B,


	input		wire				sysACE_CLK1,
	output 	wire	[6:0]		sysACE_MPADD,
	inout 	wire	[15:0]	sysACE_MPDATA,
	output	wire				sysACE_MPCE,
	output	wire				sysACE_MPWE,
	output	wire				sysACE_MPOE,

	output	wire	[12:0]		LED,

	input wire RST

);



wire clk_1, clk_2, clk_RNG, sysACE_CLK;
CLOCK_TRNG CLOCK_TRNG1(
    .CLK_IN1(sysACE_CLK1),
    .CLK_OUT1(clk_1),
    .CLK_OUT2(clk_2),
    .CLK_OUT3(clk_RNG),
    .CLK_OUT4(sysACE_CLK));
	 

wire wea;	 
wire [12:0] addra, raddr;
wire [12:0] waddr;
wire [7:0] dina, douta;
assign addra = wea? waddr : raddr;
wire mem_clk;

BUFGMUX_CTRL MEMCLK (
.O(mem_clk),
.I0(clk_user_interface),
.I1(clk_1),
.S(wea)
);

RMEM rmem1 (
  .clka(mem_clk),
  .wea(wea),
  .addra(addra),
  .dina(dina),
  .douta(douta)
);

parameter N_CB = 64;
wire [7:0] test_result;
testPUF #(N_CB)(
    .clk_1(clk_1),
    .clk_2(clk_2),
    .clk_RNG(clk_RNG),
	.rst(RST),
    .mem_we(wea),
    .mem_waddr(waddr),
    .mem_din(dina),
    .test_result(test_result)
    );

assign LED[7:0] = test_result;	 
assign LED[8] = ~wea;	
assign LED[12:9] = 0;








	wire hard_reset_high;
		




	IBUF reset_ibuf (.I(RESET), .O(hard_reset_high));







	wire clk_200;
	wire clk_125_eth_i;
	wire clk_125_eth;
	wire pllFB;
	wire pllLock;


	wire clk_user_interface_i;
	wire clk_user_interface;
	
	IBUFGDS bufCLK_DS ( .I(CLK_200P), .IB(CLK_200N), .O(clk_200) );

	PLL_BASE #(
		.COMPENSATION("SYSTEM_SYNCHRONOUS"),
		.BANDWIDTH("OPTIMIZED"),

		.CLKFBOUT_MULT(5),
		.DIVCLK_DIVIDE(1),
		.CLKFBOUT_PHASE(0.0),
		.REF_JITTER(0.100),
		.CLKIN_PERIOD(5.0),

		.CLKOUT0_DIVIDE(8),
		.CLKOUT0_PHASE(0.0),
		.CLKOUT0_DUTY_CYCLE(0.5),





		.CLKOUT1_DIVIDE(6),
		.CLKOUT1_PHASE(0.0),
		.CLKOUT1_DUTY_CYCLE(0.5)
	) clkBPLL (
		.CLKOUT0(clk_125_eth_i),


		.CLKOUT1(clk_user_interface_i),					
		.CLKFBOUT(pllFB),
		.CLKIN(clk_200),
		.CLKFBIN(pllFB),
		.LOCKED(pllLock),

		.RST(hard_reset_high)
	);



	BUFG bufCLK_125 (.O(clk_125_eth), .I(clk_125_eth_i));
	BUFG bufCLK_user (.O(clk_user_interface), .I(clk_user_interface_i));
	





	wire userLogicReset;
	

	wire userRunValue;
	wire userRunClear;
	

	wire register32CmdReq;
	wire register32CmdAck;
	wire [31:0] register32WriteData;
	wire [7:0] register32Address;
	wire register32WriteEn;
	wire register32ReadDataValid;
	wire [31:0] register32ReadData;
									

	wire inputMemoryReadReq;
	wire inputMemoryReadAck;
	wire [(INMEM_USER_ADDRESS_WIDTH - 1):0] 		inputMemoryReadAdd;
	wire inputMemoryReadDataValid;
	wire [((INMEM_USER_BYTE_WIDTH * 8) - 1):0] 	inputMemoryReadData;


	wire outputMemoryWriteReq;
	wire outputMemoryWriteAck;
	wire [(OUTMEM_USER_ADDRESS_WIDTH - 1):0] 		outputMemoryWriteAdd;
	wire [((OUTMEM_USER_BYTE_WIDTH * 8) - 1):0]	outputMemoryWriteData;
	wire [(OUTMEM_USER_BYTE_WIDTH - 1):0]			outputMemoryWriteByteMask;

	ethernet2BlockMem #(

		.INMEM_USER_BYTE_WIDTH(INMEM_USER_BYTE_WIDTH),
		.OUTMEM_USER_BYTE_WIDTH(OUTMEM_USER_BYTE_WIDTH),
		.INMEM_USER_ADDRESS_WIDTH(INMEM_USER_ADDRESS_WIDTH),
		.OUTMEM_USER_ADDRESS_WIDTH(OUTMEM_USER_ADDRESS_WIDTH),
		.INMEM_USER_REGISTER(INMEM_USER_REGISTER),
		.MAC_ADDRESS(MAC_ADDRESS)
	) E2M(
		.refClock(clk_200),
		.clockLock(pllLock),
		.hardResetLow(~hard_reset_high),

		.ethClock(clk_125_eth),
		

		.GMII_TXD(GMII_TXD_0),
		.GMII_TX_EN(GMII_TX_EN_0),
		.GMII_TX_ER(GMII_TX_ER_0),
		.GMII_GTX_CLK(GMII_GTX_CLK_0),
		.GMII_RXD(GMII_RXD_0),
		.GMII_RX_DV(GMII_RX_DV_0),
		.GMII_RX_ER(GMII_RX_ER_0),
		.GMII_RX_CLK(GMII_RX_CLK_0),
		.GMII_RESET_B(GMII_RESET_B),


		.sysACE_CLK(sysACE_CLK),
		.sysACE_MPADD(sysACE_MPADD),
		.sysACE_MPDATA(sysACE_MPDATA),
		.sysACE_MPCE(sysACE_MPCE),
		.sysACE_MPWE(sysACE_MPWE),
		.sysACE_MPOE(sysACE_MPOE),




		.userInterfaceClk(clk_user_interface),
		.userLogicReset(userLogicReset),


		.userRunValue(userRunValue),
		.userRunClear(userRunClear),
		

		.register32CmdReq(register32CmdReq),
		.register32CmdAck(register32CmdAck),
		.register32WriteData(register32WriteData),
		.register32Address(register32Address),
		.register32WriteEn(register32WriteEn),
		.register32ReadDataValid(register32ReadDataValid),
		.register32ReadData(register32ReadData),
		

		.inputMemoryReadReq(inputMemoryReadReq),
		.inputMemoryReadAck(inputMemoryReadAck),
		.inputMemoryReadAdd(inputMemoryReadAdd),
		.inputMemoryReadDataValid(inputMemoryReadDataValid),
		.inputMemoryReadData(inputMemoryReadData),
		

		.outputMemoryWriteReq(outputMemoryWriteReq),
		.outputMemoryWriteAck(outputMemoryWriteAck),
		.outputMemoryWriteAdd(outputMemoryWriteAdd),
		.outputMemoryWriteData(outputMemoryWriteData),
		.outputMemoryWriteByteMask(outputMemoryWriteByteMask)
	);






	simpleTestModuleOne #(

		.INMEM_BYTE_WIDTH(INMEM_USER_BYTE_WIDTH),
		.OUTMEM_BYTE_WIDTH(OUTMEM_USER_BYTE_WIDTH),
		.INMEM_ADDRESS_WIDTH(INMEM_USER_ADDRESS_WIDTH),
		.OUTMEM_ADDRESS_WIDTH(OUTMEM_USER_ADDRESS_WIDTH)
	) tm(										
      .clk(clk_user_interface),

      .reset(userLogicReset),
		
		.userRunValue(userRunValue),
		.userRunClear(userRunClear),

		

		.register32CmdReq(register32CmdReq),
		.register32CmdAck(register32CmdAck),
		.register32WriteData(register32WriteData),
		.register32Address(register32Address),
		.register32WriteEn(register32WriteEn),
		.register32ReadDataValid(register32ReadDataValid),
		.register32ReadData(register32ReadData),
		

		.inputMemoryReadReq(inputMemoryReadReq),
		.inputMemoryReadAck(inputMemoryReadAck),
		.inputMemoryReadAdd(inputMemoryReadAdd),
		.inputMemoryReadDataValid(inputMemoryReadDataValid),
		.inputMemoryReadData(inputMemoryReadData),
		

		.outputMemoryWriteReq(outputMemoryWriteReq),
		.outputMemoryWriteAck(outputMemoryWriteAck),
		.outputMemoryWriteAdd(outputMemoryWriteAdd),
		.outputMemoryWriteData(outputMemoryWriteData),
		.outputMemoryWriteByteMask(outputMemoryWriteByteMask),
		



		.RAND(douta),
		.ADDRA(raddr)

	); 


endmodule
module system #(
	parameter INMEM_USER_BYTE_WIDTH = 1,
	parameter OUTMEM_USER_BYTE_WIDTH = 1,

	parameter INMEM_USER_ADDRESS_WIDTH = 17,
	parameter OUTMEM_USER_ADDRESS_WIDTH = 13,

	parameter INMEM_USER_REGISTER = 1,

	parameter MAC_ADDRESS = 48'hAAAAAAAAAAAA
)(	
	input		wire			CLK_200N,
	input		wire			CLK_200P,
	input		wire			RESET,
														

	output	wire	[7:0]	GMII_TXD_0,
	output	wire			GMII_TX_EN_0,
	output	wire			GMII_TX_ER_0,
	output	wire			GMII_GTX_CLK_0,
	input    wire	[7:0]	GMII_RXD_0,
	input		wire			GMII_RX_DV_0,
	input		wire			GMII_RX_ER_0,
	input		wire			GMII_RX_CLK_0,
	output	wire			GMII_RESET_B,


	input		wire				sysACE_CLK1,
	output 	wire	[6:0]		sysACE_MPADD,
	inout 	wire	[15:0]	sysACE_MPDATA,
	output	wire				sysACE_MPCE,
	output	wire				sysACE_MPWE,
	output	wire				sysACE_MPOE,

	output	wire	[12:0]		LED,

	input wire RST

);




wire clk_1, clk_2, clk_RNG, sysACE_CLK;
CLOCK_TRNG CLOCK_TRNG1(
    .CLK_IN1(sysACE_CLK1),
    .CLK_OUT1(clk_1),
    .CLK_OUT2(clk_2),
    .CLK_OUT3(clk_RNG),
    .CLK_OUT4(sysACE_CLK));
	 

wire wea;	 
wire [12:0] addra, raddr;
wire [12:0] waddr;
wire [7:0] dina, douta;
assign addra = wea? waddr : raddr;
wire mem_clk;

BUFGMUX_CTRL MEMCLK (
.O(mem_clk),
.I0(clk_user_interface),
.I1(clk_1),
.S(wea)
);

RMEM rmem1 (
  .clka(mem_clk),
  .wea(wea),
  .addra(addra),
  .dina(dina),
  .douta(douta)
);

parameter N_CB = 64;
wire [7:0] test_result;
testPUF #(N_CB)(
    .clk_1(clk_1),
    .clk_2(clk_2),
    .clk_RNG(clk_RNG),
	.rst(RST),
    .mem_we(wea),
    .mem_waddr(waddr),
    .mem_din(dina),
    .test_result(test_result)
    );

assign LED[7:0] = test_result;	 
assign LED[8] = ~wea;	
assign LED[12:9] = 0;








	wire hard_reset_high;
		




	IBUF reset_ibuf (.I(RESET), .O(hard_reset_high));







	wire clk_200;
	wire clk_125_eth_i;
	wire clk_125_eth;
	wire pllFB;
	wire pllLock;


	wire clk_user_interface_i;
	wire clk_user_interface;
	
	IBUFGDS bufCLK_DS ( .I(CLK_200P), .IB(CLK_200N), .O(clk_200) );

	PLL_BASE #(
		.COMPENSATION("SYSTEM_SYNCHRONOUS"),
		.BANDWIDTH("OPTIMIZED"),

		.CLKFBOUT_MULT(5),
		.DIVCLK_DIVIDE(1),
		.CLKFBOUT_PHASE(0.0),
		.REF_JITTER(0.100),
		.CLKIN_PERIOD(5.0),

		.CLKOUT0_DIVIDE(8),
		.CLKOUT0_PHASE(0.0),
		.CLKOUT0_DUTY_CYCLE(0.5),





		.CLKOUT1_DIVIDE(6),
		.CLKOUT1_PHASE(0.0),
		.CLKOUT1_DUTY_CYCLE(0.5)
	) clkBPLL (
		.CLKOUT0(clk_125_eth_i),


		.CLKOUT1(clk_user_interface_i),					
		.CLKFBOUT(pllFB),
		.CLKIN(clk_200),
		.CLKFBIN(pllFB),
		.LOCKED(pllLock),

		.RST(hard_reset_high)
	);



	BUFG bufCLK_125 (.O(clk_125_eth), .I(clk_125_eth_i));
	BUFG bufCLK_user (.O(clk_user_interface), .I(clk_user_interface_i));
	





	wire userLogicReset;
	

	wire userRunValue;
	wire userRunClear;
	

	wire register32CmdReq;
	wire register32CmdAck;
	wire [31:0] register32WriteData;
	wire [7:0] register32Address;
	wire register32WriteEn;
	wire register32ReadDataValid;
	wire [31:0] register32ReadData;
									

	wire inputMemoryReadReq;
	wire inputMemoryReadAck;
	wire [(INMEM_USER_ADDRESS_WIDTH - 1):0] 		inputMemoryReadAdd;
	wire inputMemoryReadDataValid;
	wire [((INMEM_USER_BYTE_WIDTH * 8) - 1):0] 	inputMemoryReadData;


	wire outputMemoryWriteReq;
	wire outputMemoryWriteAck;
	wire [(OUTMEM_USER_ADDRESS_WIDTH - 1):0] 		outputMemoryWriteAdd;
	wire [((OUTMEM_USER_BYTE_WIDTH * 8) - 1):0]	outputMemoryWriteData;
	wire [(OUTMEM_USER_BYTE_WIDTH - 1):0]			outputMemoryWriteByteMask;

	ethernet2BlockMem #(

		.INMEM_USER_BYTE_WIDTH(INMEM_USER_BYTE_WIDTH),
		.OUTMEM_USER_BYTE_WIDTH(OUTMEM_USER_BYTE_WIDTH),
		.INMEM_USER_ADDRESS_WIDTH(INMEM_USER_ADDRESS_WIDTH),
		.OUTMEM_USER_ADDRESS_WIDTH(OUTMEM_USER_ADDRESS_WIDTH),
		.INMEM_USER_REGISTER(INMEM_USER_REGISTER),
		.MAC_ADDRESS(MAC_ADDRESS)
	) E2M(
		.refClock(clk_200),
		.clockLock(pllLock),
		.hardResetLow(~hard_reset_high),

		.ethClock(clk_125_eth),
		

		.GMII_TXD(GMII_TXD_0),
		.GMII_TX_EN(GMII_TX_EN_0),
		.GMII_TX_ER(GMII_TX_ER_0),
		.GMII_GTX_CLK(GMII_GTX_CLK_0),
		.GMII_RXD(GMII_RXD_0),
		.GMII_RX_DV(GMII_RX_DV_0),
		.GMII_RX_ER(GMII_RX_ER_0),
		.GMII_RX_CLK(GMII_RX_CLK_0),
		.GMII_RESET_B(GMII_RESET_B),


		.sysACE_CLK(sysACE_CLK),
		.sysACE_MPADD(sysACE_MPADD),
		.sysACE_MPDATA(sysACE_MPDATA),
		.sysACE_MPCE(sysACE_MPCE),
		.sysACE_MPWE(sysACE_MPWE),
		.sysACE_MPOE(sysACE_MPOE),




		.userInterfaceClk(clk_user_interface),
		.userLogicReset(userLogicReset),


		.userRunValue(userRunValue),
		.userRunClear(userRunClear),
		

		.register32CmdReq(register32CmdReq),
		.register32CmdAck(register32CmdAck),
		.register32WriteData(register32WriteData),
		.register32Address(register32Address),
		.register32WriteEn(register32WriteEn),
		.register32ReadDataValid(register32ReadDataValid),
		.register32ReadData(register32ReadData),
		

		.inputMemoryReadReq(inputMemoryReadReq),
		.inputMemoryReadAck(inputMemoryReadAck),
		.inputMemoryReadAdd(inputMemoryReadAdd),
		.inputMemoryReadDataValid(inputMemoryReadDataValid),
		.inputMemoryReadData(inputMemoryReadData),
		

		.outputMemoryWriteReq(outputMemoryWriteReq),
		.outputMemoryWriteAck(outputMemoryWriteAck),
		.outputMemoryWriteAdd(outputMemoryWriteAdd),
		.outputMemoryWriteData(outputMemoryWriteData),
		.outputMemoryWriteByteMask(outputMemoryWriteByteMask)
	);






	simpleTestModuleOne #(

		.INMEM_BYTE_WIDTH(INMEM_USER_BYTE_WIDTH),
		.OUTMEM_BYTE_WIDTH(OUTMEM_USER_BYTE_WIDTH),
		.INMEM_ADDRESS_WIDTH(INMEM_USER_ADDRESS_WIDTH),
		.OUTMEM_ADDRESS_WIDTH(OUTMEM_USER_ADDRESS_WIDTH)
	) tm(										
      .clk(clk_user_interface),

      .reset(userLogicReset),
		
		.userRunValue(userRunValue),
		.userRunClear(userRunClear),

		

		.register32CmdReq(register32CmdReq),
		.register32CmdAck(register32CmdAck),
		.register32WriteData(register32WriteData),
		.register32Address(register32Address),
		.register32WriteEn(register32WriteEn),
		.register32ReadDataValid(register32ReadDataValid),
		.register32ReadData(register32ReadData),
		

		.inputMemoryReadReq(inputMemoryReadReq),
		.inputMemoryReadAck(inputMemoryReadAck),
		.inputMemoryReadAdd(inputMemoryReadAdd),
		.inputMemoryReadDataValid(inputMemoryReadDataValid),
		.inputMemoryReadData(inputMemoryReadData),
		

		.outputMemoryWriteReq(outputMemoryWriteReq),
		.outputMemoryWriteAck(outputMemoryWriteAck),
		.outputMemoryWriteAdd(outputMemoryWriteAdd),
		.outputMemoryWriteData(outputMemoryWriteData),
		.outputMemoryWriteByteMask(outputMemoryWriteByteMask),
		



		.RAND(douta),
		.ADDRA(raddr)

	); 


endmodule