data/full_repos/permissive/143278/ivltests/enum_ports.v
 line:22: before: "typedef"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/enum_ports.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/enum_ports.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/enum_ports.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module enum_ports(input wire t_var var_i, output t_var var_o, output reg is_var_rst);

initial begin
    var_o = var_presence;
end

always @(var_i)
begin
    if(var_i == var_rst)
        is_var_rst = 1'b1;
    else
        is_var_rst = 1'b0;
end
endmodule
module enum_ports(input wire t_var var_i, output t_var var_o, output reg is_var_rst);


initial begin
    var_o = var_presence;
end

always @(var_i)
begin
    if(var_i == var_rst)
        is_var_rst = 1'b1;
    else
        is_var_rst = 1'b0;
end
endmodule