data/full_repos/permissive/159312910/thales-risc-v-vivado/git/ip_repo/risc_v_CPU_1.0/src/jtag_vpi.v
 line:95: before: "wait"
1: b'%Error: data/full_repos/permissive/159312910/thales-risc-v-vivado/git/ip_repo/risc_v_CPU_1.0/src/jtag_vpi.v:95: Unsupported: wait statements\n wait(init_done)\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/159312910/thales-risc-v-vivado/git/ip_repo/risc_v_CPU_1.0/src/jtag_vpi.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #INIT_DELAY \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/159312910/thales-risc-v-vivado/git/ip_repo/risc_v_CPU_1.0/src/jtag_vpi.v:115: Unsupported or unknown PLI call: $check_for_command\n                     #CMD_DELAY $check_for_command(cmd, length, nb_bits, buffer_out);\n                                ^~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159312910/thales-risc-v-vivado/git/ip_repo/risc_v_CPU_1.0/src/jtag_vpi.v:115: Unsupported: Ignoring delay on this delayed statement.\n                     #CMD_DELAY $check_for_command(cmd, length, nb_bits, buffer_out);\n                     ^\n%Error: data/full_repos/permissive/159312910/thales-risc-v-vivado/git/ip_repo/risc_v_CPU_1.0/src/jtag_vpi.v:142: Unsupported or unknown PLI call: $send_result_to_server\n   $send_result_to_server(length, buffer_in);\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/159312910/thales-risc-v-vivado/git/ip_repo/risc_v_CPU_1.0/src/jtag_vpi.v:151: Unsupported or unknown PLI call: $send_result_to_server\n   $send_result_to_server(length, buffer_in);\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159312910/thales-risc-v-vivado/git/ip_repo/risc_v_CPU_1.0/src/jtag_vpi.v:185: Unsupported: Ignoring delay on this delayed statement.\n  #TCK_HALF_PERIOD tck <= 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159312910/thales-risc-v-vivado/git/ip_repo/risc_v_CPU_1.0/src/jtag_vpi.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #TCK_HALF_PERIOD tck <= 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159312910/thales-risc-v-vivado/git/ip_repo/risc_v_CPU_1.0/src/jtag_vpi.v:288: Unsupported: Ignoring delay on this delayed statement.\n   #TCK_HALF_PERIOD tck <= 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/159312910/thales-risc-v-vivado/git/ip_repo/risc_v_CPU_1.0/src/jtag_vpi.v:290: Unsupported: Ignoring delay on this delayed statement.\n   #TCK_HALF_PERIOD tck <= 0;\n   ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module JTAGVPI
#(	parameter DEBUG_INFO = 0,
	parameter TP = 1,
	parameter TCK_HALF_PERIOD = 2,
        parameter CMD_DELAY = 2,
        parameter INIT_DELAY = 200
)   
(
	output jtag_TMS,
	output jtag_TCK,
	output jtag_TDI,
	input  jtag_TDO_data,
        input  jtag_TDO_driven,

	input  enable,
	input  init_done);

   reg                  tms;
   reg                  tck;
   reg                  tdi;
   wire                 tdo;
   
   assign jtag_TMS = tms;
   assign jtag_TCK = tck;
   assign jtag_TDI = tdi;
   assign tdo = jtag_TDO_driven ? jtag_TDO_data : 1'bz;
      
integer		cmd;
integer		length;
integer		nb_bits;

reg [31:0] 	buffer_out [0:4095];
reg [31:0] 	buffer_in  [0:4095];

integer		flip_tms;

reg [31:0]	data_out;
reg [31:0]	data_in;

integer		debug;

initial
begin
	tck		<= #TP 1'b0;
	tdi		<= #TP 1'bz;
	tms		<= #TP 1'b0;

	data_out	<= 32'h0;
	data_in		<= 32'h0;



        #INIT_DELAY 
          
	wait(init_done)
		if($test$plusargs("jtag_vpi_enable")) main;
end

task main;
begin
	$display("JTAG debug module with VPI interface enabled\n");

	reset_tap;
	goto_run_test_idle_from_reset;

	while (1) begin




		cmd = -1;

		while (cmd == -1)
		begin
                     #CMD_DELAY $check_for_command(cmd, length, nb_bits, buffer_out);
		end


		case (cmd)

		`CMD_RESET :
		begin
			if (DEBUG_INFO)
				$display("%t ----> CMD_RESET %h\n", $time, length);
			reset_tap;
			goto_run_test_idle_from_reset;
		end

		`CMD_TMS_SEQ :
		begin
			if (DEBUG_INFO)
				$display("%t ----> CMD_TMS_SEQ\n", $time);
			do_tms_seq;
		end

		`CMD_SCAN_CHAIN :
		begin
			if (DEBUG_INFO)
				$display("%t ----> CMD_SCAN_CHAIN\n", $time);
			flip_tms = 0;
			do_scan_chain;
			$send_result_to_server(length, buffer_in);
		end

		`CMD_SCAN_CHAIN_FLIP_TMS :
		begin
			if(DEBUG_INFO)
				$display("%t ----> CMD_SCAN_CHAIN\n", $time);
			flip_tms = 1;
			do_scan_chain;
			$send_result_to_server(length, buffer_in);
		end

		`CMD_STOP_SIMU :
		begin
			if(DEBUG_INFO)
				$display("%t ----> End of simulation\n", $time);
			$finish();
		end

		default:
		begin
			$display("Somehow got to the default case in the command case statement.");
			$display("Command was: %x", cmd);
			$display("Exiting...");
			$finish();
		end

		endcase

	end
end

endtask



task gen_clk;
input [31:0] number;
integer i;

begin
	for (i = 0; i < number; i = i + 1)
	begin
		#TCK_HALF_PERIOD tck <= 1;
		#TCK_HALF_PERIOD tck <= 0;
	end
end

endtask


task reset_tap;
begin
	if (DEBUG_INFO)
		$display("(%0t) Task reset_tap", $time);
	tms <= #1 1'b1;
	gen_clk(5);
end

endtask



task goto_run_test_idle_from_reset;
begin
	if (DEBUG_INFO)
		$display("(%0t) Task goto_run_test_idle_from_reset", $time);
	tms <= #1 1'b0;
	gen_clk(1);
end

endtask


task do_tms_seq;

integer		i,j;
reg [31:0]	data;
integer		nb_bits_rem;
integer		nb_bits_in_this_byte;

begin
	if (DEBUG_INFO)
		$display("(%0t) Task do_tms_seq of %d bits (length = %d)", $time, nb_bits, length);


	nb_bits_rem = nb_bits % 8;

	for (i = 0; i < length; i = i + 1)
	begin


		nb_bits_in_this_byte = (i == (length - 1)) ? nb_bits_rem : 8;

		data = buffer_out[i];
		for (j = 0; j < nb_bits_in_this_byte; j = j + 1)
		begin
			tms <= #1 1'b0;
			if (data[j] == 1) begin
				tms <= #1 1'b1;
                        end
			gen_clk(1);
		end
	end

	tms <= #1 1'b0;
end

endtask



task do_scan_chain;

integer		_bit;
integer		nb_bits_rem;
integer		nb_bits_in_this_byte;
integer		index;

begin
	if(DEBUG_INFO)
		$display("(%0t) Task do_scan_chain of %d bits (length = %d)", $time, nb_bits, length);


	nb_bits_rem = nb_bits % 8;

	for (index = 0; index < length; index = index + 1)
	begin



		nb_bits_in_this_byte = (index == (length - 1)) ? ((nb_bits_rem == 0) ? 8 : nb_bits_rem) : 8;

		data_out = buffer_out[index];
		for (_bit = 0; _bit < nb_bits_in_this_byte; _bit = _bit + 1)
		begin
			tdi <= 1'b0;
			if (data_out[_bit] == 1'b1) begin
				tdi <= 1'b1;
			end


			if (((_bit == (nb_bits_in_this_byte - 1)) && (index == (length - 1))) && (flip_tms == 1)) begin
				tms <= 1'b1;
			end

			#TCK_HALF_PERIOD tck <= 1;
			data_in[_bit] <= tdo;
			#TCK_HALF_PERIOD tck <= 0;
		end
		buffer_in[index] = data_in;
	end

	tdi <= 1'b0;
	tms <= 1'b0;
end

endtask

endmodule
module JTAGVPI
#(	parameter DEBUG_INFO = 0,
	parameter TP = 1,
	parameter TCK_HALF_PERIOD = 2,
        parameter CMD_DELAY = 2,
        parameter INIT_DELAY = 200
)   
(
	output jtag_TMS,
	output jtag_TCK,
	output jtag_TDI,
	input  jtag_TDO_data,
        input  jtag_TDO_driven,

	input  enable,
	input  init_done);


   reg                  tms;
   reg                  tck;
   reg                  tdi;
   wire                 tdo;
   
   assign jtag_TMS = tms;
   assign jtag_TCK = tck;
   assign jtag_TDI = tdi;
   assign tdo = jtag_TDO_driven ? jtag_TDO_data : 1'bz;
      
integer		cmd;
integer		length;
integer		nb_bits;

reg [31:0] 	buffer_out [0:4095];
reg [31:0] 	buffer_in  [0:4095];

integer		flip_tms;

reg [31:0]	data_out;
reg [31:0]	data_in;

integer		debug;

initial
begin
	tck		<= #TP 1'b0;
	tdi		<= #TP 1'bz;
	tms		<= #TP 1'b0;

	data_out	<= 32'h0;
	data_in		<= 32'h0;



        #INIT_DELAY 
          
	wait(init_done)
		if($test$plusargs("jtag_vpi_enable")) main;
end

task main;
begin
	$display("JTAG debug module with VPI interface enabled\n");

	reset_tap;
	goto_run_test_idle_from_reset;

	while (1) begin




		cmd = -1;

		while (cmd == -1)
		begin
                     #CMD_DELAY $check_for_command(cmd, length, nb_bits, buffer_out);
		end


		case (cmd)

		`CMD_RESET :
		begin
			if (DEBUG_INFO)
				$display("%t ----> CMD_RESET %h\n", $time, length);
			reset_tap;
			goto_run_test_idle_from_reset;
		end

		`CMD_TMS_SEQ :
		begin
			if (DEBUG_INFO)
				$display("%t ----> CMD_TMS_SEQ\n", $time);
			do_tms_seq;
		end

		`CMD_SCAN_CHAIN :
		begin
			if (DEBUG_INFO)
				$display("%t ----> CMD_SCAN_CHAIN\n", $time);
			flip_tms = 0;
			do_scan_chain;
			$send_result_to_server(length, buffer_in);
		end

		`CMD_SCAN_CHAIN_FLIP_TMS :
		begin
			if(DEBUG_INFO)
				$display("%t ----> CMD_SCAN_CHAIN\n", $time);
			flip_tms = 1;
			do_scan_chain;
			$send_result_to_server(length, buffer_in);
		end

		`CMD_STOP_SIMU :
		begin
			if(DEBUG_INFO)
				$display("%t ----> End of simulation\n", $time);
			$finish();
		end

		default:
		begin
			$display("Somehow got to the default case in the command case statement.");
			$display("Command was: %x", cmd);
			$display("Exiting...");
			$finish();
		end

		endcase

	end
end

endtask



task gen_clk;
input [31:0] number;
integer i;

begin
	for (i = 0; i < number; i = i + 1)
	begin
		#TCK_HALF_PERIOD tck <= 1;
		#TCK_HALF_PERIOD tck <= 0;
	end
end

endtask


task reset_tap;
begin
	if (DEBUG_INFO)
		$display("(%0t) Task reset_tap", $time);
	tms <= #1 1'b1;
	gen_clk(5);
end

endtask



task goto_run_test_idle_from_reset;
begin
	if (DEBUG_INFO)
		$display("(%0t) Task goto_run_test_idle_from_reset", $time);
	tms <= #1 1'b0;
	gen_clk(1);
end

endtask


task do_tms_seq;

integer		i,j;
reg [31:0]	data;
integer		nb_bits_rem;
integer		nb_bits_in_this_byte;

begin
	if (DEBUG_INFO)
		$display("(%0t) Task do_tms_seq of %d bits (length = %d)", $time, nb_bits, length);


	nb_bits_rem = nb_bits % 8;

	for (i = 0; i < length; i = i + 1)
	begin


		nb_bits_in_this_byte = (i == (length - 1)) ? nb_bits_rem : 8;

		data = buffer_out[i];
		for (j = 0; j < nb_bits_in_this_byte; j = j + 1)
		begin
			tms <= #1 1'b0;
			if (data[j] == 1) begin
				tms <= #1 1'b1;
                        end
			gen_clk(1);
		end
	end

	tms <= #1 1'b0;
end

endtask



task do_scan_chain;

integer		_bit;
integer		nb_bits_rem;
integer		nb_bits_in_this_byte;
integer		index;

begin
	if(DEBUG_INFO)
		$display("(%0t) Task do_scan_chain of %d bits (length = %d)", $time, nb_bits, length);


	nb_bits_rem = nb_bits % 8;

	for (index = 0; index < length; index = index + 1)
	begin



		nb_bits_in_this_byte = (index == (length - 1)) ? ((nb_bits_rem == 0) ? 8 : nb_bits_rem) : 8;

		data_out = buffer_out[index];
		for (_bit = 0; _bit < nb_bits_in_this_byte; _bit = _bit + 1)
		begin
			tdi <= 1'b0;
			if (data_out[_bit] == 1'b1) begin
				tdi <= 1'b1;
			end


			if (((_bit == (nb_bits_in_this_byte - 1)) && (index == (length - 1))) && (flip_tms == 1)) begin
				tms <= 1'b1;
			end

			#TCK_HALF_PERIOD tck <= 1;
			data_in[_bit] <= tdo;
			#TCK_HALF_PERIOD tck <= 0;
		end
		buffer_in[index] = data_in;
	end

	tdi <= 1'b0;
	tms <= 1'b0;
end

endtask

endmodule