data/full_repos/permissive/135852214/Verilog/qcnot.v
 line:39: before: "data_in"
data/verilator_xmls/372a8f8e-f9f6-422d-8554-a60b3962ff0f.xml
module qcnot(
    input [4:0] in,
    output [4:0] out
    );
assign out[0] = in[0];
assign out[1] = in[1] ^ in[0];
assign out[2] = in[2] ^ in[0];
assign out[3] = in[3] ^ in[0];
assign out[4] = in[4] ^ in[0];

endmodule
module qcnot(
    input [4:0] in,
    output [4:0] out
    );

assign out[0] = in[0];
assign out[1] = in[1] ^ in[0];
assign out[2] = in[2] ^ in[0];
assign out[3] = in[3] ^ in[0];
assign out[4] = in[4] ^ in[0];

endmodule