data/full_repos/permissive/123304708/src/datapath/IF_ID.v
data/verilator_xmls/51011b7a-7e3a-4415-8b0c-682a73e0172a.xml
module if_id(
  input clk,
  input PC_IFWrite,
  input IF_flush,
  input [31:0] pc_in,
  input [31:0] din,
  output reg[31:0] pc_out,
  output reg[31:0] dout
  );

  always@(posedge clk)
  begin
    if(IF_flush)
    begin
      dout <= 0;
      pc_out <= 0;
    end
    else
    begin
     if(PC_IFWrite)
     begin
       dout <= din;
       pc_out = pc_in;
     end
   end
 end

endmodule
module if_id(
  input clk,
  input PC_IFWrite,
  input IF_flush,
  input [31:0] pc_in,
  input [31:0] din,
  output reg[31:0] pc_out,
  output reg[31:0] dout
  );


  always@(posedge clk)
  begin
    if(IF_flush)
    begin
      dout <= 0;
      pc_out <= 0;
    end
    else
    begin
     if(PC_IFWrite)
     begin
       dout <= din;
       pc_out = pc_in;
     end
   end
 end

endmodule