data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v
1: b'%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:24: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h2000\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[0] = 20\'h02000; \n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:25: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h12e4\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[1] = 20\'h012E4;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:26: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h9fb\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[2] = 20\'h009FB;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:27: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h511\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[3] = 20\'h00511;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:28: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h28b\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[4] = 20\'h0028B;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:29: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h145\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[5] = 20\'h00145;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:30: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'ha2\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[6] = 20\'h000A2;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:31: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h51\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[7] = 20\'h00051;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:32: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h28\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[8] = 20\'h00028;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:33: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h14\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[9] = 20\'h00014;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:34: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'ha\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[10] = 20\'h0000A;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:35: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h5\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[11] = 20\'h00005;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:36: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h2\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[12] = 20\'h00002;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:37: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h1\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[13] = 20\'h00001;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:38: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h0\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[14] = 20\'h00000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/118406297/rotation/assign_initial_rotation.v:39: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'20\'h0\' generates 20 bits.\n                                                                                          : ... In instance stages_rotation\n    assign atan[15] = 20\'h00000;\n                    ^\n%Error: Exiting due to 16 warning(s)\n'
module stages_rotation #(parameter data_width=16,angle_width=16,cordic_steps=16,stage_number=1)(
    input clk,
    input nreset,
    input enable,
    
    input signed [data_width-1:0] x_vec_in,
    input signed [data_width-1:0] y_vec_in,
    
    input signed [angle_width-1:0]angle_in,
    input signed [angle_width-1:0]target_angle,
    
    output signed [data_width-1:0] x_vec_out,
    output signed [data_width-1:0] y_vec_out,
    
    output reg signed [angle_width-1:0]angle_out,
    output reg signed [angle_width-1:0]target_angle_out,
    output reg done
    );
    
    wire signed [angle_width-1:0] atan [cordic_steps-1:0];
    
    assign atan[0] = 20'h02000;
    assign atan[1] = 20'h012E4;
    assign atan[2] = 20'h009FB;
    assign atan[3] = 20'h00511;
    assign atan[4] = 20'h0028B;
    assign atan[5] = 20'h00145;
    assign atan[6] = 20'h000A2;
    assign atan[7] = 20'h00051;
    assign atan[8] = 20'h00028;
    assign atan[9] = 20'h00014;
    assign atan[10] = 20'h0000A;
    assign atan[11] = 20'h00005;
    assign atan[12] = 20'h00002;
    assign atan[13] = 20'h00001;
    assign atan[14] = 20'h00000;
    assign atan[15] = 20'h00000;

    reg signed [data_width-1:0]x_temp_out,y_temp_out;
    
    assign x_vec_out = x_temp_out;
    assign y_vec_out = y_temp_out;
    
    always @(posedge clk) begin
        if (~nreset) begin
            x_temp_out <= $signed({data_width{1'b0}});
            y_temp_out <= $signed({data_width{1'b0}});
				angle_out <= 0;
            done <= 1'b0;
        end
        else begin
            if (enable) begin
                if ($signed(target_angle) <= $signed(angle_in)) begin
                    x_temp_out <= x_vec_in + (y_vec_in>>>(stage_number-1));
                    y_temp_out <= y_vec_in - (x_vec_in>>>(stage_number-1));
                    angle_out <= angle_in - atan[stage_number-1];
                end
                else begin
                    x_temp_out <= x_vec_in - (y_vec_in>>>(stage_number-1));
                    y_temp_out <= y_vec_in + (x_vec_in>>>(stage_number-1));
                    angle_out <= angle_in + atan[(stage_number-1)];
                end
                target_angle_out <= target_angle;
                done <= 1'b1;
            end
            else begin
                x_temp_out <= $signed({data_width{1'b0}});
                y_temp_out <= $signed({data_width{1'b0}});
					 angle_out <= 0;
                done <= 1'b0;
            end
        end
    end
    
endmodule
module stages_rotation #(parameter data_width=16,angle_width=16,cordic_steps=16,stage_number=1)(
    input clk,
    input nreset,
    input enable,
    
    input signed [data_width-1:0] x_vec_in,
    input signed [data_width-1:0] y_vec_in,
    
    input signed [angle_width-1:0]angle_in,
    input signed [angle_width-1:0]target_angle,
    
    output signed [data_width-1:0] x_vec_out,
    output signed [data_width-1:0] y_vec_out,
    
    output reg signed [angle_width-1:0]angle_out,
    output reg signed [angle_width-1:0]target_angle_out,
    output reg done
    );

    
    wire signed [angle_width-1:0] atan [cordic_steps-1:0];
    
    assign atan[0] = 20'h02000;
    assign atan[1] = 20'h012E4;
    assign atan[2] = 20'h009FB;
    assign atan[3] = 20'h00511;
    assign atan[4] = 20'h0028B;
    assign atan[5] = 20'h00145;
    assign atan[6] = 20'h000A2;
    assign atan[7] = 20'h00051;
    assign atan[8] = 20'h00028;
    assign atan[9] = 20'h00014;
    assign atan[10] = 20'h0000A;
    assign atan[11] = 20'h00005;
    assign atan[12] = 20'h00002;
    assign atan[13] = 20'h00001;
    assign atan[14] = 20'h00000;
    assign atan[15] = 20'h00000;

    reg signed [data_width-1:0]x_temp_out,y_temp_out;
    
    assign x_vec_out = x_temp_out;
    assign y_vec_out = y_temp_out;
    
    always @(posedge clk) begin
        if (~nreset) begin
            x_temp_out <= $signed({data_width{1'b0}});
            y_temp_out <= $signed({data_width{1'b0}});
				angle_out <= 0;
            done <= 1'b0;
        end
        else begin
            if (enable) begin
                if ($signed(target_angle) <= $signed(angle_in)) begin
                    x_temp_out <= x_vec_in + (y_vec_in>>>(stage_number-1));
                    y_temp_out <= y_vec_in - (x_vec_in>>>(stage_number-1));
                    angle_out <= angle_in - atan[stage_number-1];
                end
                else begin
                    x_temp_out <= x_vec_in - (y_vec_in>>>(stage_number-1));
                    y_temp_out <= y_vec_in + (x_vec_in>>>(stage_number-1));
                    angle_out <= angle_in + atan[(stage_number-1)];
                end
                target_angle_out <= target_angle;
                done <= 1'b1;
            end
            else begin
                x_temp_out <= $signed({data_width{1'b0}});
                y_temp_out <= $signed({data_width{1'b0}});
					 angle_out <= 0;
                done <= 1'b0;
            end
        end
    end
    
endmodule