data/full_repos/permissive/213397499/verilog/barrel_shifter.v
1: b"%Error: data/full_repos/permissive/213397499/verilog/barrel_shifter.v:34: Cannot find file containing module: 'mux2_1'\n    mux2_1 u_data_reverse_in (up_dat[i], up_dat[w-1-i], ctrl[4], reverse_in[i]);\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/213397499/verilog,data/full_repos/permissive/213397499/mux2_1\n             data/full_repos/permissive/213397499/verilog,data/full_repos/permissive/213397499/mux2_1.v\n             data/full_repos/permissive/213397499/verilog,data/full_repos/permissive/213397499/mux2_1.sv\n             mux2_1\n             mux2_1.v\n             mux2_1.sv\n             obj_dir/mux2_1\n             obj_dir/mux2_1.v\n             obj_dir/mux2_1.sv\n%Error: data/full_repos/permissive/213397499/verilog/barrel_shifter.v:45: Cannot find file containing module: 'mux2_1'\n    mux2_1 u_mux_shift8_bits (reverse_in[i], reverse_in[i+8], ctrl[3], shift_8[i]);\n    ^~~~~~\n%Error: data/full_repos/permissive/213397499/verilog/barrel_shifter.v:52: Cannot find file containing module: 'mux2_1'\n    mux2_1 u_mux_shift8_zero (reverse_in[i], 1'b0, ctrl[3], shift_8[i]);\n    ^~~~~~\n%Error: data/full_repos/permissive/213397499/verilog/barrel_shifter.v:63: Cannot find file containing module: 'mux2_1'\n    mux2_1 u_mux_shift4_bits (shift_8[i], up_dat[i+4], ctrl[2], shift_4[i]);\n    ^~~~~~\n%Error: data/full_repos/permissive/213397499/verilog/barrel_shifter.v:70: Cannot find file containing module: 'mux2_1'\n    mux2_1 u_mux_shift4_zero (shift_8[i], 1'b0, ctrl[2], shift_4[i]);\n    ^~~~~~\n%Error: data/full_repos/permissive/213397499/verilog/barrel_shifter.v:81: Cannot find file containing module: 'mux2_1'\n    mux2_1 u_mux_shift2_bits (shift_4[i], up_dat[i+2], ctrl[1], shift_2[i]);\n    ^~~~~~\n%Error: data/full_repos/permissive/213397499/verilog/barrel_shifter.v:88: Cannot find file containing module: 'mux2_1'\n    mux2_1 u_mux_shift2_zero (shift_4[i], 1'b0, ctrl[1], shift_2[i]);\n    ^~~~~~\n%Error: data/full_repos/permissive/213397499/verilog/barrel_shifter.v:100: Cannot find file containing module: 'mux2_1'\n    mux2_1 u_mux_shift1_bits (shift_2[i], up_dat[i+1], ctrl[0], shift_1[i]);\n    ^~~~~~\n%Error: data/full_repos/permissive/213397499/verilog/barrel_shifter.v:107: Cannot find file containing module: 'mux2_1'\n    mux2_1 u_mux_shift1_zero (shift_2[i], 1'b0, ctrl[0], shift_1[i]);\n    ^~~~~~\n%Error: data/full_repos/permissive/213397499/verilog/barrel_shifter.v:117: Cannot find file containing module: 'mux2_1'\n    mux2_1 u_data_reverse_out (shift_1[i], shift_1[w-1-i], ctrl[4], reverse_out[i]);\n    ^~~~~~\n%Error: Exiting due to 10 error(s)\n"
module barrel_shifter
# (
  parameter w = 32
)
(
  input           clk,
  input           rst_n,
  input  [w-1:0]  up_dat,
  output [w-1:0]  dn_dat,
  input  [4:0]    ctrl
);

genvar i;

wire  [w-1:0] reverse_in;
wire  [w-1:0] shift_8;
wire  [w-1:0] shift_4;
wire  [w-1:0] shift_2;
wire  [w-1:0] shift_1;
wire  [w-1:0] reverse_out;





generate
for(i=0; i<w; i=i+1)
begin : DATA_REVERSE_IN
    mux2_1 u_data_reverse_in (up_dat[i], up_dat[w-1-i], ctrl[4], reverse_in[i]);
end
endgenerate





generate
for(i=0; i<w-8; i=i+1)
begin : SHIFT8_BITS
    mux2_1 u_mux_shift8_bits (reverse_in[i], reverse_in[i+8], ctrl[3], shift_8[i]);
end
endgenerate

generate
for(i=w-8; i<w; i=i+1)
begin : SHIFT8_ZERO
    mux2_1 u_mux_shift8_zero (reverse_in[i], 1'b0, ctrl[3], shift_8[i]);
end
endgenerate





generate
for(i=0; i<w-4; i=i+1)
begin : SHIFT4_BITS
    mux2_1 u_mux_shift4_bits (shift_8[i], up_dat[i+4], ctrl[2], shift_4[i]);
end
endgenerate

generate
for(i=w-4; i<w; i=i+1)
begin : SHIFT4_ZERO
    mux2_1 u_mux_shift4_zero (shift_8[i], 1'b0, ctrl[2], shift_4[i]);
end
endgenerate





generate
for(i=0; i<w-2; i=i+1)
begin : SHIFT2_BITS
    mux2_1 u_mux_shift2_bits (shift_4[i], up_dat[i+2], ctrl[1], shift_2[i]);
end
endgenerate

generate
for(i=w-2; i<w; i=i+1)
begin : SHIFT2_ZERO
    mux2_1 u_mux_shift2_zero (shift_4[i], 1'b0, ctrl[1], shift_2[i]);
end
endgenerate






generate
for(i=0; i<w-1; i=i+1)
begin : SHIFT1_BITS
    mux2_1 u_mux_shift1_bits (shift_2[i], up_dat[i+1], ctrl[0], shift_1[i]);
end
endgenerate

generate
for(i=w-1; i<w; i=i+1)
begin : SHIFT1_ZERO
    mux2_1 u_mux_shift1_zero (shift_2[i], 1'b0, ctrl[0], shift_1[i]);
end
endgenerate




generate
for(i=0; i<w; i=i+1)
begin : DATA_REVERSE_OUT
    mux2_1 u_data_reverse_out (shift_1[i], shift_1[w-1-i], ctrl[4], reverse_out[i]);
end
endgenerate

assign dn_dat = reverse_out;

endmodule
module barrel_shifter
# (
  parameter w = 32
)
(
  input           clk,
  input           rst_n,
  input  [w-1:0]  up_dat,
  output [w-1:0]  dn_dat,
  input  [4:0]    ctrl
);


genvar i;

wire  [w-1:0] reverse_in;
wire  [w-1:0] shift_8;
wire  [w-1:0] shift_4;
wire  [w-1:0] shift_2;
wire  [w-1:0] shift_1;
wire  [w-1:0] reverse_out;





generate
for(i=0; i<w; i=i+1)
begin : DATA_REVERSE_IN
    mux2_1 u_data_reverse_in (up_dat[i], up_dat[w-1-i], ctrl[4], reverse_in[i]);
end
endgenerate





generate
for(i=0; i<w-8; i=i+1)
begin : SHIFT8_BITS
    mux2_1 u_mux_shift8_bits (reverse_in[i], reverse_in[i+8], ctrl[3], shift_8[i]);
end
endgenerate

generate
for(i=w-8; i<w; i=i+1)
begin : SHIFT8_ZERO
    mux2_1 u_mux_shift8_zero (reverse_in[i], 1'b0, ctrl[3], shift_8[i]);
end
endgenerate





generate
for(i=0; i<w-4; i=i+1)
begin : SHIFT4_BITS
    mux2_1 u_mux_shift4_bits (shift_8[i], up_dat[i+4], ctrl[2], shift_4[i]);
end
endgenerate

generate
for(i=w-4; i<w; i=i+1)
begin : SHIFT4_ZERO
    mux2_1 u_mux_shift4_zero (shift_8[i], 1'b0, ctrl[2], shift_4[i]);
end
endgenerate





generate
for(i=0; i<w-2; i=i+1)
begin : SHIFT2_BITS
    mux2_1 u_mux_shift2_bits (shift_4[i], up_dat[i+2], ctrl[1], shift_2[i]);
end
endgenerate

generate
for(i=w-2; i<w; i=i+1)
begin : SHIFT2_ZERO
    mux2_1 u_mux_shift2_zero (shift_4[i], 1'b0, ctrl[1], shift_2[i]);
end
endgenerate






generate
for(i=0; i<w-1; i=i+1)
begin : SHIFT1_BITS
    mux2_1 u_mux_shift1_bits (shift_2[i], up_dat[i+1], ctrl[0], shift_1[i]);
end
endgenerate

generate
for(i=w-1; i<w; i=i+1)
begin : SHIFT1_ZERO
    mux2_1 u_mux_shift1_zero (shift_2[i], 1'b0, ctrl[0], shift_1[i]);
end
endgenerate




generate
for(i=0; i<w; i=i+1)
begin : DATA_REVERSE_OUT
    mux2_1 u_data_reverse_out (shift_1[i], shift_1[w-1-i], ctrl[4], reverse_out[i]);
end
endgenerate

assign dn_dat = reverse_out;

endmodule