data/full_repos/permissive/121410129/Step1/Gray_4bits_RTL.v
data/verilator_xmls/164dcd72-20b5-44db-8d8f-b97270c6a711.xml
module gray_4bits (clk, reset, gray_out);
input wire clk, reset;
output wire [3:0]gray_out;

reg [3:0]state;

assign gray_out = state;

always @(posedge clk or posedge reset)
begin
	if (reset == 1'b1) begin
		state <= 4'b0000;
	end
	else begin
		case (gray_out)
			4'b0000: state <= 4'b0001;
			4'b0001: state <= 4'b0011;
			4'b0011: state <= 4'b0010;
			4'b0010: state <= 4'b0110;
			4'b0110: state <= 4'b0111;
			4'b0111: state <= 4'b0101;
			4'b0101: state <= 4'b0100;
			4'b0100: state <= 4'b1100;
			4'b1100: state <= 4'b1101;
			4'b1101: state <= 4'b1111;
			4'b1111: state <= 4'b1110;
			4'b1110: state <= 4'b1010;
			4'b1010: state <= 4'b1011;
			4'b1011: state <= 4'b1001;
			4'b1001: state <= 4'b1000;
			4'b1000: state <= 4'b0000;
			default: state <= 4'b0000;
		endcase
	end
end

endmodule
module gray_4bits (clk, reset, gray_out);

input wire clk, reset;
output wire [3:0]gray_out;

reg [3:0]state;

assign gray_out = state;

always @(posedge clk or posedge reset)
begin
	if (reset == 1'b1) begin
		state <= 4'b0000;
	end
	else begin
		case (gray_out)
			4'b0000: state <= 4'b0001;
			4'b0001: state <= 4'b0011;
			4'b0011: state <= 4'b0010;
			4'b0010: state <= 4'b0110;
			4'b0110: state <= 4'b0111;
			4'b0111: state <= 4'b0101;
			4'b0101: state <= 4'b0100;
			4'b0100: state <= 4'b1100;
			4'b1100: state <= 4'b1101;
			4'b1101: state <= 4'b1111;
			4'b1111: state <= 4'b1110;
			4'b1110: state <= 4'b1010;
			4'b1010: state <= 4'b1011;
			4'b1011: state <= 4'b1001;
			4'b1001: state <= 4'b1000;
			4'b1000: state <= 4'b0000;
			default: state <= 4'b0000;
		endcase
	end
end

endmodule