data/full_repos/permissive/20662519/ClockGenerator.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/20662519/ClockGenerator.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #0.1 clock = ~clock;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20662519/ClockGenerator.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #20 reset = 0;\n    ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ClockGenerator(
  output reg clock,
  output reg reset
);
   
  always begin


    #0.1 clock = ~clock;
    
  end
  
 initial 
  begin
    clock = 0;
    reset = 1;
    #20 reset = 0;
  end
    
endmodule
module ClockGenerator(
  output reg clock,
  output reg reset
);

   
  always begin


    #0.1 clock = ~clock;
    
  end
  
 initial 
  begin
    clock = 0;
    reset = 1;
    #20 reset = 0;
  end
    
endmodule