data/full_repos/permissive/13773754/hydra/testbench/strand_driver_tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/strand_driver_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = !clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/13773754/hydra/testbench/strand_driver_tb.v:55: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("strand_driver_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/13773754/hydra/testbench/strand_driver_tb.v:56: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, strand_driver_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/strand_driver_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #20 rst_n = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/strand_driver_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #20 start_frame = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/strand_driver_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #20 start_frame = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/13773754/hydra/testbench/strand_driver_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #300000 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module strand_driver_tb;

    parameter MEM_DATA_WIDTH = 24;
    parameter STRAND_PARAM_WIDTH = 16;

    reg clk = 0;
    reg rst_n = 1;

    reg ws2811_mode = 0;
    reg start_frame = 0;

    reg [STRAND_PARAM_WIDTH-1:0] strand_length = 160;

    wire [STRAND_PARAM_WIDTH-1:0] current_idx;
    reg [MEM_DATA_WIDTH-1:0] mem_data = 24'b101011001110000110101110;

    wire busy;
    wire done;

    wire strand_clk;
    wire strand_data;


    strand_driver sd_inst (
            .clk(clk),
            .rst_n(rst_n),
            .ws2811_mode(ws2811_mode),
            .strand_length(strand_length),
            .current_idx(current_idx),
            .mem_data(mem_data),
            .start_frame(start_frame),
            .busy(busy),
            .done(done),
            .strand_clk(strand_clk),
            .strand_data(strand_data)
        );


    always #10 clk = !clk;


    initial begin

        $dumpfile("strand_driver_tb.vcd");
        $dumpvars(0, strand_driver_tb);

        rst_n = 0;
        #20 rst_n = 1;
        #20 start_frame = 1;
        #20 start_frame = 0;

        #300000 $finish;
    end

endmodule
module strand_driver_tb;


    parameter MEM_DATA_WIDTH = 24;
    parameter STRAND_PARAM_WIDTH = 16;

    reg clk = 0;
    reg rst_n = 1;

    reg ws2811_mode = 0;
    reg start_frame = 0;

    reg [STRAND_PARAM_WIDTH-1:0] strand_length = 160;

    wire [STRAND_PARAM_WIDTH-1:0] current_idx;
    reg [MEM_DATA_WIDTH-1:0] mem_data = 24'b101011001110000110101110;

    wire busy;
    wire done;

    wire strand_clk;
    wire strand_data;


    strand_driver sd_inst (
            .clk(clk),
            .rst_n(rst_n),
            .ws2811_mode(ws2811_mode),
            .strand_length(strand_length),
            .current_idx(current_idx),
            .mem_data(mem_data),
            .start_frame(start_frame),
            .busy(busy),
            .done(done),
            .strand_clk(strand_clk),
            .strand_data(strand_data)
        );


    always #10 clk = !clk;


    initial begin

        $dumpfile("strand_driver_tb.vcd");
        $dumpvars(0, strand_driver_tb);

        rst_n = 0;
        #20 rst_n = 1;
        #20 start_frame = 1;
        #20 start_frame = 0;

        #300000 $finish;
    end

endmodule