data/full_repos/permissive/141745123/Lab_6.srcs/sim_1/new/Top.v
'utf-8' codec can't decode byte 0xb3 in position 525: invalid start byte
1: b'%Warning-STMTDLY: data/full_repos/permissive/141745123/Lab_6.srcs/sim_1/new/Top.v:33: Unsupported: Ignoring delay on this delayed statement.\n       #5 clk = ~clk; \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/141745123/Lab_6.srcs/sim_1/new/Top.v:37: Unsupported: Ignoring delay on this delayed statement.\n       #1 rst = 0;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/141745123/Lab_6.srcs/sim_1/new/Top.v:38: Unsupported: Ignoring delay on this delayed statement.\n       #20 rst = 1; \n       ^\n%Warning-STMTDLY: data/full_repos/permissive/141745123/Lab_6.srcs/sim_1/new/Top.v:39: Unsupported: Ignoring delay on this delayed statement.\n       #1000 $stop; \n       ^\n%Error: data/full_repos/permissive/141745123/Lab_6.srcs/sim_1/new/Top.v:25: Cannot find file containing module: \'CPU\'\n   CPU cpu0(clk, rst);\n   ^~~\n        ... Looked in:\n             data/full_repos/permissive/141745123/Lab_6.srcs/sim_1/new,data/full_repos/permissive/141745123/CPU\n             data/full_repos/permissive/141745123/Lab_6.srcs/sim_1/new,data/full_repos/permissive/141745123/CPU.v\n             data/full_repos/permissive/141745123/Lab_6.srcs/sim_1/new,data/full_repos/permissive/141745123/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Top();
   reg clk, rst;
   CPU cpu0(clk, rst);

   initial begin
   clk = 0;
   rst = 1;
   end
   
   always begin
       #5 clk = ~clk;
   end
   
   initial begin
       #1 rst = 0;
       #20 rst = 1;
       #1000 $stop;
   end
endmodule
module Top();

   reg clk, rst;
   CPU cpu0(clk, rst);

   initial begin
   clk = 0;
   rst = 1;
   end
   
   always begin
       #5 clk = ~clk;
   end
   
   initial begin
       #1 rst = 0;
       #20 rst = 1;
       #1000 $stop;
   end
endmodule