data/full_repos/permissive/141038711/hdl/apb_fastdecode.v
1: b'%Warning-WIDTH: data/full_repos/permissive/141038711/hdl/apb_fastdecode.v:71: Operator GTE expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'pre_select_bits\' generates 1 bits.\n                                                                            : ... In instance apb_fastdecode\n   assign select_error = pre_select_bits>=PORTS;\n                                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/141038711/hdl/apb_fastdecode.v:75: Operator COND expects 32 or 2 bits on the Conditional False, but Conditional False\'s VARREF \'pre_select_bits\' generates 1 bits.\n                                                                            : ... In instance apb_fastdecode\n   assign select_bits  = TOP_DEFAULT & select_error ? PORTS-1 :  pre_select_bits;\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/141038711/hdl/apb_fastdecode.v:75: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 2 bits.\n                                                                            : ... In instance apb_fastdecode\n   assign select_bits  = TOP_DEFAULT & select_error ? PORTS-1 :  pre_select_bits;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/141038711/hdl/apb_fastdecode.v:79: Operator SHIFTL expects 2 bits on the LHS, but LHS\'s VARREF \'s_psel\' generates 1 bits.\n                                                                            : ... In instance apb_fastdecode\n   assign m_psel    = ~TOP_DEFAULT & select_error ? {PORTS{1\'b0}} : s_psel<<select_bits;\n                                                                          ^~\n%Error: Exiting due to 4 warning(s)\n'
module apb_fastdecode
#(parameter PORTS      = 2,
            MS_SLVADR  = 9,

            TOP_DEFAULT = 0
 )
(

   input      [31:0] s_paddr,
   input             s_pwrite,
   input             s_psel,
   input             s_penable,
   input      [31:0] s_pwdata,
   output     [31:0] s_prdata,
   output            s_pready,
   output            s_pslverr,
   

   output    [MS_SLVADR:0] m_paddr,  
   output                 m_pwrite,
   output     [PORTS-1:0] m_psel,
   output                 m_penable,
   output          [31:0] m_pwdata,
   input   [PORTS*32-1:0] m_prdata,
   input      [PORTS-1:0] m_pready,
   input      [PORTS-1:0] m_pslverr
);


localparam SELBITS = PORTS<=2    ? 1 :
                     PORTS<=4    ? 2 :
                     PORTS<=8    ? 3 :
                     PORTS<=16   ? 4 : 
                     PORTS<=32   ? 5 :
                     PORTS<=64   ? 6 :
                     PORTS<=128  ? 7 :
                     0 ;

 

wire select_error;    
wire [SELBITS-1:0] pre_select_bits,select_bits;


   assign m_paddr   = s_paddr[MS_SLVADR:0]; 
   assign m_pwrite  = s_pwrite;
   assign m_penable = s_penable;
   assign m_pwdata  = s_pwdata;
   

   assign pre_select_bits = s_paddr[MS_SLVADR+1 +: SELBITS];
   

   assign select_error = pre_select_bits>=PORTS;
   


   assign select_bits  = TOP_DEFAULT & select_error ? PORTS-1 :  pre_select_bits;
  


   assign m_psel    = ~TOP_DEFAULT & select_error ? {PORTS{1'b0}} : s_psel<<select_bits;
   assign s_prdata  = m_prdata[select_bits*32 +: 32];
   

   assign s_pready  = m_pready[select_bits]  | (~TOP_DEFAULT & select_error);
   assign s_pslverr = m_pslverr[select_bits] | (~TOP_DEFAULT & select_error);

endmodule
module apb_fastdecode
#(parameter PORTS      = 2,
            MS_SLVADR  = 9,

            TOP_DEFAULT = 0
 )
(

   input      [31:0] s_paddr,
   input             s_pwrite,
   input             s_psel,
   input             s_penable,
   input      [31:0] s_pwdata,
   output     [31:0] s_prdata,
   output            s_pready,
   output            s_pslverr,
   

   output    [MS_SLVADR:0] m_paddr,  
   output                 m_pwrite,
   output     [PORTS-1:0] m_psel,
   output                 m_penable,
   output          [31:0] m_pwdata,
   input   [PORTS*32-1:0] m_prdata,
   input      [PORTS-1:0] m_pready,
   input      [PORTS-1:0] m_pslverr
);



localparam SELBITS = PORTS<=2    ? 1 :
                     PORTS<=4    ? 2 :
                     PORTS<=8    ? 3 :
                     PORTS<=16   ? 4 : 
                     PORTS<=32   ? 5 :
                     PORTS<=64   ? 6 :
                     PORTS<=128  ? 7 :
                     0 ;

 

wire select_error;    
wire [SELBITS-1:0] pre_select_bits,select_bits;


   assign m_paddr   = s_paddr[MS_SLVADR:0]; 
   assign m_pwrite  = s_pwrite;
   assign m_penable = s_penable;
   assign m_pwdata  = s_pwdata;
   

   assign pre_select_bits = s_paddr[MS_SLVADR+1 +: SELBITS];
   

   assign select_error = pre_select_bits>=PORTS;
   


   assign select_bits  = TOP_DEFAULT & select_error ? PORTS-1 :  pre_select_bits;
  


   assign m_psel    = ~TOP_DEFAULT & select_error ? {PORTS{1'b0}} : s_psel<<select_bits;
   assign s_prdata  = m_prdata[select_bits*32 +: 32];
   

   assign s_pready  = m_pready[select_bits]  | (~TOP_DEFAULT & select_error);
   assign s_pslverr = m_pslverr[select_bits] | (~TOP_DEFAULT & select_error);

endmodule