data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v
 line:71: before: "begin"
1: b'%Error: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:62: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("coredump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:63: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars();\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:71: Unsupported: Ignoring delay on this delayed statement.\n    initial #5 begin\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:75: Unsupported: Ignoring delay on this delayed statement.\n    initial #100 begin\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #1220 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #300  iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:96: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:83: Unsupported: Ignoring delay on this delayed statement.\n    initial #3001564 begin\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #1220 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #300  iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:112: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:99: Unsupported: Ignoring delay on this delayed statement.\n    initial #3055300 begin\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:117: Unsupported: Ignoring delay on this delayed statement.\n        #1220 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #300  iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:123: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:125: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:126: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:128: Unsupported: Ignoring delay on this delayed statement.\n        #1024 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:115: Unsupported: Ignoring delay on this delayed statement.\n    initial #3115300 begin\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:133: Unsupported: Ignoring delay on this delayed statement.\n        #1220 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:135: Unsupported: Ignoring delay on this delayed statement.\n        #200 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:136: Unsupported: Ignoring delay on this delayed statement.\n        #200 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:137: Unsupported: Ignoring delay on this delayed statement.\n        #200 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:138: Unsupported: Ignoring delay on this delayed statement.\n        #200 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #200 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #200 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #200 iTTLSerialRX <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #200 iTTLSerialRX <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:131: Unsupported: Ignoring delay on this delayed statement.\n    initial #6453642 begin\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/173814379/implementation/testbench/coretb_v5r0.v:146: Unsupported: Ignoring delay on this delayed statement.\n    initial #50000000 begin\n            ^\n%Error: Exiting due to 2 error(s), 46 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module epRISC_coreTB();

    reg iBoardClock, iBoardReset; 
    wire iBoardSense, iBoardReceive;
    wire oBoardAcknowledge, oBoardTransmit;
    wire bBoardDebug0, bBoardDebug1, bBoardDebug2, bBoardDebug3, bBoardDebug4, bBoardDebug5;

    wire iBusInterrupt;
    wire [0:7] iBusMISO;
    wire oBusClock;
    wire [0:1] oBusSelect;
    wire [0:7] oBusMOSI;

    wire oMemoryCKE, oMemoryCLK, oMemoryWE, oMemoryCAS, oMemoryRAS, oMemoryCS;
    wire [0:1] oMemoryBank;
    wire [0:3] oMemoryDQM;
    wire [0:11] oMemoryAddress;
    wire [0:32] bMemoryData;

    wire iSerialRX, iSerialCTS, iSerialDCD, iSerialDSR;
    wire oSerialDTR, oSerialRTS, oSerialTX;

    reg iTTLSerialRX, iTTLSerialRST;
    wire oTTLSerialTX;
                          
    wire bGPIO0, bGPIO1, bGPIO2, bGPIO3, bGPIO4, bGPIO5, bGPIO6, bGPIO7, bGPIO8, bGPIO9, bGPIO10, bGPIO11, bGPIO12, bGPIO13, bGPIO14, bGPIO15;
                           
    wire iExtBusInterrupt;
    wire [3:0] iExtBusMISO;
    wire oExtBusClock;
    wire [1:0] oExtBusSS;
    wire [3:0] oExtBusMOSI;
        
    reg iSPIMISO;                   
    wire iSPIDetect0, iSPIDetect1, iSPIWrite0, iSPIWrite1;
    wire oSPIMOSI, oSPISelect, oSPIClock;
                           
    wire oVGAHorizontal, oVGAVertical;
    wire [7:0] oVGAColor; 
                           
    wire bPS2Data, bPS2Clock;

    epRISC_machine machine(iBoardClock, iBoardReset, iBoardSense, oBoardAcknowledge, iBoardReceive, oBoardTransmit,
                      bBoardDebug0, bBoardDebug2, bBoardDebug3, bBoardDebug4, bBoardDebug5,
                      oBusMOSI, iBusMISO, oBusClock, iBusInterrupt, oBusSelect,
                      bMemoryData, oMemoryAddress, oMemoryBank, oMemoryDQM, oMemoryCKE, oMemoryCLK, oMemoryWE, oMemoryCAS, oMemoryRAS, oMemoryCS);

    epRISC_iocontroller controller(oBusClock, oBusSelect, oBusMOSI, iBusInterrupt, iBusMISO,
                           iBoardClock, iBoardReset, bBoardDebug0, bBoardDebug1, bBoardDebug2, bBoardDebug3, bBoardDebug4, bBoardDebug5,
                           oSerialDTR, oSerialRTS, oSerialTX, iSerialRX, iSerialCTS, iSerialDCD, iSerialDSR,
                           oTTLSerialTX, iTTLSerialRX, iTTLSerialRST,
                           bGPIO0, bGPIO1, bGPIO2, bGPIO3, bGPIO4, bGPIO5, bGPIO6, bGPIO7, bGPIO8, bGPIO9, bGPIO10, bGPIO11, bGPIO12, bGPIO13, bGPIO14, bGPIO15,
                           oExtBusMOSI, oExtBusSS, oExtBusClock, iExtBusMISO, iExtBusInterrupt,
                           oSPIMOSI, oSPISelect, oSPIClock, iSPIMISO, iSPIDetect0, iSPIDetect1, iSPIWrite0, iSPIWrite1,
                           oVGAColor, oVGAHorizontal, oVGAVertical,
                           bPS2Data, bPS2Clock);

   
    initial begin
        $dumpfile("coredump.vcd");
        $dumpvars();
        
        iBoardClock = 0;
        iBoardReset = 1;
        iTTLSerialRX <= 1;
        iSPIMISO <= 1;
    end
    
    initial #5 begin
        iBoardReset = 0;
    end
    
    initial #100 begin
        iBoardReset = 1;
    end
   
    initial begin
        forever iBoardClock = #2 !iBoardClock;
    end
   
    initial #3001564 begin
        iTTLSerialRX <= 0;
        #1220 iTTLSerialRX <= 1;
        
        #300  iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        
        #1024 iTTLSerialRX <= 1;
    end
    
    initial #3055300 begin
        iTTLSerialRX <= 0;
        #1220 iTTLSerialRX <= 1;
        
        #300  iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        
        #1024 iTTLSerialRX <= 1;
    end
    
    initial #3115300 begin
        iTTLSerialRX <= 0;
        #1220 iTTLSerialRX <= 1;
        
        #300  iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 0;
        
        #1024 iTTLSerialRX <= 1;
    end
    
    initial #6453642 begin
        iTTLSerialRX <= 0;
        #1220 iTTLSerialRX <= 1;
        
        #200 iTTLSerialRX <= 0;
        #200 iTTLSerialRX <= 1;
        #200 iTTLSerialRX <= 1;
        #200 iTTLSerialRX <= 0;
        #200 iTTLSerialRX <= 0;
        #200 iTTLSerialRX <= 0;
        #200 iTTLSerialRX <= 0;
        
        #200 iTTLSerialRX <= 1;
    end
    
    initial #50000000 begin
        $finish;
    end
    
endmodule
module epRISC_coreTB();


    reg iBoardClock, iBoardReset; 
    wire iBoardSense, iBoardReceive;
    wire oBoardAcknowledge, oBoardTransmit;
    wire bBoardDebug0, bBoardDebug1, bBoardDebug2, bBoardDebug3, bBoardDebug4, bBoardDebug5;

    wire iBusInterrupt;
    wire [0:7] iBusMISO;
    wire oBusClock;
    wire [0:1] oBusSelect;
    wire [0:7] oBusMOSI;

    wire oMemoryCKE, oMemoryCLK, oMemoryWE, oMemoryCAS, oMemoryRAS, oMemoryCS;
    wire [0:1] oMemoryBank;
    wire [0:3] oMemoryDQM;
    wire [0:11] oMemoryAddress;
    wire [0:32] bMemoryData;

    wire iSerialRX, iSerialCTS, iSerialDCD, iSerialDSR;
    wire oSerialDTR, oSerialRTS, oSerialTX;

    reg iTTLSerialRX, iTTLSerialRST;
    wire oTTLSerialTX;
                          
    wire bGPIO0, bGPIO1, bGPIO2, bGPIO3, bGPIO4, bGPIO5, bGPIO6, bGPIO7, bGPIO8, bGPIO9, bGPIO10, bGPIO11, bGPIO12, bGPIO13, bGPIO14, bGPIO15;
                           
    wire iExtBusInterrupt;
    wire [3:0] iExtBusMISO;
    wire oExtBusClock;
    wire [1:0] oExtBusSS;
    wire [3:0] oExtBusMOSI;
        
    reg iSPIMISO;                   
    wire iSPIDetect0, iSPIDetect1, iSPIWrite0, iSPIWrite1;
    wire oSPIMOSI, oSPISelect, oSPIClock;
                           
    wire oVGAHorizontal, oVGAVertical;
    wire [7:0] oVGAColor; 
                           
    wire bPS2Data, bPS2Clock;

    epRISC_machine machine(iBoardClock, iBoardReset, iBoardSense, oBoardAcknowledge, iBoardReceive, oBoardTransmit,
                      bBoardDebug0, bBoardDebug2, bBoardDebug3, bBoardDebug4, bBoardDebug5,
                      oBusMOSI, iBusMISO, oBusClock, iBusInterrupt, oBusSelect,
                      bMemoryData, oMemoryAddress, oMemoryBank, oMemoryDQM, oMemoryCKE, oMemoryCLK, oMemoryWE, oMemoryCAS, oMemoryRAS, oMemoryCS);

    epRISC_iocontroller controller(oBusClock, oBusSelect, oBusMOSI, iBusInterrupt, iBusMISO,
                           iBoardClock, iBoardReset, bBoardDebug0, bBoardDebug1, bBoardDebug2, bBoardDebug3, bBoardDebug4, bBoardDebug5,
                           oSerialDTR, oSerialRTS, oSerialTX, iSerialRX, iSerialCTS, iSerialDCD, iSerialDSR,
                           oTTLSerialTX, iTTLSerialRX, iTTLSerialRST,
                           bGPIO0, bGPIO1, bGPIO2, bGPIO3, bGPIO4, bGPIO5, bGPIO6, bGPIO7, bGPIO8, bGPIO9, bGPIO10, bGPIO11, bGPIO12, bGPIO13, bGPIO14, bGPIO15,
                           oExtBusMOSI, oExtBusSS, oExtBusClock, iExtBusMISO, iExtBusInterrupt,
                           oSPIMOSI, oSPISelect, oSPIClock, iSPIMISO, iSPIDetect0, iSPIDetect1, iSPIWrite0, iSPIWrite1,
                           oVGAColor, oVGAHorizontal, oVGAVertical,
                           bPS2Data, bPS2Clock);

   
    initial begin
        $dumpfile("coredump.vcd");
        $dumpvars();
        
        iBoardClock = 0;
        iBoardReset = 1;
        iTTLSerialRX <= 1;
        iSPIMISO <= 1;
    end
    
    initial #5 begin
        iBoardReset = 0;
    end
    
    initial #100 begin
        iBoardReset = 1;
    end
   
    initial begin
        forever iBoardClock = #2 !iBoardClock;
    end
   
    initial #3001564 begin
        iTTLSerialRX <= 0;
        #1220 iTTLSerialRX <= 1;
        
        #300  iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        
        #1024 iTTLSerialRX <= 1;
    end
    
    initial #3055300 begin
        iTTLSerialRX <= 0;
        #1220 iTTLSerialRX <= 1;
        
        #300  iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        
        #1024 iTTLSerialRX <= 1;
    end
    
    initial #3115300 begin
        iTTLSerialRX <= 0;
        #1220 iTTLSerialRX <= 1;
        
        #300  iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 0;
        #1024 iTTLSerialRX <= 1;
        #1024 iTTLSerialRX <= 0;
        
        #1024 iTTLSerialRX <= 1;
    end
    
    initial #6453642 begin
        iTTLSerialRX <= 0;
        #1220 iTTLSerialRX <= 1;
        
        #200 iTTLSerialRX <= 0;
        #200 iTTLSerialRX <= 1;
        #200 iTTLSerialRX <= 1;
        #200 iTTLSerialRX <= 0;
        #200 iTTLSerialRX <= 0;
        #200 iTTLSerialRX <= 0;
        #200 iTTLSerialRX <= 0;
        
        #200 iTTLSerialRX <= 1;
    end
    
    initial #50000000 begin
        $finish;
    end
    
endmodule