data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v
1: b'%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:22: Cannot find include file: inc/regs.v\n`include "inc/regs.v"               //                                         \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/136510272/projects/version.1.zx80,data/full_repos/permissive/136510272/inc/regs.v\n             data/full_repos/permissive/136510272/projects/version.1.zx80,data/full_repos/permissive/136510272/inc/regs.v.v\n             data/full_repos/permissive/136510272/projects/version.1.zx80,data/full_repos/permissive/136510272/inc/regs.v.sv\n             inc/regs.v\n             inc/regs.v.v\n             inc/regs.v.sv\n             obj_dir/inc/regs.v\n             obj_dir/inc/regs.v.v\n             obj_dir/inc/regs.v.sv\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:23: Cannot find include file: inc/initial.v\n`include "inc/initial.v"            //                            \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:24: Cannot find include file: inc/regs_write.v\n`include "inc/regs_write.v"         //                                \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:25: Cannot find include file: inc/alu.v\n`include "inc/alu.v"                //                     -                                          \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:26: Cannot find include file: inc/decoder.v\n`include "inc/decoder.v"            //                                     \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:27: Cannot find include file: inc/irq.v\n`include "inc/irq.v"                // IRQ \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:176: Define or directive not defined: \'`REG_B\'\n                w_num <= `REG_B;\n                         ^~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:176: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                w_num <= `REG_B;\n                               ^\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:205: Define or directive not defined: \'`CF\'\n                if (f[ o[4] ? `CF : `ZF] == o[3]) begin\n                              ^~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:205: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n                if (f[ o[4] ? `CF : `ZF] == o[3]) begin\n                                  ^\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:205: Define or directive not defined: \'`ZF\'\n                if (f[ o[4] ? `CF : `ZF] == o[3]) begin\n                                    ^~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:216: syntax error, unexpected else, expecting endcase\n            else if (I_LD_R16I) begin\n            ^~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:225: syntax error, unexpected else\n            else if (I_ADD_HLR16) begin\n            ^~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:278: syntax error, unexpected <=, expecting IDENTIFIER\n                if (O_HLMEM_53) begin t_state <= 1\'b1; ap <= HL; end\n                                              ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:279: syntax error, unexpected <=, expecting IDENTIFIER\n                           else begin t_state <= 1\'b0; flags <= f_incdec_r8; end\n                                              ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:295: Define or directive not defined: \'`REG_A\'\n                w_num <= `REG_A;\n                         ^~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:301: syntax error, unexpected <=, expecting IDENTIFIER\n                    3\'b100: begin w_r <= A; flags <= F[7:0]; end\n                                      ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:307: syntax error, unexpected <=, expecting IDENTIFIER\n                        flags <= { F[7:6], !A[5], 1\'b1, !A[3], F[2], 1\'b1, F[0]};\n                              ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:312: syntax error, unexpected <=, expecting IDENTIFIER\n                    3\'b110: flags <= {F[7:5], 1\'b0, F[3:2], 1\'b0, 1\'b1};  \n                                  ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:313: syntax error, unexpected <=, expecting IDENTIFIER\n                    3\'b111: flags <= {F[7:5], 1\'b0, F[3:2], 1\'b0, 1\'b0};  \n                                  ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:319: syntax error, unexpected <=, expecting IDENTIFIER\n                        w_r   <= r_gs;\n                              ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:326: syntax error, unexpected end\n            end\n            ^~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:343: syntax error, unexpected <=, expecting IDENTIFIER\n                    o_data  <= r8_20;\n                            ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:351: syntax error, unexpected <=, expecting IDENTIFIER\n                    pc      <= pc + 1\'b1;\n                            ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:358: syntax error, unexpected <=, expecting IDENTIFIER\n                    w_r     <= r8_20;\n                            ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:368: Define or directive not defined: \'`REG_A\'\n                w_num   <= `REG_A;\n                           ^~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:375: syntax error, unexpected <=, expecting IDENTIFIER\n                if (O_HLMEM_20) t_state <= 1\'b1;\n                                        ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:418: Define or directive not defined: \'`REG_A\'\n                w_num   <= `REG_A;\n                           ^~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:511: Define or directive not defined: \'`REG_A\'\n                w_num   <= `REG_A;  \n                           ^~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:588: syntax error, unexpected <=, expecting IDENTIFIER\n                if (I_ADDI8) pc <= pc + 1\'b1;\n                                ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:665: syntax error, unexpected <=, expecting IDENTIFIER\n                    mem     <= 1\'b1;\n                            ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:673: syntax error, unexpected <=, expecting IDENTIFIER\n                    t_state <= 1\'b0;\n                            ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:742: syntax error, unexpected <=, expecting IDENTIFIER\n                if (o[3] == 1\'b0) o_wr <= 1\'b1;\n                                       ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:789: syntax error, unexpected <=, expecting IDENTIFIER\n                    o_wr    <= 1\'b1;\n                            ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:793: syntax error, unexpected <=, expecting IDENTIFIER\n                end else t_state <= 1\'b0;\n                                 ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:828: Define or directive not defined: \'`REG_A\'\n                w_num   <= `REG_A;\n                           ^~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:849: Define or directive not defined: \'`REG_A\'\n                    w_num  <= o[4] ? `REG_A : `REG_L;  \n                                     ^~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:849: Define or directive not defined: \'`REG_L\'\n                    w_num  <= o[4] ? `REG_A : `REG_L;  \n                                              ^~~~~~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:855: syntax error, unexpected <=, expecting IDENTIFIER\n                        mem     <= 1\'b0;\n                                ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:861: syntax error, unexpected <=, expecting IDENTIFIER\n                        t_state <= 4\'h4;\n                                ^~\n%Error: data/full_repos/permissive/136510272/projects/version.1.zx80/processor.v:920: Define or directive not defined: \'`REG_H\'\n                if (o[3]) begin w_num <= `REG_H; w_r <= i_data; end\n                                         ^~~~~~\n%Error: Cannot continue\n'
module processor(

    input   wire            clock,
    output  wire    [15:0]  o_addr,
    input   wire    [7:0]   i_data,
    output  reg     [7:0]   o_data,
    output  reg             o_wr,


    output reg      [15:0]  port_addr,
    output reg      [7:0]   port_data,
    output wire     [7:0]   port_in,
    output reg              port_clock
);

assign o_addr = mem ? ap : pc;
assign led = A;



`include "inc/regs.v"
`include "inc/initial.v"
`include "inc/regs_write.v"
`include "inc/alu.v"
`include "inc/decoder.v"
`include "inc/irq.v"






always @(posedge clock) begin


    if (irq_38_timer == 16'd32 & ie) irq <= 3'h7;


    else case (t_state)



        4'h0: begin





            w_r16af <= 1'b0;


            w_reg   <= I_DJNZ |


                       ((I_INCR8 | I_DECR8) & !O_HLMEM_53) |


                       (I_SSDAA & (o[5:3] < 3'b110)) |


                       (I_LD & !O_HLMEM_53 & !O_HLMEM_20) |


                       (I_ALUR8 & !O_HLMEM_20 & (o[5:3] != 3'b111));


            w_reg16 <= I_ADD_HLR16 | I_INCR16 | I_DECR16 | I_LDSPHL | I_EXDEHL;


            w_flag  <= I_ADD_HLR16 | I_SSDAA |


                       ((I_INCR8 | I_DECR8) & !O_HLMEM_53) |


                       (I_ALUR8 & !O_HLMEM_20);


            mem     <= I_LDXXA | I_LDAXX |


                       (O_HLMEM_53 & (I_INCR8 | I_DECR8)) |


                       (I_LD & ( O_HLMEM_53 | O_HLMEM_20 )) |


                       (I_ALUR8 & O_HLMEM_20) |


                       ((I_RET_CCC) & K_JUMP_CCC) |


                       I_POP16 | I_RET | I_PUSH16 | I_RST | I_EXSPHL | I_IRQ;


            o_wr     <= I_LDXXA | (I_LD & O_HLMEM_53) | I_PUSH16 | I_RST | I_IRQ;


            postpref <= prefixed;




            prefixed <= (I_PREFIX_IX | I_PREFIX_IY) | (I_BITS & prefixed);


            port_clock <= 1'b0;







            if (I_RST | I_IRQ) begin

                ap      <= sp - 2'h2;
                w_r     <= I_IRQ ? pc[15:8] : pcn[15:8];
                o_data  <= I_IRQ ? pc[7:0]  : pcn[7:0];
                t_state <= I_IRQ ? 4'h8 : 1'b1;

            end


            else if (I_NOP) pc <= pc + 1'b1;



            else if (I_PREFIX_IX | I_PREFIX_IY) begin

                pc     <= pc + 1'b1;
                prefix <= I_PREFIX_IY;

            end


            else if (I_EX_AF) begin

                bank_af <= !bank_af;
                pc      <= pc + 1'b1;

            end


            else if (I_EXX) begin

                bank_r  <= !bank_r;
                pc      <= pc + 1'b1;

            end


            else if (I_JPHL) begin

                pc      <= HL;
                t_state <= 1'b1;

            end


            else if (I_LDSPHL) begin

                w_r16   <= HL;
                w_num16 <= 2'h3;
                pc      <= pc + 1'b1;

            end


            else if (I_DJNZ) begin

                w_num <= `REG_B;
                w_r   <= B - 1'b1;


                if (B == 1'b1) begin

                    pc      <= pc + 2'h2;

                end else begin

                    pc      <= pc + 1'b1;
                    t_state <= 1'b1;

                end

            end


            else if (I_JR) begin

                t_state <= 1'b1;
                pc      <= pc + 1'b1;

            end


            else if (I_JR_CC8) begin


                if (f[ o[4] ? `CF : `ZF] == o[3]) begin

                    t_state <= 1'b1;
                    pc      <= pc + 1'b1;


                end else pc <= pc + 2'h2;

            end


            else if (I_LD_R16I) begin

                w_num16 <= o[5:4];
                pc      <= pc + 1'b1;
                t_state <= 1'b1;

            end


            else if (I_ADD_HLR16) begin

                w_r16   <= r_addhl_rr;
                flags   <= f_addhl_rr;
                w_num16 <= 2'b10;
                pc      <= pc + 1'b1;

            end



            else if (I_LDXXA | I_LDAXX) begin

                ap      <= o[4] ? DE : BC;
                o_data  <= A;
                pc      <= pc + 1'b1;
                t_state <= 1'b1;

            end



            else if (I_nnnn_HLA) begin

                pc      <= pc + 1'b1;
                t_state <= 1'b1;

            end



            else if (I_INCR16 | I_DECR16) begin


                w_r16   <= o[5:4] == 2'b00 ? (I_INCR16 ? BC + 1'b1 : BC - 1'b1) :
                           o[5:4] == 2'b01 ? (I_INCR16 ? DE + 1'b1 : DE - 1'b1) :
                           o[5:4] == 2'b10 ? (I_INCR16 ? HL + 1'b1 : HL - 1'b1) :
                                             (I_INCR16 ? sp + 1'b1 : sp - 1'b1);

                w_num16 <= o[5:4];
                pc      <= pc + 1'b1;

            end



            else if (I_INCR8 | I_DECR8) begin

                w_r     <= r_incdec_r8;
                w_num   <= {o[5:4], !o[3]};
                pc      <= pc + 1'b1;


                if (O_HLMEM_53) begin t_state <= 1'b1; ap <= HL; end
                           else begin t_state <= 1'b0; flags <= f_incdec_r8; end

            end


            else if (I_LDR8I) begin

                pc      <= pc + 1'b1;
                t_state <= 1'b1;
                w_num   <= {o[5:4], !o[3]};

            end


            else if (I_SSDAA) begin

                w_num <= `REG_A;
                pc    <= pc + 1'b1;

                case (o[5:3])


                    3'b100: begin w_r <= A; flags <= F[7:0]; end


                    3'b101: begin


                        flags <= { F[7:6], !A[5], 1'b1, !A[3], F[2], 1'b1, F[0]};
                        w_r   <= A ^ 8'hFF;

                    end

                    3'b110: flags <= {F[7:5], 1'b0, F[3:2], 1'b0, 1'b1};
                    3'b111: flags <= {F[7:5], 1'b0, F[3:2], 1'b0, 1'b0};



                    default: begin

                        w_r   <= r_gs;
                        flags <= f_gs_fin;

                    end

                endcase

            end


            else if (I_LD) begin

                ap    <= HL;
                w_num <= {o[5:4], !o[3]};


                if (o[5:0] == 6'b110110) begin



                end

                else if (o[5:3] == 3'b110) begin

                    o_data  <= r8_20;
                    pc      <= pc + 1'b1;
                    t_state <= 1'b1;

                end

                else if (o[2:0] == 3'b110) begin

                    pc      <= pc + 1'b1;
                    t_state <= 1'b1;

                end

                else begin

                    w_r     <= r8_20;
                    pc      <= pc + 1'b1;

                end

            end


            else if (I_ALUR8) begin

                w_num   <= `REG_A;
                w_r     <= r_alur8[7:0];
                flags   <= f_alur8;
                ap      <= HL;
                pc      <= pc + 1'b1;


                if (O_HLMEM_20) t_state <= 1'b1;

            end




            else if (I_RET_CCC | I_POP16 | I_RET) begin

                ap      <= sp;
                pc      <= pc + 1'b1;
                t_state <= K_JUMP_CCC | I_POP16 | I_RET;

            end




            else if (I_JP_CCC | I_CALL_CCC | I_JP | I_CALL) begin


                pc      <= K_JUMP_CCC | I_JP | I_CALL? pc + 1'b1 : pc + 2'h3;
                t_state <= K_JUMP_CCC | I_JP | I_CALL;

            end


            else if (I_PUSH16) begin


                o_data  <= o[5:4] == 2'b00 ? C :
                           o[5:4] == 2'b01 ? E :
                           o[5:4] == 2'b10 ? L : F;

                ap      <= sp - 2'h2;
                pc      <= pc + 1'b1;
                t_state <= 1'b1;

            end


            else if (I_ADDI8) begin

                w_num   <= `REG_A;
                pc      <= pc + 1'b1;
                t_state <= 1'b1;

            end


            else if (I_DI | I_EI) begin

                pc <= pc + 1'b1;
                ie <= I_EI;

            end


            else if (I_EXDEHL) begin

                w_r16   <= HL;
                w_num16 <= 2'b01;
                ap      <= DE;
                pc      <= pc + 1'b1;
                t_state <= 1'b1;

            end


            else if (I_EXSPHL) begin

                pc      <= pc + 1'b1;
                ap      <= sp;
                t_state <= 1'b1;

            end


            else if (I_BITS) begin

                t_state <= 1'b1;
                ap      <= HL;
                pc      <= pc + 1'b1;

            end



            else if (I_OUT8A | I_INA8) begin

                pc      <= pc + 1'b1;
                t_state <= 2'h1;

            end

            opc <= i_data;

        end



        4'h1: begin


            if (I_DJNZ || I_JR || I_JR_CC8) begin

                pc      <= pc + {{8{i_data[7]}}, i_data[7:0]} + 1'b1;
                t_state <= 1'b0;

            end


            else if (I_LD_R16I) begin

                w_r16[7:0] <= i_data;
                pc         <= pc + 1'b1;
                t_state    <= 2'h2;

            end


            else if (I_LDXXA) begin

                o_wr    <= 1'b0;
                mem     <= 1'b0;
                t_state <= 1'b0;

            end


            else if (I_LDAXX) begin

                w_reg   <= 1'b1;
                w_r     <= i_data;
                w_num   <= `REG_A;
                mem     <= 1'b0;
                t_state <= 1'b0;

            end


            else if (I_nnnn_HLA) begin

                ap[7:0] <= i_data;
                pc      <= pc + 1'b1;
                t_state <= 2'h2;

            end


            else if (I_INCR8 | I_DECR8) begin

                o_data  <= r_incdec_r8;
                o_wr    <= 1'b1;
                t_state <= 2'h2;
                w_flag  <= 1'b1;
                flags   <= f_incdec_r8;

            end


            else if (I_LDR8I) begin


                if (O_HLMEM_53) begin

                    ap      <= HL;
                    o_data  <= i_data;
                    mem     <= 1'b1;
                    o_wr    <= 1'b1;
                    t_state <= 2'h2;


                end else begin

                    w_r     <= i_data;
                    w_reg   <= 1'b1;
                    t_state <= 1'b0;

                end

                pc <= pc + 1'b1;

            end


            else if (I_LD) begin


                if ((o[2:0] == 3'b110)) begin w_r <= i_data; w_reg <= 1'b1; end


                o_wr    <= 1'b0;
                mem     <= 1'b0;
                t_state <= 1'b0;

            end



            else if (I_ALUR8 | I_ADDI8) begin


                if (o[5:3] != 3'b111) w_reg <= 1'b1;

                w_r     <= r_alur8[7:0];
                mem     <= 1'b0;
                w_flag  <= 1'b1;
                flags   <= f_alur8;
                t_state <= 1'b0;

                if (I_ADDI8) pc <= pc + 1'b1;

            end


            else if (I_RET_CCC | I_POP16 | I_RET) begin

                w_r     <= i_data;
                ap      <= ap + 1'b1;
                t_state <= 2'h2;


                w_r16    <= sp + 2'h2;
                w_reg16  <= 1'b1;
                w_num16  <= 2'h3;

            end


            else if (I_JP_CCC | I_CALL_CCC | I_JP | I_CALL) begin

                w_r     <= i_data;
                pc      <= pc + 1'b1;
                t_state <= 2'h2;

            end


            else if (I_JPHL) begin

                w_r     <= i_data;
                pc      <= pc + 1'b1;
                t_state <= 2'h2;

            end


            else if (I_PUSH16) begin


                o_data  <= o[5:4] == 2'b00 ? B :
                           o[5:4] == 2'b01 ? D :
                           o[5:4] == 2'b10 ? H : A;

                ap      <= ap + 1'b1;
                t_state <= 4'h4;

            end


            else if (I_EXDEHL) begin

                w_r16   <= ap;
                w_num16 <= 2'b10;
                t_state <= 1'b0;

            end


            else if (I_EXSPHL) begin

                w_r16[7:0] <= i_data;
                ap         <= ap + 1'b1;
                t_state    <= 2'h2;

            end


            else if (I_BITS) begin

                pc        <= pc + 1'b1;
                opc_cb    <= i_data;
                prefixed  <= 1'b0;


                if (O_HLMEM_20) begin

                    mem     <= 1'b1;
                    t_state <= 2'h2;

                end


                else begin

                    t_state <= 1'b0;
                    w_flag  <= gc[7:6] <  2'h2;
                    w_reg   <= gc[7:6] != 2'b01;
                    w_num   <= {gc[2:1], !gc[0]};
                    w_r     <= r_gs_fin;
                    flags   <= f_gs_fin;

                end

            end


            else if (I_OUT8A) begin

                pc         <= pc + 1'b1;
                port_addr  <= i_data;
                port_data  <= A;
                port_clock <= 1'b1;
                t_state    <= 1'b0;

            end


            else if (I_INA8) begin

                pc         <= pc + 1'b1;
                port_addr  <= i_data;
                t_state    <= 2'h2;

            end


            else if (I_RST) begin

                o_data  <= w_r;
                ap      <= ap + 1'b1;
                pc      <= {o[5:3], 3'b000};
                t_state <= 4'h4;

            end

        end



        4'h2: begin


            if (I_LD_R16I) begin

                w_r16[15:8] <= i_data;
                pc      <= pc + 1'b1;
                w_reg16 <= 1'b1;
                t_state <= 1'b0;

            end


            else if (I_nnnn_HLA) begin

                ap[15:8] <= i_data;
                pc       <= pc + 1'b1;
                mem      <= 1'b1;
                o_data   <= o[4] ? A : L;
                t_state  <= 4'h3;


                if (o[3] == 1'b0) o_wr <= 1'b1;

            end


            else if (I_INCR8 | I_DECR8 | I_LDR8I) begin

                o_wr    <= 1'b0;
                mem     <= 1'b0;
                t_state <= 1'b0;

            end


            else if (I_RET_CCC | I_RET) begin


                pc       <= {i_data[7:0], w_r[7:0]};
                mem      <= 1'b0;
                w_reg16  <= 1'b0;
                t_state  <= 1'b0;

            end


            else if (I_POP16) begin


                w_r16   <= {i_data[7:0], w_r[7:0]};
                w_r16af <= o[5:4] == 2'b11;
                w_num16 <= o[5:4];
                mem     <= 1'b0;
                t_state <= 1'b0;

            end


            else if (I_JPHL | I_JP_CCC| I_CALL_CCC | I_JP | I_CALL) begin

                w_r     <= pcn[15:8];
                o_data  <= pcn[7:0];
                ap      <= sp - 2'h2;
                pc      <= {i_data[7:0], w_r[7:0]};


                if (I_CALL_CCC | I_CALL) begin

                    o_wr    <= 1'b1;
                    mem     <= 1'b1;
                    t_state <= 4'h3;

                end else t_state <= 1'b0;


            end


            else if (I_EXSPHL) begin

                w_r16[15:8] <= i_data;
                w_reg16     <= 1'b1;
                w_num16     <= 2'h2;
                ap          <= ap - 1'b1;
                o_data      <= L;
                w_r         <= H;
                o_wr        <= 1'b1;
                t_state     <= 2'h3;

            end


            else if (I_BITS) begin

                t_state <= 3'h4;
                w_flag  <= gc[7:6] <  2'h2;
                o_wr    <= 1'b1;
                w_num   <= {gc[2:1], !gc[0]};
                o_data  <= r_gs_fin;
                flags   <= f_gs_fin;

            end


            else if (I_INA8) begin

                w_reg   <= 1'b1;
                w_num   <= `REG_A;
                w_r     <= port_in;
                t_state <= 1'b0;

            end

        end



        4'h3: begin


            if (I_nnnn_HLA) begin


                if (o[3]) begin

                    w_r    <= i_data;
                    w_num  <= o[4] ? `REG_A : `REG_L;
                    w_reg  <= 1'b1;


                    if (o[4]) begin

                        mem     <= 1'b0;
                        t_state <= 1'b0;


                    end else begin

                        t_state <= 4'h4;
                        ap      <= ap + 1'b1;

                    end


                end else begin


                    if (o[4]) begin

                        mem     <= 1'b0;
                        o_wr    <= 1'b0;
                        t_state <= 1'b0;


                    end else begin

                        o_data  <= H;
                        ap      <= ap + 1'b1;
                        t_state <= 4'h4;

                    end

                end

            end


            else if (I_CALL_CCC | I_CALL) begin

                o_data  <= w_r;
                ap      <= ap + 1'b1;
                t_state <= 4'h4;

            end


            else if (I_EXSPHL) begin

                o_data  <= w_r;
                ap      <= ap + 1'b1;
                t_state <= 4'h4;
                w_reg16 <= 1'b0;

            end

        end



        4'h4: begin


            if (I_nnnn_HLA) begin


                if (o[3]) begin w_num <= `REG_H; w_r <= i_data; end


                mem     <= 1'b0;
                o_wr    <= 1'b0;
                t_state <= 1'b0;

            end


            else if (I_EXSPHL | I_BITS) begin

                o_wr    <= 1'b0;
                mem     <= 1'b0;
                t_state <= 1'b0;


            end


            else if (I_CALL_CCC | I_CALL | I_PUSH16 | I_RST) begin

                o_wr    <= 1'b0;
                mem     <= 1'b0;
                t_state <= 1'b0;


                w_reg16 <= 1'b1;
                w_r16   <= sp - 2'h2;
                w_num16 <= 3'h3;

            end

        end


        4'h8: begin

            o_data  <= w_r;
            ap      <= ap + 1'b1;
            pc      <= {irq, 3'b000};
            irq     <= 1'b0;
            t_state <= 4'h9;

        end

        4'h9: begin

            o_wr    <= 1'b0; mem   <= 1'b0;      t_state <= 1'b0;
            w_reg16 <= 1'b1; w_r16 <= sp - 2'h2; w_num16 <= 3'h3;

        end

    endcase

end

endmodule
module processor(

    input   wire            clock,
    output  wire    [15:0]  o_addr,
    input   wire    [7:0]   i_data,
    output  reg     [7:0]   o_data,
    output  reg             o_wr,


    output reg      [15:0]  port_addr,
    output reg      [7:0]   port_data,
    output wire     [7:0]   port_in,
    output reg              port_clock
);


assign o_addr = mem ? ap : pc;
assign led = A;



`include "inc/regs.v"
`include "inc/initial.v"
`include "inc/regs_write.v"
`include "inc/alu.v"
`include "inc/decoder.v"
`include "inc/irq.v"






always @(posedge clock) begin


    if (irq_38_timer == 16'd32 & ie) irq <= 3'h7;


    else case (t_state)



        4'h0: begin





            w_r16af <= 1'b0;


            w_reg   <= I_DJNZ |


                       ((I_INCR8 | I_DECR8) & !O_HLMEM_53) |


                       (I_SSDAA & (o[5:3] < 3'b110)) |


                       (I_LD & !O_HLMEM_53 & !O_HLMEM_20) |


                       (I_ALUR8 & !O_HLMEM_20 & (o[5:3] != 3'b111));


            w_reg16 <= I_ADD_HLR16 | I_INCR16 | I_DECR16 | I_LDSPHL | I_EXDEHL;


            w_flag  <= I_ADD_HLR16 | I_SSDAA |


                       ((I_INCR8 | I_DECR8) & !O_HLMEM_53) |


                       (I_ALUR8 & !O_HLMEM_20);


            mem     <= I_LDXXA | I_LDAXX |


                       (O_HLMEM_53 & (I_INCR8 | I_DECR8)) |


                       (I_LD & ( O_HLMEM_53 | O_HLMEM_20 )) |


                       (I_ALUR8 & O_HLMEM_20) |


                       ((I_RET_CCC) & K_JUMP_CCC) |


                       I_POP16 | I_RET | I_PUSH16 | I_RST | I_EXSPHL | I_IRQ;


            o_wr     <= I_LDXXA | (I_LD & O_HLMEM_53) | I_PUSH16 | I_RST | I_IRQ;


            postpref <= prefixed;




            prefixed <= (I_PREFIX_IX | I_PREFIX_IY) | (I_BITS & prefixed);


            port_clock <= 1'b0;







            if (I_RST | I_IRQ) begin

                ap      <= sp - 2'h2;
                w_r     <= I_IRQ ? pc[15:8] : pcn[15:8];
                o_data  <= I_IRQ ? pc[7:0]  : pcn[7:0];
                t_state <= I_IRQ ? 4'h8 : 1'b1;

            end


            else if (I_NOP) pc <= pc + 1'b1;



            else if (I_PREFIX_IX | I_PREFIX_IY) begin

                pc     <= pc + 1'b1;
                prefix <= I_PREFIX_IY;

            end


            else if (I_EX_AF) begin

                bank_af <= !bank_af;
                pc      <= pc + 1'b1;

            end


            else if (I_EXX) begin

                bank_r  <= !bank_r;
                pc      <= pc + 1'b1;

            end


            else if (I_JPHL) begin

                pc      <= HL;
                t_state <= 1'b1;

            end


            else if (I_LDSPHL) begin

                w_r16   <= HL;
                w_num16 <= 2'h3;
                pc      <= pc + 1'b1;

            end


            else if (I_DJNZ) begin

                w_num <= `REG_B;
                w_r   <= B - 1'b1;


                if (B == 1'b1) begin

                    pc      <= pc + 2'h2;

                end else begin

                    pc      <= pc + 1'b1;
                    t_state <= 1'b1;

                end

            end


            else if (I_JR) begin

                t_state <= 1'b1;
                pc      <= pc + 1'b1;

            end


            else if (I_JR_CC8) begin


                if (f[ o[4] ? `CF : `ZF] == o[3]) begin

                    t_state <= 1'b1;
                    pc      <= pc + 1'b1;


                end else pc <= pc + 2'h2;

            end


            else if (I_LD_R16I) begin

                w_num16 <= o[5:4];
                pc      <= pc + 1'b1;
                t_state <= 1'b1;

            end


            else if (I_ADD_HLR16) begin

                w_r16   <= r_addhl_rr;
                flags   <= f_addhl_rr;
                w_num16 <= 2'b10;
                pc      <= pc + 1'b1;

            end



            else if (I_LDXXA | I_LDAXX) begin

                ap      <= o[4] ? DE : BC;
                o_data  <= A;
                pc      <= pc + 1'b1;
                t_state <= 1'b1;

            end



            else if (I_nnnn_HLA) begin

                pc      <= pc + 1'b1;
                t_state <= 1'b1;

            end



            else if (I_INCR16 | I_DECR16) begin


                w_r16   <= o[5:4] == 2'b00 ? (I_INCR16 ? BC + 1'b1 : BC - 1'b1) :
                           o[5:4] == 2'b01 ? (I_INCR16 ? DE + 1'b1 : DE - 1'b1) :
                           o[5:4] == 2'b10 ? (I_INCR16 ? HL + 1'b1 : HL - 1'b1) :
                                             (I_INCR16 ? sp + 1'b1 : sp - 1'b1);

                w_num16 <= o[5:4];
                pc      <= pc + 1'b1;

            end



            else if (I_INCR8 | I_DECR8) begin

                w_r     <= r_incdec_r8;
                w_num   <= {o[5:4], !o[3]};
                pc      <= pc + 1'b1;


                if (O_HLMEM_53) begin t_state <= 1'b1; ap <= HL; end
                           else begin t_state <= 1'b0; flags <= f_incdec_r8; end

            end


            else if (I_LDR8I) begin

                pc      <= pc + 1'b1;
                t_state <= 1'b1;
                w_num   <= {o[5:4], !o[3]};

            end


            else if (I_SSDAA) begin

                w_num <= `REG_A;
                pc    <= pc + 1'b1;

                case (o[5:3])


                    3'b100: begin w_r <= A; flags <= F[7:0]; end


                    3'b101: begin


                        flags <= { F[7:6], !A[5], 1'b1, !A[3], F[2], 1'b1, F[0]};
                        w_r   <= A ^ 8'hFF;

                    end

                    3'b110: flags <= {F[7:5], 1'b0, F[3:2], 1'b0, 1'b1};
                    3'b111: flags <= {F[7:5], 1'b0, F[3:2], 1'b0, 1'b0};



                    default: begin

                        w_r   <= r_gs;
                        flags <= f_gs_fin;

                    end

                endcase

            end


            else if (I_LD) begin

                ap    <= HL;
                w_num <= {o[5:4], !o[3]};


                if (o[5:0] == 6'b110110) begin



                end

                else if (o[5:3] == 3'b110) begin

                    o_data  <= r8_20;
                    pc      <= pc + 1'b1;
                    t_state <= 1'b1;

                end

                else if (o[2:0] == 3'b110) begin

                    pc      <= pc + 1'b1;
                    t_state <= 1'b1;

                end

                else begin

                    w_r     <= r8_20;
                    pc      <= pc + 1'b1;

                end

            end


            else if (I_ALUR8) begin

                w_num   <= `REG_A;
                w_r     <= r_alur8[7:0];
                flags   <= f_alur8;
                ap      <= HL;
                pc      <= pc + 1'b1;


                if (O_HLMEM_20) t_state <= 1'b1;

            end




            else if (I_RET_CCC | I_POP16 | I_RET) begin

                ap      <= sp;
                pc      <= pc + 1'b1;
                t_state <= K_JUMP_CCC | I_POP16 | I_RET;

            end




            else if (I_JP_CCC | I_CALL_CCC | I_JP | I_CALL) begin


                pc      <= K_JUMP_CCC | I_JP | I_CALL? pc + 1'b1 : pc + 2'h3;
                t_state <= K_JUMP_CCC | I_JP | I_CALL;

            end


            else if (I_PUSH16) begin


                o_data  <= o[5:4] == 2'b00 ? C :
                           o[5:4] == 2'b01 ? E :
                           o[5:4] == 2'b10 ? L : F;

                ap      <= sp - 2'h2;
                pc      <= pc + 1'b1;
                t_state <= 1'b1;

            end


            else if (I_ADDI8) begin

                w_num   <= `REG_A;
                pc      <= pc + 1'b1;
                t_state <= 1'b1;

            end


            else if (I_DI | I_EI) begin

                pc <= pc + 1'b1;
                ie <= I_EI;

            end


            else if (I_EXDEHL) begin

                w_r16   <= HL;
                w_num16 <= 2'b01;
                ap      <= DE;
                pc      <= pc + 1'b1;
                t_state <= 1'b1;

            end


            else if (I_EXSPHL) begin

                pc      <= pc + 1'b1;
                ap      <= sp;
                t_state <= 1'b1;

            end


            else if (I_BITS) begin

                t_state <= 1'b1;
                ap      <= HL;
                pc      <= pc + 1'b1;

            end



            else if (I_OUT8A | I_INA8) begin

                pc      <= pc + 1'b1;
                t_state <= 2'h1;

            end

            opc <= i_data;

        end



        4'h1: begin


            if (I_DJNZ || I_JR || I_JR_CC8) begin

                pc      <= pc + {{8{i_data[7]}}, i_data[7:0]} + 1'b1;
                t_state <= 1'b0;

            end


            else if (I_LD_R16I) begin

                w_r16[7:0] <= i_data;
                pc         <= pc + 1'b1;
                t_state    <= 2'h2;

            end


            else if (I_LDXXA) begin

                o_wr    <= 1'b0;
                mem     <= 1'b0;
                t_state <= 1'b0;

            end


            else if (I_LDAXX) begin

                w_reg   <= 1'b1;
                w_r     <= i_data;
                w_num   <= `REG_A;
                mem     <= 1'b0;
                t_state <= 1'b0;

            end


            else if (I_nnnn_HLA) begin

                ap[7:0] <= i_data;
                pc      <= pc + 1'b1;
                t_state <= 2'h2;

            end


            else if (I_INCR8 | I_DECR8) begin

                o_data  <= r_incdec_r8;
                o_wr    <= 1'b1;
                t_state <= 2'h2;
                w_flag  <= 1'b1;
                flags   <= f_incdec_r8;

            end


            else if (I_LDR8I) begin


                if (O_HLMEM_53) begin

                    ap      <= HL;
                    o_data  <= i_data;
                    mem     <= 1'b1;
                    o_wr    <= 1'b1;
                    t_state <= 2'h2;


                end else begin

                    w_r     <= i_data;
                    w_reg   <= 1'b1;
                    t_state <= 1'b0;

                end

                pc <= pc + 1'b1;

            end


            else if (I_LD) begin


                if ((o[2:0] == 3'b110)) begin w_r <= i_data; w_reg <= 1'b1; end


                o_wr    <= 1'b0;
                mem     <= 1'b0;
                t_state <= 1'b0;

            end



            else if (I_ALUR8 | I_ADDI8) begin


                if (o[5:3] != 3'b111) w_reg <= 1'b1;

                w_r     <= r_alur8[7:0];
                mem     <= 1'b0;
                w_flag  <= 1'b1;
                flags   <= f_alur8;
                t_state <= 1'b0;

                if (I_ADDI8) pc <= pc + 1'b1;

            end


            else if (I_RET_CCC | I_POP16 | I_RET) begin

                w_r     <= i_data;
                ap      <= ap + 1'b1;
                t_state <= 2'h2;


                w_r16    <= sp + 2'h2;
                w_reg16  <= 1'b1;
                w_num16  <= 2'h3;

            end


            else if (I_JP_CCC | I_CALL_CCC | I_JP | I_CALL) begin

                w_r     <= i_data;
                pc      <= pc + 1'b1;
                t_state <= 2'h2;

            end


            else if (I_JPHL) begin

                w_r     <= i_data;
                pc      <= pc + 1'b1;
                t_state <= 2'h2;

            end


            else if (I_PUSH16) begin


                o_data  <= o[5:4] == 2'b00 ? B :
                           o[5:4] == 2'b01 ? D :
                           o[5:4] == 2'b10 ? H : A;

                ap      <= ap + 1'b1;
                t_state <= 4'h4;

            end


            else if (I_EXDEHL) begin

                w_r16   <= ap;
                w_num16 <= 2'b10;
                t_state <= 1'b0;

            end


            else if (I_EXSPHL) begin

                w_r16[7:0] <= i_data;
                ap         <= ap + 1'b1;
                t_state    <= 2'h2;

            end


            else if (I_BITS) begin

                pc        <= pc + 1'b1;
                opc_cb    <= i_data;
                prefixed  <= 1'b0;


                if (O_HLMEM_20) begin

                    mem     <= 1'b1;
                    t_state <= 2'h2;

                end


                else begin

                    t_state <= 1'b0;
                    w_flag  <= gc[7:6] <  2'h2;
                    w_reg   <= gc[7:6] != 2'b01;
                    w_num   <= {gc[2:1], !gc[0]};
                    w_r     <= r_gs_fin;
                    flags   <= f_gs_fin;

                end

            end


            else if (I_OUT8A) begin

                pc         <= pc + 1'b1;
                port_addr  <= i_data;
                port_data  <= A;
                port_clock <= 1'b1;
                t_state    <= 1'b0;

            end


            else if (I_INA8) begin

                pc         <= pc + 1'b1;
                port_addr  <= i_data;
                t_state    <= 2'h2;

            end


            else if (I_RST) begin

                o_data  <= w_r;
                ap      <= ap + 1'b1;
                pc      <= {o[5:3], 3'b000};
                t_state <= 4'h4;

            end

        end



        4'h2: begin


            if (I_LD_R16I) begin

                w_r16[15:8] <= i_data;
                pc      <= pc + 1'b1;
                w_reg16 <= 1'b1;
                t_state <= 1'b0;

            end


            else if (I_nnnn_HLA) begin

                ap[15:8] <= i_data;
                pc       <= pc + 1'b1;
                mem      <= 1'b1;
                o_data   <= o[4] ? A : L;
                t_state  <= 4'h3;


                if (o[3] == 1'b0) o_wr <= 1'b1;

            end


            else if (I_INCR8 | I_DECR8 | I_LDR8I) begin

                o_wr    <= 1'b0;
                mem     <= 1'b0;
                t_state <= 1'b0;

            end


            else if (I_RET_CCC | I_RET) begin


                pc       <= {i_data[7:0], w_r[7:0]};
                mem      <= 1'b0;
                w_reg16  <= 1'b0;
                t_state  <= 1'b0;

            end


            else if (I_POP16) begin


                w_r16   <= {i_data[7:0], w_r[7:0]};
                w_r16af <= o[5:4] == 2'b11;
                w_num16 <= o[5:4];
                mem     <= 1'b0;
                t_state <= 1'b0;

            end


            else if (I_JPHL | I_JP_CCC| I_CALL_CCC | I_JP | I_CALL) begin

                w_r     <= pcn[15:8];
                o_data  <= pcn[7:0];
                ap      <= sp - 2'h2;
                pc      <= {i_data[7:0], w_r[7:0]};


                if (I_CALL_CCC | I_CALL) begin

                    o_wr    <= 1'b1;
                    mem     <= 1'b1;
                    t_state <= 4'h3;

                end else t_state <= 1'b0;


            end


            else if (I_EXSPHL) begin

                w_r16[15:8] <= i_data;
                w_reg16     <= 1'b1;
                w_num16     <= 2'h2;
                ap          <= ap - 1'b1;
                o_data      <= L;
                w_r         <= H;
                o_wr        <= 1'b1;
                t_state     <= 2'h3;

            end


            else if (I_BITS) begin

                t_state <= 3'h4;
                w_flag  <= gc[7:6] <  2'h2;
                o_wr    <= 1'b1;
                w_num   <= {gc[2:1], !gc[0]};
                o_data  <= r_gs_fin;
                flags   <= f_gs_fin;

            end


            else if (I_INA8) begin

                w_reg   <= 1'b1;
                w_num   <= `REG_A;
                w_r     <= port_in;
                t_state <= 1'b0;

            end

        end



        4'h3: begin


            if (I_nnnn_HLA) begin


                if (o[3]) begin

                    w_r    <= i_data;
                    w_num  <= o[4] ? `REG_A : `REG_L;
                    w_reg  <= 1'b1;


                    if (o[4]) begin

                        mem     <= 1'b0;
                        t_state <= 1'b0;


                    end else begin

                        t_state <= 4'h4;
                        ap      <= ap + 1'b1;

                    end


                end else begin


                    if (o[4]) begin

                        mem     <= 1'b0;
                        o_wr    <= 1'b0;
                        t_state <= 1'b0;


                    end else begin

                        o_data  <= H;
                        ap      <= ap + 1'b1;
                        t_state <= 4'h4;

                    end

                end

            end


            else if (I_CALL_CCC | I_CALL) begin

                o_data  <= w_r;
                ap      <= ap + 1'b1;
                t_state <= 4'h4;

            end


            else if (I_EXSPHL) begin

                o_data  <= w_r;
                ap      <= ap + 1'b1;
                t_state <= 4'h4;
                w_reg16 <= 1'b0;

            end

        end



        4'h4: begin


            if (I_nnnn_HLA) begin


                if (o[3]) begin w_num <= `REG_H; w_r <= i_data; end


                mem     <= 1'b0;
                o_wr    <= 1'b0;
                t_state <= 1'b0;

            end


            else if (I_EXSPHL | I_BITS) begin

                o_wr    <= 1'b0;
                mem     <= 1'b0;
                t_state <= 1'b0;


            end


            else if (I_CALL_CCC | I_CALL | I_PUSH16 | I_RST) begin

                o_wr    <= 1'b0;
                mem     <= 1'b0;
                t_state <= 1'b0;


                w_reg16 <= 1'b1;
                w_r16   <= sp - 2'h2;
                w_num16 <= 3'h3;

            end

        end


        4'h8: begin

            o_data  <= w_r;
            ap      <= ap + 1'b1;
            pc      <= {irq, 3'b000};
            irq     <= 1'b0;
            t_state <= 4'h9;

        end

        4'h9: begin

            o_wr    <= 1'b0; mem   <= 1'b0;      t_state <= 1'b0;
            w_reg16 <= 1'b1; w_r16 <= sp - 2'h2; w_num16 <= 3'h3;

        end

    endcase

end

endmodule