data/full_repos/permissive/200314387/verilog/lib/display.v
 line:9: before: "["
data/verilator_xmls/bb0ef6dd-874a-4a60-88f3-9c314ca8b764.xml
module display;
 reg [80:0][7:0] label = "xxx";

 task display(reg [80:0][7:0] x);
    begin
        label = x;
        $display("\n%-s", x);
    end
 endtask
endmodule
module display;

 reg [80:0][7:0] label = "xxx";

 task display(reg [80:0][7:0] x);
    begin
        label = x;
        $display("\n%-s", x);
    end
 endtask
endmodule