data/full_repos/permissive/118303050/sim/lab_2_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/118303050/sim/lab_2_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #500;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/118303050/sim/lab_2_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/118303050/sim/lab_2_tb.v:40: Cannot find file containing module: \'top\'\n top top(\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/118303050/sim,data/full_repos/permissive/118303050/top\n             data/full_repos/permissive/118303050/sim,data/full_repos/permissive/118303050/top.v\n             data/full_repos/permissive/118303050/sim,data/full_repos/permissive/118303050/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_bench(

    );
	
	reg rst;
	reg clk;
	wire [7:0] ans;
	wire [6:0] seg;
	wire [9:0] led;
	initial
	begin 
		clk = 1'b0;
		rst = 1'b1;
		#500;
		rst = 1'b0;
	end
	always #10 clk = ~clk;
	top top(
		.hclk(clk),
		.rst(rst),
		.seg(seg),
	    .ans(ans),
	    .led(led)
		);
endmodule
module test_bench(

    );

	
	reg rst;
	reg clk;
	wire [7:0] ans;
	wire [6:0] seg;
	wire [9:0] led;
	initial
	begin 
		clk = 1'b0;
		rst = 1'b1;
		#500;
		rst = 1'b0;
	end
	always #10 clk = ~clk;
	top top(
		.hclk(clk),
		.rst(rst),
		.seg(seg),
	    .ans(ans),
	    .led(led)
		);
endmodule