data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v
 line:71: before: "for"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:51: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:53: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:67: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:70: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:87: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:96: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:102: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:110: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:127: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:129: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:131: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:159: Unsupported: Ignoring delay on this delayed statement.\n    #10 $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:160: Unsupported: Ignoring delay on this delayed statement.\n    #5 $finish;\n    ^\n%Error: data/full_repos/permissive/117026779/sim/Test_QuadratureDecoder.v:35: Cannot find file containing module: \'QuadratureDecoder\'\nQuadratureDecoder U0 (\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/QuadratureDecoder\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/QuadratureDecoder.v\n             data/full_repos/permissive/117026779/sim,data/full_repos/permissive/117026779/QuadratureDecoder.sv\n             QuadratureDecoder\n             QuadratureDecoder.v\n             QuadratureDecoder.sv\n             obj_dir/QuadratureDecoder\n             obj_dir/QuadratureDecoder.v\n             obj_dir/QuadratureDecoder.sv\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_QuadratureDecoder;

reg success_flag;

reg clk, rst;
reg oe, we;
reg ext_phase_a, ext_phase_b;
reg [31:0] data_reg;
reg test_write_enable;
wire [31:0] data;

QuadratureDecoder U0 (
    .clk(clk),
    .rst(rst),
    .oe(oe),
    .we(we),
    .ext_phase_a(ext_phase_a),
    .ext_phase_b(ext_phase_b),
    .data(data)
);

assign data = (test_write_enable) ? data_reg : 32'bZ;

integer i;

task CLOCK;
begin
	#1
	clk = 0;
	#1
	clk = 1;
    #1
    clk = 0;
end
endtask

task QUADRATURE_ENCODER_STEP;
	input [31:0] distance;
	input direction;
	integer k;
begin
	oe = 0;
	we = 0;
	#1
	ext_phase_b = direction;
	ext_phase_a = 0;
	#1
	for (k=0; k < distance-1; k = k +1)
	begin
	   #1
		ext_phase_a = ~ext_phase_a;
		CLOCK;
		ext_phase_b = ~ext_phase_b;
		CLOCK;
	end
end
endtask

task STROBE_OUTPUT_ENABLE;
begin
	oe = 0;
	#1000
	oe = 1;
	#1000
	oe = 0;
end
endtask

task CHECK_OUTPUT;
	input [31:0] value;
begin
	oe = 1;
	#1000
	if(data != value)
	begin
		success_flag = 0;
		$display("!!ERROR!! @ %d 0x%X !== 0x%X", $time, data, value);
	end
	#1
	oe = 0;
end
endtask;

task LOAD_QUADRATURE_ENCODER;
	input [31:0] value;
begin
	#1000
	data_reg = value;
	test_write_enable = 1;
	we = 1;
	CLOCK;
	we = 0;
	test_write_enable = 0;
end
endtask

initial begin
	success_flag = 1;
    rst = 0;
    clk = 0;
    oe = 0;
    we = 0;
    test_write_enable = 0;
    #5
    rst = 1;
    #5
    rst = 0;
	#5

	QUADRATURE_ENCODER_STEP(32'hFF, 1);

	CHECK_OUTPUT(32'hFE);

	QUADRATURE_ENCODER_STEP(32'hFF, 0);

	CHECK_OUTPUT(32'h0);

	LOAD_QUADRATURE_ENCODER(32'hABCD);

	CHECK_OUTPUT(32'hABCD);

	LOAD_QUADRATURE_ENCODER(32'h0);

	QUADRATURE_ENCODER_STEP(32'h2, 0);

	CHECK_OUTPUT(32'hFFFFFFFF);


	if (success_flag == 0) begin
		$display("*FAILED* TEST!");
	end
	else begin
		$display("**PASSED** TEST!");
	end

    #10 $stop;
    #5 $finish;
end

endmodule
module Test_QuadratureDecoder;


reg success_flag;

reg clk, rst;
reg oe, we;
reg ext_phase_a, ext_phase_b;
reg [31:0] data_reg;
reg test_write_enable;
wire [31:0] data;

QuadratureDecoder U0 (
    .clk(clk),
    .rst(rst),
    .oe(oe),
    .we(we),
    .ext_phase_a(ext_phase_a),
    .ext_phase_b(ext_phase_b),
    .data(data)
);

assign data = (test_write_enable) ? data_reg : 32'bZ;

integer i;

task CLOCK;
begin
	#1
	clk = 0;
	#1
	clk = 1;
    #1
    clk = 0;
end
endtask

task QUADRATURE_ENCODER_STEP;
	input [31:0] distance;
	input direction;
	integer k;
begin
	oe = 0;
	we = 0;
	#1
	ext_phase_b = direction;
	ext_phase_a = 0;
	#1
	for (k=0; k < distance-1; k = k +1)
	begin
	   #1
		ext_phase_a = ~ext_phase_a;
		CLOCK;
		ext_phase_b = ~ext_phase_b;
		CLOCK;
	end
end
endtask

task STROBE_OUTPUT_ENABLE;
begin
	oe = 0;
	#1000
	oe = 1;
	#1000
	oe = 0;
end
endtask

task CHECK_OUTPUT;
	input [31:0] value;
begin
	oe = 1;
	#1000
	if(data != value)
	begin
		success_flag = 0;
		$display("!!ERROR!! @ %d 0x%X !== 0x%X", $time, data, value);
	end
	#1
	oe = 0;
end
endtask;

task LOAD_QUADRATURE_ENCODER;
	input [31:0] value;
begin
	#1000
	data_reg = value;
	test_write_enable = 1;
	we = 1;
	CLOCK;
	we = 0;
	test_write_enable = 0;
end
endtask

initial begin
	success_flag = 1;
    rst = 0;
    clk = 0;
    oe = 0;
    we = 0;
    test_write_enable = 0;
    #5
    rst = 1;
    #5
    rst = 0;
	#5

	QUADRATURE_ENCODER_STEP(32'hFF, 1);

	CHECK_OUTPUT(32'hFE);

	QUADRATURE_ENCODER_STEP(32'hFF, 0);

	CHECK_OUTPUT(32'h0);

	LOAD_QUADRATURE_ENCODER(32'hABCD);

	CHECK_OUTPUT(32'hABCD);

	LOAD_QUADRATURE_ENCODER(32'h0);

	QUADRATURE_ENCODER_STEP(32'h2, 0);

	CHECK_OUTPUT(32'hFFFFFFFF);


	if (success_flag == 0) begin
		$display("*FAILED* TEST!");
	end
	else begin
		$display("**PASSED** TEST!");
	end

    #10 $stop;
    #5 $finish;
end

endmodule