data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v
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1: b'%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #10;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #90;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #35;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #180;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #150;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:57: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:60: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:68: Unsupported: Ignoring delay on this delayed statement.\n   #25 clk = ~clk;\n   ^\n%Error: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:73: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("./insCache.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/156417892/hdl/InstructionFetch/InsCache/InsCache_test.v:74: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_test;


   reg clk, rstn=1;
   reg [31:0] iaddr;
   reg [127:0] imem_in;
   

   wire [31:0] oins;
   wire        ohit;
   
   integer     i;
   

   InsCache uut(clk,
                rstn,
                iaddr,
                imem_in,
                ohit,
                oins);

   initial begin

      #10;
      rstn = 0;
      
      #10;

      iaddr = 7;
      
      #90;
      imem_in = {32'hDEADBEEF ,32'hABABABAB,
                 32'hCDCDCDCD, 32'hEFEFEFEF};
      #35;
      #180;
      iaddr = 0;

      #50;
      iaddr = 4;

      #50;
      iaddr = 8;

      #50;
      iaddr = 12;

      #50;
      iaddr = 16;

      #150;

      #50;
      iaddr = 20;

      #50;
      iaddr = 24;

      #50;
      iaddr = 28;
      
   end

   initial begin
      clk = 0;
      for (i = 0; i < 64; i = i + 1)
   #25 clk = ~clk;
   end


   initial begin
      $dumpfile("./insCache.vcd");
      $dumpvars;
   end

endmodule
module main_test;



   reg clk, rstn=1;
   reg [31:0] iaddr;
   reg [127:0] imem_in;
   

   wire [31:0] oins;
   wire        ohit;
   
   integer     i;
   

   InsCache uut(clk,
                rstn,
                iaddr,
                imem_in,
                ohit,
                oins);

   initial begin

      #10;
      rstn = 0;
      
      #10;

      iaddr = 7;
      
      #90;
      imem_in = {32'hDEADBEEF ,32'hABABABAB,
                 32'hCDCDCDCD, 32'hEFEFEFEF};
      #35;
      #180;
      iaddr = 0;

      #50;
      iaddr = 4;

      #50;
      iaddr = 8;

      #50;
      iaddr = 12;

      #50;
      iaddr = 16;

      #150;

      #50;
      iaddr = 20;

      #50;
      iaddr = 24;

      #50;
      iaddr = 28;
      
   end

   initial begin
      clk = 0;
      for (i = 0; i < 64; i = i + 1)
   #25 clk = ~clk;
   end


   initial begin
      $dumpfile("./insCache.vcd");
      $dumpvars;
   end

endmodule