data/full_repos/permissive/133149315/common/rstn_sync.v
data/verilator_xmls/b704149f-03a7-4e40-a353-fcc4a5213914.xml
module rstn_sync(
input  i_clk,
input  i_rstn,
input  i_test_mode,
output o_rstn
);


reg rstn;
always @(posedge i_clk or negedge i_rstn)begin
  if(!i_rstn)
     rstn <= 1'h0;
  else
     rstn <= 1'h1;
end


reg rstn_d;
always @(posedge i_clk or negedge i_rstn)begin
  if(!i_rstn)
     rstn_d <= 1'h0;
  else
     rstn_d <= rstn;
end

assign o_rstn = i_test_mode ? i_rstn : rstn_d;

endmodule
module rstn_sync(
input  i_clk,
input  i_rstn,
input  i_test_mode,
output o_rstn
);



reg rstn;
always @(posedge i_clk or negedge i_rstn)begin
  if(!i_rstn)
     rstn <= 1'h0;
  else
     rstn <= 1'h1;
end


reg rstn_d;
always @(posedge i_clk or negedge i_rstn)begin
  if(!i_rstn)
     rstn_d <= 1'h0;
  else
     rstn_d <= rstn;
end

assign o_rstn = i_test_mode ? i_rstn : rstn_d;

endmodule