data/full_repos/permissive/204736068/SoM/RTL/misc/delay.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/204736068/SoM/RTL/misc/delay.v:70: Multiple top level modules\n                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                               : ... Top module \'delay_bit\'\nmodule delay_bit #(\n       ^~~~~~~~~\n                                                                               : ... Top module \'delay_bus\'\nmodule delay_bus #(\n       ^~~~~~~~~\n                                                                               : ... Top module \'delay_toggle\'\nmodule delay_toggle #(\n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module delay_bit #(
	parameter integer DELAY = 1
)(
	input  wire d,
	output wire q,
	input  wire clk
);

	reg [DELAY-1:0] dl;

	generate
		if (DELAY > 1)
			always @(posedge clk)
				dl <= { dl[DELAY-2:0], d };
		else
			always @(posedge clk)
				dl <= d;
	endgenerate

	assign q = dl[DELAY-1];

endmodule
module delay_bit #(
	parameter integer DELAY = 1
)(
	input  wire d,
	output wire q,
	input  wire clk
);


	reg [DELAY-1:0] dl;

	generate
		if (DELAY > 1)
			always @(posedge clk)
				dl <= { dl[DELAY-2:0], d };
		else
			always @(posedge clk)
				dl <= d;
	endgenerate

	assign q = dl[DELAY-1];

endmodule