data/full_repos/permissive/17099167/system/hardware/cores/adv_debug_sys/Hardware/jtag/cells/rtl/verilog/ControlCell.v
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data/verilator_xmls/5ec6c88e-b191-465a-982d-f9809ecf19a7.xml
module ControlCell( OutputControl, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, ToOutputEnable);
input  OutputControl;
input  FromPreviousBSCell;
input  CaptureDR;
input  ShiftDR;
input  UpdateDR;
input  extest;
input  TCK;

reg Latch;

output ToNextBSCell;
output ToOutputEnable;

reg    ToNextBSCell;
reg ShiftedControl;

wire SelectedInput = CaptureDR? OutputControl : FromPreviousBSCell;

always @ (posedge TCK)
begin
	if(CaptureDR | ShiftDR)
		Latch<=SelectedInput;
end

always @ (negedge TCK)
begin
	ToNextBSCell<=Latch;
end

always @ (negedge TCK)
begin
	if(UpdateDR)
		ShiftedControl<=ToNextBSCell;
end

assign ToOutputEnable = extest? ShiftedControl : OutputControl;

endmodule
module ControlCell( OutputControl, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, ToOutputEnable);

input  OutputControl;
input  FromPreviousBSCell;
input  CaptureDR;
input  ShiftDR;
input  UpdateDR;
input  extest;
input  TCK;

reg Latch;

output ToNextBSCell;
output ToOutputEnable;

reg    ToNextBSCell;
reg ShiftedControl;

wire SelectedInput = CaptureDR? OutputControl : FromPreviousBSCell;

always @ (posedge TCK)
begin
	if(CaptureDR | ShiftDR)
		Latch<=SelectedInput;
end

always @ (negedge TCK)
begin
	ToNextBSCell<=Latch;
end

always @ (negedge TCK)
begin
	if(UpdateDR)
		ShiftedControl<=ToNextBSCell;
end

assign ToOutputEnable = extest? ShiftedControl : OutputControl;

endmodule