data/full_repos/permissive/157696705/brainfuck computer/Register_Bunch.v
1: b'%Error: Cannot find file containing module: computer,data/full_repos/permissive/157696705\n        ... Looked in:\n             data/full_repos/permissive/157696705/brainfuck/computer,data/full_repos/permissive/157696705\n             data/full_repos/permissive/157696705/brainfuck/computer,data/full_repos/permissive/157696705.v\n             data/full_repos/permissive/157696705/brainfuck/computer,data/full_repos/permissive/157696705.sv\n             computer,data/full_repos/permissive/157696705\n             computer,data/full_repos/permissive/157696705.v\n             computer,data/full_repos/permissive/157696705.sv\n             obj_dir/computer,data/full_repos/permissive/157696705\n             obj_dir/computer,data/full_repos/permissive/157696705.v\n             obj_dir/computer,data/full_repos/permissive/157696705.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/157696705/brainfuck\n%Error: Cannot find file containing module: computer/Register_Bunch.v\n%Error: Exiting due to 3 error(s)\n'
module Register_Bunch(
    input               enable, RW,
    input       [9:0]   ADR,
    input       [7:0]   word_in,
    output  reg [7:0]   word_out
);

reg [7:0]    Register[1023:0];
integer i;

always @(posedge RW or negedge RW)
begin
  if(enable)
  begin
    for(i = 0; i < 1024; i = i + 1)
    begin
      Register[i][7:0] = 8'h00;
    end
    if(RW)
    begin
      word_out[7:0] = Register[ADR[9:0]][7:0];
    end
    else
    begin
      Register[ADR[9:0]][7:0] = word_in[7:0];
    end
  end
end
endmodule
module Register_Bunch(
    input               enable, RW,
    input       [9:0]   ADR,
    input       [7:0]   word_in,
    output  reg [7:0]   word_out
);


reg [7:0]    Register[1023:0];
integer i;

always @(posedge RW or negedge RW)
begin
  if(enable)
  begin
    for(i = 0; i < 1024; i = i + 1)
    begin
      Register[i][7:0] = 8'h00;
    end
    if(RW)
    begin
      word_out[7:0] = Register[ADR[9:0]][7:0];
    end
    else
    begin
      Register[ADR[9:0]][7:0] = word_in[7:0];
    end
  end
end
endmodule