data/full_repos/permissive/129155059/proyecto-02/all/testbench.v
 line:1: before: "("
1: b'%Error: data/full_repos/permissive/129155059/proyecto-02/all/testbench.v:1: Cannot find include file: tester.v\n`include "tester.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129155059/proyecto-02/all,data/full_repos/permissive/129155059/tester.v\n             data/full_repos/permissive/129155059/proyecto-02/all,data/full_repos/permissive/129155059/tester.v.v\n             data/full_repos/permissive/129155059/proyecto-02/all,data/full_repos/permissive/129155059/tester.v.sv\n             tester.v\n             tester.v.v\n             tester.v.sv\n             obj_dir/tester.v\n             obj_dir/tester.v.v\n             obj_dir/tester.v.sv\n%Error: data/full_repos/permissive/129155059/proyecto-02/all/testbench.v:2: Cannot find include file: qos_cond.v\n`include "qos_cond.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/all/testbench.v:3: Cannot find include file: qos_synth.v\n`include "qos_synth.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/all/testbench.v:4: Cannot find include file: cmos_cells.v\n`include "cmos_cells.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/129155059/proyecto-02/all/testbench.v:11: syntax error, unexpected wire, expecting IDENTIFIER or do or final\n  wire       enb,\n  ^~~~\n%Error: Exiting due to 5 error(s)\n'
module testbench;

  wire       clk,
  wire       enb,
  wire       reset,
  wire [3:0] Data_Word,
  wire       edit_weight,
  wire [1:0] vc_assign,
  wire [2:0] weight_assign,
  wire       sInit,

  wire [3:0] lectura, escritura,
  wire [2:0] umbralVacio0, umbralLleno0,
  wire [2:0] umbralVacio1, umbralLleno1,
  wire [2:0] umbralVacio2, umbralLleno2,
  wire [2:0] umbralVacio3, umbralLleno3,
  wire      oInit,
  wire      oIdle,
  wire [3:0]oError, stbPause, stbContinue,
  wire [7:0]State, nState

  tester  letest( .weight_assign  (weight_assign_tb),
                  .vc_assign      (vc_assign_tb),
                  .CLK_2MHz       (clk_tb),
                  .reset          (reset_tb),
                  .edit_weight    (edit_weight_tb),
                  .Data_Word      (Data_Word_tb)
  );

  qos_cond conditional();

  qos_synth synthetized();


endmodule
module testbench;


  wire       clk,
  wire       enb,
  wire       reset,
  wire [3:0] Data_Word,
  wire       edit_weight,
  wire [1:0] vc_assign,
  wire [2:0] weight_assign,
  wire       sInit,

  wire [3:0] lectura, escritura,
  wire [2:0] umbralVacio0, umbralLleno0,
  wire [2:0] umbralVacio1, umbralLleno1,
  wire [2:0] umbralVacio2, umbralLleno2,
  wire [2:0] umbralVacio3, umbralLleno3,
  wire      oInit,
  wire      oIdle,
  wire [3:0]oError, stbPause, stbContinue,
  wire [7:0]State, nState

  tester  letest( .weight_assign  (weight_assign_tb),
                  .vc_assign      (vc_assign_tb),
                  .CLK_2MHz       (clk_tb),
                  .reset          (reset_tb),
                  .edit_weight    (edit_weight_tb),
                  .Data_Word      (Data_Word_tb)
  );

  qos_cond conditional();

  qos_synth synthetized();


endmodule