data/full_repos/permissive/136422019/src/inPort.v
data/verilator_xmls/6a860856-bb79-47c6-89cf-91a098e4c169.xml
module inPort(
	output reg[31:0] dataOut,
	input wire[31:0] dataIn,
	input wire clr, clk
);


initial begin
	dataOut <= 0;
end

always @(*) begin
	if(clr == 1)
		dataOut <= 0;
	else
		dataOut <= dataIn;
end

endmodule
module inPort(
	output reg[31:0] dataOut,
	input wire[31:0] dataIn,
	input wire clr, clk
);



initial begin
	dataOut <= 0;
end

always @(*) begin
	if(clr == 1)
		dataOut <= 0;
	else
		dataOut <= dataIn;
end

endmodule