data/full_repos/permissive/173670949/ws2812/bsp.v
1: b"%Error: data/full_repos/permissive/173670949/ws2812/bsp.v:32: Cannot find file containing module: 'Top'\n    Top #(.F_CLK(50_000_000)) top(clk, ws2812_dat, ws2812_done, ws2812_reset);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/173670949/ws2812,data/full_repos/permissive/173670949/Top\n             data/full_repos/permissive/173670949/ws2812,data/full_repos/permissive/173670949/Top.v\n             data/full_repos/permissive/173670949/ws2812,data/full_repos/permissive/173670949/Top.sv\n             Top\n             Top.v\n             Top.sv\n             obj_dir/Top\n             obj_dir/Top.v\n             obj_dir/Top.sv\n%Error: Exiting due to 1 error(s)\n"
module BSP (
    input ICE_CLK,
    output GLED5,
    output RLED1,
    output RLED2,
    output RLED3,
    output RLED4,
    output J3_10
);





    wire clk;
    wire ws2812_dat;
    wire ws2812_done;
    wire ws2812_reset;
    assign clk = ICE_CLK;

    assign J3_10 = ws2812_dat;
    assign GLED5 = ws2812_dat;
    assign RLED1 = 0;
    assign RLED2 = ws2812_done;
    assign RLED3 = ws2812_reset;
    assign RLED4 = 0;

    Top #(.F_CLK(50_000_000)) top(clk, ws2812_dat, ws2812_done, ws2812_reset);

endmodule
module BSP (
    input ICE_CLK,
    output GLED5,
    output RLED1,
    output RLED2,
    output RLED3,
    output RLED4,
    output J3_10
);






    wire clk;
    wire ws2812_dat;
    wire ws2812_done;
    wire ws2812_reset;
    assign clk = ICE_CLK;

    assign J3_10 = ws2812_dat;
    assign GLED5 = ws2812_dat;
    assign RLED1 = 0;
    assign RLED2 = ws2812_done;
    assign RLED3 = ws2812_reset;
    assign RLED4 = 0;

    Top #(.F_CLK(50_000_000)) top(clk, ws2812_dat, ws2812_done, ws2812_reset);

endmodule