data/full_repos/permissive/20759093/test_ctrl.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/20759093/test_ctrl.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: data/full_repos/permissive/20759093/test_ctrl.v:44: Cannot find file containing module: \'control\'\n control uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/control\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/control.v\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/control.sv\n             control\n             control.v\n             control.sv\n             obj_dir/control\n             obj_dir/control.v\n             obj_dir/control.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_ctrl;


	reg [5:0] op;
	reg [5:0] funct;


	wire RegDst;
	wire RegWrite;
	wire ALUSrc;
	wire MemRead;
	wire MemWrite;
	wire MemtoReg;
	wire Jump;
	wire JumpReg;
	wire Branch;
	wire [3:0] ALUCtrl;


	control uut (
		.op(op), 
		.funct(funct), 
		.RegDst(RegDst), 
		.RegWrite(RegWrite), 
		.ALUSrc(ALUSrc), 
		.MemRead(MemRead), 
		.MemWrite(MemWrite), 
		.MemtoReg(MemtoReg), 
		.Jump(Jump), 
		.JumpReg(JumpReg), 
		.Branch(Branch), 
		.ALUCtrl(ALUCtrl)
	);

	initial begin

		op = 0;
		funct = 0;


		#100;
        

		#20;
		op = 6'h08;
		funct = 6'h02;
		#20;
		op = 6'h0C;
		funct = 6'h02;
		#20;
		op = 6'h0D;
		funct = 6'h02;
		#20;
		op = 6'h0E;
		funct = 6'h02;
		#20;
		op = 6'h0F;
		funct = 6'h02;
		#20;
		op = 6'h23;
		funct = 6'h02;
		#20;
		op = 6'h2B;
		funct = 6'h02;
		#20;
		op = 6'h04;
		funct = 6'h02;
		#20;
		op = 6'h05;
		funct = 6'h02;
		#20;
		op = 6'h0A;
		funct = 6'h02;
		#20;
		op = 6'h00;
		funct = 6'h32;
		#20;
		funct = 6'h34;
		#20;
		funct = 6'h36;
		#20;
		funct = 6'h37;
		#20;
		funct = 6'h38;
		#20;
		funct = 6'h39;
		#20;
		funct = 6'h42;
		#20;
		funct = 6'h02;
		#20;
		funct = 6'h00;
		
	end
      
endmodule
module test_ctrl;



	reg [5:0] op;
	reg [5:0] funct;


	wire RegDst;
	wire RegWrite;
	wire ALUSrc;
	wire MemRead;
	wire MemWrite;
	wire MemtoReg;
	wire Jump;
	wire JumpReg;
	wire Branch;
	wire [3:0] ALUCtrl;


	control uut (
		.op(op), 
		.funct(funct), 
		.RegDst(RegDst), 
		.RegWrite(RegWrite), 
		.ALUSrc(ALUSrc), 
		.MemRead(MemRead), 
		.MemWrite(MemWrite), 
		.MemtoReg(MemtoReg), 
		.Jump(Jump), 
		.JumpReg(JumpReg), 
		.Branch(Branch), 
		.ALUCtrl(ALUCtrl)
	);

	initial begin

		op = 0;
		funct = 0;


		#100;
        

		#20;
		op = 6'h08;
		funct = 6'h02;
		#20;
		op = 6'h0C;
		funct = 6'h02;
		#20;
		op = 6'h0D;
		funct = 6'h02;
		#20;
		op = 6'h0E;
		funct = 6'h02;
		#20;
		op = 6'h0F;
		funct = 6'h02;
		#20;
		op = 6'h23;
		funct = 6'h02;
		#20;
		op = 6'h2B;
		funct = 6'h02;
		#20;
		op = 6'h04;
		funct = 6'h02;
		#20;
		op = 6'h05;
		funct = 6'h02;
		#20;
		op = 6'h0A;
		funct = 6'h02;
		#20;
		op = 6'h00;
		funct = 6'h32;
		#20;
		funct = 6'h34;
		#20;
		funct = 6'h36;
		#20;
		funct = 6'h37;
		#20;
		funct = 6'h38;
		#20;
		funct = 6'h39;
		#20;
		funct = 6'h42;
		#20;
		funct = 6'h02;
		#20;
		funct = 6'h00;
		
	end
      
endmodule