data/full_repos/permissive/161526648/mux5bit.v
data/verilator_xmls/e77a8dc1-93db-417a-bdbd-749b2a1f0cab.xml
module mux5bit(src1,src2,sel,result);
	parameter size = 5;
	input [size-1:0] src1,src2;
	input sel;
	output reg [size-1:0] result;
	
	always @(sel,src1,src2) begin
		case (sel) 
			1'b0: result = src1;
			1'b1: result = src2;
		endcase
	end
endmodule
module mux5bit(src1,src2,sel,result);

	parameter size = 5;
	input [size-1:0] src1,src2;
	input sel;
	output reg [size-1:0] result;
	
	always @(sel,src1,src2) begin
		case (sel) 
			1'b0: result = src1;
			1'b1: result = src2;
		endcase
	end
endmodule