data/full_repos/permissive/175808891/verilog/prv32.v
 line:209: before: "("
1: b"%Error: data/full_repos/permissive/175808891/verilog/prv32.v:280: syntax error, unexpected type\n    shifter shifter0(.a(a), .shamt(shamt), .type(alufn[1:0]),  .r(sh));\n                                            ^~~~\n%Error: data/full_repos/permissive/175808891/verilog/prv32.v:310: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    output reg [31:0] do\n                      ^~\n%Error: data/full_repos/permissive/175808891/verilog/prv32.v:315: syntax error, unexpected '='\n        3'b100  : do = {24'b0,di[7:0]};\n                     ^\n%Error: Cannot continue\n"
module prv32_ControlHazardUnit (
	input cf, zf, vf, sf,
	input[2:0] func3,
	input[1:0] ctrl,
	output reg taken
);
	always @ * begin
		taken = 1'b0;
		case (ctrl)
		    2'd0   :   taken = 1'b0;
		    2'd1   :   taken = 1'b1;
		    2'd2   :   taken = 1'b1;
		    2'd3   :   begin
                    		(* full_case *)
                    		(* parallel_case *)
                    		case(func3)
                    			`BR_BEQ :   taken = zf;
                    			`BR_BNE :   taken = ~zf;
                    			`BR_BLT :   taken = (sf != vf);
                    			`BR_BGE :   taken = (sf == vf);
                    			`BR_BLTU:   taken = (~cf);
                    			`BR_BGEU:   taken = (cf);
                    			default :   taken = 1'b0;
                    		endcase
                        end
        endcase
	end
endmodule
module prv32_ControlHazardUnit (
	input cf, zf, vf, sf,
	input[2:0] func3,
	input[1:0] ctrl,
	output reg taken
);

	always @ * begin
		taken = 1'b0;
		case (ctrl)
		    2'd0   :   taken = 1'b0;
		    2'd1   :   taken = 1'b1;
		    2'd2   :   taken = 1'b1;
		    2'd3   :   begin
                    		(* full_case *)
                    		(* parallel_case *)
                    		case(func3)
                    			`BR_BEQ :   taken = zf;
                    			`BR_BNE :   taken = ~zf;
                    			`BR_BLT :   taken = (sf != vf);
                    			`BR_BGE :   taken = (sf == vf);
                    			`BR_BLTU:   taken = (~cf);
                    			`BR_BGEU:   taken = (cf);
                    			default :   taken = 1'b0;
                    		endcase
                        end
        endcase
	end
endmodule