data/full_repos/permissive/202237519/verilog/digitalsystem7/jk.v
1: b'%Error: data/full_repos/permissive/202237519/verilog/digitalsystem7/jk.v:1: Cannot find include file: dff.v\n`include "dff.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/202237519/verilog/digitalsystem7,data/full_repos/permissive/202237519/dff.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem7,data/full_repos/permissive/202237519/dff.v.v\n             data/full_repos/permissive/202237519/verilog/digitalsystem7,data/full_repos/permissive/202237519/dff.v.sv\n             dff.v\n             dff.v.v\n             dff.v.sv\n             obj_dir/dff.v\n             obj_dir/dff.v.v\n             obj_dir/dff.v.sv\n%Error: Exiting due to 1 error(s)\n'
module JK_FF(CLK, set, J, K, Q, nQ);
  input CLK, J, K, set;
  output Q,  nQ;
  wire w1;
  assign w1 = (J & nQ) | (~K & Q);
  D_FF F1(CLK, w1, set, Q, nQ); 
endmodule
module JK_FF(CLK, set, J, K, Q, nQ);

  input CLK, J, K, set;
  output Q,  nQ;
  wire w1;
  assign w1 = (J & nQ) | (~K & Q);
  D_FF F1(CLK, w1, set, Q, nQ); 
endmodule