data/full_repos/permissive/129127690/demux_1_4_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/129127690/demux_1_4_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/129127690/demux_1_4_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129127690/demux_1_4_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/129127690/demux_1_4_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/129127690/demux_1_4_tb.v:16: Cannot find file containing module: \'demux_1_4\'\n demux_1_4 #(.bus_size(bus_size)) uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/demux_1_4\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/demux_1_4.v\n             data/full_repos/permissive/129127690,data/full_repos/permissive/129127690/demux_1_4.sv\n             demux_1_4\n             demux_1_4.v\n             demux_1_4.sv\n             obj_dir/demux_1_4\n             obj_dir/demux_1_4.v\n             obj_dir/demux_1_4.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module demux_1_4_tb #(parameter bus_size = 4);


	reg [1:0] select;
	reg [bus_size-1:0] in;


	wire [bus_size-1:0] a;
	wire [bus_size-1:0] b;
	wire [bus_size-1:0] c;
	wire [bus_size-1:0] d;


	demux_1_4 #(.bus_size(bus_size)) uut (
		.in(in),
		.select(select), 
		.a(a),
		.b(b),
		.c(c),
		.d(d)
	);

	initial begin

		select = 2'b00;
		in = 4'b1010;
		#10
		select = 2'b01;
		in = 4'b1011;
		#10
		select = 2'b10;
		in = 4'b1111;
		#10
		select = 2'b11;
		in = 4'b0001;
		#10;
	end
      
endmodule
module demux_1_4_tb #(parameter bus_size = 4);



	reg [1:0] select;
	reg [bus_size-1:0] in;


	wire [bus_size-1:0] a;
	wire [bus_size-1:0] b;
	wire [bus_size-1:0] c;
	wire [bus_size-1:0] d;


	demux_1_4 #(.bus_size(bus_size)) uut (
		.in(in),
		.select(select), 
		.a(a),
		.b(b),
		.c(c),
		.d(d)
	);

	initial begin

		select = 2'b00;
		in = 4'b1010;
		#10
		select = 2'b01;
		in = 4'b1011;
		#10
		select = 2'b10;
		in = 4'b1111;
		#10
		select = 2'b11;
		in = 4'b0001;
		#10;
	end
      
endmodule