data/full_repos/permissive/199632300/HDLBits/Circuits/Combiantional_Logic/Basic_Gates/mt2015_q4b.v
data/verilator_xmls/1b31e9d6-a15f-4f8f-bd65-c530165567e7.xml
module top_module ( input x, input y, output z );
    assign z = ~(x^y);
endmodule
module top_module ( input x, input y, output z );

    assign z = ~(x^y);
endmodule