data/full_repos/permissive/218103167/code/s5/si570_controller/si570_controller.v
1: b"%Error: data/full_repos/permissive/218103167/code/s5/si570_controller/si570_controller.v:100: Cannot find file containing module: 'i2c_reg_controller'\ni2c_reg_controller u1(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/218103167/code/s5/si570_controller,data/full_repos/permissive/218103167/i2c_reg_controller\n             data/full_repos/permissive/218103167/code/s5/si570_controller,data/full_repos/permissive/218103167/i2c_reg_controller.v\n             data/full_repos/permissive/218103167/code/s5/si570_controller,data/full_repos/permissive/218103167/i2c_reg_controller.sv\n             i2c_reg_controller\n             i2c_reg_controller.v\n             i2c_reg_controller.sv\n             obj_dir/i2c_reg_controller\n             obj_dir/i2c_reg_controller.v\n             obj_dir/i2c_reg_controller.sv\n%Error: data/full_repos/permissive/218103167/code/s5/si570_controller/si570_controller.v:120: Cannot find file containing module: 'initial_config'\ninitial_config initial_config(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218103167/code/s5/si570_controller/si570_controller.v:133: Cannot find file containing module: 'clock_divider'\nclock_divider u3(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218103167/code/s5/si570_controller/si570_controller.v:140: Cannot find file containing module: 'i2c_bus_controller'\ni2c_bus_controller u4 (\n^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module si570_controller (

iCLK,
iRST_n,
iStart,
iFREQ_MODE,
oController_Ready,
I2C_CLK,
I2C_DATA,
oREAD_Data,
oSI570_ONE_CLK_CONFIG_DONE
);









input          iCLK;
input          iRST_n;
input	       iStart;
output         I2C_CLK;
inout          I2C_DATA;
output         oSI570_ONE_CLK_CONFIG_DONE;
output  [7:0]  oREAD_Data;
input   [2:0]  iFREQ_MODE;
output         oController_Ready;




wire [6:0]	slave_addr;
wire [7:0]	byte_addr;
wire [7:0]	byte_data;
wire		 	wr_cmd;
wire [7:0]	oREAD_Data;
wire [2:0]	iFREQ_MODE;
wire 			i2c_control_start;
wire 			i2c_reg_control_start;
wire 			i2c_bus_controller_state;
wire			iINITIAL_ENABLE;
wire 			system_start;
wire 			i2c_clk;
wire			i2c_controller_config_done;
wire			oController_Ready;
wire			initial_start;




i2c_reg_controller u1(

.iCLK(iCLK),
.iRST_n(iRST_n),
.iENABLE(system_start),
.iI2C_CONTROLLER_STATE(i2c_bus_controller_state),
.iFREQ_MODE(iFREQ_MODE),
.oSLAVE_ADDR(slave_addr), 
.oBYTE_ADDR(byte_addr),
.oBYTE_DATA(byte_data),
.oWR_CMD(wr_cmd),
.oStart(i2c_reg_control_start),
.iI2C_CONTROLLER_CONFIG_DONE(i2c_controller_config_done),
.oSI570_ONE_CLK_CONFIG_DONE(oSI570_ONE_CLK_CONFIG_DONE),
.i2c_read_data(oREAD_Data),
.i2c_read_data_rdy(i2c_read_data_rdy),
.oController_Ready(oController_Ready)
);


initial_config initial_config(

.iCLK(iCLK),
.iRST_n(iRST_n),
.oINITIAL_START(initial_start),
.iINITIAL_ENABLE(1'b1)
);



assign system_start = iStart|initial_start;


clock_divider u3(
.iCLK(iCLK),
.iRST_n(iRST_n),
.oCLK_OUT(i2c_clk)
);


i2c_bus_controller u4	(

	.iCLK(i2c_clk),
	.iRST_n(iRST_n),
	.iStart(i2c_reg_control_start),
	.iSlave_addr(slave_addr),
	.iWord_addr(byte_addr),
	.iSequential_read(1'b0),
	.iRead_length(8'd1),
	
	.i2c_clk(I2C_CLK),
	.i2c_data(I2C_DATA),
	.i2c_read_data(oREAD_Data),
	.i2c_read_data_rdy(i2c_read_data_rdy),
	.wr_data(byte_data),
	.wr_cmd(wr_cmd),
   .oSYSTEM_STATE(i2c_bus_controller_state),
	.oCONFIG_DONE(i2c_controller_config_done)
				);


endmodule
module si570_controller (

iCLK,
iRST_n,
iStart,
iFREQ_MODE,
oController_Ready,
I2C_CLK,
I2C_DATA,
oREAD_Data,
oSI570_ONE_CLK_CONFIG_DONE
);










input          iCLK;
input          iRST_n;
input	       iStart;
output         I2C_CLK;
inout          I2C_DATA;
output         oSI570_ONE_CLK_CONFIG_DONE;
output  [7:0]  oREAD_Data;
input   [2:0]  iFREQ_MODE;
output         oController_Ready;




wire [6:0]	slave_addr;
wire [7:0]	byte_addr;
wire [7:0]	byte_data;
wire		 	wr_cmd;
wire [7:0]	oREAD_Data;
wire [2:0]	iFREQ_MODE;
wire 			i2c_control_start;
wire 			i2c_reg_control_start;
wire 			i2c_bus_controller_state;
wire			iINITIAL_ENABLE;
wire 			system_start;
wire 			i2c_clk;
wire			i2c_controller_config_done;
wire			oController_Ready;
wire			initial_start;




i2c_reg_controller u1(

.iCLK(iCLK),
.iRST_n(iRST_n),
.iENABLE(system_start),
.iI2C_CONTROLLER_STATE(i2c_bus_controller_state),
.iFREQ_MODE(iFREQ_MODE),
.oSLAVE_ADDR(slave_addr), 
.oBYTE_ADDR(byte_addr),
.oBYTE_DATA(byte_data),
.oWR_CMD(wr_cmd),
.oStart(i2c_reg_control_start),
.iI2C_CONTROLLER_CONFIG_DONE(i2c_controller_config_done),
.oSI570_ONE_CLK_CONFIG_DONE(oSI570_ONE_CLK_CONFIG_DONE),
.i2c_read_data(oREAD_Data),
.i2c_read_data_rdy(i2c_read_data_rdy),
.oController_Ready(oController_Ready)
);


initial_config initial_config(

.iCLK(iCLK),
.iRST_n(iRST_n),
.oINITIAL_START(initial_start),
.iINITIAL_ENABLE(1'b1)
);



assign system_start = iStart|initial_start;


clock_divider u3(
.iCLK(iCLK),
.iRST_n(iRST_n),
.oCLK_OUT(i2c_clk)
);


i2c_bus_controller u4	(

	.iCLK(i2c_clk),
	.iRST_n(iRST_n),
	.iStart(i2c_reg_control_start),
	.iSlave_addr(slave_addr),
	.iWord_addr(byte_addr),
	.iSequential_read(1'b0),
	.iRead_length(8'd1),
	
	.i2c_clk(I2C_CLK),
	.i2c_data(I2C_DATA),
	.i2c_read_data(oREAD_Data),
	.i2c_read_data_rdy(i2c_read_data_rdy),
	.wr_data(byte_data),
	.wr_cmd(wr_cmd),
   .oSYSTEM_STATE(i2c_bus_controller_state),
	.oCONFIG_DONE(i2c_controller_config_done)
				);


endmodule