data/full_repos/permissive/143278/ivltests/tri2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri2.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri2.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri2.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri2.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri2.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/tri2.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
	wire [15:0] bus;
	reg l_en, s_en;
	integer fails=0;
	long l(.p(bus), .en(l_en));
	short s(.p(bus[7:0]), .en(s_en));
	initial begin


		l_en = 0;
		s_en = 0;
		#10;
		l_en = 1;
		#10;
		$display("s.p = %4x", s.p);
		if (s.p !== 8'haa) fails=1;
		#10;
		l_en = 0;
		s_en = 1;
		#10;
		$display("l.p = %4x", l.p);
		if (l.p !== 16'hzz55) fails=2;
		#10;
		s_en = 0;
		#10;
		if (fails == 0) $display("PASSED");
		else $display("FAILED ",fails);
	end
endmodule
module main;

	wire [15:0] bus;
	reg l_en, s_en;
	integer fails=0;
	long l(.p(bus), .en(l_en));
	short s(.p(bus[7:0]), .en(s_en));
	initial begin


		l_en = 0;
		s_en = 0;
		#10;
		l_en = 1;
		#10;
		$display("s.p = %4x", s.p);
		if (s.p !== 8'haa) fails=1;
		#10;
		l_en = 0;
		s_en = 1;
		#10;
		$display("l.p = %4x", l.p);
		if (l.p !== 16'hzz55) fails=2;
		#10;
		s_en = 0;
		#10;
		if (fails == 0) $display("PASSED");
		else $display("FAILED ",fails);
	end
endmodule