data/full_repos/permissive/114811571/test/samples/mips-cpu/im.v
None: at end of input
data/verilator_xmls/5c15d46e-2f06-43e4-9ed5-20b28ab4c4f7.xml
module im(
		input wire			clk,
		input wire 	[31:0] 	addr,
		output wire [31:0] 	data);

	parameter NMEM = 128;

	parameter IM_DATA = "im_data.txt";

	reg [31:0] mem [0:127];





	assign data = mem[addr[8:2]][31:0];
endmodule
module im(
		input wire			clk,
		input wire 	[31:0] 	addr,
		output wire [31:0] 	data);


	parameter NMEM = 128;

	parameter IM_DATA = "im_data.txt";

	reg [31:0] mem [0:127];





	assign data = mem[addr[8:2]][31:0];
endmodule