data/full_repos/permissive/211878730/atlys/practice/counter4_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/counter4_test.v:21: Unsupported: Ignoring delay on this delayed statement.\n  forever #1 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/211878730/atlys/practice/counter4_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/211878730/atlys/practice/counter4_test.v:12: Cannot find file containing module: \'counter4\'\n counter4 uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/counter4\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/counter4.v\n             data/full_repos/permissive/211878730/atlys/practice,data/full_repos/permissive/211878730/counter4.sv\n             counter4\n             counter4.v\n             counter4.sv\n             obj_dir/counter4\n             obj_dir/counter4.v\n             obj_dir/counter4.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter4_test;


	reg clk;


	reg [1:0] count;


	counter4 uut (
		.clk(clk), 
		.count(count)
	);

	initial begin

		clk = 0;
		count = 0;
		forever #1 clk = ~clk;

		#1;
        


	end
      
endmodule
module counter4_test;



	reg clk;


	reg [1:0] count;


	counter4 uut (
		.clk(clk), 
		.count(count)
	);

	initial begin

		clk = 0;
		count = 0;
		forever #1 clk = ~clk;

		#1;
        


	end
      
endmodule