data/full_repos/permissive/143278/ivltests/pr1909940b.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr1909940b.v:6: Unsupported: Ignoring delay on this delayed statement.\n  initial #1 if (out == 1\'b1) $display("PASSED"); else $display("FAILED");\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/143278/ivltests/pr1909940b.v:4: Signal definition not found, creating implicitly: \'in\'\n  assign out = ~in;\n                ^~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  wire out;

  assign out = ~in;
  zero zzz(in);
  initial #1 if (out == 1'b1) $display("PASSED"); else $display("FAILED");
endmodule
module top;

  wire out;

  assign out = ~in;
  zero zzz(in);
  initial #1 if (out == 1'b1) $display("PASSED"); else $display("FAILED");
endmodule