data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Error: data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v:21: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("priority-arbiter-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v:22: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, priority_arbiter_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = ~CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #15; {REQ_2, REQ_1, REQ_0} = 3\'b001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #20; {REQ_2, REQ_1, REQ_0} = 3\'b010;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #20; {REQ_2, REQ_1, REQ_0} = 3\'b011;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #20; {REQ_2, REQ_1, REQ_0} = 3\'b100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #20; {REQ_2, REQ_1, REQ_0} = 3\'b101;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #20; {REQ_2, REQ_1, REQ_0} = 3\'b110;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #20; {REQ_2, REQ_1, REQ_0} = 3\'b111;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #20  RST = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/sequential-logic/arbiters/priority-arbiter/priority-arbiter-tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module priority_arbiter_tb;


reg  CLK, RST;
reg  REQ_0, REQ_1, REQ_2;
wire GNT_0, GNT_1, GNT_2;


priority_arbiter uut(
    .clk(CLK), .rst(RST),
    .req_0(REQ_0), .req_1(REQ_1), .req_2(REQ_2),
    .gnt_0(GNT_0), .gnt_1(GNT_1), .gnt_2(GNT_2)
);


initial begin
    $dumpfile("priority-arbiter-tb.vcd");
    $dumpvars(0, priority_arbiter_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    RST = 0;
    {REQ_2, REQ_1, REQ_0} = 3'b000;
    
    #15; {REQ_2, REQ_1, REQ_0} = 3'b001;
    #20; {REQ_2, REQ_1, REQ_0} = 3'b010;
    #20; {REQ_2, REQ_1, REQ_0} = 3'b011;
    #20; {REQ_2, REQ_1, REQ_0} = 3'b100;
    #20; {REQ_2, REQ_1, REQ_0} = 3'b101;
    #20; {REQ_2, REQ_1, REQ_0} = 3'b110;
    #20; {REQ_2, REQ_1, REQ_0} = 3'b111;
    #20  RST = 1;
    #20

    $display("test complete");
    $finish;
end

endmodule
module priority_arbiter_tb;



reg  CLK, RST;
reg  REQ_0, REQ_1, REQ_2;
wire GNT_0, GNT_1, GNT_2;


priority_arbiter uut(
    .clk(CLK), .rst(RST),
    .req_0(REQ_0), .req_1(REQ_1), .req_2(REQ_2),
    .gnt_0(GNT_0), .gnt_1(GNT_1), .gnt_2(GNT_2)
);


initial begin
    $dumpfile("priority-arbiter-tb.vcd");
    $dumpvars(0, priority_arbiter_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    RST = 0;
    {REQ_2, REQ_1, REQ_0} = 3'b000;
    
    #15; {REQ_2, REQ_1, REQ_0} = 3'b001;
    #20; {REQ_2, REQ_1, REQ_0} = 3'b010;
    #20; {REQ_2, REQ_1, REQ_0} = 3'b011;
    #20; {REQ_2, REQ_1, REQ_0} = 3'b100;
    #20; {REQ_2, REQ_1, REQ_0} = 3'b101;
    #20; {REQ_2, REQ_1, REQ_0} = 3'b110;
    #20; {REQ_2, REQ_1, REQ_0} = 3'b111;
    #20  RST = 1;
    #20

    $display("test complete");
    $finish;
end

endmodule