data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl/edge_detector.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/175070965/lib/AMBA/COMMON/rtl/edge_detector.v:83: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                              : ... Top module \'rising_edge_detector\'\nmodule rising_edge_detector(\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'falling_edge_detector\'\nmodule falling_edge_detector(\n       ^~~~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'rising_edge_detector_with_dataout\'\nmodule rising_edge_detector_with_dataout(\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'falling_edge_detector_with_dataout\'\nmodule falling_edge_detector_with_dataout(\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                              : ... Top module \'edge_detector\'\nmodule edge_detector(\n       ^~~~~~~~~~~~~\n                                                                                              : ... Top module \'edge_detector_with_dataout\'\nmodule edge_detector_with_dataout(\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module falling_edge_detector_with_dataout(
    input wire clk,
    input wire nRST,
    input wire enable,
    input wire DataIn,
    output wire DataOut,
    output reg falling_edge
);

reg prev_value;

always @(posedge clk or negedge nRST) begin
    if(nRST == 1'b0) begin
        prev_value <= 1'b0;
    end else begin
        if(enable == 1'b1) begin
            prev_value <= DataIn;
        end else begin
            prev_value <= 1'b0;
        end
    end
end

always @* begin
    if((prev_value == 1'b1) && (DataIn == 1'b0) && (enable == 1'b1)) begin
        falling_edge = 1'b1;
    end else begin
        falling_edge = 1'b0;
    end
end

assign DataOut = falling_edge;

endmodule
module falling_edge_detector_with_dataout(
    input wire clk,
    input wire nRST,
    input wire enable,
    input wire DataIn,
    output wire DataOut,
    output reg falling_edge
);


reg prev_value;

always @(posedge clk or negedge nRST) begin
    if(nRST == 1'b0) begin
        prev_value <= 1'b0;
    end else begin
        if(enable == 1'b1) begin
            prev_value <= DataIn;
        end else begin
            prev_value <= 1'b0;
        end
    end
end

always @* begin
    if((prev_value == 1'b1) && (DataIn == 1'b0) && (enable == 1'b1)) begin
        falling_edge = 1'b1;
    end else begin
        falling_edge = 1'b0;
    end
end

assign DataOut = falling_edge;

endmodule