data/full_repos/permissive/156129873/verilog/pc.v
1: b'%Error: data/full_repos/permissive/156129873/verilog/pc.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.v\n             data/full_repos/permissive/156129873/verilog,data/full_repos/permissive/156129873/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:33: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:33: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if (rst == `RstEnable) begin\n                       ^\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:36: Define or directive not defined: \'`Disable\'\n   MMU_pause <= `Disable;\n                ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   MMU_pause <= `Disable;\n                        ^\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:40: Define or directive not defined: \'`Enable\'\n   if (pause == `Enable) MMU_pause <= `Enable;\n                ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:40: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   if (pause == `Enable) MMU_pause <= `Enable;\n                       ^\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:40: Define or directive not defined: \'`Enable\'\n   if (pause == `Enable) MMU_pause <= `Enable;\n                                      ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:41: Define or directive not defined: \'`Disable\'\n   else MMU_pause <= `Disable;\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:42: Define or directive not defined: \'`Enable\'\n   if (branchFlag_i == `Enable) branchPC <= branchPC_i;\n                       ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:42: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   if (branchFlag_i == `Enable) branchPC <= branchPC_i;\n                              ^\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:49: Define or directive not defined: \'`Enable\'\n  if (vmem_pause_i == `Enable || pause == `Enable) nextPC = pc;\n                      ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:49: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n  if (vmem_pause_i == `Enable || pause == `Enable) nextPC = pc;\n                              ^~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:49: Define or directive not defined: \'`Enable\'\n  if (vmem_pause_i == `Enable || pause == `Enable) nextPC = pc;\n                                          ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:52: Define or directive not defined: \'`Enable\'\n    if (branchFlag_i == `Enable) begin\n                        ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if (branchFlag_i == `Enable) begin\n                               ^\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:53: Define or directive not defined: \'`Enable\'\n     if (vmem_pause_i == `Enable || pause == `Enable) begin\n                         ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:53: Define or directive not defined: \'`Enable\'\n     if (vmem_pause_i == `Enable || pause == `Enable) begin\n                                             ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:60: Define or directive not defined: \'`Enable\'\n    else if (vmem_pause_i == `Enable || pause == `Enable)\n                             ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:60: Define or directive not defined: \'`Enable\'\n    else if (vmem_pause_i == `Enable || pause == `Enable)\n                                                 ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:65: Define or directive not defined: \'`Enable\'\n    if (vmem_pause_i == `Enable || pause == `Enable)\n                        ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:65: Define or directive not defined: \'`Enable\'\n    if (vmem_pause_i == `Enable || pause == `Enable)\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:73: Define or directive not defined: \'`Enable\'\n    if (branchFlag_i == `Enable) begin\n                        ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:74: Define or directive not defined: \'`Enable\'\n     if (vmem_pause_i == `Enable || pause == `Enable)\n                         ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:74: Define or directive not defined: \'`Enable\'\n     if (vmem_pause_i == `Enable || pause == `Enable)\n                                             ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:77: Define or directive not defined: \'`Enable\'\n    end else if (vmem_pause_i == `Enable || pause == `Enable)\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/156129873/verilog/pc.v:77: Define or directive not defined: \'`Enable\'\n    end else if (vmem_pause_i == `Enable || pause == `Enable)\n                                                     ^~~~~~~\n%Error: Cannot continue\n'
module pc(
    input wire clk,
    input wire rst,
    input wire pause,
    input wire branchFlag_i,
    input wire[15:0] branchPC_i,


    input wire vmem_pause_i,
    
    output reg[15:0] pc,
	 output reg[6:0] disp0,
	 output reg[6:0] disp1,
	 

	 output reg MMU_pause
    );

	reg[2:0] pause_state;
	reg[2:0] next_pause_state;
	reg[15:0] branchPC;
	reg[15:0] nextPC;

	`define NORMAL 3'b000
	`define PAUSE 3'b001
	`define BRANCH 3'b010
	`define D_BRANCH 3'b011
	`define DELAY 3'b100

	always @(posedge clk) begin
		if (rst == `RstEnable) begin
			pc <= 16'h0000;
			pause_state <= `NORMAL;
			MMU_pause <= `Disable;
		end else begin
			pause_state <= next_pause_state;
			pc <= nextPC;
			if (pause == `Enable) MMU_pause <= `Enable;
			else MMU_pause <= `Disable;
			if (branchFlag_i == `Enable) branchPC <= branchPC_i;
			else branchPC <= branchPC;
		end
	end

	always @(*) begin
		nextPC = pc + 1;
		if (vmem_pause_i == `Enable || pause == `Enable) nextPC = pc;
		case (pause_state)
			`NORMAL: begin
				if (branchFlag_i == `Enable) begin
					if (vmem_pause_i == `Enable || pause == `Enable) begin
						next_pause_state = `BRANCH;
					end else begin
						nextPC = branchPC_i;
						next_pause_state = `NORMAL;
					end
				end
				else if (vmem_pause_i == `Enable || pause == `Enable)
					next_pause_state = `PAUSE;
				else next_pause_state = `NORMAL;
			end
			`BRANCH: begin
				if (vmem_pause_i == `Enable || pause == `Enable)
					next_pause_state = `BRANCH;
				else begin
					nextPC = branchPC;
					next_pause_state = `NORMAL;
				end
			end
			`PAUSE: begin
				if (branchFlag_i == `Enable) begin
					if (vmem_pause_i == `Enable || pause == `Enable)
						next_pause_state = `D_BRANCH;
					else next_pause_state = `DELAY;
				end else if (vmem_pause_i == `Enable || pause == `Enable)
					next_pause_state = `PAUSE;
				else
					next_pause_state = `NORMAL;
			end
			`D_BRANCH: begin
				next_pause_state = `DELAY;
			end
			`DELAY: begin
				nextPC = branchPC;
				next_pause_state = `NORMAL;
			end
			default: next_pause_state = `NORMAL;
		endcase
	end


	`define D0 7'b0111111
	`define D1 7'b0000110
	`define D2 7'b1011011
	`define D3 7'b1001111
	`define D4 7'b1100110
	`define D5 7'b1101101
	`define D6 7'b1111101
	`define D7 7'b0000111
	`define D8 7'b1111111
	`define D9 7'b1101111
	`define DA 7'b0000001
	`define DB 7'b0000010
	`define DC 7'b0000100
	`define DD 7'b0001000
	`define DE 7'b0010000
	`define DF 7'b0100000
	`define DNull 7'b0000000
	 
	 always @(*) begin
		case (nextPC[3:0])
			4'd0: disp0 = `D0;
			4'd1: disp0 = `D1;
			4'd2: disp0 = `D2;
			4'd3: disp0 = `D3;
			4'd4: disp0 = `D4;
			4'd5: disp0 = `D5;
			4'd6: disp0 = `D6;
			4'd7: disp0 = `D7;
			4'd8: disp0 = `D8;
			4'd9: disp0 = `D9;
			4'd10: disp0 = `DA;
			4'd11: disp0 = `DB;
			4'd12: disp0 = `DC;
			4'd13: disp0 = `DD;
			4'd14: disp0 = `DE;
			4'd15: disp0 = `DF;
			default: disp0 = `DNull;
		endcase
		case (nextPC[7:4])
			4'd0: disp1 = `D0;
			4'd1: disp1 = `D1;
			4'd2: disp1 = `D2;
			4'd3: disp1 = `D3;
			4'd4: disp1 = `D4;
			4'd5: disp1 = `D5;
			4'd6: disp1 = `D6;
			4'd7: disp1 = `D7;
			4'd8: disp1 = `D8;
			4'd9: disp1 = `D9;
			4'd10: disp1 = `DA;
			4'd11: disp1 = `DB;
			4'd12: disp1 = `DC;
			4'd13: disp1 = `DD;
			4'd14: disp1 = `DE;
			4'd15: disp1 = `DF;
			default: disp1 = `DNull;
		endcase
	 end

endmodule
module pc(
    input wire clk,
    input wire rst,
    input wire pause,
    input wire branchFlag_i,
    input wire[15:0] branchPC_i,


    input wire vmem_pause_i,
    
    output reg[15:0] pc,
	 output reg[6:0] disp0,
	 output reg[6:0] disp1,
	 

	 output reg MMU_pause
    );


	reg[2:0] pause_state;
	reg[2:0] next_pause_state;
	reg[15:0] branchPC;
	reg[15:0] nextPC;

	`define NORMAL 3'b000
	`define PAUSE 3'b001
	`define BRANCH 3'b010
	`define D_BRANCH 3'b011
	`define DELAY 3'b100

	always @(posedge clk) begin
		if (rst == `RstEnable) begin
			pc <= 16'h0000;
			pause_state <= `NORMAL;
			MMU_pause <= `Disable;
		end else begin
			pause_state <= next_pause_state;
			pc <= nextPC;
			if (pause == `Enable) MMU_pause <= `Enable;
			else MMU_pause <= `Disable;
			if (branchFlag_i == `Enable) branchPC <= branchPC_i;
			else branchPC <= branchPC;
		end
	end

	always @(*) begin
		nextPC = pc + 1;
		if (vmem_pause_i == `Enable || pause == `Enable) nextPC = pc;
		case (pause_state)
			`NORMAL: begin
				if (branchFlag_i == `Enable) begin
					if (vmem_pause_i == `Enable || pause == `Enable) begin
						next_pause_state = `BRANCH;
					end else begin
						nextPC = branchPC_i;
						next_pause_state = `NORMAL;
					end
				end
				else if (vmem_pause_i == `Enable || pause == `Enable)
					next_pause_state = `PAUSE;
				else next_pause_state = `NORMAL;
			end
			`BRANCH: begin
				if (vmem_pause_i == `Enable || pause == `Enable)
					next_pause_state = `BRANCH;
				else begin
					nextPC = branchPC;
					next_pause_state = `NORMAL;
				end
			end
			`PAUSE: begin
				if (branchFlag_i == `Enable) begin
					if (vmem_pause_i == `Enable || pause == `Enable)
						next_pause_state = `D_BRANCH;
					else next_pause_state = `DELAY;
				end else if (vmem_pause_i == `Enable || pause == `Enable)
					next_pause_state = `PAUSE;
				else
					next_pause_state = `NORMAL;
			end
			`D_BRANCH: begin
				next_pause_state = `DELAY;
			end
			`DELAY: begin
				nextPC = branchPC;
				next_pause_state = `NORMAL;
			end
			default: next_pause_state = `NORMAL;
		endcase
	end


	`define D0 7'b0111111
	`define D1 7'b0000110
	`define D2 7'b1011011
	`define D3 7'b1001111
	`define D4 7'b1100110
	`define D5 7'b1101101
	`define D6 7'b1111101
	`define D7 7'b0000111
	`define D8 7'b1111111
	`define D9 7'b1101111
	`define DA 7'b0000001
	`define DB 7'b0000010
	`define DC 7'b0000100
	`define DD 7'b0001000
	`define DE 7'b0010000
	`define DF 7'b0100000
	`define DNull 7'b0000000
	 
	 always @(*) begin
		case (nextPC[3:0])
			4'd0: disp0 = `D0;
			4'd1: disp0 = `D1;
			4'd2: disp0 = `D2;
			4'd3: disp0 = `D3;
			4'd4: disp0 = `D4;
			4'd5: disp0 = `D5;
			4'd6: disp0 = `D6;
			4'd7: disp0 = `D7;
			4'd8: disp0 = `D8;
			4'd9: disp0 = `D9;
			4'd10: disp0 = `DA;
			4'd11: disp0 = `DB;
			4'd12: disp0 = `DC;
			4'd13: disp0 = `DD;
			4'd14: disp0 = `DE;
			4'd15: disp0 = `DF;
			default: disp0 = `DNull;
		endcase
		case (nextPC[7:4])
			4'd0: disp1 = `D0;
			4'd1: disp1 = `D1;
			4'd2: disp1 = `D2;
			4'd3: disp1 = `D3;
			4'd4: disp1 = `D4;
			4'd5: disp1 = `D5;
			4'd6: disp1 = `D6;
			4'd7: disp1 = `D7;
			4'd8: disp1 = `D8;
			4'd9: disp1 = `D9;
			4'd10: disp1 = `DA;
			4'd11: disp1 = `DB;
			4'd12: disp1 = `DC;
			4'd13: disp1 = `DD;
			4'd14: disp1 = `DE;
			4'd15: disp1 = `DF;
			default: disp1 = `DNull;
		endcase
	 end

endmodule