data/full_repos/permissive/167489907/Testbenches/CLA_adder64bit_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/CLA_adder64bit_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/CLA_adder64bit_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/CLA_adder64bit_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/167489907/Testbenches/CLA_adder64bit_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10; $stop;\n ^\n%Error: data/full_repos/permissive/167489907/Testbenches/CLA_adder64bit_tb.v:7: Cannot find file containing module: \'CLA_adder64bit\'\nCLA_adder64bit uut (.A(A), .B(B), .S(S), .CF(CF));\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/167489907/Testbenches,data/full_repos/permissive/167489907/CLA_adder64bit\n             data/full_repos/permissive/167489907/Testbenches,data/full_repos/permissive/167489907/CLA_adder64bit.v\n             data/full_repos/permissive/167489907/Testbenches,data/full_repos/permissive/167489907/CLA_adder64bit.sv\n             CLA_adder64bit\n             CLA_adder64bit.v\n             CLA_adder64bit.sv\n             obj_dir/CLA_adder64bit\n             obj_dir/CLA_adder64bit.v\n             obj_dir/CLA_adder64bit.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CLA_adder64bit_tb;

reg [63:0] A, B;
wire [63:0] S;
wire CF;

CLA_adder64bit uut (.A(A), .B(B), .S(S), .CF(CF));

initial begin
	#10;
	A = 64'hFFFF0000FFFF0000;
	B = 64'h00000000FFFFFFFF;
	#10;
	A = 64'hC4C4C4C4C4C4C4C4;
	B = 64'h0111111111111111;
	#10;
	A = 64'hFFFFFFFFFFFFFFFF;
	B = 64'h0000000000000001;
	#10; $stop;
end
endmodule
module CLA_adder64bit_tb;


reg [63:0] A, B;
wire [63:0] S;
wire CF;

CLA_adder64bit uut (.A(A), .B(B), .S(S), .CF(CF));

initial begin
	#10;
	A = 64'hFFFF0000FFFF0000;
	B = 64'h00000000FFFFFFFF;
	#10;
	A = 64'hC4C4C4C4C4C4C4C4;
	B = 64'h0111111111111111;
	#10;
	A = 64'hFFFFFFFFFFFFFFFF;
	B = 64'h0000000000000001;
	#10; $stop;
end
endmodule