data/full_repos/permissive/210844779/lab4/4.3.1/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/210844779/lab4/4.3.1/tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab4/4.3.1/tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/210844779/lab4/4.3.1/tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: data/full_repos/permissive/210844779/lab4/4.3.1/tb.v:6: Cannot find file containing module: \'mem\'\n  mem u0(d,clk,addr,we,q);\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/210844779/lab4/4.3.1,data/full_repos/permissive/210844779/mem\n             data/full_repos/permissive/210844779/lab4/4.3.1,data/full_repos/permissive/210844779/mem.v\n             data/full_repos/permissive/210844779/lab4/4.3.1,data/full_repos/permissive/210844779/mem.sv\n             mem\n             mem.v\n             mem.sv\n             obj_dir/mem\n             obj_dir/mem.v\n             obj_dir/mem.sv\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab4/4.3.1/tb.v:18: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                       : ... In instance tb\n    d=$random;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab4/4.3.1/tb.v:19: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                       : ... In instance tb\n    addr=$random;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/210844779/lab4/4.3.1/tb.v:20: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                       : ... In instance tb\n    we=$random;\n      ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
  reg [3:0]d,addr;
  reg clk,we;
  wire [3:0]q;
  
  mem u0(d,clk,addr,we,q);
  
  always
  begin
    clk=0;
    #5
    clk=1;
    #5;
  end
  
  always
  begin
    d=$random;
    addr=$random;
    we=$random;
    #10;
  end
  
endmodule
module tb();

  reg [3:0]d,addr;
  reg clk,we;
  wire [3:0]q;
  
  mem u0(d,clk,addr,we,q);
  
  always
  begin
    clk=0;
    #5
    clk=1;
    #5;
  end
  
  always
  begin
    d=$random;
    addr=$random;
    we=$random;
    #10;
  end
  
endmodule