data/full_repos/permissive/161526648/Adder_32b.v
data/verilator_xmls/b0ea9670-a4ee-4397-9b84-263d3c9534d1.xml
module Adder_32b(A,B,C);
   input [31:0] A,B;
	output [31:0] C;
   assign C=A+B;
endmodule
module Adder_32b(A,B,C);

   input [31:0] A,B;
	output [31:0] C;
   assign C=A+B;
endmodule