data/full_repos/permissive/146479393/RTL/Freq_Divider.v
 line:40: before: "("
1: b'%Warning-WIDTH: data/full_repos/permissive/146479393/RTL/Freq_Divider.v:28: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'counter\' generates 3 bits.\n                                                                          : ... In instance Freq_Divider\n    if (counter == max-1)\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Freq_Divider#(
  parameter sys_clk = 50000000,
				clk_out = 5000000
							)
  (Clk_in, Clk_out);


  input wire Clk_in;


  output reg Clk_out;
  
	 initial begin
	 Clk_out=1'b0;
  end


  parameter max = sys_clk / (2*clk_out);

  localparam N=log2(max);

  reg [N-1:0]counter = 0;

  always@(posedge Clk_in) begin
    if (counter == max-1)
      begin
        counter <= 0;
        Clk_out <= ~Clk_out;
      end
    else
      begin
        counter <= counter + 1'd1;
      end
  end


  function integer log2(input integer n);
    integer i;
    begin
      log2=1;
      for (i=0; 2**i < n; i=i+1)
        log2=i+1;
    end

  endfunction

endmodule
module Freq_Divider#(
  parameter sys_clk = 50000000,
				clk_out = 5000000
							)
  (Clk_in, Clk_out);



  input wire Clk_in;


  output reg Clk_out;
  
	 initial begin
	 Clk_out=1'b0;
  end


  parameter max = sys_clk / (2*clk_out);

  localparam N=log2(max);

  reg [N-1:0]counter = 0;

  always@(posedge Clk_in) begin
    if (counter == max-1)
      begin
        counter <= 0;
        Clk_out <= ~Clk_out;
      end
    else
      begin
        counter <= counter + 1'd1;
      end
  end


  function integer log2(input integer n);
    integer i;
    begin
      log2=1;
      for (i=0; 2**i < n; i=i+1)
        log2=i+1;
    end

  endfunction

endmodule