data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v
None: at end of input
1: b'%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:15: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(net_1, net_2, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:16: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_1, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:17: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(gnd, y, net_2);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:18: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(net_2, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:19: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_2, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:20: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, vdd, net_2);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:32: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_3, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:33: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_4, ab);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:34: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_3, y, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:35: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(net_4, y, bb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:36: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(gnd, bb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:37: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, ab, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:38: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_0(y, net_7, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:39: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(net_7, vdd, ab);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:40: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(y, net_8, bb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:41: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_8, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:42: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(bb, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:43: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(ab, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:70: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_0(gnd, net_1, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:71: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_1(gnd, net_1, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:72: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_2(net_1, coutb, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:73: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_3(gnd, net_11, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:74: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_4(net_11, coutb, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:75: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_5(gnd, net_23, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:76: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_6(gnd, net_23, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:77: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_7(gnd, net_23, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:78: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_8(net_23, sb, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:79: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_9(gnd, net_33, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:80: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_10(net_33, net_32, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:81: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_11(net_32, sb, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:82: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_12(gnd, cout, coutb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:83: Unsupported: Verilog 1995 gate primitive: tranif1\n  tranif1 nmos_13(gnd, s, sb);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:84: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_1(sb, net_92, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:85: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_2(net_92, net_90, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:86: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_3(net_90, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:87: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_4(sb, net_94, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:88: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_5(net_94, vdd, b);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:89: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_6(net_94, vdd, c);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:90: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_7(net_94, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:91: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_8(cout, vdd, coutb);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:92: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_9(net_95, vdd, a);\n          ^~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:93: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_10(coutb, net_95, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:94: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_11(net_111, vdd, a);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:95: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_12(net_111, vdd, b);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:96: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_13(coutb, net_111, c);\n          ^~~~~~~\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/CPA/CPA.v:97: Unsupported: Verilog 1995 gate primitive: tranif0\n  tranif0 pmos_14(s, vdd, sb);\n          ^~~~~~~\n%Error: Exiting due to 46 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPA(a0, a1, a10, a11, a12, a2, a3, a4, a5, a6, a7, a8, a9, b0, b1, b10, 
      b11, b12, b2, b3, b4, b5, b6, b7, b8, b9, cout, overflow, s0, s1, s10, 
      s11, s12, s2, s3, s4, s5, s6, s7, s8, s9);
      
  input a0;
  input a1;
  input a10;
  input a11;
  input a12;
  input a2;
  input a3;
  input a4;
  input a5;
  input a6;
  input a7;
  input a8;
  input a9;
  input b0;
  input b1;
  input b10;
  input b11;
  input b12;
  input b2;
  input b3;
  input b4;
  input b5;
  input b6;
  input b7;
  input b8;
  input b9;
  output cout;
  output overflow;
  output s0;
  output s1;
  output s10;
  output s11;
  output s12;
  output s2;
  output s3;
  output s4;
  output s5;
  output s6;
  output s7;
  output s8;
  output s9;

  supply1 vdd;
  supply0 gnd;
  wire net_0, net_1, net_10, net_11, net_2, net_3, net_4, net_5, net_6, net_7;
  wire net_8, net_9;

  wordlib8__HalfAdder HalfAdde_0(.a(a0), .b(b0), .Cout(net_0), .s(s0));
  muddlib07__fulladder fulladde_0(.a(a1), .b(b1), .c(net_0), .cout(net_1), 
      .s(s1));
  muddlib07__fulladder fulladde_1(.a(a2), .b(b2), .c(net_1), .cout(net_2), 
      .s(s2));
  muddlib07__fulladder fulladde_2(.a(a3), .b(b3), .c(net_2), .cout(net_3), 
      .s(s3));
  muddlib07__fulladder fulladde_3(.a(a4), .b(b4), .c(net_3), .cout(net_4), 
      .s(s4));
  muddlib07__fulladder fulladde_4(.a(a5), .b(b5), .c(net_4), .cout(net_5), 
      .s(s5));
  muddlib07__fulladder fulladde_5(.a(a6), .b(b6), .c(net_5), .cout(net_6), 
      .s(s6));
  muddlib07__fulladder fulladde_6(.a(a7), .b(b7), .c(net_6), .cout(net_7), 
      .s(s7));
  muddlib07__fulladder fulladde_7(.a(a8), .b(b8), .c(net_7), .cout(net_8), 
      .s(s8));
  muddlib07__fulladder fulladde_8(.a(a9), .b(b9), .c(net_8), .cout(net_9), 
      .s(s9));
  muddlib07__fulladder fulladde_9(.a(a10), .b(b10), .c(net_9), .cout(net_10), 
      .s(s10));
  muddlib07__fulladder fulladde_10(.a(a11), .b(b11), .c(net_10), .cout(net_11), 
      .s(s11));
  muddlib07__fulladder fulladde_11(.a(a12), .b(b12), .c(net_11), .cout(cout), 
      .s(s12));
  muddlib07__xor2_1x xor2_1x_0(.a(net_11), .b(cout), .y(overflow));
endmodule
module CPA(a0, a1, a10, a11, a12, a2, a3, a4, a5, a6, a7, a8, a9, b0, b1, b10, 
      b11, b12, b2, b3, b4, b5, b6, b7, b8, b9, cout, overflow, s0, s1, s10, 
      s11, s12, s2, s3, s4, s5, s6, s7, s8, s9);

      
  input a0;
  input a1;
  input a10;
  input a11;
  input a12;
  input a2;
  input a3;
  input a4;
  input a5;
  input a6;
  input a7;
  input a8;
  input a9;
  input b0;
  input b1;
  input b10;
  input b11;
  input b12;
  input b2;
  input b3;
  input b4;
  input b5;
  input b6;
  input b7;
  input b8;
  input b9;
  output cout;
  output overflow;
  output s0;
  output s1;
  output s10;
  output s11;
  output s12;
  output s2;
  output s3;
  output s4;
  output s5;
  output s6;
  output s7;
  output s8;
  output s9;

  supply1 vdd;
  supply0 gnd;
  wire net_0, net_1, net_10, net_11, net_2, net_3, net_4, net_5, net_6, net_7;
  wire net_8, net_9;

  wordlib8__HalfAdder HalfAdde_0(.a(a0), .b(b0), .Cout(net_0), .s(s0));
  muddlib07__fulladder fulladde_0(.a(a1), .b(b1), .c(net_0), .cout(net_1), 
      .s(s1));
  muddlib07__fulladder fulladde_1(.a(a2), .b(b2), .c(net_1), .cout(net_2), 
      .s(s2));
  muddlib07__fulladder fulladde_2(.a(a3), .b(b3), .c(net_2), .cout(net_3), 
      .s(s3));
  muddlib07__fulladder fulladde_3(.a(a4), .b(b4), .c(net_3), .cout(net_4), 
      .s(s4));
  muddlib07__fulladder fulladde_4(.a(a5), .b(b5), .c(net_4), .cout(net_5), 
      .s(s5));
  muddlib07__fulladder fulladde_5(.a(a6), .b(b6), .c(net_5), .cout(net_6), 
      .s(s6));
  muddlib07__fulladder fulladde_6(.a(a7), .b(b7), .c(net_6), .cout(net_7), 
      .s(s7));
  muddlib07__fulladder fulladde_7(.a(a8), .b(b8), .c(net_7), .cout(net_8), 
      .s(s8));
  muddlib07__fulladder fulladde_8(.a(a9), .b(b9), .c(net_8), .cout(net_9), 
      .s(s9));
  muddlib07__fulladder fulladde_9(.a(a10), .b(b10), .c(net_9), .cout(net_10), 
      .s(s10));
  muddlib07__fulladder fulladde_10(.a(a11), .b(b11), .c(net_10), .cout(net_11), 
      .s(s11));
  muddlib07__fulladder fulladde_11(.a(a12), .b(b12), .c(net_11), .cout(cout), 
      .s(s12));
  muddlib07__xor2_1x xor2_1x_0(.a(net_11), .b(cout), .y(overflow));
endmodule