data/full_repos/permissive/143597583/rtl/verilog/up_conv.v
data/verilator_xmls/2d0495ab-a643-43ab-b8a8-1ccf772ae102.xml
module up_conv # (
  parameter ntaps = 32
)
(

  input wire clk,
  input wire rst,

  input wire [15:0] x_a_i,
  input wire [15:0] x_b_i,
  input wire x_valid_i,
  output wire x_ready_o,

  output wire [15:0] y_a_o,
  output wire [15:0] y_b_o,
  output wire y_valid_o,
  input wire y_ready_i
);

	reg [7:0] cntr;

	always @(posedge clk) begin
		if (rst) begin
			cntr <= 0;
		end
		else if (y_ready_i) begin
			cntr <= cntr + 1;
		end
	end

	assign y_a_o = (cntr[2:0] == 0) ? x_a_i : 0;
	assign y_b_o = (cntr[2:0] == 0) ? x_b_i : 0;
	assign x_ready_o = (cntr[2:0] == 0) ? 1 : 0;
	assign y_valid_o = 1;

endmodule
module up_conv # (
  parameter ntaps = 32
)
(

  input wire clk,
  input wire rst,

  input wire [15:0] x_a_i,
  input wire [15:0] x_b_i,
  input wire x_valid_i,
  output wire x_ready_o,

  output wire [15:0] y_a_o,
  output wire [15:0] y_b_o,
  output wire y_valid_o,
  input wire y_ready_i
);


	reg [7:0] cntr;

	always @(posedge clk) begin
		if (rst) begin
			cntr <= 0;
		end
		else if (y_ready_i) begin
			cntr <= cntr + 1;
		end
	end

	assign y_a_o = (cntr[2:0] == 0) ? x_a_i : 0;
	assign y_b_o = (cntr[2:0] == 0) ? x_b_i : 0;
	assign x_ready_o = (cntr[2:0] == 0) ? 1 : 0;
	assign y_valid_o = 1;

endmodule