data/full_repos/permissive/11584509/experimental/CM1/xilinx_ram.v
data/verilator_xmls/9ee8ec4c-b44a-4da8-93d1-b5706846912d.xml
module ram # ( parameter ADDRBITS=10 ) (
	raddr,
	waddr,
	clock,
	data,
	wren,
	q);

	input	[ADDRBITS-1:0]  raddr;
	input	[ADDRBITS-1:0]  waddr;
	input	  clock;
	input	[255:0]  data;
	input	  wren;
	output	[255:0]  q;


	reg [255:0] store [(2 << (ADDRBITS-1))-1:0];
	reg[ADDRBITS-1:0] raddr_reg;
	
	always @ (posedge clock)
	begin
		raddr_reg <= raddr;
		if (wren)
			store[waddr] <= data;
	end
	
	assign q = store[raddr_reg];
			
endmodule
module ram # ( parameter ADDRBITS=10 ) (
	raddr,
	waddr,
	clock,
	data,
	wren,
	q);


	input	[ADDRBITS-1:0]  raddr;
	input	[ADDRBITS-1:0]  waddr;
	input	  clock;
	input	[255:0]  data;
	input	  wren;
	output	[255:0]  q;


	reg [255:0] store [(2 << (ADDRBITS-1))-1:0];
	reg[ADDRBITS-1:0] raddr_reg;
	
	always @ (posedge clock)
	begin
		raddr_reg <= raddr;
		if (wren)
			store[waddr] <= data;
	end
	
	assign q = store[raddr_reg];
			
endmodule