data/full_repos/permissive/141038711/hdl/apb_pulse.v
data/verilator_xmls/cfcb08b0-c80f-498d-b0c7-4c15bdee4571.xml
module apb_pulse (

   input             reset_n,
   input             enable,


   input             pclk,            
   input      [ 3:0] paddr,
   input             pwrite,
   input             psel,
   input             penable,
   input      [31:0] pwdata,
   output     [31:0] prdata,
   output            pready,
   output            pslverr,


   output reg       pulse_write,
   output reg       pulse_writebit,
   output reg       pulse_read
  
);

wire apb_write = psel & penable & pwrite;
wire apb_read  = psel & ~pwrite;

   assign pready  = 1'b1;
   assign pslverr = 1'b0;
   assign prdata  = 32'h0;
   
   always @(posedge pclk or negedge reset_n)
   begin
      if (!reset_n)
      begin
         pulse_write    <= 1'b0;
         pulse_writebit <= 1'b0;
         pulse_read     <= 1'b0;
      end
      else if (enable)
      begin
         
         pulse_write    <= 1'b0;
         pulse_writebit <= 1'b0;
         pulse_read     <= 1'b0;
          
         if (apb_write)
         begin
            case (paddr)
            4'h00 :  pulse_write <= 1'b1; 
            4'h04 :  pulse_writebit <= pwdata[0]; 
            endcase
         end
         
         if (apb_read)
         begin


            case (paddr)


            4'h08 : pulse_read <= penable;
            endcase
         end
      end
   end
   
endmodule
module apb_pulse (

   input             reset_n,
   input             enable,


   input             pclk,            
   input      [ 3:0] paddr,
   input             pwrite,
   input             psel,
   input             penable,
   input      [31:0] pwdata,
   output     [31:0] prdata,
   output            pready,
   output            pslverr,


   output reg       pulse_write,
   output reg       pulse_writebit,
   output reg       pulse_read
  
);


wire apb_write = psel & penable & pwrite;
wire apb_read  = psel & ~pwrite;

   assign pready  = 1'b1;
   assign pslverr = 1'b0;
   assign prdata  = 32'h0;
   
   always @(posedge pclk or negedge reset_n)
   begin
      if (!reset_n)
      begin
         pulse_write    <= 1'b0;
         pulse_writebit <= 1'b0;
         pulse_read     <= 1'b0;
      end
      else if (enable)
      begin
         
         pulse_write    <= 1'b0;
         pulse_writebit <= 1'b0;
         pulse_read     <= 1'b0;
          
         if (apb_write)
         begin
            case (paddr)
            4'h00 :  pulse_write <= 1'b1; 
            4'h04 :  pulse_writebit <= pwdata[0]; 
            endcase
         end
         
         if (apb_read)
         begin


            case (paddr)


            4'h08 : pulse_read <= penable;
            endcase
         end
      end
   end
   
endmodule