data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_4_lg_credit_to_token_decimation_p_16/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_4_lg_credit_to_token_decimation_p_16/top.v:61: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                           : ... In instance top.wrapper.bapg.ptr_sync.sync_p_z_blss\n                          (N1)? iclk_data_i : 1\'b0;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_4_lg_credit_to_token_decimation_p_16/top.v:154: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                            : ... In instance top.wrapper.bapg\n                        (N1)? w_ptr_gray_r_o : 1\'b0;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_4_lg_credit_to_token_decimation_p_16/top.v:218: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'r_dec_credit_i\' generates 1 bits.\n                                                                                                                                                                            : ... In instance top.wrapper\n  assign { N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } = r_counter_r + r_dec_credit_i;\n                                                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/217060808/bsg_async/bsg_async_credit_counter/bsg_async_credit_counter_max_tokens_p_4_lg_credit_to_token_decimation_p_16/top.v:220: Operator COND expects 19 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                                                                            : ... In instance top.wrapper\n                                                                                                             (N1)? { N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } : 1\'b0;\n                                                                                                                 ^\n%Error: Exiting due to 4 warning(s)\n'
module bsg_launch_sync_sync_posedge_3_unit
(
  iclk_i,
  iclk_reset_i,
  oclk_i,
  iclk_data_i,
  iclk_data_o,
  oclk_data_o
);

  input [2:0] iclk_data_i;
  output [2:0] iclk_data_o;
  output [2:0] oclk_data_o;
  input iclk_i;
  input iclk_reset_i;
  input oclk_i;
  wire N0,N1,N2,N3,N4,N5;
  reg [2:0] iclk_data_o,bsg_SYNC_1_r,oclk_data_o;
  assign { N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0 } : 
                          (N1)? iclk_data_i : 1'b0;
  assign N0 = iclk_reset_i;
  assign N1 = N2;
  assign N2 = ~iclk_reset_i;

  always @(posedge iclk_i) begin
    if(1'b1) begin
      { iclk_data_o[2:0] } <= { N5, N4, N3 };
    end 
  end


  always @(posedge oclk_i) begin
    if(1'b1) begin
      { bsg_SYNC_1_r[2:0] } <= { iclk_data_o[2:0] };
      { oclk_data_o[2:0] } <= { bsg_SYNC_1_r[2:0] };
    end 
  end


endmodule
module bsg_launch_sync_sync_posedge_3_unit
(
  iclk_i,
  iclk_reset_i,
  oclk_i,
  iclk_data_i,
  iclk_data_o,
  oclk_data_o
);


  input [2:0] iclk_data_i;
  output [2:0] iclk_data_o;
  output [2:0] oclk_data_o;
  input iclk_i;
  input iclk_reset_i;
  input oclk_i;
  wire N0,N1,N2,N3,N4,N5;
  reg [2:0] iclk_data_o,bsg_SYNC_1_r,oclk_data_o;
  assign { N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0 } : 
                          (N1)? iclk_data_i : 1'b0;
  assign N0 = iclk_reset_i;
  assign N1 = N2;
  assign N2 = ~iclk_reset_i;

  always @(posedge iclk_i) begin
    if(1'b1) begin
      { iclk_data_o[2:0] } <= { N5, N4, N3 };
    end 
  end


  always @(posedge oclk_i) begin
    if(1'b1) begin
      { bsg_SYNC_1_r[2:0] } <= { iclk_data_o[2:0] };
      { oclk_data_o[2:0] } <= { bsg_SYNC_1_r[2:0] };
    end 
  end


endmodule