data/full_repos/permissive/217768747/comp_8.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_8.v:7: Signal definition not found, creating implicitly: \'lt0\'\nassign l=(lt0 | lt1) && (~gt1);\n          ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_8.v:7: Signal definition not found, creating implicitly: \'lt1\'\n                                                                  : ... Suggested alternative: \'lt0\'\nassign l=(lt0 | lt1) && (~gt1);\n                ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_8.v:7: Signal definition not found, creating implicitly: \'gt1\'\n                                                                  : ... Suggested alternative: \'lt1\'\nassign l=(lt0 | lt1) && (~gt1);\n                          ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_8.v:8: Signal definition not found, creating implicitly: \'gt0\'\n                                                                  : ... Suggested alternative: \'gt1\'\nassign g=(gt0 | gt1) && (~lt1);\n          ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_8.v:9: Signal definition not found, creating implicitly: \'equ0\'\n                                                                  : ... Suggested alternative: \'eq\'\nassign eq=equ0 && equ1;\n          ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/217768747/comp_8.v:9: Signal definition not found, creating implicitly: \'equ1\'\n                                                                  : ... Suggested alternative: \'equ0\'\nassign eq=equ0 && equ1;\n                  ^~~~\n%Error: data/full_repos/permissive/217768747/comp_8.v:5: Cannot find file containing module: \'comp4\'\ncomp4 f_8(a[3:0], b[3:0],lt0,gt0, equ0);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/comp4\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/comp4.v\n             data/full_repos/permissive/217768747,data/full_repos/permissive/217768747/comp4.sv\n             comp4\n             comp4.v\n             comp4.sv\n             obj_dir/comp4\n             obj_dir/comp4.v\n             obj_dir/comp4.sv\n%Error: data/full_repos/permissive/217768747/comp_8.v:6: Cannot find file containing module: \'comp4\'\ncomp4 s_8(a[7:4], b[7:4],lt1,gt1, equ1);\n^~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n'
module comp8(a,b,l,g,eq);
input [7:0] a;
input [7:0] b;
output l,g,eq;
comp4 f_8(a[3:0], b[3:0],lt0,gt0, equ0);
comp4 s_8(a[7:4], b[7:4],lt1,gt1, equ1);
assign l=(lt0 | lt1) && (~gt1);
assign g=(gt0 | gt1) && (~lt1);
assign eq=equ0 && equ1;
endmodule
module comp8(a,b,l,g,eq);

input [7:0] a;
input [7:0] b;
output l,g,eq;
comp4 f_8(a[3:0], b[3:0],lt0,gt0, equ0);
comp4 s_8(a[7:4], b[7:4],lt1,gt1, equ1);
assign l=(lt0 | lt1) && (~gt1);
assign g=(gt0 | gt1) && (~lt1);
assign eq=equ0 && equ1;
endmodule