data/full_repos/permissive/169382915/verif/tb/tb_formal.v
 line:135: before: "*"
1: b'%Error: data/full_repos/permissive/169382915/verif/tb/tb_formal.v:12: Cannot find include file: fml_common.vh\n`include "fml_common.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/169382915/verif/tb,data/full_repos/permissive/169382915/fml_common.vh\n             data/full_repos/permissive/169382915/verif/tb,data/full_repos/permissive/169382915/fml_common.vh.v\n             data/full_repos/permissive/169382915/verif/tb,data/full_repos/permissive/169382915/fml_common.vh.sv\n             fml_common.vh\n             fml_common.vh.v\n             fml_common.vh.sv\n             obj_dir/fml_common.vh\n             obj_dir/fml_common.vh.v\n             obj_dir/fml_common.vh.sv\n%Error: data/full_repos/permissive/169382915/verif/tb/tb_formal.v:78: Define or directive not defined: \'`VTX_REGISTER_PORTS_CON\'\n`VTX_REGISTER_PORTS_CON(cprs_snoop, vtx_cprs_snoop)\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169382915/verif/tb/tb_formal.v:78: syntax error, unexpected \',\'\n`VTX_REGISTER_PORTS_CON(cprs_snoop, vtx_cprs_snoop)\n                                  ^\n%Error: data/full_repos/permissive/169382915/verif/tb/tb_formal.v:109: Define or directive not defined: \'`VTX_REGISTER_PORTS_CON\'\n`VTX_REGISTER_PORTS_CON(cprs_snoop, vtx_cprs_snoop)\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/169382915/verif/tb/tb_formal.v:109: syntax error, unexpected \',\'\n`VTX_REGISTER_PORTS_CON(cprs_snoop, vtx_cprs_snoop)\n                                  ^\n%Error: Exiting due to 5 error(s)\n'
module tb_formal (




input  wire             g_clk           ,
input  wire             g_resetn        ,



input  wire             cpu_insn_req    ,
input  wire [31:0]      cpu_insn_enc    ,
input  wire [31:0]      cpu_rs1         ,
input  wire [31:0]      cpu_rs2         ,

input  wire             cpu_insn_ack    ,



input  wire [31:0]      cop_mem_rdata   ,
input  wire             cop_mem_stall   ,
input  wire             cop_mem_error


);



wire        g_clk_req       ;
wire        cop_insn_ack    ;

wire [31:0] cop_random      ;
wire        cop_rand_sample ;

wire        cop_wen         ;
wire [ 4:0] cop_waddr       ;
wire [31:0] cop_wdata       ;
wire [ 2:0] cop_result      ;
wire        cop_insn_rsp    ;

wire        cop_mem_cen     ;
wire        cop_mem_wen     ;
wire [31:0] cop_mem_addr    ;
wire [31:0] cop_mem_wdata   ;
wire [ 3:0] cop_mem_ben     ;


wire[31:0] vtx_cprs_snoop   [15:0];







scarv_cop_top i_dut(
.g_clk         (g_clk        ) ,
.g_clk_req     (g_clk_req    ) ,
.g_resetn      (g_resetn     ) ,
`VTX_REGISTER_PORTS_CON(cprs_snoop, vtx_cprs_snoop)
.cpu_insn_req  (cpu_insn_req ) ,
.cop_insn_ack  (cop_insn_ack ) ,
.cpu_insn_enc  (cpu_insn_enc ) ,
.cpu_rs1       (cpu_rs1      ) ,
.cpu_rs2       (cpu_rs2      ) ,
.cop_wen       (cop_wen      ) ,
.cop_waddr     (cop_waddr    ) ,
.cop_wdata     (cop_wdata    ) ,
.cop_result    (cop_result   ) ,
.cop_insn_rsp  (cop_insn_rsp ) ,
.cpu_insn_ack  (cpu_insn_ack ) ,
.cop_random      (cop_random      ),
.cop_rand_sample (cop_rand_sample ),
.cop_mem_cen   (cop_mem_cen  ) ,
.cop_mem_wen   (cop_mem_wen  ) ,
.cop_mem_addr  (cop_mem_addr ) ,
.cop_mem_wdata (cop_mem_wdata) ,
.cop_mem_rdata (cop_mem_rdata) ,
.cop_mem_ben   (cop_mem_ben  ) ,
.cop_mem_stall (cop_mem_stall) ,
.cop_mem_error (cop_mem_error)
);




fml_top i_fml_top(
.g_clk         (g_clk        ) ,
.g_clk_req     (g_clk_req    ) ,
.g_resetn      (g_resetn     ) ,
`VTX_REGISTER_PORTS_CON(cprs_snoop, vtx_cprs_snoop)
.cpu_insn_req  (cpu_insn_req ) ,
.cop_insn_ack  (cop_insn_ack ) ,
.cpu_insn_enc  (cpu_insn_enc ) ,
.cpu_rs1       (cpu_rs1      ) ,
.cpu_rs2       (cpu_rs2      ) ,
.cop_wen       (cop_wen      ) ,
.cop_waddr     (cop_waddr    ) ,
.cop_wdata     (cop_wdata    ) ,
.cop_result    (cop_result   ) ,
.cop_insn_rsp  (cop_insn_rsp ) ,
.cpu_insn_ack  (cpu_insn_ack ) ,
.cop_random      (cop_random      ),
.cop_rand_sample (cop_rand_sample ),
.cop_mem_cen   (cop_mem_cen  ) ,
.cop_mem_wen   (cop_mem_wen  ) ,
.cop_mem_addr  (cop_mem_addr ) ,
.cop_mem_wdata (cop_mem_wdata) ,
.cop_mem_rdata (cop_mem_rdata) ,
.cop_mem_ben   (cop_mem_ben  ) ,
.cop_mem_stall (cop_mem_stall) ,
.cop_mem_error (cop_mem_error)
);

endmodule
module tb_formal (




input  wire             g_clk           ,
input  wire             g_resetn        ,



input  wire             cpu_insn_req    ,
input  wire [31:0]      cpu_insn_enc    ,
input  wire [31:0]      cpu_rs1         ,
input  wire [31:0]      cpu_rs2         ,

input  wire             cpu_insn_ack    ,



input  wire [31:0]      cop_mem_rdata   ,
input  wire             cop_mem_stall   ,
input  wire             cop_mem_error


);




wire        g_clk_req       ;
wire        cop_insn_ack    ;

wire [31:0] cop_random      ;
wire        cop_rand_sample ;

wire        cop_wen         ;
wire [ 4:0] cop_waddr       ;
wire [31:0] cop_wdata       ;
wire [ 2:0] cop_result      ;
wire        cop_insn_rsp    ;

wire        cop_mem_cen     ;
wire        cop_mem_wen     ;
wire [31:0] cop_mem_addr    ;
wire [31:0] cop_mem_wdata   ;
wire [ 3:0] cop_mem_ben     ;


wire[31:0] vtx_cprs_snoop   [15:0];







scarv_cop_top i_dut(
.g_clk         (g_clk        ) ,
.g_clk_req     (g_clk_req    ) ,
.g_resetn      (g_resetn     ) ,
`VTX_REGISTER_PORTS_CON(cprs_snoop, vtx_cprs_snoop)
.cpu_insn_req  (cpu_insn_req ) ,
.cop_insn_ack  (cop_insn_ack ) ,
.cpu_insn_enc  (cpu_insn_enc ) ,
.cpu_rs1       (cpu_rs1      ) ,
.cpu_rs2       (cpu_rs2      ) ,
.cop_wen       (cop_wen      ) ,
.cop_waddr     (cop_waddr    ) ,
.cop_wdata     (cop_wdata    ) ,
.cop_result    (cop_result   ) ,
.cop_insn_rsp  (cop_insn_rsp ) ,
.cpu_insn_ack  (cpu_insn_ack ) ,
.cop_random      (cop_random      ),
.cop_rand_sample (cop_rand_sample ),
.cop_mem_cen   (cop_mem_cen  ) ,
.cop_mem_wen   (cop_mem_wen  ) ,
.cop_mem_addr  (cop_mem_addr ) ,
.cop_mem_wdata (cop_mem_wdata) ,
.cop_mem_rdata (cop_mem_rdata) ,
.cop_mem_ben   (cop_mem_ben  ) ,
.cop_mem_stall (cop_mem_stall) ,
.cop_mem_error (cop_mem_error)
);




fml_top i_fml_top(
.g_clk         (g_clk        ) ,
.g_clk_req     (g_clk_req    ) ,
.g_resetn      (g_resetn     ) ,
`VTX_REGISTER_PORTS_CON(cprs_snoop, vtx_cprs_snoop)
.cpu_insn_req  (cpu_insn_req ) ,
.cop_insn_ack  (cop_insn_ack ) ,
.cpu_insn_enc  (cpu_insn_enc ) ,
.cpu_rs1       (cpu_rs1      ) ,
.cpu_rs2       (cpu_rs2      ) ,
.cop_wen       (cop_wen      ) ,
.cop_waddr     (cop_waddr    ) ,
.cop_wdata     (cop_wdata    ) ,
.cop_result    (cop_result   ) ,
.cop_insn_rsp  (cop_insn_rsp ) ,
.cpu_insn_ack  (cpu_insn_ack ) ,
.cop_random      (cop_random      ),
.cop_rand_sample (cop_rand_sample ),
.cop_mem_cen   (cop_mem_cen  ) ,
.cop_mem_wen   (cop_mem_wen  ) ,
.cop_mem_addr  (cop_mem_addr ) ,
.cop_mem_wdata (cop_mem_wdata) ,
.cop_mem_rdata (cop_mem_rdata) ,
.cop_mem_ben   (cop_mem_ben  ) ,
.cop_mem_stall (cop_mem_stall) ,
.cop_mem_error (cop_mem_error)
);

endmodule