data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v
1: b'%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:1: Cannot find include file: Instruction_def.v\n`include "Instruction_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/159902111/PCPU_INT,data/full_repos/permissive/159902111/Instruction_def.v\n             data/full_repos/permissive/159902111/PCPU_INT,data/full_repos/permissive/159902111/Instruction_def.v.v\n             data/full_repos/permissive/159902111/PCPU_INT,data/full_repos/permissive/159902111/Instruction_def.v.sv\n             Instruction_def.v\n             Instruction_def.v.v\n             Instruction_def.v.sv\n             obj_dir/Instruction_def.v\n             obj_dir/Instruction_def.v.v\n             obj_dir/Instruction_def.v.sv\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:45: Define or directive not defined: \'`R_type\'\n         `R_type:\n         ^~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:45: syntax error, unexpected \':\', expecting endcase\n         `R_type:\n                ^\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:74: Define or directive not defined: \'`J\'\n         `J:\n         ^~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:75: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:79: Define or directive not defined: \'`JAL\'\n         `JAL:\n         ^~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:80: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:84: Define or directive not defined: \'`LB\'\n         `LB:\n         ^~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:85: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:90: Define or directive not defined: \'`LBU\'\n         `LBU:\n         ^~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:91: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:96: Define or directive not defined: \'`LH\'\n         `LH:\n         ^~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:97: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:102: Define or directive not defined: \'`LHU\'\n         `LHU:\n         ^~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:103: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:108: Define or directive not defined: \'`LW\'\n         `LW:\n         ^~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:109: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:114: Define or directive not defined: \'`SB\'\n         `SB:\n         ^~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:115: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:120: Define or directive not defined: \'`SH\'\n         `SH:\n         ^~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:121: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:126: Define or directive not defined: \'`SW\'\n         `SW:\n         ^~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:127: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:132: Define or directive not defined: \'`ADDI\'\n         `ADDI:\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:133: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:138: Define or directive not defined: \'`ADDIU\'\n         `ADDIU:\n         ^~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:139: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:144: Define or directive not defined: \'`ANDI\'\n         `ANDI:\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:145: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:150: Define or directive not defined: \'`ORI\'\n         `ORI:\n         ^~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:151: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:156: Define or directive not defined: \'`XORI\'\n         `XORI:\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:157: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:162: Define or directive not defined: \'`LUI\'\n         `LUI:\n         ^~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:163: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:168: Define or directive not defined: \'`SLTI\'\n         `SLTI:\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:169: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:174: Define or directive not defined: \'`SLTIU\'\n         `SLTIU:\n         ^~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:175: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:180: Define or directive not defined: \'`BEQ\'\n         `BEQ:\n         ^~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:181: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:185: Define or directive not defined: \'`BNE\'\n         `BNE:\n         ^~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:186: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:190: Define or directive not defined: \'`BLEZ\'\n         `BLEZ:\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:191: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:195: Define or directive not defined: \'`BGTZ\'\n         `BGTZ:\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:196: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:200: Define or directive not defined: \'`BLTZ_BGEZ\'\n         `BLTZ_BGEZ:\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:201: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n         begin\n         ^~~~~\n%Error: data/full_repos/permissive/159902111/PCPU_INT/Ctrl.v:207: Define or directive not defined: \'`mfc0_mtc0_eret\'\n         `mfc0_mtc0_eret:\n         ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module Ctrl(
  input        INT,
  input  [31:0]Instr_i,
  input  [5:0] opcode_i,
  input        mark_i,
  input  [5:0] funct_i,
  input        Overflow_i,
  input  [31:0]Status_i,
  input        PC_IFWrite_i,
  
  output [2:0] Branch_o,
  output [1:0] PCSource_o,
  output       Jump_o,
  output [1:0] EXTOp_o,
  output [1:0] RegDst_o,
  output       ALUSrcA_o,
  output       ALUSrcB_o,
  output [2:0] ALUOp_o,
  output [2:0] BEOp_o,
  output       MemRead_o,
  output       MemWrite_o,
  output [1:0] MemtoReg_o,
  output       RegWrite_o,
  output       CauseEPCWrite_o,
  output [1:0] Cause_o,
  output [1:0] EPCOp_o,
  output [1:0] PCOp_o,
  output       RETOp_o,
  output       CRFWrite_o,
  output       First_o,
  output	      Exception_o
  );
  reg [2:0] Branch, ALUOp, BEOp;
  reg       Jump, ALUSrcA, ALUSrcB, MemRead, MemWrite, RegWrite, CauseEPCWrite, RETOp, CRFWrite, First, Exception;
  reg [1:0] PCSource, EXTOp, RegDst, MemtoReg, Cause, EPCOp, PCOp;
  always@(*)
  begin
  	if (!INT || !Status_i[0] || !PC_IFWrite_i || (Instr_i == 32'hc))
  	begin
	    if(!Overflow_i) 
	    begin
	      case(opcode_i)
	        `R_type:
	        begin
	          Branch <= 3'b111; RegDst <= 2'b1; ALUSrcB <= 1'b0;
	          ALUOp <= 3'b010; MemRead <= 1'b0; MemWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0;
	          if (!funct_i[5:2])
	          begin
	            PCSource <= 2'b0; Jump <= 1'b0; ALUSrcA <= 1'b1; MemtoReg <= 2'b0; RegWrite <= 1'b1; PCOp <= 2'b0;
	            CauseEPCWrite <= 1'b0; Exception <= 1'b0;
	          end
	          else if (funct_i == 6'h9)
	          begin
	            PCSource <= 2'b11; Jump <= 1'b1; MemtoReg <= 2'b10; RegWrite <= 1'b1; PCOp <= 2'b0; CauseEPCWrite <= 1'b0;
	            Exception <= 1'b0;
	          end
	          else if (funct_i == 6'h8)
	          begin
	            PCSource <= 2'b11; Jump <= 1'b1; RegWrite <= 1'b0; PCOp <= 2'b0; CauseEPCWrite <= 1'b0; Exception <= 1'b0;
	          end
	          else if (funct_i == 6'hc)
	          begin
	            PCOp <= 2'b10; CauseEPCWrite <= 1'b1; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; PCSource <= 2'b0;  
	            Jump <= 1'b0; ALUSrcA <= 1'b0; MemtoReg <= 2'b0; Exception <= 1'b1; Cause <= 2'b01; EPCOp <= 2'b0;
	          end
	          else
	          begin
	            PCSource <= 2'b0; Jump <= 1'b0; ALUSrcA <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1; PCOp <= 2'b0; CauseEPCWrite <= 1'b0;
	            Exception <= 1'b0;
	          end
	        end
	        `J:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b10; Jump <= 1'b1; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `JAL:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b10; Jump <= 1'b1; RegDst <= 2'b10; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b10; RegWrite <= 1'b1;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `LB:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b111; MemRead <= 1'b1; MemWrite <= 1'b0; MemtoReg <= 2'b01; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `LBU:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b00; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b110; MemRead <= 1'b1; MemWrite <= 1'b0; MemtoReg <= 2'b01; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `LH:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b101; MemRead <= 1'b1; MemWrite <= 1'b0; MemtoReg <= 2'b01; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `LHU:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b00; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b100; MemRead <= 1'b1; MemWrite <= 1'b0; MemtoReg <= 2'b01; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `LW:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b011; MemRead <= 1'b1; MemWrite <= 1'b0; MemtoReg <= 2'b01; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `SB:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b010; MemRead <= 1'b0; MemWrite <= 1'b1; RegWrite <= 1'b0; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `SH:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b001; MemRead <= 1'b0; MemWrite <= 1'b1; RegWrite <= 1'b0; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `SW:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b000; MemRead <= 1'b0; MemWrite <= 1'b1; RegWrite <= 1'b0; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `ADDI:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `ADDIU:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b00; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `ANDI:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b00; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b1; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `ORI:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b00; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b011; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `XORI:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b00; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b100; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `LUI:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b10; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b11; RegWrite <= 1'b1;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `SLTI:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b110; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `SLTIU:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b111; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `BEQ:
	        begin
	          Branch <= 3'b000; PCSource <= 2'b01; Jump <= 1'b0; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; EXTOp <= 2'b01;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `BNE:
	        begin
	          Branch <= 3'b001; PCSource <= 2'b01; Jump <= 1'b0; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; EXTOp <= 2'b01;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `BLEZ:
	        begin
	          Branch <= 3'b100; PCSource <= 2'b01; Jump <= 1'b0; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; EXTOp <= 2'b01;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `BGTZ:
	        begin
	          Branch <= 3'b010; PCSource <= 2'b01; Jump <= 1'b0; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; EXTOp <= 2'b01;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `BLTZ_BGEZ:
	        begin
	          PCSource <= 2'b01; Jump <= 1'b0; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; EXTOp <= 2'b01; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	          if (mark_i) Branch <= 3'b101;
	          else Branch <= 3'b011;
	        end
	        `mfc0_mtc0_eret:
	        begin
	          MemRead <= 1'b0; MemWrite <= 1'b0; PCSource <= 2'b0; Jump <= 1'b0; ALUSrcA <= 1'b0; 
	          MemtoReg <= 2'b0; CauseEPCWrite <= 1'b0; Branch <= 3'b111;
	          if (!funct_i)
	            begin
	              if (!{Instr_i[25:21]}) begin
	                  RegWrite <= 1'b1; First <= 1'b1; CRFWrite <= 1'b0; PCOp <= 2'b0; RETOp <= 1'b0; Exception <= 1'b0;
	                  RegDst <= 2'b0;
	                end
	              else begin
	                  RegWrite <= 1'b0; First <= 1'b0; CRFWrite <= 1'b1; PCOp <= 2'b0; RETOp <= 1'b0; Exception <= 1'b0;
	                end
	            end
	          else begin
	              RegWrite <= 1'b0; First <= 1'b0; CRFWrite <= 1'b0; PCOp <= 2'b01; RETOp <= 1'b1; Exception <= 1'b1;
	            end
	        end
	        default:
	        begin
	          MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; PCSource <= 2'b0; Jump <= 1'b0; ALUSrcA <= 1'b0; 
	          MemtoReg <= 2'b0; PCOp <= 2'b10; CauseEPCWrite <= 1'b1; RETOp <= 1'b0; CRFWrite <= 1'b0; 
	          Exception <= 1'b1; Cause <= 2'b10; EPCOp <= 2'b00; First <= 1'b0;
	        end
	      endcase
	    end
	    else
	    begin
	      MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; PCSource <= 2'b0; Jump <= 1'b0; PCOp <= 2'b10; 
	      CauseEPCWrite <= 1'b1; RETOp <= 1'b0; CRFWrite <= 1'b0; Cause <= 2'b11; Exception <= 1'b1;
	      EPCOp <= 2'b01; First <= 1'b0;
	    end
	end
	else if(Status_i[0] && PC_IFWrite_i)
	begin
		MemRead <= 1'b0; MemWrite <= 1'b0;  RegWrite <= 1'b0; Jump <= 1'b0; PCOp <= 2'b10; CauseEPCWrite <= 1'b1;
		RETOp <= 1'b0; CRFWrite <= 1'b0; Cause <= 2'b00; Exception <= 1'b1; EPCOp <= 2'b10; First <=  1'b0;
	end

  end
  assign Branch_o = Branch;
  assign PCSource_o = PCSource;
  assign Jump_o = Jump;
  assign EXTOp_o = EXTOp;
  assign RegDst_o = RegDst;
  assign ALUSrcA_o = ALUSrcA;
  assign ALUSrcB_o = ALUSrcB;
  assign ALUOp_o = ALUOp;
  assign BEOp_o = BEOp;
  assign MemRead_o = MemRead;
  assign MemWrite_o = MemWrite;
  assign MemtoReg_o = MemtoReg;
  assign RegWrite_o = RegWrite;
  assign CauseEPCWrite_o  = CauseEPCWrite;
  assign Cause_o = Cause;
  assign EPCOp_o = EPCOp;
  assign PCOp_o = PCOp;
  assign CRFWrite_o = CRFWrite;
  assign First_o = First;
  assign Exception_o = Exception;
  assign RETOp_o  = RETOp;
endmodule
module Ctrl(
  input        INT,
  input  [31:0]Instr_i,
  input  [5:0] opcode_i,
  input        mark_i,
  input  [5:0] funct_i,
  input        Overflow_i,
  input  [31:0]Status_i,
  input        PC_IFWrite_i,
  
  output [2:0] Branch_o,
  output [1:0] PCSource_o,
  output       Jump_o,
  output [1:0] EXTOp_o,
  output [1:0] RegDst_o,
  output       ALUSrcA_o,
  output       ALUSrcB_o,
  output [2:0] ALUOp_o,
  output [2:0] BEOp_o,
  output       MemRead_o,
  output       MemWrite_o,
  output [1:0] MemtoReg_o,
  output       RegWrite_o,
  output       CauseEPCWrite_o,
  output [1:0] Cause_o,
  output [1:0] EPCOp_o,
  output [1:0] PCOp_o,
  output       RETOp_o,
  output       CRFWrite_o,
  output       First_o,
  output	      Exception_o
  );

  reg [2:0] Branch, ALUOp, BEOp;
  reg       Jump, ALUSrcA, ALUSrcB, MemRead, MemWrite, RegWrite, CauseEPCWrite, RETOp, CRFWrite, First, Exception;
  reg [1:0] PCSource, EXTOp, RegDst, MemtoReg, Cause, EPCOp, PCOp;
  always@(*)
  begin
  	if (!INT || !Status_i[0] || !PC_IFWrite_i || (Instr_i == 32'hc))
  	begin
	    if(!Overflow_i) 
	    begin
	      case(opcode_i)
	        `R_type:
	        begin
	          Branch <= 3'b111; RegDst <= 2'b1; ALUSrcB <= 1'b0;
	          ALUOp <= 3'b010; MemRead <= 1'b0; MemWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0;
	          if (!funct_i[5:2])
	          begin
	            PCSource <= 2'b0; Jump <= 1'b0; ALUSrcA <= 1'b1; MemtoReg <= 2'b0; RegWrite <= 1'b1; PCOp <= 2'b0;
	            CauseEPCWrite <= 1'b0; Exception <= 1'b0;
	          end
	          else if (funct_i == 6'h9)
	          begin
	            PCSource <= 2'b11; Jump <= 1'b1; MemtoReg <= 2'b10; RegWrite <= 1'b1; PCOp <= 2'b0; CauseEPCWrite <= 1'b0;
	            Exception <= 1'b0;
	          end
	          else if (funct_i == 6'h8)
	          begin
	            PCSource <= 2'b11; Jump <= 1'b1; RegWrite <= 1'b0; PCOp <= 2'b0; CauseEPCWrite <= 1'b0; Exception <= 1'b0;
	          end
	          else if (funct_i == 6'hc)
	          begin
	            PCOp <= 2'b10; CauseEPCWrite <= 1'b1; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; PCSource <= 2'b0;  
	            Jump <= 1'b0; ALUSrcA <= 1'b0; MemtoReg <= 2'b0; Exception <= 1'b1; Cause <= 2'b01; EPCOp <= 2'b0;
	          end
	          else
	          begin
	            PCSource <= 2'b0; Jump <= 1'b0; ALUSrcA <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1; PCOp <= 2'b0; CauseEPCWrite <= 1'b0;
	            Exception <= 1'b0;
	          end
	        end
	        `J:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b10; Jump <= 1'b1; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `JAL:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b10; Jump <= 1'b1; RegDst <= 2'b10; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b10; RegWrite <= 1'b1;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `LB:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b111; MemRead <= 1'b1; MemWrite <= 1'b0; MemtoReg <= 2'b01; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `LBU:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b00; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b110; MemRead <= 1'b1; MemWrite <= 1'b0; MemtoReg <= 2'b01; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `LH:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b101; MemRead <= 1'b1; MemWrite <= 1'b0; MemtoReg <= 2'b01; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `LHU:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b00; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b100; MemRead <= 1'b1; MemWrite <= 1'b0; MemtoReg <= 2'b01; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `LW:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b011; MemRead <= 1'b1; MemWrite <= 1'b0; MemtoReg <= 2'b01; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `SB:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b010; MemRead <= 1'b0; MemWrite <= 1'b1; RegWrite <= 1'b0; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `SH:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b001; MemRead <= 1'b0; MemWrite <= 1'b1; RegWrite <= 1'b0; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `SW:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; BEOp <= 3'b000; MemRead <= 1'b0; MemWrite <= 1'b1; RegWrite <= 1'b0; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `ADDI:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `ADDIU:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b00; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b0; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `ANDI:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b00; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b1; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `ORI:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b00; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b011; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `XORI:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b00; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b100; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `LUI:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b10; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b11; RegWrite <= 1'b1;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `SLTI:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b110; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `SLTIU:
	        begin
	          Branch <= 3'b111; PCSource <= 2'b00; Jump <= 1'b0; EXTOp <= 2'b01; RegDst <= 2'b00; ALUSrcA <= 1'b0; ALUSrcB <= 1'b1;
	          ALUOp <= 3'b111; MemRead <= 1'b0; MemWrite <= 1'b0; MemtoReg <= 2'b0; RegWrite <= 1'b1;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `BEQ:
	        begin
	          Branch <= 3'b000; PCSource <= 2'b01; Jump <= 1'b0; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; EXTOp <= 2'b01;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `BNE:
	        begin
	          Branch <= 3'b001; PCSource <= 2'b01; Jump <= 1'b0; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; EXTOp <= 2'b01;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `BLEZ:
	        begin
	          Branch <= 3'b100; PCSource <= 2'b01; Jump <= 1'b0; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; EXTOp <= 2'b01;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `BGTZ:
	        begin
	          Branch <= 3'b010; PCSource <= 2'b01; Jump <= 1'b0; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; EXTOp <= 2'b01;
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	        end
	        `BLTZ_BGEZ:
	        begin
	          PCSource <= 2'b01; Jump <= 1'b0; MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; EXTOp <= 2'b01; 
	          PCOp <= 2'b0; CauseEPCWrite <= 1'b0; RETOp <= 1'b0; CRFWrite <= 1'b0; First <= 1'b0; Exception <= 1'b0;
	          if (mark_i) Branch <= 3'b101;
	          else Branch <= 3'b011;
	        end
	        `mfc0_mtc0_eret:
	        begin
	          MemRead <= 1'b0; MemWrite <= 1'b0; PCSource <= 2'b0; Jump <= 1'b0; ALUSrcA <= 1'b0; 
	          MemtoReg <= 2'b0; CauseEPCWrite <= 1'b0; Branch <= 3'b111;
	          if (!funct_i)
	            begin
	              if (!{Instr_i[25:21]}) begin
	                  RegWrite <= 1'b1; First <= 1'b1; CRFWrite <= 1'b0; PCOp <= 2'b0; RETOp <= 1'b0; Exception <= 1'b0;
	                  RegDst <= 2'b0;
	                end
	              else begin
	                  RegWrite <= 1'b0; First <= 1'b0; CRFWrite <= 1'b1; PCOp <= 2'b0; RETOp <= 1'b0; Exception <= 1'b0;
	                end
	            end
	          else begin
	              RegWrite <= 1'b0; First <= 1'b0; CRFWrite <= 1'b0; PCOp <= 2'b01; RETOp <= 1'b1; Exception <= 1'b1;
	            end
	        end
	        default:
	        begin
	          MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; PCSource <= 2'b0; Jump <= 1'b0; ALUSrcA <= 1'b0; 
	          MemtoReg <= 2'b0; PCOp <= 2'b10; CauseEPCWrite <= 1'b1; RETOp <= 1'b0; CRFWrite <= 1'b0; 
	          Exception <= 1'b1; Cause <= 2'b10; EPCOp <= 2'b00; First <= 1'b0;
	        end
	      endcase
	    end
	    else
	    begin
	      MemRead <= 1'b0; MemWrite <= 1'b0; RegWrite <= 1'b0; PCSource <= 2'b0; Jump <= 1'b0; PCOp <= 2'b10; 
	      CauseEPCWrite <= 1'b1; RETOp <= 1'b0; CRFWrite <= 1'b0; Cause <= 2'b11; Exception <= 1'b1;
	      EPCOp <= 2'b01; First <= 1'b0;
	    end
	end
	else if(Status_i[0] && PC_IFWrite_i)
	begin
		MemRead <= 1'b0; MemWrite <= 1'b0;  RegWrite <= 1'b0; Jump <= 1'b0; PCOp <= 2'b10; CauseEPCWrite <= 1'b1;
		RETOp <= 1'b0; CRFWrite <= 1'b0; Cause <= 2'b00; Exception <= 1'b1; EPCOp <= 2'b10; First <=  1'b0;
	end

  end
  assign Branch_o = Branch;
  assign PCSource_o = PCSource;
  assign Jump_o = Jump;
  assign EXTOp_o = EXTOp;
  assign RegDst_o = RegDst;
  assign ALUSrcA_o = ALUSrcA;
  assign ALUSrcB_o = ALUSrcB;
  assign ALUOp_o = ALUOp;
  assign BEOp_o = BEOp;
  assign MemRead_o = MemRead;
  assign MemWrite_o = MemWrite;
  assign MemtoReg_o = MemtoReg;
  assign RegWrite_o = RegWrite;
  assign CauseEPCWrite_o  = CauseEPCWrite;
  assign Cause_o = Cause;
  assign EPCOp_o = EPCOp;
  assign PCOp_o = PCOp;
  assign CRFWrite_o = CRFWrite;
  assign First_o = First;
  assign Exception_o = Exception;
  assign RETOp_o  = RETOp;
endmodule