data/full_repos/permissive/108382235/Pipelined.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/108382235/Pipelined.v:688: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'Pipelined\'\nmodule Pipelined(s0, s1, s2, s3, s4, s5, s6, s7, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, CurrentPC,  SwitchClk_10, reset);\n       ^~~~~~~~~\n                                                                       : ... Top module \'ChooseOutput\'\nmodule ChooseOutput(ShowNum, PCOut, ShowRegOut, ShowPC);\n       ^~~~~~~~~~~~\n                                                                       : ... Top module \'SSD_Driver\'\nmodule SSD_Driver (Num_0, Num_1, Num_2, Num_3, Cathod, Anode, clk_500);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'clk_500_Hz\'\nmodule clk_500_Hz(clk_50M, clk_500);\n       ^~~~~~~~~~\n                                                                       : ... Top module \'clk_10_Hz\'\nmodule clk_10_Hz(clk_50M, clk_10, reset);\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:641: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_MEM.M_Dmemory\n  if (MemRead) ReadData=Dmemory[Address[31:2]];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:648: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_MEM.M_Dmemory\n  else if (MemWrite) Dmemory[Address[31:2]]=WriteData;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:625: Bit extraction of array[31:0] requires 5 bit index, not 30 bits.\n                                                                    : ... In instance Pipelined.M_IF.M_Imemory\n always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];\n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/108382235/Pipelined.v:111: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n                                                                    : ... In instance Pipelined\n   IDEX_JumpAddr<={IFID_PC[31:20], JumpAddr_28}; \n                ^~\n%Error: Exiting due to 5 warning(s)\n'
module InstructionMemory(Instruction, ReadAddress);
	input [31:0] ReadAddress;
	output [31:0] Instruction;

	reg [31:0] Instruction;
	reg [31:0] Imemory [31:0];

	initial begin
		Imemory[0] = 32'b00100000000010000000000000100000;
		Imemory[1] = 32'b00100000000010010000000000110111;
		Imemory[2] = 32'b00000001000010011000000000100100;
		Imemory[3] = 32'b00000001000010011000000000100101;
		Imemory[4] = 32'b10101100000100000000000000000100;
		Imemory[5] = 32'b10101100000010000000000000001000;
		Imemory[6] = 32'b00000001000010011000100000100000;
		Imemory[7] = 32'b00000001000010011001000000100010;
		Imemory[8] = 32'b00010010001100100000000000001001;
		Imemory[9] = 32'b10001100000100010000000000000100;
		Imemory[10]= 32'b00110010001100100000000001001000;
		Imemory[11] =32'b00010010001100100000000000001001;
		Imemory[12] =32'b10001100000100110000000000001000;
		Imemory[13] =32'b00010010000100110000000000001010;
		Imemory[14] =32'b00000010010100011010000000101010;
		Imemory[15] =32'b00010010100000000000000000001111;
		Imemory[16] =32'b00000010001000001001000000100000;
		Imemory[17] =32'b00001000000000000000000000001110;
		Imemory[18] =32'b00100000000010000000000000000000;
		Imemory[19] =32'b00100000000010010000000000000000;
		Imemory[20] =32'b00001000000000000000000000011111;
		Imemory[21] =32'b00100000000010000000000000000001;
		Imemory[22] =32'b00100000000010010000000000000001;
		Imemory[23] =32'b00001000000000000000000000011111;
		Imemory[24] =32'b00100000000010000000000000000010;
		Imemory[25] =32'b00100000000010010000000000000010;
		Imemory[26] =32'b00001000000000000000000000011111;
		Imemory[27] =32'b00100000000010000000000000000011;
		Imemory[28] =32'b00100000000010010000000000000011;
		Imemory[29] =32'b00001000000000000000000000011111;
		Imemory[30] =32'b00000000000000000000000000000000;
		Imemory[31] =32'b00000000000000000000000000000000;

	end

	always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];

endmodule
module InstructionMemory(Instruction, ReadAddress);

	input [31:0] ReadAddress;
	output [31:0] Instruction;

	reg [31:0] Instruction;
	reg [31:0] Imemory [31:0];

	initial begin
		Imemory[0] = 32'b00100000000010000000000000100000;
		Imemory[1] = 32'b00100000000010010000000000110111;
		Imemory[2] = 32'b00000001000010011000000000100100;
		Imemory[3] = 32'b00000001000010011000000000100101;
		Imemory[4] = 32'b10101100000100000000000000000100;
		Imemory[5] = 32'b10101100000010000000000000001000;
		Imemory[6] = 32'b00000001000010011000100000100000;
		Imemory[7] = 32'b00000001000010011001000000100010;
		Imemory[8] = 32'b00010010001100100000000000001001;
		Imemory[9] = 32'b10001100000100010000000000000100;
		Imemory[10]= 32'b00110010001100100000000001001000;
		Imemory[11] =32'b00010010001100100000000000001001;
		Imemory[12] =32'b10001100000100110000000000001000;
		Imemory[13] =32'b00010010000100110000000000001010;
		Imemory[14] =32'b00000010010100011010000000101010;
		Imemory[15] =32'b00010010100000000000000000001111;
		Imemory[16] =32'b00000010001000001001000000100000;
		Imemory[17] =32'b00001000000000000000000000001110;
		Imemory[18] =32'b00100000000010000000000000000000;
		Imemory[19] =32'b00100000000010010000000000000000;
		Imemory[20] =32'b00001000000000000000000000011111;
		Imemory[21] =32'b00100000000010000000000000000001;
		Imemory[22] =32'b00100000000010010000000000000001;
		Imemory[23] =32'b00001000000000000000000000011111;
		Imemory[24] =32'b00100000000010000000000000000010;
		Imemory[25] =32'b00100000000010010000000000000010;
		Imemory[26] =32'b00001000000000000000000000011111;
		Imemory[27] =32'b00100000000010000000000000000011;
		Imemory[28] =32'b00100000000010010000000000000011;
		Imemory[29] =32'b00001000000000000000000000011111;
		Imemory[30] =32'b00000000000000000000000000000000;
		Imemory[31] =32'b00000000000000000000000000000000;

	end

	always @(ReadAddress or Imemory[ReadAddress[31:2]]) Instruction=Imemory[ReadAddress[31:2]];

endmodule