data/full_repos/permissive/112219256/execute_stage.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/112219256/execute_stage.v:305: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'execute_stage\'\nmodule execute_stage(\n       ^~~~~~~~~~~~~\n                                                                           : ... Top module \'MUX_3_5\'\nmodule MUX_3_5(\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/112219256/execute_stage.v:409: Operator NOT expects 3 bits on the LHS, but LHS\'s VARREF \'vaddr\' generates 2 bits.\n                                                                        : ... In instance execute_stage.Store\n  assign size_r = &(~vaddr) ? 3\'b010 : ~vaddr;  \n                                       ^\n%Error: data/full_repos/permissive/112219256/execute_stage.v:241: Cannot find file containing module: \'MUX_4_32\'\n    MUX_4_32 ALUA_MUX(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.v\n             data/full_repos/permissive/112219256,data/full_repos/permissive/112219256/MUX_4_32.sv\n             MUX_4_32\n             MUX_4_32.v\n             MUX_4_32.sv\n             obj_dir/MUX_4_32\n             obj_dir/MUX_4_32.v\n             obj_dir/MUX_4_32.sv\n%Error: data/full_repos/permissive/112219256/execute_stage.v:250: Cannot find file containing module: \'MUX_4_32\'\n    MUX_4_32 ALUB_MUX(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/112219256/execute_stage.v:259: Cannot find file containing module: \'ALU\'\n    ALU ALU(\n    ^~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module MUX_3_5(
    input  [4:0] Src1,
    input  [4:0] Src2,
    input  [4:0] Src3,
    input  [1:0] op,
    output [4:0] Result
);
    wire [4:0] and1, and2, and3, op1, op1x, op0, op0x;

	  assign op1  = {5{ op[1]}};
    assign op1x = {5{~op[1]}};
    assign op0  = {5{ op[0]}};
    assign op0x = {5{~op[0]}};
    assign and1 = Src1   & op1x & op0x;
    assign and2 = Src2   & op1x & op0;
    assign and3 = Src3   & op1  & op0x;

    assign Result = and1 | and2 | and3;
endmodule
module MUX_3_5(
    input  [4:0] Src1,
    input  [4:0] Src2,
    input  [4:0] Src3,
    input  [1:0] op,
    output [4:0] Result
);

    wire [4:0] and1, and2, and3, op1, op1x, op0, op0x;

	  assign op1  = {5{ op[1]}};
    assign op1x = {5{~op[1]}};
    assign op0  = {5{ op[0]}};
    assign op0x = {5{~op[0]}};
    assign and1 = Src1   & op1x & op0x;
    assign and2 = Src2   & op1x & op0;
    assign and3 = Src3   & op1  & op0x;

    assign Result = and1 | and2 | and3;
endmodule