data/full_repos/permissive/104305228/code/ctrl.v
1: b'%Error: data/full_repos/permissive/104305228/code/ctrl.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.v\n             data/full_repos/permissive/104305228/code,data/full_repos/permissive/104305228/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/104305228/code/ctrl.v:9: Define or directive not defined: \'`RstEnable\'\n  if (rst == `RstEnable) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ctrl.v:9: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if (rst == `RstEnable) begin\n                       ^\n%Error: data/full_repos/permissive/104305228/code/ctrl.v:13: Define or directive not defined: \'`StallEnable\'\n   if (ex_stallsignal == `StallEnable) begin\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104305228/code/ctrl.v:16: Define or directive not defined: \'`StallEnable\'\n   else if (id_stallsignal == `StallEnable) begin\n                              ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module ctrl(
	input rst,
	input id_stallsignal,
	input ex_stallsignal,
	output reg[5:0] stall
);
	always @ (*) begin
		if (rst == `RstEnable) begin
			stall <= 6'b000000;
		end
		else begin
			if (ex_stallsignal == `StallEnable) begin
				stall <= 6'b001111;
			end
			else if (id_stallsignal == `StallEnable) begin
				stall <= 6'b000111;
			end
			else begin
				stall <= 6'b000000;
			end
		end
	end
endmodule
module ctrl(
	input rst,
	input id_stallsignal,
	input ex_stallsignal,
	output reg[5:0] stall
);

	always @ (*) begin
		if (rst == `RstEnable) begin
			stall <= 6'b000000;
		end
		else begin
			if (ex_stallsignal == `StallEnable) begin
				stall <= 6'b001111;
			end
			else if (id_stallsignal == `StallEnable) begin
				stall <= 6'b000111;
			end
			else begin
				stall <= 6'b000000;
			end
		end
	end
endmodule