data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv
 line:1: before: "class"
1: b"%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:1: Unsupported: classes\nclass mult_coverage extends uvm_subscriber #(mult_input_t);\n^~~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:1: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass mult_coverage extends uvm_subscriber #(mult_input_t);\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:2: Define or directive not defined: '`uvm_component_utils'\n`uvm_component_utils(mult_coverage);\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:4: syntax error, unexpected ::, expecting ':'\nlogic signed [dut_pkg::DATA_WIDTH-1:0] A,B;\n                     ^~\n                                                                                     : ... Perhaps 'dut_pkg' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:5: syntax error, unexpected ::, expecting ':'\nlogic signed [2*dut_pkg::DATA_WIDTH-1:0] result;\n                       ^~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: 'covergroup'\ncovergroup range_value;\n^~~~~~~~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: 'coverpoint'\n  a_leg: coverpoint A { \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n      bins neg    = {[$:-2]};  \n      ^~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n      bins minus1 = {-1};      \n      ^~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n      bins zero   = {0};       \n      ^~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n      bins plus1  = {1};       \n      ^~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n      bins pos    = {[2:$]};   \n      ^~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: 'coverpoint'\n  b_leg: coverpoint B { \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n      bins neg    = {[$:-2]};  \n      ^~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n      bins minus1 = {-1};      \n      ^~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n      bins zero   = {0};       \n      ^~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n      bins plus1  = {1};       \n      ^~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: 'bins'\n      bins pos    = {[2:$]};   \n      ^~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: 'cross'\n  a_b:  cross a_leg, b_leg;\n        ^~~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: 'endgroup'\nendgroup: range_value\n^~~~~~~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:27: syntax error, unexpected IDENTIFIER, expecting ')'\nfunction void write(mult_input_t t);\n                                 ^\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:35: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n         ^~~\n%Error: data/full_repos/permissive/158608551/mult/tb/common/mult_coverage_signed.sv:35: syntax error, unexpected IDENTIFIER, expecting ')'\nfunction new(string name, uvm_component parent);\n                                        ^~~~~~\n%Error: Exiting due to 23 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
function void write(mult_input_t t);
  result = t.dout;
  A = t.A;
  B = t.B;

  range_value.sample();
endfunction
function void write(mult_input_t t);

  result = t.dout;
  A = t.A;
  B = t.B;

  range_value.sample();
endfunction