data/full_repos/permissive/120142431/DualRam.v
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data/verilator_xmls/33a2b9b7-3fd4-4e9c-a111-ef82417c59cb.xml
module DualRAM(clk, aData, bData, aAdrs, bAdrs, aWE, bWE, aVal, bVal);
input [15:0] aData;
input [15:0] bData;

input [15:0] aAdrs;
input [15:0] bAdrs;

input aWE;
input bWE;

input clk;

output reg [15:0] aVal;
output reg [15:0] bVal;


(* ram_init_file = "RAMData.mif", ramstyle = "no_rw_check" *) reg [15:0] mem[65535:0];


	

always @ (posedge clk)
begin
	if (aWE) 
	begin
		mem[aAdrs] <= aData;
		aVal <= aData;
	end
	else 
	begin
		aVal <= mem[aAdrs];
	end
end


always @ (posedge clk)
begin
	if (bWE)
	begin
		mem[bAdrs] <= bData;
		bVal <= bData;
	end
	else
	begin
		bVal <= mem[bAdrs];
	end
end

endmodule
module DualRAM(clk, aData, bData, aAdrs, bAdrs, aWE, bWE, aVal, bVal);

input [15:0] aData;
input [15:0] bData;

input [15:0] aAdrs;
input [15:0] bAdrs;

input aWE;
input bWE;

input clk;

output reg [15:0] aVal;
output reg [15:0] bVal;


(* ram_init_file = "RAMData.mif", ramstyle = "no_rw_check" *) reg [15:0] mem[65535:0];


	

always @ (posedge clk)
begin
	if (aWE) 
	begin
		mem[aAdrs] <= aData;
		aVal <= aData;
	end
	else 
	begin
		aVal <= mem[aAdrs];
	end
end


always @ (posedge clk)
begin
	if (bWE)
	begin
		mem[bAdrs] <= bData;
		bVal <= bData;
	end
	else
	begin
		bVal <= mem[bAdrs];
	end
end

endmodule