data/full_repos/permissive/181665138/verilog/capitolo_i/Rete_Totale_1.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/181665138/verilog/capitolo_i/Rete_Totale_1.v:50: Signal definition not found, creating implicitly: \'A_R1_e_R2\'\n                                                                                             : ... Suggested alternative: \'a_R1_e_R2\'\n                   R2(da_R2, a_R2, A_R1_e_R2);\n                                   ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Rete_di_Tipo_B(z3_z0, x15_x0);
    input   [15:0]  x15_x0;
    output  [3:0]   z3_z0;


endmodule
module Rete_di_Tipo_B(z3_z0, x15_x0);

    input   [15:0]  x15_x0;
    output  [3:0]   z3_z0;


endmodule