data/full_repos/permissive/123627914/src/main/modules/read-clock-frequency-divider/readClockFrequencyDivider.v
data/verilator_xmls/a80d0cb5-6193-4d36-8834-60242b24738d.xml
module readClockFrequencyDivider(
IN_50Mhz    ,
OUT
);

parameter COUNTER_WIDTH = 10;


input IN_50Mhz;


output reg OUT = 1'b0;


reg         [COUNTER_WIDTH-1:0] COUNTER = {COUNTER_WIDTH{1'b0}};
localparam  [COUNTER_WIDTH-1:0] MAXVALUE = 10'd1023;




always @ (posedge IN_50Mhz) begin
    if (COUNTER < MAXVALUE) begin
        COUNTER <= COUNTER + 1'b1;
    end else begin
        COUNTER <= {COUNTER_WIDTH{1'b0}};
        OUT <= ~OUT;
    end
end

endmodule
module readClockFrequencyDivider(
IN_50Mhz    ,
OUT
);


parameter COUNTER_WIDTH = 10;


input IN_50Mhz;


output reg OUT = 1'b0;


reg         [COUNTER_WIDTH-1:0] COUNTER = {COUNTER_WIDTH{1'b0}};
localparam  [COUNTER_WIDTH-1:0] MAXVALUE = 10'd1023;




always @ (posedge IN_50Mhz) begin
    if (COUNTER < MAXVALUE) begin
        COUNTER <= COUNTER + 1'b1;
    end else begin
        COUNTER <= {COUNTER_WIDTH{1'b0}};
        OUT <= ~OUT;
    end
end

endmodule