data/full_repos/permissive/211316121/lab6_2/sources_1/new/Timer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/211316121/lab6_2/sources_1/new/Timer.v:58: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                       : ... Top module \'digitalClock_top\'\nmodule digitalClock_top(\n       ^~~~~~~~~~~~~~~~\n                                                                                       : ... Top module \'_74LS163\'\nmodule _74LS163(\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module _74LS163(
input CP,
input CR_n,
input LD_n,
input EP,
input ET,
input [3:0] D,
output reg [3:0] Q
);

always@(posedge CP)
begin
if(~CR_n) Q<=0;
else if(~LD_n) Q<=D;
else if(LD_n && EP && ET) Q<=Q+1;
end

endmodule
module _74LS163(
input CP,
input CR_n,
input LD_n,
input EP,
input ET,
input [3:0] D,
output reg [3:0] Q
);


always@(posedge CP)
begin
if(~CR_n) Q<=0;
else if(~LD_n) Q<=D;
else if(LD_n && EP && ET) Q<=Q+1;
end

endmodule