data/full_repos/permissive/198653989/JTAG2AXIS/fifo_bram_sync.v
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1: b"%Error: data/full_repos/permissive/198653989/JTAG2AXIS/fifo_bram_sync.v:105: Cannot find file containing module: 'ramb_infer'\nramb_infer\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/198653989/JTAG2AXIS,data/full_repos/permissive/198653989/ramb_infer\n             data/full_repos/permissive/198653989/JTAG2AXIS,data/full_repos/permissive/198653989/ramb_infer.v\n             data/full_repos/permissive/198653989/JTAG2AXIS,data/full_repos/permissive/198653989/ramb_infer.sv\n             ramb_infer\n             ramb_infer.v\n             ramb_infer.sv\n             obj_dir/ramb_infer\n             obj_dir/ramb_infer.v\n             obj_dir/ramb_infer.sv\n%Error: Exiting due to 1 error(s)\n"
module fifo_bram_sync
#(
    parameter   Z = 0,
    parameter   DATA_WIDTH = 64,
    parameter   DEPTH = 9,
    parameter   AFULL_OFFSET = 2,
    parameter   AEMPTY_OFFSET = 2
)
(
    input   wire                            CLK,
    
    input   wire                            RST,

    input   wire    [ DATA_WIDTH - 1 : 0 ]  DIN,
    input   wire                            DIN_WR,
    output  wire                            DIN_FULL,
    output  wire                            DIN_AFULL,
    
    output  wire    [ DATA_WIDTH - 1 : 0 ]  DOUT,
    input   wire                            DOUT_RD,
    output  wire                            DOUT_EMPTY,
    output  wire                            DOUT_AEMPTY

    );



reg     [ DEPTH - 1 : 0 ]       r_wr_adr = 0, r_rd_adr = 0;
(*KEEP = "TRUE"*)
reg     [ DEPTH     : 0 ]       r_fifo_wrd_cnt = 0; 
(*KEEP = "TRUE"*)
reg     [ DEPTH     : 0 ]       r_fifo_wrd_cnt1 = 0;

reg     [ DEPTH     : 0 ]       r_fifo_wrd_cnt_limit_full,r_fifo_wrd_cnt_limit_afull, r_fifo_wrd_cnt_limit_aempty;

wire                            w_full;
wire                            w_afull;
wire                            w_empty;
reg                             r_aempty = 0;
wire                            w_aempty;

reg                             r_error = 1'b0;

wire                            w_rd_en;

wire    [ DATA_WIDTH - 1 : 0]   w_bram_data;


assign w_rd_en = DOUT_RD;


ramb_infer
#(
    .LATENCY        (             1     ),
    .WIDTH          (     DATA_WIDTH    ),
    .DEPTH          (     DEPTH         ),
    .WRITE_MODE_A   ( "WRITE_FIRST"     ),
    .WRITE_MODE_B   ( "WRITE_FIRST"     ),
    .INIT_FILE      ( ""                )
)
ramb_infer_fifo_bram_sync
(
    .ENA            ( DIN_WR            ),
    .CLKA           ( CLK               ),
    .WEA            ( DIN_WR            ),
    .ADDRA          ( r_wr_adr          ),
    .DIA            ( DIN               ),
    .DOA            (                   ),

    .ENB            ( w_rd_en           ),
    .CLKB           ( CLK               ),
    .WEB            ( 1'b0              ),
    .ADDRB          ( r_rd_adr          ),
    .DIB            (                   ),
    .DOB            ( w_bram_data       )
);


always @(posedge CLK)
if(RST == 1'b1)
begin
    r_wr_adr <=#Z 0;
end
else
begin
    if(DIN_WR == 1'b1)
        r_wr_adr <=#Z r_wr_adr + 1'b1;
end




always @(posedge CLK)
if(RST == 1'b1)
begin
    r_rd_adr <=#Z 0;
end
else
begin
    if(DOUT_RD == 1'b1)
        r_rd_adr <=#Z r_rd_adr + 1'b1;
    
end



always @(posedge CLK)
if(RST == 1'b1)
    r_fifo_wrd_cnt <=#Z 0;
else
    if((DIN_WR & ~DOUT_RD) && (w_full == 1'b0) )
        r_fifo_wrd_cnt <=#Z r_fifo_wrd_cnt + 1'b1;
    else
        if((~DIN_WR & DOUT_RD) && (|r_fifo_wrd_cnt == 1'b1))
            r_fifo_wrd_cnt <=#Z r_fifo_wrd_cnt - 1'b1;
            
            
always @(posedge CLK)
if(RST == 1'b1)
    r_fifo_wrd_cnt1 <=#Z 0;
else
    if((DIN_WR & ~DOUT_RD) && ~(r_fifo_wrd_cnt1 == r_fifo_wrd_cnt_limit_full) )
        r_fifo_wrd_cnt1 <=#Z r_fifo_wrd_cnt1 + 1'b1;
    else
        if((~DIN_WR & DOUT_RD) && (|r_fifo_wrd_cnt1 == 1'b1))
            r_fifo_wrd_cnt1 <=#Z r_fifo_wrd_cnt1 - 1'b1;            


  

always @(posedge CLK)
begin
    r_fifo_wrd_cnt_limit_afull      <=#Z {1'b0,{DEPTH{1'b1}}} - AFULL_OFFSET;
    r_fifo_wrd_cnt_limit_full       <=#Z {1'b1,{DEPTH{1'b0}}};
    r_fifo_wrd_cnt_limit_aempty     <=#Z AEMPTY_OFFSET;
end    
    
assign w_full =  (r_fifo_wrd_cnt == r_fifo_wrd_cnt_limit_full) ? 1'b1 : 1'b0;
assign w_afull = (r_fifo_wrd_cnt > r_fifo_wrd_cnt_limit_afull) ? 1'b1 : 1'b0;

assign w_empty  = (r_fifo_wrd_cnt1 == 0) ? 1'b1 : 1'b0;

assign w_aempty = (r_fifo_wrd_cnt1 <= r_fifo_wrd_cnt_limit_aempty) ? 1'b1 : 1'b0;

    
always @(posedge CLK)    
begin
    if( ((w_full == 1'b1) && (DIN_WR == 1'b1) && (RST == 1'b0)) || ((w_empty == 1'b1) && (DOUT_RD == 1'b1) && (RST == 1'b0)))
        r_error <=#Z 1'b1;
    else
        r_error <=#Z 1'b0;
end

`ifdef SIM
always @(posedge CLK)
begin
    if(r_error == 1'b1)
    begin
        $display("%m: r_error flag ! stopping");
        $stop();
    end
end
`endif


assign DIN_FULL     = w_full;
assign DIN_AFULL    = w_afull | w_full;


assign DOUT_EMPTY   = w_empty;
assign DOUT_AEMPTY  = w_aempty;

assign DOUT = w_bram_data;

endmodule
module fifo_bram_sync
#(
    parameter   Z = 0,
    parameter   DATA_WIDTH = 64,
    parameter   DEPTH = 9,
    parameter   AFULL_OFFSET = 2,
    parameter   AEMPTY_OFFSET = 2
)
(
    input   wire                            CLK,
    
    input   wire                            RST,

    input   wire    [ DATA_WIDTH - 1 : 0 ]  DIN,
    input   wire                            DIN_WR,
    output  wire                            DIN_FULL,
    output  wire                            DIN_AFULL,
    
    output  wire    [ DATA_WIDTH - 1 : 0 ]  DOUT,
    input   wire                            DOUT_RD,
    output  wire                            DOUT_EMPTY,
    output  wire                            DOUT_AEMPTY

    );




reg     [ DEPTH - 1 : 0 ]       r_wr_adr = 0, r_rd_adr = 0;
(*KEEP = "TRUE"*)
reg     [ DEPTH     : 0 ]       r_fifo_wrd_cnt = 0; 
(*KEEP = "TRUE"*)
reg     [ DEPTH     : 0 ]       r_fifo_wrd_cnt1 = 0;

reg     [ DEPTH     : 0 ]       r_fifo_wrd_cnt_limit_full,r_fifo_wrd_cnt_limit_afull, r_fifo_wrd_cnt_limit_aempty;

wire                            w_full;
wire                            w_afull;
wire                            w_empty;
reg                             r_aempty = 0;
wire                            w_aempty;

reg                             r_error = 1'b0;

wire                            w_rd_en;

wire    [ DATA_WIDTH - 1 : 0]   w_bram_data;


assign w_rd_en = DOUT_RD;


ramb_infer
#(
    .LATENCY        (             1     ),
    .WIDTH          (     DATA_WIDTH    ),
    .DEPTH          (     DEPTH         ),
    .WRITE_MODE_A   ( "WRITE_FIRST"     ),
    .WRITE_MODE_B   ( "WRITE_FIRST"     ),
    .INIT_FILE      ( ""                )
)
ramb_infer_fifo_bram_sync
(
    .ENA            ( DIN_WR            ),
    .CLKA           ( CLK               ),
    .WEA            ( DIN_WR            ),
    .ADDRA          ( r_wr_adr          ),
    .DIA            ( DIN               ),
    .DOA            (                   ),

    .ENB            ( w_rd_en           ),
    .CLKB           ( CLK               ),
    .WEB            ( 1'b0              ),
    .ADDRB          ( r_rd_adr          ),
    .DIB            (                   ),
    .DOB            ( w_bram_data       )
);


always @(posedge CLK)
if(RST == 1'b1)
begin
    r_wr_adr <=#Z 0;
end
else
begin
    if(DIN_WR == 1'b1)
        r_wr_adr <=#Z r_wr_adr + 1'b1;
end




always @(posedge CLK)
if(RST == 1'b1)
begin
    r_rd_adr <=#Z 0;
end
else
begin
    if(DOUT_RD == 1'b1)
        r_rd_adr <=#Z r_rd_adr + 1'b1;
    
end



always @(posedge CLK)
if(RST == 1'b1)
    r_fifo_wrd_cnt <=#Z 0;
else
    if((DIN_WR & ~DOUT_RD) && (w_full == 1'b0) )
        r_fifo_wrd_cnt <=#Z r_fifo_wrd_cnt + 1'b1;
    else
        if((~DIN_WR & DOUT_RD) && (|r_fifo_wrd_cnt == 1'b1))
            r_fifo_wrd_cnt <=#Z r_fifo_wrd_cnt - 1'b1;
            
            
always @(posedge CLK)
if(RST == 1'b1)
    r_fifo_wrd_cnt1 <=#Z 0;
else
    if((DIN_WR & ~DOUT_RD) && ~(r_fifo_wrd_cnt1 == r_fifo_wrd_cnt_limit_full) )
        r_fifo_wrd_cnt1 <=#Z r_fifo_wrd_cnt1 + 1'b1;
    else
        if((~DIN_WR & DOUT_RD) && (|r_fifo_wrd_cnt1 == 1'b1))
            r_fifo_wrd_cnt1 <=#Z r_fifo_wrd_cnt1 - 1'b1;            


  

always @(posedge CLK)
begin
    r_fifo_wrd_cnt_limit_afull      <=#Z {1'b0,{DEPTH{1'b1}}} - AFULL_OFFSET;
    r_fifo_wrd_cnt_limit_full       <=#Z {1'b1,{DEPTH{1'b0}}};
    r_fifo_wrd_cnt_limit_aempty     <=#Z AEMPTY_OFFSET;
end    
    
assign w_full =  (r_fifo_wrd_cnt == r_fifo_wrd_cnt_limit_full) ? 1'b1 : 1'b0;
assign w_afull = (r_fifo_wrd_cnt > r_fifo_wrd_cnt_limit_afull) ? 1'b1 : 1'b0;

assign w_empty  = (r_fifo_wrd_cnt1 == 0) ? 1'b1 : 1'b0;

assign w_aempty = (r_fifo_wrd_cnt1 <= r_fifo_wrd_cnt_limit_aempty) ? 1'b1 : 1'b0;

    
always @(posedge CLK)    
begin
    if( ((w_full == 1'b1) && (DIN_WR == 1'b1) && (RST == 1'b0)) || ((w_empty == 1'b1) && (DOUT_RD == 1'b1) && (RST == 1'b0)))
        r_error <=#Z 1'b1;
    else
        r_error <=#Z 1'b0;
end

`ifdef SIM
always @(posedge CLK)
begin
    if(r_error == 1'b1)
    begin
        $display("%m: r_error flag ! stopping");
        $stop();
    end
end
`endif


assign DIN_FULL     = w_full;
assign DIN_AFULL    = w_afull | w_full;


assign DOUT_EMPTY   = w_empty;
assign DOUT_AEMPTY  = w_aempty;

assign DOUT = w_bram_data;

endmodule