data/full_repos/permissive/206169433/single cycle/mem.v
1: b'%Error: Cannot find file containing module: cycle,data/full_repos/permissive/206169433\n        ... Looked in:\n             data/full_repos/permissive/206169433/single/cycle,data/full_repos/permissive/206169433\n             data/full_repos/permissive/206169433/single/cycle,data/full_repos/permissive/206169433.v\n             data/full_repos/permissive/206169433/single/cycle,data/full_repos/permissive/206169433.sv\n             cycle,data/full_repos/permissive/206169433\n             cycle,data/full_repos/permissive/206169433.v\n             cycle,data/full_repos/permissive/206169433.sv\n             obj_dir/cycle,data/full_repos/permissive/206169433\n             obj_dir/cycle,data/full_repos/permissive/206169433.v\n             obj_dir/cycle,data/full_repos/permissive/206169433.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/206169433/single\n%Error: Cannot find file containing module: cycle/mem.v\n%Error: Exiting due to 3 error(s)\n'
module mem(clk, address, data, out, memread, memwrite);
    input clk;
    input [31:0] address, data;
    output reg[31:0] out;
    input memread, memwrite;

    parameter size = 64;
    reg [31:0] memory [0:size-1];


    integer i;
    initial begin
      for(i=0; i<size; i=i+1)
        memory[i] = 32'b0;
    end

    always @(address[31:2], memread, memory[address>>2]) begin
            if (memread) out=memory[address>>2];
    end
        always @(negedge clk) begin
            
            if (memwrite) memory[address>>2]=data;
        end

endmodule
module mem(clk, address, data, out, memread, memwrite);

    input clk;
    input [31:0] address, data;
    output reg[31:0] out;
    input memread, memwrite;

    parameter size = 64;
    reg [31:0] memory [0:size-1];


    integer i;
    initial begin
      for(i=0; i<size; i=i+1)
        memory[i] = 32'b0;
    end

    always @(address[31:2], memread, memory[address>>2]) begin
            if (memread) out=memory[address>>2];
    end
        always @(negedge clk) begin
            
            if (memwrite) memory[address>>2]=data;
        end

endmodule