data/full_repos/permissive/18477150/lib/shared/sonic_irq_generator.sv
 line:241: before: "unsigned"
1: b'%Error: data/full_repos/permissive/18477150/lib/shared/sonic_irq_generator.sv:5: Cannot find include file: sonic_constants.sv\n`include "sonic_constants.sv" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18477150/lib/shared,data/full_repos/permissive/18477150/sonic_constants.sv\n             data/full_repos/permissive/18477150/lib/shared,data/full_repos/permissive/18477150/sonic_constants.sv.v\n             data/full_repos/permissive/18477150/lib/shared,data/full_repos/permissive/18477150/sonic_constants.sv.sv\n             sonic_constants.sv\n             sonic_constants.sv.v\n             sonic_constants.sv.sv\n             obj_dir/sonic_constants.sv\n             obj_dir/sonic_constants.sv.v\n             obj_dir/sonic_constants.sv.sv\n%Error: data/full_repos/permissive/18477150/lib/shared/sonic_irq_generator.sv:58: Define or directive not defined: \'`RX_WRITE_ADDR_WIDTH\'\n input [`RX_WRITE_ADDR_WIDTH-1:0] rx_ring_wptr,\n        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/shared/sonic_irq_generator.sv:62: Define or directive not defined: \'`TX_READ_ADDR_WIDTH\'\n input [`TX_READ_ADDR_WIDTH-1:0] tx_ring_rptr,\n        ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/shared/sonic_irq_generator.sv:220: Define or directive not defined: \'`RC_UPD_IRQ_MODE\'\n    rc_update.MODE = `RC_UPD_IRQ_MODE,\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/18477150/lib/shared/sonic_irq_generator.sv:220: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    rc_update.MODE = `RC_UPD_IRQ_MODE,\n                                     ^\n%Error: Exiting due to 5 error(s)\n'
module sonic_irq_generator #(
	parameter USED_QWORDS_WIDTH = 13,
	parameter USE_MSI = 1'b1,
			     parameter PORT_NUM = 0
	) (
	input			clk_in,
	input			reset,


	input			init,


	output			tx_req,
	input			tx_ack,
	output [127:0]  tx_desc,
	input			tx_ws,
	output reg		tx_dv,
	output			tx_dfr,
	output [127:0]	tx_data,
	output			tx_err,
	

	input			tx_sel,
	output reg		tx_busy, 
	output			tx_ready,
	input			tx_ready_others,
	

	input			app_msi_ack,
	output			app_msi_req,
	input			msi_sel   ,
	output			msi_ready ,
	output			msi_busy  ,
	

	input [31:0]					rx_block_size,
	input [31:0]					rx_ring_size,
	input [`RX_WRITE_ADDR_WIDTH-1:0]	rx_ring_wptr,
	input							rdreq,


	input [`TX_READ_ADDR_WIDTH-1:0] tx_ring_rptr,


	input logic [63:0]	irq_base_rc,
	input logic			enable_sfp,
	input logic			irq_msi_enable,


	input logic			force_flush_rc
	);

	localparam INTR_DATA_DWORDS  = 4;
	localparam INTR_DATA_OWORDS  = INTR_DATA_DWORDS/4;	

	enum int unsigned {IDLE_UPD_IRQ = 0, START_TX_UPD_IRQ  = 1, MWR_REQ_UPD_IRQ   = 2,
				MWR_DV_UPD_IRQ = 3, START_INTR_MSI=4, MWR_INTR_REQ_MSI=5} cstate, nstate;

	reg		rx_rc_update_req;
	reg	[7:0] irq_generated_count;







	reg [USED_QWORDS_WIDTH-1:0]  msi_ptr;
	reg [23:0]					 msi_offset;
	reg [23:0]					 temp;

	reg [USED_QWORDS_WIDTH-1:0] rx_block_size_reg;






	always @ (*) begin
	case (cstate)
		IDLE_UPD_IRQ:
		begin
			if ((init==1'b0) && (rx_rc_update_req==1'b1 || force_flush_rc==1'b1))
				nstate = START_TX_UPD_IRQ;
			else
				nstate = IDLE_UPD_IRQ;
		end

		START_TX_UPD_IRQ:
		begin
			if (init==1'b1)
				nstate = IDLE_UPD_IRQ;
			else if ((tx_sel==1'b1) && (tx_ws==1'b0) && (tx_ready_others==1'b0))
				nstate = MWR_REQ_UPD_IRQ;
			else
				nstate = START_TX_UPD_IRQ;
		end

		MWR_REQ_UPD_IRQ:
		begin
			if (init==1'b1)
				nstate = IDLE_UPD_IRQ;
			else if (tx_ack==1'b1)
				nstate = MWR_DV_UPD_IRQ;
			else
				nstate = MWR_REQ_UPD_IRQ;
		end

		MWR_DV_UPD_IRQ:
		begin
			if ((tx_ws==1'b0) || (tx_dv==1'b0)) begin
				if (irq_generated_count == 1) begin
					nstate = START_INTR_MSI;
				end 
				else begin
					nstate = IDLE_UPD_IRQ;
				end
			end
			else begin
				nstate = MWR_DV_UPD_IRQ;
			end
		end

		START_INTR_MSI:		
		begin
			if ((msi_sel==1'b1) && (tx_ws==1'b0))
				nstate = MWR_INTR_REQ_MSI;
			else
				nstate = START_INTR_MSI;
		end

		MWR_INTR_REQ_MSI:
		begin
			if (app_msi_ack==1'b1)
				nstate = IDLE_UPD_IRQ;
			else
				nstate = MWR_INTR_REQ_MSI;
		end

		default:
			nstate = IDLE_UPD_IRQ;
	endcase
	end

	always @ (posedge reset or posedge clk_in)
	begin
		if (reset == 1'b1)
			cstate  = IDLE_UPD_IRQ;
		else
			cstate = nstate;
	end


	assign app_msi_req = (USE_MSI==0)?1'b0:(cstate==MWR_INTR_REQ_MSI)?1'b1:1'b0;
	assign msi_ready   = (USE_MSI==0)?1'b0:(cstate==START_INTR_MSI)?1'b1:1'b0;
	assign msi_busy	   = (USE_MSI==0)?1'b0:(cstate==MWR_INTR_REQ_MSI)?1'b1:1'b0;






	
	sonic_rc_update rc_update(
		.clk_in(clk_in),
		.rstn(~reset),
		.init(init),
		.tx_req(tx_req),
		.tx_ack(tx_ack),
		.tx_desc(tx_desc),
		.tx_ws(tx_ws),
		.tx_dv(tx_dv),
		.tx_dfr(tx_dfr),
		.tx_data(tx_data),
		.tx_err(tx_err),
		.tx_sel(tx_sel),
		.tx_busy(tx_busy),
		.tx_ready(tx_ready),
		.tx_ready_others(tx_ready_others),
		.cstate(cstate),
		.nstate(nstate),
		.base_rc(irq_base_rc),

		.cmd_response(),
		.cmd_error_code(),

		.sfp1_on(enable_sfp),
		.sfp2_on(1'b0),

		.byte_ready(24'h0),
		.byte_sent(32'h0),
		.byte_dropped_tx(32'h0),
		.byte_dropped_rx(32'h0),
		.rx_ring_wptr(rx_ring_wptr),
		.tx_ring_rptr(tx_ring_rptr)
	);
	defparam rc_update.START_TX = START_TX_UPD_IRQ,
			 rc_update.MWR_REQ = MWR_REQ_UPD_IRQ,
			 rc_update.MWR_DV = MWR_DV_UPD_IRQ,
			 rc_update.MODE = `RC_UPD_IRQ_MODE,
	  rc_update.PORT_NUM = PORT_NUM;

	







   reg [31:0] irq_timer;
   reg [31:0] interval_reg;
   
   always @ (posedge clk_in or posedge reset or posedge init) begin
      if ((reset == 1'b1) || (init == 1'b1)) begin
	 rx_rc_update_req <= 0;
	 interval_reg <= {32{1'b1}};
	 irq_timer <= 32'h0;
      end
      else if ((irq_msi_enable == 1'b1) & (enable_sfp == 1'b1)) begin
	 interval_reg <= rx_block_size[31:0];

	 if (irq_timer < interval_reg) begin
	    irq_timer <= irq_timer + 1;
	    rx_rc_update_req <= 0;
	 end
	 else begin
	    irq_timer <= 0;
	    rx_rc_update_req <= 1;
	 end
      end
   end
   


 
endmodule
module sonic_irq_generator #(
	parameter USED_QWORDS_WIDTH = 13,
	parameter USE_MSI = 1'b1,
			     parameter PORT_NUM = 0
	) (
	input			clk_in,
	input			reset,


	input			init,


	output			tx_req,
	input			tx_ack,
	output [127:0]  tx_desc,
	input			tx_ws,
	output reg		tx_dv,
	output			tx_dfr,
	output [127:0]	tx_data,
	output			tx_err,
	

	input			tx_sel,
	output reg		tx_busy, 
	output			tx_ready,
	input			tx_ready_others,
	

	input			app_msi_ack,
	output			app_msi_req,
	input			msi_sel   ,
	output			msi_ready ,
	output			msi_busy  ,
	

	input [31:0]					rx_block_size,
	input [31:0]					rx_ring_size,
	input [`RX_WRITE_ADDR_WIDTH-1:0]	rx_ring_wptr,
	input							rdreq,


	input [`TX_READ_ADDR_WIDTH-1:0] tx_ring_rptr,


	input logic [63:0]	irq_base_rc,
	input logic			enable_sfp,
	input logic			irq_msi_enable,


	input logic			force_flush_rc
	);


	localparam INTR_DATA_DWORDS  = 4;
	localparam INTR_DATA_OWORDS  = INTR_DATA_DWORDS/4;	

	enum int unsigned {IDLE_UPD_IRQ = 0, START_TX_UPD_IRQ  = 1, MWR_REQ_UPD_IRQ   = 2,
				MWR_DV_UPD_IRQ = 3, START_INTR_MSI=4, MWR_INTR_REQ_MSI=5} cstate, nstate;

	reg		rx_rc_update_req;
	reg	[7:0] irq_generated_count;







	reg [USED_QWORDS_WIDTH-1:0]  msi_ptr;
	reg [23:0]					 msi_offset;
	reg [23:0]					 temp;

	reg [USED_QWORDS_WIDTH-1:0] rx_block_size_reg;






	always @ (*) begin
	case (cstate)
		IDLE_UPD_IRQ:
		begin
			if ((init==1'b0) && (rx_rc_update_req==1'b1 || force_flush_rc==1'b1))
				nstate = START_TX_UPD_IRQ;
			else
				nstate = IDLE_UPD_IRQ;
		end

		START_TX_UPD_IRQ:
		begin
			if (init==1'b1)
				nstate = IDLE_UPD_IRQ;
			else if ((tx_sel==1'b1) && (tx_ws==1'b0) && (tx_ready_others==1'b0))
				nstate = MWR_REQ_UPD_IRQ;
			else
				nstate = START_TX_UPD_IRQ;
		end

		MWR_REQ_UPD_IRQ:
		begin
			if (init==1'b1)
				nstate = IDLE_UPD_IRQ;
			else if (tx_ack==1'b1)
				nstate = MWR_DV_UPD_IRQ;
			else
				nstate = MWR_REQ_UPD_IRQ;
		end

		MWR_DV_UPD_IRQ:
		begin
			if ((tx_ws==1'b0) || (tx_dv==1'b0)) begin
				if (irq_generated_count == 1) begin
					nstate = START_INTR_MSI;
				end 
				else begin
					nstate = IDLE_UPD_IRQ;
				end
			end
			else begin
				nstate = MWR_DV_UPD_IRQ;
			end
		end

		START_INTR_MSI:		
		begin
			if ((msi_sel==1'b1) && (tx_ws==1'b0))
				nstate = MWR_INTR_REQ_MSI;
			else
				nstate = START_INTR_MSI;
		end

		MWR_INTR_REQ_MSI:
		begin
			if (app_msi_ack==1'b1)
				nstate = IDLE_UPD_IRQ;
			else
				nstate = MWR_INTR_REQ_MSI;
		end

		default:
			nstate = IDLE_UPD_IRQ;
	endcase
	end

	always @ (posedge reset or posedge clk_in)
	begin
		if (reset == 1'b1)
			cstate  = IDLE_UPD_IRQ;
		else
			cstate = nstate;
	end


	assign app_msi_req = (USE_MSI==0)?1'b0:(cstate==MWR_INTR_REQ_MSI)?1'b1:1'b0;
	assign msi_ready   = (USE_MSI==0)?1'b0:(cstate==START_INTR_MSI)?1'b1:1'b0;
	assign msi_busy	   = (USE_MSI==0)?1'b0:(cstate==MWR_INTR_REQ_MSI)?1'b1:1'b0;






	
	sonic_rc_update rc_update(
		.clk_in(clk_in),
		.rstn(~reset),
		.init(init),
		.tx_req(tx_req),
		.tx_ack(tx_ack),
		.tx_desc(tx_desc),
		.tx_ws(tx_ws),
		.tx_dv(tx_dv),
		.tx_dfr(tx_dfr),
		.tx_data(tx_data),
		.tx_err(tx_err),
		.tx_sel(tx_sel),
		.tx_busy(tx_busy),
		.tx_ready(tx_ready),
		.tx_ready_others(tx_ready_others),
		.cstate(cstate),
		.nstate(nstate),
		.base_rc(irq_base_rc),

		.cmd_response(),
		.cmd_error_code(),

		.sfp1_on(enable_sfp),
		.sfp2_on(1'b0),

		.byte_ready(24'h0),
		.byte_sent(32'h0),
		.byte_dropped_tx(32'h0),
		.byte_dropped_rx(32'h0),
		.rx_ring_wptr(rx_ring_wptr),
		.tx_ring_rptr(tx_ring_rptr)
	);
	defparam rc_update.START_TX = START_TX_UPD_IRQ,
			 rc_update.MWR_REQ = MWR_REQ_UPD_IRQ,
			 rc_update.MWR_DV = MWR_DV_UPD_IRQ,
			 rc_update.MODE = `RC_UPD_IRQ_MODE,
	  rc_update.PORT_NUM = PORT_NUM;

	







   reg [31:0] irq_timer;
   reg [31:0] interval_reg;
   
   always @ (posedge clk_in or posedge reset or posedge init) begin
      if ((reset == 1'b1) || (init == 1'b1)) begin
	 rx_rc_update_req <= 0;
	 interval_reg <= {32{1'b1}};
	 irq_timer <= 32'h0;
      end
      else if ((irq_msi_enable == 1'b1) & (enable_sfp == 1'b1)) begin
	 interval_reg <= rx_block_size[31:0];

	 if (irq_timer < interval_reg) begin
	    irq_timer <= irq_timer + 1;
	    rx_rc_update_req <= 0;
	 end
	 else begin
	    irq_timer <= 0;
	    rx_rc_update_req <= 1;
	 end
      end
   end
   


 
endmodule