data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:17: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'operand_A\' generates 32 bits.\n                                                                                            : ... In instance ALU\nassign ALU_result = (ALU_Control == 6\'b000000)?operand_A+operand_B:\n                                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:17: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'operand_B\' generates 32 bits.\n                                                                                            : ... In instance ALU\nassign ALU_result = (ALU_Control == 6\'b000000)?operand_A+operand_B:\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:18: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s VARREF \'operand_A\' generates 32 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control[4:0] == 5\'b11111)?operand_A:\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:19: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s EQ generates 1 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b010000)?operand_A==operand_B:\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:20: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s NEQ generates 1 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b010001)?operand_A!=operand_B:\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:21: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s LTS generates 1 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b010100 || ALU_Control == 6\'b000010)?($signed(operand_A) < $signed(operand_B)):\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:22: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s GTES generates 1 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b010101)?$signed(operand_A) >= $signed(operand_B):\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:23: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s LT generates 1 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b010110|| ALU_Control == 6\'b000011)?operand_A < operand_B:\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:24: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s GTE generates 1 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b010111)?operand_A >= operand_B:\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:25: Operator XOR expects 64 bits on the LHS, but LHS\'s VARREF \'operand_A\' generates 32 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b000100)?(operand_A)^(operand_B):\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:25: Operator XOR expects 64 bits on the RHS, but RHS\'s VARREF \'operand_B\' generates 32 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b000100)?(operand_A)^(operand_B):\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:26: Operator OR expects 64 bits on the LHS, but LHS\'s VARREF \'operand_A\' generates 32 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b000110)?(operand_A)|(operand_B):\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:26: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'operand_B\' generates 32 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b000110)?(operand_A)|(operand_B):\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:27: Operator AND expects 64 bits on the LHS, but LHS\'s VARREF \'operand_A\' generates 32 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b000111)?(operand_A)&(operand_B):\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:27: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'operand_B\' generates 32 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b000111)?(operand_A)&(operand_B):\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:28: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'operand_A\' generates 32 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b000001)? operand_A << operand_B[4:0]:\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:29: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'operand_A\' generates 32 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b000101)? operand_A >> operand_B[4:0]:\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:31: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'operand_A\' generates 32 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b001000)?operand_A-operand_B:\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:31: Operator SUB expects 64 bits on the RHS, but RHS\'s VARREF \'operand_B\' generates 32 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b001000)?operand_A-operand_B:\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:31: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                            : ... In instance ALU\n     (ALU_Control == 6\'b001000)?operand_A-operand_B:\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:17: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 64 bits.\n                                                                                            : ... In instance ALU\nassign ALU_result = (ALU_Control == 6\'b000000)?operand_A+operand_B:\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/184366791/VerilogSourceFiles/SourceFiles/ALU.v:34: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                            : ... In instance ALU\nassign branch = (branch_op == 1)?ALU_result:0;\n              ^\n%Error: Exiting due to 22 warning(s)\n'
module ALU (
  input branch_op,
  input [5:0]  ALU_Control,
  input [31:0] operand_A,
  input [31:0] operand_B,
  output [31:0] ALU_result,
  output branch
);


assign ALU_result = (ALU_Control == 6'b000000)?operand_A+operand_B:
					(ALU_Control[4:0] == 5'b11111)?operand_A:
					(ALU_Control == 6'b010000)?operand_A==operand_B:
					(ALU_Control == 6'b010001)?operand_A!=operand_B:
					(ALU_Control == 6'b010100 || ALU_Control == 6'b000010)?($signed(operand_A) < $signed(operand_B)):
					(ALU_Control == 6'b010101)?$signed(operand_A) >= $signed(operand_B):
					(ALU_Control == 6'b010110|| ALU_Control == 6'b000011)?operand_A < operand_B:
					(ALU_Control == 6'b010111)?operand_A >= operand_B:
					(ALU_Control == 6'b000100)?(operand_A)^(operand_B):
					(ALU_Control == 6'b000110)?(operand_A)|(operand_B):
					(ALU_Control == 6'b000111)?(operand_A)&(operand_B):
					(ALU_Control == 6'b000001)? operand_A << operand_B[4:0]:
					(ALU_Control == 6'b000101)? operand_A >> operand_B[4:0]:
					(ALU_Control == 6'b001101)? {{32{operand_A[31]}}, operand_A} >> operand_B[4:0]:
					(ALU_Control == 6'b001000)?operand_A-operand_B:
					32'd0;
							
assign branch = (branch_op == 1)?ALU_result:0;

endmodule
module ALU (
  input branch_op,
  input [5:0]  ALU_Control,
  input [31:0] operand_A,
  input [31:0] operand_B,
  output [31:0] ALU_result,
  output branch
);



assign ALU_result = (ALU_Control == 6'b000000)?operand_A+operand_B:
					(ALU_Control[4:0] == 5'b11111)?operand_A:
					(ALU_Control == 6'b010000)?operand_A==operand_B:
					(ALU_Control == 6'b010001)?operand_A!=operand_B:
					(ALU_Control == 6'b010100 || ALU_Control == 6'b000010)?($signed(operand_A) < $signed(operand_B)):
					(ALU_Control == 6'b010101)?$signed(operand_A) >= $signed(operand_B):
					(ALU_Control == 6'b010110|| ALU_Control == 6'b000011)?operand_A < operand_B:
					(ALU_Control == 6'b010111)?operand_A >= operand_B:
					(ALU_Control == 6'b000100)?(operand_A)^(operand_B):
					(ALU_Control == 6'b000110)?(operand_A)|(operand_B):
					(ALU_Control == 6'b000111)?(operand_A)&(operand_B):
					(ALU_Control == 6'b000001)? operand_A << operand_B[4:0]:
					(ALU_Control == 6'b000101)? operand_A >> operand_B[4:0]:
					(ALU_Control == 6'b001101)? {{32{operand_A[31]}}, operand_A} >> operand_B[4:0]:
					(ALU_Control == 6'b001000)?operand_A-operand_B:
					32'd0;
							
assign branch = (branch_op == 1)?ALU_result:0;

endmodule