data/full_repos/permissive/190595283/Modulos/PC.v
data/verilator_xmls/cbe2148f-c496-43c7-96e1-bfd4eb256ba5.xml
module PC (entrada,saida,clk);
  input clk;
  input [31:0] entrada;
  output reg[31:0] saida;
  always @ (posedge clk) begin
    saida = entrada;
  end
endmodule
module PC (entrada,saida,clk);

  input clk;
  input [31:0] entrada;
  output reg[31:0] saida;
  always @ (posedge clk) begin
    saida = entrada;
  end
endmodule