data/full_repos/permissive/132157042/src/spi.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/132157042/src/spi.v:17: syntax error, unexpected ')', expecting '['\n   );\n   ^\n%Error: data/full_repos/permissive/132157042/src/spi.v:47: syntax error, unexpected assign\n   assign sample =    (CPOL ^  (CPHA ^ spi_clk_reg))\n   ^~~~~~\n%Error: data/full_repos/permissive/132157042/src/spi.v:58: syntax error, unexpected always\n   always @(posedge clk) begin\n   ^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module spi_slave
  (
   input        clk,
   input        resetn,
   input        spi_clk,
   input        spi_mosi,
   input        spi_cs,

   output [7:0] read_value,
   output [0:0] first_byte,

   output [0:0] done,

   );



   parameter CPOL = 0;


   parameter CPHA = 0;
   parameter LSBFIRST = 0;


   parameter TIMEOUT__NOT_CS = 0;
   parameter TIMEOUT_CYCLES  = 2;

   reg [3:0]    state = 0;
   reg [7:0]    value_int = 0;
   reg [7:0]    read_value = 0;
   reg [0:0]    done = 0;
   reg [0:0]    first_byte = 0;
   wire [0:0]   sample;
   wire [0:0]   write;
   reg [0:0]    spi_clk_reg;
   reg [0:0]    spi_clk_pre;
   reg [0:0]    spi_cs_reg;
   reg [0:0]    spi_cs_pre;
   reg [0:0]    spi_mosi_reg;
   reg [0:0]    spi_mosi_pre;
   reg [0:0]    reset_timeout;
   reg [0:0]    first_byte_int;

   assign sample =    (CPOL ^  (CPHA ^ spi_clk_reg))
     && (CPOL ^ !(CPHA ^ spi_clk_pre));

   assign write  =    (CPOL ^ !(CPHA ^ spi_clk_reg))
     && (CPOL ^  (CPHA ^ spi_clk_pre));

   localparam TIMEOUT_CYCLE_BITS = TIMEOUT__NOT_CS * ($clog2(TIMEOUT_CYCLES)-1);
   reg [TIMEOUT_CYCLE_BITS:0] timeout_counter = 0;
   reg [0:0]                  timeout_expired = 1;


   always @(posedge clk) begin
      if (!resetn) begin
         state           <= 0;
         reset_timeout   <= 1;
         done            <= 0;
         timeout_counter <= 0;
         timeout_expired <= 1;
         first_byte      <= 0;
         spi_clk_reg     <= 0;
         spi_clk_pre     <= 0;
      end else begin
         timeout_counter <= reset_timeout ? TIMEOUT_CYCLES :
                            (timeout_counter ? timeout_counter - 1 : 0);
         if (!TIMEOUT__NOT_CS) begin
            timeout_expired <= spi_cs_reg;
         end else begin
            timeout_expired <= !timeout_counter;
         end


         spi_cs_reg <= spi_cs;
         spi_cs_pre <= spi_cs_reg;

         spi_clk_reg  <= spi_clk;
         spi_clk_pre  <= spi_clk_reg;

         spi_mosi_reg <= spi_mosi;
         spi_mosi_pre <= spi_mosi_reg;


         reset_timeout <= 0;
         read_value <= 0;
         first_byte <= 0;
         done <= 0;


         if (!spi_cs_reg && spi_cs_pre) first_byte_int <= 1;

         if (timeout_expired) begin
            state <= 0;
            reset_timeout <= 1;
         end else if (sample) begin
            reset_timeout <= 1;
            value_int <= LSBFIRST ? {spi_mosi, value_int[7:1]}
                         : {value_int[6:0], spi_mosi};
            if (state < 8) begin

               state <= state + 1;
            end
         end else if (state == 8) begin
            first_byte     <= first_byte_int;
            first_byte_int <= 0;
            read_value     <= value_int;
            done           <= 1;
            state          <= 0;
         end
      end
   end



endmodule
module spi_slave
  (
   input        clk,
   input        resetn,
   input        spi_clk,
   input        spi_mosi,
   input        spi_cs,

   output [7:0] read_value,
   output [0:0] first_byte,

   output [0:0] done,

   );




   parameter CPOL = 0;


   parameter CPHA = 0;
   parameter LSBFIRST = 0;


   parameter TIMEOUT__NOT_CS = 0;
   parameter TIMEOUT_CYCLES  = 2;

   reg [3:0]    state = 0;
   reg [7:0]    value_int = 0;
   reg [7:0]    read_value = 0;
   reg [0:0]    done = 0;
   reg [0:0]    first_byte = 0;
   wire [0:0]   sample;
   wire [0:0]   write;
   reg [0:0]    spi_clk_reg;
   reg [0:0]    spi_clk_pre;
   reg [0:0]    spi_cs_reg;
   reg [0:0]    spi_cs_pre;
   reg [0:0]    spi_mosi_reg;
   reg [0:0]    spi_mosi_pre;
   reg [0:0]    reset_timeout;
   reg [0:0]    first_byte_int;

   assign sample =    (CPOL ^  (CPHA ^ spi_clk_reg))
     && (CPOL ^ !(CPHA ^ spi_clk_pre));

   assign write  =    (CPOL ^ !(CPHA ^ spi_clk_reg))
     && (CPOL ^  (CPHA ^ spi_clk_pre));

   localparam TIMEOUT_CYCLE_BITS = TIMEOUT__NOT_CS * ($clog2(TIMEOUT_CYCLES)-1);
   reg [TIMEOUT_CYCLE_BITS:0] timeout_counter = 0;
   reg [0:0]                  timeout_expired = 1;


   always @(posedge clk) begin
      if (!resetn) begin
         state           <= 0;
         reset_timeout   <= 1;
         done            <= 0;
         timeout_counter <= 0;
         timeout_expired <= 1;
         first_byte      <= 0;
         spi_clk_reg     <= 0;
         spi_clk_pre     <= 0;
      end else begin
         timeout_counter <= reset_timeout ? TIMEOUT_CYCLES :
                            (timeout_counter ? timeout_counter - 1 : 0);
         if (!TIMEOUT__NOT_CS) begin
            timeout_expired <= spi_cs_reg;
         end else begin
            timeout_expired <= !timeout_counter;
         end


         spi_cs_reg <= spi_cs;
         spi_cs_pre <= spi_cs_reg;

         spi_clk_reg  <= spi_clk;
         spi_clk_pre  <= spi_clk_reg;

         spi_mosi_reg <= spi_mosi;
         spi_mosi_pre <= spi_mosi_reg;


         reset_timeout <= 0;
         read_value <= 0;
         first_byte <= 0;
         done <= 0;


         if (!spi_cs_reg && spi_cs_pre) first_byte_int <= 1;

         if (timeout_expired) begin
            state <= 0;
            reset_timeout <= 1;
         end else if (sample) begin
            reset_timeout <= 1;
            value_int <= LSBFIRST ? {spi_mosi, value_int[7:1]}
                         : {value_int[6:0], spi_mosi};
            if (state < 8) begin

               state <= state + 1;
            end
         end else if (state == 8) begin
            first_byte     <= first_byte_int;
            first_byte_int <= 0;
            read_value     <= value_int;
            done           <= 1;
            state          <= 0;
         end
      end
   end



endmodule