data/full_repos/permissive/146246005/RISC-y Processor/RISCY_CPU.sv
 line:3: before: "package"
1: b'%Error: Cannot find file containing module: Processor,data/full_repos/permissive/146246005\n        ... Looked in:\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.v\n             data/full_repos/permissive/146246005/RISC-y/Processor,data/full_repos/permissive/146246005.sv\n             Processor,data/full_repos/permissive/146246005\n             Processor,data/full_repos/permissive/146246005.v\n             Processor,data/full_repos/permissive/146246005.sv\n             obj_dir/Processor,data/full_repos/permissive/146246005\n             obj_dir/Processor,data/full_repos/permissive/146246005.v\n             obj_dir/Processor,data/full_repos/permissive/146246005.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/146246005/RISC-y\n%Error: Cannot find file containing module: Processor/RISCY_CPU.sv\n%Error: Exiting due to 3 error(s)\n'
module SCALE_REG(REG_OUT,DATA_IN,EN,CLOCK);
	parameter RegSize = 1;
	output reg [ RegSize - 1 : 0] REG_OUT;
	input reg [ RegSize - 1 : 0] DATA_IN;
	input CLOCK,EN;
  always @ (posedge CLOCK) begin
	if(EN)
		REG_OUT <= DATA_IN;
	else
		REG_OUT <= REG_OUT;
  end
endmodule
module SCALE_REG(REG_OUT,DATA_IN,EN,CLOCK);

	parameter RegSize = 1;
	output reg [ RegSize - 1 : 0] REG_OUT;
	input reg [ RegSize - 1 : 0] DATA_IN;
	input CLOCK,EN;
  always @ (posedge CLOCK) begin
	if(EN)
		REG_OUT <= DATA_IN;
	else
		REG_OUT <= REG_OUT;
  end
endmodule