data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCfunct.sv
 line:40 column:21: Illegal character '"'
1: b'%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCfunct.sv:41: Unterminated string\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCfunct.sv:42: Unterminated string\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCfunct.sv:18: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCfunct.sv:18: Unsupported: Ignoring delay on this delayed statement.\n       clk = 1; #10; clk = 0; #10;\n                              ^\n%Error: data/full_repos/permissive/13847835/ProjectStatusReport/TestBenches/PPR/tester/FTCfunct.sv:40: syntax error, unexpected \'%\', expecting \')\'\n          $display(          S %h (%h expected)          errors = errors + 1;\n                                   ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module FTC(Cin, I1, I2, I3, I4, C, Cout, S);
  input Cin;
  input I1;
  input I2;
  input I3;
  input I4;
  output C;
  output Cout;
  output S;


 assign S = Cin ^ I1 ^ I2 ^ I3 ^ I4;
 assign C = ((I1 ^ I2 ^ I3) & I4) | ((I1 ^ I2 ^ I3) & Cin) | (I4 & Cin);
 assign Cout = (I1 & I2) | (I1 & I3) | (I2 & I3);
 
 
 
endmodule
module FTC(Cin, I1, I2, I3, I4, C, Cout, S);

  input Cin;
  input I1;
  input I2;
  input I3;
  input I4;
  output C;
  output Cout;
  output S;


 assign S = Cin ^ I1 ^ I2 ^ I3 ^ I4;
 assign C = ((I1 ^ I2 ^ I3) & I4) | ((I1 ^ I2 ^ I3) & Cin) | (I4 & Cin);
 assign Cout = (I1 & I2) | (I1 & I3) | (I2 & I3);
 
 
 
endmodule