data/full_repos/permissive/107499099/mips_de2-115/MIPS/is_branch.v
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data/verilator_xmls/438660ba-5d95-4690-8c17-c6046265c987.xml
module is_branch (d0, d1, y);
  input  [2:0] d0;
  input  [1:0] d1;
  output  y;

  reg   y_temp;
 
  always @(d0 or d1) begin
    case (d0)
          `EQ:      y_temp = (d1 == 2'b00) ? 1'b1 : 1'b0;
         `NEQ:      y_temp = (d1 == 2'b00) ? 1'b0 : 1'b1;
          `GE:      y_temp = (d1[1] == 1'b0) ? 1'b1 : 1'b0;
          `LE:      y_temp = (d1[0] == 1'b0) ? 1'b1 : 1'b0;
          `GT:      y_temp = (d1 == 2'b01) ? 1'b1 : 1'b0;
          `LT:      y_temp = (d1 == 2'b10) ? 1'b1 : 1'b0;
           `X:      y_temp = 1'b0;
      default:      y_temp = 1'b0;
    endcase
  end

  assign y = y_temp;

endmodule
module is_branch (d0, d1, y);

  input  [2:0] d0;
  input  [1:0] d1;
  output  y;

  reg   y_temp;
 
  always @(d0 or d1) begin
    case (d0)
          `EQ:      y_temp = (d1 == 2'b00) ? 1'b1 : 1'b0;
         `NEQ:      y_temp = (d1 == 2'b00) ? 1'b0 : 1'b1;
          `GE:      y_temp = (d1[1] == 1'b0) ? 1'b1 : 1'b0;
          `LE:      y_temp = (d1[0] == 1'b0) ? 1'b1 : 1'b0;
          `GT:      y_temp = (d1 == 2'b01) ? 1'b1 : 1'b0;
          `LT:      y_temp = (d1 == 2'b10) ? 1'b1 : 1'b0;
           `X:      y_temp = 1'b0;
      default:      y_temp = 1'b0;
    endcase
  end

  assign y = y_temp;

endmodule