data/full_repos/permissive/204736068/SoM/RTL/spi/spi_shifter.sv
[Errno 2] No such file or directory: 'preprocess.output'
data/verilator_xmls/866bf4c2-9031-414a-a6c0-9451f23c9ef9.xml
module spi_shifter (

        input logic ssn,
        input logic sck,
        input logic mosi,
        output logic miso,


        input logic clk,
        input logic rst,
    

        output logic [7:0] rx_dat,
        output logic rx_vld,


        input logic tx_vld,
        output logic tx_rdy,
        input logic [7:0] tx_dat,


        output logic start,
        output logic tx_byte_done,
        output logic tx_overrun,
        output logic busy
        );


    logic [2:0] tx_bit_cnt;
    logic [7:0] tx_buf[1:0];
    logic tx_buf_sel;
    logic [1:0] tx_demet;
    logic tx_ack;
    
    always @(negedge sck or posedge ssn) begin
        if (ssn) begin
            tx_buf_sel <= '0;
            tx_bit_cnt <= '0;
            tx_buf[0] <= '0; tx_buf[1] <= '0;
            tx_demet <= '0;
            tx_ack <= '0;
        end else begin


            if (tx_pend) begin
                tx_buf[~tx_buf_sel] <= tx_pend_dat;
                tx_ack <= '1;
            end else if (tx_bit_cnt =='d7)
                tx_ack <= '0;
            

            tx_bit_cnt <= tx_bit_cnt + 'd1;
           

            if (tx_bit_cnt == 'd7)
                tx_buf_sel <= ~tx_buf_sel;
            

            tx_buf[tx_buf_sel] <= {tx_buf[tx_buf_sel][6:0], 1'b0};
        end
    end
    
    assign tx_rdy = ~tx_pend;
    
    assign miso = tx_buf[tx_buf_sel][7];


    logic [7:0] tx_buf0, tx_buf1;
    assign tx_buf0 = tx_buf[0];
    assign tx_buf1 = tx_buf[1];
    
    logic [2:0] rx_bit_cnt;
    logic [7:0] rx_buf[1:0];
    logic rx_buf_sel;
    always @(negedge sck or posedge ssn) begin
        if (ssn) begin
            rx_buf[0] <= '0; rx_buf[1] <= '0;
            rx_buf_sel <= '0;
            rx_bit_cnt <= '0;
        end else begin

            rx_bit_cnt <= rx_bit_cnt + 'd1;
            

            if (rx_bit_cnt == 'd7)
                rx_buf_sel <= ~rx_buf_sel;
            

            rx_buf[rx_buf_sel] <= {rx_buf[rx_buf_sel][6:0], mosi};
        end
    end
    

    logic [1:0] rx_demet;
    logic [1:0] ssn_demet;
    logic tx_pend;
    logic [7:0] tx_pend_dat;
    always @(posedge clk) begin
        if (rst) begin
            rx_demet <= '0;
            ssn_demet <= '0;
            tx_pend <= '0;
            tx_pend_dat <= '0;
            tx_overrun <= '0;
        end else begin

            rx_demet <= {rx_demet[0], rx_buf_sel};
            ssn_demet <= {ssn_demet[0], ssn};
            
            if (ssn) begin
                tx_pend <= '0;
                tx_pend_dat <= '0;
            end if (tx_vld) begin
                tx_pend <= '1;
                tx_pend_dat <= tx_dat;
            end else if (tx_ack)
                tx_pend <= '0;


            if (tx_vld & tx_pend)
                tx_overrun <= '1;



            start <= ssn_demet[1] & ~ssn_demet[0];

            busy <= ~ssn;
        end
    end
    

    assign rx_vld = ~ssn & ( (rx_demet[1] & ~rx_demet[0]) | (~rx_demet[1] & rx_demet[0]) );
        

    assign rx_dat = rx_buf[~rx_buf_sel];
    
    assign tx_byte_done = tx_pend & tx_ack;

endmodule
module spi_shifter (

        input logic ssn,
        input logic sck,
        input logic mosi,
        output logic miso,


        input logic clk,
        input logic rst,
    

        output logic [7:0] rx_dat,
        output logic rx_vld,


        input logic tx_vld,
        output logic tx_rdy,
        input logic [7:0] tx_dat,


        output logic start,
        output logic tx_byte_done,
        output logic tx_overrun,
        output logic busy
        );



    logic [2:0] tx_bit_cnt;
    logic [7:0] tx_buf[1:0];
    logic tx_buf_sel;
    logic [1:0] tx_demet;
    logic tx_ack;
    
    always @(negedge sck or posedge ssn) begin
        if (ssn) begin
            tx_buf_sel <= '0;
            tx_bit_cnt <= '0;
            tx_buf[0] <= '0; tx_buf[1] <= '0;
            tx_demet <= '0;
            tx_ack <= '0;
        end else begin


            if (tx_pend) begin
                tx_buf[~tx_buf_sel] <= tx_pend_dat;
                tx_ack <= '1;
            end else if (tx_bit_cnt =='d7)
                tx_ack <= '0;
            

            tx_bit_cnt <= tx_bit_cnt + 'd1;
           

            if (tx_bit_cnt == 'd7)
                tx_buf_sel <= ~tx_buf_sel;
            

            tx_buf[tx_buf_sel] <= {tx_buf[tx_buf_sel][6:0], 1'b0};
        end
    end
    
    assign tx_rdy = ~tx_pend;
    
    assign miso = tx_buf[tx_buf_sel][7];


    logic [7:0] tx_buf0, tx_buf1;
    assign tx_buf0 = tx_buf[0];
    assign tx_buf1 = tx_buf[1];
    
    logic [2:0] rx_bit_cnt;
    logic [7:0] rx_buf[1:0];
    logic rx_buf_sel;
    always @(negedge sck or posedge ssn) begin
        if (ssn) begin
            rx_buf[0] <= '0; rx_buf[1] <= '0;
            rx_buf_sel <= '0;
            rx_bit_cnt <= '0;
        end else begin

            rx_bit_cnt <= rx_bit_cnt + 'd1;
            

            if (rx_bit_cnt == 'd7)
                rx_buf_sel <= ~rx_buf_sel;
            

            rx_buf[rx_buf_sel] <= {rx_buf[rx_buf_sel][6:0], mosi};
        end
    end
    

    logic [1:0] rx_demet;
    logic [1:0] ssn_demet;
    logic tx_pend;
    logic [7:0] tx_pend_dat;
    always @(posedge clk) begin
        if (rst) begin
            rx_demet <= '0;
            ssn_demet <= '0;
            tx_pend <= '0;
            tx_pend_dat <= '0;
            tx_overrun <= '0;
        end else begin

            rx_demet <= {rx_demet[0], rx_buf_sel};
            ssn_demet <= {ssn_demet[0], ssn};
            
            if (ssn) begin
                tx_pend <= '0;
                tx_pend_dat <= '0;
            end if (tx_vld) begin
                tx_pend <= '1;
                tx_pend_dat <= tx_dat;
            end else if (tx_ack)
                tx_pend <= '0;


            if (tx_vld & tx_pend)
                tx_overrun <= '1;



            start <= ssn_demet[1] & ~ssn_demet[0];

            busy <= ~ssn;
        end
    end
    

    assign rx_vld = ~ssn & ( (rx_demet[1] & ~rx_demet[0]) | (~rx_demet[1] & rx_demet[0]) );
        

    assign rx_dat = rx_buf[~rx_buf_sel];
    
    assign tx_byte_done = tx_pend & tx_ack;

endmodule