data/full_repos/permissive/194847941/demo/4_Running_LED/Running_led_tdrtl.v
data/verilator_xmls/263793f4-1f97-4e93-a0d9-face4da97195.xml
module running_led
  (
  clk_24m,
  led
  );

  input clk_24m;
  output [15:0] led;

  parameter CNT = 25'b0101101110001101100000000;
  wire [24:0] cnt_time;
  wire [24:0] n1;
  wire [15:0] n6;
  wire flag;
  wire n0;
  wire n5;

  add_pu25_pu25_o25 add0 (
    .i0(cnt_time),
    .i1(25'b0000000000000000000000001),
    .o(n1));
  eq_w25 eq0 (
    .i0(cnt_time),
    .i1(25'b0101101110001101011111111),
    .o(n0));
  eq_w16 eq1 (
    .i0(led),
    .i1(16'b0000000000000000),
    .o(n5));
  reg_sr_ss_w1 flag_reg (
    .clk(clk_24m),
    .d(flag),
    .en(1'b1),
    .reset(~led[0]),
    .set(~led[15]),
    .q(flag));
  binary_mux_s1_w1 mux1_b0 (
    .i0(led[15]),
    .i1(led[1]),
    .sel(flag),
    .o(n6[0]));
  binary_mux_s1_w1 mux1_b1 (
    .i0(led[0]),
    .i1(led[2]),
    .sel(flag),
    .o(n6[1]));
  binary_mux_s1_w1 mux1_b10 (
    .i0(led[9]),
    .i1(led[11]),
    .sel(flag),
    .o(n6[10]));
  binary_mux_s1_w1 mux1_b11 (
    .i0(led[10]),
    .i1(led[12]),
    .sel(flag),
    .o(n6[11]));
  binary_mux_s1_w1 mux1_b12 (
    .i0(led[11]),
    .i1(led[13]),
    .sel(flag),
    .o(n6[12]));
  binary_mux_s1_w1 mux1_b13 (
    .i0(led[12]),
    .i1(led[14]),
    .sel(flag),
    .o(n6[13]));
  binary_mux_s1_w1 mux1_b14 (
    .i0(led[13]),
    .i1(led[15]),
    .sel(flag),
    .o(n6[14]));
  binary_mux_s1_w1 mux1_b15 (
    .i0(led[14]),
    .i1(led[0]),
    .sel(flag),
    .o(n6[15]));
  binary_mux_s1_w1 mux1_b2 (
    .i0(led[1]),
    .i1(led[3]),
    .sel(flag),
    .o(n6[2]));
  binary_mux_s1_w1 mux1_b3 (
    .i0(led[2]),
    .i1(led[4]),
    .sel(flag),
    .o(n6[3]));
  binary_mux_s1_w1 mux1_b4 (
    .i0(led[3]),
    .i1(led[5]),
    .sel(flag),
    .o(n6[4]));
  binary_mux_s1_w1 mux1_b5 (
    .i0(led[4]),
    .i1(led[6]),
    .sel(flag),
    .o(n6[5]));
  binary_mux_s1_w1 mux1_b6 (
    .i0(led[5]),
    .i1(led[7]),
    .sel(flag),
    .o(n6[6]));
  binary_mux_s1_w1 mux1_b7 (
    .i0(led[6]),
    .i1(led[8]),
    .sel(flag),
    .o(n6[7]));
  binary_mux_s1_w1 mux1_b8 (
    .i0(led[7]),
    .i1(led[9]),
    .sel(flag),
    .o(n6[8]));
  binary_mux_s1_w1 mux1_b9 (
    .i0(led[8]),
    .i1(led[10]),
    .sel(flag),
    .o(n6[9]));
  reg_sr_as_w1 reg0_b0 (
    .clk(clk_24m),
    .d(n6[0]),
    .en(n0),
    .reset(n5),
    .set(1'b0),
    .q(led[0]));
  reg_ar_ss_w1 reg0_b1 (
    .clk(clk_24m),
    .d(n6[1]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[1]));
  reg_ar_ss_w1 reg0_b10 (
    .clk(clk_24m),
    .d(n6[10]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[10]));
  reg_ar_ss_w1 reg0_b11 (
    .clk(clk_24m),
    .d(n6[11]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[11]));
  reg_ar_ss_w1 reg0_b12 (
    .clk(clk_24m),
    .d(n6[12]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[12]));
  reg_ar_ss_w1 reg0_b13 (
    .clk(clk_24m),
    .d(n6[13]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[13]));
  reg_ar_ss_w1 reg0_b14 (
    .clk(clk_24m),
    .d(n6[14]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[14]));
  reg_ar_ss_w1 reg0_b15 (
    .clk(clk_24m),
    .d(n6[15]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[15]));
  reg_ar_ss_w1 reg0_b2 (
    .clk(clk_24m),
    .d(n6[2]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[2]));
  reg_ar_ss_w1 reg0_b3 (
    .clk(clk_24m),
    .d(n6[3]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[3]));
  reg_ar_ss_w1 reg0_b4 (
    .clk(clk_24m),
    .d(n6[4]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[4]));
  reg_ar_ss_w1 reg0_b5 (
    .clk(clk_24m),
    .d(n6[5]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[5]));
  reg_ar_ss_w1 reg0_b6 (
    .clk(clk_24m),
    .d(n6[6]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[6]));
  reg_ar_ss_w1 reg0_b7 (
    .clk(clk_24m),
    .d(n6[7]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[7]));
  reg_ar_ss_w1 reg0_b8 (
    .clk(clk_24m),
    .d(n6[8]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[8]));
  reg_ar_ss_w1 reg0_b9 (
    .clk(clk_24m),
    .d(n6[9]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[9]));
  reg_sr_as_w1 reg1_b0 (
    .clk(clk_24m),
    .d(n1[0]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[0]));
  reg_sr_as_w1 reg1_b1 (
    .clk(clk_24m),
    .d(n1[1]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[1]));
  reg_sr_as_w1 reg1_b10 (
    .clk(clk_24m),
    .d(n1[10]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[10]));
  reg_sr_as_w1 reg1_b11 (
    .clk(clk_24m),
    .d(n1[11]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[11]));
  reg_sr_as_w1 reg1_b12 (
    .clk(clk_24m),
    .d(n1[12]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[12]));
  reg_sr_as_w1 reg1_b13 (
    .clk(clk_24m),
    .d(n1[13]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[13]));
  reg_sr_as_w1 reg1_b14 (
    .clk(clk_24m),
    .d(n1[14]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[14]));
  reg_sr_as_w1 reg1_b15 (
    .clk(clk_24m),
    .d(n1[15]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[15]));
  reg_sr_as_w1 reg1_b16 (
    .clk(clk_24m),
    .d(n1[16]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[16]));
  reg_sr_as_w1 reg1_b17 (
    .clk(clk_24m),
    .d(n1[17]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[17]));
  reg_sr_as_w1 reg1_b18 (
    .clk(clk_24m),
    .d(n1[18]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[18]));
  reg_sr_as_w1 reg1_b19 (
    .clk(clk_24m),
    .d(n1[19]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[19]));
  reg_sr_as_w1 reg1_b2 (
    .clk(clk_24m),
    .d(n1[2]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[2]));
  reg_sr_as_w1 reg1_b20 (
    .clk(clk_24m),
    .d(n1[20]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[20]));
  reg_sr_as_w1 reg1_b21 (
    .clk(clk_24m),
    .d(n1[21]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[21]));
  reg_sr_as_w1 reg1_b22 (
    .clk(clk_24m),
    .d(n1[22]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[22]));
  reg_sr_as_w1 reg1_b23 (
    .clk(clk_24m),
    .d(n1[23]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[23]));
  reg_sr_as_w1 reg1_b24 (
    .clk(clk_24m),
    .d(n1[24]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[24]));
  reg_sr_as_w1 reg1_b3 (
    .clk(clk_24m),
    .d(n1[3]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[3]));
  reg_sr_as_w1 reg1_b4 (
    .clk(clk_24m),
    .d(n1[4]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[4]));
  reg_sr_as_w1 reg1_b5 (
    .clk(clk_24m),
    .d(n1[5]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[5]));
  reg_sr_as_w1 reg1_b6 (
    .clk(clk_24m),
    .d(n1[6]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[6]));
  reg_sr_as_w1 reg1_b7 (
    .clk(clk_24m),
    .d(n1[7]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[7]));
  reg_sr_as_w1 reg1_b8 (
    .clk(clk_24m),
    .d(n1[8]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[8]));
  reg_sr_as_w1 reg1_b9 (
    .clk(clk_24m),
    .d(n1[9]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[9]));

endmodule
module running_led
  (
  clk_24m,
  led
  );


  input clk_24m;
  output [15:0] led;

  parameter CNT = 25'b0101101110001101100000000;
  wire [24:0] cnt_time;
  wire [24:0] n1;
  wire [15:0] n6;
  wire flag;
  wire n0;
  wire n5;

  add_pu25_pu25_o25 add0 (
    .i0(cnt_time),
    .i1(25'b0000000000000000000000001),
    .o(n1));
  eq_w25 eq0 (
    .i0(cnt_time),
    .i1(25'b0101101110001101011111111),
    .o(n0));
  eq_w16 eq1 (
    .i0(led),
    .i1(16'b0000000000000000),
    .o(n5));
  reg_sr_ss_w1 flag_reg (
    .clk(clk_24m),
    .d(flag),
    .en(1'b1),
    .reset(~led[0]),
    .set(~led[15]),
    .q(flag));
  binary_mux_s1_w1 mux1_b0 (
    .i0(led[15]),
    .i1(led[1]),
    .sel(flag),
    .o(n6[0]));
  binary_mux_s1_w1 mux1_b1 (
    .i0(led[0]),
    .i1(led[2]),
    .sel(flag),
    .o(n6[1]));
  binary_mux_s1_w1 mux1_b10 (
    .i0(led[9]),
    .i1(led[11]),
    .sel(flag),
    .o(n6[10]));
  binary_mux_s1_w1 mux1_b11 (
    .i0(led[10]),
    .i1(led[12]),
    .sel(flag),
    .o(n6[11]));
  binary_mux_s1_w1 mux1_b12 (
    .i0(led[11]),
    .i1(led[13]),
    .sel(flag),
    .o(n6[12]));
  binary_mux_s1_w1 mux1_b13 (
    .i0(led[12]),
    .i1(led[14]),
    .sel(flag),
    .o(n6[13]));
  binary_mux_s1_w1 mux1_b14 (
    .i0(led[13]),
    .i1(led[15]),
    .sel(flag),
    .o(n6[14]));
  binary_mux_s1_w1 mux1_b15 (
    .i0(led[14]),
    .i1(led[0]),
    .sel(flag),
    .o(n6[15]));
  binary_mux_s1_w1 mux1_b2 (
    .i0(led[1]),
    .i1(led[3]),
    .sel(flag),
    .o(n6[2]));
  binary_mux_s1_w1 mux1_b3 (
    .i0(led[2]),
    .i1(led[4]),
    .sel(flag),
    .o(n6[3]));
  binary_mux_s1_w1 mux1_b4 (
    .i0(led[3]),
    .i1(led[5]),
    .sel(flag),
    .o(n6[4]));
  binary_mux_s1_w1 mux1_b5 (
    .i0(led[4]),
    .i1(led[6]),
    .sel(flag),
    .o(n6[5]));
  binary_mux_s1_w1 mux1_b6 (
    .i0(led[5]),
    .i1(led[7]),
    .sel(flag),
    .o(n6[6]));
  binary_mux_s1_w1 mux1_b7 (
    .i0(led[6]),
    .i1(led[8]),
    .sel(flag),
    .o(n6[7]));
  binary_mux_s1_w1 mux1_b8 (
    .i0(led[7]),
    .i1(led[9]),
    .sel(flag),
    .o(n6[8]));
  binary_mux_s1_w1 mux1_b9 (
    .i0(led[8]),
    .i1(led[10]),
    .sel(flag),
    .o(n6[9]));
  reg_sr_as_w1 reg0_b0 (
    .clk(clk_24m),
    .d(n6[0]),
    .en(n0),
    .reset(n5),
    .set(1'b0),
    .q(led[0]));
  reg_ar_ss_w1 reg0_b1 (
    .clk(clk_24m),
    .d(n6[1]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[1]));
  reg_ar_ss_w1 reg0_b10 (
    .clk(clk_24m),
    .d(n6[10]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[10]));
  reg_ar_ss_w1 reg0_b11 (
    .clk(clk_24m),
    .d(n6[11]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[11]));
  reg_ar_ss_w1 reg0_b12 (
    .clk(clk_24m),
    .d(n6[12]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[12]));
  reg_ar_ss_w1 reg0_b13 (
    .clk(clk_24m),
    .d(n6[13]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[13]));
  reg_ar_ss_w1 reg0_b14 (
    .clk(clk_24m),
    .d(n6[14]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[14]));
  reg_ar_ss_w1 reg0_b15 (
    .clk(clk_24m),
    .d(n6[15]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[15]));
  reg_ar_ss_w1 reg0_b2 (
    .clk(clk_24m),
    .d(n6[2]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[2]));
  reg_ar_ss_w1 reg0_b3 (
    .clk(clk_24m),
    .d(n6[3]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[3]));
  reg_ar_ss_w1 reg0_b4 (
    .clk(clk_24m),
    .d(n6[4]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[4]));
  reg_ar_ss_w1 reg0_b5 (
    .clk(clk_24m),
    .d(n6[5]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[5]));
  reg_ar_ss_w1 reg0_b6 (
    .clk(clk_24m),
    .d(n6[6]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[6]));
  reg_ar_ss_w1 reg0_b7 (
    .clk(clk_24m),
    .d(n6[7]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[7]));
  reg_ar_ss_w1 reg0_b8 (
    .clk(clk_24m),
    .d(n6[8]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[8]));
  reg_ar_ss_w1 reg0_b9 (
    .clk(clk_24m),
    .d(n6[9]),
    .en(n0),
    .reset(1'b0),
    .set(n5),
    .q(led[9]));
  reg_sr_as_w1 reg1_b0 (
    .clk(clk_24m),
    .d(n1[0]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[0]));
  reg_sr_as_w1 reg1_b1 (
    .clk(clk_24m),
    .d(n1[1]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[1]));
  reg_sr_as_w1 reg1_b10 (
    .clk(clk_24m),
    .d(n1[10]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[10]));
  reg_sr_as_w1 reg1_b11 (
    .clk(clk_24m),
    .d(n1[11]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[11]));
  reg_sr_as_w1 reg1_b12 (
    .clk(clk_24m),
    .d(n1[12]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[12]));
  reg_sr_as_w1 reg1_b13 (
    .clk(clk_24m),
    .d(n1[13]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[13]));
  reg_sr_as_w1 reg1_b14 (
    .clk(clk_24m),
    .d(n1[14]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[14]));
  reg_sr_as_w1 reg1_b15 (
    .clk(clk_24m),
    .d(n1[15]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[15]));
  reg_sr_as_w1 reg1_b16 (
    .clk(clk_24m),
    .d(n1[16]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[16]));
  reg_sr_as_w1 reg1_b17 (
    .clk(clk_24m),
    .d(n1[17]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[17]));
  reg_sr_as_w1 reg1_b18 (
    .clk(clk_24m),
    .d(n1[18]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[18]));
  reg_sr_as_w1 reg1_b19 (
    .clk(clk_24m),
    .d(n1[19]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[19]));
  reg_sr_as_w1 reg1_b2 (
    .clk(clk_24m),
    .d(n1[2]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[2]));
  reg_sr_as_w1 reg1_b20 (
    .clk(clk_24m),
    .d(n1[20]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[20]));
  reg_sr_as_w1 reg1_b21 (
    .clk(clk_24m),
    .d(n1[21]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[21]));
  reg_sr_as_w1 reg1_b22 (
    .clk(clk_24m),
    .d(n1[22]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[22]));
  reg_sr_as_w1 reg1_b23 (
    .clk(clk_24m),
    .d(n1[23]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[23]));
  reg_sr_as_w1 reg1_b24 (
    .clk(clk_24m),
    .d(n1[24]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[24]));
  reg_sr_as_w1 reg1_b3 (
    .clk(clk_24m),
    .d(n1[3]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[3]));
  reg_sr_as_w1 reg1_b4 (
    .clk(clk_24m),
    .d(n1[4]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[4]));
  reg_sr_as_w1 reg1_b5 (
    .clk(clk_24m),
    .d(n1[5]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[5]));
  reg_sr_as_w1 reg1_b6 (
    .clk(clk_24m),
    .d(n1[6]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[6]));
  reg_sr_as_w1 reg1_b7 (
    .clk(clk_24m),
    .d(n1[7]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[7]));
  reg_sr_as_w1 reg1_b8 (
    .clk(clk_24m),
    .d(n1[8]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[8]));
  reg_sr_as_w1 reg1_b9 (
    .clk(clk_24m),
    .d(n1[9]),
    .en(1'b1),
    .reset(n0),
    .set(1'b0),
    .q(cnt_time[9]));

endmodule