data/full_repos/permissive/214823094/lab_7/project_1/project_1.srcs/sources_1/new/bus.v
data/verilator_xmls/7f7dd0f0-285f-46b7-bf12-d5571dcce98b.xml
module MUX_2_1(
    input s,
    input [3:0] i0,
    input [3:0] i1,
    output reg [3:0] y
    );
    
    always@(*)
    begin
        case(s)
        1'b0:y<=i0;
        1'b1:y<=i1;
        endcase
    end
    
endmodule
module MUX_2_1(
    input s,
    input [3:0] i0,
    input [3:0] i1,
    output reg [3:0] y
    );

    
    always@(*)
    begin
        case(s)
        1'b0:y<=i0;
        1'b1:y<=i1;
        endcase
    end
    
endmodule