data/full_repos/permissive/109846502/main_test.v
 line:65: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/109846502/main_test.v:55: Unsupported: Ignoring delay on this delayed statement.\n  forever #1 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/109846502/main_test.v:60: Unsupported: Ignoring delay on this delayed statement.\n #105;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/main_test.v:65: Unsupported: Ignoring delay on this delayed statement.\n repeat(200) #1 \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/main_test.v:73: Unsupported: Ignoring delay on this delayed statement.\n  repeat(100) #1 \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/109846502/main_test.v:81: Unsupported: Ignoring delay on this delayed statement.\n  repeat(100) #1 \n              ^\n%Error: data/full_repos/permissive/109846502/main_test.v:41: Cannot find file containing module: \'main\'\n main uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main.v\n             data/full_repos/permissive/109846502,data/full_repos/permissive/109846502/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_test;


	reg rst;
	reg clk;
	reg [3:0] row;


	wire [3:0] col;
	wire rw_out;
	wire rs_out;
	wire e_out;
	wire [7:0] db_out;
	wire [6:0] leds;


	main uut (
		.rst(rst), 
		.clk(clk), 
		.row(row), 
		.col(col), 
		.rw_out(rw_out), 
		.rs_out(rs_out), 
		.e_out(e_out), 
		.db_out(db_out), 
		.leds(leds)
	);

	initial begin
		clk = 1'b0;
		forever #1 clk = ~clk;
	end
	
	initial begin
	rst = 1'b1;
	#105;
	rst = 1'b0;
	end
	
	initial begin
	repeat(200) #1	
		case(col)
			4'b0111: row = 4'b1111;
			4'b1011: row = 4'b1101;
			4'b1101: row = 4'b1111;
			4'b1110: row = 4'b1111;
		endcase
		
		repeat(100) #1	
		case(col)
			4'b0111: row = 4'b1111;
			4'b1011: row = 4'b1111;
			4'b1101: row = 4'b1111;
			4'b1110: row = 4'b1111;
		endcase
		
		repeat(100) #1	
		case(col)
			4'b0111: row = 4'b1101;
			4'b1011: row = 4'b1111;
			4'b1101: row = 4'b1111;
			4'b1110: row = 4'b1111;
		endcase
	end 
      
endmodule
module main_test;



	reg rst;
	reg clk;
	reg [3:0] row;


	wire [3:0] col;
	wire rw_out;
	wire rs_out;
	wire e_out;
	wire [7:0] db_out;
	wire [6:0] leds;


	main uut (
		.rst(rst), 
		.clk(clk), 
		.row(row), 
		.col(col), 
		.rw_out(rw_out), 
		.rs_out(rs_out), 
		.e_out(e_out), 
		.db_out(db_out), 
		.leds(leds)
	);

	initial begin
		clk = 1'b0;
		forever #1 clk = ~clk;
	end
	
	initial begin
	rst = 1'b1;
	#105;
	rst = 1'b0;
	end
	
	initial begin
	repeat(200) #1	
		case(col)
			4'b0111: row = 4'b1111;
			4'b1011: row = 4'b1101;
			4'b1101: row = 4'b1111;
			4'b1110: row = 4'b1111;
		endcase
		
		repeat(100) #1	
		case(col)
			4'b0111: row = 4'b1111;
			4'b1011: row = 4'b1111;
			4'b1101: row = 4'b1111;
			4'b1110: row = 4'b1111;
		endcase
		
		repeat(100) #1	
		case(col)
			4'b0111: row = 4'b1101;
			4'b1011: row = 4'b1111;
			4'b1101: row = 4'b1111;
			4'b1110: row = 4'b1111;
		endcase
	end 
      
endmodule