data/full_repos/permissive/101423580/v/control_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/101423580/v/control_test.v:76: Unsupported: Ignoring delay on this delayed statement.\n   #54; col <= col + 1\'b1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/101423580/v/control_test.v:46: Cannot find file containing module: \'control\'\n control uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/control\n             data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/control.v\n             data/full_repos/permissive/101423580/v,data/full_repos/permissive/101423580/control.sv\n             control\n             control.v\n             control.sv\n             obj_dir/control\n             obj_dir/control.v\n             obj_dir/control.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control_test;


	reg clk;
	reg [9:0] col;
	reg [8:0] row;
	reg [3:0] RAMData;
	reg rst;
	reg [2:0] mode;
	reg [11:0] Din;


	wire [4:0] SyncAddr;
	wire [11:0] Dout;
	wire RAMaddrEN;
	wire [2:0] ROMmux2;
	wire [4:0] RAMaddr;
	wire [3:0] ROMmux;
	wire [12:0] ROMaddr;


	control uut (
		.clk(clk), 
		.col(col), 
		.row(row), 
		.RAMData(RAMData), 
		.rst(rst), 
		.mode(mode), 
		.Din(Din), 
		.SyncAddr(SyncAddr), 
		.Dout(Dout), 
		.RAMaddrEN(RAMaddrEN), 
		.ROMmux2(ROMmux2), 
		.RAMaddr(RAMaddr), 
		.ROMmux(ROMmux), 
		.ROMaddr(ROMaddr)
	);

	initial begin

		clk = 0;
		col = 144;
		row = 20;
		RAMData = 0;
		rst = 0;
		mode = 0;
		Din = 0;
	end
	
	always @ *
		begin
			#54; col <= col + 1'b1;
		end
	
	
      
endmodule
module control_test;



	reg clk;
	reg [9:0] col;
	reg [8:0] row;
	reg [3:0] RAMData;
	reg rst;
	reg [2:0] mode;
	reg [11:0] Din;


	wire [4:0] SyncAddr;
	wire [11:0] Dout;
	wire RAMaddrEN;
	wire [2:0] ROMmux2;
	wire [4:0] RAMaddr;
	wire [3:0] ROMmux;
	wire [12:0] ROMaddr;


	control uut (
		.clk(clk), 
		.col(col), 
		.row(row), 
		.RAMData(RAMData), 
		.rst(rst), 
		.mode(mode), 
		.Din(Din), 
		.SyncAddr(SyncAddr), 
		.Dout(Dout), 
		.RAMaddrEN(RAMaddrEN), 
		.ROMmux2(ROMmux2), 
		.RAMaddr(RAMaddr), 
		.ROMmux(ROMmux), 
		.ROMaddr(ROMaddr)
	);

	initial begin

		clk = 0;
		col = 144;
		row = 20;
		RAMData = 0;
		rst = 0;
		mode = 0;
		Din = 0;
	end
	
	always @ *
		begin
			#54; col <= col + 1'b1;
		end
	
	
      
endmodule