data/full_repos/permissive/143278/ivltests/vhdl_generic_eval.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/vhdl_generic_eval.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/143278/ivltests/vhdl_generic_eval.v:25: Cannot find file containing module: \'test_eval_generic\'\ntest_eval_generic dut(data, out_bit_def, out_bit_ovr);\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/test_eval_generic\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/test_eval_generic.v\n             data/full_repos/permissive/143278/ivltests,data/full_repos/permissive/143278/test_eval_generic.sv\n             test_eval_generic\n             test_eval_generic.v\n             test_eval_generic.sv\n             obj_dir/test_eval_generic\n             obj_dir/test_eval_generic.v\n             obj_dir/test_eval_generic.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module generic_eval();
reg [7:0] data;
reg out_bit_def, out_bit_ovr;
test_eval_generic dut(data, out_bit_def, out_bit_ovr);

initial begin
    data = 8'b11010010;
    #1;

    if(out_bit_def !== 1'b0 || out_bit_ovr !== 1'b1) begin
        $display("FAILED");
        $finish();
    end

    $display("PASSED");
end
endmodule
module generic_eval();

reg [7:0] data;
reg out_bit_def, out_bit_ovr;
test_eval_generic dut(data, out_bit_def, out_bit_ovr);

initial begin
    data = 8'b11010010;
    #1;

    if(out_bit_def !== 1'b0 || out_bit_ovr !== 1'b1) begin
        $display("FAILED");
        $finish();
    end

    $display("PASSED");
end
endmodule