data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim/stream_sink.v
 line:63: before: "integer"
1: b'%Error: data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim/stream_sink.v:40: Cannot find include file: stream_common.vh\n`include "stream_common.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh.v\n             data/full_repos/permissive/181738725/wavetrace/verilog/lib/stream/sim,data/full_repos/permissive/181738725/stream_common.vh.sv\n             stream_common.vh\n             stream_common.vh.v\n             stream_common.vh.sv\n             obj_dir/stream_common.vh\n             obj_dir/stream_common.vh.v\n             obj_dir/stream_common.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module stream_sink (clk, rst, din_valid, din_ready, din_data, done, err);
`include "stream_common.vh"

  parameter FilenameDump  = "undefined";
  parameter FilenameRef   = "undefined";
  parameter CheckData     = 1;
  parameter NumSymbols    = 2;
  parameter SymbolBits    = {32'd8, 32'd2};

  parameter MinThroughput = 0;
  parameter MaxThroughput = 100;
  parameter Period        = 1487;
  parameter Seed          = 2;

  localparam TotalWidth   = calc_total(NumSymbols, SymbolBits);

  input                   clk;
  input                   rst;
  output                  din_ready;
  input                   din_valid;
  input  [TotalWidth-1:0] din_data;
  output                  done;
  output                  err;





  stream_spy
    #(.FilenameDump(FilenameDump),
      .FilenameRef (FilenameRef),
      .NumSymbols  (NumSymbols),
      .CheckData   (CheckData),
      .SymbolBits  (SymbolBits))
  spy(
    .clk      (clk),
    .rst      (rst),
    .din_ready(din_ready),
    .din_valid(din_valid),
    .din_data (din_data),
    .done     (done),
    .err      (err));




  rate_ctrl
    #(.MaxThroughput(MaxThroughput),
      .MinThroughput(MinThroughput),
      .Period       (Period),
      .Seed         (Seed))
  rate(
    .clk    (clk),
    .rst    (rst),
    .active (din_ready),
    .ack    (din_valid));

endmodule
module stream_sink (clk, rst, din_valid, din_ready, din_data, done, err);

`include "stream_common.vh"

  parameter FilenameDump  = "undefined";
  parameter FilenameRef   = "undefined";
  parameter CheckData     = 1;
  parameter NumSymbols    = 2;
  parameter SymbolBits    = {32'd8, 32'd2};

  parameter MinThroughput = 0;
  parameter MaxThroughput = 100;
  parameter Period        = 1487;
  parameter Seed          = 2;

  localparam TotalWidth   = calc_total(NumSymbols, SymbolBits);

  input                   clk;
  input                   rst;
  output                  din_ready;
  input                   din_valid;
  input  [TotalWidth-1:0] din_data;
  output                  done;
  output                  err;





  stream_spy
    #(.FilenameDump(FilenameDump),
      .FilenameRef (FilenameRef),
      .NumSymbols  (NumSymbols),
      .CheckData   (CheckData),
      .SymbolBits  (SymbolBits))
  spy(
    .clk      (clk),
    .rst      (rst),
    .din_ready(din_ready),
    .din_valid(din_valid),
    .din_data (din_data),
    .done     (done),
    .err      (err));




  rate_ctrl
    #(.MaxThroughput(MaxThroughput),
      .MinThroughput(MinThroughput),
      .Period       (Period),
      .Seed         (Seed))
  rate(
    .clk    (clk),
    .rst    (rst),
    .active (din_ready),
    .ack    (din_valid));

endmodule