data/full_repos/permissive/13111265/verilog/src/displays/BarGraph.v
data/verilator_xmls/057f3e7f-80bc-428c-8f36-e95a7a305130.xml
module BarGraph #(
    parameter IN_WIDTH  = 8,
    parameter OUT_WIDTH = 8,
    parameter LSB       = 0
)
(
    input  wire                 clk,
    input  wire                 rst,
    input  wire                 en,
    input  wire [IN_WIDTH-1:0]  data,
    output reg  [OUT_WIDTH-1:0] bar
);

localparam OUT_RANGE = (OUT_WIDTH+LSB > IN_WIDTH) ? (IN_WIDTH-LSB) : OUT_WIDTH;

integer i;

always @(posedge clk) begin
    if (rst) begin
        bar <= 'd0;
    end
    else begin
        for (i=0; i<OUT_RANGE; i=i+1) begin
            bar[i] <= |(data >> (i+LSB));
        end
    end
end

endmodule
module BarGraph #(
    parameter IN_WIDTH  = 8,
    parameter OUT_WIDTH = 8,
    parameter LSB       = 0
)
(
    input  wire                 clk,
    input  wire                 rst,
    input  wire                 en,
    input  wire [IN_WIDTH-1:0]  data,
    output reg  [OUT_WIDTH-1:0] bar
);


localparam OUT_RANGE = (OUT_WIDTH+LSB > IN_WIDTH) ? (IN_WIDTH-LSB) : OUT_WIDTH;

integer i;

always @(posedge clk) begin
    if (rst) begin
        bar <= 'd0;
    end
    else begin
        for (i=0; i<OUT_RANGE; i=i+1) begin
            bar[i] <= |(data >> (i+LSB));
        end
    end
end

endmodule