data/full_repos/permissive/206017343/single-cycle.srcs/sim_1/new/simulation.v
None: at end of input
1: b'%Warning-STMTDLY: data/full_repos/permissive/206017343/single-cycle.srcs/sim_1/new/simulation.v:15: Unsupported: Ignoring delay on this delayed statement.\n           #10 rst = 0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/206017343/single-cycle.srcs/sim_1/new/simulation.v:19: Unsupported: Ignoring delay on this delayed statement.\n           #20 clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sim_1/new/simulation.v:10: Can\'t find definition of \'mIM\' in dotted scope/variable: \'mTOP.mIM\'\n           $readmemh ("D:/VIVADO2017.2/repos/single-cycle/single-cycle.srcs/sim_1/new/instructions.txt", mTOP.mIM.im);  \n                                                                                                              ^~~\n        ... Known scopes under \'mTOP\': <no cells found>\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sim_1/new/simulation.v:11: Can\'t find definition of \'mRF\' in dotted scope/variable: \'mTOP.mRF\'\n           $readmemh ("D:/VIVADO2017.2/repos/single-cycle/single-cycle.srcs/sim_1/new/register_file.txt", mTOP.mRF.gpr);  \n                                                                                                               ^~~\n        ... Known scopes under \'mTOP\': <no cells found>\n%Error: data/full_repos/permissive/206017343/single-cycle.srcs/sim_1/new/simulation.v:12: Can\'t find definition of \'mDM\' in dotted scope/variable: \'mTOP.mDM\'\n           $readmemh ("D:/VIVADO2017.2/repos/single-cycle/single-cycle.srcs/sim_1/new/data_memory.txt", mTOP.mDM.dm);  \n                                                                                                             ^~~\n        ... Known scopes under \'mTOP\': <no cells found>\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simulation();
       
       reg clk,rst;

       top mTOP(.clk(clk), .rst(rst));

       initial begin
           $readmemh ("D:/VIVADO2017.2/repos/single-cycle/single-cycle.srcs/sim_1/new/instructions.txt", mTOP.mIM.im);
           $readmemh ("D:/VIVADO2017.2/repos/single-cycle/single-cycle.srcs/sim_1/new/register_file.txt", mTOP.mRF.gpr);
           $readmemh ("D:/VIVADO2017.2/repos/single-cycle/single-cycle.srcs/sim_1/new/data_memory.txt", mTOP.mDM.dm);
           rst = 1;
           clk = 0;
           #10 rst = 0;
       end

       always begin
           #20 clk = ~clk;
       end

endmodule
module simulation();

       
       reg clk,rst;

       top mTOP(.clk(clk), .rst(rst));

       initial begin
           $readmemh ("D:/VIVADO2017.2/repos/single-cycle/single-cycle.srcs/sim_1/new/instructions.txt", mTOP.mIM.im);
           $readmemh ("D:/VIVADO2017.2/repos/single-cycle/single-cycle.srcs/sim_1/new/register_file.txt", mTOP.mRF.gpr);
           $readmemh ("D:/VIVADO2017.2/repos/single-cycle/single-cycle.srcs/sim_1/new/data_memory.txt", mTOP.mDM.dm);
           rst = 1;
           clk = 0;
           #10 rst = 0;
       end

       always begin
           #20 clk = ~clk;
       end

endmodule