data/full_repos/permissive/202473002/Stereo.srcs/sources_1/imports/FPGA/decoders.v
 line:49: before: "/"
data/verilator_xmls/c4074185-c609-4696-925a-087345766ede.xml
module decoder2(out, in, enable);
    
    output [1:0] out;    
    input in;
    input enable;
    
    and a0(out[0], enable, !in);
    and a1(out[1], enable, in);
    
endmodule
module decoder2(out, in, enable);

    
    output [1:0] out;    
    input in;
    input enable;
    
    and a0(out[0], enable, !in);
    and a1(out[1], enable, in);
    
endmodule