data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v
None: at end of input
1: b'%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:1: Cannot find include file: Util/Math.v\n`include "Util/Math.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory,data/full_repos/permissive/131921633/Util/Math.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory,data/full_repos/permissive/131921633/Util/Math.v.v\n             data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory,data/full_repos/permissive/131921633/Util/Math.v.sv\n             Util/Math.v\n             Util/Math.v.v\n             Util/Math.v.sv\n             obj_dir/Util/Math.v\n             obj_dir/Util/Math.v.v\n             obj_dir/Util/Math.v.sv\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:2: Cannot find include file: Util/Delay/array.v\n`include "Util/Delay/array.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:3: Cannot find include file: Data/Control/Control.v\n`include "Data/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:4: Cannot find include file: Data/Control/invert.v\n`include "Data/Control/invert.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:5: Cannot find include file: Data/Memory/bam.v\n`include "Data/Memory/bam.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:7: Cannot find include file: Mips/Control/Control.v\n`include "Mips/Control/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:8: Cannot find include file: Mips/Control/Signal/Memory/Control.v\n`include "Mips/Control/Signal/Memory/Control.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:9: Cannot find include file: Mips/Control/Signal/Memory/Signal/ByteEnable.v\n`include "Mips/Control/Signal/Memory/Signal/ByteEnable.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:10: Cannot find include file: Mips/Control/Signal/Memory/Signal/ByteExtend.v\n`include "Mips/Control/Signal/Memory/Signal/ByteExtend.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:11: Cannot find include file: Mips/Control/Signal/Memory/Signal/WriteEnable.v\n`include "Mips/Control/Signal/Memory/Signal/WriteEnable.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:13: Cannot find include file: Mips/Datapath/Memory/byteEnable.v\n`include "Mips/Datapath/Memory/byteEnable.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:14: Cannot find include file: Mips/Datapath/Memory/outMask.v\n`include "Mips/Datapath/Memory/outMask.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:16: Cannot find include file: Mips/Type/Word.v\n`include "Mips/Type/Word.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:23: Define or directive not defined: \'`Data_Control_Control_T\'\n ( `Data_Control_Control_T (input) ctrl\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:23: syntax error, unexpected \'(\', expecting \'[\'\n ( `Data_Control_Control_T (input) ctrl\n                            ^~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:24: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T       (input) aluResult\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:25: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T       (input) regPort2\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:26: Define or directive not defined: \'`Mips_Control_Control_T\'\n , `Mips_Control_Control_T (input) control\n   ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:27: Define or directive not defined: \'`Mips_Type_Word_T\'\n , `Mips_Type_Word_T       (output) out\n   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:30: Define or directive not defined: \'`Util_Math_log2_expr\'\n`Util_Math_log2_expr\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:32: Define or directive not defined: \'`Mips_Control_Signal_Memory_Control_T\'\n`Mips_Control_Signal_Memory_Control_T (wire) memControl;\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:33: Define or directive not defined: \'`Mips_Control_Control_Memory\'\nassign memControl = `Mips_Control_Control_Memory(control);\n                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:34: Define or directive not defined: \'`Mips_Control_Signal_Memory_Control_T\'\n`Mips_Control_Signal_Memory_Control_T (reg) memControl$;\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:35: Define or directive not defined: \'`Data_Control_Control_Clock\'\nalways @(posedge `Data_Control_Control_Clock(ctrl))\n                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:38: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) memAddr;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:41: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T (wire) memData;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:45: syntax error, unexpected IDENTIFIER\nMips_Datapath_Memory_byteEnable BYTE\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:46: Define or directive not defined: \'`Mips_Control_Signal_Memory_Control_ByteEnable\'\n ( .control (`Mips_Control_Signal_Memory_Control_ByteEnable(memControl))\n             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:50: Define or directive not defined: \'`Data_Control_Control_T\'\n`Data_Control_Control_T(wire) ctrl$;\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:61: Define or directive not defined: \'`Mips_Type_Word_T\'\n`Mips_Type_Word_T(wire) memOut;\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:70: Define or directive not defined: \'`Mips_Control_Signal_Memory_Control_WriteEnable\'\n , .wren  (`Mips_Control_Signal_Memory_Control_WriteEnable(memControl))\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/131921633/tv/Mips/Datapath/Memory/datapath.v:74: Define or directive not defined: \'`Mips_Control_Signal_Memory_Control_ByteEnable\'\n ( .control (`Mips_Control_Signal_Memory_Control_ByteEnable(memControl$))\n             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 32 error(s)\n'
module Mips_Datapath_Memory_datapath #
	( parameter ADDR_L = 64
	, parameter ADDR_W = Util_Math_log2(ADDR_L)
	, parameter INVERT_CTRL = 1
	)
	( `Data_Control_Control_T (input) ctrl
	, `Mips_Type_Word_T       (input) aluResult
	, `Mips_Type_Word_T       (input) regPort2
	, `Mips_Control_Control_T (input) control
	, `Mips_Type_Word_T       (output) out
	);

`Util_Math_log2_expr

`Mips_Control_Signal_Memory_Control_T (wire) memControl;
assign memControl = `Mips_Control_Control_Memory(control);
`Mips_Control_Signal_Memory_Control_T (reg) memControl$;
always @(posedge `Data_Control_Control_Clock(ctrl))
	memControl$ <= memControl;

`Mips_Type_Word_T (wire) memAddr;
assign memAddr = aluResult;

`Mips_Type_Word_T (wire) memData;
assign memData = regPort2;

wire [3:0] byteEnable;
Mips_Datapath_Memory_byteEnable BYTE
	( .control (`Mips_Control_Signal_Memory_Control_ByteEnable(memControl))
	, .byteEnable (byteEnable)
	);

`Data_Control_Control_T(wire) ctrl$;
generate
	if(INVERT_CTRL)
		Data_Control_invert CTRLINV
			( .in (ctrl)
			, .out (ctrl$)
			);
	else
		assign ctrl$ = ctrl;
endgenerate

`Mips_Type_Word_T(wire) memOut;
Data_Memory_bam #
	( .ADDR_WORD_L (ADDR_L)
	) BAM
	( .ctrl  (ctrl$)
	, .addr  (memAddr[ADDR_W+1:0])
	, .data  (memData)
	, .bytes (byteEnable)
	, .out   (memOut)
	, .wren  (`Mips_Control_Signal_Memory_Control_WriteEnable(memControl))
	);

Mips_Datapath_Memory_outMask MASK
	( .control (`Mips_Control_Signal_Memory_Control_ByteEnable(memControl$))
	, .in (memOut)
	, .out (out)
	);

endmodule
module Mips_Datapath_Memory_datapath #
	( parameter ADDR_L = 64
	, parameter ADDR_W = Util_Math_log2(ADDR_L)
	, parameter INVERT_CTRL = 1
	)
	( `Data_Control_Control_T (input) ctrl
	, `Mips_Type_Word_T       (input) aluResult
	, `Mips_Type_Word_T       (input) regPort2
	, `Mips_Control_Control_T (input) control
	, `Mips_Type_Word_T       (output) out
	);


`Util_Math_log2_expr

`Mips_Control_Signal_Memory_Control_T (wire) memControl;
assign memControl = `Mips_Control_Control_Memory(control);
`Mips_Control_Signal_Memory_Control_T (reg) memControl$;
always @(posedge `Data_Control_Control_Clock(ctrl))
	memControl$ <= memControl;

`Mips_Type_Word_T (wire) memAddr;
assign memAddr = aluResult;

`Mips_Type_Word_T (wire) memData;
assign memData = regPort2;

wire [3:0] byteEnable;
Mips_Datapath_Memory_byteEnable BYTE
	( .control (`Mips_Control_Signal_Memory_Control_ByteEnable(memControl))
	, .byteEnable (byteEnable)
	);

`Data_Control_Control_T(wire) ctrl$;
generate
	if(INVERT_CTRL)
		Data_Control_invert CTRLINV
			( .in (ctrl)
			, .out (ctrl$)
			);
	else
		assign ctrl$ = ctrl;
endgenerate

`Mips_Type_Word_T(wire) memOut;
Data_Memory_bam #
	( .ADDR_WORD_L (ADDR_L)
	) BAM
	( .ctrl  (ctrl$)
	, .addr  (memAddr[ADDR_W+1:0])
	, .data  (memData)
	, .bytes (byteEnable)
	, .out   (memOut)
	, .wren  (`Mips_Control_Signal_Memory_Control_WriteEnable(memControl))
	);

Mips_Datapath_Memory_outMask MASK
	( .control (`Mips_Control_Signal_Memory_Control_ByteEnable(memControl$))
	, .in (memOut)
	, .out (out)
	);

endmodule