data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v
 line:20: before: "integer"
1: b'%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:117: Cannot find file containing module: \'IBUFGDS\'\n IBUFGDS #(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/IBUFGDS\n             data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/IBUFGDS.v\n             data/full_repos/permissive/11584509/experimental/CM1,data/full_repos/permissive/11584509/IBUFGDS.sv\n             IBUFGDS\n             IBUFGDS.v\n             IBUFGDS.sv\n             obj_dir/IBUFGDS\n             obj_dir/IBUFGDS.v\n             obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:127: Cannot find file containing module: \'BUFG\'\n BUFG CLK_COMM_BUF\n ^~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:134: Cannot find file containing module: \'main_dcm\'\n main_dcm #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:154: Cannot find file containing module: \'dcm_controller\'\n dcm_controller #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:172: Cannot find file containing module: \'hub_core\'\n   hub_core #(\n   ^~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:186: Cannot find file containing module: \'serial_core\'\n serial_core #(\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:210: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                     : ... In instance HASHVOODOO\n reg [3:0]syncloadnonce = 3\'d0;\n                          ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:221: Cannot find file containing module: \'pbkdfengine\'\n pbkdfengine #(.SBITS(SBITS)) P1\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:228: Cannot find file containing module: \'salsaengine\'\n salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:263: Cannot find file containing module: \'flasher\'\n flasher #(\n ^~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:271: Cannot find file containing module: \'pwm_fade\'\n pwm_fade PWM_FADE_NONCE (\n ^~~~~~~~\n%Error: data/full_repos/permissive/11584509/experimental/CM1/hashvoodoo.v:278: Cannot find file containing module: \'pwm_fade\'\n pwm_fade PWM_FADE_COMM (\n ^~~~~~~~\n%Error: Exiting due to 11 error(s), 1 warning(s)\n'
module HASHVOODOO (
		clk_p, 
		clk_n, 
		clk_comm, 
		RxD, 
		TxD, 
		led, 
		dip, 
		reset_a, 
		reset_b, 
		reset_select
	);

	function integer clog2;
		input integer value;
		begin
		value = value-1;
		for (clog2=0; value>0; clog2=clog2+1)
		value = value>>1;
		end
	endfunction



	parameter CLOCK_RATE = 25000000;
	parameter DCM_DIVIDER = 10;
	parameter DCM_MULTIPLIER_START = 70;
	parameter DCM_MULTIPLIER_CAP = 120;
	parameter DCM_MULTIPLIER_MIN = 20;
	parameter UART_BAUD_RATE = 115200;
	parameter UART_SAMPLE_POINT = 8;
	parameter CLOCK_FLASH_BITS = 26;



`ifdef DUALCORE
	localparam LOCAL_MINERS = 2;
`else
	localparam LOCAL_MINERS = 1;
`endif

	localparam ADDRBITS = 12 - clog2(LOCAL_MINERS);
	localparam SBITS = 8;
	


   input clk_p;
   input clk_n;
   input clk_comm;
   input RxD;
   output TxD;
   output [3:0] led;
	input [3:0]dip;
	input reset_a;
	input reset_b;
	input reset_select;



	reg reset;
	wire clk_buf;
	wire clk_dcm;
	wire clk_comm_buf;
	wire clock_flash;
	wire miner_busy;
	wire serial_send;
	wire serial_busy;
	wire [31:0] golden_nonce;
	wire [255:0] data1, data2;
	wire [127:0] data3;
	wire start_mining;
	wire syncstart_mining;
	reg syncstart_mining_d = 1'b0;
	wire led_nonce_fade;
	wire led_serial_fade;
	wire dcm_prog_en;
	wire dcm_prog_data;
	wire dcm_prog_done;
	wire dcm_valid;
	wire dcm_reset = 1'b0;
	wire identify_flag;
	wire identify_flasher;
	
	reg [3:0] syncticket1 = 0;
	wire got_ticket1;
`ifdef DUALCORE
	wire [63:0] slave_nonces;
	reg [1:0] new_nonces;
	reg [3:0] syncticket2 = 0;
	wire got_ticket2;
`else
	wire [31:0] slave_nonces;
	reg [0:0] new_nonces;
`endif




	assign led[0] = (led_serial_fade || identify_flasher);
	assign led[1] = (clock_flash || ~dcm_valid || identify_flasher);


	assign led[2] = (led_nonce_fade || identify_flasher);
	assign led[3] = (~miner_busy || identify_flasher);
	assign identify_flasher = (clock_flash && identify_flag);
	



`ifndef SIM	

	IBUFGDS #(
			.DIFF_TERM("TRUE"),
			.IOSTANDARD("DEFAULT")
		) CLK_LVDS_BUF (
			.O(clk_buf),
			.I(clk_p),
			.IB(clk_n)
		);
	

	BUFG CLK_COMM_BUF
		(
			.I   (clk_comm),
			.O   (clk_comm_buf)
		);


	main_dcm #(
			.DCM_DIVIDER(DCM_DIVIDER),
			.DCM_MULTIPLIER(DCM_MULTIPLIER_START)
		) MAINDCM(
			.RESET(dcm_reset),
			.CLK_VALID(dcm_valid),
			.CLK_OSC(clk_buf), 
			.CLK_HASH(clk_dcm),
			.PROGCLK(clk_comm_buf),
			.PROGDATA(dcm_prog_data),
			.PROGEN(dcm_prog_en),
			.PROGDONE(dcm_prog_done)
		);
`else
	assign clk_buf = clk_p;
	assign clk_dcm = clk_buf;
	assign clk_comm_buf = clk_comm;
`endif


	dcm_controller #(
			.MAXIMUM_MULTIPLIER(DCM_MULTIPLIER_CAP),
			.MINIMUM_MULTIPLIER(DCM_MULTIPLIER_MIN),
			.INITIAL_MULTIPLIER(DCM_MULTIPLIER_START),
			.INITIAL_DIVIDER(DCM_DIVIDER)
		) DCM_CONTROL (
			.clk(clk_comm_buf),
			.data2({data2[255:96], data3[95:0]}),
			.midstate(data1),
			.start(start_mining),
			.dcm_prog_clk(clk_comm_buf),
			.dcm_prog_en(dcm_prog_en),
			.dcm_prog_data(dcm_prog_data),
			.dcm_prog_done(dcm_prog_done),
			.identify(identify_flag)
		);
	

   hub_core #(
			.SLAVES(LOCAL_MINERS)
		) HUBCORE (
			.hash_clk(clk_comm_buf), 
			.new_nonces(new_nonces), 
			.golden_nonce(golden_nonce), 
			.serial_send(serial_send), 
			.serial_busy(serial_busy), 
			.slave_nonces(slave_nonces)
		);
	

	wire unused_rx_busy;
	
	serial_core #(
			.CLOCK(CLOCK_RATE),
			.BAUD(UART_BAUD_RATE),
			.SAMPLE_POINT(UART_SAMPLE_POINT)
		) SERIAL_COMM (
			.clk(clk_comm_buf),
			.rx(RxD),
			.tx(TxD),
			.rx_ready(start_mining),
			.tx_ready(serial_send),
			.data1(data1),
			.data2(data2),
			.data3(data3),
			.word(golden_nonce),
			.tx_busy(serial_busy),
			.rx_busy(unused_rx_busy)
		);
	
	wire [31:0] unused_nonce_out1, unused_hash_out1;
	wire [31:0] unused_nonce_out2, unused_hash_out2;
	


	reg loadnonce = 1'b0;
	reg [3:0]syncloadnonce = 3'd0;

	wire [31:0] mod_target = 32'h00007fff;

	wire gn_match_1;
	wire [31:0] golden_nonce_1;
	wire [31:0] hash_1, nonce_out_1;
	wire salsa_busy_1, salsa_result_1, salsa_reset_1, salsa_start_1, salsa_shift_1;
	wire [SBITS-1:0] salsa_din_1;
	wire [SBITS-1:0] salsa_dout_1;

	pbkdfengine #(.SBITS(SBITS)) P1
		(.hash_clk(clk_dcm), .pbkdf_clk(clk_dcm), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
		.nonce_msb( 4'd0 ), .nonce_out(nonce_out_1), .golden_nonce_out(golden_nonce_1),
		.golden_nonce_match(gn_match_1), .loadnonce(loadnonce),
		.salsa_din(salsa_din_1), .salsa_dout(salsa_dout_1), .salsa_busy(salsa_busy_1), .salsa_result(salsa_result_1),
		.salsa_reset(salsa_reset_1), .salsa_start(salsa_start_1), .salsa_shift(salsa_shift_1), .hash_out(hash_1));

	salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1
		(.hash_clk(clk_dcm), .reset(salsa_reset_1), .din(salsa_din_1), .dout(salsa_dout_1),
		.shift(salsa_shift_1), .start(salsa_start_1), .busy(salsa_busy_1), .result(salsa_result_1) );

`ifdef DUALCORE
	wire gn_match_2;
	wire [31:0] golden_nonce_2;
	wire [31:0] hash_2, nonce_out_2;
	wire salsa_busy_2, salsa_result_2, salsa_reset_2, salsa_start_2, salsa_shift_2;
	wire [SBITS-1:0] salsa_din_2;
	wire [SBITS-1:0] salsa_dout_2;

	pbkdfengine #(.SBITS(SBITS)) P2
		(.hash_clk(clk_dcm), .pbkdf_clk(clk_dcm), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
		.nonce_msb( 4'd8 ), .nonce_out(nonce_out_2), .golden_nonce_out(golden_nonce_2),
		.golden_nonce_match(gn_match_2), .loadnonce(loadnonce),
		.salsa_din(salsa_din_2), .salsa_dout(salsa_dout_2), .salsa_busy(salsa_busy_2), .salsa_result(salsa_result_2),
		.salsa_reset(salsa_reset_2), .salsa_start(salsa_start_2), .salsa_shift(salsa_shift_2), .hash_out(hash_2));

	salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S2
		(.hash_clk(clk_dcm), .reset(salsa_reset_2), .din(salsa_din_2), .dout(salsa_dout_2),
		.shift(salsa_shift_2), .start(salsa_start_2), .busy(salsa_busy_2), .result(salsa_result_2) );

	assign got_ticket1 = gn_match_1;
	assign got_ticket2 = gn_match_2;
	assign slave_nonces = { golden_nonce_2 , golden_nonce_1 };
`else

	assign got_ticket1 = gn_match_1;
	assign slave_nonces = golden_nonce_1;
`endif

	assign miner_busy = ~ (|nonce_out_1[30:20]);


	flasher #(
			.BITS(CLOCK_FLASH_BITS)
		) CLK_FLASH (
			.clk(clk_dcm),
			.flash(clock_flash)
		);
	

	pwm_fade PWM_FADE_NONCE (
			.clk(clk_comm_buf), 
			.trigger(|new_nonces), 
			.drive(led_nonce_fade)
		);	


	pwm_fade PWM_FADE_COMM (
			.clk(clk_comm_buf), 
			.trigger(~TxD || ~RxD), 
			.drive(led_serial_fade)
		);	
	


`ifdef SIM	
	assign syncstart_mining = reset_a;
`else
	assign syncstart_mining = start_mining;
`endif

	always@ (posedge clk_dcm)
		begin
			if (got_ticket1)
				syncticket1[0] <= ~syncticket1[0];
`ifdef DUALCORE
			if (got_ticket2)
				syncticket2[0] <= ~syncticket2[0];
`endif
			syncloadnonce[3:1] <= syncloadnonce[2:0];
			loadnonce <= (syncloadnonce[3] != syncloadnonce[2]);
		end

	always@ (posedge clk_comm_buf)
		begin
			syncticket1[3:1] <= syncticket1[2:0];
			new_nonces[0] <= (syncticket1[3] != syncticket1[2]);
`ifdef DUALCORE
			syncticket2[3:1] <= syncticket2[2:0];
			new_nonces[1] <= (syncticket2[3] != syncticket2[2]);
`endif
		syncstart_mining_d <= syncstart_mining;
		if (syncstart_mining & ~syncstart_mining_d)
			syncloadnonce[0] <= ~ syncloadnonce[0];
		end

endmodule
module HASHVOODOO (
		clk_p, 
		clk_n, 
		clk_comm, 
		RxD, 
		TxD, 
		led, 
		dip, 
		reset_a, 
		reset_b, 
		reset_select
	);


	function integer clog2;
		input integer value;
		begin
		value = value-1;
		for (clog2=0; value>0; clog2=clog2+1)
		value = value>>1;
		end
	endfunction



	parameter CLOCK_RATE = 25000000;
	parameter DCM_DIVIDER = 10;
	parameter DCM_MULTIPLIER_START = 70;
	parameter DCM_MULTIPLIER_CAP = 120;
	parameter DCM_MULTIPLIER_MIN = 20;
	parameter UART_BAUD_RATE = 115200;
	parameter UART_SAMPLE_POINT = 8;
	parameter CLOCK_FLASH_BITS = 26;



`ifdef DUALCORE
	localparam LOCAL_MINERS = 2;
`else
	localparam LOCAL_MINERS = 1;
`endif

	localparam ADDRBITS = 12 - clog2(LOCAL_MINERS);
	localparam SBITS = 8;
	


   input clk_p;
   input clk_n;
   input clk_comm;
   input RxD;
   output TxD;
   output [3:0] led;
	input [3:0]dip;
	input reset_a;
	input reset_b;
	input reset_select;



	reg reset;
	wire clk_buf;
	wire clk_dcm;
	wire clk_comm_buf;
	wire clock_flash;
	wire miner_busy;
	wire serial_send;
	wire serial_busy;
	wire [31:0] golden_nonce;
	wire [255:0] data1, data2;
	wire [127:0] data3;
	wire start_mining;
	wire syncstart_mining;
	reg syncstart_mining_d = 1'b0;
	wire led_nonce_fade;
	wire led_serial_fade;
	wire dcm_prog_en;
	wire dcm_prog_data;
	wire dcm_prog_done;
	wire dcm_valid;
	wire dcm_reset = 1'b0;
	wire identify_flag;
	wire identify_flasher;
	
	reg [3:0] syncticket1 = 0;
	wire got_ticket1;
`ifdef DUALCORE
	wire [63:0] slave_nonces;
	reg [1:0] new_nonces;
	reg [3:0] syncticket2 = 0;
	wire got_ticket2;
`else
	wire [31:0] slave_nonces;
	reg [0:0] new_nonces;
`endif




	assign led[0] = (led_serial_fade || identify_flasher);
	assign led[1] = (clock_flash || ~dcm_valid || identify_flasher);


	assign led[2] = (led_nonce_fade || identify_flasher);
	assign led[3] = (~miner_busy || identify_flasher);
	assign identify_flasher = (clock_flash && identify_flag);
	



`ifndef SIM	

	IBUFGDS #(
			.DIFF_TERM("TRUE"),
			.IOSTANDARD("DEFAULT")
		) CLK_LVDS_BUF (
			.O(clk_buf),
			.I(clk_p),
			.IB(clk_n)
		);
	

	BUFG CLK_COMM_BUF
		(
			.I   (clk_comm),
			.O   (clk_comm_buf)
		);


	main_dcm #(
			.DCM_DIVIDER(DCM_DIVIDER),
			.DCM_MULTIPLIER(DCM_MULTIPLIER_START)
		) MAINDCM(
			.RESET(dcm_reset),
			.CLK_VALID(dcm_valid),
			.CLK_OSC(clk_buf), 
			.CLK_HASH(clk_dcm),
			.PROGCLK(clk_comm_buf),
			.PROGDATA(dcm_prog_data),
			.PROGEN(dcm_prog_en),
			.PROGDONE(dcm_prog_done)
		);
`else
	assign clk_buf = clk_p;
	assign clk_dcm = clk_buf;
	assign clk_comm_buf = clk_comm;
`endif


	dcm_controller #(
			.MAXIMUM_MULTIPLIER(DCM_MULTIPLIER_CAP),
			.MINIMUM_MULTIPLIER(DCM_MULTIPLIER_MIN),
			.INITIAL_MULTIPLIER(DCM_MULTIPLIER_START),
			.INITIAL_DIVIDER(DCM_DIVIDER)
		) DCM_CONTROL (
			.clk(clk_comm_buf),
			.data2({data2[255:96], data3[95:0]}),
			.midstate(data1),
			.start(start_mining),
			.dcm_prog_clk(clk_comm_buf),
			.dcm_prog_en(dcm_prog_en),
			.dcm_prog_data(dcm_prog_data),
			.dcm_prog_done(dcm_prog_done),
			.identify(identify_flag)
		);
	

   hub_core #(
			.SLAVES(LOCAL_MINERS)
		) HUBCORE (
			.hash_clk(clk_comm_buf), 
			.new_nonces(new_nonces), 
			.golden_nonce(golden_nonce), 
			.serial_send(serial_send), 
			.serial_busy(serial_busy), 
			.slave_nonces(slave_nonces)
		);
	

	wire unused_rx_busy;
	
	serial_core #(
			.CLOCK(CLOCK_RATE),
			.BAUD(UART_BAUD_RATE),
			.SAMPLE_POINT(UART_SAMPLE_POINT)
		) SERIAL_COMM (
			.clk(clk_comm_buf),
			.rx(RxD),
			.tx(TxD),
			.rx_ready(start_mining),
			.tx_ready(serial_send),
			.data1(data1),
			.data2(data2),
			.data3(data3),
			.word(golden_nonce),
			.tx_busy(serial_busy),
			.rx_busy(unused_rx_busy)
		);
	
	wire [31:0] unused_nonce_out1, unused_hash_out1;
	wire [31:0] unused_nonce_out2, unused_hash_out2;
	


	reg loadnonce = 1'b0;
	reg [3:0]syncloadnonce = 3'd0;

	wire [31:0] mod_target = 32'h00007fff;

	wire gn_match_1;
	wire [31:0] golden_nonce_1;
	wire [31:0] hash_1, nonce_out_1;
	wire salsa_busy_1, salsa_result_1, salsa_reset_1, salsa_start_1, salsa_shift_1;
	wire [SBITS-1:0] salsa_din_1;
	wire [SBITS-1:0] salsa_dout_1;

	pbkdfengine #(.SBITS(SBITS)) P1
		(.hash_clk(clk_dcm), .pbkdf_clk(clk_dcm), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
		.nonce_msb( 4'd0 ), .nonce_out(nonce_out_1), .golden_nonce_out(golden_nonce_1),
		.golden_nonce_match(gn_match_1), .loadnonce(loadnonce),
		.salsa_din(salsa_din_1), .salsa_dout(salsa_dout_1), .salsa_busy(salsa_busy_1), .salsa_result(salsa_result_1),
		.salsa_reset(salsa_reset_1), .salsa_start(salsa_start_1), .salsa_shift(salsa_shift_1), .hash_out(hash_1));

	salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1
		(.hash_clk(clk_dcm), .reset(salsa_reset_1), .din(salsa_din_1), .dout(salsa_dout_1),
		.shift(salsa_shift_1), .start(salsa_start_1), .busy(salsa_busy_1), .result(salsa_result_1) );

`ifdef DUALCORE
	wire gn_match_2;
	wire [31:0] golden_nonce_2;
	wire [31:0] hash_2, nonce_out_2;
	wire salsa_busy_2, salsa_result_2, salsa_reset_2, salsa_start_2, salsa_shift_2;
	wire [SBITS-1:0] salsa_din_2;
	wire [SBITS-1:0] salsa_dout_2;

	pbkdfengine #(.SBITS(SBITS)) P2
		(.hash_clk(clk_dcm), .pbkdf_clk(clk_dcm), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
		.nonce_msb( 4'd8 ), .nonce_out(nonce_out_2), .golden_nonce_out(golden_nonce_2),
		.golden_nonce_match(gn_match_2), .loadnonce(loadnonce),
		.salsa_din(salsa_din_2), .salsa_dout(salsa_dout_2), .salsa_busy(salsa_busy_2), .salsa_result(salsa_result_2),
		.salsa_reset(salsa_reset_2), .salsa_start(salsa_start_2), .salsa_shift(salsa_shift_2), .hash_out(hash_2));

	salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S2
		(.hash_clk(clk_dcm), .reset(salsa_reset_2), .din(salsa_din_2), .dout(salsa_dout_2),
		.shift(salsa_shift_2), .start(salsa_start_2), .busy(salsa_busy_2), .result(salsa_result_2) );

	assign got_ticket1 = gn_match_1;
	assign got_ticket2 = gn_match_2;
	assign slave_nonces = { golden_nonce_2 , golden_nonce_1 };
`else

	assign got_ticket1 = gn_match_1;
	assign slave_nonces = golden_nonce_1;
`endif

	assign miner_busy = ~ (|nonce_out_1[30:20]);


	flasher #(
			.BITS(CLOCK_FLASH_BITS)
		) CLK_FLASH (
			.clk(clk_dcm),
			.flash(clock_flash)
		);
	

	pwm_fade PWM_FADE_NONCE (
			.clk(clk_comm_buf), 
			.trigger(|new_nonces), 
			.drive(led_nonce_fade)
		);	


	pwm_fade PWM_FADE_COMM (
			.clk(clk_comm_buf), 
			.trigger(~TxD || ~RxD), 
			.drive(led_serial_fade)
		);	
	


`ifdef SIM	
	assign syncstart_mining = reset_a;
`else
	assign syncstart_mining = start_mining;
`endif

	always@ (posedge clk_dcm)
		begin
			if (got_ticket1)
				syncticket1[0] <= ~syncticket1[0];
`ifdef DUALCORE
			if (got_ticket2)
				syncticket2[0] <= ~syncticket2[0];
`endif
			syncloadnonce[3:1] <= syncloadnonce[2:0];
			loadnonce <= (syncloadnonce[3] != syncloadnonce[2]);
		end

	always@ (posedge clk_comm_buf)
		begin
			syncticket1[3:1] <= syncticket1[2:0];
			new_nonces[0] <= (syncticket1[3] != syncticket1[2]);
`ifdef DUALCORE
			syncticket2[3:1] <= syncticket2[2:0];
			new_nonces[1] <= (syncticket2[3] != syncticket2[2]);
`endif
		syncstart_mining_d <= syncstart_mining;
		if (syncstart_mining & ~syncstart_mining_d)
			syncloadnonce[0] <= ~ syncloadnonce[0];
		end

endmodule