data/full_repos/permissive/169496369/shiftright.v
data/verilator_xmls/f0276167-6152-4f69-873d-0ee02e722ea4.xml
module shiftright(a, sbits, o);
    input [23:0]a;
    input [7:0]sbits;
    
    output logic [23:0]o;
    
    assign o = (a >> sbits);
endmodule
module shiftright(a, sbits, o);

    input [23:0]a;
    input [7:0]sbits;
    
    output logic [23:0]o;
    
    assign o = (a >> sbits);
endmodule