data/full_repos/permissive/125927162/HC1645/piso.v
None: at end of input
data/verilator_xmls/a44584df-32d7-4ba2-983f-12f514abbead.xml
module piso (clk, shld, q_n, q, ser, parin);
   parameter WIDTH = 8;
   input clk;
   input shld;
   input ser;
   input [WIDTH-1:0] parin;
   output q_n;
   output q;

   reg [WIDTH-1:0] data;
   
   always @ (posedge clk)
      if (shld) begin
	 data[WIDTH-2:0] <= data[WIDTH-1:1];
	 data[WIDTH-1] <= ser;
      end

   always @ (negedge shld) data <= parin;

   assign q = data[0];
   assign q_n = ~data[0];
endmodule
module piso (clk, shld, q_n, q, ser, parin);

   parameter WIDTH = 8;
   input clk;
   input shld;
   input ser;
   input [WIDTH-1:0] parin;
   output q_n;
   output q;

   reg [WIDTH-1:0] data;
   
   always @ (posedge clk)
      if (shld) begin
	 data[WIDTH-2:0] <= data[WIDTH-1:1];
	 data[WIDTH-1] <= ser;
      end

   always @ (negedge shld) data <= parin;

   assign q = data[0];
   assign q_n = ~data[0];
endmodule