data/full_repos/permissive/143344034/hdl/anton_neopixel_registers.v
 line:60: before: "localparam"
1: b'%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_registers.v:1: Cannot find include file: anton_common.vh\n`include "anton_common.vh" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143344034/hdl,data/full_repos/permissive/143344034/anton_common.vh\n             data/full_repos/permissive/143344034/hdl,data/full_repos/permissive/143344034/anton_common.vh.v\n             data/full_repos/permissive/143344034/hdl,data/full_repos/permissive/143344034/anton_common.vh.sv\n             anton_common.vh\n             anton_common.vh.v\n             anton_common.vh.sv\n             obj_dir/anton_common.vh\n             obj_dir/anton_common.vh.v\n             obj_dir/anton_common.vh.sv\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_registers.v:4: Define or directive not defined: \'`BUFFER_END_DEFAULT\'\n  parameter  BUFFER_END  = `BUFFER_END_DEFAULT,  \n                           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_registers.v:4: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  parameter  BUFFER_END  = `BUFFER_END_DEFAULT,  \n                                              ^\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_registers.v:5: Define or directive not defined: \'`CLOG2\'\n  localparam BUFFER_BITS = `CLOG2(BUFFER_END+1)  \n                           ^~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_registers.v:6: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_registers.v:49: syntax error, unexpected IDENTIFIER\n  anton_ram_2port_raddreg #(\n  ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143344034/hdl/anton_neopixel_registers.v:50: Define or directive not defined: \'`SANITIZE_BUFFER_END\'\n    .BUFFER_END(`SANITIZE_BUFFER_END(BUFFER_END))\n                ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module anton_neopixel_registers #(
  parameter  BUFFER_END  = `BUFFER_END_DEFAULT,
  localparam BUFFER_BITS = `CLOG2(BUFFER_END+1)
)(
  input                    busClk,
  input  [13:0]            busAddr,
  input  [7:0]             busDataIn,
  input                    busWrite,
  input                    busRead,
  output [7:0]             busDataOut,

  input  [BUFFER_BITS-1:0] pixelIxComb,
  output [7:0]             pixelByte,

  input                    streamSyncOf,

  input                    syncStart,
  input                    state,
  output [12:0]            regMax,
  output                   regCtrlInit,
  output                   regCtrlLimit,
  output                   regCtrlRun,
  output                   regCtrlLoop,
  output                   regCtrl32bit,
  output                   initSlow,
  input                    initSlowDone
);

  reg  [7:0]             busDataOutB;



  reg  [12:0]            regMaxB; 

  reg                    initSlowB     = 'b0;
  
  reg                    regCtrlInitB  = 'b0;
  reg                    regCtrlLimitB = 'b0;
  reg                    regCtrlRunB   = 'b0;
  reg                    regCtrlLoopB  = 'b0;
  reg                    regCtrl32bitB = 'b0;

  reg                    ramTwoPortWrite = 'b0;



  anton_ram_2port_raddreg #(
    .BUFFER_END(`SANITIZE_BUFFER_END(BUFFER_END))
  ) tpram(
    .clk(busClk), 

    .rAddr(pixelIxComb), 
    .dOut(pixelByte),

    .wr(ramTwoPortWrite), 
    .wAddr(busAddr[BUFFER_BITS-1:0]), 
    .dIn(busDataIn)
  );




  
  always @(posedge busClk) begin
    if (streamSyncOf) regCtrlRunB <= regCtrlLoopB;

    if (syncStart) regCtrlRunB <= 'b1;

    if (initSlowDone) begin
      regCtrlInitB <= 'b0;
      initSlowB    <= 'b0;
    end

    if (regCtrlInitB) begin
      regCtrlLimitB <= 'b0;
      regCtrlRunB   <= 'b0;
      regCtrlLoopB  <= 'b0;
      regCtrl32bitB <= 'b0;

      initSlowB     <= 'b1;
    end

    ramTwoPortWrite <= 'b0;
    if (busWrite) begin
      if (busAddr[13] == 'b0) begin
        ramTwoPortWrite <= 'b1;
      end else begin



        case (busAddr[2:0])
          0: regMaxB[7:0]  <= busDataIn;
          1: regMaxB[12:8] <= busDataIn[4:0];
          2: {regCtrl32bitB, regCtrlLoopB, regCtrlRunB, regCtrlLimitB, regCtrlInitB} <= busDataIn[4:0];
        endcase
      end
    end

    if (busRead) begin
      if (busAddr[13] == 'b0) begin


        busDataOutB <= 8'b11111111;
      end else begin


          case (busAddr[2:0])
          0: busDataOutB <= regMaxB[7:0];
          1: busDataOutB <= { 3'b000, regMaxB[12:8] };
          2: busDataOutB <= { 3'b000, regCtrl32bitB, regCtrlLoopB, regCtrlRunB, regCtrlLimitB, regCtrlInitB };
          3: busDataOutB <= { 7'b0000000, state };
        endcase
      end
    end
  end


  assign busDataOut   = busDataOutB;
  assign regMax       = regMaxB;
  assign initSlow     = initSlowB;
  assign regCtrlInit  = regCtrlInitB;
  assign regCtrlLimit = regCtrlLimitB;
  assign regCtrlRun   = regCtrlRunB;
  assign regCtrlLoop  = regCtrlLoopB;
  assign regCtrl32bit = regCtrl32bitB;

endmodule
module anton_neopixel_registers #(
  parameter  BUFFER_END  = `BUFFER_END_DEFAULT,
  localparam BUFFER_BITS = `CLOG2(BUFFER_END+1)
)(
  input                    busClk,
  input  [13:0]            busAddr,
  input  [7:0]             busDataIn,
  input                    busWrite,
  input                    busRead,
  output [7:0]             busDataOut,

  input  [BUFFER_BITS-1:0] pixelIxComb,
  output [7:0]             pixelByte,

  input                    streamSyncOf,

  input                    syncStart,
  input                    state,
  output [12:0]            regMax,
  output                   regCtrlInit,
  output                   regCtrlLimit,
  output                   regCtrlRun,
  output                   regCtrlLoop,
  output                   regCtrl32bit,
  output                   initSlow,
  input                    initSlowDone
);


  reg  [7:0]             busDataOutB;



  reg  [12:0]            regMaxB; 

  reg                    initSlowB     = 'b0;
  
  reg                    regCtrlInitB  = 'b0;
  reg                    regCtrlLimitB = 'b0;
  reg                    regCtrlRunB   = 'b0;
  reg                    regCtrlLoopB  = 'b0;
  reg                    regCtrl32bitB = 'b0;

  reg                    ramTwoPortWrite = 'b0;



  anton_ram_2port_raddreg #(
    .BUFFER_END(`SANITIZE_BUFFER_END(BUFFER_END))
  ) tpram(
    .clk(busClk), 

    .rAddr(pixelIxComb), 
    .dOut(pixelByte),

    .wr(ramTwoPortWrite), 
    .wAddr(busAddr[BUFFER_BITS-1:0]), 
    .dIn(busDataIn)
  );




  
  always @(posedge busClk) begin
    if (streamSyncOf) regCtrlRunB <= regCtrlLoopB;

    if (syncStart) regCtrlRunB <= 'b1;

    if (initSlowDone) begin
      regCtrlInitB <= 'b0;
      initSlowB    <= 'b0;
    end

    if (regCtrlInitB) begin
      regCtrlLimitB <= 'b0;
      regCtrlRunB   <= 'b0;
      regCtrlLoopB  <= 'b0;
      regCtrl32bitB <= 'b0;

      initSlowB     <= 'b1;
    end

    ramTwoPortWrite <= 'b0;
    if (busWrite) begin
      if (busAddr[13] == 'b0) begin
        ramTwoPortWrite <= 'b1;
      end else begin



        case (busAddr[2:0])
          0: regMaxB[7:0]  <= busDataIn;
          1: regMaxB[12:8] <= busDataIn[4:0];
          2: {regCtrl32bitB, regCtrlLoopB, regCtrlRunB, regCtrlLimitB, regCtrlInitB} <= busDataIn[4:0];
        endcase
      end
    end

    if (busRead) begin
      if (busAddr[13] == 'b0) begin


        busDataOutB <= 8'b11111111;
      end else begin


          case (busAddr[2:0])
          0: busDataOutB <= regMaxB[7:0];
          1: busDataOutB <= { 3'b000, regMaxB[12:8] };
          2: busDataOutB <= { 3'b000, regCtrl32bitB, regCtrlLoopB, regCtrlRunB, regCtrlLimitB, regCtrlInitB };
          3: busDataOutB <= { 7'b0000000, state };
        endcase
      end
    end
  end


  assign busDataOut   = busDataOutB;
  assign regMax       = regMaxB;
  assign initSlow     = initSlowB;
  assign regCtrlInit  = regCtrlInitB;
  assign regCtrlLimit = regCtrlLimitB;
  assign regCtrlRun   = regCtrlRunB;
  assign regCtrlLoop  = regCtrlLoopB;
  assign regCtrl32bit = regCtrl32bitB;

endmodule