data/full_repos/permissive/174263347/scanconv/hdl/vga.v
data/verilator_xmls/9ad79bcc-ffa1-4845-8d9c-2c0bd4cddaf1.xml
module myFAILINGEX (clk, reset, ena, in, out);

	input	clk;
	input	reset;
	input	ena;
	input	in;
	output	out;

	reg		[1:0] rise;

	always @ (posedge clk or posedge reset) 
	begin
		if(reset)
			rise <= 0;
		else if (ena)
			rise <= {rise[0], in};
	end
	
	assign out	= rise[1] & ~rise[0];

endmodule
module myFAILINGEX (clk, reset, ena, in, out);


	input	clk;
	input	reset;
	input	ena;
	input	in;
	output	out;

	reg		[1:0] rise;

	always @ (posedge clk or posedge reset) 
	begin
		if(reset)
			rise <= 0;
		else if (ena)
			rise <= {rise[0], in};
	end
	
	assign out	= rise[1] & ~rise[0];

endmodule