data/full_repos/permissive/174510456/blinky_soc/blinky_soc.v
 line:193: before: ")"
1: b"%Error: data/full_repos/permissive/174510456/blinky_soc/blinky_soc.v:108: Cannot find file containing module: 'pll'\n    pll u_pll(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/174510456/blinky_soc,data/full_repos/permissive/174510456/pll\n             data/full_repos/permissive/174510456/blinky_soc,data/full_repos/permissive/174510456/pll.v\n             data/full_repos/permissive/174510456/blinky_soc,data/full_repos/permissive/174510456/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Error: data/full_repos/permissive/174510456/blinky_soc/blinky_soc.v:114: Cannot find file containing module: 'baud_rate_gen'\n    baud_rate_gen u_br_gen(\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/174510456/blinky_soc/blinky_soc.v:175: Cannot find file containing module: 'transmitter'\n    transmitter u_tx(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/174510456/blinky_soc/blinky_soc.v:186: Cannot find file containing module: 'data_mem'\n    data_mem u_data_mem (\n    ^~~~~~~~\n%Error: data/full_repos/permissive/174510456/blinky_soc/blinky_soc.v:198: Cannot find file containing module: 'rom_blinky_hello_world'\n    rom_blinky_hello_world u_inst_mem (\n    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/174510456/blinky_soc/blinky_soc.v:213: Cannot find file containing module: 'noobs_cpu'\n    noobs_cpu u_noobs_cpu(\n    ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module blinky_soc (
    clk,
    LED,
    uart_tx
);

    input   clk;
    output  LED;
    output  uart_tx;

    reg [25:0] counter;
    always @(posedge clk) begin
        counter <= counter + 1'b1;
    end



    reg[23:0] prim_reset_gen_cnt;
    reg[23:0] sec_reset_gen_cnt;
    always @(posedge clk) begin
        if(prim_reset_gen_cnt != 24'hffffff)
            prim_reset_gen_cnt <= prim_reset_gen_cnt + 1'b1;
    end

    wire prim_rst_;
    assign prim_rst_ = (prim_reset_gen_cnt == 24'hffffff);

    always @(posedge clk) begin
        if(!prim_rst_) begin
            sec_reset_gen_cnt <= 24'h0;
        end
        else if(sec_reset_gen_cnt != 24'hffffff) begin
            sec_reset_gen_cnt <= sec_reset_gen_cnt + 1'b1;
        end
    end

    wire sec_rst_;
    assign sec_rst_ = (sec_reset_gen_cnt == 24'hffffff);

    wire system_reset_;
    assign system_reset_ = prim_rst_ & sec_rst_;





    wire cpu_clk =  clk;

    wire [7:0] i_data;
    wire [7:0] m_rd_data;
    wire [7:0] m_wr_data;

    wire [10:0] m_addr;
    wire [10:0] i_addr;

    wire m_rd;
    wire m_wr;
    wire m_en;


    wire [11:0] data_mem_addr;
    assign data_mem_addr = (m_addr - 8);



    reg led_out;
    reg led_out_next;

    always @(posedge cpu_clk) begin
        if(!system_reset_) begin
            led_out <= 1'b1;
        end
        else begin
            led_out <= led_out_next;
        end
    end

    always @(*) begin
        if((m_addr == `LED_M_ADDR) && m_wr & m_en) begin
            led_out_next = |m_wr_data;
        end
        else begin
            led_out_next = led_out;
        end
    end

    assign LED = led_out;



    wire clk50m;
    wire txclk_en;
    wire tx;
    assign uart_tx = tx;

    pll u_pll(
	    .clock_in(clk),
	    .clock_out(clk50m),
	    .locked()
	);

    baud_rate_gen u_br_gen(
        .clk_50m(clk50m),
		.rxclk_en(),
		.txclk_en(txclk_en)
    );

    reg [7:0] tx_data_out;
    reg [7:0] tx_data_out_next;

    reg tx_data_wr;
    reg tx_data_wr_next;
    always @(posedge cpu_clk) begin
        if(!system_reset_) begin
            tx_data_out <= 8'd0;
            tx_data_wr  <= 1'b0;
        end
        else begin
            tx_data_out <= tx_data_out_next;
            tx_data_wr  <= tx_data_wr_next;
        end
    end

    always @(*) begin
        if((m_addr == `UART_TX_M_ADDR) && m_wr & m_en) begin
            tx_data_out_next = m_wr_data;
            tx_data_wr_next = 1'b1;
        end
        else begin
            tx_data_out_next = tx_data_out;
            tx_data_wr_next = 1'b0;
        end
    end

    reg tx_wr;
    reg tx_wr_q;
    always @(posedge clk50m) begin
        if(!system_reset_) begin
            tx_wr   <= 1'b0;
            tx_wr_q <= 1'b0;
        end
        else begin
            tx_wr     <= tx_data_wr;
            tx_wr_q   <= tx_wr;
        end
    end

    wire wr_en;
    assign wr_en = tx_wr & (tx_wr ^ tx_wr_q);

    wire tx_busy;

    wire [7:0] cpu_rd_data;
    always @(*) begin
        if((m_addr == `UART_TX_M_ADDR) & m_rd & m_en) begin
            cpu_rd_data = {7'd0,tx_busy};
        end
        else begin
            cpu_rd_data = m_rd_data;
        end
    end

    transmitter u_tx(
           .din(tx_data_out),
		   .wr_en(wr_en),
		   .clk_50m(clk50m),
		   .clken(txclk_en),
		   .tx(tx),
		   .tx_busy(tx_busy)
     );



    data_mem u_data_mem (
        .clk(cpu_clk),
        .addr(data_mem_addr),
        .rd_data(m_rd_data),
        .wr_data(m_wr_data),
        .wr(m_wr),
        .rd(m_rd),
    );


    `define _BLINKY_ROM_
    `ifdef _BLINKY_ROM_
    rom_blinky_hello_world u_inst_mem (
        .addr(i_addr),
        .data(i_data),
    );
    `else
    inst_mem u_inst_mem (
        .clk(cpu_clk),
        .addr(i_addr),
        .rd_data(i_data),
        .rd(1'b1),
    );
    `endif



    noobs_cpu u_noobs_cpu(
        .clk(cpu_clk),
        .reset_(system_reset_),
        .i_data(i_data),
        .i_addr(i_addr),
        .m_wr_data(m_wr_data),
        .m_rd_data(cpu_rd_data),
        .m_addr(m_addr),
        .m_rd(m_rd),
        .m_wr(m_wr),
        .m_en(m_en)
    );

endmodule
module blinky_soc (
    clk,
    LED,
    uart_tx
);


    input   clk;
    output  LED;
    output  uart_tx;

    reg [25:0] counter;
    always @(posedge clk) begin
        counter <= counter + 1'b1;
    end



    reg[23:0] prim_reset_gen_cnt;
    reg[23:0] sec_reset_gen_cnt;
    always @(posedge clk) begin
        if(prim_reset_gen_cnt != 24'hffffff)
            prim_reset_gen_cnt <= prim_reset_gen_cnt + 1'b1;
    end

    wire prim_rst_;
    assign prim_rst_ = (prim_reset_gen_cnt == 24'hffffff);

    always @(posedge clk) begin
        if(!prim_rst_) begin
            sec_reset_gen_cnt <= 24'h0;
        end
        else if(sec_reset_gen_cnt != 24'hffffff) begin
            sec_reset_gen_cnt <= sec_reset_gen_cnt + 1'b1;
        end
    end

    wire sec_rst_;
    assign sec_rst_ = (sec_reset_gen_cnt == 24'hffffff);

    wire system_reset_;
    assign system_reset_ = prim_rst_ & sec_rst_;





    wire cpu_clk =  clk;

    wire [7:0] i_data;
    wire [7:0] m_rd_data;
    wire [7:0] m_wr_data;

    wire [10:0] m_addr;
    wire [10:0] i_addr;

    wire m_rd;
    wire m_wr;
    wire m_en;


    wire [11:0] data_mem_addr;
    assign data_mem_addr = (m_addr - 8);



    reg led_out;
    reg led_out_next;

    always @(posedge cpu_clk) begin
        if(!system_reset_) begin
            led_out <= 1'b1;
        end
        else begin
            led_out <= led_out_next;
        end
    end

    always @(*) begin
        if((m_addr == `LED_M_ADDR) && m_wr & m_en) begin
            led_out_next = |m_wr_data;
        end
        else begin
            led_out_next = led_out;
        end
    end

    assign LED = led_out;



    wire clk50m;
    wire txclk_en;
    wire tx;
    assign uart_tx = tx;

    pll u_pll(
	    .clock_in(clk),
	    .clock_out(clk50m),
	    .locked()
	);

    baud_rate_gen u_br_gen(
        .clk_50m(clk50m),
		.rxclk_en(),
		.txclk_en(txclk_en)
    );

    reg [7:0] tx_data_out;
    reg [7:0] tx_data_out_next;

    reg tx_data_wr;
    reg tx_data_wr_next;
    always @(posedge cpu_clk) begin
        if(!system_reset_) begin
            tx_data_out <= 8'd0;
            tx_data_wr  <= 1'b0;
        end
        else begin
            tx_data_out <= tx_data_out_next;
            tx_data_wr  <= tx_data_wr_next;
        end
    end

    always @(*) begin
        if((m_addr == `UART_TX_M_ADDR) && m_wr & m_en) begin
            tx_data_out_next = m_wr_data;
            tx_data_wr_next = 1'b1;
        end
        else begin
            tx_data_out_next = tx_data_out;
            tx_data_wr_next = 1'b0;
        end
    end

    reg tx_wr;
    reg tx_wr_q;
    always @(posedge clk50m) begin
        if(!system_reset_) begin
            tx_wr   <= 1'b0;
            tx_wr_q <= 1'b0;
        end
        else begin
            tx_wr     <= tx_data_wr;
            tx_wr_q   <= tx_wr;
        end
    end

    wire wr_en;
    assign wr_en = tx_wr & (tx_wr ^ tx_wr_q);

    wire tx_busy;

    wire [7:0] cpu_rd_data;
    always @(*) begin
        if((m_addr == `UART_TX_M_ADDR) & m_rd & m_en) begin
            cpu_rd_data = {7'd0,tx_busy};
        end
        else begin
            cpu_rd_data = m_rd_data;
        end
    end

    transmitter u_tx(
           .din(tx_data_out),
		   .wr_en(wr_en),
		   .clk_50m(clk50m),
		   .clken(txclk_en),
		   .tx(tx),
		   .tx_busy(tx_busy)
     );



    data_mem u_data_mem (
        .clk(cpu_clk),
        .addr(data_mem_addr),
        .rd_data(m_rd_data),
        .wr_data(m_wr_data),
        .wr(m_wr),
        .rd(m_rd),
    );


    `define _BLINKY_ROM_
    `ifdef _BLINKY_ROM_
    rom_blinky_hello_world u_inst_mem (
        .addr(i_addr),
        .data(i_data),
    );
    `else
    inst_mem u_inst_mem (
        .clk(cpu_clk),
        .addr(i_addr),
        .rd_data(i_data),
        .rd(1'b1),
    );
    `endif



    noobs_cpu u_noobs_cpu(
        .clk(cpu_clk),
        .reset_(system_reset_),
        .i_data(i_data),
        .i_addr(i_addr),
        .m_wr_data(m_wr_data),
        .m_rd_data(cpu_rd_data),
        .m_addr(m_addr),
        .m_rd(m_rd),
        .m_wr(m_wr),
        .m_en(m_en)
    );

endmodule