data/full_repos/permissive/212981921/rtl/ls93.v
None: at end of input
data/verilator_xmls/bdbcf9af-37fb-4047-8a2b-5d0f0f8c6c99.xml
module ls93
(
    input wire  _cp0,_cp1, mr1, mr2,
    output reg  q0, q1, q2, q3
);

wire mr;
assign mr = (mr1 & mr2);

always @(negedge _cp0 or posedge mr) begin
    if (mr == 1'b1) begin
        q0 <= 1'b0;
    end else begin
        q0 <= ~q0;
    end
end

always @(negedge q0 or posedge mr) begin
    if (mr == 1'b1) begin
        q1 <= 1'b0;
    end else begin
        q1 <= ~q1;
    end
end

always @(negedge q1 or posedge mr) begin
    if (mr == 1'b1) begin
        q2 <= 1'b0;
    end else begin
        q2 <= ~q2;
    end
end

always @(negedge q2 or posedge mr) begin
    if (mr == 1'b1) begin
        q3 <= 1'b0;
    end else begin
        q3 <= ~q3;
    end
end

endmodule
module ls93
(
    input wire  _cp0,_cp1, mr1, mr2,
    output reg  q0, q1, q2, q3
);


wire mr;
assign mr = (mr1 & mr2);

always @(negedge _cp0 or posedge mr) begin
    if (mr == 1'b1) begin
        q0 <= 1'b0;
    end else begin
        q0 <= ~q0;
    end
end

always @(negedge q0 or posedge mr) begin
    if (mr == 1'b1) begin
        q1 <= 1'b0;
    end else begin
        q1 <= ~q1;
    end
end

always @(negedge q1 or posedge mr) begin
    if (mr == 1'b1) begin
        q2 <= 1'b0;
    end else begin
        q2 <= ~q2;
    end
end

always @(negedge q2 or posedge mr) begin
    if (mr == 1'b1) begin
        q3 <= 1'b0;
    end else begin
        q3 <= ~q3;
    end
end

endmodule