data/full_repos/permissive/143278/ivltests/delay5.v
 line:3: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/delay5.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #1 drive <= 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/delay5.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #9 if (trace !== drive) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/delay5.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #7 if (trace !== 1\'b1) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/delay5.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #2 if (trace !== drive) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/delay5.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #1 drive <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/delay5.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #5 if (trace !== 1\'b0) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/delay5.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #2 if (trace !== drive) begin\n      ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   time period;
   reg	drive;



   wire #(period/3) trace = drive;

   initial begin
      period = 8*3;


      #1 drive <= 1;
      #9 if (trace !== drive) begin
	 $display("FAILED -- time=%0t, drive=%b, trace=%b",
		  $time, drive, trace);
	 $finish;
      end


      drive <= 0;

      #7 if (trace !== 1'b1) begin
	 $display("FAILED -- time=%0t, drive=%b, trace=%b",
		  $time, drive, trace);
	 $finish;
      end
      #2 if (trace !== drive) begin
	 $display("FAILED -- time=%0t, drive=%b, trace=%b",
		  $time, drive, trace);
	 $finish;
      end


      period = 6*3;


      #1 drive <= 1;

      #5 if (trace !== 1'b0) begin
	 $display("FAILED -- time=%0t, drive=%b, trace=%b",
		  $time, drive, trace);
	 $finish;
      end

      #2 if (trace !== drive) begin
	 $display("FAILED -- time=%0t, drive=%b, trace=%b",
		  $time, drive, trace);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   time period;
   reg	drive;



   wire #(period/3) trace = drive;

   initial begin
      period = 8*3;


      #1 drive <= 1;
      #9 if (trace !== drive) begin
	 $display("FAILED -- time=%0t, drive=%b, trace=%b",
		  $time, drive, trace);
	 $finish;
      end


      drive <= 0;

      #7 if (trace !== 1'b1) begin
	 $display("FAILED -- time=%0t, drive=%b, trace=%b",
		  $time, drive, trace);
	 $finish;
      end
      #2 if (trace !== drive) begin
	 $display("FAILED -- time=%0t, drive=%b, trace=%b",
		  $time, drive, trace);
	 $finish;
      end


      period = 6*3;


      #1 drive <= 1;

      #5 if (trace !== 1'b0) begin
	 $display("FAILED -- time=%0t, drive=%b, trace=%b",
		  $time, drive, trace);
	 $finish;
      end

      #2 if (trace !== drive) begin
	 $display("FAILED -- time=%0t, drive=%b, trace=%b",
		  $time, drive, trace);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule