data/full_repos/permissive/161526648/mux2_1.v
data/verilator_xmls/2008924a-dac2-4010-a2a0-1d349857490f.xml
module mux2_1(src1,src2,sel,result);
	parameter N = 32;
	input [N-1:0] src1,src2;
	input sel;
	output reg [N-1:0] result;
	
	always @(sel,src1,src2) begin
		case (sel)
			1'b0: result = src1;
			1'b1: result = src2;
		endcase
	end
endmodule
module mux2_1(src1,src2,sel,result);

	parameter N = 32;
	input [N-1:0] src1,src2;
	input sel;
	output reg [N-1:0] result;
	
	always @(sel,src1,src2) begin
		case (sel)
			1'b0: result = src1;
			1'b1: result = src2;
		endcase
	end
endmodule