data/full_repos/permissive/157049472/Verilog Test Benches/bram_tb.v
1: b'%Error: Cannot find file containing module: Test\n        ... Looked in:\n             data/full_repos/permissive/157049472/Verilog/Test\n             data/full_repos/permissive/157049472/Verilog/Test.v\n             data/full_repos/permissive/157049472/Verilog/Test.sv\n             Test\n             Test.v\n             Test.sv\n             obj_dir/Test\n             obj_dir/Test.v\n             obj_dir/Test.sv\n%Error: Cannot find file containing module: Benches,data/full_repos/permissive/157049472\n%Error: Cannot find file containing module: data/full_repos/permissive/157049472/Verilog\n%Error: Cannot find file containing module: Benches/bram_tb.v\n%Error: Exiting due to 4 error(s)\n'
module bram_tb;


	reg clka;
	reg rsta;
	reg ena;
	reg [0:0] wea;
	reg [4:0] addra;
	reg [31:0] dina;


	wire [31:0] douta;


	blk_mem_gen_v7_3 uut (
		.clka(clka), 
		.rsta(rsta), 
		.ena(ena), 
		.wea(wea), 
		.addra(addra), 
		.dina(dina), 
		.douta(douta)
	);

	initial begin

		clka = 0;
		rsta = 1;
		ena = 1;
		wea = 0;
		addra = 0;
		dina = 0;


		#100;
        

		#10 rsta = 0;
		#10 addra = 1;
		#10 addra = 2;
		#10 addra = 3;

	end
	always begin
		#5 clka = ~clka;
   end
endmodule
module bram_tb;



	reg clka;
	reg rsta;
	reg ena;
	reg [0:0] wea;
	reg [4:0] addra;
	reg [31:0] dina;


	wire [31:0] douta;


	blk_mem_gen_v7_3 uut (
		.clka(clka), 
		.rsta(rsta), 
		.ena(ena), 
		.wea(wea), 
		.addra(addra), 
		.dina(dina), 
		.douta(douta)
	);

	initial begin

		clka = 0;
		rsta = 1;
		ena = 1;
		wea = 0;
		addra = 0;
		dina = 0;


		#100;
        

		#10 rsta = 0;
		#10 addra = 1;
		#10 addra = 2;
		#10 addra = 3;

	end
	always begin
		#5 clka = ~clka;
   end
endmodule