data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new/Calculator_Top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new/Calculator_Top_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk_tb = ~clk_tb;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new/Calculator_Top_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #10 go_tb=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new/Calculator_Top_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n                        #5 if(cs_tb_1 !== cs_tb_2)\n                        ^\n%Error: data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new/Calculator_Top_tb.v:18: Cannot find file containing module: \'Calculator_Top\'\n    Calculator_Top DUT (\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new,data/full_repos/permissive/128497744/Calculator_Top\n             data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new,data/full_repos/permissive/128497744/Calculator_Top.v\n             data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new,data/full_repos/permissive/128497744/Calculator_Top.sv\n             Calculator_Top\n             Calculator_Top.v\n             Calculator_Top.sv\n             obj_dir/Calculator_Top\n             obj_dir/Calculator_Top.v\n             obj_dir/Calculator_Top.sv\n%Error: data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new/Calculator_Top_tb.v:28: Cannot find file containing module: \'FSM_CU\'\n    FSM_CU CU(\n    ^~~~~~\n%Error: data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new/Calculator_Top_tb.v:36: Cannot find file containing module: \'DP\'\n    DP DP(\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new/Calculator_Top_tb.v:68: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                                                             : ... In instance Calculator_Top_tb\n            In1_tb = i;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new/Calculator_Top_tb.v:71: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'j\' generates 32 bits.\n                                                                                                                                             : ... In instance Calculator_Top_tb\n                In2_tb = j;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/128497744/fsm_calculator_part1/fsm_calculator/fsm_calculator.srcs/sim_1/new/Calculator_Top_tb.v:74: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                                                             : ... In instance Calculator_Top_tb\n                    op_tb = {k};\n                          ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Calculator_Top_tb;

    reg go_tb, clk_tb;
    reg [1:0] op_tb;
    reg [2:0] In1_tb, In2_tb;
    
    wire [3:0] cs_tb_1, cs_tb_2;
    wire [2:0] out_tb_1, out_tb_2;
    wire done_tb_1, done_tb_2;
    
    wire [14:0] cw;
    wire [1:0] s1, wa, raa, rab, c;
    wire we, rea, reb, s2;

    assign {s1, wa, we, raa, rea, rab, reb, c, s2, done_tb_2} = cw;
    
    Calculator_Top DUT (
        .go(go_tb),
        .op(op_tb),
        .clk(clk_tb),
        .in1(In1_tb),
        .in2(In2_tb),
        .cs(cs_tb_1),
        .out(out_tb_1),
        .done(done_tb_1)
        );
    FSM_CU CU(
            .go(go_tb),
            .clk(clk_tb),
            .op(op_tb),
            .cs(cs_tb_2),
            .cw(cw)
            );
                                
    DP DP(
            .in1(In1_tb),
            .in2(In2_tb),
            .s1(s1),
            .wa(wa),
            .raa(raa),
            .rab(rab),
            .c(c),
            .we(we),
            .rea(rea),
            .reb(reb),
            .s2(s2),
            .clk(clk_tb),
            .out(out_tb_2)
            );
    always
    begin
        #1 clk_tb = ~clk_tb;
    end
    
    integer i = 0;
    integer j = 0;
    integer k = 0;
    integer l = 0;
    
    initial
    begin
        $display("Begin Test.\n");
        clk_tb=1'b0;
        #10 go_tb=0;
        for (i=0; i<8; i=i+1)
        begin
            In1_tb = i;
            for (j = 0; j<8; j=j+1)
            begin
                In2_tb = j;
                for (k=0; k<4; k=k+1)
                begin
                    op_tb = {k};
                    go_tb = 1;
                    
                    for (l=0; l<6; l=l+1)
                    begin
                        #5 if(cs_tb_1 !== cs_tb_2)
                        begin
                            $display("ERROR at time %d: Expected cs_tb_1 = %d, found %d instead.\n", $time, cs_tb_1, cs_tb_2);
                            $stop;
                        end
                        else if (out_tb_1 !== out_tb_2)
                        begin
                            $display("ERROR at time %d: Expected out_tb_1 = %d, found %d instead.\n", $time, out_tb_1, out_tb_2);
                            $stop;
                        end
                        else if (done_tb_1 !== done_tb_2)
                        begin
                            $display("ERROR at time %d: Expected done_tb_1 = %d, found %d instead.\n", $time, done_tb_1, done_tb_2);
                            $stop;
                        end
                    end
                end
            end
        end
    $display("Test Sucessfull.\n");
    $finish;
    end    
endmodule
module Calculator_Top_tb;


    reg go_tb, clk_tb;
    reg [1:0] op_tb;
    reg [2:0] In1_tb, In2_tb;
    
    wire [3:0] cs_tb_1, cs_tb_2;
    wire [2:0] out_tb_1, out_tb_2;
    wire done_tb_1, done_tb_2;
    
    wire [14:0] cw;
    wire [1:0] s1, wa, raa, rab, c;
    wire we, rea, reb, s2;

    assign {s1, wa, we, raa, rea, rab, reb, c, s2, done_tb_2} = cw;
    
    Calculator_Top DUT (
        .go(go_tb),
        .op(op_tb),
        .clk(clk_tb),
        .in1(In1_tb),
        .in2(In2_tb),
        .cs(cs_tb_1),
        .out(out_tb_1),
        .done(done_tb_1)
        );
    FSM_CU CU(
            .go(go_tb),
            .clk(clk_tb),
            .op(op_tb),
            .cs(cs_tb_2),
            .cw(cw)
            );
                                
    DP DP(
            .in1(In1_tb),
            .in2(In2_tb),
            .s1(s1),
            .wa(wa),
            .raa(raa),
            .rab(rab),
            .c(c),
            .we(we),
            .rea(rea),
            .reb(reb),
            .s2(s2),
            .clk(clk_tb),
            .out(out_tb_2)
            );
    always
    begin
        #1 clk_tb = ~clk_tb;
    end
    
    integer i = 0;
    integer j = 0;
    integer k = 0;
    integer l = 0;
    
    initial
    begin
        $display("Begin Test.\n");
        clk_tb=1'b0;
        #10 go_tb=0;
        for (i=0; i<8; i=i+1)
        begin
            In1_tb = i;
            for (j = 0; j<8; j=j+1)
            begin
                In2_tb = j;
                for (k=0; k<4; k=k+1)
                begin
                    op_tb = {k};
                    go_tb = 1;
                    
                    for (l=0; l<6; l=l+1)
                    begin
                        #5 if(cs_tb_1 !== cs_tb_2)
                        begin
                            $display("ERROR at time %d: Expected cs_tb_1 = %d, found %d instead.\n", $time, cs_tb_1, cs_tb_2);
                            $stop;
                        end
                        else if (out_tb_1 !== out_tb_2)
                        begin
                            $display("ERROR at time %d: Expected out_tb_1 = %d, found %d instead.\n", $time, out_tb_1, out_tb_2);
                            $stop;
                        end
                        else if (done_tb_1 !== done_tb_2)
                        begin
                            $display("ERROR at time %d: Expected done_tb_1 = %d, found %d instead.\n", $time, done_tb_1, done_tb_2);
                            $stop;
                        end
                    end
                end
            end
        end
    $display("Test Sucessfull.\n");
    $finish;
    end    
endmodule