data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v:107: Operator AND expects 4 bits on the LHS, but LHS\'s VARREF \'wb_cyc_i\' generates 1 bits.\n                                                                                                  : ... In instance minsoc_onchip_ram_top\nassign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; \n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v:107: Operator AND expects 4 bits on the RHS, but RHS\'s VARREF \'wb_stb_i\' generates 1 bits.\n                                                                                                  : ... In instance minsoc_onchip_ram_top\nassign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; \n                        ^\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v:193: Cannot find file containing module: \'minsoc_onchip_ram\'\n        minsoc_onchip_ram block_ram_0 ( \n        ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog,data/full_repos/permissive/19905110/minsoc_onchip_ram\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog,data/full_repos/permissive/19905110/minsoc_onchip_ram.v\n             data/full_repos/permissive/19905110/minsoc/rtl/verilog,data/full_repos/permissive/19905110/minsoc_onchip_ram.sv\n             minsoc_onchip_ram\n             minsoc_onchip_ram.v\n             minsoc_onchip_ram.sv\n             obj_dir/minsoc_onchip_ram\n             obj_dir/minsoc_onchip_ram.v\n             obj_dir/minsoc_onchip_ram.sv\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v:205: Cannot find file containing module: \'minsoc_onchip_ram\'\n        minsoc_onchip_ram block_ram_1 ( \n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v:216: Cannot find file containing module: \'minsoc_onchip_ram\'\n        minsoc_onchip_ram block_ram_2 ( \n        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/19905110/minsoc/rtl/verilog/minsoc_onchip_ram_top.v:227: Cannot find file containing module: \'minsoc_onchip_ram\'\n        minsoc_onchip_ram block_ram_3 ( \n        ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module mux2(sel,in1,in2,out);

parameter dw = 32;

input sel;
input [dw-1:0] in1, in2;
output reg [dw-1:0] out;

always @ (sel or in1 or in2)
begin
	case (sel)
		1'b0: out = in1;
		1'b1: out = in2;
	endcase
end

endmodule
module mux2(sel,in1,in2,out);


parameter dw = 32;

input sel;
input [dw-1:0] in1, in2;
output reg [dw-1:0] out;

always @ (sel or in1 or in2)
begin
	case (sel)
		1'b0: out = in1;
		1'b1: out = in2;
	endcase
end

endmodule