data/full_repos/permissive/214823094/lab_6/project_1/project_1.srcs/sources_1/new/traffic_lights_1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/214823094/lab_6/project_1/project_1.srcs/sources_1/new/traffic_lights_1.v:101: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                                                        : ... In instance traffic_lights_1\n        if(reset)begin counter<=5\'b00000;state<=0;end\n                              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/214823094/lab_6/project_1/project_1.srcs/sources_1/new/traffic_lights_1.v:107: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                                                        : ... In instance traffic_lights_1\n            else if(counter==5\'b11000) begin state<=0;counter<=5\'b00000;end \n                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/214823094/lab_6/project_1/project_1.srcs/sources_1/new/traffic_lights_1.v:107: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h18\' generates 5 bits.\n                                                                                                                        : ... In instance traffic_lights_1\n            else if(counter==5\'b11000) begin state<=0;counter<=5\'b00000;end \n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/214823094/lab_6/project_1/project_1.srcs/sources_1/new/traffic_lights_1.v:106: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h15\' generates 5 bits.\n                                                                                                                        : ... In instance traffic_lights_1\n            else if(counter==5\'b10101) state<=3;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/214823094/lab_6/project_1/project_1.srcs/sources_1/new/traffic_lights_1.v:105: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'hc\' generates 5 bits.\n                                                                                                                        : ... In instance traffic_lights_1\n            else if(counter==5\'b01100) state<=2;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/214823094/lab_6/project_1/project_1.srcs/sources_1/new/traffic_lights_1.v:104: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h9\' generates 5 bits.\n                                                                                                                        : ... In instance traffic_lights_1\n            if(counter==5\'b01001) state<=1;\n                      ^~\n%Error: Exiting due to 6 warning(s)\n'
module traffic_lights_1(input clk, input reset, output reg [2:0] N, output reg [2:0] S, output reg [2:0] E, output reg [2:0] W);
    wire myclk;
reg [5:0] counter; reg [2:0] state;
    clkdiv c1(clk,myclk);
parameter yellow=3'b010; parameter green=3'b001; parameter red=3'b100;
always@(posedge myclk, posedge reset)
    begin
        if(reset)begin counter<=5'b00000;state<=0;end
        else 
begin counter<=counter+1;
            if(counter==5'b01001) state<=1;
            else if(counter==5'b01100) state<=2;
            else if(counter==5'b10101) state<=3;
            else if(counter==5'b11000) begin state<=0;counter<=5'b00000;end 
        end
    end
    always@(state)
    case(state)
    0: begin N<=green; S<=green; E<=red; W<=red; end 
    1: begin N<=yellow; S<=yellow; E<=red; W<=red; end
    2: begin N<=red; S<=red; E<=green; W<=green; end 
    3: begin N<=red; S<=red; E<=yellow; W<=yellow; end
endcase
endmodule
module traffic_lights_1(input clk, input reset, output reg [2:0] N, output reg [2:0] S, output reg [2:0] E, output reg [2:0] W);

    wire myclk;
reg [5:0] counter; reg [2:0] state;
    clkdiv c1(clk,myclk);
parameter yellow=3'b010; parameter green=3'b001; parameter red=3'b100;
always@(posedge myclk, posedge reset)
    begin
        if(reset)begin counter<=5'b00000;state<=0;end
        else 
begin counter<=counter+1;
            if(counter==5'b01001) state<=1;
            else if(counter==5'b01100) state<=2;
            else if(counter==5'b10101) state<=3;
            else if(counter==5'b11000) begin state<=0;counter<=5'b00000;end 
        end
    end
    always@(state)
    case(state)
    0: begin N<=green; S<=green; E<=red; W<=red; end 
    1: begin N<=yellow; S<=yellow; E<=red; W<=red; end
    2: begin N<=red; S<=red; E<=green; W<=green; end 
    3: begin N<=red; S<=red; E<=yellow; W<=yellow; end
endcase
endmodule