data/full_repos/permissive/213397499/verilog/mux2_1.v
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data/verilator_xmls/c91e4834-d0b0-44c3-a90c-330ec5a7146a.xml
module mux2_1
(
  input           up_dat0,
  input           up_dat1,
  input           sel,
  output          dn_dat
);

assign dn_dat=(sel)?up_dat1:up_dat0;

endmodule
module mux2_1
(
  input           up_dat0,
  input           up_dat1,
  input           sel,
  output          dn_dat
);


assign dn_dat=(sel)?up_dat1:up_dat0;

endmodule