data/full_repos/permissive/168753118/rtl/modules/BRU.v
data/verilator_xmls/62f97f94-944c-4f7b-8584-0ee9e1526672.xml
module BRU #(
  parameter DATA_WIDTH = 32
)(
  input bru_prediction_in,
  input [3:0] bru_uop_in,
  input [DATA_WIDTH-1:0] bru_pc_in,
  input [DATA_WIDTH-1:0] bru_rs1_in,
  input [DATA_WIDTH-1:0] bru_rs2_in,
  input [DATA_WIDTH-1:0] bru_imm_in,

  output reg bru_correction_out,
  output reg [DATA_WIDTH-1:0] bru_target_out
);


reg _result_flag;



always @ (*) begin

    case(bru_uop_in)
      4'b0000: _result_flag = (bru_rs1_in == bru_rs2_in) ? 1'b1:1'b0;
      4'b0001: _result_flag = (bru_rs1_in != bru_rs2_in) ? 1'b1:1'b0;
      4'b0010: _result_flag = (bru_rs1_in <  bru_rs2_in) ? 1'b1:1'b0;
      4'b0011: _result_flag = (bru_rs1_in >= bru_rs2_in) ? 1'b1:1'b0;
      4'b0110: _result_flag = 1'b0;
      4'b0111: _result_flag = (bru_rs1_in >  bru_rs2_in) ? 1'b1:1'b0;
      default: _result_flag = 1'b0;
    endcase


    bru_correction_out = (bru_prediction_in == _result_flag) ? 1'b0:1'b1;


    bru_target_out = bru_pc_in + bru_imm_in;

end

endmodule
module BRU #(
  parameter DATA_WIDTH = 32
)(
  input bru_prediction_in,
  input [3:0] bru_uop_in,
  input [DATA_WIDTH-1:0] bru_pc_in,
  input [DATA_WIDTH-1:0] bru_rs1_in,
  input [DATA_WIDTH-1:0] bru_rs2_in,
  input [DATA_WIDTH-1:0] bru_imm_in,

  output reg bru_correction_out,
  output reg [DATA_WIDTH-1:0] bru_target_out
);



reg _result_flag;



always @ (*) begin

    case(bru_uop_in)
      4'b0000: _result_flag = (bru_rs1_in == bru_rs2_in) ? 1'b1:1'b0;
      4'b0001: _result_flag = (bru_rs1_in != bru_rs2_in) ? 1'b1:1'b0;
      4'b0010: _result_flag = (bru_rs1_in <  bru_rs2_in) ? 1'b1:1'b0;
      4'b0011: _result_flag = (bru_rs1_in >= bru_rs2_in) ? 1'b1:1'b0;
      4'b0110: _result_flag = 1'b0;
      4'b0111: _result_flag = (bru_rs1_in >  bru_rs2_in) ? 1'b1:1'b0;
      default: _result_flag = 1'b0;
    endcase


    bru_correction_out = (bru_prediction_in == _result_flag) ? 1'b0:1'b1;


    bru_target_out = bru_pc_in + bru_imm_in;

end

endmodule