data/full_repos/permissive/174323821/hdl/sdram/jtframe_sdram_rq.v
 line:97: before: "/"
1: b"%Error: data/full_repos/permissive/174323821/hdl/sdram/jtframe_sdram_rq.v:78: Cannot find file containing module: 'jtframe_romrq'\n    jtframe_romrq #(.AW(AW),.DW(DW) )u_ro(\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174323821/hdl/sdram,data/full_repos/permissive/174323821/jtframe_romrq\n             data/full_repos/permissive/174323821/hdl/sdram,data/full_repos/permissive/174323821/jtframe_romrq.v\n             data/full_repos/permissive/174323821/hdl/sdram,data/full_repos/permissive/174323821/jtframe_romrq.sv\n             jtframe_romrq\n             jtframe_romrq.v\n             jtframe_romrq.sv\n             obj_dir/jtframe_romrq\n             obj_dir/jtframe_romrq.v\n             obj_dir/jtframe_romrq.sv\n%Error: Exiting due to 1 error(s)\n"
module jtframe_sdram_rq #(parameter AW=18, DW=8, TYPE=0)(
    input               rst,
    input               clk,
    input               clr,
    input [AW-1:0]      addr,
    input [  21:0]      offset,
    input               addr_ok,
    input [31:0]        din,
    input               din_ok,
    input               wrin,
    input               we,
    output              req,
    output              req_rnw,
    output              data_ok,
    output     [21:0]   sdram_addr,
    input    [DW-1:0]   wrdata,
    output   [DW-1:0]   dout
);


generate






if( TYPE==2 ) begin : rw_type
    jtframe_ram_rq #(.AW(AW), .DW(DW) ) u_rw(
        .rst        ( rst           ),
        .clk        ( clk           ),
        .addr       ( addr          ),
        .offset     ( offset        ),
        .addr_ok    ( addr_ok       ),
        .din        ( din           ),
        .din_ok     ( din_ok        ),
        .wrin       ( wrin          ),
        .we         ( we            ),
        .req        ( req           ),
        .req_rnw    ( req_rnw       ),
        .data_ok    ( data_ok       ),
        .sdram_addr ( sdram_addr    ),
        .wrdata     ( wrdata        ),
        .dout       ( dout          )
    );
end




if( TYPE==0) begin : ro_type

    assign req_rnw = 1'b1;

    jtframe_romrq #(.AW(AW),.DW(DW) )u_ro(
        .rst        ( rst       ),
        .clk        ( clk       ),
        .clr        ( clr       ),
        .offset     ( offset    ),
        .addr       ( addr      ),
        .addr_ok    ( addr_ok   ),
        .din        ( din       ),
        .din_ok     ( din_ok    ),
        .we         ( we        ),
        .req        ( req       ),
        .data_ok    ( data_ok   ),
        .sdram_addr ( sdram_addr),
        .dout       ( dout      )
    );
end

endgenerate

endmodule
module jtframe_sdram_rq #(parameter AW=18, DW=8, TYPE=0)(
    input               rst,
    input               clk,
    input               clr,
    input [AW-1:0]      addr,
    input [  21:0]      offset,
    input               addr_ok,
    input [31:0]        din,
    input               din_ok,
    input               wrin,
    input               we,
    output              req,
    output              req_rnw,
    output              data_ok,
    output     [21:0]   sdram_addr,
    input    [DW-1:0]   wrdata,
    output   [DW-1:0]   dout
);



generate






if( TYPE==2 ) begin : rw_type
    jtframe_ram_rq #(.AW(AW), .DW(DW) ) u_rw(
        .rst        ( rst           ),
        .clk        ( clk           ),
        .addr       ( addr          ),
        .offset     ( offset        ),
        .addr_ok    ( addr_ok       ),
        .din        ( din           ),
        .din_ok     ( din_ok        ),
        .wrin       ( wrin          ),
        .we         ( we            ),
        .req        ( req           ),
        .req_rnw    ( req_rnw       ),
        .data_ok    ( data_ok       ),
        .sdram_addr ( sdram_addr    ),
        .wrdata     ( wrdata        ),
        .dout       ( dout          )
    );
end




if( TYPE==0) begin : ro_type

    assign req_rnw = 1'b1;

    jtframe_romrq #(.AW(AW),.DW(DW) )u_ro(
        .rst        ( rst       ),
        .clk        ( clk       ),
        .clr        ( clr       ),
        .offset     ( offset    ),
        .addr       ( addr      ),
        .addr_ok    ( addr_ok   ),
        .din        ( din       ),
        .din_ok     ( din_ok    ),
        .we         ( we        ),
        .req        ( req       ),
        .data_ok    ( data_ok   ),
        .sdram_addr ( sdram_addr),
        .dout       ( dout      )
    );
end

endgenerate

endmodule