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1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:27: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:30: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:36: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:39: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:50: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:53: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:58: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:61: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:72: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:75: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:80: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:83: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:94: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:97: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:102: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:105: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:110: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:113: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:118: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:121: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:126: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:129: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:134: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:137: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:142: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:145: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:150: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:153: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:158: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:162: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:167: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:170: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:175: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:178: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:183: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:186: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:197: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:200: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:205: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:208: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:213: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:216: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:221: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:224: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:229: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:232: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:237: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:240: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:245: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:248: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:253: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:256: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:261: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:265: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:270: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:273: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:278: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:281: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:286: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:289: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:300: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:303: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:308: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:311: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:316: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:319: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:324: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:327: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:332: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:335: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:340: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:343: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:348: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:351: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:356: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:359: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:364: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:368: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:373: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:376: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:381: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:384: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:389: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:392: Unsupported: Ignoring delay on this delayed statement.\n     #1;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:25: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                            : ... In instance test\n     a_reg = $random % L;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:26: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                            : ... In instance test\n     amount = $random % K;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:28: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'a_reg\' generates 9 bits.\n                                                                            : ... In instance test\n     temp = a_reg + amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:28: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                            : ... In instance test\n     temp = a_reg + amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:32: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_reg\' generates 9 bits.\n                                                                            : ... In instance test\n     if (temp !== a_reg) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:37: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'a_reg\' generates 9 bits.\n                                                                            : ... In instance test\n     temp = a_reg - amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:37: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                            : ... In instance test\n     temp = a_reg - amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:40: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_reg\' generates 9 bits.\n                                                                            : ... In instance test\n     if (temp !== a_reg) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:48: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                            : ... In instance test\n     a_bit = $random % L;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:49: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                            : ... In instance test\n     amount = $random % K;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:51: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'a_bit\' generates 9 bits.\n                                                                            : ... In instance test\n     temp = a_bit + amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:51: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                            : ... In instance test\n     temp = a_bit + amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:54: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_bit\' generates 9 bits.\n                                                                            : ... In instance test\n     if (temp !== a_bit) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:59: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'a_bit\' generates 9 bits.\n                                                                            : ... In instance test\n     temp = a_bit - amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:59: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                            : ... In instance test\n     temp = a_bit - amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:62: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_bit\' generates 9 bits.\n                                                                            : ... In instance test\n     if (temp !== a_bit) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:70: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                            : ... In instance test\n     a_byte = $random % L;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:71: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                            : ... In instance test\n     amount = $random % K;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:73: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'a_byte\' generates 8 bits.\n                                                                            : ... In instance test\n     temp = a_byte + amount;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:73: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                            : ... In instance test\n     temp = a_byte + amount;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:76: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_byte\' generates 8 bits.\n                                                                            : ... In instance test\n     if (temp !== a_byte) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:81: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'a_byte\' generates 8 bits.\n                                                                            : ... In instance test\n     temp = a_byte - amount;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:81: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                            : ... In instance test\n     temp = a_byte - amount;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:84: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_byte\' generates 8 bits.\n                                                                            : ... In instance test\n     if (temp !== a_byte) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:92: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n                                                                            : ... In instance test\n     a_short = 2*($random % L);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:93: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n                                                                            : ... In instance test\n     amount = 2*($random % K);\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:95: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                            : ... In instance test\n     temp = a_short + amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:95: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                            : ... In instance test\n     temp = a_short + amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:96: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                            : ... In instance test\n     a_short += amount;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:98: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                            : ... In instance test\n     if (temp !== a_short) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:103: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     temp = a_short - amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:103: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_short - amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:104: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_short -= amount;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:106: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     if (temp !== a_short) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:114: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     if (temp !== a_short) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:119: Operator DIVS expects 32 bits on the LHS, but LHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     temp = a_short / amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:119: Operator DIVS expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_short / amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:120: Operator DIVS expects 16 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_short /= amount;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:122: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     if (temp !== a_short) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:127: Operator MODDIVS expects 32 bits on the LHS, but LHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     temp = a_short % amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:127: Operator MODDIVS expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_short % amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:128: Operator MODDIVS expects 16 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_short %= amount;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:130: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     if (temp !== a_short) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:135: Operator AND expects 32 bits on the LHS, but LHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     temp = a_short & amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:135: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_short & amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:136: Operator AND expects 16 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_short &= amount;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:138: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     if (temp !== a_short) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:143: Operator OR expects 32 bits on the LHS, but LHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     temp = a_short | amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:143: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_short | amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:144: Operator OR expects 16 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_short |= amount;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:146: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     if (temp !== a_short) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:151: Operator XOR expects 32 bits on the LHS, but LHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     temp = a_short ^ amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:151: Operator XOR expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_short ^ amount;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:152: Operator XOR expects 16 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_short ^= amount;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:154: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     if (temp !== a_short) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:159: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MUL generates 32 bits.\n                                                                             : ... In instance test\n     pos = 2*({$random} % K);\n         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:160: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     temp = a_short << pos;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:163: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     if (temp !== a_short) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:168: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     temp = a_short >> pos;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:171: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     if (temp !== a_short) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:176: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     temp = a_short <<< pos;\n                    ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:179: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     if (temp !== a_short) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:184: Operator SHIFTRS expects 32 bits on the LHS, but LHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     temp = a_short >>> pos;\n                    ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:187: Operator NEQCASE expects 32 bits on the RHS, but RHS\'s VARREF \'a_short\' generates 16 bits.\n                                                                             : ... In instance test\n     if (temp !== a_short) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:196: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n                                                                             : ... In instance test\n     amount = 4*($random % K);\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:198: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_int + amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:199: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_int += amount;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:206: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_int - amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:207: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_int -= amount;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:222: Operator DIVS expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_int / amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:223: Operator DIVS expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_int /= amount;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:230: Operator MODDIVS expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_int % amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:231: Operator MODDIVS expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_int %= amount;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:238: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_int & amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:239: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_int &= amount;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:246: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_int | amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:247: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_int |= amount;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:254: Operator XOR expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_int ^ amount;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:255: Operator XOR expects 32 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_int ^= amount;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:262: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MUL generates 32 bits.\n                                                                             : ... In instance test\n     pos = 4*({$random} % K);\n         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:298: Operator MODDIVS expects 64 bits on the LHS, but LHS\'s RAND generates 32 bits.\n                                                                             : ... In instance test\n     a_long = 8*($random % L);\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:299: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MULS generates 32 bits.\n                                                                             : ... In instance test\n     amount = 8*($random % K);\n            ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:301: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_long + amount;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:301: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s ADD generates 64 bits.\n                                                                             : ... In instance test\n     temp = a_long + amount;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:302: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_long += amount;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:304: Operator NEQCASE expects 64 bits on the LHS, but LHS\'s VARREF \'temp\' generates 32 bits.\n                                                                             : ... In instance test\n     if (temp !== a_long) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:309: Operator SUB expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_long - amount;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:309: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SUB generates 64 bits.\n                                                                             : ... In instance test\n     temp = a_long - amount;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:310: Operator SUB expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_long -= amount;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:312: Operator NEQCASE expects 64 bits on the LHS, but LHS\'s VARREF \'temp\' generates 32 bits.\n                                                                             : ... In instance test\n     if (temp !== a_long) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:317: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s MULS generates 64 bits.\n                                                                             : ... In instance test\n     temp = a_long * amount;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:320: Operator NEQCASE expects 64 bits on the LHS, but LHS\'s VARREF \'temp\' generates 32 bits.\n                                                                             : ... In instance test\n     if (temp !== a_long) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:325: Operator DIVS expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_long / amount;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:325: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s DIVS generates 64 bits.\n                                                                             : ... In instance test\n     temp = a_long / amount;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:326: Operator DIVS expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_long /= amount;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:328: Operator NEQCASE expects 64 bits on the LHS, but LHS\'s VARREF \'temp\' generates 32 bits.\n                                                                             : ... In instance test\n     if (temp !== a_long) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:333: Operator MODDIVS expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_long % amount;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:333: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 64 bits.\n                                                                             : ... In instance test\n     temp = a_long % amount;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:334: Operator MODDIVS expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_long %= amount;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:336: Operator NEQCASE expects 64 bits on the LHS, but LHS\'s VARREF \'temp\' generates 32 bits.\n                                                                             : ... In instance test\n     if (temp !== a_long) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:341: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_long & amount;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:341: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s AND generates 64 bits.\n                                                                             : ... In instance test\n     temp = a_long & amount;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:342: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_long &= amount;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:344: Operator NEQCASE expects 64 bits on the LHS, but LHS\'s VARREF \'temp\' generates 32 bits.\n                                                                             : ... In instance test\n     if (temp !== a_long) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:349: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_long | amount;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:349: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s OR generates 64 bits.\n                                                                             : ... In instance test\n     temp = a_long | amount;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:350: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_long |= amount;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:352: Operator NEQCASE expects 64 bits on the LHS, but LHS\'s VARREF \'temp\' generates 32 bits.\n                                                                             : ... In instance test\n     if (temp !== a_long) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:357: Operator XOR expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     temp = a_long ^ amount;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:357: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s XOR generates 64 bits.\n                                                                             : ... In instance test\n     temp = a_long ^ amount;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:358: Operator XOR expects 64 bits on the RHS, but RHS\'s VARREF \'amount\' generates 8 bits.\n                                                                             : ... In instance test\n     a_long ^= amount;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:360: Operator NEQCASE expects 64 bits on the LHS, but LHS\'s VARREF \'temp\' generates 32 bits.\n                                                                             : ... In instance test\n     if (temp !== a_long) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:365: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s MUL generates 32 bits.\n                                                                             : ... In instance test\n     pos = 8*({$random} % K);\n         ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:366: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTL generates 64 bits.\n                                                                             : ... In instance test\n     temp = a_long << pos;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:369: Operator NEQCASE expects 64 bits on the LHS, but LHS\'s VARREF \'temp\' generates 32 bits.\n                                                                             : ... In instance test\n     if (temp !== a_long) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:374: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 64 bits.\n                                                                             : ... In instance test\n     temp = a_long >> pos;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:377: Operator NEQCASE expects 64 bits on the LHS, but LHS\'s VARREF \'temp\' generates 32 bits.\n                                                                             : ... In instance test\n     if (temp !== a_long) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:382: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTL generates 64 bits.\n                                                                             : ... In instance test\n     temp = a_long <<< pos;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:385: Operator NEQCASE expects 64 bits on the LHS, but LHS\'s VARREF \'temp\' generates 32 bits.\n                                                                             : ... In instance test\n     if (temp !== a_long) begin\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:390: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 64 bits.\n                                                                             : ... In instance test\n     temp = a_long >>> pos;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/143278/ivltests/test_inc_dec.v:393: Operator NEQCASE expects 64 bits on the LHS, but LHS\'s VARREF \'temp\' generates 32 bits.\n                                                                             : ... In instance test\n     if (temp !== a_long) begin\n              ^~~\n%Error: Exiting due to 205 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

parameter S = 9;
parameter K = 3;
parameter L = 2**(S-K);
parameter N = 2**(S-1);

reg signed [S-1:0] a_reg;
bit signed [S-1:0] a_bit;
byte signed a_byte;
shortint signed a_short;
int signed a_int;
longint signed a_long;
byte signed amount;
byte unsigned pos;
int temp;
int i;

initial begin

   for (i = 0; i < N; i = i+1) begin
     a_reg = $random % L;
     amount = $random % K;
     #1;
     temp = a_reg + amount;
     a_reg += amount;
     #1;

     if (temp !== a_reg) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_reg - amount;
     a_reg -= amount;
     #1;
     if (temp !== a_reg) begin
        $display("FAILED");
        $finish;
     end
   end


   for (i = 0; i < N; i = i+1) begin
     a_bit = $random % L;
     amount = $random % K;
     #1;
     temp = a_bit + amount;
     a_bit += amount;
     #1;
     if (temp !== a_bit) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_bit - amount;
     a_bit -= amount;
     #1;
     if (temp !== a_bit) begin
        $display("FAILED");
        $finish;
     end
   end


   for (i = 0; i < N; i = i+1) begin
     a_byte = $random % L;
     amount = $random % K;
     #1;
     temp = a_byte + amount;
     a_byte += amount;
     #1;
     if (temp !== a_byte) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_byte - amount;
     a_byte -= amount;
     #1;
     if (temp !== a_byte) begin
        $display("FAILED");
        $finish;
     end
   end


   for (i = 0; i < N; i = i+1) begin
     a_short = 2*($random % L);
     amount = 2*($random % K);
     #1;
     temp = a_short + amount;
     a_short += amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short - amount;
     a_short -= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short * amount;
     a_short *= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short / amount;
     a_short /= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short % amount;
     a_short %= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short & amount;
     a_short &= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short | amount;
     a_short |= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short ^ amount;
     a_short ^= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     pos = 2*({$random} % K);
     temp = a_short << pos;
     a_short <<= pos;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short >> pos;
     a_short >>= pos;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short <<< pos;
     a_short <<<= pos;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short >>> pos;
     a_short >>>= pos;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
   end


   for (i = 0; i < N; i = i+1) begin
     a_int = 4*($random % L);
     amount = 4*($random % K);
     #1;
     temp = a_int + amount;
     a_int += amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int - amount;
     a_int -= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int * amount;
     a_int *= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int / amount;
     a_int /= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int % amount;
     a_int %= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int & amount;
     a_int &= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int | amount;
     a_int |= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int ^ amount;
     a_int ^= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     pos = 4*({$random} % K);
     temp = a_int << pos;
     a_int <<= pos;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int >> pos;
     a_int >>= pos;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int <<< pos;
     a_int <<<= pos;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int >>> pos;
     a_int >>= pos;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
   end


   for (i = 0; i < N; i = i+1) begin
     a_long = 8*($random % L);
     amount = 8*($random % K);
     #1;
     temp = a_long + amount;
     a_long += amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long - amount;
     a_long -= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long * amount;
     a_long *= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long / amount;
     a_long /= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long % amount;
     a_long %= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long & amount;
     a_long &= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long | amount;
     a_long |= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long ^ amount;
     a_long ^= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     pos = 8*({$random} % K);
     temp = a_long << pos;
     a_long <<= pos;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long >> pos;
     a_long >>= pos;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long <<< pos;
     a_long <<<= pos;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long >>> pos;
     a_long >>= pos;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
   end

   $display("PASSED");
   $finish;
end

endmodule
module test;


parameter S = 9;
parameter K = 3;
parameter L = 2**(S-K);
parameter N = 2**(S-1);

reg signed [S-1:0] a_reg;
bit signed [S-1:0] a_bit;
byte signed a_byte;
shortint signed a_short;
int signed a_int;
longint signed a_long;
byte signed amount;
byte unsigned pos;
int temp;
int i;

initial begin

   for (i = 0; i < N; i = i+1) begin
     a_reg = $random % L;
     amount = $random % K;
     #1;
     temp = a_reg + amount;
     a_reg += amount;
     #1;

     if (temp !== a_reg) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_reg - amount;
     a_reg -= amount;
     #1;
     if (temp !== a_reg) begin
        $display("FAILED");
        $finish;
     end
   end


   for (i = 0; i < N; i = i+1) begin
     a_bit = $random % L;
     amount = $random % K;
     #1;
     temp = a_bit + amount;
     a_bit += amount;
     #1;
     if (temp !== a_bit) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_bit - amount;
     a_bit -= amount;
     #1;
     if (temp !== a_bit) begin
        $display("FAILED");
        $finish;
     end
   end


   for (i = 0; i < N; i = i+1) begin
     a_byte = $random % L;
     amount = $random % K;
     #1;
     temp = a_byte + amount;
     a_byte += amount;
     #1;
     if (temp !== a_byte) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_byte - amount;
     a_byte -= amount;
     #1;
     if (temp !== a_byte) begin
        $display("FAILED");
        $finish;
     end
   end


   for (i = 0; i < N; i = i+1) begin
     a_short = 2*($random % L);
     amount = 2*($random % K);
     #1;
     temp = a_short + amount;
     a_short += amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short - amount;
     a_short -= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short * amount;
     a_short *= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short / amount;
     a_short /= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short % amount;
     a_short %= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short & amount;
     a_short &= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short | amount;
     a_short |= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short ^ amount;
     a_short ^= amount;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     pos = 2*({$random} % K);
     temp = a_short << pos;
     a_short <<= pos;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short >> pos;
     a_short >>= pos;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short <<< pos;
     a_short <<<= pos;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_short >>> pos;
     a_short >>>= pos;
     #1;
     if (temp !== a_short) begin
        $display("FAILED");
        $finish;
     end
   end


   for (i = 0; i < N; i = i+1) begin
     a_int = 4*($random % L);
     amount = 4*($random % K);
     #1;
     temp = a_int + amount;
     a_int += amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int - amount;
     a_int -= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int * amount;
     a_int *= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int / amount;
     a_int /= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int % amount;
     a_int %= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int & amount;
     a_int &= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int | amount;
     a_int |= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int ^ amount;
     a_int ^= amount;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     pos = 4*({$random} % K);
     temp = a_int << pos;
     a_int <<= pos;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int >> pos;
     a_int >>= pos;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int <<< pos;
     a_int <<<= pos;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_int >>> pos;
     a_int >>= pos;
     #1;
     if (temp !== a_int) begin
        $display("FAILED");
        $finish;
     end
   end


   for (i = 0; i < N; i = i+1) begin
     a_long = 8*($random % L);
     amount = 8*($random % K);
     #1;
     temp = a_long + amount;
     a_long += amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long - amount;
     a_long -= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long * amount;
     a_long *= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long / amount;
     a_long /= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long % amount;
     a_long %= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long & amount;
     a_long &= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long | amount;
     a_long |= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long ^ amount;
     a_long ^= amount;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     pos = 8*({$random} % K);
     temp = a_long << pos;
     a_long <<= pos;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long >> pos;
     a_long >>= pos;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long <<< pos;
     a_long <<<= pos;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
     #1;
     temp = a_long >>> pos;
     a_long >>= pos;
     #1;
     if (temp !== a_long) begin
        $display("FAILED");
        $finish;
     end
   end

   $display("PASSED");
   $finish;
end

endmodule