data/full_repos/permissive/175100691/gpu/shadercore/Registers.v
1: b"%Error: data/full_repos/permissive/175100691/gpu/shadercore/Registers.v:22: Cannot find file containing module: 'RegisterFile'\n    RegisterFile #(.WORD_WIDTH(WORD_WIDTH), .ADDRESS_WIDTH(ADDRESS_WIDTH))\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175100691/gpu/shadercore,data/full_repos/permissive/175100691/RegisterFile\n             data/full_repos/permissive/175100691/gpu/shadercore,data/full_repos/permissive/175100691/RegisterFile.v\n             data/full_repos/permissive/175100691/gpu/shadercore,data/full_repos/permissive/175100691/RegisterFile.sv\n             RegisterFile\n             RegisterFile.v\n             RegisterFile.sv\n             obj_dir/RegisterFile\n             obj_dir/RegisterFile.v\n             obj_dir/RegisterFile.sv\n%Error: data/full_repos/permissive/175100691/gpu/shadercore/Registers.v:31: Cannot find file containing module: 'RegisterFile'\n    RegisterFile #(.WORD_WIDTH(WORD_WIDTH), .ADDRESS_WIDTH(ADDRESS_WIDTH))\n    ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module Registers
    #(parameter WORD_WIDTH=32, ADDRESS_WIDTH=5) 
(
    input wire clock,


    input wire [ADDRESS_WIDTH-1:0] write_address,
    input wire write,
    input wire [WORD_WIDTH-1:0] write_data,


    input wire [ADDRESS_WIDTH-1:0] read1_address,
    output wire [WORD_WIDTH-1:0] read1_data,


    input wire [ADDRESS_WIDTH-1:0] read2_address,
    output wire [WORD_WIDTH-1:0] read2_data
);

    RegisterFile #(.WORD_WIDTH(WORD_WIDTH), .ADDRESS_WIDTH(ADDRESS_WIDTH))
        bank1(
            .clock(clock),
            .write_address(write_address),
            .write(write),
            .write_data(write_data),
            .read_address(read1_address),
            .read_data(read1_data));

    RegisterFile #(.WORD_WIDTH(WORD_WIDTH), .ADDRESS_WIDTH(ADDRESS_WIDTH))
        bank2(
            .clock(clock),
            .write_address(write_address),
            .write(write),
            .write_data(write_data),
            .read_address(read2_address),
            .read_data(read2_data));

endmodule
module Registers
    #(parameter WORD_WIDTH=32, ADDRESS_WIDTH=5) 
(
    input wire clock,


    input wire [ADDRESS_WIDTH-1:0] write_address,
    input wire write,
    input wire [WORD_WIDTH-1:0] write_data,


    input wire [ADDRESS_WIDTH-1:0] read1_address,
    output wire [WORD_WIDTH-1:0] read1_data,


    input wire [ADDRESS_WIDTH-1:0] read2_address,
    output wire [WORD_WIDTH-1:0] read2_data
);


    RegisterFile #(.WORD_WIDTH(WORD_WIDTH), .ADDRESS_WIDTH(ADDRESS_WIDTH))
        bank1(
            .clock(clock),
            .write_address(write_address),
            .write(write),
            .write_data(write_data),
            .read_address(read1_address),
            .read_data(read1_data));

    RegisterFile #(.WORD_WIDTH(WORD_WIDTH), .ADDRESS_WIDTH(ADDRESS_WIDTH))
        bank2(
            .clock(clock),
            .write_address(write_address),
            .write(write),
            .write_data(write_data),
            .read_address(read2_address),
            .read_data(read2_data));

endmodule