data/full_repos/permissive/152986713/ice40/sprite_renderer.v
1: b'%Error: data/full_repos/permissive/152986713/ice40/sprite_renderer.v:5: Cannot find include file: hvsync_generator.v\n`include "hvsync_generator.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/152986713/ice40,data/full_repos/permissive/152986713/hvsync_generator.v\n             data/full_repos/permissive/152986713/ice40,data/full_repos/permissive/152986713/hvsync_generator.v.v\n             data/full_repos/permissive/152986713/ice40,data/full_repos/permissive/152986713/hvsync_generator.v.sv\n             hvsync_generator.v\n             hvsync_generator.v.v\n             hvsync_generator.v.sv\n             obj_dir/hvsync_generator.v\n             obj_dir/hvsync_generator.v.v\n             obj_dir/hvsync_generator.v.sv\n%Error: data/full_repos/permissive/152986713/ice40/sprite_renderer.v:6: Cannot find include file: sprite_bitmap.v\n`include "sprite_bitmap.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/152986713/ice40/sprite_renderer.v:99: `ifdef not terminated at EOF\n%Error: Exiting due to 3 error(s)\n'
module sprite_renderer(clk, reset,
                       vstart, load, hstart, rom_addr, rom_bits, 
                       gfx, in_progress);
  
  input clk;
  input reset;
  input vstart;
  input load;
  input hstart;
  output reg [3:0] rom_addr;
  input [7:0] rom_bits;
  output reg gfx;
  output in_progress;
  
  reg [2:0] state;
  reg [3:0] ycount;
  reg [3:0] xcount;
  
  reg [7:0] outbits;
  

  localparam WAIT_FOR_VSTART = 0;
  localparam WAIT_FOR_LOAD   = 1;
  localparam LOAD1_SETUP     = 2;
  localparam LOAD1_FETCH     = 3;
  localparam WAIT_FOR_HSTART = 4;
  localparam DRAW            = 5;


  assign in_progress = state != WAIT_FOR_VSTART;

  always @(posedge clk or posedge reset)
    if (reset) begin
      state <= WAIT_FOR_VSTART;
    end else begin
      case (state)
        WAIT_FOR_VSTART: begin
          ycount <= 0;
          gfx <= 0;

          if (vstart)
            state <= WAIT_FOR_LOAD;
        end
        WAIT_FOR_LOAD: begin
          xcount <= 0;
	  gfx <= 0;

          if (load)
            state <= LOAD1_SETUP;
        end
        LOAD1_SETUP: begin
          rom_addr <= ycount;
          state <= LOAD1_FETCH;
        end
        LOAD1_FETCH: begin
	  outbits <= rom_bits;
          state <= WAIT_FOR_HSTART;
        end
        WAIT_FOR_HSTART: begin

          if (hstart)
            state <= DRAW;
        end
        DRAW: begin

          gfx <= outbits[xcount<8 ? xcount[2:0] : ~xcount[2:0]];
          xcount <= xcount + 1;

          if (xcount == 15) begin
            ycount <= ycount + 1;

            if (ycount == 15)
              state <= WAIT_FOR_VSTART;
            else
	      state <= WAIT_FOR_LOAD;
          end
        end

        default: begin
          state <= WAIT_FOR_VSTART; 
        end
      endcase
    end
  
endmodule
module sprite_renderer(clk, reset,
                       vstart, load, hstart, rom_addr, rom_bits, 
                       gfx, in_progress);

  
  input clk;
  input reset;
  input vstart;
  input load;
  input hstart;
  output reg [3:0] rom_addr;
  input [7:0] rom_bits;
  output reg gfx;
  output in_progress;
  
  reg [2:0] state;
  reg [3:0] ycount;
  reg [3:0] xcount;
  
  reg [7:0] outbits;
  

  localparam WAIT_FOR_VSTART = 0;
  localparam WAIT_FOR_LOAD   = 1;
  localparam LOAD1_SETUP     = 2;
  localparam LOAD1_FETCH     = 3;
  localparam WAIT_FOR_HSTART = 4;
  localparam DRAW            = 5;


  assign in_progress = state != WAIT_FOR_VSTART;

  always @(posedge clk or posedge reset)
    if (reset) begin
      state <= WAIT_FOR_VSTART;
    end else begin
      case (state)
        WAIT_FOR_VSTART: begin
          ycount <= 0;
          gfx <= 0;

          if (vstart)
            state <= WAIT_FOR_LOAD;
        end
        WAIT_FOR_LOAD: begin
          xcount <= 0;
	  gfx <= 0;

          if (load)
            state <= LOAD1_SETUP;
        end
        LOAD1_SETUP: begin
          rom_addr <= ycount;
          state <= LOAD1_FETCH;
        end
        LOAD1_FETCH: begin
	  outbits <= rom_bits;
          state <= WAIT_FOR_HSTART;
        end
        WAIT_FOR_HSTART: begin

          if (hstart)
            state <= DRAW;
        end
        DRAW: begin

          gfx <= outbits[xcount<8 ? xcount[2:0] : ~xcount[2:0]];
          xcount <= xcount + 1;

          if (xcount == 15) begin
            ycount <= ycount + 1;

            if (ycount == 15)
              state <= WAIT_FOR_VSTART;
            else
	      state <= WAIT_FOR_LOAD;
          end
        end

        default: begin
          state <= WAIT_FOR_VSTART; 
        end
      endcase
    end
  
endmodule