data/full_repos/permissive/205055389/test/verga/timing1.v
 line:72: before: "$"
1: b'%Error: data/full_repos/permissive/205055389/test/verga/timing1.v:8: Unsupported or unknown PLI call: $monitor\n    $monitor("%4d: ck=%b data=%b en=%b - out=%b",$time,ck,data,en,out);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #50 ck = !ck;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #95;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #85;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #15;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #91; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #9;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #50; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #50;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:39: Unsupported: Ignoring delay on this delayed statement.\n      #95; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:41: Unsupported: Ignoring delay on this delayed statement.\n      #5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #2; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #98;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #2;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #98;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #11;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/205055389/test/verga/timing1.v:57: Unsupported: Ignoring delay on this delayed statement.\n      #89;\n      ^\n%Error: Exiting due to 1 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module latch(ck,data,en,out);
input ck,data,en;
output out;
reg out = 1'bx;

  specify
    $setup(data, posedge ck &&& en, 10);
    $hold(posedge ck &&& en, data, 10);
  endspecify

  always @(posedge ck)
    if (en)
      begin
	 out = data;
      end

endmodule
module latch(ck,data,en,out);

input ck,data,en;
output out;
reg out = 1'bx;

  specify
    $setup(data, posedge ck &&& en, 10);
    $hold(posedge ck &&& en, data, 10);
  endspecify

  always @(posedge ck)
    if (en)
      begin
	 out = data;
      end

endmodule