data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v
None: at end of input
1: b'%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v:13: Cannot find include file: uart_conf.inc\n`include "uart_conf.inc" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart,data/full_repos/permissive/143584361/uart_conf.inc\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart,data/full_repos/permissive/143584361/uart_conf.inc.v\n             data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart,data/full_repos/permissive/143584361/uart_conf.inc.sv\n             uart_conf.inc\n             uart_conf.inc.v\n             uart_conf.inc.sv\n             obj_dir/uart_conf.inc\n             obj_dir/uart_conf.inc.v\n             obj_dir/uart_conf.inc.sv\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v:37: Define or directive not defined: \'`UART_ONE_HALF_CYCLE\'\n  else if(bit_count_zero_flag && base_counter==(`UART_ONE_HALF_CYCLE))\n                                                ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v:37: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  else if(bit_count_zero_flag && base_counter==(`UART_ONE_HALF_CYCLE))\n                                                                    ^\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v:42: Define or directive not defined: \'`UART_ONE_CYCLE\'\n  else if(!bit_count_zero_flag && base_counter == (`UART_ONE_CYCLE))\n                                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v:63: Define or directive not defined: \'`UART_ONE_CYCLE\'\n wire sample = (counter == (`UART_ONE_CYCLE));\n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v:63: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire sample = (counter == (`UART_ONE_CYCLE));\n                                           ^\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v:84: Define or directive not defined: \'`UART_HALF_CYCLE\'\n  else if(bit_count_zero_flag && base_counter==(`UART_HALF_CYCLE))\n                                                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  else if(bit_count_zero_flag && base_counter==(`UART_HALF_CYCLE))\n                                                                ^\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v:187: Define or directive not defined: \'`UART_ONE_CYCLE\'\n     if(tx_cnt>=`UART_ONE_CYCLE)\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v:187: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     if(tx_cnt>=`UART_ONE_CYCLE)\n                               ^\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v:202: syntax error, unexpected else, expecting endcase\n     else \n     ^~~~\n%Error: data/full_repos/permissive/143584361/projects/aFPGA/00_user_logic/uart/uart_rtl.v:206: syntax error, unexpected \':\', expecting clocking\n    default: begin\n           ^\n%Error: Exiting due to 12 error(s)\n'
module uart_rtl(clock,rst,uart_rxd,rx_en,rx_data,uart_txd,tx_en,tx_data,tx_busy);

	input		clock,rst;
	input		uart_rxd;
	output		rx_en;
	output		[7:0]	rx_data;
	output		uart_txd;
	input		tx_en;
	input		[31:0]	tx_data;
	output	reg	tx_busy;
	

	reg			[15:0]	base_counter;
	reg			[3:0]	bit_counter;
	wire		bit_count_zero_flag;
	
	
	reg			ready;
	reg			bit_in;
	
	always @(posedge clock)
		if(rst || !ready)
			base_counter <= 16'D0;
		else if(bit_count_zero_flag && base_counter==(`UART_ONE_HALF_CYCLE))
			begin
				base_counter <= 16'D0;
				bit_in <= 1'B1;
			end
		else if(!bit_count_zero_flag && base_counter == (`UART_ONE_CYCLE))
			begin
				base_counter <= 16'D0;
				bit_in <= 1'B1;
			end
		else
			begin
				base_counter <= base_counter + 16'D1;
				bit_in <= 1'B0;
			end
		
	
	always @(posedge clock)
		if(rst || !ready || (bit_counter == 4'D8 && bit_in && uart_rxd==1'B1))
			bit_counter <= 4'D0;
		else if(bit_in)
			bit_counter <= bit_counter + 4'D1;
	
	assign	bit_count_zero_flag = (bit_counter==4'D0);
	
	reg		[15:0]	counter;
	wire	sample = (counter == (`UART_ONE_CYCLE));
	always @(posedge clock)
		if(rst)
			counter <= 16'D0;
		else if(sample)
			counter <= 16'D0;
		else
			counter <= counter + 16'D1;
	
	reg		[10:0]	recv;
	always @(posedge clock)
		if(rst)
			recv <= 11'H000;
		else if(sample)

			recv <= {recv[9:0],uart_rxd};
			
	reg		first_bit;
	always @(posedge clock)
		if(rst)
			first_bit <= 1'B0;
		else if(bit_count_zero_flag && base_counter==(`UART_HALF_CYCLE))
			first_bit <= uart_rxd;
	
	

	reg		[3:0]	jrxd;
	always @(posedge clock)
		if(rst)
			jrxd <= 4'H0;
		else
			jrxd <= {jrxd[2:0],uart_rxd};
	wire	rxd_dn = (jrxd == 4'HC);
	
	reg		recv_ones;
	always @(posedge clock)
		if(rst)
			recv_ones <= 1'B0;
		else if(recv == 11'H7FF)
			recv_ones <= 1'B1;
		else 
			recv_ones <= 1'B0;
	
	reg		recv_ones_x;
	always @(posedge clock)
		recv_ones_x <= recv_ones;
	wire	recv_ones_up = !recv_ones_x && recv_ones;
	
	always @(posedge clock)
		if(rst || recv_ones_up)
			ready <= 1'B0;
		else if(!ready && rxd_dn)
			ready <= 1'B1;

		else if(ready && bit_counter==4'D8 && bit_in && uart_rxd==1'B1)
			ready <= 1'B0;
		
	reg		[9:0]	ready_x;
	always @(posedge clock)
		if(rst)
			ready_x <= 10'H000;
		else
			ready_x <= {ready_x[8:0],ready};
	
	

	reg		[7:0]	rx_datax;
	reg		[7:0]	data_recv;
	always @(posedge clock)	
		if(rst || !ready)
			rx_datax <= 8'H00;
		else if(ready && bit_in && bit_counter<=4'D7)
			rx_datax <= {uart_rxd,rx_datax[7:1]};
	
	always @(posedge clock)
		if(rst)
			data_recv <= 8'H00;
		else if(ready && bit_counter==4'D8 && bit_in)
			data_recv <= rx_datax;
	
	assign	rx_en = (ready_x==10'H3E0);
	assign	rx_data = data_recv;

	

	integer			i;
	reg		[31:0]	tx_data_reversed;
	always @(*)
		for(i=0; i<32; i=i+1)
			tx_data_reversed[i] = tx_data[31-i];
	

	reg		[31:0]	tx_cnt;
	reg		[43:0]	tx_shifter;
	reg		[9:0]	tx_bit;
	reg		[3:0]	tx_state;
	always @(posedge clock)
		if(rst)
		begin
			tx_shifter <= 44'HFFF_FFFF_FFFF;
			tx_cnt <= 0;
			tx_bit <= 0;
			tx_busy <= 0;
			tx_state <= 0;
		end
		else 
		begin
			case(tx_state)
				0: begin
					if(tx_en)
					begin
						tx_shifter <= {	2'B10, tx_data_reversed[7:0], 1'B1,
										2'B10, tx_data_reversed[15:8], 1'B1,
										2'B10, tx_data_reversed[23:16], 1'B1,
										2'B10, tx_data_reversed[31:24], 1'B1
									};
						tx_busy <= 1;
						tx_cnt <= 0;
						tx_bit <= 0;
						tx_state <= 1;
					end
				end
				
				1: begin
					if(tx_cnt>=`UART_ONE_CYCLE)
					begin
						tx_cnt <= 0;
						if(tx_bit>=43)
						begin
							tx_busy <= 0;
							tx_state <= 0;
							tx_bit <= 0;
						end
						else
						begin
							tx_bit <= tx_bit + 1;
							tx_shifter <= {tx_shifter[42:0], 1'B1};
						end
					end
					else 
						tx_cnt <= tx_cnt + 1;
				end
				
				default: begin
					tx_shifter <= 44'HFFF_FFFF_FFFF;
					tx_cnt <= 0;
					tx_bit <= 0;
					tx_busy <= 0;
					tx_state <= 0;
				end
			endcase
		end
	
	assign	uart_txd = tx_shifter[43];
			
endmodule
module uart_rtl(clock,rst,uart_rxd,rx_en,rx_data,uart_txd,tx_en,tx_data,tx_busy);


	input		clock,rst;
	input		uart_rxd;
	output		rx_en;
	output		[7:0]	rx_data;
	output		uart_txd;
	input		tx_en;
	input		[31:0]	tx_data;
	output	reg	tx_busy;
	

	reg			[15:0]	base_counter;
	reg			[3:0]	bit_counter;
	wire		bit_count_zero_flag;
	
	
	reg			ready;
	reg			bit_in;
	
	always @(posedge clock)
		if(rst || !ready)
			base_counter <= 16'D0;
		else if(bit_count_zero_flag && base_counter==(`UART_ONE_HALF_CYCLE))
			begin
				base_counter <= 16'D0;
				bit_in <= 1'B1;
			end
		else if(!bit_count_zero_flag && base_counter == (`UART_ONE_CYCLE))
			begin
				base_counter <= 16'D0;
				bit_in <= 1'B1;
			end
		else
			begin
				base_counter <= base_counter + 16'D1;
				bit_in <= 1'B0;
			end
		
	
	always @(posedge clock)
		if(rst || !ready || (bit_counter == 4'D8 && bit_in && uart_rxd==1'B1))
			bit_counter <= 4'D0;
		else if(bit_in)
			bit_counter <= bit_counter + 4'D1;
	
	assign	bit_count_zero_flag = (bit_counter==4'D0);
	
	reg		[15:0]	counter;
	wire	sample = (counter == (`UART_ONE_CYCLE));
	always @(posedge clock)
		if(rst)
			counter <= 16'D0;
		else if(sample)
			counter <= 16'D0;
		else
			counter <= counter + 16'D1;
	
	reg		[10:0]	recv;
	always @(posedge clock)
		if(rst)
			recv <= 11'H000;
		else if(sample)

			recv <= {recv[9:0],uart_rxd};
			
	reg		first_bit;
	always @(posedge clock)
		if(rst)
			first_bit <= 1'B0;
		else if(bit_count_zero_flag && base_counter==(`UART_HALF_CYCLE))
			first_bit <= uart_rxd;
	
	

	reg		[3:0]	jrxd;
	always @(posedge clock)
		if(rst)
			jrxd <= 4'H0;
		else
			jrxd <= {jrxd[2:0],uart_rxd};
	wire	rxd_dn = (jrxd == 4'HC);
	
	reg		recv_ones;
	always @(posedge clock)
		if(rst)
			recv_ones <= 1'B0;
		else if(recv == 11'H7FF)
			recv_ones <= 1'B1;
		else 
			recv_ones <= 1'B0;
	
	reg		recv_ones_x;
	always @(posedge clock)
		recv_ones_x <= recv_ones;
	wire	recv_ones_up = !recv_ones_x && recv_ones;
	
	always @(posedge clock)
		if(rst || recv_ones_up)
			ready <= 1'B0;
		else if(!ready && rxd_dn)
			ready <= 1'B1;

		else if(ready && bit_counter==4'D8 && bit_in && uart_rxd==1'B1)
			ready <= 1'B0;
		
	reg		[9:0]	ready_x;
	always @(posedge clock)
		if(rst)
			ready_x <= 10'H000;
		else
			ready_x <= {ready_x[8:0],ready};
	
	

	reg		[7:0]	rx_datax;
	reg		[7:0]	data_recv;
	always @(posedge clock)	
		if(rst || !ready)
			rx_datax <= 8'H00;
		else if(ready && bit_in && bit_counter<=4'D7)
			rx_datax <= {uart_rxd,rx_datax[7:1]};
	
	always @(posedge clock)
		if(rst)
			data_recv <= 8'H00;
		else if(ready && bit_counter==4'D8 && bit_in)
			data_recv <= rx_datax;
	
	assign	rx_en = (ready_x==10'H3E0);
	assign	rx_data = data_recv;

	

	integer			i;
	reg		[31:0]	tx_data_reversed;
	always @(*)
		for(i=0; i<32; i=i+1)
			tx_data_reversed[i] = tx_data[31-i];
	

	reg		[31:0]	tx_cnt;
	reg		[43:0]	tx_shifter;
	reg		[9:0]	tx_bit;
	reg		[3:0]	tx_state;
	always @(posedge clock)
		if(rst)
		begin
			tx_shifter <= 44'HFFF_FFFF_FFFF;
			tx_cnt <= 0;
			tx_bit <= 0;
			tx_busy <= 0;
			tx_state <= 0;
		end
		else 
		begin
			case(tx_state)
				0: begin
					if(tx_en)
					begin
						tx_shifter <= {	2'B10, tx_data_reversed[7:0], 1'B1,
										2'B10, tx_data_reversed[15:8], 1'B1,
										2'B10, tx_data_reversed[23:16], 1'B1,
										2'B10, tx_data_reversed[31:24], 1'B1
									};
						tx_busy <= 1;
						tx_cnt <= 0;
						tx_bit <= 0;
						tx_state <= 1;
					end
				end
				
				1: begin
					if(tx_cnt>=`UART_ONE_CYCLE)
					begin
						tx_cnt <= 0;
						if(tx_bit>=43)
						begin
							tx_busy <= 0;
							tx_state <= 0;
							tx_bit <= 0;
						end
						else
						begin
							tx_bit <= tx_bit + 1;
							tx_shifter <= {tx_shifter[42:0], 1'B1};
						end
					end
					else 
						tx_cnt <= tx_cnt + 1;
				end
				
				default: begin
					tx_shifter <= 44'HFFF_FFFF_FFFF;
					tx_cnt <= 0;
					tx_bit <= 0;
					tx_busy <= 0;
					tx_state <= 0;
				end
			endcase
		end
	
	assign	uart_txd = tx_shifter[43];
			
endmodule