data/full_repos/permissive/21203606/wishbone_uart_tx/tx_port.v
1: b'%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/tx_port.v:32: Cannot find include file: reg_defs.v\n`include "reg_defs.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21203606/wishbone_uart_tx,data/full_repos/permissive/21203606/reg_defs.v\n             data/full_repos/permissive/21203606/wishbone_uart_tx,data/full_repos/permissive/21203606/reg_defs.v.v\n             data/full_repos/permissive/21203606/wishbone_uart_tx,data/full_repos/permissive/21203606/reg_defs.v.sv\n             reg_defs.v\n             reg_defs.v.v\n             reg_defs.v.sv\n             obj_dir/reg_defs.v\n             obj_dir/reg_defs.v.v\n             obj_dir/reg_defs.v.sv\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/tx_port.v:33: Cannot find include file: uart_tx.v\n`include "uart_tx.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/tx_port.v:79: Define or directive not defined: \'`UART_STATUS\'\n        `UART_STATUS:\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/tx_port.v:79: syntax error, unexpected \':\', expecting endcase\n        `UART_STATUS:\n                    ^\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/tx_port.v:93: Define or directive not defined: \'`UART_DATAREG\'\n        `UART_DATAREG:\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/tx_port.v:94: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n        begin\n        ^~~~~\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/tx_port.v:100: syntax error, unexpected else\n          else  \n          ^~~~\n%Error: data/full_repos/permissive/21203606/wishbone_uart_tx/tx_port.v:105: syntax error, unexpected end\n        end\n        ^~~\n%Error: Cannot continue\n'
module  krake_tx_port(
    input wire        clk_i,
    input wire        rst_i,
    output reg        ack_o,
    input wire [7:0]  dat_i,
    input wire [3:0]  adr_i,
    output reg [7:0]  dat_o,
    input wire        stb_i,
    input wire        we_i,
    output wire       dout);
    
reg [7:0] data;
reg tx_en;
wire tx_rdy;
reg tx_rst;

uart_tx txi(
  .clk(clk_i),
  .rst(rst_i),
  .en(tx_en),
  .data_out(data),
  .rdy(tx_rdy),
  .dout(dout));

always @ (posedge clk_i)
begin
  if(rst_i)
  begin
    tx_rst <= 1'd1;
    data <= 8'd0;
    tx_en <= 1'd0;
  end
  else
  begin

    ack_o <= 1'b0;
    dat_o <= 8'd0;
    tx_en <= 1'b0;
    data <= data;

    if(stb_i)
    begin
      case(adr_i)

        `UART_STATUS:
        begin
          if(we_i)
          begin
            tx_en <= dat_i[0];
            ack_o <= 1'b1;
          end
          else
          begin
            dat_o[0] <= tx_rdy;
            ack_o <= 1'b1;
          end
        end

        `UART_DATAREG:
        begin
          if(we_i)
          begin
            data <= dat_i;
            ack_o <= 1'b1;
          end
          else
          begin
            dat_o <= data;
            ack_o <= 1'b1;
          end
        end


      endcase
    end
  end
end

endmodule
module  krake_tx_port(
    input wire        clk_i,
    input wire        rst_i,
    output reg        ack_o,
    input wire [7:0]  dat_i,
    input wire [3:0]  adr_i,
    output reg [7:0]  dat_o,
    input wire        stb_i,
    input wire        we_i,
    output wire       dout);

    
reg [7:0] data;
reg tx_en;
wire tx_rdy;
reg tx_rst;

uart_tx txi(
  .clk(clk_i),
  .rst(rst_i),
  .en(tx_en),
  .data_out(data),
  .rdy(tx_rdy),
  .dout(dout));

always @ (posedge clk_i)
begin
  if(rst_i)
  begin
    tx_rst <= 1'd1;
    data <= 8'd0;
    tx_en <= 1'd0;
  end
  else
  begin

    ack_o <= 1'b0;
    dat_o <= 8'd0;
    tx_en <= 1'b0;
    data <= data;

    if(stb_i)
    begin
      case(adr_i)

        `UART_STATUS:
        begin
          if(we_i)
          begin
            tx_en <= dat_i[0];
            ack_o <= 1'b1;
          end
          else
          begin
            dat_o[0] <= tx_rdy;
            ack_o <= 1'b1;
          end
        end

        `UART_DATAREG:
        begin
          if(we_i)
          begin
            data <= dat_i;
            ack_o <= 1'b1;
          end
          else
          begin
            dat_o <= data;
            ack_o <= 1'b1;
          end
        end


      endcase
    end
  end
end

endmodule