data/full_repos/permissive/200314387/verilog/74423/test.v
1: b'%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:4: Cannot find include file: hct74423.v\n`include "hct74423.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/200314387/verilog/74423,data/full_repos/permissive/200314387/hct74423.v\n             data/full_repos/permissive/200314387/verilog/74423,data/full_repos/permissive/200314387/hct74423.v.v\n             data/full_repos/permissive/200314387/verilog/74423,data/full_repos/permissive/200314387/hct74423.v.sv\n             hct74423.v\n             hct74423.v.v\n             hct74423.v.sv\n             obj_dir/hct74423.v\n             obj_dir/hct74423.v.v\n             obj_dir/hct74423.v.sv\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:5: Cannot find include file: ../lib/assertion.v\n`include "../lib/assertion.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:17: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:18: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, monostable);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:24: Define or directive not defined: \'`Equals\'\n        `Equals(Q, 1\'bx);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:24: syntax error, unexpected \',\'\n        `Equals(Q, 1\'bx);\n                 ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:25: Define or directive not defined: \'`Equals\'\n        `Equals(_Q, 1\'bx);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:25: syntax error, unexpected \',\'\n        `Equals(_Q, 1\'bx);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:28: Define or directive not defined: \'`Equals\'\n        `Equals(Q, 1\'bx);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:28: syntax error, unexpected \',\'\n        `Equals(Q, 1\'bx);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74423/test.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:29: Define or directive not defined: \'`Equals\'\n        `Equals(_Q, 1\'bx);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:29: syntax error, unexpected \',\'\n        `Equals(_Q, 1\'bx);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:34: Define or directive not defined: \'`Equals\'\n        `Equals(Q, 1\'b0);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:34: syntax error, unexpected \',\'\n        `Equals(Q, 1\'b0);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74423/test.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:35: Define or directive not defined: \'`Equals\'\n        `Equals(_Q, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:35: syntax error, unexpected \',\'\n        `Equals(_Q, 1\'b1);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:40: Define or directive not defined: \'`Equals\'\n        `Equals(Q, 1\'b0);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:40: syntax error, unexpected \',\'\n        `Equals(Q, 1\'b0);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74423/test.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:41: Define or directive not defined: \'`Equals\'\n        `Equals(_Q, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:41: syntax error, unexpected \',\'\n        `Equals(_Q, 1\'b1);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:48: Define or directive not defined: \'`Equals\'\n        `Equals(Q, 1\'b0);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:48: syntax error, unexpected \',\'\n        `Equals(Q, 1\'b0);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74423/test.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:49: Define or directive not defined: \'`Equals\'\n        `Equals(_Q, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:49: syntax error, unexpected \',\'\n        `Equals(_Q, 1\'b1);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:54: Define or directive not defined: \'`Equals\'\n        `Equals(Q, 1\'b0);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:54: syntax error, unexpected \',\'\n        `Equals(Q, 1\'b0);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74423/test.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #20  \n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:55: Define or directive not defined: \'`Equals\'\n        `Equals(_Q, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:55: syntax error, unexpected \',\'\n        `Equals(_Q, 1\'b1);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:57: Define or directive not defined: \'`Equals\'\n        `Equals(Q, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:57: syntax error, unexpected \',\'\n        `Equals(Q, 1\'b1);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74423/test.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #20  \n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:58: Define or directive not defined: \'`Equals\'\n        `Equals(_Q, 1\'b0);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:58: syntax error, unexpected \',\'\n        `Equals(_Q, 1\'b0);\n                  ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:62: Define or directive not defined: \'`Equals\'\n        `Equals(Q, 1\'b0);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:62: syntax error, unexpected \',\'\n        `Equals(Q, 1\'b0);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/200314387/verilog/74423/test.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #100  \n        ^\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:63: Define or directive not defined: \'`Equals\'\n        `Equals(_Q, 1\'b1);\n        ^~~~~~~\n%Error: data/full_repos/permissive/200314387/verilog/74423/test.v:63: syntax error, unexpected \',\'\n        `Equals(_Q, 1\'b1);\n                  ^\n%Error: Exiting due to 36 error(s), 7 warning(s)\n'
module icarus_tb();
    
	logic _A,  B, _R;
    wire Q, _Q;
    
	hct74423 #(.PulseWidth(100)) monostable(_A, B, _R, Q, _Q);
    
    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0, monostable);
    end

    always @* $display ($time, "_A=%1b B=%1b _R=%1b  ->  Q=%1b _Q=%1b", _A, B, _R, Q, _Q);

    initial begin
        `Equals(Q, 1'bx);
        `Equals(_Q, 1'bx);

        #100
        `Equals(Q, 1'bx);
        `Equals(_Q, 1'bx);

        $display("reset");
        _R=0;
        #100
        `Equals(Q, 1'b0);
        `Equals(_Q, 1'b1);
            
        $display("unreset");
        _R=1;
        #100
        `Equals(Q, 1'b0);
        `Equals(_Q, 1'b1);
            
        $display("prep");
        _A=0;
        B=0;
        _R=1;
        #100
        `Equals(Q, 1'b0);
        `Equals(_Q, 1'b1);

        $display("trigger");
        B=1;
        #20
        `Equals(Q, 1'b0);
        `Equals(_Q, 1'b1);
        #20
        `Equals(Q, 1'b1);
        `Equals(_Q, 1'b0);

        $display("pulse should have ended");
        #100
        `Equals(Q, 1'b0);
        `Equals(_Q, 1'b1);

    end

endmodule
module icarus_tb();

    
	logic _A,  B, _R;
    wire Q, _Q;
    
	hct74423 #(.PulseWidth(100)) monostable(_A, B, _R, Q, _Q);
    
    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars(0, monostable);
    end

    always @* $display ($time, "_A=%1b B=%1b _R=%1b  ->  Q=%1b _Q=%1b", _A, B, _R, Q, _Q);

    initial begin
        `Equals(Q, 1'bx);
        `Equals(_Q, 1'bx);

        #100
        `Equals(Q, 1'bx);
        `Equals(_Q, 1'bx);

        $display("reset");
        _R=0;
        #100
        `Equals(Q, 1'b0);
        `Equals(_Q, 1'b1);
            
        $display("unreset");
        _R=1;
        #100
        `Equals(Q, 1'b0);
        `Equals(_Q, 1'b1);
            
        $display("prep");
        _A=0;
        B=0;
        _R=1;
        #100
        `Equals(Q, 1'b0);
        `Equals(_Q, 1'b1);

        $display("trigger");
        B=1;
        #20
        `Equals(Q, 1'b0);
        `Equals(_Q, 1'b1);
        #20
        `Equals(Q, 1'b1);
        `Equals(_Q, 1'b0);

        $display("pulse should have ended");
        #100
        `Equals(Q, 1'b0);
        `Equals(_Q, 1'b1);

    end

endmodule