data/full_repos/permissive/175393019/rtl/xtop_tb.v
 line:117: before: ";"
1: b'%Error: data/full_repos/permissive/175393019/rtl/xtop_tb.v:3: Cannot find include file: xdefs.vh\n`include "xdefs.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175393019/rtl,data/full_repos/permissive/175393019/xdefs.vh\n             data/full_repos/permissive/175393019/rtl,data/full_repos/permissive/175393019/xdefs.vh.v\n             data/full_repos/permissive/175393019/rtl,data/full_repos/permissive/175393019/xdefs.vh.sv\n             xdefs.vh\n             xdefs.vh.v\n             xdefs.vh.sv\n             obj_dir/xdefs.vh\n             obj_dir/xdefs.vh.v\n             obj_dir/xdefs.vh.sv\n%Error: data/full_repos/permissive/175393019/rtl/xtop_tb.v:17: Define or directive not defined: \'`REGF_ADDR_W\'\n   reg  [`REGF_ADDR_W-1:0] par_addr;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xtop_tb.v:19: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W-1:0]     par_in;\n        ^~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xtop_tb.v:24: Define or directive not defined: \'`DATA_W\'\n   wire [`DATA_W-1:0]     par_out;\n         ^~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xtop_tb.v:31: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W-1:0] data [2**`REGF_ADDR_W-1:0];\n        ^~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xtop_tb.v:31: Define or directive not defined: \'`REGF_ADDR_W\'\n   reg [`DATA_W-1:0] data [2**`REGF_ADDR_W-1:0];\n                              ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/175393019/rtl/xtop_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n      #(clk_period+1)\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/175393019/rtl/xtop_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n      #clk_period;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/175393019/rtl/xtop_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n      #(5*clk_period) par_addr = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/175393019/rtl/xtop_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n      #clk_period par_we = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/175393019/rtl/xtop_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n      while(finish != 0) #clk_period;\n                         ^\n%Error: data/full_repos/permissive/175393019/rtl/xtop_tb.v:92: Define or directive not defined: \'`REGF_ADDR_W\'\n      for (k = 0; k < 2**`REGF_ADDR_W; k=k+1) begin\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xtop_tb.v:92: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      for (k = 0; k < 2**`REGF_ADDR_W; k=k+1) begin\n                                     ^\n%Error: data/full_repos/permissive/175393019/rtl/xtop_tb.v:92: syntax error, unexpected \')\', expecting \';\'\n      for (k = 0; k < 2**`REGF_ADDR_W; k=k+1) begin\n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/175393019/rtl/xtop_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #clk_period par_addr = par_addr + 1;\n  ^\n%Error: data/full_repos/permissive/175393019/rtl/xtop_tb.v:97: syntax error, unexpected $writememh\n      $writememh("data_out.hex", data, 0, 2**`REGF_ADDR_W - 1);\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xtop_tb.v:97: Define or directive not defined: \'`REGF_ADDR_W\'\n      $writememh("data_out.hex", data, 0, 2**`REGF_ADDR_W - 1);\n                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/175393019/rtl/xtop_tb.v:112: Define or directive not defined: \'`DATA_W\'\n   wire [`DATA_W-1:0] r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;\n         ^~~~~~~\n%Error: Exiting due to 12 error(s), 6 warning(s)\n'
module xtop_tb;
   

   parameter clk_period = 10;




   reg clk;
   reg rst;


   reg 	[`REGF_ADDR_W-1:0] par_addr;
   reg 			   par_we;
   reg [`DATA_W-1:0] 	   par_in;
   reg PS2_DATA;
   reg PS2_CLK;
   reg [7:0]leds;
   reg [6:0]sevenseg;
   wire [`DATA_W-1:0] 	   par_out;
   reg finish;


   integer 		   k, start_time;


   reg [`DATA_W-1:0] data [2**`REGF_ADDR_W-1:0];
   

   xtop uut (
	      .clk(clk),
         .rst(rst),


	    .par_we(par_we),
        .PS2_DATA(PS2_DATA),
        .PS2_CLK(PS2_CLK),
        .leds(leds),

        .sevenseg(sevenseg)


	      );
   
   initial begin
      
`ifdef DEBUG
      $dumpfile("xtop.vcd");
      $dumpvars();
`endif
        

      clk = 1;
      rst = 0;  
      

      par_addr = 0;
      par_we = 1;
      par_in = 0;


      #(clk_period+1)
      rst = 1;
      #clk_period;
      rst = 0;
      




      #(5*clk_period) par_addr = 0;
      par_we = 0;
      par_in = 1;

      start_time = $time;

      #clk_period par_we = 0;
      par_addr = 0;


      while(finish != 0) #clk_period;

      $display("Execution time in clock cycles: %0d",($time-start_time)/clk_period);




      for (k = 0; k < 2**`REGF_ADDR_W; k=k+1) begin
	   data[k] = par_out;
	 #clk_period par_addr = par_addr + 1;
      end
  
      $writememh("data_out.hex", data, 0, 2**`REGF_ADDR_W - 1);




      #clk_period $finish;


   end

   
   always 
     #(clk_period/2) clk = ~clk;


   wire [`DATA_W-1:0] r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;

   assign r0 = uut.regf.reg_1[0];
   assign r1 = uut.regf.reg_1[1];
   assign r2 = uut.regf.reg_1[2];
   assign r3 = uut.regf.reg_1[3];
   assign r4 = uut.regf.reg_1[4];
   assign r5 = uut.regf.reg_1[5];
   assign r6 = uut.regf.reg_1[6];
   assign r7 = uut.regf.reg_1[7];
   assign r8 = uut.regf.reg_1[8];
   assign r9 = uut.regf.reg_1[9];
   assign r10 = uut.regf.reg_1[10];
   assign r11 = uut.regf.reg_1[11];
   assign r12 = uut.regf.reg_1[12];
   assign r13 = uut.regf.reg_1[13];
   assign r14 = uut.regf.reg_1[14];
   assign r15 = uut.regf.reg_1[15];  

endmodule
module xtop_tb;

   

   parameter clk_period = 10;




   reg clk;
   reg rst;


   reg 	[`REGF_ADDR_W-1:0] par_addr;
   reg 			   par_we;
   reg [`DATA_W-1:0] 	   par_in;
   reg PS2_DATA;
   reg PS2_CLK;
   reg [7:0]leds;
   reg [6:0]sevenseg;
   wire [`DATA_W-1:0] 	   par_out;
   reg finish;


   integer 		   k, start_time;


   reg [`DATA_W-1:0] data [2**`REGF_ADDR_W-1:0];
   

   xtop uut (
	      .clk(clk),
         .rst(rst),


	    .par_we(par_we),
        .PS2_DATA(PS2_DATA),
        .PS2_CLK(PS2_CLK),
        .leds(leds),

        .sevenseg(sevenseg)


	      );
   
   initial begin
      
`ifdef DEBUG
      $dumpfile("xtop.vcd");
      $dumpvars();
`endif
        

      clk = 1;
      rst = 0;  
      

      par_addr = 0;
      par_we = 1;
      par_in = 0;


      #(clk_period+1)
      rst = 1;
      #clk_period;
      rst = 0;
      




      #(5*clk_period) par_addr = 0;
      par_we = 0;
      par_in = 1;

      start_time = $time;

      #clk_period par_we = 0;
      par_addr = 0;


      while(finish != 0) #clk_period;

      $display("Execution time in clock cycles: %0d",($time-start_time)/clk_period);




      for (k = 0; k < 2**`REGF_ADDR_W; k=k+1) begin
	   data[k] = par_out;
	 #clk_period par_addr = par_addr + 1;
      end
  
      $writememh("data_out.hex", data, 0, 2**`REGF_ADDR_W - 1);




      #clk_period $finish;


   end

   
   always 
     #(clk_period/2) clk = ~clk;


   wire [`DATA_W-1:0] r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;

   assign r0 = uut.regf.reg_1[0];
   assign r1 = uut.regf.reg_1[1];
   assign r2 = uut.regf.reg_1[2];
   assign r3 = uut.regf.reg_1[3];
   assign r4 = uut.regf.reg_1[4];
   assign r5 = uut.regf.reg_1[5];
   assign r6 = uut.regf.reg_1[6];
   assign r7 = uut.regf.reg_1[7];
   assign r8 = uut.regf.reg_1[8];
   assign r9 = uut.regf.reg_1[9];
   assign r10 = uut.regf.reg_1[10];
   assign r11 = uut.regf.reg_1[11];
   assign r12 = uut.regf.reg_1[12];
   assign r13 = uut.regf.reg_1[13];
   assign r14 = uut.regf.reg_1[14];
   assign r15 = uut.regf.reg_1[15];  

endmodule