data/full_repos/permissive/132157042/src/pixram.v
1: b"%Error-ASSIGNIN: data/full_repos/permissive/132157042/src/pixram.v:47: Assigning to input/const variable: 'data_out'\n   bram #(12, 8) bram_a(clk, read, write_a, raddr, waddr[11:0], data_out[31:24], data_in);\n                                                                ^~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/132157042/src/pixram.v:48: Assigning to input/const variable: 'data_out'\n   bram #(12, 8) bram_b(clk, read, write_b, raddr, waddr[11:0], data_out[23:16], data_in);\n                                                                ^~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/132157042/src/pixram.v:49: Assigning to input/const variable: 'data_out'\n   bram #(12, 8) bram_c(clk, read, write_c, raddr, waddr[11:0], data_out[15:8], data_in);\n                                                                ^~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/132157042/src/pixram.v:50: Assigning to input/const variable: 'data_out'\n   bram #(12, 8) bram_d(clk, read, write_d, raddr, waddr[11:0], data_out[7:0], data_in);\n                                                                ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module bram
  #(
    parameter ADDR_WIDTH = 12,
    parameter DATA_WIDTH = 8
    ) (
       input wire                   clk,
       input wire                   read,
       input wire                   write,
       input wire [ADDR_WIDTH-1:0]  raddr,
       input wire [ADDR_WIDTH-1:0]  waddr,
       output wire [DATA_WIDTH-1:0] data_out,
       input wire [DATA_WIDTH-1:0]  data_in
       );

   reg [DATA_WIDTH-1:0]             mem [0:(2**ADDR_WIDTH)-1];

   always @(posedge clk) begin
      if (write)
        mem[waddr] <= data_in;

      if (read)
        data_out <= mem[raddr];
   end
endmodule
module bram
  #(
    parameter ADDR_WIDTH = 12,
    parameter DATA_WIDTH = 8
    ) (
       input wire                   clk,
       input wire                   read,
       input wire                   write,
       input wire [ADDR_WIDTH-1:0]  raddr,
       input wire [ADDR_WIDTH-1:0]  waddr,
       output wire [DATA_WIDTH-1:0] data_out,
       input wire [DATA_WIDTH-1:0]  data_in
       );


   reg [DATA_WIDTH-1:0]             mem [0:(2**ADDR_WIDTH)-1];

   always @(posedge clk) begin
      if (write)
        mem[waddr] <= data_in;

      if (read)
        data_out <= mem[raddr];
   end
endmodule