data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/top.v
1: b'%Error: data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/top.v:110: Cannot find file containing module: \'OSCH\'\n        OSCH #( .NOM_FREQ("13.3")) IOSC\n        ^~~~\n        ... Looked in:\n             data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410,data/full_repos/permissive/166492247/OSCH\n             data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410,data/full_repos/permissive/166492247/OSCH.v\n             data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410,data/full_repos/permissive/166492247/OSCH.sv\n             OSCH\n             OSCH.v\n             OSCH.sv\n             obj_dir/OSCH\n             obj_dir/OSCH.v\n             obj_dir/OSCH.sv\n%Error: data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/top.v:117: Cannot find file containing module: \'clk\'\nclk clk(.CLKI(clk_13_3m),.CLKOP(clk_40m));\n^~~\n%Error: data/full_repos/permissive/166492247/LCMXO3LF-6900C_HDMI_TFP410/top.v:149: Cannot find file containing module: \'vga_core\'\nvga_core u_vga_core\n^~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module top
(
  input  wire         rst_l,









	output wire out_vga_vs,
	output wire out_vga_hs,
	output wire out_vga_de,
	output wire out_vga_ck,
	output wire out_vga_r,
	output wire out_vga_g,
	output wire out_vga_b,
	output wire [7:0] led

);

  wire clk_40m;
  wire clk_13_3m;

  wire          reset_loc;

  reg  [29:0]   led_cnt;
  reg  [29:0]   led_cnt_p1;
  wire          vga_de;
  wire          vga_ck;
  wire          vga_hs;
  wire          vga_vs;
  wire [23:0]   vga_rgb;
  reg  [31:0]   random_num;
  wire [7:0]    r;
  wire [7:0]    g;
  wire [7:0]    b;
  reg           mode_bit;


  assign reset_loc  = ~rst_l;








        OSCH #( .NOM_FREQ("13.3")) IOSC
        (
          .STDBY(1'b0),
          .OSC(clk_13_3m),
          .SEDSTDBY()
        );

clk clk(.CLKI(clk_13_3m),.CLKOP(clk_40m));


























assign led = ~led_cnt[29:22];




vga_core u_vga_core
(
  .reset             ( reset_loc           ),
  .random_num        ( random_num[31:0]    ),
  .color_3b          ( 1'b0                ),
  .mode_bit          ( mode_bit            ),
  .clk_dot           ( clk_40m        ),
  .vga_active        ( vga_de              ),
  .vga_hsync         ( vga_hs              ),
  .vga_vsync         ( vga_vs              ),
  .vga_pixel_rgb     ( vga_rgb[23:0]       )
);
  assign r = vga_rgb[23:16];
  assign g = vga_rgb[15:8];
  assign b = vga_rgb[7:0];







	assign vga_ck = clk_40m;














	assign out_vga_vs = vga_vs;
	assign out_vga_hs = vga_hs;
	assign out_vga_de = vga_de;
	assign out_vga_ck = vga_ck;
	assign out_vga_r = r[7];
	assign out_vga_g = g[7];
	assign out_vga_b = b[7];




	
	always @ ( posedge clk_40m or posedge reset_loc ) begin : proc_led 
 if ( reset_loc == 1 ) begin
   random_num   <= 32'd0;
   led_cnt      <= 30'd0;
   led_cnt_p1   <= 30'd0;

   mode_bit     <= 0;
 end else begin
   random_num   <= random_num + 3;

   led_cnt_p1   <= led_cnt[29:0];
   led_cnt      <= led_cnt + 1;
   if ( led_cnt[19] == 1 ) begin

   end
   if ( led_cnt[29:27] == 3'd0 ) begin
     mode_bit <= 0;
   end else begin
     mode_bit <= 1;
   end 

 end
end
	
endmodule
module top
(
  input  wire         rst_l,









	output wire out_vga_vs,
	output wire out_vga_hs,
	output wire out_vga_de,
	output wire out_vga_ck,
	output wire out_vga_r,
	output wire out_vga_g,
	output wire out_vga_b,
	output wire [7:0] led

);


  wire clk_40m;
  wire clk_13_3m;

  wire          reset_loc;

  reg  [29:0]   led_cnt;
  reg  [29:0]   led_cnt_p1;
  wire          vga_de;
  wire          vga_ck;
  wire          vga_hs;
  wire          vga_vs;
  wire [23:0]   vga_rgb;
  reg  [31:0]   random_num;
  wire [7:0]    r;
  wire [7:0]    g;
  wire [7:0]    b;
  reg           mode_bit;


  assign reset_loc  = ~rst_l;








        OSCH #( .NOM_FREQ("13.3")) IOSC
        (
          .STDBY(1'b0),
          .OSC(clk_13_3m),
          .SEDSTDBY()
        );

clk clk(.CLKI(clk_13_3m),.CLKOP(clk_40m));


























assign led = ~led_cnt[29:22];




vga_core u_vga_core
(
  .reset             ( reset_loc           ),
  .random_num        ( random_num[31:0]    ),
  .color_3b          ( 1'b0                ),
  .mode_bit          ( mode_bit            ),
  .clk_dot           ( clk_40m        ),
  .vga_active        ( vga_de              ),
  .vga_hsync         ( vga_hs              ),
  .vga_vsync         ( vga_vs              ),
  .vga_pixel_rgb     ( vga_rgb[23:0]       )
);
  assign r = vga_rgb[23:16];
  assign g = vga_rgb[15:8];
  assign b = vga_rgb[7:0];







	assign vga_ck = clk_40m;














	assign out_vga_vs = vga_vs;
	assign out_vga_hs = vga_hs;
	assign out_vga_de = vga_de;
	assign out_vga_ck = vga_ck;
	assign out_vga_r = r[7];
	assign out_vga_g = g[7];
	assign out_vga_b = b[7];




	
	always @ ( posedge clk_40m or posedge reset_loc ) begin : proc_led 
 if ( reset_loc == 1 ) begin
   random_num   <= 32'd0;
   led_cnt      <= 30'd0;
   led_cnt_p1   <= 30'd0;

   mode_bit     <= 0;
 end else begin
   random_num   <= random_num + 3;

   led_cnt_p1   <= led_cnt[29:0];
   led_cnt      <= led_cnt + 1;
   if ( led_cnt[19] == 1 ) begin

   end
   if ( led_cnt[29:27] == 3'd0 ) begin
     mode_bit <= 0;
   end else begin
     mode_bit <= 1;
   end 

 end
end
	
endmodule