data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu/pipeline_cpu.v
'utf-8' codec can't decode byte 0xc6 in position 2712: invalid continuation byte
1: b"%Error: data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu/pipeline_cpu.v:59: Cannot find file containing module: 'cu'\n    cu CU_module(\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu,data/full_repos/permissive/184371514/cu\n             data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu,data/full_repos/permissive/184371514/cu.v\n             data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu,data/full_repos/permissive/184371514/cu.sv\n             cu\n             cu.v\n             cu.sv\n             obj_dir/cu\n             obj_dir/cu.v\n             obj_dir/cu.sv\n%Error: data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu/pipeline_cpu.v:153: Cannot find file containing module: 'fetch'\n    fetch IF_module(              \n    ^~~~~\n%Error: data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu/pipeline_cpu.v:172: Cannot find file containing module: 'decode'\n    decode ID_module(                \n    ^~~~~~\n%Error: data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu/pipeline_cpu.v:194: Cannot find file containing module: 'exe'\n    exe EXE_module(                    \n    ^~~\n%Error: data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu/pipeline_cpu.v:208: Cannot find file containing module: 'mem'\n    mem MEM_module(                      \n    ^~~\n%Error: data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu/pipeline_cpu.v:227: Cannot find file containing module: 'wb'\n    wb WB_module(                      \n    ^~\n%Error: data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu/pipeline_cpu.v:248: Cannot find file containing module: 'inst_rom'\n    inst_rom inst_rom_module(          \n    ^~~~~~~~\n%Error: data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu/pipeline_cpu.v:254: Cannot find file containing module: 'regfile'\n    regfile rf_module(         \n    ^~~~~~~\n%Error: data/full_repos/permissive/184371514/6pipeline_CU_cpu/6pipeline_CU_cpu.srcs/sources_1/imports/LS_CPU_LAB/8_pipeline_cpu/pipeline_cpu.v:269: Cannot find file containing module: 'data_ram'\n    data_ram data_ram_module(    \n    ^~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module pipeline_cpu(
    input clk,
    input resetn,
    

    input  [ 4:0] rf_addr,
    input  [31:0] mem_addr,
    
    output [31:0] rf_data,
    output [31:0] mem_data,
    output [31:0] IF_pc,
    output [31:0] IF_inst,
    output [31:0] ID_pc,
    output [31:0] EXE_pc,
    output [31:0] MEM_pc,
    output [31:0] WB_pc,
    

    output [31:0] cpu_5_valid,
    output [31:0] HI_data,
    output [31:0] LO_data
    );

    wire IF_over;
    wire ID_over;
    wire EXE_over;
    wire MEM_over;
    wire WB_over;
    wire cancel;



    wire IFTOID;
    wire IDTOEX;
    wire EXTOMEM;
    wire MEMTOWB;

    
    

    wire next_fetch;

    wire IF_valid;
    wire   ID_valid;
    wire   EXE_valid;
    wire   MEM_valid;
    wire   WB_valid;
    
    wire MEM_allow_in;

    cu CU_module(
       .clk(clk),
    .resetn(resetn),


    .IF_over(IF_over),
    .ID_over(ID_over),
   .EXE_over(EXE_over),
   .MEM_over(MEM_over),
   .WB_over(WB_over),
   .cancel(cancel), 



   .IFTOID(IFTOID),
   .IDTOEX(IDTOEX),
   .EXTOMEM(EXTOMEM),
   .MEMTOWB(MEMTOWB),
.MEM_allow_in(MEM_allow_in),
    
    

    .next_fetch(next_fetch),

  .IF_valid(IF_valid),
   .ID_valid(ID_valid),
   .EXE_valid(EXE_valid),
   .MEM_valid(MEM_valid),
   .WB_valid(WB_valid),
    
    
    .cpu_5_valid(cpu_5_valid)
    );



    wire [ 63:0] IF_ID_bus;
    wire [166:0] ID_EXE_bus;
    wire [153:0] EXE_MEM_bus;
    wire [117:0] MEM_WB_bus;
    

    reg [ 63:0] IF_ID_bus_r;
    reg [166:0] ID_EXE_bus_r;
    reg [153:0] EXE_MEM_bus_r;
    reg [117:0] MEM_WB_bus_r;
    

    always @(posedge clk)
    begin
        if(IFTOID)IF_ID_bus_r <= IF_ID_bus;
        if(IDTOEX)ID_EXE_bus_r <= ID_EXE_bus;
        if(EXTOMEM) EXE_MEM_bus_r <= EXE_MEM_bus;
        if(MEMTOWB) MEM_WB_bus_r <= MEM_WB_bus;
    end




    wire [ 32:0] jbr_bus;    


    wire [31:0] inst_addr;
    wire [31:0] inst;


    wire [ 4:0] EXE_wdest;
    wire [ 4:0] MEM_wdest;
    wire [ 4:0] WB_wdest;
    

    wire [ 3:0] dm_wen;
    wire [31:0] dm_addr;
    wire [31:0] dm_wdata;
    wire [31:0] dm_rdata;


    wire [ 4:0] rs;
    wire [ 4:0] rt;   
    wire [31:0] rs_value;
    wire [31:0] rt_value;
    

    wire        rf_wen;
    wire [ 4:0] rf_wdest;
    wire [31:0] rf_wdata;    
    

    wire [32:0] exc_bus;





    fetch IF_module(
        .clk       (clk       ),
        .resetn    (resetn    ),
        .IF_valid  (IF_valid  ),
        .next_fetch(next_fetch),
        .inst      (inst      ),
        .jbr_bus   (jbr_bus   ),
        .inst_addr (inst_addr ),
        .IF_over   (IF_over   ),
        .IF_ID_bus (IF_ID_bus ),
        

        .exc_bus   (exc_bus   ),
        

        .IF_pc     (IF_pc     ),
        .IF_inst   (IF_inst   )
    );

    decode ID_module(
        .ID_valid   (ID_valid   ),
        .IF_ID_bus_r(IF_ID_bus_r),
        .rs_value   (rs_value   ),
        .rt_value   (rt_value   ),
        .rs         (rs         ),
        .rt         (rt         ),
        .jbr_bus    (jbr_bus    ),

        .ID_over    (ID_over    ),
        .ID_EXE_bus (ID_EXE_bus ),
        

        .IF_over     (IF_over     ),
        .EXE_wdest   (EXE_wdest   ),
        .MEM_wdest   (MEM_wdest   ),
        .WB_wdest    (WB_wdest    ),
        

        .ID_pc       (ID_pc       )
    ); 

    exe EXE_module(
        .EXE_valid   (EXE_valid   ),
        .ID_EXE_bus_r(ID_EXE_bus_r),
        .EXE_over    (EXE_over    ),
        .EXE_MEM_bus (EXE_MEM_bus ),
        

        .clk         (clk         ),
        .EXE_wdest   (EXE_wdest   ),
        

        .EXE_pc      (EXE_pc      )
    );

    mem MEM_module(
        .clk          (clk          ),
        .MEM_valid    (MEM_valid    ),
        .EXE_MEM_bus_r(EXE_MEM_bus_r),
        .dm_rdata     (dm_rdata     ),
        .dm_addr      (dm_addr      ),
        .dm_wen       (dm_wen       ),
        .dm_wdata     (dm_wdata     ),
        .MEM_over     (MEM_over     ),
        .MEM_WB_bus   (MEM_WB_bus   ),
        

        .MEM_allow_in (MEM_allow_in ),
        .MEM_wdest    (MEM_wdest    ),
        

        .MEM_pc       (MEM_pc       )
    );          
 
    wb WB_module(
        .WB_valid    (WB_valid    ),
        .MEM_WB_bus_r(MEM_WB_bus_r),
        .rf_wen      (rf_wen      ),
        .rf_wdest    (rf_wdest    ),
        .rf_wdata    (rf_wdata    ),
          .WB_over     (WB_over     ),
        

        .clk         (clk         ),
      .resetn      (resetn      ),
        .exc_bus     (exc_bus     ),
        .WB_wdest    (WB_wdest    ),
        .cancel      (cancel      ),
        

        .WB_pc       (WB_pc       ),
        .HI_data     (HI_data     ),
        .LO_data     (LO_data     )
    );

    inst_rom inst_rom_module(
        .clka       (clk           ),
        .addra      (inst_addr[9:2]),
        .douta      (inst          )
    );

    regfile rf_module(
        .clk    (clk      ),
        .wen    (rf_wen   ),
        .raddr1 (rs       ),
        .raddr2 (rt       ),
        .waddr  (rf_wdest ),
        .wdata  (rf_wdata ),
        .rdata1 (rs_value ),
        .rdata2 (rt_value ),


        .test_addr(rf_addr),
        .test_data(rf_data)
    );
    
    data_ram data_ram_module(
        .clka   (clk         ),
        .wea    (dm_wen      ),
        .addra  (dm_addr[9:2]),
        .dina   (dm_wdata    ),
        .douta  (dm_rdata    ),


        .clkb   (clk          ),
        .web    (4'd0         ),
        .addrb  (mem_addr[9:2]),
        .doutb  (mem_data     ),
        .dinb   (32'd0        )
    );

endmodule
module pipeline_cpu(
    input clk,
    input resetn,
    

    input  [ 4:0] rf_addr,
    input  [31:0] mem_addr,
    
    output [31:0] rf_data,
    output [31:0] mem_data,
    output [31:0] IF_pc,
    output [31:0] IF_inst,
    output [31:0] ID_pc,
    output [31:0] EXE_pc,
    output [31:0] MEM_pc,
    output [31:0] WB_pc,
    

    output [31:0] cpu_5_valid,
    output [31:0] HI_data,
    output [31:0] LO_data
    );


    wire IF_over;
    wire ID_over;
    wire EXE_over;
    wire MEM_over;
    wire WB_over;
    wire cancel;



    wire IFTOID;
    wire IDTOEX;
    wire EXTOMEM;
    wire MEMTOWB;

    
    

    wire next_fetch;

    wire IF_valid;
    wire   ID_valid;
    wire   EXE_valid;
    wire   MEM_valid;
    wire   WB_valid;
    
    wire MEM_allow_in;

    cu CU_module(
       .clk(clk),
    .resetn(resetn),


    .IF_over(IF_over),
    .ID_over(ID_over),
   .EXE_over(EXE_over),
   .MEM_over(MEM_over),
   .WB_over(WB_over),
   .cancel(cancel), 



   .IFTOID(IFTOID),
   .IDTOEX(IDTOEX),
   .EXTOMEM(EXTOMEM),
   .MEMTOWB(MEMTOWB),
.MEM_allow_in(MEM_allow_in),
    
    

    .next_fetch(next_fetch),

  .IF_valid(IF_valid),
   .ID_valid(ID_valid),
   .EXE_valid(EXE_valid),
   .MEM_valid(MEM_valid),
   .WB_valid(WB_valid),
    
    
    .cpu_5_valid(cpu_5_valid)
    );



    wire [ 63:0] IF_ID_bus;
    wire [166:0] ID_EXE_bus;
    wire [153:0] EXE_MEM_bus;
    wire [117:0] MEM_WB_bus;
    

    reg [ 63:0] IF_ID_bus_r;
    reg [166:0] ID_EXE_bus_r;
    reg [153:0] EXE_MEM_bus_r;
    reg [117:0] MEM_WB_bus_r;
    

    always @(posedge clk)
    begin
        if(IFTOID)IF_ID_bus_r <= IF_ID_bus;
        if(IDTOEX)ID_EXE_bus_r <= ID_EXE_bus;
        if(EXTOMEM) EXE_MEM_bus_r <= EXE_MEM_bus;
        if(MEMTOWB) MEM_WB_bus_r <= MEM_WB_bus;
    end




    wire [ 32:0] jbr_bus;    


    wire [31:0] inst_addr;
    wire [31:0] inst;


    wire [ 4:0] EXE_wdest;
    wire [ 4:0] MEM_wdest;
    wire [ 4:0] WB_wdest;
    

    wire [ 3:0] dm_wen;
    wire [31:0] dm_addr;
    wire [31:0] dm_wdata;
    wire [31:0] dm_rdata;


    wire [ 4:0] rs;
    wire [ 4:0] rt;   
    wire [31:0] rs_value;
    wire [31:0] rt_value;
    

    wire        rf_wen;
    wire [ 4:0] rf_wdest;
    wire [31:0] rf_wdata;    
    

    wire [32:0] exc_bus;





    fetch IF_module(
        .clk       (clk       ),
        .resetn    (resetn    ),
        .IF_valid  (IF_valid  ),
        .next_fetch(next_fetch),
        .inst      (inst      ),
        .jbr_bus   (jbr_bus   ),
        .inst_addr (inst_addr ),
        .IF_over   (IF_over   ),
        .IF_ID_bus (IF_ID_bus ),
        

        .exc_bus   (exc_bus   ),
        

        .IF_pc     (IF_pc     ),
        .IF_inst   (IF_inst   )
    );

    decode ID_module(
        .ID_valid   (ID_valid   ),
        .IF_ID_bus_r(IF_ID_bus_r),
        .rs_value   (rs_value   ),
        .rt_value   (rt_value   ),
        .rs         (rs         ),
        .rt         (rt         ),
        .jbr_bus    (jbr_bus    ),

        .ID_over    (ID_over    ),
        .ID_EXE_bus (ID_EXE_bus ),
        

        .IF_over     (IF_over     ),
        .EXE_wdest   (EXE_wdest   ),
        .MEM_wdest   (MEM_wdest   ),
        .WB_wdest    (WB_wdest    ),
        

        .ID_pc       (ID_pc       )
    ); 

    exe EXE_module(
        .EXE_valid   (EXE_valid   ),
        .ID_EXE_bus_r(ID_EXE_bus_r),
        .EXE_over    (EXE_over    ),
        .EXE_MEM_bus (EXE_MEM_bus ),
        

        .clk         (clk         ),
        .EXE_wdest   (EXE_wdest   ),
        

        .EXE_pc      (EXE_pc      )
    );

    mem MEM_module(
        .clk          (clk          ),
        .MEM_valid    (MEM_valid    ),
        .EXE_MEM_bus_r(EXE_MEM_bus_r),
        .dm_rdata     (dm_rdata     ),
        .dm_addr      (dm_addr      ),
        .dm_wen       (dm_wen       ),
        .dm_wdata     (dm_wdata     ),
        .MEM_over     (MEM_over     ),
        .MEM_WB_bus   (MEM_WB_bus   ),
        

        .MEM_allow_in (MEM_allow_in ),
        .MEM_wdest    (MEM_wdest    ),
        

        .MEM_pc       (MEM_pc       )
    );          
 
    wb WB_module(
        .WB_valid    (WB_valid    ),
        .MEM_WB_bus_r(MEM_WB_bus_r),
        .rf_wen      (rf_wen      ),
        .rf_wdest    (rf_wdest    ),
        .rf_wdata    (rf_wdata    ),
          .WB_over     (WB_over     ),
        

        .clk         (clk         ),
      .resetn      (resetn      ),
        .exc_bus     (exc_bus     ),
        .WB_wdest    (WB_wdest    ),
        .cancel      (cancel      ),
        

        .WB_pc       (WB_pc       ),
        .HI_data     (HI_data     ),
        .LO_data     (LO_data     )
    );

    inst_rom inst_rom_module(
        .clka       (clk           ),
        .addra      (inst_addr[9:2]),
        .douta      (inst          )
    );

    regfile rf_module(
        .clk    (clk      ),
        .wen    (rf_wen   ),
        .raddr1 (rs       ),
        .raddr2 (rt       ),
        .waddr  (rf_wdest ),
        .wdata  (rf_wdata ),
        .rdata1 (rs_value ),
        .rdata2 (rt_value ),


        .test_addr(rf_addr),
        .test_data(rf_data)
    );
    
    data_ram data_ram_module(
        .clka   (clk         ),
        .wea    (dm_wen      ),
        .addra  (dm_addr[9:2]),
        .dina   (dm_wdata    ),
        .douta  (dm_rdata    ),


        .clkb   (clk          ),
        .web    (4'd0         ),
        .addrb  (mem_addr[9:2]),
        .doutb  (mem_data     ),
        .dinb   (32'd0        )
    );

endmodule