data/full_repos/permissive/155759747/instruction_stack.v
data/verilator_xmls/5556fbd8-808b-4d7d-91c0-25075264374a.xml
module instruction_stack(in, out, push, pop, current_state, clk, reset_n);

	input[23:0] in;

	output reg[23:0] out;

	input push, pop;

	input clk;
	input reset_n;

	output[3:0]  current_state;


	reg[23:0] memory[255:0];

	reg[7:0] stack_ptr;

	wire incr, decr, read, write;
	
	control ctrl(push, pop, incr, decr, read, write, clk, reset_n);

	always@(posedge clk)
	begin
		if(!reset_n)
			out <= 24'b0;
		else begin
			if(incr)
				stack_ptr <= stack_ptr + 1;
			if(decr)
				stack_ptr <= stack_ptr - 1;
			if(read)
				out <= memory[stack_ptr];
			if(write)
				memory[stack_ptr] <= in;
		end
	end

endmodule
module instruction_stack(in, out, push, pop, current_state, clk, reset_n);


	input[23:0] in;

	output reg[23:0] out;

	input push, pop;

	input clk;
	input reset_n;

	output[3:0]  current_state;


	reg[23:0] memory[255:0];

	reg[7:0] stack_ptr;

	wire incr, decr, read, write;
	
	control ctrl(push, pop, incr, decr, read, write, clk, reset_n);

	always@(posedge clk)
	begin
		if(!reset_n)
			out <= 24'b0;
		else begin
			if(incr)
				stack_ptr <= stack_ptr + 1;
			if(decr)
				stack_ptr <= stack_ptr - 1;
			if(read)
				out <= memory[stack_ptr];
			if(write)
				memory[stack_ptr] <= in;
		end
	end

endmodule