data/full_repos/permissive/20951436/Code/fpga code/advanced code/Advanced code.v
1: b'%Error: Cannot find file containing module: code/advanced\n        ... Looked in:\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.v\n             data/full_repos/permissive/20951436/Code/fpga/code/advanced.sv\n             code/advanced\n             code/advanced.v\n             code/advanced.sv\n             obj_dir/code/advanced\n             obj_dir/code/advanced.v\n             obj_dir/code/advanced.sv\n%Error: Cannot find file containing module: code,data/full_repos/permissive/20951436\n%Error: Cannot find file containing module: data/full_repos/permissive/20951436/Code/fpga\n%Error: Cannot find file containing module: code/Advanced\n%Error: Cannot find file containing module: code.v\n%Error: Exiting due to 5 error(s)\n'
module multiplier(input clk, input sign, input [31:0] oprnd1, oprnd2, input en, output [63:0] product, output comp_sig);

	reg [63:0] product_temp;

	reg [31:0] oprnd1_copy;
	reg [63:0] oprnd2_copy;
	

	wire negative_output; assign negative_output = ( sign && ((oprnd1[31] && !oprnd2[31]) || (!oprnd1[31] && oprnd2[31])) );
   
	reg [5:0] bit_consumed;
   
	assign comp_sig = &(~bit_consumed);



	assign product = ( (negative_output) ? ~product_temp + 1'b1 : product_temp );
	reg en_hist;
	always @(negedge clk) begin
		en_hist<=en;
		if (en && (~en_hist)) begin

			bit_consumed <= 6'd32; 
			product_temp <= 0;


			oprnd2_copy <= ( (!sign || !oprnd2[31]) ? { 32'd0, oprnd2 } : { 32'd0, ~oprnd2 + 1'b1} );
			oprnd1_copy <= ( (!sign || !oprnd1[31]) ? oprnd1 : ~oprnd1 + 1'b1 );
		end else begin
			if (bit_consumed > 0) begin

				if( oprnd1_copy[0] == 1'b1 ) product_temp <= product_temp + oprnd2_copy;

				oprnd1_copy <= oprnd1_copy >> 1;
				oprnd2_copy <= oprnd2_copy << 1;
				bit_consumed <= bit_consumed - 1'b1;

		  end
		end
  end
endmodule
module multiplier(input clk, input sign, input [31:0] oprnd1, oprnd2, input en, output [63:0] product, output comp_sig);


	reg [63:0] product_temp;

	reg [31:0] oprnd1_copy;
	reg [63:0] oprnd2_copy;
	

	wire negative_output; assign negative_output = ( sign && ((oprnd1[31] && !oprnd2[31]) || (!oprnd1[31] && oprnd2[31])) );
   
	reg [5:0] bit_consumed;
   
	assign comp_sig = &(~bit_consumed);



	assign product = ( (negative_output) ? ~product_temp + 1'b1 : product_temp );
	reg en_hist;
	always @(negedge clk) begin
		en_hist<=en;
		if (en && (~en_hist)) begin

			bit_consumed <= 6'd32; 
			product_temp <= 0;


			oprnd2_copy <= ( (!sign || !oprnd2[31]) ? { 32'd0, oprnd2 } : { 32'd0, ~oprnd2 + 1'b1} );
			oprnd1_copy <= ( (!sign || !oprnd1[31]) ? oprnd1 : ~oprnd1 + 1'b1 );
		end else begin
			if (bit_consumed > 0) begin

				if( oprnd1_copy[0] == 1'b1 ) product_temp <= product_temp + oprnd2_copy;

				oprnd1_copy <= oprnd1_copy >> 1;
				oprnd2_copy <= oprnd2_copy << 1;
				bit_consumed <= bit_consumed - 1'b1;

		  end
		end
  end
endmodule