data/full_repos/permissive/168395472/problems/07_cpu_v1/alu.v
data/verilator_xmls/6e2d106e-0d72-409b-893b-1c58a43be8b6.xml
module alu(
    input [31:0]src_a,
    input [31:0]src_b,
    input [2:0]op,

    output reg [31:0]res
);

always @(*) begin

end

endmodule
module alu(
    input [31:0]src_a,
    input [31:0]src_b,
    input [2:0]op,

    output reg [31:0]res
);


always @(*) begin

end

endmodule