data/full_repos/permissive/139213403/FPGA/led_bar_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/led_bar_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/led_bar_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/led_bar_testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n   #(T / 2);\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/led_bar_testbench.v:50: syntax error, unexpected \'@\'\n   @(negedge reset);\n   ^\n%Error: data/full_repos/permissive/139213403/FPGA/led_bar_testbench.v:54: syntax error, unexpected \'@\'\n     @(negedge clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/led_bar_testbench.v:58: Unsupported: Ignoring delay on this delayed statement.\n     #(1000);\n     ^\n%Error: data/full_repos/permissive/139213403/FPGA/led_bar_testbench.v:59: syntax error, unexpected \'@\'\n     @(negedge clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/led_bar_testbench.v:61: Unsupported: Ignoring delay on this delayed statement.\n     #(1000);\n     ^\n%Error: data/full_repos/permissive/139213403/FPGA/led_bar_testbench.v:62: syntax error, unexpected \'@\'\n     @(negedge clk);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/139213403/FPGA/led_bar_testbench.v:64: Unsupported: Ignoring delay on this delayed statement.\n     #(1000);\n     ^\n%Error: data/full_repos/permissive/139213403/FPGA/led_bar_testbench.v:65: syntax error, unexpected \'@\'\n     @(negedge clk);\n     ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module led_bar_testbench;
	
	localparam T=20,
	           VAL_BITS = 3,
				  LEDS_I = 4,
				  LEDS_O = 2,
				  VAL_L = 0,
				  VAL_U = 7;
	
	reg clk, reset;
	reg en;
	reg [VAL_BITS-1:0] value;
	reg blink;
	wire [LEDS_I-1:0] in_en;
	wire [LEDS_O-1:0] out_en;
	integer i;
	
	led_bar         #(
								.LEDS_I(LEDS_I), .LEDS_O(LEDS_O), .LEDS_BITS(4),
								.VAL_L(VAL_L), .VAL_U(VAL_U), .VAL_Z(3), .VAL_BITS(VAL_BITS),
								.C_ON(2), .C_OFF(3), .C_BITS(3)
						  )
						 uut
						 (
								.clk(clk), .reset(reset), .en(en),
								.value(value), .blink(blink),
								.in_en(in_en), .out_en(out_en)
						 );

	always
		begin
			clk = 1'b1;
			#(T / 2);
			clk = 1'b0;
			#(T / 2);
		end
		

	initial
		begin
			reset = 1'b1;
			#(T / 2);
			reset = 1'b0;
		end
	
	initial
		begin
			@(negedge reset);
			
			for (i = VAL_L; i <= VAL_U; i = i + 1)
				begin
					@(negedge clk);
					en = 1;
					blink = 0;
					value = i;
					#(1000);
					@(negedge clk);
					blink = 1;
					#(1000);
					@(negedge clk);
					en = 0;
					#(1000);
					@(negedge clk);
				end
		
			$stop;
		end
	
endmodule
module led_bar_testbench;

	
	localparam T=20,
	           VAL_BITS = 3,
				  LEDS_I = 4,
				  LEDS_O = 2,
				  VAL_L = 0,
				  VAL_U = 7;
	
	reg clk, reset;
	reg en;
	reg [VAL_BITS-1:0] value;
	reg blink;
	wire [LEDS_I-1:0] in_en;
	wire [LEDS_O-1:0] out_en;
	integer i;
	
	led_bar         #(
								.LEDS_I(LEDS_I), .LEDS_O(LEDS_O), .LEDS_BITS(4),
								.VAL_L(VAL_L), .VAL_U(VAL_U), .VAL_Z(3), .VAL_BITS(VAL_BITS),
								.C_ON(2), .C_OFF(3), .C_BITS(3)
						  )
						 uut
						 (
								.clk(clk), .reset(reset), .en(en),
								.value(value), .blink(blink),
								.in_en(in_en), .out_en(out_en)
						 );

	always
		begin
			clk = 1'b1;
			#(T / 2);
			clk = 1'b0;
			#(T / 2);
		end
		

	initial
		begin
			reset = 1'b1;
			#(T / 2);
			reset = 1'b0;
		end
	
	initial
		begin
			@(negedge reset);
			
			for (i = VAL_L; i <= VAL_U; i = i + 1)
				begin
					@(negedge clk);
					en = 1;
					blink = 0;
					value = i;
					#(1000);
					@(negedge clk);
					blink = 1;
					#(1000);
					@(negedge clk);
					en = 0;
					#(1000);
					@(negedge clk);
				end
		
			$stop;
		end
	
endmodule