data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/input_m.v
1: b'%Warning-WIDTH: data/full_repos/permissive/163602545/NoCSimp/NoCSimp_Modelsim/input_m.v:153: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance InPort\n          if (Inr[port] == 1\'b1) step =1\'b0;\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module InPort 
   #(
        parameter DATA_WIDTH = 37,
        parameter POSITION = 4'b0101
   )
(
dataInE, 
dataInW,
dataInS,
dataInN,
dataInL,
clk,
full,
reset,
Inr_L,Inr_N,Inr_E,Inr_S,Inr_W,
Inw_L,Inw_N,Inw_E,Inw_S,Inw_W,
DataFiFo,
wrreq
);

input [DATA_WIDTH-1:0]  dataInE, dataInW, dataInS, dataInN, dataInL;
input full;
input reset;
input clk;
input Inr_L,Inr_N,Inr_E,Inr_S,Inr_W;
output Inw_L,Inw_N,Inw_E,Inw_S,Inw_W;
output [DATA_WIDTH-1:0] DataFiFo;
output wrreq;
reg wrreq;
reg [DATA_WIDTH-1:0] DataFiFo;
reg [1:0] step;
reg [2:0] port;
reg [4:0] Inw;
wire [4:0] Inr;

assign Inr = {Inr_L,Inr_N,Inr_E,Inr_S,Inr_W};
assign {Inw_L,Inw_N,Inw_E,Inw_S,Inw_W} = Inw;

always @(posedge clk or posedge reset)
begin
	if (reset == 1'b1)
        begin
			step<=0;
			port<=0;
			wrreq<=0;
			Inw<=0;
			DataFiFo<=0;
		end
    else
		begin

			case (step)
				0:  begin
						if (full) $display("SW full %b", POSITION);

						if ((!full) && (Inr > 0))

							begin

								if (Inr[port] != 1'b1)
									begin


										port=(port+1)%5;
										if (Inr[port] != 1'b1)
										begin
										  port=(port+1)%5;
										  if (Inr[port] != 1'b1)
										  begin
										    port=(port+1)%5;
										    if (Inr[port] != 1'b1)
										    begin
										      port=(port+1)%5;
										      if (Inr[port] != 1'b1)
										      port=(port+1)%5;
										    end
										  end
										end
									end
							  else

									begin
										Inw<=(1'b1 << port);
										case (port)
											0: DataFiFo=dataInW;
											1: DataFiFo=dataInS;
											2: DataFiFo=dataInE;
											3: DataFiFo=dataInN;
											4: DataFiFo=dataInL;	
										endcase

										$display("SW %d: Received flit at time: %t to %d", POSITION, $time, DataFiFo[3:0]);
										wrreq<=1'b1;
										step=1;
									end
							end
														
							
					end	
				1:  begin
				    
						wrreq<=1'b0;
						if (Inr[port] == 1'b0) 
							begin 
								Inw<=0;
								if (DataFiFo[4] == 1'b1) 
								  begin 
								    step=0; 
								    port=(port+1)%5; 
								  end
								else step = 2; 									
							end
					end
				2:  begin
				      if (Inr[port] == 1'b1) step =1'b0;
				    end
				
			endcase
		end
	
end
endmodule
module InPort 
   #(
        parameter DATA_WIDTH = 37,
        parameter POSITION = 4'b0101
   )
(
dataInE, 
dataInW,
dataInS,
dataInN,
dataInL,
clk,
full,
reset,
Inr_L,Inr_N,Inr_E,Inr_S,Inr_W,
Inw_L,Inw_N,Inw_E,Inw_S,Inw_W,
DataFiFo,
wrreq
);


input [DATA_WIDTH-1:0]  dataInE, dataInW, dataInS, dataInN, dataInL;
input full;
input reset;
input clk;
input Inr_L,Inr_N,Inr_E,Inr_S,Inr_W;
output Inw_L,Inw_N,Inw_E,Inw_S,Inw_W;
output [DATA_WIDTH-1:0] DataFiFo;
output wrreq;
reg wrreq;
reg [DATA_WIDTH-1:0] DataFiFo;
reg [1:0] step;
reg [2:0] port;
reg [4:0] Inw;
wire [4:0] Inr;

assign Inr = {Inr_L,Inr_N,Inr_E,Inr_S,Inr_W};
assign {Inw_L,Inw_N,Inw_E,Inw_S,Inw_W} = Inw;

always @(posedge clk or posedge reset)
begin
	if (reset == 1'b1)
        begin
			step<=0;
			port<=0;
			wrreq<=0;
			Inw<=0;
			DataFiFo<=0;
		end
    else
		begin

			case (step)
				0:  begin
						if (full) $display("SW full %b", POSITION);

						if ((!full) && (Inr > 0))

							begin

								if (Inr[port] != 1'b1)
									begin


										port=(port+1)%5;
										if (Inr[port] != 1'b1)
										begin
										  port=(port+1)%5;
										  if (Inr[port] != 1'b1)
										  begin
										    port=(port+1)%5;
										    if (Inr[port] != 1'b1)
										    begin
										      port=(port+1)%5;
										      if (Inr[port] != 1'b1)
										      port=(port+1)%5;
										    end
										  end
										end
									end
							  else

									begin
										Inw<=(1'b1 << port);
										case (port)
											0: DataFiFo=dataInW;
											1: DataFiFo=dataInS;
											2: DataFiFo=dataInE;
											3: DataFiFo=dataInN;
											4: DataFiFo=dataInL;	
										endcase

										$display("SW %d: Received flit at time: %t to %d", POSITION, $time, DataFiFo[3:0]);
										wrreq<=1'b1;
										step=1;
									end
							end
														
							
					end	
				1:  begin
				    
						wrreq<=1'b0;
						if (Inr[port] == 1'b0) 
							begin 
								Inw<=0;
								if (DataFiFo[4] == 1'b1) 
								  begin 
								    step=0; 
								    port=(port+1)%5; 
								  end
								else step = 2; 									
							end
					end
				2:  begin
				      if (Inr[port] == 1'b1) step =1'b0;
				    end
				
			endcase
		end
	
end
endmodule