data/full_repos/permissive/141038711/tb/apb_wrtsetclr_test.v
 line:44: before: "#"
1: b'%Error: data/full_repos/permissive/141038711/tb/apb_wrtsetclr_test.v:43: syntax error, unexpected \'@\'\n      @(posedge pclk)\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/141038711/tb/apb_wrtsetclr_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n       #(CLK_PERIOD*5) ; \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/141038711/tb/apb_wrtsetclr_test.v:68: Unsupported: Ignoring delay on this delayed statement.\n   #500 $stop;       \n   ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module apb_wrtsetclr_test;

localparam CLK_PERIOD=100;




reg          reset_n;
reg          enable;


wire         pclk;
wire [ 15:0] paddr;
wire         pwrite;
wire         psel;
wire         penable;
wire [ 31:0] pwdata;
wire [ 31:0] prdata;
wire         pready;
wire         pslverr;


wire [ 31:0] control32;


reg flag;

   initial
   begin


      reset_n    = 1'b0;
      enable     = 1'b1;
      flag       = 1'b0;
      
      @(posedge pclk)
         #(CLK_PERIOD*5) ; 
      reset_n = 1'b1;
       #(CLK_PERIOD*5) ; 
       

       apb_bus0.write(16'h0,32'hAAAA5555);
       apb_bus0.read(16'h0,32'hAAAA5555);
       apb_bus0.read(16'h4,32'hAAAA5555);


       apb_bus0.write(16'h0,32'h55550000);
       apb_bus0.read(16'h0,32'hFFFF5555);
       apb_bus0.read(16'h4,32'hFFFF5555);
       

       apb_bus0.write(16'h4,32'h00005500);
       apb_bus0.read(16'h0,32'hFFFF0055);
       apb_bus0.read(16'h4,32'hFFFF0055);
       apb_bus0.delay(3);
       if (apb_bus0.errors==0)
          $display("apb_wrtsetclr test passed");
       else
          $display("apb_wrtsetclr test FAILED!");
		
		 #500 $stop;       
   end


apb_wrtsetclr
apb_wrtsetclr_0 (


      .reset_n  (reset_n),
      .enable   (enable),


      .pclk     (pclk),
      .paddr    (paddr[2:0]),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr),


      .control32(control32)
   );
   
apb_bus 
#(.CLKPER(CLK_PERIOD)
 )
apb_bus0 (

      .pclk     (pclk),
      .paddr    (paddr),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr)
      ); 
   


endmodule
module apb_wrtsetclr_test;


localparam CLK_PERIOD=100;




reg          reset_n;
reg          enable;


wire         pclk;
wire [ 15:0] paddr;
wire         pwrite;
wire         psel;
wire         penable;
wire [ 31:0] pwdata;
wire [ 31:0] prdata;
wire         pready;
wire         pslverr;


wire [ 31:0] control32;


reg flag;

   initial
   begin


      reset_n    = 1'b0;
      enable     = 1'b1;
      flag       = 1'b0;
      
      @(posedge pclk)
         #(CLK_PERIOD*5) ; 
      reset_n = 1'b1;
       #(CLK_PERIOD*5) ; 
       

       apb_bus0.write(16'h0,32'hAAAA5555);
       apb_bus0.read(16'h0,32'hAAAA5555);
       apb_bus0.read(16'h4,32'hAAAA5555);


       apb_bus0.write(16'h0,32'h55550000);
       apb_bus0.read(16'h0,32'hFFFF5555);
       apb_bus0.read(16'h4,32'hFFFF5555);
       

       apb_bus0.write(16'h4,32'h00005500);
       apb_bus0.read(16'h0,32'hFFFF0055);
       apb_bus0.read(16'h4,32'hFFFF0055);
       apb_bus0.delay(3);
       if (apb_bus0.errors==0)
          $display("apb_wrtsetclr test passed");
       else
          $display("apb_wrtsetclr test FAILED!");
		
		 #500 $stop;       
   end


apb_wrtsetclr
apb_wrtsetclr_0 (


      .reset_n  (reset_n),
      .enable   (enable),


      .pclk     (pclk),
      .paddr    (paddr[2:0]),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr),


      .control32(control32)
   );
   
apb_bus 
#(.CLKPER(CLK_PERIOD)
 )
apb_bus0 (

      .pclk     (pclk),
      .paddr    (paddr),
      .pwrite   (pwrite),
      .psel     (psel),
      .penable  (penable),
      .pwdata   (pwdata),
      .prdata   (prdata),
      .pready   (pready),
      .pslverr  (pslverr)
      ); 
   


endmodule