data/full_repos/permissive/143278/ivltests/delay_assign_nb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/delay_assign_nb.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a !== 0) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/delay_assign_nb.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #2 if (a !== 1\'b1) begin\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main ;

   reg a;

   initial begin
      a = 0;
      if (a !== 0) begin
	 $display("FAILED -- a at 0 is %b", a);
	 $finish;
      end

      a <= #2 1;

      if (a !== 0) begin
	 $display("FAILED -- (0) a should still be 0 but is %b", a);
	 $finish;
      end

      #1 if (a !== 0) begin
	 $display("FAILED -- (1) a should still be 0 but is %b", a);
	 $finish;
      end

      #2 if (a !== 1'b1) begin
	 $display("FAILED -- a should now be 1, but is %b", a);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module main ;


   reg a;

   initial begin
      a = 0;
      if (a !== 0) begin
	 $display("FAILED -- a at 0 is %b", a);
	 $finish;
      end

      a <= #2 1;

      if (a !== 0) begin
	 $display("FAILED -- (0) a should still be 0 but is %b", a);
	 $finish;
      end

      #1 if (a !== 0) begin
	 $display("FAILED -- (1) a should still be 0 but is %b", a);
	 $finish;
      end

      #2 if (a !== 1'b1) begin
	 $display("FAILED -- a should now be 1, but is %b", a);
	 $finish;
      end

      $display("PASSED");
   end

endmodule