data/full_repos/permissive/116308238/hdl/axilite_control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/116308238/hdl/axilite_control.v:415: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                              : ... In instance axilite_control\n       axi_araddr  <= 32\'b0;\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/116308238/hdl/axilite_control.v:554: Cannot find file containing module: \'wordalign\'\n    wordalign align(\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/116308238/hdl,data/full_repos/permissive/116308238/wordalign\n             data/full_repos/permissive/116308238/hdl,data/full_repos/permissive/116308238/wordalign.v\n             data/full_repos/permissive/116308238/hdl,data/full_repos/permissive/116308238/wordalign.sv\n             wordalign\n             wordalign.v\n             wordalign.sv\n             obj_dir/wordalign\n             obj_dir/wordalign.v\n             obj_dir/wordalign.sv\n%Error: data/full_repos/permissive/116308238/hdl/axilite_control.v:565: Cannot find file containing module: \'pckthandler\'\n    pckthandler depacket(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/116308238/hdl/axilite_control.v:577: Cannot find file containing module: \'raw10_decoder\'\n    raw10_decoder unpack(\n    ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module axilite_control #
(

    parameter integer N_DATA_LANES = 2,


	parameter integer C_S_AXI_DATA_WIDTH	= 32,

	parameter integer C_S_AXI_ADDR_WIDTH	= 5
)
(

	output wire csi_intr,
	

	input wire rxbyteclkhs_resetn,
	

	input wire cl_stopstate,
	output wire cl_enable,
	input wire rxbyteclkhs,
	
	input wire dl0_rxactivehs,
	input wire dl0_rxsynchs,
	output wire dl0_enable,
	output wire dl0_forcerxmode,
	input wire dl0_rxvalidhs,
	input wire [7:0] dl0_rxdatahs,
	
	input wire dl1_rxactivehs,
    input wire dl1_rxsynchs,
    output wire dl1_enable,
    output wire dl1_forcerxmode,
    input wire dl1_rxvalidhs,
    input wire [7:0] dl1_rxdatahs,
    



    output wire m_axis_tvalid,
    output wire [63:0] m_axis_tdata,
    output wire [7:0] m_axis_tstrb,
    output wire m_axis_tlast,
    input wire m_axis_tready,





	input wire  S_AXI_ACLK,

	input wire  S_AXI_ARESETN,

	input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



	input wire [2 : 0] S_AXI_AWPROT,


	input wire  S_AXI_AWVALID,


	output wire  S_AXI_AWREADY,

	input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



	input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


	input wire  S_AXI_WVALID,


	output wire  S_AXI_WREADY,


	output wire [1 : 0] S_AXI_BRESP,


	output wire  S_AXI_BVALID,


	input wire  S_AXI_BREADY,

	input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



	input wire [2 : 0] S_AXI_ARPROT,


	input wire  S_AXI_ARVALID,


	output wire  S_AXI_ARREADY,

	output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


	output wire [1 : 0] S_AXI_RRESP,


	output wire  S_AXI_RVALID,


	input wire  S_AXI_RREADY
);
    

    localparam NUM_INTRS    = 2;
    localparam SOF_REG_BIT  = 2;
    localparam SOF_INTR_BIT = 0;
    localparam EOF_REG_BIT  = 3;
    localparam OUTPUT_EN_BIT = 4;
    localparam EOF_INTR_BIT = 1;
    localparam GLOBALINT_BIT= 1;
    localparam RS_REG_BIT   = 0;
    
    reg [(NUM_INTRS-1):0] irqs_posted, irqs_acked;
    reg frame_active_new, frame_active_last;
    reg RS_flag;
    reg RS_new, RS_last;
    reg enable_output;
    

    wire reset;
    wire [(N_DATA_LANES*8)-1:0] aligned_word_out;
    wire aligned_word_valid;
    wire frame_active;
    wire frame_valid;
    wire [(N_DATA_LANES*8)-1:0] frame_out;
    wire [63:0] unpacked_out;
    wire unpacked_out_valid;
    wire unpacked_last;
    wire last_packet;
    


	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;






	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 2;




	reg [C_S_AXI_DATA_WIDTH-1:0]	CSI_CONFIG_REG;
	reg [C_S_AXI_DATA_WIDTH-1:0]	CSI_CTRL_SET_REG;
	reg [C_S_AXI_DATA_WIDTH-1:0]	CSI_CTRL_CLEAR_REG;
	reg [C_S_AXI_DATA_WIDTH-1:0]	CSI_STATUS_REG;
	reg [C_S_AXI_DATA_WIDTH-1:0]	CSI_FR_LINES_REG;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg5;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg6;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg7;
	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;
	reg	 aw_en;



	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	      aw_en <= 1'b1;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
	        begin




	          axi_awready <= 1'b1;
	          aw_en <= 1'b0;
	        end
	        else if (S_AXI_BREADY && axi_bvalid)
	            begin
	              aw_en <= 1'b1;
	              axi_awready <= 1'b0;
	            end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
	        begin

	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
	        begin




	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      CSI_CONFIG_REG       <= 0;
	      CSI_CTRL_SET_REG     <= 0;
	      CSI_CTRL_CLEAR_REG   <= 0;
	      CSI_STATUS_REG       <= 0;
	      CSI_FR_LINES_REG     <= 0;
	      slv_reg5 <= 0;
	      slv_reg6 <= 0;
	      slv_reg7 <= 0;
	      
	      irqs_acked <= 0;
	      RS_new <= 0;
	      RS_last <= 0;
	    end 
	  else begin
	    irqs_acked <= 0;
	    RS_last <= RS_new;
	  
	    if (slv_reg_wren)
	      begin
	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	          3'h0: begin
	                CSI_CONFIG_REG <= S_AXI_WDATA;
	              end  
	          3'h1: begin	                	                

	               irqs_acked <= {2{S_AXI_WDATA[GLOBALINT_BIT]}} | {S_AXI_WDATA[EOF_REG_BIT], S_AXI_WDATA[SOF_REG_BIT]};
	                

	                if(S_AXI_WDATA[0] & ~RS_flag) begin
	                   RS_new <= 1'b1;
	                   RS_last <= 1'b0;
	                end
	              end  
	          3'h2: begin
	                if(S_AXI_WDATA[0] == 1'b1) begin
	                   RS_new <= 1'b0;
	                end
	              end  
	          3'h3: begin


	                   CSI_STATUS_REG <= CSI_STATUS_REG;
	               end 
	          3'h4: begin
	                   CSI_FR_LINES_REG <= S_AXI_WDATA;
	               end 
	          3'h5:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          3'h6:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          3'h7:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          default : begin
	                      CSI_CONFIG_REG <= CSI_CONFIG_REG;
	                      CSI_CTRL_SET_REG <= CSI_CTRL_SET_REG;
	                      CSI_CTRL_CLEAR_REG <= CSI_CTRL_CLEAR_REG;
	                      CSI_STATUS_REG <= CSI_STATUS_REG;
	                      CSI_FR_LINES_REG <= CSI_FR_LINES_REG;
	                      slv_reg5 <= slv_reg5;
	                      slv_reg6 <= slv_reg6;
	                      slv_reg7 <= slv_reg7;
	                    end
	        endcase
	      end
	  end
	end    







	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin

	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0;
	        end
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 


	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   








	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin

	          axi_arready <= 1'b1;

	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin

	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0;
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin

	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    




	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin

	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	        3'h0   : reg_data_out <= CSI_CONFIG_REG;
	        3'h1   : reg_data_out <= 0;
	        3'h2   : reg_data_out <= 0;
	        3'h3   : begin

	             reg_data_out[31:4] <= 0;
	             reg_data_out[3] <= irqs_posted[EOF_INTR_BIT];
	             reg_data_out[2] <= irqs_posted[SOF_INTR_BIT];
	             reg_data_out[1] <= (| irqs_posted);
	             reg_data_out[0] <= RS_flag;
	           end
	        3'h4   : reg_data_out <= CSI_FR_LINES_REG;
	        3'h5   : reg_data_out <= 32'hDEADBEEF;
	        3'h6   : reg_data_out <= 32'hDEADBEEF;
	        3'h7   : reg_data_out <= 32'hDEADBEEF;
	        default : reg_data_out <= 0;
	      endcase
	end


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    



	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;
	        end   
	    end
	end    


	

	assign reset = ~rxbyteclkhs_resetn | ~RS_flag;
		

	assign csi_intr = CSI_CONFIG_REG[GLOBALINT_BIT] & (| (irqs_posted & CSI_CONFIG_REG[EOF_REG_BIT:SOF_REG_BIT]));


    always @(posedge S_AXI_ACLK)
    begin
        if ( S_AXI_ARESETN == 1'b0 )
        begin
            irqs_posted <= 0;
            frame_active_new <= 0;
            frame_active_last <= 0;
        end
        else begin
            frame_active_new <= frame_active;
            frame_active_last <= frame_active_new;
            
            if(~frame_active_last & frame_active_new) irqs_posted[SOF_INTR_BIT] <= 1'b1;
            else if(frame_active_last & ~frame_active_new) irqs_posted[EOF_INTR_BIT] <= 1'b1;
            else begin
                irqs_posted[SOF_INTR_BIT] <= irqs_posted[SOF_INTR_BIT] & ~irqs_acked[SOF_INTR_BIT];
                irqs_posted[EOF_INTR_BIT] <= irqs_posted[EOF_INTR_BIT] & ~irqs_acked[EOF_INTR_BIT];
            end
        end
    end
   
    

    always @(posedge S_AXI_ACLK)
    begin
        if ( S_AXI_ARESETN == 1'b0 ) RS_flag <= 0;
        else begin
            if(RS_last & ~RS_new) RS_flag <= 1'b0;
            else if(~RS_last & RS_new) RS_flag <= 1'b1;
            else if(~CSI_CONFIG_REG[RS_REG_BIT] & ~frame_active_new & frame_active_last) RS_flag <= 1'b0;
            else RS_flag <= RS_flag;
        end
    end
    

    wordalign align(
        .clk(rxbyteclkhs),
        .resetn(rxbyteclkhs_resetn),
        .dl0_rxvalidhs(dl0_rxvalidhs),
        .dl0_rxdatahs(dl0_rxdatahs),
        .dl1_rxvalidhs(dl1_rxvalidhs),
        .dl1_rxdatahs(dl1_rxdatahs),
        .word_out(aligned_word_out),
        .word_valid(aligned_word_valid)
    );
    
    pckthandler depacket(
        .rxbyteclkhs(rxbyteclkhs),
        .reset(reset),
        .in_stream_valid(aligned_word_valid),
        .in_stream(aligned_word_out),
        .frame_active(frame_active),
        .frame_valid(frame_valid),
        .out_stream(frame_out),
        .lines_per_frame(CSI_FR_LINES_REG),
        .last_packet(last_packet)
    );
    
    raw10_decoder unpack(
        .rxbyteclkhs(rxbyteclkhs),
        .reset(reset),
        .frame_active(frame_active),
        .frame_valid(frame_valid),
        .data_in(frame_out),
        .out_valid(unpacked_out_valid),
        .data_out(unpacked_out),
        .last_packet_in(last_packet),
        .last_packet_out(unpacked_last)
    );
    



    always @(posedge S_AXI_ACLK)
    begin
        if ( S_AXI_ARESETN == 1'b0 )
            enable_output <= 0;
        else if(~frame_active_last & frame_active_new)
            enable_output <= CSI_CONFIG_REG[OUTPUT_EN_BIT];
        else
            enable_output <= enable_output;
    end


    assign m_axis_tdata =  enable_output ? unpacked_out : 0;
    assign m_axis_tvalid = enable_output ? unpacked_out_valid : 0;
    assign m_axis_tstrb =  enable_output ? 8'b11111111 : 0;
    assign m_axis_tlast =  enable_output ? unpacked_last : 0;
    

    assign cl_enable = 1'b1;
    assign dl0_enable = 1'b1;
    assign dl1_enable = 1'b1;
    

    assign dl0_forcerxmode = 1'b1;
    assign dl1_forcerxmode = 1'b1;
    


	endmodule
module axilite_control #
(

    parameter integer N_DATA_LANES = 2,


	parameter integer C_S_AXI_DATA_WIDTH	= 32,

	parameter integer C_S_AXI_ADDR_WIDTH	= 5
)
(

	output wire csi_intr,
	

	input wire rxbyteclkhs_resetn,
	

	input wire cl_stopstate,
	output wire cl_enable,
	input wire rxbyteclkhs,
	
	input wire dl0_rxactivehs,
	input wire dl0_rxsynchs,
	output wire dl0_enable,
	output wire dl0_forcerxmode,
	input wire dl0_rxvalidhs,
	input wire [7:0] dl0_rxdatahs,
	
	input wire dl1_rxactivehs,
    input wire dl1_rxsynchs,
    output wire dl1_enable,
    output wire dl1_forcerxmode,
    input wire dl1_rxvalidhs,
    input wire [7:0] dl1_rxdatahs,
    



    output wire m_axis_tvalid,
    output wire [63:0] m_axis_tdata,
    output wire [7:0] m_axis_tstrb,
    output wire m_axis_tlast,
    input wire m_axis_tready,





	input wire  S_AXI_ACLK,

	input wire  S_AXI_ARESETN,

	input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,



	input wire [2 : 0] S_AXI_AWPROT,


	input wire  S_AXI_AWVALID,


	output wire  S_AXI_AWREADY,

	input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,



	input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,


	input wire  S_AXI_WVALID,


	output wire  S_AXI_WREADY,


	output wire [1 : 0] S_AXI_BRESP,


	output wire  S_AXI_BVALID,


	input wire  S_AXI_BREADY,

	input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,



	input wire [2 : 0] S_AXI_ARPROT,


	input wire  S_AXI_ARVALID,


	output wire  S_AXI_ARREADY,

	output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,


	output wire [1 : 0] S_AXI_RRESP,


	output wire  S_AXI_RVALID,


	input wire  S_AXI_RREADY
);

    

    localparam NUM_INTRS    = 2;
    localparam SOF_REG_BIT  = 2;
    localparam SOF_INTR_BIT = 0;
    localparam EOF_REG_BIT  = 3;
    localparam OUTPUT_EN_BIT = 4;
    localparam EOF_INTR_BIT = 1;
    localparam GLOBALINT_BIT= 1;
    localparam RS_REG_BIT   = 0;
    
    reg [(NUM_INTRS-1):0] irqs_posted, irqs_acked;
    reg frame_active_new, frame_active_last;
    reg RS_flag;
    reg RS_new, RS_last;
    reg enable_output;
    

    wire reset;
    wire [(N_DATA_LANES*8)-1:0] aligned_word_out;
    wire aligned_word_valid;
    wire frame_active;
    wire frame_valid;
    wire [(N_DATA_LANES*8)-1:0] frame_out;
    wire [63:0] unpacked_out;
    wire unpacked_out_valid;
    wire unpacked_last;
    wire last_packet;
    


	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;






	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 2;




	reg [C_S_AXI_DATA_WIDTH-1:0]	CSI_CONFIG_REG;
	reg [C_S_AXI_DATA_WIDTH-1:0]	CSI_CTRL_SET_REG;
	reg [C_S_AXI_DATA_WIDTH-1:0]	CSI_CTRL_CLEAR_REG;
	reg [C_S_AXI_DATA_WIDTH-1:0]	CSI_STATUS_REG;
	reg [C_S_AXI_DATA_WIDTH-1:0]	CSI_FR_LINES_REG;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg5;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg6;
	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg7;
	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	integer	 byte_index;
	reg	 aw_en;



	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	      aw_en <= 1'b1;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
	        begin




	          axi_awready <= 1'b1;
	          aw_en <= 1'b0;
	        end
	        else if (S_AXI_BREADY && axi_bvalid)
	            begin
	              aw_en <= 1'b1;
	              axi_awready <= 1'b0;
	            end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       





	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
	        begin

	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       






	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
	        begin




	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       








	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      CSI_CONFIG_REG       <= 0;
	      CSI_CTRL_SET_REG     <= 0;
	      CSI_CTRL_CLEAR_REG   <= 0;
	      CSI_STATUS_REG       <= 0;
	      CSI_FR_LINES_REG     <= 0;
	      slv_reg5 <= 0;
	      slv_reg6 <= 0;
	      slv_reg7 <= 0;
	      
	      irqs_acked <= 0;
	      RS_new <= 0;
	      RS_last <= 0;
	    end 
	  else begin
	    irqs_acked <= 0;
	    RS_last <= RS_new;
	  
	    if (slv_reg_wren)
	      begin
	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	          3'h0: begin
	                CSI_CONFIG_REG <= S_AXI_WDATA;
	              end  
	          3'h1: begin	                	                

	               irqs_acked <= {2{S_AXI_WDATA[GLOBALINT_BIT]}} | {S_AXI_WDATA[EOF_REG_BIT], S_AXI_WDATA[SOF_REG_BIT]};
	                

	                if(S_AXI_WDATA[0] & ~RS_flag) begin
	                   RS_new <= 1'b1;
	                   RS_last <= 1'b0;
	                end
	              end  
	          3'h2: begin
	                if(S_AXI_WDATA[0] == 1'b1) begin
	                   RS_new <= 1'b0;
	                end
	              end  
	          3'h3: begin


	                   CSI_STATUS_REG <= CSI_STATUS_REG;
	               end 
	          3'h4: begin
	                   CSI_FR_LINES_REG <= S_AXI_WDATA;
	               end 
	          3'h5:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          3'h6:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          3'h7:
	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin


	                slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
	              end  
	          default : begin
	                      CSI_CONFIG_REG <= CSI_CONFIG_REG;
	                      CSI_CTRL_SET_REG <= CSI_CTRL_SET_REG;
	                      CSI_CTRL_CLEAR_REG <= CSI_CTRL_CLEAR_REG;
	                      CSI_STATUS_REG <= CSI_STATUS_REG;
	                      CSI_FR_LINES_REG <= CSI_FR_LINES_REG;
	                      slv_reg5 <= slv_reg5;
	                      slv_reg6 <= slv_reg6;
	                      slv_reg7 <= slv_reg7;
	                    end
	        endcase
	      end
	  end
	end    







	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin

	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0;
	        end
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 


	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   








	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin

	          axi_arready <= 1'b1;

	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       









	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin

	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0;
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin

	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    




	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin

	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
	        3'h0   : reg_data_out <= CSI_CONFIG_REG;
	        3'h1   : reg_data_out <= 0;
	        3'h2   : reg_data_out <= 0;
	        3'h3   : begin

	             reg_data_out[31:4] <= 0;
	             reg_data_out[3] <= irqs_posted[EOF_INTR_BIT];
	             reg_data_out[2] <= irqs_posted[SOF_INTR_BIT];
	             reg_data_out[1] <= (| irqs_posted);
	             reg_data_out[0] <= RS_flag;
	           end
	        3'h4   : reg_data_out <= CSI_FR_LINES_REG;
	        3'h5   : reg_data_out <= 32'hDEADBEEF;
	        3'h6   : reg_data_out <= 32'hDEADBEEF;
	        3'h7   : reg_data_out <= 32'hDEADBEEF;
	        default : reg_data_out <= 0;
	      endcase
	end


	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    



	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;
	        end   
	    end
	end    


	

	assign reset = ~rxbyteclkhs_resetn | ~RS_flag;
		

	assign csi_intr = CSI_CONFIG_REG[GLOBALINT_BIT] & (| (irqs_posted & CSI_CONFIG_REG[EOF_REG_BIT:SOF_REG_BIT]));


    always @(posedge S_AXI_ACLK)
    begin
        if ( S_AXI_ARESETN == 1'b0 )
        begin
            irqs_posted <= 0;
            frame_active_new <= 0;
            frame_active_last <= 0;
        end
        else begin
            frame_active_new <= frame_active;
            frame_active_last <= frame_active_new;
            
            if(~frame_active_last & frame_active_new) irqs_posted[SOF_INTR_BIT] <= 1'b1;
            else if(frame_active_last & ~frame_active_new) irqs_posted[EOF_INTR_BIT] <= 1'b1;
            else begin
                irqs_posted[SOF_INTR_BIT] <= irqs_posted[SOF_INTR_BIT] & ~irqs_acked[SOF_INTR_BIT];
                irqs_posted[EOF_INTR_BIT] <= irqs_posted[EOF_INTR_BIT] & ~irqs_acked[EOF_INTR_BIT];
            end
        end
    end
   
    

    always @(posedge S_AXI_ACLK)
    begin
        if ( S_AXI_ARESETN == 1'b0 ) RS_flag <= 0;
        else begin
            if(RS_last & ~RS_new) RS_flag <= 1'b0;
            else if(~RS_last & RS_new) RS_flag <= 1'b1;
            else if(~CSI_CONFIG_REG[RS_REG_BIT] & ~frame_active_new & frame_active_last) RS_flag <= 1'b0;
            else RS_flag <= RS_flag;
        end
    end
    

    wordalign align(
        .clk(rxbyteclkhs),
        .resetn(rxbyteclkhs_resetn),
        .dl0_rxvalidhs(dl0_rxvalidhs),
        .dl0_rxdatahs(dl0_rxdatahs),
        .dl1_rxvalidhs(dl1_rxvalidhs),
        .dl1_rxdatahs(dl1_rxdatahs),
        .word_out(aligned_word_out),
        .word_valid(aligned_word_valid)
    );
    
    pckthandler depacket(
        .rxbyteclkhs(rxbyteclkhs),
        .reset(reset),
        .in_stream_valid(aligned_word_valid),
        .in_stream(aligned_word_out),
        .frame_active(frame_active),
        .frame_valid(frame_valid),
        .out_stream(frame_out),
        .lines_per_frame(CSI_FR_LINES_REG),
        .last_packet(last_packet)
    );
    
    raw10_decoder unpack(
        .rxbyteclkhs(rxbyteclkhs),
        .reset(reset),
        .frame_active(frame_active),
        .frame_valid(frame_valid),
        .data_in(frame_out),
        .out_valid(unpacked_out_valid),
        .data_out(unpacked_out),
        .last_packet_in(last_packet),
        .last_packet_out(unpacked_last)
    );
    



    always @(posedge S_AXI_ACLK)
    begin
        if ( S_AXI_ARESETN == 1'b0 )
            enable_output <= 0;
        else if(~frame_active_last & frame_active_new)
            enable_output <= CSI_CONFIG_REG[OUTPUT_EN_BIT];
        else
            enable_output <= enable_output;
    end


    assign m_axis_tdata =  enable_output ? unpacked_out : 0;
    assign m_axis_tvalid = enable_output ? unpacked_out_valid : 0;
    assign m_axis_tstrb =  enable_output ? 8'b11111111 : 0;
    assign m_axis_tlast =  enable_output ? unpacked_last : 0;
    

    assign cl_enable = 1'b1;
    assign dl0_enable = 1'b1;
    assign dl1_enable = 1'b1;
    

    assign dl0_forcerxmode = 1'b1;
    assign dl1_forcerxmode = 1'b1;
    


	endmodule