data/full_repos/permissive/143278/ivltests/pr3064511.v
 line:337: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr3064511.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  parameter param = -1;

  reg passed;
  wire [3:0] val = 11;
  wire [3:0] res = val + param;

  reg [3:0] rgval = 11;
  reg [3:0] rgres;

  initial begin
    passed = 1'b1;
    #1;

    if (res !== 10) begin
      $display("FAILED wire result, expected 10, got %d", res);
      passed = 1'b0;
    end

    rgres = rgval + param;
    if (rgres !== 10) begin
      $display("FAILED reg result, expected 10, got %d", rgres);
      passed = 1'b0;
    end

    if (passed) $display("PASSED");
  end
endmodule
module top;

  parameter param = -1;

  reg passed;
  wire [3:0] val = 11;
  wire [3:0] res = val + param;

  reg [3:0] rgval = 11;
  reg [3:0] rgres;

  initial begin
    passed = 1'b1;
    #1;

    if (res !== 10) begin
      $display("FAILED wire result, expected 10, got %d", res);
      passed = 1'b0;
    end

    rgres = rgval + param;
    if (rgres !== 10) begin
      $display("FAILED reg result, expected 10, got %d", rgres);
      passed = 1'b0;
    end

    if (passed) $display("PASSED");
  end
endmodule