data/full_repos/permissive/216344104/speed_setting.v
'utf-8' codec can't decode byte 0xb9 in position 80: invalid start byte
1: b'%Warning-WIDTH: data/full_repos/permissive/216344104/speed_setting.v:32: Operator EQ expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 13 bits.\n                                                                       : ... In instance speed_setting\n else if((cnt == (10_000_000/20/96)) || !bps_start) cnt <= 13\'d0;  \n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/216344104/speed_setting.v:37: Operator EQ expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 13 bits.\n                                                                       : ... In instance speed_setting\n else if(cnt == ((10_000_000/20/96)/2)) clk_bps <= 1\'b1;  \n             ^~\n%Error: Exiting due to 2 warning(s)\n'
module speed_setting(
				input clk,
				input rst_n,
				input bps_start,
				output reg clk_bps
			);

`define BPS_9600
`define CLK_PERIORD	20
`define BPS_SET		96

`define BPS_PARA	(10_000_000/`CLK_PERIORD/`BPS_SET)
`define BPS_PARA_2	(`BPS_PARA/2)

reg[12:0] cnt;


reg[2:0] uart_ctrl;


always @ (posedge clk or negedge rst_n)
	if(!rst_n) cnt <= 13'd0;
	else if((cnt == `BPS_PARA) || !bps_start) cnt <= 13'd0;
	else cnt <= cnt+1'b1;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) clk_bps <= 1'b0;
	else if(cnt == `BPS_PARA_2) clk_bps <= 1'b1;
	else clk_bps <= 1'b0;

	
endmodule
module speed_setting(
				input clk,
				input rst_n,
				input bps_start,
				output reg clk_bps
			);


`define BPS_9600
`define CLK_PERIORD	20
`define BPS_SET		96

`define BPS_PARA	(10_000_000/`CLK_PERIORD/`BPS_SET)
`define BPS_PARA_2	(`BPS_PARA/2)

reg[12:0] cnt;


reg[2:0] uart_ctrl;


always @ (posedge clk or negedge rst_n)
	if(!rst_n) cnt <= 13'd0;
	else if((cnt == `BPS_PARA) || !bps_start) cnt <= 13'd0;
	else cnt <= cnt+1'b1;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) clk_bps <= 1'b0;
	else if(cnt == `BPS_PARA_2) clk_bps <= 1'b1;
	else clk_bps <= 1'b0;

	
endmodule