data/full_repos/permissive/201025648/Verilog/3.59.v
data/verilator_xmls/ebccf647-1ec1-4e31-b360-dfaeb3e76bf4.xml
module edge_detect_gate(
input wire clk,reset,
input wire level,
output wire tick);

reg delay_reg;
always @(posedge clk,posedge reset)
begin
if(reset)
delay_reg<=1'b0;
else
delay_reg<=level;
end
assign tick=~delay_reg&level;
endmodule
module edge_detect_gate(
input wire clk,reset,
input wire level,
output wire tick);


reg delay_reg;
always @(posedge clk,posedge reset)
begin
if(reset)
delay_reg<=1'b0;
else
delay_reg<=level;
end
assign tick=~delay_reg&level;
endmodule