data/full_repos/permissive/175132042/testbench/fw_interface/fw_interface.v
None: at end of input
1: b"%Error: data/full_repos/permissive/175132042/testbench/fw_interface/fw_interface.v:64: Cannot find file containing module: 'fw_interface_wb'\n   fw_interface_wb wb( \n   ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/175132042/testbench/fw_interface,data/full_repos/permissive/175132042/fw_interface_wb\n             data/full_repos/permissive/175132042/testbench/fw_interface,data/full_repos/permissive/175132042/fw_interface_wb.v\n             data/full_repos/permissive/175132042/testbench/fw_interface,data/full_repos/permissive/175132042/fw_interface_wb.sv\n             fw_interface_wb\n             fw_interface_wb.v\n             fw_interface_wb.sv\n             obj_dir/fw_interface_wb\n             obj_dir/fw_interface_wb.v\n             obj_dir/fw_interface_wb.sv\n%Error: data/full_repos/permissive/175132042/testbench/fw_interface/fw_interface.v:96: Cannot find file containing module: 'fw_interface_logic'\n   fw_interface_logic logic_inst( \n   ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module fw_interface (

   wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o, trigger_reg,

   wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i,
   wb_bte_i, wb_cti_i, wb_cyc_i, wb_stb_i, interrupts
   ) ;




   input wire	   wb_clk_i;
   input wire      wb_rst_i;
   
   input wire [31:0] wb_adr_i;
   input wire [31:0] wb_dat_i;
   input wire [3:0]  wb_sel_i;
   input wire        wb_we_i;
   input wire [1:0]  wb_bte_i;
   input wire [2:0]  wb_cti_i;
   input wire        wb_cyc_i;
   input wire        wb_stb_i;
   
   output wire    wb_ack_o;
   output wire    wb_err_o;
   output wire    wb_rty_o;   
   output wire [31:0] wb_dat_o;
   output wire [31:0] trigger_reg;
   



   input wire [31:0]  interrupts;
   





   wire [7:0]           data;
   wire [31:0]          error_reg;
   wire [31:0]          expected_reg;
   wire [5:0]           index;
   wire [31:0]          measured_reg;
   wire                 new_compare;
   wire                 new_error;
   wire                 new_report;
   wire                 new_warning;
   wire [31:0]          report_reg;
   wire [31:0]          warning_reg;
   wire                 write_mem;


   fw_interface_wb wb(

                      .wb_ack_o         (wb_ack_o),
                      .wb_rty_o         (wb_rty_o),
                      .wb_err_o         (wb_err_o),
                      .wb_dat_o         (wb_dat_o[31:0]),
                      .new_report       (new_report),
                      .new_warning      (new_warning),
                      .new_error        (new_error),
                      .new_compare      (new_compare),
                      .report_reg       (report_reg[31:0]),
                      .warning_reg      (warning_reg[31:0]),
                      .error_reg        (error_reg[31:0]),
                      .expected_reg     (expected_reg[31:0]),
                      .measured_reg     (measured_reg[31:0]),
                      .trigger_reg      (trigger_reg[31:0]),
                      .write_mem        (write_mem),
                      .data             (data[7:0]),
                      .index            (index[5:0]),

                      .wb_clk_i         (wb_clk_i),
                      .wb_rst_i         (wb_rst_i),
                      .wb_adr_i         (wb_adr_i[31:0]),
                      .wb_dat_i         (wb_dat_i[31:0]),
                      .wb_sel_i         (wb_sel_i[3:0]),
                      .wb_we_i          (wb_we_i),
                      .wb_bte_i         (wb_bte_i[1:0]),
                      .wb_cti_i         (wb_cti_i[2:0]),
                      .wb_cyc_i         (wb_cyc_i),
                      .wb_stb_i         (wb_stb_i));
   

   fw_interface_logic logic_inst(

                                 .wb_clk_i              (wb_clk_i),
                                 .wb_rst_i              (wb_rst_i),
                                 .new_report            (new_report),
                                 .new_warning           (new_warning),
                                 .new_error             (new_error),
                                 .new_compare           (new_compare),
                                 .report_reg            (report_reg[31:0]),
                                 .warning_reg           (warning_reg[31:0]),
                                 .error_reg             (error_reg[31:0]),
                                 .expected_reg          (expected_reg[31:0]),
                                 .measured_reg          (measured_reg[31:0]),
                                 .index                 (index[5:0]),
                                 .data                  (data[7:0]),
                                 .write_mem             (write_mem));
   
   
endmodule
module fw_interface (

   wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o, trigger_reg,

   wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i,
   wb_bte_i, wb_cti_i, wb_cyc_i, wb_stb_i, interrupts
   ) ;





   input wire	   wb_clk_i;
   input wire      wb_rst_i;
   
   input wire [31:0] wb_adr_i;
   input wire [31:0] wb_dat_i;
   input wire [3:0]  wb_sel_i;
   input wire        wb_we_i;
   input wire [1:0]  wb_bte_i;
   input wire [2:0]  wb_cti_i;
   input wire        wb_cyc_i;
   input wire        wb_stb_i;
   
   output wire    wb_ack_o;
   output wire    wb_err_o;
   output wire    wb_rty_o;   
   output wire [31:0] wb_dat_o;
   output wire [31:0] trigger_reg;
   



   input wire [31:0]  interrupts;
   





   wire [7:0]           data;
   wire [31:0]          error_reg;
   wire [31:0]          expected_reg;
   wire [5:0]           index;
   wire [31:0]          measured_reg;
   wire                 new_compare;
   wire                 new_error;
   wire                 new_report;
   wire                 new_warning;
   wire [31:0]          report_reg;
   wire [31:0]          warning_reg;
   wire                 write_mem;


   fw_interface_wb wb(

                      .wb_ack_o         (wb_ack_o),
                      .wb_rty_o         (wb_rty_o),
                      .wb_err_o         (wb_err_o),
                      .wb_dat_o         (wb_dat_o[31:0]),
                      .new_report       (new_report),
                      .new_warning      (new_warning),
                      .new_error        (new_error),
                      .new_compare      (new_compare),
                      .report_reg       (report_reg[31:0]),
                      .warning_reg      (warning_reg[31:0]),
                      .error_reg        (error_reg[31:0]),
                      .expected_reg     (expected_reg[31:0]),
                      .measured_reg     (measured_reg[31:0]),
                      .trigger_reg      (trigger_reg[31:0]),
                      .write_mem        (write_mem),
                      .data             (data[7:0]),
                      .index            (index[5:0]),

                      .wb_clk_i         (wb_clk_i),
                      .wb_rst_i         (wb_rst_i),
                      .wb_adr_i         (wb_adr_i[31:0]),
                      .wb_dat_i         (wb_dat_i[31:0]),
                      .wb_sel_i         (wb_sel_i[3:0]),
                      .wb_we_i          (wb_we_i),
                      .wb_bte_i         (wb_bte_i[1:0]),
                      .wb_cti_i         (wb_cti_i[2:0]),
                      .wb_cyc_i         (wb_cyc_i),
                      .wb_stb_i         (wb_stb_i));
   

   fw_interface_logic logic_inst(

                                 .wb_clk_i              (wb_clk_i),
                                 .wb_rst_i              (wb_rst_i),
                                 .new_report            (new_report),
                                 .new_warning           (new_warning),
                                 .new_error             (new_error),
                                 .new_compare           (new_compare),
                                 .report_reg            (report_reg[31:0]),
                                 .warning_reg           (warning_reg[31:0]),
                                 .error_reg             (error_reg[31:0]),
                                 .expected_reg          (expected_reg[31:0]),
                                 .measured_reg          (measured_reg[31:0]),
                                 .index                 (index[5:0]),
                                 .data                  (data[7:0]),
                                 .write_mem             (write_mem));
   
   
endmodule