data/full_repos/permissive/201666736/src_v/spi_lite.v
1: b'%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:35: Cannot find include file: spi_lite_defs.v\n`include "spi_lite_defs.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/201666736/src_v,data/full_repos/permissive/201666736/spi_lite_defs.v\n             data/full_repos/permissive/201666736/src_v,data/full_repos/permissive/201666736/spi_lite_defs.v.v\n             data/full_repos/permissive/201666736/src_v,data/full_repos/permissive/201666736/spi_lite_defs.v.sv\n             spi_lite_defs.v\n             spi_lite_defs.v.v\n             spi_lite_defs.v.sv\n             obj_dir/spi_lite_defs.v\n             obj_dir/spi_lite_defs.v.v\n             obj_dir/spi_lite_defs.v.sv\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:154: Define or directive not defined: \'`SPI_DGIER\'\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_DGIER))\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:154: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_DGIER))\n                                                    ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:164: Number is missing value digits: 1\'d\n    spi_dgier_gie_q <= 1\'d`SPI_DGIER_GIE_DEFAULT;\n                       ^~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:164: Define or directive not defined: \'`SPI_DGIER_GIE_DEFAULT\'\n    spi_dgier_gie_q <= 1\'d`SPI_DGIER_GIE_DEFAULT;\n                          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:165: Define or directive not defined: \'`SPI_DGIER\'\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_DGIER))\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:165: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_DGIER))\n                                                    ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:166: Define or directive not defined: \'`SPI_DGIER_GIE_R\'\n    spi_dgier_gie_q <= cfg_wdata_i[`SPI_DGIER_GIE_R];\n                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:179: Define or directive not defined: \'`SPI_IPISR\'\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_IPISR))\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:179: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_IPISR))\n                                                    ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:185: Define or directive not defined: \'`SPI_IPISR_TX_EMPTY_R\'\nwire        spi_ipisr_tx_empty_out_w = wr_data_q[`SPI_IPISR_TX_EMPTY_R];\n                                                 ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:185: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire        spi_ipisr_tx_empty_out_w = wr_data_q[`SPI_IPISR_TX_EMPTY_R];\n                                                                      ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:196: Define or directive not defined: \'`SPI_IPIER\'\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_IPIER))\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:196: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_IPIER))\n                                                    ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:206: Number is missing value digits: 1\'d\n    spi_ipier_tx_empty_q <= 1\'d`SPI_IPIER_TX_EMPTY_DEFAULT;\n                            ^~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:206: Define or directive not defined: \'`SPI_IPIER_TX_EMPTY_DEFAULT\'\n    spi_ipier_tx_empty_q <= 1\'d`SPI_IPIER_TX_EMPTY_DEFAULT;\n                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:207: Define or directive not defined: \'`SPI_IPIER\'\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_IPIER))\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:207: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_IPIER))\n                                                    ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:208: Define or directive not defined: \'`SPI_IPIER_TX_EMPTY_R\'\n    spi_ipier_tx_empty_q <= cfg_wdata_i[`SPI_IPIER_TX_EMPTY_R];\n                                        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:221: Define or directive not defined: \'`SPI_SRR\'\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_SRR))\n                                          ^~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:221: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_SRR))\n                                                  ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:231: Number is missing value digits: 32\'d\n    spi_srr_reset_q <= 32\'d`SPI_SRR_RESET_DEFAULT;\n                       ^~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:231: Define or directive not defined: \'`SPI_SRR_RESET_DEFAULT\'\n    spi_srr_reset_q <= 32\'d`SPI_SRR_RESET_DEFAULT;\n                           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:232: Define or directive not defined: \'`SPI_SRR\'\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_SRR))\n                                          ^~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:232: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_SRR))\n                                                  ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:233: Define or directive not defined: \'`SPI_SRR_RESET_R\'\n    spi_srr_reset_q <= cfg_wdata_i[`SPI_SRR_RESET_R];\n                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:235: Number is missing value digits: 32\'d\n    spi_srr_reset_q <= 32\'d`SPI_SRR_RESET_DEFAULT;\n                       ^~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:235: Define or directive not defined: \'`SPI_SRR_RESET_DEFAULT\'\n    spi_srr_reset_q <= 32\'d`SPI_SRR_RESET_DEFAULT;\n                           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:248: Define or directive not defined: \'`SPI_CR\'\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_CR))\n                                          ^~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:248: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_CR))\n                                                 ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:258: Number is missing value digits: 1\'d\n    spi_cr_loop_q <= 1\'d`SPI_CR_LOOP_DEFAULT;\n                     ^~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:258: Define or directive not defined: \'`SPI_CR_LOOP_DEFAULT\'\n    spi_cr_loop_q <= 1\'d`SPI_CR_LOOP_DEFAULT;\n                        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:259: Define or directive not defined: \'`SPI_CR\'\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_CR))\n                                          ^~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:259: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_CR))\n                                                 ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:260: Define or directive not defined: \'`SPI_CR_LOOP_R\'\n    spi_cr_loop_q <= cfg_wdata_i[`SPI_CR_LOOP_R];\n                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:270: Number is missing value digits: 1\'d\n    spi_cr_spe_q <= 1\'d`SPI_CR_SPE_DEFAULT;\n                    ^~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:270: Define or directive not defined: \'`SPI_CR_SPE_DEFAULT\'\n    spi_cr_spe_q <= 1\'d`SPI_CR_SPE_DEFAULT;\n                       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:271: Define or directive not defined: \'`SPI_CR\'\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_CR))\n                                          ^~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:271: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_CR))\n                                                 ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:272: Define or directive not defined: \'`SPI_CR_SPE_R\'\n    spi_cr_spe_q <= cfg_wdata_i[`SPI_CR_SPE_R];\n                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:282: Number is missing value digits: 1\'d\n    spi_cr_master_q <= 1\'d`SPI_CR_MASTER_DEFAULT;\n                       ^~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:282: Define or directive not defined: \'`SPI_CR_MASTER_DEFAULT\'\n    spi_cr_master_q <= 1\'d`SPI_CR_MASTER_DEFAULT;\n                          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:283: Define or directive not defined: \'`SPI_CR\'\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_CR))\n                                          ^~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:283: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_CR))\n                                                 ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:284: Define or directive not defined: \'`SPI_CR_MASTER_R\'\n    spi_cr_master_q <= cfg_wdata_i[`SPI_CR_MASTER_R];\n                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:294: Number is missing value digits: 1\'d\n    spi_cr_cpol_q <= 1\'d`SPI_CR_CPOL_DEFAULT;\n                     ^~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:294: Define or directive not defined: \'`SPI_CR_CPOL_DEFAULT\'\n    spi_cr_cpol_q <= 1\'d`SPI_CR_CPOL_DEFAULT;\n                        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:295: Define or directive not defined: \'`SPI_CR\'\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_CR))\n                                          ^~~~~~~\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:295: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nelse if (write_en_w && (wr_addr_w[7:0] == `SPI_CR))\n                                                 ^\n%Error: data/full_repos/permissive/201666736/src_v/spi_lite.v:296: Define or directive not defined: \'`SPI_CR_CPOL_R\'\n    spi_cr_cpol_q <= cfg_wdata_i[`SPI_CR_CPOL_R];\n                                 ^~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module spi_lite_fifo



#(
    parameter WIDTH   = 8,
    parameter DEPTH   = 4,
    parameter ADDR_W  = 2
)



(

     input               clk_i
    ,input               rst_i
    ,input  [WIDTH-1:0]  data_in_i
    ,input               push_i
    ,input               pop_i
    ,input               flush_i


    ,output [WIDTH-1:0]  data_out_o
    ,output              accept_o
    ,output              valid_o
);




localparam COUNT_W = ADDR_W + 1;




reg [WIDTH-1:0]   ram_q[DEPTH-1:0];
reg [ADDR_W-1:0]  rd_ptr_q;
reg [ADDR_W-1:0]  wr_ptr_q;
reg [COUNT_W-1:0] count_q;




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    count_q   <= {(COUNT_W) {1'b0}};
    rd_ptr_q  <= {(ADDR_W) {1'b0}};
    wr_ptr_q  <= {(ADDR_W) {1'b0}};
end
else if (flush_i)
begin
    count_q   <= {(COUNT_W) {1'b0}};
    rd_ptr_q  <= {(ADDR_W) {1'b0}};
    wr_ptr_q  <= {(ADDR_W) {1'b0}};
end
else
begin

    if (push_i & accept_o)
    begin
        ram_q[wr_ptr_q] <= data_in_i;
        wr_ptr_q        <= wr_ptr_q + 1;
    end


    if (pop_i & valid_o)
        rd_ptr_q      <= rd_ptr_q + 1;


    if ((push_i & accept_o) & ~(pop_i & valid_o))
        count_q <= count_q + 1;

    else if (~(push_i & accept_o) & (pop_i & valid_o))
        count_q <= count_q - 1;
end





assign valid_o       = (count_q != 0);
assign accept_o      = (count_q != DEPTH);


assign data_out_o    = ram_q[rd_ptr_q];



endmodule
module spi_lite_fifo



#(
    parameter WIDTH   = 8,
    parameter DEPTH   = 4,
    parameter ADDR_W  = 2
)



(

     input               clk_i
    ,input               rst_i
    ,input  [WIDTH-1:0]  data_in_i
    ,input               push_i
    ,input               pop_i
    ,input               flush_i


    ,output [WIDTH-1:0]  data_out_o
    ,output              accept_o
    ,output              valid_o
);





localparam COUNT_W = ADDR_W + 1;




reg [WIDTH-1:0]   ram_q[DEPTH-1:0];
reg [ADDR_W-1:0]  rd_ptr_q;
reg [ADDR_W-1:0]  wr_ptr_q;
reg [COUNT_W-1:0] count_q;




always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    count_q   <= {(COUNT_W) {1'b0}};
    rd_ptr_q  <= {(ADDR_W) {1'b0}};
    wr_ptr_q  <= {(ADDR_W) {1'b0}};
end
else if (flush_i)
begin
    count_q   <= {(COUNT_W) {1'b0}};
    rd_ptr_q  <= {(ADDR_W) {1'b0}};
    wr_ptr_q  <= {(ADDR_W) {1'b0}};
end
else
begin

    if (push_i & accept_o)
    begin
        ram_q[wr_ptr_q] <= data_in_i;
        wr_ptr_q        <= wr_ptr_q + 1;
    end


    if (pop_i & valid_o)
        rd_ptr_q      <= rd_ptr_q + 1;


    if ((push_i & accept_o) & ~(pop_i & valid_o))
        count_q <= count_q + 1;

    else if (~(push_i & accept_o) & (pop_i & valid_o))
        count_q <= count_q - 1;
end





assign valid_o       = (count_q != 0);
assign accept_o      = (count_q != DEPTH);


assign data_out_o    = ram_q[rd_ptr_q];



endmodule