data/full_repos/permissive/143278/ivltests/escape3.v
None: at end of input
data/verilator_xmls/32b38c6c-0cb5-4456-a92f-2b5fbb4df490.xml
module top;

   reg \cpu3 ;

   initial begin
      cpu3 = 1;
      $display("cpu3 == %b", \cpu3 );
      if (top.\cpu3  !== cpu3) begin
	 $display("FAILED -- top.\\cpu3 !== cpu3");
	 $finish;
      end

      if (\top .cpu3  !== \cpu3 ) begin
	 $display("FAILED -- \\top .cpu3 !== cpu3");
	 $finish;
      end

      if (top.\cpu3  !== 1) begin
	 $display("FAILED -- top.\\cpu3 !== 1");
	 $finish;
      end

      $display("PASSED");
   end
endmodule
module top;


   reg \cpu3 ;

   initial begin
      cpu3 = 1;
      $display("cpu3 == %b", \cpu3 );
      if (top.\cpu3  !== cpu3) begin
	 $display("FAILED -- top.\\cpu3 !== cpu3");
	 $finish;
      end

      if (\top .cpu3  !== \cpu3 ) begin
	 $display("FAILED -- \\top .cpu3 !== cpu3");
	 $finish;
      end

      if (top.\cpu3  !== 1) begin
	 $display("FAILED -- top.\\cpu3 !== 1");
	 $finish;
      end

      $display("PASSED");
   end
endmodule