data/full_repos/permissive/152883307/Project/ADC_SCALE_DISPLAY.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152883307/Project/ADC_SCALE_DISPLAY.v:27: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 19 bits.\n                                                                                   : ... In instance ADC_SCALE_DISPLAY\n    dig_0 =  bindata*500000/4095 %10;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/152883307/Project/ADC_SCALE_DISPLAY.v:28: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 19 bits.\n                                                                                   : ... In instance ADC_SCALE_DISPLAY\n            dig_1 = ( bindata*500000/4095 / 10 ) % 10;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152883307/Project/ADC_SCALE_DISPLAY.v:29: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 19 bits.\n                                                                                   : ... In instance ADC_SCALE_DISPLAY\n            dig_2 = ( bindata*500000/4095 / 100 ) % 10;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152883307/Project/ADC_SCALE_DISPLAY.v:30: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 19 bits.\n                                                                                   : ... In instance ADC_SCALE_DISPLAY\n            dig_3 = ( bindata*500000/4095 / 1000 ) % 10;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152883307/Project/ADC_SCALE_DISPLAY.v:31: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 19 bits.\n                                                                                   : ... In instance ADC_SCALE_DISPLAY\n            dig_4 = ( bindata*500000/4095 / 10000 ) % 10;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152883307/Project/ADC_SCALE_DISPLAY.v:32: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 19 bits.\n                                                                                   : ... In instance ADC_SCALE_DISPLAY\n    dig_5 = ( bindata*500000/4095 / 100000 ) % 10;  \n          ^\n%Error: Exiting due to 6 warning(s)\n'
module ADC_SCALE_DISPLAY(
	input 				Clock_in, 
	input 				reset_n, 
	input 		[11:0]bindata, 
	output reg 	[3:0] dig_5,
	output reg 	[3:0] dig_4, 
	output reg 	[3:0] dig_3, 
	output reg 	[3:0] dig_2, 
	output reg 	[3:0] dig_1,
	output reg 	[3:0] dig_0
);

always@(negedge reset_n or negedge Clock_in)
begin
    if (reset_n == 0)
        begin
            dig_5 = 0;
            dig_4 = 0;
            dig_3 = 0;
            dig_2 = 0;
            dig_1 = 0;
            dig_0 = 0;
        end
    else
        begin

				dig_0 =  bindata*500000/4095 %10;
            dig_1 = ( bindata*500000/4095 / 10 ) % 10;
            dig_2 = ( bindata*500000/4095 / 100 ) % 10;
            dig_3 = ( bindata*500000/4095 / 1000 ) % 10;
            dig_4 = ( bindata*500000/4095 / 10000 ) % 10;
				dig_5 = ( bindata*500000/4095 / 100000 ) % 10;	 

        end
end

endmodule
module ADC_SCALE_DISPLAY(
	input 				Clock_in, 
	input 				reset_n, 
	input 		[11:0]bindata, 
	output reg 	[3:0] dig_5,
	output reg 	[3:0] dig_4, 
	output reg 	[3:0] dig_3, 
	output reg 	[3:0] dig_2, 
	output reg 	[3:0] dig_1,
	output reg 	[3:0] dig_0
);


always@(negedge reset_n or negedge Clock_in)
begin
    if (reset_n == 0)
        begin
            dig_5 = 0;
            dig_4 = 0;
            dig_3 = 0;
            dig_2 = 0;
            dig_1 = 0;
            dig_0 = 0;
        end
    else
        begin

				dig_0 =  bindata*500000/4095 %10;
            dig_1 = ( bindata*500000/4095 / 10 ) % 10;
            dig_2 = ( bindata*500000/4095 / 100 ) % 10;
            dig_3 = ( bindata*500000/4095 / 1000 ) % 10;
            dig_4 = ( bindata*500000/4095 / 10000 ) % 10;
				dig_5 = ( bindata*500000/4095 / 100000 ) % 10;	 

        end
end

endmodule