data/full_repos/permissive/123304708/src/control/hazard_detection.v
1: b'%Warning-WIDTH: data/full_repos/permissive/123304708/src/control/hazard_detection.v:14: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'rt\' generates 5 bits.\n                                                                                      : ... In instance hazard_detection\n    if(MemRead_ex && (rf_wa == rt || rf_wa == rs))  \n                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/123304708/src/control/hazard_detection.v:14: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'rs\' generates 5 bits.\n                                                                                      : ... In instance hazard_detection\n    if(MemRead_ex && (rf_wa == rt || rf_wa == rs))  \n                                           ^~\n%Error: Exiting due to 2 warning(s)\n'
module hazard_detection(
  input [4:0] rs,
  input [4:0] rt,
  input [31:0] rf_wa,
  input MemRead_ex, 
  input RegWrite_ex,
  
  output reg PC_IFWrite,
  output reg stall
  );

  always@(*)
  begin
    if(MemRead_ex && (rf_wa == rt || rf_wa == rs))
    begin
      stall = 1;
      PC_IFWrite = 0;
    end
    else
    begin
      stall = 0;
      PC_IFWrite = 1;
    end
  end
  
endmodule
module hazard_detection(
  input [4:0] rs,
  input [4:0] rt,
  input [31:0] rf_wa,
  input MemRead_ex, 
  input RegWrite_ex,
  
  output reg PC_IFWrite,
  output reg stall
  );


  always@(*)
  begin
    if(MemRead_ex && (rf_wa == rt || rf_wa == rs))
    begin
      stall = 1;
      PC_IFWrite = 0;
    end
    else
    begin
      stall = 0;
      PC_IFWrite = 1;
    end
  end
  
endmodule