data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v
 line:1 column:1: Illegal character '\x00'
1: b'%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:570: Operator SUB expects 7 bits on the RHS, but RHS\'s VARREF \'master_readdatavalid\' generates 1 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_discards <= pending_discards + pending_reads - master_readdatavalid;\n                                                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:572: Operator COND expects 32 or 7 bits on the Conditional True, but Conditional True\'s VARREF \'master_burstcount\' generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_reads <= pending_reads + (avm_read_accepted ? master_burstcount : 0) - keep_read;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:572: Operator SUB expects 32 or 7 bits on the RHS, but RHS\'s VARREF \'keep_read\' generates 1 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_reads <= pending_reads + (avm_read_accepted ? master_burstcount : 0) - keep_read;\n                                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:573: Operator NOT expects 7 bits on the LHS, but LHS\'s VARREF \'finished_discard\' generates 1 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_discards <= pending_discards - (~finished_discard & master_readdatavalid);\n                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:573: Operator AND expects 7 bits on the RHS, but RHS\'s VARREF \'master_readdatavalid\' generates 1 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_burst_master\n                pending_discards <= pending_discards - (~finished_discard & master_readdatavalid);\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:418: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign user_read_addr_word   = (user_read_addr   >> MBYTE_SELECT_BITS);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:419: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign user_read_addr_r_word = (user_read_addr_r >> MBYTE_SELECT_BITS);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:420: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign avm_read_addr_word    = (avm_read_addr    >> MBYTE_SELECT_BITS);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:421: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign wr_addr_word          = (wr_addr          >> MBYTE_SELECT_BITS);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:422: Operator AND expects 27 bits on the RHS, but RHS\'s REPLICATE generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign wr_fifo_addr = wr_addr_word & {LOG2_DEPTH{1\'b1}};\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:422: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s AND generates 27 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign wr_fifo_addr = wr_addr_word & {LOG2_DEPTH{1\'b1}};\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:425: Operator AND expects 27 bits on the RHS, but RHS\'s REPLICATE generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign rd_fifo_addr = wait_for_read_int_r ? (user_read_addr_r_word & {LOG2_DEPTH{1\'b1}}) : \n                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:426: Operator AND expects 27 bits on the RHS, but RHS\'s REPLICATE generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                                                (user_read_addr_word   & {LOG2_DEPTH{1\'b1}}) ;\n                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:425: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s COND generates 27 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign rd_fifo_addr = wait_for_read_int_r ? (user_read_addr_r_word & {LOG2_DEPTH{1\'b1}}) : \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:428: Operator ASSIGNW expects 27 bits on the Assign RHS, but Assign RHS\'s SUB generates 28 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n    assign fifo_addr_diff = {1\'b0, avm_read_addr_word} - {1\'b0, user_read_addr_r_word};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:490: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 32 or 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size    <= (first_burst_boundary_word_address & 1) ? 1 : (MAXBURSTCOUNT - first_burst_boundary_word_address);\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:490: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'first_burst_boundary_word_address\' generates 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size    <= (first_burst_boundary_word_address & 1) ? 1 : (MAXBURSTCOUNT - first_burst_boundary_word_address);\n                                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:490: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size    <= (first_burst_boundary_word_address & 1) ? 1 : (MAXBURSTCOUNT - first_burst_boundary_word_address);\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:493: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'avm_burst_size\' generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_read_addr  <= (avm_read_addr + (avm_read_success ? (avm_burst_size << MBYTE_SELECT_BITS) : 0));\n                                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:494: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'avm_burst_boundary_word_address\' generates 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size <= avm_read_success_r ? (MAXBURSTCOUNT - avm_burst_boundary_word_address) : avm_burst_size;  \n                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:494: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'avm_burst_size\' generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size <= avm_read_success_r ? (MAXBURSTCOUNT - avm_burst_boundary_word_address) : avm_burst_size;  \n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:494: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_burst_size <= avm_read_success_r ? (MAXBURSTCOUNT - avm_burst_boundary_word_address) : avm_burst_size;  \n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:499: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'num_words_in_fifo\' generates 6 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n                avm_read <= (avm_ctrl_state == 2) & !empty & (fifo_addr_diff_overflow | (num_words_in_fifo < (DEPTH - MAXBURSTCOUNT)));  \n                                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:513: Operator AND expects 32 bits on the RHS, but RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n            assign first_burst_boundary_word_address = (user_read_addr_r >> MBYTE_SELECT_BITS) & {(BURSTCOUNT_WIDTH - 1){1\'b1}};\n                                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:513: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n            assign first_burst_boundary_word_address = (user_read_addr_r >> MBYTE_SELECT_BITS) & {(BURSTCOUNT_WIDTH - 1){1\'b1}};\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:514: Operator AND expects 32 bits on the RHS, but RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n            assign avm_burst_boundary_word_address   = (avm_read_addr >> MBYTE_SELECT_BITS)    & {(BURSTCOUNT_WIDTH - 1){1\'b1}};\n                                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:514: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                                                                                                   : ... In instance lsu_streaming_prefetch_read.u_fifo\n            assign avm_burst_boundary_word_address   = (avm_read_addr >> MBYTE_SELECT_BITS)    & {(BURSTCOUNT_WIDTH - 1){1\'b1}};\n                                                     ^\n%Error: data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules/lsu_streaming_prefetch.v:83: Cannot find file containing module: \'acl_data_fifo\'\nacl_data_fifo #(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules,data/full_repos/permissive/205229557/acl_data_fifo\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules,data/full_repos/permissive/205229557/acl_data_fifo.v\n             data/full_repos/permissive/205229557/new/lab2/airplane_CL/aocl_airplane/device/airplane_cl/system/synthesis/submodules,data/full_repos/permissive/205229557/acl_data_fifo.sv\n             acl_data_fifo\n             acl_data_fifo.v\n             acl_data_fifo.sv\n             obj_dir/acl_data_fifo\n             obj_dir/acl_data_fifo.v\n             obj_dir/acl_data_fifo.sv\n%Error: Exiting due to 1 error(s), 27 warning(s)\n'
module lsu_streaming_prefetch_read 
(
   clk, reset, flush, o_stall, i_valid, i_address, i_stall, i_nop, o_valid, o_readdata, 
   o_active,
   avm_address, avm_burstcount, avm_read, 
   avm_readdata, avm_waitrequest, avm_byteenable, avm_readdatavalid
);


parameter AWIDTH=32;
parameter WIDTH_BYTES=32;
parameter MWIDTH_BYTES=32;
parameter ALIGNMENT_ABITS=6;
parameter BURSTCOUNT_WIDTH=6;
parameter KERNEL_SIDE_MEM_LATENCY=1;
parameter MEMORY_SIDE_MEM_LATENCY=1;


localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam MBYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam BYTE_SELECT_BITS=$clog2(WIDTH_BYTES);
localparam MAXBURSTCOUNT=2**(BURSTCOUNT_WIDTH-1);








localparam _FIFO_DEPTH = MAXBURSTCOUNT + 10 + ((MEMORY_SIDE_MEM_LATENCY * WIDTH_BYTES + MWIDTH_BYTES - 1) / MWIDTH_BYTES);

localparam FIFO_DEPTH = 2**$clog2(_FIFO_DEPTH);

localparam FIFO_DEPTH_LOG2=$clog2(FIFO_DEPTH);




input clk;
input reset;
input flush;


output o_stall;
input i_valid;
input i_nop;
input [AWIDTH-1:0] i_address;


input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
output o_active;


output [AWIDTH-1:0] avm_address;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
output avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_readdatavalid;


wire f_avm_read;
wire f_avm_waitrequest;
wire [AWIDTH-1:0] f_avm_address;
wire [BURSTCOUNT_WIDTH-1:0] f_avm_burstcount;

acl_data_fifo #(
  .DATA_WIDTH(AWIDTH+BURSTCOUNT_WIDTH),
  .DEPTH(2),
  .IMPL("ll_reg")
) avm_buffer (
  .clock(clk),
  .resetn(!reset),
  .data_in( {f_avm_address,f_avm_burstcount} ),
  .valid_in( f_avm_read ),
  .data_out( {avm_address,avm_burstcount} ),
  .valid_out( avm_read ),
  .stall_in( avm_waitrequest ),
  .stall_out( f_avm_waitrequest )
);




reg              i_valid_r;
reg [AWIDTH-1:0] i_address_r;

reg              i_valid_rr;
reg [AWIDTH-1:0] i_address_rr;


reg addr_before_fifo;
reg addr_after_fifo;
reg empty_r;
wire flush_on_fifo_miss;
reg flush_on_fifo_miss_r;
wire internal_flush;

wire [AWIDTH - 1 : 0] i_mem_addr_r;
wire [AWIDTH - 1 : 0] i_mem_addr_rr;


wire [AWIDTH - 1 : 0] fifo_high_addr;
wire                  empty;
wire  [MWIDTH -1 : 0] user_data_out;
wire                  wait_for_read;


wire          [AWIDTH - 1 : 0] fifo2master_read_addr;
wire                           fifo2master_read;
wire [BURSTCOUNT_WIDTH -1 : 0] fifo2master_burst_size;
wire                           fifo2master_data_valid;
wire           [MWIDTH -1 : 0] fifo2master_data;
wire                           fifo2master_ready;





always @(posedge clk or posedge reset) begin
    if (reset) begin
        i_valid_r          <= 1'b0;
        i_address_r        <= 0;
        i_valid_rr         <= 1'b0;
        i_address_rr       <= 0;
    end else begin
        if (flush) begin
            i_valid_r   <= 1'b0;
            i_valid_rr  <= 1'b0;
        end else if (!o_stall) begin

            i_valid_r   <= i_valid;


            i_address_r <= ((i_address >> ALIGNMENT_ABITS) << ALIGNMENT_ABITS);


            i_valid_rr   <= i_valid_r;
            i_address_rr <= i_valid_r ? i_address_r : i_address_rr;
        end

    end
end







assign i_mem_addr_r  = ((i_address_r  >> MBYTE_SELECT_BITS) << MBYTE_SELECT_BITS);
assign i_mem_addr_rr = ((i_address_rr >> MBYTE_SELECT_BITS) << MBYTE_SELECT_BITS);

always @(posedge clk or posedge reset) begin
    if (reset) begin

        addr_before_fifo <= 1'b0;
        addr_after_fifo  <= 1'b0;

        empty_r <= 1;
        flush_on_fifo_miss_r <= 0;
    end else begin
           
        if (flush) begin
            addr_before_fifo <= 1'b0;
            addr_after_fifo  <= 1'b0;

            empty_r <= 1;
        end else if (!o_stall) begin

            addr_before_fifo <= (i_mem_addr_rr > i_mem_addr_r);
            addr_after_fifo  <= (fifo_high_addr <= i_mem_addr_r);

            empty_r <= empty;
        end


        flush_on_fifo_miss_r <= flush ? 0 : flush_on_fifo_miss & o_stall;

    end
end


assign flush_on_fifo_miss = (addr_before_fifo | addr_after_fifo | empty_r) & !empty;
assign internal_flush = (flush_on_fifo_miss & ~flush_on_fifo_miss_r);




lsu_streaming_prefetch_fifo #(
        .DEPTH             (FIFO_DEPTH       ),
        .LOG2_DEPTH        (FIFO_DEPTH_LOG2  ),
        .MWIDTH            (MWIDTH           ),
        .AWIDTH            (AWIDTH           ),
        .MBYTE_SELECT_BITS (MBYTE_SELECT_BITS),
        .MAXBURSTCOUNT     (MAXBURSTCOUNT    ),
        .BURSTCOUNT_WIDTH  (BURSTCOUNT_WIDTH )
    ) u_fifo (
        .clk   (clk),
        .reset (reset),
        .flush_external (flush),
        .flush_internal (internal_flush),


        .user_read_addr  (i_address_r          ),
        .user_valid      (i_valid_r & !flush   ),
        .user_data_out   (user_data_out        ),

        .user_read_addr_r (i_address_rr        ),
        .user_valid_r     (i_valid_rr & ~flush ),
        .wait_for_read    (wait_for_read       ),

        .i_stall (i_stall),


        .empty          (empty         ),
        .fifo_high_addr (fifo_high_addr),


        .avm_read_addr  (fifo2master_read_addr ),
        .avm_read       (fifo2master_read      ),
        .avm_burst_size (fifo2master_burst_size),
        .avm_data_valid (fifo2master_data_valid),
        .avm_data       (fifo2master_data      ),
        .avm_ready      (fifo2master_ready     )
    ); 




lsu_streaming_prefetch_avalon_bust_master #(
        .AWIDTH           (AWIDTH          ),
        .MWIDTH           (MWIDTH          ),
        .MWIDTH_BYTES     (MWIDTH_BYTES    ),
        .BURSTCOUNT_WIDTH (BURSTCOUNT_WIDTH),
        .FIFO_DEPTH_LOG2  (FIFO_DEPTH_LOG2 )
    ) u_burst_master (
        .clk    (clk),
        .reset  (reset),
        .flush  (flush | internal_flush),
        .active (o_active),


        .fifo_read_addr  (fifo2master_read_addr ),
        .fifo_read       (fifo2master_read      ),
        .fifo_burst_size (fifo2master_burst_size),
        .fifo_data_valid (fifo2master_data_valid),
        .fifo_data       (fifo2master_data      ),
        .ready           (fifo2master_ready     ),


        .master_address       (f_avm_address    ),
        .master_read          (f_avm_read       ),
        .master_byteenable    (avm_byteenable   ),
        .master_readdata      (avm_readdata     ),
        .master_readdatavalid (avm_readdatavalid),
        .master_burstcount    (f_avm_burstcount ),
        .master_waitrequest   (f_avm_waitrequest)
    );





assign o_stall = (i_stall | internal_flush | (wait_for_read & i_valid_rr));

assign o_valid = i_valid_rr & !(internal_flush | wait_for_read);


generate
    if(MBYTE_SELECT_BITS != BYTE_SELECT_BITS) begin
        assign o_readdata = user_data_out[i_address_rr[MBYTE_SELECT_BITS-1:BYTE_SELECT_BITS] * WIDTH +: WIDTH];
    end else begin

        assign o_readdata = user_data_out;
    end
endgenerate


endmodule
module lsu_streaming_prefetch_read 
(
   clk, reset, flush, o_stall, i_valid, i_address, i_stall, i_nop, o_valid, o_readdata, 
   o_active,
   avm_address, avm_burstcount, avm_read, 
   avm_readdata, avm_waitrequest, avm_byteenable, avm_readdatavalid
);



parameter AWIDTH=32;
parameter WIDTH_BYTES=32;
parameter MWIDTH_BYTES=32;
parameter ALIGNMENT_ABITS=6;
parameter BURSTCOUNT_WIDTH=6;
parameter KERNEL_SIDE_MEM_LATENCY=1;
parameter MEMORY_SIDE_MEM_LATENCY=1;


localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam MBYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam BYTE_SELECT_BITS=$clog2(WIDTH_BYTES);
localparam MAXBURSTCOUNT=2**(BURSTCOUNT_WIDTH-1);








localparam _FIFO_DEPTH = MAXBURSTCOUNT + 10 + ((MEMORY_SIDE_MEM_LATENCY * WIDTH_BYTES + MWIDTH_BYTES - 1) / MWIDTH_BYTES);

localparam FIFO_DEPTH = 2**$clog2(_FIFO_DEPTH);

localparam FIFO_DEPTH_LOG2=$clog2(FIFO_DEPTH);




input clk;
input reset;
input flush;


output o_stall;
input i_valid;
input i_nop;
input [AWIDTH-1:0] i_address;


input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
output o_active;


output [AWIDTH-1:0] avm_address;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
output avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_readdatavalid;


wire f_avm_read;
wire f_avm_waitrequest;
wire [AWIDTH-1:0] f_avm_address;
wire [BURSTCOUNT_WIDTH-1:0] f_avm_burstcount;

acl_data_fifo #(
  .DATA_WIDTH(AWIDTH+BURSTCOUNT_WIDTH),
  .DEPTH(2),
  .IMPL("ll_reg")
) avm_buffer (
  .clock(clk),
  .resetn(!reset),
  .data_in( {f_avm_address,f_avm_burstcount} ),
  .valid_in( f_avm_read ),
  .data_out( {avm_address,avm_burstcount} ),
  .valid_out( avm_read ),
  .stall_in( avm_waitrequest ),
  .stall_out( f_avm_waitrequest )
);




reg              i_valid_r;
reg [AWIDTH-1:0] i_address_r;

reg              i_valid_rr;
reg [AWIDTH-1:0] i_address_rr;


reg addr_before_fifo;
reg addr_after_fifo;
reg empty_r;
wire flush_on_fifo_miss;
reg flush_on_fifo_miss_r;
wire internal_flush;

wire [AWIDTH - 1 : 0] i_mem_addr_r;
wire [AWIDTH - 1 : 0] i_mem_addr_rr;


wire [AWIDTH - 1 : 0] fifo_high_addr;
wire                  empty;
wire  [MWIDTH -1 : 0] user_data_out;
wire                  wait_for_read;


wire          [AWIDTH - 1 : 0] fifo2master_read_addr;
wire                           fifo2master_read;
wire [BURSTCOUNT_WIDTH -1 : 0] fifo2master_burst_size;
wire                           fifo2master_data_valid;
wire           [MWIDTH -1 : 0] fifo2master_data;
wire                           fifo2master_ready;





always @(posedge clk or posedge reset) begin
    if (reset) begin
        i_valid_r          <= 1'b0;
        i_address_r        <= 0;
        i_valid_rr         <= 1'b0;
        i_address_rr       <= 0;
    end else begin
        if (flush) begin
            i_valid_r   <= 1'b0;
            i_valid_rr  <= 1'b0;
        end else if (!o_stall) begin

            i_valid_r   <= i_valid;


            i_address_r <= ((i_address >> ALIGNMENT_ABITS) << ALIGNMENT_ABITS);


            i_valid_rr   <= i_valid_r;
            i_address_rr <= i_valid_r ? i_address_r : i_address_rr;
        end

    end
end







assign i_mem_addr_r  = ((i_address_r  >> MBYTE_SELECT_BITS) << MBYTE_SELECT_BITS);
assign i_mem_addr_rr = ((i_address_rr >> MBYTE_SELECT_BITS) << MBYTE_SELECT_BITS);

always @(posedge clk or posedge reset) begin
    if (reset) begin

        addr_before_fifo <= 1'b0;
        addr_after_fifo  <= 1'b0;

        empty_r <= 1;
        flush_on_fifo_miss_r <= 0;
    end else begin
           
        if (flush) begin
            addr_before_fifo <= 1'b0;
            addr_after_fifo  <= 1'b0;

            empty_r <= 1;
        end else if (!o_stall) begin

            addr_before_fifo <= (i_mem_addr_rr > i_mem_addr_r);
            addr_after_fifo  <= (fifo_high_addr <= i_mem_addr_r);

            empty_r <= empty;
        end


        flush_on_fifo_miss_r <= flush ? 0 : flush_on_fifo_miss & o_stall;

    end
end


assign flush_on_fifo_miss = (addr_before_fifo | addr_after_fifo | empty_r) & !empty;
assign internal_flush = (flush_on_fifo_miss & ~flush_on_fifo_miss_r);




lsu_streaming_prefetch_fifo #(
        .DEPTH             (FIFO_DEPTH       ),
        .LOG2_DEPTH        (FIFO_DEPTH_LOG2  ),
        .MWIDTH            (MWIDTH           ),
        .AWIDTH            (AWIDTH           ),
        .MBYTE_SELECT_BITS (MBYTE_SELECT_BITS),
        .MAXBURSTCOUNT     (MAXBURSTCOUNT    ),
        .BURSTCOUNT_WIDTH  (BURSTCOUNT_WIDTH )
    ) u_fifo (
        .clk   (clk),
        .reset (reset),
        .flush_external (flush),
        .flush_internal (internal_flush),


        .user_read_addr  (i_address_r          ),
        .user_valid      (i_valid_r & !flush   ),
        .user_data_out   (user_data_out        ),

        .user_read_addr_r (i_address_rr        ),
        .user_valid_r     (i_valid_rr & ~flush ),
        .wait_for_read    (wait_for_read       ),

        .i_stall (i_stall),


        .empty          (empty         ),
        .fifo_high_addr (fifo_high_addr),


        .avm_read_addr  (fifo2master_read_addr ),
        .avm_read       (fifo2master_read      ),
        .avm_burst_size (fifo2master_burst_size),
        .avm_data_valid (fifo2master_data_valid),
        .avm_data       (fifo2master_data      ),
        .avm_ready      (fifo2master_ready     )
    ); 




lsu_streaming_prefetch_avalon_bust_master #(
        .AWIDTH           (AWIDTH          ),
        .MWIDTH           (MWIDTH          ),
        .MWIDTH_BYTES     (MWIDTH_BYTES    ),
        .BURSTCOUNT_WIDTH (BURSTCOUNT_WIDTH),
        .FIFO_DEPTH_LOG2  (FIFO_DEPTH_LOG2 )
    ) u_burst_master (
        .clk    (clk),
        .reset  (reset),
        .flush  (flush | internal_flush),
        .active (o_active),


        .fifo_read_addr  (fifo2master_read_addr ),
        .fifo_read       (fifo2master_read      ),
        .fifo_burst_size (fifo2master_burst_size),
        .fifo_data_valid (fifo2master_data_valid),
        .fifo_data       (fifo2master_data      ),
        .ready           (fifo2master_ready     ),


        .master_address       (f_avm_address    ),
        .master_read          (f_avm_read       ),
        .master_byteenable    (avm_byteenable   ),
        .master_readdata      (avm_readdata     ),
        .master_readdatavalid (avm_readdatavalid),
        .master_burstcount    (f_avm_burstcount ),
        .master_waitrequest   (f_avm_waitrequest)
    );





assign o_stall = (i_stall | internal_flush | (wait_for_read & i_valid_rr));

assign o_valid = i_valid_rr & !(internal_flush | wait_for_read);


generate
    if(MBYTE_SELECT_BITS != BYTE_SELECT_BITS) begin
        assign o_readdata = user_data_out[i_address_rr[MBYTE_SELECT_BITS-1:BYTE_SELECT_BITS] * WIDTH +: WIDTH];
    end else begin

        assign o_readdata = user_data_out;
    end
endgenerate


endmodule