data/full_repos/permissive/174783592/Adder_PL/sum16bit.sv
1: b'%Error: data/full_repos/permissive/174783592/Adder_PL/sum16bit.sv:1: Cannot find include file: kpgGen.v\n `include "kpgGen.v" \n          ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/174783592/Adder_PL,data/full_repos/permissive/174783592/kpgGen.v\n             data/full_repos/permissive/174783592/Adder_PL,data/full_repos/permissive/174783592/kpgGen.v.v\n             data/full_repos/permissive/174783592/Adder_PL,data/full_repos/permissive/174783592/kpgGen.v.sv\n             kpgGen.v\n             kpgGen.v.v\n             kpgGen.v.sv\n             obj_dir/kpgGen.v\n             obj_dir/kpgGen.v.v\n             obj_dir/kpgGen.v.sv\n%Error: data/full_repos/permissive/174783592/Adder_PL/sum16bit.sv:2: Cannot find include file: kpgCmp.v\n `include "kpgCmp.v" \n          ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module sum16bit(a,b,kIn,sum);


	input [15:0] a;
	input [15:0] b;
	input [1:0] kIn;

	wire [16:0] sumwire;
	output  [16:0]sum;

	wire [1:0] kpgIn [16:0];
	wire [1:0] wl1 [16:0];

	wire [1:0] wl2 [16:0];

	wire [1:0] wl3 [16:0];

	wire [1:0] wl4 [16:0];


	wire [1:0] kpgOut[22:0];

	wire [15:0] temp;
	assign kpgIn [0] = kIn;	
	generate
		genvar i;


		for(i =0;i<16; i = i + 1)
		begin
			kpgGen gen(a[i],b[i],kpgIn[i+1]);
		end

		for(i=0;i<16;i = i +1)
		begin
			kpgCmp cmp(kpgIn[i+1],kpgIn[i],wl1[i+1]);
		end

		for(i=0;i<15;i = i +1)
		begin
			kpgCmp cmp(wl1[i+2],wl1[i],wl2[i+2]);
		end

		
		for(i=0;i<13;i = i +1)
		begin
			kpgCmp cmp(wl2[i+4],wl2[i],wl3[i+4]);
		end
	

		
		for(i=0;i<9;i = i +1)
		begin
			kpgCmp cmp(wl3[i+8],wl3[i],wl4[i+8]);
		end

	endgenerate

    assign wl1[0] = kpgIn[0];
    assign wl2[0] = wl1[0];
	assign wl2[1] = wl1[1];
    assign wl3[0] = wl2[0];
	assign wl3[1] = wl2[1];
	assign wl3[2] = wl2[2];
	assign wl3[3] = wl2[3];


	generate
		for(i=0 ;i<8;i= i+1)
		begin
		assign wl4[i] = wl3[i];
		end
		endgenerate








	





	
	
    assign kpgOut[16]= wl4[16];
	assign kpgOut[15]= wl4[15];
	assign kpgOut[14]= wl4[14];
	assign kpgOut[13]= wl4[13];
	assign kpgOut[12]= wl4[12];
	assign kpgOut[11]= wl4[11];
	assign kpgOut[10]= wl4[10];
	assign kpgOut[9]= wl4[9];
	assign kpgOut[8]= wl4[8];
	assign kpgOut[7]= wl4[7];
	assign kpgOut[6]= wl4[6];
	assign kpgOut[5]= wl4[5];
	assign kpgOut[4]= wl4[4];
	assign kpgOut[3]= wl4[3];
	assign kpgOut[2]= wl4[2];
	assign kpgOut[1]= wl4[1];
	assign kpgOut[0]= wl4[0];













    

	generate 
    genvar j;
    
	for(j=0;j<16;j=j+1)
		begin
			assign temp[j] = kpgOut[j][0]|kpgOut[j][1];
			assign sum[j]  = a[j]^b[j]^temp[j];
		end
	

	 assign sum[16] = kpgOut[16][0] ;

    endgenerate





	endmodule
module sum16bit(a,b,kIn,sum);



	input [15:0] a;
	input [15:0] b;
	input [1:0] kIn;

	wire [16:0] sumwire;
	output  [16:0]sum;

	wire [1:0] kpgIn [16:0];
	wire [1:0] wl1 [16:0];

	wire [1:0] wl2 [16:0];

	wire [1:0] wl3 [16:0];

	wire [1:0] wl4 [16:0];


	wire [1:0] kpgOut[22:0];

	wire [15:0] temp;
	assign kpgIn [0] = kIn;	
	generate
		genvar i;


		for(i =0;i<16; i = i + 1)
		begin
			kpgGen gen(a[i],b[i],kpgIn[i+1]);
		end

		for(i=0;i<16;i = i +1)
		begin
			kpgCmp cmp(kpgIn[i+1],kpgIn[i],wl1[i+1]);
		end

		for(i=0;i<15;i = i +1)
		begin
			kpgCmp cmp(wl1[i+2],wl1[i],wl2[i+2]);
		end

		
		for(i=0;i<13;i = i +1)
		begin
			kpgCmp cmp(wl2[i+4],wl2[i],wl3[i+4]);
		end
	

		
		for(i=0;i<9;i = i +1)
		begin
			kpgCmp cmp(wl3[i+8],wl3[i],wl4[i+8]);
		end

	endgenerate

    assign wl1[0] = kpgIn[0];
    assign wl2[0] = wl1[0];
	assign wl2[1] = wl1[1];
    assign wl3[0] = wl2[0];
	assign wl3[1] = wl2[1];
	assign wl3[2] = wl2[2];
	assign wl3[3] = wl2[3];


	generate
		for(i=0 ;i<8;i= i+1)
		begin
		assign wl4[i] = wl3[i];
		end
		endgenerate








	





	
	
    assign kpgOut[16]= wl4[16];
	assign kpgOut[15]= wl4[15];
	assign kpgOut[14]= wl4[14];
	assign kpgOut[13]= wl4[13];
	assign kpgOut[12]= wl4[12];
	assign kpgOut[11]= wl4[11];
	assign kpgOut[10]= wl4[10];
	assign kpgOut[9]= wl4[9];
	assign kpgOut[8]= wl4[8];
	assign kpgOut[7]= wl4[7];
	assign kpgOut[6]= wl4[6];
	assign kpgOut[5]= wl4[5];
	assign kpgOut[4]= wl4[4];
	assign kpgOut[3]= wl4[3];
	assign kpgOut[2]= wl4[2];
	assign kpgOut[1]= wl4[1];
	assign kpgOut[0]= wl4[0];













    

	generate 
    genvar j;
    
	for(j=0;j<16;j=j+1)
		begin
			assign temp[j] = kpgOut[j][0]|kpgOut[j][1];
			assign sum[j]  = a[j]^b[j]^temp[j];
		end
	

	 assign sum[16] = kpgOut[16][0] ;

    endgenerate





	endmodule