data/full_repos/permissive/201488448/2_circuits/2_sequential/xx_bcdcounter.v
data/verilator_xmls/7ff5d2b3-58ea-45f6-ba52-d962acec9ebc.xml
module top_module (
    input clk,
    input reset,
    input enable,
    output reg [3:0] Q
);

    always@(posedge clk) begin
        if(reset)
            Q <= 4'd0;
        else if(enable) begin
            if(Q==9)
                Q <= 4'd0;
            else
                Q <= Q + 1'b1;
        end
    end
    
endmodule
module top_module (
    input clk,
    input reset,
    input enable,
    output reg [3:0] Q
);


    always@(posedge clk) begin
        if(reset)
            Q <= 4'd0;
        else if(enable) begin
            if(Q==9)
                Q <= 4'd0;
            else
                Q <= Q + 1'b1;
        end
    end
    
endmodule