data/full_repos/permissive/135820056/rtl/jt12/jt12_rst.v
 line:38: before: "/"
data/verilator_xmls/b39a1b48-3c3d-46c9-abce-af4111dfc156.xml
module jt12_rst(
    input   rst,
    input   clk,
    output  reg rst_n
);

reg r;

always @(negedge clk)
    if( rst ) begin
        r     <= 1'b0;
        rst_n <= 1'b0;
    end else begin
        { rst_n, r } <= { r, 1'b1 };
    end

endmodule
module jt12_rst(
    input   rst,
    input   clk,
    output  reg rst_n
);


reg r;

always @(negedge clk)
    if( rst ) begin
        r     <= 1'b0;
        rst_n <= 1'b0;
    end else begin
        { rst_n, r } <= { r, 1'b1 };
    end

endmodule