data/full_repos/permissive/105948944/sources/sensor_IP_v2.v
1: b"%Error: data/full_repos/permissive/105948944/sources/sensor_IP_v2.v:39: Cannot find file containing module: 'sync_rebuiltSignal'\n    sync_rebuiltSignal sycIP_front(\n    ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/sync_rebuiltSignal\n             data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/sync_rebuiltSignal.v\n             data/full_repos/permissive/105948944/sources,data/full_repos/permissive/105948944/sync_rebuiltSignal.sv\n             sync_rebuiltSignal\n             sync_rebuiltSignal.v\n             sync_rebuiltSignal.sv\n             obj_dir/sync_rebuiltSignal\n             obj_dir/sync_rebuiltSignal.v\n             obj_dir/sync_rebuiltSignal.sv\n%Error: data/full_repos/permissive/105948944/sources/sensor_IP_v2.v:45: Cannot find file containing module: 'sync_rebuiltSignal'\n    sync_rebuiltSignal sycIP_back(\n    ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module sensor_IP_v2(
    input clock,
    input [3:0]  IPsensFront_in,
    input [3:0]  IPsensBack_in,
    
    output [3:0] IPsensFront_out,
    output [3:0] IPsensBack_out
);
    reg [3:0] IPsensFront_reg;
    reg [3:0] IPsensBack_reg;
    wire [3:0] IPsensFront_synced_wire;
    wire [3:0] IPsensBack_synced_wire;
    
    always@(posedge clock) begin 
        IPsensFront_reg <= ~IPsensFront_in;
        IPsensBack_reg <= ~IPsensBack_in;
    end
     
    sync_rebuiltSignal sycIP_front(
        .clock(clock),
        .sensors(IPsensFront_reg),
        .rebuiltSignal(IPsensFront_synced_wire)
        );
    
    sync_rebuiltSignal sycIP_back(
        .clock(clock),
        .sensors(IPsensBack_reg),
        .rebuiltSignal(IPsensBack_synced_wire)
        );        

    assign IPsensFront_out = IPsensFront_synced_wire;
    assign IPsensBack_out = IPsensBack_synced_wire;
endmodule
module sensor_IP_v2(
    input clock,
    input [3:0]  IPsensFront_in,
    input [3:0]  IPsensBack_in,
    
    output [3:0] IPsensFront_out,
    output [3:0] IPsensBack_out
);

    reg [3:0] IPsensFront_reg;
    reg [3:0] IPsensBack_reg;
    wire [3:0] IPsensFront_synced_wire;
    wire [3:0] IPsensBack_synced_wire;
    
    always@(posedge clock) begin 
        IPsensFront_reg <= ~IPsensFront_in;
        IPsensBack_reg <= ~IPsensBack_in;
    end
     
    sync_rebuiltSignal sycIP_front(
        .clock(clock),
        .sensors(IPsensFront_reg),
        .rebuiltSignal(IPsensFront_synced_wire)
        );
    
    sync_rebuiltSignal sycIP_back(
        .clock(clock),
        .sensors(IPsensBack_reg),
        .rebuiltSignal(IPsensBack_synced_wire)
        );        

    assign IPsensFront_out = IPsensFront_synced_wire;
    assign IPsensBack_out = IPsensBack_synced_wire;
endmodule