data/full_repos/permissive/208741034/key_control_beep/rtl/beep_control.v
 line:24: before: "/"
data/verilator_xmls/44dd8e0d-c265-4102-b5e7-46c964efff2b.xml
module beep_control(
    input clk,
    input rst_n,

    input key_flag,
    input key_value,
    output reg beep
  
);

always @(posedge clk or negedge rst_n) begin
    if(!rst_n) 
       beep <= 1'b0;
    
    else begin
        if(key_flag && (~key_value))
        beep <= ~beep;
        else
        beep <= beep;        
    end

end

endmodule
module beep_control(
    input clk,
    input rst_n,

    input key_flag,
    input key_value,
    output reg beep
  
);


always @(posedge clk or negedge rst_n) begin
    if(!rst_n) 
       beep <= 1'b0;
    
    else begin
        if(key_flag && (~key_value))
        beep <= ~beep;
        else
        beep <= beep;        
    end

end

endmodule