data/full_repos/permissive/102515926/Modules/CIRCUIT1.v
1: b"%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:19: Cannot find file containing module: 'ADD'\n    ADD #(8) ADD_1(a, b, d);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.v\n             data/full_repos/permissive/102515926/Modules,data/full_repos/permissive/102515926/ADD.sv\n             ADD\n             ADD.v\n             ADD.sv\n             obj_dir/ADD\n             obj_dir/ADD.v\n             obj_dir/ADD.sv\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:20: Cannot find file containing module: 'ADD'\n    ADD #(8) ADD_2(a, c, e);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:21: Cannot find file containing module: 'COMP'\n    COMP #(8) COMP_1(d, e, g_gt, g_lt, g_eq);\n    ^~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:22: Cannot find file containing module: 'MUX2x1'\n    MUX2x1 #(8) MUX2x1_1(e, d, g_gt, z);\n    ^~~~~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:23: Cannot find file containing module: 'MUL'\n    MUL #(8) MUL_1(a, c, f);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:24: Cannot find file containing module: 'SUB'\n    SUB #(16) SUB_1(f, d, xwire);\n    ^~~\n%Error: data/full_repos/permissive/102515926/Modules/CIRCUIT1.v:25: Cannot find file containing module: 'REG'\n    REG #(16) REG_1(xwire, Clk, Rst, x);\n    ^~~\n%Error: Exiting due to 7 error(s)\n"
module CIRCUIT1(a, b, c, x, z, Clk, Rst);
    
    input Clk, Rst;
    input [7:0] a, b, c;
    output [7:0] z;
    output [15:0] x;
    
    wire [7:0] d, e;
    wire [15:0] f, g_lt, g_gt, g_eq, xwire;
    
    ADD #(8) ADD_1(a, b, d);
    ADD #(8) ADD_2(a, c, e);
    COMP #(8) COMP_1(d, e, g_gt, g_lt, g_eq);
    MUX2x1 #(8) MUX2x1_1(e, d, g_gt, z);
    MUL #(8) MUL_1(a, c, f);
    SUB #(16) SUB_1(f, d, xwire);
    REG #(16) REG_1(xwire, Clk, Rst, x);

endmodule
module CIRCUIT1(a, b, c, x, z, Clk, Rst);

    
    input Clk, Rst;
    input [7:0] a, b, c;
    output [7:0] z;
    output [15:0] x;
    
    wire [7:0] d, e;
    wire [15:0] f, g_lt, g_gt, g_eq, xwire;
    
    ADD #(8) ADD_1(a, b, d);
    ADD #(8) ADD_2(a, c, e);
    COMP #(8) COMP_1(d, e, g_gt, g_lt, g_eq);
    MUX2x1 #(8) MUX2x1_1(e, d, g_gt, z);
    MUL #(8) MUL_1(a, c, f);
    SUB #(16) SUB_1(f, d, xwire);
    REG #(16) REG_1(xwire, Clk, Rst, x);

endmodule