data/full_repos/permissive/143278/ivltests/not_a_latch2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:51: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:61: Unsupported: Ignoring delay on this delayed statement.\n      #1 ;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:67: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/not_a_latch2.v:68: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test(input wire load, drain,
	    input wire clk, data,
	    output reg foo_nxt, bar_nxt);

   reg		       foo, bar;

   (* ivl_combinational *)
   always @* begin
      foo_nxt = foo;
      bar_nxt = bar;

      if (load) begin
	 foo_nxt = data;
	 bar_nxt = 1;
      end else if (drain) begin
	 bar_nxt = 0;
      end
   end

   always @(posedge clk) begin
      foo <= foo_nxt;
      bar <= bar_nxt;
   end

endmodule
module test(input wire load, drain,
	    input wire clk, data,
	    output reg foo_nxt, bar_nxt);


   reg		       foo, bar;

   (* ivl_combinational *)
   always @* begin
      foo_nxt = foo;
      bar_nxt = bar;

      if (load) begin
	 foo_nxt = data;
	 bar_nxt = 1;
      end else if (drain) begin
	 bar_nxt = 0;
      end
   end

   always @(posedge clk) begin
      foo <= foo_nxt;
      bar <= bar_nxt;
   end

endmodule