data/full_repos/permissive/174323821/hdl/cpu/jtframe_68kramcs.v
data/verilator_xmls/e1c48990-98f1-4b7b-b712-b1f21e876543.xml
module jtframe_68kramcs #(parameter W=2)(
    input          rst,
    input          clk,
    input          cpu_cen,

    input          UDSWn,
    input          LDSWn,

    input  [W-1:0] pre_cs,
    output [W-1:0] cs
);

reg         dsn_dly;
reg [W-1:0] cs_latch;




assign cs  = dsn_dly ? (cs_latch&pre_cs)  : pre_cs;

always @(posedge clk) begin
    if( rst ) begin
        cs_latch <= 0;
        dsn_dly  <= 1;
    end else if(cpu_cen) begin
        cs_latch <= pre_cs;
        dsn_dly  <= &{UDSWn,LDSWn};
    end
end

endmodule
module jtframe_68kramcs #(parameter W=2)(
    input          rst,
    input          clk,
    input          cpu_cen,

    input          UDSWn,
    input          LDSWn,

    input  [W-1:0] pre_cs,
    output [W-1:0] cs
);


reg         dsn_dly;
reg [W-1:0] cs_latch;




assign cs  = dsn_dly ? (cs_latch&pre_cs)  : pre_cs;

always @(posedge clk) begin
    if( rst ) begin
        cs_latch <= 0;
        dsn_dly  <= 1;
    end else if(cpu_cen) begin
        cs_latch <= pre_cs;
        dsn_dly  <= &{UDSWn,LDSWn};
    end
end

endmodule