data/full_repos/permissive/178355189/bus_arbiter.template.v
 line:24: before: "{"
1: b"%Error: data/full_repos/permissive/178355189/bus_arbiter.template.v:24: syntax error, unexpected '{'\n{% set num_channels = 8 %}\n^\n%Error: data/full_repos/permissive/178355189/bus_arbiter.template.v:30: syntax error, unexpected '{', expecting '['\n    {% for index in indices %}\n    ^\n%Error: data/full_repos/permissive/178355189/bus_arbiter.template.v:44: syntax error, unexpected '{'\n{% for index in indices %}\n^\n%Error: data/full_repos/permissive/178355189/bus_arbiter.template.v:47: syntax error, unexpected '{', expecting ',' or ';'\nreg[DATA_WIDTH-1:0] data_reg_{{index}};\n                             ^\n%Error: data/full_repos/permissive/178355189/bus_arbiter.template.v:51: syntax error, unexpected '{', expecting ',' or ';'\nreg data_rdy_reg_{{index}};\n                 ^\n%Error: data/full_repos/permissive/178355189/bus_arbiter.template.v:55: syntax error, unexpected '{', expecting ',' or ';'\nwire data_req_outstanding_{{index}};\n                          ^\n%Error: data/full_repos/permissive/178355189/bus_arbiter.template.v:59: syntax error, unexpected '{', expecting ',' or ';'\nreg data_cmpl_read_reg_{{index}};\n                       ^\n%Error: Exiting due to 7 error(s)\n"
module bus_arbiter(
    input clk,
    input rst,

    {% for index in indices %}
    input data_req_{{index}},
    input[ADDRESS_WIDTH-1:0] data_addr_{{index}},
    output[DATA_WIDTH-1:0] data_{{index}},
    output data_rdy_{{index}},
    {% endfor %}

    output[ADDRESS_WIDTH-1:0] mem_data_addr,
    input[DATA_WIDTH-1:0] mem_data
);

parameter ADDRESS_WIDTH = 8;
parameter DATA_WIDTH = 8;

{% for index in indices %}


reg[DATA_WIDTH-1:0] data_reg_{{index}};
assign data_{{index}} = data_reg_{{index}};


reg data_rdy_reg_{{index}};
assign data_rdy_{{index}} = data_rdy_reg_{{index}};


wire data_req_outstanding_{{index}};
assign data_req_outstanding_{{index}} = (data_req_{{index}} & !data_rdy_reg_{{index}});


reg data_cmpl_read_reg_{{index}};
{% endfor %}



assign mem_data_addr = (
    {% for index in indices %}
    (data_req_outstanding_{{index}} ? data_addr_{{index}} :
    {% endfor %}
    0
    {% for index in indices %}
    )
    {% endfor %}
);


always @(posedge clk) begin
    if (rst) begin
        {% for index in indices %}
        data_rdy_reg_{{index}} <= 0;
        data_reg_{{index}} <= 0;
        data_cmpl_read_reg_{{index}} <= 0;
        {% endfor %}
    end else begin

        {% for index in indices %}
        if (!data_req_{{index}}) begin
            data_rdy_reg_{{index}} <= 0;
            data_cmpl_read_reg_{{index}} <= 0;
        end
        {% endfor %}


        {% for index in indices %}
        if (data_req_outstanding_{{index}}) begin
            if (data_cmpl_read_reg_{{index}}) begin
                data_reg_{{index}} <= mem_data;
                data_rdy_reg_{{index}} <= 1;
            end else begin
                data_cmpl_read_reg_{{index}} <= 1;
            end
        end
            {% if index != indices[-1] %}
            else
            {% endif %}
        {% endfor %}
    end
end

endmodule
module bus_arbiter(
    input clk,
    input rst,

    {% for index in indices %}
    input data_req_{{index}},
    input[ADDRESS_WIDTH-1:0] data_addr_{{index}},
    output[DATA_WIDTH-1:0] data_{{index}},
    output data_rdy_{{index}},
    {% endfor %}

    output[ADDRESS_WIDTH-1:0] mem_data_addr,
    input[DATA_WIDTH-1:0] mem_data
);


parameter ADDRESS_WIDTH = 8;
parameter DATA_WIDTH = 8;

{% for index in indices %}


reg[DATA_WIDTH-1:0] data_reg_{{index}};
assign data_{{index}} = data_reg_{{index}};


reg data_rdy_reg_{{index}};
assign data_rdy_{{index}} = data_rdy_reg_{{index}};


wire data_req_outstanding_{{index}};
assign data_req_outstanding_{{index}} = (data_req_{{index}} & !data_rdy_reg_{{index}});


reg data_cmpl_read_reg_{{index}};
{% endfor %}



assign mem_data_addr = (
    {% for index in indices %}
    (data_req_outstanding_{{index}} ? data_addr_{{index}} :
    {% endfor %}
    0
    {% for index in indices %}
    )
    {% endfor %}
);


always @(posedge clk) begin
    if (rst) begin
        {% for index in indices %}
        data_rdy_reg_{{index}} <= 0;
        data_reg_{{index}} <= 0;
        data_cmpl_read_reg_{{index}} <= 0;
        {% endfor %}
    end else begin

        {% for index in indices %}
        if (!data_req_{{index}}) begin
            data_rdy_reg_{{index}} <= 0;
            data_cmpl_read_reg_{{index}} <= 0;
        end
        {% endfor %}


        {% for index in indices %}
        if (data_req_outstanding_{{index}}) begin
            if (data_cmpl_read_reg_{{index}}) begin
                data_reg_{{index}} <= mem_data;
                data_rdy_reg_{{index}} <= 1;
            end else begin
                data_cmpl_read_reg_{{index}} <= 1;
            end
        end
            {% if index != indices[-1] %}
            else
            {% endif %}
        {% endfor %}
    end
end

endmodule