data/full_repos/permissive/125592111/verilog/Multiplexers_tb.v
 line:57: before: "$"
1: b'%Error: data/full_repos/permissive/125592111/verilog/Multiplexers_tb.v:29: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("mux_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/Multiplexers_tb.v:30: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(-1, dut);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/125592111/verilog/Multiplexers_tb.v:31: Unsupported or unknown PLI call: $monitor\n  $monitor("%b", out);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/125592111/verilog/Multiplexers_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/125592111/verilog/Multiplexers_tb.v:38: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n  In1_RegRs = $random(seed);\n              ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/125592111/verilog/Multiplexers_tb.v:38: ../V3Ast.cpp:358: Null item passed to setOp1p\n  In1_RegRs = $random(seed);\n            ^\n                        ... See the manual and https://verilator.org for more assistance.\n'
module regDst_mux_3_to_1_tb();

parameter tck = 10;


reg [4:0] In1_imm_destination_rt, In2_rType_rd, In3_jal_ra;
reg [1:0] Ctrl_RegDst;
wire [4:0] out;

regDst_mux_3_to_1 dut(	

	.In1_imm_destination_rt(In1_imm_destination_rt), 
	.In2_rType_rd(In2_rType_rd), 
	.In3_jal_ra(In3_jal_ra), 
	.Ctrl_RegDst(Ctrl_RegDst),
	.out(out)

			);

integer seed = 2 ;

initial begin

		$dumpvars(-1, dut);
		$monitor("%b", out);
	end

initial begin
		Ctrl_RegDst = 0;
		#5
		Ctrl_RegDst = 0;
		In1_imm_destination_rt = $random(seed);
		In2_rType_rd = $random(seed);
		In3_jal_ra = $random(seed);
		#5
		Ctrl_RegDst = 1;
		In1_imm_destination_rt = $random(seed);
		In2_rType_rd = $random(seed);
		In3_jal_ra = $random(seed);
		#5
		Ctrl_RegDst = 2;
		In1_imm_destination_rt = $random(seed);
		In2_rType_rd = $random(seed);
		In3_jal_ra = $random(seed);
		#5
		Ctrl_RegDst = 0;
		In1_imm_destination_rt = $random(seed);
		In2_rType_rd = $random(seed);
		In3_jal_ra = $random(seed);
		#5
		$finish;
	end

endmodule
module regDst_mux_3_to_1_tb();


parameter tck = 10;


reg [4:0] In1_imm_destination_rt, In2_rType_rd, In3_jal_ra;
reg [1:0] Ctrl_RegDst;
wire [4:0] out;

regDst_mux_3_to_1 dut(	

	.In1_imm_destination_rt(In1_imm_destination_rt), 
	.In2_rType_rd(In2_rType_rd), 
	.In3_jal_ra(In3_jal_ra), 
	.Ctrl_RegDst(Ctrl_RegDst),
	.out(out)

			);

integer seed = 2 ;

initial begin

		$dumpvars(-1, dut);
		$monitor("%b", out);
	end

initial begin
		Ctrl_RegDst = 0;
		#5
		Ctrl_RegDst = 0;
		In1_imm_destination_rt = $random(seed);
		In2_rType_rd = $random(seed);
		In3_jal_ra = $random(seed);
		#5
		Ctrl_RegDst = 1;
		In1_imm_destination_rt = $random(seed);
		In2_rType_rd = $random(seed);
		In3_jal_ra = $random(seed);
		#5
		Ctrl_RegDst = 2;
		In1_imm_destination_rt = $random(seed);
		In2_rType_rd = $random(seed);
		In3_jal_ra = $random(seed);
		#5
		Ctrl_RegDst = 0;
		In1_imm_destination_rt = $random(seed);
		In2_rType_rd = $random(seed);
		In3_jal_ra = $random(seed);
		#5
		$finish;
	end

endmodule