data/full_repos/permissive/20759093/CPU_TOP.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/20759093/CPU_TOP.v:241: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'Single_Cycle_CPU\'\nmodule Single_Cycle_CPU(\n       ^~~~~~~~~~~~~~~~\n                                                                    : ... Top module \'mux_2_to_1_5\'\nmodule mux_2_to_1_5(\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/20759093/CPU_TOP.v:496: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                 : ... In instance Single_Cycle_CPU.M4\n            4\'b1001 : result <= (A < B);\n                             ^~\n%Error: data/full_repos/permissive/20759093/CPU_TOP.v:104: Cannot find file containing module: \'RAM_A\'\n    RAM_A M8(\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A.v\n             data/full_repos/permissive/20759093,data/full_repos/permissive/20759093/RAM_A.sv\n             RAM_A\n             RAM_A.v\n             RAM_A.sv\n             obj_dir/RAM_A\n             obj_dir/RAM_A.v\n             obj_dir/RAM_A.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module display(
    input clk,
    input [15:0]disp_num,
    output reg [6:0]seg,
    output reg [3:0]anode
);

    reg [26:0]tick;
    reg [1:0]an;
    reg [3:0]num;
    reg t;
    
    initial begin
        an <= 2'b00;
        tick <= 0;
    end
    
    always @(posedge clk)
        tick = tick+1;
    
    always @(posedge tick[16]) 
        an = an + 1;
    
    always @(an) begin
        anode <= ~(4'b1<<an);
        case(an) 
            2'b00: num = disp_num[3:0];
            2'b01: num = disp_num[7:4];
            2'b10: num = disp_num[11:8];
            2'b11: num = disp_num[15:12];
            default:;
        endcase
    end

    always @(anode or num) begin
        case(num)
            4'h0 : seg[6:0] = 7'b1000000;
            4'h1 : seg[6:0] = 7'b1111001;
            4'h2 : seg[6:0] = 7'b0100100;
            4'h3 : seg[6:0] = 7'b0110000;
            4'h4 : seg[6:0] = 7'b0011001;
            4'h5 : seg[6:0] = 7'b0010010;
            4'h6 : seg[6:0] = 7'b0000010;
            4'h7 : seg[6:0] = 7'b1111000;
            4'h8 : seg[6:0] = 7'b0000000;
            4'h9 : seg[6:0] = 7'b0010000;
            4'hA : seg[6:0] = 7'b0001000;
            4'hB : seg[6:0] = 7'b0000011;
            4'hC : seg[6:0] = 7'b1000110;
            4'hD : seg[6:0] = 7'b0100001;
            4'hE : seg[6:0] = 7'b0000110;
            default : seg[6:0] = 7'b0001110;
        endcase
    end

endmodule
module display(
    input clk,
    input [15:0]disp_num,
    output reg [6:0]seg,
    output reg [3:0]anode
);


    reg [26:0]tick;
    reg [1:0]an;
    reg [3:0]num;
    reg t;
    
    initial begin
        an <= 2'b00;
        tick <= 0;
    end
    
    always @(posedge clk)
        tick = tick+1;
    
    always @(posedge tick[16]) 
        an = an + 1;
    
    always @(an) begin
        anode <= ~(4'b1<<an);
        case(an) 
            2'b00: num = disp_num[3:0];
            2'b01: num = disp_num[7:4];
            2'b10: num = disp_num[11:8];
            2'b11: num = disp_num[15:12];
            default:;
        endcase
    end

    always @(anode or num) begin
        case(num)
            4'h0 : seg[6:0] = 7'b1000000;
            4'h1 : seg[6:0] = 7'b1111001;
            4'h2 : seg[6:0] = 7'b0100100;
            4'h3 : seg[6:0] = 7'b0110000;
            4'h4 : seg[6:0] = 7'b0011001;
            4'h5 : seg[6:0] = 7'b0010010;
            4'h6 : seg[6:0] = 7'b0000010;
            4'h7 : seg[6:0] = 7'b1111000;
            4'h8 : seg[6:0] = 7'b0000000;
            4'h9 : seg[6:0] = 7'b0010000;
            4'hA : seg[6:0] = 7'b0001000;
            4'hB : seg[6:0] = 7'b0000011;
            4'hC : seg[6:0] = 7'b1000110;
            4'hD : seg[6:0] = 7'b0100001;
            4'hE : seg[6:0] = 7'b0000110;
            default : seg[6:0] = 7'b0001110;
        endcase
    end

endmodule