data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v
 line:20: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:11: Unsupported: Ignoring delay on this delayed statement.\n #00 clock = 1\'b0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:12: Unsupported: Ignoring delay on this delayed statement.\n forever #20 clock = ~clock;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:17: Unsupported: Ignoring delay on this delayed statement.\n #00 ud = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:18: Unsupported: Ignoring delay on this delayed statement.\n #1250 ud = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:19: Unsupported: Ignoring delay on this delayed statement.\n #1250 ud = 1\'b0;\n ^\n%Error: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:21: syntax error, unexpected end, expecting \';\'\nend\n^~~\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:20: Unsupported: Ignoring delay on this delayed statement.\n #1250 $stop\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:26: Unsupported: Ignoring delay on this delayed statement.\n #30 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:27: Unsupported: Ignoring delay on this delayed statement.\n #2000 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:28: Unsupported: Ignoring delay on this delayed statement.\n #30 reset = 1\'b1;\n ^\n%Error: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:33: Unsupported or unknown PLI call: $monitor\n $monitor("time=%3d, high=%4b, low=%4b, ud=%b, clock=%b, reset=%b", $time, high, low, ud, clock, reset);\n ^~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:38: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("bcd_ud_counter_8bit.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:39: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:51: Value too large for 1 bit number: 5\nparameter limit_msb = 1\'d5;\n                      ^~~~\n%Error: data/full_repos/permissive/117880471/HW2/bcd_ud_counter_8bit.v:53: syntax error, unexpected negedge, expecting TYPE-IDENTIFIER\nalways@*(negedge clock, ~reset)\n         ^~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_bcd_ud_counter_8bit();
wire [3:0] high, low;
reg ud, clock, reset;

bcd_ud_counter_8bit uut(high, low, ud, clock, reset);

initial
begin
	#00	clock = 1'b0;
	forever #20 clock = ~clock;
end

initial
begin
	#00 ud = 1'b1;
	#1250 ud = 1'b0;
	#1250 ud = 1'b0;
	#1250 $stop
end

initial
begin
	#00 reset = 1'b0;
	#30 reset = 1'b1;
	#2000 reset = 1'b0;
	#30 reset = 1'b1;
end

initial
begin
	$monitor("time=%3d, high=%4b, low=%4b, ud=%b, clock=%b, reset=%b", $time, high, low, ud, clock, reset);
end

initial
begin
	$dumpfile("bcd_ud_counter_8bit.vcd");
	$dumpvars;
end

endmodule
module tb_bcd_ud_counter_8bit();

wire [3:0] high, low;
reg ud, clock, reset;

bcd_ud_counter_8bit uut(high, low, ud, clock, reset);

initial
begin
	#00	clock = 1'b0;
	forever #20 clock = ~clock;
end

initial
begin
	#00 ud = 1'b1;
	#1250 ud = 1'b0;
	#1250 ud = 1'b0;
	#1250 $stop
end

initial
begin
	#00 reset = 1'b0;
	#30 reset = 1'b1;
	#2000 reset = 1'b0;
	#30 reset = 1'b1;
end

initial
begin
	$monitor("time=%3d, high=%4b, low=%4b, ud=%b, clock=%b, reset=%b", $time, high, low, ud, clock, reset);
end

initial
begin
	$dumpfile("bcd_ud_counter_8bit.vcd");
	$dumpvars;
end

endmodule