data/full_repos/permissive/116866011/PipeCNN/project/device/RTL/mult_add_fix8bx4/mult_add_fix8bx4.v
1: b"%Error: data/full_repos/permissive/116866011/PipeCNN/project/device/RTL/mult_add_fix8bx4/mult_add_fix8bx4.v:34: Cannot find file containing module: 'mult_add_fix8bx4_0002'\n mult_add_fix8bx4_0002 mult_add_fix8bx4_inst (\n ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/116866011/PipeCNN/project/device/RTL/mult_add_fix8bx4,data/full_repos/permissive/116866011/mult_add_fix8bx4_0002\n             data/full_repos/permissive/116866011/PipeCNN/project/device/RTL/mult_add_fix8bx4,data/full_repos/permissive/116866011/mult_add_fix8bx4_0002.v\n             data/full_repos/permissive/116866011/PipeCNN/project/device/RTL/mult_add_fix8bx4,data/full_repos/permissive/116866011/mult_add_fix8bx4_0002.sv\n             mult_add_fix8bx4_0002\n             mult_add_fix8bx4_0002.v\n             mult_add_fix8bx4_0002.sv\n             obj_dir/mult_add_fix8bx4_0002\n             obj_dir/mult_add_fix8bx4_0002.v\n             obj_dir/mult_add_fix8bx4_0002.sv\n%Error: Exiting due to 1 error(s)\n"
module mult_add_fix8bx4 (
		input   clock,
		input   resetn,
		input   ivalid, 
		input   iready,
		output  ovalid, 
		output  oready,
		
		input  wire [7:0]  dataa_0,
		input  wire [7:0]  datab_0,
		
		input  wire [7:0]  dataa_1,
		input  wire [7:0]  datab_1,
		
		input  wire [7:0]  dataa_2,
		input  wire [7:0]  datab_2,
		
		input  wire [7:0]  dataa_3,
		input  wire [7:0]  datab_3,
		
		output wire [31:0] result
	);

	wire [17:0] result_18b;

	assign ovalid = 1'b1;
	assign oready = 1'b1;


	assign result = {{14{result_18b[17]}}, result_18b};


	mult_add_fix8bx4_0002 mult_add_fix8bx4_inst (
		.result  (result_18b),
		.dataa_0 (dataa_0),
		.dataa_1 (dataa_1),
		.dataa_2 (dataa_2),
		.dataa_3 (dataa_3),
		.datab_0 (datab_0),
		.datab_1 (datab_1),
		.datab_2 (datab_2),
		.datab_3 (datab_3),
		.clock0  (clock)
	);

endmodule
module mult_add_fix8bx4 (
		input   clock,
		input   resetn,
		input   ivalid, 
		input   iready,
		output  ovalid, 
		output  oready,
		
		input  wire [7:0]  dataa_0,
		input  wire [7:0]  datab_0,
		
		input  wire [7:0]  dataa_1,
		input  wire [7:0]  datab_1,
		
		input  wire [7:0]  dataa_2,
		input  wire [7:0]  datab_2,
		
		input  wire [7:0]  dataa_3,
		input  wire [7:0]  datab_3,
		
		output wire [31:0] result
	);


	wire [17:0] result_18b;

	assign ovalid = 1'b1;
	assign oready = 1'b1;


	assign result = {{14{result_18b[17]}}, result_18b};


	mult_add_fix8bx4_0002 mult_add_fix8bx4_inst (
		.result  (result_18b),
		.dataa_0 (dataa_0),
		.dataa_1 (dataa_1),
		.dataa_2 (dataa_2),
		.dataa_3 (dataa_3),
		.datab_0 (datab_0),
		.datab_1 (datab_1),
		.datab_2 (datab_2),
		.datab_3 (datab_3),
		.clock0  (clock)
	);

endmodule