data/full_repos/permissive/137416811/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
data/verilator_xmls/dede8e61-f8d2-410c-a020-cb887ad5d732.xml
module mac_8(a, b, c, out);
parameter DATA_WIDTH = 8;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out = a * b + c;

endmodule
module mac_8(a, b, c, out);

parameter DATA_WIDTH = 8;
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;

assign out = a * b + c;

endmodule