data/full_repos/permissive/19340845/test/ForwardingTest.v
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1: b'%Error: data/full_repos/permissive/19340845/test/ForwardingTest.v:9: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("ForwadingTest.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19340845/test/ForwardingTest.v:10: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, FORWARDINGTEST);\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/19340845/test/ForwardingTest.v:11: Unsupported or unknown PLI call: $monitor\n      $monitor ("%t: oneA = %b, oneB = %b, twoA = %b, twoB = %b, one_A = %b, one_B = %b, two_A = %b, two_B = %b, outA = %b, outB = %b", $time, oneA, oneB, twoA, twoB, one_A, one_B, two_A, two_B, outA, outB);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #10 \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:18: Unsupported: Ignoring delay on this delayed statement.\n      #10 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #10 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #10 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #10 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #10 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #10 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #10 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #10 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #10 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #10 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #10 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:40: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:46: Unsupported: Ignoring delay on this delayed statement.\n      #10\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/19340845/test/ForwardingTest.v:48: Unsupported: Ignoring delay on this delayed statement.\n      #10 $finish;\n      ^\n%Error: Exiting due to 3 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FORWARDINGTEST;
   reg [15:0] oneA, oneB, twoA, twoB;
   reg 	      one_A, one_B, two_A, two_B;
   wire [15:0] outA, outB;
   
   Forwarding fw (oneA, oneB, twoA, twoB, one_A, one_B, two_A, two_B, outA, outB);

   initial begin
      $dumpfile("ForwadingTest.vcd");
      $dumpvars(0, FORWARDINGTEST);
      $monitor ("%t: oneA = %b, oneB = %b, twoA = %b, twoB = %b, one_A = %b, one_B = %b, two_A = %b, two_B = %b, outA = %b, outB = %b", $time, oneA, oneB, twoA, twoB, one_A, one_B, two_A, two_B, outA, outB);

      oneA = 16'b0000_1111_0000_0000; oneB = 16'b0000_0000_1111_0000;
      twoA = 16'b1111_0000_0000_0000; twoB = 16'b0000_0000_0000_1111;
      one_A = 1'b0; one_B = 1'b0; two_A = 1'b0; two_B = 1'b0;
      #10 
      one_A = 1'b0; one_B = 1'b0; two_A = 1'b0; two_B = 1'b1;
      #10 
      one_A = 1'b0; one_B = 1'b0; two_A = 1'b1; two_B = 1'b0;
      #10 
      one_A = 1'b0; one_B = 1'b0; two_A = 1'b1; two_B = 1'b1;
      #10 
      one_A = 1'b0; one_B = 1'b1; two_A = 1'b0; two_B = 1'b0;
      #10 
      one_A = 1'b0; one_B = 1'b1; two_A = 1'b0; two_B = 1'b1;
      #10 
      one_A = 1'b0; one_B = 1'b1; two_A = 1'b1; two_B = 1'b0;
      #10 
      one_A = 1'b0; one_B = 1'b1; two_A = 1'b1; two_B = 1'b1;
      #10 
      one_A = 1'b1; one_B = 1'b0; two_A = 1'b0; two_B = 1'b0;
      #10 
      one_A = 1'b1; one_B = 1'b0; two_A = 1'b0; two_B = 1'b1;
      #10 
      one_A = 1'b1; one_B = 1'b0; two_A = 1'b1; two_B = 1'b0;
      #10 
      one_A = 1'b1; one_B = 1'b0; two_A = 1'b1; two_B = 1'b1;
      #10 
      one_A = 1'b1; one_B = 1'b1; two_A = 1'b0; two_B = 1'b0;
      #10
      one_A = 1'b1; one_B = 1'b1; two_A = 1'b0; two_B = 1'b1;
      #10
      one_A = 1'b1; one_B = 1'b1; two_A = 1'b1; two_B = 1'b0;
      #10
      one_A = 1'b1; one_B = 1'b1; two_A = 1'b1; two_B = 1'b1;
      #10
      one_A = 1'b0; one_B = 1'b0; two_A = 1'b0; two_B = 1'b0;
      #10 $finish;
   end
endmodule
module FORWARDINGTEST;

   reg [15:0] oneA, oneB, twoA, twoB;
   reg 	      one_A, one_B, two_A, two_B;
   wire [15:0] outA, outB;
   
   Forwarding fw (oneA, oneB, twoA, twoB, one_A, one_B, two_A, two_B, outA, outB);

   initial begin
      $dumpfile("ForwadingTest.vcd");
      $dumpvars(0, FORWARDINGTEST);
      $monitor ("%t: oneA = %b, oneB = %b, twoA = %b, twoB = %b, one_A = %b, one_B = %b, two_A = %b, two_B = %b, outA = %b, outB = %b", $time, oneA, oneB, twoA, twoB, one_A, one_B, two_A, two_B, outA, outB);

      oneA = 16'b0000_1111_0000_0000; oneB = 16'b0000_0000_1111_0000;
      twoA = 16'b1111_0000_0000_0000; twoB = 16'b0000_0000_0000_1111;
      one_A = 1'b0; one_B = 1'b0; two_A = 1'b0; two_B = 1'b0;
      #10 
      one_A = 1'b0; one_B = 1'b0; two_A = 1'b0; two_B = 1'b1;
      #10 
      one_A = 1'b0; one_B = 1'b0; two_A = 1'b1; two_B = 1'b0;
      #10 
      one_A = 1'b0; one_B = 1'b0; two_A = 1'b1; two_B = 1'b1;
      #10 
      one_A = 1'b0; one_B = 1'b1; two_A = 1'b0; two_B = 1'b0;
      #10 
      one_A = 1'b0; one_B = 1'b1; two_A = 1'b0; two_B = 1'b1;
      #10 
      one_A = 1'b0; one_B = 1'b1; two_A = 1'b1; two_B = 1'b0;
      #10 
      one_A = 1'b0; one_B = 1'b1; two_A = 1'b1; two_B = 1'b1;
      #10 
      one_A = 1'b1; one_B = 1'b0; two_A = 1'b0; two_B = 1'b0;
      #10 
      one_A = 1'b1; one_B = 1'b0; two_A = 1'b0; two_B = 1'b1;
      #10 
      one_A = 1'b1; one_B = 1'b0; two_A = 1'b1; two_B = 1'b0;
      #10 
      one_A = 1'b1; one_B = 1'b0; two_A = 1'b1; two_B = 1'b1;
      #10 
      one_A = 1'b1; one_B = 1'b1; two_A = 1'b0; two_B = 1'b0;
      #10
      one_A = 1'b1; one_B = 1'b1; two_A = 1'b0; two_B = 1'b1;
      #10
      one_A = 1'b1; one_B = 1'b1; two_A = 1'b1; two_B = 1'b0;
      #10
      one_A = 1'b1; one_B = 1'b1; two_A = 1'b1; two_B = 1'b1;
      #10
      one_A = 1'b0; one_B = 1'b0; two_A = 1'b0; two_B = 1'b0;
      #10 $finish;
   end
endmodule