data/full_repos/permissive/208113388/dlx/ocx_dlx_tx_flt.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/208113388/dlx/ocx_dlx_tx_flt.v:360: Cannot find file containing module: 'ocx_dlx_crc'\nocx_dlx_crc crc_mod (.init (zero_crc),       \n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/208113388/dlx,data/full_repos/permissive/208113388/ocx_dlx_crc\n             data/full_repos/permissive/208113388/dlx,data/full_repos/permissive/208113388/ocx_dlx_crc.v\n             data/full_repos/permissive/208113388/dlx,data/full_repos/permissive/208113388/ocx_dlx_crc.sv\n             ocx_dlx_crc\n             ocx_dlx_crc.v\n             ocx_dlx_crc.sv\n             obj_dir/ocx_dlx_crc\n             obj_dir/ocx_dlx_crc.v\n             obj_dir/ocx_dlx_crc.sv\n%Error: data/full_repos/permissive/208113388/dlx/ocx_dlx_tx_flt.v:423: Cannot find file containing module: 'ocx_bram_infer'\n    ocx_bram_infer bram (\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ocx_dlx_tx_flt (

     dlx_reset
    ,rx_tx_sync
    ,rx_tx_lane_inverted
    ,tlx_dlx_debug_encode
    ,tlx_dlx_debug_info
    ,ctl_flt_train_done
    ,ctl_flt_stall
    ,ctl_x4_not_x8_tx_mode
    ,ctl_que_tx_ts2
    ,pulse_1us

 

    ,dlx_tlx_init_flit_depth
    ,dlx_tlx_flit_credit
    ,tlx_dlx_flit_valid
    ,tlx_dlx_flit
    ,cfg_transmit_order


    ,rx_tx_crc_error
    ,rx_tx_nack
    ,rx_tx_rx_ack_inc
    ,rx_tx_tx_ack_rtn
    ,rx_tx_tx_ack_ptr_vld
    ,rx_tx_tx_ack_ptr


    ,tx_rx_reset
    ,error_no_fwd_progress


    ,flt_que_data



    ,dlx_clk
    );

    input          dlx_reset;
    input  [7:0]   rx_tx_sync;
    input  [7:0]   rx_tx_lane_inverted;
    input  [3:0]   tlx_dlx_debug_encode;
    input  [31:0]  tlx_dlx_debug_info;

    input          ctl_flt_train_done;
    input          ctl_flt_stall;
    input          ctl_x4_not_x8_tx_mode;
    input          ctl_que_tx_ts2;
    input          pulse_1us;

    output [2:0]   dlx_tlx_init_flit_depth;
    output         dlx_tlx_flit_credit;
    input          tlx_dlx_flit_valid;
    input  [511:0] tlx_dlx_flit;
    input          cfg_transmit_order;


    input          rx_tx_crc_error;
    input          rx_tx_nack;
    input  [3:0]   rx_tx_rx_ack_inc;
    input  [4:0]   rx_tx_tx_ack_rtn;
    input          rx_tx_tx_ack_ptr_vld;
    input  [6:0]   rx_tx_tx_ack_ptr;


    output         tx_rx_reset;
    output         error_no_fwd_progress;
 

    output [511:0] flt_que_data;


    input          dlx_clk;











function [35:0] reverse36 (input [35:0] forward);
  integer i;
  for (i=0; i<=35; i=i+1)
    reverse36[35-i] = forward[i];
endfunction

    wire [511:0] flt_que_data_int;

    wire [511:0] zeros = 512'h0;
    wire         reset_din; 
    wire         no_fwd_progress; 
    reg          reset_q;
    wire [1:0]   flit_type;  
    wire [1:0]   flit_type_din;  
    reg  [1:0]   flit_type_q;
    wire [3:0]   run_length_din;
    reg  [3:0]   run_length_q;
    wire         train_done;
    wire         train_done_din;
    reg          train_done_q;
    wire [7:0]   link_errors_din;
    reg  [7:0]   link_errors_q;
    wire [7:0]   lane_inverted_din;
    reg  [7:0]   lane_inverted_q;
    wire [7:0]   sync_was_detected_din;
    reg  [7:0]   sync_was_detected_q;
    wire [63:0]  link_info_din;
    reg  [63:0]  link_info_q;
    wire [6:0]   rx_ack_ptr_din;  
    reg  [6:0] rx_ack_ptr_q;
    wire [6:0]   tx_ack_ptr_din;
    reg  [6:0] tx_ack_ptr_q;
    wire [5:0]   no_progress_cnt_din;
    reg  [5:0]   no_progress_cnt_q;
    wire [5:0]   rtn_ack_cnt_din;
    reg  [5:0]   rtn_ack_cnt_q;
    wire [5:0]   rtn_acks;
    wire         acks_sent;
    wire         max_ack_cnt;
    wire [1:0]   dl2dl_ack;
    wire         replay_start;
    wire         idle;
    wire         crc_zero_din;
    reg          crc_zero_q;
    wire         crc_zero_d1_din;
    reg          crc_zero_d1_q;
    wire         crc_zero_d2_din;
    reg          crc_zero_d2_q;


    wire         stall_d0_din;
    reg          stall_d0_q;
    wire         stall_d1_din;
    reg          stall_d1_q;
    wire         stall_d2_din;
    reg          stall_d2_q;
    wire         stall_d3_din;
    reg          stall_d3_q;
    wire         stall_d4_din;
    reg          stall_d4_q;
    wire         send_nack_din;
    reg          send_nack_q;


    wire [511:0] flit_buf0_data_din;
    wire [511:0] flit_buf1_data_din;
    wire [511:0] flit_buf2_data_din;
    wire [511:0] flit_buf3_data_din;
    reg  [511:0] flit_buf0_data_q;
    reg  [511:0] flit_buf1_data_q;
    reg  [511:0] flit_buf2_data_q;
    reg  [511:0] flit_buf3_data_q;
    wire [1:0]   flit_wr_ptr_din;
    reg  [1:0]   flit_wr_ptr_q;
    wire [1:0]   flit_rd_ptr_din;
    reg  [1:0]   flit_rd_ptr_q; 
    wire         flit_vld;
    wire         ftb_empty;
    wire         flit_vld_din;
    reg          flit_vld_q;
    wire         x4_replay_restart;
    wire         x4_replay_restart_din;
    reg          x4_replay_restart_q;
    wire         x4_replay_restart_d1_din;
    reg          x4_replay_restart_d1_q;
    wire         ftb_full_din;
    reg          ftb_full_q;
    wire [511:0] flit_data;
    wire [511:0] rpb_data;
    wire [6:0]   rpb_ecc;   
    wire [3:0]   replay_cnt_s0_din;
    reg  [3:0]   replay_cnt_s0_q;
    wire [3:0]   replay_cnt_s2_din;
    reg  [3:0]   replay_cnt_s2_q;
    wire [6:0]   rpb_wr_ptr_din;
    reg  [6:0]   rpb_wr_ptr_q;
    wire [6:0]   rpb_rd_ptr_din; 
    reg  [6:0]   rpb_rd_ptr_q; 
    wire         rpb_rd_vld_din;
    reg          rpb_rd_vld_q;
    wire         rpb_full_din;
    reg          rpb_full_q;
    wire         rpb_empty;
    wire         sbiterr;
    wire         dbiterr;
    wire         replay_done;
    wire [511:0] tlx_data;
    wire [511:0] ctl_flit;
    wire         send_ctl_flit;
    wire         init_replay_done_din;
    reg          init_replay_done_q;
    wire         nack_din;
    reg          nack_q;
    wire         nack_dly_din;
    reg          nack_dly_q;
    wire         nack_pend_din;
    reg          nack_pend_q;
    wire         dl_rp_flit_ip_din;
    reg          dl_rp_flit_ip_q;
    wire         replay_done_din; 
    reg          replay_done_q;
    wire         replay_done_dly_din; 
    reg          replay_done_dly_q;
    wire         replay_ip_din; 
    reg          replay_ip_q;
    wire [3:0]   prev_cmd_run_length;
    wire [511:0] dl2dl_replay_flit;
    wire [511:0] dl2dl_idle_flit;      
    wire [511:0] mux_data;
    wire [511:0] pre_crc_data_din;
    reg  [511:0] pre_crc_data_q;
    wire [511:0] out_data_din;
    reg  [511:0] out_data_q;
    wire [35:0]  crc_checkbits_din;
    reg  [35:0]  crc_checkbits_q;
    wire [35:0]  crc_checkbits0_out;
    wire [35:0]  crc_checkbits1_out;
    reg          flit_vld_dly_q;
    wire         flit_vld_dly_din;
    reg          ftb_empty_dly_q;
    wire         ftb_empty_dly_din;
    wire         full_idle;
    wire         tlx_input_error;
    wire [3:0]   dlx_errors;
    wire [31:0]  dlx_info;
    wire         flt_buf_underrun_din;
    reg          flt_buf_underrun_q;
    wire         flt_buf_overflow_din;
    reg          flt_buf_overflow_q;
    wire         rpb_buf_underrun_din;
    reg          rpb_buf_underrun_q;
    wire         rpb_buf_overflow_din;
    reg          rpb_buf_overflow_q;

    wire         cfg_force_crc_error;
    wire         injected_crc_error;
    wire [2:0]   injected_crc_cnt_din;
    reg  [2:0]   injected_crc_cnt_q;
    wire         zero_crc;
    wire [6:0]   replay_flit_rpb_pointer_din;
    reg  [6:0]   replay_flit_rpb_pointer_q;
    wire         init_replay_done_dly_din;
    reg          init_replay_done_dly_q;
    wire         rpb_empty_din;
    reg          rpb_empty_q;
    wire         rpb_empty_d1_din;
    reg          rpb_empty_d1_q;
    wire         send_no_replay_data_din;
    reg          send_no_replay_data_q;
    wire [7:0]   link_errors_last_din;
    reg  [7:0]   link_errors_last_q;
    wire         replay_due2_errors;
    wire         vld_switch_to_idle;
    reg          tx_rl_not_vld_q;
    wire         tx_rl_not_vld_din;
    reg          rx_ack_ptr_6_d_q;
    wire         rx_ack_ptr_6_d_din;
    reg          rx_rl_not_vld_q;
    wire         rx_rl_not_vld_din;
    reg          force_idle_flit_q;
    wire         force_idle_flit_din;
    reg          force_idle_2nd_cycle_q;
    wire         force_idle_2nd_cycle_din;
    reg          replay_after_idle_f_q;
    wire         replay_after_idle_f_din;
    reg          replay_start_q;
    wire         replay_start_din;

















assign flit_buf0_data_din[511:0] = ((flit_wr_ptr_q == 2'b00) && tlx_dlx_flit_valid) ? tlx_dlx_flit[511:0]:
                                                                                      flit_buf0_data_q[511:0];

assign flit_buf1_data_din[511:0] = ((flit_wr_ptr_q == 2'b01) && tlx_dlx_flit_valid) ? tlx_dlx_flit[511:0]:
                                                                                      flit_buf1_data_q[511:0];

assign flit_buf2_data_din[511:0] = ((flit_wr_ptr_q == 2'b10) && tlx_dlx_flit_valid) ? tlx_dlx_flit[511:0]:
                                                                                      flit_buf2_data_q[511:0];

assign flit_buf3_data_din[511:0] = ((flit_wr_ptr_q == 2'b11) && tlx_dlx_flit_valid) ? tlx_dlx_flit[511:0]:
                                                                                      flit_buf3_data_q[511:0];


assign flit_data[511:0] = (flit_rd_ptr_q == 2'b00) ? flit_buf0_data_q[511:0]: 
                          (flit_rd_ptr_q == 2'b01) ? flit_buf1_data_q[511:0]:
                          (flit_rd_ptr_q == 2'b10) ? flit_buf2_data_q[511:0]:
                                                     flit_buf3_data_q[511:0];




assign tlx_data[511:0] = (flit_type[1:0] == 2'b01) ?  rpb_data[511:0]:
                                                     flit_data[511:0];


assign mux_data[511:0] = (flit_type == 2'b10) & ~stall_d2_q ? dl2dl_replay_flit[511:0]:
                         (flit_type == 2'b01) & ~stall_d2_q ?          tlx_data[511:0]:
                         (flit_type == 2'b00) & ~stall_d2_q ?          tlx_data[511:0]:
                         (flit_type == 2'b11) & ~stall_d2_q ?   dl2dl_idle_flit[511:0]:
                                                                 pre_crc_data_q[511:0];


assign pre_crc_data_din[511:0] = stall_d2_q    ? pre_crc_data_q[511:0]:
                                 send_ctl_flit ?       ctl_flit[511:0]:
                                                       mux_data[511:0];


assign out_data_din[511:0] = pre_crc_data_q[511:0];


ocx_dlx_crc crc_mod (.init (zero_crc),       
                     .checkbits_in (crc_checkbits_q[35:0]),
                     .data (pre_crc_data_q[511:0]),
                     .checkbits0_out (crc_checkbits0_out[35:0]),
                     .checkbits1_out (crc_checkbits1_out[35:0])
                     );


assign crc_checkbits_din =  stall_d3_q ? crc_checkbits_q: 
                                         crc_checkbits0_out ^ crc_checkbits1_out;





assign flt_que_data_int[511:0] = crc_zero_d1_q & ~injected_crc_error ? {reverse36(crc_checkbits_q[35:0]), out_data_q[475:0]}:
                                 crc_zero_d1_q                       ? {reverse36({crc_checkbits_q[35:1],~crc_checkbits_q[0]}), out_data_q[475:0]}:
                                                                        out_data_q[511:0];
assign flt_que_data[511:0] = cfg_transmit_order ?  flt_que_data_int[511:0] :
                                                  {flt_que_data_int[511:496],flt_que_data_int[383:368],flt_que_data_int[255:240],flt_que_data_int[127:112],
                                                   flt_que_data_int[495:480],flt_que_data_int[367:352],flt_que_data_int[239:224],flt_que_data_int[111:096],
                                                   flt_que_data_int[479:464],flt_que_data_int[351:336],flt_que_data_int[223:208],flt_que_data_int[095:080],
                                                   flt_que_data_int[463:448],flt_que_data_int[335:320],flt_que_data_int[207:192],flt_que_data_int[079:064],
                                                   flt_que_data_int[447:432],flt_que_data_int[319:304],flt_que_data_int[191:176],flt_que_data_int[063:048],
                                                   flt_que_data_int[431:416],flt_que_data_int[303:288],flt_que_data_int[175:160],flt_que_data_int[047:032],
                                                   flt_que_data_int[415:400],flt_que_data_int[287:272],flt_que_data_int[159:144],flt_que_data_int[031:016],
                                                   flt_que_data_int[399:384],flt_que_data_int[271:256],flt_que_data_int[143:128],flt_que_data_int[015:000]};

                                                  



assign ctl_flit[511:0] = {zeros[511:476],                         /
                          rtn_acks[4:0],                          /
                          dl2dl_ack[1:0],                         /
                          mux_data[468:0]};                       /


assign dl2dl_replay_flit[511:0] = {zeros[511:476],                /
                                   rtn_acks[4:0],                 /
                                   dl2dl_ack[1:0],                /
                                   send_nack_q,                   /
                                   zeros[467:464],                /
                                   link_errors_q[7:0],            /
                                   prev_cmd_run_length[3:0],      /
                                   4'hA,                          /
                                   zeros[447:439],                /
                                   replay_flit_rpb_pointer_q,     /
                                   zeros[431:423],                /
                                   rx_ack_ptr_q[6:0],             /
                                   link_info_q[63:0],             /
                                   zeros[351:0]};             


assign dl2dl_idle_flit[511:0] = {zeros[511:476],                  /
                                 rtn_acks[4:0],                   /
                                 dl2dl_ack[1:0],                  /
                                 zeros[468:452], 
                                 4'hF,                            /
                                 zeros[447:0]};



    ocx_bram_infer bram (
         .clka (dlx_clk)
        ,.clkb      (1'b0)
        ,.ena       (1'b0)
        ,.enb       (rpb_rd_vld_q)
        ,.wea       (flit_vld_q)
        ,.addra     (rpb_wr_ptr_q[6:0])
        ,.addrb     (rpb_rd_ptr_q[6:0])
        ,.dina      (pre_crc_data_q[511:0])
        ,.doutb     (rpb_data[511:0])
        ,.dbiterr   (dbiterr)
        ,.rdaddrecc (rpb_ecc)
        ,.sbiterr   (sbiterr)
        ,.rstb      (1'b0)
        );
  




assign reset_din   = dlx_reset;
assign tx_rx_reset = reset_q;


assign stall_d0_din            = ctl_flt_stall; 
assign stall_d1_din            = stall_d0_q;
assign stall_d2_din            = stall_d1_q;
assign stall_d3_din            = stall_d2_q;
assign stall_d4_din            = stall_d3_q; 

assign train_done                 = ctl_flt_train_done & ~train_done_q;
assign train_done_din             = ctl_flt_train_done;



assign init_replay_done_dly_din = init_replay_done_q;


assign vld_switch_to_idle = (((run_length_q[3:0] - 4'h1) == 4'h0) | (flit_data[451:448] == 4'h0));

assign flit_type[1:0] = ((force_idle_flit_q & replay_start & (replay_cnt_s2_q == 4'b1000)) | (force_idle_2nd_cycle_q & ctl_x4_not_x8_tx_mode))                        ? 2'b11:
                        replay_start | ((replay_cnt_s2_q < 4'b1000) | ~ctl_flt_train_done) | ((replay_cnt_s2_q == 4'b1000) & (ctl_x4_not_x8_tx_mode & ~stall_d1_q))   ? 2'b10:
                        (replay_ip_q  | ((replay_cnt_s2_q == 4'b1000) & ~replay_done_dly_q)) & init_replay_done_dly_q & ~send_no_replay_data_q                        ? 2'b01:
                        ~ftb_empty & idle & vld_switch_to_idle                                                                                                        ? 2'b11:
                        ~ftb_empty & ~idle                                                                                                                            ? 2'b00:
                                                                                                                                                                        2'b11;

assign flit_type_din[1:0] = flit_type[1:0];



assign run_length_din[3:0] = reset_q | replay_start                                                                                   ? 4'b0000:
                             stall_d2_q                                                                                               ? run_length_q[3:0]:
                             (run_length_q[3:0] > 4'h0)                                                                               ? run_length_q[3:0] - 4'h1:
                             ((flit_type[1:0]==2'b10) && (replay_cnt_s2_q[3:0] == 4'b0111) && init_replay_done_q)
                                                                      & (rx_rl_not_vld_q & (prev_cmd_run_length[3:0] == 4'b0000))     ? 4'b0000:
                             ((flit_type[1:0]==2'b10) && (replay_cnt_s2_q[3:0] == 4'b0111) && init_replay_done_q)                     ? prev_cmd_run_length[3:0]:
                             (flit_type[1:0]==2'b00) | (flit_type[1:0]==2'b01)                                                        ? tlx_data[451:448]:
                                                                                                                                        4'b0000;         

assign send_ctl_flit         = (run_length_q[3:0] == 4'b0000) | replay_start;      

assign crc_zero_din          = stall_d2_q ? crc_zero_q:
                                            send_ctl_flit;

assign crc_zero_d1_din       = crc_zero_q;
assign crc_zero_d2_din       = crc_zero_d1_q | replay_start | replay_start_q;

assign zero_crc              = ctl_x4_not_x8_tx_mode ? crc_zero_d2_q:
                                                       crc_zero_d1_q;








assign rx_ack_ptr_din[6:0] = reset_q  ? 7'b0000000:
                                        rx_ack_ptr_q[6:0] + {3'b000, rx_tx_rx_ack_inc[3:0]};





assign rtn_ack_cnt_din[5:0] = reset_q                         ? 6'b0:
                              (rtn_ack_cnt_q[5] && acks_sent) ? {2'b0, rx_tx_rx_ack_inc[3:0]} + {1'b0, rtn_ack_cnt_q[4:0]} + 6'b000001:
                              acks_sent                       ? {2'b0, rx_tx_rx_ack_inc[3:0]}:
                                                                {2'b0, rx_tx_rx_ack_inc[3:0]} + rtn_ack_cnt_q[5:0]; 



assign rtn_acks[5:0] = rtn_ack_cnt_q[5] ? 6'b011111:
                                          rtn_ack_cnt_q[5:0];


assign acks_sent = (send_ctl_flit || flit_type[1]) && ~stall_d2_q;  



assign max_ack_cnt = (rtn_ack_cnt_q[5:4] == 2'b11);
    

assign tx_ack_ptr_din[6:0] = reset_q              ? 7'b0000000:
                             rx_tx_tx_ack_ptr_vld ? rx_tx_tx_ack_ptr[6:0]: 
                                                    tx_ack_ptr_q[6:0] + {2'b00, rx_tx_tx_ack_rtn[4:0]};

assign send_no_replay_data_din = reset_q                                                                                                                  ? 1'b0:
                                 ((ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0100)) | (~ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0011))) ? (rpb_wr_ptr_q[6:0] == tx_ack_ptr_q[6:0]): 
                                                                                                                                                            send_no_replay_data_q;


assign flit_vld = train_done_q && (flit_type[1:0] == 2'b00) && ~idle && ~stall_d2_q;

assign flit_vld_dly_din = flit_vld;
assign flit_vld_din = flit_vld;


assign dlx_tlx_flit_credit = ctl_x4_not_x8_tx_mode ? flit_vld_dly_q & ~ftb_empty_dly_q:
                                                     flit_vld;


assign dl2dl_ack[1:0] = 2'b00; 




assign flit_wr_ptr_din[1:0] = reset_q              ? 2'b0:
                              tlx_dlx_flit_valid   ? flit_wr_ptr_q[1:0] + 2'b01:
                                                     flit_wr_ptr_q[1:0];
 
assign flit_rd_ptr_din[1:0] = reset_q               ? 2'b0:
                              flit_vld & ~ftb_empty ? flit_rd_ptr_q[1:0] + 2'b01 :
                                                      flit_rd_ptr_q[1:0];



assign dlx_tlx_init_flit_depth = 3'b100;



assign ftb_full_din = ((((flit_wr_ptr_q[1:0] + 2'b01) == flit_rd_ptr_q[1:0]) && tlx_dlx_flit_valid  && ~flit_vld) ||
                        ((flit_wr_ptr_q[1:0]          == flit_rd_ptr_q[1:0]) && ftb_full_q && ~flit_vld) ||
                        ((flit_wr_ptr_q[1:0]          == flit_rd_ptr_q[1:0]) && ctl_x4_not_x8_tx_mode && ftb_full_q && ~flit_vld_dly_q))
                      & ~reset_q;


assign ftb_empty = ((flit_wr_ptr_q[1:0] == flit_rd_ptr_q[1:0]) && ~ftb_full_q);
assign ftb_empty_dly_din = ftb_empty;

assign flt_buf_overflow_din      = (flit_wr_ptr_q[1:0] == flit_rd_ptr_q[1:0]) & ftb_full_q  & tlx_dlx_flit_valid;
assign flt_buf_underrun_din      = ftb_empty & flit_vld;


 




assign rpb_full_din = (rpb_wr_ptr_q[6:4] + 3'b001) == tx_ack_ptr_q[6:4];


assign rpb_empty = ((rpb_wr_ptr_q[6:0] == rpb_rd_ptr_q[6:0]) && ~rpb_full_q);
assign rpb_empty_din = rpb_empty;
assign rpb_empty_d1_din = rpb_empty_q;


assign rpb_wr_ptr_din[6:0] = reset_q     ? 7'b0000000:
                             flit_vld_q  ? rpb_wr_ptr_q[6:0] + 7'b0000001: 
                                           rpb_wr_ptr_q[6:0];

assign rpb_rd_vld_din = (replay_cnt_s0_q[3:0] == 4'b0001)                                                                                                                  ? 1'b0:
                        ((ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0] == 4'b0110)) | (~ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0] == 4'b0100))) & init_replay_done_q  ? 1'b1:
                        ((((rpb_rd_ptr_q[6:0] + 7'b0000001) == rpb_wr_ptr_q[6:0]) & ~stall_d0_q) | rpb_empty)                                                              ? 1'b0:
                                                                                                                                                                             rpb_rd_vld_q;


assign replay_flit_rpb_pointer_din[6:0] = ((ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0100)) | (~ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0011))) ? tx_ack_ptr_q[6:0]:
                                                                                                                                                                     replay_flit_rpb_pointer_q[6:0];


assign rpb_rd_ptr_din[6:0] = reset_q                                                                                                                                              ? 7'b0000000:
                             ((ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0100)) | (~ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0011)))                             ? tx_ack_ptr_q[6:0]:
                             ((ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0101) & ~stall_d2_q) | (~ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0100) & ~stall_d0_q)) ? rpb_rd_ptr_q[6:0] - 7'b1:
                             (rpb_rd_vld_q & ~stall_d0_q)                                                                                                                         ? rpb_rd_ptr_q[6:0] + 7'b1:
                                                                                                                                                                                    rpb_rd_ptr_q[6:0];

assign tx_rl_not_vld_din           = (reset_q | tx_rl_not_vld_q) &  (tx_ack_ptr_q[6:0] == 7'b0000000);
assign rx_ack_ptr_6_d_din          = rx_ack_ptr_q[6];
assign rx_rl_not_vld_din           = (reset_q | rx_rl_not_vld_q) & ~(rx_ack_ptr_6_d_q & ~rx_ack_ptr_q[6]) ;


assign replay_done         =  (rpb_rd_ptr_q[6:0] == rpb_wr_ptr_q[6:0]) & ~stall_d0_q;
assign replay_done_din     = replay_done;
assign replay_done_dly_din = replay_done_q;

assign rpb_buf_overflow_din      = (tx_ack_ptr_q[6:0] == (rpb_wr_ptr_q[6:0] + 7'b0000001));
assign rpb_buf_underrun_din      = (rpb_rd_ptr_q[6:0] == rpb_wr_ptr_q[6:0]) & rpb_rd_vld_q & ~stall_d1_q;




assign replay_start = ((nack_dly_q || nack_q || nack_pend_q || replay_after_idle_f_q) & ~dl_rp_flit_ip_q & ~stall_d2_q & ctl_flt_train_done) | train_done;

assign replay_start_din = replay_start;



assign init_replay_done_din = ((~stall_d2_q & (replay_cnt_s2_q[3:0]==4'b1000)) | init_replay_done_q) & ~reset_q;


assign dl_rp_flit_ip_din = (replay_start & ~force_idle_flit_q) | (dl_rp_flit_ip_q & ~((ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0] == 4'h8)) | (~ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0] == 4'h7))));


assign nack_din = (rx_tx_crc_error || replay_due2_errors || (nack_q && (~replay_start || stall_d2_q || idle))) && ~reset_q; 
assign nack_dly_din = (nack_q | nack_dly_q) & ~init_replay_done_q;



assign nack_pend_din = (rx_tx_nack || (nack_pend_q && (~replay_start || stall_d2_q || idle))) && ~reset_q;

assign force_idle_flit_din = ctl_que_tx_ts2                                          ? 1'b0:
                             nack_pend_q & (replay_cnt_s2_q == 4'b0110)              ? 1'b1:
                             (flit_type[1:0] == 2'b11)                               ? 1'b0:
                                                                                       force_idle_flit_q;

assign force_idle_2nd_cycle_din = force_idle_flit_q & replay_start;

assign replay_after_idle_f_din = ((force_idle_flit_q & replay_start) | replay_after_idle_f_q) & ~(replay_cnt_s2_q == 4'b0010) ;



assign send_nack_din = nack_q || (send_nack_q && ~(replay_cnt_s2_q[3] == 1'b1)); 
    

assign replay_cnt_s0_din[3:0] = reset_q                                                             ? 4'b0000:
                                                         replay_start & ~stall_d0_q & ~stall_d1_q   ? 4'b0000:
                                ~ctl_x4_not_x8_tx_mode & replay_start & ~stall_d0_q &  stall_d1_q   ? 4'b1111:
                                                         replay_start &  stall_d0_q & ~stall_d1_q   ? 4'b1111:
                                ~ctl_x4_not_x8_tx_mode & replay_start &  stall_d0_q &  stall_d1_q   ? 4'b1110:
                                 ctl_x4_not_x8_tx_mode & replay_start &  stall_d0_q                 ? 4'b1111:
                                 ctl_x4_not_x8_tx_mode & replay_start                               ? 4'b0000:
                                stall_d0_q                                                          ? replay_cnt_s0_q[3:0]:
                                (replay_cnt_s0_q[3] == 1'b0) | (replay_cnt_s0_q[3:2] == 2'b11)      ? replay_cnt_s0_q[3:0] + 4'h1:
                                                                                                      4'b1011;

assign x4_replay_restart_din     = (x4_replay_restart_q | ((replay_cnt_s2_q[3:0] == 4'b0010) & ctl_x4_not_x8_tx_mode & ~init_replay_done_q)) & ~reset_q;
assign x4_replay_restart_d1_din  = x4_replay_restart_q;
assign x4_replay_restart         = x4_replay_restart_q & ~x4_replay_restart_d1_q;


assign replay_cnt_s2_din[3:0] = reset_q                                    ? 4'b1111:
                                (replay_start | x4_replay_restart)         ? 4'b0000:
                                stall_d2_q                                 ? replay_cnt_s2_q[3:0]:
                                (replay_cnt_s2_q[3:0] <= 4'h7)             ? replay_cnt_s2_q[3:0] + 4'h1:
                                                                             4'b1111;
           

assign replay_ip_din = ((((replay_cnt_s2_q[3:0] == 4'b1000) && ~stall_d2_q) || replay_ip_q) && ~replay_done_q && ~(replay_start || reset_q || ~init_replay_done_dly_q)); 



assign full_idle = ((rpb_full_q) && send_ctl_flit && ~(replay_start || replay_ip_q || dl_rp_flit_ip_q));
assign idle      = reset_q || max_ack_cnt || ((full_idle || ftb_empty) && ~(replay_start || replay_ip_din || replay_ip_q || dl_rp_flit_ip_q));



assign prev_cmd_run_length[3:0]  = (replay_cnt_s2_q[3:0] == 4'b0111) & init_replay_done_dly_q & ~tx_rl_not_vld_q & ~force_idle_flit_q & ~nack_pend_q ? rpb_data[451:448]:
                                                                                                                                                      4'b0000;
 





assign no_progress_cnt_din[5:0]  = (flit_vld | ~train_done_q)  ? 6'b000000                          :
                                   (pulse_1us & ~ftb_empty)    ? no_progress_cnt_q[5:0] + 6'b000001 :
                                                                 no_progress_cnt_q[5:0]; 

assign no_fwd_progress           = train_done_q & no_progress_cnt_q[3];
assign error_no_fwd_progress     = no_fwd_progress;


assign tlx_input_error = ftb_empty & (run_length_din[3:0]==4'b0000) & (flit_type[1:0]==2'b00);

assign dlx_errors[3:0]      = {(flt_buf_underrun_q | flt_buf_overflow_q | rpb_buf_underrun_q | rpb_buf_overflow_q | tlx_input_error ), no_fwd_progress, 1'b0, 1'b0};

assign dlx_info[31:0]       =  {flt_buf_underrun_q,
                                flt_buf_overflow_q,
                                rpb_buf_underrun_q,
                                rpb_buf_overflow_q,
                                tlx_input_error,
                                3'b000,
                                no_fwd_progress,
                                7'b0,
                                lane_inverted_q[7:0], sync_was_detected_q[7:0] };


assign sync_was_detected_din[7:0] =  reset_q   ?  8'b00000000         :
                                                  (rx_tx_sync[7:0] | sync_was_detected_q[7:0]);


assign lane_inverted_din[7:0]    =  rx_tx_lane_inverted[7:0];

assign link_errors_din[7:0]      = {dlx_errors[3:0],tlx_dlx_debug_encode[3:0]};
assign link_errors_last_din[7:0] = link_errors_q[7:0];
assign link_info_din[63:0]       = {dlx_info[31:0] ,tlx_dlx_debug_info[31:0]};

assign replay_due2_errors        = ~(link_errors_q[7:0] == link_errors_last_din[7:0]);




assign cfg_force_crc_error       = 1'b0; 
assign injected_crc_error        =  cfg_force_crc_error & (out_data_q[11:0] == 12'h3C0) & (injected_crc_cnt_q[2:0] == 3'b0);
assign injected_crc_cnt_din[2:0] = (cfg_force_crc_error & (out_data_q[11:0] == 12'h3C0)) ? injected_crc_cnt_q[2:0] + 3'b1 :
                                                                                           injected_crc_cnt_q[2:0];



    always @(posedge dlx_clk) begin
      injected_crc_cnt_q[2:0]  <= injected_crc_cnt_din[2:0];
      crc_zero_q               <= crc_zero_din;
      crc_zero_d1_q            <= crc_zero_d1_din;
      crc_zero_d2_q            <= crc_zero_d2_din;

      crc_checkbits_q[35:0]    <= crc_checkbits_din[35:0];
      dl_rp_flit_ip_q          <= dl_rp_flit_ip_din;
      flit_buf0_data_q[511:0]  <= ((flit_wr_ptr_q == 2'b00) && tlx_dlx_flit_valid) ? flit_buf0_data_din[511:0] : flit_buf0_data_q[511:0];
      flit_buf1_data_q[511:0]  <= ((flit_wr_ptr_q == 2'b01) && tlx_dlx_flit_valid) ? flit_buf1_data_din[511:0] : flit_buf1_data_q[511:0];
      flit_buf2_data_q[511:0]  <= ((flit_wr_ptr_q == 2'b10) && tlx_dlx_flit_valid) ? flit_buf2_data_din[511:0] : flit_buf2_data_q[511:0];
      flit_buf3_data_q[511:0]  <= ((flit_wr_ptr_q == 2'b11) && tlx_dlx_flit_valid) ? flit_buf3_data_din[511:0] : flit_buf3_data_q[511:0];
      flit_rd_ptr_q[1:0]       <= flit_rd_ptr_din[1:0];
      flit_vld_q              <= flit_vld_din;
      flit_type_q[1:0]         <= flit_type_din[1:0];
      flit_wr_ptr_q[1:0]       <= flit_wr_ptr_din[1:0];
      ftb_full_q               <= ftb_full_din;
      link_errors_q[7:0]       <= link_errors_din[7:0];
      lane_inverted_q[7:0]     <= lane_inverted_din[7:0];
      sync_was_detected_q[7:0] <= sync_was_detected_din[7:0];
      link_info_q[63:0]        <= link_info_din[63:0];
      nack_pend_q              <= nack_pend_din;
      nack_q                   <= nack_din;
      nack_dly_q               <= nack_dly_din;
      init_replay_done_q       <= init_replay_done_din;
      out_data_q[511:0]        <= out_data_din[511:0];
      pre_crc_data_q[511:0]    <= pre_crc_data_din[511:0];
      replay_cnt_s0_q[3:0]     <= replay_cnt_s0_din[3:0];
      replay_cnt_s2_q[3:0]     <= replay_cnt_s2_din[3:0];
      x4_replay_restart_q      <= x4_replay_restart_din;
      x4_replay_restart_d1_q   <= x4_replay_restart_d1_din;
      replay_done_q            <= replay_done_din;
      replay_done_dly_q        <= replay_done_dly_din;
      replay_ip_q              <= replay_ip_din; 
      reset_q                  <= reset_din;
      rpb_full_q               <= rpb_full_din;
      rpb_rd_ptr_q[6:0]        <= rpb_rd_ptr_din[6:0];
      rpb_rd_vld_q             <= rpb_rd_vld_din;
      rpb_wr_ptr_q[6:0]        <= rpb_wr_ptr_din[6:0];
      rtn_ack_cnt_q[5:0]       <= rtn_ack_cnt_din[5:0];
      run_length_q[3:0]        <= run_length_din[3:0];
      rx_ack_ptr_q[6:0]        <= rx_ack_ptr_din[6:0];
      send_nack_q              <= send_nack_din;
      stall_d0_q               <= stall_d0_din;
      stall_d1_q               <= stall_d1_din;
      stall_d2_q               <= stall_d2_din;
      stall_d3_q               <= stall_d3_din;
      stall_d4_q               <= stall_d4_din;
      train_done_q             <= train_done_din;
      tx_ack_ptr_q[6:0]        <= tx_ack_ptr_din[6:0];
      no_progress_cnt_q[5:0]   <= no_progress_cnt_din[5:0];
      flt_buf_underrun_q       <= flt_buf_underrun_din;
      flt_buf_overflow_q       <= flt_buf_overflow_din;
      rpb_buf_underrun_q       <= rpb_buf_underrun_din;
      rpb_buf_overflow_q       <= rpb_buf_overflow_din;
      flit_vld_dly_q           <= flit_vld_dly_din;
      ftb_empty_dly_q          <= ftb_empty_dly_din;
      replay_flit_rpb_pointer_q[6:0] <= replay_flit_rpb_pointer_din[6:0];
      init_replay_done_dly_q   <= init_replay_done_dly_din;
      rpb_empty_q              <= rpb_empty_din;
      rpb_empty_d1_q           <= rpb_empty_d1_din;
      send_no_replay_data_q    <= send_no_replay_data_din;
      link_errors_last_q       <= link_errors_last_din;
      tx_rl_not_vld_q          <= tx_rl_not_vld_din;
      rx_ack_ptr_6_d_q         <= rx_ack_ptr_6_d_din;
      rx_rl_not_vld_q          <= rx_rl_not_vld_din;
      force_idle_flit_q        <= force_idle_flit_din;
      force_idle_2nd_cycle_q   <= force_idle_2nd_cycle_din;
      replay_after_idle_f_q    <= replay_after_idle_f_din;
      replay_start_q           <= replay_start_din;
    end

endmodule
module ocx_dlx_tx_flt (

     dlx_reset
    ,rx_tx_sync
    ,rx_tx_lane_inverted
    ,tlx_dlx_debug_encode
    ,tlx_dlx_debug_info
    ,ctl_flt_train_done
    ,ctl_flt_stall
    ,ctl_x4_not_x8_tx_mode
    ,ctl_que_tx_ts2
    ,pulse_1us

 

    ,dlx_tlx_init_flit_depth
    ,dlx_tlx_flit_credit
    ,tlx_dlx_flit_valid
    ,tlx_dlx_flit
    ,cfg_transmit_order


    ,rx_tx_crc_error
    ,rx_tx_nack
    ,rx_tx_rx_ack_inc
    ,rx_tx_tx_ack_rtn
    ,rx_tx_tx_ack_ptr_vld
    ,rx_tx_tx_ack_ptr


    ,tx_rx_reset
    ,error_no_fwd_progress


    ,flt_que_data



    ,dlx_clk
    );


    input          dlx_reset;
    input  [7:0]   rx_tx_sync;
    input  [7:0]   rx_tx_lane_inverted;
    input  [3:0]   tlx_dlx_debug_encode;
    input  [31:0]  tlx_dlx_debug_info;

    input          ctl_flt_train_done;
    input          ctl_flt_stall;
    input          ctl_x4_not_x8_tx_mode;
    input          ctl_que_tx_ts2;
    input          pulse_1us;

    output [2:0]   dlx_tlx_init_flit_depth;
    output         dlx_tlx_flit_credit;
    input          tlx_dlx_flit_valid;
    input  [511:0] tlx_dlx_flit;
    input          cfg_transmit_order;


    input          rx_tx_crc_error;
    input          rx_tx_nack;
    input  [3:0]   rx_tx_rx_ack_inc;
    input  [4:0]   rx_tx_tx_ack_rtn;
    input          rx_tx_tx_ack_ptr_vld;
    input  [6:0]   rx_tx_tx_ack_ptr;


    output         tx_rx_reset;
    output         error_no_fwd_progress;
 

    output [511:0] flt_que_data;


    input          dlx_clk;











function [35:0] reverse36 (input [35:0] forward);
  integer i;
  for (i=0; i<=35; i=i+1)
    reverse36[35-i] = forward[i];
endfunction

    wire [511:0] flt_que_data_int;

    wire [511:0] zeros = 512'h0;
    wire         reset_din; 
    wire         no_fwd_progress; 
    reg          reset_q;
    wire [1:0]   flit_type;  
    wire [1:0]   flit_type_din;  
    reg  [1:0]   flit_type_q;
    wire [3:0]   run_length_din;
    reg  [3:0]   run_length_q;
    wire         train_done;
    wire         train_done_din;
    reg          train_done_q;
    wire [7:0]   link_errors_din;
    reg  [7:0]   link_errors_q;
    wire [7:0]   lane_inverted_din;
    reg  [7:0]   lane_inverted_q;
    wire [7:0]   sync_was_detected_din;
    reg  [7:0]   sync_was_detected_q;
    wire [63:0]  link_info_din;
    reg  [63:0]  link_info_q;
    wire [6:0]   rx_ack_ptr_din;  
    reg  [6:0] rx_ack_ptr_q;
    wire [6:0]   tx_ack_ptr_din;
    reg  [6:0] tx_ack_ptr_q;
    wire [5:0]   no_progress_cnt_din;
    reg  [5:0]   no_progress_cnt_q;
    wire [5:0]   rtn_ack_cnt_din;
    reg  [5:0]   rtn_ack_cnt_q;
    wire [5:0]   rtn_acks;
    wire         acks_sent;
    wire         max_ack_cnt;
    wire [1:0]   dl2dl_ack;
    wire         replay_start;
    wire         idle;
    wire         crc_zero_din;
    reg          crc_zero_q;
    wire         crc_zero_d1_din;
    reg          crc_zero_d1_q;
    wire         crc_zero_d2_din;
    reg          crc_zero_d2_q;


    wire         stall_d0_din;
    reg          stall_d0_q;
    wire         stall_d1_din;
    reg          stall_d1_q;
    wire         stall_d2_din;
    reg          stall_d2_q;
    wire         stall_d3_din;
    reg          stall_d3_q;
    wire         stall_d4_din;
    reg          stall_d4_q;
    wire         send_nack_din;
    reg          send_nack_q;


    wire [511:0] flit_buf0_data_din;
    wire [511:0] flit_buf1_data_din;
    wire [511:0] flit_buf2_data_din;
    wire [511:0] flit_buf3_data_din;
    reg  [511:0] flit_buf0_data_q;
    reg  [511:0] flit_buf1_data_q;
    reg  [511:0] flit_buf2_data_q;
    reg  [511:0] flit_buf3_data_q;
    wire [1:0]   flit_wr_ptr_din;
    reg  [1:0]   flit_wr_ptr_q;
    wire [1:0]   flit_rd_ptr_din;
    reg  [1:0]   flit_rd_ptr_q; 
    wire         flit_vld;
    wire         ftb_empty;
    wire         flit_vld_din;
    reg          flit_vld_q;
    wire         x4_replay_restart;
    wire         x4_replay_restart_din;
    reg          x4_replay_restart_q;
    wire         x4_replay_restart_d1_din;
    reg          x4_replay_restart_d1_q;
    wire         ftb_full_din;
    reg          ftb_full_q;
    wire [511:0] flit_data;
    wire [511:0] rpb_data;
    wire [6:0]   rpb_ecc;   
    wire [3:0]   replay_cnt_s0_din;
    reg  [3:0]   replay_cnt_s0_q;
    wire [3:0]   replay_cnt_s2_din;
    reg  [3:0]   replay_cnt_s2_q;
    wire [6:0]   rpb_wr_ptr_din;
    reg  [6:0]   rpb_wr_ptr_q;
    wire [6:0]   rpb_rd_ptr_din; 
    reg  [6:0]   rpb_rd_ptr_q; 
    wire         rpb_rd_vld_din;
    reg          rpb_rd_vld_q;
    wire         rpb_full_din;
    reg          rpb_full_q;
    wire         rpb_empty;
    wire         sbiterr;
    wire         dbiterr;
    wire         replay_done;
    wire [511:0] tlx_data;
    wire [511:0] ctl_flit;
    wire         send_ctl_flit;
    wire         init_replay_done_din;
    reg          init_replay_done_q;
    wire         nack_din;
    reg          nack_q;
    wire         nack_dly_din;
    reg          nack_dly_q;
    wire         nack_pend_din;
    reg          nack_pend_q;
    wire         dl_rp_flit_ip_din;
    reg          dl_rp_flit_ip_q;
    wire         replay_done_din; 
    reg          replay_done_q;
    wire         replay_done_dly_din; 
    reg          replay_done_dly_q;
    wire         replay_ip_din; 
    reg          replay_ip_q;
    wire [3:0]   prev_cmd_run_length;
    wire [511:0] dl2dl_replay_flit;
    wire [511:0] dl2dl_idle_flit;      
    wire [511:0] mux_data;
    wire [511:0] pre_crc_data_din;
    reg  [511:0] pre_crc_data_q;
    wire [511:0] out_data_din;
    reg  [511:0] out_data_q;
    wire [35:0]  crc_checkbits_din;
    reg  [35:0]  crc_checkbits_q;
    wire [35:0]  crc_checkbits0_out;
    wire [35:0]  crc_checkbits1_out;
    reg          flit_vld_dly_q;
    wire         flit_vld_dly_din;
    reg          ftb_empty_dly_q;
    wire         ftb_empty_dly_din;
    wire         full_idle;
    wire         tlx_input_error;
    wire [3:0]   dlx_errors;
    wire [31:0]  dlx_info;
    wire         flt_buf_underrun_din;
    reg          flt_buf_underrun_q;
    wire         flt_buf_overflow_din;
    reg          flt_buf_overflow_q;
    wire         rpb_buf_underrun_din;
    reg          rpb_buf_underrun_q;
    wire         rpb_buf_overflow_din;
    reg          rpb_buf_overflow_q;

    wire         cfg_force_crc_error;
    wire         injected_crc_error;
    wire [2:0]   injected_crc_cnt_din;
    reg  [2:0]   injected_crc_cnt_q;
    wire         zero_crc;
    wire [6:0]   replay_flit_rpb_pointer_din;
    reg  [6:0]   replay_flit_rpb_pointer_q;
    wire         init_replay_done_dly_din;
    reg          init_replay_done_dly_q;
    wire         rpb_empty_din;
    reg          rpb_empty_q;
    wire         rpb_empty_d1_din;
    reg          rpb_empty_d1_q;
    wire         send_no_replay_data_din;
    reg          send_no_replay_data_q;
    wire [7:0]   link_errors_last_din;
    reg  [7:0]   link_errors_last_q;
    wire         replay_due2_errors;
    wire         vld_switch_to_idle;
    reg          tx_rl_not_vld_q;
    wire         tx_rl_not_vld_din;
    reg          rx_ack_ptr_6_d_q;
    wire         rx_ack_ptr_6_d_din;
    reg          rx_rl_not_vld_q;
    wire         rx_rl_not_vld_din;
    reg          force_idle_flit_q;
    wire         force_idle_flit_din;
    reg          force_idle_2nd_cycle_q;
    wire         force_idle_2nd_cycle_din;
    reg          replay_after_idle_f_q;
    wire         replay_after_idle_f_din;
    reg          replay_start_q;
    wire         replay_start_din;

















assign flit_buf0_data_din[511:0] = ((flit_wr_ptr_q == 2'b00) && tlx_dlx_flit_valid) ? tlx_dlx_flit[511:0]:
                                                                                      flit_buf0_data_q[511:0];

assign flit_buf1_data_din[511:0] = ((flit_wr_ptr_q == 2'b01) && tlx_dlx_flit_valid) ? tlx_dlx_flit[511:0]:
                                                                                      flit_buf1_data_q[511:0];

assign flit_buf2_data_din[511:0] = ((flit_wr_ptr_q == 2'b10) && tlx_dlx_flit_valid) ? tlx_dlx_flit[511:0]:
                                                                                      flit_buf2_data_q[511:0];

assign flit_buf3_data_din[511:0] = ((flit_wr_ptr_q == 2'b11) && tlx_dlx_flit_valid) ? tlx_dlx_flit[511:0]:
                                                                                      flit_buf3_data_q[511:0];


assign flit_data[511:0] = (flit_rd_ptr_q == 2'b00) ? flit_buf0_data_q[511:0]: 
                          (flit_rd_ptr_q == 2'b01) ? flit_buf1_data_q[511:0]:
                          (flit_rd_ptr_q == 2'b10) ? flit_buf2_data_q[511:0]:
                                                     flit_buf3_data_q[511:0];




assign tlx_data[511:0] = (flit_type[1:0] == 2'b01) ?  rpb_data[511:0]:
                                                     flit_data[511:0];


assign mux_data[511:0] = (flit_type == 2'b10) & ~stall_d2_q ? dl2dl_replay_flit[511:0]:
                         (flit_type == 2'b01) & ~stall_d2_q ?          tlx_data[511:0]:
                         (flit_type == 2'b00) & ~stall_d2_q ?          tlx_data[511:0]:
                         (flit_type == 2'b11) & ~stall_d2_q ?   dl2dl_idle_flit[511:0]:
                                                                 pre_crc_data_q[511:0];


assign pre_crc_data_din[511:0] = stall_d2_q    ? pre_crc_data_q[511:0]:
                                 send_ctl_flit ?       ctl_flit[511:0]:
                                                       mux_data[511:0];


assign out_data_din[511:0] = pre_crc_data_q[511:0];


ocx_dlx_crc crc_mod (.init (zero_crc),       
                     .checkbits_in (crc_checkbits_q[35:0]),
                     .data (pre_crc_data_q[511:0]),
                     .checkbits0_out (crc_checkbits0_out[35:0]),
                     .checkbits1_out (crc_checkbits1_out[35:0])
                     );


assign crc_checkbits_din =  stall_d3_q ? crc_checkbits_q: 
                                         crc_checkbits0_out ^ crc_checkbits1_out;





assign flt_que_data_int[511:0] = crc_zero_d1_q & ~injected_crc_error ? {reverse36(crc_checkbits_q[35:0]), out_data_q[475:0]}:
                                 crc_zero_d1_q                       ? {reverse36({crc_checkbits_q[35:1],~crc_checkbits_q[0]}), out_data_q[475:0]}:
                                                                        out_data_q[511:0];
assign flt_que_data[511:0] = cfg_transmit_order ?  flt_que_data_int[511:0] :
                                                  {flt_que_data_int[511:496],flt_que_data_int[383:368],flt_que_data_int[255:240],flt_que_data_int[127:112],
                                                   flt_que_data_int[495:480],flt_que_data_int[367:352],flt_que_data_int[239:224],flt_que_data_int[111:096],
                                                   flt_que_data_int[479:464],flt_que_data_int[351:336],flt_que_data_int[223:208],flt_que_data_int[095:080],
                                                   flt_que_data_int[463:448],flt_que_data_int[335:320],flt_que_data_int[207:192],flt_que_data_int[079:064],
                                                   flt_que_data_int[447:432],flt_que_data_int[319:304],flt_que_data_int[191:176],flt_que_data_int[063:048],
                                                   flt_que_data_int[431:416],flt_que_data_int[303:288],flt_que_data_int[175:160],flt_que_data_int[047:032],
                                                   flt_que_data_int[415:400],flt_que_data_int[287:272],flt_que_data_int[159:144],flt_que_data_int[031:016],
                                                   flt_que_data_int[399:384],flt_que_data_int[271:256],flt_que_data_int[143:128],flt_que_data_int[015:000]};

                                                  



assign ctl_flit[511:0] = {zeros[511:476],                         /
                          rtn_acks[4:0],                          /
                          dl2dl_ack[1:0],                         /
                          mux_data[468:0]};                       /


assign dl2dl_replay_flit[511:0] = {zeros[511:476],                /
                                   rtn_acks[4:0],                 /
                                   dl2dl_ack[1:0],                /
                                   send_nack_q,                   /
                                   zeros[467:464],                /
                                   link_errors_q[7:0],            /
                                   prev_cmd_run_length[3:0],      /
                                   4'hA,                          /
                                   zeros[447:439],                /
                                   replay_flit_rpb_pointer_q,     /
                                   zeros[431:423],                /
                                   rx_ack_ptr_q[6:0],             /
                                   link_info_q[63:0],             /
                                   zeros[351:0]};             


assign dl2dl_idle_flit[511:0] = {zeros[511:476],                  /
                                 rtn_acks[4:0],                   /
                                 dl2dl_ack[1:0],                  /
                                 zeros[468:452], 
                                 4'hF,                            /
                                 zeros[447:0]};



    ocx_bram_infer bram (
         .clka (dlx_clk)
        ,.clkb      (1'b0)
        ,.ena       (1'b0)
        ,.enb       (rpb_rd_vld_q)
        ,.wea       (flit_vld_q)
        ,.addra     (rpb_wr_ptr_q[6:0])
        ,.addrb     (rpb_rd_ptr_q[6:0])
        ,.dina      (pre_crc_data_q[511:0])
        ,.doutb     (rpb_data[511:0])
        ,.dbiterr   (dbiterr)
        ,.rdaddrecc (rpb_ecc)
        ,.sbiterr   (sbiterr)
        ,.rstb      (1'b0)
        );
  




assign reset_din   = dlx_reset;
assign tx_rx_reset = reset_q;


assign stall_d0_din            = ctl_flt_stall; 
assign stall_d1_din            = stall_d0_q;
assign stall_d2_din            = stall_d1_q;
assign stall_d3_din            = stall_d2_q;
assign stall_d4_din            = stall_d3_q; 

assign train_done                 = ctl_flt_train_done & ~train_done_q;
assign train_done_din             = ctl_flt_train_done;



assign init_replay_done_dly_din = init_replay_done_q;


assign vld_switch_to_idle = (((run_length_q[3:0] - 4'h1) == 4'h0) | (flit_data[451:448] == 4'h0));

assign flit_type[1:0] = ((force_idle_flit_q & replay_start & (replay_cnt_s2_q == 4'b1000)) | (force_idle_2nd_cycle_q & ctl_x4_not_x8_tx_mode))                        ? 2'b11:
                        replay_start | ((replay_cnt_s2_q < 4'b1000) | ~ctl_flt_train_done) | ((replay_cnt_s2_q == 4'b1000) & (ctl_x4_not_x8_tx_mode & ~stall_d1_q))   ? 2'b10:
                        (replay_ip_q  | ((replay_cnt_s2_q == 4'b1000) & ~replay_done_dly_q)) & init_replay_done_dly_q & ~send_no_replay_data_q                        ? 2'b01:
                        ~ftb_empty & idle & vld_switch_to_idle                                                                                                        ? 2'b11:
                        ~ftb_empty & ~idle                                                                                                                            ? 2'b00:
                                                                                                                                                                        2'b11;

assign flit_type_din[1:0] = flit_type[1:0];



assign run_length_din[3:0] = reset_q | replay_start                                                                                   ? 4'b0000:
                             stall_d2_q                                                                                               ? run_length_q[3:0]:
                             (run_length_q[3:0] > 4'h0)                                                                               ? run_length_q[3:0] - 4'h1:
                             ((flit_type[1:0]==2'b10) && (replay_cnt_s2_q[3:0] == 4'b0111) && init_replay_done_q)
                                                                      & (rx_rl_not_vld_q & (prev_cmd_run_length[3:0] == 4'b0000))     ? 4'b0000:
                             ((flit_type[1:0]==2'b10) && (replay_cnt_s2_q[3:0] == 4'b0111) && init_replay_done_q)                     ? prev_cmd_run_length[3:0]:
                             (flit_type[1:0]==2'b00) | (flit_type[1:0]==2'b01)                                                        ? tlx_data[451:448]:
                                                                                                                                        4'b0000;         

assign send_ctl_flit         = (run_length_q[3:0] == 4'b0000) | replay_start;      

assign crc_zero_din          = stall_d2_q ? crc_zero_q:
                                            send_ctl_flit;

assign crc_zero_d1_din       = crc_zero_q;
assign crc_zero_d2_din       = crc_zero_d1_q | replay_start | replay_start_q;

assign zero_crc              = ctl_x4_not_x8_tx_mode ? crc_zero_d2_q:
                                                       crc_zero_d1_q;








assign rx_ack_ptr_din[6:0] = reset_q  ? 7'b0000000:
                                        rx_ack_ptr_q[6:0] + {3'b000, rx_tx_rx_ack_inc[3:0]};





assign rtn_ack_cnt_din[5:0] = reset_q                         ? 6'b0:
                              (rtn_ack_cnt_q[5] && acks_sent) ? {2'b0, rx_tx_rx_ack_inc[3:0]} + {1'b0, rtn_ack_cnt_q[4:0]} + 6'b000001:
                              acks_sent                       ? {2'b0, rx_tx_rx_ack_inc[3:0]}:
                                                                {2'b0, rx_tx_rx_ack_inc[3:0]} + rtn_ack_cnt_q[5:0]; 



assign rtn_acks[5:0] = rtn_ack_cnt_q[5] ? 6'b011111:
                                          rtn_ack_cnt_q[5:0];


assign acks_sent = (send_ctl_flit || flit_type[1]) && ~stall_d2_q;  



assign max_ack_cnt = (rtn_ack_cnt_q[5:4] == 2'b11);
    

assign tx_ack_ptr_din[6:0] = reset_q              ? 7'b0000000:
                             rx_tx_tx_ack_ptr_vld ? rx_tx_tx_ack_ptr[6:0]: 
                                                    tx_ack_ptr_q[6:0] + {2'b00, rx_tx_tx_ack_rtn[4:0]};

assign send_no_replay_data_din = reset_q                                                                                                                  ? 1'b0:
                                 ((ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0100)) | (~ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0011))) ? (rpb_wr_ptr_q[6:0] == tx_ack_ptr_q[6:0]): 
                                                                                                                                                            send_no_replay_data_q;


assign flit_vld = train_done_q && (flit_type[1:0] == 2'b00) && ~idle && ~stall_d2_q;

assign flit_vld_dly_din = flit_vld;
assign flit_vld_din = flit_vld;


assign dlx_tlx_flit_credit = ctl_x4_not_x8_tx_mode ? flit_vld_dly_q & ~ftb_empty_dly_q:
                                                     flit_vld;


assign dl2dl_ack[1:0] = 2'b00; 




assign flit_wr_ptr_din[1:0] = reset_q              ? 2'b0:
                              tlx_dlx_flit_valid   ? flit_wr_ptr_q[1:0] + 2'b01:
                                                     flit_wr_ptr_q[1:0];
 
assign flit_rd_ptr_din[1:0] = reset_q               ? 2'b0:
                              flit_vld & ~ftb_empty ? flit_rd_ptr_q[1:0] + 2'b01 :
                                                      flit_rd_ptr_q[1:0];



assign dlx_tlx_init_flit_depth = 3'b100;



assign ftb_full_din = ((((flit_wr_ptr_q[1:0] + 2'b01) == flit_rd_ptr_q[1:0]) && tlx_dlx_flit_valid  && ~flit_vld) ||
                        ((flit_wr_ptr_q[1:0]          == flit_rd_ptr_q[1:0]) && ftb_full_q && ~flit_vld) ||
                        ((flit_wr_ptr_q[1:0]          == flit_rd_ptr_q[1:0]) && ctl_x4_not_x8_tx_mode && ftb_full_q && ~flit_vld_dly_q))
                      & ~reset_q;


assign ftb_empty = ((flit_wr_ptr_q[1:0] == flit_rd_ptr_q[1:0]) && ~ftb_full_q);
assign ftb_empty_dly_din = ftb_empty;

assign flt_buf_overflow_din      = (flit_wr_ptr_q[1:0] == flit_rd_ptr_q[1:0]) & ftb_full_q  & tlx_dlx_flit_valid;
assign flt_buf_underrun_din      = ftb_empty & flit_vld;


 




assign rpb_full_din = (rpb_wr_ptr_q[6:4] + 3'b001) == tx_ack_ptr_q[6:4];


assign rpb_empty = ((rpb_wr_ptr_q[6:0] == rpb_rd_ptr_q[6:0]) && ~rpb_full_q);
assign rpb_empty_din = rpb_empty;
assign rpb_empty_d1_din = rpb_empty_q;


assign rpb_wr_ptr_din[6:0] = reset_q     ? 7'b0000000:
                             flit_vld_q  ? rpb_wr_ptr_q[6:0] + 7'b0000001: 
                                           rpb_wr_ptr_q[6:0];

assign rpb_rd_vld_din = (replay_cnt_s0_q[3:0] == 4'b0001)                                                                                                                  ? 1'b0:
                        ((ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0] == 4'b0110)) | (~ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0] == 4'b0100))) & init_replay_done_q  ? 1'b1:
                        ((((rpb_rd_ptr_q[6:0] + 7'b0000001) == rpb_wr_ptr_q[6:0]) & ~stall_d0_q) | rpb_empty)                                                              ? 1'b0:
                                                                                                                                                                             rpb_rd_vld_q;


assign replay_flit_rpb_pointer_din[6:0] = ((ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0100)) | (~ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0011))) ? tx_ack_ptr_q[6:0]:
                                                                                                                                                                     replay_flit_rpb_pointer_q[6:0];


assign rpb_rd_ptr_din[6:0] = reset_q                                                                                                                                              ? 7'b0000000:
                             ((ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0100)) | (~ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0011)))                             ? tx_ack_ptr_q[6:0]:
                             ((ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0101) & ~stall_d2_q) | (~ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0]==4'b0100) & ~stall_d0_q)) ? rpb_rd_ptr_q[6:0] - 7'b1:
                             (rpb_rd_vld_q & ~stall_d0_q)                                                                                                                         ? rpb_rd_ptr_q[6:0] + 7'b1:
                                                                                                                                                                                    rpb_rd_ptr_q[6:0];

assign tx_rl_not_vld_din           = (reset_q | tx_rl_not_vld_q) &  (tx_ack_ptr_q[6:0] == 7'b0000000);
assign rx_ack_ptr_6_d_din          = rx_ack_ptr_q[6];
assign rx_rl_not_vld_din           = (reset_q | rx_rl_not_vld_q) & ~(rx_ack_ptr_6_d_q & ~rx_ack_ptr_q[6]) ;


assign replay_done         =  (rpb_rd_ptr_q[6:0] == rpb_wr_ptr_q[6:0]) & ~stall_d0_q;
assign replay_done_din     = replay_done;
assign replay_done_dly_din = replay_done_q;

assign rpb_buf_overflow_din      = (tx_ack_ptr_q[6:0] == (rpb_wr_ptr_q[6:0] + 7'b0000001));
assign rpb_buf_underrun_din      = (rpb_rd_ptr_q[6:0] == rpb_wr_ptr_q[6:0]) & rpb_rd_vld_q & ~stall_d1_q;




assign replay_start = ((nack_dly_q || nack_q || nack_pend_q || replay_after_idle_f_q) & ~dl_rp_flit_ip_q & ~stall_d2_q & ctl_flt_train_done) | train_done;

assign replay_start_din = replay_start;



assign init_replay_done_din = ((~stall_d2_q & (replay_cnt_s2_q[3:0]==4'b1000)) | init_replay_done_q) & ~reset_q;


assign dl_rp_flit_ip_din = (replay_start & ~force_idle_flit_q) | (dl_rp_flit_ip_q & ~((ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0] == 4'h8)) | (~ctl_x4_not_x8_tx_mode & (replay_cnt_s0_q[3:0] == 4'h7))));


assign nack_din = (rx_tx_crc_error || replay_due2_errors || (nack_q && (~replay_start || stall_d2_q || idle))) && ~reset_q; 
assign nack_dly_din = (nack_q | nack_dly_q) & ~init_replay_done_q;



assign nack_pend_din = (rx_tx_nack || (nack_pend_q && (~replay_start || stall_d2_q || idle))) && ~reset_q;

assign force_idle_flit_din = ctl_que_tx_ts2                                          ? 1'b0:
                             nack_pend_q & (replay_cnt_s2_q == 4'b0110)              ? 1'b1:
                             (flit_type[1:0] == 2'b11)                               ? 1'b0:
                                                                                       force_idle_flit_q;

assign force_idle_2nd_cycle_din = force_idle_flit_q & replay_start;

assign replay_after_idle_f_din = ((force_idle_flit_q & replay_start) | replay_after_idle_f_q) & ~(replay_cnt_s2_q == 4'b0010) ;



assign send_nack_din = nack_q || (send_nack_q && ~(replay_cnt_s2_q[3] == 1'b1)); 
    

assign replay_cnt_s0_din[3:0] = reset_q                                                             ? 4'b0000:
                                                         replay_start & ~stall_d0_q & ~stall_d1_q   ? 4'b0000:
                                ~ctl_x4_not_x8_tx_mode & replay_start & ~stall_d0_q &  stall_d1_q   ? 4'b1111:
                                                         replay_start &  stall_d0_q & ~stall_d1_q   ? 4'b1111:
                                ~ctl_x4_not_x8_tx_mode & replay_start &  stall_d0_q &  stall_d1_q   ? 4'b1110:
                                 ctl_x4_not_x8_tx_mode & replay_start &  stall_d0_q                 ? 4'b1111:
                                 ctl_x4_not_x8_tx_mode & replay_start                               ? 4'b0000:
                                stall_d0_q                                                          ? replay_cnt_s0_q[3:0]:
                                (replay_cnt_s0_q[3] == 1'b0) | (replay_cnt_s0_q[3:2] == 2'b11)      ? replay_cnt_s0_q[3:0] + 4'h1:
                                                                                                      4'b1011;

assign x4_replay_restart_din     = (x4_replay_restart_q | ((replay_cnt_s2_q[3:0] == 4'b0010) & ctl_x4_not_x8_tx_mode & ~init_replay_done_q)) & ~reset_q;
assign x4_replay_restart_d1_din  = x4_replay_restart_q;
assign x4_replay_restart         = x4_replay_restart_q & ~x4_replay_restart_d1_q;


assign replay_cnt_s2_din[3:0] = reset_q                                    ? 4'b1111:
                                (replay_start | x4_replay_restart)         ? 4'b0000:
                                stall_d2_q                                 ? replay_cnt_s2_q[3:0]:
                                (replay_cnt_s2_q[3:0] <= 4'h7)             ? replay_cnt_s2_q[3:0] + 4'h1:
                                                                             4'b1111;
           

assign replay_ip_din = ((((replay_cnt_s2_q[3:0] == 4'b1000) && ~stall_d2_q) || replay_ip_q) && ~replay_done_q && ~(replay_start || reset_q || ~init_replay_done_dly_q)); 



assign full_idle = ((rpb_full_q) && send_ctl_flit && ~(replay_start || replay_ip_q || dl_rp_flit_ip_q));
assign idle      = reset_q || max_ack_cnt || ((full_idle || ftb_empty) && ~(replay_start || replay_ip_din || replay_ip_q || dl_rp_flit_ip_q));



assign prev_cmd_run_length[3:0]  = (replay_cnt_s2_q[3:0] == 4'b0111) & init_replay_done_dly_q & ~tx_rl_not_vld_q & ~force_idle_flit_q & ~nack_pend_q ? rpb_data[451:448]:
                                                                                                                                                      4'b0000;
 





assign no_progress_cnt_din[5:0]  = (flit_vld | ~train_done_q)  ? 6'b000000                          :
                                   (pulse_1us & ~ftb_empty)    ? no_progress_cnt_q[5:0] + 6'b000001 :
                                                                 no_progress_cnt_q[5:0]; 

assign no_fwd_progress           = train_done_q & no_progress_cnt_q[3];
assign error_no_fwd_progress     = no_fwd_progress;


assign tlx_input_error = ftb_empty & (run_length_din[3:0]==4'b0000) & (flit_type[1:0]==2'b00);

assign dlx_errors[3:0]      = {(flt_buf_underrun_q | flt_buf_overflow_q | rpb_buf_underrun_q | rpb_buf_overflow_q | tlx_input_error ), no_fwd_progress, 1'b0, 1'b0};

assign dlx_info[31:0]       =  {flt_buf_underrun_q,
                                flt_buf_overflow_q,
                                rpb_buf_underrun_q,
                                rpb_buf_overflow_q,
                                tlx_input_error,
                                3'b000,
                                no_fwd_progress,
                                7'b0,
                                lane_inverted_q[7:0], sync_was_detected_q[7:0] };


assign sync_was_detected_din[7:0] =  reset_q   ?  8'b00000000         :
                                                  (rx_tx_sync[7:0] | sync_was_detected_q[7:0]);


assign lane_inverted_din[7:0]    =  rx_tx_lane_inverted[7:0];

assign link_errors_din[7:0]      = {dlx_errors[3:0],tlx_dlx_debug_encode[3:0]};
assign link_errors_last_din[7:0] = link_errors_q[7:0];
assign link_info_din[63:0]       = {dlx_info[31:0] ,tlx_dlx_debug_info[31:0]};

assign replay_due2_errors        = ~(link_errors_q[7:0] == link_errors_last_din[7:0]);




assign cfg_force_crc_error       = 1'b0; 
assign injected_crc_error        =  cfg_force_crc_error & (out_data_q[11:0] == 12'h3C0) & (injected_crc_cnt_q[2:0] == 3'b0);
assign injected_crc_cnt_din[2:0] = (cfg_force_crc_error & (out_data_q[11:0] == 12'h3C0)) ? injected_crc_cnt_q[2:0] + 3'b1 :
                                                                                           injected_crc_cnt_q[2:0];



    always @(posedge dlx_clk) begin
      injected_crc_cnt_q[2:0]  <= injected_crc_cnt_din[2:0];
      crc_zero_q               <= crc_zero_din;
      crc_zero_d1_q            <= crc_zero_d1_din;
      crc_zero_d2_q            <= crc_zero_d2_din;

      crc_checkbits_q[35:0]    <= crc_checkbits_din[35:0];
      dl_rp_flit_ip_q          <= dl_rp_flit_ip_din;
      flit_buf0_data_q[511:0]  <= ((flit_wr_ptr_q == 2'b00) && tlx_dlx_flit_valid) ? flit_buf0_data_din[511:0] : flit_buf0_data_q[511:0];
      flit_buf1_data_q[511:0]  <= ((flit_wr_ptr_q == 2'b01) && tlx_dlx_flit_valid) ? flit_buf1_data_din[511:0] : flit_buf1_data_q[511:0];
      flit_buf2_data_q[511:0]  <= ((flit_wr_ptr_q == 2'b10) && tlx_dlx_flit_valid) ? flit_buf2_data_din[511:0] : flit_buf2_data_q[511:0];
      flit_buf3_data_q[511:0]  <= ((flit_wr_ptr_q == 2'b11) && tlx_dlx_flit_valid) ? flit_buf3_data_din[511:0] : flit_buf3_data_q[511:0];
      flit_rd_ptr_q[1:0]       <= flit_rd_ptr_din[1:0];
      flit_vld_q              <= flit_vld_din;
      flit_type_q[1:0]         <= flit_type_din[1:0];
      flit_wr_ptr_q[1:0]       <= flit_wr_ptr_din[1:0];
      ftb_full_q               <= ftb_full_din;
      link_errors_q[7:0]       <= link_errors_din[7:0];
      lane_inverted_q[7:0]     <= lane_inverted_din[7:0];
      sync_was_detected_q[7:0] <= sync_was_detected_din[7:0];
      link_info_q[63:0]        <= link_info_din[63:0];
      nack_pend_q              <= nack_pend_din;
      nack_q                   <= nack_din;
      nack_dly_q               <= nack_dly_din;
      init_replay_done_q       <= init_replay_done_din;
      out_data_q[511:0]        <= out_data_din[511:0];
      pre_crc_data_q[511:0]    <= pre_crc_data_din[511:0];
      replay_cnt_s0_q[3:0]     <= replay_cnt_s0_din[3:0];
      replay_cnt_s2_q[3:0]     <= replay_cnt_s2_din[3:0];
      x4_replay_restart_q      <= x4_replay_restart_din;
      x4_replay_restart_d1_q   <= x4_replay_restart_d1_din;
      replay_done_q            <= replay_done_din;
      replay_done_dly_q        <= replay_done_dly_din;
      replay_ip_q              <= replay_ip_din; 
      reset_q                  <= reset_din;
      rpb_full_q               <= rpb_full_din;
      rpb_rd_ptr_q[6:0]        <= rpb_rd_ptr_din[6:0];
      rpb_rd_vld_q             <= rpb_rd_vld_din;
      rpb_wr_ptr_q[6:0]        <= rpb_wr_ptr_din[6:0];
      rtn_ack_cnt_q[5:0]       <= rtn_ack_cnt_din[5:0];
      run_length_q[3:0]        <= run_length_din[3:0];
      rx_ack_ptr_q[6:0]        <= rx_ack_ptr_din[6:0];
      send_nack_q              <= send_nack_din;
      stall_d0_q               <= stall_d0_din;
      stall_d1_q               <= stall_d1_din;
      stall_d2_q               <= stall_d2_din;
      stall_d3_q               <= stall_d3_din;
      stall_d4_q               <= stall_d4_din;
      train_done_q             <= train_done_din;
      tx_ack_ptr_q[6:0]        <= tx_ack_ptr_din[6:0];
      no_progress_cnt_q[5:0]   <= no_progress_cnt_din[5:0];
      flt_buf_underrun_q       <= flt_buf_underrun_din;
      flt_buf_overflow_q       <= flt_buf_overflow_din;
      rpb_buf_underrun_q       <= rpb_buf_underrun_din;
      rpb_buf_overflow_q       <= rpb_buf_overflow_din;
      flit_vld_dly_q           <= flit_vld_dly_din;
      ftb_empty_dly_q          <= ftb_empty_dly_din;
      replay_flit_rpb_pointer_q[6:0] <= replay_flit_rpb_pointer_din[6:0];
      init_replay_done_dly_q   <= init_replay_done_dly_din;
      rpb_empty_q              <= rpb_empty_din;
      rpb_empty_d1_q           <= rpb_empty_d1_din;
      send_no_replay_data_q    <= send_no_replay_data_din;
      link_errors_last_q       <= link_errors_last_din;
      tx_rl_not_vld_q          <= tx_rl_not_vld_din;
      rx_ack_ptr_6_d_q         <= rx_ack_ptr_6_d_din;
      rx_rl_not_vld_q          <= rx_rl_not_vld_din;
      force_idle_flit_q        <= force_idle_flit_din;
      force_idle_2nd_cycle_q   <= force_idle_2nd_cycle_din;
      replay_after_idle_f_q    <= replay_after_idle_f_din;
      replay_start_q           <= replay_start_din;
    end

endmodule