data/full_repos/permissive/14636651/ProgramCounter.v
data/verilator_xmls/ba29d3f6-21fe-4686-8210-c01cefc352cf.xml
module ProgramCounter(input clk, rst, input [15:0] din, output reg [15:0] dout);
	always@(posedge clk)
	begin
		dout <= rst? 0 : din;
	end
endmodule
module ProgramCounter(input clk, rst, input [15:0] din, output reg [15:0] dout);

	always@(posedge clk)
	begin
		dout <= rst? 0 : din;
	end
endmodule