data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v
 line:54: before: "integer"
1: b'%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:84: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                               : ... In instance salsaengine\n reg [5:0] mcount = 5\'d0;  \n                    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:197: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                      : ... In instance salsaengine\n assign rd_addr = { phase_addr+1, addrsourceSave_in ? memtop[ADDRBITS-THREADS_BITS:1] : adj_addr };  \n                              ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:197: Unsized numbers/parameters not allowed in replications.\n                                                                                                      : ... In instance salsaengine\n assign rd_addr = { phase_addr+1, addrsourceSave_in ? memtop[ADDRBITS-THREADS_BITS:1] : adj_addr };  \n                                ^\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:215: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren_d, ram1_dout);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A,data/full_repos/permissive/11584509/ram\n             data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A,data/full_repos/permissive/11584509/ram.v\n             data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A,data/full_repos/permissive/11584509/ram.sv\n             ram\n             ram.v\n             ram.sv\n             obj_dir/ram\n             obj_dir/ram.v\n             obj_dir/ram.sv\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:216: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren_d, ram2_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:217: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren_d, ram3_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:218: Cannot find file containing module: \'ram\'\n ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren_d, ram4_dout);\n ^~~\n%Error: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:224: Cannot find file containing module: \'salsa\'\n salsa salsa_blk (hash_clk, mixfeedback_d, X0, X1, Xmix, X0out, X1out, Xaddr);\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:240: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                                : ... In instance salsaengine\n assign { mstate_in, mcount_in, writeaddr_in, cycle_in, doneROM_in, mixfeedback_in, addrsourceMix_in, addrsourceSave_in, mixspecial_in,  intcycles_in} = (phase == THREADS) ? 0 : sstate[phase];\n                                                                                                                                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:240: Operator ASSIGNW expects 41 bits on the Assign RHS, but Assign RHS\'s COND generates 42 bits.\n                                                                                                : ... In instance salsaengine\n assign { mstate_in, mcount_in, writeaddr_in, cycle_in, doneROM_in, mixfeedback_in, addrsourceMix_in, addrsourceSave_in, mixspecial_in,  intcycles_in} = (phase == THREADS) ? 0 : sstate[phase];\n                                                                                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:274: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                                : ... In instance salsaengine\n   sstate[phase_d] <= reset ? 0 : { mstate, mcount, writeaddr, cycle, doneROM, mixfeedback, addrsourceMix,\n         ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:274: Operator COND expects 42 bits on the Conditional False, but Conditional False\'s REPLICATE generates 41 bits.\n                                                                                                : ... In instance salsaengine\n   sstate[phase_d] <= reset ? 0 : { mstate, mcount, writeaddr, cycle, doneROM, mixfeedback, addrsourceMix,\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:297: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'phase\' generates 4 bits.\n                                                                                                : ... In instance salsaengine\n  phase_addr_d1 <= phase;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:298: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'phase\' generates 4 bits.\n                                                                                                : ... In instance salsaengine\n  phase_addr_d2 <= phase;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:299: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'phase\' generates 4 bits.\n                                                                                                : ... In instance salsaengine\n  phase_addr_d3 <= phase;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:300: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'phase\' generates 4 bits.\n                                                                                                : ... In instance salsaengine\n  phase_addr_d4 <= phase;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:325: Operator EQ expects 32 or 19 bits on the LHS, but LHS\'s VARREF \'start_count\' generates 16 bits.\n                                                                                                : ... In instance salsaengine\n  if (reset || start_count == START_INTERVAL)\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:343: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                                : ... In instance salsaengine\n   nonce_sr <= snonce[phase_d];   \n                     ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:344: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                                                : ... In instance salsaengine\n   snonce[phase_d] <= nonce_sr;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:419: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                : ... In instance salsaengine\n        intcycles <= { {THREADS_BITS+12-ADDRBITSX{1\'b0}}, Xaddr[12-ADDRBITSX:0] };  \n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:422: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                : ... In instance salsaengine\n         intcycles <= { {THREADS_BITS+11-ADDRBITSX{1\'b0}}, 1\'b1, Xaddr[12-ADDRBITSX:0] };\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:489: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                : ... In instance salsaengine\n        intcycles <= { {THREADS_BITS+12-ADDRBITSX{1\'b0}}, Xaddr[12-ADDRBITSX:0] };  \n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/11584509/experimental/LX150-EIGHT-A/salsaengine.v:492: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                : ... In instance salsaengine\n         intcycles <= { {THREADS_BITS+11-ADDRBITSX{1\'b0}}, 1\'b1, Xaddr[12-ADDRBITSX:0] };\n                   ^~\n%Error: Exiting due to 5 error(s), 18 warning(s)\n'
function integer clog2;
		input integer value;
		begin
		value = value-1;
		for (clog2=0; value>0; clog2=clog2+1)
		value = value>>1;
		end
	endfunction
function integer clog2;

		input integer value;
		begin
		value = value-1;
		for (clog2=0; value>0; clog2=clog2+1)
		value = value>>1;
		end
	endfunction