data/full_repos/permissive/146073027/Simple 32bit integer ALU.v
 line:28: before: "assign"
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/146073027/Simple\n        ... Looked in:\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple.v\n             data/full_repos/permissive/146073027,data/full_repos/permissive/146073027/data/full_repos/permissive/146073027/Simple.sv\n             data/full_repos/permissive/146073027/Simple\n             data/full_repos/permissive/146073027/Simple.v\n             data/full_repos/permissive/146073027/Simple.sv\n             obj_dir/data/full_repos/permissive/146073027/Simple\n             obj_dir/data/full_repos/permissive/146073027/Simple.v\n             obj_dir/data/full_repos/permissive/146073027/Simple.sv\n%Error: Cannot find file containing module: 32bit\n%Error: Cannot find file containing module: integer\n%Error: Cannot find file containing module: ALU.v\n%Error: Exiting due to 4 error(s)\n'
module two_bit_comparator(out1,out2,in1,in2,cont);
  input [1:0]in1,in2;
  output out1,out2;
  input cont;
  wire t1,t2,t3,t4,t5,t6,t7,t8;
  
  and(t1,in1[1],~in2[1]);
  and(t2,in1[0],~in2[1],~in2[0]);
  and(t3,in1[1],in1[0],~in2[0]);
  or(t4,t1,t2,t3);
  and(out1,t4,cont);
  and(t5,in2[1],~in1[1]);
  and(t6,in2[0],~in1[1],~in1[0]);
  and(t7,in2[1],in2[0],~in1[0]);
  or(t8,t5,t6,t7);
  and(out2,t8,cont);
endmodule
module two_bit_comparator(out1,out2,in1,in2,cont);

  input [1:0]in1,in2;
  output out1,out2;
  input cont;
  wire t1,t2,t3,t4,t5,t6,t7,t8;
  
  and(t1,in1[1],~in2[1]);
  and(t2,in1[0],~in2[1],~in2[0]);
  and(t3,in1[1],in1[0],~in2[0]);
  or(t4,t1,t2,t3);
  and(out1,t4,cont);
  and(t5,in2[1],~in1[1]);
  and(t6,in2[0],~in1[1],~in1[0]);
  and(t7,in2[1],in2[0],~in1[0]);
  or(t8,t5,t6,t7);
  and(out2,t8,cont);
endmodule