data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v
1: b'%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:6: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v.v\n             data/full_repos/permissive/188068190/ridecore-src-buggy,data/full_repos/permissive/188068190/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:75: Define or directive not defined: \'`SERIAL_WCNT\'\n      end else if( waitnum >= `SERIAL_WCNT ) begin\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:75: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      end else if( waitnum >= `SERIAL_WCNT ) begin\n                                           ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:81: syntax error, unexpected else\n      end else begin\n          ^~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:192: Define or directive not defined: \'`SERIAL_WCNT\'\n   assign waitcnt = `SERIAL_WCNT;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:192: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   assign waitcnt = `SERIAL_WCNT;\n                                ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:283: Define or directive not defined: \'`APP_SIZE\'\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:283: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                               ^\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:287: Define or directive not defined: \'`APP_SIZE\'\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/188068190/ridecore-src-buggy/uart.v:287: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            if(waddr>=`APP_SIZE) DONE <= 1;\n                               ^\n%Error: Exiting due to 10 error(s)\n'
module UartTx(CLK, RST_X, DATA, WE, TXD, READY);
   input wire  CLK, RST_X, WE;
   input wire [7:0] DATA;
   output reg  TXD, READY;

   reg [8:0]   cmd;
   reg [11:0]  waitnum;
   reg [3:0]   cnt;

   always @(posedge CLK or negedge RST_X) begin
      if(~RST_X) begin
         TXD       <= 1'b1;
         READY     <= 1'b1;
         cmd       <= 9'h1ff;
         waitnum   <= 0;
         cnt       <= 0;
      end else if( READY ) begin
         TXD       <= 1'b1;
         waitnum   <= 0;
         if( WE )begin
            READY <= 1'b0;
            cmd   <= {DATA, 1'b0};
            cnt   <= 10;
         end
      end else if( waitnum >= `SERIAL_WCNT ) begin
         TXD       <= cmd[0];
         READY     <= (cnt == 1);
         cmd       <= {1'b1, cmd[8:1]};
         waitnum   <= 1;
         cnt       <= cnt - 1;
      end else begin
         waitnum   <= waitnum + 1;
      end
   end
endmodule
module UartTx(CLK, RST_X, DATA, WE, TXD, READY);

   input wire  CLK, RST_X, WE;
   input wire [7:0] DATA;
   output reg  TXD, READY;

   reg [8:0]   cmd;
   reg [11:0]  waitnum;
   reg [3:0]   cnt;

   always @(posedge CLK or negedge RST_X) begin
      if(~RST_X) begin
         TXD       <= 1'b1;
         READY     <= 1'b1;
         cmd       <= 9'h1ff;
         waitnum   <= 0;
         cnt       <= 0;
      end else if( READY ) begin
         TXD       <= 1'b1;
         waitnum   <= 0;
         if( WE )begin
            READY <= 1'b0;
            cmd   <= {DATA, 1'b0};
            cnt   <= 10;
         end
      end else if( waitnum >= `SERIAL_WCNT ) begin
         TXD       <= cmd[0];
         READY     <= (cnt == 1);
         cmd       <= {1'b1, cmd[8:1]};
         waitnum   <= 1;
         cnt       <= cnt - 1;
      end else begin
         waitnum   <= waitnum + 1;
      end
   end
endmodule