data/full_repos/permissive/216210370/soc/rtc.v
1: b"%Error: data/full_repos/permissive/216210370/soc/rtc.v:892: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.v\n             data/full_repos/permissive/216210370/soc,data/full_repos/permissive/216210370/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:510: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:469: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:409: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/216210370/soc/rtc.v:197: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  gatecell (\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module rtc_ig(
  cnt_en,
  count_val,
  i_rtc_ext_clk,
  int_flag,
  intr_en,
  intr_mask,
  match_val,
  pdu_aou_int_clr,
  rtc0_vic_intr,
  rtc_etb_trig,
  rtc_por_rst_n
);
input           cnt_en;         
input   [31:0]  count_val;      
input           i_rtc_ext_clk;  
input           intr_en;        
input           intr_mask;      
input   [31:0]  match_val;      
input           pdu_aou_int_clr; 
input           rtc_por_rst_n;  
output          int_flag;       
output          rtc0_vic_intr;  
output          rtc_etb_trig;   
reg             cmp_res;        
reg             int_flag;       
reg             rtc_etb_trig;   
wire            cnt_en;         
wire    [31:0]  count_val;      
wire            i_rtc_ext_clk;  
wire            int_intr;       
wire            intr_en;        
wire            intr_mask;      
wire    [31:0]  match_val;      
wire            pdu_aou_int_clr; 
wire            rtc0_vic_intr;  
wire            rtc_por_rst_n;  
 always @ (match_val[31:0] or count_val[31:0] or cnt_en)
 begin
   if((match_val[31:0] == count_val[31:0]) && cnt_en)
     begin
       cmp_res = 1'b1;
     end
   else
     begin
       cmp_res = 1'b0;
     end
 end
assign int_intr = cmp_res && intr_en;
assign rtc0_vic_intr = intr_mask ? 1'b0 : (int_flag && ~pdu_aou_int_clr);
 always @ (posedge i_rtc_ext_clk or negedge rtc_por_rst_n)
 begin
   if(!rtc_por_rst_n)
     begin
       int_flag <= 1'b0;
     end
   else if(int_intr)
     begin
       int_flag <= 1'b1;
     end
   else if (pdu_aou_int_clr)
     begin
       int_flag <= 1'b0;
     end
 end
 always @ (posedge i_rtc_ext_clk or negedge rtc_por_rst_n)
 begin
   if(!rtc_por_rst_n)
     begin
       rtc_etb_trig <= 1'b0;
     end
   else if(cmp_res)
     begin
       rtc_etb_trig <= 1'b1;
     end
   else
     begin
       rtc_etb_trig <= 1'b0;
     end
 end
endmodule
module rtc_ig(
  cnt_en,
  count_val,
  i_rtc_ext_clk,
  int_flag,
  intr_en,
  intr_mask,
  match_val,
  pdu_aou_int_clr,
  rtc0_vic_intr,
  rtc_etb_trig,
  rtc_por_rst_n
);

input           cnt_en;         
input   [31:0]  count_val;      
input           i_rtc_ext_clk;  
input           intr_en;        
input           intr_mask;      
input   [31:0]  match_val;      
input           pdu_aou_int_clr; 
input           rtc_por_rst_n;  
output          int_flag;       
output          rtc0_vic_intr;  
output          rtc_etb_trig;   
reg             cmp_res;        
reg             int_flag;       
reg             rtc_etb_trig;   
wire            cnt_en;         
wire    [31:0]  count_val;      
wire            i_rtc_ext_clk;  
wire            int_intr;       
wire            intr_en;        
wire            intr_mask;      
wire    [31:0]  match_val;      
wire            pdu_aou_int_clr; 
wire            rtc0_vic_intr;  
wire            rtc_por_rst_n;  
 always @ (match_val[31:0] or count_val[31:0] or cnt_en)
 begin
   if((match_val[31:0] == count_val[31:0]) && cnt_en)
     begin
       cmp_res = 1'b1;
     end
   else
     begin
       cmp_res = 1'b0;
     end
 end
assign int_intr = cmp_res && intr_en;
assign rtc0_vic_intr = intr_mask ? 1'b0 : (int_flag && ~pdu_aou_int_clr);
 always @ (posedge i_rtc_ext_clk or negedge rtc_por_rst_n)
 begin
   if(!rtc_por_rst_n)
     begin
       int_flag <= 1'b0;
     end
   else if(int_intr)
     begin
       int_flag <= 1'b1;
     end
   else if (pdu_aou_int_clr)
     begin
       int_flag <= 1'b0;
     end
 end
 always @ (posedge i_rtc_ext_clk or negedge rtc_por_rst_n)
 begin
   if(!rtc_por_rst_n)
     begin
       rtc_etb_trig <= 1'b0;
     end
   else if(cmp_res)
     begin
       rtc_etb_trig <= 1'b1;
     end
   else
     begin
       rtc_etb_trig <= 1'b0;
     end
 end
endmodule