data/full_repos/permissive/147790758/tb2_sum.v
 line:19: before: "("
1: b'%Warning-STMTDLY: data/full_repos/permissive/147790758/tb2_sum.v:18: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/147790758/tb2_sum.v:9: Cannot find file containing module: \'sum\'\nsum #(.WIDTH(4)) DUT (.data_a(term1), .data_b(term2), .c_out(actual[4]), .sum(actual[3:0]));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/sum\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/sum.v\n             data/full_repos/permissive/147790758,data/full_repos/permissive/147790758/sum.sv\n             sum\n             sum.v\n             sum.sv\n             obj_dir/sum\n             obj_dir/sum.v\n             obj_dir/sum.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb2_sum();
	reg [3:0]term1;
	reg [3:0]term2;
	reg [4:0]expected;
	wire [4:0]actual;
	integer i,j;
sum #(.WIDTH(4)) DUT	(.data_a(term1), .data_b(term2), .c_out(actual[4]), .sum(actual[3:0]));

initial begin: make_data
	$display("**UNIT TEST STARTED**");
	term1 = 4'd0;
	for (i=0;i<=15;i=i+1) begin
		term2 = 4'd0;
		for (j=0;j<=15;j=j+1) begin
			expected = term1 + term2;
			#10;
			check_data(expected,actual);
			term2 = term2 + 1'd1;
			end
		term1 = term1 + 1'd1;	
		end 
	$display("**ALL TESTS PASSED**");
	$stop;
end 

task check_data;
		input [4:0]expected;
		input [4:0]actual;
begin
	$display("Now testing with inputs: %b %b, Expected result: %b Actual result: %b", term1, term2, expected, actual);
	if(expected != actual) begin
		$display("ERROR: expected %b, but got %b. Inputs were: %b and %b.", expected, actual, term1, term2);
		$display("**ERROR: UNIT DOES NOT WORK PROPERLY**");
		$stop;
	end
end	
endtask
endmodule
module tb2_sum();

	reg [3:0]term1;
	reg [3:0]term2;
	reg [4:0]expected;
	wire [4:0]actual;
	integer i,j;
sum #(.WIDTH(4)) DUT	(.data_a(term1), .data_b(term2), .c_out(actual[4]), .sum(actual[3:0]));

initial begin: make_data
	$display("**UNIT TEST STARTED**");
	term1 = 4'd0;
	for (i=0;i<=15;i=i+1) begin
		term2 = 4'd0;
		for (j=0;j<=15;j=j+1) begin
			expected = term1 + term2;
			#10;
			check_data(expected,actual);
			term2 = term2 + 1'd1;
			end
		term1 = term1 + 1'd1;	
		end 
	$display("**ALL TESTS PASSED**");
	$stop;
end 

task check_data;
		input [4:0]expected;
		input [4:0]actual;
begin
	$display("Now testing with inputs: %b %b, Expected result: %b Actual result: %b", term1, term2, expected, actual);
	if(expected != actual) begin
		$display("ERROR: expected %b, but got %b. Inputs were: %b and %b.", expected, actual, term1, term2);
		$display("**ERROR: UNIT DOES NOT WORK PROPERLY**");
		$stop;
	end
end	
endtask
endmodule