data/full_repos/permissive/170210550/hw3_2/rca_16b.v
1: b"%Error: data/full_repos/permissive/170210550/hw3_2/rca_16b.v:20: Cannot find file containing module: 'rca_4b'\n    rca_4b bit3_0 (.S(S[3:0]), .C_out(c_out0), .A(A[3:0]), .B(B[3:0]), .C_in(C_in));\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/170210550/hw3_2,data/full_repos/permissive/170210550/rca_4b\n             data/full_repos/permissive/170210550/hw3_2,data/full_repos/permissive/170210550/rca_4b.v\n             data/full_repos/permissive/170210550/hw3_2,data/full_repos/permissive/170210550/rca_4b.sv\n             rca_4b\n             rca_4b.v\n             rca_4b.sv\n             obj_dir/rca_4b\n             obj_dir/rca_4b.v\n             obj_dir/rca_4b.sv\n%Error: data/full_repos/permissive/170210550/hw3_2/rca_16b.v:21: Cannot find file containing module: 'rca_4b'\n    rca_4b bit7_4 (.S(S[7:4]), .C_out(c_out1), .A(A[7:4]), .B(B[7:4]), .C_in(c_out0));\n    ^~~~~~\n%Error: data/full_repos/permissive/170210550/hw3_2/rca_16b.v:22: Cannot find file containing module: 'rca_4b'\n    rca_4b bit11_8 (.S(S[11:8]), .C_out(c_out2), .A(A[11:8]), .B(B[11:8]), .C_in(c_out1));\n    ^~~~~~\n%Error: data/full_repos/permissive/170210550/hw3_2/rca_16b.v:23: Cannot find file containing module: 'rca_4b'\n    rca_4b bit15_12 (.S(S[15:12]), .C_out(C_out), .A(A[15:12]), .B(B[15:12]), .C_in(c_out2));\n    ^~~~~~\n%Error: Exiting due to 4 error(s)\n"
module rca_16b(A, B, C_in, S, C_out);


    parameter   N = 16;

    input [N-1: 0] A, B;
    input          C_in;
    output [N-1:0] S;
    output         C_out;


    wire c_out0, c_out1, c_out2;

    rca_4b bit3_0 (.S(S[3:0]), .C_out(c_out0), .A(A[3:0]), .B(B[3:0]), .C_in(C_in));
    rca_4b bit7_4 (.S(S[7:4]), .C_out(c_out1), .A(A[7:4]), .B(B[7:4]), .C_in(c_out0));
    rca_4b bit11_8 (.S(S[11:8]), .C_out(c_out2), .A(A[11:8]), .B(B[11:8]), .C_in(c_out1));
    rca_4b bit15_12 (.S(S[15:12]), .C_out(C_out), .A(A[15:12]), .B(B[15:12]), .C_in(c_out2));

endmodule
module rca_16b(A, B, C_in, S, C_out);



    parameter   N = 16;

    input [N-1: 0] A, B;
    input          C_in;
    output [N-1:0] S;
    output         C_out;


    wire c_out0, c_out1, c_out2;

    rca_4b bit3_0 (.S(S[3:0]), .C_out(c_out0), .A(A[3:0]), .B(B[3:0]), .C_in(C_in));
    rca_4b bit7_4 (.S(S[7:4]), .C_out(c_out1), .A(A[7:4]), .B(B[7:4]), .C_in(c_out0));
    rca_4b bit11_8 (.S(S[11:8]), .C_out(c_out2), .A(A[11:8]), .B(B[11:8]), .C_in(c_out1));
    rca_4b bit15_12 (.S(S[15:12]), .C_out(C_out), .A(A[15:12]), .B(B[15:12]), .C_in(c_out2));

endmodule