data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv
 line:26: before: "class"
1: b'%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:26: Unsupported: classes\nclass axi_mm_mst_agent extends uvm_driver #(axi_mm_transaction);\n^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:26: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass axi_mm_mst_agent extends uvm_driver #(axi_mm_transaction);\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:28: Unsupported: virtual interface\n    virtual interface               axi_vip_if `AXI_VIP_MM_MASTER_PARAMS mm_mst_vif;\n    ^~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:28: Define or directive not defined: \'`AXI_VIP_MM_MASTER_PARAMS\'\n    virtual interface               axi_vip_if `AXI_VIP_MM_MASTER_PARAMS mm_mst_vif;\n                                               ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:29: Unsupported: virtual interface\n    virtual interface               intrp_interface intrp_vif;\n    ^~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:30: syntax error, unexpected IDENTIFIER\n    act_cfg_obj                     act_cfg;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:36: Unsupported: classes\n    class master_delay_packet;\n    ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:43: syntax error, unexpected IDENTIFIER\n    axi_mm_transaction              axi_read_queue[$];      \n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:53: Define or directive not defined: \'`uvm_component_utils_begin\'\n    `uvm_component_utils_begin(axi_mm_mst_agent)\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:53: syntax error, unexpected \'(\'\n    `uvm_component_utils_begin(axi_mm_mst_agent)\n                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:54: Define or directive not defined: \'`uvm_field_enum\'\n        `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_ALL_ON)\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:55: Define or directive not defined: \'`uvm_component_utils_end\'\n    `uvm_component_utils_end\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:57: Unsupported: new constructor\n    extern function new(string name = "axi_mm_mst_agent", uvm_component parent = null);\n                    ^~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:57: syntax error, unexpected IDENTIFIER, expecting \')\'\n    extern function new(string name = "axi_mm_mst_agent", uvm_component parent = null);\n                                                                        ^~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:61: syntax error, unexpected IDENTIFIER, expecting \')\'\n    extern function void build_phase(uvm_phase phase);\n                                               ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:62: syntax error, unexpected IDENTIFIER, expecting \')\'\n    extern function void connect_phase(uvm_phase phase);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:68: syntax error, unexpected IDENTIFIER, expecting \')\'\n    extern task          main_phase(uvm_phase phase);\n                                              ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:76: syntax error, unexpected extern\n    extern task          get_axi_trans();\n    ^~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:89: Unsupported: super\n    super.new(name, parent);\n    ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:89: Unsupported: new with arguments\n    super.new(name, parent);\n          ^~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:89: Unsupported: dotted new\n    super.new(name, parent);\n    ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:91: syntax error, unexpected endfunction, expecting endtask\nendfunction : new\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:95: Unsupported: Hierarchical class references\nfunction void axi_mm_mst_agent::build_phase(uvm_phase phase);\n                              ^~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:95: Unsupported: scoped class reference\nfunction void axi_mm_mst_agent::build_phase(uvm_phase phase);\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:75: Unsupported: Out of class block function declaration\n    extern task          reset_intrp_signal();\n                                           ^\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:95: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void axi_mm_mst_agent::build_phase(uvm_phase phase);\n                                                      ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:97: Define or directive not defined: \'`uvm_info\'\n    `uvm_info(tID, $sformatf("build_phase begin ..."), UVM_HIGH)\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:98: Unsupported: virtual data type\n    if(!uvm_config_db#(virtual axi_vip_if `AXI_VIP_MM_MASTER_PARAMS)::get(this, "", "axi_vip_mm_master_vif", mm_mst_vif)) begin\n                       ^~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:98: Define or directive not defined: \'`AXI_VIP_MM_MASTER_PARAMS\'\n    if(!uvm_config_db#(virtual axi_vip_if `AXI_VIP_MM_MASTER_PARAMS)::get(this, "", "axi_vip_mm_master_vif", mm_mst_vif)) begin\n                                          ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:99: Define or directive not defined: \'`uvm_fatal\'\n        `uvm_fatal(tID, "No virtual interface axi_vip_mm_master_vif specified for axi_mm_mst_agent.")\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:101: Unsupported: virtual data type\n    if(!uvm_config_db#(virtual intrp_interface)::get(this, "", "intrp_vif", intrp_vif)) begin\n                       ^~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:102: Define or directive not defined: \'`uvm_fatal\'\n        `uvm_fatal(tID, "No virtual interface intrp_vif specified for axi_mm_mst_agent.")\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:108: Unsupported: Hierarchical class references\nfunction void axi_mm_mst_agent::connect_phase(uvm_phase phase);\n                              ^~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:108: Unsupported: scoped class reference\nfunction void axi_mm_mst_agent::connect_phase(uvm_phase phase);\n                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:95: Unsupported: Out of class block function declaration\nfunction void axi_mm_mst_agent::build_phase(uvm_phase phase);\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:108: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void axi_mm_mst_agent::connect_phase(uvm_phase phase);\n                                                        ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:110: Define or directive not defined: \'`uvm_info\'\n    `uvm_info(tID, $sformatf("connect_phase begin ..."), UVM_HIGH)\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:112: Define or directive not defined: \'`uvm_error\'\n                                                                                                       : ... Suggested alternative: \'`error\'\n        `uvm_error(get_type_name(), "Can\'t get act_cfg_obj!")\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:116: Unsupported: Hierarchical class references\ntask axi_mm_mst_agent::main_phase(uvm_phase phase);\n                     ^~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:116: Unsupported: scoped class reference\ntask axi_mm_mst_agent::main_phase(uvm_phase phase);\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:108: Unsupported: Out of class block function declaration\nfunction void axi_mm_mst_agent::connect_phase(uvm_phase phase);\n         ^~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:116: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask axi_mm_mst_agent::main_phase(uvm_phase phase);\n                                            ^~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:118: Define or directive not defined: \'`uvm_info\'\n    `uvm_info(tID, $sformatf("main_phase begin ..."), UVM_HIGH)\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:146: Unsupported: Hierarchical class references\ntask axi_mm_mst_agent::reset_intrp_signal();\n                     ^~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:146: Unsupported: scoped class reference\ntask axi_mm_mst_agent::reset_intrp_signal();\n                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:116: Unsupported: Out of class block function declaration\ntask axi_mm_mst_agent::main_phase(uvm_phase phase);\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:153: Unsupported: Hierarchical class references\ntask axi_mm_mst_agent::get_axi_trans();\n                     ^~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:153: Unsupported: scoped class reference\ntask axi_mm_mst_agent::get_axi_trans();\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:146: Unsupported: Out of class block function declaration\ntask axi_mm_mst_agent::reset_intrp_signal();\n                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/218463548/hardware/sim/unit_verif/action_bfm/axi_mm_mst_agent.sv:156: syntax error, unexpected ::\n        if(req.trans == axi_mm_transaction::READ)begin\n                                          ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
function void axi_mm_mst_agent::build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info(tID, $sformatf("build_phase begin ..."), UVM_HIGH)
    if(!uvm_config_db#(virtual axi_vip_if `AXI_VIP_MM_MASTER_PARAMS)::get(this, "", "axi_vip_mm_master_vif", mm_mst_vif)) begin
        `uvm_fatal(tID, "No virtual interface axi_vip_mm_master_vif specified for axi_mm_mst_agent.")
    end
    if(!uvm_config_db#(virtual intrp_interface)::get(this, "", "intrp_vif", intrp_vif)) begin
        `uvm_fatal(tID, "No virtual interface intrp_vif specified for axi_mm_mst_agent.")
    end
endfunction
function void axi_mm_mst_agent::build_phase(uvm_phase phase);

    super.build_phase(phase);
    `uvm_info(tID, $sformatf("build_phase begin ..."), UVM_HIGH)
    if(!uvm_config_db#(virtual axi_vip_if `AXI_VIP_MM_MASTER_PARAMS)::get(this, "", "axi_vip_mm_master_vif", mm_mst_vif)) begin
        `uvm_fatal(tID, "No virtual interface axi_vip_mm_master_vif specified for axi_mm_mst_agent.")
    end
    if(!uvm_config_db#(virtual intrp_interface)::get(this, "", "intrp_vif", intrp_vif)) begin
        `uvm_fatal(tID, "No virtual interface intrp_vif specified for axi_mm_mst_agent.")
    end
endfunction