data/full_repos/permissive/147690299/lab/27_seq_syncronizers/rtl/board_top.v
1: b'%Error: data/full_repos/permissive/147690299/lab/27_seq_syncronizers/rtl/board_top.v:2: Cannot find include file: config.vh\n`include "config.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/147690299/lab/27_seq_syncronizers/rtl,data/full_repos/permissive/147690299/config.vh\n             data/full_repos/permissive/147690299/lab/27_seq_syncronizers/rtl,data/full_repos/permissive/147690299/config.vh.v\n             data/full_repos/permissive/147690299/lab/27_seq_syncronizers/rtl,data/full_repos/permissive/147690299/config.vh.sv\n             config.vh\n             config.vh.v\n             config.vh.sv\n             obj_dir/config.vh\n             obj_dir/config.vh.v\n             obj_dir/config.vh.sv\n%Error: data/full_repos/permissive/147690299/lab/27_seq_syncronizers/rtl/board_top.v:14: Define or directive not defined: \'`MOD_SYNC\'\n    `MOD_SYNC sync\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/147690299/lab/27_seq_syncronizers/rtl/board_top.v:16: syntax error, unexpected \'(\', expecting IDENTIFIER\n        .clk ( CLK ),\n        ^\n%Error: Exiting due to 3 error(s)\n'
module board_top
(
    input         CLK,
    input  [ 0:0] SW,
    inout  [ 0:0] GPIO,
    output [ 1:0] LED
);
    wire d   = SW[0] ^ GPIO[0];
    wire q;

    `MOD_SYNC sync
    (
        .clk ( CLK ),
        .d   ( d   ),
        .q   ( q   )
    );

    assign LED[  0] =  q;
    assign LED[  1] = ~q;

endmodule
module board_top
(
    input         CLK,
    input  [ 0:0] SW,
    inout  [ 0:0] GPIO,
    output [ 1:0] LED
);

    wire d   = SW[0] ^ GPIO[0];
    wire q;

    `MOD_SYNC sync
    (
        .clk ( CLK ),
        .d   ( d   ),
        .q   ( q   )
    );

    assign LED[  0] =  q;
    assign LED[  1] = ~q;

endmodule