data/full_repos/permissive/180624253/datapath.v
1: b'%Warning-WIDTH: data/full_repos/permissive/180624253/datapath.v:30: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                  : ... In instance datapath\n assign x_out = x_in + count[1:0];\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/180624253/datapath.v:31: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                  : ... In instance datapath\n assign y_out = y_in + count[3:2];\n                     ^\n%Error: Exiting due to 2 warning(s)\n'
module datapath(clock, x_in, y_in, colour_in, reset_n, load_x, load_y, draw, erase, x_out, y_out, colour_out);
	input [7:0] x_in;
	input [6:0] y_in;
	input [2:0] colour_in;
	input clock;
	input reset_n; 
	input load_x; 
	input load_y; 
	input draw; 
	input erase;
	output [7:0] x_out;
	output [6:0] y_out;
	output [2:0] colour_out;
	
	reg [3:0] count;
	
	always @(posedge clock)
	begin
		if (!reset_n)
			count <= 4'b0000;
		else if (draw || erase)
			begin
				if(count == 4'b1111)
					count <= 4'b0000;
				else
					count <= count + 1'b1;
			end
	end
	
	assign x_out = x_in + count[1:0];
	assign y_out = y_in + count[3:2];
	assign colour_out = (draw) ? colour_in : 3'b000;
endmodule
module datapath(clock, x_in, y_in, colour_in, reset_n, load_x, load_y, draw, erase, x_out, y_out, colour_out);

	input [7:0] x_in;
	input [6:0] y_in;
	input [2:0] colour_in;
	input clock;
	input reset_n; 
	input load_x; 
	input load_y; 
	input draw; 
	input erase;
	output [7:0] x_out;
	output [6:0] y_out;
	output [2:0] colour_out;
	
	reg [3:0] count;
	
	always @(posedge clock)
	begin
		if (!reset_n)
			count <= 4'b0000;
		else if (draw || erase)
			begin
				if(count == 4'b1111)
					count <= 4'b0000;
				else
					count <= count + 1'b1;
			end
	end
	
	assign x_out = x_in + count[1:0];
	assign y_out = y_in + count[3:2];
	assign colour_out = (draw) ? colour_in : 3'b000;
endmodule