data/full_repos/permissive/154123726/3rdParty/simd/do_reduce.v
data/verilator_xmls/4b3351aa-e56b-4e5a-9dc3-ec045ce736a6.xml
module do_reduce(ai, 
				 ao);

	input signed [16:0] ai;
	

	output signed [14:0] ao;
	
	wire signed [9:0] diff;
	wire signed [9:0] High8;
	wire signed [9:0] Low8;
	assign High8 = {ai[16],ai[16:8]};
	assign Low8 = {2'b0, ai[7:0]};
	assign diff = Low8 - High8;
	assign ao = {{5{diff[9]}},diff};
endmodule
module do_reduce(ai, 
				 ao);


	input signed [16:0] ai;
	

	output signed [14:0] ao;
	
	wire signed [9:0] diff;
	wire signed [9:0] High8;
	wire signed [9:0] Low8;
	assign High8 = {ai[16],ai[16:8]};
	assign Low8 = {2'b0, ai[7:0]};
	assign diff = Low8 - High8;
	assign ao = {{5{diff[9]}},diff};
endmodule