data/full_repos/permissive/203526788/GoBoard/SPI_master/Display.v
1: b'%Error: data/full_repos/permissive/203526788/GoBoard/SPI_master/Display.v:59: `ifdef not terminated at EOF\n%Error: Exiting due to 1 error(s)\n'
module SevenSegment (
	input CLK,
	output [6:0] SEGMENT,
	input  [3:0] DATA
	);


always @(posedge CLK)
begin
	case (DATA)
		4'd0: SEGMENT <= 7'b0000001;
		4'd1: SEGMENT <= 7'b1001111;
		4'd2: SEGMENT <= 7'b0010010;
		4'd3: SEGMENT <= 7'b0000110;
		4'd4: SEGMENT <= 7'b1001100;
		4'd5: SEGMENT <= 7'b0100100;
		4'd6: SEGMENT <= 7'b0100000;
		4'd7: SEGMENT <= 7'b0001111;
		4'd8: SEGMENT <= 7'b0000000;
		4'd9: SEGMENT <= 7'b0000100;
		default: SEGMENT <= 7'b1111111;
	endcase
end
endmodule
module SevenSegment (
	input CLK,
	output [6:0] SEGMENT,
	input  [3:0] DATA
	);



always @(posedge CLK)
begin
	case (DATA)
		4'd0: SEGMENT <= 7'b0000001;
		4'd1: SEGMENT <= 7'b1001111;
		4'd2: SEGMENT <= 7'b0010010;
		4'd3: SEGMENT <= 7'b0000110;
		4'd4: SEGMENT <= 7'b1001100;
		4'd5: SEGMENT <= 7'b0100100;
		4'd6: SEGMENT <= 7'b0100000;
		4'd7: SEGMENT <= 7'b0001111;
		4'd8: SEGMENT <= 7'b0000000;
		4'd9: SEGMENT <= 7'b0000100;
		default: SEGMENT <= 7'b1111111;
	endcase
end
endmodule