data/full_repos/permissive/169574047/mux4_to_1/mux4_to_1.srcs/sources_1/new/logic2_mux4_to_1.v
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data/verilator_xmls/cc7dd3ff-7f17-4a7a-9b83-07187794495e.xml
module logic2_mux4_to_1(output out, input i0,i1,i2,i3, input s1,s0);

assign out = s1 ? ( s0 ? i3 : i2 ) : ( s0 ? i1 : i0 ) ;

endmodule
module logic2_mux4_to_1(output out, input i0,i1,i2,i3, input s1,s0);


assign out = s1 ? ( s0 ? i3 : i2 ) : ( s0 ? i1 : i0 ) ;

endmodule