data/full_repos/permissive/170365068/Splitted modules/Main modules/Registers.v
1: b'%Error: Cannot find file containing module: modules/Main\n        ... Looked in:\n             data/full_repos/permissive/170365068/Splitted/modules/Main\n             data/full_repos/permissive/170365068/Splitted/modules/Main.v\n             data/full_repos/permissive/170365068/Splitted/modules/Main.sv\n             modules/Main\n             modules/Main.v\n             modules/Main.sv\n             obj_dir/modules/Main\n             obj_dir/modules/Main.v\n             obj_dir/modules/Main.sv\n%Error: Cannot find file containing module: modules,data/full_repos/permissive/170365068\n%Error: Cannot find file containing module: data/full_repos/permissive/170365068/Splitted\n%Error: Cannot find file containing module: modules/Registers.v\n%Error: Exiting due to 4 error(s)\n'
module Registers(clk,ReadRegister1,ReadRegister2,WriteRegister,WriteData,ReadData1,ReadData2,RegWrite,reset);
	input [4:0] ReadRegister1,ReadRegister2,WriteRegister;
	input [31:0] WriteData;
	input RegWrite,reset,clk;
	output [31:0] ReadData1,ReadData2;
	reg [31:0] regBank [8:0];
	integer i;
	always@ (posedge clk)
	begin
	if(reset) 
		for(i=0;i<9;i=i+1)  
                regBank[i] <= 0;
    	else begin
		if(RegWrite)
			regBank[WriteRegister]<=WriteData;
	end
	end
	assign ReadData1=regBank[ReadRegister1];
	assign ReadData2=regBank[ReadRegister2];
endmodule
module Registers(clk,ReadRegister1,ReadRegister2,WriteRegister,WriteData,ReadData1,ReadData2,RegWrite,reset);

	input [4:0] ReadRegister1,ReadRegister2,WriteRegister;
	input [31:0] WriteData;
	input RegWrite,reset,clk;
	output [31:0] ReadData1,ReadData2;
	reg [31:0] regBank [8:0];
	integer i;
	always@ (posedge clk)
	begin
	if(reset) 
		for(i=0;i<9;i=i+1)  
                regBank[i] <= 0;
    	else begin
		if(RegWrite)
			regBank[WriteRegister]<=WriteData;
	end
	end
	assign ReadData1=regBank[ReadRegister1];
	assign ReadData2=regBank[ReadRegister2];
endmodule