data/full_repos/permissive/181665138/verilog/capitolo_v/Formatore_di_Impulsi.v
 line:63: before: "=="
1: b"%Error: data/full_repos/permissive/181665138/verilog/capitolo_v/Formatore_di_Impulsi.v:63: syntax error, unexpected ==, expecting ')' or ',' or or\n    always @(reset_ == 0) #1\n                    ^~\n%Error: Cannot continue\n"
module Formatore_di_Impulsi(dav_, rfd, numero, out, clock, reset_);
    input clock, reset_;
    input dav_;
    input [7:0] numero;

    output rfd;
    output out;

    reg RFD;
    assign rfd = RFD;

    reg OUT;
    assign out = OUT;

    reg [7:0] COUNT;
    reg [1:0] STAR;

    parameter s0 = 'B00, s1 = 'B01, s2 = 'B10;

    always @(reset_ == 0) #1
        begin
            RFD <= 1;
            OUT <= 0;
            STAR <= s0;
        end

    always @(posedge clock) if (reset_ == 1) #3
        casex(STAR)
            s0: begin
                    RFD <= 1;
                    OUT <= 0;
                    COUNT <= numero;
                    STAR <= (dav_ == 1)?s0:s1;
                end

            s1: begin
                    RFD <= 0;
                    OUT <= 1;
                    COUNT <= COUNT - 1;
                    STAR <= (COUNT == 1)?s2:s1;
                end

            s2: begin
                    RFD <= 0;
                    OUT <= 0;
                    STAR <= (dav_ == 1)?s0:s2;
                end
        endcase
endmodule
module Formatore_di_Impulsi(dav_, rfd, numero, out, clock, reset_);

    input clock, reset_;
    input dav_;
    input [7:0] numero;

    output rfd;
    output out;

    reg RFD;
    assign rfd = RFD;

    reg OUT;
    assign out = OUT;

    reg [7:0] COUNT;
    reg [1:0] STAR;

    parameter s0 = 'B00, s1 = 'B01, s2 = 'B10;

    always @(reset_ == 0) #1
        begin
            RFD <= 1;
            OUT <= 0;
            STAR <= s0;
        end

    always @(posedge clock) if (reset_ == 1) #3
        casex(STAR)
            s0: begin
                    RFD <= 1;
                    OUT <= 0;
                    COUNT <= numero;
                    STAR <= (dav_ == 1)?s0:s1;
                end

            s1: begin
                    RFD <= 0;
                    OUT <= 1;
                    COUNT <= COUNT - 1;
                    STAR <= (COUNT == 1)?s2:s1;
                end

            s2: begin
                    RFD <= 0;
                    OUT <= 0;
                    STAR <= (dav_ == 1)?s0:s2;
                end
        endcase
endmodule