data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/io_port.v
1: b"%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/io_port.v:36: Cannot find file containing module: 'timer'\n   timer TIMER0\n   ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/timer\n             data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/timer.v\n             data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/timer.sv\n             timer\n             timer.v\n             timer.sv\n             obj_dir/timer\n             obj_dir/timer.v\n             obj_dir/timer.sv\n%Error: Exiting due to 1 error(s)\n"
module io_port
  (
   input wire 	      clk,
   input wire 	      resetb,

   input wire [7:0]   io_addr,
   input wire 	      io_en,

   input wire 	      io_we,
   input wire [31:0]  io_data_write,
   output wire [31:0] io_data_read,
   output wire 	      irq_mtimecmp,
   output reg [7:0]   gpio0
   );

   wire 	      mtime_we;
   wire [31:0] 	      mtime_dout;

   assign mtime_we = io_addr[7:4] == 4'b0001 ? io_we : 1'b0;

   assign io_data_read = io_addr[7:4] == 4'b0001 ? mtime_dout : 32'bX;



   always @ (posedge clk) begin : GPIO0
      if (!resetb) begin
	 gpio0 <= 8'b0;
      end
      else if (clk) begin
	 if (io_addr[7:2] == 6'b0 && io_we) begin
	    gpio0 <= io_data_write[7:0];
	 end
      end
   end

   timer TIMER0
     (
      .clk(clk), .resetb(resetb),
      .io_addr_3_2(io_addr[3:2]), .io_we(mtime_we), .io_din(io_data_write),
      .io_dout(mtime_dout), .irq_mtimecmp(irq_mtimecmp)
      );

endmodule
module io_port
  (
   input wire 	      clk,
   input wire 	      resetb,

   input wire [7:0]   io_addr,
   input wire 	      io_en,

   input wire 	      io_we,
   input wire [31:0]  io_data_write,
   output wire [31:0] io_data_read,
   output wire 	      irq_mtimecmp,
   output reg [7:0]   gpio0
   );


   wire 	      mtime_we;
   wire [31:0] 	      mtime_dout;

   assign mtime_we = io_addr[7:4] == 4'b0001 ? io_we : 1'b0;

   assign io_data_read = io_addr[7:4] == 4'b0001 ? mtime_dout : 32'bX;



   always @ (posedge clk) begin : GPIO0
      if (!resetb) begin
	 gpio0 <= 8'b0;
      end
      else if (clk) begin
	 if (io_addr[7:2] == 6'b0 && io_we) begin
	    gpio0 <= io_data_write[7:0];
	 end
      end
   end

   timer TIMER0
     (
      .clk(clk), .resetb(resetb),
      .io_addr_3_2(io_addr[3:2]), .io_we(mtime_we), .io_din(io_data_write),
      .io_dout(mtime_dout), .irq_mtimecmp(irq_mtimecmp)
      );

endmodule