data/full_repos/permissive/18770871/project_tb.v
 line:18: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/18770871/project_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #10 rst = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/18770871/project_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #20 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/project_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #300 $stop;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18770871/project_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = ~clk;\n  ^\n%Error: data/full_repos/permissive/18770871/project_tb.v:7: Cannot find file containing module: \'phase1_top\'\nphase1_top CPU(.clk(clk), .rst(rst));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/18770871,data/full_repos/permissive/18770871/phase1_top\n             data/full_repos/permissive/18770871,data/full_repos/permissive/18770871/phase1_top.v\n             data/full_repos/permissive/18770871,data/full_repos/permissive/18770871/phase1_top.sv\n             phase1_top\n             phase1_top.v\n             phase1_top.sv\n             obj_dir/phase1_top\n             obj_dir/phase1_top.v\n             obj_dir/phase1_top.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module project_tb;
reg clk;
reg rst;

phase1_top CPU(.clk(clk), .rst(rst));

initial
begin
  clk = 0;



  rst=0;
  #10 rst = 1;
  #20 rst = 0;
  #300 $stop;
end

always begin
  #5 clk = ~clk;
end


endmodule
module project_tb;

reg clk;
reg rst;

phase1_top CPU(.clk(clk), .rst(rst));

initial
begin
  clk = 0;



  rst=0;
  #10 rst = 1;
  #20 rst = 0;
  #300 $stop;
end

always begin
  #5 clk = ~clk;
end


endmodule