data/full_repos/permissive/143278/ivltests/pull371.v
 line:12: before: "typedef"
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pull371.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (out !== A) begin\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pull371.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (out !== B) begin\n      ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
   E in;
   wire E out;

   M foo (in, out);

   initial begin
      in = A;
      #1 if (out !== A) begin
	 $display("FAIL: in=%0d, out=%0d", in, out);
	 $finish;
      end

      in = B;
      #1 if (out !== B) begin
	 $display("FAIL: in=%0d, out=%0d", in, out);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end
endmodule
module main;

   E in;
   wire E out;

   M foo (in, out);

   initial begin
      in = A;
      #1 if (out !== A) begin
	 $display("FAIL: in=%0d, out=%0d", in, out);
	 $finish;
      end

      in = B;
      #1 if (out !== B) begin
	 $display("FAIL: in=%0d, out=%0d", in, out);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end
endmodule