data/full_repos/permissive/197252258/src/ram/ram_2p_wrapper.v
None: at end of input
1: b'%Error: data/full_repos/permissive/197252258/src/ram/ram_2p_wrapper.v:189: Cannot find include file: clogb2.vh\n`include "clogb2.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/197252258/src/ram,data/full_repos/permissive/197252258/clogb2.vh\n             data/full_repos/permissive/197252258/src/ram,data/full_repos/permissive/197252258/clogb2.vh.v\n             data/full_repos/permissive/197252258/src/ram,data/full_repos/permissive/197252258/clogb2.vh.sv\n             clogb2.vh\n             clogb2.vh.v\n             clogb2.vh.sv\n             obj_dir/clogb2.vh\n             obj_dir/clogb2.vh.v\n             obj_dir/clogb2.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module ram_2p_wrapper #(
    parameter   RAM_TYPE        = -1,
    parameter   RAM_DEPTH       = -1,
    parameter   RAM_ADDR_WIDTH  = -1,
    parameter   RAM_DATA_WIDTH  = -1
)(
    input                                   rst_n,
    input                                   clka,
    input                                   ena,
    input                                   wea,
    input           [RAM_ADDR_WIDTH-1:0]    addra,
    input           [RAM_DATA_WIDTH-1:0]    dina,
    output          [RAM_DATA_WIDTH-1:0]    douta,
    input                                   clkb,
    input                                   enb,
    input                                   web,
    input           [RAM_ADDR_WIDTH-1:0]    addrb,
    input           [RAM_DATA_WIDTH-1:0]    dinb,
    output          [RAM_DATA_WIDTH-1:0]    doutb
);
`ifdef VCS_SIMULATION

reg     [RAM_DATA_WIDTH-1:0]    mem [RAM_DEPTH-1:0];
reg     [RAM_DATA_WIDTH-1:0]    douta_f;
reg     [RAM_DATA_WIDTH-1:0]    doutb_f;

genvar ii;

assign douta = douta_f;
assign doutb = doutb_f;

generate
    for (ii = 0; ii < RAM_DEPTH; ii = ii + 1) begin: mem_gen
        always @(posedge clka) begin
            if (~rst_n) begin
                mem[ii] <= {RAM_DATA_WIDTH{1'b0}};
            end
            else begin
                mem[ii] <= ena & wea & (ii == addra) ? dina :
                           enb & web & (ii == addrb) ? dinb : mem[ii];
            end
        end
    end
endgenerate

always @(posedge clka) begin
    douta_f <= ena & ~wea ? mem[addra] : {RAM_DATA_WIDTH{1'bx}};
    doutb_f <= enb & ~web ? mem[addrb] : {RAM_DATA_WIDTH{1'bx}};
end

`else


generate
    if (RAM_TYPE == 0) begin
        ram_2p_type_0  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end
    else if (RAM_TYPE == 1) begin
        ram_2p_type_1  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end
    else if (RAM_TYPE == 2) begin
        ram_2p_type_2  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end
    else if (RAM_TYPE == 3) begin
        ram_2p_type_3  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end
    else if (RAM_TYPE == 4) begin
        ram_2p_type_4  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end
    else if (RAM_TYPE == 5) begin
        ram_2p_type_5  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end
    else if (RAM_TYPE == 6) begin
        ram_2p_type_6  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end

endgenerate

`endif







`include "clogb2.vh"

endmodule
module ram_2p_wrapper #(
    parameter   RAM_TYPE        = -1,
    parameter   RAM_DEPTH       = -1,
    parameter   RAM_ADDR_WIDTH  = -1,
    parameter   RAM_DATA_WIDTH  = -1
)(
    input                                   rst_n,
    input                                   clka,
    input                                   ena,
    input                                   wea,
    input           [RAM_ADDR_WIDTH-1:0]    addra,
    input           [RAM_DATA_WIDTH-1:0]    dina,
    output          [RAM_DATA_WIDTH-1:0]    douta,
    input                                   clkb,
    input                                   enb,
    input                                   web,
    input           [RAM_ADDR_WIDTH-1:0]    addrb,
    input           [RAM_DATA_WIDTH-1:0]    dinb,
    output          [RAM_DATA_WIDTH-1:0]    doutb
);

`ifdef VCS_SIMULATION

reg     [RAM_DATA_WIDTH-1:0]    mem [RAM_DEPTH-1:0];
reg     [RAM_DATA_WIDTH-1:0]    douta_f;
reg     [RAM_DATA_WIDTH-1:0]    doutb_f;

genvar ii;

assign douta = douta_f;
assign doutb = doutb_f;

generate
    for (ii = 0; ii < RAM_DEPTH; ii = ii + 1) begin: mem_gen
        always @(posedge clka) begin
            if (~rst_n) begin
                mem[ii] <= {RAM_DATA_WIDTH{1'b0}};
            end
            else begin
                mem[ii] <= ena & wea & (ii == addra) ? dina :
                           enb & web & (ii == addrb) ? dinb : mem[ii];
            end
        end
    end
endgenerate

always @(posedge clka) begin
    douta_f <= ena & ~wea ? mem[addra] : {RAM_DATA_WIDTH{1'bx}};
    doutb_f <= enb & ~web ? mem[addrb] : {RAM_DATA_WIDTH{1'bx}};
end

`else


generate
    if (RAM_TYPE == 0) begin
        ram_2p_type_0  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end
    else if (RAM_TYPE == 1) begin
        ram_2p_type_1  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end
    else if (RAM_TYPE == 2) begin
        ram_2p_type_2  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end
    else if (RAM_TYPE == 3) begin
        ram_2p_type_3  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end
    else if (RAM_TYPE == 4) begin
        ram_2p_type_4  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end
    else if (RAM_TYPE == 5) begin
        ram_2p_type_5  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end
    else if (RAM_TYPE == 6) begin
        ram_2p_type_6  ram_2p   (
          .clka     (clka   ),
          .ena      (ena    ),
          .wea      (wea    ),
          .addra    (addra  ),
          .dina     (dina   ),
          .douta    (douta  ),
          .clkb     (clkb   ),
          .enb      (enb    ),
          .web      (web    ),
          .addrb    (addrb  ),
          .dinb     (dinb   ),
          .doutb    (doutb  ) 
        );
    end

endgenerate

`endif







`include "clogb2.vh"

endmodule