data/full_repos/permissive/18921956/DigitalDesign/Final/final/final_101062124/risc_t.v
 line:148: before: ";"
1: b'%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/Final/final/final_101062124/risc_t.v:96: Unsupported: Ignoring delay on this delayed statement.\n  always #(period/2) clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/18921956/DigitalDesign/Final/final/final_101062124/risc_t.v:113: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile(vcd_file);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/18921956/DigitalDesign/Final/final/final_101062124/risc_t.v:114: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, stimulus);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/Final/final/final_101062124/risc_t.v:132: Unsupported: Ignoring delay on this delayed statement.\n    #(period) rst_n = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/Final/final/final_101062124/risc_t.v:139: Unsupported: Ignoring delay on this delayed statement.\n    #(period*10) rst_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/Final/final/final_101062124/risc_t.v:146: Unsupported: Ignoring delay on this delayed statement.\n  #(period);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/Final/final/final_101062124/risc_t.v:148: Unsupported: Ignoring delay on this delayed statement.\n    #(period) idle;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/Final/final/final_101062124/risc_t.v:149: Unsupported: Ignoring delay on this delayed statement.\n    #(period) idle;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/Final/final/final_101062124/risc_t.v:150: Unsupported: Ignoring delay on this delayed statement.\n    #(period) idle;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/18921956/DigitalDesign/Final/final/final_101062124/risc_t.v:152: Unsupported: Ignoring delay on this delayed statement.\n    #(period*4);\n    ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stimulus;
  parameter data_width = 32;
  parameter address_width = 32;
  parameter address_depth = 2048;
  parameter opcode_width = 7;
  parameter reg_addr_width = 5;
  parameter immediate_width = 15;
  parameter period = 20;
  parameter delay = 1;



  parameter program_code  = "03_division-bin.dat";
  parameter program_data  = "03_division-data.dat";
  parameter sdf_file      = "Processor.sdf";
  parameter fsdb_syn_file = "risc_syn.fsdb";
  parameter fsdb_file     = "risc.fsdb";
  parameter vcd_syn_file  = "risc_syn.vcd";
  parameter vcd_file      = "risc.vcd";
  parameter instr_count   = 20;
  parameter HALT = 32'b11111111111111111111111111111111;

  reg clk;
  reg rst_n;
  wire [31:0] pPC, pdatain, paddr;
  wire pwen, poen;


  reg im_cen;
  reg im_wen;
  reg [10:0] im_addr;
  reg [31:0] im_datain;
  reg im_oen;
  wire [31:0] im_dataout;


  reg dm_cen;
  reg dm_wen;
  reg [10:0] dm_addr;
  reg [31:0] dm_datain;
  reg dm_oen;
  wire [31:0] dm_dataout;

  reg [data_width - 1:0] pc;
  reg [data_width - 1:0] pc_pre;
  reg [data_width - 1:0] ir;
  reg [opcode_width - 1:0] opcode;
  reg [reg_addr_width - 1:0] dr, sa, sb, sh;
  reg signed [immediate_width - 1:0] imm;

  RAM2Kx32 #(
   .preload_file(program_code)
  ) IMEM (
   .Q(im_dataout),
   .CLK(clk),
   .CEN(im_cen),
   .WEN(im_wen),
   .A(im_addr),
   .D(im_datain),
   .OEN(im_oen)
  );

  RAM2Kx32 #(
   .preload_file(program_data)
  ) DMEM (
   .Q(dm_dataout),
   .CLK(clk),
   .CEN(dm_cen),
   .WEN(dm_wen),
   .A(dm_addr),
   .D(dm_datain),
   .OEN(dm_oen)
  );
  SingleCycleProcessor processor (
  	.PC(pPC),
	.datain(pdatain),
	.address(paddr),
	.MW(pwen),
	.MR(poen),
	.instruction(im_dataout),
	.dataout(dm_dataout),
	.clk(clk),
	.reset_n(rst_n)
  );
  always #(period/2) clk = ~clk;

  initial begin
    `ifdef NETLIST
      $sdf_annotate(sdf_file, processor);
      `ifdef FSDB
        $fsdbDumpfile(fsdb_syn_file);
        $fsdbDumpvars;
      `else
        $dumpfile(vcd_syn_file);
        $dumpvars(0, stimulus);
      `endif
    `else
      `ifdef FSDB
        $fsdbDumpfile(fsdb_file);
        $fsdbDumpvars;
      `else
        $dumpfile(vcd_file);
        $dumpvars(0, stimulus);
      `endif
    `endif
  end

  initial begin

    clk = 1;
    rst_n = 1'b1;
    im_cen = 0;
    im_wen = 1'b1;
    im_oen = 1'b1;
    dm_cen = 0;
    dm_wen = 1'b1;
    dm_oen = 1'b1;
    pc = 0;
    pc_pre = 0;

    #(period) rst_n = 0;
	im_oen = 1'b0;
	im_addr = 0;
	dm_datain = pdatain;
	dm_addr = paddr;
	dm_wen = pwen;
	dm_oen = poen;
    #(period*10) rst_n = 1;
	while (im_dataout != HALT) begin
		im_addr = pPC;
		dm_datain = pdatain;
		dm_addr = paddr;
		dm_wen = pwen;
		dm_oen = poen;
		#(period);
	end
    #(period) idle;
    #(period) idle;
    #(period) idle;

    #(period*4);
    $finish;
  end


  task idle;
    begin
      im_wen = 1;
      im_oen = 1;
      im_datain = 32'bz;
    end
  endtask
  task dm_nop;
    begin
      dm_wen = 1;
      dm_oen = 1;
      dm_datain = 32'bz;
    end
  endtask
  always @(posedge clk) begin
    pc_pre = #(delay) pc;
  end

endmodule
module stimulus;

  parameter data_width = 32;
  parameter address_width = 32;
  parameter address_depth = 2048;
  parameter opcode_width = 7;
  parameter reg_addr_width = 5;
  parameter immediate_width = 15;
  parameter period = 20;
  parameter delay = 1;



  parameter program_code  = "03_division-bin.dat";
  parameter program_data  = "03_division-data.dat";
  parameter sdf_file      = "Processor.sdf";
  parameter fsdb_syn_file = "risc_syn.fsdb";
  parameter fsdb_file     = "risc.fsdb";
  parameter vcd_syn_file  = "risc_syn.vcd";
  parameter vcd_file      = "risc.vcd";
  parameter instr_count   = 20;
  parameter HALT = 32'b11111111111111111111111111111111;

  reg clk;
  reg rst_n;
  wire [31:0] pPC, pdatain, paddr;
  wire pwen, poen;


  reg im_cen;
  reg im_wen;
  reg [10:0] im_addr;
  reg [31:0] im_datain;
  reg im_oen;
  wire [31:0] im_dataout;


  reg dm_cen;
  reg dm_wen;
  reg [10:0] dm_addr;
  reg [31:0] dm_datain;
  reg dm_oen;
  wire [31:0] dm_dataout;

  reg [data_width - 1:0] pc;
  reg [data_width - 1:0] pc_pre;
  reg [data_width - 1:0] ir;
  reg [opcode_width - 1:0] opcode;
  reg [reg_addr_width - 1:0] dr, sa, sb, sh;
  reg signed [immediate_width - 1:0] imm;

  RAM2Kx32 #(
   .preload_file(program_code)
  ) IMEM (
   .Q(im_dataout),
   .CLK(clk),
   .CEN(im_cen),
   .WEN(im_wen),
   .A(im_addr),
   .D(im_datain),
   .OEN(im_oen)
  );

  RAM2Kx32 #(
   .preload_file(program_data)
  ) DMEM (
   .Q(dm_dataout),
   .CLK(clk),
   .CEN(dm_cen),
   .WEN(dm_wen),
   .A(dm_addr),
   .D(dm_datain),
   .OEN(dm_oen)
  );
  SingleCycleProcessor processor (
  	.PC(pPC),
	.datain(pdatain),
	.address(paddr),
	.MW(pwen),
	.MR(poen),
	.instruction(im_dataout),
	.dataout(dm_dataout),
	.clk(clk),
	.reset_n(rst_n)
  );
  always #(period/2) clk = ~clk;

  initial begin
    `ifdef NETLIST
      $sdf_annotate(sdf_file, processor);
      `ifdef FSDB
        $fsdbDumpfile(fsdb_syn_file);
        $fsdbDumpvars;
      `else
        $dumpfile(vcd_syn_file);
        $dumpvars(0, stimulus);
      `endif
    `else
      `ifdef FSDB
        $fsdbDumpfile(fsdb_file);
        $fsdbDumpvars;
      `else
        $dumpfile(vcd_file);
        $dumpvars(0, stimulus);
      `endif
    `endif
  end

  initial begin

    clk = 1;
    rst_n = 1'b1;
    im_cen = 0;
    im_wen = 1'b1;
    im_oen = 1'b1;
    dm_cen = 0;
    dm_wen = 1'b1;
    dm_oen = 1'b1;
    pc = 0;
    pc_pre = 0;

    #(period) rst_n = 0;
	im_oen = 1'b0;
	im_addr = 0;
	dm_datain = pdatain;
	dm_addr = paddr;
	dm_wen = pwen;
	dm_oen = poen;
    #(period*10) rst_n = 1;
	while (im_dataout != HALT) begin
		im_addr = pPC;
		dm_datain = pdatain;
		dm_addr = paddr;
		dm_wen = pwen;
		dm_oen = poen;
		#(period);
	end
    #(period) idle;
    #(period) idle;
    #(period) idle;

    #(period*4);
    $finish;
  end


  task idle;
    begin
      im_wen = 1;
      im_oen = 1;
      im_datain = 32'bz;
    end
  endtask
  task dm_nop;
    begin
      dm_wen = 1;
      dm_oen = 1;
      dm_datain = 32'bz;
    end
  endtask
  always @(posedge clk) begin
    pc_pre = #(delay) pc;
  end

endmodule