data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v
 line:272: before: "function"
1: b'%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:49: Cannot find include file: trellis.vh\n`include "trellis.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh.v\n             data/full_repos/permissive/125531440/core/src/main/verilog/loopback,data/full_repos/permissive/125531440/trellis.vh.sv\n             trellis.vh\n             trellis.vh.v\n             trellis.vh.sv\n             obj_dir/trellis.vh\n             obj_dir/trellis.vh.v\n             obj_dir/trellis.vh.sv\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:50: Cannot find include file: ultrascale.vh\n`include "ultrascale.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:66: Define or directive not defined: \'`SIG_CPLID_W\'\n     input [`SIG_CPLID_W-1:0]                CONFIG_COMPLETER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:74: Define or directive not defined: \'`SIG_RQ_TUSER_W\'\n     output [`SIG_RQ_TUSER_W-1:0]            S_AXIS_RQ_TUSER,\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:86: Define or directive not defined: \'`SIG_FBE_W\'\n     input [`SIG_FBE_W-1:0]                  TXR_META_FDWBE, \n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:87: Define or directive not defined: \'`SIG_LBE_W\'\n     input [`SIG_LBE_W-1:0]                  TXR_META_LDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:88: Define or directive not defined: \'`SIG_ADDR_W\'\n     input [`SIG_ADDR_W-1:0]                 TXR_META_ADDR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:89: Define or directive not defined: \'`SIG_LEN_W\'\n     input [`SIG_LEN_W-1:0]                  TXR_META_LENGTH,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:90: Define or directive not defined: \'`SIG_TAG_W\'\n     input [`SIG_TAG_W-1:0]                  TXR_META_TAG,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:91: Define or directive not defined: \'`SIG_TC_W\'\n     input [`SIG_TC_W-1:0]                   TXR_META_TC,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:92: Define or directive not defined: \'`SIG_ATTR_W\'\n     input [`SIG_ATTR_W-1:0]                 TXR_META_ATTR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:93: Define or directive not defined: \'`SIG_TYPE_W\'\n     input [`SIG_TYPE_W-1:0]                 TXR_META_TYPE,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:100: Define or directive not defined: \'`UPKT_TXR_MAXHDR_W\'\n    localparam C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W;\n                                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    localparam C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W;\n                                                   ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:116: Define or directive not defined: \'`SIG_NONPAY_W\'\n    wire [`SIG_NONPAY_W-1:0]                 wTxHdrNonpayLen;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:117: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n    wire [`SIG_PACKETLEN_W-1:0]              wTxHdrPacketLen;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:118: Define or directive not defined: \'`SIG_LEN_W\'\n    wire [`SIG_LEN_W-1:0]                    wTxHdrPayloadLen; \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:177: Define or directive not defined: \'`SIG_LEN_W\'\n         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:178: Define or directive not defined: \'`SIG_NONPAY_W\'\n         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:179: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:188: Define or directive not defined: \'`SIG_CPLID_W\'\n         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),\n                                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:190: Define or directive not defined: \'`SIG_FBE_W\'\n         .TXR_META_FDWBE                (TXR_META_FDWBE[`SIG_FBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:191: Define or directive not defined: \'`SIG_LBE_W\'\n         .TXR_META_LDWBE                (TXR_META_LDWBE[`SIG_LBE_W-1:0]),\n                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:192: Define or directive not defined: \'`SIG_ADDR_W\'\n         .TXR_META_ADDR                 (TXR_META_ADDR[`SIG_ADDR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:193: Define or directive not defined: \'`SIG_LEN_W\'\n         .TXR_META_LENGTH               (TXR_META_LENGTH[`SIG_LEN_W-1:0]),\n                                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:194: Define or directive not defined: \'`SIG_TAG_W\'\n         .TXR_META_TAG                  (TXR_META_TAG[`SIG_TAG_W-1:0]),\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:195: Define or directive not defined: \'`SIG_TC_W\'\n         .TXR_META_TC                   (TXR_META_TC[`SIG_TC_W-1:0]),\n                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:196: Define or directive not defined: \'`SIG_ATTR_W\'\n         .TXR_META_ATTR                 (TXR_META_ATTR[`SIG_ATTR_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:197: Define or directive not defined: \'`SIG_TYPE_W\'\n         .TXR_META_TYPE                 (TXR_META_TYPE[`SIG_TYPE_W-1:0]),\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:225: Define or directive not defined: \'`SIG_LEN_W\'\n         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:226: Define or directive not defined: \'`SIG_NONPAY_W\'\n         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:227: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:264: Define or directive not defined: \'`SIG_RQ_TUSER_W\'\n         .S_AXIS_RQ_TUSER               (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),\n                                                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:278: Define or directive not defined: \'`UPKT_TXR_MAXHDR_W\'\n      parameter C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W,\n                                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:278: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      parameter C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W,\n                                                    ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:280: syntax error, unexpected parameter, expecting IDENTIFIER\n      parameter C_MAX_PACKET_DWORDS = 10\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:281: syntax error, unexpected \')\', expecting \';\'\n      )\n      ^\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:290: Define or directive not defined: \'`SIG_CPLID_W\'\n     input [`SIG_CPLID_W-1:0]      CONFIG_COMPLETER_ID,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:294: Define or directive not defined: \'`SIG_FBE_W\'\n     input [`SIG_FBE_W-1:0]        TXR_META_FDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:295: Define or directive not defined: \'`SIG_LBE_W\'\n     input [`SIG_LBE_W-1:0]        TXR_META_LDWBE,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:296: Define or directive not defined: \'`SIG_ADDR_W\'\n     input [`SIG_ADDR_W-1:0]       TXR_META_ADDR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:297: Define or directive not defined: \'`SIG_LEN_W\'\n     input [`SIG_LEN_W-1:0]        TXR_META_LENGTH,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:298: Define or directive not defined: \'`SIG_TAG_W\'\n     input [`SIG_TAG_W-1:0]        TXR_META_TAG,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:299: Define or directive not defined: \'`SIG_TC_W\'\n     input [`SIG_TC_W-1:0]         TXR_META_TC,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:300: Define or directive not defined: \'`SIG_ATTR_W\'\n     input [`SIG_ATTR_W-1:0]       TXR_META_ATTR,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:301: Define or directive not defined: \'`SIG_TYPE_W\'\n     input [`SIG_TYPE_W-1:0]       TXR_META_TYPE,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:308: Define or directive not defined: \'`SIG_LEN_W\'\n     output [`SIG_LEN_W-1:0]       TX_HDR_PAYLOAD_LEN,\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:309: Define or directive not defined: \'`SIG_NONPAY_W\'\n     output [`SIG_NONPAY_W-1:0]    TX_HDR_NONPAY_LEN,\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:310: Define or directive not defined: \'`SIG_PACKETLEN_W\'\n     output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/125531440/core/src/main/verilog/loopback/txr_engine_ultrascale.v:316: Define or directive not defined: \'`UPKT_TXR_MAXHDR_W\'\n    wire [`UPKT_TXR_MAXHDR_W-1:0]  wHdr;\n          ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module txr_engine_ultrascale
    #(parameter C_PCI_DATA_WIDTH = 128,
      parameter C_PIPELINE_INPUT = 1,
      parameter C_PIPELINE_OUTPUT = 1,
      parameter C_DEPTH_PACKETS = 10,
      parameter C_MAX_PAYLOAD_DWORDS = 256)
    (
     input                                   CLK,


     input                                   RST_BUS,
     input                                   RST_LOGIC,
     output                                  DONE_TXR_RST,


     input [`SIG_CPLID_W-1:0]                CONFIG_COMPLETER_ID,


     input                                   S_AXIS_RQ_TREADY,
     output                                  S_AXIS_RQ_TVALID,
     output                                  S_AXIS_RQ_TLAST,
     output [C_PCI_DATA_WIDTH-1:0]           S_AXIS_RQ_TDATA,
     output [(C_PCI_DATA_WIDTH/32)-1:0]      S_AXIS_RQ_TKEEP,
     output [`SIG_RQ_TUSER_W-1:0]            S_AXIS_RQ_TUSER,


     input                                   TXR_DATA_VALID,
     input [C_PCI_DATA_WIDTH-1:0]            TXR_DATA,
     input                                   TXR_DATA_START_FLAG,
     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
     input                                   TXR_DATA_END_FLAG,
     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
     output                                  TXR_DATA_READY,

     input                                   TXR_META_VALID,
     input [`SIG_FBE_W-1:0]                  TXR_META_FDWBE, 
     input [`SIG_LBE_W-1:0]                  TXR_META_LDWBE,
     input [`SIG_ADDR_W-1:0]                 TXR_META_ADDR,
     input [`SIG_LEN_W-1:0]                  TXR_META_LENGTH,
     input [`SIG_TAG_W-1:0]                  TXR_META_TAG,
     input [`SIG_TC_W-1:0]                   TXR_META_TC,
     input [`SIG_ATTR_W-1:0]                 TXR_META_ATTR,
     input [`SIG_TYPE_W-1:0]                 TXR_META_TYPE,
     input                                   TXR_META_EP,
     output                                  TXR_META_READY     
     );

    localparam C_VENDOR = "XILINX";
    localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
    localparam C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W;
    localparam C_MAX_HDR_DWORDS = C_MAX_HDR_WIDTH/32;
    localparam C_MAX_ALIGN_DWORDS = 0;
    localparam C_MAX_NONPAY_DWORDS = C_MAX_HDR_DWORDS + C_MAX_ALIGN_DWORDS + 1;
    localparam C_MAX_PACKET_DWORDS = C_MAX_NONPAY_DWORDS + C_MAX_PAYLOAD_DWORDS;
    localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
    localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
    localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
    localparam C_RST_COUNT = 10;



    
    wire                                     wTxHdrReady;
    wire                                     wTxHdrValid;
    wire [C_MAX_HDR_WIDTH-1:0]               wTxHdr;
    wire [`SIG_NONPAY_W-1:0]                 wTxHdrNonpayLen;
    wire [`SIG_PACKETLEN_W-1:0]              wTxHdrPacketLen;
    wire [`SIG_LEN_W-1:0]                    wTxHdrPayloadLen; 
    wire                                     wTxHdrNopayload;

    wire                                     wTxDataReady;
    wire [C_PCI_DATA_WIDTH-1:0]              wTxData;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxDataEndOffset;
    wire                                     wTxDataStartFlag;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wTxDataEndFlags;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wTxDataWordValid;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wTxDataWordReady;

    wire [C_PCI_DATA_WIDTH-1:0]              wTxrPkt;
    wire                                     wTxrPktEndFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxrPktEndOffset;
    wire                                     wTxrPktStartFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxrPktStartOffset;
    wire                                     wTxrPktValid;
    wire                                     wTxrPktReady;

    wire                                     wTransDoneRst;
    wire                                     wTransRstOut;
    wire                                     wDoneEngRst;
    wire                                     wRst;
    wire [C_RST_COUNT:0]                     wShiftRegRst;

    assign DONE_TXR_RST = wTransDoneRst & wDoneEngRst;
    assign wRst = wShiftRegRst[C_RST_COUNT-3];
    assign wDoneEngRst = ~wShiftRegRst[C_RST_COUNT];
    
    shiftreg
        #(
          .C_DEPTH                      (C_RST_COUNT),
          .C_WIDTH                      (1),
          .C_VALUE                      (1)
)
    rst_shiftreg
        (
         .RD_DATA                       (wShiftRegRst),

         .RST_IN                        (RST_BUS),
         .WR_DATA                       (wTransRstOut),


         .CLK                           (CLK));
         
    txr_formatter_ultrascale
        #(.C_PIPELINE_OUTPUT            (C_PIPELINE_FORMATTER_OUTPUT),
          .C_PIPELINE_INPUT             (C_PIPELINE_FORMATTER_INPUT),


          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH),
          .C_MAX_NONPAY_DWORDS          (C_MAX_NONPAY_DWORDS),
          .C_MAX_PACKET_DWORDS          (C_MAX_PACKET_DWORDS))
    txr_formatter_inst
        (
         .TX_HDR_VALID                  (wTxHdrValid),
         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
         .TX_HDR_NOPAYLOAD              (wTxHdrNopayload),
         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),

         .TX_HDR_READY                  (wTxHdrReady),
         .RST_IN                        (wRst),


         .TXR_META_READY                (TXR_META_READY),

         .CLK                           (CLK),
         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
         .TXR_META_VALID                (TXR_META_VALID),
         .TXR_META_FDWBE                (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
         .TXR_META_LDWBE                (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
         .TXR_META_ADDR                 (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
         .TXR_META_LENGTH               (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
         .TXR_META_TAG                  (TXR_META_TAG[`SIG_TAG_W-1:0]),
         .TXR_META_TC                   (TXR_META_TC[`SIG_TC_W-1:0]),
         .TXR_META_ATTR                 (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
         .TXR_META_TYPE                 (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
         .TXR_META_EP                   (TXR_META_EP));

    tx_engine
        #(.C_DATA_WIDTH                 (C_PCI_DATA_WIDTH),


          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS),
          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
          .C_FORMATTER_DELAY            (C_FORMATTER_DELAY),
          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH),
          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_DWORDS),
          .C_VENDOR                     (C_VENDOR))
    txr_engine_inst
        (
         .TX_HDR_READY                  (wTxHdrReady),
         .TX_DATA_READY                 (TXR_DATA_READY),
         .TX_PKT                        (wTxrPkt[C_DATA_WIDTH-1:0]),
         .TX_PKT_START_FLAG             (wTxrPktStartFlag),
         .TX_PKT_START_OFFSET           (wTxrPktStartOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
         .TX_PKT_END_FLAG               (wTxrPktEndFlag),
         .TX_PKT_END_OFFSET             (wTxrPktEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
         .TX_PKT_VALID                  (wTxrPktValid),

         .TX_HDR_VALID                  (wTxHdrValid),
         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
         .TX_HDR_NOPAYLOAD              (wTxHdrNopayload),
         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
         .TX_DATA_VALID                 (TXR_DATA_VALID),
         .TX_DATA                       (TXR_DATA[C_DATA_WIDTH-1:0]),
         .TX_DATA_START_FLAG            (TXR_DATA_START_FLAG),
         .TX_DATA_START_OFFSET          (TXR_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
         .TX_DATA_END_FLAG              (TXR_DATA_END_FLAG),
         .TX_DATA_END_OFFSET            (TXR_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
         .TX_PKT_READY                  (wTxrPktReady),
         .RST_IN                        (wRst),


         .CLK                           (CLK));

    txr_translation_layer
        #(

          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
          .C_RST_COUNT                  (C_RST_COUNT))
    txr_trans_inst
        (
         .TXR_PKT_READY                 (wTxrPktReady),
         .DONE_RST                      (wTransDoneRst),
         .RST_OUT                       (wTransRstOut),

         .TXR_PKT                       (wTxrPkt),
         .TXR_PKT_VALID                 (wTxrPktValid),
         .TXR_PKT_START_FLAG            (wTxrPktStartFlag),
         .TXR_PKT_START_OFFSET          (wTxrPktStartOffset),
         .TXR_PKT_END_FLAG              (wTxrPktEndFlag),
         .TXR_PKT_END_OFFSET            (wTxrPktEndOffset),


         .S_AXIS_RQ_TVALID              (S_AXIS_RQ_TVALID),
         .S_AXIS_RQ_TLAST               (S_AXIS_RQ_TLAST),
         .S_AXIS_RQ_TDATA               (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
         .S_AXIS_RQ_TKEEP               (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
         .S_AXIS_RQ_TUSER               (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),

         .CLK                           (CLK),
         .RST_BUS                       (RST_BUS),
         .RST_LOGIC                     (RST_LOGIC),
         .S_AXIS_RQ_TREADY              (S_AXIS_RQ_TREADY));
endmodule
module txr_engine_ultrascale
    #(parameter C_PCI_DATA_WIDTH = 128,
      parameter C_PIPELINE_INPUT = 1,
      parameter C_PIPELINE_OUTPUT = 1,
      parameter C_DEPTH_PACKETS = 10,
      parameter C_MAX_PAYLOAD_DWORDS = 256)
    (
     input                                   CLK,


     input                                   RST_BUS,
     input                                   RST_LOGIC,
     output                                  DONE_TXR_RST,


     input [`SIG_CPLID_W-1:0]                CONFIG_COMPLETER_ID,


     input                                   S_AXIS_RQ_TREADY,
     output                                  S_AXIS_RQ_TVALID,
     output                                  S_AXIS_RQ_TLAST,
     output [C_PCI_DATA_WIDTH-1:0]           S_AXIS_RQ_TDATA,
     output [(C_PCI_DATA_WIDTH/32)-1:0]      S_AXIS_RQ_TKEEP,
     output [`SIG_RQ_TUSER_W-1:0]            S_AXIS_RQ_TUSER,


     input                                   TXR_DATA_VALID,
     input [C_PCI_DATA_WIDTH-1:0]            TXR_DATA,
     input                                   TXR_DATA_START_FLAG,
     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
     input                                   TXR_DATA_END_FLAG,
     input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
     output                                  TXR_DATA_READY,

     input                                   TXR_META_VALID,
     input [`SIG_FBE_W-1:0]                  TXR_META_FDWBE, 
     input [`SIG_LBE_W-1:0]                  TXR_META_LDWBE,
     input [`SIG_ADDR_W-1:0]                 TXR_META_ADDR,
     input [`SIG_LEN_W-1:0]                  TXR_META_LENGTH,
     input [`SIG_TAG_W-1:0]                  TXR_META_TAG,
     input [`SIG_TC_W-1:0]                   TXR_META_TC,
     input [`SIG_ATTR_W-1:0]                 TXR_META_ATTR,
     input [`SIG_TYPE_W-1:0]                 TXR_META_TYPE,
     input                                   TXR_META_EP,
     output                                  TXR_META_READY     
     );


    localparam C_VENDOR = "XILINX";
    localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
    localparam C_MAX_HDR_WIDTH = `UPKT_TXR_MAXHDR_W;
    localparam C_MAX_HDR_DWORDS = C_MAX_HDR_WIDTH/32;
    localparam C_MAX_ALIGN_DWORDS = 0;
    localparam C_MAX_NONPAY_DWORDS = C_MAX_HDR_DWORDS + C_MAX_ALIGN_DWORDS + 1;
    localparam C_MAX_PACKET_DWORDS = C_MAX_NONPAY_DWORDS + C_MAX_PAYLOAD_DWORDS;
    localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
    localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
    localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
    localparam C_RST_COUNT = 10;



    
    wire                                     wTxHdrReady;
    wire                                     wTxHdrValid;
    wire [C_MAX_HDR_WIDTH-1:0]               wTxHdr;
    wire [`SIG_NONPAY_W-1:0]                 wTxHdrNonpayLen;
    wire [`SIG_PACKETLEN_W-1:0]              wTxHdrPacketLen;
    wire [`SIG_LEN_W-1:0]                    wTxHdrPayloadLen; 
    wire                                     wTxHdrNopayload;

    wire                                     wTxDataReady;
    wire [C_PCI_DATA_WIDTH-1:0]              wTxData;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxDataEndOffset;
    wire                                     wTxDataStartFlag;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wTxDataEndFlags;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wTxDataWordValid;
    wire [(C_PCI_DATA_WIDTH/32)-1:0]         wTxDataWordReady;

    wire [C_PCI_DATA_WIDTH-1:0]              wTxrPkt;
    wire                                     wTxrPktEndFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxrPktEndOffset;
    wire                                     wTxrPktStartFlag;
    wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0]   wTxrPktStartOffset;
    wire                                     wTxrPktValid;
    wire                                     wTxrPktReady;

    wire                                     wTransDoneRst;
    wire                                     wTransRstOut;
    wire                                     wDoneEngRst;
    wire                                     wRst;
    wire [C_RST_COUNT:0]                     wShiftRegRst;

    assign DONE_TXR_RST = wTransDoneRst & wDoneEngRst;
    assign wRst = wShiftRegRst[C_RST_COUNT-3];
    assign wDoneEngRst = ~wShiftRegRst[C_RST_COUNT];
    
    shiftreg
        #(
          .C_DEPTH                      (C_RST_COUNT),
          .C_WIDTH                      (1),
          .C_VALUE                      (1)
)
    rst_shiftreg
        (
         .RD_DATA                       (wShiftRegRst),

         .RST_IN                        (RST_BUS),
         .WR_DATA                       (wTransRstOut),


         .CLK                           (CLK));
         
    txr_formatter_ultrascale
        #(.C_PIPELINE_OUTPUT            (C_PIPELINE_FORMATTER_OUTPUT),
          .C_PIPELINE_INPUT             (C_PIPELINE_FORMATTER_INPUT),


          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH),
          .C_MAX_NONPAY_DWORDS          (C_MAX_NONPAY_DWORDS),
          .C_MAX_PACKET_DWORDS          (C_MAX_PACKET_DWORDS))
    txr_formatter_inst
        (
         .TX_HDR_VALID                  (wTxHdrValid),
         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
         .TX_HDR_NOPAYLOAD              (wTxHdrNopayload),
         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),

         .TX_HDR_READY                  (wTxHdrReady),
         .RST_IN                        (wRst),


         .TXR_META_READY                (TXR_META_READY),

         .CLK                           (CLK),
         .CONFIG_COMPLETER_ID           (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
         .TXR_META_VALID                (TXR_META_VALID),
         .TXR_META_FDWBE                (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
         .TXR_META_LDWBE                (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
         .TXR_META_ADDR                 (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
         .TXR_META_LENGTH               (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
         .TXR_META_TAG                  (TXR_META_TAG[`SIG_TAG_W-1:0]),
         .TXR_META_TC                   (TXR_META_TC[`SIG_TC_W-1:0]),
         .TXR_META_ATTR                 (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
         .TXR_META_TYPE                 (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
         .TXR_META_EP                   (TXR_META_EP));

    tx_engine
        #(.C_DATA_WIDTH                 (C_PCI_DATA_WIDTH),


          .C_DEPTH_PACKETS              (C_DEPTH_PACKETS),
          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
          .C_PIPELINE_OUTPUT            (C_PIPELINE_OUTPUT),
          .C_FORMATTER_DELAY            (C_FORMATTER_DELAY),
          .C_MAX_HDR_WIDTH              (C_MAX_HDR_WIDTH),
          .C_MAX_PAYLOAD_DWORDS         (C_MAX_PAYLOAD_DWORDS),
          .C_VENDOR                     (C_VENDOR))
    txr_engine_inst
        (
         .TX_HDR_READY                  (wTxHdrReady),
         .TX_DATA_READY                 (TXR_DATA_READY),
         .TX_PKT                        (wTxrPkt[C_DATA_WIDTH-1:0]),
         .TX_PKT_START_FLAG             (wTxrPktStartFlag),
         .TX_PKT_START_OFFSET           (wTxrPktStartOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
         .TX_PKT_END_FLAG               (wTxrPktEndFlag),
         .TX_PKT_END_OFFSET             (wTxrPktEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
         .TX_PKT_VALID                  (wTxrPktValid),

         .TX_HDR_VALID                  (wTxHdrValid),
         .TX_HDR                        (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
         .TX_HDR_NOPAYLOAD              (wTxHdrNopayload),
         .TX_HDR_PAYLOAD_LEN            (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
         .TX_HDR_NONPAY_LEN             (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
         .TX_HDR_PACKET_LEN             (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
         .TX_DATA_VALID                 (TXR_DATA_VALID),
         .TX_DATA                       (TXR_DATA[C_DATA_WIDTH-1:0]),
         .TX_DATA_START_FLAG            (TXR_DATA_START_FLAG),
         .TX_DATA_START_OFFSET          (TXR_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
         .TX_DATA_END_FLAG              (TXR_DATA_END_FLAG),
         .TX_DATA_END_OFFSET            (TXR_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
         .TX_PKT_READY                  (wTxrPktReady),
         .RST_IN                        (wRst),


         .CLK                           (CLK));

    txr_translation_layer
        #(

          .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
          .C_PIPELINE_INPUT             (C_PIPELINE_INPUT),
          .C_RST_COUNT                  (C_RST_COUNT))
    txr_trans_inst
        (
         .TXR_PKT_READY                 (wTxrPktReady),
         .DONE_RST                      (wTransDoneRst),
         .RST_OUT                       (wTransRstOut),

         .TXR_PKT                       (wTxrPkt),
         .TXR_PKT_VALID                 (wTxrPktValid),
         .TXR_PKT_START_FLAG            (wTxrPktStartFlag),
         .TXR_PKT_START_OFFSET          (wTxrPktStartOffset),
         .TXR_PKT_END_FLAG              (wTxrPktEndFlag),
         .TXR_PKT_END_OFFSET            (wTxrPktEndOffset),


         .S_AXIS_RQ_TVALID              (S_AXIS_RQ_TVALID),
         .S_AXIS_RQ_TLAST               (S_AXIS_RQ_TLAST),
         .S_AXIS_RQ_TDATA               (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
         .S_AXIS_RQ_TKEEP               (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
         .S_AXIS_RQ_TUSER               (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),

         .CLK                           (CLK),
         .RST_BUS                       (RST_BUS),
         .RST_LOGIC                     (RST_LOGIC),
         .S_AXIS_RQ_TREADY              (S_AXIS_RQ_TREADY));
endmodule