data/full_repos/permissive/13953497/unary_select_pair.v
[Errno 2] No such file or directory: 'preprocess.output'
1: b"%Error: data/full_repos/permissive/13953497/unary_select_pair.v:50: Can't find definition of task/function: 'LAG_route_valid_turn'\n  assign selected[i*WB+j] = (LAG_route_valid_turn(input_port, i)) ?\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module unary_select_pair (sel_a, sel_b, data_in, selected_bit);

   parameter input_port = 0;
   parameter WA = 4;
   parameter WB = 4;

   input [WA-1:0] sel_a;
   input [WB-1:0] sel_b;
   input [WA*WB-1:0] data_in;
   output selected_bit;

   genvar i,j;

   wire [WA*WB-1:0]  selected;
   
   generate
   for (i=0; i<WA; i=i+1) begin:ol
      for (j=0; j<WB; j=j+1) begin:il

	 assign selected[i*WB+j] = (LAG_route_valid_turn(input_port, i)) ?
				   data_in[i*WB+j] & sel_a[i] & sel_b[j] : 1'b0;
	 

      end
   end
   endgenerate

   assign selected_bit=|selected;
   
endmodule
module unary_select_pair (sel_a, sel_b, data_in, selected_bit);


   parameter input_port = 0;
   parameter WA = 4;
   parameter WB = 4;

   input [WA-1:0] sel_a;
   input [WB-1:0] sel_b;
   input [WA*WB-1:0] data_in;
   output selected_bit;

   genvar i,j;

   wire [WA*WB-1:0]  selected;
   
   generate
   for (i=0; i<WA; i=i+1) begin:ol
      for (j=0; j<WB; j=j+1) begin:il

	 assign selected[i*WB+j] = (LAG_route_valid_turn(input_port, i)) ?
				   data_in[i*WB+j] & sel_a[i] & sel_b[j] : 1'b0;
	 

      end
   end
   endgenerate

   assign selected_bit=|selected;
   
endmodule