data/full_repos/permissive/152129793/comun/modulos.v
1: b'%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:576: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.los_interruptores\n  wire [7:0] posx = hc - XINIT;   \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:577: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.los_interruptores\n  wire [7:0] posy = vc - YINIT;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:503: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.display_leds\n  wire [7:0] pos = hc - XINIT;   \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:399: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 or 11 bits.\n                                                                        : ... In instance display.display_digitos\n    posicion_caracter_en_pantalla = (hc - XINIT + 1)>>4;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:403: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.display_digitos\n  wire [7:0] posx = hc - XINIT;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:404: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                        : ... In instance display.display_digitos\n  wire [7:0] posy = vc - YINIT;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/152129793/comun/modulos.v:436: Bit extraction of array[127:0] requires 7 bit index, not 8 bits.\n                                                                        : ... In instance display.display_digitos\n        scan_actual <= chars[charaddr];\n                            ^\n%Warning-UNSIGNED: data/full_repos/permissive/152129793/comun/modulos.v:216: Comparison is constant due to unsigned arithmetic\n                                                                           : ... In instance display.sincronismos\n    if (hcont>=0 && hcont<HACTIVE && vcont>=0 && vcont<VACTIVE)\n             ^~\n%Warning-UNSIGNED: data/full_repos/permissive/152129793/comun/modulos.v:216: Comparison is constant due to unsigned arithmetic\n                                                                           : ... In instance display.sincronismos\n    if (hcont>=0 && hcont<HACTIVE && vcont>=0 && vcont<VACTIVE)\n                                          ^~\n%Error: Exiting due to 9 warning(s)\n'
module videosyncs (
  input wire clk,
  output reg hs,
  output reg vs,
 	output wire [10:0] hc,
	output wire [10:0] vc,
  output reg display_enable
  );
	






  parameter HACTIVE = 640;
  parameter HFRONTPORCH = 656;
  parameter HSYNCPULSE = 752;
	parameter HTOTAL = 800;
  parameter VACTIVE = 480;
  parameter VFRONTPORCH = 490;
  parameter VSYNCPULSE = 492;
  parameter VTOTAL = 525;
  parameter HSYNCPOL = 0;
  parameter VSYNCPOL = 0;

  reg [10:0] hcont = 0;
  reg [10:0] vcont = 0;
	
  assign hc = hcont;
  assign vc = vcont;

  always @(posedge clk) begin
      if (hcont == HTOTAL-1) begin
         hcont <= 11'd0;
         if (vcont == VTOTAL-1) begin
            vcont <= 11'd0;
         end
         else begin
            vcont <= vcont + 11'd1;
         end
      end
      else begin
         hcont <= hcont + 11'd1;
      end
  end
   
  always @* begin
    if (hcont>=0 && hcont<HACTIVE && vcont>=0 && vcont<VACTIVE)
      display_enable = 1'b1;
    else
      display_enable = 1'b0;

    if (hcont>=HFRONTPORCH && hcont<HSYNCPULSE)
      hs = HSYNCPOL;
    else
      hs = ~HSYNCPOL;

    if (vcont>=VFRONTPORCH && vcont<VSYNCPULSE)
      vs = VSYNCPOL;
    else
      vs = ~VSYNCPOL;
  end
endmodule
module videosyncs (
  input wire clk,
  output reg hs,
  output reg vs,
 	output wire [10:0] hc,
	output wire [10:0] vc,
  output reg display_enable
  );

	






  parameter HACTIVE = 640;
  parameter HFRONTPORCH = 656;
  parameter HSYNCPULSE = 752;
	parameter HTOTAL = 800;
  parameter VACTIVE = 480;
  parameter VFRONTPORCH = 490;
  parameter VSYNCPULSE = 492;
  parameter VTOTAL = 525;
  parameter HSYNCPOL = 0;
  parameter VSYNCPOL = 0;

  reg [10:0] hcont = 0;
  reg [10:0] vcont = 0;
	
  assign hc = hcont;
  assign vc = vcont;

  always @(posedge clk) begin
      if (hcont == HTOTAL-1) begin
         hcont <= 11'd0;
         if (vcont == VTOTAL-1) begin
            vcont <= 11'd0;
         end
         else begin
            vcont <= vcont + 11'd1;
         end
      end
      else begin
         hcont <= hcont + 11'd1;
      end
  end
   
  always @* begin
    if (hcont>=0 && hcont<HACTIVE && vcont>=0 && vcont<VACTIVE)
      display_enable = 1'b1;
    else
      display_enable = 1'b0;

    if (hcont>=HFRONTPORCH && hcont<HSYNCPULSE)
      hs = HSYNCPOL;
    else
      hs = ~HSYNCPOL;

    if (vcont>=VFRONTPORCH && vcont<VSYNCPULSE)
      vs = VSYNCPOL;
    else
      vs = ~VSYNCPOL;
  end
endmodule