data/full_repos/permissive/161029703/testbench/cache_test/test_cache.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/161029703/testbench/cache_test/test_cache.sv:57: Unsupported: Ignoring delay on this delayed statement.\n    #5 rst_n = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/161029703/testbench/cache_test/test_cache.sv:58: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: data/full_repos/permissive/161029703/testbench/cache_test/test_cache.sv:67: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: data/full_repos/permissive/161029703/testbench/cache_test/test_cache.sv:72: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: data/full_repos/permissive/161029703/testbench/cache_test/test_cache.sv:79: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: data/full_repos/permissive/161029703/testbench/cache_test/test_cache.sv:85: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/161029703/testbench/cache_test/test_cache.sv:91: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;  \n       ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_cache ();



		
reg        rst_n;
reg        clk;
		
reg [31:0] avalon_slave_address;
reg        avalon_slave_read;
reg        avalon_slave_write;
wire [31:0] avalon_slave_readdata;
reg [31:0] avalon_slave_writedata;
wire        avalon_slave_waitrequest;
		
reg [31:0] avalon_rdslave_address;
reg        avalon_rdslave_read;
wire [31:0] avalon_rdslave_readdata;
wire        avalon_rdslave_waitrequest;


Cache #(
            .CACHE_LINE_WIDTH (4), 
            .TAG_WIDTH        (24),
            .ADDR_WIDTH       (32)
) cache (
  .avalon_master_address(),
  .avalon_master_burstcount(),
  .avalon_master_readdata(),
  .avalon_master_writedata(),
  .avalon_master_waitrequest(),
  .avalon_master_read(),
  .avalon_master_write(),
  .avalon_master_readdatavalid(),
  
  .rst_n(rst_n),
  .clk(clk),
  
  .avalon_slave_address(avalon_slave_address),
  .avalon_slave_read(avalon_slave_read),
  .avalon_slave_write(avalon_slave_write),
  .avalon_slave_readdata(avalon_slave_readdata),
  .avalon_slave_writedata(avalon_slave_writedata),
  .avalon_slave_waitrequest(avalon_slave_waitrequest),
  
  .avalon_rdslave_address(avalon_rdslave_address),
  .avalon_rdslave_read(avalon_rdslave_read),
  .avalon_rdslave_readdata(avalon_rdslave_readdata),
  .avalon_rdslave_waitrequest(avalon_rdslave_waitrequest)
);


initial begin 
    clk = 0;
    rst_n = 0;
    #5 rst_n = 1;
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
    
    avalon_slave_address = 32'h000000_0_c;
    avalon_slave_read = 1;
    avalon_rdslave_address = 32'h000000_1_4;
    avalon_rdslave_read = 1;
    
    @(negedge clk);
    
      avalon_slave_address = 32'h000000_2_0;
    avalon_rdslave_address = 32'h000000_2_8;
    
    @(negedge clk);
    
    avalon_slave_read = 0;
    avalon_rdslave_read = 0;
    avalon_slave_write = 1;
    avalon_slave_writedata = 32'hdeadbeef;
    
    @(negedge clk);
    
    avalon_slave_write = 0;
    avalon_rdslave_read = 1;
    avalon_rdslave_address = 32'h000000_2_0;
    
    @(negedge clk);
    avalon_rdslave_read = 0;
    
    
end

always #1 clk = ~clk;

endmodule
module test_cache ();




		
reg        rst_n;
reg        clk;
		
reg [31:0] avalon_slave_address;
reg        avalon_slave_read;
reg        avalon_slave_write;
wire [31:0] avalon_slave_readdata;
reg [31:0] avalon_slave_writedata;
wire        avalon_slave_waitrequest;
		
reg [31:0] avalon_rdslave_address;
reg        avalon_rdslave_read;
wire [31:0] avalon_rdslave_readdata;
wire        avalon_rdslave_waitrequest;


Cache #(
            .CACHE_LINE_WIDTH (4), 
            .TAG_WIDTH        (24),
            .ADDR_WIDTH       (32)
) cache (
  .avalon_master_address(),
  .avalon_master_burstcount(),
  .avalon_master_readdata(),
  .avalon_master_writedata(),
  .avalon_master_waitrequest(),
  .avalon_master_read(),
  .avalon_master_write(),
  .avalon_master_readdatavalid(),
  
  .rst_n(rst_n),
  .clk(clk),
  
  .avalon_slave_address(avalon_slave_address),
  .avalon_slave_read(avalon_slave_read),
  .avalon_slave_write(avalon_slave_write),
  .avalon_slave_readdata(avalon_slave_readdata),
  .avalon_slave_writedata(avalon_slave_writedata),
  .avalon_slave_waitrequest(avalon_slave_waitrequest),
  
  .avalon_rdslave_address(avalon_rdslave_address),
  .avalon_rdslave_read(avalon_rdslave_read),
  .avalon_rdslave_readdata(avalon_rdslave_readdata),
  .avalon_rdslave_waitrequest(avalon_rdslave_waitrequest)
);


initial begin 
    clk = 0;
    rst_n = 0;
    #5 rst_n = 1;
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
    
    avalon_slave_address = 32'h000000_0_c;
    avalon_slave_read = 1;
    avalon_rdslave_address = 32'h000000_1_4;
    avalon_rdslave_read = 1;
    
    @(negedge clk);
    
      avalon_slave_address = 32'h000000_2_0;
    avalon_rdslave_address = 32'h000000_2_8;
    
    @(negedge clk);
    
    avalon_slave_read = 0;
    avalon_rdslave_read = 0;
    avalon_slave_write = 1;
    avalon_slave_writedata = 32'hdeadbeef;
    
    @(negedge clk);
    
    avalon_slave_write = 0;
    avalon_rdslave_read = 1;
    avalon_rdslave_address = 32'h000000_2_0;
    
    @(negedge clk);
    avalon_rdslave_read = 0;
    
    
end

always #1 clk = ~clk;

endmodule