data/full_repos/permissive/135008983/code/D_FF.v
data/verilator_xmls/44e8f8a4-5318-41b0-816e-6115633aab84.xml
module D_FF (Q, D, Store, nRST);
parameter   N =  3;
output reg [N:0] Q; 
input      [N:0] D;
input  Store, nRST; 

always @(posedge Store or negedge nRST)
begin
	if (!nRST) Q <= 4'b0000; 
	else Q <= D;
end
endmodule
module D_FF (Q, D, Store, nRST);

parameter   N =  3;
output reg [N:0] Q; 
input      [N:0] D;
input  Store, nRST; 

always @(posedge Store or negedge nRST)
begin
	if (!nRST) Q <= 4'b0000; 
	else Q <= D;
end
endmodule