data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_stagger.v
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1: b'%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_stagger.v:120: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                             : ... In instance signal_stagger\n      phase_offset = $random;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_stagger.v:132: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                             : ... In instance signal_stagger\n        phase_jitter = $random;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_stagger.v:150: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n                                                                                                             : ... In instance signal_stagger\n       q   <= #DELAY \'bz;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/20430511/hardware/FPGA/tart_spi/bench/capture/signal_stagger.v:175: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'rnext\' generates 5 bits.\n                                                                                                             : ... In instance signal_stagger\n        ratio <= #DELAY rnext;\n              ^~\n%Error: Exiting due to 4 warning(s)\n'
module signal_stagger
  #(
    parameter WIDTH = 1,
    parameter MSB   = WIDTH-1,


    parameter RATIO = 12,
    parameter RBITS = 4,
    parameter RSB   = RBITS-1,
    parameter RZERO = 0,
    parameter RHALF = RATIO>>1,
    parameter RMAX  = RATIO-1,

    parameter CBITS = RBITS+1,
    parameter CSB   = CBITS-1,
    parameter CZERO = 0,
    parameter CHALF = RATIO>>1,
    parameter CMAX  = RATIO-1,


    parameter PHASE_JITTER = 1,
    parameter PHASE_OFFSET = 1,
    parameter CYCLE_JITTER = 1,


    parameter NOISY = 0,
    parameter DELAY = 3)
   (
    input              clk,
    input              rst,
    input              ce,
    input [MSB:0]      d,
    output reg         vld = 1'b0,
    output             stb,
    output reg [MSB:0] q = {WIDTH{1'b0}}
    );





   reg signed [CSB:0]  count = CZERO;
   wire [CBITS:0]      count_next;
   wire                count_wrap;
   wire [CSB:0]        phase;



   reg signed [RSB:0]  phase_jitter;
   reg signed [RSB:0]  phase_offset;
   reg signed [RSB:0]  cycle_jitter;



   reg [RSB:0]         ratio = RZERO;
   reg                 cycle = 1'b0;
   wire [RBITS:0]      rnext;
   wire                rwrap, valid;




   assign count_next = count + 1;
   assign count_wrap = count == CMAX;
   assign phase      = count + phase_offset + phase_jitter;

   assign rnext      = rwrap ? RZERO : ratio + 1;
   assign rwrap      = ratio == RMAX;
   assign valid      = phase >= CHALF && cycle;



   assign stb        = cycle;






   initial begin
      phase_offset = $random;
      phase_offset = phase_offset % (PHASE_OFFSET + 1);
      if (NOISY)
        $display("Phase offset (%m):\t%d", phase_offset);
   end





   always @(posedge clk)
     if (rst || ce && count_wrap) begin
        phase_jitter = $random;
        phase_jitter = phase_jitter % (PHASE_JITTER + 1);
     end



   always @(posedge clk)
     if (rst)
       count <= #DELAY CZERO;
     else if (ce)
       count <= #DELAY count_wrap ? CZERO : count+1 ;
     else
       count <= #DELAY count;



   always @(posedge clk)
     if (rst || !ce)
       q   <= #DELAY 'bz;
     else if (phase == CHALF)
       q   <= #DELAY d;
     else
       q   <= #DELAY q;

   always @(posedge clk)
     if (rst || !ce)
       vld <= #DELAY 1'b0;
     else if (valid)
       vld <= #DELAY 1'b1;
     else
       vld <= #DELAY vld;





   always @(posedge clk)
     if (rst || !ce) begin
        cycle <= #DELAY 1'b0;
        ratio <= #DELAY RZERO;
     end
     else begin
        cycle <= #DELAY rnext == RMAX;
        ratio <= #DELAY rnext;
     end


endmodule
module signal_stagger
  #(
    parameter WIDTH = 1,
    parameter MSB   = WIDTH-1,


    parameter RATIO = 12,
    parameter RBITS = 4,
    parameter RSB   = RBITS-1,
    parameter RZERO = 0,
    parameter RHALF = RATIO>>1,
    parameter RMAX  = RATIO-1,

    parameter CBITS = RBITS+1,
    parameter CSB   = CBITS-1,
    parameter CZERO = 0,
    parameter CHALF = RATIO>>1,
    parameter CMAX  = RATIO-1,


    parameter PHASE_JITTER = 1,
    parameter PHASE_OFFSET = 1,
    parameter CYCLE_JITTER = 1,


    parameter NOISY = 0,
    parameter DELAY = 3)
   (
    input              clk,
    input              rst,
    input              ce,
    input [MSB:0]      d,
    output reg         vld = 1'b0,
    output             stb,
    output reg [MSB:0] q = {WIDTH{1'b0}}
    );






   reg signed [CSB:0]  count = CZERO;
   wire [CBITS:0]      count_next;
   wire                count_wrap;
   wire [CSB:0]        phase;



   reg signed [RSB:0]  phase_jitter;
   reg signed [RSB:0]  phase_offset;
   reg signed [RSB:0]  cycle_jitter;



   reg [RSB:0]         ratio = RZERO;
   reg                 cycle = 1'b0;
   wire [RBITS:0]      rnext;
   wire                rwrap, valid;




   assign count_next = count + 1;
   assign count_wrap = count == CMAX;
   assign phase      = count + phase_offset + phase_jitter;

   assign rnext      = rwrap ? RZERO : ratio + 1;
   assign rwrap      = ratio == RMAX;
   assign valid      = phase >= CHALF && cycle;



   assign stb        = cycle;






   initial begin
      phase_offset = $random;
      phase_offset = phase_offset % (PHASE_OFFSET + 1);
      if (NOISY)
        $display("Phase offset (%m):\t%d", phase_offset);
   end





   always @(posedge clk)
     if (rst || ce && count_wrap) begin
        phase_jitter = $random;
        phase_jitter = phase_jitter % (PHASE_JITTER + 1);
     end



   always @(posedge clk)
     if (rst)
       count <= #DELAY CZERO;
     else if (ce)
       count <= #DELAY count_wrap ? CZERO : count+1 ;
     else
       count <= #DELAY count;



   always @(posedge clk)
     if (rst || !ce)
       q   <= #DELAY 'bz;
     else if (phase == CHALF)
       q   <= #DELAY d;
     else
       q   <= #DELAY q;

   always @(posedge clk)
     if (rst || !ce)
       vld <= #DELAY 1'b0;
     else if (valid)
       vld <= #DELAY 1'b1;
     else
       vld <= #DELAY vld;





   always @(posedge clk)
     if (rst || !ce) begin
        cycle <= #DELAY 1'b0;
        ratio <= #DELAY RZERO;
     end
     else begin
        cycle <= #DELAY rnext == RMAX;
        ratio <= #DELAY rnext;
     end


endmodule