data/full_repos/permissive/208741034/seg_led_dynamic/rtl/count.v
1: b'%Warning-WIDTH: data/full_repos/permissive/208741034/seg_led_dynamic/rtl/count.v:21: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                   : ... In instance count\n    cnt <= 22\'d0;\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module count(    

    input  clk,
    input  rst_n,

    output reg[19 : 0]  data,
    output reg[ 5 : 0]  point,
    output reg          en   ,
    output reg          sign
    
);


parameter MAX_NUM = 23'd5_000_000;
reg [22 : 0]cnt;
reg         flag;

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
    cnt <= 22'd0;
    flag <= 1'b0;
    end
    else begin
        if(cnt < MAX_NUM - 1)begin
        cnt  <= cnt + 1;
        flag <= 1'b0;
        end
        else begin
        cnt <= 23'd0;
        flag <= 1'b1;
        end
    end

    
end


always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
       data <= 20'd0;
       point <= 6'b000_000;
       en    <= 1'b0;
       sign  <= 1'b0;
    end
    else begin
        point <= 6'b000_000;
        sign <=  1'd0;
        en   <=  1'd1;
        if(flag )begin
            if(data <= 20'd999_999)
              data <= data + 1;
            else
              data <= 20'd0;
            
        end

    end
    
end

endmodule
module count(    

    input  clk,
    input  rst_n,

    output reg[19 : 0]  data,
    output reg[ 5 : 0]  point,
    output reg          en   ,
    output reg          sign
    
);



parameter MAX_NUM = 23'd5_000_000;
reg [22 : 0]cnt;
reg         flag;

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
    cnt <= 22'd0;
    flag <= 1'b0;
    end
    else begin
        if(cnt < MAX_NUM - 1)begin
        cnt  <= cnt + 1;
        flag <= 1'b0;
        end
        else begin
        cnt <= 23'd0;
        flag <= 1'b1;
        end
    end

    
end


always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
       data <= 20'd0;
       point <= 6'b000_000;
       en    <= 1'b0;
       sign  <= 1'b0;
    end
    else begin
        point <= 6'b000_000;
        sign <=  1'd0;
        en   <=  1'd1;
        if(flag )begin
            if(data <= 20'd999_999)
              data <= data + 1;
            else
              data <= 20'd0;
            
        end

    end
    
end

endmodule