data/full_repos/permissive/167856740/cpu/mux3.v
data/verilator_xmls/5cd85d85-17ce-47fd-b2f5-19854adec3a1.xml
module mux3(
		input wire [1:0] I_sel,
		input wire [31:0] I_data1,
		input wire [31:0] I_data2,
		input wire [31:0] I_data3,
		output reg [31:0] O_data
	  );

    always @(*) begin
        case(I_sel)
            2'b00: O_data = I_data1;
            2'b01: O_data = I_data2;
            2'b10: O_data = I_data3;
            default: O_data = 32'h00000000;
        endcase
    end

endmodule
module mux3(
		input wire [1:0] I_sel,
		input wire [31:0] I_data1,
		input wire [31:0] I_data2,
		input wire [31:0] I_data3,
		output reg [31:0] O_data
	  );


    always @(*) begin
        case(I_sel)
            2'b00: O_data = I_data1;
            2'b01: O_data = I_data2;
            2'b10: O_data = I_data3;
            default: O_data = 32'h00000000;
        endcase
    end

endmodule