data/full_repos/permissive/143278/ivltests/pr910.v
 line:15: before: ","
1: b'%Error: data/full_repos/permissive/143278/ivltests/pr910.v:15: Unsupported or unknown PLI call: $monitor\n $monitor( X00, X31, VSS, VSS,,, N2166, N1110 ) ;\n ^~~~~~~~\n%Error: data/full_repos/permissive/143278/ivltests/pr910.v:15: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n $monitor( X00, X31, VSS, VSS,,, N2166, N1110 ) ;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr910.v:16: Unsupported: Ignoring delay on this delayed statement.\n #10 state = 1 ;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr910.v:17: Unsupported: Ignoring delay on this delayed statement.\n #10 state = 0 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr910.v:18: Unsupported: Ignoring delay on this delayed statement.\n #10 state = 1 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr910.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10 state = 0 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr910.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish(0);\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MULT32;
    wire VDD = 1 ;
    wire VSS = 0 ;
    wire X00, X31 ;
    reg [1:0] state ;
    assign {X31, X00} = state ;

    ADDERXY XX1 (VSS, N1110, VSS, N2166, X00, X31);

    ADDERXY XX127 (N1076, N1044, N2131, N2100, VSS, VSS);

    initial
	begin
	state = 0 ;
	$monitor( X00, X31, VSS, VSS,,, N2166, N1110 ) ;
	#10 state = 1 ;
	#10 state = 0 ;
	#10 state = 1 ;
	#10 state = 0 ;
	#10 $finish(0);
	end

endmodule
module MULT32;

    wire VDD = 1 ;
    wire VSS = 0 ;
    wire X00, X31 ;
    reg [1:0] state ;
    assign {X31, X00} = state ;

    ADDERXY XX1 (VSS, N1110, VSS, N2166, X00, X31);

    ADDERXY XX127 (N1076, N1044, N2131, N2100, VSS, VSS);

    initial
	begin
	state = 0 ;
	$monitor( X00, X31, VSS, VSS,,, N2166, N1110 ) ;
	#10 state = 1 ;
	#10 state = 0 ;
	#10 state = 1 ;
	#10 state = 0 ;
	#10 $finish(0);
	end

endmodule