data/full_repos/permissive/143278/ivltests/pr2219441.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 2\'b00) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 2\'b10) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 2\'b01) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/pr2219441.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (Z !== 2\'bzz) begin\n    ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module child(input sel, input A, inout Z);
  assign Z = (sel) ? A : 1'bz;
endmodule
module child(input sel, input A, inout Z);

  assign Z = (sel) ? A : 1'bz;
endmodule