data/full_repos/permissive/165901145/seq_detector.srcs/sources_1/new/D-flip-flop.v
data/verilator_xmls/22edc4ed-1923-4c41-b78d-cc94de99c849.xml
module gated_D(
    input D,
    input clk,
    input rest_n,
    input enable,
    output reg Q
    );
    always @(posedge clk,negedge rest_n)
    begin
    if(rest_n == 0) Q <= 0;
    else if(enable) Q <= D ;
    end
endmodule
module gated_D(
    input D,
    input clk,
    input rest_n,
    input enable,
    output reg Q
    );

    always @(posedge clk,negedge rest_n)
    begin
    if(rest_n == 0) Q <= 0;
    else if(enable) Q <= D ;
    end
endmodule