data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v
1: b'%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:2: Cannot find include file: def.v\n`include "def.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.v\n             data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.sv\n             def.v\n             def.v.v\n             def.v.sv\n             obj_dir/def.v\n             obj_dir/def.v.v\n             obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:54: Define or directive not defined: \'`True\'\n  if (rst == `True) begin\n             ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:54: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if (rst == `True) begin\n                  ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:56: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n   lkd0 <= `False;\n           ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   lkd0 <= `False;\n                 ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:59: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n    lkd0 <= `False;\n            ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:63: Define or directive not defined: \'`True\'\n    lkd0 <= `True;\n            ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:64: Define or directive not defined: \'`True\'\n   end else if (wr0Is == `True && rr0 == wr0) begin\n                         ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:65: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n    lkd0 <= `False;\n            ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:67: Define or directive not defined: \'`True\'\n   end else if (wr1Is == `True && rr0 == wr1) begin\n                         ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:68: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n    lkd0 <= `False;\n            ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:71: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n    lkd0 <= `False;\n            ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:79: Define or directive not defined: \'`True\'\n  if (rst == `True) begin\n             ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:81: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n   lkd1 <= `False;\n           ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:84: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n    lkd1 <= `False;\n            ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:87: Define or directive not defined: \'`True\'\n    lkd1 <= `True;\n            ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:88: Define or directive not defined: \'`True\'\n   end else if (wr0Is == `True && rr1 == wr0) begin\n                         ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:89: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n    lkd1 <= `False;\n            ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:91: Define or directive not defined: \'`True\'\n   end else if (wr1Is == `True && rr1 == wr1) begin\n                         ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:92: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n    lkd1 <= `False;\n            ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:95: Define or directive not defined: \'`False\'\n                                                                              : ... Suggested alternative: \'`else\'\n    lkd1 <= `False;\n            ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:102: Define or directive not defined: \'`True\'\n  if ( rst == `True ) begin\n              ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:135: Define or directive not defined: \'`True\'\n  end else if ( we == `True ) begin\n                      ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:142: Define or directive not defined: \'`True\'\n   if (wr1Is == `True && wr1 != 5\'d0)\n                ^~~~~\n%Error: Cannot continue\n'
module RegFile (
	clk, rst, we,
	rr0, rr1, rd0, rd1,


	lk0,


	lkd0, lkd1,

	wr0Is,
	wr0, wd0,
	wr1Is,
	wr1, wd1
	);
	input wire 			clk, rst, we;
	input wire [4  : 0] rr0, rr1;
	output reg [31 : 0] rd0, rd1;

	input wire lk0;
	output reg lkd0, lkd1;

	input wire 			wr0Is, wr1Is;
	input wire [4  : 0] wr0, wr1;
	input wire [31 : 0] wd0, wd1;

	reg [31 : 0] regs [31:0];


	always @(*) begin
		if (rst == `True) begin
			rd0  <= 32'd0;
			lkd0 <= `False;
		end else begin
			if (rr0 == 5'd0) begin
				lkd0 <= `False;
				rd0 <= 32'd0;

			end else if ({lk0, wr0} == {1'b1, rr0}) begin
				lkd0 <= `True;
			end else if (wr0Is == `True && rr0 == wr0) begin
				lkd0 <= `False;
				rd0  <= wd0;
			end else if (wr1Is == `True && rr0 == wr1) begin
				lkd0 <= `False;
				rd0  <= wd1;
			end else begin
				lkd0 <= `False;
				rd0  <= regs[rr0];
			end
		end
	end


	always @(*) begin
		if (rst == `True) begin
			rd1  <= 32'd0;
			lkd1 <= `False;
		end else begin
			if (rr1 == 5'd0) begin
				lkd1 <= `False;
				rd1  <= 32'd0;
			end else if ({lk0, wr0} == {1'b1, rr1}) begin
				lkd1 <= `True;
			end else if (wr0Is == `True && rr1 == wr0) begin
				lkd1 <= `False;
				rd1  <= wd0;
			end else if (wr1Is == `True && rr1 == wr1) begin
				lkd1 <= `False;
				rd1  <= wd1;
			end else begin
				lkd1 <= `False;
				rd1  <= regs[rr1];
			end
		end
	end

	always @(posedge clk) begin
		if ( rst == `True ) begin
			regs[0]  <= 32'b0;
			regs[1]  <= 32'b0;
			regs[2]  <= 32'b0;
			regs[3]  <= 32'b0;
			regs[4]  <= 32'b0;
			regs[5]  <= 32'b0;
			regs[6]  <= 32'b0;
			regs[7]  <= 32'b0;
			regs[8]  <= 32'b0;
			regs[9]  <= 32'b0;
			regs[10] <= 32'b0;
			regs[11] <= 32'b0;
			regs[12] <= 32'b0;
			regs[13] <= 32'b0;
			regs[14] <= 32'b0;
			regs[15] <= 32'b0;
			regs[16] <= 32'b0;
			regs[17] <= 32'b0;
			regs[18] <= 32'b0;
			regs[19] <= 32'b0;
			regs[20] <= 32'b0;
			regs[21] <= 32'b0;
			regs[22] <= 32'b0;
			regs[23] <= 32'b0;
			regs[24] <= 32'b0;
			regs[25] <= 32'b0;
			regs[26] <= 32'b0;
			regs[27] <= 32'b0;
			regs[28] <= 32'b0;
			regs[29] <= 32'b0;
			regs[30] <= 32'b0;
			regs[31] <= 32'b0;
		end else if ( we == `True ) begin

			if (wr1Is == `True && wr1 != 5'd0)
				regs[wr1] <= wd1;
		end
	end
endmodule
module RegFile (
	clk, rst, we,
	rr0, rr1, rd0, rd1,


	lk0,


	lkd0, lkd1,

	wr0Is,
	wr0, wd0,
	wr1Is,
	wr1, wd1
	);

	input wire 			clk, rst, we;
	input wire [4  : 0] rr0, rr1;
	output reg [31 : 0] rd0, rd1;

	input wire lk0;
	output reg lkd0, lkd1;

	input wire 			wr0Is, wr1Is;
	input wire [4  : 0] wr0, wr1;
	input wire [31 : 0] wd0, wd1;

	reg [31 : 0] regs [31:0];


	always @(*) begin
		if (rst == `True) begin
			rd0  <= 32'd0;
			lkd0 <= `False;
		end else begin
			if (rr0 == 5'd0) begin
				lkd0 <= `False;
				rd0 <= 32'd0;

			end else if ({lk0, wr0} == {1'b1, rr0}) begin
				lkd0 <= `True;
			end else if (wr0Is == `True && rr0 == wr0) begin
				lkd0 <= `False;
				rd0  <= wd0;
			end else if (wr1Is == `True && rr0 == wr1) begin
				lkd0 <= `False;
				rd0  <= wd1;
			end else begin
				lkd0 <= `False;
				rd0  <= regs[rr0];
			end
		end
	end


	always @(*) begin
		if (rst == `True) begin
			rd1  <= 32'd0;
			lkd1 <= `False;
		end else begin
			if (rr1 == 5'd0) begin
				lkd1 <= `False;
				rd1  <= 32'd0;
			end else if ({lk0, wr0} == {1'b1, rr1}) begin
				lkd1 <= `True;
			end else if (wr0Is == `True && rr1 == wr0) begin
				lkd1 <= `False;
				rd1  <= wd0;
			end else if (wr1Is == `True && rr1 == wr1) begin
				lkd1 <= `False;
				rd1  <= wd1;
			end else begin
				lkd1 <= `False;
				rd1  <= regs[rr1];
			end
		end
	end

	always @(posedge clk) begin
		if ( rst == `True ) begin
			regs[0]  <= 32'b0;
			regs[1]  <= 32'b0;
			regs[2]  <= 32'b0;
			regs[3]  <= 32'b0;
			regs[4]  <= 32'b0;
			regs[5]  <= 32'b0;
			regs[6]  <= 32'b0;
			regs[7]  <= 32'b0;
			regs[8]  <= 32'b0;
			regs[9]  <= 32'b0;
			regs[10] <= 32'b0;
			regs[11] <= 32'b0;
			regs[12] <= 32'b0;
			regs[13] <= 32'b0;
			regs[14] <= 32'b0;
			regs[15] <= 32'b0;
			regs[16] <= 32'b0;
			regs[17] <= 32'b0;
			regs[18] <= 32'b0;
			regs[19] <= 32'b0;
			regs[20] <= 32'b0;
			regs[21] <= 32'b0;
			regs[22] <= 32'b0;
			regs[23] <= 32'b0;
			regs[24] <= 32'b0;
			regs[25] <= 32'b0;
			regs[26] <= 32'b0;
			regs[27] <= 32'b0;
			regs[28] <= 32'b0;
			regs[29] <= 32'b0;
			regs[30] <= 32'b0;
			regs[31] <= 32'b0;
		end else if ( we == `True ) begin

			if (wr1Is == `True && wr1 != 5'd0)
				regs[wr1] <= wd1;
		end
	end
endmodule