data/full_repos/permissive/167274925/Mux3to1.v
data/verilator_xmls/3ef40cb5-1d32-4c32-b50b-86b8663b924c.xml
module Mux3to1(sel,A,B,C,out);
input [31:0]A,B,C;
input [1:0]sel;
output reg [31:0]out;
        always@(*)begin 
        case(sel)
        2'd0: out<=A;
        2'd1: out<=B;
        2'd2: out<=C;
        endcase 
        end 
endmodule
module Mux3to1(sel,A,B,C,out);

input [31:0]A,B,C;
input [1:0]sel;
output reg [31:0]out;
        always@(*)begin 
        case(sel)
        2'd0: out<=A;
        2'd1: out<=B;
        2'd2: out<=C;
        endcase 
        end 
endmodule