data/full_repos/permissive/104269513/ALU_final_smaller.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:416: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:422: Unsupported: Ignoring delay on this delayed statement.\n#99\n^\n%Error: data/full_repos/permissive/104269513/ALU_final_smaller.v:424: Too many digits for 32 bit number: \'hFFFF_FFFF_FFFF_FFFF\nA=\'hFFFF_FFFF_FFFF_FFFF;\n  ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:428: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:431: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:434: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:437: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:440: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:443: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/104269513/ALU_final_smaller.v:446: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_ctrl_tb();

reg [63:0] A;
reg [63:0] B;
reg [3:0] cmd;
reg clk;
reg rst;
wire [31:0] psw;
wire [63:0] Data_out;

ALU_ctrl ALU_ctrl(.A(A), .B(B), .cmd(cmd), .psw(psw), .Data_out(Data_out));	

initial 
begin
clk=0;
rst=1;

forever #10 clk=~clk;
			
end

initial
begin
#99
rst=0;
A='hFFFF_FFFF_FFFF_FFFF;
B='h0000_0000_0000_0030;
cmd=0;

#20
cmd=1;

#20
cmd=2;

#20
cmd=3;

#20
cmd=4;

#20
cmd=6;

#20
cmd=7;

#20
cmd=8;

end

endmodule
module ALU_ctrl_tb();


reg [63:0] A;
reg [63:0] B;
reg [3:0] cmd;
reg clk;
reg rst;
wire [31:0] psw;
wire [63:0] Data_out;

ALU_ctrl ALU_ctrl(.A(A), .B(B), .cmd(cmd), .psw(psw), .Data_out(Data_out));	

initial 
begin
clk=0;
rst=1;

forever #10 clk=~clk;
			
end

initial
begin
#99
rst=0;
A='hFFFF_FFFF_FFFF_FFFF;
B='h0000_0000_0000_0030;
cmd=0;

#20
cmd=1;

#20
cmd=2;

#20
cmd=3;

#20
cmd=4;

#20
cmd=6;

#20
cmd=7;

#20
cmd=8;

end

endmodule