data/full_repos/permissive/174643991/DCPU/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/ALU.v:54: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'ICF\' generates 1 bits.\n                                                                  : ... In instance ALU\n                {OCF,ROUT}  = IN1+IN2+ICF;\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/ALU.v:65: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'ICF\' generates 1 bits.\n                                                                  : ... In instance ALU\n                ROUT        = IN1-IN2-ICF;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/ALU.v:92: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'IN1\' generates 16 bits.\n                                                                  : ... In instance ALU\n                {OCF,ROUT}  = IN1 << IN2[3:0]; \n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/ALU.v:95: Operator SHIFTL expects 17 bits on the LHS, but LHS\'s VARREF \'IN1\' generates 16 bits.\n                                                                  : ... In instance ALU\n                {OCF,ROUT}  = IN1 <<< IN2[3:0];\n                                  ^~~\n%Warning-WIDTH: data/full_repos/permissive/174643991/DCPU/ALU.v:103: Operator ASSIGN expects 17 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 33 bits.\n                                                                   : ... In instance ALU\n                if(IN1[15]) {ROUT,OCF}  = {ShiftMark,IN1,OCF} >>> IN2[3:0];\n                                        ^\n%Error: Exiting due to 5 warning(s)\n'
module ALU(
  input  wire[3:0]  OPC,
  input  wire[15:0] IN1,
  input  wire[15:0] IN2,
  input  wire       ICF,
  output wire[15:0] OUT,
  output reg        OCF,
  output wire       OZF,
  output wire       ONF
);
  
  reg [15:0] ROUT;
  wire[15:0] ShiftMark; assign ShiftMark = 16'hFFFF;
  
  

  assign OZF = (ROUT == 16'b0);
  

  assign ONF = (OPC[3]) ? (1'b0) : (ROUT[15]);
  

  assign OUT = (OPC==4'b0000) ? (16'b0) : (ROUT);
  always @(*) case(OPC)
      4'b0000:begin
                ROUT        = IN1-IN2;
                OCF         = 0;
              end
      4'b0001:begin
                ROUT        = 0;
                OCF         = 0;
              end
      4'b0010:begin
                {OCF,ROUT}  = IN1+IN2+ICF;
              end
      4'b0011:begin
                ROUT        = 0;
                OCF         = 0;
              end
      4'b0100:begin
                ROUT        = 0;
                OCF         = 0;
               end
      4'b0101:begin
                ROUT        = IN1-IN2-ICF;
                OCF         = 0;
              end
      4'b0110:begin
                {OCF,ROUT}  = IN1+1;
              end
      4'b0111:begin
                ROUT        = IN2;
                OCF         = 0;
              end
      4'b1000:begin
                ROUT        = 0;
                OCF         = 0;
              end
      4'b1001:begin
                ROUT        = IN1^IN2;
                OCF         = 0;
              end
      4'b1010:begin
                ROUT        = IN1&IN2;
                OCF         = 0;
              end
      4'b1011:begin
                ROUT        = IN1|IN2;
                OCF         = 0;
              end
      4'b1100:begin
                {OCF,ROUT}  = IN1 << IN2[3:0]; 
              end
      4'b1101:begin
                {OCF,ROUT}  = IN1 <<< IN2[3:0];
              end
      4'b1110:begin
                OCF         = 0;
                {ROUT,OCF}  = {IN1,OCF} >> IN2[3:0];
              end
      4'b1111:begin
                OCF         = 0;
                if(IN1[15]) {ROUT,OCF}  = {ShiftMark,IN1,OCF} >>> IN2[3:0];
                else        {ROUT,OCF}  = {IN1,OCF} >>> IN2[3:0];
              end
  endcase
  
endmodule
module ALU(
  input  wire[3:0]  OPC,
  input  wire[15:0] IN1,
  input  wire[15:0] IN2,
  input  wire       ICF,
  output wire[15:0] OUT,
  output reg        OCF,
  output wire       OZF,
  output wire       ONF
);

  
  reg [15:0] ROUT;
  wire[15:0] ShiftMark; assign ShiftMark = 16'hFFFF;
  
  

  assign OZF = (ROUT == 16'b0);
  

  assign ONF = (OPC[3]) ? (1'b0) : (ROUT[15]);
  

  assign OUT = (OPC==4'b0000) ? (16'b0) : (ROUT);
  always @(*) case(OPC)
      4'b0000:begin
                ROUT        = IN1-IN2;
                OCF         = 0;
              end
      4'b0001:begin
                ROUT        = 0;
                OCF         = 0;
              end
      4'b0010:begin
                {OCF,ROUT}  = IN1+IN2+ICF;
              end
      4'b0011:begin
                ROUT        = 0;
                OCF         = 0;
              end
      4'b0100:begin
                ROUT        = 0;
                OCF         = 0;
               end
      4'b0101:begin
                ROUT        = IN1-IN2-ICF;
                OCF         = 0;
              end
      4'b0110:begin
                {OCF,ROUT}  = IN1+1;
              end
      4'b0111:begin
                ROUT        = IN2;
                OCF         = 0;
              end
      4'b1000:begin
                ROUT        = 0;
                OCF         = 0;
              end
      4'b1001:begin
                ROUT        = IN1^IN2;
                OCF         = 0;
              end
      4'b1010:begin
                ROUT        = IN1&IN2;
                OCF         = 0;
              end
      4'b1011:begin
                ROUT        = IN1|IN2;
                OCF         = 0;
              end
      4'b1100:begin
                {OCF,ROUT}  = IN1 << IN2[3:0]; 
              end
      4'b1101:begin
                {OCF,ROUT}  = IN1 <<< IN2[3:0];
              end
      4'b1110:begin
                OCF         = 0;
                {ROUT,OCF}  = {IN1,OCF} >> IN2[3:0];
              end
      4'b1111:begin
                OCF         = 0;
                if(IN1[15]) {ROUT,OCF}  = {ShiftMark,IN1,OCF} >>> IN2[3:0];
                else        {ROUT,OCF}  = {IN1,OCF} >>> IN2[3:0];
              end
  endcase
  
endmodule