data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v
None: at end of input
1: b'%Error: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:48: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("buttons-tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:49: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, buttons_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #10 CLK = ~CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #15\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/174155074/fpga-development-boards/buttons/buttons/buttons-tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Error: Exiting due to 2 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module buttons_tb;


reg        CLK;
reg        PRESSED;
wire       BUTTON_SYNC_PUSH_RELEASE;
wire       BUTTON_SYNC_CLOCK_PULSE_OUT;
wire       BUTTON_ASYNC_CLOCK_PULSE_OUT;
wire       BUTTON_SYNC_TWO_PRESSES_OUT;
wire       BUTTON_ASYNC_TWO_PRESSES_OUT;

button_sync_push_release SYNC_PUSH_RELEASE (
    .clk(CLK),
    .pressed(PRESSED),
    .out(BUTTON_SYNC_PUSH_RELEASE)
);

button_sync_clock_pulse SYNC_CLOCK_PULSE (
    .clk(CLK),
    .pressed(PRESSED),
    .out(BUTTON_SYNC_CLOCK_PULSE_OUT)
);

button_async_clock_pulse ASYNC_CLOCK_PULSE (
    .clk(CLK),
    .pressed(PRESSED),
    .out(BUTTON_ASYNC_CLOCK_PULSE_OUT)
);

button_sync_two_presses SYNC_TWO_PRESSES (
    .clk(CLK),
    .pressed(PRESSED),
    .out(BUTTON_SYNC_TWO_PRESSES_OUT)
);

button_async_two_presses ASYNC_TWO_PRESSES (
    .clk(CLK),
    .pressed(PRESSED),
    .out(BUTTON_ASYNC_TWO_PRESSES_OUT)
);


initial begin
    $dumpfile("buttons-tb.vcd");
    $dumpvars(0, buttons_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    PRESSED = 0;
    #100


    PRESSED = 1;
    #20
    PRESSED = 0;
    #100


    PRESSED = 1;
    #20
    PRESSED = 0;
    #100


    PRESSED = 1;
    #100
    PRESSED = 0;
    #100


    PRESSED = 1;
    #100
    PRESSED = 0;
    #100
    

    PRESSED = 1;
    #5
    PRESSED = 0;
    #15
    #100


    PRESSED = 1;
    #100
    PRESSED = 0;
    #100

    $display("test complete");
    $finish;
end

endmodule
module buttons_tb;



reg        CLK;
reg        PRESSED;
wire       BUTTON_SYNC_PUSH_RELEASE;
wire       BUTTON_SYNC_CLOCK_PULSE_OUT;
wire       BUTTON_ASYNC_CLOCK_PULSE_OUT;
wire       BUTTON_SYNC_TWO_PRESSES_OUT;
wire       BUTTON_ASYNC_TWO_PRESSES_OUT;

button_sync_push_release SYNC_PUSH_RELEASE (
    .clk(CLK),
    .pressed(PRESSED),
    .out(BUTTON_SYNC_PUSH_RELEASE)
);

button_sync_clock_pulse SYNC_CLOCK_PULSE (
    .clk(CLK),
    .pressed(PRESSED),
    .out(BUTTON_SYNC_CLOCK_PULSE_OUT)
);

button_async_clock_pulse ASYNC_CLOCK_PULSE (
    .clk(CLK),
    .pressed(PRESSED),
    .out(BUTTON_ASYNC_CLOCK_PULSE_OUT)
);

button_sync_two_presses SYNC_TWO_PRESSES (
    .clk(CLK),
    .pressed(PRESSED),
    .out(BUTTON_SYNC_TWO_PRESSES_OUT)
);

button_async_two_presses ASYNC_TWO_PRESSES (
    .clk(CLK),
    .pressed(PRESSED),
    .out(BUTTON_ASYNC_TWO_PRESSES_OUT)
);


initial begin
    $dumpfile("buttons-tb.vcd");
    $dumpvars(0, buttons_tb);
end


always begin
    #10 CLK = ~CLK;
end


initial begin
    $display("test start");
    CLK = 0;
    PRESSED = 0;
    #100


    PRESSED = 1;
    #20
    PRESSED = 0;
    #100


    PRESSED = 1;
    #20
    PRESSED = 0;
    #100


    PRESSED = 1;
    #100
    PRESSED = 0;
    #100


    PRESSED = 1;
    #100
    PRESSED = 0;
    #100
    

    PRESSED = 1;
    #5
    PRESSED = 0;
    #15
    #100


    PRESSED = 1;
    #100
    PRESSED = 0;
    #100

    $display("test complete");
    $finish;
end

endmodule