data/full_repos/permissive/173691730/ccmb28_FPGA/sources_1/select_frequence.v
 line:41: before: "ync"
data/verilator_xmls/fd011735-d723-4ac4-91f5-d529c519c3fb.xml
module select_frequence(sw,frequence);
input sw;
output reg [1:0]frequence;

initial begin
   frequence = 0;
end

always@(posedge sw)
begin
    case(frequence)
        2'b00:frequence=2'b01;
        2'b01:frequence=2'b10;
        2'b10:frequence=2'b11;
        2'b11:frequence=2'b00;
    endcase
end
endmodule
module select_frequence(sw,frequence);

input sw;
output reg [1:0]frequence;

initial begin
   frequence = 0;
end

always@(posedge sw)
begin
    case(frequence)
        2'b00:frequence=2'b01;
        2'b01:frequence=2'b10;
        2'b10:frequence=2'b11;
        2'b11:frequence=2'b00;
    endcase
end
endmodule