data/full_repos/permissive/156609923/RoundRobin/probador.v
 line:34: before: "@"
1: b'%Warning-STMTDLY: data/full_repos/permissive/156609923/RoundRobin/probador.v:19: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/156609923/RoundRobin/probador.v:23: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("round_robin.vcd");  \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/156609923/RoundRobin/probador.v:24: Unsupported or unknown PLI call: $dumpvars\n       $dumpvars(0,testbench);   \n       ^~~~~~~~~\n%Error: data/full_repos/permissive/156609923/RoundRobin/probador.v:31: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/156609923/RoundRobin/probador.v:34: syntax error, unexpected \'@\'\n    #20 @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/RoundRobin/probador.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #20 @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/156609923/RoundRobin/probador.v:38: syntax error, unexpected \'@\'\n   #20 @(posedge clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/RoundRobin/probador.v:38: Unsupported: Ignoring delay on this delayed statement.\n   #20 @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/RoundRobin/probador.v:42: syntax error, unexpected \'@\'\n   #20 @(posedge clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/RoundRobin/probador.v:42: Unsupported: Ignoring delay on this delayed statement.\n   #20 @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/156609923/RoundRobin/probador.v:46: syntax error, unexpected \'@\'\n   #20 @(posedge clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/RoundRobin/probador.v:46: Unsupported: Ignoring delay on this delayed statement.\n   #20 @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/156609923/RoundRobin/probador.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #20 $finish;\n    ^\n%Error: Exiting due to 7 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador (	input portMux_condu,
									input validMux_condu,
									input pop0_condu,
									input pop1_condu,
									input portMux_estru,
									input validMux_estru,
									input pop0_estru,
									input pop1_estru,
									output reg clk,
									output reg reset_L,
									output reg request0,
									output reg request1);




	initial clk <= 0;
	always #1 clk = ~clk;

	initial
	begin
		$dumpfile("round_robin.vcd");
     		$dumpvars(0,testbench);


	   reset_L <= 0;
		 request0 <= 0;
		 request1 <= 0;

	   @(posedge clk);
	   reset_L <= 1;

	   #20 @(posedge clk);
		 request0 <= 0;
		 request1 <= 1;

		 #20 @(posedge clk);
		 request0 <= 1;
		 request1 <= 1;

		 #20 @(posedge clk);
		 request0 <= 1;
		 request1 <= 0;

		 #20 @(posedge clk);
		 reset_L <= 0;

	   #20 $finish;

	end

endmodule
module probador (	input portMux_condu,
									input validMux_condu,
									input pop0_condu,
									input pop1_condu,
									input portMux_estru,
									input validMux_estru,
									input pop0_estru,
									input pop1_estru,
									output reg clk,
									output reg reset_L,
									output reg request0,
									output reg request1);





	initial clk <= 0;
	always #1 clk = ~clk;

	initial
	begin
		$dumpfile("round_robin.vcd");
     		$dumpvars(0,testbench);


	   reset_L <= 0;
		 request0 <= 0;
		 request1 <= 0;

	   @(posedge clk);
	   reset_L <= 1;

	   #20 @(posedge clk);
		 request0 <= 0;
		 request1 <= 1;

		 #20 @(posedge clk);
		 request0 <= 1;
		 request1 <= 1;

		 #20 @(posedge clk);
		 request0 <= 1;
		 request1 <= 0;

		 #20 @(posedge clk);
		 reset_L <= 0;

	   #20 $finish;

	end

endmodule