data/full_repos/permissive/159555381/parity.v
 line:28: before: "begin"
1: b'%Error: data/full_repos/permissive/159555381/parity.v:41: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("parity.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/159555381/parity.v:42: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, wb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/159555381/parity.v:45: Unsupported: Ignoring delay on this delayed statement.\n always  #5 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/159555381/parity.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #2 x = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/parity.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/parity.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 1; #10 x = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/parity.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 1; #10 x = 1;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/parity.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/parity.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/159555381/parity.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: data/full_repos/permissive/159555381/parity.v:55: Unsupported or unknown PLI call: $monitor\n  $monitor($time,,,"input : %b, output: %b, state: %b, clk : %b\\n", x, z, ev, clk);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/159555381/parity.v:55: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  $monitor($time,,,"input : %b, output: %b, state: %b, clk : %b\\n", x, z, ev, clk);\n                 ^\n%Error: Exiting due to 4 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module parity (x, clk, z, ev);
	input x, clk;
	output reg z, ev;
	parameter EVEN = 0, ODD = 1;
	reg even_odd;
	always @(posedge clk) 
		case(even_odd)
			EVEN:
				begin
					z <= x ? 1 : 0;
					even_odd <= x ? ODD : EVEN;
					ev = even_odd;
				end
			ODD:
				begin
					z <= x ? 0 : 1;
					even_odd <= x ? EVEN : ODD;
					ev = even_odd;
				end
			default 
				begin
				even_odd = EVEN;
				ev = even_odd;
			end
		endcase
endmodule
module parity (x, clk, z, ev);

	input x, clk;
	output reg z, ev;
	parameter EVEN = 0, ODD = 1;
	reg even_odd;
	always @(posedge clk) 
		case(even_odd)
			EVEN:
				begin
					z <= x ? 1 : 0;
					even_odd <= x ? ODD : EVEN;
					ev = even_odd;
				end
			ODD:
				begin
					z <= x ? 0 : 1;
					even_odd <= x ? EVEN : ODD;
					ev = even_odd;
				end
			default 
				begin
				even_odd = EVEN;
				ev = even_odd;
			end
		endcase
endmodule