data/full_repos/permissive/13201424/vlog/tmds_encode.v
 line:103: before: "for"
1: b'%Warning-IMPLICIT: data/full_repos/permissive/13201424/vlog/tmds_encode.v:119: Signal definition not found, creating implicitly: \'inversion_needed\'\n assign inversion_needed = (need_more_ones && data_has_more_zeroes) | \n        ^~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/13201424/vlog/tmds_encode.v:124: Signal definition not found, creating implicitly: \'invert_data\'\n assign invert_data = (disparity_zero | data_balanced) ? \n        ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:138: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n   s1_n1 <= d[7] + d[6] + d[5] + d[4] + d[3] + d[2] + d[1] + d[0];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:138: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n   s1_n1 <= d[7] + d[6] + d[5] + d[4] + d[3] + d[2] + d[1] + d[0];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:138: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n   s1_n1 <= d[7] + d[6] + d[5] + d[4] + d[3] + d[2] + d[1] + d[0];\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:138: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n   s1_n1 <= d[7] + d[6] + d[5] + d[4] + d[3] + d[2] + d[1] + d[0];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:138: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n   s1_n1 <= d[7] + d[6] + d[5] + d[4] + d[3] + d[2] + d[1] + d[0];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:138: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n   s1_n1 <= d[7] + d[6] + d[5] + d[4] + d[3] + d[2] + d[1] + d[0];\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:138: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n   s1_n1 <= d[7] + d[6] + d[5] + d[4] + d[3] + d[2] + d[1] + d[0];\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:138: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n   s1_n1 <= d[7] + d[6] + d[5] + d[4] + d[3] + d[2] + d[1] + d[0];\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:146: Operator ADD expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n    s1_q[7] + s1_q[6] + s1_q[5] + s1_q[4] + \n            ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:146: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n    s1_q[7] + s1_q[6] + s1_q[5] + s1_q[4] + \n            ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:146: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n    s1_q[7] + s1_q[6] + s1_q[5] + s1_q[4] + \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:146: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n    s1_q[7] + s1_q[6] + s1_q[5] + s1_q[4] + \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:146: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n    s1_q[7] + s1_q[6] + s1_q[5] + s1_q[4] + \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:147: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n    s1_q[3] + s1_q[2] + s1_q[1] + s1_q[0];\n            ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:147: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n    s1_q[3] + s1_q[2] + s1_q[1] + s1_q[0];\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:147: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encode\n    s1_q[3] + s1_q[2] + s1_q[1] + s1_q[0];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:169: Operator SUB expects 5 bits on the LHS, but LHS\'s REPLICATE generates 2 bits.\n                                                                          : ... In instance tmds_encode\n    s2_flag_bits_disparity = {invert_data && s2_q[8], 1\'b0} - {~(invert_data || s2_q[8]), 1\'b0};\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/13201424/vlog/tmds_encode.v:169: Operator SUB expects 5 bits on the RHS, but RHS\'s REPLICATE generates 2 bits.\n                                                                          : ... In instance tmds_encode\n    s2_flag_bits_disparity = {invert_data && s2_q[8], 1\'b0} - {~(invert_data || s2_q[8]), 1\'b0};\n                                                            ^\n%Error: Exiting due to 20 warning(s)\n'
module tmds_encode (
	input clk,
	input rst,
	input [7:0] d,
	input de,
	input c0,
	input c1,
	output reg [9:0] q_out

	);
	




	reg [7:0] s1_d;
	reg s1_de, s1_c0, s1_c1;
	

	reg s2_de, s2_c0, s2_c1;
	reg [8:0] s2_q;
	

	wire [8:0] s1_q;
	

	reg [3:0] s1_n1;
	

	reg [3:0] s2_n1;
	



	reg signed [4:0] s2_cnt;
	reg signed [4:0] s2_flag_bits_disparity, s2_q_disparity;








	wire use_xnor = (s1_n1 > 4'h4) || ((s1_n1 == 4'h4) && (s1_d[0] == 1'b0));
	assign s1_q[0] = s1_d[0];
	
	genvar i;
	for (i = 1; i < 8; i = i + 1) begin : xnor_loop
		assign s1_q[i] = (use_xnor) ? (~(s1_q[i - 1] ^ s1_d[i])) : (s1_q[i - 1] ^ s1_d[i]);
	end
	assign s1_q[8] = ~use_xnor;



	wire data_balanced = (s2_n1 == 4);
	wire data_has_more_zeroes = (s2_n1 < 4);
	wire data_has_more_ones = (s2_n1 > 4);
	wire disparity_zero = (s2_cnt == 0);
	wire need_more_ones = s2_cnt[4];
	



	assign inversion_needed = (need_more_ones && data_has_more_zeroes) | 
		((~need_more_ones) && data_has_more_ones);



	assign invert_data = (disparity_zero | data_balanced) ? 
		(~s2_q[8]) : (inversion_needed);
	

	wire signed [4:0] s2_data_disparity = {s2_n1, 1'b0} - 8;
	


	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			s2_cnt <= 0;
		end else begin


			s1_n1 <= d[7] + d[6] + d[5] + d[4] + d[3] + d[2] + d[1] + d[0];
			s1_d <= d;
			s1_de <= de;
			s1_c0 <= c0;
			s1_c1 <= c1;
			

			s2_n1 <= 
				s1_q[7] + s1_q[6] + s1_q[5] + s1_q[4] + 
				s1_q[3] + s1_q[2] + s1_q[1] + s1_q[0];
			s2_de <= s1_de;
			s2_c0 <= s1_c0;
			s2_c1 <= s1_c1;
			s2_q <= s1_q;
			
			if (s2_de == 1'b0) begin



				case ({s2_c1, s2_c0})
					2'b00   : q_out <= 10'b1101010100;
					2'b01   : q_out <= 10'b0010101011;
					2'b10   : q_out <= 10'b0101010100;
					default : q_out <= 10'b1010101011;
				endcase
				s2_cnt <= 0;

			end else begin
				q_out[9] <= invert_data;
				q_out[8] <= s2_q[8];
				q_out[7:0] <= (invert_data) ? (~s2_q[7:0]) : (s2_q[7:0]);
				s2_flag_bits_disparity = {invert_data && s2_q[8], 1'b0} - {~(invert_data || s2_q[8]), 1'b0};
				s2_q_disparity = (invert_data) ? (s2_flag_bits_disparity - s2_data_disparity) : (s2_flag_bits_disparity + s2_data_disparity);

				s2_cnt <= s2_cnt + s2_q_disparity;
			end
		end
	end
endmodule
module tmds_encode (
	input clk,
	input rst,
	input [7:0] d,
	input de,
	input c0,
	input c1,
	output reg [9:0] q_out

	);

	




	reg [7:0] s1_d;
	reg s1_de, s1_c0, s1_c1;
	

	reg s2_de, s2_c0, s2_c1;
	reg [8:0] s2_q;
	

	wire [8:0] s1_q;
	

	reg [3:0] s1_n1;
	

	reg [3:0] s2_n1;
	



	reg signed [4:0] s2_cnt;
	reg signed [4:0] s2_flag_bits_disparity, s2_q_disparity;








	wire use_xnor = (s1_n1 > 4'h4) || ((s1_n1 == 4'h4) && (s1_d[0] == 1'b0));
	assign s1_q[0] = s1_d[0];
	
	genvar i;
	for (i = 1; i < 8; i = i + 1) begin : xnor_loop
		assign s1_q[i] = (use_xnor) ? (~(s1_q[i - 1] ^ s1_d[i])) : (s1_q[i - 1] ^ s1_d[i]);
	end
	assign s1_q[8] = ~use_xnor;



	wire data_balanced = (s2_n1 == 4);
	wire data_has_more_zeroes = (s2_n1 < 4);
	wire data_has_more_ones = (s2_n1 > 4);
	wire disparity_zero = (s2_cnt == 0);
	wire need_more_ones = s2_cnt[4];
	



	assign inversion_needed = (need_more_ones && data_has_more_zeroes) | 
		((~need_more_ones) && data_has_more_ones);



	assign invert_data = (disparity_zero | data_balanced) ? 
		(~s2_q[8]) : (inversion_needed);
	

	wire signed [4:0] s2_data_disparity = {s2_n1, 1'b0} - 8;
	


	always @ (posedge clk or posedge rst) begin
		if (rst) begin
			s2_cnt <= 0;
		end else begin


			s1_n1 <= d[7] + d[6] + d[5] + d[4] + d[3] + d[2] + d[1] + d[0];
			s1_d <= d;
			s1_de <= de;
			s1_c0 <= c0;
			s1_c1 <= c1;
			

			s2_n1 <= 
				s1_q[7] + s1_q[6] + s1_q[5] + s1_q[4] + 
				s1_q[3] + s1_q[2] + s1_q[1] + s1_q[0];
			s2_de <= s1_de;
			s2_c0 <= s1_c0;
			s2_c1 <= s1_c1;
			s2_q <= s1_q;
			
			if (s2_de == 1'b0) begin



				case ({s2_c1, s2_c0})
					2'b00   : q_out <= 10'b1101010100;
					2'b01   : q_out <= 10'b0010101011;
					2'b10   : q_out <= 10'b0101010100;
					default : q_out <= 10'b1010101011;
				endcase
				s2_cnt <= 0;

			end else begin
				q_out[9] <= invert_data;
				q_out[8] <= s2_q[8];
				q_out[7:0] <= (invert_data) ? (~s2_q[7:0]) : (s2_q[7:0]);
				s2_flag_bits_disparity = {invert_data && s2_q[8], 1'b0} - {~(invert_data || s2_q[8]), 1'b0};
				s2_q_disparity = (invert_data) ? (s2_flag_bits_disparity - s2_data_disparity) : (s2_flag_bits_disparity + s2_data_disparity);

				s2_cnt <= s2_cnt + s2_q_disparity;
			end
		end
	end
endmodule