data/full_repos/permissive/143278/ivltests/memassign.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memassign.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memassign.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memassign.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #100  ;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memassign.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memassign.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #100 ;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memassign.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memassign.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memassign.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memassign.v:88: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memassign.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/143278/ivltests/memassign.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: Exiting due to 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module  demo_assign_problem;

reg     [7:0] mem_buffer [0:3];
wire    [31:0] big_word;
reg     error;
reg     [31:0] myconst;

integer i;

assign big_word[ 31: 24] = mem_buffer[0];
assign big_word[ 23: 16] = mem_buffer[1];
assign big_word[ 15:  8] = mem_buffer[2];
assign big_word[  7:  0] = mem_buffer[3];

initial
  begin
  error = 0;

  for (i = 0; i < 4; i = i+1)
    mem_buffer[i] = 0;
  #50;
  mem_buffer[0] = 8'h12;
  #50;
  myconst = 32'h12_00_00_00;
  if(big_word !== 32'h12_00_00_00)
    begin
      $display("FAILED -Memory assign - expect %h, but have %h",
                myconst,big_word);
      error = 1;
    end
  #100  ;
  mem_buffer[1] = 8'h34;
  #50;
  myconst = 32'h12_34_00_00;
  if(big_word !== 32'h12_34_00_00)
    begin
      $display("FAILED -Memory assign - expect %h, but have %h",
                 myconst,big_word);
      error = 1;
    end
  #100 ;
  mem_buffer[2] = 8'h56;
  #50;
  myconst = 32'h12_34_56_00;
  if(big_word !== 32'h12_34_56_00)
    begin
      $display("FAILED -Memory assign - expect %h, but have %h",
                 myconst,big_word);
      error = 1;
    end
  #100;
  mem_buffer[3] = 8'h78;
  #50;
  myconst = 32'h12_34_56_00;
  if(big_word !== 32'h12_34_56_78)
    begin
      $display("FAILED - Memory assign - expect %h, but have %h",
               myconst,big_word);
      error = 1;
    end
  #100;
  mem_buffer[0] = 8'hab;
  #50;
  myconst = 32'hab_34_56_00;
  if(big_word !== 32'hab_34_56_78)
    begin
      $display("FAILED - Memory assign - expect %h, but have %h",
                myconst,big_word);
      error = 1;
    end

  #100;
  if (error ===0)
     $display("PASSED");


end
endmodule
module  demo_assign_problem;


reg     [7:0] mem_buffer [0:3];
wire    [31:0] big_word;
reg     error;
reg     [31:0] myconst;

integer i;

assign big_word[ 31: 24] = mem_buffer[0];
assign big_word[ 23: 16] = mem_buffer[1];
assign big_word[ 15:  8] = mem_buffer[2];
assign big_word[  7:  0] = mem_buffer[3];

initial
  begin
  error = 0;

  for (i = 0; i < 4; i = i+1)
    mem_buffer[i] = 0;
  #50;
  mem_buffer[0] = 8'h12;
  #50;
  myconst = 32'h12_00_00_00;
  if(big_word !== 32'h12_00_00_00)
    begin
      $display("FAILED -Memory assign - expect %h, but have %h",
                myconst,big_word);
      error = 1;
    end
  #100  ;
  mem_buffer[1] = 8'h34;
  #50;
  myconst = 32'h12_34_00_00;
  if(big_word !== 32'h12_34_00_00)
    begin
      $display("FAILED -Memory assign - expect %h, but have %h",
                 myconst,big_word);
      error = 1;
    end
  #100 ;
  mem_buffer[2] = 8'h56;
  #50;
  myconst = 32'h12_34_56_00;
  if(big_word !== 32'h12_34_56_00)
    begin
      $display("FAILED -Memory assign - expect %h, but have %h",
                 myconst,big_word);
      error = 1;
    end
  #100;
  mem_buffer[3] = 8'h78;
  #50;
  myconst = 32'h12_34_56_00;
  if(big_word !== 32'h12_34_56_78)
    begin
      $display("FAILED - Memory assign - expect %h, but have %h",
               myconst,big_word);
      error = 1;
    end
  #100;
  mem_buffer[0] = 8'hab;
  #50;
  myconst = 32'hab_34_56_00;
  if(big_word !== 32'hab_34_56_78)
    begin
      $display("FAILED - Memory assign - expect %h, but have %h",
                myconst,big_word);
      error = 1;
    end

  #100;
  if (error ===0)
     $display("PASSED");


end
endmodule