data/full_repos/permissive/172201645/test_benches/tb_data_stream.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_data_stream.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #4     \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/172201645/test_benches/tb_data_stream.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #4     \n  ^\n%Error: data/full_repos/permissive/172201645/test_benches/tb_data_stream.v:97: Cannot find file containing module: \'test_source\'\ntest_source i_test_source(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/test_source\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/test_source.v\n             data/full_repos/permissive/172201645/test_benches,data/full_repos/permissive/172201645/test_source.sv\n             test_source\n             test_source.v\n             test_source.sv\n             obj_dir/test_source\n             obj_dir/test_source.v\n             obj_dir/test_source.sv\n%Error: data/full_repos/permissive/172201645/test_benches/tb_data_stream.v:105: Cannot find file containing module: \'main_stream_processing\'\nmain_stream_processing i_main_stream_processing(\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_data_stream;

reg        tx_symbol_clk;
reg        tx_align_train;       
reg        tx_clock_train;       
reg        tx_link_established;
reg f;

wire [72:0] msa_merged_data;
wire        test_signal_ready;
wire  [2:0] stream_channel_count;

initial begin
  tx_symbol_clk       = 1'b0;
  tx_align_train      = 1'b0;
  tx_clock_train      = 1'b0;
  tx_link_established = 1'b1;
end

always begin
  #4
  tx_symbol_clk = ~tx_symbol_clk;
  #4
  tx_symbol_clk = ~tx_symbol_clk;
  $display("%b %b", 
         msa_merged_data[8:0],  msa_merged_data[26:18]
  );

  $display("%b %b", 
         msa_merged_data[17:9], msa_merged_data[35:27]
  );
end




test_source i_test_source(
        .clk                  (tx_symbol_clk),
        .stream_channel_count (stream_channel_count),
        .ready                (test_signal_ready),
        .data                 (msa_merged_data)
    );

wire [79:0] tx_symbols;
main_stream_processing i_main_stream_processing(
        .symbol_clk          (tx_symbol_clk),
        .tx_link_established (tx_link_established),
        .source_ready        (test_signal_ready),
        .tx_clock_train      (tx_clock_train),
        .tx_align_train      (tx_align_train),
        .in_data             (msa_merged_data),
        .tx_symbols          (tx_symbols)
    );

endmodule
module tb_data_stream;


reg        tx_symbol_clk;
reg        tx_align_train;       
reg        tx_clock_train;       
reg        tx_link_established;
reg f;

wire [72:0] msa_merged_data;
wire        test_signal_ready;
wire  [2:0] stream_channel_count;

initial begin
  tx_symbol_clk       = 1'b0;
  tx_align_train      = 1'b0;
  tx_clock_train      = 1'b0;
  tx_link_established = 1'b1;
end

always begin
  #4
  tx_symbol_clk = ~tx_symbol_clk;
  #4
  tx_symbol_clk = ~tx_symbol_clk;
  $display("%b %b", 
         msa_merged_data[8:0],  msa_merged_data[26:18]
  );

  $display("%b %b", 
         msa_merged_data[17:9], msa_merged_data[35:27]
  );
end




test_source i_test_source(
        .clk                  (tx_symbol_clk),
        .stream_channel_count (stream_channel_count),
        .ready                (test_signal_ready),
        .data                 (msa_merged_data)
    );

wire [79:0] tx_symbols;
main_stream_processing i_main_stream_processing(
        .symbol_clk          (tx_symbol_clk),
        .tx_link_established (tx_link_established),
        .source_ready        (test_signal_ready),
        .tx_clock_train      (tx_clock_train),
        .tx_align_train      (tx_align_train),
        .in_data             (msa_merged_data),
        .tx_symbols          (tx_symbols)
    );

endmodule