data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v
 line:50: before: "$"
1: b'%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #200\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #1000\n ^\n%Error: data/full_repos/permissive/106583614/Lab3/VGAMemory_tb.v:12: Cannot find file containing module: \'VGAMemory\'\nVGAMemory vga_vram_0(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAMemory\n             data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAMemory.v\n             data/full_repos/permissive/106583614/Lab3,data/full_repos/permissive/106583614/VGAMemory.sv\n             VGAMemory\n             VGAMemory.v\n             VGAMemory.sv\n             obj_dir/VGAMemory\n             obj_dir/VGAMemory.v\n             obj_dir/VGAMemory.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module VGAMemory_tb;
reg clk;
reg rst_n;
reg [13:0] pixel_addr_a;
reg [13:0] pixel_addr_b;

wire [31:0] VGA_Red0_p1, VGA_Green0_p1, VGA_Blue1_p1;
wire [31:0] VGA_Red0_p2, VGA_Green0_p2, VGA_Blue1_p2;
 
VGAMemory vga_vram_0(
	.reset (rst_n),
	.clk (clk),
  	.pixel_addr_a(pixel_addr_a),
	.pixel_addr_b(pixel_addr_b),
	.red_out_p1 (VGA_Red0_p1),
	.green_out_p1 (VGA_Green0_p1),
	.blue_out_p1 (VGA_Blue1_p1) ,
	.red_out_p2 (VGA_Red0_p2),
	.green_out_p2 (VGA_Green0_p2),
	.blue_out_p2 (VGA_Blue1_p2)
);

localparam CLK_PERIOD = 20;
always #(CLK_PERIOD/2) clk=~clk;

initial begin
	rst_n = 1;
	clk = 1;
	#20; 
	rst_n = 0;
	#200
	pixel_addr_a = 14'h0000;
	pixel_addr_b = 14'h0020;
	#20;
	pixel_addr_a = 14'h0040;
	pixel_addr_b = 14'h0060;
	#20;
	pixel_addr_a = 14'h0080;
	pixel_addr_b = 14'h00a0;
	#20;
	pixel_addr_a = 14'h00c0;
	pixel_addr_b = 14'h00e0;
	#20;
	pixel_addr_a = 14'h00ff;
	pixel_addr_b = 14'h0100;

	#1000
	$finish;

end

endmodule
module VGAMemory_tb;

reg clk;
reg rst_n;
reg [13:0] pixel_addr_a;
reg [13:0] pixel_addr_b;

wire [31:0] VGA_Red0_p1, VGA_Green0_p1, VGA_Blue1_p1;
wire [31:0] VGA_Red0_p2, VGA_Green0_p2, VGA_Blue1_p2;
 
VGAMemory vga_vram_0(
	.reset (rst_n),
	.clk (clk),
  	.pixel_addr_a(pixel_addr_a),
	.pixel_addr_b(pixel_addr_b),
	.red_out_p1 (VGA_Red0_p1),
	.green_out_p1 (VGA_Green0_p1),
	.blue_out_p1 (VGA_Blue1_p1) ,
	.red_out_p2 (VGA_Red0_p2),
	.green_out_p2 (VGA_Green0_p2),
	.blue_out_p2 (VGA_Blue1_p2)
);

localparam CLK_PERIOD = 20;
always #(CLK_PERIOD/2) clk=~clk;

initial begin
	rst_n = 1;
	clk = 1;
	#20; 
	rst_n = 0;
	#200
	pixel_addr_a = 14'h0000;
	pixel_addr_b = 14'h0020;
	#20;
	pixel_addr_a = 14'h0040;
	pixel_addr_b = 14'h0060;
	#20;
	pixel_addr_a = 14'h0080;
	pixel_addr_b = 14'h00a0;
	#20;
	pixel_addr_a = 14'h00c0;
	pixel_addr_b = 14'h00e0;
	#20;
	pixel_addr_a = 14'h00ff;
	pixel_addr_b = 14'h0100;

	#1000
	$finish;

end

endmodule