data/full_repos/permissive/21438680/DAQ_Firmware/src/ok/okLibrary.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/21438680/DAQ_Firmware/src/ok/okLibrary.v:94: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'okHost\'\nmodule okHost(\n       ^~~~~~\n                                                                                         : ... Top module \'okWireOR\'\nmodule okWireOR # (parameter N = 1) (\n       ^~~~~~~~\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ok/okLibrary.v:35: Cannot find file containing module: \'ok_altpll\'\n ok_altpll ok_altpll0 (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/21438680/DAQ_Firmware/src/ok,data/full_repos/permissive/21438680/ok_altpll\n             data/full_repos/permissive/21438680/DAQ_Firmware/src/ok,data/full_repos/permissive/21438680/ok_altpll.v\n             data/full_repos/permissive/21438680/DAQ_Firmware/src/ok,data/full_repos/permissive/21438680/ok_altpll.sv\n             ok_altpll\n             ok_altpll.v\n             ok_altpll.sv\n             obj_dir/ok_altpll\n             obj_dir/ok_altpll.v\n             obj_dir/ok_altpll.sv\n%Error: data/full_repos/permissive/21438680/DAQ_Firmware/src/ok/okLibrary.v:90: Cannot find file containing module: \'okCoreHarness\'\n okCoreHarness core0(.okHC(okHC), .okCH(okCH), .okHE(okHE), .okEH(okEH));\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module okWireOR # (parameter N = 1)	(
	output reg  [64:0]     okEH,
	input  wire [N*65-1:0] okEHx
	);

	integer i;
	always @(okEHx)
	begin
		okEH = 0;
		for (i=0; i<N; i=i+1) begin: wireOR
			okEH = okEH | okEHx[ i*65 +: 65 ];
		end
	end
endmodule
module okWireOR # (parameter N = 1)	(
	output reg  [64:0]     okEH,
	input  wire [N*65-1:0] okEHx
	);


	integer i;
	always @(okEHx)
	begin
		okEH = 0;
		for (i=0; i<N; i=i+1) begin: wireOR
			okEH = okEH | okEHx[ i*65 +: 65 ];
		end
	end
endmodule