In a single cycle datapath, do 'decode' and 'operand fetch' occur simultaneously? After instruction has been fetched, does it go to control unit and register file at the same time or one after the other?
For example if the control unit and register read both have 80ps delay, and we're calculating the total delay for a cycle, would we take their delay as 80ps(if they occur simultaneously) or if they happen one after the other so in that case delay of decode and operand fetch would be 160ps. Which one is correct?
Figured it out. The control unit and register file are accessed one after the other. So the total delay would be 160ps.