D flip flop : How does it work in depth I'm coming to you today because I have some trouble to understand how works D flip flop in depth. Two weeks ago we started at school learning sequential logic and so register and everything that come with. We saw how to build a D flip flop using RS Asynchronous flip flop like this one :  

Then we made a synchronous version of this one using two AND logic gate (one per input) and a clock input. The D flip flop we made is only a RS Asynchronous using only one input linked to S, and the NOT linked to R. Just like this :



And as I wrote it works on HIGH LEVEL. So to make any shift register based on this it is impossible. So I decided to go my own way and I ended with something like this :


I was conviced that it's the good way. It works on falling edge so it's perfect for shift register. And then my teacher told me that we couldn't use any gate on clock (in my case I use a NOT gate). But he can't tell me clearly how to do a D flip flop working on rising or falling edge. Even if Logisim (the software I use to simulate circuits) there is a D flip flop where you can make it working on Rising, falling edge or even at high or low level.
So my main question is : What is the good way to make a D flip flop working or RISING or FALLING edge if we can't use a single gate on clock ? And why can't we use gate on clock ?
Here's a big hint, and then I'll let you work out the rest for yourself. Because we want cs.SE to be a collection of questions and answers, please post your solution as an answer.

Edge-triggered D flip flops are generally done using the "two RS flip flop" design that you have. You got that right. Reading from left to right, I'm going to call these RS flip flops "stage 1" and "stage 2".

Before the transition "happens", stage 1 should load the data. The effect of the transition is to make stage 1 hold its data and make stage 2 load its data from the output of stage 1.

So to create a D flip flop that is triggered on the rising edge:


When the clock is low, stage 1 should load its data and stage 2 should hold its data.
When the the clock is high, and stage 2 should load its data and stage 1 should hold its data.


The effect of this is that the transition from low to high shifts the result from stage 1 to stage 2.

Conversely, to create a D flip flop that is triggered on the falling edge, stage 1 should load when the clock is high, and stage 2 should load when the clock is low.

Now can you implement that?

Incidentally, I don't understand your teacher's requirement "we couldn't use any gate on clock". When you realise digital circuits in CMOS or NMOS, clock fanout is a large practical issue. Besides, you only get inverting gates, so putting gates on clock lines is normal and expected.

Nonetheless, perhaps they meant you to use de Morgan's laws to reduce the gate count?