How does MIPS ( or any other multi-byte word arch ) fetch a word? I've recently been studying MIPS as part of a CS course, but something bugs me.
We've seen so far that MIPS increments the PC by 4 each cycle because each word is in fact comprised of 4 bytes (32 bits), each with their own address. 
I've also seen that a theoretical RISC machine has instructions that should only take a single cycle to execute.

Ignoring memory latency, how does it manage to generate an address for each 4 bytes? 
It can't have four adders for memory address calculation right? That'd be too expensive! Or am I incorrect in this assumption? 
I've also seen other architectures that manage to pull multiple bytes from memory (even multiple words) in a single step/cycle/instruction, but how is this achieved if each byte needs an address?
MIPS can load a 32-bit (4-byte) word in a single instruction (load word, LW). The fact that each byte of the word is individually addressable doesn't affect this.  Effectively, the instruction says "Read the four bytes beginning at this address", not "Read the byte at this address.  Increment the address by one.  Read the byte at that address.  Increment the address by one.  Read the byte at that address.  Increment the address by one.  Read the byte at that address."

By way of an analogy, you can photocopy any two facing pages of a book simultaneously, even though each has its own number.