Where do these DRAM row/column calculations come from? Let r be the number of rows in a DRAM array, and c be the number of columns.

Apparently, DRAM with organization 16x1 requires least pins when r = c = 4 because fewer address bits are required to represent them, and so does DRAM with organization 16x4. Why are these the same? Doesn't the latter have 4 columns instead of 1?
The first value describing the DRAM is the number of data-interface-sized "chunks" it contains and the second value is the width of the data interface in bits, i.e., bits per "chunk".  A 16x1 DRAM would only have 16 bits addressable at 1-bit granularity, with four rows and four columns allowing a minimization of address pins.  A 16x4 DRAM would have 64 bits addressable at 4-bit granularity (and with 16 addressable units a 4 row and 4 column arrangement would minimize address pins).