In cycle stealing mode, Does CPU gets blocked for 1 cycle or blocked till DMA transfer completion? In cycle stealing mode, is CPU idle during data transfer between peripheral devices or idle only for 1 cycle ( during shifting of bus controls ) ? 
Because I'm unable to understand these lines. 


  The DMA module is transferring characters at the rate of 1200 characters per second. or one every 833 microsecond. The DMA therefore steals every 833rd cycle. 


Now, I think these lines make sense only if we assume CPU is blocked for 1 cycle not during 833microsecond(during DMA transfer). 
Please anyone help me where I'm wrong or am I missing something.
The CPU doesn't stay idle at all. It just gives the control of the data Bus to the DMA for 1 memory cycle . DMA transfers the data in this cycle which is consistent with it's transfer rate. Meanwhile the CPU can perform operations which do not involve the memory bus (by the means of cache memory and registers). In the scenario which you have presented assuming each instruction takes 1 cycle to complete , every 833rd instruction will have to wait for the DMA to complete its operation.