Compiler instructions to sync core caches: are they really needed? I have read reviews of this book, and quote the following from one of the reviews (emphasis mine):


  Other than straining your eyes with old-styled C++, you can read such
  misconceptions in the book like "Since Boolean values are generally
  atomic, setting and checking can be done simultaneously without risk
  or requiring a mutex." Which ignores the facts that, the compiler
  doesn't necessarily have to generate instructions to resync the value
  in register with the one in memory. And even if it does, the hardware
  doesn't have to resync the cache lines.


I have also followed all of the "High Performance Computer Architecture" course from Georgia Tech (also on YouTube) and learned about cache coherency protocols.

From what I have learned, modern processors will use the write-invalidate protocol; when one core writes to a block, any other cores that share this same block will learn of the change via an invalidation message sent on the bus so they will have to go and get the new value from memory instead of using their cached copy.

With this in mind, what is the author of this comment talking about?  It seems the coherency protocol is doing everything for me, hence there is no need to use synchronisation?  Are they wrong or am I missing something?

PS Yes I know I mention C++ but I feel this is more hardware related hence me asking it here.

PPS If I've missed something, please post a link to the information before just downvoting; a downvote without explanation is useless.

Update

If a boolean b was being used in two threads, each one on a different core, what would making the variable atomic/using a sync variable do regarding the cache coherency that doesn't happen with a none-atomic var/no use of a sync variable?  (I think this is the problem in my understanding - I am believing that the cache coherency protocol fires off "for free" (is this right?); or do I need to use some special instruction to "start it off" (that is, trigger the sending of the invalidation message on the bus) for want of a better phrase?)

Update 2

Write Invalidate Snooping Coherence - Georgia Tech - HPCA: Part 5 talks about how the caches of different cores operating on the same block are synchronized.

My confusion stems from the fact that the comment I quote seems to state that boolean values are not guaranteed to be synchronized between caches on different cores, and that some sort of atomic operation or synchronization primitive (eg mutex) is needed to do this.  The video I link to however mentions nothing of the sort; it suggests (to me at least) that the caches are updated automatically by virtue of the coherency protocol, not by any special instructions (such as those generated for atomic operations or synchronization primitives) in the code.  This is what I am asking for clarification on.
This is very simple actually, and has nothing to do with hardware whatsoever. If you have a variable

static bool b;


and some code

b = true;
dosomething();
b = false;
dosomethingelse();
b = true;


If the compiler can figure out that dosomething() and dosomethingelse() don't read or write b, then the compiler is not required to generate code for the assignments to b, except the last one. 

With the book's subtitle "Write robust, concurrent, and parallel applications" this is quite worrying.