Differences between SISD, SIMD and MIMD architecture (Flynn classification) I have a problem with classifying certain CPUs to the proper classes of Flynn's Taxonomy.

1. Zilog Z80

According to this article on Sega Retro, Z80 has limited abilities to be classified as SIMD:


  a limited ability for SIMD (Single Instruction, Multiple Data) with instructions to perform copy, compare, input, and output over contiguous blocks of memory;  


For what I understand, Z80 is usually behaving as a SISD but when it comes to performing thing like copying or comparing Z80 is able to process multiple data using a single instruction.

How should we classify Z80 then? Is the ability to become SIMD processor a voice for or against saying that Z80 implements SIMD architecture?

2. Intel i5 (Dual core)

Form what I understand, we classify multicore CPUs as MIMD. 

Is it as simple as that?

3. ARM Cortex-A15 (single core)

I'd classify the architecture of this processor as a SIMD model. Wikipedia says that it has superscalar pipeline, but as we know from Why is a superscalar processor SIMD? that multiple pipelines does not imply MIMD model.

Are "modern" single cores usually implementing SIMD model or not?
Michael J. Flynn is one of the all-time great computer architects.  He was the design manager of the IBM 360/91, and made numerous foundational contributions in the areas of pipelining, and in computer arithmetic.

But the Flynn Taxonomy has not stood the test of time, and is no longer useful.

The SI/MI part of the taxonomy is easy to differentiate on the surface: how many hardware instruction pointers (sometimes called program counters) does the machine have?  If there is one hardware instruction pointer the machine is "SI" (either SISD or SIMD).  If there is more than one hardware instruction pointer the machine is "MI" (either MISD or MIMD).

If you go a bit deeper, it becomes less clear though.  Does a vector machine with one instruction pointer but vector predicate registers count as SI or MI?  Why is a machine with only one fetch unit that can quickly (just a few cycles) switch back and forth between two different instruction pointers MI, but a machine with only one fetch unit that can context switch once ever few-hundred or thousand cycles considered SI?  Is a machine with two hardware instruction pointers, but that only context switches at long-latency cache misses SI or MI?

The SD vs. MD distinction is just a complete mess.  When Flynn made up the classification I believe he was referring to whether the machine had instructions that could operate on multiple independent pieces of data or not.  That does not mean that the operations happen simultaneously.  It could mean that the machine has instructions that operate on vectors of numbers, one at a time (or maybe pipelined), like the CDC STAR-100. The vector instructions in the CDC STAR-100 were pretty complex, giving two vectors start addresses to load, a start address for storing the result vector back to memory, and an arithmetic operation.  The vector lengths were controllable on the CDC STAR-100.  The CDC STAR-100 designers could have leveraged the implicit independence of the operations in the vector instructions to make some of those operations happen truly simultaneously, but they did not.

It may be more appropriate to talk about whether certain instructions in an instruction set architecture are "SIMD" or not.  The ARM NEON instructions are SIMD instructions, but most of the other ARM instructions are not SIMD.

I don't know whether the Z-80's copy instruction was SIMD or not.  I guess I'd call it SIMD because I can't think of any reason not to call it SIMD.