Why reverse pipeline stages in cycle-level simulator? In pipeline simulator exercise, it says that:


  Traversing the stages in backwards order simplifies the instruction flow through the pipeline.


Also, in gpgpu-sim source code, the stages are reversed (line 2442):

void shader_core_ctx::cycle()
{
    m_stats-&gt;shader_cycles[m_sid]++;
    writeback();
    execute();
    read_operands();
    issue();
    decode();
    fetch();
}


Why? What problem it solves? Can anyone elaborate a bit or give a pointer to books/papers on this particular "trick"? 

Many thanks!
This solves the problem that, if you put them in "forward" order, an instruction can stream all the way from fetch to writeback in a single cycle of the emulator. An other solution is explicitly emulating the clocked logic between the stages as it would exist in hardware, but it takes more effort that way. Running the stages in reverse is a simple trick that also ensures that instructions properly "wait" at the boundaries between stages.