How can I calculate the effective bandwidth of a memory system? I am currently doing my homework for my Computer Architecture class. One of the questions asks: 


  A computer has a 64-bit data bus and 64-bit-wide memory blocks. The memory devices have an access time of 35 ns. A clock running at 200 MHz controls the computer and all operations take an integral (i.e. whole number) of clock cycles. What is the effective bandwidth of the memory system?


The problem is, there's pretty much nothing in my textbook that explains how to figure this out. Searching online doesn't return much help either. I'm not asking anybody to answer the actual homework question for me, but if you could explain to me how to figure it out, or point me in the right direction I'd really appreciate it!
An N-bit wide data bus can transfer N bits in one clock cycle, after a latency of d clock cycles (or t seconds).

I think the above sentence has everything you'd need to solve this problem.