Harvard processor structure In my books it is written that the concept of pipelining can happen only with Harvard structure as CPU can both fetch data from and write back data to memory at the same time my question is how can fetching and writing back be done at the same time when there is only one bus for data just like von Neumann structure? How can using an instruction bus be helpful when it only carries instruction but not data?

So if I want to add 2+5 here 2 and 5 are data but + would be the instruction right?
If I fetch 2 and 5 from data cache and add from instruction cache then execute and again write back the result 7 which would be a data to memory and before the whole process is done fetch another data for example 7 and 6 like in what the book stated according to the picture would it still be fetching (the data 7 and 6) and rewriting the data 7 (result of execution) happen at the same time both these numbers are data and have to be fetched and rewritten using data bus so it still be impossible to fetch and rewrite them at the same time and the instruction bus wouldn't be useful.
This is one of the reasons why most modern general-purpose CPUs have split L1 caches, one for instructions and one for data. (It's not the only reason, of course.)
You see, modern CPU pipelines don't interact with a von Neumann-type bus at all, but directly with cache. As far as the pipeline is concerned, instruction memory and data memory are separate because the caches are separate.