What does "fast-forwarding" mean in the context of CPU simulation? I'm using a simulator for my thesis and I've come across the term "Fast-forwarding" but I have found no definition anywhere in the documentation or online. From a pdf I've been reading about the simulator I am using (gem5), I've come across this section:


  The gem5 simulator supports four different CPU models: AtomicSimple,
  TimingSimple, InOrder, and O3. AtomicSimple and TimingSimple are
  non-pipelined CPU models that attempt to fetch, decode, execute and
  commit a single instruction on every cycle. The AtomicSimple CPU is a
  minimal, single IPC CPU which completes all memory accesses
  immediately. This low overhead makes AtomicSimple a good choice for
  simulation tasks such as fast-forwarding. Correspondingly, the
  TimingSimple CPU also only allows one outstanding memory request at a
  time, but the CPU does model the timing of memory accesses.


Does anyone know what this term actually means?
Fast forwarding is used to warm-up microarchitectural state (caches, branch predictors, etc.) in preparation for more accurate simulation of a particular section of interest within an application. Since microarchitectural state can depend on operation ordering (e.g., cache replacement for data accesses and interactions between threads), speculation (e.g., instruction caching behavior), and even timing (e.g., thermal behavior), this is not a perfectly accurate warm-up, but "all models are wrong".