Determining cycle time and and hold time in logic circuits First I have general question. In a circuit with both logic and D edge flip flop does hold time have to satisfy $t_{hold} &lt; t_{setup}($D-FF$) + t_{pd-min}$(Logic), 

or is it enough that $t_{hold} \le t_{setup}($D-FF$) + t_{pd-min}$(Logic) ?

Also i have a question about a specific circuit: 

with the following times: 

the question is how much time at least, before and after the fall of the clock does the Input have to be steady? when it is given that $t_{hold}=8ns$

Now, from what I know, the input has to be kept steady for at least $t &lt; t_{pd-min}$(Logic) +$t_{setup}$ time. So I don't understand how $t_{hold}$ comes into consideration here. I'll be glad if could explain.
Well if someone is interested I have solved the question myself. 

First of all, it indeed is possible that $t_{hold} = t_{setup} + t_{pd-min}$.

And about the input time, it has to satisfy: $$t_{hold} \le t_{pd-min}(logic) + t_{input-valid-min}$$

since $t_{hold} = 8ns$ and $t_{pd-min}(Logic) = 10ns$ , even $t_{input-valid-min} = 0$ satisfies this.