How is clock syncing implemented? I'm looking for an explanation or reference on the implementation of computer clock. To keep the question at the level of logical abstractions: say, we put together some combinational and sequential logic from basic gates. The role of the clock (an oscillator of some sort, but that's going into more detail than needed for my abstraction) is to synchronise the unorderly chorus of inputs and outputs passing through the gates. Exactly how does the clock synchronize the signals? 

To render things more concrete... Take a two-way NAND gate. Say, I set the two inputs (U1) to high signal, and obtain (after some inherent delay) a stable low signal at the other end (U2). Now, to add basic sequential logic to this inverter, let's add a Data Flip-Flop (DFF). The effect is that we can be certain that the Q end of the DFF will broadcast the low signal "definitively" at the start of the next clock cycle. What happens within the cycle is not to be trusted. The clock period is set such that the other circuitry (NAND gate in my case) has the time to stabilize during the cycle. This is the contract. But how is it achieved?

The metaphor in my mind is that the clock acts as a sluice. But the comparison is misleading, in that the signal entering and exiting the DFF is not truncated at any point. We could physically measure the signal within the tick-tock cycle of the clock at the Q end of the DFF. Another high-flown metaphor would be the warm-up motions of an orchestra before the rehearsal gradually transforming into an attuned performance, with the conductor setting the beat. 

How is the proper signal (attuned to the clock's oscillations) distinguished from the noise propagating through gate circuitry at all times? I realize, there may be missing parts in my picture, so that question should be framed in constructive terms: 
How can one implement this basic circuit to allow the logic to distinguish between signal and noise?




Edit: Judging by responses to this question, my original question must be poorly phrased. I understand the reasons behind the choice of frequency for the system clock to ensure the circuit is stable on the tick of the clock. The responses from @Ran G. and @slebetman emphasize the "contractual" side of things. My question is really about why the contract holds. In retrospect, what I was getting at is the trivial fact that measuring instruments (system clock) must be selected based on the degree of precision required -- in a typical case discussed here, for our human sluggish attention span. 

To illustrate, here's a graph of the clock pulse against data-in and Qa output for a DFF. 



Say, in the 2nd clock cycle, Captain Marvel sends a pulse on the data-in line and -- oblivious to the clock period -- expects to read it off immediately (mid-phase). With his lightning speed, there's no way he can make sense of the output of this circuit because the clock cycle is geological time to him. Billy Watson, on the other hand, can read it just fine. Neither Captain M. nor Billy W. is synchronized with the system clock. Not in the sense that the gate circuitry is. But for Billy's experience of time, the clock's time scale is sufficiently precise.
I feel there are multiple questions in your post. I will attempt to answer the first -
&quot;...The clock period is set such that the other circuitry (NAND gate in my case) has the time to stabilize during the cycle. This is the contract. But how is it achieved?
Shown below is a transistor level circuit of the D flip-flop shown in the picture in your post.
If you replace your D-ff schematic with the above picture, you can see how the signal propagates from the D input to the Q output.
Your second question is
How can one implement this basic circuit to allow the logic to distinguish between signal and noise?
Logic does not distinguish signal from noise. Noise is a signal. It is an (usually) unwanted signal, but a signal all the same. It is the job of the designer to ensure that noise from various sources does not pollute the actual signal so much that it results in an incorrect reading at the Q output.
Circuits have some amount of noise immunity. Chips and cell libraries are designed such that the noise does not cross the specified noise immunity of the circuit.