why are WAW and WAR hazards not possible in mips architecture i have read about data hazards and then came across that mips architecture doesn't allow WAR AND WAW hazards can someone please help me understand it? the reason is not given in the book the MIPS pipeline is divided into :

1.IF(instruction fetch) 2.ID(decode the instruction) 3.EX(execute instruction) 4.MEM(write or read from the memory) 5.WB(write back to the register file)
for eg in case of  WAW hazards :

I1:  LOAD R1,0(R2)      

I2:  ADD R1, R2, R3 

I1:  |IF|ID|EX|MEM|WB |
I2      |IF|ID|EX |MEM|WB|


The above is expected way in which the instructions execute without data hazards
but here the second instruction has to wait till the WB phase of the instruction I1  for getting the value of R1  hence it will stall till the value of R1 is available in register file i.e till WB phase of the I1. here what my doubt is in case I2 Takes less number of clock cycles than I1 for completion then can I2 access the register file going to WB phase directly in case it has nothing to do in the phase of MEM  will this give rise to a hazard?
in case I2 Takes less number of clock cycles than I1 for completion then can I2 access the register file going to WB phase directly in case it has nothing to do in the phase of MEM will this give rise to a hazard?


I2 reads the register R1 at its ID phase. Therefore, if implemented directly, we must have time(I2.ID)>time(I1.WB).
A more sophisticated solution would bypass the register file and take the values directly from the Memory output. In this case we need 
time(I2.ID)>time(I1.MEM) and the controller becomes more involved.

If I understand your question correctly, you ask whether I2 must take 5 clocks although it doesn't use the MEM phase. The answer is YES or otherwise, it may conflict with other instructions that would try to use MEM at the same time (unless the pipeline controller stalls them when congestion appears).