Nandgame--I am not sure I understand the Data Flip-Flop specifications Nandgame (nandgame.com) has you solve puzzles of increasing complexity which culminate in constructing a simple CPU. You start at the level of nand gates, and build everything else up out of those.

I'm having trouble understanding the specifications for the Data Flip-Flop puzzle. If I'm reading it correctly, when the "clock" bit changes from zero to one, the storage device should send its value to output, but while the "clock" bit remains either one or zero, nothing should change the output value.

What I'm stuck on is this idea of having output change when and only when the clock changes from zero to one I can't see a way to do that which doesn't allow the output to change any time the clock bit is equal to one (or trivially, equal to zero if I thrown an inverter on it fsr). But that results in a failure when I submit such solutions.

Could I just be reading the specifications incorrectly somehow?

Here is a transcription of the specification:

A DFF (Data Flip-Flop) component stores and outputs a bit, but only change the output when the clock signal change from 0 to 1.

When st (store) is 1 and cl (clock signal) is 0 the value on d is stored. But the previous value is still emitted.

When the clock signal changes to 1, the flip-flop starts emitting the new value.

When st is 0, the value of d does not have any effect.

When cl is 1, the value of st and d does not have any effect.
I have worked 20 years as FPGA logic designer but I stop at task Data Flip-Flop!
It is possible to build Data Flip-Flop. Two latches is required (sequential connection). First latch stores input data when st&amp;!cl, second latch stores result of first latch to output when st&amp;cl. Unbeliveable! Thanks to google...