What is the difference between Data Hazard and Dependencies in Pipelining In my GATE Exam I have given with the following question  statements and

R5 ← R0 + R1
R6 ← R2 * R5
R5 ← R3 - R6
R6 ← R5/R4
X  ← R6

the question was to calculate number of Output, True and Anti Dependencies in the instructions.
I calculated and it turns out to be
RAW (True Dependency)

I1 - I2 (R5)
I2 - I3 (R6)
I3 - I4 (R5)
I4 - I5 (R6)

WAR  (Anti-Dependency)

I2 - I3 (R5)
I3 - I4 (R6)

WAW (Output Dependency)

I1 - I3 (R5)
I2 - I4 (R6)

Now my friend argued

Had the question been to calculate the number of possible data hazards the answer would have been different because Dependencies and hazards are not same

When we calculate possible hazards we should reorder the instructions and find the dependencies. Dependencies and hazards are closely related but not same. He has also gave me a pdf which implies that a dependency may not be a hazard. A dependency is a &quot;possible hazard&quot; considering all cases which involve reordering of instructions etc. But the solution of GATE question is involving those dependencies only which are causing hazards only not potential or possible hazard.
I go through them but was not able to finalize proper relationship between hazard and dependencies.
Can someone please explain how Dependencies, Possible Hazards and Potential Hazards  relate to each other in a way more easily understood? (Explanation using the above instruction set  is preferred)
I think a dependency is something you see by looking at the code and trying to figure out possible WAW, WAR, RAW hazards that could happen. Actual hazards instead are a property of the pipeline which means that a dependency you found earlier may or may not generate an hazard depending on the actual code execution in the processor. 
In your example there's an output dependency between the instructions I2 - I4, but if we assume that the pipeline does not stall for any reason between the two and that the execution time for each instr. is the same, I2 wll be completed before I4 thus not generating any hazard. 
To make the answer more clear, with the information you give about the excercise it's impossible to know the number of hazards because we don't know the architecture on which that code is executed nor the state of the pipeline. 
I found your question searching for an answer so I'm not completely sure. Since you asked some months ago maybe you already found the correct answer. If so could you share it please ?