Query about FP Divide latency and Initiation Interval Latency is defined as the number of intervening cycles between an instruction that produces a result and an instruction that uses the result. The initiation or repeat interval is the number of cycles that must elapse between issuing two operations of a given type.

In the Appendix C, pages 52-54 of Computer Architecture: A Quantitative approach 5th edition, it was mentioned that 


the FP adder is of 4 stages and pipelined, so latency =3(No. of pipeline stages -1) and initiation interval =1 (as pipelined)
the FP multiply is of 7 stages  and pipelined, so latency =6(No. of pipeline stages -1) and initiation interval =1 (as pipelined)


So for
3. The FP divide of 24 stages and unpipelined, so latency =23(No. of pipeline stages -1) and initiation interval =24 (as unpipelined). But it was mentioned that   the latency was 24 and initiation interval was 25.

latency and initiation interval and FP pipeline

Why is this?

Can anyone explain me? As I missing something
You can think latency as the time (# intervening clock cycles here) required to get a result from a producer instruction to a consumer instruction. For FP divider it is required 25 cycles and the unit is unpipelined. So, the #intervening CC = 24.
On the other hand, initiation interval is the duration of time that is required to issue two similar type instruction. As FP divider is unpipelined, so you can issue another FP divider after finishing the previous one which requires 25 clock cycles. If it was pipelined, I guess it would be 1.