Why S=1, R=1 Is forbidden in RS-Flip Flop I have come across about RS Flip Flop &amp; I have tried implementing that on a simulator &amp; using actual logic gates. But I'm still not sure whether I have correctly understood the case unstable or the forbidden case S=1, R=1 in Flip flop. Can anyone tell me what exactly is that?

By the way I have used 2-INPUT NAND Gates to implement the flip Flop. What is the difference between the NAND Gate Flip Flop &amp; NOR Gate Flip Flop, ?
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Digest: If you had both inputs set to $1$, both outputs would be $0$ but they are supposed to be complementary.