Loading a word from byte-addressable cache I have asked a similar question at stack-overflow, but then I found this question here, and figured it should go here instead..
So, my question is pretty much the same as the one in the question I linked:
I know that in a byte-addressable cache, a byte-offset (usually the LSB of the address) is used to determine which byte to access out of the designated cache block.
But, if the offset allows the selection of 1 byte out of the block, we would need 4 subsequent accesses to the cache in order to access a single word (assuming a word equals 4 bytes), and I somehow doubt that's the way things execute in real time.. Any clarification regarding that will be appreciated, as I didn't find an answer to that in the previous question).
Thanks in advance :)
Edit:
To clarify my question - I'm trying to understand how can a Byte-Addressable memory output more than 1 Byte at a time. 
I'd understand it if the memory Always outputs a whole word, for example, and the byte is then extracted by the CPU according to the requested address by specifying an offset of 0x0 to indicate that it needs 2 bytes - the 1st and 2nd bytes, 0x1 to indicate it needs the 3rd and 4th bytes, 0x00 to indicate it needs only 1 byte - the first byte, 0x01 to extract only the 2nd byte, 0x02 to extract only the 3rd byte, 0x03 to extract only the 4th byte, and specifying no offset at all to tell the CPU &quot;do not extract any specific bytes - process the word as a whole&quot;.  That will make for a nice explanation - But I've seen no indication of anything of the sorts while looking at various CPU implementations..
What makes you think that? 

If you have a modern high-performance CPU with 256 bit = 32 byte vector registers, then the byte offset determines which group of 1, 2, 4, 8, 16 or 32 consecutive bytes to transfer. Nobody in their right mind would transfer individual bytes. Much too slow. 

What will happen and may slow down things a little bit is that if the group of bytes to transfer is not contained in one single cache line, then two accesses are made to two different cache lines. For example, if your cachle lines are 64 bytes and you try to access a 32 bit (four byte) item at byte offset 61, 62 or 63.