Applying information theory to processor clocks Has there been any research on the subject of applying information theory to a processors clock? It occurred to me that a clock is actually transmitting data that is used for synchronization of different processor components. Once I started to apply information theory concepts to the clock a lot of interesting ideas came up. I.e. clock speed is equivalent to bandwidth, the two voltage levels it transmits are the equivalent to symbols making is a 2-level transmitter (duh), and the logical limitations on how to usefully apply those two symbols is equivalent to noise. Processor manufacturers increase channel capacity by increasing processor speed and processor architects try to increase information rate by designing smarter encoding/decoding techniques like pipe-lining, branch prediction, speculative execution, and even multi-core processors.

After looking at it like this, and considering that systems designers are going to greater and greater lengths to squeeze greater information rates from just two symbols, wouldn't it make sense to increase the symbol rate? I don't mean going to ternary or quaternary or any other-ary processing, but just giving the clock more symbols or using multiple "clocks". Of course the incredibly high speeds in modern processors and the extremely tiny transistor sizes tend toward not doing so, but it does introduce some interesting thought experiments.

Has anyone explored this in an academic or experimental setting?
Technically, clock skew does this already. Specifically the technique known as "useful skew". When a data signal is going to travel from one storage element to another (both updating based on the clock), the clock that the source and destination elements receive are not quite the same.

In "useful skew", the clock at the destination is delayed such that the data has more time to travel before the capture clock edge arrives at the destination storage element. This allowed more distance of travel as well as more computation.