Transport Triggered CPU Architecture MOV and Turing Completeness Reading up on TTA CPU designs and the wikipedia article states that 


  Some TTA implementations support conditional execution.


The trick to make an TTA ISA Turing-complete with an unconditional MOV instruction escapes me. Can anyone explain how that would work?
(or share some resources where it is explained)
For a CPU designed to use a TTA (Transport Triggered Architecture), one way to implement conditional branch could use a couple of addresses for these purposes:


BRANCH_ADDRESS: stores the location to branch to
BRANCH_ZERO: Sets PC to BRANCH_ADDRESS when value written is 0. Otherwise does nothing.


This could be used to implement a 'branch-if-zero'. You could also add additional addresses that implement other branch modes, including those ithat hook into flags/state of other components hooked up to the TTA CPU, such as an ALU.