How does a CPU differentiate between 1-operand instructions and 2-operand instructions? Suppose that we have 5 different instruction categories (1 OP, 2 OP, 0 OP, branch, and sub-routine instructions), how does a CPU manage to know which category is which whenever it reads an instruction from IR register using the least number of bits for each category? For instance, PDP-11 uses 4 bits (15 → 9) for two-operand instructions and 10 bits (15 → 8) for one-operand ones to denote the opcode of a particular instruction, how does it identify in the first place whether it's a two-operand or a one-operand instruction so that it would read the first 4 or 10 bits accordingly?
Normally the opcode encoding is designed to make it easy to tell.  The details of exactly how that works will depend on the particular architecture.  For instance, in your example, the first 4 bits might be enough to determine which category the instruction is in.  This decoding is performed by the instruction decoder.

As Ran G. explains,


  usually, either all instructions have the same length -- and then different OPCODEs signify different operations, or the instructions have variable length, and then there is some sort of prefix-coding that allows the CPU to determine which instruction it is (and what it length is) by its prefix.