How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline? In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is:


List item before effective address calculation has started
during effective address calculation
after effective address calculation has completed
after data cache lookup has completed


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I think answer is 3.

Reason- Virtual address is given for TLB look up. TLB -Translation Lookaside Buffer, here Lookaside means during Address translation (from Virtual to Physical). But virtual address must be there before we look into TLB.

Please, explain which is the correct option. According to book the answer is 2.
I think that option 2, is wrong as it is explaining for physical address resolution and not for effective address calculation.
Often the effective address is the sum of a small constant and a value from a register. Not always, so this trick does not always apply. The trick then is to make a gamble: access the TLB based on just the value from the register, in parallel with adding the offset to it. Usually the small offset won't change the page being accessed, if that works out then you might have the result from the TLB a cycle earlier. Of course there needs to be a check afterwards to see if the upper bits of the virtual address didn't change, and if it fails the TLB access has to be re-done.

There is even a patent for this, with way more detail: Guess mechanism for faster address calculation in a pipelined microprocessor