Consensus anomaly about read-write registers and test&set I read this answer below and got into another question.

Why is the consensus number for test-and-set, 2?

I also read that read/write registers have consensus number 1.

But I see that in test&amp;set (also in compare&amp;swap) by using read write registers alone, we still arrive at consensus.

I think I am missing something very fundamental here. Need help.

The protocol in the accepted answer of the link is as mentioned below


  Suppose that we have two threads 0 and 1 that need to reach consensus.
  We could do this by letting each thread follow the consensus protocol
  below:
  
  
  Write your proposed value to A[t], where t is the thread id and A is an array of size 2
  Perform the test-and-set instruction on some register R, with R initialised to 0. 
  If the return value is 0, you were first: return A[t]. Otherwise, you were second: return A[|t−1|].
Consensus number and consensus hierarchy are defined in the classic paper "Wait-Free Synchronization" by Maurice Herlihy, 1991.

Note the keyword: wait-free.

Since you did not give the algorithms for test&amp;set using read/write registers only, I guess that they are not wait-free. (They may be lock-free instead.)



Added: 

After the discussions with the OP in the comments, I realize that the OP has not fully understood the difference between atomic test&amp;set registers and atomic read/write registers. He/she thought that the protocol given in the post uses read/write registers only. In fact, it uses test&amp;set registers/operations/instructions in the second step. 

A test&amp;set register supports the test&amp;set operation, which is a combination of test and set that cannot be interrupted. See this wiki for more details.