Could I simulate the implementation of memory components I am currently reading the IEEE paper A Memory-Efficient Parallel String Matching
Architecture for High-Speed Intrusion Detection by Kai Zheng,  Bin Liu,  Xin Zhang, and  Yunhao Liu. 

In the paper they propose a model for
 a memory-efficient multiple-character-approaching architecture
consisting of multiple parallel DFAs. 

I have read the paper and I have understood to an extent. 

But when I think of implementation, could I simulate the SRAM, LE,BCAM etc.. as in the case of a network simulator (NS-2,OPNET,OMNET).
You can simulate the architecture using a hardware-description language. 

Try VHDL (http://esd.cs.ucr.edu/labs/tutorial/) or Verilog ( http://www.asic-world.com/verilog/veritut.html) two of the most popular hardware description languages.