Any CPUs using value prediction, dynamic instruction reuse? There is a lot of research about techniques that try to reuse the previous result of an instruction, either memory loads or arithmetic, such as dynamic instruction reuse, value prediction, based on the concept of value locality.

What I wonder if there is any commercial CPU from Intel/AMD/ARM that actually uses any of these techniques, or are they still far away from being implemented in CPUs?

I mostly see these techniques as the runtime, CPU version of compiler optimizations such as common-subexpression elimination, loop invariant code motion, redundant load removal, catching cases that cannot be handled due to pointer aliasing, side-effects, etc.

Two of the papers that seem to have introduced these ideas:
Dynamic instruction reuse
Value Locality and Load Value Prediction
Modern Intel processors use prediction of values in several situations. 

One, when the target of a branch instruction is stored in memory including the location where the return address of a call is stored, that value is predicted. 

Second, when a store is followed by a load, it is predicted whether the addresses are the same (or overlapping) or not. That allows the load to be performed speculatively even before the value to be stored is calculated, if it is predicted that the addresses are different.