Memory Invalidation and Misses Assume this particular architecture of a machine. Say we have 4 processors and each processor has its private L1 cache and shared L2 cache. Now if we write to an address in one of the private cache's of the L1 cache then we Invalidate the blocks in the other private cache which contains the same address. Say P0(processor 0) reads an address 100 and so the block containing it say B0 gets stored in the private cache of P0 and as well as in the shared L2 cache. Now say P2  writes to the location 100. So we need to invalidate the block B0 from the private cache of P0. Now if P0 wants to read from address 100 again it will suffer a miss in its private cache, but will it get HIT or MISS in the L2 cache?
I think it will get HIT. Can anyone confirm.
It will be HIT in the L2 cache as you have guessed it because L2 cache maintains a directory or a bit vector which tells in which of the private caches the modified state of the block is in. So when L1 of P0 requests it for the second time, L2 will supply the latest modified block.