Memory access on byte/word addressable memory I'm doing a question on architecture and I've come across this question which I do not understand how to answer the question.

Q. How many bits are required to address 4G x 32-bit main memory if

a) Main memory is word addressable
b) Main memory is byte addressable

I have read this question Word- or byte-addressable? Correct terminology but it did not clear up my understanding of the question as I am NOT asking what is the difference between byte and word addressable, more specifically I want to understand this question I've written. 

The answer given says we need 34 bits for byte addressable memory and 32 bits for word addressable memory. I have thought about this for a while and have come to this conclusion which I do not know if it is correct or not:

Each row in the main memory is 32 bits in width and if it is byte addressable then we have 4 bytes in each row. To select a byte from the row requires log2(4) = 2 bits. Row width + 2 = 34 bits? Similiar concept for 32 bits. Is this correct logic?
The question is probably about address bits, not data bits.

A 4G x 32bits memory size is 16Gbytes.


With a 8bits data bus, you need 34 address bits (typically A[33:0])
With a 32bits data bus, you need 32 address bits (typically A[33:2]. A[1:0] is for selecting individual bytes inside the 32bits word.)