Would increasing system memory speed reduce a Von Neumann Architecture bottleneck? A Von Neumann Architecture bottleneck is a limit on the amount of data a computer can process due to limited bandwidth between the CPU and RAM. Possible mitigations to the problem according to Wikipedia are...


Providing a cache between the CPU and the main memory
Providing separate caches or separate access paths for data and instructions
Using branch predictor algorithms and logic
Providing a limited CPU stack or other on-chip scratchpad memory to reduce memory access
Implementing the CPU and the memory hierarchy as a system on chip, providing greater locality of reference and thus reducing latency and increasing throughput between processor registers and main memory.


I know that increasing the number of data lanes between the CPU and RAM would help, but would increasing the system memory speed also help?
No, increasing the memory speed won't help solve the Von Neumann architecture bottleneck. The reason is as memory size is increased the time required to access the memory contents increases. So no matter how fast the memory is, if it is large it will be slower. So faster, smaller memories called caches are used to provide the illusion of a large, fast memory to the user.