Process address space separation in L1 cache of Intel hyperthreaded CPUs Since a processing core with hyperthreading enabled is presented as two or more cores to the operating system, it can run completely different processes with different, isolated virtual memory spaces. There must be a mechanism that guarantees process address space isolation. How is it done in Intel hyperthreaded CPUs with regards to L1 cache? I can think of three possibilities:

1) virtual-physical address mapping is done before L1 (could add delay to L1);

2) each virtual core has its own L1 cache (costs space on the die);

3) only different threads of the same process are allowed to be hyperthreaded (must be implemented in the OS kernel)

Or is it something completely different?
In modern Intel processors, the virtual-physical mapping is done in parallel with the lookup into the L1 cache.  There is a trick that gets the effect of doing lookups on virtual addresses, without actually having to complete the virtual-physical mapping before the cache lookup (and thus avoiding the delay you are worried about).  See https://stackoverflow.com/q/19039280/781723 and https://software.intel.com/en-us/articles/how-memory-is-accessedfor details of how they make this work.

There is only one L1 cache per physical core.  The two virtual cores on the same physical core share the same L1 cache.  See, e.g., https://stackoverflow.com/q/27797424/781723 and https://stackoverflow.com/q/32979067/781723.

Different processes can be hyperthreaded on the same physical core.

In general, you can often find answers to these questions by reading the Intel reference manuals.