Difference between delayed branches and out-of-order execution I have been reading about instruction pipeline and I stumbled upon the term delayed branches. From what I have understood, delayed branches will keep the pipeline busy, by executing instructions, regardless of the outcome of the branch. This will avoid the usages of NOP instructions.

What I do not understand is, how is it it different than Out-of-order execution? In the following example, which I just made up:

1    MOV eax, 5
2    MOV ecx, 6
3    MOV ebx, 2
4    CMP eax, ecx
5    JG label1
6    SUB ecx, ebx
7    CALL someFunc
8 label1: 
9    SUB eax, ecx
10    CALL someOtherFunc


if I have understood delayed branches, before the decision is made, whether the jump to label1 will occur, the instructions on line 6 and 7 will be loaded in the pipeline. But isn't this exactly out-of-order execution?
I suppose you could view branch delay slots as a very special sort of out-of-order execution, but this isn't usually what we mean when we talk about out-of-order execution: generally, we're referring to a CPU that has a more general mechanism to detect when instructions can be re-ordered.  In addition, usually out-of-order execution takes care to avoid changing the semantics/behavior of the instructions.  In contrast, a branch delay slot does change the behavior of the instructions (because it affects whether the instruction after the branch is executed or not).