How can i compute tag-index-displacement bits of an address if cache size is not a power of two? How can i compute tag-index-displacement bits from an address if cache size is not a power of two? 
Intuitively, i would be inclined to think that i can not directly indicate which bits of the address are used to tag, index blocks and displacement. Instead, i think that i should do some conversion such that it appears that the sum of the bits of tag, index and displacement must be greater than the bits of address. This because for the index i need a number i of bits such that i ≥ log_2(number of blocks), for displacement i need a number d of bits such that d ≥ log_2(dimension of each block in bytes) if i suppose a byte addressable cache. Some suggestions?

As suggested by maverick1989, i explicate the data of the part of the exercise that give me trouble. I have a cache direct-mapped of 5256KB with 32B blocks. Assume a 32-bit addressing mode. This mean that i have (5256*1024)/32 = 168192 blocks. Thus, i need log_2(32)=5 bits of displacement to address a single byte in a block and log_2(168192)=17.3597... bits of index to address a block in the cache. Obviously i have to use 18 bits instead of 17.35.... Now i have some trouble to find the value of these 18 bits, given the address. And after that, what about tag bits?
One way is by having multiple cache banks, each of which is a power of two in size. For example, 3 banks of 16kB each. The first 3 (bank_num) bits can be used with one-hot encoding to decide which bank would need to be checked to access the requested data (or to write to). 

The rest of the cache access would proceed as usual (look up TLB to get tag bits, index into cache in parallel, etc.)

However, usually non-powers of two caches are not used because the IPC to cache size curve is such that it you find the sweet spot very close to a number that is a power of two (or you don't lose significantly in IPC by moving to a power of two).