How does the cache / memory know where to return results of read requests to? The pipeline of a modern processor has many stages that may issue read
requests to main memory, e.g. in fetching the next command or loading
some memory location into a register. How is the result of a read
request returned to the right pipeline stage, given that there are more than one possible recipients?
Since most CPUs access main memory via a cache hierarchy, the question
becomes: how does the L1 cache know which part of the pipeline to
return a result to?
I imagine that access to the L1 cache is queued, but each access
presumably needs a 'return address'. How is this typically handled?
Processors tend to have a LSU (= load-store unit), see [1, 2] for example, but those descriptions tend not to mention how  read data finds its recipient.


RISC-V Boom, The Load/Store Unit (LSU).

Arm, Load Store Unit (LSU).
Every machine instruction encodes the source and destination registers and/or memory locations. For memory location, some temporary buffer (register) within the processor is used. If the memory location happened to be in the cache, the stage of pipeline which depends on the content of memory location, stalls for few cycles.
Also, there are buffer registers between every pipeline stage, that stores the input for next stage and output of previous stage. If the processor is superscalar, i.e., multiple instructions can be in flight at a certain point of time, then multiple copies of buffers are maintained. Since the instruction can be executed Out-of-Order on superscalar processors, buffers like ROB (re-order buffers) are maintained for every hardware (SMT) threads. Put simply, multiple register sets which are copies of processor register sets are maintained within a processor.
In other words, Control unit that control the instruction execution cycles, appropriately route the content of memory location to marked registers. Registers are either specified by instruction code or determined by control unit itself.