Number of MUX required for Cache Mapping I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why?

I know that the size of each multiplexer has to be S to 1, where S is the number of sets in a k-way associative cache (For Direct Mapped, no. of sets = no. of lines). That's because we have to select one of the sets using the set offset (or index) bits.

I'm not being able to reason with the number of multiplexers required though.
A multiplexer can output only a single bit on output line.
So, to output one complete tag to the comparator ,

Number of multiplexers required = Number of bits in the tag. (say T)

If there are k lines in one set, then number of tags to output = K,

thus ,

number of multiplexers required = Number of lines in one set (K) x Number of bits in the tag(T).

TOTAL MUX REQUIRED = K*T