Question about a diagram of PWM detection I have this diagram in a book(taken from Slideshare for clarity) 
as described in the book PWM is put on the differential to obtain A(as starting of pulse) and B(as the end of pulse)
The A is used to start the integrator and B to stop it, at the same time A work as a clock for the sample and hold, to obtain the PAM signal of PWM
my question is, why A is used as the clock for the sample and hold?! I think B must be used for the clock to capture the amplitude! I don't understand this point!
From the diagrams, the integrator is reset to zero (sometimes this will be called "dumped", as in "integrate and dump") right after its value is sent to the hold.

The reason that I can see for doing this is that it appears that the leading edge of the PWM happens on a steady period, with the trailing edge varying to establish the width.  By sampling on the "A" pulse you insure that the timing of the PAM pulses is consistent; sampling on the "B" pulses would mean that the timing of the output would depend on the    amplitude; this would induce a nonlinearity.