How does the world's simplest sigma-delta DAC work? I have run into a simple delta-sigma (supposedly, where is the delta part?) DAC implementation utilizing an accumulator and then using the overflow bit as a modulated 1-bit output.
From https://www.fpga4fun.com/PWM_DAC_2.html:
module PWM(clk, PWM_in, PWM_out);
input clk;
input [7:0] PWM_in;
output PWM_out;

reg [8:0] PWM_accumulator;
always @(posedge clk) PWM_accumulator &lt;= PWM_accumulator[7:0] + PWM_in;

assign PWM_out = PWM_accumulator[8];
endmodule

I have implemented this and tested on an FPGA and compared it to a delta-sigma DAC from Xilinx app note: https://www.xilinx.com/support/documentation/application_notes/xapp154.pdf
module ds_modulator (
        output DACout,
        input [7:0] DACin,
        input Clk,
        input Resetn
);

reg DACout;
reg [9:0] DeltaAdder;
reg [9:0] SigmaAdder;
reg [9:0] SigmaLatch;
reg [9:0] DeltaB;

assign DeltaB = {SigmaLatch[9], SigmaLatch[9], 8'b0};
assign DeltaAdder = DACin + DeltaB;
assign SigmaAdder = DeltaAdder + SigmaLatch;

always @(posedge Clk, negedge Resetn) begin
    if (!Resetn) begin
            SigmaLatch &lt;= 10'b1111111111;
            DACout &lt;= 1'b0;
    end else begin
            SigmaLatch &lt;= SigmaAdder;
            DACout &lt;= SigmaLatch[9];
    end
end

endmodule

I am looking for as simple as possible delta-sigma DAC containing minimum logic while still maintaining reasonable performance. The very simple accumulator-overflow solution seems to work great. I understand it conceptually--high values will cause more frequent overflows and low values will cause less frequent overflows. Are there any disadvantages? I am using 120 MHz sampling frequency and generating sine waves between 100 kHz and 500 kHz through direct digital synthesis.
I am interested in this simple approach. Can someone shine light on why it works so well while being so simple? Also, if there is an official name for this approach or if there is some analysis somewhere online, it would be greatly appreciated if you can reference it in your reply.
I also found the simple accumulator-overflow DAC reference here (page 71): https://github.com/hamsternz/IntroToSpartanFPGABook/blob/master/IntroToSpartanFPGABook.pdf
Thank you.
This is just a first-order sigma delta DAC with the input as an unsigned binary number. The classical variant with a signed digital number is shown below where the MSB as the sign bit would subtract (Delta) from the input. In this signed variant, consider the input being a scaled digital number ranging from +/- Full Scale, and the feedback would either be +Full Scale or -Full Scale; in this case the accumulator can count up or down with a ramp rate based on the difference between the actual input value and +/-Full Scale with the output toggling when the accumulator output crosses midrange.
In comparison for the OP's case, the input is unsigned and the accumulator grows only in the positive direction with a ramp rate based on the difference between the input and +Full Scale. When the accumulator overflows, it is reset to 0 plus the overflow, which is essentially subtracting Full Scale (which is the Delta in this case).

This has all the drawbacks of any first order Sigma Delta: lower noise supression than a higher order architecture (-9 dB/octave) requiring a higher oversampling ratio to achieve a desired equivalent number of bits, and suffers from pattern noise leading to higher spurious content if the input is not changing.