simulating multipath via tap delays in FPGA I have a Xilinx FPGA running at 200MHz with an ADC and DAC on board.  I am taking a 2462MHz sine wave (pretending it is 802.11b chan 11), mixing it down to 40MHz putting it through my FPGA, mixing it back up and looking at it on a Spectrum Analyzer.

I have 4 taps (255 clock delays deep) to play with in my FPGA and am currently only using 2 of them.  I worked out the phase delay on each tap index by saying that the phase for a particular index (i) is phase=i*(2*pi)(2.462e9/200e6).  So index 1 has a phase of 0.13(2*pi) and index 250 has a phase of pi.

Armed with that, I put my signal through with no delay on the first tap, and then delayed the signal on my second tap by 250 clocks (so it should be 180 degrees out of phase).  Yet the signal doesn't disappear on the specAn.  I haven't found a tap that does make the signal cancel out, so that was where I was curious what I was doing wrong.

I was hoping there was something simple I am missing, as opposed to finding out it can't be done without implementing some sort of fractional delay filters (or something to that effect).
Perfect destructive interference is possible in theory, but very difficult to do in practice without feedback to dynamically adjust.  The reason for this is that there are three things you have to get just right to eliminate the tone: frequency, time (or equivalently, phase), and amplitude.  If you get any of those wrong there will still be a tone (or rather, two tones) left over.

Frequency  No matter what you do at the baseband level (i.e. in the FPGA), the frequency will not match if your upmixing does not exactly match your downmixing.

Time/Phase  This is a lot more complicated than you realize.  First, your phase-per-tap calculation requires that the sinusoid be exactly 2.462GHz and that your FPGA frequency be exactly 200MHz.  Neither one is.  You can never get an exact frequency, there is always some error and jitter.  If you take the derivative of the phase-per-tap with respect to the sinusoid frequency (2.462GHz), you will find that the phase per tap is very sensitive to sinusoid frequency errors.

You have also not taken into consideration the time delays through your ADC, DAC, and connectors, passive analog components, etc.  They all matter too.  Long story short, I would not try to figure out the correct delay, I would empirically see how the jammer's phase relates to the original sinusoid and adjust from there.  Yes, you will almost certainly have to use fractional delays.

Amplitude  Even if you get the frequency and phase right you will only be changing the tone's magnitude unless you match its amplitude.

I hope that see that you have taken on a very difficult task.  Since you are only trying to test simulated delays, I would find an easier way to do that.  I would look at using chirp signals, and then vary the delays to move the responding chirp in time.