Quantization error of SAR-ADCs My question is related to the quantization error and the functionality of SAR-ADCs. In general, the quantization error of an ADC is defined as +-0.5LSB. If this concept is correct a voltage that equals 1.75LSB, would produce 2LSB at the output of the ADC and a voltage that equals 1.25LSB would produce 1LSB at the output of the ADC. Based on the linked example transformation curve we got U_LSB = 1V/(2^3bit) = 0,125V, so an input voltage of 0,21875V (1.75LSB) would produce an output voltage of 0,250V and an input voltage of 0,15625V would produce an output voltage of 0,125V. So far so good. Let’s jump to the basic concept of an SAR-ADC.

An input voltage Vin is sampled by a sample-and-hold block. This sampled voltage is then compared by a comparator with a known voltage. This known voltage V_DAC is provided by the DAC that is supplied by a reference voltage Vref. The digital input for the DAC is generated by a SAR register as a digital word. This digital word depends on the result from the comparator. Initially the SAR begins with setting the MSB. After that the output voltage V_DAC of the ADC is compared with the input voltage Vin. If Vin is greater than V_DAC the MSB stays set. If Vin is less than V_DAC the MSB will be set to zero again. In the next step the SAR register sets the following bit and the comparison process of V_DAC and Vin goes on, until the LSB is reached.
My problem lies in this strict comparison process, which will never allow the output voltage of the ADC to be higher than the input voltage Vin. When I take the example from the first paragraph a SAR-ADC would give me 0,125V (1LSB) as an output voltage, as long as I don’t exceed 0,250V (2LSB). So an input voltage of 1.25LSB and 1.75LSB would both provide 1LSB output. This would mean the concept of +-0.5LSB quantization error wouldn’t be correct for SAR-ADCs and the ideal transformation steps would be shifted to the right for like 0.5ULSB (see diagram with red curve). The new quantization error would be max. -1LSB.

Is this thinking process correct or am I missing something? I can’t imagine that the general concept of quantization error does not match with the architecture of SAR-ADCs…
What the OP shows is the difference between truncation and rounding which in terms of error simply introduces an offset. They generate the same quantization noise spectrally; the standard deviation of the quantization noise (and equivalently noise power) is equivalents since DC offset is ignored in those computations. If there was concern with the offset error introduced (1/2 lsb) it can also easily be subtracted.
Further it should be clarified that DAC's and ADC's will have a finite DC offset regardless due to the analog portion of the electronics, this is often consistent with other DC offsets in the analog chain (consider the offset voltage between the negative and positive Op-amp terminal for example, or carrier leakage in zero-IF receivers), and when an actual issue (for a system where we are trying to measure a DC value) would be incorporated in an overall DC-offset removal algorithm with either calibration or cancellation loop) as part of all offsets combined. Since most DAC's and ADC's have a precision out to what there self-noise factors allow, the ENOB (equivalent number of bits) is often 1 to 2 bits worst than the stated precision (for example, a 12 bit converter may have an ENOB of 10.5 bits). For this reason it is often not even a concern if there is a DC offset introduced of 0.5 bits since that is well below the actual achieved precision overall. These details with regards to ENOB are clarified on ADC and DAC datasheets.
The OP asked for how the noise equivalence can be verified. It is obvious by inspection of the plots given that the only difference between the two is a static offset, but the equivalence can be computed simply enough for further verification by creating a floating point full scale  sine wave and then creating two quantization signals by both rounding and truncating the sine wave to the closest integer. Subtract the quantized fixed-point (integer) signal from the original floating point signal to get the quantization error alone. Then compute the standard deviation of each and they will be equivalent.
This chart I have demonstrates this graphically; specifically what is shown is generalized to a complex waveform (two ADC's with I and Q) but the concept is the same for a single ADC (real waveform), in that the rounded or truncated waveform is the sum of quantization noise with the higher precision waveform (such as floating point or more specifically samples of analog waveform prior quantization through rounding/truncation).

Further, if you use an incommensurate sine wave (choosing a frequency for the sine wave that isn't an integer sub-multiple of the sampling clock), you can also see through subsequent FFT and other statistical analysis how the quantization noise is well modeled as a uniform white noise distribution, and you can also confirm for either case (truncation or rounding) the formula used to estimate the SNR (the total power of the quantization noise floor relative to the full-scale sine wave) as given by:
$$SNR = 6.02 \text{dB/bit} + 1.76 \text{dB}$$
Which I detail further at this link:
What are advantages of having higher sampling rate of a signal?