FIR-Decimation and Low-pass filter (taps vs number of input points vs number of decimation stages) I am new to digital filters and trying to understand parameters behind them.

Scenario

I am trying to get DC value from signals sampled at 100kHz sampling rate. such high frequency is used due to system hardware limitations. A very sharp low-pass filter is to be used with cut-off frequency at 1Hz. The plan is to capture 10000 ponints first and then FIR-Decimate the income signal with several stages:


stage 1: decimation factor 10, FIR cutoff frequency 1/20 (128 taps), 100kHz->10kHz

income 10000 points, result 1000 points

stage 2: decimation factor 10, FIR cutoff frequency 1/20 (128 taps), 10kHz->1kHz

income 1000 points, result 100 points

stage 3: decimation factor 10, FIR cutoff frequency 1/20 (128 taps), 1kHz->100Hz

income 100 points, result 10 points

stage 4: decimation factor 10, FIR cutoff frequency 1/20 (128 taps), 100Hz->10Hz

income 10 points, result 1 point

Then a FIR with cut off frequency will be implemented with cutoff frequency 1/10. 


Questions


In the FIR decimation, the FIR cut-off frequency is always stricter than the decimation factor to avoid aliasing, is this design necessary?
What are the tradeoffs of choosing number of decimation stages and decimation factors?
At stage 4, there are only 10 income points. However, FIR has 64 taps... Would the one point result still be valid?
I'll answer your questions first:


You should look at the final decimation factor when designing the earlier filters. Hence, for the first stage you can have a cutoff frequency of 1Hz and stopband frequency of 100000/10 - 1 = 9999 Hz, since this is what is folded/aliased into your band of interest. You would actually prefer to have several stopbands 9999-10001, 19999-20001, 29999-30001, 39999-40001, and 49999-50000 Hz /you'll have to normalize yourself...). This would require a rather low order filters, which is nice since it runs at the highest sample rate. For the next stage, 999-1001, 1999-2001, and so on. Higher order (about ten times), but ten times lower sample rate. And so on.
Roughly more stages => fewer multiplications per input sample (given that you do a proper design as above). This holds up to some limit which can be quite straightforwardly determined by searching some combinations. 
After the first stage you will have $1000 + 2 \times 127$ samples (with 128 taps) and so on.


If you want to get the DC value you can just average the sequence. This is, apart from the possibly obvious observation that the DC level should be the average "offset" of the otherwise AC signal, also what the DC component of the DFT evaluates to.