Would it be feasible to implement the Sliding DFT on a digital signal processor? The Sliding DFT generates the spectrum for every input sample. Using the FFT, the spectrum is generated only after a certain number of samples (N) are obtained. It appears to me as though the cycles to perform the Sliding DFT would be much larger than the cycles required to do an FFT, to generate an N point DFT. Would it be recommended to use the Sliding DFT to generate an N point spectrum? The motivation for me to consider using the Sliding DFT to generate an N point spectrum is time resolution. 

Could anyone give me an idea of the challenges in implementing the Sliding DFT on a DSP?
The paper Sliding DFT control algorithm for three-phase active power filter implements a sliding a sliding DFT on a TMS320F2812 from Texas Instruments, and discusses some advantages, and An Enhanced Interpolated-Modulated Sliding DFT for High Reporting Rate PMUs does similar work on FPGA.  

From what I remember, you may have a look at the stability, see  The Sliding DFT.