CIC SINC3 Filter with unsigned Integrators I want to use the AD7401 Sigma delta modulator connected to my FPGA.

The Datasheet pg.15 has some demo verilog code which I understand alright except one thing:

They use unsigned integers for all of the registers. Which means especially for the Integrators(that only get 0 or 1 added) that they will definately overflow at some point.
The Integrators of CIC Filters are designed to overflow, but all the sources I found explicitly say that this requires twos complement to work properly.
Am I missing something, or why does the Decimator work with unsigned Integrators aswell(that dont wrap around "nicely").

Also am I right that switching all the registers to signed, and mapping the IO Input (0,1) -> to First Integrator(-1,1) will fix this and result in a signed output.
Addition and subtraction in 2's complement or unsigned is the same. The only difference is for overflows.

Assuming 16-bit arithmetic, overflows occur in unsigned addition when you go over 0xFFFF (65535). For example, if you add 1 to 0xFFFF you will wrap around to 0.

In 2's complement, the overflow will technically occur when you go over 0x7FFF (32767). If you add 1 to 0x7FFF you will wrap around to 0x8000 (-32768). 

Notice however that 0xFFFF + 0x0001 = 0x0000 and 0x7FFF + 0x001 = 0x8000 whether you're in 2's complement or unsigned. 

Therefore, it does not matter whether it is implemented in 2's complement or unsigned, the behaviour will be the same.