Choosing clock frequency and number of bits of an OFDM transceiver I want to implement an OFDM transceiver chip and my question is how to choose the clock frequency of the IFFT block? The number of output bits of the IFFT block? Also, how has the clock frequency and the number of output bits of the digital-to-analog converter (DAC) to be chosen?
The clock frequency $f_\mathrm{s}$ of the digital-to-analog converter (DAC) ultimately depends on the desired bitrate $R$ and some other parameters like guard interval length and number of bits per subcarrier. You can find the detailed formulas in a related question.

The speed of the IFFT block depends on $f_\mathrm{s}$ and the number of subcarriers $N_\mathrm{SC}$. It has to transfrom $f_\mathrm{S}/N_\mathrm{SC}$ sets of values each set consisting of $N_\mathrm{SC}$ complex numbers. What clock frequencies are involved in such an IFFT block depends on implementation details (mainly degree of parallelization) and cannot be answered in general.