Why do most digital pll's only use the positive zero crossing? I've been trying to get my head around digital plls from knowing nothing and seen that most examples only use the positive zero crossing, not the negative. I've tried to find the answer but the best i could find is a textbook that said "complications arise when using the negative zero crossing so this type of PLL isn't as common" without further explanation. 

The only reason that i can think of is that it would require more processing, but surely this would be worthwhile as you would be able to achieve faster lock times?
Getting accurate lock when using both edges or zero-crossings requires that the duty cycles of both the PLL local oscillator and the reference signal match and/or be as stable as the frequency.  If the duty cycles don't match when using both edges, then you would have to filter out some twice per cycle jitter which could well slow down lock speed.