Band-edge timing error detector, time accumulator im trying to implement a band-edge FLL and timing locked loop from this paper (https://www.researchgate.net/publication/261499267_Band_edge_filters_perform_non_data-aided_carrier_and_timing_synchronization_of_software_defined_radio_QAM_receivers).
The FLL works fine but i didnt understand the time accumulator and the interpolator.
Usually the interpolator would decimate the signal to 1 smpl/sym.
In this application it is just a variable delay filter?
How do i pick the optimal sample afterwards?
Thanks for your hints and answers. That helped me.
Ive got my code to work now. Its not fine tuned but here is my solution:
-As loop filter i use a PI Filter with a relatively low Ki.
The loop filter is just updated at a 1 Sps/Sym rate when the time accumulator gives an overflow.
-The time accumulator is a modulo interpolation controller
-The interpolator is a farrow structure for cubic interpolation
The IQ plot isn't stationary because the phase isn't locked. But i wont add a following pll anyways because it is a pi/4-DQPSK signal. A bit of phase shifting shouldn't bother me