Confusion with ADC conversion in MCP3424 I am learning about ADC MCP3422 Chip, because I want to use ADC Pi chip with my Raspberry Pi which is using MCP3424 ADCs, but I am having trouble understanding how the ADC calculation is done in the datasheet. 

(Data sheet links are available in the end)

From what I know of ADCs,

An ADC has a bit size.
and ADC tends to generate the total number of level based on the Reference Voltage. 

for example,

If there is a 3-bit ADC then and the Reference Voltage is 2volts, then,

2^3 = 8-bits

Now 2volts will be divided in 8 levels.

8/2 = 0.25volts (each level will represent 0.25 volts

and,

000 = 0 -&gt; 0.25 volts
001 = 0.25 -&gt; 0.50
010 = 0.50 -&gt; 0.75
011 = 0.75 -&gt; 1.00
100 = 1.00 -&gt; 1.25
101 = 1.25 -&gt; 1.50
110 = 1.50 -&gt; 1.75
111 = 1.75 -&gt; 2.00


Now, in case of MCP3424, I have so much confusions

The bit size is 18.
Reference voltage is 2.048volts

2^18 = 262144

Does that mean there will be 262144 levels ?

So, 2.048/262144 = 0.000007812volts
Does that mean each level will represent, 0.000007812 volts ? 

Also, the data sheet says,

The data rate for analogue to digital conversions is 3.75 (17 bit), 15 (15
bit), 60 (13 bit) or 240 (11 bit) samples per second. Data rate and
resolution can be configured within software using the I2C interface.


How the data rate is calculated here, and how come reducing the bit is increasing the Data Rate ?

MCP3424 Datasheet: www.pridopia.co.uk/pi-doc/mcp3424.pdf‎

ADC Pi Datasheet: http://www.abelectronics.co.uk/docs/stock/raspberrypi/adcpi2/Datasheet-ADCPiV2.pdf
If the conversion is 18-bit, there will be 262144 levels.

However, it seems to me that on the ADC Pi board, one of the differential inputs of each MCP3424 converter channel is grounded ; so this actually halve the range, and the first bit of a word read from the ADC will always be zero. That's why the ADC Pi datasheet reports half the resolutions compared to those published on the MCP3424 datasheet (17-bit, 15-bit, 13-bit, 11-bit).

There is a relationship between data rate and bit rate because the converter has a delta-sigma architecture. There is an internal conversion/integration clocked at a fixed 983040 Hz, and this conversion "budget" can be used at your whim to achieve different data rate / bit-rate ratios with:

$$s_r = \frac{983040}{2^{b_r}}$$

Intuitively (and this is a gross mis-simplification), reducing the sample rate gives the ADC more time to extract the finer details of each sample.