Open source ASIC design plans in Hardware Description Language (HDL) format? Are there any freely-available ("open source") ASIC design plans in, e.g., HDL or AHDL format(s)?
No. ASIC designs are all proprietary. This is controlled to the point where gaining information about the use for packaged chips is subject to a highly restrictive NDA. Some optimizations in use are non-public, and at any rate nobody is going to give away millions or tens of millions of dollars worth of NRE cost to their competitors. It seems unlikely that any of the older manufacturers will make their designs open source, as most have collapsed since selling their devices. The public manufacturers like BFL, HashFast, CoinTerra, ASICminer have all struggled to even exist after selling their devices due to the large NRE cost and difficult market for the devices. 

There are however some ancient FPGA miner designs written in VHDL which are open source. 

https://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-Miner

They aren't very much use to anyone for practical use but may give some idea of how hardware miners function. ASIC miners are significantly more efficient than FPGA miners even on the same process, especially now that some are moving to regulator-less supply rail chaining designs, so there is no realistic chance of this information being profitable for anybody at this point in time.