How is data stored into a frame buffer? I am an electronic engineer. I am trying to design (personal project) a 3D graphics hardware renderer. It shall only render wireframes at this stage, no filling and no shading, not even backface culling and whatever else we take for granted.

I understand that the most efficient method to draw a line on screen is via Bresenham's integer line drawing algorithm. Provided that I have implemented the algorithm in VHDL and am able to calculate all pixel values for the line one by one, how do I store them into the frame buffer?

E.g I have 100 lines, I can take say 10 lines and calculate their pixel values in parallel, longer lines will take longer to calculate. Every clock cycle I am able to get the next pixel value for the line, now if I just read 1 byte from memory, overwrite it with the line pixel data and write that byte back and do it for every pixel for every line, that 1 byte read-write method appears to be rather cumbersome and inefficient. So, do you know how it is worked out how to store data into the frame buffer efficiently or do people just use a very fast memory but the actual method is cumbersome and inefficient?
Real GPUs, like CPUs, have a cache hierarchy. So the rasterizer doesn't directly store to memory, but stores into a cache that eventually gets flushed to memory. 

Rasterization will usually have some spatial locality (it will generate writes to nearby pixels close together in time), so if those pixels are in the same cache line it will reduce the overall number of memory transactions. This is more effective for filled polygon rasterization than for lines, but even lines have some locality (especially if multiple nearby lines are being rasterized at once).

Another trick is to store the framebuffer in a tiled format instead of linearly left-to-right  and top-to-bottom. You'd pick a tile size such as 4×4 or 8×8 and store the pixels in each tile in a contiguous memory block, then make the whole framebuffer out of an array of tiles. This gives you locality in both dimensions, not just one, which improves cache performance. And tiling is easy to do in hardware, as it comes down to just swizzling the order of some X and Y address bits.