Build a 2-way universal logic processor using NAND logic gates A 2-way universal logic processor (2ULP) is a network of logic gates that takes two input wires A and B, as well as four other inputs L_, L_a, L_b, and L_ab, and produces a single output L(a, b) using the four L inputs as a truth table function:


The 2ULP returns L_ if A and B are both 0.
It returns L_a if A = 1 and B = 0.
It returns L_b if A = 0 and B = 1.
It returns L_ab if A and B are both 1.


For example, given the inputs L_ = 0, L_a = 1, L_b = 1, and L_ab = 0, then the output L(a, b) will be equal to A xor B.

Your task is to build a 2ULP using only NAND gates, using as few NAND gates as possible. To simplify things, you may use AND, OR, NOT, and XOR gates in your diagram, with the following corresponding scores:


NOT: 1
AND: 2
OR: 3
XOR: 4


Each of these scores corresponds to the number of NAND gates that it takes to construct the corresponding gate.

The logic circuit that uses the fewest NAND gates to produce a correct construction wins.
11 NANDs

Define the gate MUX (cost 4) as

MUX(P, Q, R) = (P NAND Q) NAND (NOT P NAND R)


with truth table

P Q R    (P NAND Q)   (NOT P NAND R)    MUX
0 0 0        1               1           0
0 0 1        1               0           1
0 1 0        1               1           0
0 1 1        1               0           1
1 0 0        1               1           0
1 0 1        1               1           0
1 1 0        0               1           1
1 1 1        0               1           1


Then this is the familiar ternary operator MUX(P, Q, R) = P ? Q : R

We simply have

2ULP = MUX(A, MUX(B, L_ab, L_a), MUX(B, L_b, L_))


for a cost 12, but there's a trivial one-gate saving by reusing the NOT B from the two inner MUXes.