Build an EBCDIC converter using NAND logic gates In this question, a mapping is defined between EBCDIC and a superset of ISO-8859-1.

Your task is to build a network of two-input NAND gates that will take eight inputs A1, A2, A4, ..., A128 representing an EBCDIC character and return eight outputs B1, B2, B4, ..., B128 that represent the corresponding "ISO-8859-1" character according to that mapping.

To simplify things, you may use AND, OR, NOT, and XOR gates in your diagram, with the following corresponding scores:


NOT: 1
AND: 2
OR: 3
XOR: 4


Each of these scores corresponds to the number of NAND gates that it takes to construct the corresponding gate.

The logic circuit that uses the fewest NAND gates to correctly implement all the above requirements wins.
727 Gates


How I did it:


turned the code page translation from wikipedia into an appropriately formatted truth table using Excel (15 minutes)
minimized the truth table using Espresso (5 minutes, 30 minutes on 1st iteration getting back into the saddle)
fed the minimized truth table into a schematic generator (1 minute)
iterated on 2&amp;3 until I got a reasonable answer (&lt;1 hour)
turned the schematic into an uploadable image (30 min, %$#@! Microsoft)


Here's the 100% NAND gate result:



If I was actually going to implement this, I'd drop the NAND-centric scoring. Building XOR gates out of NANDs is a big waste of transistors. Then I'd start worrying about UMC, fire up the FPGA design tools, maybe break out the HDL manuals, etc. Whew! I love software.

NB, for hobbyists interested in FPGAs, I'll recommend FPGA4fun.