Error Correcting Codes Post Quantum Finalists I have been looking into error-correcting codes in lattice, I am specifically hoping to find some information on hardware implementations for the NIST PQ PKE/KEM finalists (Saber, CRYSTALS-Kyber, NTRU).
I was reading this article on Timing Attacks on Error Correcting Codes in Post-Quantum Schemes and it mentions:

Kyber [31] and Saber [11] choose their parameters so that
their failure probability is small enough without need for ECC. NTRU [36] and
NTRU prime [6] even eliminate all decryption failures without using any ECC.
These schemes are therefore not vulnerable to side-channel analysis on ECC and
do not need the extra protection against these types of attacks.

I also understand the Lattice codes are also referred to as &quot;Sphere packing&quot;. Something I have read about conceptually, although I am not sure how it works practically.
However, I have also seen a few articles (such a this) that have been published recently about RLWE (Ring-Learning with Error) that tackle error correction and fault detection in that space, however none of the finalists use RLWE (as far as I can tell?)
My question is somewhat broad:
I want to investigate ECC/fault detection in hardware (or more accurately their lattice counterparts), specifically with one of the NIST finalists. Does anyone have any insights into this sector of Lattice Cryptography? I am very new to this field (I'm a student, looking to define a thesis topic) but any insights would be appreciated.
I want to investigate ECC/fault detection in hardware (or more accurately their lattice counterparts), specifically with one of the NIST finalists. Does anyone have any insights into this sector of Lattice Cryptography?

Actually, none on the NIST Lattice finalists (Kyber, NTRU, Saber) use error correction; for that matter, neither do the NIST Lattice alternates (Frodo, NTRUPrime).  Hence, that wouldn't be a promising avenue to research.  Several round 2 candidates (LAC, Round5, probably others) did, however they didn't make the cut.
As for fault detection, well, that's always a possible concern.  Glancing through the paper you cited, it would appear that they are concerned mostly about deterministic faults (e.g. a gate within the hardware breaks), and less about deliberate fault attacks (e.g. the attacker glitches the power supply at just the right time to cause a single value to be miscomputed).  You might consider investigating that (possibly starting with figuring out how out would perform a fault attack on the reference implementation, and using that to form a generalized concept about how a fault attack would work; then, you form a defense against that (assuming some limit on how powerful the attacker is; obviously, if he can fault things arbitrarily, he can make the hardware do anything...)

however none of the finalists use RLWE (as far as I can tell?)

No, but as ideal lattices, they aren't that different; of course, as a part of your thesis, you would need to explore them in detail...