Is timing analysis attack the same as cache timing attack? I am working on an essay on timing attacks on DES but then i have seen resources mostly about cache timing attacks. so is timing analysis attack the same as cache timing?
No, cache timing attack is not the same thing as timing attack. The former is a subcategory of the later.

Timing attacks are about inferring information about confidential data (key, plaintext..) from measurement of a computation's execution time. Obviously, timing attacks are only possible when the execution time varies for some reason, and that reason has some corelation with confidential data.

Cache timing attack is a special form of timing attack where the cause of the measured variations of the execution time is operation of some cache (typically, cache memory in a CPU, even though a branching cache would also fit).

For terminally bad implementations of DES, it is conceivable that other causes of execution time variation correlated with confidential data exist, beyond a cache. Examples:


permutations implemented using if .. then
logical operations implemented using short-circuit Booleans


However no competent DES implementer would do such thing (other than deliberately to enable timing attack), leaving cache (memory) timing attack as practically the only kind of timing attack worth academic interest in the case of DES implementations.

In domains other than DES implementations, there are several other causes of timing variation beyond caches, and timing attack worth investigations, including:


comparisons (including, of DES-based MACs) made using memcmp, strcmp, or similar method that stop on the first difference found
at what point verification fails in a sequence of verifications, e.g. timing variation of Bleichenbacher's attack on RSA with PKCS#1 v1.5 padding
influence of the bit pattern in the exponent (resp. multiplier) in modular exponentiation (resp. group multiplication)
variations of duration of the multiplication instruction of a CPU as a function of the bit size of one of the operand
variations of duration of the division instruction of a CPU
if a subtraction of modulus occurs, or not, in a modular reduction