What is a practical non-von Neumann architecture?
When I say "von Neumann architecture", I mean some hardware that is limited by the "von Neumann bottleneck" -- i.e., it has all data is funneled through some narrow data bus.

The non-von Neumann programming languages I bump into most often are VHDL and Verilog.
In VHDL and Verilog, by default, everything happens at the same time.
The programmer has to go to extra effort to make a series of events occur in sequential order.
That is very different from most other programming languages that imply a "instruction pointer" that, by default, executes at most one line of code at any one instant, and the programmer has to go to extra effort to get multiple things happening at the same time.

Some people would say that's a more natural default.
Lots of beginning programming students expect a "while( x > 0 ){...}" loop to exit the instant that x becomes equal to zero, and they are surprised to learn that the computer doesn't continously evaluate that condition.

Most people writing VHDL and Verilog code compile their programs onto FPGAs,
creating little blocks of activity that all run at full speed all the time.
Often such people set up a "pipeline" that reads data from the input pins, processes it through a series of blocks, the output pins of one block directly wired to the input pins of the next block, and the final block sends the result out the output pins.
It's reminiscent of the Unix pipeline, except that a new piece of data goes in and a new piece of data comes out on every clock cycle.

The input pins, the intermediate stages, and the output pins are all independent of each other -- you don't have to re-use a single data bus multiplexed between the various pieces of data.

You might also be interested in: Are there other computer architectures apart fom the von neumann /turing architectures?