Page Table Size in a 4 Level Hierarchical Page Table
The virtual addresses must be canonical, the top 16 bits are all copies of the 48th bit. Using a non-canonical address (in the sense of using it as an address) generates a #GP. See also, the manual, volume 3, chapters 3 and 4.

That is independent from the maximum physical address, which is not "canonical" in that way but just goes from 0 to some large number determined by MAXPHYADDR. You can find MAXPHYADDR using CPUID:80000008H, the lowest 8 bits in eax. It specifies the bit index in the page table entries (and some other places where you specify a physical address) at which the physical address stops and the reserved region begins. It's at least 36. It could be 48, but that wouldn't have anything to do with the limits on virtual addresses. The page table entry format allows it to go up to 52 (allowing you to address 4PB of RAM), but that hasn't happened yet. Intel seems to like 39 and 46, AMD seems to mostly use 48 now (they've used lower in the past) (source).