Maximum I/O Data Transfer if DMA is used
After reading more about it and reading the question again and again, I understood the logic


  The question says that on an average an instruction requires $5$
  $cycles$ and the CPU is busy $95$% of the time in executing those
  instructions. Out of these $5\ cycles$, $3\ cycles$ are needed for memory operations. During this time $DMA$ cannot access the memory. 


So only $2\ cycles$ are left for $DMA$ to use for 95% of the time.
For 95% time DMA uses
$$0.95 * 2\ cycles$$

For rest 5% time, CPU isn't executing instructions, so all cycles are available, so DMA uses
$$0.05 * 5\ cycles$$

Total cycles available for DMA
$$(0.05 * 5 + 0.95 * 2)\ cycles$$

In $1 second$, CPU can execute  $10^6$ instructions. So rate of transfer is 

$$
10^6 * (0.05 * 5 + 0.95 * 2) = 2.15 * 10^6 
$$