How does RAMDAC get notified about framebuffer write?
It probably depends on the architecture in general, but bear in mind that the phrase "the conversion can be done while writing to the framebuffer" is quite vague. The important point is that generating the video signal is a hard real-time operation, and the graphics hardware is designed to ensure that it always happens, even if someone is trying to write to the framebuffer at the same time.

There are a few ways this could be achieved. Some possibilities include:


Reads and writes to the framebuffer might always happen at different times. If you consider a square wave clock, for example, writes could happen on the leading edge of the clock signal and reads could happen on the trailing edge. This way, the result of the write is always available when the read occurs.
If there is contention between a read and a write, the write could stall or be buffered somewhere.
Reads from the framebuffer to generate the video signal could be buffered in a FIFO or something like that. If a write occurs, it could be allowed to happen as long as the FIFO hasn't drained.


It's possible that there could (as you say) be some kind of bypass circuitry, similar to forwarding logic in CPUs. The input to the RAMDAC could be a multiplexer, with one input directly from framebuffer RAM and another from somewhere else.

I think this is unlikely, because it seems excessive to implement extra circuitry just to ensure that a write that is happening right now appears on this frame. A buffer or stall seems much more likely.