Determining cycle time and and hold time in logic circuits
Well if someone is interested I have solved the question myself. 

First of all, it indeed is possible that $t_{hold} = t_{setup} + t_{pd-min}$.

And about the input time, it has to satisfy: $$t_{hold} \le t_{pd-min}(logic) + t_{input-valid-min}$$

since $t_{hold} = 8ns$ and $t_{pd-min}(Logic) = 10ns$ , even $t_{input-valid-min} = 0$ satisfies this.