Write Serialization for Cache Coherence in the presence of Store Buffers
From a coherence perspective, I think your example is coherent.  All processors believe that the write and read from A happened first, then the write and read from B happened later.

From a consistency standpoint you need to be more careful.  (Consistency is the global ordering of memory operations to different addresses.) The way consistency is handled in practice is that the store buffer sits before retirement, not after.  The store buffer acts as a little coherent cache for the speculative memory state.  A store instruction is not permitted to retire until its processor has acquired write ownership of the appropriate cache line.

The store buffer needs to be aware of all the coherence traffic reaching the cache.  If a speculative load gets its value from the store buffer, but the corresponding memory location is invalidated before the load retires, the load (and everything following it in the reorder-buffer) needs to be squashed and reexecuted.