MIPS pipeline: choosing between slowing down a stage and adding a new stage
Your answer is probably correct for an exam. 

In reality, adding a pipeline stage to MIPS is a major undertaking. The MIPS pipeline is very simple, that’s why it is taught in CS courses. Adding a pipeline stage adds a whole new level of complexity. Take an instruction sequence 

X = A+B
X = C+D
Z = X+Y


In the current pipeline design, Z can just about be made to pick up the correct X - when C+D is stored, it goes directly into the first input of X+Y. With an additional pipeline stage, the second X is nowhere near ready when the third instruction starts. So you must make that instruction wait. But only because X isn’t ready in time. Since you don’t want to always wait, you need to detect this and add logic for that. And then the question is how often does this happen. 

The alternative is that instructions using the second pipeline stage - and only those - stop all the other stages from progressing. So the timing would be the same as if this instruction was two instructions. In that case you could just make it two instructions.