Indirection in IAS computer
the book is describing low level machine language architecture associated with the CPU &amp; what is also known as "microcode". it would be possible to design opcodes that use multiple registers (that does occur in some mostly uncommon cases) but most opcodes generally refer to one register or a memory location, unless its a transfer between two registers. the register number is usually encoded into the opcode in binary. that is, registers serve as a sort of small intermediate "hub" or even a small "cache" between memory and the CPU. 

if one had opcodes that refer to multiple registers it quickly leads to a combinatorial explosion where the opcodes become very numerous. even a 2-way register opcode scheme takes roughly $c \cdot r^2$ encodings where $r$ is the number of registers. a 3-way register operation would require $c \cdot r^3$ etc... another scheme is to limit multiway register operations to just a few "privileged" registers, not the full set.

a good case study or example might be the 6502 CPU that has an accumulator, an auxiliary X and Y register, and some limited operations to move between them. a full/general level of register interchange is then supported by stringing several/multiple register manipulation opcodes together.