In which pipeline stage are exceptions detected?
Both.

I'll assume you are talking about pipelined machine organizations with


out-of-order completion (different instructions take different amounts of time to produce their results)
precise interrupts (instructions appear to produce their effects in-order).


An exception might be detected in the instruction fetch stage (if, for example, there is a page fault when trying to access the instruction memory), in the execution stage (like in your example of an overflow) or, for memory instructions, for a page fault when trying to access the data memory.

One important question is what to do with the other instructions in the pipeline.  Instructions that were fetched before the excepting instruction should appear to commit their changes before the interrupt, and instructions that were fetched after the excepting instruction should get cancelled somehow before they commit any changes at all.

Typically you deal with this by having some form of commit stage (called the "write-back" stage in the 5-stage pipeline that is often used in computer organization courses.)  Instructions commit in order, even if they "complete" their execution out-of-order.  At the time the excepting instruction arrives at the commit stage all the previous in-order instructions will have committed, but their will be some number of instructions that were fetched after the excepting instruction still in the pipeline.  Those following instructions need to be cancelled, and this is often done by keeping a cancelled bit with each instruction as it flows down the pipeline.  The commit stage just doesn't write-back the results of any cancelled instructions.

The other question that needs to be answered is when do you redirect the fetch unit to the exception handler.  It would be simplest to signal the fetch unit only from the commit stage, but for longer pipelines that can cause an extremely long bubble between the exception being detected and the exception handler starting to fetch.  In that case you might redirect the fetch unit when you detect the exception.  The Pentium 4 did it this way, for example.