D flip flop : How does it work in depth
Here's a big hint, and then I'll let you work out the rest for yourself. Because we want cs.SE to be a collection of questions and answers, please post your solution as an answer.

Edge-triggered D flip flops are generally done using the "two RS flip flop" design that you have. You got that right. Reading from left to right, I'm going to call these RS flip flops "stage 1" and "stage 2".

Before the transition "happens", stage 1 should load the data. The effect of the transition is to make stage 1 hold its data and make stage 2 load its data from the output of stage 1.

So to create a D flip flop that is triggered on the rising edge:


When the clock is low, stage 1 should load its data and stage 2 should hold its data.
When the the clock is high, and stage 2 should load its data and stage 1 should hold its data.


The effect of this is that the transition from low to high shifts the result from stage 1 to stage 2.

Conversely, to create a D flip flop that is triggered on the falling edge, stage 1 should load when the clock is high, and stage 2 should load when the clock is low.

Now can you implement that?

Incidentally, I don't understand your teacher's requirement "we couldn't use any gate on clock". When you realise digital circuits in CMOS or NMOS, clock fanout is a large practical issue. Besides, you only get inverting gates, so putting gates on clock lines is normal and expected.

Nonetheless, perhaps they meant you to use de Morgan's laws to reduce the gate count?