Relation between size of address bus and memory size; memory Segmentation in 8086
That's the beauty of cisc machines.
For starters as you can see address bus is 20bit wide but resisters are 16bit wide, so microprocessor will process 16bit at a time.

Now let's answer your questions :

1) Address size has nothing to do with architecture size. You can have instructions that can map 64bit or 128 bit address space in instructions. For example mov   can be hard coded in hardware itself to fetch next addressing scheme as required which eliminates requirements of same size bus and resistors. The same mov command with proper bit masking can use address of special resistors instead of memory spaces. It drills down to the choice of system architecture. Thus the name complex instruction set.
It goes beyond this simple explanation, but to give an idea, instructions are flexible enough to understand addressing schemes.

So answer is no when you are storing resistor data into memory, it refers to 16bit wide data bus. It is still storing data as usual way. But micro processor can operate on 8bit, 16bit or divide 32bit operation in sub operations as well depending on instruction. 

It uses segments to divide memory into  usable chunks which is mapped by combing 16bit address scheme but by shifting it to 4bit and adding offset bits to get actual physical address. Modern cpu uses dedicated hardware called memory management unit having multiple operating mode of direct memory access and IO access as well.

Here's the quote :


  Rather than concatenating the segment register with the address
  register, as in most processors whose address space exceeds their
  register size, the 8086 shifts the 16-bit segment only four bits left
  before adding it to the 16-bit offset (16×segment + offset), therefore
  producing a 20-bit external (or effective or physical) address from
  the 32-bit segment:offset pair. As a result, each external address can
  be referred to by 212 = 4096 different segment:offset pairs.


2) Answer to this question is linked on how 8086 translates address to segments. As you can see it doesn't add offsets immediately but directly uses address schemes to map physical address without adding extra hardware. It's a clever way of addressing and doesn't require offset as it's already mapped to stored address space which is kind of 32bit wide when you add address+offset, enough to store 4GB space which you can see in 80386 models. Making it backward compatible as well.