Byte/word addressing in cache
Huh? Let's modernise what you are saying a bit. Typical cache size nowadays is 64 bytes. So here is what a processor will typically do for such a cache: 

Step 1a: Take the number of bytes accessed by the instruction, and the lowest six bits of the address, and determine whether the data is all within one cache line or straddles over two cache lines. (For example two consecutive bytes will in most cases be in one cache line, except if the lowest six bits are equal to 63. 16 consecutive bytes will often be in one cache line, except if the lowest six bits are greater than 48).

Step 1b: Use the other bits to determine the cache line where the data might be stored. If the cache has more than one way (say four way cache) this actually determines four possible cache lines. 

Step 1c: Take the whole of the address to determine which of the possible ways contains the data. Also detect if the data is in the cache at all, and if not, start loading the data into cache which is much too complicated to explain here. When done, start all over again.

Steps 1a to 1c are performed in parallel if at all possible. Once the cache line containing the data, or the first part of the data is found, take the lowest six bits of the address, combine with the data size, and transfer as many bytes as needed and available. 

If not all bytes needed are in the same cache line, repeat everything to get the remaining bytes. 

Where your ideas went wrong: We don't set any bits of the address to zero, and we don't shift anything. We just take the parts of the address that are needed for every operation. To determine the cache line, you don't shift the address, you just take the address bits that are needed and you don't take the bits that are not needed. Since the lowest two bits are never zeroed, there is no problem accessing a byte anywhere in a cache line.