How do you go about designing a vector processor architecture for the sum of matrix products?
From talking to the OP, algorithms that handle parallel matrix multiplication are apparently acceptable answers. Matrix multiplication and parallel algorithms for it are a highly studied problem in CS partly because of its widespread application e.g. in scientific computing. There are other ways to parallelize the problem given in the question, e.g. an obvious "map-reduce" that maps the separate matrices to separate processors and the reduce step does the addition.


There is some discussion on Wikipedia, Matrix multiplication, "Communication-avoiding and distributed algorithms." 
Here is a somewhat recent survey of performance of standard algorithms. 
Performance Analysis and Evaluation of Parallel Matrix Multiplication Algorithms
Ziad A.A. Alqadi, Musbah Aqel, and Ibrahiem M. M. El Emary.
The standard (scientific computing) matrix libraries BLAS and LAPACK have standard parallel matrix multiplication algorithms built in.
The problem as stated is also readily computed by a GPU e.g. via standard CUDA programming. This subject is increasingly studied in undergraduate classes e.g. at CalTech.


Note also the new "scicomp" stackexchange for questions on scientific computing.