Importance of Frequency vs CAS Latency in memory performance
The presented timing for first word assumes the row is currently open (i.e., is only CAS latency, in nanoseconds). For random accesses, RAS latency is added; if another row in the bank is still active, PRECHARGE latency (to write back the active row before opening the desired row) is added. RAS and PRECHARGE latencies are typically proportional to CAS latency.

Given that cache misses add both cache probing delay and various delays in the on-chip network (including queuing delay) and at the memory controller (e.g., scheduling delay), the delay of the DRAM chip itself are a little less significant. (Adding buffering to support larger capacity, e.g., load-reduced DIMMs, further increases latency.)

(There are additional constraints on DRAM activity, so some access patterns may be unexpectedly slow compared to the simple model of PRECHARGE, RAS, CAS.)

Frequency controls peak bandwidth, which is more important for some workloads. Frequency also determines the occupancy of a DRAM data channel, so a higher frequency DRAM can satisfy more requests per second as long as they are "well-behaved" (only accessing different rows in the same bank will be slow), reducing queuing delays.