Where do these DRAM row/column calculations come from?
The first value describing the DRAM is the number of data-interface-sized "chunks" it contains and the second value is the width of the data interface in bits, i.e., bits per "chunk".  A 16x1 DRAM would only have 16 bits addressable at 1-bit granularity, with four rows and four columns allowing a minimization of address pins.  A 16x4 DRAM would have 64 bits addressable at 4-bit granularity (and with 16 addressable units a 4 row and 4 column arrangement would minimize address pins).