Vector clock :why Singhal Kshemkalyani differential technique require FIFO for message passing?
All it's saying is that the messages between two processes need to be received in the order they are sent. If I'm going to send only differences between the previous message, we both better agree on what "the previous message" is.

For example, if I send "increment the first and second component" and then "increment the first and third component" but you receive them in the opposite order, you are likely to make form incorrect assumptions about how these messages relate to messages you're receiving from other processes. The correct intermediate state will have a vector clock that looks like $(1,1,0)$ but the one you'd reconstruct from the out of order messages is $(1,0,1)$. A message from another process with vector clock $(2,0,1)$ might then look like its strictly after the out-of-order message when, in fact, it is concurrent with it.