Load and Store Data hazard problem in 5-stages pipeline
Assuming the stages are IF, ID, EX, MEM and WB, I believe the Load instruction cannot be carried out until the value has been written back in the first instruction i.e the WB stage.

This is what happens in the ID stage (from Hennessey-Patterson, Computer Architecture - A Quantitative Approach 4 ed.):


  Decode the instruction and read the registers corresponding to register source specifiers from the register file. 


Since we have to read the registers in the ID stage, this cannot be done until the WB stage of the previous instruction has been completed as otherwise, it would lead to reading an incorrect value.

EDIT: On further notice, I've realised this might be incorrect. I wrote this answer under the assumption that the Store instruction passes through all the five pipeline stages. However, here, it is mentioned that:


  The store instruction stores to memory, so the "write" is performed inside MA.


So it won't have to wait till the WB stage, it can read the value after the MEM stage of the previous instruction. 

That being said, more details about the instruction set would be helpful and how exactly are Load and Store defined would be helpful.