Mapping several memories to one address space
Each RAM chip (e.g., DIMM module) has its own range of physical addresses.  The memory controller connects the CPU to the RAM chips via a memory bus.

In its simplest form, each read or write operation sent on the memory bus contains some bits that select which RAM chip it applies to, and some bits that indicate the address to be selected within that RAM chip.  So, physical memory is partitioned among the RAM chips.  The memory controller is responsible for managing this partition and determining, based on the physical address, which RAM chip to select (what to write on the chip select bits of the memory bus).  The specific architectural details have evolved over time and may differ from platform to platform.

Physical addresses are normally not visible to user-level applications.  Instead, a virtual memory subsystem (page tables) are used to translate from virtual addresses to physical addresses.  The user-level application seems virtual addresses.  There need not be any simple way that ranges of virtual memory addresses correspond to RAM chips.