How on-chip multithreading prevents cache misses from stalling a processor pipeline?
It's called "out of order execution". 

When one instruction stalls, that doesn't mean the whole pipeline stalls. All instructions that don't depend on this one instruction can continue. Sometimes there is enough work to do even with a single thread to keep all the execution units busy even if one instruction stalls for 40 cycles. But with hyperthreading, you have a whole thread whose instructions are all independent of the stalling instruction, and which can all continue executing.