Instruction level parallelism
Instruction-level parallelism, data-level parallelism, loop-level parallelism, and task-level parallelism are not well defined terms.  The definable concept is parallelism.  Two operations can run simultaneously (or "in parallel") when the portions of the state they write are non-overlapping, and when the portion of the state written by each operation does not overlap with any of the state read by the other operation.

So two different instructions can run in parallel when the registers and memory they read and write don't overlap.  The sub-operations of a SIMD instruction can run in parallel because they are defined to only perform sub-operations that each read or write different portions of a vector register or cache line.

I like to say


  parallelism is as parallelism does


and what parallelism does is run multiple operations simultaneously.

The benefit of SIMD instructions, over just using 4 or 8 or N individual instructions that perform the same sub-operations, is that the fetch, decode, renaming, and scheduling units of the processor don't need to do as much work to exploit the parallelism between the sub-operations.