Data hazard after in load word after addi
THe answers are correct.
There is a data hazard when the information stored in the "regular" location (generally a data reg) is incorrect with respect to the program flow.

Here information copied in the ID stage at line 2 will be the previous value of $t1, as the new one will be copied at the end of WB stage of instruction 1 (and hence at the end of MEM stage of instr 2).

Forwarding means discarding the regular information and replacing it by the new (and correct value).
It can be done

1/ as soon as the new value is available in the processor. Lets call t_a this time 

2/ up to the last time that this information is required (because it will be transformed by the ALU, written to the mem, etc). Lets call t_u this instant

If t_a &lt;= t_u, simple forwarding can be done. Otherwise one or more stalls are required.

Lets look at the code

1 addi $t1,$zero,0x30
2 lw $t2,0($t1)


Say Stage IF of instr 1 is t1, ID t2, etc

1 the new value of $t1 will be available at the end of stage WB (t5)

2 the value of $t1 is read at the start of ID stage (t3)

There is a data hazard.

When is the information associated with $t1 available ? After EX stage of 1. So t_a=t3

When is the last time that this information is required by instruction 2 ? Just before the adresse (0+$t1) is computed by the ALU. I.e. t_u=t4

There is no need of any stall. The value read in $t1 register is just discarded and replaced by the one in the ppline register.

Consider now instructions 2 and 3. 

2 lw $t2,0($t1)  
3 sw $t2,0xff18($zero) 


There is a hasard as  $t2 is written at the end of WB stage of inst 2 (t6) and read at the beginning of ID stage of inst 3 (t4).

When if the information associated with $t2 available in the processor. At the end of MEM of instr 2 it is written in some ppline reg of the proc (t5=t_a).

When is this information required ? Just before writing to the memory by inst 3. After it is too late. That is at the start of MEM stage of inst 3 t6=t_u.

Again a simple forward can solve the problem.

(note that if instr 3 had been
sw $t5,0xff18($t2)
the situation would have been different. $t2 would have been required for the address computation (start of EX stage of inst 3 at t5), that is before its production (end of MEM of instr 2 t5), and a stall would have been required over the forwarding.)