Computer Architecture, cache hit and misses
You may wish to ask your TA/Prof. what they mean by "0.5% global miss rate". The way I read it is the following:


  Out of $x$ accesses to the L2 cache, $0.005x$ accesses are a miss.


This interpretation makes more sense than assuming the miss rate is out of all the store/load instruction.

So each miss of the L1 cache becomes an access to the L2 cache, and out of these, 0.5% are a miss at the L2 cache. From here, it seems you can fill out the details by yourself, building on your own attempts.