Memory Consistency vs Cache Coherence
As you pointed out, coherence is a property of an individual memory location while consistency refers to the order of accesses to all memory locations.  Sequential consistency is a strictly stronger property than coherence.  That is: every system that is sequentially consistent is also coherent at every memory location.  The opposite is not true, a memory that is coherent at every location is not necessarily sequentially consistent.  In fact, there are many real cache-coherent multiprocessors where the memory model is only weakly consistent (there are cases where different processors observe accesses to different locations happen in different orders.)

Proof of sequentially consistent implies coherent:

Given any trace from a sequentially consistent system, by definition that trace must have a total order that is agreed on by every processor in the system.  Now look at the accesses just to location $x$ in that trace.  Because a total order is transitive, the accesses just to location $x$ also have a total order on them that is agreed on by every processor in the system.  Thus all memory locations are coherent.

The reverse doesn't work out.  Consider two coherent memory locations $x$ and $y$ with just a single access to each $x_0$ and $y_0$.  All the processors agree on the order of accesses to location $x$ and all the processors agree on the total order of accesses to location $y$, but some processors may observe the order $x \rightarrow y$, while others may observe the order $y \rightarrow x$.  So coherence doesn't imply sequential consistency.

This can lead to surprising results.  For example

initially A=B=0
process 1               process 2
store A := 1            load B (gets 1)
store B := 1            load A (gets 0) 


This trace is coherent: 


for A the order is: proc2 loads A(gets 0), proc1 stores A:=1
for B the order is: proc1 stores B:=1, proc2 loads B(gets 1)


But it is not consistent! Since if proc2 load B returns 1, then proc1 store A := 1 already happened and proc2 load A should also return 1.