Understanding non-faulting and faulting software prefetches
A faulting prefetch is one which (as gnasher729's answer notes) generates any translation (e.g., invalid page table entry), permission, or other fault (e.g., ECC failure, data watchpoint match) associated with the access. Such a prefetch acts as if the memory location was accessed normally. For data accesses such a prefetch can be provided by software on architectures that lack prefetch instructions. (For instruction accesses, a return operation would need to be placed in the cache block reducing the amount of useful code that would fit in the block.)

By acting as a normal access, a faulting prefetch effectively guarantees that the chunk of memory will be cached (a non-faulting prefetch may be dropped under high memory use or even a TLB miss) and that its address translation will be cached. This behavior may be preferred if the address is known to be accessed in the near future, especially if a timing critical section is about to be entered.

In some RISC ISAs, a faulting data read prefetch could be provided by a simple load to the zero register. Other ISAs could preform a normal load at the cost of temporary use of a register.

Non-faulting prefetches are purely hints to hardware, allowing hardware to drop the access if it is perceived as too expensive. By avoiding faults, such prefetches can be used without concern about whether the address is valid; prefetching from a null pointer or past the end of an array is safe.
A non-faulting prefetch is purely speculative. (Some ISAs provide support for speculative, non-faulting loads. In such an ISA, non-faulting prefetches could be implemented using such a load. Since the speculative load value may be used, hardware will typically treat such as an actual access and merely suppress any exceptions.)