What is the theoretical speedup with pipeline system over a nonpipelined system?
The total time to compute $n$ tasks with no pipelining is $nT$ (the top of your fraction).  The total time to compute $n$ tasks with a pipeline $k$ stages deep, and a clock cycle time of $t$ is $nt$ (to produce the results once the first task reaches the last pipeline stage) + $(k-1)t$ to get the first task from the beginning of the pipeline to the last stage.  This is the $(k + n - 1)t$ in the bottom of your fraction.

The part you are missing is that $kt$ (the time for each task to get from beginning to end of the pipeline) must be larger than $T$.  This is because in the perfect case you would divide the circuit of delay $T$ into $k$ exactly equal segment, but then you would need to insert a register between each segment and the next, which will add delay.

So replace $t$ with $T/k$ in your fraction and take the limit as $k\rightarrow\infty$ and you will have your answer.

More interesting is to replace $t$ with $T/k + r$ where $r$ is the  constant extra register delay that you need to add between stages, take the derivative of your fraction with respect to $k$ and set it equal to 0 and solve