How does the cache / memory know where to return results of read requests to?
Every machine instruction encodes the source and destination registers and/or memory locations. For memory location, some temporary buffer (register) within the processor is used. If the memory location happened to be in the cache, the stage of pipeline which depends on the content of memory location, stalls for few cycles.
Also, there are buffer registers between every pipeline stage, that stores the input for next stage and output of previous stage. If the processor is superscalar, i.e., multiple instructions can be in flight at a certain point of time, then multiple copies of buffers are maintained. Since the instruction can be executed Out-of-Order on superscalar processors, buffers like ROB (re-order buffers) are maintained for every hardware (SMT) threads. Put simply, multiple register sets which are copies of processor register sets are maintained within a processor.
In other words, Control unit that control the instruction execution cycles, appropriately route the content of memory location to marked registers. Registers are either specified by instruction code or determined by control unit itself.