How to calculate a direct mapped chace capacity with tag and valid bits?
Unless specified otherwise, addresses are always byte adresses (and with a cache with 1B/block, any other choice would not make sense)

Ram size is relevant as it indicates addresse width.

Cache blocs are 1 byte -> offset=0b (offset indicates byte position in block and only 1 possible position).

RAM is 2kB (2^11) -> address is 11 bits

Adress width=Tag with+Index width+Offset width

Tag=7b, Address=11b, Offset=0b -> index=4b

Cache is direct Mapped -> Cache size for data=number of blocks * block size = 2^(index size)*(Block size)

-> Cache Size (data) = 2^4*1B=16B

Block associated with Tag(7b) + 1 valid bit -> 1 extra B for control per block

Total cache size = 16 block each with 1B data and 1B control -> 32B