Is it reasonable to model row buffers in DRAM corresponding to the same bank ID as one big row buffer?
You can look at how one of the existing DRAM simulators work. Consider, for example, Ramulator, which is a popular academic DRAM simulator. Ramulator Models main memory as a tree of nodes, where the root node represents a memory channel and lower nodes represent ranks, bank groups (supported in DDR4), banks, rows, and columns. For the DRR4 and DRR3 protocols, these levels are defined in the source code here and here, respectively. Therefore, the physical row buffer of each chip of the same bank are actually treated as a single row buffer whose state is maintained using a single value.