How does hardware interrupt work on a physical layer
The CPU has specific pins on the outside to detect hardware interrupts.  

Take for instance the 6502 used in the Apple II and c64 it has two interrupt pins:
IRQ on pin 4 and  (can be ignored)
NMI on pin 6  (cannot be ignored)  

If the signal on pin 6 falls from high voltage to low voltage the CPU will perform a call to the non-maskable-interrupt handler.
It will read the contents of address $FFFE and jump to the 16-bit location contained in that address.
After it's done it will return to where execution was before and resume operation as if nothing happened.  

In the interrupt handler the CPU will query its peripherals to find out which one generated the interrupt.
Usually a specific chip is connected to the interrupt pin and that chip can be queried using an INput/OUTput instruction to get the relevant info quickly. On the c64 the CIA 6526 was used.  


  Are there specific areas of the CPU that contain addresses for handlers registered by the OS?  


You set up the CPU so that it calls a predetermined address when it receives an interrupt.
In early CPU's this address has hardcoded in the chip. In newer chips the system kernel can change the interrupt address using a privileged instruction.  

On modern processors this works the same but things are complicated because everything is virtualised.