When the stall is actually going to happen?
As part of the instruction decode phase, the operands are fetched for the instruction. In a very naive pipeline implementation, the operands for read  will only be visible after the write instruction has written back its changes to the internal registers (so the last stage).
To prevent such long stalls, a CPU can apply tricks like forwarding the store to the load as soon as the value is determined instead of needing to wait for the write to the registers.
Check out the following for a more detailed answer:
https://youtu.be/EL8uqzSsg_Q?t=433