About the connection of pipelined execution and latency
In a processor that would nowadays be considered simple, you need two numbers for an instruction: what is the total execution time (for example 4 for load) and how long you need to wait before another independent operation can be issued - it seems that someone assumed 1 cycle between instructions for load. A different processor might only allow a load every two cycles, and your numbers would be totally different.
The PowerPC 603 was interesting in that a multiplication took 4 cycles, but it couldn’t start four multiplications in a row, so your multiplications would have started at cycles 4, 5, 6, 8, 9, 10, 12 etc.
Things get more interesting when you have multiple independent execution units; like you assume at least three units capable of load, store, and multiplication. And more interesting if you have limits decoding instructions, dispatching to execution units etc.