lw and sw hazards example MIPS
The hazard stems from the fact that the lw instruction updates register \$r0 at the 5th stage of the pipe (write-back) while the sw and the add instructions require the updated data at the 2nd stage of the pipe (decode/read).

Putting everything on a single time line (assuming the lw execution begins at time $t=1$), the correct value of \$r0 will be available not before $t=4$ and the other instructions must be stalled (at the decoding phase) until this data is available. After $t=4$ a forwarding unit can be used to forward the data to the correct place, e.g., to the execution stage for the sw or to the decoding stage for the add (if needed).