How to show potential pipeline hazards
A data hazard occurs whenever you access a register after updating it. Due to the pipeline structure updating the register happens after it is being accessed by the successive instruction. That is, when accessed, the register holds the old value rather than the updated value.

For instance:

1. R2 = R1 + 1    // update R2
2. R3 = R2 + X    // access R2


Instruction 1 updates R2 at S4 (see the table). Instruction 2 reads R2 at S2. But at this time the new value of R2 is not stored yet -- it will be stored only on the next clock. This problem is the hazard.