Loading a word from a byte addressed cache
For nearly all major architectures, a cache line is 64 bytes wide. All memory transactions from your L1 cache all the way out to DRAM will use 64 byte lines. The only place where the byte address-ability comes into play is between the processor core and the L1 cache. It is common for L1 RAMs to be built with byte enables or some from of specification to a subset of the bytes from a 64 byte cache line.

Let's assume the interface from the processor to the L1 cache yields an address and a width (number of bytes). Suppose you want address 0xF002 and you want 4 bytes. The cache line is address 0xF000 (0xF002 &amp; ~0x003f), the offset within the cache line is 0x0002 (0xF002 &amp; 0x003f), and because you specified a 4 byte width you'd receive bytes 0xF002, 0xF003, 0xF004, and 0xF005.

Most processor/cache interfaces will only support common widths (1, 2, 4, 8 bytes), and basic architectures will force the addresses to be aligned (i.e., a 2 byte read can't start at an odd address). More advanced architectures will handle the misalignment in hardware (see MIPS unaligned load/store for a bad implementation). x86 allows unaligned loads and stores. Here is a short list of reasons unaligned memory accesses are bad:


  Why unaligned access is bad
  
  The effects of performing an unaligned memory access vary from
  architecture to architecture. It would be easy to write a whole
  document on the differences here; a summary of the common scenarios is
  presented below:
  
  
  Some architectures are able to perform unaligned memory accesses    transparently, but there is usually a significant performance cost.
  Some architectures raise processor exceptions when unaligned accesses    happen. The exception handler is able to correct the
  unaligned access,    at significant cost to performance.
  Some architectures raise processor exceptions when unaligned accesses    happen, but the exceptions do not contain enough
  information for the    unaligned access to be corrected.
  Some architectures are not capable of unaligned memory access, but will    silently perform a different memory access to the one that was
  requested,    resulting in a subtle code bug that is hard to detect!
  
  
  It should be obvious from the above that if your code causes unaligned
  memory accesses to happen, your code will not work correctly on
  certain platforms and will cause performance problems on others.
  from: https://www.kernel.org/doc/Documentation/unaligned-memory-access.txt