Architecture - calculating miss penalty
Let us assume/understand that "memory access latency" means the "memory access latency" to access the cache when there is a hit. (It appears reasonable to just say "memory access latency" since the latency to access the cache might be (almost) the same whether there is  hit or miss.) Otherwise, there is no solution to this problem or we have to introduce other less straightforward assumptions.

Once we have made that assumption/understanding, the miss penalty is easy to solve.

Miss Penalty = (AMAT - Hit time) / Miss Rate 
             = (AMAT - hit-rate * memory-access-latency) / Miss Rate 
             = (80 - (1 - 0.4) * 60 ) / 0.4
             = 110


However, it is rather unnatural to interpret "memory access latency" as referring to accessing the cache since by default, "memory" refers to the main memory while the cache memory, L1 memory and L2 memory are referred as cache. 

Another plausible situation is the last given condition is, for example, memory access latency = 160 instead of memory access latency = 60. Then we can understand "memory access latency" as, very naturally, the latency to access the main memory when there is a cache miss. I put an emphasis because it is reasonable to assume there is no way to skip the cache (in this kind of exercises). Note that this natural interpretation cannot make much sense originally when the value is 60, which is less than the given "AVG Memory Access Time", 80. I will leave the question as an exercise for you if the last condition is indeed changed to memory access latency when there is miss = 160. 

(Yet another way to resolve the situation is to change AVG Memory Access Time = 80 to, for example, AVG Memory Access Time = 30.)

You may check my answer for related information.