Depth of a pipeline in a CPU's architecture
I think that depth is a measure of the overlapping of instructions while number of stages is a hardware constant. When you increase the number of stages, you usually make the CPU faster but it is with dimishing margin. See Almdahl's law about this and the book "Computer Organization and Design" by Pattersson and Hennesay. 



The more stages, the larger the depth but it is stated that there can be optimal number of stages or optimal depth:

According to (M.S. Hrishikeshi et. al. the 29th International Symposium on Computer Architecture) 


  The difference between pipeline depth and pipeline stages; is the
  Optimal Logic Depth Per Pipeline Stage which about is 6 to 8 FO4
  Inverter Delays. In that, by decreasing the amount of logic per
  pipeline stage increases pipeline depth, which in turn reduces IPC due
  to increased branch misprediction penalties and functional unit
  latencies. In addition, reducing the amount of logic per pipeline
  stage reduces the amount of useful work per cycle while not affecting
  overheads associated with latches, clock skew and jitter. Therefore,
  shorter pipeline stages cause the overhead to become a greater
  fraction of the clock period, which reduces the effective frequency
  gains.