Can the memory cache hold instructions?
tillz is broadly correct, however there is one more detail of many modern systems which you should be aware of.

On some modern CPUs, when the power is first turned on and the CPU transfers control to firmware, almost all of the hardware needs to be initialised before it's used. This includes the hardware which arbitrates between cores in a multicore machine. One upshot of this is that main memory may not be available.

So some CPUs (notably Intel-esque machines) do support a mode where cache can be used as if it were RAM. Intel calls this "no-fill mode", and AMD calls it "cache-as-RAM mode". This is handled by the same mechanism that the CPU uses to implement non-cached memory (e.g. memory-mapped I/O).

On most modern CPUs, L1 cache split in two: an instruction cache, which is read-only, and the data cache, which is read-write. It does this so that the CPU pipeline can maintain the illusion of a Harvard architecture on top of a von Neumann architecture: the L1 instruction cache is "program memory" and the L1 data cache is "data memory", and they sit on top of a combined lower-level (probably L2) cache. "Combined" here means "both instructions and data", that is, it implements the von Neumann memory model.

Because the L1 instruction cache is read-only, the only way you can get anything in it is by filling from somewhere, and that somewhere is the next-level cache. So it's actually the lower-level cache which is acting as RAM, not the L1 cache.