How is clock syncing implemented?
I feel there are multiple questions in your post. I will attempt to answer the first -
&quot;...The clock period is set such that the other circuitry (NAND gate in my case) has the time to stabilize during the cycle. This is the contract. But how is it achieved?
Shown below is a transistor level circuit of the D flip-flop shown in the picture in your post.
If you replace your D-ff schematic with the above picture, you can see how the signal propagates from the D input to the Q output.
Your second question is
How can one implement this basic circuit to allow the logic to distinguish between signal and noise?
Logic does not distinguish signal from noise. Noise is a signal. It is an (usually) unwanted signal, but a signal all the same. It is the job of the designer to ensure that noise from various sources does not pollute the actual signal so much that it results in an incorrect reading at the Q output.
Circuits have some amount of noise immunity. Chips and cell libraries are designed such that the noise does not cross the specified noise immunity of the circuit.