Flags register in an out-of-order processor
The flags register is handled using one of the standard techniques for dealing with dependencies in out-of-order processors.  Either


the registers are renamed (there are multiple physical flags registers, and the renaming and retirement mechanisms make sure the correct physical flags register is being used by each instruction) or
the scheduler respects anti- and output- dependencies, in which case the two CMP instructions execute in-order because the second is output-dependent on the first.


Same thing with ADD instructions.  In a machine with ADDs that set an overflow flag, the overflow flag needs to be handled either by renaming or by stalling on anti- and output- dependencies.