Where are 'Base & Bounds' registers located?
The values for base and limit must be stored in registers somewhere; it would be highly inefficient to read these from memory on every memory access.

The distinction between "CPU" and "MMU" isn't really an important one on the old Cray vector architectures, and also isn't really important today. This is more about older microprocessors where a "processor" lived on more than one die (e.g. the 68000 architecture which had an external MMU). Today, address translation is closely tied to the rest of the CPU. This actually made the news this week, since Meltdown uses the interaction between the MMU and instruction speculation as a side-channel attack against some Intel CPUs. But I digress.

The diagram is talking about Cray vector computers, so probably the best reference is to look at an old Cray manual.

So here is the Cray Y-MP EL (i.e. the "entry level" model) functional description document, and the description of the exchange mechanism in particular:


  Address Base and Limit Fields
  
  Four registers in the exchange package define a program's data range
  and instruction range anywhere in memory and allocate specific amounts
  of memory to each range. This memory allocation technique has two
  benefits. First, all programs are relocatable. When a program is
  written, the programmer does not need to know where in memory the
  instruction and data fields will be located. Second, each program can
  have its memory access restricted to certain parts of memory. A
  program can be halted if it tries to run an instruction outside of its
  allowed instruction range or if it tries to read or write data outside
  of its allowed data range. This is especially important where more
  than one program occupies memory at the same time; programs can be
  prevented from executing instructions or operating on data that
  belongs to other programs. The four registers are described in the
  following list.
  
  
  The instruction base address (IBA) register holds the
  base address of the user's instruction range. It determines where in
  memory an instruction fetch is made. This is done by adding the
  contents of the P register to the contents of the IBA register. The
  sum equals the absolute memory address for the fetch.
  The limit address (ILA) register holds the upper limit address of the
  user's instruction range. It determines the highest absolute address
  that can be accessed during an instruction fetch sequence. If this
  absolute address exceeds the limit, a program range error flag is set,
  which generates an interrupt.
  The data base address (DBA) register
  holds the base address of the user's data range. It determines where
  in memory a program's data field is located. This is done by adding
  the memory address generated by the instruction to the contents of the
  DBA register. The sum equals the absolute address for any memory read
  or write operation.
  The data limit address (DLA) register holds the
  upper limit address of the user's data range. It determines the
  highest absolute memory address that a program can use for reading or
  writing data. If this absolute address exceeds the limit, the memory
  reference is aborted. The operand range error flag is set, which
  generates an interrupt if the interrupt-on-operand range error bit is
  set.
  


Altering these registers is typically a privileged operation, in that it is reserved for supervisor-level code rather than user-level code. On Cray machines, these registers were set with an "exchange package", which is more or less the equivalent of a process control block, so it was presumably an operating system routine that set the registers when a task was run.

Now let's take a quick look at a modern architecture.

For Intel x86, this is called memory segmentation. The base and limit registers aren't accessed like normal registers, but are stored in a special data structure called a segment descriptor, which is loaded with the LGDT or LLDT instruction. The difference between the two is that the x86 architecture supports two descriptor tables: "global" and "local". Each process can have its own local table, which is used for features such as thread-local storage.

The situation changed completely with the advent of 64 bit CPUs. In 64-bit mode, segment descriptors are, for the most part, no longer used. There are two segment selectors, FS and GS, which support loading a base field using the model-specific register mechanism, as well as a special instruction called SWAPGS, the details of which are only important for operating system implementors. Note that these selectors have no limit field. Protecting memory from unauthorised access is handled using the paging mechanism, not segmentation limits.

This brings the Intel architecture in line with most other modern CPUs, such as ARM, which do not support memory segmentation.