Consensus anomaly about read-write registers and test&set
Consensus number and consensus hierarchy are defined in the classic paper "Wait-Free Synchronization" by Maurice Herlihy, 1991.

Note the keyword: wait-free.

Since you did not give the algorithms for test&amp;set using read/write registers only, I guess that they are not wait-free. (They may be lock-free instead.)



Added: 

After the discussions with the OP in the comments, I realize that the OP has not fully understood the difference between atomic test&amp;set registers and atomic read/write registers. He/she thought that the protocol given in the post uses read/write registers only. In fact, it uses test&amp;set registers/operations/instructions in the second step. 

A test&amp;set register supports the test&amp;set operation, which is a combination of test and set that cannot be interrupted. See this wiki for more details.