IDE and EIDE data transfer speed
tl;dr: 25 times the clock frequency and two transfers per clock cycle equals 50 times the data rate.
First of all, let's forget about the terms IDE and EIDE. They were never specified in any standard or reference, and they were used in widely different manners by different people.
Some people use the term IDE (Integrated Drive Electronics) for any interface where the drive controller is integrated into the drive hardware, i.e. they use the term IDE to refer to any ATA, SATA, SCSI, SAS, IEEE1394, USB, or Thunderbolt drive. Some use it to refer to ATA-1 and the proprietary predecessors only, some use to refer to all ATA versions. Some people use the term EIDE to exclusively refer to ATA-2, some use it to refer to ATA-2 and ATA-3, some to any standard starting with ATA-2, excluding SATA, and some to any standard starting with ATA-2 including SATA.
So, let's stick to just official ATA versions, and let's call the proprietary versions before ATA-1 pre-ATA.
(Almost) every new ATA version has introduced new transfer modes, starting with the very simple PIO 0 transfer mode of pre-ATA. Each transfer mode has its own maximum transfer rate and cycle time.
Looking at Wikipedia, those were:

pre-ATA:

PIO 0 [3.3 MB∕s | 660 ns]


ATA-1: adds

PIO 1 [5.1 MB∕s | 383 ns]
PIO 2 [8.3 MB∕s | 240 ns]
Single-word DMA 0 [2.1 MB∕s | 960 ns]
Single-word DMA 1 [4.2 MB∕s | 480 ns]
Single-word DMA 2 [8.3 MB∕s | 240 ns]
Multi-word DMA 0 [4.2 MB∕s | 480 ns]


ATA-2: adds

PIO 3 [11.1 MB∕s | 180 ns]
PIO 4 [16.7 MB∕s | 120 ns]
Multi-word DMA 1 [13.3 MB∕s | 150 ns]
Multi-word DMA 2 [16.7 MB∕s | 120 ns]


ATA-3: drops all Single-word DMA modes
ATA/ATAPI-4: adds

Ultra-DMA 0 [16.7 MB∕s | 240 ns ÷ 2]
Ultra-DMA 1 [25.0 MB∕s | 160 ns ÷ 2]
Ultra-DMA 2 [33.3 MB∕s | 120 ns ÷ 2]


ATA/ATAPI-5: adds

Ultra-DMA 3 [44.4 MB∕s | 90 ns ÷ 2]
Ultra-DMA 4 [66.7 MB∕s | 60 ns ÷ 2]


ATA/ATAPI-6: adds

Ultra DMA 5 [100 MB∕s | 40 ns ÷ 2]


ATA/ATAPI-7: adds

Ultra DMA 6 [133 MB∕s | 30 ns ÷ 2]



Note that the Ultra DMA 4, 5, and 6 transfer modes required 80-wire ribbon cables instead of the older 40-wire ribbon cables. The 80-wire ribbon cables still had 40 connectors with the same pinout and semantics as the older cables, every other wire was a ground wire that was intended to provide physical separation as well as reduce capacitative coupling between the signal wires.
Also note that the Ultra DMA modes have two transfers per clock cycle, hence Ultra DMA 0 has the same maximum transfer rate as PIO 4 at half the clock speed.
Also, later versions introduced independent device timing, which allowed the host adapter to talk to each of the two devices on the bus with a different timing, whereas before that, it had to use the timing of the slower of the two devices.
Other than improvements to the transfer mode, there were also improvements to the command set that improved performance especially with multiple drives per bus. Originally, commands were completely serialized. The host adapter was only allowed to send a new command once the previous command was finished. ATA/ATAPI-4 introduced overlapped commands and queued commands as optional extensions to the ATA Command Set (ACS).
Overlapped commands allow the host adapter to send overlapping commands to both Device 0 and Device 1 on the bus, i.e. it allows the host adapter to parallelize communication with the two devices. Queued commands allow the host adapter to place multiple commands in a queue on the device, thus allowing the device to schedule the commands in a way that makes most sense for the device.
E.g. imagine, there is a WRITE command to write A into block 23, another WRITE command to write B into block 23 and a READ command for block 23, the drive could just throw away the first WRITE command, have the READ command immediately return B without even moving the read head, and only execute the second WRITE command.
However, neither overlapped nor queued commands were actually widely implemented because they caused a large load on the host CPU due to the way they were designed for backwards-compatibility with the ISA bus (from which the original pre-ATA bus was derived in 1986 and even the very latest version of Ultra DMA 6 in 2005 still had to be compatible with). Placing this large load on the host CPU meant that in most cases, while raw drive performance might have slightly increased depending on workload, the overall system performance didn't improve.
So, performance improvements were mostly made by improving the transfer mode, mainly by increasing the clock frequency (from 1.67 MHz in pre-ATA all the way up to 41.67 MHz in Ultra DMA 7), and later making two transfers per clock cycle (Ultra DMA). The command set added (optional) features for performance improvements as well, but those features were widely ignored.
Using DMA transfer as opposed to Polling I/O also helped, especially reducing load on the host CPU.