What data size is sent to and read from physical RAM?
There is no requirement that a transfer between memory and cache use one line per bit. In fact, DDR3 DRAM uses a burst length of eight, meaning that eight bits are transferred per line in four cycles at double data rate. (DDR3 supports burst chop of only four transfers, but this has the same timing constraints for a read following a read and a write following a write. Burst chop can reduce energy use and other DRAM ranks can use the memory channel during the inactive time.) By requiring burst transfers, memory chips can be made more cheaply while still providing high bandwidth.

The write interface to DRAM is likewise constrained. In addition, the modified nature of portions of cache smaller than a cache block is usually not tracked, so the cache would not know that it actually only needs to writeback part of the cache block. (Such constraints are not inherent in memory systems. Caches could track validity or cleanness at any granularity, at the cost of addition storage and complexity. Interfaces could be defined to support arbitrary sized transfers, including the use of mask bits to tell the memory chips to ignore specific data, but the complexity is generally not considered worthwhile.)

One advantage of a narrower interface is that synchronization of all the lines is easier, making it easier to produce an interface with a fast clock providing higher bandwidth with the same number of lines.

Note also that more than one memory channel can be implemented in a CPU. It is also possible to gang two or more memory channels together to form a single interface.