Nandgame--I am not sure I understand the Data Flip-Flop specifications
I have worked 20 years as FPGA logic designer but I stop at task Data Flip-Flop!
It is possible to build Data Flip-Flop. Two latches is required (sequential connection). First latch stores input data when st&amp;!cl, second latch stores result of first latch to output when st&amp;cl. Unbeliveable! Thanks to google...