Cache read controller
Information about on die structures are scarce for the intel CPUs. You can look at https://en.wikichip.org/wiki/amd/microarchitectures/zen#Memory_Controller for information on AMD CPUs. Especially the following images:


You have the actual die seen under a microscope for the Zen microarchitecture. You clearly see the L3 and L2 controllers. There is one L2 cache per core while there is a shared big L3 cache in the middle.