Data hazard or forward in MIPS SW after LW in this case?
It is unclear to me if you ask about the "real" MIPS chips, or about the simplified educational version one sees in class.

If you mean the former, then I would guess it does. Well, the CPU probably has way more steps in its pipeline, caches, and tons of other fancy machinery, but I think it is safe to assume that any valid code will run correctly on it.

As for the simplified 5-step pipelined MIPS: again, it depends on which version you refer to. Certain books have load-hazard circuits which are supposed to take care of most situations. But if you have a drawing of the circuits I guess you will be able to tell by yourself if forwarding units exist or not.

The moral is - the MIPS must run correctly any piece of code. If the code you present causes a hazard, then the MIPS hardware must$^*$ deal with it somehow. In most classes that teach MIPS they leave some parts off so maybe you saw a partial design that doesn't take care of it. If you have a specific version in hand, you can check.



$^*$Well, if the MIPS hardware doesn't take care of this, then the programmer (i.e., the compiler) must take care of it. This is less desirable.