Which hazards are solved by instruction reordering?
Instruction reordering in cpu-pipelines doesn't solve any hazards problem.

Register renaming eliminates write-after-write data hazards on registers and write-after-read data hazards on registers.

Speculative execution tries to find some useful work to do in the presence of control hazards.

Instruction reordering only works between instructions that are already completely independent of one another (either because they work with completely different registers or because after register renaming they don't need any of the same registers).  At best I would say that instruction reordering solves a "bookkeeping hazard" (I just made that term up).  The reason you would not do instruction reordering dynamically in the pipeline is if the bookkeeping hardware to do instruction reordering is too expensive for one reason or another.  Issuing instructions in-order is cheaper (in terms of hardware) than implementing the queues and logic to do out-of-order issue.