In cycle stealing mode, Does CPU gets blocked for 1 cycle or blocked till DMA transfer completion?
The CPU doesn't stay idle at all. It just gives the control of the data Bus to the DMA for 1 memory cycle . DMA transfers the data in this cycle which is consistent with it's transfer rate. Meanwhile the CPU can perform operations which do not involve the memory bus (by the means of cache memory and registers). In the scenario which you have presented assuming each instruction takes 1 cycle to complete , every 833rd instruction will have to wait for the DMA to complete its operation.