Number of hardware page tables and page directories kept in the MMU
The page tables are not kept in the MMU. In the MMU is a cache called the TLB which holds translated addresses. The TLB holds virtual addresses to physical addresses translations. For example, the TLB on intel core i5 has 64 entries for pages of 4KB.
Since the 10 upper bits are used as the offset in the page directory on 32 bits architecture, there are 2^10 = 1024 possible entries. The page directory has 1024 entries which hold the addresses of the page tables. Each page table has again 1024 entries holding the actual addresses of the page frames.
The CR3 register is used to locate the bottom of the page directory by the MMU. It holds a physical address (doesn't need to be translated).