Difficulty understanding the faster multiplication hardware
You want to multiply x by y, where both are 32 bit numbers. 

The result is the sum of 32 numbers. The first number is x if bit #31 of y is 1, and 0 if bit #31 of y is 0. This number is shifted by 31 bits. The second number is x if bit #30 of y is 1, and 0 if bit #30 of y is 0. This number is shifted by 30 bits. And so on. The last number is x if bit #0 of y is 1, and 0 if bit #0 of y is 0. This number is shifted by 0 bits. 

So you have 32 numbers to add. You use 16 adders in parallel to add the first and second, the third and fourth, the fifth and sixth number and so on. You get sixteen 34 bit results. Next you use 8 adders in parallel to each add two of these sums. Then 4 adders in parallel, then 2 adders in parallel, then one adder to get the final result. 

Obviously you figure out how big each result can be, and where you would be adding zeroes (which obviously don't need adding). In total you need 31 adders, five levels deep, so the delay for the multiplier is about five times that of a 32 bit adder. 

(BTW. There are methods that can get the result faster and I think with less hardware).