Does the databus size matter for determining the range of the memory addresses?
On most general purpose CPUs since the '70s, addresses are byte addresses.
This includes 6800, 680X0, PowerPC, x86, ARM, MIPS, SPARC, SuperH, Z80, PA-RISC...


There are sometimes exceptions with DSPs that are not meant for processing bytes. (example : Analog Devices SHARC)
Some small embedded CPUs may also have different addressing, or separate address spaces for instructions (example : Microsemi PIC)
Some CPU support address spaces where data is aliased and expanded. For example mapping each bit at a different byte address (example : Some ARMs)


The actual width of the data bus is not directly related to the CPU internal architecture, wether it is a 8bits, 16bits or 32bits CPU.

For example:


The MC68008 was a 16/32bits CPU with a 8 bits bus.
The G3/G4 PowerPCs (PPC603, MPC755, MPC7450...) are 32bits CPUs with a 64bits data bus.


With a 32bits CPU, aligned 32bits word adresses are 0000_0000, 0000_0004, 000_0008 ... to ... FFFF_FFF0, FFFF_FFF4, FFFF_FFF8, FFFF_FFFC.

Some CPUs can do unaligned accesses, usually slower than aligned ones. An example : x86.

In that case, you could access a 32bits value at address 0000_0001.