Finding $t$, $r$ and $w$ in Cache - Direct Mapping
I think i found out the solution, may be helpful for others reading this.

The size of a block is 8 bytes. And the memory is adressed with 2 bytes. So each block contains 4 words (considering 1 adressible unit = 1 word).

4 = 2^2, Then $w$ = 2 bits

Since cache has a size of 64 bytes which is 2^6, than $r$ + $w$ must be 6. 

$r$ + $w$ = 6, $w$ = 2 so $r$ = 6-2 = 4 bits

Lastly the MAR is 10 bits so the length of RA ($r$ + $w$ + $t$) must be 10.

$r$ + $w$ + $t$ = 10, $r$ + $w$ = 6, then $t$ = 10 - 6  = 4 bits .

So the RA distribution will be like:

+----------------------------------------+
| t = 4 |       r = 4      |    w = 2    |
+----------------------------------------+