What counts as a pipeline?
In 2-4(a) each stage processes one instruction at a time using one unit for every stage. In 2-5 the instruction fetch unit remains the same but fetches two instructions that are then processed parallelly, each with its own unit. So we have two pipelines of cause. They are logically and physically seperated. 
But as far as I understand, the main difference between 2-5 and 2-6 is that in 2-6 the CPU decides dynamically what the order of execution of the instructions will be (out-of-order-execution) so that it can eliminate dependencies and hazards. The multipipeline approach executes parallel but in-order. But a superscalar CPU will as well need all stages twice. I personally think it would be wrong to say a superscalar has one single pipeline.