How exactly the "load word" instruction loads from RAM?
Responding only to your UPDATE: MIPS always had load/store byte.  The original models may not have allowed unaligned word accesses.  Load byte is (relatively) easy on a 32-bit bus.  For example, you could fetch the entire word from memory (by setting the bottom 2 address bits to "0") and then add a little circuit so that when the word reaches the processor you use the bottom 2 address bits to shift and mask the correct byte into the destination register.

Store byte is somewhat more complicated.  At the beginning of the store-byte operation the processor shifts the byte into the desired position in the 32 bit word, and then sends the entire 32-bit word along with the entire address (including the 2 low-order bits) to the cache.  The cache uses the 2 low-order bits to control which bytes do and do-not get written.  (The cache has such control (at the word level) anyway, since typically the SRAM array is something like 256x256 bits (= 8Kbytes) or 512x512 bits (= 32Kbytes).)

The only recent architecture I can think of that didn't include load/store byte instructions was the DEC Alpha 21064 (released 1992).  Instead they added a lot of special bit shift-and-mask operations to extract bytes from words.  If you needed to store a byte on the 21064, I think you may have had to load the word that contained the byte, shifted and masked in the byte that you wanted to write, and then write back the entire word.

They added load/store byte instructions in the 21164A (released 1996) because the extra instructions to do all that extra work in software were making the instruction cache less effective than it should have been for programs with a lot of byte operations.