Query about FP Divide latency and Initiation Interval
You can think latency as the time (# intervening clock cycles here) required to get a result from a producer instruction to a consumer instruction. For FP divider it is required 25 cycles and the unit is unpipelined. So, the #intervening CC = 24.
On the other hand, initiation interval is the duration of time that is required to issue two similar type instruction. As FP divider is unpipelined, so you can issue another FP divider after finishing the previous one which requires 25 clock cycles. If it was pipelined, I guess it would be 1.