structure of cache when CPU uses words smaller than the main memory
So the question is a bit confusing because there are two types of words: CPU words that are 16 bits, and memory words that are 32 bits. This can happen when the CPU registers have 16 bits but the memory chip is organized in such a way that the minimum accessible unit (a word) is 32-bit. The cache will always read/write multiple of memory words, in this case one word per line. Since the CPU word is 16 bits, each memory word (32 bits) actually holds two CPU words, those are the Word 0 and Word 1 on the picture.

Now, when the CPU accesses memory, the cache will find which lines corresponds to the request. This line contains 32-bit, but maybe the CPU only wanted 8 bits, so we have to extract those 8 bits from the line. In this example, bit 1 will select between Word 0 and Word 1 (which are CPU words). The resulting word still has 16 bit, so we use bit 0 to select between the low or high 8 bits of that word.

If you still find confusing, forgot about Word 0 and Word 1 and just imagine that each cache line stores 4 bytes (=32 bits). Now to select one byte in 4, you need to discriminate based on the lower 2 bits of the address. If the cache had 8 bytes per line, then you would use 3 bits. And so on. In general, the format of an address is

| Tag | Index | Offset |


where Index selects the line (there are many way of doing so) and Offset selects the byte within the Line.