Does the Hack computer from "The Elements of Computing Systems" use Von Neumann architecture?
I had the same suspicion going through the Nand to Tetris course.
Indeed, if you look at John K. Bennett's annotated version of &quot;The Elements of Computing Systems&quot;, specifically Chapter 5, he calls this out:

The Hack architecture would more properly be called a “Harvard Architecture,” since the data and instruction memories are separate.


We can also do some digging for ourselves.
If we consult Wikipedia, it states that the Harvard architecture is distinguished by:

The term &quot;von Neumann architecture&quot; has evolved to mean any stored-program computer in which an instruction fetch and a data operation cannot occur at the same time because they share a common bus.
The design of a von Neumann architecture machine is simpler than a Harvard architecture machine—which is also a stored-program system but has one dedicated set of address and data buses for reading and writing to memory, and another set of address and data buses to fetch instructions.

The latter is indeed the architecture of the Hack machine, which has two separate memories and can do an instruction lookup, data lookup, and computation all in one step* of the CPU. You can see this in the book's diagram:

Last, this is also explicitly stated at the end of Chapter 5 of the original book:

Unlike Hack, most general-purpose computers use a single address space for storing both data and instructions. In such architectures, the instruction address as well as the optional data address specified by the instruction must be fed into the same destination: the single address input of the shared address space. Clearly, this cannot be done at the same time.... In contrast, the Hack architecture is unique in that it partitions the address space into two separate parts, allowing a single-cycle fetch-execute logic.

*Note: In the Hack machine language, it actually takes two steps (e.g. @dataaddr then D = M + 1) to do an operation on data in memory. However, during the second instruction, both the instruction and the data in memory can be read by the CPU simultaneously.