why are WAW and WAR hazards not possible in mips architecture
in case I2 Takes less number of clock cycles than I1 for completion then can I2 access the register file going to WB phase directly in case it has nothing to do in the phase of MEM will this give rise to a hazard?


I2 reads the register R1 at its ID phase. Therefore, if implemented directly, we must have time(I2.ID)>time(I1.WB).
A more sophisticated solution would bypass the register file and take the values directly from the Memory output. In this case we need 
time(I2.ID)>time(I1.MEM) and the controller becomes more involved.

If I understand your question correctly, you ask whether I2 must take 5 clocks although it doesn't use the MEM phase. The answer is YES or otherwise, it may conflict with other instructions that would try to use MEM at the same time (unless the pipeline controller stalls them when congestion appears).