Clarification on interplay between cache line size and read/write sizes
Cache lines always start at a byte address that is a multiple of the cache size, like 0, 64, 128 etc. If you need 8 bytes starting at byte 30, then the cache line containing bytes 0 to 63 will be loaded. 

If you need 8 bytes starting at byte 60, then you need bytes from two cache lines, so the cache line from byte 0 to 63 is loaded, then the line from byte 64 to 127. (Since this is more complicated, it very much depends on the CPU how long this will take, usually anything from "a little bit longer" to "a lot longer". Compilers will usually try to align data to minimise the cost of data straddling cache lines).

Sometimes the cache line size is bigger than the amount of bytes that can be read from RAM in one operation (say 64 byte vs 32 bytes). Some CPUs can then read the "right" 32 bytes first and deliver the data to the CPU, while the rest of the cache is being loaded. So if you want bytes 40..47 the CPU may be able to load bytes 32..63 first, then give the 8 bytes to the CPU while loading the second half.