Why are FPGA's less efficient than fully hard-coded ASIC's?
Functionality of FPGAs in very coarse lines:
At the core functionality of FPGAs are small memories called Look Up Tables (LUTs). An FPGA instead of actually compute in hardware the output of a function, say f(x), what it does is store in these small memories all possible outputs of f. So next time an input x is given fpga passes x as address in a small memory and "looks up" the answer. As it happens with all kind of memories the larger the memory the bigger the delay. So FPGAs are consisted of "a lot" of very small LUTs distributed all over their surface. Every LUT "solves" a tiny subproblem and passes the answer to subsequent LUTs for further processing (answers). Loading the LUTs with different answers and connecting them in a programmable way gives FPGAs the ability to solve any kind of problem.

LUTs are interconnected each other in an hierarchical manner. That is, as it happens with computer networks, or with buildings, it would be infeasible to connect via road each building with every other, buildings are interconnected in an hierachical manner where you have small streets, bigger streets, highways etc. So to route a package from A to B you don't have a direct-short/fast-link between A and B, but instead you may use a lengthier route which is consisted of various kinds of roads.
According to the previous analogy LUTs are the buildings and roads are the signal interconnections between LUTs. In FPGAs LUTs which are a kind of processing units are fixed in specific places, so in order to pass a signal from one LUT to another you have to follow the specific route hierarchy of FPGA. Instead in an ASIC you can place processing units in more efficient manner, and also make direct interconnection where is critical to do so, in order to minimize the delay.
Even the simplest form of processing in an FPGA (consisting only of programmable logic) has to be in the form of a LUT. For example to compute the output of a 2 input AND gate you would need a LUT. In an ASIC you would need just an AND gate. The total circuitry of the LUT certainly has greater delay that just an AND gate of the same technology.
To sum it up the sources of inefficiency of an FPGA are the 


routing delay you might have due to fixed routing hierarchy and 
circuitry overhead of LUTs themselves 


Have in mind also that an FPGA is actually an ASIC, in which the "specific application" is to be programmable!