Whats the point of caching if the minimum single clock cycle time is the prorogation delay of the slowest component (fetching from DRAM)?
You are right that the clock speed is determined by the slowest stage. But on most architectures it is not true that fetching(or any kind of memory access in fact) takes one cycle. This is an illusion provided by the CPU to makes things manageable. In practice if your CPU tries to fetch and the operation cannot be completed in one cycle then it will stall(on pipelined processor it will introduce a "bubble") until it gets the memory content. Thus if your memory takes 100 cycles to read, then the CPU will stall 100 times in the fetching stage. The same applies to read(and to some extent write) stages.

This is why caching is so important: by caching the processor can reduce the fetch/read/write delay and maintain this illusion that it takes one cycle when really it does not. Example latencies for memory read are:


L1 cache: 1 cycle
L2 cache: 10 cycles
DRAM: 100 cycles


Do not take those figures literally, it is very architecture dependent. But you can see that without caching, your CPU would take 100 cycles to fetch each instruction, this is obviously unacceptable.