Miss penalty for Write request in a Write-Back style system
Depends on what you mean by "penalty". In theory (and in practice in high performance processors), a store does not need to stall subsequent instructions, so there's essentially no penalty at all from a store miss.

If you're talking about issue-to-commit time (i.e. when the store can be considered permanent) then the latency would indeed be when the cache line read occurs.

NOTE:

Most if not all architectures (ARM for example) allow non-temporal store hints. In practice most processors treat these as non-cacheable stores. So they go directly to memory without the need to grab the data into cache.

Some microarchitectures detect store streams to a temporal block. They support a type of RdNoData command that simply grabs store permissions without transferring data.