Data addresses with ADD instruction in various architectures?
First some terminology:

Let's consider the ADD operation that is a logically three operand operation: two sources and one target, so these 3 are the maximum that could be provided.

A (hardware) machine instruction is subdivided into fields, the main one of which is the opcode field.  The instructions can also be fixed-length or variable length.

An addressing mode is a way of specifying what memory address (i.e. data address) to use for reading or writing.  The architectures that you are asking about vary in the instructions that allow for addressing modes as fields in the instruction.  Typically, the fields associated with an addressing mode require a fair number of bits, such as 12, 16, 20 or more because they contain parts of memory addresses.



In a stack-based architecture, operations such as ADD implicitly target the stack, for both sources as well as for the target.  So, an ADD instruction has just one field, the opcode field, and will have no instruction set fields regarding source and target.  Initial operands are moved to the (expression) stack using PUSH instructions and popped of this stack using STORE (or POP) instructions.  It is the PUSH &amp; STORE instructions that have the potential to indicate sources and targets that reference memory (e.g. data addresses).  The following accomplishes an ADD in a stack architecture.

PUSH  item1
PUSH  item2
ADD
STORE item3


item1, item2, and item3 would be considered addressing modes within those instructions, and might allow access to local variables and global variables.  Because the PUSH &amp; STORE instructions have additional fields beyond the opcode whereas the ADD instruction does not, stack machine architectures typically use varying length instructions.  The hardware advances the PC by the right amount for each instruction so that it can execute the logically following instruction.  When several computations (multiple ADD or ADD &amp; SUB, etc..) are combined the stack machine can use the stack to transfer intermediate computations without intervening PUSH &amp; POP instructions.



In an accumulator-based architecture, you will typically have opcodes with one addressing mode.  The following sequence would be typical of them:

LOAD  item1
ADD   item2
STORE item3


You can see that a similar code sequence has one less instruction, and the instructions tend to be more regular.  As a result of this, accumulator machines might choose a fixed length instruction set (e.g. 16-bits).  The accumulator is implicitly sourced and targeted and does not require an instruction field.  



A RISC register architecture, like MIPS will have a large number of registers (e.g. 32 or more), and support three operand instructions, though only between registers.  Memory operations will require separate LOAD and STORE instructions.

LOAD  r1, item1
LOAD  r2, item2
ADD   r3,r1,r2
STORE r3, item2


Here we have a longer sequence for the same operation; however, the RISC machine has so many registers that the idea is to use them instead of memory for local variables and such.  Thus, many of the loads and stores you might otherwise expect are eliminated.



x86, for the most part, is two operand machine.  It has more registers than your single accumulator machine, but fewer than a RISC machine.  Most instructions on x86 allow specifying a register number and an addressing mode, which might refer to another register or might refer to a memory addressing mode.

MOV AX, item1
ADD AX, item2
MOV item3, AX


Like the RISC machine, the 8 or so registers can be used for heavily used local variables, reducing the memory access.  However, will fewer registers the advantage isn't as good as with a RISC machine.



There are considerable trade-offs between these various architectural approaches to instruction set architecture.  Generally speaking, the stack machines result in smaller code space, because of their variable length instruction sets.  Code space has a huge impact on instruction cache performance, so the smaller the code, the better.  However, by comparison with RISC machines with their fixed-size instructions, the variable length instructions (and more of them) require substantially more complex decoding hardware, which either costs transistors or sacrifices performance.