Can an instruction with a dependency read the register in same cycle as it's being written?
With modern processors, arithmetic units tend to be able to deliver results simultaneously to a register, and to another arithmetic unit that requires that result. 

There is a limit to this, so if you have three add instructions "x = a + b, y = x + x, z = x + x", then the a+b operation is unlikely to be able to send the result to a register, and to four inputs of two more additions. Even reading from a register is likely limited, so in this extreme example you could have (assuming an adder can forward to one input and a register, and registers can be read by two inputs): 

Cycle 0: Adds a+b, sends result to x and first input of y = x + x.
Cycle 1: y = x + x reads second input from x; z = x + x reads first input from x
Cycle 2: Adds x + x, sends result to y. z = x + x reads second input
Cycle 3: Adds x + x, sends result to z. 


On the other hand, take x = a + b, y = x + a, z = x + b:

Cycle 0: Adds a + b, sends result to x and first input of y = x + a
         y = x + a reads a, z = x + b reads b.
Cycle 1: Adds x + a, sends result to y. z = x + b reads x.
Cycle 2: Adds x + b, sends to z.


So an instruction cannot read a register at the time it is written to, but often results can be forwarded to an instruction at the same time they are written to a register.