Difference between memory access and write-back in RISC pipeline
In a classic 5-stage RISC pipeline, WB writes a value into a register. If the instruction doesn't write a value into a register (e.g. store), then that stage isn't used.

I1 stores a result into a register (namely R1), so it uses WB.

I2 stores a result into a register (R1) so it uses WB.

I3 does not store a result into a register, so it doesn't use WB.

You basically got it with I3: the store instruction stores to memory, so the "write" is performed inside MA.

Incidentally, on "real" RISC machines, MA tends to be more complex (and multi-cycle) because of multi-level caches and virtual memory. A store instruction may cause a page fault, so in a sense it has a "result" that isn't just the memory access.