Bus and System Clocks
In a simple computer architecture with a single active CPU connected to RAM and other passive peripherals by a bus, then there is a timing signal (typically produced by a quartz oscillator) that synchronises the internal operation of the CPU. This clock signal is the system clock.

There may also be a separate timing signal that synchronises the activities of writing to and reading from the bus. This is the bus clock. Because the speed at which data can be reliably transmitted across the bus may be lower than the internal speed at which the CPU runs, the bus clock signal is usually at a lower frequency than the system clock. The bus clock signal may be produced by passing the higher frequency system clock signal through a frequency divider.

In more complex architectures, where there are multiple active components (CPUs, FPUs, graphics cards, memory controllers, I/O controllers) running at different speeds, then the bus clock is often the fundamental synchronising signal, and each component then multiplies the frequency of the bus clock signal by a specific ratio to obtain its internal system clock signal.

For more details see https://anydifferencebetween.com/difference-between-system-clock-and-bus-clock/ and https://en.wikipedia.org/wiki/CPU_multiplier.