How earliest that the data TLB (Translation Lookaside Buffer) can be accessed in an instruction execution pipeline?
Often the effective address is the sum of a small constant and a value from a register. Not always, so this trick does not always apply. The trick then is to make a gamble: access the TLB based on just the value from the register, in parallel with adding the offset to it. Usually the small offset won't change the page being accessed, if that works out then you might have the result from the TLB a cycle earlier. Of course there needs to be a check afterwards to see if the upper bits of the virtual address didn't change, and if it fails the TLB access has to be re-done.

There is even a patent for this, with way more detail: Guess mechanism for faster address calculation in a pipelined microprocessor