Role of the MMU in a Page Fault Swap
For x86 if the hardware page table walker tries to load a page table entry from a speculative access (or hinted by a prefetch instruction) and the Present Bit is zero, then a page-fault exception is generated (Intel® 64 and IA-32 Architectures Software Developer’s Manual, Vol. 3A, 4.7 PAGE-FAULT EXCEPTIONS).

The OS then handles this exception by using OS-specific structures to find where the page is stored and return it to memory. (An OS can choose to mark a page as not present even though it is still in memory. This could be used to give the page a brief last chance before being victimized with potentially less overhead in the common case of the page not being reused before another free page is required.)

A transfer from a hard drive is almost certain to use DMA as such is more efficient. (Network storage using something like ISCSI or a network file system would typically have more processor involvement since such protocols are not typically implemented as part of the networking hardware interface.)

Other ISAs with hardware page table walkers would behave similarly. (An ISA whose hardware page table walker uses hashed page tables like Power Servers and Itanium [which also has the option of using linear page tables] can have a page table miss from a conflict in the hash table. Such page tables are sometimes used as "software TLBs" in that software fills the page table and like a TLB the page table can suffer a miss, which is different than a hit with the page table entry marked invalid/not-present.) 

With a software page table walker (e.g., older MIPS, Itanium using linear page tables when the virtual address associated with the location of the PTE is a TLB miss), the software would typically check to ensure the page table entry was marked as valid/present before inserting it into the TLB (loading an invalid PTE usually only makes sense for a sectored TLB entry where multiple PTEs are cached with a single virtual address tag). This avoids an additional exception.