What is this trapezoid-shaped logic component?
Looking at slide 5-43 "Data Path Revisited" these are MUX, multiplexors.

As such they are a "switch": When the red input is 1, we have immediate mode and the SEXT output is passed through unchanged. When it is 0 it needs to look up a value based on the SEXT value and some memory or register.

Also in the slides, a MUX is represented again at BR and JMP, slides 5-31 and 5-35, again without actually clearly defining the alternative scenarios, and the BR case confuses the issue a bit because it clearly calculates a relative jump previously.

I'd guess the red input is the result of the branch condition and if false the original PC is passed through, but if that was the case they might as well have connected up the lines in this diagram.

For the JMP it is currently showing an absolute jump and under a different red arrow input it could be an indirect jump, similar to the ADD case.

(My latter suggestions have not actually been reconsidered much after reviewing slide 5-43.)