MIPS with one read port in the register file?
For your MIPS CPU with 1read + 1write register file :


ALU instructions will last two cycles as you describe.
Load instructions can be executed in 1 cycle (with data in cache, etc...)
Store instructions must be split in two cycles to get the two source registers.


Another example, in SPARCs, STORE R1,[R2+R3] require two cycles with a 2R1W register bank, whereas LOAD [R1+R2],R3 can be executed in 1 cycle.