Origin of tFAW (Four Activation Window) in DRAM timing constraint
The magic number is just 4 since (within one rank) you have just 8 banks where you can spread your consecutive accesses. The problem lies with the bank activation current drained from the entire array (or bank) of single cells (transistor + capacitor) needed to prepare the memory location to be read. If the consecutive read operations are falling each time in a different ROW within each bank than you have the activation problem kicking in each time. In order to avert a high current drain from the arrays you need to limit the number of consecutive bank activation over a rolling window of time. The reason why you need to prevent the bank from high energy / current drain is because this may cause a Voltage Reference (VR) deterioration. The VR is the standard Voltage level against which earch data read from the bank is compared to verify if what you are reading is 1 or a 0. Risking to alter the VR level may mean that the reliability of what your read or write is compromised.

However these tFAW and tRRD parameters are usually overestimated and a memory tuner may increase system performances by slightly changing these parameters.