Understanding Multilevel Caches
Block sizes (aka Cache line lenghts) can be different on different levels of caches. L1 caches should be optimised for the type of access the CPU does while L3 caches should be optimised for the burst lenght and data width of the attached DRAM memory.

It is possible to fill/spill only one block of the L1 with a larger block sized L2 (in your example 4 words). On write back, either the whole L2 block is marked as modified, or use sub-blocking (effectively reducing block size without raising associativity).

One advantage with using the same size is probably with exclusive caches (AMD did that many times) : As soon as a block is in L1, copied from L2, the L2 block can be made available for new data.

Edit

Many examples there : http://www.7-cpu.com/
Using different block sizes across different cache levels seems very rare : Several recent x86 use 64Bytes, ARMs 32Bytes, PowerPCs 128Bytes, but they keep the same size on all levels. Note also the bus width : Internal busses can be extremely large, able to transfer 16 or 32 bytes in one cycle.