Why can't CPU access secondary memory
There are CPUs that can execute programs directly from secondary memory. (I'm kind of surprised at you not being able to simply search this: e.g.http://www.analog.com/media/en/technical-documentation/application-notes/EE363v01.pdf) 

That being said, many CPUs cannot. It generally boils down to access speeds and/or I/O type. Secondary storage (flash, etc) can be slower and/or have more latency than RAM, and for a simple CPU (i.e. embedded system or similar, generally) the CPU may not be able to wait the length of time necessary to do an instruction fetch. (Or rather, it may assume that an instruction fetch will complete in  cycles as opposed to having a mechanism to wait until the instruction is actually fetched) 

Also, unless you have memory-mapped I/O or a proper MMU you'll need explicit support by the CPU to issue the I/O instructions required, which increases the complexity of the CPU and may increase the critical path, limiting the speed of the CPU. (If you have a MMU you can just have a page fault handler that fetches the appropriate page from secondary memory on first access)

An elaboration:

Ultimately, a CPU has to be able to read the data for its next instruction. This is generally only a few bytes at most. However, many devices only support block-level access (e.g. 512 bytes, etc) of larger block sizes than the instruction size. Note that this includes many forms of RAM! (For instance, if you have DDR ram (64 bits transferred at a time) and an instruction set that isn't always 64 bits wide) There are a couple of ways to deal with this mismatch: you can fetch the block and toss away the data you don't need for that instruction, you can fetch the block into a small sliding window of the next few instructions (throwing away the rest of the block) so you only need to do a fetch every few instructions, or you can fetch the entire block into a buffer. Fetching every instruction is slow, and in particular is latency-sensitive. It also wastes memory bandwidth that could be otherwise used for DMA, for instance. Fetching into a sliding window can faster, but substantially more complex. It also introduces latency variations (if you have unpredictable branches you may not be able to keep the window filled, for instance) And fetching the entire thing limits you and requires a lot of die space for the buffer (you need to have a buffer at least as large as the block size), and is prone to problems (e.g. what happens when an instruction overlaps two blocks? There are a lot of edge cases.)