Whats the logic between MAR, MBR and Control Bus
The RAM typically has a input pin called MW for "memory write" (maybe with inverted logic, then written with an overbar), to distinguish between read and write operations.

Control will probably use an extra wire to the RAM. In theory, you could use an usused high address bit for that, too, but I guess that would be considered to be a very questionable design - in fact "invalid" memory addresses are used for other strange things, like talking to non-memory devices such as line printers.

An address decoder will select the appropriate memory cell.

After that, the rest will depend on the MW bit... on the writing side, if it's static RAM (SRAM), you can use MW for enabling ("gating") the flipflop S (set) pin. On the reading side, you could use a transmission gate to connect or disconnect the RAM output from the data bus (logic gates won't do here, as the RAM output has to be decoupled from the data bus, unless you are actually reading values).