Polynomial division hardware implementation
The method you describe is called the "pencil and paper algorithm" and is well described in Knuth's Book, Semi-Numerical Algorithm II.

In fact the number of steps can be easily determined by the size of operands. If Dividend D, is m-bit and Divisor d, is n-bit, then the Quotient q, will be (m-n+1)-bit, and the remainder in case of binary division will be at most (n-1)-bit.

Under these conditions, the algorithm il like that follow:

Shift the divisor (m-n)-bit left (this is called Normalization step by Knuth), We use some registers to be initiated by the operand 
Reg_D &lt;-- D: init with D, used as an Accumulator,
Reg_d &lt;-- d: init with divisor $2^{m-n}$d; remains unchanged during all the process iteration,
Reg_q &lt;-- 0: init with Operand 0,

for k from (m-n) DownTo 0, Do:
   - Reg_q &lt;-- 2.Reg_q;  //Shift Reg_q 1-bit Left (or equivalently q = 2.q)
   - Reg_D = Reg_D XOR Reg_d;   //... XORing(Reg_D, Reg_d): 
   - q_k=MSB(Reg_D); //Get the bit which represent the partial bit of quotient. 
   - Reg_q = Reg_q + q_k; //... Inject bit q_k in Reg_q, or 
   - if( !k)
           Reg_D = 2.Reg_D;  //... Shift  1-bit Left D excepted for last step!
End For;


NB: Observe: 


The Remainder is contained in  Reg_D,
To obtain the quotient, Complement the content of Reg_q.


To optimise the process, in case of multiple division with the same divisor you can try two methods described by Knuth:


Normalization of the Divisor,
Precomputation tables.


Good Luck for your project.