Could an algorithm be made ASIC-resistant by simply adding deterministic permutations depending on the hash of the previous block and the nonce?
Your solution will least at most a year until dynamically reconfigurable FPGAs appears in the market. Then creating any logic circuit on the fly will be possible, and so efficient FPGAs will outperform CPUs by a large margin.

See for example: http://en.wikipedia.org/wiki/Partial_re-configuration