DSSS direct sequence spread spectrum - encoding each raw data bit (question)
In your title and your question overall, you confuse bits and symbols. Not a big deal – we can just work with the idea that we use a constellation where one symbol is equivalent to one bit (e.g. BPSK). But remember that there's no restriction that says you can't DSSS e.g. a 64-QAM modulated symbol stream. (In fact, that's what IEEE802.11b does, iirc).

I'll hence use "symbol" in place of "bit" where I cite you below, whenever it doesn't make a difference. When it does, I'll try to explain.


  Will this mean that we have to find hardware that generates a clock rate (for the PN generator) having 15 times the frequency of the raw symbol rate?


Yes! We call that higher rate chip rate, by the way.


  Initially, I was thinking that a high frequency clock could be used as a reference. However, conventional flip flop frequency dividing methods divide frequencies by even amounts, like divide by 2, divide by 4 etc. There is no option for 'divide by 15' (or divide by an odd number).


Well, you can certainly build a digital counter that counts to 15 and resets – your 1/15 clock divider. So, I think you might be imagining problems where there aren't problems. It's not as trivial as a $2^N$ counter, but honestly, a $2^N-1$ counter is just either a $2^N$ counter where you reset all bits to 0, but the lowest bit to 1 (giving you a single count of headstart), or really just a counter with a $N$-input NOR gate. Or really, just a counter that can compare to an arbitrary value. All these aren't hard to build. This isn't the 1960s!


  So if I want to use LFSR PN sequence patterns for encoding raw symbols, then what kind of method should be used? Is this the usual problem faced when using maximal LFSR generators?


The thing is even easier: You've got a device that repeats itself every 15 states, and changes at the high clock rate. Why not simply use that exact device to build your frequency divider? You could just compare all the state of SR to the one state on which you output a pulse. Done!

But again, integer frequency division really isn't that hard to implement at the rates you're probably worried about.

As another matter of fact: you'd probably not even use the higher frequency as reference, but a lower frequency, from which you synthesize the symbol and the chip rate, and quite possibly also the RF local oscillator. Since the relationship between chip and symbol rate is a rational one, a relatively simple integer-N synthesizer might be used, but frankly, aside from spur performance, there's little reason not to go to fractional-N synthesizers – which, by the way, are especially made for such systems. 


  Due to the odd-valued number of bits, is there generally going to be an issue with coming up with a system for generating the clock rate that is 7 times higher than the raw data rate? I can understand that generating 8 times data rate would be relatively easy to do, because 8 is a 2^N value.


There's no hard tasks here. Count to 7, emit a pulse, reset your counter. Counters are relatively easy to build capable of high clock rates.


  Would fractional DDS type frequency generation methods be used instead?


Not quite sure what fractional DDS is, but a DDS method involves jumping through a table at high rates, to produce lower-frequency tones. I don't even think that's easier than a odd-number-counter to build a frequency divider. DDS is generally used to produce tones, not digital clocks.