Would it be feasible to implement the Sliding DFT on a digital signal processor?
The paper Sliding DFT control algorithm for three-phase active power filter implements a sliding a sliding DFT on a TMS320F2812 from Texas Instruments, and discusses some advantages, and An Enhanced Interpolated-Modulated Sliding DFT for High Reporting Rate PMUs does similar work on FPGA.  

From what I remember, you may have a look at the stability, see  The Sliding DFT.