Transfer function of a PLL Loop Filter that can support a linearly increasing (chirping) frequency
To track a frequency ramp with a Phase lock loop, with zero steady state error requires a type 3 PLL Loop; which means three integrations (DC Poles) in the open loop gain (your NCO would be one of the integrators and your loop filter needs to provide the other two). Stabilizing such a system becomes more challenging but here is one reference paper detailing an approach to the design:

http://vbn.aau.dk/files/72548181/Final_PLL.pdf

This picture helps clarify tracking and loop order; given a phase lock loop, phase is the parameter being tracked. A frequency ramp as you are dealing with is an accelerating phase, hence the requirement for a type 3 loop.  The detailed loop filter design would depend on your overall system and related gain coefficients for your specific design, but I hope the above reference offers some guidance to help you.  

Also note that many people often confuse "Type" with "Order", so to be very clear a Type Three Loop is not the same as a Third Order Loop. Specifically a Type Three Loop must be Third Order (or higher), but a Third Order Loop need not be Type 3. Type specifically is number of integrators in the loop, which are poles at z=1 in the open loop gain, while order is the total number of poles, regardless of location (specifically the order of the denominator polynomial of the open loop gain, which ends up being the order of the closed loop gain given proper transfer functions).