What is formula for quantization step size?
The actual quantization step size depends on the implementation of the quantizer, and would be by definition the input voltage change that would cause the digital output to increase by 1 bit.
You can find the specifics for the actual device you are using on the manufacturer datasheet, such as this example from ADI's AD9459 ADC, where the input range is from $\pm V_{ref}$ where $V_{ref}$ is an externally supplied reference voltage, and OR in the table is an out of range indicator:

The actual threshold down to 0.5 lsb levels is of no practical use since the self-noise within most ADCs typically exceed 1 lsb (otherwise the core could be used as a higher bit converter). Datasheets will also specific ENOB (Equivalent Number of Bits) which is dependent on sampling rate and input frequency. This captures all noise sources and provides a metric of the same number of bits the device provides compared to a &quot;perfect&quot; ADC. Note that this precision is maximized with an input signal that is typically 1 to 2 dB below actual full scale where clipping would occur (as we approach the actual full scale, spurious signals increase due to non-linearities which degrades overall dynamic range and therefore precision).
That said it is sufficient in most cases to simply use the total input range (up to the backed off full scale) and divide by $2^{b}$ where $b$ is the stated precision in ENOB.