Fixed-point and ARM CMSIS-DSP FIR filters
I don't think either will increase your precision as such, although there are benefits to each approach.

Using the lower 11 bits of 1.15 would provide you with 24dB of extra headroom (obviously being careful to sign extend properly). Alternatively, using the upper 11 bits could potentially lower the power in your quantisation error after 1.15 * 1.15 multiplication (for example). 

The design is a compromise being headroom and dynamic range, and hence the best route probably depends on the magnitude of your coefficients. 

The following example shows how extra headroom can be useful:

Let's say you have an FIR filter (1.15 fractional binary) with 2 coefficients, which are both 0.8 (for some reason). If your input was 0.9 for two samples in a row, your output would be (0.8 * 0.9) + (0.8 * 0.9) = 1.44. This value would lead to an overflow or hard clipping since it doesn't fit into 1.15 (fractional). To avoid this you could first shift the input down by 1 bit, to give yourself 6dB of headroom. This would change the sum to be (0.4 * 0.9) + (0.4 * 0.9) = 0.72, which now safely fits into a 1.15 container.

In a normal system where you're using all 16 bits you'd then have to worry about (or just remember!) the fact that your signal is halved in amplitude. In your case you don't need to worry about this, as your full scale signal is only 12 bits to start with.