Can I create my IF signal on SDR before bringing data to PC?
The theoretical data rate to transmit a signal with bandwidth $W$ Hz and resolution $R$ b/sample is simply $2WR$ b/s. In practice, you will need somewhere between that and $4WR$.
One way to reduce the required rate is to preprocess the signal in the SDR's FPGA. This will require delving into Verilog, integrating your hardware with what is already there, and very likely simulating and debugging it. What can be done also depends on how much space is left on the particular FPGA in your device.