IIR Filter structure implementation dynamic range
Peter's correct.  at least if fixed-point arithmetic is used.  the DF2 has poles before zeros.  that means the signal is getting boosted by the poles before the zeros (which are often sitting very close to the poles) beat the gain back down to reasonable levels.  so if the signal overflows, saturates, and distorts due to this gain, the attenuation offered by the zeros does not reverse that distortion error.  it's too late.

now the DF1 implements the zeros before the poles, and if you did not have an accumulator that has a double word width, then the DF1 suffers a sorta opposite flaw.  instead of potentially overflowing (and saturating) due to gain from the poles which is what the DF2 does, the DF1 will have attenuation first (due to the zeros) followed by the compensating gain from the poles.  if the accumulator is no wider than the signal word going in, there is roundoff error due to quantizing the attenuated signal.  then when the poles act on the attenuated and quantized signal, that quantization error is boosted by the poles.

BUT if your DSP (or whatever processor you use) has an accumulator that is twice the width of the two multiplicands, there is no roundoff error for the poles to boost.  so the DF1 avoids the overflow problems of the DF2, but if and only if there is a double-wide accumulator, does not suffer from boosting the roundoff error.