Why FIR uses often direct-form instead of transposed-form?
I don't see how memory or computational burden can possibly be reduced between the two implementations (note this is not implying simplicity, just number of computations required, please read on...) Usually the decision to use transposed-form is for high speed FPGA implementations with a large number of taps as you can eliminate a long adder tree which would otherwise limit the maximum clock frequency to a lower number due to the accumulated effect of multiplier and adder delay, but this can get more complicated for a fixed precision implementation since the bit width must grow as you proceed in the filter. (This consideration is particularly important in IIR implementations where feedback exists but affects FIR implementations with large adder trees, and also a reason to factor longer IIR filters in cascade form). At lower speeds the direct-form is more convenient to implement as you can use a single extended precision accumulator.

I include a summary of the basic forms applicable to FIR/IIR below for benefit of readers that may be less familiar, and see link from Ben in the comments for more advanced structures specific to FPGA implementations: