Clear examples of Fixed Point Algorithm Specification Block Diagram for FPGA Implementer
I designed a lot of DSP algorithms and I would usually be the one implementing them in an FPGA. I rarely had to explain the internals of an algorithm to other people. That beind said, it is a good idea to represent the number of bits (I usually used the s:m:f notation from Sony Playstation 2) in a block diagram/design document for every components. You should also specify whether or not the FPGA designer must truncate or round.
Otherwise if you leave the number of bits used for the internal calculations up to the FPGA designer, you're looking for trouble. Using an insufficient number of bits can render your algorithm useless or unstable.
It is also a good idea to create a fixed-point model of your algorithm in Matlab/Python/Octave/C++ for 2 reasons. First, you will be able to validate the number of bits needed so that your fixed-point algorithm behaves similarly to the floating-point arithmetic algorithm. Secondly, you will be able to compare the FPGA implementation to your fixed-point model. The FPGA implementation should behave exactly the same as your fixed-point model.