DDS - Supersampling above the FPGA clock frequency
So, as far as I understand your system, you've basically taken your target sample stream and decomposed it into 8 polyphase components; thus, each DDS runs at $\frac18$ of the target 1600 MS/s rate, i.e. at 200 MS/s.

Thus, the phase increment that a single DDS does per sample it produces is 8 times the phase increment of the interleaved samples.

Thus, if you wanted to produce a wave at 200 MHz, that means one period of the output would take 8 samples; therefore the output's phase difference between successive samples is $\frac{2\pi}8=\frac\pi4$. And thus, the period, from the point of view of the individiual DDS has a period of 1 sample, meaning $\Delta_\phi =0$! That makes sense: if you want to produce an exact 200 MHz wave, your 8 polyphase components would always be the same samples of a sine wave period. 

So, your behaviour is fully expected. When your output frequency is 200 MHz, the individual DDS'es frequency must be 0. You basically work based on aliases.

This has nothing to do with integer overflows, but is just like the math for polyphase signal generation is. 

So, nothing wrong here, you'll just have to figure out what the right phase offset per DDS is.