Sampling rate vs ADC noise tradeoff
In theory, a 4x oversampled quantizer with n-th order noise shaping feedback, is capable of providing you equivalent bit savings (wrt a direct quantization of the critically sampled signal) of 1 bits for n=0, 2.2 bits for n=1, 2.9 bits for n=2 and 3.5 bits for n=3 (this list goes further but in practice high order noise shaping feedback is difficult to implement due to potential instability)
Note that spectral shape of quantization noise (or analog noise present before sampling) is an important factor in achieving these gains. (Table excerpted from ch.4,section 4.9.2, Discrete-Time Signal Processing 2e, A.Oppenheim)

The mathematical exposition of this fact is a little long but you can find them in many DSP books which include an indepth discussion of sampling and ADC strategies...

In rough terms doubling the awgn noise power would yield 3dB SNR loss which is equivalent to a loss of less than 1 bit of linear uniform ADC. So you could expect SNR gains for feedback orders of n=1 or higher. 

However the question is whether you can embed that sensor into the noise shaping quantization loop in a practically convenient way or not? If you can, then certainly go for 4X oversampled case. If your project is restricted in resources such that you cannot afford for such added DSP cost, then stay at the 1X rate.