About how to increase the FIR filter sampling frequency in FPGA? And what is the tradeoff of increasing the sampling frequency?
Does the “one tap” delay equal to “1/Fs (sampling frequency)”?


Yes


  If I have N-tap, the total delay will be N/Fs?


Depends on how you define "total" delay, but in general the answer is no. For a minimum phase filter the delay will be 1. For a linear phase filter it would roughly be N/2


  If the Fs sampling frequency is increased, the “one tap” delay is decreased?


Yes. But it also changes the frequency response of your filter. 


  Is there any trade off/drawback of increasing the sampling frequency?


Many. It really depends on what the requirements of your application are.