Band-edge timing error detector, time accumulator
Thanks for your hints and answers. That helped me.
Ive got my code to work now. Its not fine tuned but here is my solution:
-As loop filter i use a PI Filter with a relatively low Ki.
The loop filter is just updated at a 1 Sps/Sym rate when the time accumulator gives an overflow.
-The time accumulator is a modulo interpolation controller
-The interpolator is a farrow structure for cubic interpolation
The IQ plot isn't stationary because the phase isn't locked. But i wont add a following pll anyways because it is a pi/4-DQPSK signal. A bit of phase shifting shouldn't bother me