How to plot noise shaped spectrum of First order Incremental Sigma Delta ADC's output?
Update: as Sundar commented his question is specific to the “incremental Sigma Delta ADC” of which I only have a vague understanding of. To the extent the incremental implementation is a traditional Sigma Delta ADC that is reset periodically I would believe this model still applies as described similar to using a moving average frequency response to model an integrate and dump. Comments welcome.



Below is how I use an equivalent loop equation to model the noise shaping in first and higher order Sigma Delta architectures. This is qualitative since the quantizer is highly non-linear (So would a apply from a small signal perspective, and can be further more accurately approximated with a piece-wise linear approximation to the quantizer gain.

Below shows continuous time equivalents, with $N_q$ as the quantization noise input from the 1 bit converter. The discrete time equivalent is easily derived by mapping the integrator. An integrator using either Backward Euler or Impulse Invariance mappings both result in:

$$\frac{1}{s} \leftrightarrow \frac{T}{1-z^{-1}}$$