80-tap Decimation Filter: divide into stages? / Cost of having a number of taps
Does the number of taps affect a cost of implementation of FIR?

Well, insert your definition of &quot;cost&quot;, and your question should really answer itself.

FIR filters belong to the class of linear filters, the combination of N lower order filters can create the desired FIR filter of the higher order. So I was thinking If it makes sense to implement the combination of N lower order filters instead of a one 80 taps filter?


Is the decimation implemented in one stage usually?

Indeed, splitting decimation into multiple stages is something that is commonly done, because then only the first filter needs to run at the highest rate.
Now, 80 taps is not what we'd usually call a large filter, so yes, you can do that splitting, it's even advisable.
However, it might really be premature optimization: Your FPGA is probably fast enough to do all 80 MACs at full rate, and it doesn't even have to do that, seeing that you're building a decimating filter, so everything but the most naive implementation would be a polyphase filter implementation, which reduces your complexity to 80/(decimation) per input sample. Seeing that your filter is only 80 taps long, you're probably also not aiming for a very high decimation, anyway.