Digital Signal Quantized Processor Complexity
First, if there's a more formal way to do this than what I'm going to show, I don't know it.

Call out the MAC operations along with data path widths.  I.e., &quot;the FFT algorithm used takes $4 n \log n$ operations with 24-bit wide data paths&quot;

A corollary to this would be that sometimes you may have different precision in your coefficients and your actual data.  So you may call out &quot;24 bit signal path, 16 bit coefficients&quot;.


Call out the LUTs used (in an FPGA).  This isn't direct, and has a lot to do with the cleverness of the implementation, but within a specific FPGA technology it has meaning.

Note that these days, unless you're doing full-custom ASIC design, data paths come in chunks - processors give you multiples of their native word width, and FPGAs come with &quot;DSP blocks&quot; that come in fixed widths.  I'm only guessing, but I'd bet money that if you go to design an ASIC then at the first level of design complexity there will be signal processing libraries with their own fixed-width data paths, and that libraries with variable-width data paths would take more engineering resources to use.