What does an ADC DNL specification mean, exactly?
Differential non-linearity specifically is the deviation from ideal between successive bits. For an ADC, the ideal would be the converted signal will not transition to another bit value until the input deviates by 1 bit. If the DNL is greater than 1 bit, non-monotonic behavior could result (an linearly increasing input could result in some transitions actually going down). 

If the spec claims ±1 bit, this is a absolute maximum limit and is therefore guaranteeing monotonic behaviour. The "typical" limits are not so stringent in what that means and you would need to ask the manufacturer directly, but in essence it is what you could typically expect, on average (so therefore could be the the mean of the absolute value of the deviation). 

Similar to if I said I had a 9V battery that had a spec of +/-0.5V and provided 9V typical. The average is 9V, the peak limit that the manufacturer will guarantee is 8.5V to 9.5V; now as far as the statistics that is completely up to them in balancing yield at final test in what they will ship.   

If I was to model this, I was first tempted to generate a Gaussian random sequence with a standard deviation of $\sigma = (0.6) 4/\pi$ and clamp it at $\pm 1$ since the mean of the absolute value of a Gaussian R.V. Is $(4/\pi)\sigma$... but the clamping reduces the mean, so increasing that to $\sigma = (0.7) 4/\pi$ results in a random (clamped Gaussian) distribution that never exceeds ±1 but also has an average magnitude (therefore typical) of 0.6.