simulating multipath via tap delays in FPGA
Perfect destructive interference is possible in theory, but very difficult to do in practice without feedback to dynamically adjust.  The reason for this is that there are three things you have to get just right to eliminate the tone: frequency, time (or equivalently, phase), and amplitude.  If you get any of those wrong there will still be a tone (or rather, two tones) left over.

Frequency  No matter what you do at the baseband level (i.e. in the FPGA), the frequency will not match if your upmixing does not exactly match your downmixing.

Time/Phase  This is a lot more complicated than you realize.  First, your phase-per-tap calculation requires that the sinusoid be exactly 2.462GHz and that your FPGA frequency be exactly 200MHz.  Neither one is.  You can never get an exact frequency, there is always some error and jitter.  If you take the derivative of the phase-per-tap with respect to the sinusoid frequency (2.462GHz), you will find that the phase per tap is very sensitive to sinusoid frequency errors.

You have also not taken into consideration the time delays through your ADC, DAC, and connectors, passive analog components, etc.  They all matter too.  Long story short, I would not try to figure out the correct delay, I would empirically see how the jammer's phase relates to the original sinusoid and adjust from there.  Yes, you will almost certainly have to use fractional delays.

Amplitude  Even if you get the frequency and phase right you will only be changing the tone's magnitude unless you match its amplitude.

I hope that see that you have taken on a very difficult task.  Since you are only trying to test simulated delays, I would find an easier way to do that.  I would look at using chirp signals, and then vary the delays to move the responding chirp in time.