How does the world's simplest sigma-delta DAC work?
This is just a first-order sigma delta DAC with the input as an unsigned binary number. The classical variant with a signed digital number is shown below where the MSB as the sign bit would subtract (Delta) from the input. In this signed variant, consider the input being a scaled digital number ranging from +/- Full Scale, and the feedback would either be +Full Scale or -Full Scale; in this case the accumulator can count up or down with a ramp rate based on the difference between the actual input value and +/-Full Scale with the output toggling when the accumulator output crosses midrange.
In comparison for the OP's case, the input is unsigned and the accumulator grows only in the positive direction with a ramp rate based on the difference between the input and +Full Scale. When the accumulator overflows, it is reset to 0 plus the overflow, which is essentially subtracting Full Scale (which is the Delta in this case).

This has all the drawbacks of any first order Sigma Delta: lower noise supression than a higher order architecture (-9 dB/octave) requiring a higher oversampling ratio to achieve a desired equivalent number of bits, and suffers from pattern noise leading to higher spurious content if the input is not changing.