clock + phase recovery
A receiver needs to synchronize on those two timings in order to demodulate with best performance:

Transmitter symbol rate
Transmitter carrier

Synchronization state of the art way is to use a PLL. You need two loops processing at the same time. The same PLL architecture can be used for both synchronizations but instantiated separately. That is the case for the filtering part of the loop.
Except:

Each loop has a different timing error detector: One detects symbol rate error and the other carrier phase error. Different algorithms for each.
The feedback correction is applied in different areas in the chain: Symbol rate feedback is applied on a resampler, carrier error correction where the frequency translation is done.

Also important, a PLL is a fine synchronization. Which means that if you have a too large offset it won't be able to synchronize alone. A process ahead in the chain should perform the coarse synchronization.
Timing error detector for each loop should be smartly selected. As they can interfere between themselves. For example Gardner when applicable is able to estimate the symbol rate timing error with a carrier phase offset inside.