Sample and Hold Circuit at Digital to Analog Converters
The output of a DAC represents a zero-order hold (equivalently called a sample and hold) of the digital input samples: each sample is held at the value in the analog domain for the time duration between samples. There are also other DAC implementations such as a RTZ (Return-to-zero) DAC which brings the signal back to zero midway in the duration. 

The zero-order hold is equivalent to convolving in the time domain the digital samples, which represent impulses in the time domain, with a rectangular pulse as wide as the time duration between samples. Convolution in the time domain is multiplication in the frequency domain, and therefore the DAC output will have a "droop" over frequency with the magnitude going to zero as the frequency approaches the sampling rate. The RTZ implementation moves the first zero out to twice the sampling rate, at the expense of signal loss.

See pages 13 and 15 of this TI presentation for more details: https://training.ti.com/sites/default/files/docs/TIPL4705%20-%20DAC%20Output%20Response.pdf