SNR of a 16-bit DSP with 12-bit ADC, 40-bit accumulator
Let me add the following additional important consideration to dynamic range on the ADC side of the equation to the other answer provided. 

The SNR as characterized with a full scale sine wave for a typical (uniform quantization noise) ADC is well established to be given by the following relationship: 

$$SNR = 6.02 dB/bit + 1.76 dB + 10 Log(N)$$

(For more on how that equation is derived, see What are advantages of having higher sampling rate of a signal?)

Which demonstrates the consideration given for oversampling to dynamic range.  (And just to mention, there are other ADC typologies such as Delta-Sigma with noise shaping offering even more dynamic range improvement due to oversampling; however in any case the sampling and the distribution of the quantization noise is limited to the architectural implementation of the ADC itself). 

The example below illustrates this with a 10 MHz BW signal at a digital IF of 25 MHz, sampled at 100 Msps.  This example was done with Analog Devices HMCAD1520 which is a 14 bit ADC with a SINAD (Signal to Noise and Distortion) of 72.5 dB. 72.5 dB translates to an ENOB (Effective Number of Bits) of 11.8 (using the same 6dB/bit+1.76 dB equation). This means that with a full scale sine-wave, the additive noise due to the ADC sampling process will be 72.5 dB lower than the power level of the sine-wave itself. However this noise, well approximated as a white noise source is spread evenly across the sampling spectrum. Thus as shown in the figure below, the portion of the noise that is within the bandwidth of the signal is 1/5 or -7 dB lower.

The rest of the noise, out of the band of interest, can be filtered out in the DSP, down to the limits of the datapath (unless special provisions are made to effectively increase the datapath precision as suggested in the other answer). For this filtering purpose, extended precision accumulators are particularly important, as described in more detail in other posts.  (for example, see what is the suitable design Method to the filter?)

Some of the distortion is in spurious frequencies, but referring to the datasheet for this device, the SFDR (Spurious Free Dynamic Range) is 83 dB, so in this specific case, with this oversampling rate, the dynamic range will not be limited by spurs.  



So given a sine wave at full scale (to establish a consistent metric point), we can establish the ADC noise floor.  However for dynamic range, we also need to consider the headroom required for a modulated signal. For this reason I have created the following graph which is applicable to Gaussian distributed waveforms in magnitude (such as OFDM and CDMA both of which are well approximated by Gaussian distributions), and shows the optimum set point in rms level below full scale in order to maximize dynamic range for the case of a modulated waveform based on the number of bits. This is applicable throughout the digital system everywhere in the datapath, not just at the ADC, so is a very important consideration. This shows specifically the effect of clipping noise as the rms signal level approaches full scale, and the effect of quantization noise increasing relative to the signal, as the rms signal level is reduced from full scale.  The term "dBFS DC" is the level in dB below full scale of a DC signal (a sine wave at "0 dBFS" is -3dB below '0 dBFS DC"). The 0 dBFS DC mark is also applicable to full scale for a single tone in a complex datapath (with I and Q).