How to separate Even and odd part (in-phase bit streams I and quadrature-bit streams Q) of the signal?
The OP is mis-understanding how this QPSK signaling scheme operates.
There is a stream of input bits $b_0, b_1, b_2, b_3, \ldots,$ that is coming serially at the rate of one bit every $T$ seconds, so $b_0$ during $[0,T)$, $b_1$ during $[T,2T)$, and more generally, $b_n$ during $[nT, (n+1)T)$.. So, there is a clock signal at $\frac  1T$ Hz at the input.
The first thing that happens is the serial-to-parallel conversion where the serial bit stream gets converted into a stream of dibits (two bits in parallel), one bit on each of two individual wires and each bit lasting for $2T$ seconds (that is, the dibit lasts for $2T$ seconds.  Thus, we have
$$(b_0, b_1) \to \left[\begin{matrix}b_0\\b_1\end{matrix}\right], \quad (b_2, b_3) \to \left[\begin{matrix}b_2\\b_3\end{matrix}\right], \cdots \cdots
(b_{2n}, b_{2n+1}) \to \left[\begin{matrix}b_{2n}\\b_{2n+1}\end{matrix}\right], \cdots$$
So immediately we need to understand that

The output of the serial-to-parallel converter is clocked at with a clock at $\frac{1}{2T}$ Hz, and this clock is synchronized with the input clock of the serial to parallel converter,
There is a delay of $2T$ seconds in that $\left[\begin{matrix}b_0\\b_1\end{matrix}\right]$ is the output of the serial-to-parallel converter during $[2T,4T)$,  $\left[\begin{matrix}b_2\\b_3\end{matrix}\right]$ is the output during $[4T,6T)$, and so on,
The &quot;even bits&quot; have been sorted into appearing on the upper wire and the &quot;odd bits&quot; on the lower of the two wires, just as is envisioned in the OP's diagram. These are the Inphase and Quadrature branches of the transmitter.

The dibit enters into the direct-sequence modulator which says multiplication but this is if the bits ($0$ or $1$) have been converted into real numbers $+1$ and $-1$ respectively, and ditto the PN sequence. The logical operation with $0$s and $1$ is the XOR operation: the bit $b$ lasting $2T$ seconds is replaced by a serial stream of $N$ bits $(b\oplus \text{PN}_0, b\oplus \text{PN}_1, \cdots, b\oplus \text{PN}_{N-1})$ which last for a total of $2T$ seconds.  Thus the PN sequence generators (usually different ones in the I and Q branches) are clocked at $\frac{N}{2T}$ Hz, and this clock is also synchronous with all the other clocks.
Everything is digital up to this point. To get the actual transmitted signal, the $0$s and $1$s are mapped to $\pm 1$, each rectangular pulse (of duration $2T/N$ seconds in the direct-sequence QPSK system) is replaced by the desired baseband pulse shape (e.g. root raised cosine) to get the complex baseband representation $I(t)+jQ(t)$ of the QPSK signal. The actual RF signals in the I and Q branches
of the transmitter are $I(t)\cos(2\pi f_c t)$ and $-Q(t)\sin(2\pi f_c t)$ where $f_c \gg \frac{1}{2NT}$ is the RF carrier frequency. Thus the actual RF QPSK
signal is of the form
$$s(t) = I(t)\cos(2\pi f_c t)-Q(t)\sin(2\pi f_c t) = \text{Re}\big((I(t)+jQ(t))\exp(j2\pi f_ct)\big)$$ and results from modulating a (spread) dibit onto an RF carrier. Dibits consist of two bits; all Americans know that make two bits make a quarter, which explains why they think that the Q in QPSK stands for quaternary instead of quadrature or quadriphase.....