Is the common FIR Filter delay line (see pic) also valid on purely logical FPGA implementations?
I'm not sure if I understood our question right, and therefore sorry if I point something wrong, but the delay in the delay line comes from signal sampling and not from computational processing type. Therefore whether you realize that signal flow graph in a von Neumann type serial architecture or in aparallel FPGA based architecture doesn't matter. You will always have the delay per input sample as dictated by your systems sampling rate. 

On the other hand of course a parallel implementation would take much less clock cycles, based on the amount of parallelisation, to compute per sample output campared to a serial architecture of a general purpose CPU, however as I said the delay in the delay line is nothing related with computational delay of the hardware system.

Finally the signal flow graph yields a pictorial representation of processing structure, you don't really implment those delays. They are represented by registers or memory locations, as possibly you know, which are updated either per sampling clock or via buffer copies which provides that delay effect represented in the flow graph.