Multiplier in digital signal processing?
Once upon a time, chips (processor ICs) did not have anywhere close to millions (now billions) of transistors on them.

A typical fast multiplier, say made out of a tree of layers of carry-save-adder cells, requires a lot more logic gates (thus transistors) than a simple adder, thus also requiring a lot more power, and with less of them fitting on a particular silicon die area.

Repeated conditional-add-and-shift is slower (in the same transistor technology) but requires a lot less logic gates (thus less transistors) when done sequentially.

If an (ancient) FPGA has tons of small memories (but no multipliers), the memories might be useful as look-up tables that are faster than the equivalent logic equations implemented in fabric connected LUT cells.