Apply decay envelope to waveform without multiplication
There are other methods if you can't support direct hardware multiplication, but you're going to have to sacrifice something. For instance, if you have multiple clock cycles to spare, you could use an iterative approach. C-like pseudocode:

accum = 0
for (i = 0; i &lt; LENGTH(envelope); ++i)
{
    if (((envelope &gt;&gt; i) &amp; 0x1) == 0) accum += signal &gt;&gt; (i + 1)
}
// "accum" now holds the multiplication result


Translating the above functionality to Verilog is an exercise left to the interested reader (it's been a while since I've written in that language). This scheme essentially performs long base-2 multiplication using additions and shifts. For each bit that is set in the envelope scaling factor, an appropriately-right-shifted version of the signal sample is added to the accumulator. The result of the multiplication is held in the accumulator after the loop is complete.

As I said, this isn't the most efficient approach in the world; it's probable that a good synthesis tool would come up with something better even on a device without hardware multipliers. This method trades resource usage for latency in the form of extra clock cycles required to perform the iterations of the unrolled multiply. I'm left to wonder what drives the no-multiplication constraint in your application. Could you add more details on that? 

Note: You may need to tweak the amount of extra shift that you apply to the signal when adding to the accumulator based on the numeric format of accum and signal. If they are both of the same fixed-point format (like Q15), then the above approach should work properly.