Question about a diagram of PWM detection
From the diagrams, the integrator is reset to zero (sometimes this will be called "dumped", as in "integrate and dump") right after its value is sent to the hold.

The reason that I can see for doing this is that it appears that the leading edge of the PWM happens on a steady period, with the trailing edge varying to establish the width.  By sampling on the "A" pulse you insure that the timing of the PAM pulses is consistent; sampling on the "B" pulses would mean that the timing of the output would depend on the    amplitude; this would induce a nonlinearity.