How to properly match bit growth of a FIR filter with a reference value
I've worked a lot with FIR and IIR filters in FPGAs, here are a few pointers

1 - Keep track of your bits and their respective weights.

2 - Keep track of your filter gain and the number of bits for the coefficients. For example, assume you have a 14-bit signed input. Your input can go from +16383 to -16384. Now you filter it in a 17-taps FIR low-pass filter (for example), its DC gain should be '1'. Assuming 16-bit coefficients, and no coefficient greater than or equal to '1', the sum of the coefficients should be 32768 (2^15). It could be slightly smaller, it doesn't really matter, especially if you round the output. However, it is possible, that because of the scaling, the sum of the coefficients could be 32769, 32770, etc. In this case your DC gain would be slightly bigger than unity and you will likely need guard bits.

3 - Assuming there can be no overflow at the output of the filters, now you need to determine how many "fractional bits" you need to keep. There are no simple answers. Assuming no decimation, it could be a good idea to keep the output format the same as the input. For example, 14-bit input with 1 sign-bit ---> 14-bit ouput with 1 sign bit. However, please round the data before truncating, otherwise you could insert some DC offset or other unpleasantness.

4 - If you decimate, one of the reasons why could be to increase the resolution of your data, in this case your output should have more fractional bits than your input.

5 - If your filters have a gain higher than 1 (on purpose, not because of quantization), such a resonant IIR filter, you will need to implement the appropriate number of guard bits. For example, you add a 20 dB-gain at a certain frequency, you will need 4 additional guard bits at the output.