Design of a low pass filter with Red Pitaya's FPGA
There are 2 steps for the solution
Step 1 - Design some kind of low-pass filter to measure the DC component.
In order to perform step 1 you need to answer a few questions :
What do you mean by DC? For example, measure the DC for the last 10 seconds?
What is the input sampling rate? What is the desired output sampling rate?
You need to provide this information, we cannot guess it for you.
Step 2 - Implement the filter in Verilog.
There are examples on opencores. I can also give you a hand if you need help with implementing a FIR or IIR filter in Verilog.
You could also look at the Xilinx FIR Cores in the Core generator.