What is the term for this construction of ADC?
It is called a digital ramp ADC.
The specific ADC described by the OP does not have a sample-and-hold and relies on the input signal being steady but there is no reason it couldn't have one. It just compares the input signal to the output of a DAC with a comparator, and it ramps up the DAC value and whenever the DAC output just exceeds the ADC input, it latches the DAC input to the ADC output. Then it restarts the ramp. As a result, it has latency that varies based on the input value which is not a desirable trait.