Delay circuit having different high-to-low and low-to-high delays
I think the problem is simply that the pulse is too short to charge the capacitor fully. I created a simulation using CD4000 series inverters at a time scale long enough that propagation delays are insignificant, and with an external resistor to ensure symmetrical output resistance. It showed the same effect as your circuit. 

 



With this short pulse length (relative to the delay time) the capacitor barely has enough time to charge above the gate input threshold before the pulse ends, then it only has to discharge a little bit to get below the threshold again. The result is much shorter delay after the falling edge of the pulse than the leading edge.

If the pulse was longer or the on/off ratio was closer to 50% the delays would be more symmetrical, but if you need to delay a short intermittent pulse while maintaining its width this technique is not suitable.