VHDL synthesize std_logic 'H'
There won't be a universal answer except &quot;no&quot;.
But check the synthesis guide for your chosen FPGA in case it is an exception (can synthesise 'H' to an internal pullup).
You'd be better treating the output and input aspects separately on your cores (SDAout/SDAin) and combining both/all SDAouts (which are '0' or '1') in logic gates in the top level design, and feeding the result to all SDAins. (Ditto SCL to handle clock stretching).
This mimics the strategy of avoiding bidirectional internal buses with Data_Out/Data_In buses and multiplexing in the top level design.