Error when passing wire of different size to module input
Have you looked at what is being synthesized? You are performing some math (modulo) operations on the output. Inside your UART RX module, the received byte is probably in a buffer of some type. If you don't have a storage / stated up element of some type, you're asking your FPGA code to combinatorially operate on your receive data and complete all operations before the next byte comes in. Using 'out' there passes 8-bits of data raw to your display module and probably infers quite a few latches.

By registering your data (I note you used the word 'copy' -- I take it you are a computer programmer branching into FPGA?), you are increasing latency slightly but you have now stored data in a stateful manner and provided a clocked, synchronous system during which things can be done.