Input decap in switching regulators
suppose your swtich handles 1 amp in 10 nanoseconds. the dI/dT = 10^+8 amp/second

Now have a total of 100 nanoHnry inductance in the input loop: the Vin wiring, the Ground wiring, the capacitor wiring, the PCB?, the switch/FET wiring.

What will be the voltage spike?

Vinductor = L * dI/dT

Vinductor = 100nanoHenry * 1 amp / 10 nanoSeconds

Vinductor = 100 / 10 = 10 volts

Have the VDD wiring OVER the Ground plane.

Have the FET drain wiring over the FET source wiring.

You must design the wiring, for minimum enclosed area.