Pipelined designs with outputs in differentes delay clocks
If the design is fully pipelined, skipping later pipeline steps doesn't gain you anything and introduces flow control problems. That's why it's uncommon.
If your design consisted just of this one component, adding a second output port that reports results early if possible would be easy, but it would make life harder for the surrounding components that now have to integrate two streams of result data where results may appear on both during the same cycle.
If I were tasked to design the surrounding logic, I'd probably look into your component and see that it has a guarantee that nine cycles after a result on the &quot;early&quot; path there will be no result on the &quot;regular&quot; path, so I can just delay by nine cycles and merge without introducing a FIFO (which would have additional error states).
The other issue is that if results arrive out of order, I need a tagging system to identify them, which adds even more logic.
Out-of-order processing is often done in black box models, e.g. if you have a bus system like PCIe, the components send packets to each other and responses are generated as they become ready -- for example an access to main memory could be satisfied immediately (as the memory is mapped and the mapping is cached), with a slight delay (the memory is mapped, but the mapping needs to be looked up) or with a long delay (the memory is swapped out and needs to be brought back from the harddisk) -- but these are generally high-level operations.
Again, the premise for all of this is that this is a fully pipelined computation that is optimized for throughput (i.e. one input, one output per cycle).