How do I represent in Verilog a circuit with a resistor?
You can't represent arbitrary resistors in verilog as resistors are analog and verilog is digital (as opposed to verilog-a, which is analog).  However, you can model pull-ups with the pullup primitive, like this:

pullup p (some_signal);


There is also a similar pulldown primitive that pulls to 0 instead of 1:

pulldown p (some_signal);