Logic gates - Creating a Digital counter
Your second schematic is almost a direct replacement of the DFF in the first schematic. The convention for the clock of FF is positive edge triggered (output change on positive edge). But the bottom schematic's FF is negative edge triggered and the clock label should be \$ \overline{CLK} \$ or equivalent.

Therefore, if you take four copies of the bottom schematic, insert them in place of the DFF above while inverting each of the clock, then you have the equivalent of the top schematic (which is a 4-bit ripple up counter) in discrete gates.

By the way, the explanations of flip-flops found on the Web are full of errors.



Response to comment:

In your comment, you have included a schematic that have the equivalent of two flip flops. To make that into a two bit ripple counter, you need to make some corrections, as in here:



By feeding-back \$ \overline{Q} \$ to D, the connection causes the FF to toggle at the active clock edge. By connecting the output of the first FF to the clock of the second, the two toggle FFs become a 2-bit ripple counter.