Register File for MIPS Processor
I'll turn my comment into an answer.


I strongly suggest you start using a wave-form display for debugging. You can not debug HDL code with $display and $write statements once you get past trivial examples. 
I noticed that your clock and data have the same delay: clock changes every #5 and your data at #10 and #100. Your clock edges and signal arrive at the same time which is a recipe for disaster. 
Unless this is a school assignment which forbid this, you should use HDL constructs (I am using different names but you should get the gist)


    reg  [31:0] regbank [0:3];
    wire  [1:0] write_index,read1_index,read2_index;
    wire [31:0] write_data;
    ..
       if (WriteReg)
          regbank[write_index] &lt;= write_data;
       read_data1 &lt;= regbank[read1_index];
       read_data2 &lt;= regbank[read2_index];
    ..



Designing logic on rising and falling edges should be a used only as last resort and only if you really know what you are doing. In normal design it is a big NO NO! 


In the example above you can do write forwarding like this:

   if (write_index==read1_index)
      read_data1 &lt;= write_data
   else
      read_data1 &lt;= regbank[read1_index];
   if (write_index==read2_index)
   ....