Is there anything macro-like, in VHDL?
I would advice to use a procedure over a function for this, since putting this in a function results in impure functions, which always bring along a number of issues. Procedures are exactly what you describe here. Syntax for your example:

procedure proc_do_something(input_a : in integer range 0 to c_argument_max,
                            output_b : out integer range 0 to c_argument_max) is
begin
  counter &lt;= counter + 1;
  output_b &lt;= input_a &amp; other_input;
  other_output &lt;= input_a;
end procedure proc_do_something


Definition is done between the is and begin of the process you want to use it in. I know declaration can theoretically be done in packages in case of blackbox behaviour, although I've never seen that done before.