How to place SDRAM data-lane correctly in 4-layer PCB?
The challenge with 4 layers is to maintain a good reference plane if you have to change layers. It's not impossible, but it takes planning.

Generally, use this stackup:


L1: Signal
L2: GND
L3: Power
L4: Signal


Try to route on L1 as much as possible. If you have to change planes, place a bypass cap near the signal via where the plane change takes place. This provides an AC return path for your signal.

DQ / DQM and DQS are the fussiest. Give them priority in routing, and use as few layer changes as you can (preferably 0, no more than 1.) CLK and address/control will generally route together.

That all said, you say '4 banks' - did you mean ranks? That is, 32-bit wide x 4 sets of chips? If your board is that big, do not consider 4 layers at all, the signal integrity issues will be all but impossible to surmount.

This may be useful to you: DDR bus design review