Is it possible to create a working JK-flip flop using gate level description in Verilog
Well, that certainly isn't what I would call a JKFF. I normally reserve that term for a true master-slave edge-triggered device. With your circuit, when J, K and clk are all high, the outputs will simply oscillate as fast as the simulator allows. (Actually, it will probably just tell you that no stable state can be found.)

There is no combination of inputs that will force your circuit into a known state. The usual solution to this is to make g2 and g3 into 3-input gates. Label the extra input on g2 as set_l (active-low direct-set input) and the extra input on g3 as reset_l. These will be able to force the state of Q and Q_not when they are asserted low, regardless of the state of the other inputs.