What is wrong with my 2-bit adder?
How does Logisim handle xor gates without exactly two inputs?  A two-input xor gate should have an output which is true if one input is true and the other is false, but it's not completely unambiguous from just that description how that should be generalized to N inputs.  The normal approach is to say that the output of an XOR gate of any size should be true if the number of "high" inputs is an odd number; I would consider any other meaning to be non-standard.  Nonetheless, it's possible that Logisim is defining "xor(a,b,c)" as being "and(or(a,b,c), nand(a,b,c))" (meaning at least one, but not all, of the inputs is true).  Split the 3-input xor into two cascaded two-input xor's and the circuit should behave normally.