Toggling the Output in VHDL
Read the Synthesis Style Guide for your FPGA.
Synthesis may use the closest type of FF available on the FPGA and there may be none that implement that precise functionality.
Also, look at the synthesised circuit, identify the FF that was used, and read its description (paying attention to what it does with S and R both asserted).
Not all valid VHDL is synthesisable, and the synthesis guide is there to tell you what can or can't be implemented.
A good useful guide is to follow the supported patterns for synchronous processes, as described in the synthesis style guide. These will work : deviating from them may sometimes work, but will not always be well supported by the tools.
And of course, a different synthesis tool or a different FPGA may deliver different results.