V1401 ADAT transmitter and PCM4222 ADC
The ADAT part is really odd ... I presume it's a relic of the 1990's Alesis ADAT 8 channel tape system. Anyway it appears (from the datasheet) to use a UART style interface relying on the relatively low jitter of a crystal generated 48 kHz LRCK. 

So it generates a 64*Fs clock and keeps it internal, relying on incoming data to appear on the pins at exactly the right time (stable around the middle of each 64*Fs period. (Page 3, figure 1 and text).

Which is what you need from the ADC.

Now the only way I can see to get that directly from the ADC is at Fs = 48 kHz, in left justified mode, with BCK freq = 64* Fs.

Which the ADC does not support in master mode (p.21)


  For the I 2 S and Left-Justified data formats, the BCK clock output rate is fixed in Master mode, with the Normal mode being 128fS


However the BCK pin can be an input, and BCK = 64*Fs is then supported:


  In Slave Mode, a BCK clock input rate of
  64f S or 128f S is recommended for Normal mode, while 64f S is recommended for Double and Quad Rate modes.


So I think you have to use the ADC in Slave mode. That means you need to supply it with:


MCKI : 256*Fs = 12.288 MHz
BCK  : 64*Fs = 3.072 MHz, with the correct hase relationship to LRCK
LRCK : Fs = 48 kHz.


Not difficult (ignoring any other consequences of operating it in Slave mode)
Now the real Master is your clock generator, which supplies LRCK to both ADC and ADAT.

Question 2 : how do I set WDCLKNEG ?

By referring to the detailed description on each datasheet, and noting carefully which channel is L and which is R on the ADC.

Then if the violins come blasting into your right ear, inverting it.



Leaving the big question : why choose the ADAT in the first place?