Synthesising "constant" in VHDL
No, for almost all synthesis tools there will be no difference.  

However, people with a background in ASIC design will discourage the use of initial values for signals and recommend the use of a resest signal to set the initial value. This is because for ASICs there is no configuration phase as for FPGAs and registers will usually be in an unknown state after power-on.  

For FPGAs some vendors will recommend the use of initial values instead of resets whenever possible, since this can result in lower resource utilization. This is because during the configuration phase of SRAM-based FPGAs, when the bitstream is loaded to the FPGA, each register can be set to an initial value.  

For simulation it will make no difference too.