Understanding basic computer hardware diagram of address decoding circuit
The tricky thing about the circuit is all of the negated signals.  If you construct a logic truth table for the inputs and output of each if the gates, you will see how the circuit works.  I assume this is homework, so I'm only going to do one for you, and let you figure out the rest.

I can't put bars over the negated signals, so I am using a leading ! instead.

For the top OR gate:

Address  !Read   !Read0

   0       0       0
   0       1       1
   1       0       1
   1       1       1


So you can see that the output !Read0 will only be active (0) if Address is 0 and !Read is 0.  For all other cases, !Read0 will be 1.

Note that the truth table above is the same as a NAND gate with inverted inputs, which is equivalent to an OR gate by DeMorgan's Theorem:



BTW the schematic is poorly drawn, there should be dots where the signals are actually connected, and no dots where the lines simply cross each other.  It is possible to make out what the intent is here, but for a more complicated circuit it would be impossible.