How can I layout these regulators to minimize board size and EMI?
If I pack the components as much as I can, what will the consequences
  be?


The parasitic resistance and inductance between components will go down, this will lead to less loss in traces and slightly better performance. 

The thermal resistance between components will also go down, because there is less copper separating components, leading to more heat from components on less area of the board, and the heat from components affecting other components 

In other words, you need to find out how much power is being dissipated in both regulators, and do a thermal analysis on the PCB (usually done with FEM software). In the least you need to know how many watts of heat are going into the PCB and space hot components away from each other. 

You should be fine on EMC if you follow the recommended layout patterns of manufacturers. They usually also post results of EMC on eval boards so you should expect similar results with the same layout.