PISO buffer for the MachXO2
Double-buffering shouldn't require a parallel copy. The normal technique is to have two blocks of RAM, and when you get your "trigger" or whatever criteria you have to switch buffers, you simply switch which block you're writing to.







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The switches represent multiplexers. In the current state, U1 is being written and U2 is being read. When your trigger occurs, flip all of the switches, and now you're writing to U2 and reading from U1.



If you're going to do this with FIFOs, the technique is similar, but there's a subtlety. Your problem description says that you essentially want to save the last 512 samples that were taken before the trigger, which implies that you will be throwing away data if the triggers are more than 512 samples apart. With FIFOs, you need to explicitly account for this, by removing data once they fill up. This is shown below with the addition of the AND gates.







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