An Explanation of CMOS Logic
It's actually quite simple, and it's based on two requirements:


Every node in the signal path must be connected to either Vcc or GND, to be at logical level 1 or 0 respectively;
There should never exist a conductive path between Vcc and GND, else it will short the supply and start draining a lot of current and possibly burning some parts here and there.


Therefore you must make sure that if the pull-up network is conducting, the pull-down is not. Hence their logical function must be the opposite.