Is combinational logic affected by the clock in FPGA?
If it is combinational, then not it is not affected by the clock.

For example in VHDL

COMB_PROCESS : Process(A,B)
begin
   Y &lt;= A xor B;
end process;


The sensitivity list is only useful for the simulation tools, it is not used by the synthesizer. So even if you put

COMB_PROCESS_WITH_WRONG_SENSITIVITY : Process(A,B, CLK)
begin
   Y &lt;= A xor B;
end process;


the result will be the same. Except your simulator will evaluate this process every time the clock changes which is not the best. 

And for your information, with simple combinational logic, it is often easier not to use processes instead :

Y &lt;= A xor B;