Introduce delay on a single bit signal w.r.t. input clock
That is not a correct way to add a delay. This technique will lead to missed pulses, or wrong pulse length. Bascially, here, you're just synchronizing your output every 4 cycles.

To make a proper delay, you need n flip-flops, n being the number of delay cycles you want to introduce. Make it an array: reg[3:0] bits;. Now, at each clock cycle (posedge / negedge, as you want), set the output to the value of the the last bit: vsync_o &lt;= bits[3]; and shift the whole array, inserting the current input value: bits &lt;= {bits[2:0], vsync};.

You don't need (and don't want) a counter. What you need to remember is the state for each clock cycle you're delaying. This is basically simply a shift register.

Edit: Okay, I was hoping it wasn't necessary, but here is the full code for a 5 cycles delay (did not try to compile it, though):

module SyncDelay( clk_27,vsync,vsync_o);
input clk_27;
input wire vsync;
output reg vsync_o;

reg[3:0] bits;

always @ (posedge clk_27)
begin
    vsync_o &lt;= bits[3];
    bits &lt;= {bits[2:0], vsync};
end //always

endmodule