FSM transition table from verilog code
What you called "the answer" I'd call a state diagram, not a state transition table. If the question asks you to produce a state transition table, I would not expect this diagram to be an acceptable answer. 
I agree with you that the outputs shown in the diagram don't match the Verilog code. You'll need to read your assignment carefully or check with your instructor to find out which states are supposed to produce a high output in your table.