Resolving an issue with syntax in SystemVerilog
The 1st compile error I get is related to the sel port.

In module mux4_test, change:

logic d0,d1,d2,d3,sel[1:0], z;


to:

logic d0,d1,d2,d3, z;
logic [1:0] sel;


sel[1:0] (unpacked) is not the same as [1:0] sel (packed).

The 2nd compile error I get is related to the mux2b instance.  Change:

mux2 mux2b(
.d2(d0),
.d3(d1),
.sel(sel[0]),
.z(w2)
);


to:

mux2 mux2b(
.d0(d2),
.d1(d3),
.sel(sel[0]),
.z(w2)
);


mux2 does not have d2 and d3 ports.

Your code compiles cleanly for me.  I do not see errors related to the Z port; here is the code on edaplayground



We concluded that the Z error was a bug in the user's simulator.  The OP updated to the latest version of ModelSim, and now all errors are gone.