STM32F4 Timer accuracy
As Tut was first to suggest, the observed error arrises from the fact that the total number of cycles in these dividers is one more than the value loaded into the corresponding register.

You took this into account in the prescaler register, but not in the period register.

When you apportion the net division equitably between the two stages, each has a moderately large value and so the effect of "off-by-one" is small.  

But when you apportion the division unequally such that one value is only 28, the difference between 29 counts (28+1) vs the correct 28 (27+1) is responsible for the 1-part-in-28 error you see.