Error handling two posedge signals in “always” block
I'm not sure why you need this functionality — there's almost certainly a better approach — but here's how I'd go about it. I hope the comments make it self-explanatory. I'm assuming that signal is slower than your 12 MHz clock.
module syncRX (
  input                 clk,
  input                 signal,
  output reg      [7:0] detect,
  output                clk_1khz
);

  freq_div div (
    .clk        (clk),
    .clk_1khz   (clk_1khz)
  );

  /* Bring &quot;signal&quot; into the 12 MHz clock domain and do positive edge detection.
   */
  reg signal_delay_a;
  reg signal_delay_b;
  always @(posedge clk) begin
    signal_delay_a &lt;= signal;
    signal_delay_b &lt;= signal_delay_a;
  end
  wire signal_posedge = signal_delay_a &amp; !signal_delay_b;

  /* &quot;clk_1khz&quot; is already in the 12 MHz clock domain; do positive edge
   * detection.
   */
  reg reference_delay;
  always @(posedge clk) reference_delay &lt;= clk_1khz;
  wire reference_posedge = clk_1khz &amp; !reference_delay;

  /* Increment the counter if either or both posedges occur.
   */
  always @(posedge clk) detect &lt;= detect + signal_posedge + reference_posedge;

  /* For simulation
   */
  initial detect &lt;= 0;

endmodule

The key concept is that FPGAs are highly optimized for synchronous logic, and you constantly need to keep in mind which &quot;clock domain&quot; each signal is associated with — or whether a signal is asynchronous altogether. If you want to combine signals from multiple clock domains, you need to pick one and bring the other signals into it via suitable mechanisms, such as synchronizers or FIFOs.