JTAG TAP Design code verilog( Advanced Debug Interface)
I'll start with the when/where to latch data question.

On the rising edge, sample TMS, TDI.
On the falling edge, TDO changes state. Additionally, by spec, when TDO is inactive, it should be High-Z.

So as you probably know, you enter a state on the rising edge of TCK. You may then perform an action as soon as the next falling edge, or the next rising edge (if you are still in the state). For your logic, your device should only consider the instruction 'latched' upon the completion of Update-IR. Section 6.2.1, Rule d) indicates that you shall latch the data from the register at the falling edge of TCK in the Update-IR state.

Now, as to why he used two registers, remember the structure of JTAG registers. During the Shift-xR phase, you're shifting through data for the entire chain. If you have a device with a 8-bit IR that is second in the chain, the entire chain length is actually 9 bits (assuming the first device is in BYPASS). Upon shifting in the correct number of bits, you then latch (I guess you could consider it a 'copy') the desired instruction into your internal state register.

My strong recommendation: if this is destined for production or silicon, purchase a qualified / validated JTAG TAP IP. Additionally, get access to the published specification. It takes some time to understand the nuances of the protocol, and a faulty JTAG implementation is the last thing you want in a production device.