k-bit signed multiplier
A simple approach would be to convert both factors to sign/magnitude representation. Be sure to use 1 bit for sign and 4 for magnitude to avoid overflow for the value -8. XOR the signs and apply that to the result. This can be done in another verilog module, wrapping your multiply4bits-module.

This combinatorial function will probably be optimized to something completely different when you look at the synthesis result. There are far better approaches when you want to optimize for resources or delay. Look at this excellent paper by Ray Andraka for an overview.

In your case, Booth's algorithm would be a good approach.