8bit shift left register with serial in, serial out implementation in verilog
HDL languages do not work like other computer languages. They all have what is called 'concurrent' assignments. Which means all assignments take place 'at the same time'. 

Thus tmp[0] gets the value si at the same time as tmp[7:1] get the value from tmp[6:0].


  Am I right?


No, I strongly suggest you study Verilog and VHDL in more detail.



I think I see where you are coming from.
In Verilog when there are multiple concurrent assignments, the last one wins.

Thus tmp[0] gets assigned a zero: tmp &lt;= tmp &lt;&lt; 1;
Next it gets assigned si: tmp[0] &lt;= si;
The last one overrides the previous.

I agree it is sloppy coding here. 

However there are cases where using that technique greatly improves code readability. I always add a comment like this:

...
... // big complex FSM 
...
// Overrides all previous assignments above!     
if (emergency_stop)
   state &lt;= FSM_IDLE;