Interlacing Verilog and schematic in a FSM
You don't say what FGPA or what tools you're using, so this answer can only be very generic.

You have to choose whether the "top level" of your design is going to be schematic (block diagram) or HDL (Verilog).

If schematic, then you need to instantiate your Verilog module as a block in the block diagram. The module ports in the Verilog code will correspond to "pins" on the block in the block diagram, and you'll wire those to the corresponding pins on the other IP you've already got there.

If HDL, then the block diagram containing your other IP must itself have external connections, which then become the module ports of a "black box" module that you instantiate in your Verilog top level module. Make the connections between this module and the rest of your FSM code using ordinary Verilog statements.