Naming of PLA and PAL
To summarize the link that jonk put in the comments: There are three ways to implement a generic programmable sum-of-products (AND gates followed by OR gates) function. In historical order, they are:


PROM Programmable Read-Only Memory - the word decoder (AND gates) are fixed, and the data (OR gates) are programmable.
PLA Programmable Logic Array - both the AND gates and the OR gates are programmable. This allows more complex functions than a straight PROM allows with a much more efficient implementation.
PAL Programmable Array Logic - the AND gates are programmable, but the OR gates are fixed. It was realized that the PLA was overkill for many simple functions that only needed a limited number of product terms per output, so fixing the OR structure allowed a much smaller chip.


The similarity of the last two names is mainly a historical artifact, and also probably a function of how the devices were marketed.