Timing two parallel lines on FPGA [Beginner]
Is my understanding correct ?


Even aside from your misunderstanding of "clock cycles", which has been addressed in comments, your intuition about propagation time is actually incorrect here.

The function you're describing would be implemented as a single 2-LUT for each bit of X (with the function Xout[i] = X[i] ^ NX), not as two separate combinational paths. The propagation time of the LUT is independent of the logic which it was synthesized from.

In practice, this 2-LUT would probably be absorbed into LUTs used for other logic surrounding this function.