multiple Open Drain UART over long distance
If I setup the TX lines of the slaves as Open Drain it works fine, but
  the signal doesn't have steep ramps. I thought this happens due to
  Pull-up resistors.   


Yes. Since the lines are said to be open drain, the lines goes high via charging a \$R*C\$. The capacitance is of the bus and the connected pins and the resistance is the pull-up resistance.  


  And I also think that is going to be better with 8 slaves on the bus,
  right?    


Yes to some extent (you will be increasing the capacitance in the other hand) but also consider the fact that lower the pull-up resistance higher will be the current the pins has to sink when sending a logic zero.


  Why doesn't that topology work if the TX lines of the slaves are not
  Open Drain?  


When the master is in listening state form on of the slave, if all other slave TX pins are in Push Pull state, as soon as slave outputs a low, there will be unwanted high current flowing from all the remaining slave TX pins to the TX pin of the transmitting slave. This is never ever recommended.. 


  Also I noticed that the edges of the signal was sharper. Why are they
  sharper in that case?  


Can you post the waveform? Maybe  the UART communication with push pull setting enabled.  


  And the Open Drain would make a voltage divider 2.52KΩ + 2.7KΩ. Which
  means with 8 slaves and Open Drain topology the signal will not go
  lower than 1V which is the threshold of the low level. Is that
  correct?  


Yes. If I assume that the series resistors you have connected are of 2.7 kOhms, then they do form a voltage divider for a logic zero. For logic One, they do not pose significant threat. When a high is sent on the line, there will a tiny bit slightly lower value than VCC. When a logic zero is sent, the level will be about a Volt.  Eliminating one series resistor (perhaps connected to master) will bring down the voltage levels into valid range for both logic high and low .
It will also help to increase the bus speed.


  What is the maximum baud rate for such distance?  


In a ideal no noise world, the baud rate is limited by the bus capacitance and the series resistor you have used. At 9600, the bit period is \$104 us\$ and let us assume we prefer to have rise time and fall time of 10% which will be about \$10 us\$. In this case, the allowed bus capacitance is \$\frac{10us}{ 2.7 kOhms * 3} \$. It depends on the cables used.


  The concern about signal integrity. 
  You have got it right.   


No world is ideal. The master UARTmay have to implement complex protocols for error checking and so on. I have personally implemented software upgrade feature FPGAs and DSPs present for multiple daughter boards and my best choice was LVDS. They are just channels. You can use UART itself with a new IC in front of UART will automatically translate things to the outside world which are immune to external noise and ground potential offset due to cable resistance and more. Please consider the last point. Explore more options. The final solution will be still UART but the cable just got a immunity option.



Please update all resistor values in the image and any missing voltage values.



Another suggestion to avoid multidrop:use a 1:8 Analog Mux DeMux. Think about it.