Edge-triggered flipflops - keep CP high or low, most of the time?
If you have a pull-up or -down resistor on the CP signal, you could save some power by making the idle state the state where no current flows.

If there is noise in your environment, and you can predict its effect (this is unlikely to be the case), then you could reduce the risk of disturbances by making the idle state the state that is less affected by the noise.

But otherwise, it does not matter at all.
For normal CMOS inputs and outputs, low and high signals behave pretty much symmetrically. For TTL, the levels are not symmetrical, but that does not matter if you interface only with other (TTL-compatible) CMOS devices.
Use whatever makes the rest of your circuit or your software simpler.