I'm designing a mod-3 asynchronous counter. The circuit is expected to count from 0 to 2 and the flip flops are set as soon as q become 3
Two big issues:


Do not have a flop asynchronously reset itself. This included indirectly through combinational logic. It might work in simulation (in your case it appears not to), but on FGPA/ASIC the pulse with has a good change of being too short and may case metastability. Adding delays to create a cleaner pulse is a band-aid; it may work on the conditions you try then unexpectedly fail with different routing, parasitic, or other deviations. It is also important to keep all asynchronous set/reset signals glitch free, else run the risk of unintended set/reset or metastability.
Do not use daisy-chain counters (where the q of one flop functions as the clock of another flop) are not recommended for real designs. They can have bad timing and glitchy outputs. Real flops have clock-to-q delays, you can mimic the delay in Verilog with a non-blocking delay (e.g. q &lt;= #1 ~q;). String a bunch of this together and you will see the it takes longer for the value to settle.
Daisy-chain counters are fine for learning but best if all the flops are driven by the exact same clock. Unlike point 1, a small daisy-chain counter is unlikely to cause major issues, but is a best not to get in the practice of using them.


Keep the design synchronous in one clock domain. Example:

always @(negedge clk or negedge rst) begin
  if (!rst) begin
    q &lt;= 2'b00;
  end
  else if (q &lt; 2) begin
    q &lt;= q + 2'b01;
  end
  else begin
    q &lt;= 2'b00;
  end
end