Why any modern CPU masks 5 lower bits in a CL register for shifting operations
As said in the 286 programming reference, they mask the count to limit shift and rotate instruction execution time. These did not have a barrel shifter. Basically the CPU would sit in a loop that shifts data and decrements CL until CL is zero. Earlier CPUs such as 8086 could accept 255 in CL so it would take just needlessly long to execute. And limiting to 5 bits is enough, as that allows shifting of 16-bit registers via carry.