How is a DRAM volatile with capacitors?
In both cases (EEPROM/flash and DRAM) a small (femtofarads) capacitor is used. The difference is the way the capacitor is connected. 

In the case of DRAM it is connected to the source or drain of a MOSFET. There is a tiny bit of leakage through the transistor channel and the charge will leak off in a relatively short period of time (seconds or minutes at room temperature). Generally the cells are specified to be refreshed every 64ms, so even at high temperature the data is reliably held. Reading the data is usually destructive so it needs to be re-written after every read. 

In the case of a flash or EEPROM cell as used to store configuration data, the capacitor is connected to the gate of a MOSFET. The insulation of the gate/capacitor is very close to perfect and the tiny charge will hold for many years, even at high temperature. The disadvantage is that some method such as quantum tunneling must be used to change the charge on the "floating gate", and that is a much slower process, far too slow to be practical for working memory. Reading is fast and non-destructive, at least in the short term. Using tunneling exposes the gate insulator to a relatively high voltage gradient and exposes failure modes wherein the cell will effectively wear out after a number of writes (typically specified as 10^3 to 10^6 or more).