Problem relating to FSM machine
You are writing Verilog as if it is a standard programming language. HDL languages work rather different. 


In your count section use non-blocking assignments. 
In your always section you are generating latches. The whole 'always' section should be controlled by a clock as you have 'memory' elements in there: You want the values of prev, temp and present to be 'remembered'.
It is common (good) practice to always use begin-end sections.
In your case it works because you have a single statement (if and case).
The Fibonacci sequence starts with 1,1 which is not in your code.
If you use non-blocking assignments, you no longer need the 'temp' variable:




prev    &lt;= present
present &lt;= present + prev;


Side notes:


A name like 'out' is not very descriptive. Even if you write short test snippets use descriptive names.  
It is bad practice to use always @( variable ) these days. It can lead to simulation synthesis mismatches. You should use always @( * ) or alway_comb.  
Comment as at the bottom of your example is rather superfluous:




//output logic   
assign out = present;