Why is serial output from shift register offset from others?
The QH' output of the shift register is offset because it does not become valid from the previous shift register stage value after the rising edge of the SRCLK. 

The reason your second stage works is because the QH' is setup almost a full clock time till the next SRCLK rising edge. It has the setup time requirement as would be specified as the tsetup time in the 'HC595 data sheet. Another timing parameter required for the 'HC595 is the thold time. If you look at the data sheet you will find that the hold time requirement for the SER_IN pin is less than the minimum delay time from the SRCLK to QH' of the previous chip in your daisy chain.

The reason the data sheet timing diagram shows the QH output offset from the QH' is because the QH output is changing after the rising of the RCLK. The TI timing diagram shows RCLK offset from the SRCLK.