How to size CMOS transistors
Here is the NOR that is probably being referred to:



In the state where both C&amp;D signals are high both of the lower NMOS transistors are on and thus discharge the "Out" node faster than a single NMOS could (in the case of when only one of C or D is high).

Basically you don't worry about it, because there are other more dominant effects.  And to fully get the fastest effect both C &amp; D must arrive synchronously within the rise time (ps for advanced processes).

The bigger issue arrises in the case of the upper PMOS transistors which are ~ 2.2X slower than the NMOS and are thus the limiting factor for the highest speed. Because they are in series, in order to match these transistors the Widths must be 2X (series) 2.2X (conductance) = ~ 4.5X wider for the same Gm.  This greatly dominates the area used as well as the Fan-in numbers.  This fan is effect will be a dominant effect as well.

Any associated timing numbers (propagation delays) are numbers that must be met, or are guaranteed.  If the device switches faster in certain conditions then it doesn't matter and is not designed for.

Or you can use a different structure.