Word alignment / bitslip in LVDS Receiver
When you use a frame clock, which in your case would be 200Mbps/8=25MHz, then there is information contained within the clock as to where the word boundary is, and you can (assuming you set the phase relationship correctly) know immediately which bit is bit 0.

When using a data clock, which runs at the same frequency as the serial data - i.e. 200MHz for 200Mbps, then you have no information in the clock signal as to where bit 0 is located. The PLL could lock at any clock edge and the deserialiser will start counting from there. In such situations, you need to implement link training logic to perform word alignment.

If the clock you are feeding in is 200MHz, and the data rate is 200Mbps, that means that you are using a data clock rather than a frame clock. As such there is no information from the clock as to where the word boundary is and will need to perform alignment.



The process of word alignment using link training is roughly as follows:


You send a predetermined pattern over the serial link - a value which when deserialised will only result in the correct value when deserialised with the correct word alignment. For example the binary value 11110000 is one such value.
In the receiver you deserialise the value and compare it with your test pattern. If it matches you are done.
If the value doesn't match your pattern, you perform a bit-slip - that is, you shift the data in the serial stream one serial clock cycle. The SERDES IP core you are using should have some form of bitslip or similarly named signal to do this. Once you have slipped a bit, go back to 2.