Activating components one after another
VHDL is a hardware description language...you don't activate components, you instantiate them. All of your components, the three ands and the voter, will be created and will exist forever (i.e. as long as the simulation is running or until you reprogram the FPGA). You need to change your perspective on "programming" with an HDL.

Having said that, a combinational component is essentially idle until its inputs change. You don't explicitly activate it, it just works concurrently and asynchronously along with all of the other combinational components.