VHDL--counter for 7 segment display
The first issue I can see is that you're using a "std_logic_vector" type for your counter. You can't increment a std_logic_vector type, and so the "+" operator you're using will be doing weird things. (I'm not completely sure what "000" + '1' would give you, but it won't be the integer addition you're hoping for.)  Use an unsigned type instead.

Secondly, by using an if statement with no else statement in your asynchronous (unclocked) process, you're inferring a latch. (The synthesis process has to find somewhere to store the value of the counter for the process iterations where it's not incremented). This is generally considered bad practice - you're not fully defining the behaviour of the process, and the synthesis of latches can be very inefficient, using lots of space on the FPGA.

This would be much easier to approach if you used a synchronous (clocked) process. You could then compare the current switch value to the value at the last clock cycle. This would also deal with the inferred latch that you have in your if statement. 

My counter process would look something like this:

...
signal counter : unsigned(2 downto 0);
...

process (RST, CLK)
begin
if RST = '1' then
    counter &lt;= (others =&gt; '0')
elsif rising_edge(CLK) then
    if KEY(0) = '1' and key_prev = '0' then
        counter &lt;= counter + 1;
    end if;
end if;
end process;

process (CLK)
begin
if rising_edge(CLK) then
    key_prev &lt;= KEY(0);
end if;
end process;


Switch bounce will be an issue which I've not addressed. You'll need to have another process which deals with that and outputs a debounced std_logic which you can use instead of KEY(0).