is it posssible to make a 4-bit up/down asychronous counter using jk flip flops, xnor gates and nothing else?
You're thinking too much. You don't have to use any sophisticated techniques for logic synthesis. It's not only possible to make the counter, it's very simple.
BTW, If the &quot;last&quot; stage is the most significant stage, and CLK is the signal being counted, there's no answer. All the less significant stages would need a faster clock, from somewhere. &quot;Last&quot; must mean the least significant stage.
Another hint (looking for another anonymous down vote): the answer isn't a counter whose next count is the current count minus 1 when the direction command changes from up to down, or to the current count plus 1 when the command changes from down to up. The giveaway is the given &quot;last&quot; stage. When the direction command changes it toggles the LSB before seeing the next clock pulse. The answer, then, only has to be a counter that changes from being an up counter to a down counter, or vice-versa, but not very smoothly.