Any way to build Analogue Multiplexers using MOSFETs or JFETs or BJTs
Here are two NMOS based analog muxes. I don't know how your resistor network looks like schematic wise, but I suppose you know how to glue it all together and make it work. So I'll leave that problem to you.  




Link to interactive simulation

You can make a transmission gate (TG) by tying 2x NMOS's source and gate together. 

If the input lives between -5 V and 5 V then you need to pull the gate above 5 V + the gate threshold voltage which in this case is 1.5 V. But the higher the gate is above the gate threshold voltage, the less Rd(on) you'll have. I chose 12 V because it will turn on the TG hard. 

To turn it off you simply pull the gate around the floor of the input voltage, -3.5 V will make the TG to start turning off. So I chose -5 V. 

Then there's some other NMOS around to act as boolean algebra + logic level converters to make it into a functional analog mux.

Concerns with this circuit that you should know about: 


The gate to source voltage will be flying all over the place, all from 17 (12+5) V to -10 (-5-5) V. It might be hard to find a NMOS with those voltage ratings. I haven't checked, but thought I'd mention it. 
I have absolutely no idea if it will introduce less than 1 ppm errors, I like designing circuits, so I did it because it was fun. If I'd want to be professional about it I'd demand your resistor network schematic. Maybe there's an entirely other way of solving your problem that is much more realistic. Who knows. 
NMOS and all other MOSFETs capacitances, so you are introducing quite a lot of capacitance to your signal, maybe your signal is quite DC, maybe it's AC, who knows. Maybe you can find a NMOS with low capacitances. 





Link to interactive simulation

This version uses two op-amps to set the gate to source voltage. This way you won't see 17 V and -10 V between the gate and the source. It's easier to find these kinds of NMOS. Now you can buy logic level NMOS. The problem with logic level NMOS are that they usually have very low maximum gate to source voltage and drain to source voltage.

The 100 nF is only there for simulation, in the real world you'll maybe have around 500 pF which is a part of the NMOS which you can't remove. 

The resistor going from the op-amp to the gates should be there so you turn it into a low-pass filter. You could add the 100 nF in, in case the op-amps are too slow, or is it too fast? I think there might be oscillations if there's no low-pass filter. Not 100% certain. 

Concerns with this circuit that you should know about: 


If your analog signal has high frequencies then the op-amps might have problems to follow it and will mess up the voltage at the gate. So make sure that your op-amps bandwidth is above whatever frequencies you are working with. 
When you set the input to 0 V, meaning that you want 0 V across a gate to source, then it won't get to 0 V because the TG deactivates itself when the gate to source is below the threshold voltage. You can see this in the image above where I set it to 0.5 V and get 1.384 V instead. It turned off itself at 1.5 V and then floated randomly downwards.




If anyone else sees any obvious mistakes or problems in my circuits, tell me about it. I'd love to hear them.