generic and generic map | total time delay for each files
Since the longest path in a half adder is only one gate, the delay of the entire circuit will be equal to the gate delay. In this case, the gate delay is 6 ns. The default values for gate_delay of both gate entities are overridden in the instantiations you write.

Note that your code will not work since and and xor are reserved words in VHDL. You will need to rename to something like and_gate and xor_gate

Another side note: VHDL code like this is only used for gate level simulation with timing annotations, usually after synthesis and place and route. If you want to write an adder in VHDL, you should write a &lt;= b + c;