Problem mapping VHDL onto development board
The problem is statements:
if(rising_edge(Set_Button) and Set_Button = '1')
.
.
if(rising_edge(Enable_Button) and Enable_Button = '1')

When you synthesise this code, the synthesiser recognises these two signals as the clocks in your design.
These are also Input Ports in your module. If these signals were truly clock inputs in your design (which I don't think you intended to do so), you should map these to Clock Capable Pins in the FPGA. Otherwise the synthesiser won't be able to use dedicated clock routing from the respective IOs thru BUFGs, to the flip-flops clocked by them. Hence, the error messages.
Well, anyway I don't think you intended to use them as clocks, so this is what you might be looking for instead -
if rising_edge(clk) then

   if Enable_button = '1' then 
      ..
   end if

   if Set_button = '1' then
      ...
   end if   

end if