Why does this RAM component have unpredictable behavior in Multisim?
That is not a wrong behaviour for your RAM as far as what I understood from the limited information in the link you have given. You fed some data to some addresses in the RAM. Now you wanna read those data. When WE = 0 and and  CS = 1, the data is read into Q0-Q7 depending upon the address inputs A0-A7. Now you pull CS = 0. At this time, the previous data which was read before, may stay latched in the output Q0-Q7 data lines. It is not necessary that all Q outputs should be reset. When you pull CS= 1 again, new data is read again depending upon the address inputs A0-A7. Here since the RAM has no clock, CS should be clocked like 0->1 for writing or reading new data.