There is the presence of noise(High frequency) at simulation (post-synthesis and post-implementation)
Your problem lies with the following lines of code:

always @(temp)
begin
   if(temp==26'b10111110101111000010000000)//clock divided by 50Mhz
    slow&lt;=slow+1;
 end


Which is equivalent to:

assign slow = (temp==...) ? slow + 1 : slow;


That will cause slow to be incremented asynchronously as fast as the simulation time step will allow once the temp value reaches your compare value.

In a combinational always block (i.e. on with no edge sensitivity), you should never assign variable x (or whatever the name) a value which is derived from x (e.g. x &lt;= x + 1) as this is by definition a combinational loop.

Your logic for clock division is also flawed because you don't reset the value of temp to zero when the compare match occurs, meaning the division value is basically just the full range of a 26bit counter.

The following will work synchronously and reset temp at the correct time:

always@(posedge clk)
    if(temp==26'b10111110101111000001111111) begin //clock divided by 50Mhz
        slow&lt;=slow+1;
        temp&lt;=1'b0
    end else begin
        temp&lt;=temp+1;
    end
end