Some question about RTL Design and VHDL
For part (2) - if the sensitivity list of a process contains other signals, and there is activity on those signals while clk = '1' then the process will operate multiple times per clock cycle. If it's a counter, that would be bad...

Worse, synthesis would ignore the extra events (because there is no hardware feature to implement them) so simulation and synth would behave differently.

Incidentally, if(clk'event &amp; clk = 1) has been obsolete for over 20 years; so your teaching materials are sorely out of date. As @Paebbels says, use if rising_edge(clk) instead. 

Part (1) is neither a VHDL nor an RTL question but basic arithmetic : searching "multiplication by shift and add" should net more information than you will ever want.