Process statements and sequential execution in VHDL
Within a process, statements are indeed carried out sequentially. However, values assigned to signals are not carried out immediately but scheduled to occur at the end of the process.

For example, when your third assignment c &lt;= a; is carried out, the value of a is still the value a had at the start of the process.

This is because the first assignment a &lt;= b; has not yet been carried out and a has not changed.

In fact, the first assignment will never be carried out because of the fourth assignment a &lt;= c;, which will be scheduled to occur at the process end instead.

This behaviour reflects the behaviour of real logic circuitry, which is what  VHDL was designed to do.

I recommend you read up on how VHDL processes work. Make sure you avoid a classic HDL trap: seeing a Hardware Design Language that models a logic circuit as a computer program that is executed by a CPU.