minimum clock cycles needed?
To answer such a question a lot more context must be given and assumptions must be made explicit. Just a few issues:

1) The call-method you describe here is typical for ARM/Cortex and some less known architectures. An 8085 uses the more common stack based method.

2) Most architectures have dedicated hardware and data paths for incrementing the PC, so the ALU does not need to be involved, and it can be done in parallel with another operation.

3) An 8085 is an 8-bit architecture with a 16-bit address, hence getting an address from memory involves two memory accesses (with accompanying PC increments).

4) You seem to assume that a memory access takes 2 internal cycles worth of time. IIRC it was 1 for an 8085 (but I might be wrong), and it is often many many more for modern processors.

5) In step 3) you mention an accumulator, you probably mean the ALU result register, which on most register-based architectures is not a programmer-visible register.

6) If storing the result in Rn takes a cycle, it seems reasonable to assume that storing the destination address in the PC also takes a cycle.