Ground Plane Net Tie - Question about current design
Yes that works if all you are doing is tieing the ground planes together. You are also creating an inductor with about 0.1nH and 7mΩ for the copper trace and roughly  0.3nH and 0.1mΩ for the vias on one side (for only three vias). 

What doesn't make sens to me is why the vias are paralleled and then the trace is necked down to what I'd estimate somewhere in the range of 10 to 14mils. The resistance of the trace is much higher than the paralleled vias.

The other thing is your creating a long path for any return currents to get back to the processor by placing the net tie so far away from the other traces. The ground planes are separated with inductance and it doesn't look like you have a lot traces that crossover. If any of these are high speed (more than 20Mhz) the net tie will create problems. 

Separating the ground planes with a net tie such as this creates a dipole antenna, which could create problems if you need to pass the limits of an FCC unintentional radiator (or equivalent) test. 

If adding additional inductance and resistance between ground planes is what you intended then it looks good. 

One recommended strategy (by Henery Ott) is to place zero ohm stitching resistors (maybe about every 2-3cm along the ground plane separation and see if removing them helps or hurts the situation, usually separated ground planes creates more EMI EMC problems then separating them solves. If your seeing your ground plane bounce from a high load, this can usually be solved by directing the return currents than separating ground planes. If you are moving power from one side of the ground plane to another, the net tie will create common mode noise problems, and you need a better way to stitch the grounds together.