Additional bits computation in VHDL
You are underestimating the number of bits when you ignore the fractional part of the log2 function. What you really want is ceiling(log2()), sometimes called clog2() because it is so commonly used in this type of situation.
So:

clog2(10) = 4 (not 3)
clog2(7) = 3 (not 2)
clog2(69) = 7 (not 6)

Since 4 + 3 = 7, now the results are self-consistent.