Why Vin should be above Vout by a Vbe in LDO using NPN?
The explanation is correct for the schematic given , however if a PNP or Pch FET were used this drop can be reduced.  typical Bipolar LDO's need 1 to 2.5V drop due to the NPN output and bias voltage above output dependent on load current.

Whereas Pch LDO's can have dropout V in xx mV range depending on If* Rdson