Why can't all data be sent across 4 wires?
Serial buses are widely used for high speed transfer.
This diagram shows the available data transfer / clocking rate of a number of serial and parallel buses. In addition, it is common to implement multiple &quot;lanes&quot; each using serial transfer.
Serial buses are able, in practice, to implement higher transfer rates &quot;per lane&quot; and even parallel buses with very wide buses (eg PCI 64 bit) are still unable to match the thoughput of the fastest sinle lane serial buses (eg USB 3.1).

The above diagram is from Multi-gigabit serial protocols demystified which addresses your question far better than can be done here.
They say:

... There is a physical limitation on the clock rates of parallel buses at around 1 to 2 GHz. This is because of skew introduced by individual clock and data lines that cause bit errors at faster rates.
High-speed serial buses send encoded data that contains both data and clocking information in a single differential signal, allowing engineers to avoid the speed limitations of parallel buses.
Today, it is common to see high-speed serial links with data lanes running at 10 Gb/sec. Additionally, multiple lanes of serial links can be coherently bonded together to form communication links with higher data throughputs. ...&quot;

Also see:
Web search super high speed serial bus - much good material