Why is vo = 0 when VI(gate voltage) = 0. Also why is are both mosfets operating in the saturation region . Could someone explain why this is so?
According to the book Vo =0 when VI(gate-voltage) = 0. Why is that so?


Because the two transistors are perfectly matched, \$I_{DP}=I_{DN}\$. So there's no current through the resistor. Which means there's no voltage across the resistor, so \$v_o\$ is at ground potential.


  Why does the book also assume that both mosfets are operating in the saturation region?


The condition for saturation of the NMOS device is \$V_{GS} \gt V_{t}\$ and \$V_{DS} \ge V_{GS}-V_t\$.

Since the gate and drain are at the same potential, we know \$V_{DS} = V_{GS}\$ and therefore \$V_{DS}\$ is greater than \$V_{GS}\$ minus some positive value. 

The same argument holds for the PMOS device with appropriate sign changes.