RFID RC522 with STM32F769I-Discovery
Your suspicion seems to be correct and your SPI clock settings are incorrect. It can be observed in the logic analyzer's image that the data changes on rising edge and stable on the falling edge.

If you check the SPI timing diagram in the datasheet of the RC522. You can see that the clock is LOW before the communication, the data is sampled on the rising edge and the data changes on the falling edge.

Now the STM32 has the CPOL and CPHA settings which you assumed to be wrong.
The description for those from the STM32F7xx reference manual:

Bit1 CPOL:  Clock polarity
0: CK to 0 when idle
1: CK to 1 when idle
Bit 0 CPHA: Clock phase
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge

For you CPHA setting: SpiHandle.Init.CLKPhase = SPI_PHASE_1EDGE; is correct, on the timing diagram the data is sampled on the first clock transition. But it should be a rising edge and not a falling.
For CPOL your setting is idle HIGH while on the timing diagram it is idle LOW. If you observe that if your clock signal would be negated then the first clock transition would be a rising edge while the data is stable and the data would change on falling edge.
So all in all I would try changing this line:
SpiHandle.Init.CLKPolarity       = SPI_POLARITY_HIGH;

to:
SpiHandle.Init.CLKPolarity       = SPI_POLARITY_LOW;

You can also go with trial and error because you have a maximum 4 types of clock and the logic analyzer to check the signals.