Finite State Machine FSM
Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits.

When one builds a state machine using standard parts, he probably appreciates a construction where all logic gates in the state transition  &amp; output logic are replaced by a single easily programmable IC.

I would add buffer latches to input and output bits to keep sure that inputs are read and outputs are updated in sync, the output bits should in the rom should be surely settled before they are used.