Is this address decoding circuit correct?
Your circuit will not work as intended. This is not a simple, or typical, memory decoding problem since the starting and ending addresses are not integral multiples of the RAM capacities - 4K (4,096 decimal) or 1000 Hex. 

You must account for the 50 hex offset in the supplied addresses so that the bottom supplied address (2050h or 3050h) aligns with address 0000 in the RAM(s). This will require some sort of adder logic. 

If the RAMs were larger capacity, you could likely get away with this type of  simple decoding because the required space of X050 to Y04F would all fit within the larger RAM space. Must there be two separate RAMs in the solution? Must the write and read action of the RAMs be strictly combined to the 2050h to 404Fh area of the RAM? In other words are there other devices in the adjacent memory space (e.g. at 204Fh and 4050h) that would collide with RAM operations made beyond the specified source address space? These are all considerations that would perhaps make the design of the decoder.