Why is length matching performed with the clock trace length as the target length?
Data is sent in respect to the clock signal.
Data has to be stable before the clock edge (setup time) and it has to be stable after the clock edge (hold time).
If the clock wiring is too long compared to data, clock will appear too late to be within hold time specs, and if data wiring is too long compared to clock, clock will appear too early to be within setup time specs.