Generate Short negative pulse from an open collector output?
This is asychronous logic- when you activate the reset input the counter resets. 

If you decode the count of 6 then you will get a short pulse from the propagation delay of the decoding logic. The pulse will be over once the counter resets, but you need to also ensure that the counter really resets fully. 

It is recommended that the reset pulse be longer than 25ns, according to the datasheet. A typical 74xx gate has a delay of around 10ns, so if the decoding logic has at least 3 gate delays you should be okay. If there are not enough gate delays you can add a couple inverters (one fed by the other) to get another 20ns.  

If you are mixing logic types (74AS types or whatever) be cognizant of the various propagation delays. 

If you would prefer a nice fat pulse that is easily visible on an oscilloscope, then I would suggest using a one-shot multivibrator such as 74123. 

In this case the output is a relatively high voltage sort-of open collector output that is &lt;2.5V when sinking 7mA. So you can do something like this: 







simulate this circuit &ndash; Schematic created using CircuitLab