D Latches & D Flip Flops
Take a look at: Wikipdia: D-Latch

Specifically, this figure:



The inverting buffer is already required from the D input, and inverting Q to the input of D is a double negative.

Note that the lower And gate has a non-inverted input form D, so you could just move the not gate from the top and gate to the bottom.

The "un-optimized solution":







simulate this circuit &ndash; Schematic created using CircuitLab

Using the double not-gate optimization:







simulate this circuit

"Cheating" and getting rid of both not gates:







simulate this circuit