FPGA Implementation of Matrix Inverse on Basys 3 Board
I suspect you have several problems, but my crystal ball is in for service at the moment so seeing the code is a bit tricky. What does the data_mat type look like? 

I think you probably have inputs and outputs defined as 8 bits times 64 matrix elements = 512 pins or so, clearly not going to work. 

What would probably work would be to declare a 64*8 block ram and then load it using an 8 bit data bus and a 6 bit address select bus plus a strobe, that way you can get the data in over multiple clocks one value at a time using just 15 pins. 

Now on to the logic: 
The usual tradeoff in an FPGA is space for latency, and I suspect from that huge mess of logic that you are trying to get a result in one massively slow clock cycle, I also see division operations in there which turn into a whole mess of logic. 

You seem to be writing VHDL like it was software, this is always a mistake, you should be describing a logic circuit not trying to write a program, a fundamentally different way of thinking. 

I would have a state machine do one step of each of the outer two loops per clock with a 'trigger' and a 'done' signal pair to control the thing, similarly the division could be a mixture of lookup tables and shift operations that may or may not complete in a single cycle depending on how you trade this off, maybe you could pipeline it.  

What are your targets for thruput and latency?