Parasitic source and gate inductance of SiC MOSFETs
After looking at the file, the parasitic inductance Lg and R_Lg have something to to do with gate timing. I can't post the circuit that I reverse engineered from the spice file because it would almost certainly violate the terms and agreements of downloading the file. 

I can say this, in my opinion :


It doesn't look like this value of gate inductance is related to a physical construction of the gate. The inductance value is too high.   
The model is unlike any mosfet model I have seen.