AND gate output always high?
simulate this circuit &ndash; Schematic created using CircuitLab

Figure 1. The NAND gate is much simpler.

As you are discovering the AND gate is not so simple. 

Try simulating this NAND gate and see how you get on. To make an AND gate you need to invert the NAND output. Note that in a logic chip that this would increase the propagation delay.

Note also that the I've added individual base resistors to prevent short circuiting the bases together.

From comment:


  This isn't really answering my question. I was wondering about the AND gate, and also, my question is why wouldn't the output always be high? isn't the output just connected directly to +5v through R1?


No. The output in my Figure 1 is connected to a potential divider consisting of R1, Q1 and Q2. If both Q1 and Q2 turn on their resistance will be much lower than R1's and the output voltage will be pulled low - to about 2 x \$ V_{SAT} \$ = 2 x 0.2 = 0.4 V or so.

Your AND gate suffers a few problems. One major one is that using NPN transistors in that configuration you lose 0.7 V on the base-emitter junction. Anyway, as you have seen, the bias through the bottom transistor tends to raise the emitter voltage.

To have the resistance in the negative leg of your "AND" gate you would have to use PNP transistors.







simulate this circuit

Truth table
In1  In2  OUT
0    0    1
1    0    1
0    1    1
1    1    0


This is still a NAND gate! You need an inverter after it to create an AND.