Why do we have single ended DQ and differential DQS in DDRIO?
DQS is a timing reference and benefits from being differential in noise immunity and edge accuracy. As you noted, differential DQS was introduced with DDR2.

DQ is a data signal, and can tolerate more skew than DQS. There are also a lot more DQ than DQS (8x more); making them all differential would be a pincount problem.

DQ-DQ crosstalk can be a problem. It is managed by good layout that addresses basic signal integrity, and by the provision of termination in the die in the faster DDR variants (called On-Die Termination, or ODT.)

Future memory technology could move to serial connections which are self-clocking. Serial technology is already being used for flash (NVMe, UFS, HFS/SD Card).