How to model devices external to FPGA in a testbench?
If you are to use an external SRAM in your FPGA platform, then you need not only the "cycle accurate", but also (mostly) "timing-accurate" model, if you want something to work. The timing depends on particular memory chip and manufacturer, so the normal way is to download the model form manufacturer's site.

Again, you keep repeating your questions, but continuously mixing "SRAM" with "SDRAM" and other types of memory. The SDRAM (dynamic RAM) is totally different beast as compared to SRAM (static RAM), and requires much more complex on-FPGA controller, cycle-configurable and therefore very cycle-accurate. Same thing, the behavioral and interface timing model are coming from manufacturers.