pulse width modulation
I didn't read the question before I commented, so will post some hints for you. I'm not going to give you an answer as it's your assignment to do.

One period of your counter needs to be \$0.05\mathrm{ms}\$. So that means it needs to count from 0 to its maximum value in that time. So from that you can work out at what frequency the counter needs to count at (hint: it is an 8bit counter, so what's the maximum value?). This gives you your required \$f_{enable}\$.

However, you don't have a clock of that frequency, instead you have one of \$100\mathrm{MHz}\$. The questions use of the word "Delay" is quite misleading and not a very good description. In fact the "Delay Counter" is a clock divider - it generates a clock enable signal which allows something to count at a lower frequency.

Look at the diagram, notice how the "Delay" is connected to an "Enable" pin. You can infer from this that the counter must be enabled for one \$100\mathrm{MHz}\$ clock cycle in every \$n\$ cycles. By doing this the counter will count at a frequency of \$f_{enable}=\frac{100\mathrm{MHz}}{n}\mathrm{Hz}\$. 

What value of \$n\$ must be used to make the required period counter frequency?