CMOS and gate implementation
Let us analyze your circuit.

When both inputs are low, the PMOS are on, the NMOS are off, the out is tied low by the PMOS.

When both inputs are high, the NMOS are on, the PMOS are off, the out is tied high by the NMOS.

When one input is high and one is low, e.g. A=1, B=0, the rightmost PMOS is on, while the leftmost is off, the top NMOS is on but the bottom NMOS is off, so the output is tied low by the rightmost PMOS and no transistor can try to tie it high, so the circuit is still working.

If you work out the truth table you will see that the circuit is indeed an AND port.

The circuit has a problem though: it employs PMOS for the low side, and NMOS for the high side. If you use transistors with an high threshold voltage when you try to turn them on, with Vgs=0, they are not really on, they are in subthreshold region and conduct just a bit more than a transistor with a negative (wrt to the usual gate voltage you would apply to it depending on the MOS polarity) gate to source voltage.

The problem can be solved by using devices with a negative threshold voltage, so that Vgs=0 is enough to turn them fully on.

Please note that statically, having transistors in ST region might not be a big problem, but they can carry a lower than usual current, which results in slower transients of the output, especially with capacitive loads.