Maximum and Minimum delay of combinational logic circuits
Let's take this one step at a time. You seem to be confused about the term "clock skew". Clock skew is the amount of time by which the clocks as seen by two different flip-flops can be different.

For example, if you take the clock at FF2 as your reference, the rising edge of the clock at FF3 might occur anywhere from 0.2 ns before the same edge at FF2 to 0.2 ns after that edge.

What this means is that from the "point of view" of FF2, the setup and hold times of FF3 have been "blurred" or expanded by &plusmn;0.2 ns, and you now have to think of them as being 0.7 and 1.2 ns worst-case, respectively.

EDIT: So, the maximum delay for C is the clock period (10 ns) minus the quantity (FF3 setup time (0.5 ns) plus the clock skew (0.2 ns) plus the maximum delay for S (2.0 ns) plus the maximum FF2 clock-to-output delay (0.2 ns)), or 10 &#150; (0.5 + 0.2 + 2.0 + 0.2) = 7.1 ns.

Similarly, the minimum delay for C is determined by the hold-time requirement of FF3. You add together the FF3 hold time plus the clock skew, and subtract out the minimum FF2 clock-to-output delay and the minimum delay through S. This works out to (1.0 + 0.2) &#150; (0.2 + 0.5) = 0.5 ns.