Why my register file operates abnormally
Allora, the one suspicious element I see are the two D flops in series that implement your FF compoent. As you stated, these are actually latches. (The “&gt;” symbol on the inputs is misleading – that denotes an edge-sensitive clock. Should probably use “G” to denote a gated latch.) So with the two D latches there is a race condition: rising CLK causes 1st Q to change, but also causes falling clk (gate) to 2nd latch, which latches output. So 2nd latch’s D and G are changing at essentially the same time. Non si fa cosi.
If the simulation is using post-layout timing, then it could be that only some paths fail because their internal routing delays resulted in setup/hold violations at the second latch.