FPGA Jtag Hooking to User Logic
Boundary scan (and internal scan) testing, whether using JTAG or not are intended for production test. This is completely different to using JTAG or SWD for software debug. Sometimes the same pins will be used, but this is not a given.

It looks like the Altera USER0, USER1 instructions are used to access internal (user connected) scan chains. This permits you to connect (with a test-mode mux on each flop) all your design flops together into (here two) long scan chains. You have the ability to read and pre-load all of the logic in your design.

Internal scan chains like this can be used to check for manufacturing faults in the actual silicon. If you use scan for the external pins, it gives you a way to test for solder open/short on the PCB.

Scan can be used to debug a design, but it's the last resort. If you experience a lockup which no other debug method can shed any light on the cause, it's possible to use scan to extract the design state just after your failure (before is possible, but that would need a trigger or deterministic failure). This state can be used to guide your investigation into what the design state that causes the failure is, and help reproduce in simulation.

Tools like SignalTap now provide a more user-accessible approach to real-time FPGA debug, these are much more akin to having a logic analyzer hooked in to a pre-defined selection of internal nodes - remember scan is a 1 cycle at-a-time approach.