How to change reg in two different always blocks?
For synthesis, each always @(posedge clk) block needs to follow the pattern of a D flip-flop, otherwise the synthesis tool won't recognize it. So the problem becomes, you have two conditions where you need to change the value of the register (temp), but temp can only have one driver. This problem gets even worse when you have two different clock domains (as in your example, clk1 and clk2).

Fundamentally you can't have a flip-flop in two different clock domains, so the synthesis tool doesn't know if  the temp flip-flop should be clocked by clk1 or clk2. That's why this code cannot be synthesized: there's no way to implement this design in hardware.

Crossing two different clock domains is tricky, in your example you would have to split temp into clk1_temp and clk2_temp,

// clock domain clk1
reg clk1_temp;
wire clk1_tempClear;
wire clk1_tempSet;

// clock domain clk2
reg clk2_temp;
wire clk2_tempClear;
wire clk2_tempSet;

// clock domain clk1
always @(posedge clk1) begin
    if (clk1_tempClear) begin
        clk1_temp &lt;= 0; 
    end;
    if (clk1_tempSet) begin
        clk1_temp &lt;= 1; 
    end;
end

// clock domain clk2
always @(posedge clk2) begin
    if (clk2_tempClear) begin
        clk2_temp &lt;= 0; 
    end;
    if (clk2_tempSet) begin
        clk2_temp &lt;= 1; 
    end;
end


Now you have two separate flip flops, one is clocked by clk1 and drives clk1_temp, the other flip-flop is clocked by clk2 and drives clk2_temp.

In practical use, there's usually many signals that have to cross from one clock domain into the other. See my answer about crossing clock domains: fpga verilog dual access