How is asynchronous reset physically implemented in a flip-flop?
Asynchronous reset is level-sensitive so the timing relative to the clock edge is of no importance. 

Think of the output cross-coupled gates of a master-slave flip-flop and add inputs to the gates to force the outputs to a given state. For example (from this website):



So long as the /RESET input is low, the /Q output must be high. In reality it has to be a bit more complex than this because you don't want glitching on the Q output. Here is the gate-level representation of a real D-FF (74LS74):