Why don’t most RISC ISAs write integer MULH/MUL or DIV/REM to two general-purpose registers?
Generally, the business requirements for processor designs are directed to meet either synthetic benchmarks or real-world application workloads. Features that don't address either of those are harder to sell, and therefore more likely to be left out.

During the 80s, the Dhrystone benchmark was very popular. Usually this would be presented in a high-level language, usually C. Dhrystone does not include any remainder operations! So designers targeting a high Dhrystone score might leave out remainder operation to shave a few picoseconds off the cycle time.

Most high-level languages have separate arithmetic operators for quotient and remainder, very few provide standardised operations to give both from a single operation (partly because C and FORTRAN don't have native tuples!). Until recently compilers haven't been great at the kind of optimisation-spotting that would enable them to fold two operations into one instruction.

If we look at the kind of arithmetic-heavy work that processors have been optimised for, it tends not to care about remainders. The big examples are FFT and matrix multiplication for linear algebra. Those are why processors tend to have multiply-accumulate instructions and SIMD instructions.