Verilog Shift Register with Two Inputs
As it stands you have a shift register whose clock is both DATA0 and DATA1. This cannot be synthesised as FPGAs don't have dual-clock flip flops.

To make it work you will need two things:


A single clock sufficiently fast to sample the DATA0 and DATA1 signals
Edge detection logic for the DATA0 and DATA1 signals.


Edge detection is a pretty straight forward thing to do:

module fallingEdge (
    input clock,
    input signal,

    output reg edge
);

reg signalDly;

always @ (posedge clock) begin
    signalDly &lt;= signal; //Delay signal by one clock cycle.
    edge &lt;= signalDly &amp;&amp; !signal; //If the signal was high in the last cycle but low now, it must be a falling edge
end

endmodule


The output of that block will be high for exactly one clock cycle when there is a falling edge of the data signal.

You will need an edge detector for each of DATA0 and DATA1 which will result in two new signals (say EDGE0 and EDGE1). 

Your shift register is then clocked by your 'clock' signal (1), and you simply check the edge signals in that block. If EDGE0 is high, clock in a 0. If EDGE1 is high, clock in a 1. If they are both high at the same time, you'll need to decide whether 0 or 1 takes priority.