Design a T flip flop in VHDL using Modelsim, signal values not changing as expected
A simpler and more direct implementation would be:

library ieee;
use ieee.std_logic_1164.all;

entity TFF is
  port(
    CLK     : in  std_logic;
    RST     : in  std_logic;
    T       : in  std_logic;
    Q       : out std_logic;
    Q_N     : out std_logic
  );
end entity TFF;

architecture behaviour of TFF is

  signal tState      : std_logic;

begin

  pFlipFlop : process(RST, CLK) is
  begin
    if (RST = '1') then
      tState  &lt;=  '0';

    elsif (CLK'event and CLK = '1') then

      if (T = '1') then
        tState  &lt;=  not tState;
      end if;

    end if;

  end process pFlipFlop;

  Q    &lt;=      tState;
  Q_N  &lt;=  not tState;

end behaviour;


but this introduces a delta delay onto Q_N which may be a problem if this feeds another CLKed flip-flop input.  

Alternatively, you could use the below but it may implement more than one flip-flop, though synthesis optimisation should reduce it to one.

library ieee;
use ieee.std_logic_1164.all;

entity TFF is
  port(
    CLK     : in  std_logic;
    RST     : in  std_logic;
    T       : in  std_logic;
    Q       : out std_logic;
    Q_N     : out std_logic
  );
end entity TFF;

architecture behaviour of TFF is

  signal tState      : std_logic;

begin

  pFlipFlop : process(RST, CLK) is
  begin
    if (RST = '1') then
      tState  &lt;=  '1';
      Q       &lt;=  '0';
      Q_N     &lt;=  '1';

    elsif (CLK'event and CLK = '1') then

      if (T = '1') then
        tState  &lt;=  not tState;
        Q       &lt;=      tState;
        Q_N     &lt;=  not tState;
      end if;

    end if;

  end process pFlipFlop;

end behaviour;