Daisy Chaining Shift Register Concerns and Fan-out Limits
There are some (potential) problems, these I can think of right now:

depending on what you are doing with that many outputs, you might get significant ground currents, which can mess with your ground voltage relative to an output (ground raise, ground bounce)

these shift registers have fundamental problem when chained: the output that you have for chaining changes on the same edge as used by the next chip for sampling its input. (Chips that are designed for chaining have an opposite-edge chain data output.)  This creates a (potentional) data race. Solutions are a) delaying the data (R+C), or b) feeding the clock from the FAR end.

32 or 64 clock inputs is quite a capacitive load. Consider using distributed buffers, or a high-capacity buffer (check drivers that are meant for power mosfet gates) BUT sharper edges create more reflections (which you don't want on a clock line, the data lines are less problematic), so you might need to add series resistors to combat false clocks due to reflections.


I dunno what you want to do, but if it is driving lots of LEDs you might consider other options, like neopixels, max7219 (64 LEDs per chip, up to 8 chips chained), or driving a LED matrix directly.