Why are bitfields in register not sequential?
Register layout is generally determined by the hardware designer. There's usually a reason for  unused bits - most likely first:


Functionality from an earlier design was removed, the bit flags are now reserved to avoid confusing old revisions of software (backwards compatibility).
To leave space to implement behaviour in future revisions. Or indeed the bits may hide features implemented (perhaps partially) that will only be documented in the next revision.
Undocumented bits may be driven by signals only useful for testing/debugging so cannot be  publicly documented without exposing implementation details. For instance they may read internal state machine encodings or unexpected condition flags.
Unused bits may simply be there for data alignment. Some CPUs may be faster processing fields where related bits are packed to byte alignment.