Why does Modelsim say that VHDL shared variables must be protected?
Non-protected shared variables are fine if you know what you are doing, and I would personally prefer if Modelsim did not produce the warning. (It is not present if you compile for VHDL-93.)

In your case you could replace your shared std_logic variable with a small protected type with an internal variable and set and get procedures. This would get rid of the warning, but provide zero extra protection.

Not to say that protected types are not useful in some situations.