Creating a Delay Locked Loop (DLL) on an FPGA
I strongly advise you flip the design round so that all the D-flops are clocked from the same system-wide clock resource, and that you place the delays on your data. FPGAs work very hard to distribute a clock to all parts of the chip with decent fanout and minimal skew, you want to ride that horse in the direction it's going.
The fun part is going to be persuading high level tools to make any sort of delay in your data path, let alone making them of any particular value. Timing synthesis is dedicated to making delays meet maximum constraints, so you have to be quite creative to achieve definite delays. You would have to take control of the PAR process from the high level tools and provide a full hardware level layout for the components to be used as the delays. One simple way I've used in the past to create a definite delay is to force it to route a signal between two pins on opposite sides of the chip (something the PAR couldn't 'optimise' away), but that would could run out of resources quickly if you wanted many stages.