How is this PMOS FET working as ESD protection?
In the bottom right circuit, there are 2 NMOS devices used for ESD protection. The "diodes" in parallel will be for (-) ESD events.

From what I've been taught by the in-house ESD guy, the circuits are very layout-dependent; the location of metal-active contacts, the placing of metal over active where displacement currents from high dV/dT Efield transients, the adjacency of gate-poly to metal, the placement of substrate contacts needed to move enormous transient currents DEEP into the bulk material and dissipate ESD heat in the volume of material instead of at the (shallow) surface FET implants ---- all must be planned.

And tested. And probably will fail under transient tests because the desired SNAPBACK
behavior occurs at the WRONG voltage and downstream gate-oxides will be over stressed. So a phase2 design/fab/test is needed.

It ain't magic, but thus throwing down any old FET dopants, with casual metallization and contacts and bulk ties ------ does not suffice.

The FETs and the various layout methods are crafted to impose a BIPOLAR SNAPBACK at a low voltage, with huge currents steered to flow only DEEP below the FETs.