What are the minimum and maximum number of cycles consumed when executing an interrupt on an STM32F0 MCU?
Look at the exception entry timing diagram on this page.
Stacking

Entering the ISR on an Cortex M3 uses 12 clock cycles. For your ARM core and for leaving the ISR, maybe you can find a similar diagram.

The "stolen" cycles should equal all cycles used for entering, executing and leaving your ISR.