evaluating ESD protection for 3.3V i2c
I've got a couple of comments.  

Series resistance. When the master drives an I²C line low, the series resistors and the pull-up resistors form a voltage divider.  As a result, the logic low voltage which the slave sees will be higher.  You need to make sure that this actual logic low is below the logic low threshold for each slave device.  (Similar rationale applies when slave is driving an I²C line and master is receiving information.)  

Bus capacitance.  TVS diodes have their own parasitic capacitance.  TVS with capacitance on the order of few pF are available.  Look for TVS intended for protecting USB 2.0 ports.  

The tradeoff is between series resistance, pull-up resistance, bus capacitance, and bus speed.  If this were my design, I would definitely remove the 1 kΩ resistors, and 100 Ω maybe too (maybe leave pads for the 100 Ω). 

Because of bus capacitance and weak pull-up, you you may have to reduce the bit rate on the I²C bus.

Are you overextending the I²C beyond its intended application?  You are running the I²C through wires to multiple board.  That's not something  I²C is intended for.  You may end-up like me that time.