Via layout for decoupling capacitors
Looking at EMC is important. Placement of decoupling capacitors is important, and placement of vias can be more important. Well done for considering it.
The general rule is: make the inductive loop as small as possible.
Assuming you have a 4 layer PCB, the middle two layers are a GND plane and a power plane. This means that you can then put a via at the IC power pins, and at the IC GND pins, so that power and GND are both connected straight to the plane.
You can then also connect the capacitors GND and power pins straight to vias. This way you can put the capacitors in the most sensible place between the GND and POWER of the IC depending on the other restrictions on your board.
As mentioned by yourself; you want to reduce the inductive loop between power and ground with the capacitors. This is reducing the loop for the IC (the thing you're decoupling), and so ideally you want the capacitors rotated by 90 compared to how you have them, as that reduces the loop by the size of the capacitor. There is an argument that this will make a small difference, as the parasitic inductance in the capacitor is probably going to have more of an impact. But every little helps! (Using the physically smallest capacitors as possibly will help too).
To directly answer your questions:

Connect the vias to both the IC and the capacitors
The more vias to connect to power and ground is sometimes better, rarely worse
The datasheet is showing how to reduce the inductive loop between the power and ground pin of the IC (by connecting them as tightly as possible) so that is a good idea.