How does a poorly designed SMPS affect another device
[1] Suppose you have a Switcher, online, with 200 volts being switched in 200 nanoseconds, thus 1 volt/nanosecond slewrate. Suppose the Switcher is un-cased. Suppose the heatsink is moving that 200 volts in 200 nanoseconds (yes, bad design). How much coupling occurs, 4" away from a 4" by 4" heatsink, to a sensitive PCB also 4" by 4" in size?

Capacitance = Eo * Er * Area / Distance = 9e-12 Farad/meter * 0.1m * 0.1m/0.1m = 9-13F ~~ 1pF.

The current through the air is (I = C * dV/dT) = 1pF * 1volt/nSec = 1mA.

Thus that sensitive PCB has 1mA injected, for 200 nanoseconds. 

Suppose on that PCB, there is 4" trace with width 1mm. That trace gets 10UA injected, and that 10uA will explore all possible paths to return to the Switcher.

Thus electro-static shields are used.

[2] These surges consume charge, as you know. To reduce loop area and reduce external magnetic fields, we use local capacitors(and coils, at times) to supply fast charge movement; yet the filters generate magnetic fields.
I use this formula, frequently, to determine the approximate risks of fast currents in a long wire coupling magnetically into a small loop in a sensitive circuit

Vinduce = [MU0 * MUr * Area/(2 * pi * Distance)] * dI/dT

which becomes 2e-7 * Area/Distance * dI/dT.

A customer had problems with ICs failing. The PCB had 6 layers, with no clearly implemented planes, thus had many potential circulating paths for eddy currents.
They were switching 2,000 amps in 1uS, 30mm away (yes 3cm) away from the IGBT control board. Running the numbers,
Vinduce = 2e-7 * 0.1meter * 0.1 meter/0.03meter * 2 Billion amps/second
Vinduce = 2e-7 * 1/3 * 2 Billion = 4/3 * 100 = 133 volts driving eddy currents in the PCB planes. Given "GND" has nominally ZERO resistance, but when fragmented on multiple PCB layers the resistance soars what with Vias needed between layers, who knows what the circulating currents were, or how much voltage difference occurred between "GND" here and "GND over there, 2 or 3 or 4" away. We asked the customer to place a shield plate between the PCB and the 2,000 amp bus.

[3] In all the filtering used to attempt to isolate switching trash, we encounter the parasitics of the filtering components; 0.1nH and 2 Billion amps/second becomes 0.2 volts upset. Thus the very regulatory loops have upsets, unless magnetically shielded.

[4] Suppose the "shields" are poorly tied to the "local Switcher GND"----another 1 nanoHenry path. A shield, necessarily close to the internal fast-moving nodes and pieces of metal, may collect 0.1 amps of [displacement current] charge during the Efield events.
The onset of slewing may be 10nS as the MOSFETs turn on. 
The voltage across the piece of metal tasked with tying the Shield to rest of Switcher has V = L * dT/dT = 1nH (easily could be 5nH) * 0.1amp/10nS
V = 1e-9 * 0.1 * 10e-9 = 10 milliVolts.

Can you place any sensitive circuit near 10mV trash generators?

Our shield, purportedly "quiet", actually is a 10mV radiator on Switcher trash.

EDIT having (now) read your link, with the excellent diagrams of methods of generating trash and then reducing trash, all I have provided here are actual REAL SITUATIONS with real numbers.

Do you want more examples?

How about a picture?







simulate this circuit &ndash; Schematic created using CircuitLab

This switchreg has lotta problems: all the caps are too small, as are the inductors. The feedback resistors are way too high (why?). The GROUND currents are totally uncontrolled.

The FET heatsink injects a massive current through the 1mil insulation between the FET heattab and the heatsink which is "grounded".

There is no input PI filtering. There is no output PI filtering.

The IC driving the FET gate has to supply huge gate currents for fast switching.