Converting Bin-to-BCD code from VHDL to Verilog
The variable assigment in VHDL (with :=) takes place immediately. To get the same behaviour in Verilog, you have to use the blocking assignment with = instead of the non-blocking one (&lt;=). In your example, blocking assigments for variable z are required because your code checks the new value of z immediately after assigning it.

Moreover, the loop runs from 0 to 4 (inclusive) in VHDL. In your Verilog code, it goes from 0 to 3 because it breaks out on 4. You have to change the condition in your for statement to "less or equal" comparison:

for(i=0; i&lt;=4; i=i+1) begin


Minor code improvements:

After changing the assigment for z to a blocking one, you can remove these else-cases, because they have no effect:

    else
      z = z


In the addition, you should add a constant with a specific length:

      z[11:8] =z[11:8] +4'd3;
      z[15:12]=z[15:12]+4'd3;


The constant 3 without a length specification has a length of 32-bit and the synthesis compiler issues a warning about truncating to 4 bits.