Rising Edge vs Falling Edge D Flip-Flops
The difference is as simple as their names, there's nothing hidden in the depths.
A positive-edge triggered flip-flop triggers on the positive-going (0-to-1) edge of its clock input.
A negative-edge triggered flip-flop triggers on the negative-going (1-to-0) edge of its clock input and is a perfectly valid thing to do, though rarely is it done.
In all other respects, their behaviour and function are the same.
Putting in an inverter between the clock and the flip-flop's clock input will indeed change the trigger edge of the resultant circuit.
That inverter will introduce a clock propagation delay, so that circuit's timing will be slower to a dedicated flip-flop of the opposite polarity. Mind you, if you implement that circuit inside an FPGA, CPLD or ASIC, the synthesis tools will almost certainly optimise away the inverter and use the opposite polarity flip-flop to what you put in an HDL or schematic.