Data transfer from Latch to PIPO
Any signal (net/register) for synthesizable code must be assigned in exactly one always block. In the code pipo_lat is defined in two separate always blocks. cnt should also be removed from the sensitivity list for synchronous logic. Active reset should assign values to a constant. For combination blocks and latch logic, it is better to use always @* then putting the full sensitivity list, except you are forced to follow IEEE Std 1364-1995 and nothing newer. 

module latch_to_pipo #(N=192, M=48, RSTVAL = 1'b0) (
    input wire sclk, rst, xlat,
    input wire [191:0] sipo_out_gs,
    output reg [47:0] pipo_lat );

  reg [7:0]   cnt;
  reg [N-1:0] gs_latch;

  always @* begin // latch
    if(rst)
      gs_latch &lt;= {N{RSTVAL}};
    else if(xlat == 1)
      gs_latch &lt;= sipo_out_gs;
  end

  /* 48 BITS DATA FROM LATCH TO PIPO */
  /* counter for grayscale to count upto 192 bits */
  always @(posedge sclk, posedge rst) begin
    if(rst) begin
      pipo_lat &lt;= {M{RSTVAL}};
      cnt &lt;= 0;
    end
    else begin
      case (cnt)
        8'd47  : pipo_lat &lt;= gs_latch[47:0];
        8'd95  : pipo_lat &lt;= gs_latch[95:48];
        8'd143 : pipo_lat &lt;= gs_latch[143:96];
        8'd191 : pipo_lat &lt;= gs_latch[191:144];
        default: pipo_lat &lt;= pipo_lat;
      endcase
      if(cnt &lt; N-1)
        cnt &lt;= cnt + 1;
      else
        cnt &lt;= 0;
    end
  end
endmodule


If your tool supports SystemVerilog, I recommend you your the SV keywords always_comb, always_ff, always_latch, unique, priority, and other SystemVerilog for design keywords where ever applicable. A good modern simulator/linter/synthesizer will give errors and warnings when common mistakes are make, which is especially usefully for debug. If need be one can always easily degrade to older (and still clean) syntax with a few simple text replacements. 

the latest SystemVerilog LRM available for free from IEEE