The detailed working steps of the DRAM 3T1C cell?
It is the intrinsic gate capacitance of T2. It is where the bit is stored in this DRAM cell.


  If the charges remain on T2, will T2's gate stay open?


Yea, but there is leakage current and eventually capacitor will get discharged in order of milliseconds. This is the biggest drawback of DRAM cells.

Since we assume MOSFETs like switches here, it is more logical to use terms 'closed' for ON state and 'opened' for OFF state. You have used it the other way in your explanations.

There are some problems in steps 5, 6, 7, 8 of "Steps to Write and Read "0" to and from the cell" which seems like comes from the misunderstanding in MOSFET's switching operation.

After writing '0', the capacitor has discharged to zero and T2 is off now. 

When read rowline goes high later, T3 remains off -- because T2 is off, and hence the source terminal of T3 doesn't pull to ground. 

Since both MOSFETS are off, read bitline is not pulled to ground either. The read bitline should already be pulled up to Vcc thru a pull-up resistor, and therefore it is read as 'high', which is then interpreted as logic '0'.