Does VHDL permit "alias" for procedures in packages like we can use them for "external signasl"?
Thanks to @DonFusili and @user8352 for their help.
Alias definition:
VHDL 1076-2008, paragraph 6.6 Alias declarations 6.6.1 General:

An alias declaration declares an alternate name for an existing named entity.
...
An alias can be declared for all named entities except for labels, loop parameters, and generate parameters.

It is used improves readability or differentiate among identically named items in different packages (your case).
Alias for an object:

An object alias is an alias whose alias designator denotes an object (i.e., a constant, a variable, a signal, or a file).

alias identifier [ : subtype_indication ] is name;  where subtype_indication is optional.
Some examples:
signal Instruction : Bit_Vector(9 downto 0);
alias Destin : Bit_Vector(1 downto 0) is Instruction(9 downto 8);
alias ImmDat : Bit_Vector(7 downto 0) is Instruction(7 downto 0); 

alias STD_BIT is STD.STANDARD.BIT;

Alias for a non-object:

A nonobject alias is an alias whose alias designator denotes some named entity other than an object.

alias ( identifier | character_literal | operator_symbol ) is name [ signature ]; 
Note that here, you need the square parenthesis (brackets) around the signature of the non-object if you specify the signature.
VHDL 1076-2008, paragraph 4.5 Subprogram overloading 4.5.3 Signatures:

A signature distinguishes between overloaded subprograms and overloaded enumeration literals based on their parameter and result type profiles. A signature can be used in a subprogram instantiation declaration, attribute name, entity designator, or alias declaration.

In other word, to me, it is way to represent/reference your non-object which will be used by your alias.
Some examples:
alias LOW is STD.STANDARD.'0' [return STD.STANDARD.BIT];

alias HIGH is STD.STANDARD.'1' [return STD.STANDARD.BIT];

alias &quot;&lt;&quot; is my_compare [my_type, my_type, return boolean];

with my_compare is a function you created.
Your problem:
Consequently, to answer your question, yes you can use an alias for a procedure inside a package inside a library:
alias lib_a_print is lib_a.pkg_a.print [TypeName1, TypeName2, TypeName3]
If you had a function, it would have been:
alias lib_a_print is lib_a.pkg_a.print [TypeName1, TypeName2, TypeName3 return TypeName4 ]
I have tested it under Vivado 2018.1 and it works with a similar example.
Sources : VHDL 1076-2008 and ICS - VHDL golden rules page 15
Some examples comes from:

VHDL 1076-2008
Renerta
CECS