How to implement a delay in VHDL
I have changes your code in some parts (I hope your ok with that). Why do I think this version is better?


Now all process are clocked by real clock. 
Each process has a name.
Signals are written on one place only


The code could be made even better:


What you are using in process "output_generator" is some kind of state machine to generate your pattern. Have a look at the examples of Altera how to make it more readable and easier to debug.
We could transform some signals into variables (temp, count, dcount). They they would be visible only in the area needed and would not clutter our definitions section. 
What are the start / stop signals for? They lead no where.


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architecture Behavioral of PSOL is
   signal temp : std_logic := '0';
   signal count : integer range 0 to 1301 := 0; --1301
   signal dcount : integer range 0 to 11 := 0; --
   signal start : std_logic  := '1'; -- indicates the start of 
   signal parity : std_logic := '1'; --used to varify data sent
   signal stop : std_logic := '0'; --indicate when word/command has 
   signal enable : std_logic := '0';


begin

-- The clock divider generates a 50% duty cycle signal with 19kHz as clock for the output. 
-- and a enable signal that is high for one clock cyncle on each rising edge of clk_19kHz
clockdivider: process (clk)
begin
    if rising_edge(clk) then
        if (count = 1301) then --1301
            temp &lt;= not(temp);
            count &lt;=0;
            clk_19khz &lt;= temp;

            if temp = '1' then -- only on rising edge 
                enable &lt;= '1';
            end if;
        else
            enable &lt;= '0';    -- make it a puls
            count &lt;= count + 1;     
        end if;
    end if;
end process clockdivider;

-- Here we generate the dout signal. 
output_generator: process(clk)
begin
    if rising_edge(clk) then
        if enable = '1' then  -- use only the clocks where enable is 1
            dcount &lt;= dcount + 1;
            parity &lt;= '1';
            stop &lt;= '0';
            start &lt;='1';

            if (dcount &lt; 12 and start = '1' and stop = '0') then
                CASE dcount is
                    when 0 =&gt; Dout &lt;= start; -- what happens with dcount = 0?
                    when 1 =&gt; Dout &lt;= start;
                    when 2 =&gt; Dout &lt;= '0';
                    when 3 =&gt; Dout &lt;= '1';
                    when 4 =&gt; Dout &lt;= '0';
                    when 5 =&gt; Dout &lt;= '1';
                    when 6 =&gt; Dout &lt;= '0';
                    when 7 =&gt; Dout &lt;= '0';
                    when 8 =&gt; Dout &lt;= '1';
                    when 9 =&gt; Dout &lt;= '1';
                    when 10 =&gt; Dout &lt;= parity;
                    when 11 =&gt; Dout &lt;= stop;
                    when others =&gt; null;
                end case;
            end if; 
        end if; 
    end if;
end process output_generator;

end Behavioral;