using the clock of FPGA in system generator
I have seen at least two ways to use System Generator:


Within Simulink, run all the way through synthesis and implementation and produce a .bit file
Convert the System Generator design to the two VHDL files yourdesign.vhd and yourdesign_cw.vhd. Then run synthesis and implmentation in ISE or Vivado after importing the VHDL files into your project and tying the ports manually.


I'm not sure if what you're asking is possible if you're using method 1. However if you're using method 2, you can always connect the we input of the FIFO to a yellow input block, then when you place your auto-generated VHDL component into your top-level design, you can tie the clock to the we port you created.