Verilog - Iterating Over All Cases In Testbench
If you treat the inputs as a bus, you can add 1 to them until they overflow. Something like this works (online simulation):

initial begin
  $monitor("%d %d %d %d", A, B, C, D);
  {A,B,C,D} = 4'b0000;
end 
always begin
  #10;
  {A,B,C,D} = {A,B,C,D} + 4'b1;
  if (&amp;{A,B,C,D}) begin
    #10;
    $finish;
  end
end