Birectional I/O pin in verilog
Inouts are actually "wire" so you can't use any procedural/sequential assignments (where the left hand side must be a reg). Generally speaking:


input : internally must always be of type net, externally the inputs
can be connected to a variable of type reg or net. 
output :
internally can be of type net or reg, externally the outputs must be
connected to a variable of type net. 
inout : internally or
externally must always be type net, can only be connected to a
variable net type.


A common approach is to have an "enable" signal for the output of your inout, and to drive to high impedance if the output is not enabled. In your case direction is playing that role.

So try this instead:

module test(
    input  clk,      // The standard clock
    input  direction,  // Direction of io, 1 = set output, 0 = read input
    input  data_in,    // Data to send out when direction is 1
    output data_out,   // Result of input pin when direction is 0
    inout  io_port     // The i/o port to send data through
    );

    reg a, b;    

    assign io_port  = direction ? a : 1'bz;
    assign data_out = b;

    always @ (posedge clk)
    begin
       b &lt;= io_port;
       a &lt;= data_in;
    end

endmodule


The hardware corresponding to the above code would look something like this: