What is the basic principle for a cmos vcc detector circuit?
Power on reset circuits are used to trigger the point that a microprocessor can start executing its code without the need to worry about whether the voltage supplies are within their prescribed limits for successful operation.

The basic principle is based on charging a capacitor. The capacitor charges at a rate intentionally slower than what the power supply takes to reach its intended value of 5V or 3V3 or whatever the logic circuit needs to work.

So, the power is up and running, and some short time later the capacitor charge voltage reaches a point that is detected by the "hardware inside the MCU" and the MCU switches on proper and executes its programme.

The charging capacitor is based, in its simplest form, on a resistor from the positive power rail to a capacitor connected to ground. The R x C value might be 100kohm x 1uF which corresponds to a time delay of 100msecs - this is usually enough time. In more precise terms, the RC time of 100msecs represents the cap charging to 62% of the logic supply and a comparator (set to trigger at this voltage or above) instigates the starting gun for the code to begin executing.

There are more complicated features in power-on reset circuits but this is the crux of them.