SystemVerilog - Enforcing prevention of inline initialization of logic/reg elements used as flip-flops
Inline initialization is not good, even for the b signal. A commercial tool I use for ASIC synthesis ignores those initializations and throws warnings.
If b is a constant, the below would be better (still not ideal).
logic b;
assign b = 1;

I experienced failures in formal equivalence checking (RTL vs. synthesis netlist) as well, so I avoid inline initializations in design.