Verilog memory designs with multiple read/write ports - poor circuit performance when synthesized?
Firstly, are you synthesizing to an FPGA?

This paper from Cypress shows a dual-port RAM as a block diagram. It's not quite clear from there, but the dual-port array in the middle is an array which has a double set of lines: 2 row selects, 2 write column sets, 2 read column sets.

Scaling beyond 2 is difficult because then you need 3, 4 etc sets of wires, and your RAM density goes down as you run out of space for wires.

If you write Verilog which implies more than 2 ports, the synthesis tool will build it out of flops with multiplexors on the front, consuming far more space than RAM cells.

Why do you actually need multiple ports? How large a RAM do you want? Building a memory arbitrator on the front of a normal RAM may be the solution you want.