How to distinguish between clock stretching and MSB in I2C EFR32FG14
The hardware takes care of receiving a byte with clock stretching - you won't get an interrupt until the complete byte has been received. The clock stretching is transparent to the software.
If there has been an error such as Clock Low Timeout you will receive the appropriate interrupt to indicate the error. You may need to institute a recovery mechanism to get the buss working again in such an instance.
An I2C bus can get locked up if a slave pulls the clock low permanently; the usual recovery by sending 9 clock pulses won't work in such instances.
SMBus added a couple of features including timeouts at the slaves to avoid the problems. In a system without such capability it may be necessary to power-cycle the offending slaves. Some designers do add that capability.
I'm unable to find anywhere in the manual regarding the mechanism of the support for clock-stretching in the reference manual for the EFR32 other than a statement that it is supported (Section 17.3.1.5). The state machine descriptions (section 17.3.7.1) are at the byte level not the bit level.
A question on the support section had the reply &quot;...our EFR32 I2C clock stretching is mandatory, not an option.  EFR32 I2C master support  clock stretching by hardware, no need additional config.&quot;
Answer to question re clock-stretching