Precharging circuits in SRAM
It mentions it as diode-connected NMOS pair. Why?


Consider the following connection topology of a bipolar transistor where the collector and base of the transistor are short circuited. 



Clearly this resulting 'two-terminal' device acts as a diode. And hence it was named as 'diode connected' transistor. 

When the similar configuration was implemented with field effect transistors, the same name was used. 

The \$I_C\ vs\ V_{BE}\$ and the \$I_D\ vs\ V_{GS}\$ graph justifies the same. 




  Q2: This burns more power during write operations where one of the bitlines is pulled low by the write amp, again fighting this constant pullup.


The circuit in (a) is diode connected and hence the NMOS will be in saturation (Vdd > Vt assumed) and hence this would always try to pull up the bitlines to Vdd.  

For writing a '0', BL should be pulled down to GND but extra power would be needed to pull down BL because the NMOS is trying to pull it up. Similarly, for writing '1', BLB should be pulled down to GND.

Or,

While writing, the write amplifier will be trying to pull down the bitline (BL or BLB) to GND. So there will exist a low resistance path from Vdd to GND. This will cause more current to flow through the circuit increasing the power dissipation.




  What is advantage of (d) over (c)?


The obvious one is that (d) requires less number of transistors. 

The diode connected NMOS causes a drop of Vt across it. Now this Vdd - Vt should be capable of switching the transistors below. So The supply voltage can not be reduced beyond a limit in this circuit. Hence this configuration can be used for moderate supply voltages. Where as configuration in (d) can be used for smaller voltages.