How exactly does activating CLEAR cause an asynchronous modulus 12 counter to reset?
In this case, the flip-flops are set to 0 (reset) by the application of a logic HI to the reset input (labelled 0) of each flip-flop - not a falling edge. As long as the Selector line is low this cannot happen. When the selector line is HI, as soon as both F3 and F4 go high, all 4 FFs are reset.
If only F3 and F4 were connected to the Clear gate, it would be theoretically possible for F1 to be high and not affected by the reset pulse. This is unlikely to occur during &quot;normal&quot; operation, but for instance it might occur on power-on. Or, if for some reason the Selector line were not always high and were applied when the counter were at (let's say) a hex value of D, the same result would occur.
Also note that the Preset line (input &quot;1&quot; at each FF) works much like the preset line, except that it sets the FF LOW rather than HIGH. And yes, if you set both the 0 and 1 inputs to a HIGH condition simultaneously, Bad Things happen - so it's important not to do it. In effect, this means that if the Select line is HIGH, the Preset line should be LOW.