what is BUFGP used for?
In order to use an external clock signal effectively you will need to buffer it internally in the device.  This is because a single input clock signal usually drives lots of other internal gates, or in EE terms it has high "fan out".

You can read more about fan out here or here.

Most FPGAs have dedicated circuitry to buffer clock signals for you and ensure they are routed around the FPGA silicon properly using the lowest latency path.  You don't mention your device but the BUFGP suggests Xilinx.

In the document linked by apalopohapa you can find the following:


  Verilog Instantiation Template
  
  BUFGP instance_name (.O (user_O), .I (user_I));


So in your line of code you are declaring a BUFGP named BUFGP1 which connects the input signal CLK to the output signal board_clk (do you have this backwards?).

However you will also find this quote in the document:


  Synthesis tools usually infer a BUFGP on any clock net


So unless you are having specific issues with the Xilinx tools not generating a buffered clock signal then it might not be necessary to manually code it yourself.  Make sure your input clock comes into one of the dedicated clock pins on the device, there are usually only a small number of these.