32 Transistors As a 16x2 Mux
The functionality you're describing is exactly the same as what was discussed in PISO buffer for the MachXO2 a short while ago. Here's the first diagram from that answer:



Note that there's no switching at all required for the "write data" bus &mdash; you simply connect it directly to both RAM chips.

But you do need multiplexers (NOT demuxes!) for the address pins and for the "read data" bus, as well as the write enable pins.



In any case, trying to use BJTs to implement "pass transistor logic" is pretty much doomed to failure. The offsets introduced by all of those PN junctions pretty much destroy any concept of "logic high" and "logic low", especially if you're trying to interface to chips designed to TTL standards. Just get a bunch of quad 2:1 mux chips in the proper logic family already.