Substrate design in MOS ICs
There is no rule that mandates a P-sub/N-well process. In fact, there are many CMOS processes which work the other way, with N-sub/P-well. An example of a chip that uses such a process is the LMC660. A look at its schematic emphasizes this: the NPN's Q26/27 in its bias circuit are constructed as lateral N+/P-well/N+ (with a parasitic vertical substrate collector tied to \$V_{DD}\$). 

As far as CMOS IC design goes, the primary impact is to determine which devices (between NMOS and PMOS) can have wells at different potentials. 

As you probably know, a P-well should be more negative than the N+ source/drain diffusions of the NMOS inside it, and an N-well should be more positive than the P+ source/drain diffusions of the PMOS inside. If you have only one option of P-well (because the substrate is P-type), then you have only one option of \$V_{SS}\$; likewise, if you have only one option of N-well (because the substrate is N-type), then you have only one option of \$V_{DD}\$.

Most electronics are pretty happy to have only one \$V_{SS}\$, because more often than not it's the system ground. \$V_{DD}\$, on the other hand, is quite commonly a collection of voltages (for example, 2.5V, 3.3V, 5V...), and therefore it's useful for a circuit to have multiple N-wells so that it can interface with these different power domains. For this reason, P-sub/N-well processes are more popular than N-sub/P-well for CMOS.