fgpa timing constraint on enable signal
If you can guarantee that your enable will never be present faster than a particular rate, you can use a multi-cycle path constraint to tell the tools this.  You don't say which FPGA family you are using, but searching the vendors helpfiles for multi-cycle should get you the information you need.

Having said that, in my experience these constraints are hard to verify.  Checking that only the right logic is covered by them is hard, and if some additional logic gets included by accident, the design has a latent timing violation that is unknown to the designer.

So unless I have no other choice, I tend to aim for clock-speed improvement (for example using a better synthesiser, or pipelining, or..).  Then I can run that logic at full speed, even though I don't have to, and I don't have to worry about validating complex multi-cycle path constraints.