Xilinx Vivado: How are inputs/outputs handled that are not in the constraints file?
If you did not explicitly assign them in your .UCF file they are "randomly" assigned.  You should see B assigned to an output (as the output of your logic), and A and switch are assigned to inputs.  Open your PAR report to see where they were assigned.  Create a UCF file to constrain them, and add it to your PAR phase.  There are other constraints that belong in the UCF as well.  IO standard, slew rate, direction, setup/hold times, etc.

If you aren't familiar with a .UCF file syntax, look in the /docs of your install, or online for the "constraints guide"