VHDL: Constraining Record with another record
With code that analyzes:
library ieee;
use ieee.std_logic_1164.all;

entity rec_constraint is
end entity;

architecture foo of rec_constraint is
    type Axi4s_M2S is record
      Tvalid : std_logic;
      Tdata  : std_logic_vector;
      Tstrb  : std_logic_vector;
      Tkeep  : std_logic_vector;
      Tlast  : std_logic;
      Tid    : std_logic_vector;
      Tdest  : std_logic_vector;
      Tuser  : std_logic_vector;
    end record Axi4s_M2S;
    
    signal A: Axi4s_M2S(Tdata(7 downto 0), Tstrb(3 downto 0), Tkeep(3 downto 0),
              Tid(31 downto 0), Tdest(7 downto 0), Tuser(3 downto 0));
    signal B: A'subtype;
begin
end architecture;

VHDL -2008 supports record constraints in object declarations as well as a predefined attribute that returns the subtype of an object. With those the subtype of A can be used in the declaration of B.
Note that the record type declaration didn't match the type of signals A and B in the question nor was the record constraint complete.