Difference between 32 KHz clock output load vs. clock input impedance requirement
I have a wifi chip that requires a input impedence of >100kohms and &lt;5pF


You are misunderstanding the datasheet. That means that the input impedance of the clock input will be greater than 100 kΩ, and have a load capacitance of less than 5 pF.

This means that you need a clock source with a significantly lower output impedance than 100 kΩ, and can tolerate at least a 5 pF capacitive load. Luckily, just about every clock source, including your clock source, is able to drive this input.

Edit:

However, note the input signal amplitude specified: 200-1800 mV. The 3.3 V output from the oscillator exceeds this. A voltage divider should be fine, the 32 kHz signal is slow enough that a voltage divider is not an issue.