How does radiation produce transient bit errors in DRAM?
Transient bit errors can be caused by a single high energy particle that deposits enough energy into the capacitor that stores the SDRAM's data, a single bit.  This energy deposition can cause the bit to flip.
This phenomenon is a function of technology (CMOS being the most commonly used for SDRAMs) and feature size (the smaller the capacitor that stores the bit, the smaller the charge on that cap and so the lower the amount of energy needed to flip the bit).  It can also be influenced by package style, plastic vs ceramic, for example.
And yes, the susceptibility of a SDRAM cell to being flipped is related to the energy of the particle that hits it.  The higher the particle energy, the greater the chance of an upset.
This is an example of a Single Event Upset, or SEU.
Long term radiation effects fall under the category of Total Ionizing Dose, or TID effects.  These effects usually cause DC type of changes, such as increasing leakage currents and shifting operating point biases which over time cause the part to degrade or stop working altogether.
SEU effects can be mitigated by various forms of scrubbing and ECC.
TID mitigation means buying a part that is inherently more radiation tolerant/hard or adding shielding to the vehicle.  Note that shielding generally does NOT help with SEUs.
EDIT 1
The preceding discussion applies to individual bits/cells in a DRAM.  But a DRAM consists of more than just the storage cells.  A DRAM contains a lot of digital and analog circuitry that controls the writing and reading of data from the storage cells.  An SEU to a critical part of this read/write circuitry can render the entire DRAM inoperable, faulting all the data that is stored.  This type of fault needs to mitigated at the system level (i.e. system level EDC), not at the chip level.