PCB layout for SOIC packaged op amp
Although vias 'can introduce parasitics', the important thing is the detail, how much extra inductance in a via compared to a length of trace?

Your idea has merit, but without a more detailed analysis of path lengths, stray inductance, stray capacitance, of both layouts, it would not be possible to declare a winner.

In addition to overall length of the feedback path (and here we dive into more detail), the capacitance on the -ve input pin is a key factor in feedback stability, usually more important than the total length. Your method has to have a track long enough to escape the package on the side, whereas a via to the other side could place Rf directly opposite the -ve input pin.

It's often not clear whether 'short track length' is being used to encourage low inductance end to end, low stray capacitance to ground, or low phase shift when viewed as a transmission line. C to ground is a killer, and that stray ground capacitance varies proportionally to the length of the track, but only very weakly as the width, shortening the track is much more effective than making it narrower.

It's interesting to note that the highest speed op-amps (GHz GBW and above) have a pair of output pins both bonded directly to the output pin on the chip, one on the 'output' side for the conventional output, and one next to the input pin, for direct connection to the feedback components. Take a look at the Analog Devices' AD8045 data sheet for instance