What is the criteria of choosing a given pin pattern in ICs?
It's a complex topic that only the manufacturer can fully answer. There's lots of decisions when it comes to pin bonding, but in short, it's about EMC, internal supplies and internal clocks. The sensitive pins are those for supply, ground, oscillator/PLL and ADC. The GPIO pins around probably the least sensitive ones, so where they end up is the less important.

If you look at the S12Z part, you can see that they have clearly tried to separate analog and digital parts, with ADC and analog comparators to the bottom left, and digital buses SPI/CAN etc to the right. Analog supply at the bottom, oscillator to the left etc etc.

If you dig up the 80 and 112 pin versions of the S12 you'll see how more pins of the same kind expand next to each other. These are typically designed with the 112 pin version in mind and the smaller ones get pins stripped off in order to cram everything down to 48 pins, making the 48 pin version less intuitive than the 112 pin one.