What is power dissipation capacitance?
The power dissipation of a CMOS chip can be considered as the sum of the static power dissipation (leakage current times supply voltage) and dynamic power dissipation. 

Dynamic power dissipation in turn consists of the power dissipation related to switching internal nodes and drivers and the power dissipation related to switching external load capacitance. Every time you charge and discharge (one cycle) a capacitor energy is consumed E = \$ \frac {C V^2}{2}\$, so if the frequency is \$f_0\$  then the dynamic power consumption is P = \$ \frac {f_0 C V^2}{2}\$ (per node). Half the energy transferred is lost as heat on each edge. 

In the case of the 74HC595, the internal dynamic power consumption is then 

\$ P_{dyn int} =  \frac {f_0 C_{PD} V^2}{2}\$  (specified in the datasheet as with all bits switching) 

To get the total power dissipation you would add the static power dissipation, the above internal dynamic power dissipation and the dissipation due to load capacitance on each output 

(similarly it will be  \$ \frac {f_0 C_L V^2}{2}\$ for each output). 

Although the static power dissipation is mostly related to the power supply voltage, note that the dynamic power dissipation is proportional to the square of the supply voltage, so a reduction in supply voltage from 5V to 1.8V (2.8:1) will reduce the dynamic power consumption by a factor of 7.7:1. 

So, if you're a board-level designer and are interested in low power, you can use the slowest frequency and (especially) the lowest supply voltage possible. If you're a chip designer you want the parts to work at very low supply voltages (which means they can't handle relatively high voltages generally). As a side effect, such transistors tend to leak more so the static power dissipation increases even for transistors that are not switching at all.