D flip flop with asynchronous level triggered reset
The best answer for blocking vs non-blocking flip-flops assignment is already answered on Stack Overflow here. That answer also references to a paper by Cliff Cummings, here.

Now, the code for your second attempt will always result in with the behavior shown in the waveform, even with non-blocking assignments:

always @(posedge clock, rst)
begin
  if (rst) q &lt;= 1'b0 ;
  else     q &lt;= d ;
end


This is because the sensitivity list for signal rst is incorrect. The posedge keyword only applies to the signal immediately right of the keyword and not the following signals after the comma. @(posedge clock, rst) is equivalent to @(posedge clock, posedge rst, negedge rst). The else condition will be evaluated on the falling edged of rst, which is not desired.

A good linting, synthesizer, or LEC (logical equivalently check) tool should flag the dual edge trigger on rst as an issue; possible as a warning.