Adaptative Logic Module : Logic Element equivalence
In this file, it is written that 2 4 bits independent LUTs can be implemented in one ALMs. Does it mean that 1 8 bits LUTs can be implemented in an ALMs ? If not, how many ALMs are needed ?


No. Refer to Figure 6 on the PDF you linked (page 7). A single ALM contains two LUT4s and four LUT3s. There are only 64 bits of configuration "state" in these six LUTs -- 16 in each LUT4 and 8 in each LUT3 -- so it's impossible to use them to emulate anything larger than a LUT6 in the general case. As noted in Table 1 (page 2), there are some special cases where it may be possible to emulate a larger LUT, but these cases depend on the LUT contents having certain specific structures.


  When I set only one LUT in my design and compile, the number of Logic Element used is 35. This number is a little bit unexpected since I have read that an ALM should be equivalent to 2 Logic Elements. Is that correct ? In this case, does this value seem correct ?


Hard to say exactly without a lot more details on the design you're implementing, but there are a few possibilities that occur to me:


Are you looking at an exact count of logic elements, or is it estimating a number of "logic cells"? The latter is an inexact estimate of the number of 2-input logic gates that would be needed to synthesize a design, and as such is expected to be much higher than the number of LUTs or LEs used.
The fitter may have opted to not pack your design into a single physical LE, either because splitting it up may have helped with routing and timing, or because you've pulled out an intermediate signal that wouldn't be available in a single-LE layout, or even just because Quartus just didn't feel like it that day. (FPGA software can be fickle like that sometimes.)


Viewing the exact physical design that's been implemented in the Quartus Chip Editor may be instructive.