Circuit to enable (inverted) clock glitch free
I think, that in this case you should delay the inverted clock signal, using the even number of inverters between the CLK input of REG1 and the lower input of the AND gate.

Please note, that even in this case you may run into trouble caused by the metastability of REG1. To reduce this risk, I'd suggest to add yet one stage of synchronization of the ena signal (however of course it will slightly change the functionality, as ENA will be delayed).







simulate this circuit &ndash; Schematic created using CircuitLab

You can also try another circuits shown in the article linked in my response to your previous question, however you should keep in mind that the last and most promising one seems to be patented :-(.