Verilog Counter is not working
Your module port order in your jkfflop instances doesn’t match the module definition.
A way to avoid this is to use ‘ANSI-C’ style port declaration in the instances.
Example:
jkfflop ff1 (
   .J(j-input),
   .K(k-input),
   .clk(clk-input),
   .Q(q-output)
);

Then there’s no issue with port order: the port-to-pin connections are explicit.
But... that’s the hard way to do a counter. Here’s an easier way: use a procedural block. Example:
reg [3:0] count;

always @ (posedge sclk)
begin
    if (reset)
        count &lt;= 0;
    else
        count &lt;= count + 1;
end

This will synthesize to four flops with appropriate carry logic. The reset is necessary if you want to simulate the counter, otherwise it starts up in an unknown state. Here the reset is synchonous, if you want asynchronous, add reset to the sensitivity list.
Another hint: a case statement for the segment decoder will be much easier to understand.
There’s a few other things that could be better; but understanding procedurals and case statements are two very powerful tools in the Verilog toolbox for making readable, error-free code.