Parallel Prefix Adder explained
I recall benefitting from a version of this lecture: http://www.cmosvlsi.com/lect11.ppt
I think of the adders that compute "Propagate" and "Generate" signals as parallel prefix, but I might be wrong about that.

Parallel prefix adders are a good solution and generalization of the problem of how to describe logic circuits that add two numbers quickly. CLA may be implemented as a type of PPA that uses a repeated block of bits to perform ripple carry addition over a group of bits at a time so the number of logical stages is related to the number of bits, directly as it grows, but is some factor of the number of bits. There's an example in that presentation that has 4 bit groups, and it assumes a very high radix adder to do it. After talking about the CLA, you asked about it proceeds to describe most of the state of the art adders and the reasoning with which someone might select them. Each of those is based on a paper that describes them, and once you understand PPA's each of them is reasonably easy to implement.