Confused with the time diagram and wiring for this SSI interface
Am I doing wrong by not using CSn here?


Yes, you are wrong by not using CSn. It is clear from the datasheet that this signal is required and must be driven low, with the timing shown in the diagram you supplied from the datasheet.


  Where and how should the CSn pin be connected?


It would be driven by the same device (MCU?) which is driving the CLK signal (unless you are doing something very unusual).