Gate capacitance vs. Gate charge in n-ch FETs, and how to calculate power dissipation during charging/discharging of the gate
Like endolith says you have to look at the conditions for parameters. the 30nC are a maximum value for \$V_{GS}\$ = 10V. The graph on page 3 of the datasheet says typically 10nC @ 5V, then C = \$\frac{10nC}{5V}\$ = 2nF. Another graph also on page 3 gives a value of 1nF for \$C_{ISS}\$. The discrepancy is because capacitance isn't constant (that's why they give a charge value).  

The gate resistance will indeed have an influence. The gate's time constant will be (9\$\Omega\$ + 3.6\$\Omega\$) \$\times\$ 2nF = 25ns, instead of 9\$\Omega \times\$ 2nF = 18ns.

In theory there will be a slight difference between switching on and off, because when switching off you start from a higher temperature. But if the time between on and off is small (lots of margin here, we talk about tens of seconds) temperature is constant, and the characteristic will be more or less symmetrical.

About your side question. This isn't usually given in datasheets, because the current will depend on \$V_{GS}\$, \$V_{DS}\$ and temperature, and 4-dimensional graphs don't work well in two dimensions. The only solution is to measure it. One way is to record \$I_D\$ and \$V_{DS}\$ graphs between off and on and, multiply both and integrate. This transition normally will happen fast, so you'll probably can measure only over a few points, but that should give you a good approximation. Doing the transition more slowly will yield more points, but the temperature will be different, and hence the result will be less accurate.