How to truncate the least significant bits in a Verilog assignment?
There is no easier way to do this in Verilog. A logical shift right requires similar width parameters. 

This would be easier using SystemVerilog's streaming operator which left justifies assignments.

bit [BIG_REG_MSB_INDEX:0] filler;

{{&gt;&gt;{rSmall1,Filler}} &lt;= rBig;
{{&gt;&gt;{rSmall2,Filler}} &lt;= rBig;