How to implement Quartus IP cores using ALMs?
This is up to the design of the core. If there are configuration options for the core that determine how the internal operations are implemented, then yes, just configure the core however you like. If not, then no, there is no way to do that. IP cores are generally black boxes to the FPGA toolchain. They are usually synthesized separately and can do all sorts of stuff including direct instantiation of device primitives. When your design is synthesized, all the toolchain gets for the IP core is a netlist, and if that calls for a DSP slice, then that's what you get.