CMOS vs LVDS oscillator
(answering from the comments)

You could use a slower, inexpensive oscillator as your base clock, then use a PLL in the FPGA to generate various internal clocks at higher, lower or equal frequencies for use in your design.

The functionality of the PLL's that are available to your design will depend on the type of FPGA; by way of example (modern) Xilinx parts typically allow both multiplication and division by user-selectable integers between 1 and 32.  Multiple stages can be cascaded to get finer frequency adjustment.

Extending this to your requirements, you could use an inexpensive 16MHz oscillator as your base clock and use a PLL to multiply it by 20 to 320MHz for use in your design.

Exactly what your options are will depend on what type of FPGA you're designing for and how tight your clock tolerances are.  You need to carefully read through the datasheets of everything that you're considering using.