Charge pumps operation
When the clock is low, the first capacitor is charged up to Vdd, then the switch to Vdd opens, and the clock goes high, the relative voltage of Vdd of the capacitor is then offset by CK, as a higher voltage, the capacitor still had the same amount of charge, that has not changed, but the voltage on its top terminal is now a higher voltage, 

Next cycle this voltage is used to charge the next capacitor in the chain, this averages the voltage between the 2 capacitors in a charge (voltage) divider, so initially it would be closer to (Vdd + CK) / 2, but as time goes on and the second capacitor charges up with more cycles, as the next time will be (Vdd + CK) * 3 / 4 (the average of the 2 capacitor voltages), and so on and so on, until you end up with Vdd+CK directly,

Due to this, any kind of output load on a charge pump will cause the output voltage to fall, and the more stages you have, the furthur it falls.