What really limits off-chip I/O? Capacitance or Inductance?
One limiting factor for getting data off chip is impedance. I worked on a microwave divider chip a while ago, and the single-ended output terminal consisted of two adjacent pins for signal, flanked by two further pins for local ground, in an effort to get the impedance of the transmission line from chip to PCB down to something within spitting distance of a practical 50Ω. The requirement was high power delivered to the load.
High speed serial links like HDMI, SATA  etc use differential signalling and low swing at the receiver, so they can launch currents into practical impedances while allowing the chip to PCB path to be fairly high impedance. The requirement is high speed, with only sufficient power for good quality reception.
Another similar but distinct factor is charging the capacitance of the remote node. Why does Miller ignore inductance? He regards inductance as a complicating factor, which can in theory be eliminated by using a suitable geometry. It's a common simplification in this sort of analysis, choose a best case, and compute a lower bound for it. The actual performance will always be worse than this, due to the factors you have ignored.