VHDL internal signal assignment
You have multiple drivers for q0_s and q1_s:

architecture beh of reg2 is
    signal q0_s, q0_ns, q1_s, q1_ns : std_logic;
begin
    reg : process (clk, res)
    begin
        if res = '1' then
            q0_s &lt;= '0';
            q1_s &lt;= '0';
        elsif clk'event and clk = '1' then
            q0_s &lt;= q0_ns;
            q1_s &lt;= q1_ns;
        end if;
    end process reg;

    q0 &lt;= q0_s after 2 ns;
    q1 &lt;= q1_s after 2 ns;

    mux : process (load, q0_s, q1_s, d0, d1)
        begin
            if load = '1' then
                q0_s &lt;= d0 after 3 ns;
                q1_s &lt;= d1 after 3 ns;
            else
                q0_ns &lt;= q0_s after 4 ns;
                q1_ns &lt;= q1_s after 4 ns;
            end if;
    end process mux;


end beh;


Each process has it's own drivers for any signals assigned within that process.

The value of the signals is the resolved value of the two drivers, std_logic is a resolved type.  It uses the resolution function and resolution_table found in the body of the std_logic_1164 package to perform that resolution. 

These two assignments to q0_s and q1_s should be to q0_ns and q1_ns like found in the else:

mux : process (load, q0_s, q1_s, d0, d1)
    begin
        if load = '1' then
            q0_ns &lt;= d0 after 3 ns;  -- was to q0_s
            q1_ns &lt;= d1 after 3 ns;  -- was to q1_s


This gives a better result: