Logic gates that does not need to to tie to 1 k resistor and ground open inputs to drive it low
The behaviour of a TTL input is determined by its construction.
The only way to have a TTL input default to low would be to integrate the pull-down resistor into the chip, but this would increase the power usage when the input is driven high, so nobody makes such a chip.

Please note that in Designing with TTL (AN-363), Fairchild says:


  Unused inputs on TTL devices float at threshold, anywhere from 1.1V to 1.5V, depending upon the device and its family. While this usually simulates a “high”, many application problems can be traced to open inputs. Inputs floating at threshold are very susceptible to induced noise (transmitted from other lines) and can easily switch the state of the device. A good design rule is to tie unused inputs to a solid logic level.


So you should never have any open input, whether high or low.



To reduce the amount of components (but not cables) you need, you can share a single, appropriately-sized pull-down resistor for multiple fixed-low inputs. Alternatively, use CMOS logic ICs, whose inputs can be tied directly to VCC/GND.