How latches are used to implement High-speed VLSI Designs?
First of all, a latch is physically smaller than an edge-triggered FF, so it saves on die area and therefore reduces routing delays in general.

Second, every time you use an edge-triggered FF, you add its setup time and propagation delay directly to the overall path delay. The latch allows you to "hide" the setup time and its propagation delay is less, resulting in a lower overall timing penalty. In exchange, you must use a two-phase clock scheme and follow additional restrictions on how you design your logic.