Connection between std_logic and std_logic_vector(0 downto 0)
Do it like this.

uut: bloque_4 
    port map (
        ...
        wea(0) =&gt; write_en_b34,
        ..
        );


Its perfectly OK to associate slices or elements of port with a mix of signals and constants.  The only restriction is that if you associate any of the port bits then must associate them all.

Here is an example of entity foo with an 8 bit port_a.

signal s_1 : std_logic;
signal s_2 : std_logic_vector(3 downto 0);
...
x:  foo
port map(
  port_a(0)          =&gt; signal_1,
  port_a(4 downto 1) =&gt; signal_2,
  port_a(7 downto 5) =&gt; "000"
);


In the example above it would be an error if only some of the bits in port_a were not attached to a signal or a constant value.  It would not be an error if none of the bits in port_a were attached, so long as the port had a default value in the entity definition.