syntax error near module or module not declared?
There are several major issues I can see:


You have a random and completely unnecessary #include "adder.v" statement. (Though I see you say you have removed it, but why then is it still in your question)
Your adder module is not written properly. You have put an assign statement within an initial block which is not a legal syntax. Furthermore you don't want it to be done in an initial block as otherwise it would try to infer ROM type logic ("add these two numbers only at power up") using non-constant expressions which is not possible to do for synthesis. Get rid of theinitial statement.

module adder(
    output reg [3:0] S_out,
    input      [3:0] S_in,
    input      [3:0] coin
);
    assign S_out = S_in + coin;
endmodule

You cannot infer an instance of a module in an always block.

always @(posedge CLK) begin 
    ...
    adder jjjjj(.S_out(S_out), .coin(coin), .S_in(S_in));//here is the error -&gt; of course!!
    ...
end 


Remember you are not writing a program. Verilog is a HDL, you are describing hardware. Basically what you are describing here "always at the positive edge of CLK, suddenly add some extra hardware, then delete it again". That makes no sense as a construct and is an illegal syntax.

Instead you should be inferring modules outside always blocks. All hardware must exist at synthesis, it cannot be dynamically created from nowhere.
In fact that entire always block is complete nonsense. You are mixing blocking and non-blocking assignments, you are adding time delays which are not synthesisable (simulation only), you are  trying to instantiate modules as in (3), you begin and end statements are all over the place, etc.

I would highly recommend adopting the style of always using begin and end statements, and put each one on its own line - that will make it far easier for you and anyone else reading it to work out what you are trying to do. For example:

always @ (posedge CLK) begin
    if (reset) begin
        //do reset stuff
    end else begin
        //do non-reset stuff
        //Notice how it is much clearer with stuff on separate lines. and well indented.
    end
end