Understanding square braces in verilog
The provided Verilog code defines two 2-dimensional arrays. Once component of the array is packed and the other is unpacked. A packed array is sometimes refereed to as a vector.

IEEE Std 1800-2012 &sect; 7.4 Packed and unpacked arrays states:


  ... The term packed array is used to refer to the dimensions declared before the data identifier name. The term unpacked array is used to refer to the dimensions declared after the data identifier name.


IEEE Std 1800-2012 &sect; 7.4.1 Packed arrays states:


  A packed array is a mechanism for subdividing a vector into subfields, which can be conveniently accessed as array elements. Consequently, a packed array is guaranteed to be represented as a contiguous set of bits. An unpacked array may or may not be so represented. A packed array differs from an unpacked array in that, when a packed array appears as a primary, it is treated as a single vector.


IEEE Std 1800-2012 &sect; 7.4.2 Unpacked arrays states:


  Unpacked arrays can be made of any data type. Arrays whose elements are themselves arrays are declared as multidimensional arrays (see 7.4.5). Unpacked arrays shall be declared by specifying the element address range(s) after the declared identifier.


Declared on the left of the net name is the packed range definition; signed [I_width : -F_width]. Since I_width and F_width are both 5, the range is [5:-5], a 11-bit value. Being declared a packed, the value can be assigned as a whole, or assign a single bit, or part-select within the [5:-5] range. Begin declared as signed mean p_to_pipe[unpacked_index] can hold negative values using 2's complement. 

Declared on the right of the net name is unpacked range definition; [order : 0]. With order equal to 2, unpacked_index of p_to_pipe[unpacked_index] can have a value of 0, 1 or 2. Any other value would be out of range.

Note that x_to_pipe has the sample dimensions as p_to_pipe. The packed portion of the array carries over to all variables defined in the line. Unpacked is speciffic to one variable name. Therefore:

wire signed [I_width : -F_width] p_to_pipe[order : 0], x_to_pipe[order : 0];


Is equivalent to:

wire signed [I_width : -F_width] p_to_pipe[order : 0];
wire signed [I_width : -F_width] x_to_pipe[order : 0];


I recommend reading all of IEEE Std 1800-2012 &sect; 7.4. It is intended for SystemVerilog but it is free unlike the Verilog language reference manuals from IEEE. If you must strictly use Verilog, try finding a copy of IEEE Std 1364. Arrays are defined in:


IEEE Std 1364-2005 &sect; 4.9 Arrays
IEEE Std 1364-2001 &sect; 3.10 Arrays
IEEE Std 1364-1995 &sect; 3.8 Memories