VHDL: signal doesnt keep a value
This might not work out so well depending on your synthesis tool. All your signals and variables will be implemented as latches, which is in any case not a good idea.

I assume that T is generated in a synchronous process with a clock. If you convert your asynchronous process to a clocked process as well that will probably solve your problems. E.g.:

PROCESS(clk)
variable A:    std_logic_vector(3 DOWNTO 0);
variable B:    std_logic_vector(3 DOWNTO 0);
variable C:    STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN 
  IF rising_edge(clk) THEN
    IF T="00000" THEN--0
(...)