SAP-2 ADD instruction possible in 4 T states?
Answering my own question here.

The SAP-2 is modeled after the Intel 8080, which also has a 4 cycle ADD instruction.

According to the Intel 8080 System Manual, Table 2-16, during the T4 state of the ADD instruction the accumulator inputs are provided (SSS->TMP, A->ACT) but the result is not written back to the A register.

The write-back to A occurs during the NEXT instruction's T2 state in which Table 2-16 indicates ACT+TMP->A.

This is very likely to be the intended design of the SAP-2 and is simply a detail omitted from the text.