LUT vs. hard IP based multipliers on Spartan-3 FPGA for constant coefficient multiplication
According to the datasheet  the hard multiplier takes between 4 and 5 ns to propogate from inputs to outputs in combinational mode.  You'll lose a few more 100s of ps getting to and from the multiplier to the rest of your logic.  If that's fast enough, then just make use of it.

If not, build your LUT-based multiplier by just writing some code with the * operator in it, synthesise it, place and route, and see if that's fast enough. You may needs an attribute to force it to not use the hard multipliers (see the MULT_STYLE attribute in the XST manual).  You could even try just forcing a single LUT-based (non-constant) multiplier with that constraint and see what the result is - that's a very quick test.

Only if those fail should you go down the route of hand-building a LUT-based structure - and even then only if you've looked at the output of the synthesiser and are pretty sure you can beat it for some reason.  The synthesisers have been tuned to work out constant coefficient multipliers very well in my experience - I doubt coregen will gain much.



Wet finger estimate: A LUT delay is ~0.7ns. Assuming routing delays are of a similar magnitude, you can afford a chain of only 3-4 LUTs in the delay of the hard multiplier.  It seems unlikely to me that you'll achieve what you need in that depth of logic.