Unknown identifier error, new to VHDL and having trouble with this error. I use model sim
The port maps for some of your instantiations are referencing signals that have not been declared in the top level of your design.

For example:U17: full_adder port map (cin, AB0(1), AB1(0), add1(0), cout1(0));

Where in the top level are the signals cin &amp; cout1(0) declared? 
They are not, which is why you get the error message. As an aside, I bet the above statement is on line 67.

This is quite a common occurrence to new users to VHDL, particularly those who have used high level software languages. VHDL is a Strongly Typed language. It will assume nothing about your intent and will throw an error if you aren't exact in what you want, unlike other languages. Declare all the signals used in your design and your errors will go away. I will leave it as an exercise for yourself to identify the other missing signals.