IO mapped IO design problem
You are asking about the high 3 address lines, which are the 3 input bits to the 3 to 8 line decoder.  All 8 possible combinations of A5-A7 (same as A13-A15 in this case) cause one of the 8 outputs to be asserted.  It takes 011 to assert the output that drives the chip select of the 8255.

The schematic is sloppily written in that the outputs of the decoder aren't labeled.  From context, we can guess that the outputs are 0 to 7 top to bottom.  This means the output that drives chip select is 3, so the inputs to the decoder need to be 011 to enable it.

The part you highlighted by putting a box around is obviously just a mistake.  Clearly, the binary value is meant to be 0110 0000.  Note that the HEX representation of the same value is correct (60h).  Again, it's just a typo.