Using capacitive coupling to implement pulse transition
Your question is a bit vague &mdash; can you provide a specific example?

But in any case, the general concept is that an RC high-pass filter will convert a rising edge into a narrow positive pulse and a falling edge into a negative pulse. The negative pulses can be inverted to create a second set of positive pulses that's offset in time. Essentially, you end up creating  a "local" 2-phase pulse-type clock out of the original single-phase square-wave clock.

In older logic technologies (think vacuum tubes), it was possible to "tune" the pulse widths so that data would propagate through just one flip-flop during one pulse duration, so multi-phase clocks were not necessary. However, as systems became larger and more complex, and we moved on to newer technologies (solid state) whose characteristics were less well-controlled, this approach had to be abandoned as unworkable. Multi-phase clocks became common (up through the first generation of IC microprocessors), and eventually, we switched entirely to master-slave flip-flops, which allowed us to migrate to single-phase square-wave clocks, simplifying clock generation and distribution.