Why do we use a gray encoded signal by 2 stage flip-flop in asynchronous FIFO to avoid race-condition issue?
Obviously, the slow side of the FIFO is not going to see every state of the fast-side counter when it is counting at full speed. Fortunately, with proper design, such as using Gray code to transfer the values between clock domains, this doesn't matter at all. When the slow sample occurs, it will get some valid value of the fast counter, or at worst, one of two adjacent values if a bit happens to go metastable.
And of course, once the fast side pauses in its counting, the slow side will get the correct final value of the counter after the synchronizer delay.
I wrote this up in a lot more detail here: gray code clock domain crossing FIFO fast to slow