Stress testing an FPGA's power supply
What you describe in your question is not stress-testing the FPGA, it's stress-testing the power supply.

It sounds like what you want to know is, if you were to fully utilize your FPGA resources, would your power supply still be able to provide in-spec power.


Use the power estimator tool for your FPGA to determine the maximum draw for your device, given your clock frequency, I/O assignments, etc. The main thing is, when it asks how many registers and logic elements you're using, use a number that's 2x or so what's in your actual design, or 75 - 80% of what's physically available in the chip.
Choose power resistors to provide an equivalent load. Hook them up to the various supplies (VCC_core, VCC_io, etc).
Put the whole circuit into a thermal chamber at the maximum operating temperature you want it to run at. This is the part that will be hardest if you are not working in a well-equipped lab. If you're doing this for hobby work, put it on the dashboard of your car on a hot summer day. Run test leads out from the VCC nodes and ground to outside the chamber. 
Run the circuit for some reasonable time to allow it to warm up.
Measure the fully loaded and temperature-stressed Vcc's.


As other answers have said, cycling the load like you propose is not especially important.