What does these Verilog line of code mean?
These are reduction-ORs as you suspect. It is a unary operator, whose result is the result of OR'ing all of the bits in the operand. For example, supposing that x is declared reg[3:0] with value 4'b0011, |x is 1 while |x[3:2] is 0.

The first line indicates, "if any bit in count[0:13] is set, then perform the following block". The second indicates that data_addr_out_of_range is 1 if data_addr[26] is 1 or data_addr[25] is 1.