VHDL if statement doesn't work
The problem with your code is that there is no 'alternative'.

What should the hardware do if lp_good='0'? You have not specified that.
In simulation the VHDL simulator will at startup assign a value of 'U' (unknown). If lp_good stays at '0' the value of 'U' remains, but that does not exist in hardware. 

Thus as far as the synthesis tool knows the stat_led output should become 1 and never changes. There is no reset value thus it optimizes it to always '1'. You get an output port where the input is connected to the VCC.

I happened to have a Verilog design open and used the equivalent of your code:

always @(posedge sys_clk)
begin
  if (eoln==1'b1)
  begin
    stat_led &lt;= 1'b1;
    stat_led2 &lt;= 1'b0;      
  end
  ...


This is what comes out: