How to implement 8b10b en/decoding protocol between two FPGAs?
You need a "clock data recovery" (CDR) circuit. Your FPGA may include one as a hard core, if you are using signal rates in the gigabit-per-second range. 

This function generally requires some specialized parts, such as a voltage-controlled oscillator (VCO) and an analog control circuit for the VCO, that aren't easily implemented in the FPGA fabric. So if you want to work at frequencies where the FPGA's hard cores don't work, you would need to purchase an external IC to do this function. You'd need to choose a data rate that is used commonly enough to make it worth building ICs to work there. 

If you want to send this data at a relatively slow rate (say, below 50 Mb/s), you might want to use Manchester encoding instead of 8b/10b. With Manchester encoding, you can recover the clock from the data using a simple circuit requiring only a couple of gates, without needing a VCO or PLL. Your synthesis tool might not be happy about implementing this circuit, but at low data rates it should work just fine.