Signal is missing in the sensitivity list and expression truncation
Your always block logic is broken. Exactly as written, the logic you're describing will try to load out_13 both on clock edge and on reset assertion, because you're not including it in the else case.

There's no standard synthesizable equivalent to a flop which loads a dynamic value on positive edge of the clock and when reset is asserted, which is likely why the tool is complaining. 

Should look like this instead:

always @ ( posedge clk or negedge rst )
begin
if (~rst)
    clkState &lt;= 0;
else begin 
    clkState &lt;= clkState + 1;

    //Clk based State
    case (clkState)
    1: out_13 &lt;= (in_87)?in_86 : in_85;

    endcase
end
end