FIFO circular buffer size in over UART
Obviously, you need to have some process that is taking data out of the FIFO whenever it discovers that it is not empty. The FIFO then needs to be deep enough to take care of the worst-case mismatch between the putting-in rate and the taking-out rate.

Generally speaking, UARTs are normally slow enough that the other CPU activities can keep up, meaning that the FIFO can be relatively shallow, but if your application is sufficiently complex, you might find that a larger buffer is needed.

For example, if you know that the consuming process can be blocked for some amount of time, the FIFO must be deep enough to hold at least the number of characters that can arrive in that amount of time.