Why does CPLD has four clock sources?
Multiple clocks are often needed because several parts of the CPLD (or FPGA for that matter) will be programmed with separate functionality that operates asynchronously from other parts using separated clock domains. 

Other times some clocks will be generated from an external clock source using one of the specialty clock generator chips that created different clocks that have defined phase relationships. These can be leveraged in different parts of the CPLD/FPGA in a way to optimize the operational behavior of the chip programming. 

It is perfectly safe to have different parts of the CPLD / FPGA using different clocks. Your challenge as the designer is to use extreme care to keep each circuit confined to its own clock domain. And if it turns out to be necessary for some logic to make a crossing from one clock domain to another that you apply the necessary design rigor to apply the necessary clock synchronization circuits to the crossing paths to ensure that the resulting logic is stable and not subject to metastability problems.