understanding a SPI data sheet - FIFO size versus recieve register size
Receive register size = The number of bits per transfer. The minimum amount of data that can be sent.

Receive FIFO size = The number of transfers that can be buffered up waiting for the CPU to read them before data is lost. Since the transfer size is variable this is done using a fixed amount of memory rather than holding a fixed number of transfers in order to avoid wasted memory. The number of transfers stored will depend upon the transfer size.

Normally SPI buses are used in an interrupt based setup, once a transfer is complete an interrupt is generated. The CPU then stops what it is doing, copies the received data into a software buffer and then either processes it or sets a flag that there is new data and returns to what it was going before.

But SPI can run very fast, what happens if the CPU can't drop everything and read the data before the next transfer comes in? That's where the receive FIFO comes in. It allows the hardware to buffer up multiple transfers so that the CPU doesn't have to respond quite so quickly. Depending upon the amount of data being sent it may even make it practical to use a polled system rather than interrupts.