How to minimize the effect of threshold voltage mismatch of a current mirror?
How to minimize threshold voltage mismatch of a current mirror?
I want to minimize the effect of the mismatch ...

minimizing the mismatch and minimizing the effect of the mismatch are two different things.
for the former, no choice other than a different topology, pre-selection / classification of transistors before putting them in a circuit, or in the case of an IC, process uniformity.
for the latter, more options are available, like degeneration.
You probably want to pick one of the two for a more in-depth discussion.