SPI clock - slow frequency but fast rise time issue with waveforms
Fast rise times will cause lots of crosstalk, as you've mentioned this is independent of frequency. It's hard to see in the image what's traces and what's the grid. Parallel routes, or stacking routes on multiple layers make it worse. As you've done, a capacitor can slow the rise time, but you do need to be careful not to violate set up/hold times.

You may be seeing some reflections due to an impedance mismatch. I've seen source termination used on SPI clock lines to account for this. You want the output resistance plus your source resistor to equal the impedance of your trace.

I'm not familiar with the MCU you're using, but check the datasheet to see if you have any control of the slew rate, you might be able to slow it down. This is common on FPGAs which I'm more familiar with, but I have seen it on some MCUs I've worked with.