Is an FPGA the best tool to generate a continuous flow of square pulses with arbitrary amplitude?
An FPGA driving a reasonably fast DAC could work well for this application. 100 ns pulse width and 1 mV resolution with 1 V range implies a 10 Msps 10 bit DAC may be sufficient. Do you need to adjust the pulse width, or is the pulse width fixed? If you need to adjust it, what sort of resolution do you need? How about the time between pulses? If you use a 100 Msps DAC, then you can adjust both of those with 10 ns resolution. You might also be able to do that like that with a slower DAC. A 100 Msps DAC is also more likely to give you the 10 ns rise time figure you're looking for.