Optimal USB full speed ESD conditioning
There is no such thing a "better" or "worse" in FS signaling. There is a slew rate that must not be too fast, yet not violating the FS eye diagram mask. If you meet these conditions, the design is fine and will work fine.

The difference in recommendations in managing D+/D- lines in the above two variants is due to differences in the type/quality of USB PHY. 

If a MCU has an old primitive PHY without buit-in slew control (something like just two push-pull CMOS transistors), you do need 22pF-33pF load caps to limit the edge rate, and 15 - 22 Ohms series resistors to match differential cable impedance and avoid shifts in crossover points at transmitter.

If your MCU has a modern PHY that has a buit-in control over slew rate (using many dozens of cascaded drivers), you don't need any resistors nor caps.