Maximum rate between ADC-FPGA link for Igloo 2 vs Max 10
How can I find a ball park figure?

Option 1: Build your design and synthesize it with appropriate constraints and see if timing closes.
Option 2: Gain sufficient experience with a particular product family to have a good idea how complex a design can be run at a given frequency.
That said, if the I/O pins can handle a given data rate, there are techniques such as parallelization that should allow you to handle that rate in the fabric, at the expense of increasing the number of logic blocks used.