Signal connected to multiple drivers error in Verilog
You assign the value twice - once in the always@(Reset) block, and once in the always@(posedge Clk) block.
You typically cannot reset the &quot;contents&quot; of the memory. As such your construct of using an always block to reload the values will not work.
Assuming an FPGA, you can typically (though not always) set an initial contents for the memory. The contents is then loaded whenever the FPGA does a reconfiguration cycle (e.g. power on). To do this, you would place your $readmemh statement inside an initial block.
However this will not allow you to reset the contents by some signal. The only way to acheive the behaviour you seem to be desiring is to have two memories. The first a ROM which is initialised at power-on with the default contents you intend to use for your memory. The second is your writable RAM. When the reset signal is asserted, you would need to loop through each address (one address per clock cycle) copying the values from the ROM into the RAM. This would be done either in a single always block using if-else, or could be done in two blocks if and only if your FPGA supports dual-port memory.