Understanding the mathematics in the following article about EMC
This text only refers to rise time (edge or step) relative to propagation delay. He is saying the Rule of Thumb is the max length should be &lt; 3x the propagation delay (1way) but if &lt; 6x the prop delay it would be called &quot;high-speed&quot; and impedance matching becomes important.
This rule of thumb has repercussions in other areas of EMC, namely;

unintended RF radiation or conduction = egress
undesirable RF susceptibility by conduction or radiation = ingress
spectral impedance: mismatch or matching or transformation
Return Loss (RL) with spectral amplification or attenuation,
Propagation delay, echo amplitude (RL) from mismatch, overshoot, ringing
Rise time relative to propagation delay, with mismatched loads relative to signal path Zo
Signal integrity for logic and noise margin.
Physical track width, W and gap, G to ground track(s) or ground plane(s) with W/G from 2 to &lt;&lt;0.1

this results in impedance Zo for signals with wavelengths &lt; 10x the path length with \$Z_o=\sqrt{\frac{L}{C}}\$
affects L from 0.5 to &gt;1nH/mm from wide to long thin tracks
and (est.?) C=0.1pF to 1pF/mm for no ground plane to with a ground plane and very thin dielectric



Finally we can correlate f-3dB to the edge or risetime from 10 to 90% using.

\$f_{-3dB}=\dfrac{0.35}{t_R}=\dfrac{0.35}{&gt;3 length} ~ \$

Conclusion

i.e. the signal path  circuit path of more than 10% of the standing wavelength of the max frequency component then controlled impedance must be used.  It essentially limits the path length of an uncontrolled impedance transmission line not the max length of a matched impedance line...

~~ This the Rule I used. ~~



For a simulation of what happens when you violate this rule

In regards to your question 75mm/ns vs 150 mm/ns is just another way to defining &quot;High Speed&quot; for both ends mismatched and 2 way echo time.  This means for all 3.6V logic with &lt; 1ns rise time you ought to be using controlled impedance and also possibly for 5.5V logic family in PCB layout.  Whereas in old CMOS 4xxx family we did not have to.