How to Calculate Appropriate R-2R D/A Converter Resistor Values?
To a first approximation, the resistance R cancels out, however things are not so simple. 

One factor that needs to be considered is the performance of the switches. If they are CMOS outputs they will have a substantial resistance, it will be different between switches, it will be different for "high" vs. "low" and the resistance will vary with temperature. 

Take, for example, a CMOS buffer such as the CD4050. From the linked data sheet, we can see the output characteristics. Let's assume 10V (+/-5V operation). 

 



The sourcing resistance is about 220 ohms, and the sinking resistance about 55 ohms maximum. 
It will increase by perhaps 40-50% at 125°C from the 25°C values in the graphs. 

So, even if we reduce the 2R resistors by some average value of the switch resistance, there will be errors. If you want the error due to switch resistance to be much less than one LSB on your 4-bit DAC, you can calculate a minimum value for 2R. Say we choose something like 100K. 

The maximum value of R will be limited by input bias current of your amplifier and noise, and also by parasitic capacitance if you expect the DAC to have good high frequency performance. For example, an amplifier with 200nA of input bias current and with R=100K would have an output voltage error of \$ 2 R \cdot 0.2\mu A\$ or 40mV. 

That could be reduced in cases where the offset current is much less than the bias current by placing a matching resistor on the non-inverting input of \$ 2 \over 3 \$ \$ \cdot R \$ since the ladder has a constant impedance looking into the summing node of R. 

It's pretty easy to achieve sub-LSB errors with a 4-bit DAC, but the difficulty increases rapidly as the number of bits increases.  







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