Why PMOS act like "close switch" when zero voltage
The gate voltage is relative to the source. So when the Vgs is less than* the threshold voltage, significant current  can flow from source to drain (often threshold is specified as something like 250uA). 

In your example where Vg is zero, Vgs is -Vin. So if, say, Vin is +5V then Vgs is -5V and the Rds (assuming a logic-level MOSFET) can be very low.  

* greater in magnitude, but negative in sign

Example datasheet: 



So if Vin is +5V then Rgs(on) will be less than 60m\$\Omega\$ when Vg = 0. 

When off (Vg = +5V) the leakage is guaranteed to be less than -1uA at 25°C.