how to draw a timing diagram for a logic circuit
Generally, you want to show the external inputs at the top (like your diagram does), and outputs along the bottom, and then show how a change in one of the inputs affects the system.

However (IMO) the timing diagram shown in your example is missing some important information: which input signals directly affect the outputs of various gates.  I have added the additional information here in red:



so now it is clear that when ¬S goes low, this forces Q to go high after a propagation delay tp2.  Q high along with ¬R high makes ¬Q go low after propagation delay tp1.  This is now a steady state and no further changes take place as a result of ¬S going low.

You can get a little more elaborate, such as showing on the diagram that both ¬R high and Q high ANDed together cause ¬Q to go low.  This makes it more clear that just one signal ¬S low causes Q  to go high, but two signals ANDed together (¬R high and Q high) to make ¬Q low.



To draw diagrams like this, you just change an input, and then follow it through all circuit to see how it changes the state of various elements.

In your example. assuming the D flip-flops are positive-edge triggered (like the 74HC74), and all of the flip-flops are initially reset (Q low, ¬Q high) then a rising edge clock pulse on vstup will set the first flip-flop high.  A second clock pulse on vstup will set the first flip-flop low and the second one high etc.