Should I use an asynchronous or synchronous reset?
This choice will depend a great deal on the application and use cases of the FPGA. Does it get reset only when first powered up or is it reset periodically during operation? Is the reset generated internal to the FPGA or externally? Can you synchronize the reset input when it enters the FPGA and then use it as an asynchronous reset?
It is important that you consider metastability when making this decision. If you have a truly asynchronous input to a synchronous design then metastability can happen.