8 Bit Computer Program Counter (4 bit Counter IC) Counting When Disabled
Get leaded 0.1uF caps, spread the leads out, and insert them from pin 7(GND) to pin 14(VDD) over the top of each IC.

You have made physical changes, and inductances that were LOW ENOUGH prior to changes, may not be low enough now.

Another risk is the lack of GROUND GRID. 

============================================

back at university I implemented a 70-TTL-IC tic-tac-toe machine.

Knowing little of EMI, and not yet concerned with V = L * dI/dT, I had seen professional implementation of large IC systems using wire-wrap (Augat) boards that provided solid GND and solid VDD planes (punctured by thousands of wirewrap pins).

Having no budget for such niceties, I merely included X+Y ground wires (and X_only VDD wires), soldered at each X+Y at every crossing.

These X+Y parallel wires (5 for X and 18 for Y direction), soldered at each opportunity (4 * 17 = 68 nodes) were a fine GROUND GRID and ensured the 5 nanosecond TTL edges were always within 0.1 inch of a return_ground_wire.

With 0.1uF bypass caps across each of the 70 ICs (typically pin 14 to GND grid), there were no debugging issues.