SMPS Layout, capacitors in parallel placement
The capacitance between SW node and everything else is charged and discharged on every cycle, which wastes energy and emits noise. So you should minimize that capacitance. If the layout in the appnote suggests routing SW node down a layer with vias so it has maximum capacitance, then the layout in the appnote is retarded and you should ignore it.
Here's a finger-painted improvement:

This minimizes the area of the hot loop.
Note you should not push the inductor away to place your caps, because that increases the area (and capacitance) of the SW node. Instead put the inductor on top as I did, and you have plenty of space on the left for the caps.
Also all the GND vias are in the same spot, which minimizes the amount of HF current noise injected into your ground plane.