Edge aligned Source synchronous outputs
In system synchronous interfaces, that is indeed a hold violation cz normally we want everything to be captured ONLY on the next clock edge.

In edge aligned source synchronous interfaces, clock is regenerated and fed to the receiver along with the data with minimum line to line skew. 

A sample from the same document:



The launching clock and the capturing clocks are hence two clock domains. Whether setup/hold has got violated or not depends on what is our desirable operation in this circuit.

Here our desired operation is to capture the data in the same clock edge which is transmitted along with the data. Hence our setup check will be between the SAME edges and hold check will be between the launching edge and the clock edge BEFORE it. But by default timing analyser will check setup and hold between next and same edge respectively. So We tell our requirement to the timing analyser using multipath constraint:



Timing constraints can be complex for source synchronous. The documents seems to cover every aspect well.