Quartus II Memory Read Clock Problem
Well, it's pretty hard to read the diagrams, I can't see the crucial M_ADDR, M_INP and M_OUT on the diagram as I said in the comments, and I know nothing about Quartus II, so I feel ideally qualified to comment...

Looks to me like you have either a stage of latches either in the address path or in the data out path which is causing the displayed output data to be one clock cycle delayed relative to the displayed address.



So it's not reading data from the wrong address, it's just delayed.