Relation data-rate and bit-rate of ADC
This answer is not exact but should help to provide at least a good intuition.

In a word the answer is "decimation".

As explained in this Maxim tutorial and other places, the front end of a delta-sigma ADC yields a 1-bit data stream:


  The output of the sigma-delta modulator is a 1-bit data stream at the sampling rate, which can be in the megahertz range. The purpose of the digital-and-decimation filter [...] is to extract information from this data stream and reduce the data rate to a more useful value. [...]


When you decimate a sampled signal, you in general gain one extra bit of resolution each time you halve the frequency. So a set of 1-bit samples at \$f_{s0}\$ could also be represented as a set of 2-bit samples at \$f_{s0}/2\$, or a set of 3-bit samples at \$f_{s0}/4\$, and so forth.

So for \$n\$-bit data we'd need to halve the frequency \$n-1\$ times, which is not quite the formula you have above -- we're missing one factor of two. I dunno, maybe the delta-sigma modulator is already sampling at \$f_{clk}/2\$?

BTW your datasheet might not mention \$f_{clk}\$ explicitly, but the table on page 15 shows quite neatly how each time we add 2 extra bits to the resolution we cut the sample rate by a factor of 4. (Note that the "data rate" in that table is samples per second, not bits per second.)