When is the Length of this std_logic_vector defined?
The length is defined by whatever you connect to the MySignal port. This is fixed when you "elaborate" the design, after compiling it, but before running it (or synthesising to hardware).  

The formal details are given in the other answer. 

The advantage of this approach is that you can write the unit once, and use it in different places, on inputs of different size, and (if written correctly) it just works. Change the input size? No problem, no maintenance needed.

Worth learning how to write it correctly. A few guidelines:


Length is not the only attribute : keep the list handy, and use them.
Check input parameters appropriately. Do two input ports have to be the same size? Assert A'Length = B'Length report "Size mismatch" severity Failure; This flags problems when you use it outside the cases you designed it for,
Avoid magic numbers - replace for i in 7 downto 0 loop with for i in MySignal'range loop
EDIT to add one : be wary of connecting up ports with the opposite direction (e.g. downto instead of to) depending on what the unit does, and if necessary, unit test with both directions.