Why is a 0.001uF capacitor in parallel with the base-emitter of this transistors?
Yes, this is a circuit to limit BOTH edges on a relatively high voltage (12V) signal controlled by (presumably) PWM output from MCU. This is a quick LTspice simulation of the circuit:



Edges are reduced to about 1us rise and fall time. Funny part is that removing of C1 or increasing it to 1uF has no effect on any edge, it is fully defined by C2.