How can a shift register be used to debounce a switch?
To answer your specific question, most flip-flops in general, and the flip-flops used in shift registers in particular, have a minimum clock-to-output propogation time. What this means is that the output won't change state for a certain amount of time after each clock edge, and this time is greater than the maximum input hold time of the next flip-flop.

In most cases, each flip-flop is designed so that the required input hold time is in fact zero. And no flip-flop has a minimum clock-to-output delay that is less than zero.

When you connect flip-flops in series to deal with potential metastability, even if the first one goes metastable, it can't immediately case the second one to go metastable; the metastability must persist for a clock period before it could potentially make the second one go metastable as well.