How to find power, delay, and area of a synthesized design using Design Compiler?
Here is not an ideal solution, but I would give a try.


Read the gate-level Verilog file with -netlist option, so it can be read faster than an RTL file.

read_verilog -netlist my_netlist.v

Ensure that Design Compiler doesn't optimize the design.

set_dont_touch my_netlist

Source constraint files if available. If not, define clock(s) at least.

source constraints.sdc

Compile the design with -only_design_rule option, so that mapping optimizations are not performed.

compile_ultra -only_design_rule

Then generate the reports.

report_timing
report_area
report_power



P.S. These commands don't form a complete script for synthesis.