Proper clock generation for VHDL testbenches
The simulator can't really be blamed for sometimes acting like the clock happened right after or right before the input changes, if you assign both clk and inputs using wait for.  Asking if one style is superior or inferior to the other is, in a way, the wrong question.  You need to specify behaviour in a non-ambiguous way, if you desire a deterministic and non-ambiguous output.

What I've done for years and has worked for me pretty flawlessly (for synchronous designs) is to assign the inputs preceding them with wait until rising_edge(clk) or wait until falling_edge(clk).  How you generate the clk becomes unimportant.  For simple testbenches the after one-liner does the job nicely and succinctly, but does not offer the flexibility of a process with wait for or wait until statements.

I have a little simple procedure that has served me well:

procedure wait_until_rising_edges(signal clk : in std_logic; n : in integer) is
begin
    for i in 1 to n loop
        wait until rising_edge(clk);
    end loop;
end procedure;


Which I keep in a tb_pkg.vhd that I always use in testbenches.

A use example could be: 

some_stim_proc : process
begin
    some_signal &lt;= '0';
    wait_until_rising_edges(clk,900);
    some_signal &lt;= '1';
    wait_until_rising_edges(clk,100);
end process;


Some designers assign their stimulus signals at the opposite edge to what the unit under test is sensitive to.  I personally don't like doing this because it is not how the rest of the circuit will simulate, where signals change at the 'trigger' edge.  But there is certainly nothing wrong with that approach.  The above procedure can also be used for it.