Problem using FSL with microblaze
Close the EDK and take a look at the system.mhs file. You should see the FSL clock and reset lines connected to sys_clk. If not, you can add them straight into that system.mhs file and re-generate the bitstream.

You need two lines like this in the BEGIN/END block

BEGIN fsl_v20

  PARAMETER .... 
  PARAMETER ....

  PORT SYS_Rst = sys_rst
  PORT FSL_Clk = sys_clk

END  


For a late night read, browse the FSL patent. It won't help you with your implementation, but I find it's always interesting to read up on a technology patent:  

http://www.google.com/patents/US7380106