FPGA floating pins, when place pull-up/down resistor on Input or Output
This answer was given by a member of Xilinx staff to the same question on the Xilinx forums:


  In http://www.xilinx.com/support/documentation/user_guides/ug191.pdf, apge 18, the HSWAPEN pin  if pulled to ground, will enable the weak pullups on all IO pins prior to configuration.
  
  After configuration, a pin may be set to pull up, or pull down, or to remain floating (effectively tri-state) or be driven high or driven low, depending on the IO standard chosen.  It does no harm to have pins float.
  
  The default in the software is probably not something you would like to rely on.  It is far better to design the IO to do what you want it to do and state it explicitly.
  
  I believe the default is a weak pull down for unused pins, however.
  
  The weak pull up and weak pull down may often be too weak:  a resistor of the proper value is recommended if there is a standard that you are trying to meet, as opposed to relying on the weak internal pull up or down.
  
  Austin
  Austin Lesea
  Principal Engineer
  Xilinx San Jose