Understanding Common mode voltage
LVDS signalling is depicted here on the right: -



Link to website where I stole the picture.

The common mode voltage is the average voltage of the upper and lower digital values. Upper is 1.40 volts and lower is 1.05 volts hence, the common mode voltage is 1.225 volts.

So, as you can see the transistors are neither fully on nor fully off but biased at 1.225 volts. Reason: you won't get high speed data with fully turned on or off transistors (as in CMOS).