ADC outputs random values to constant input
It is hard to give you an answer, because there is no obvious error. As my ideas exceed the limit of the comments, I write it as answer.


Did you design the circuits around the ADC well? I.e. decoupling caps between Vcc and GND and Vref and GND, may be between In+ and GND
It seems you have a scope. You should inspect DOUT while triggering on the falling edge of !CS. You should then be able to see the 24bit answer consisting of a 0 followed by the value, MSB (11) first. After bit 0, it starts to output bits 1...11 again. So, the bit stream is symmetrical, and the bits in the center should flip due to noise, while the outer should not.
The datasheet says a minimum cycle takes 16 clock cycles, while the output has a length of 24 bits. Though the datasheet does not mention it, it seems you can stop the output and initiate a new conversion after bit 0 has been put on the output. Do you do that, and can you suspend it for debugging?
Is !CS high for a sufficient period of time? I found no minimum, but may be, there is one.
The frequency of 3.125MHz is about the maximum the ADC can handle. Can you reduce it (down to 10kHz) to check if it causes problems? Also check if the waveform is in a good shape at the input of your micro controller / FPGA.


Finally, you should first check if the ADC gives reasonable results, which is easy to test with a scope. If everything is fine, you should think about the code of the micro controller / FPGA. As the ADC is quite simple, I doubt that it gives an output of 0 the first time. It's more likey you have a firmware bug.