Signed Addition of two std logic vectors while looking for overflow and carry
Your implementation is not correct:


You must perform the sign extension before the addition of a and b.
A signed addition has no carry Flag, only overflow (it can be calculated but it's not valid); unsigned addition produces a carry flag but has no valid overflow.
The sign-bit is -- per definition -- always store in the highest bit


This could be a more or less nice rewriting, which is more generic. It only depends on a, b and c's length. So you could reuse this code for 16 or 64 bit, or whatever.

-- create locale signals with suffix '_s' for signed
-- both signals have one more bit than the original
signal a_alu32_s   : SIGNED(a_alu32'length downto 0);
signal b_alu32_s   : SIGNED(b_alu32'length downto 0);
signal sum_alu32_s : SIGNED(a_alu32'length downto 0);
signal temp        : std_logic_vector(2 downto 0);

-- convert type and perform a sign-extension
a_alu32_s &lt;= resize(signed(a_alu32), a_alu32_s'length);
b_alu32_s &lt;= resize(signed(b_alu32), b_alu32_s'length);

-- addition of two 33 bit values
sum_alu32_s &lt;= a_alu32_s + b_alu32_s;

-- resize to require size and type conversion
o_alu32 &lt;= std_logic_vector(resize(sum_alu32_s, o_alu32'length));

-- flag calculations
--c_alu32  &lt;= sum_32_s(sum_alu32_s'high);

-- concat the three relevant sign-bits from a,b and sum to one vector
temp     &lt;= a_alu32_s(a_alu32_s'high) &amp; b_alu32_s(b_alu32_s'high) &amp; sum_alu32_s(sum_alu32_s'high);
ov_alu32 &lt;= (temp = "001") or (temp = "110");