Vivado : constraints setup for SPI interface with common clock
First of all:

The timing (maybe) is the most essential and hardest part of the FPGA development. So first I suggest to read/watch timing guides.

Measuring technology:

Of course, it is impossible to make mathematically equal delays. (What's more not just delay, any two quantity cannot be exactly equal.) So you need to define the ranges in between you can tolerate the differences of delay. So more precisely what do you mean in synchronous?

Particular:

I suggest to read this guide. (This is an Altera guide, but the methodology, and the xdc syntax is the same.) There is a detailed template on page 9. 

So you need to get the extremes of delays of your boards. The full pin-to-pin delays. Ask HW guys, or measure or simulate. You need the min-max values in all possible corner case. (Temperature, voltage production distribution etc.) Then fill the template with the values.