Maximum Clock Frequency
I suspect that you have failed to add constraints for the input setup time and the output delay. These must be added to get accurate timing estimates. Also, you probably need to add an additional set of registers at the input pins and another at the output pins. Once you add these registers the minimum estimated clock period should be equal to the largest propagation delay through the combinational logic plus the FF setup time plus the FF clock-to-Q delay plus wiring delay.