FIFO IP CATALAOG independent clocks
Looking at the waveform the FIFO has a fall-trough time of ~14 clocks. The behavior of the status flags after a reset seems such that it gives a 'safe' state (See below). For details you have to ask Xilinx about that. I am only worried about the 'X' from the tb_wr_rst_busy.

Further I advice you not to write to the FIFO when it claims to be full. Your three times 0x03 coming out corresponds with your write enable active at the same time as the full flag is low. 

Same for the read: do not read when it claims to be empty. 

This is also the likely explanation for the status flags after a reset: On the write side it claims to be full, on the read side it claims to be empty. This should prevent your logic from 'doing' anything with the FIFO until the reset has completed.

And yes, a FIFO with independent read and write clocks (Asynchronous FIFO) is bound to have large latency between input and output.