Dealing with arrays in HDL
In verilog you use a generate like:

   genvar i;

   generate

     for (i = 0; i &lt; 16 ; i = i + 1) begin: muxes
          Mux4Way m(.a(a[i]),.b(b[i]),.c(c[i]),.d(d[i]),.sel(sel),.out(out[i]));
     end

  endgenerate