Generate an n bit random number in Verilog
If you are able to use SystemVerilog, you can randomize a number of any width.  Either declare it as rand within a class, or use std::randomize.  Here is a simple example:

module top;

  bit[69:0] vec;

  initial begin
    assert(std::randomize(vec));
    $display("vec = %070b", vec);
  end

endmodule


If you need to stick to plain old Verilog, I think the hack you suggested is the best, simplest, and possibly the only choice. I don't think there is anything in the language to help, since $random returns a 32-bit number.

If you simply want to avoid declaring new variables and explicitly concatenating them, you could do something like this.

vec[31:0]  = $random;
vec[63:32] = $random;
vec[69:64] = $random;