FPGA how to create delay
You would use either pipeline registers or FIFOs to take up the delay. Pipeline registers are good for short delays, and you essentially get one cycle of delay per stage. At their simplest, they act like shift registers, but it is also possible to have handshaking between stages. FIFOs are good for longer delays. A FIFO will store the data in an internal RAM for the duration of the delay. Another advantage of a FIFO is that it can cross clock domains.