How to pass a signal from one module to another using dot operator in verilog
Your approach would not be synthesizable (ie., would not translate into real hardware). You don't want to use a backdoor to your memory array, it's like adding read ports that don't exist.

I'm guessing you are trying to build a pipelined implementation. At cycle 1, read the memory content at address AR. At the next cycle, decode the value you obtained and assign it to PR, DR or GR depending on the decoding. Notice how you don't have to read it again from memory, you already saved it at the previous cycle.