Unexpected behaviour in Altera clock crossing FIFO
I've designed a few FIFOs and the truth is that there is no reason for the FIFO to output zero when empty. Think of a FIFO as having two pointers: a write, and a read pointer. When you push data it is written to the write pointer address, and the write pointer is incremented. When you pop the FIFO the read pointer increments. The output of the FIFO is the data pointed by the read pointer.


Now, if there is no data to pop, you simply do not increment the read pointer. So the output will have some data that is not valid, probably the last valid data. That is why you usually use empty and full signals. 

Of course you can change this behavior,  but usually it is not required. If the output data is not valid, you do not care about it.