Buggy VHDL UART receiver
Your edit doesn't make any sense &mdash; you've changed the timing for the start bit, but not for any of the other bits. Furthermore, you only changed it for the clocked process, but not the unclocked process that actually determines the value of next_uart_state.

The main problem with your original code is your counters. For some reason, you keep resetting them to all-ones instead of all zeros. This adds an extra state to each counting sequence.

For example, your sample_count runs from 0xFF (-1) through 0x13 (+19), which is a total of 21 states, not 20 as your comments imply. This creates a 5% error in the sampling rate, which is enough to create a problem after one or two bytes have been received.

In addition, your code waits for the full period of the stop bit before going back to look for the next start bit, which means that it can never "catch up". Instead, you should verify the value of the stop bit halfway through, and then immediately go back to the START state to look for the leading edge of the next start bit. If you do this, then even if the receive clock is a little slow with respect to the transmit clock, it will be able to keep up.

Finally, I've seen lots of ways to code state machines in HDL, but this one really takes the cake. Why is your clocked process casing on next_uart_state instead of uart_state? This creating a lot of strange boundary cases that will confuse anyone reading this code &mdash; and I think you have even confused yourself.