Unexpected Behavior: i2s L/R clock only works under arbitrary conditions?
BitClk upon which you condition an always block is not a legitimate clock, but a derived signal.
In simple terms, Don't do that that.
Instead, clock your output registers from an actual clock, using a clock enable.
Work out your code such that the I2S data changes based on the source clock, when enabled by a determination that you are at the appropriate phase of division thereof.
It's actually impressively useful that the hardware so beautifully and observably glitched in response to this classic design mistake, as that really focuses attention on the fact that it is a mistake.