VHDL - Quartus II inferring latches on circuit
You need to add some default assignments:

process (y_i, estado)
begin
  --default assignments
  estaprox &lt;= estado;    -- stay in the current state, unless the case statement calculates a 'jump'
  z_o      &lt;= '0';       -- assign all outputs with a default value to prevent latches

  -- next state calculations
  case estado is
    when a =&gt;
      if y_i = '1' then
        estaprox &lt;= c;
        z_o      &lt;= '1';
  [...]
  end case;
end process Combinacional;


Three additional hints:


Some time in the future, you'll get into trouble with these short state names, if you decide to use these also as signal names: One solution could be a prefix "st_" for every state name.
Signal estado should have a default value (start-up value):
signal estado : tipo_estado := a;
You can shorten some states, if you want to :)

when j =&gt;
  estaprox &lt;= a;
  z_o      &lt;= y_i;

when k =&gt;
  estaprox &lt;= a;
  z_o      &lt;= not y_i;