Measuring phase difference - LTSPice simulation problem
The D flip-flop is working as expected, but your simulation has other issues:- 


the LT1716 comparator is much slower than the uA710 (~3us switching time vs 20ns). At 20kHz this slow switching causes noticeable pulse timing distortion. To improve accuracy you need to lower the input frequency (to eg. 2kHz). 
Your digital logic blocks are set at their default logic levels of 0-1V (compared to ~0-3.5V for TTL) so the output amplitude will be lower than in the original circuit.  


Note that the uA710 has TTL compatible outputs, but with a negative supply the LT1716 will pull below ground (which is not compatible with most digital logic families). It only works in LTspice because the simulated logic has no input voltage restrictions.   

Other issues are shared with the original circuit:-


No resistor between the flop-flop output and 2N2369 Base. In a real circuit this would probably stress the flip-flop and increase saturation voltage of the transistor.
The 2N2369 has a fairly high saturation voltage which affects the output when it is turned on. It should be replaced with a low saturation type such as FTZ849.    
When the transistor turns on it reconfigures the associated op amp from inverting to non-inverting mode, but also lowers the impedance at point E which reduces the signal voltage. This can be fixed by inserting a unity gain buffer amp between the output of the low pass filter and the 2x 15k resistors.