NMOS/PMOS logic vs. CMOS logic
I'm assuming you would relate this to the most basic forms of CMOS logic, the inverter:



For the PMOS it is still common to also use \$Vgs &gt; Vt\$ for the ON condition. But note that then the PMOS Vt would then be negative !

Condition 2 \$Id = 0\$ can also be achieved with both transistors OFF.
So condition 2 does not always imply condition 1. But for the inverter powered with a sufficient Vdd (If Vdd = 0, that would also imply Id = 0)
then either the NMOS or the PMOS transistor is ON (in a conductiong state). That is assuming Vin is either equal to 0 V or Vdd.
(If Vin = roughly \$Vdd/2\$ then both transistors are conducting and Id would not be 0).

Id = 0 is not related to the state of the circuit. It is similar to the situation that a light switch can be ON or OFF, it does not mean a current has to flow. Removing the lightbulb (so no current can flow) does not prevent the switch from being in the ON or OFF position).

Likewise in an inverter depending on it's state either the NMOS or the PMOS is in a conducting state, that does not mean a current Id has to flow. This is the great benefit of CMOS logic, (almost) no current flows when the logic is in a static position.