3-to-2 line encoder (or generally 2^(n-1)-to-n) -- not priority, but telling how many inputs are on?
The is a fairly standard building block when implementing a multiplier matrix (you are effectively &quot;counting&quot; the number of ones in a column).  It's generally referred to as a &quot;compressor&quot; and there are various forms 3:2, 4:2, 7:3, etc. that wind up giving you what is called &quot;carry-save form&quot;, ie. 2 numbers which must be added together.
Most compressors can be built out of cascaded full-adder blocks.  The 74LS183 is a dual full-adder chip.

This definitely will make a difference in how many gates are needed. I feel it.

Unfortunately, your &quot;feel&quot; is not correct for the compressor.  The problem is that a &quot;1&quot; can come from anywhere in the full number of bits.  So, at some point, you may have to add bit 2^(n-1) to Bit 0 to get the count.  That means that somehow you have to cascade all bits together so the number of gates is fixed.
Once you have the carry-save format, you have to add the two pieces together.  Your &quot;bounded sum&quot; is called a &quot;saturating add&quot;.  Yes, you can probably save some gates at this step as you don't automatically have to add all the positions (if there is a 1 in any position above the saturation point you can just return MAX).  However, that doesn't save you as many gates as you think (you still have to OR all those bits together).
However, if you are implementing in TTL you'll be better off using something like a 74LS382 (or 74LS381) and just add things up to minimize the number of chips.  And possibly a 74LS85 binary magnitude comparator to get the saturate.
Good luck.