Calculate number of ADC clock cycles required for sample time
Assume the ADC has an internal sample_hold capacitor of size 10pF.
Assume you want full 12 bit accuracy in the sampling.
For 12 bits, using NEPERS to guide you, you need 9+ time constants.
If you have an external resistor of size 1Megohm, and that resistor has to charge the PCB trace and resistor parasitics of 10pF, plus charge the ADC internal S/H cap of 10pF,
then your time constant will be 1MegOhm * (10pF + 10pF) = 20 microSeconds.
For full accuracy, you need NINE time constants, or 180 microSeconds.
At 100Kohm, you need 18 microSeconds.
At 10Kohm, you need 1.8 microSeconds.
Since the ADC analog_input likely has some series resistance (plus the FET switch channel_on_resistance), if you want to allocate less than 1.8uS, you need to carefully read the datasheet for guidelines on very short sampling times.
Often people employ a opamp buffer before the ADC, perhaps with 100 ohms and 1,000 pF LPF between opamp and ADC, with the LPF used to handle the sampling surge currents.