Understand an I2C clock line implementation
This is related to a feature of the IIC protocol called clock stretching. If a peripheral device is unable to process data from the bus master in time (or prepare its output to be transmitted back to the master), it will continue hold the SCL line low (remember that it is open-drain, so there is no bus contention), until it is ready for transmission to continue. Once it releases the clock to indicate that it is ready for the next cycle, the master can then continue clocking the bus.
An IIC-protocol-compliant master is required to support clock stretching after the ACK bit (in high-speed mode) and at all rising edge clock transitions (in low-speed mode). If it uses a delay to blindly clock the bus, it may transmit/issue edges before the peripheral is ready, causing communication failures. Famously, the Raspberry Pi had a defect in its drivers/firmware such that it did not wait for peripherals that were stretching the clock -- a delay-only realization of an I2C master would suffer from this exact defect unless it were only used with peripherals guaranteed not to stretch the clock.