Monitor coin cell voltage without loading it when power is off
Here is how I have previously designed the circuit to isolate a coin cell from a microcontroller A/D circuit. I modeled this in LTSpice so it should be easy for you to evaluate and see that the load on the battery when the test mode is OFF is very very small.

 

Note that the BSS123 may not be the most ideal NFET for this isolation circuit because its threshold voltage gets close to the delta between the +5V supply and the highest level of the coin cell voltage. You may want to select an NFET that has a guaranteed 1.5V threshold.

It is possible to get dual NFETs in one very small 6-pin SMT package so board space is not a problem with this circuit.

Some times it can give a better status of the coin cell to load the cell some during the duration of the testing. This can be accommodated by placing a resistor from the M1 drain to GND. For a 3V coin cell a 1Meg resistor would place a load of 3uA on the battery. Testing should be scheduled to only be done once a week or so to that the testing itself does not significantly reduce the battery life.

In more recent designs I have moved away from this technique of measuring the battery. Instead I use an I2C RTC chip. The battery attaches to that and the RTC chip provides a check that the battery has not gone below a critical warning threshold. This type of RTC chip also nicely provides a very low current way to maintain a clock/calendar and is far superior to trying to use the battery backed clocks that are on many MCUs. The battery switching circuits and MCU power gating for sleep modes are never quite as good as the low current draw that a good RTC chip can provide.