ADC input enable register
No. What it means is that in Step 1, the hold capacitor is charged to nearly the right voltage by the unity gain amplifier just to the left of the Sample&amp;Hold (S&amp;H) block. But that amplifier is not particularly accurate. 

So then in Step 2 the switch between amp and S&amp;H connects the capacitor directly to the selected input channel, to charge the capacitor exactly to the input voltage. How long that takes is a function of the source impedance of the signal. As that source impedance is external to the chip, it is unknown to the chip designers how long this takes. So the device caters for higher source impedances by allowing that final charging time to be programmable. You select the sample buffer time according to the external circuitry.

AFTER this step, the S&amp;H is switched into "Hold" mode which means the input voltage is now stored on that capacitor - not a register - for the next 10 cycles (for a 10 bit conversion) while the conversion takes place.