Is the simulated clock cycle latency through an entity accurate?
In theory, yes, but it depends on your hardware.  If you have an FPGA rated to run at a maximum frequency of 500 MHz and that you run at 10 clock cycles on a 10 MHz clock, you shouldn't have much problem.  However, if you run at the specified 500 MHz, you may have latency caused by your clock buffers: there is some propagation time in a FPGA, CPLD, etc.  Usually, clock lines are distributed so that they provide relatively consistent clocking across the device (center to exterior or something similar), but if you want perfect synchronism better the location where clock "starts" versus where it "ends", you may end up with latency problems.

So basically, it depends on how you got 10 cycles metrics.  If it is an asynchronous circuit that propagates on 10 cycles, it may end up slower on your hardware.  If you a a synchronous circuit, it will take up 10 cycles, but it may not be in sync with other parts of your design if you go very fast.

Simulators are usually not aware of this until post-synthesis, at least, because at prior steps, your design is rather "chip-agnostic".  In my experience, if your simulator runs before post-synthesis, it is only good to test your "logic".  IF it runs after, it may be aware of your environment.  I know that Xilinx tool chain provided such facilities a few years ago, but it was not so much awesome nor reliable.  It might be better now.

In short, it all boils down to the tool chain you are using.  Read the documentation and contact your tool chain sales representative?