generating clock signal for testbench in VHDL
By omitting the "after" clause from the first assignment in your sequence of assignments (known as a waveform), you are implicitly implying "after 1 delta cycle".  Delta cycles are the key to how the VHDL simulation is performed.  A delta cycle can be thought of as an infinitesimally small delay, but in reality that is a gross simplification.  So in your case this infinitesimally small delay is why you don't see the positive duration of the clock cycle last for very long, although this behaviour will vary slightly with different simulators.

I would suggest that you do some further reading on delta cycles and follow it up with reading your simulator's manual to understand their implementation.

Edit:

A concurrent statement is evaluated every time a signal on the right hand side changed.  It may help to think about concurrent statements such as these in their equivalent process form.  A concurrent statement is equivalent to a process that is sensitive to the signals it references on the right hand side of the statement.  If there are no referenced signals then it is equivalent to a process with an empty sensitivity list and a final wait statement.

The "clk &lt;= '0', not clk after 50ns" example is evaluated every time clk changed, clk will be scheduled with '0' after one delta cycle and "not clk" (ie '1') after 50ns.  At 50ns clk has changed and so the statement is evaluated again, at which point clk is scheduled with '0' after one delta cycle and "not clk" 50ns later.  Therefore the duration between when clk is '1' and '0' is one delta cycle.

The "clk &lt;= '0', '1' after 50ns" example is only evaluated once because there are no signals on the right hand side for it be sensitive to.  Therefore clk is scheduled with '0' after one delta cycle and '1' after 50ns at which point no further changes are scheduled.