+-10v input motor driver
simulate this circuit &ndash; Schematic created using CircuitLab

Using a CMOS full bridge with Vcc logic level inputs for direction and PWM speed control ( no load speed = kV/RPM)

These open collector hi-speed comparators perform the offset and gain control to convert  the analog +/-10V Velocity control to high speed logic level Direction on HI drive  and 0~100% PWM on LO drive using Vcc logic levels into a full CMOS bridge.

Careful R Ratios were designed to balance and get as close to 0 and 100% PWM but noise reduction is imperative on the supply and layout with suitable filters.

Theory of Operation

U3 is simply a 0V comparator to determine direction of the input velocity control signal.

U2 is a 40kHZ Astable Osc. which can be tuned with C1 (also  R7 and R10) for a desirable efficient low frequency that minimizes Eddy current losses in the motor yet is ultrasonic.  

The triangular wave of U2 is fed into U1 to create the PWM comparator using a scaled Speed signal to convert from +/-10 to match the peak to peak triangle wave created from the hysteresis of the positive feedback ratio of  (R8//R9) / R10.

All the comparators could be a quad comparator IC that require a pullup R to Vcc that suits the logic levels of your "H-bridge" except for U2 which demands a precise 10.0V swing to make the near 0 and 100% PWM possible.
A 10.0V precision LDO is not shown but assumed to be necessary and trivial.  The comparators can run off 12V or the 10.0V single supply.  The full bridge power is chosen to match your motor requirements.

You might be able to find an IC to do this, but I did it the hard way.