Step Generator Reset Circuit Alternatives
I think your main problem is that the reset is asynchronous. 

Unfortunately your counter doesn't offer a synchronous reset, so the only real solutions I see are 


to buffer your counter outputs with flip-flops or
to use a counter that has synchronous reset capabilities (e.g. TI SN74LS163).


To mitigate your issue, you might be able to reduce the spikes by fine-tuning your compare level (I think that's what R7 in your schematic does), but you might have already done that. 

Apart from that, using a very fast comparator with a well adjusted compare level instead of your transistor circuit might allow you to further reduce the spikes. 

You can also try to add a flip-flop to synchronize your reset-signal to the main clock, but that might not be faster than the comparator.

However, the real issue is your asynchronous reset logic of your counter, so some spikes will always be present.

// update: Although using the opposite edge to reset your circuit is a nice idea, it won't help in this case as this would cut off half of the last step (because the reset happens instantly, even at the 'wrong' clock edge).