Effect of increased leakage of PMOS in reversed inverter configuration
You have a shared source amplifier and you can use these in analog delay lines; however, due to your notation (weak 1, etc) you seem to want this to be a digital application.  You will never be "not leaking", and you have a subthreshold device.  When the input is 0v, the output will be whatever the drain condition is required to satisfy the the flux condition through both devices.  Without actual device information, it's hard to say where this voltage condition would be.  I would avoid this design for anything digital.  If you still want to look into it, there's a nice discussion regarding charge sharing and subthreshold in "Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs" by TA Fjeldly, M Shur.