I have designed a Mealy FSM, that performs Divide by 5 operation on a binary number. How to implement control signal state for bitstream?
This 10 state Mealy FSM uses an additional 5 states for remembering where the C_in = 0 and therefore indicating the input of the last two LSBs of the binary dividend. The input bits a_0 and a_1 are X(don't cares) for when c=0. If from a state where c=0, a next state input c=1, then the state transitions to the reset state with an output of zeroes.