PCB routing of parrallel capacitors with different values (Based on STM Nucleo64 dev board)
I believe this is a simple case of automatic copper pour following the preset parameters.
Every routing program has &quot;minimal distance&quot; that can be set for traces as well as copper pours. When these meet the pads they cannot just merge with them, because it will create very hard to solder pads due to thermal dissipation. So:
a) copper pour cannot encompass the pad, it should surround it at certain distance, connecting to the pad only with thin trace to create so called &quot;thermal relief&quot;.
This can be seen as gray areas surrounding capacitor pads.
b) copper pour cannot come closer than specified minimum distances for pour and for trace, whichever is bigger. So the copper &quot;tries to fill&quot; everywhere, but sometimes there is just not enough space between two points for it to flow.
This can be seen as weird-looking &quot;peninsulas&quot; above C21 and C23 pads, trying to reach each other and failing due to these restrictions.
It is also can be seen just above &quot;U3&quot; markings in top left corner, and under &quot;U4&quot; in the bottom right.
c) finally, following these restrictions can create local &quot;islands&quot; of copper not connected to same net on this plane. In which case VIAs can be added to connect to the actual ground plane.
This can be seen as an island of copper above C25, C22 and C21.
From the electronic design point of view this is just sloppy routing with sub-optimal characteristics. However considering that Nucleo boards are just evaluation tools not designed for commercial applications, and also that ST engineers have to release them as fast as new devices coming out, this sloppiness can be understood, if not excused.