FET H-bridge has slow convergence for the last 10% of output voltage: why? (DRV8874)
What I am seeing is reverse &quot;droop&quot; caused by un-calibrated oscilloscope probes, or a similar capacitive load at the driver IC (not likely). Could you please verify calibration of your probes, in that they have the square tops and bottoms of a clean square wave. I see no place where else where capacitance, acting to over-dampen the edges of the signal, could happen. Outside of over-dampened snubbers on MOSFET drains or un-calibrated probes, I have not seen this before.
Under-dampened probes and snubbers cause a rising front edge. With little to no dampening you get a leading edge spike, then a fast decaying ring-wave. Please advise what you find after calibrating your probes and testing driver output again.
I am going to study this driver IC to look for bias issues. None found.