FPGA Internal timing/ timing constraint
When you create a constraint for your clocks, the synthesis and P&amp;R tools of the FPGA use that as the guideline to route your design. 

It is not only for the In/Out signals, but for every flip flop in your entire project. 

If you have multiple clocks in your design and you have regions where signal cross different clock domains, you have to explicitly tell your P&amp;R tool to either ignore those path (make them FALSE_PATH) or create a multi_cycle path between these 2 clock domains.