Using a counter to count how many clock cycles a signal is high using Verilog
Don't mix &lt;= and = in a single always block. Though I have never done this way yet, I can think of that on the 2nd active clock edge after in_1's deassertion, out is updated to the new counter which has been reset to zero one clock cycle before.
What you need is to latch the counter to out only when clk sees a deassertion on in_1. Design and figure out what circuit match your requirements, and then code.
Circuit first. This is not software program.