Verilog modulo without using "%"
There are a few problems here.

The first and most immediate problem is you are using a non-blocking assignment. So the assignment to c won't happen until the end of the current time delta. This means that you have an infinite loop.

Assuming we fix that however there are still several major issues with the code.


You aren't actually counting the number of loop iterations. So you only get the remainder not the quotient.
If c is zero you have an infinite loop.
To synthesize a loop the synthesis tool must be able to statically determine the maximum number of iterations. With more complex loops it may fail to do this even if a human can see that the iterations are bounded.
Even if you fix the code to bound the number of iterations in a way the synthesis tool can understand the code will explode into a massive pile of combinatorial logic. Errors like "can't fit design in device" or "timing requirements were not met" are quite likely.
Repeated subtraction is in general a pretty terrible division algorithm.


In summary it's time to go back to the drawing board.



Some hints on how to tackle something like this.

First specify your requirements, how quickly do you need a result? how often? how big are your inputs and outputs?

Second choose an algorithm, for a beginner I would suggest binary long division, it's not the best algorithm but it's easy to understand and much less resource-intensive than repeated subtraction.

Third choose an implementation strategy, there are basically three to choose from.


Combinatorial, no flip-flops within the divider (optionally you may have flip-flops at the inputs and outputs), simple to get your head around and means you get a result quickly in terms of clock cycles but uses a lot of logic and is likely to limit your clock speed. 
State-machine based. A state machine steps through a series of steps re-using the same logic for different steps of the process. This will give a compact design that can work at high clockspeeds but you will not be able to do a division on every clock and will have to wait for the results. 
Pipelined. The process is split into major steps with flip-flops between them. Gets you high throughput at high clock speeds but uses a lot of logic, lining up the timings is a PITA and you still have to wait for your first result.