This design does not fit into the number of slices available in this device
Remove the register duplication, it increases the speed of  your design and have very negative impact on the utilization of LUTs in your design. 

Those are mainly for the designs that have high fanout and needs to duplicate some of the resources in order to meet the timing.

Also, look into your code and see if you can remove the reset from some of your logic, specially parts that can be packed into SLR or RAM, that is one of the common mistakes people make, removing the reset, will help Vivado to pack some of your logic into BRAM or SLR and you will see a significant decrease in the number of LUTs used.

If none of those works, maybe your design is just too big for the FPGA you are using!