NOT gate power consumption
Yes, this design is not power efficient.
One lower-power alternative that is widely available is the CMOS NOT gate:

In this design, we eliminated power consumption by R2 and the BJT's base-emitter junction, because a MOSFET has 0 gate current at steady state.
And we eliminated power consumption by R1 by replacing it with a p-channel MOSFET that will be in a non-conductive state whenever the n-channel MOSFET that replaced Q1 is in a conducting state (and vice versa).
In this design, the power consumption is dominated by current delivered to the load. In case the load is another CMOS gate, this current flows only during switching transitions, so power consumption can be very low indeed, especially if the gates do not change state at high frequency.