ESD protection for power lines using capacitors
ESD will charge the capacitor.  Here is an LTspice model for an ESD source.

The notable part of this model is that you are charging a 150pF and 8pF source then discharging through a R and L; the total amount of charge related to the ESD event is limited due to this.  Which is why a capacitor that can respond with sufficient speed can absorb the ESD event without creating an excessive rise in voltage.

If you want to be careful, I would suggest simulating your ESD level (the link includes a initial condition for each IEC level) against the model for the capacitance you want to include.  That should capture the total rise you will see.