Input signal types in verilog
Essentially those figures are describing uncertainty. 

For the Send signal it could be transitioning from high-to-low anywhere in that region, for the PDin bus, any of the eight signals could be transitioning, low-to-high or high-to-low, in that region.

What it's telling you is that those signals are not valid during that time. Once Send goes high, the next positive edge of Clk will sample the parallel data on PDin. Then the serial data, MSB first, will be clocked out by SCout and SDout.