Clock Issues from Buffer
If you want textbook waveforms then you must use proper probing techniques with non-inductive grounds and good C decoupling on the chip.  5V Logic is 10x faster than CD4xxx logic and 3.6V logic even faster.  

Your waveform appears to be 3.3V logic with overshoot due to 10:1 probe ground inductance and resonance and false measurement well over the supply . The 250mVpp reading appears incorrect as the scale is 1V/div and peak reading well above expected clamp levels due to measurement error.

There is nothing wrong with the circuit, but controlled impedance traces will look better.  this means reducing the 100k feedback so that the stray load capacitance is not limiting the rise time ~1~2ns 10-90% of steady state levels.

The performance is controlled by the signal at Vdd/2 and not so much with the harmonics.  Tr=0.35/f(-3dB)

What IC , layout did you use for testing?  What are your expectations?