Initialize array with variable length in vhdl
The type definition requires a constant to define the range. This is used during simulator compilation or during synthesis. It is fixed once the circuit, real or simulated, is operating.
Signals can change and are therefore not constant. Their value changes during circuit operation.
So the two are incompatible. Use a constant.
Your question doesn't describe why you want to do such a thing so I can't advise better solutions to it.