DRAM memory organisation
DRAM is organised in a multi-level hierarchy, and knowing the correct terminology for the various layers is key to making sense of it, so I'll briefly recap them to make sure we are on the same page. (This is obviously only talking about the straightforward textbook case, and not considering things like ECC.)

On the lowest level, there is the bank, which is the physical 2D array of cells (capacitors/access transistors) and the word lines and bit lines connecting them. There is one row buffer per bank, which is followed by a column decoder to select – indeed – only one bit from the row.

Eight banks per chip makes for eight data output pins per chip. Eight of these chips would then be combined to make up a rank with 64 output bits. In the case of DIMMs, each physical memory module consists of at least one such rank. For multiple-rank DIMMs, the chips that make up the different ranks share the same command and data lines, so only one rank can use the bus at any moment in time (there are chip-select lines to address them).

Finally, a channel describes the complete system of one or more ranks and the command/data busses connecting them. As far as the low-level signalling is concerned, each channel is an entirely separate bus, so different accesses never conflict, etc.

As to your question about selecting only a single byte: The memory controller is free to handle those 64 bit chunks of data in whichever way is the most appropriate. In theory, it could just include a mux to select the appropriate byte of data to read. In modern processors, however, all memory accesses are typically done in units of cache line width (64 bytes) anyway, so all the bits would be forwarded to the cache subsystem. Even if only reading one byte into a register, the whole cache line would be fetched first.