sequence detector doesn't work expected
your first always block is a sequential circuit so, never forget to use non-blocking assignment.

your second always block is a combinational circuit and you must declare all the input signals in the sensitivity list. or you can set always @(*)

(Line 16,18,21 changed)

    module SeqDect(rst,clk,ip,op);

   /*io and internal wires*/

    always @(posedge clk, posedge rst)
    begin
    if (rst)
      state&lt;=s0;
        else
      state&lt;=next_state;
    end

    always @(state, ip)
    begin
    case(state)
    /*cases*/
        endcase
    end
    endmodule


testbench module:

module tb();

reg rst;
reg clk;
reg [1:0] ip;
wire op;

SeqDect uut(rst,clk,ip,op);

always #20 clk =~clk;

initial begin
clk=0;
rst=1;
#100
rst=0;
#100
ip = 2'b00;
#100
ip = 2'b01;
#100
ip = 2'b11;
#100
$stop;
end
endmodule


modelsim simulation results: