Pulse width stretching of the 0 pulse with a constant T
Here is a grab from the innergoogle, from some old National Semiconductor publication. For your application, reverse D1 and place the R in parallel with the C. The first inverter also can be a 14 rather than an 04. The requirements for the gates is that they both be inverterrs, and that the second one must be a Schnitt Trigger type. Other than that, they can be any TTL or CMOS variety that matches the rest of your circuits.

A possible issue is that for some logic families, the pull up current capability is much less than the pull down. This means the first gate will have a harder time charging up the capacitor than in the original circuit where it is discharging the capacitor current down to GND. This will cause a delay in the leading edge of the output pulse.  If this is a problem, one solution is to use one of the newer, more "stiff" CMOS varieties like the AC or ACT series.