What is causing this level shift in my wave?
It's fairly straightforward. When Q2 is turned off, Q4 is already off. As a result, the output, LVCoilA, is left at an intermediate voltage. This is probably determined by a combination of the two MOSFETs' off current, combined with the capacitances of each MOSFET, producing a sort of voltage divider. If you look simultaneously at Q2 gate and LVCoilA, you'll see that the gate is set to the bootstrap driver's reference, which is LVCoilA, about 6 volts in this case. Since LVColA is also Q2's source, Q2 is turned off. 

When Q4 is turned on, you'll see LVCoilA, as well as Q2's gate, get pulled down to ground.

As for the noise on the voltage bus, in order to make much sense of it, you must simultaneously display (for instance) Q2's gate and +12. As it stands, the two traces differ by x5 on the timebase, and there is no obvious way to be sure which +12 transients occur with which gate events.