How to configure Atmel SAM D20 for internal 48MHz clock source?
The correct sequence to run a Atmel SAM D20 at 48MHz, without external oscillator and just using the DFLL48M and the OSC8M is shown in the code example below.

void initializeSystemFor48MHz()
{
    // Change the timing of the NVM access 
    NVMCTRL-&gt;CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val; // 1 wait state for operating at 2.7-3.3V at 48MHz.

    // Enable the bus clock for the clock system.
    PM-&gt;APBAMASK.bit.GCLK_ = true;

    // Initialise the DFLL to run in closed-loop mode at 48MHz
    // 1. Make a software reset of the clock system.
    GCLK-&gt;CTRL.bit.SWRST = true;
    while (GCLK-&gt;CTRL.bit.SWRST &amp;&amp; GCLK-&gt;STATUS.bit.SYNCBUSY) {};
    // 2. Make sure the OCM8M keeps running.
    SYSCTRL-&gt;OSC8M.bit.ONDEMAND = 0;
    // 3. Set the division factor to 64, which reduces the 1MHz source to 15.625kHz
    GCLK-&gt;GENDIV.reg =
        GCLK_GENDIV_ID(3) | // Select generator 3
        GCLK_GENDIV_DIV(64); // Set the division factor to 64
    // 4. Create generic clock generator 3 for the 15KHz signal of the DFLL
    GCLK-&gt;GENCTRL.reg =
        GCLK_GENCTRL_ID(3) | // Select generator 3
        GCLK_GENCTRL_SRC_OSC8M | // Select source OSC8M
        GCLK_GENCTRL_GENEN; // Enable this generic clock generator
    while (GCLK-&gt;STATUS.bit.SYNCBUSY) {}; // Wait for synchronization
    // 5. Configure DFLL with the
    GCLK-&gt;CLKCTRL.reg =
        GCLK_CLKCTRL_ID_DFLL48M | // Target is DFLL48M
        GCLK_CLKCTRL_GEN(3) | // Select generator 3 as source.
        GCLK_CLKCTRL_CLKEN; // Enable the DFLL48M
    while (GCLK-&gt;STATUS.bit.SYNCBUSY) {}; // Wait for synchronization
    // 6. Workaround to be able to configure the DFLL.
    SYSCTRL-&gt;DFLLCTRL.bit.ONDEMAND = false;
    while (!SYSCTRL-&gt;PCLKSR.bit.DFLLRDY) {}; // Wait for synchronization.
    // 7. Change the multiplication factor. 
    SYSCTRL-&gt;DFLLMUL.bit.MUL = 3072; // 48MHz / (1MHz / 64)
    SYSCTRL-&gt;DFLLMUL.bit.CSTEP = 1; // Coarse step = 1
    SYSCTRL-&gt;DFLLMUL.bit.FSTEP = 1; // Fine step = 1
    while (!SYSCTRL-&gt;PCLKSR.bit.DFLLRDY) {}; // Wait for synchronization.
    // 8. Start closed-loop mode
    SYSCTRL-&gt;DFLLCTRL.reg |=
        SYSCTRL_DFLLCTRL_MODE | // 1 = Closed loop mode.
        SYSCTRL_DFLLCTRL_QLDIS; // 1 = Disable quick lock.
    while (!SYSCTRL-&gt;PCLKSR.bit.DFLLRDY) {}; // Wait for synchronization.
    // 9. Clear the lock flags.
    SYSCTRL-&gt;INTFLAG.bit.DFLLLCKC = 1;
    SYSCTRL-&gt;INTFLAG.bit.DFLLLCKF = 1;
    SYSCTRL-&gt;INTFLAG.bit.DFLLRDY = 1;
    // 10. Enable the DFLL
    SYSCTRL-&gt;DFLLCTRL.bit.ENABLE = true;
    while (!SYSCTRL-&gt;PCLKSR.bit.DFLLRDY) {}; // Wait for synchronization.
    // 11. Wait for the fine and coarse locks.
    while (!SYSCTRL-&gt;INTFLAG.bit.DFLLLCKC &amp;&amp; !SYSCTRL-&gt;INTFLAG.bit.DFLLLCKF) {};
    // 12. Wait until the DFLL is ready.
    while (!SYSCTRL-&gt;INTFLAG.bit.DFLLRDY) {};  

    // Switch the main clock speed.
    // 1. Set the divisor of generic clock 0 to 0
    GCLK-&gt;GENDIV.reg =
        GCLK_GENDIV_ID(0) | // Select generator 0
        GCLK_GENDIV_DIV(0);
    while (GCLK-&gt;STATUS.bit.SYNCBUSY) {}; // Wait for synchronization       
    // 2. Switch generic clock 0 to the DFLL
    GCLK-&gt;GENCTRL.reg =
        GCLK_GENCTRL_ID(0) | // Select generator 0
        GCLK_GENCTRL_SRC_DFLL48M | // Select source DFLL
        GCLK_GENCTRL_IDC | // Set improved duty cycle 50/50
        GCLK_GENCTRL_GENEN; // Enable this generic clock generator
    while (GCLK-&gt;STATUS.bit.SYNCBUSY) {}; // Wait for synchronization
}


This is C++ code for the Atmel Studio. It just requires the "sam.h" include and nothing else.