PCB layout: am I doing local power nets correctly?
Your layout looks fine. At 2 MHz, there shouldn't be much to worry about. My only suggestion, if you haven't already, is to prioritize your most critical signals (probably analog and I2C/SPI) for your top ground coupled layer.

At higher frequencies (this includes critical fast slew rates), this topology would not be ideal. In that case we would remove the local power islands and if not possible, AC couple them with 100 nF caps.