Multiplying signed to unsigned binary numbers in verilog
The width of your expression is very important when dealing with signed arithmetic. To multiply two 6-bit numbers and get a result of -63, you need at least 7 bits. You also need a to be sign extended to 7 bits. However, in Verilog, whenever you mix signed and unsigned operands, you get an unsigned result. So you need to convert b to at least a 7-bit signed value. You can do that as shown below:


module top;
   bit signed [5:0] a = -1;
   bit [5:0]        b = 63;
   bit signed [6:0] c;

   initial begin
      c = a*$signed({1'b0,b});
      $display("%b %d",c,c);
   end
endmodule