how to define HFPERCLK using HFRCO in I2C EFR32FG14
The first prescaler defines the internal high frequency clock (HFCLK) and the second prescaler defines the high speed peripheral clock (HFPERCLK) which is distributed to all peripherals in the high frequency domain.
The individual peripherals also have a prescaler so they can operate at a lower frequency if desired.
The I2C module has a simple clock divider register at offset 0x10 (see page 511 in the reference manual).
To generate a 100kHz clock (standard speed) from a 4MHz HFPERCLK you would need to divide by 40 and to achieve that you would need to write 39 decimal (0x27) into this register.