Is there any way to inhibit this latch circuit from locking up at startup?
I've pulled my hair trying to slow down in+ a bit, but realized it's
  simply not possible.


Of course it is possible - it's the same circuit that keeps a microprocessor in a reset state when power is applied.

So, try putting an RC network in the reference voltage feed to the non-inverting input. When power is applied, the non-inverting input will remain low (due to the capacitor needing to be charged) and during the initial period of power settling, it should work to solve your problem.

R is in series feeding the op-amp input and the C is from the input to 0 volts. Also, to discharge the capacitor when power is removed, a normally reverse biased diode across R will be helpful.