Synchronous bus clock operation
This diagram is drawn from the perspective of the CPU, accessing 'an external memory'. It is a description of what it will supply the memory with, so that you can design a memory that meets the CPU's timing requirements.

The CPU guarantees to have set the address lines to a VALID address, that is, the address lines will have stopped changing, by \$T_{AD}\$ after the start of the \$T_1\$, and to keep it stable until the read has finished.

It will set \$\overline {MREQ}\$ active, which is usually used to enable external address decoding, a little later to allow easy decoding without address line glitches, and \$\overline {RD}\$ active, which is usually used to enable the memory to CPU data buffers, also later to allow easy implementation without bus contention.

The CPU will not attempt to read the data until halfway through \$T_3\$, the memory must have managed to return settled valid data to the CPU by \$T_{DS}\$ before this, let's call this total delay the memory system access time.

From this diagram, YOU must design a memory system, where the delays of the address decoder, the memory IC's access time, and the return data buffer together must be less than the memory system access time. 

Hint, CPUs are usually designed to work with logic and memories available when they're produced, there would be little point producing a CPU which did not have the rest of the system available. So you should be able to find memory components in the same sort of price range as the CPU that meet the timing specifications.