Why can't regs be assigned to multiple always blocks in synthesizable Verilog?
For example, what if a same reg is assigned to always @(posedge clk1), always @(posedge clk2) where clk1, clk2 never beat of the same time? There would be no race-condition.


The case you mention will not be synthesizable. The flip-flop that implements the reg can only be clocked from one source.

As an aside, I'd like to clarify that the rule about regs having affinity to always blocks affects synthesizability, not validity. Software simulator will handle assignments from different always blocks without any problems.