What is the use of 'import' in SystemVerilog?
There is an interesting article here regarding the difference between import and `include when it comes to packages. I'm going to attempt to summarise it here.

When you `include a file, it is basically saying take the contents of that file and paste it at the location of the include statement. This is effectively the same behaviour as #include in C/C++.

Great you are thinking, now we have everything in the file, why can't we just use it? Imagine the case though where you are declaring a package in SV. If you `include a file containing a class A into two different packages P and Q, you are basically making a different copy of it in each package, which because of the way SV handles types will be incompatible (you now have one class called P::A and another called Q::A).

This is where import comes in. Unlike `include, the import statement does not copy the definitions being brought in to the file, instead it simply makes them visible. This is similar to the way the using namespace works in C++. Lets say you still `include the class A in package P as before. But now, rather than including A directly in package Q, you import P::A instead, both P and Q now contain the same class P::A instead of having two different ones.

So in summary:


`include copies the contents of the file in making a local copy of any classes/types/etc.
import doesn't copy but rather makes the existing package declarations visible in the current file.