How to set extra source and drain pins in PMOS power chip
Tie them together on the board (drains together, sources together.) The multiple pins are provided to reduce the resistance to the FET.

Multiple connections to the same high-current signal are common with high-power / high-current devices. This one supports 8.2A; it needs more than just one SOIC pin to handle that much current.

The other purpose of multiple-lead connections like this is to help with thermal dissipation from the package: the leads conduct heat, too.