Verilog simulation: How can I start my circuit after the reset signal is turned off?
I would start with keeping the reset with the reset of your test code, thus not in an apart initial statement. Your problems starts with:

@(negedge reset);
@(negedge clk);


That is a race condition as your reset and clock have the same timing delay: "#(T/2);". It never hurts to have your reset active a bit longer (e.g. you could have somebody else's module which has a synchronous reset).
My test benches all look like:

localparam CLK_PERIOD=100;
... 
initial
begin
   reset_n   = 1'b0;
   ... 

   #(CLK_PERIOD*10) ;
   reset_n = 1'b1;
   #(CLK_PERIOD*4) ;
   // This is where the testing starts
   @(posedge clk) 


I own a website which gives complete free Verilog code with the testbenches and it has NO advertising, but I don't know the exact rules of stackexchange so I can't point you there.