VHDL how to make a process with sensitivity list wait?
For much testbench code, we do not use looping processes and process sensitivity lists to search for things.  Instead, we use wait to find events.

TestProc : process 
begin
  Out1 &lt;= '1' ; -- Steady 1 after this point.

  -- Find Reset as it deactivates
  -- a better alternative than waiting for an ad-hoc amount of time
  if Reset /= ACTIVE then
    wait until Reset = ACTIVE ; 
  end if; 
  wait until Reset /= ACTIVE ; 

  -- find ready at a level 1
  if ready /= '1' then 
    wait until ready = '1' ; 
  end if ; 
  Out2 &lt;= '1' after 5 ns ; 

  -- find a rising edge of Clock
  -- Assumes that clock always transitions from 0 to 1 
  wait until Clk = '1' ; 
  Out2 &lt;= '0' after 5 ns ; 
  ...

  -- Also find a rising edge of Clock
  -- rising_edge is extra work for the simulator and probably not necessary here
  wait until rising_edge(Clk) ; 
  Out2 &lt;= '1' after 5 ns ; 
  ...

  std.env.stop ; -- stop the testbench
end process TestProc ; 


If you are looking for a behavioral model that drives Out1 to a static value, but inverts Out2 5 ns after each time Ready rises to a 1, then you can do the following:

signal Out2 : std_logic := '0' ; 
. . . 
FollowReady : process  
begin 
  -- initialization 
  Out1 &lt;= '1' ; 
  wait for 20 ns ; 

  -- looping process like behavior
  loop 
    -- Ready is a design signal.  Only detect a 0 to 1 change
    wait until rising_edge(Ready) ;
    Out2 &lt;= not Out2 after 5 ns ; 
  end loop ; 
end process ;