Building a Sub-nanosecond Monostable with ECL Flip-Flop
EDIT - My original answer, while on the right track, was wrong. Sorry, but it's been a while since I did this stuff for real. I will provide a better answer here, but keep the original at the end of this.

Using your suggested method, you will get a pulse width of about 300 psec, the delay from the Q going high until the reset becomes active. Since you need about 500 psec, you'll need to add some delay between the Q and the reset, nominally 200 psec.







simulate this circuit &ndash; Schematic created using CircuitLab

All statements about how to implement a delay remain valid, as are those concerning edge effects. Note that a 200 psec delay line will be quite short. It's easy to do on a printed circuit board, but often a bit tricky to predict accurately, due to the effect of parasitics.

This will nominally produce a 500 psec pulse starting 300 psec after the rising clock edge, and pulse width can be adjusted by adjusting the delay.

END EDIT

While the qualitative function you want is certainly possible, you won't get the pulse width you want.

From the data you show, the propagation delay from the clock is typically 300 psec. At the same time, the delay from the reset is another 300 psec. So if you feed the output back to the reset, your output pulse will be in the vicinity of 600 psec.

However, it's pretty easy to do some pulse shaping, especially if you're not interested in super-stability of pulse width. Something like







simulate this circuit

In theory, the delay produced by the delay element will equal the output pulse width for delays less than the flip-flop output pulse width. That's in theory, but will not produce exact results. Rise and fall times, especially, will affect your final pulse width.

The delay line can be produce easily in one of two ways. First, buy an ECL compatible delay line. These come in DIP packages, usually with an assortment of taps available. 5 taps at 20% of the maximum delay is pretty standard.

Second, simply use one or more gates as delays, selecting the number of gates to tailor the delay. This has its own shortcomings, especially for an application like this. The available delays will be close to your desired delay, but may not be exactly what you want. They will vary somewhat from unit to unit, and may well vary with temperature. 

Finally, simply make a delay line using a length of twisted pair or coax. For 500 psec, this will be on the order of 4 or 5 inches, so it won't be too bulky.