Calculating Maximum execution rate of instructions
You got the right answer &mdash; 2&times; speedup, ignoring overhead &mdash; but through a completely invalid method. It's interesting that you introduced the concept of overhead, but ignored it anyway in your final answer.

The key concept that you're missing is that adding pipeline registers allows different parts of the pipeline to be working on different instructions in parallel. The latency for a single instruction increases slightly, but the number of instructions completed in a given amount of time scales with the clock frequency.

So, ignoring overhead for the moment, without pipelining, you need 20 ns to complete each instruction, for a throughput of 50 MIPS. Adding a pipeline register allows you to reduce the clock period to 10 ns, which increases the throughput to 100 MIPS, but the latency for each instruction remains at 20 ns. The speedup is a factor of 100 MIPS / 50 MIPS = 2.0.

Now, if a register adds 2 ns of overhead, this affects both calculations. Remember that there is an implied register even in the single-stage pipeline. Therefore, the clock period in that case will need to be 22 ns, giving a throughput of 45.45 MIPS. With the two-stage pipeline, the clock period becomes 12 ns, for a throughput of 83.33 MIPS, but now the latency for a single instruction is 2 &times; 12 ns = 24 ns. The speedup is a factor of 83.33 MIPS / 45.45 MIPS = 1.833.