Why polygon pour size and trace width don't influence each other in altium
Fundamentally, polygons are evaluated separately in the DRC system.

Traces are traces, and polygons are polygons. The DRC system for checking trace width runs effectively with the polygons all shelved.

Realistically, when would you ever want to have traces that violate the design rules? If they're embedded in a polygon to the point where their width is irrelevant, you can delete them. If they're not embedded in a polygon to the point that their width is irrelevant, their width is relevant.

You're doing something that does not make sense, and the DRC doesn't account for it because there is no reason to do what you are doing.