overlap error in Eagle CAD
There is a DRC option (Clearence -> Same Signals -> SMD-VIA) that checks the distance between VIAs and SMD pads, even if they connect to the same signal. This is probably the reason why you get the OVERLAP error.
As a workaround you could just set this restriction to 0. But you should consider placing  the VIAs within your package design, since the DRC will ignore the minimum distance rule in that case.