Confusion on Voltage levels in Digital Waveforms
This applies mainly to older logic such as TTL which was popular in the 1970's. That is also known occasionally as current-sinking logic. It is largely irrelevant when using modern logic devices. Circuit developments in the last 40 years mean that these constraints rarely apply.
When a logic circuit output is in the high state it will be forced to supply a small current to the succeeding circuit. In the case of traditional TTL this is a maximum of 40uA per load. The arrow for conventional current would be from the source to the load as shown in the diagram. A normal TTL output is guaranteed to be able to supply 400uA while maintaining a minimum of 2.4V (the worst case logic high) hence it can drive up to 10 loads. Typically the load draws much, much less than 40uA so it is extremely rare for this to be a limitation on drive capability.
When a logic circuit output is in the low state it will be forced to sink a small current from the succeeding circuit. In the case of traditional TTL this is a maximum of 1.6mA per load so the arrow would be from right to left as in the diagram.
This current is one factor that determines how many loads can drive - a normal TTL output can sink up to 16mA while maintaining the worst-case 0.8V for a logic low, hence up to 10 loads.
Modern CMOS logic draws essentially zero current so the drive limitation is from the ability to drive the capacitance of the load or from signal-coupling aspects.