What does this VHDL code do?
Add some line feeds and it becomes fairly self-evident:

case state is 
   when SO =&gt; 
     state &lt;= S1;
   when S1 =&gt; 
     state &lt;= S2;
   when S2 =&gt; 
     state &lt;= S0;
end case;


What it does is schedules state to be set to the next state, rotating from 2 back to 0. So S0->S1->S2->S0... If it is not within a clocked process, it will go as fast as it can forever, which is most likely not what you want to happen.