CPU ports and cache controllers
Accessing separate instruction and data caches through a single physical interface is possible and might even have made sense back when caches were off-chip and used commodity SRAM chips. Given pad/pin count limits and use of commodity SRAMs, direct-mapped caches were common, adding one bit to the address to select instruction or data cache would allow a single wide interface (at twice the speed) to provide the improved hit rate of separate caches (under direct mapping).

This could be viewed as access-type-based perfect way prediction in a two-way set associative cache.

For caches on the same chip, using separate interfaces avoids the need for handling contention. (Besides doubling the interface speed and alternating between instruction and data accesses, contention could be reduced by using a wider interface fetching two or more sequential instructions per access. Since typically less than half of all instructions access data in memory and taken branches (which could be the first of two fetched instructions and jump to the second of two instructions) are less than a fifth of instructions, this need not degrade performance too much.)

Separate interfaces allows latency to be optimized by locating data storage closer to the ALUs and instruction storage closer to the instruction decoding logic. (You might find Dyer Rolán et al.'s "Virtually Split Cache: An Efficient Mechanism to Distribute
Instructions and Data" (PDF) of interest.)

Typically an L2 cache uses a single interface. The arbitration overhead is less significant because L2 latency is already substantial and L1 misses are not the common case.