Assignment compatiblity error in verilog
On line 15, you are declaring arrays:  reg temp1[31:0],temp2 [31:0],temp3[31:0] whereas your data_out is a 32 bit vector, not an array. 

So, on line 33 you are assigning array value to a single vector value. In ModelSim 10.1d I get 


  ** Error: design.sv(33): Case item comparison:  Illegal assignment to type 'reg[31:0]' from type 'reg $[31:0]': Cannot assign an unpacked
  type to a packed type.


There you go, it says the error happened here : Cannot assign an unpacked type to a packed type. You should declare the temp variables like this: 

reg [31:0] temp1,temp2, temp3;

Also, there is an extra endcase syntax on line 61. Here is your modified code