Are there flaws in the reasoning behind the Zedboard bypass scheme?
He seems to be trying very hard to justify his design tradeoffs. @Conner Wolf is completely right, measurement across the capacitors is not (all) we care about. Trace/via impedance at the current ripple frequencies you see on power-pins on these high-clock-speed parts can become really considerable.

Its all a little unusual, every design has tradeoffs that need to be made and you try to chose wisely...and then verify under test of course. You don't need to write a PDF about why you needed to put x in position y because of limiting factor z.

BGA is generally a pain to route-out but I usually try to place/route clock sources first and then decoupling/power and THEN signals. My logic is that I've had issues with clocks before, but no issues yet with decoupling or signals and that I would consider optimising decoupling and power routing to be higher priority than signal routing.