ASIC Shuttle Service Disadvantages?
Actually the biggest cost is the design itself, then followed by the fab NRE (Fracture costs and mask making).  

The biggest risk that you have from a using a Shuttle/MPW is that you often are on the same mask set as someone who is experimenting or who may not understand areal density rules. The worst is when you have some grad student playing around with inductors and ruining the plananarization of adjacent chips.  If you are doing something more advanced or needing better matching then you should forget it.  Most P&amp;R tools should be OK for routing density, it's the odd wild card that you share the mask with that can screw you up.

Do keep in mind that with an ASIC fabless model, "proof" of a good wafer run is the from the process monitors that the fab measures.  NOT your design yielding, that is your responsibility.

The next step up, before a full production mask set is the placement of multiple layers on one mask to reduce the mask making costs.  This mask this then used (with blading) and may reduce mask costs to 1/4 or 1/3 (fracture costs stay the same).  But the fab will not go to production with this as it slows things down.  Not all fabs offer this, and different fabs use different terms for this service.