How can be creepage between two conductor points be determined for HV pcb design?
From UL840 (Jan 6 2005): **
6300Vdc/ACrms, Polution Degree IV, Material Group III (CTI 175 to 400) = 320mm

PD IV is a conductive or wet dust.

If you can go to Polution Degreee II (limited condensation and non-condutive dust) by controlling the evironment some way, then that reduces to 63mm.

If you can use a material with a higher CTI as well, then that further reduces to as low as 32mm.

From IEC60664-1 (1992): **
6300Vdc/ACrms, Polution degree III, Material group III, 100mm
6300Vdc/ACrms, Polution degree II, Material group I, 32mm

From IEC60664-3 (1997): ##
Up to 8kV DC/ACpeak = 3mm of solid insulation
This could also be an inner layer of a PCB or solid potting compound.

Notes:
 ** This is in air.  The 6kV falls of the bottom of most of the tables for any coatings.
 ** This is at &lt;1000m above MSL. e.g. At 7000m the dimensions double.
 ## Deals with coating and potting (and by inference assumes polution degree I)