How to automate Instantiation of modules in Verilog? (permutation)
You can use several approaches to generate permutations, e.g. follow this link.

Using the above, the easiest is that you explicitly generate the instantiations for each permutation e.g. in Java (all 120 instantiations, exactly as you show in your example), write it into an include file, and in your program you just `include that file. Problem solved, no generate...endgenerate needed. You can also copy-paste, if you like your code in one file.

The other way is that you explicitly generate wire values for each permutation in Java, e.g.

wire [14:0] perm [0: 119]; 
assign perm[0] = {3'd0, 3'd1, 3'd2, 3'd3, 3'd4};
assign perm[1] = {3'd0, 3'd1, 3'd2, 3'd4, 3'd3};
assign perm[2] = {3'd0, 3'd1, 3'd3, 3'd2, 3'd4};
assign perm[3] = {3'd0, 3'd1, 3'd3, 3'd4, 3'd2};
// ...etc


then `include this or copy-paste into your main file, and you can use a simple generate..endgenerate structure:

genvar ii;

generate 
  for (ii=0; ii&lt;120; ii=ii+1) begin: genblk
     sr_latch M(t_in[perm[ii][14:12]], t_in[perm[ii][11:9]], t_in[perm[ii][8:6]], t_in[perm[ii][5:3]], t_in[perm[ii][2:0]], out);
  end
endgenerate


Note that the instantiated devices are wrapped in genblk-s, so they are not named M1, M2, etc.

Finally, if you are a purist, you can take one of the algorithms (an iterative permutation calculator is the best) and implement them in Verilog. Waste of time, but nice fun. I don't recommend this though.