Is it possible to reduce the Miller's plateau voltage?
The Miller effect is due to having a capacitance across two points with a negative voltage gain between them.  

[Intuitively you can think about one side of the cap getting pulled down by the gate-drain gain while the other side is pulled up by the gate driver, so you need to add the extra charge that the drain is trying to pull out.]

It multiplies the capacitance by ~ the voltage gain.  So while you are transitioning through the linear region where the FET has gain you can't avoid it or change where it starts, you can only add more gate drive current to get through it faster.

From here: