Finding the value of a capacitance in a dynamic RAM cell? (Digital Electronics)
Yes, it is correct. I did not check the numbers, but the procedure is correct.

To help you understand what you are doing, here is an explanation of the formula. When you perform a read operation, you turn on the NMOS. This means that you somehow shortcircuit Cc and the bit line. These are two capacitors charged at different voltages, so when you connect them a redistribution of charges takes place. The formula that you are using is actually about charge conservation, and not energy conservation. The charge Q stored in a capacitor equals its capacity times the voltage across its leads:
$$ Q\ =\ C \cdot V$$
So what you are doing is just match the charge present before the connection, and the charge present after, keeping in mind that after the short circuit we can model the Cc-BL capacitor as the parallel of the two.
$$Q_i = Q_f \\
C_C\cdot V_{C_C}+C_{BL}\cdot V_{C_{BL}} = C_{tot}\cdot V_f$$
The final voltage must be greater than \$V_{C_{BL}}+\Delta V\$ if we had a high level and less than \$V_{C_{BL}}-\Delta V\$ if we had a low level. Using this condition will lead to two separate equations that are easily solved:
$$
C_{C(1)} \ge \frac{C_{BL}\cdot \Delta V}{V_{C_C(1)}-V_{BL}- \Delta V} \\
C_{C(0)} \ge \frac{-C_{BL}\cdot \Delta V}{V_{C_C(0)}-V_{BL}+ \Delta V}
$$

The higher value of capacitance is the one you are looking for.