Power rail noise calculation
in the ADC there will be analog comparators, and opamps and probably DACs.

At really high frequencies, such as the 1 nanosecond RISETIME transients of MCU clocks coupling 1cm away into your ADC VDD, VREF, VIN(+) AND VIN(-), THE PSRR of circuits within the ADC becomes ???? zero?? 

Thus 10 quanta on trash coupled onto Vref ?may? cause a 10 quanta measurement error; probably not, because of the massive averaging within the ADC digital engine.

So let us be cautious, and predict te worst-case cleanliness of that VDD.

Assume we are willing to budget 1quanta of trash to the super_clean_VDD_rail.
What should that be?

Divide 3.3 volts by 2^24 (or maybe 2^23) or 3.3 / 16,000,000 === 3.3/16 microvolts pp.
Or about 0.2 microVolts.

What can we say here?

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Once you have (at some expense, in cost and PCB area) created an ULTRA_CLEAN VDD, you need to treat that CleanVDD as a precious resource, to be protected from aggressor trash injectors.


avoid ground currents flowing across or along the PCB between VDD filtering and the ADC power pin; 2 milliAmps of (varying) ground current, passing thru 2 squares of standard_thickness 1 ounce/square foot foil that is 0.000500 ohms per square, causes a VARYING  1 microVolt trash injection into VDD; 
avoid nearby e_field transients ---- example needed (planes, gnd or vdd, are great attractors of flux lines, causing 1/distance^3 [cubed] attenuation
avoid magnetic fields of all sorts ---- expect to need some steel sheets, folded to wrap around your 24-bit system ---- example needed (copper foil has little benefit --- just a dB? --- for edges slower than 100 nanoSeconds)
power supply interference --- you have already become aware of this, and the other answers are very good guidance
cabling