Up/Down mod 105 counter based on 74193
This is fundamentally a bad approach for an FPGA design. FPGAs (and their design tools) are highly optimized to support synchronous logic, in which all of the FFs in a given module are clocked directly by a single common clock. Special techniques are used to transfer signals from one clock domain to another.

Although the 74193 is called a "synchronous counter", it is a very loose application of the term. If you look at the internal implementation in any data book, you'll see that every FF in it has a unique clock. And the "clear" and "load" functions are asynchronous, not synchronous. Duplicating the exact function of just one of these chips in an FPGA is going to be a messy proposition at best, and trying to build more complex circuits using them will be even worse.

If you must do this project using schematic entry rather than HDL, then you would be much better off using 7 separate FFs, an 8-bit register such as a 74374, or even a truly synchronous counter like the 74169.