FPGA: Bitstream vs. SRAM Object File
They are different names for what is essentially the same content.

There are three major "types" of FPGA, when dividing up how they implement their logic -- SRAM-based, Flash-based and anti-fuse, with the first being the most common (Altera and Xilinx primarily). SRAM-based FPGAs are 'blank' / un-configured every single time you power them up, and must load their configuration data from somewhere, usually an external memory IC, or an external processor. Colloquially, most engineers refer to the content to be loaded on there as the bitstream -- a binary blob of digital data that represents the connectivity and routing of the logic resources on the FPGA (and in more advanced models, it'll carry along the initial RAM contents, etc.). During development, engineers may use the JIC format (as an Altera example) more often, as they will dynamically load it over JTAG during development via a USB tool like a ByteBlaster. In production, we may use the binary formats to flash onto the SPI configuration device on the PCB.

This bitstream has many, many formats ranging from vendor-specific formats to somewhat standardized formats. If you check out your programming tool's options (Quartus II programmer or IMPACT for example), you'll see such options as JAM, SVF, STAPL, TTF, JIC, BIN, BIT, etc. Some of these are vendor-specific, others are standards (like SVF and STAPL). Formats like SVF are plain-text readable -- the configuration data is recorded as a sequence of macros, and are intended to be delivered over JTAG. Others, like a raw BIN or BIT file, is a binary blob that is intended to be flashed 1:1 onto a flash memory device.

Flash-based FPGAs are similar (ex: Actel IGLOO), but they store their configuration data on the FPGA itself -- the act of programming the array sets the design non-volatiley in the device. This data is also referred to as a bitstream, and for Actel devices at least, show up in SVF, STAPL and (proprietary) PDB forms. These FPGAs are considered 'live at power-up' as there's no need to load a configuration from an external source. Many CPLDs are flash-based as well, to reduce part-count on the BOM and to support their usage as low-power, brainstem like power-sequencing control for a more complex system.

Finally, just to complete the mention of it, anti-fuse devices can only be programmed once by a specialized programming devices actually fusing together links inside the device with high-voltage. They are always live at power-up and have generally high design-security since there's no configuration to be read or snooped -- the device is physically blown into the state it needs to be. I still refer to what I put on these devices as a bitstream, for what it's worth, but they are not re-programmable.

So basically, yes -- they are different names for generally the same content. Some are plain-text, some are binary. Some are intended for a flash storage device, others are intended for JTAG configuration at runtime (like JIC, JTAG Indirect Configuration). All of them can represent the design and state of internal logic elements or memory elements in the device.

Some common types in a non-exhaustive form:


SVF -- Serial Vector Format. Plain-text format that is very verbose and contains JTAG macros that walk a dumb programmer through the process.
XSVF -- improved version of SVF that allows for control-structures and other enhancments
STAPL -- initially Altera, now JESD-71. Allows looping, macros and control structures, reducing file size. Plain-text.
JAM -- Evolved / adopted as STAPL, plain-text.
JIC -- JTAG Indirect Configuration
SOF -- SRAM Object File, a binary file generally from Altera tools for SRAM devices
POF -- Program Object File, a binary file generally from Altera tools for flash devices (like their CPLDs)
RBF -- Raw Binary File, generally from Altera. analagous to the raw binary outputs from Xilinx or other vendors.
TTF -- Tabular Text File, a decimal/plain-text encoded version of the RBF.
BIN -- over-used extension that could be from any of a thousand tools, but is used by Xilinx design tools for a raw bitstream with no header
BIT -- (Generally) Xilinx design tool output in binary form, with a pre-amble / header
PDB -- Actel binary format


For configuring an actual memory device, many of the common formats may be used -- MCS, HEX, SREC (S19), etc. These do not target the FPGA directly.