Dealing with bidirectional communication over 1 pin
In I2C, when it's their turn to talk, either the master or slave will drives the data line low for a logic 0 or becomes a high impedance input for a logic 1.  

When it becomes high impedance, it essentially floats the line and allows the pull-up resistor to pull the line high (logic one).  When it is a high impedance input it can detect if the line is being driven low - if it tried to "write" a logic 1 in this clock cycle, then we know some kind of contention occurred.  Note that this is the only case that we care about.  If contention occurs but does not end up changing the resulting bit stream then we actually just go about our business without giving any error.  If contention does occur, the party that concedes the bus is the one that detected a logic 0 when it was trying to put out a logic 1.

I don't know Verilog, but in VHDL, if we're using the STD_LOGIC type, we can assign it as "inout" and in a process, assign it the 'Z' value (high-impedance) and then sample the pin for a high or a low.

If you are writing an I2C master, it is your responsibility to detect if the I2C line is in use, specifically, looking for start and stop conditions to signal the start and end of usage by another possible master.

NOTE: it says two-wire interface in the datasheet, I'm pretty sure this means I2C so the above should still be relevant.