Why are identical value vs different value capacitors between positive and negative voltage supply leads?
It's all about inductance.
If there is an inductance of value L in series with the power supply pin of your IC, and the IC draws a time-varying current i, then a voltage \$ e=-L di/dt \$ will appear on the inductance, which means supply voltage will drop by the same value. If it drops too much, your microcontroller will crash, for example. Or there will be too much noise on your power supply, and your analog circuits will suffer.
Generalizing, the power supply impedance seen by the chip must not be too high, so supply voltage stays stable as current varies. Inductance in the supply lines increases this impedance.
Large chips have lots of VCC/GND pins which are effectively all in parallel, which results in lower inductance. This has other beneficial effects like tight coupling to nearby highspeed signal pins and good return current path, but I digress.
Flat packs like TQFP have quite long bond wires inside, which also have inductance. So if a TQFP requires a certain maximum power supply impedance seen from the chip to operate, then it will require several power pins. BGAs and other packages have much lower pin inductance, but since they tend to be used for highspeed stuff, the problem is the same.
The job of decoupling capacitors is to lower power supply impedance by countering the PCB's inductance.
Seen from the chip, a decoupling cap will have more inductance in series if it is further away, thus it is best to place them close to power and ground pins. More precisely, inductance of a loop depends on the area of the loop, so by placing them close this is minimized. That means one cap per pin usually. Also this means the HF currents will flow in the cap and not through your GND/power planes or traces which will add noise to your power and ground.
Remember the total inductance in series with power and ground is what counts, not just the power pins. Likewise a pair of ground/power planes has much lower inductance than traces.

I understand why various different value capacitor are added in low voltage power supplies....to be able to respond and absorb various size/frequency spikes.

No, not really. Inductance of a MLCC cap depends mostly on case size, so a 10nF or a 100nF will have exactly the same HF performance if they have the same case size like 0603. The low value cap will only have better HF performance if its lower value allows you to choose a physically smaller one which then has lower inductance. But if you hand solder for a hobby project and use, for example 0603 or 0805 caps, because 0402 is just too small, then it is useless to put 10nF+100nF+1µF if they're all the same size. Just put in one 1µF cap.
Multiple values cause problems because they cause antiresonance peaks. But if you want the caps to be close to the chip, like squeezed between BGA balls under the board, then they have to be tiny. And if you need a lot of them, they have to be cheap. So you end up with tons of 10nF caps. But you don't have enough capacitance, so you add some 10µF caps. Then that creates a huge antiresonance peak, and you play whackamole squashing it down with intermediate value caps. That's pretty much the only reason why you get the classic spread of cap values.
Example

Each curve is the impedance of the parallel cap combo on the right, taking into account ESR, and ESL values more or less compatible with decent mounting. Note what matters for resonance is the inductance between the caps, which is usually pretty low if they are next to each other.
&quot;vcc&quot; is 10n+100n MLCC
&quot;vcc1&quot; is 10n+1µ MLCC, worse peak
&quot;vcc2&quot; is 10n+10µ MLCC, also worse peak
&quot;vcc3&quot; is the classic combo of an electrolytic with highish ESR and a 100nF cap that is used everywhere, it works very well due to the electrolytic ESR providing excellent damping
&quot;vcc4&quot; is my favorite for simple circuits, 10 cents Panasonic FR electrolytic which due to its lower ESR needs 1µF MLCC instead of 100nF to remove the antiresonance peak.
Note that putting several MLCCs in parallel on each pin does not reduce the power supply impedance seen by the chip if it's in a leaded package, because bondwire and package inductance are higher than the inductance of a well mounted cap.
Now what happens with two identical 100nF caps? Well that depends if they are paralleled by a low inductance plane, or a high inductance trace.

How to model this:
This is a series RLC resonant circuit. C the value of both capacitors in series, so if they're far apart in value, close to the smaller cap. L is all inductors in series, and R is all ESR in series. Then you can use the classic series RLC equations to calculate damping factor, for example. For good transient response, a damping factor &gt;1 is ideal, unfortunately it is hard to get because MLCCs have too low ESR, and ESR-controlled MLCCs are super expensive.