555 astable - frequency not linear with discharge resistor for smaller resistor values
The peak current is 2/3 the supply voltage divided by the R2 + the output resistance of the buffers. With 1K and a 3V supply voltage that would be less than 2mA. 

I suggest you make the capacitor maybe 100x less, so something like 330pF NP0 ceramic. You want the minimum resistor to be much more than the output resistance of the buffer for linearity. There will also be some nonlinearity as a result of the propagation delays in the buffer and 555. At 1kHz you will need about 2M for the resistor which is still within reason for a CMOS 555.

This will also help deal with the duty cycle issue as the duty cycle will be less dependent on the symmetry of the output resistance of the buffer. Often CMOS outputs are much better at sinking current than sourcing it (if not, the designer has placed significantly larger p-channel than n-channel transistors). In the case of the 74LVC2G17, there are hints in the datasheet that the internal resistance when sourcing is about 25-30% higher than when sinking. 



You have added the requirement that the resistor cannot be increased, in which case I would suggest a fast MOSFET driver and a couple of smallish SOT-23 ~5A  MOSFETs instead of the buffer. Good bypassing will be very important. 

You could alternatively consider a fixed resistor in series with the changing resistor, which will make it even more nonlinear, but in a quite predictable way (easy to subtract out if you are doing a measurement with a microcontroller).