How to multiply a very slow clock (1 kHz) into MHz range
PLL chips that take kilohertz inputs exist. I've used Silicon Labs parts at 4 KHz to generate ~80 MHz outputs. I'm not sure if they make anything where they can guarantee jitter performance all the way to 1000 Hz, but it doesn't sound like that's critical if you're using an MCU as the source clock anyway.

Clock source: The master divides it's MCU clock to approx. 1kHz via a counter.

Why don't you divide down that clock to something more reasonable for the ADC clock and then use the 1 KHz signal as a trigger for the ADC? That way you don't need an exotic PLL that can handle very low frequencies with (hopefully) acceptable jitter performance.