SPI bus multi-slave termination
Rather than worry about controlled impedance, matched terminations, reflections, and all that, what you should do is increase the rise and fall times of your signals.

You have a 125 ns clock period. A rise and fall time of 10-12 ns on the data signals and 6-8 ns on the clock will have negligible impact on your timing margins, but dramatically reduce the likelihood of any issues from impedance mismatches.

Since the SPI bus doesn't have bidirectional I/O's, you can do this by just adding a series resistance at every output driver. Ideally you'd calculate the capacitance of each driven line (at least roughly), and calculate the resistance to give the rise-time you want. Or you can pick a value between maybe 5 and 50 ohms, and adjust it later if you have problems or if measurements on the actual board show too fast or slow rise times.