PIC when generating a PWM signal does the used timer throw a overflow interrupt flag?
Overflow in this case means a match to the preset register, which causes the timer to reset. It's spelled out better in the description of the timer that the PWM module is based on than in the description of the PWM operation itself.




  14.2
  Timer2 Interrupt
  Timer2 can also generate an optional device interrupt.
  The Timer2 output signal (TMR2-to-PR2 match)
  provides the input for the 4-bit counter/postscaler. This
  counter generates the TMR2 match interrupt flag which
  is latched in TMR2IF of the PIR1 register. The interrupt
  is enabled by setting the TMR2 Match Interrupt Enable
  bit, TMR2IE of the PIE1 register. Interrupt Priority is
  selected with the TMR2IP bit in the IPR1 register.