FPGA - Routing Diagram - what are the physical parts
Using the terminology found in the datasheet (see Figure 1):


blue arrow: CLB (configurable logic block). This contains four "slices", where one slice comprises two LUTs (lookup tables) and two flip-flops (see Figures 11 and 12).
white arrow: This area contains both BRAM (block static RAM) and multipliers.
yellow and orange arrows: IOB (Input/Output Block) (see Figure 7)


The thin blue trace that runs all the way to the top of the diagram and then loops to the right and down again is your clock. It originates at the tiny block in the bottom row, which is a DCM (digital clock manager), and it passes through a global clock buffer on its way up.

While in the chip editor, you can zoom in on each of these blocks and even peek inside them to see exactly which resources are being used to implement your design.