Does a microcontroller fetch instructions in blocks?
No and Yes.  

No, because as alex.forencich points out most MCUs use NOR flash. This greatly simplifies MCU architectures, as it allows them to fetch and begin executing a single instruction at a time. This is almost certainly how 8-bit AVRs, and PICs, and so on operate.

Yes, because some architectures use wider buses on their flash interfaces, pre-fetch, and/or multiple-issue to help overcome the latency of the underlying memory and improve overall performance.  For instance, STM32F7 parts (Cortex M7) have a 128/256 bit bus between the flash controller and the underlying memory, and then a 64-bit AHB between the core and the flash controller.  This means the flash controller retrieves four or eight instructions at a time, and the core can retrieve two instructions from the flash controller simultaneously.  In this case, the core wants two instructions every cycle because it is uses a dual-issue pipeline, meaning that it can fetch and decode both instructions simultaneously, and in many cases dispatch both instructions to different processing units for simultaneous execution.

The flash controller may also pre-fetch additional instructions that the core has not yet requested, again to reduce the impact of flash latency.  How far ahead the controller will pre-fetch, and whether it uses additional caching or other strategies where instructions are fetched in batches is highly architecture dependent.