Implementing ADD instruction for RiSC-16 processor
RISC-16 is RISC. All RISC CPUs are RISC. Well, your example is one that would never happen in real machine. It is a nonsense. The problem may lie in the pipeline, the RISC tends to execute all instructions in the same amount of instruction cycles, composed by fetch, decode, execute. The pipeline was introduced to speed up the processor: first problem is that all instructions shall have the same the same instruction cycles in order to take the advantage of the pipeline, next it is strictly forbidden to execute a commands that will access and change the value of the same register within one instruction cycle, as the pipeline would messs up. 

The only way to reproduce your behaviour, is to intentionally write those assembler codes, as no compiler would do that. If you do program on low level, you should be aware of pipeline and its restrictions.