How to generate fast clock signal with MAX10 and PLL?
If you can divide down the input clock frequency inside the device then you can operate at (say) 200 MHz internally (easily suiting the PFD) whilst having the VCO output running at 400 MHz. I don't know if the PLL has this internal facility or not but, given that the data sheet says it can operate at frequencies (Fin) up to 472.5 MHz it would be pointless if it can't be divided by 2 to obtain a frequency that is within the operating range of the PFD (phase-frequency detector).

You need to do some digging around and hopefully you'll find that a programmable divider sits between Fin and the PFD ready for you to program to divide-by-two. If you find it you might need to juggle some other numbers because now, internally, you will be needing to compare with a 200 MHz clock.