Logic Buffers for CPLDs Outputs (and Inputs?)
Looking at the TI datasheet for 74LVC1G125, if you scroll down past the absolute maximum ratings, you'll get to the recommended operating conditions, including a maximum I_OH and I_OL. TI specs 32 mA max for either one, and that's only if you're providing 4.5 - 5 V Vcc. If you're using 3.3 V or lower, the recommended source and sink currents are lower. So I think one part of your question we can answer is, no, the 74LVC1G125 is not a good choice if you need to sink 50 - 100 mA. 

To answer the rest of your question probably needs some more information: How fast does the buffer need to switch, what power supply voltages do you have available, is the load resistive, capacitive, or something else?

One option that you could probably get to work very generally is just to use some general-purpose npn transistor on each output. With an appropriate resistor between the CPLD output pin and the transistor base to limit the current, it should be straightforward to achieve 100 mA sink current and output voltage below 0.5 V (depending on the load).