"The D-PHY specification defines the maximum lane flight time to 2 ns." Why?
I assume you're referring to MIPI.
The 2ns figure comes up in a number of places (e.g., in MIPI D-PHY spec v1.1, Annex B1.) From the doc:

B.1 Practical Distances
The maximum Lane flight time is defined at two nanoseconds. Assuming less than 100ps wiring delay within the RX-TX modules each, the physical distance that can be bridged with external interconnect is around 54cm/√ε. For most practical PCB and flex materials this corresponds to maximum distances around 25-30 cm.

What they are saying is that they wish to limit the practical cable length to 20-30cm and a capacitive load of 70pF. One reason is the influence on LP-mode: greater load capacitance will affect rise/fall times for this slow mode.
At any rate, 20-30cm of cabling is consistent with MIPI D-PHY's mission as an internal interconnect using PCB or flex cable.