Problems with dividing a clock with 2 command bits
You have,


if cpt &lt; division then



What do you expect to happen here if division is 0?

In any case, there is a much simpler approach to this kind of problem.

You can just make a modulo-8 counter. 

Now, 1 bit of the count variable will be the same as a modulo-2 counter, one bit will be the same as a modulo-4 counter, and the highest order bit will be the modulo-8 counter.

A combinatorial multiplexer can connect any of these three bits (or the original input clock itself) to the output.

If you have some additional requirements, like being able to change the divisor without creating an output glitch, you may require some additional logic to time when the multiplexer select bits are updated.