Why 4 regs to control a FSM? Verilog
First of all, there are *_d and *_q versions of each variable because the designer follows the practice of using two separate always blocks for his state machine.

The state machine requires timed waits at various stages of its operation, and instead of having a separate state for each one, he wrote just a single common WAIT state. The next_state_* variables tell the machine what to do when the WAIT is over.