How to specify a minimum clock to output time in output timing constrain?
The set_output_delay -min SDC syntax does this (Vivado XDC file.) You specify the 'min' value as a negative number as this event happens after the clock.

(What's SDC? Stands for Synopsys Design Constraints, which Xilinx, Altera and others have adopted for specifying timing and other routing / synthesis constraints. With Vivado, SDC replaces the old Xilinx ISE way of doing this. SDC is based on tcl language syntax.)

Generally,


Use an ODDR (Xilinx) clock forwarding scheme to create your external clock. This gives the best control over clock skew, and will give you some hold time by design.
Define this external forwarded clock as a virtual clock using create_generated_clock
constrain your output to the virtual clock using set_output_delay.


More about this here: http://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/

And... here: https://forums.xilinx.com/t5/Timing-Analysis/How-to-set-input-delay-and-output-delay-when-source-Synchronous/m-p/940275#M16092

(On Xilinx boards I'm vortex1601. When it comes to timing questions though, Avrum is da man ;-)

Maybe time to migrate to Vivado?