Can specific pipeline latency arithmatic block be inferred when using * or / operator in VHDL?
Sticking with Intel FPGA tools. I have recently had this exact same question.

The short answer is that you can't do what you want to do. Quartus does not allow you to specify pipe latency just using a divide operator. It's unlikely that any tool would as the divide operator is defined by the language and is overloaded by the single most common package in the language: Numeric_std.

The long answer is; you could do this if you wrote your own overloaded version of the divide operator which is, in VHDL, just a function after all. You could somehow link this to an instantiation of a divider module (create a divider elsewhere to obtain the HDL code created by the wizard. This matches the pattern the tools use to recognise a divider. Or write your own for fun) and insert the number of stages into the Generic Map.

You could then analyse the RTL and Technology Map viewers to ensure that what you've specified has actually inferred either DSP modules (if the device supports this) or the most efficient logic for a divide operation in this device.

You could then test out if you meet all the myriad timing requirements.

After all that, you can do what you want to do. Maybe.