Explanation of Edge Triggered D type flip flop triggered at positive edge of the clock pulse cycle (from Morris Mano Book)?
When clock = 0

NAND2 and NAND3 outputs are 1, simply because one of its inputs became 0 (clock). Hence S and R becomes 1 and remains at 1 as long as clock is 0. 

(R,S) = (1,1) => (Q,Q') holds present state.

When clock = 1 and D = 0

See NAND4 -- inputs are (1,0) , hence output = 1. This output feeds NAND3, whose inputs now become (1,1,1). Hence output = 0 i.e, R became 0.

See NAND1 -- inputs are (1,1), hence output = 0. This output feeds NAND2, whose inputs now become (0,1). Hence output = 1 i.e, S became 1.

Result is therefore (R,S) = (0,1) => reset condition for the third NAND based SR latch. => (Q,Q') = (0,1)

When clock = 1 and D = 1

I leave this to you.