How does modules in an asynchronous circuit know when to signal that their output is ready?
No central clock does not mean no clock at all. M1 and M2 do not need to know at which speed each runs; they must know what each other are doing, and have protocol between them defined. What they both must do is to ensure they pass data from each other properly, and it must happen in synchronized way for consistent data transfer.

In your diagram you depicted very high level request / acknowledge transfer system; in real implementation it may be more complex than that, and may include clocks between the devices.