Serial Communication Rx ISR logic design
B has so many stuff to do in the ISR

No, at least not if you architect the system right.  I would keep any decoding logic out of the ISR.  Usually my UART interrupt handler grabs the byte from the hardware, clears the interrupt condition, and stuffs the byte into a FIFO.  The foreground code can take it from there.  Make the FIFO large enough so that the foreground code can run in bursts and the FIFO doesn't overflow between bursts.

If there's just too much to do per byte, then you have a fundamental problem that firmware can't fix.  You need a faster processor or slower communication.