Verilog loop for multiple always blocks
I learned […] every reg needs to have his own always block…


I think you've got this backwards. Each register should only be assigned to by one always block. However, this doesn't mean you need a separate always block for each register! It's perfectly safe (and, in fact, quite normal) to have a single always block for all the synchronous logic in a module, e.g.

always @(posedge clk) begin
    if (reset) begin
        A &lt;= 4'b0;
        B &lt;= 4'b0;
        …etc…
    end else begin
        …etc…
    end
end



  What if I have a loop, lets say something like this:


You can't do that in a loop.

Verilog loops are for generating multiple copies of repeated logic. They are not a substitute for clocked logic -- if you need to perform multiple actions, you will probably need to make them happen on separate clocks, and implement them in a state machine.

Depending on what you need to happen, there might be some way to "unroll" the loop and make several iterations happen in a single clock. However, you will need to be very careful about how you implement this. Making multiple levels of branching logic run in a single clock cycle is generally inadvisable; data dependencies will severely limit the clock rate of such a design.