the output register remains x in the waveform even when clock changes?
The initial value (at time 0) of the reg type in Verilog is X.  At the first posedge of clk, 1 is added to X, which results in X.  So, the out signal remains at X throughout the simulation.  You have two choices:


Initialize out in an initial block (to 0, for example), or
Use a reset signal to initialize out