How does using Flip Flops between transmission links increase the maximum clock speed?
I think you may be confusing on-chip propagation delay with transmission delay.

Within a microprocessor, the maximum clock speed is limited by the longest propagation delay through the logic between one flip-flop and another. Inserting an intermediate flop and "pipelining" the design allows the increase of clock speed. The wiring is generally so short that it's not considered as a transmission line.

On a board, there's no sensible advantage to inserting discrete flip-flops.