CMOS circuit design: How to implement an interrupt circuit that detects minimum or maximum peak?
"I want this!"


You're not the only one. Such a circuit would be very useful to tell when share prices had bottomed out and I'd use the interrupt to tell me when to buy. As drawn in your second diagram you are looking for a circuit that will predict that this is the lowest value that's coming. We don't have electronics to predict the future.

What you can do is check if the voltage stops decreasing for some time (that you specify) and trigger on that. The interrupt will be delayed by that time value.







simulate this circuit &ndash; Schematic created using CircuitLab

Figure 1. Simplified interrupt circuit.


Comparitor output will go high on rising input. 
R1-C1 determine the lag of the non-inverting input.
DELAY will determine how long the signal is high for before triggering. This will have to be longer than your longest "Not This!" period.
R2 is included as a reminder that many comparitors have open-collector outputs.




Figure 2. What you can have - if you behave.

You might be able to do the delay in software by feeding the comparitor directly into the interrupt and setting a timer interrupt to check if the comparitor is still high after the required delay.