74HC377 Octal D flip-flops latching on falling edge of clock
Double clocking can happen if the clock is not clean or has a slow falling edge.
On the negative edge any noise can cause the device to interpret it is another positive edge if there is noise.
This noise could be caused by actual noise, by coupling from other signals or ringing on the clock signal itself. Noise on the ground could also cause a similar effect.
A series resistor at the source of the clock could help reduce ringing. Typically a 33 ohm resistor at the source is used.
Buffering the clock may help if the clock edge is slow.