Is this code implying a latch and unsafe (verilog)?
There is no latch inferred at all. It is simply a flip-flop (well several) with either a clock enable, or a multiplexer of its own output and some other input.

A latch would be inferred if it was asynchronous logic - i.e. you had no clock. In that situation you may indeed have a latch as the asynchronous logic would need to hold its value (in this case, if it was async, I think there would have been).

If you are using synthesis tools like Altera Quartus or Xilinx ISE, they generally include RTL netlist viewers which give you an approximate idea of what you are inferring. Below is what your code produces. Note the mux (gets called div~[32..0] by the synthesis tool) on which one of the inputs is the current value of the register.





As an aside, and while I am well aware your example is just practicing, it is worth noting that division and modulo require massive amounts of logic to implement and as such are either very slow or need lots of pipelining. The are not operations well suited to FPGAs. There are ways of doing primality tests that don't require the modulo operation which may be better suited to the FPGA. 

In case you are curious, and just for the fun of it I compiled the code targeting a Stratix V device (which are one of Altera's to end FPGAs), and the tools report that the design could only run at a whopping 21MHz - without the modulo, it could probably run at upwards of 300MHz :).