Why are INTERRUPT CONTROLLER SPECIAL REGISTERS in arm different from others?
This is an extremely useful feature.  The whole point is to be able to modify individual bits of the register with an atomic (non-interruptable) operation instead of a read-modify-write operation.  This is actually rather common for interrupt flags.  

The whole idea of interrupt flags is that the hardware sets the flag when the interrupt occurs, and then software clears it after it has handed the event.  The event to set the flag can occur at any time, including during the execution of an ISR and during an instruction that accesses the flag register.  

Suppose your flag register starts at 00000000.  A hardware event occurs that sets a bit.  Say, bit 2.  So the register reads as 00000100.  Now, another interrupt occurs and sets another bit.  Say, bit 3.  Now the register reads as 00001100.  

Now let's say the ISR to handle the first interrupt tries to clear the corresponding bit.  If the register supports atomic clearing, then the CPU can execute a single atomic write of 00000100 to clear the bit.  The register now reads 00001000.  Great.

Now, let's suppose the CPU does not support this, and the software has to do a read-modify-write operation.  Let's say the flag register is 00001100.  To clear bit 2, the software reads the flag register into a general purpose register, clears the bit, and then writes it back.  So it will read 00001100 into a register and clear the bit.  At this point the flag register is still 00001100 and the general-purpose register holds 00001000.  Then the CPU writes the register value back to the flag register.  At this point the flag register reads 00001000.  So far so good.  So what's the problem?

Well, suppose a hardware interrupt occurs AFTER the flag register is read, but BEFORE it is written back.  Let's say the flag register is 00001100.  To clear bit 2, the software reads the flag register into a general purpose register, clears the bit, and then writes it back.  So it will read 00001100 into a register and clear the bit.  At this point the flag register is still 00001100 and the general-purpose register holds 00001000.  Now suppose the interrupt controller sets bit 6, so the flag register becomes 01001100.  Then the CPU writes the register value back to the flag register.  At this point the flag register reads 00001000.  The flag that the hardware set has been reset, and that interrupt event is lost.  

This type of register would likely be implemented physically as a set of SR latches, or a flip flop with a bit of logic (perhaps D = (Q &amp; ~(WE &amp; data)) | set).  Reads would read the output of the latches.  Interrupt signals would be connected to the 'set' inputs, and writes to the register would drive the 'reset' inputs.