Fast to Speed of Three Nand Architecture, Need Help?
The question does not specify clock and clockbar.  Are we are to assume that clockbar is generated after clock? But, in real digital circuits clocks are implemented using a tree.  This means you can either go UP or DOWN the tree from a spot, either is an inversion.  So, clockbar may well be before clock.  

But, I will assume both clock and clockbar are arriving at the same time and opposite polarity.

The question does not specify the relative ratio between PMOS and NMOS.  I'll just assume they are even.

Both A &amp; B have a similar topology, except A uses an NMOS to charge the internal node during the low-phase of the clock, and B uses a PMOS to pull up the internal node during the low-phase of clock.  Precharging internal nodes in dynamic gates is done to mitigate problems due to charge sharing.  The downsides are increased area and power.

In A, the internal node is precharged to the supply voltage, because a PMOS can pull up fully to a high value.
In B, the internal node is precharged to the supply voltage minus a threshold voltage, because the NMOS cannot fully pull up to a high value.

So, by this logic, B is faster than A, because when switching A has extra charge to discharge during a falling edge.

C which is always slower because there is more contention created by the dual-keeper structure.  What I mean by this, is both keepers are fighting to keep the output node and the internal node in pulldown stack at '1' when the output is a '1'.  

So, if you want to write a '0' into this circuit after precharge (only time dynamic NAND's will really have a 'delay', since precharge causing output-rise doesn't quite count), you have to fight both PMOS which are currently trying to pull the output node/internal node up to '1'.  

One guess for why they have A faster than B? The clockbar signal.  If clockbar is assumed to be generated from clock, then there will be a gate delay (there are other ways to generate opposite polarity signals w/ minimal phase shift).  This means that when clock rises, and the inputs try to pull down the output node in circuit B, there is (for a brief period = inverter delay) an NMOS trying to pull the internal node up.  This is contention and will slow down the circuit.