biploar amplifier, voltage gain, and determining resistor values
I think it is clear, now, that you are under water on this assignment. I don't need to see the PDF file to realize this. (You could, I suppose, upload it to some service and make the link available. But then we'd have to read it and interpret it and discuss the interpretation of it with you and that all by itself would be half a chapter's worth of discussion.) You face a circuit that has a very tight \$V_{CC}=2.5\:\textrm{V}\$ requirement and you don't know anything about why the emitter leg, as shown, exists as it does. I suspect there is more you don't know about the circuit than you do know.

(This is not a criticism of you. All of us start from total ignorance and have to move forward, one step at a time. Just the fact that you are trying is what is important. Not so much where you are along the path, right now. Just apply effort and don't let anything stop you. That's all anyone can ask, I think.)

I'll toss out a few thoughts to help orient you, though. These details will not directly answer the question about setting "the resistors of this circuit that produces the highest voltage gain as possible." But in suggesting some thoughts to consider, it may trigger some recollections in you that will help you better frame the problem in your mind. I can hope.


In a circuit like this, you generally do not want the BJT to saturate. Saturation itself isn't a yes/no binary question. It's a process. A BJT moves from an active mode (with an Early Effect that may or may not be a problem) gradually into saturation that is deeper and deeper. As it moves out of the active mode and gradually into saturation, the base requires an increasing share of the total emitter current and this significantly changes the loading and therefore the DC biasing point set by \$R_2\$ and \$R_3\$. (Also, in active mode the collector is closer to a current source in behavior and in saturation the collector is closer to a voltage source in behavior.) All this means that a designer generally will want to at least stay out of heavy saturation, if not entirely out of it. Your \$V_{CC}=2.5\:\textrm{V}\$ might make a designer question this a bit and be willing to sacrifice just a few tenths of a volt into saturation, as it's almost harmless if it is this shallow. If you haven't been taught any of this yet, then you won't understand what I just wrote here. All I can offer then is that you consider using \$V_{CE_{MIN}}\approx 500\:\textrm{mV}\$ or more. The goal is "highest gain," but there is always a balancing act here with this low of a \$V_{CC}\$.
The emitter leg includes \$C_2\$, \$R_5\$, and \$R_6\$, arranged so that you have a DC bias point for the emitter, formed by the series resistance of \$R_5+R_6\$ and the quiescent emitter current. But you also have an AC gain that is set differently, due to \$C_2\$ bypassing \$R_6\$ "at AC." This assumes, of course, that the impedance of \$C_2\$ can be taken as zero for all frequencies of interest. (The reality will be different.) The reason for going to all this trouble of using three devices in the emitter leg like this is so that the DC bias point can be set to compensate for temperature and part variations of \$\beta\$, while at the same time allowing for a higher AC gain than would otherwise be possible. In addition, you need to also minimize the impact of \$r_e\approx \frac{k\: T}{q\:I_E}\$ on your AC gain and so \$R_5\$ can't be too small, either, for both temperature reasons as well as for gain variation vs signal (distortion.)


Even if someone wanted to provide a careful walk-though for you, it's just not in the cards. Not here; not now; not with what little you know about what's being asked of you.

Better guidelines might be provided, if your \$V_{CC}\$ were a lot larger -- such as \$V_{CC}=20\:\textrm{V}\$, for example. Then some of the crafted judgment issues could be waved aside and a more formulaic approach provided. But you are handed \$V_{CC}=2.5\:\textrm{V}\$ and this very low value means that many added compromises are required. Compromises that cannot even be discussed well without some more information.

I might decide here that \$V_{CE_{MIN}}=500\:\textrm{mV}\$ and just live with the fact that there might be slight saturation going on with part of the signal and accept the added distortion. But, a distortion specification might say otherwise. I might also have to compromise on the usual figure of a minimum of least ten times \$V_T\$ across \$R_5\$. But, again, I've nothing to go on so how can I decide? I also don't know what DC value to apply to the emitter. I'd like it as high as possible to minimize the impact of \$\beta\$ variation by part and over temperature. But in this situation how much minimization can I accept? I don't know, again. No information here.

Faced with so little to go on, I'd just make stuff up, document the choices, and then do a proper design on the basis of those added assumptions to the problem. Then, at least, I could justify and support the resulting design to anyone challenging it.

Let's say I went with \$V_{CE_{MIN}}=500\:\textrm{mV}\$, set the quiescent DC emitter voltage at \$V_E=500\:\textrm{mV}\$ and split the difference for the two resistors, \$R_5\$ and \$R_6\$, on the basis that I need at least \$250\:\textrm{mV}\$ across \$R_5\$ and wanted some protection vs part and temperature variation of \$\beta\$, too. Then I'd arrive at setting the quiescent voltage at the collector of about \$1.7\:\textrm{V}\$, or \$I_C\approx 90\:\mu\textrm{A}\$. I'm staring at an AC gain of less than 3, then. Does that meet the question's requirements?? How would I know? I could reduce my demands about part and temperature variations and distortion due to signal excursions, of course, and increase the gain. But how do I know how to balance all these things? There is no way to know.

Too little information.



\$A_V\ge 10\$ is an important new specification. However, it would seem on the surface to disagree with your statement the "the resistors of this circuit that produces the highest voltage gain as possible." There is a different between saying "at least 10" and "highest possible." So is which is it?

The capacitor values aren't as important here. I already gathered that \$R_4=9\:\textrm{k}\Omega\$ from a comment you made. The input impedance and the load still aren't stated.

That said, a voltage gain of 10 or more can be achieved. You know that with maximum swing at the collector, the current can at most vary from 0 to twice the quiescent current. At twice, \$2.5\approx V_{CE_{MIN}}+2 I_C \left(R_4+R_5+R_6\right)\$, discounting the slight differences between \$I_C\$ and \$I_E\$. The gain suggests that \$\frac{R_4}{R_5+\frac{26\:\textrm{mV}}{I_C}}\ge 10\$. And you need to set a quiescent emitter voltage: \$I_C\left(R_5+R_6\right)=V_{E_Q}\$. From all that, there are still a small bounded range of solutions you could select.

For example, you could select \$A_V=10\$ and \$V_{E_Q}=100\:\textrm{mV}\$ and get \$I_C\approx 100\:\mu\textrm{A}\$, \$R_5=640\:\Omega\$, and \$R_6=360\:\Omega\$. From there you can estimate the \$V_{BE}\$ of the transistor (not much more than \$600\:\textrm{mV}\$ and then work out the base voltage, likely base current and then the two base biasing resistor values.

I didn't solve the equations for you. You'll need to work that out on your own. But I did provide the results of a worked example so that you'll know when you get it right.

(You can move the gain around by keeping the total resistance of \$R_5+R_6\$ the same, while varying \$R_5\$ to modify the gain.)



Your estimating equation about \$I_C=30\:\textrm{A}\$ is way off. You need to re-figure that issue.