How to regulate voltage across capacitors
The voltage regulation is achieved by using the zener as more of a reference than a standalone regulator and as part of an overall feedback loop.

As the output starts to rise above the desired set point (about 33.7V), the base of the NPN will be pulled up (The zener will maintain about 33V across itself), causing the collector voltage to go down; this will, in turn, pull down the base of the PNP.

That will cause the collector voltage of the PNP to rise, causing the gate of the PMOS pass element to also rise, which will start to turn it off (it is actually going to increase the pass element resistance). This increase of resistance will cause the excess voltage from the source to be dropped over the PMOS device.

The PNP is therefore part of both the current limit and output voltage regulation scheme.

The 10V zener across the gate to source of the PMOS device is to prevent the gate voltage exceeding a safe level