weird Altera simulation result
The first schematic shows a latch rather than a D flip-flop -- it forwards D to Q when CLK is high. Q maintains its value for CLK low.

This would almost explain the behavior of your latter circuit. Q should remain constant when CLK is low. It will forward !Q when CLK is high and therefore oscillate.

Why the oscillation happens with CLK low I cannot explain (perhaps the two screenshots are inconsistent?).