Inferring D-latch on Zedboard within Vivado Error
One thing you could do is use an Earle latch, which is a form of D latch using an AND-OR with three terms. It shouldn't be recognized as sequential (clocked) logic by your synthesis tool. See How can I implement a simple, Q only, D-latch using VHDL?.

Without expressing a second latch for Qbar:

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
    port (
        D:      in  std_logic;
        Enable: in  std_logic;
        Q:      out std_logic;
        Qbar:   out std_logic
    );
end entity;

architecture fum of dlatch is
    signal QQ:   std_logic;
begin
    process(D, enable, QQ) 
    begin
        QQ &lt;= (Enable and D) or 
              (not Enable and QQ) or
              (D and QQ);          -- consensus term
        Q &lt;= QQ;
       Qbar &lt;= not QQ;
    end process;
end architecture;


This should be synthesis eligible.

And here is a testbench to determine the three terms are correct:

library ieee;
use ieee.std_logic_1164.all;

entity dlatch_tb is
end entity;

architecture test of dlatch_tb is
    signal D:       std_logic := '0';
    signal Enable:  std_logic := '0';
    signal Q:       std_logic;
    signal Qbar:    std_logic;

    component dlatch is
        port (
            D:      in  std_logic;
            Enable: in  std_logic;
            Q:      out std_logic;
            Qbar:   out std_logic
        );
    end component;

begin
DUT:
    dlatch
        port map (
            D =&gt; D,
            Enable =&gt; Enable,
            Q =&gt; Q,
            Qbar =&gt; Qbar
        );
STIM:
    process
    begin
        wait for 10 ns;
        Enable &lt;= '1';
        wait for 10 ns;
        Enable &lt;= '0';
        wait for 10 ns;
        d &lt;= '1';
        wait for 10 ns;
        Enable &lt;= '1';
        wait for 10 ns;
        Enable &lt;= '0';
        wait for 10 ns;
        wait;
    end process;
end architecture;


On the other hand "- Never mind"


  I'm using user I/O on the constraints for the inputs/outputs. I assign the inpu(t)s to two SWITCH Pins and the outputs to two LED pins.


and        


  How can I find a clock capable input that I can press/move like I do on the switch?


If you're using switches to operate your latch you shouldn't care about sub optimal routing and setting the 'CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING' is perfectly valid.

It's highly unlikely you can manage to toggle both switches so close together you risk getting the 'wrong' state stored with any degree of certainty which order they toggled. We're talking about sub optimal routing on the extremely close order of a nanosecond considering the low capacitive loading.