Interfacing Wiznet W5300 with a Spartan 3 FPGA?
I'm not going to provide a design example as I'm not going to do this for you and you can search Google just as effectively as I can.
All the information you require can be found in the device datasheet:

https://www.wiznet.io/wp-content/uploads/wiznethome/Chip/W5300/Documents/W5300_DS_V134E.pdf

Section 6 contains information on the data bus that would interface with the FPGA. This is a parallel data bus with a few controls (chip select, interrupt, read and write) and an address input; it is not an SPI bus. It also has a few modes (direct/indirect) that can be used to reduce the pin count of the bus at the expense of latency.

Timing diagrams can be found at the end of this section.

The premise of this setup is that you write/read to the bus as if you were writing/ reading from a memory device. The memory mapping for this device can be found in Section 2 &amp; 3.
When transmitting you write to the data area of memory and send a request to send. Conversely, when receiving, a request to read will be sent (either by an interrupt or polling the appropriate flag) when valid data is received and you read direct from the rx data buffer.

Section 4 details the individual registers and how you configure the device. Of most interest is the detail of the Socket registers.

This is actually quite a neat little device and is a good little beginners/intermediate project.

Good luck and don't forget your timing constraints!

Edit:
Quoting from a comment:


  Thank you for your reply, but I am a bit confused regarding the Address Bus width in the Direct Address Mode.The data sheet states: "In case of using a 16bit data bus width, ADDR[9:1] is used and ADDR0 is connected to ground or floated", but I am unable to understand why is the address bus of 9 bits in 16 bit data bus mode while in the case of 8 bit data bus width, ADDR[9:0] is used?


You can use either a 16 bit or 8 bit wide data bus to communicate with this device. However, the device memory space remains the same. With 8 bit data words this device allows you to address 2^9 memory locations. However, with 16 bit words you can only address 2^8 memory locations (exactly half). 

ADDR0 is the 9th bit used in 9 bit addressing (8 bit data words) and is redundant for 8 bit addressing (16 bit data words). The statement you are quoting (pg119 of the data sheet) is just telling you what to do with the unused pin.