DDR3 SE signal, is 50Ohm impedance necessary?
It might work or not...
The only thing we can be sure of is that it should work if you use a 50 Ohm impedance. Anything else is pure speculation because it's out of specs.
Of course, there is no &quot;brick wall&quot; (i.e.: at 50 Ohm it works but at 51 Ohm it doesn't work at all.). The transition is smooth and there is a region between the &quot;it works&quot; and &quot;it doesn't work&quot; : The infamous &quot;It sometimes works&quot;.
Intermittent failures are part of the most difficult things to debug.
DDR3 memory buses are very sensitive to signal integrity. And you will find documents that list an intimidating set of rules one has to follow to ensure good integrity on that bus. For instance :

Length matching between some signals (but no all)
Impedance: single ended and differential
Grounding: Don't cross a plane boundary (GND plane or power plane)
Kind of decoupling caps: Use Y5V and you are stuck...
...

Because debugging memory issues can be very difficult and time consuming, I strongly suggest that you try to follow exactly all the recommendations and guidelines. It's difficult enough to ensure a reliable design when trying to follow the rules...
If your PCB shop cannot provide a suitable stack-up, find another one that can.