Why does decreasing the voltage also decrease the circuit frequency?
Decreasing the voltage decreases the maximum frequency that can be used such that the operation of the digital system is as desired.
This is because the equivalent resistance, \$R_{eq}\$, of the MOS transistor increases if \$V_{dd} &lt; V_T\$. \$V_{dd}\$ is the supply voltage and \$V_{T}\$ is the threshold voltage. As the equivalent resistance increases the propagation delay of the inverter increases, since the propagation delay is proportional to the equivalent resistance.
Propagation delay is the average of the high to low propagation time and low to high propagation time. The output rise time and fall time depends on the propagation delay of the transistor.
The equation of propagation delay of the inverter is
\$t_p = 0.69*R_{eq}*(C_{in} + C_{ext})\$.
\$C_{in}\$ and \$C_{ext}\$ are the internal and external capacitances of the gate.
As the propagation delay increases the maximum frequency the circuit can use has to decrease, else it would violate the dynamic discipline of digital circuits. Further reading on dynamic discipline: https://computationstructures.org/notes/sequential_logic/notes.html
Modern computers use Dynamic Voltage and frequency scaling, i.e. the frequency is reduced if the supply voltage is reduced.