Is it a bad idea to use unsized integer constants in equality expressions in Verilog?
It is always a good idea to specify the bit width where possible.
(I know this may be a lot of work if you have a 4-bit counter which you used 20 times and then needed to go to 5 bits).

However what counts (to me!) is that in the end these all produce the same amount of gates:

localparam [3:0] SIZEA = 5;
localparam SIZEB = 5;
reg [3:0] ctr;
ctr &lt;= ctr + 1;
ctr &lt;= ctr + 4'd1;
ctr &lt;= ctr + SIZEA;
ctr &lt;= ctr + SIZEB;



  Are there any good guidelines about when its safe to use unsized integer constants in expressions?


The basic rule I use for myself is:

"Know what you are doing but realize others might not be as proficient in Verilog coding." 

Additional: many companies have a coding guidelines. Some where I have worked for insisted that all code pass some lint tool. The latter meant that almost every addition had to be written like:

wire [3:0] a,b,c;
assign c = {a + b};


Do you know why?   


  Because the standard addition in Verilog produces a carry. Thus a + b is 5 bits wide. But c is only 4 bits and the linting tool complains about that.  By using {...} we force the addition to the strict size of 4 bits.


Last but not least: Be extra vigilant when using constants in concatenations. 

These produce the same result:

wire [7:0] a,b;
assign a = {1,b[3:0]};
assign a = {4'h1,b[3:0]};


But these do not:

wire [7:0] a,b;
assign a = {b[3:0],1};
assign a = {b[3:0],4'h1};


Why? 


   {1,b[3:0]} equals {32'b00000000_00000000_00000000_000000001, b[3:0]}
 The top bits are dropped in the assignment so the net effect is a = {4'b0001, b[3:0]}

 This is in contrast to {b[3:0],1} which equals    {b[3:0],32'b00000000_00000000_00000000_000000001}
 Again the top bits are dropped in the assignment so the net effect is: a = {8'b00000001}