Verilog - Synthesize High Speed Leading Zero Count
Leading zero encoders can be made with a nice balanced tree structure.

First, encode bits 2 by 2 :


00 => 10 : 2 leading zeros
01 => 01 : 1 leading zero
10 => 00 : 0 leading zero
11 => 00 : 0 leading zero


Then, assemble as pairs.


If both sides start with 1xxx, the result is 10...0
If the left side start with 0 the result is 0[left]
If the left side starts with 1, the result is 01[right(msb-1:0)]


You only need multiplexers.

For example the 8 bits value : 00000111


2 by 2      : 00 00 01 11
encoded     : 10 10 01 00
assemble    : 100   001
assemble    : 0101 = 5 leading zeros.


In VHDL (I have no Verilog code at hand), you get that :

FUNCTION enc(CONSTANT a : unsigned(1 DOWNTO 0)) RETURN unsigned IS
BEGIN
  CASE a IS
    WHEN "00" =&gt; RETURN "10";
    WHEN "01" =&gt; RETURN "01";
    WHEN "10" =&gt; RETURN "00";
    WHEN OTHERS =&gt; RETURN "00";
  END CASE;
END FUNCTION enc;

FUNCTION clzi(
  CONSTANT n : IN natural;
  CONSTANT i : IN unsigned) RETURN unsigned IS
  VARIABLE v : unsigned(i'length-1 DOWNTO 0):=i;  
BEGIN
  IF v(n-1+n)='0' THEN
    RETURN (v(n-1+n) AND v(n-1)) &amp; '0' &amp; v(2*n-2 DOWNTO n);
  ELSE
    RETURN (v(n-1+n) AND v(n-1)) &amp; NOT v(n-1) &amp; v(n-2 DOWNTO 0);
  END IF;
END FUNCTION clzi;

FUNCTION clz64 (CONSTANT v : unsigned(0 TO 63)) RETURN unsigned IS
  VARIABLE e : unsigned(0 TO 63);     -- 64
  VARIABLE a : unsigned(0 TO 16*3-1); -- 48
  VARIABLE b : unsigned(0 TO 8*4-1);  -- 32
  VARIABLE c : unsigned(0 TO 4*5-1);  -- 20
  VARIABLE d : unsigned(0 TO 2*6-1);  -- 12
BEGIN
  FOR i IN 0 TO 31 LOOP e(i*2 TO i*2+1):=enc(v(i*2 TO i*2+1));  END LOOP;
  FOR i IN 0 TO 15 LOOP a(i*3 TO i*3+2):=clzi(2,e(i*4 TO i*4+3)); END   LOOP;
  FOR i IN 0 TO 7  LOOP b(i*4 TO i*4+3):=clzi(3,a(i*6 TO i*6+5)); END   LOOP;
 FOR i IN 0 TO 3  LOOP c(i*5 TO i*5+4):=clzi(4,b(i*8 TO i*8+7)); END LOOP;
 FOR i IN 0 TO 1  LOOP d(i*6 TO i*6+5):=clzi(5,c(i*10 TO i*10+9)); END LOOP;
 RETURN clzi(6,d(0 TO 11));
END FUNCTION clz64;


enc() does the encoding
clzi() merges two vectors.
clz64() is a sample implementation for a 64bits input.