Shift register - counter
For the correct answer consider the value shifted into the left most bit position to be the Exclusive OR of the current states of A and D.  So, for the first shift since A and D are both 1's the Exclusive OR would be zero and zero would be shifted into the left most bit.

(A list of logic symbols which includes what "=1" means can be found here.)

That is to say, starting with A, B, C &amp; D being 1101, the next state would be 0110. And the state after that would be 0011. Armed with this information it should be easy find the 3rd and 4th states.