A question about instantiating a module with a parameter in systemverilog
The problem is module instantiation happens at code elaboration before the simulation of any initial blocks. So you cannot use a variable to override a module parameter. 

What you can do is parse the file externally to Verilog and either create a `define definition that you compile your source code with, or Questa allows parameter overrides through the command line (look for the vopt -g/-G switches in the user manual)



The defines.vh file would look like 

`define TEXT_LEN 5


And your module file would look like

module TB();
`include "defines.vh"

ABC #(.text_len(`TEXT_LEN)) ABC_1(//some input/output arguments here);