Parallel in serial out Verilog Shift Register, odd behavior during clocking
You have misinterpreted the schematic. This line:

nand3 control(!CP, !CE, PL, bus[16]);

is in contradiction with:


CP is active high,
CE is active low (note the bar above the "CE" on the schematic). 
yet you use two inverted signals in the instantiation,


Also:


the bus you think a bus is just a wire (note the connecting dots!)
and I don't understand the control_mux concept entirely...


Now, checking out the NXP documentation, the schematic of theirs differs from what you attached.

And finally, why are you hand-instantiating gates instead of just coding up the functionality? 

Like:

module sr_74LV165A (
  input DS, CP, CE_n, PL_n,
  input D0, D1, D2, D3, D4, D5, D6, D7,
  output Q7, Q7_n
);

reg [0:7] shr;
wire      clk;

assign clk = CP | CE_n | !PL_n;

always @(posedge clk or negedge PL_n)
  if   (!PL_n) shr &lt;= { D0, D1, D2, D3, D4, D5, D6, D7 };
  else         shr &lt;= { DS, shr[0:6] };

assign Q7   =  shr[7];
assign Q7_n = !shr[7];

endmodule


After all, this is just a shift register with parallel async load.