What exactly do we write in a test vector?
test vectors sound to me like HDL (hardware description language: VHDL and Verilog).
In general, test vectors mean a listing of all possible inputs and their expected outputs in order to check the correctness of a system.
But you can also write test vectors to check a single given functionality in a complex system.
Keep in mind that for registered systems (those with memory - latches) it becomes more complex than for simple combinatorial systems.
Here is a guide from an FPGA maker to write test vectors:
http://www.actel.com/documents/TestVector_AN.pdf