How to Design D flip flop using T flip flop?
Make a logic table that shows how to get from the inputs and current state to the signal you need to generate the next state you want:

D     Q  |  T     Q'
---------------------
0     0  |  0     0
0     1  |  1     0
1     0  |  1     1
1     1  |  0     1


D is the input to the D flip-flop you are construcing. Q is the current state (output) of your flip-flop. T is the input to the T-flip-flop you are using internally to build a DFF, and Q' is the next state you are going to produce after a clock edge.

Now, what gate that you know about maps the D and Q inputs to the T signal you need?