Lattice — Should I prefer IPX/PMI over Verilog arithmetic builtins?
There's a fundamental functional difference between your code and what the IPX thing does: yours is not clocked.

Also, you can explitly tell the IPX thing how many pipeline stages you want, something that's impossible in a simple a * b combinatorial statement.

I don't know the features of IPX or PMI primitives, but you can rest assured that unless you really just need a combinatorial multiplication (that is, unclocked!), it makes sense to use a module that lets you explicitly state the way you want things to be implemented.

Generally, don't underestimate the complexity and degrees of freedom that an implementation of a basic arithmetic operation brings (and hides): For example, on a Lattice ICE40, a multiplier of two 8-bit numbers (unsigned!) can look this complex when mapped to the technology available in that FPGA:



(full 100 Megapixels (!) image)

Don't assume that a*b can magically infer whether you'd rather trade speed for space, or vice versa; whether you need the result registered or not; whether maybe high clock rate is more important than requiring a low number of clock cycles... Not even mentioning things like how the desired output width, and if lower than the maximum product, how to deal with that.