Power switch (backup battery voltage is higher than main line voltage)
How about the following design? 

(The 12V is constant, the 5V is switching on and off every second.)



When 5V is on, NMOS3 opens, pulling down gate of PMOS2, which thus also opens, pulling up gate of PMOS1, closing off 12V.

When 5V is off, NMOS3's gate is pulled low closing it, which leaves gate of PMOS2 pulled up closing it, which leaves gate of PMOS1 pulled down, opening it.

Note, that when 5V is on, there is only insignificant leakage from the battery (proportional to the leakage current of the MOS gates).