8 bit counter from T Flip Flops
Your schematic shows a T-type flip-flop, which toggles when its input is high. Your rtl code, on the other hand, implements a regular D-type flip-flop. Your module should instead read:

always@(posedge clk, negedge clr)
begin
    if(~clr)
        q &lt;= 1'b0;
    else
        q &lt;= q ^ t;
end


By XOR'ing the output with the input, you will toggle the state when t is high, creating a T-type flip-flop.

The module instantiation is also different from the schematic. Your t inputs are all missing the &amp;&amp; enable that the leftmost AND gate in the schematic implements.