In a tristate buffer which transition time should be larger
A tristate buffer has a certain minimum time from when the enable is asserted to when its output impedance starts to fall (the drivers start to turn on). Also, it has a certain maximum time from when the enable is negated to when the drivers are fully off (high output impedance).

If the former is not greater than the latter, then you cannot use the same (well, inverted) enable signals directly for two buffers on the same bus; you need to guarantee the timing by other means &mdash; either by using different clock edges, or perhaps by using a delay line.