Phase Detector for PLL: Operation and Realization
A PSD followed by a VCO can form a PLL, if the PSD output voltage can produce a correct tune voltage for the VCO. That PLL will be stable, and have a bandwidth defined by the gain round the loop. However, we invariably add a loop filter to a PLL to make it 'better', better at following the reference phase, and better at rejecting the reference high frequency noise.

If we wanted to make some assumptions about the diagram you've presented, then the PSD would swing +/- with respect to ground, being 0v for 90 degrees phase shift, and the VCO's tuning input would be 0v for nominally the correct frequency, so the resulting PLL would indeed lock at 0v = 90 degrees.

The VCO's frequency to phase transfer function is first order. That is, the gain of the loop falls at only 6dB per octave of modulation frequency. That is rarely enough to make a 'useful' loop. A loop filter gets added to any practical PLL to improve its tracking and rejection properties.

Note that the loop filter does NOT control the bandwidth of the loop, that's done by the gain round the loop, However, many tutorials and cookbooks on the subject assume a specific form for the loop filter, and then roll several calculations together, destroying intuition and making PLL design look like a black art.

To improve tracking, add an integrator to the loop. A simple integrator has 90 degrees phase shift, which added to the VCO's 90 degrees, plus any delay anywhere, and the resulting loop is guarranteed unstable. SO it has to be a 'broken' integrator, broken back before the loop bandwidth to drop its phase shift to &lt;&lt;90 degrees.

To improve rejection of high frequency noise, add a low pass filter to the loop. A LPF has up to 90 degrees phase shift per pole, so if the break frequency is set too low, it will make the loop unstable.