DAC behaviour on reset / startup LPC1768
During a reset, such as on power-up, your LPC1768 I/O ports will be configured as GPIOs in input mode. An LPC1768 I/O pin can output up to 3 uA of leakage current in this mode. When configured as a DAC, the same pin is specified as capable of driving a load resistance of 1 K or higher.

You don't specify your op-amp so let's assume that has an input leakage current of 2 uA. (You can readily find alternative op-amps with much less input leakage than this if yours is higher.)

This leakage current will be conducted to 0 V by your pull-down resistor and will produce a voltage drop across it, following V = IR. This voltage will drive your op-amp input during reset, until your software has configured your I/O for DAC operation, so the resistor voltage drop needs to be acceptably low. However, the resistor value should ideally be well above 1 K.

As an example, let's consider a resistor voltage of 20 mV. This corresponds to your op-amp driving 2 mA through your current regulator, assuming perfect accuracy there.

Then R = V/I = .02/0.000005 = 4000 ohms (a 3K9 resistor).

After reset, your software should configure the DAC while leaving the I/O pin in its initial state, as a GPIO input. Once the DAC is in the correct mode and set to zero, the GPIO can be configured as a DAC output. The I/O pin's optional pull-up resistor must not be used.

FURTHER FINDINGS...

From the LPC1768 user manual (UM10360), I didn't think the I/O pin pull-ups are enabled after reset. However, @Dorian has found information in the errata that states that they are.

Therefore, instead of the above, you can use an external defeat circuit to clamp the op-amp input to 0 V until the LPC1768 is stable and ready to drive its ADC output.

Choose a suitable logic-level FET for Q1 that is ON with a Vgs of 3 V or ideally down to Vgs of 2.7 V.







simulate this circuit &ndash; Schematic created using CircuitLab

On power-up, GPIO will be internally pulled high but it also pulled high by R2, which is added for certainty after the errata affair. Q2 will conduct and short R1 to deck, ensuring that the op-amp input is zero. Once your software is up and running, it first configures GPIO/DAC to be a DAC driving 0 V. It can then configure GPIO to be an output driving low, turning off Q2 and allowing the op-amp circuit to work normally.