Is state machine based sequence detector easier to verify than shift register based one?
In order to run an FSM, you must have a register that stores the current state of the FSM.
If you only want to recognise a specific sequence, a shift register is both verifiable and scalable. Even if your sequence is of undeterminate length, you will effectively need a shift register to parse each specifics of the sequence, resulting in the need for counters, flags, etc.
In practice, most sequences are of a specific length, which means that the task of recognition of more complex patterns within the sequences themselves is delegated to higher-level hardware.
Most likely, you might use a shift register to parse some length of the sequence and pass that on to an FSM that takes care of interpreting the sequence itself.
For example:

A shift register and comparator combination is more capable of recognising a simple specific pattern like the first bit of this sequence is zero, or The expected input is a specific bit sequence.
A FSM is more flexible in recognising more abstract patterns with multiple input and branching results, like the key sequence in a pocket calculator: while numbers are pressed keep first operand and add next digit; operation set: next number is second operand; while numbers are pressed keep second operand and add next digit; equal button pressed: calculate answer, show it to the screen and set result as first operand

However big the complexity, though, a FSM is still implemented through shift registers.