Negating a number in VHDL using least logic
begin 

     b &lt;= not(error) + "00000001"; 

end 


There are some edge cases, watch out, read this carefully.

I believe you know it but I'll mention it just in case. bits are bits and the interpretation of them is made by the user, it can be a picture, signal, number, positive number etc. most FPGAs treats numbers as 2's complement.