why fork- join is not supported in ISE Webpack?
As I don't do Verilog, it may be worth waiting for a Verilog expert to answer.

But meantime, wouldn't "fork/join" imply creating processes at runtime? If so, there's no way that will be synthesisable; you can't create or destroy gates on a running piece of hardware. And XST is a synthesis tool... (EDIT: technically gates can be destroyed but outside of fuse-based ROMs or PLDs it's not normal practice!)

Does the documentation happen to mention if this is a simulation-only construct? If so, Webpack probably does support it ... for simulation.

Incidentally I don't understand what "fork/join" is intended to accomplish here. In what I would guess to be the VHDL equivalent:

process(clk)
begin
   if rising_edge(clk) then
      a &lt;= 1;
      b &lt;= 1;
   end if;
end process;


the assignments to A and B take place simultaneously as explained here , so isn't fork/join redundant, or is Verilog even more different than I thought?