AM437x/AM335x Audio clock generation
Well, it seems you can't.

I guess you'll use McASP0 or McASP1 to drive the DAC/ADC. Their clock is derived from either CLK_M_OSC (the oscillator output, so no PLL) or CORE_CLKOUTM4/2 aka L3S_CLK (see page 4549, also confirmed by table Table 8-23 page 1143). This clock is itself derived from ADPLLS (see page 1141), not ADPLLLJ. ADPLLLJ feeds some other perpherals (see page 1144).