Is it possible to have a register with multiple drivers?
Simple answer, no.



Longer answer, ask yourself the following question


How would you connect multiple outputs to the same input in a logic circuit?


You need some form of signal combiner. That combiner is an N:1 multiplexer.

You can sometimes simplify the multiplexer if you can guarantee certain things about the incoming signals. For example if you know that the signals will always be zero unless they are the one writing, then you could use a simple OR gate. However synthesis tools are usually pretty good at making this optimisation themselves.

If this is for an FPGA, then the registers are built in logic slices usually containing some form of lookup table (LUT). It's that LUT that is used to combine the signals - configuring that LUT as a simple 2:1 multiplexer (assuming a >= 3bit LUT) uses up no more resources than a simple OR gate. So trying to optimise manually just results in harder to read code for no benefit, and increases the likelihood of mistakes.