Can signals be used directly in conditional statements in lieu of comparison to 0/1?
Signals of type Boolean : yes of course.
And you can happily use boolean types for synthesis, making life simpler, especially in internal signals, cases where 'Z' and 'X' etc cannot happen.
Signals of type std_logic : yes in VHDL-2008 mode.
It's one of the additions I least like in VHDL-2008 because it implicitly equates '1' and TRUE, and '0' and FALSE. If this is combined with negative logic or active-low signals (as are often used  for resets, RESET_N, imposed by external requirements) the result is an atrocious mess like
if RESET_N then 
  -- non-reset case
else
  -- reset case
end if;

Even worse, sometimes the signal is active low but named RESET.
In such cases, please PLEASE please write out if RESET_N = '0' then longhand...
In other cases, use judgment whether the shorter implicit version, or the longer explicit version, will make more sense to the next guy. Both have their uses.