Arbiter Physical unclonable function
To my understanding the arbiter PUFs exploit delay differences between the two paths being switched. 

It's likely the synthesis tools you are using don't really take delays into account in early synthesis, so it may only see two identical wires/paths going to both D and CLK of your DFF, which may mean the whole thing gets optimized out. Why wouldn't it, when "logically" with 0-delay model it's all the same no matter what the inputs are.

Sadly I can't provide a simple, all-environments-encompassing solution to this. I guess you should read the manuals to your synthesis tools if there is any way to make it care about the delays.

It seems that designing these on an FPGA without a massive bias in the results is quite challenging. I have done a quick search noticing there are some papers on specifically designing FPGA-based APUFs, however. You might want to take a look at those.

I wasn't previously aware of such things (PUFs), so I thank you for introducing these to me.



A side note about your coding style.


Please use human-readable names, like top, bot/bottom, challenge instead of your t, b, a; especially when you expect others to read your code.
You might want to make this design generic. Some PUF designs I saw can be as long as 512 switches, if not more. You could easily make both top/bottom signals N-bits long, and use a for-generate construct. Also, it may be nice to implement the crossover switches as one module instead of using two muxes per. I believe it would improve the readability a good amount.