Pipelined Radix-2 DIF FFT SDF Architecture
You are absolutely right, the upper half of each stage doesn't require multiplication. However, the way to implement "no multiplication" is not describe in your schematic.

As I understand it, data is serialized in and out of each stage, which is hinted by the comment that multipliers are at 50% utilization.

It seems dubious that you would reuse these multipliers for anything else. In that case, I would think it makes more sense to multiply by 1 the upper half than add a mux with matching delays.