How does SDRAM refresh interact with ECC
For starters, SDRAM Refresh does not technically move the data outside of the chip.  At an academic level it is reading the data and writing the data back, but the SDRAM Data pins does not see that data-- it is done internally to the SDRAM chip itself.  The SDRAM controller tells the SDRAM to do the refresh, but that is all that is seen externally.

ECC is done outside the SDRAM chip, in the SDRAM controller (usually located inside the CPU or chipset).  There are also many different SDRAM controllers that support ECC, so it is hard to make general statements that are always correct.  But I'll give it a shot.

When a memory location is read, and the data is corrupted but correctable, the corrected data is usually written back to RAM.  

Some ECC controllers will use "inactive" time to read every memory location and, if there is a correctable error, write the corrected data back.  The idea here is that this prevents a single bit error that is correctable from turning into an uncorrectable multi-bit error due to further "bit rot".  There is a term for this feature that I am forgetting at this moment.

Reading every memory location is a nice idea, but on more modern computers this cannot be relied upon for effectively refreshing the SDRAM.  Modern machines have a lot of memory and it takes a lot of time to read it.  The built in refresh of the SDRAM chips works quite well.  And doing this takes away valuable memory bandwidth from the CPU.  

It is much better to just use the normal refresh, and then scan memory for errors in a low-priority task.