Reading the program off a FPGA
The bitstream that controls the functionality of your FPGA is normally called the "configuration", not the "software". The configuration bitstream is generated by using FPGA synthesis tools to compile the Verilog/VHDL source code.

There are a number of different ways that the configuration can be transferred into the FPGA each time it "boots up". Roughly, they are:


The configuration can be loaded directly by the development system via the JTAG interface.
The configuration can be auto-loaded by the FPGA itself from an attached EEPROM device. The EEPROM device is itself often programmed via the JTAG interface as well.
The configuration can be loaded by your server's CPU from a disk file.


If an attacker gets control of your server's CPU, then obviously he can read the disk file if the third setup is being used.

If the server's CPU has a direct connection to the FPGA's JTAG interface, then the attacker could read the FPGA configuration either directly from the FPGA, or indirectly by reading the EEPROM device.

In a security-sensitive application, you'll want to use the second setup, with the FPGA reading the configuration from EEPROM, and you'll want to make sure the server CPU does not have access to the FPGA/EEPROM JTAG port. Obviously, you won't store any of the FPGA Verilog/VHDL source code on the server, either.