Timing violations in interfacing Flash with MSP430 using SPI interface
In general, it is believe these are the times one needs to concern them selves with as the speed of the SPI bus increases. If you do not operate the SPI bus at its upper limit, you shouldn't have to worry about these times.

A labeled timing diagram for each part would help.  

But, guessing, the Data In Hold Time is likely the minimum amount of time necessary for the MOSI data to be stable for the flash to latch it.The SIMO (aka MOSI) Output Data Hold Time is likely (as you stated) the point where master changes the data relative to the next master clock change.  The point here may be that if the  master clock period is less than 8ns + 3ns = 11ns, it may not be long enough for the slave to latch the data dependably.  That is to say, the master may change the data too fast for the slave.

Going on, the slave's Clock Low To Output Valid time is maximum 7ns.  And the master's SOMI (aka MISO) Input Data Setup Time is minimum 25ns.  This may be a bit tricky.  It could be that the master is ready to latch in the data 25ns after the master has change the clock output.  Or it could be that we need to wait 25ns after we are assured the slave's data output is correct.  In which case we need to wait 7ns + 25ns = 32ns before we are assured we can successfully latch in the MISO data.

Using just these constraints, as there might be others which need to be considered, we have a maximum SPI bus clock of about 15MHz.  Unless you need to transfer large amounts of data, this speed appears higher than most designers would use.