Sharing data in two different always @(posedge ...) blocks
To do this in an FPGA, the usual way would be to introduce a new clock, running much faster than A or B. Clock your logic from this new clock and use A and B only as control signals, not as clocks.

The new clock must be fast enough to be guaranteed to have at least one edge for each change of value of the A and B inputs.

module weird_counter(A, B, CLK, Q);
input A, B;
input CLK;
output Q;

reg [2:0] Ad;  
reg [2:0] Bd; /* Delayed copies of A and B */
reg [5:0] ctr;
reg [5:0] obuf;

assign Q = obuf[5];

always @(posedge CLK) begin
    Ad &lt;= {Ad[1:0], A};
    Bd &lt;= {Bd[1:0], B};

always @(posedge CLK) begin
    if(Ad[1] &amp; ~Ad[2]) begin /* We are seeing a rising edge on A */
         /* Do something with ctr and obuf*/
    end
    if(Bd[1] &amp; ~Bd[2]) begin /*Rising edge on B */
         /* Do something else with ctr and obuf*/
    end
end

endmodule;


Edit: Added some stages to Ad and Bd at Tom Carpenter's suggestion to demonstrate syncronizing a signal across clock boundaries. This reduces the risk of a logic fault due to violating set-up and hold times.