Error in op-amp integrator due to delay in attaining second summing point constraint
Are there any noticeable consequences of this delay when dealing with
  signals that change so fast, that the inputs aren't even at 0V?


This happens a lot and "the delay" is due, in main, to the open loop gain characteristic of the op-amp. Here's a "generic" op-amp curve courtesy of the internet: -



At DC the open loop gain is (say) 100 dB (100,000). This means that for a 1V output there is a real discrepancy between inverting and non-inverting inputs of 10 uV. Not much of course and usually a lot less than other errors.

At 1 kHz the gain has dropped to 60 dB (1,000) and for a 1V RMS sinewave on the output there is a very real input discrepancy of 1 mV RMS. It gets worse as you go up in frequency. For instance at 100 kHz the gain is 20 dB (10) and for 1 V RMS on the output the input discrepancy is 0.1 V RMS.

These are all "open-loop" figures and represent one of the many nuances exhibited by real op-amps in the real world.

The "closed-loop" consequences can be: -


Lower gain than a simple analysis would predict
Distortion of the output compared to the input (linear amplifier)
General harmonic distortion i.e. not getting predictable signal output results (i.e. in an integrator
Instability when the loop is closed (sometimes)