Traffic Light Verilog Code
Please use this code in simulation, i modified your code to a 3 always block style , ped_passed is not assigned to 1 in any state in the below code please try it at your end.SNUG paper ref

   `timescale 1ns / 1ps
    module pedestrian_st(
    input            clk, rst, ped_detected,
    output reg       ped_passed = 0, green, yellow, red,
    output reg [1:0] current_state
    );

    reg [1:0] next_state;

    parameter   GREEN_ST  = 2'b00,
                YELLOW_ST = 2'b01,
                RED_ST    = 2'b10,

    reg[2:0] count = 0;

        always @(posedge clk)
            if (rst)current_state &lt;= #1 RED_ST;     //SC has the green light priority
            else    current_state &lt;= #1 next_state; //put it in this state for now

        always@* begin
                next_state = 2'bx;
           case(current_state)
               RED_ST    : next_state = ped_detected ? GREEN_ST : RED_ST   ;
               GREEN_ST  : next_state = (count &lt; 6)  ? GREEN_ST : YELLOW_ST;
               YELLOW_ST : next_state = (count &lt; 3)  ? YELLOW_ST: RED_ST   ;
                default  : next_state = 2'bx;
           endcase
        end

        always @(posedge clk)
          case(next_state)
            GREEN_ST  : count &lt;= #1 (count &lt; 6)  ? count + 1'b1 : 3'b0 ;
            YELLOW_ST : count &lt;= #1 (count &lt; 3)  ? count + 1'b1 : 3'b0 ;
            default   : count &lt;= #1 3'b0;
          endcase

        always @(posedge clk)begin
                  red    &lt;= #1 1'b0;
                 green   &lt;= #1 1'b0;
                 yellow  &lt;= #1 1'b0;
              ped_passed &lt;= #1 1'b0;
          case(next_state)
            RED_ST    :    red   &lt;= #1 1'b1;
            GREEN_ST  :   green  &lt;= #1 1'b1;
            YELLOW_ST :   yellow &lt;= #1 1'b1;
          endcase
         end

     endmodule