Why old PMOS/NMOS logic needed multiple voltages?
Here's an example of a "depletion-mode" NMOS NAND gate circuit I found on (German) Wikipedia:



The upper transistor is used in depletion mode to provide a load approximating a current source and balancing the rise and fall times. Due to the higher threshold voltages of early MOS technology, a 12 V supply may have been needed to provide a proper bias for the gate of the load resistor. The -5 V supply might have been used to bias the back-gates (or substrate nodes) of all the FETs in order to get them in the desired operating regime.

I'm making this a Wiki answer because some of what I've said is speculation rather than hard facts and I'm sure someone here can improve or correct me.