My RTL viewer replaces NAND gates with AND gates with the inversion bubbles
While you can build everything from NAND Gates - these are the most universal - and I guess that is why you want to see em, NAND Gates are not the lowest reduction level of a boolean equation. And this is what your tool will do - it reduces the boolean equation to a optimal point prior to synthesis.
The Goal is to replace the found solution with FPGA LUTS and glue logic or optimized gates of a library of a factory like TSMC... the least thing you want to have is all NAND gates here