What benefits we have in reduction in clock cycles
At first approximation, yes, reducing the run time between power-down periods from 1000 cycles to 500 cycles will cut the overall power drawn by half.

Upon closer look, there are various reasons the power reduction might not be exactly half, but the power will still be reduced significantly.  For example, the CPU probably doesn't draw the same average current for every instruction, the sleep power isn't completely zero, etc.

When writing microcontroller code for battery-operated devices, it is often useful to optimize for the least instruction cycles, for the reason you state.  This may mean using more program memory and the like.  Remember that memory usage only matters if you run out.  Techniques like unrolling often-used critical loops, and carefully hand-crafting critical routines in assembler can all make a difference.  However, your overall firmware architecture will probably make the biggest difference.  This includes decisions like what to do in interrupts routines, whether to use a main event loop architecture as apposed to a cooperative task scheduler, etc.