Creating a clock multiplier using a PLL
The normal method for using PLL to multiply frequency is analogous to the normal method of using an op-amp to multiply the voltage of a high-impedance signal: the non-inverting input is fed the input signal directly; the inverting input is fed a scaled-down version of the output.  The op amp will vary its output voltage as necessary to make the two inputs equal.

Likewise, when a PLL is used for frequency multiplication, the "non-inverting" input will be fed from the reference signal, and the "inverting" input will be fed from a divided-down version of the oscillator's output.  The oscillator will attempt to vary its output frequency and phase as needed to make the frequency and phase of its two inputs be equal.  Suppose, for example, the "inverting" input is driven by a divide-by-four circuit.  Since the oscillator will have to output a frequency four times that of the reference input to make the frequency of the control inputs equal, that's what it will do.