how to isolate coupled noise source in parasitic capacitance in high voltage pcb design?
Parasitic capacitance is created whenever there are two conductors. The capacitance can be estimated with capacitance calculators. Parasitic capacitance values on PCB's typically exist in the pF range for traces and planes. Large plane to plane capacitance can be in the 100pF range (a 1000mm^2 has roughly 150pF of capacitance between planes).

Usually plane to plane capacitance can be used to your advantage in low voltage sections of a PCB. A ground plane can act like a bypass capacitor (with values of a few pF) which will cut out very high frequencies. 

If you don't want these capacitave effects, then don't place traces or planes adjacent to each other. You wont' be able to eliminate capacitance entirely, but it is easy to make the values negligible.

You probably already know this already but I'll include it for anyone else with the same question:

With high voltage you need to consider creepage and clearance between traces, and at 10kV also the breakdown dielectric voltage of PCB. High voltage can arc between traces, so proper distance needs to be placed between them. Here is a calculator for distance.


  Source: http://www.smpspowersupply.com/ipc2221pcbclearance.html

It might be wise to build the board out of something other than FR4 with such high voltages on the board. Follow the guidelines here