Using .lib module in a Verilog source code
The .lib file is a timing model library file described in a Synopsys propietary language interpreted by Synopsys STA tool PrimeTime. You won't be able to use it to synthesize a design, you must use a .db file, which is a Synopsys proprietary binary format to describe library cells like your memory.

Check out the options of your memory generator software to write out a library file (not timing library file) in .db format.