Different implementations of JK flip flop
First part of an answer, there are still open ends...



Found by experimenting with the mentioned logic simulator, but can be obtained by thinking, too.

The table of the AND NOR flip flop seems wrong to me.


When both S and R are 0 it's the same case as when CLK is 0 due to the ANDs. Therefore it can't be forbidden.
There is a forbidden state change if S and R are both 1 and CLK changes from 1 to 0. The circuit starts to oscillate, therefore this must be forbidden. This is the same as for the other flip flop.


It should be equal to the table of the NAND NAND flip flop concerning the actions. But when both S and R are 1 and CLK is 1, the flip flops produce different values. The NAND NAND FF sets both Q and Q' on 1, the AND NOR FF sets both on 0.

You can use transformations from NAND to NOR to see why this has to be like this.



Using a pulse detector is a difficult thing, not to say dangerous. You can't be sure that the generated pulse is wide enough to meet the setup conditions for the following gates.

As I learned edge-triggered flip flops in the real world are built from two level-triggered flip flops with complementary level sensitivity. This is called "master-slave".



Lesson learned: Not every web site that looks instructive fulfils its promises.