Analysis of two D flip-flop designs based on D latches
The timing constraints for the D Flip-Flop constructed using D latches to work are:
\$t_{ccq(initiator)} &gt;= t_{hold(follower)}\$
\$t_{ccq(initiator)}\$ represents the clock-to-q contamination delay of the initiator latch.
\$t_{hold(follower)}\$ time is the hold time of the follower latch.
Dummy logic (such as 2 inverters in series) could be inserted at the output of the initiator to meet the timing requirement.

The timing constraints for the first circuit to work are:
\$t_{ccq(initiator)} + t_{cd(inverter)} &gt;= t_{hold(follower)}\$

The timing constraints for the second circuit to work are:
\$t_{ccq(initiator)} &gt;= t_{cd(inverter)} + t_{hold(follower)}\$



D Flip-Flop using latch with positive enable

Simulate this circuit on Multisim Live: D Flip-Flop using latch with positive enable

D Flip-Flop using latch with negative enable

Simulate this circuit on Multisim Live: D Flip-Flop using latch with negative enable


Further reading
This video of MIT's OCW Free online course on Computation Structures.