How is a LUT in an FPGA configured?
The LUT is loaded with data with the internal configuration logic. Extra logic inside the FPGA (hard logic, not LUTs) reads the configuration bitstream (sof or bit file) from an external flash chip or from the JTAG interface and then stores it into the correct locations inside the FPGA. This includes LUTs, block RAM, clock management components (PLL, DCM, MMCM, etc), and the routing matrix. This configuration routine is triggered after any reset of the entire FPGA (i.e. Xilinx PROGRAM_B or Altera nCONFIG) and can load the bitstream from a number of different sources including JTAG, SPI or parallel flash chips, a microcontroller or microprocessor, another FPGA or CPLD, etc.

The routing matrix is what interconnects the reconfigurable components inside the FPGA. It consists of horizontal and vertical wires of various lengths and interconnecting switches. Closing the correct switches allows signals to be routed around the FPGA between the various components. Dedicated clock distribution networks also exist to distribute high speed, high fanout clock and reset signals.

I would highly recommend looking at an FPGA datasheet to get a feel for how these components are implemented on a commercial FPGA.  Both Xilinx and Altera have quite a bit of documentation on the specifics of the routing network and construction of the logic elements.