Execute module one after another using flag status
In Verilog, things don't execute one after the other, they execute in parallel.  If you want to feed the results of one module into the inputs of another (ie a pipeline) then you just create the wires and connect them to the appropriate inputs and outputs.

I'm not even a reasonable Verilogger, so I can't see immediately what your problem is, but it might help to use named associated rather than positional association to do the wiring as its easier to see mistakes in port ordering that way.