20MHz clock signal over several PCBs
Is this even possible with a 20MHz clock signal without using a buffer
  on each board?


It all depends on the drive-strength of the clock source, how many milli-Amperes can it source? You can approximate the trace resistance using:


trace width and copper thickness on the PCBs
wire gauge on cable


and figure out the DC loss at the end of the chain.
That should give you a good idea of what voltage level (from the original 3.3V) you'll get on the input of the last LED driver.

If the voltage swing is not sufficient, you may want to add a buffer mid-trace.
Do you need all LED boards to be identical? In this case, you could implement the buffer circuit and add a 0-Ohm bypass resistor. For 9 of your PCBs, the 0-Ohm would be loaded and the buffer circuit unloaded. For the last, the 0-Ohm resistor would be unloaded and the buffer circuit loaded.


  Will I run into EMI issues even if I route the clock signal carefully
  (e.g. applied best-practice PCB design rules for routing clocks)?


Generally, a swinging 3.3V signal at this frequency going over such a length is an EMI concern.
I don't believe your setup will act as an antenna for the main frequency (wavelength is 15 meters for 20MHz signal) but it could well be for harmonics of the signal.

There are a few things you could implement to anticipate EMI mitigation:


software control over the clock source drive-strength: you could try to find the lowest drive-strength setting still meeting the waveform requirements for all LED driver's inputs. The lower the current, the lower the EMI. The slower the signal edges, the lower the EMI
hardware control over the clock source drive-strength: if you don't have software control, you may want to add an RC circuit next to the clock source pin, load it with a 0-Ohm resistor and leave the capacitor footprint open. You can use this circuit to control the current and shape of the source waveform and perform the same EMI improvement as described above. The capacitor can help with rounding corners of the edges of the waveform, helping to reduce the harmonics of the signals
add termination resistor near each LED drive input: the LED driver input is high-impedance so to avoid reflection and any other side-effect, you could size the resistor value to match the line impedance
if you have the option of sandwiching the clock signal between 2 ground planes and using shielded or semi-shielded cable, this could help with blocking the magnetic field therefore potentially help lower EMI.




EDIT: ESP32 module drive-strength information 

On page 44 of the ESP32's datasheet, you'll find this note:


Your clock trace has a certain resistance value (but very tiny) and is capacitively coupled to your ground plane. The ESP32 pin, the connector contacts, LED driver inputs, etc. all have parasitic capacitances. Now, if you simplify, imagine the clock trace being a simple RC circuit. The more current you can push into it, the faster the capacitor will charge. In other words, the more current you push into your clock trace, the faster it will rise to 3.3V. Same for discharge, the faster you can sink current, the faster your clock signal will fall/discharge to ground.

What that table tells you is that you can control the current you can push (source) and sink for each I/O pin. I did not verify if the PWM output you are using for your clock signal does have this feature, however, I'm sure you can find this out yourself :)

Now let's say the drive-strength control is missing from your PWM pin, what I was suggesting you can do is add a parallel capacitor, as increasing the capacitance of your trace will result in slower charge/discharge and therefore slower edges (eg. improved EMI).

Again, be sure to meet the timing requirements for all the LED driver inputs when lowering drive-strength or adding an external capacitor, if the edges are too slow the drivers won't work as expected.