i2c on different logic level devices
I see valid start and restart conditions in your waveform, so I don't think SDA is the 'wrong polarity'. The valid start condition is there before writing 0xC0 (indicated by the first green dot in the capture) and the valid restart is the second green dot (before 0xC1). The fact that SDA stays low after the master ACKs the slave shouldn't be an issue as long as the master releases it before the next rising edge of SCL.

One issue could be the size of the pull-ups. If you're trying to operate faster than 100kHz, you may need stiffer pull-ups to ensure the edges are sharp.

Another issue is that the master should NACK the last expected read byte, even if it is valid data, since many slaves expect a NACK before they will allow a valid stop condition to come through. For your single-byte reads, the master should NACK the data byte. For the 16-bit registers, it should ACK the first byte and NACK the second one. I've seen quite a few slave devices hang the bus or malfunction if the last read isn't 'terminated' by a NACK.