Component Instantiations in VHDL
When creating components in VHDL and instantiating them in a source file, does it matter if component have outputs that have the same name.


For example component A has an output called Out_1 and component B has an output also called Out_1. They are nested in source files in a way that when I instantiate components A and B, I am assigning output values Out_1 =&gt; Out_1.

No problems, but it should be different than the port name so it doesn't get confusing. There is a distinction between signals names and port names.
The port names must be the same though for each instance of the same component (obviously).
If you try to assign the same signal to two output ports you will get a multi-drive error.

Now when I simulate in a test bench, the signals are orange and uninitialized. Is this something that should be avoided?

It's a good idea to initialize but I think sometimes you can get away with not initializing intermediary signals since they get affected by initialized signals further upstream.