Nonblocking simultaneous assignments to wires and registers in Verilog
//Not synthesizable because of #delays can not be translated to something that is mapping wires.

reg clk ; //Rising edge every 10 timesteps
initial begin
  clk = 0;
  #5;
  forever begin
    #5 ;
    clk = ~clk;
  end
end


//Synthesizable because I have avoided use of a delay

reg [31:0] counter;
always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    counter &lt;= 32'b0; // &lt;-- reset value! assigned on negedge of reset
  else
    counter &lt;= counter + 1;


always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    c &lt;= 1'b0;
    d &lt;= 1'b0;
    e &lt;= 1'b0;
  end
  else if (counter == 10) begin
    c &lt;=  (a+b);
    d &lt;=   a;
    e &lt;=   b;
    end
  end
endmodule