Finding Rise time and Fall time with Slew Rate Specification
The clock input rise and fall times are the minimum required for the device to properly respond, so whatever is driving this pin must provide at least that transition rate. A faster rate would be quite acceptable.

The note states 84. Full VCC range and CL = 30 pF. This means that the full transition must occur (for 0 to 3.3V or vice versa) in a time equal to or less than 33nsec but this is for proper internal operation and does not consider data rates.

At 48MHz, each bit is 20.83 nsec, but this is not a contradiction - clearly the clock pin needs to be driven faster than the minimum required to achieve this data rate which is what your scope picture shows (almost sinusoidal with full rise and fall each taking about 10 nsec - i.e. your clock transition rate is faster than the minimum required).

Your clock is, therefore, within the limits imposed by the manufacturer.

it is not at all unusual to require minimum transition rates on inputs to CMOS devices (slow transitions can damage the device). This application note goes into some detail.

You can get a lot more insight into the device (particularly the data drive) from the IBIS model. The SCK input has the model name [Model]  F_SCK