Pulling down positive voltage to limit negative voltage current
Figure 1. Original circuit.



simulate this circuit &ndash; Schematic created using CircuitLab
Figure 2. Simplified circuit. OA2 has been removed because it is only a unity gain buffer so it has no effect in this analysis.

OA1 is configured for negative feedback. If all goes well it will settle down with NODE2 very close to 0 V (which has been applied to the non-inverting input. With the R5/R4 ratio applied the U1 output voltage should be \$ V_- = -\frac {R_4}{R_5} V_+ = -\frac {10k}{1k} V_+ = -10V_+ \$.

See if that helps your understanding before going back to the original problem.