Outputting a clock signal from an FPGA
You can use any GPIO pin you want for output. It doesn't matter if it's balanced clock or arbitrary data.

Also, output at units of MHz shouldn't give you any trouble. 



In sequential logic, there is a trend to use as little of clocks as possible. This is because clocks are very often the most important signals, as many others depend on them.

I'll try to depict here the issue of propagation delay, as projected to the thing called clock skew. Imagine you have two clocks, one derived from the other:

__/--\__/--\__/--\__/--     &lt;- original clock
___/-----\_____/-----\      &lt;- clock divided by 2


Note that the clock below is delayed by 1 character (that would be one flip-flop delay, which is minuscule.) It's just greatly exaggerated in the ASCII art.

But, in a black-boxed FPGA design you don't have to worry about that. It's all taken care of for you. All those worst-case timing issues are taken into account in the form of maximum clock frequency, that the design can run at.