CD4015BC static shift register: technical specs question
The clock rise and fall times are due to (probably) 2 specific requirements.


This is a CMOS device, and slow inputs on these devices cause significant self-heating due to the input stage conducting in class A while the input is in the indeterminate region. It is normal to see a maximum rise and fall time for CMOS devices.
The clock input on the latch probably needs a transition no slower than this to attain properly deterministic operation.


Setup time. This is the amount of time that a data input must remain stable in a valid state (either high or low) before a clock transition. If this time is not met, the contents of the register will be indeterminate.

A decent reference for this may be found here

Output current. This is the maximum and minimum current available, and is defined by the resistance of the output stage. The load resistance you may use is defined by this, not the other way around.

Without a proper schematic, I cannot comment on why all the bits eventually become zero.