Vref value and Vref shunt ICs for an ADC
Let us talk about achieving a clean VREF (this example also applies to your analog Vin), in the presence of interferers.

First, we'll do math for (A) magnetic interferers, then (B) power supply interferers, then (C) Electric Field interferers from your MCU, finally (D) the effect of Ground currents. 

(A) Suppose your VREF (or Vin) has no ground plane, because you heard planes are not needed at low frequencies, and a VREF is DC.

Suppose there is 1cm by 4cm loop of PCB traces, between your VREF CIRCUIT and the ADC. In other words, the VREF trace is located 1cm away from the GND trace.

Suppose 4cm away is power wiring to the Power Supply of your system. Suppose youe system draws 10 watts (0.1 A from 117 Vac), and the rectifiers have 10X that as peak current, with 1us risetime thru the diodes. Thus your dI/dT will be 1 A / 1 micro_second.

How much trash is coupled into the VREF traces?

Lets used the formula(*)

Vinduce = 2e-7 Henry/meter * (Area / Distance) * di/dT

[if this induced trash is less than 1uv, then we can ignore this source of error.]

Vinduce = [2e-7 * (1cm * 4cm) / 4cm] * 1 A/1 us

Vinduce = 2e-7 * 0.01 * 1e+6

Vinduce = 2e-7 * 1e-2 * 1e+6 

Vinduce = 2 * 10^(-7 -2 +6) = 2 * 10^-3 = 2 mV

Thus the computed interference is 2,000X larger than our "Not a problem" threshold. 

Thus there is a problem, given the assumptions stated.

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What if you use a Ground plane? will not do much good, for pulses slower than 4 MHz  (100 nanoseconds TRise).

You will need thick copper (expensive) or thick aluminum or some steel sheets.

Ever wonder why high-precision equipment is HEAVY? Partly because of the need to SHIELD the circuitry.

(*) the base formula for magnetic coupling between a long straight wire carrying a current with some "dI/dT", into a co-planar rectangular loop of some Area and separated by Distance from the wire, is

Vinduce = [ MUo * MUr * Area/(2 * PI * Distance) ] * dI/dT

Given MUr = 1 for air and FR-4 and copper and aluminum, and MUo = 4 * pi * 1e-7,
the formula simplifies to what we use.

For complete accuracy, you can write the integral and find the effect of Natural_Log on the final result. The formula we use has the Distance being the shortest distance between the WIRE and the LOOP, thus overestimates the Vinduce.

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regarding mechanical design: placing such circuitry anywhere near high_current power cables is asking for trouble. Dishwasher motor spikes, microwave_oven rectifier spikes, airconditioner compressor spikes all ride atop the 60Hertz current waveforms.

The mechanical configuration in this math assumes the Reference IC is located 4cm away from the ADC.

(B) regarding Power Supply trash: the 24-bit ADC has 6 * 24 == 144 dB range of resolution, but only 78dB Power Supply Rejection Ratio (PSRR) at 56/60Hertz, already down over 20dB from the DC PSRR spec. Thus we'll assume the ADC is operating on a 10:1 drop in PSRR for 10:1 increase in VDD trash frequency. At 500,000 Hertz (2uS ringing, well below Switch Reg trash), the ADC likely will have ZERO ability to reject trash. ITS YOUR JOB to REMOVE THIS TRASH

LDOs cannot remove high frequency trash; their internal servo-loops cannot function fast enough, even if you spend the Iddq budget and buy a high-current LDO. YOU MUST FILTER THE RAW Power Rail BEFORE THE LDO 

For filtering, a Ferrite Bead does nothing. Use a discrete resistor and a discrete capacitor, in the voltage into the LDO. I suggest 100 ohms and 100uF, for a 10 millisecond time constant and 16Hz F3dB. And follow that with 10 ohms and 10uF, (because the first R+C will be limited in far-out attenuation by the ratio of 100 ohms and the ESR+ESL of the 100uf cap). This 2nd R+C has 100uS time constant, or 1,600Hz F3dB, and should provide 60 dB attenuation at 1MHz (about where Switch Reg L+C ringing will occur).

Is this much VDD filtering (all before the LDO), necessary? Perhaps not, because the ADS131 24-bit ADC has 5 microvolt RMS noise anyway.

(C) Electric Field interference

(D) Ground trash (or we could make this thermo-electric errors from temperature changes in the PCB, causing low frequency drift of offset.