verilog: binary code decimal and gray code counter implementation
I think you don't use FSM, instead make simple code like bellow,

module grayBCDcounter(
  input clk, rst_n, control,
  output wire [2:0] y1 
);

reg  [2:0] bcd_cnt, gray_cnt, cnt;

always @ (posedge clk or negedge rst_n)
begin
  if (!rst_n) begin
    bcd_cnt  &lt;= 3'b0;
    cnt      &lt;= 3'b0;
    gray_cnt &lt;= 3'b0;
  end else begin
    bcd_cnt  &lt;= (bcd_cnt + 1'd1) &amp; {3{control}};
    cnt      &lt;= (cnt + 1'd1) &amp; {3{!control}};
    gray_cnt &lt;= cnt ^ (cnt &gt;&gt; 1);
  end
end

assign y1 = control ? bcd_cnt : gray_cnt;

endmodule


Try it.