"Unresolved reference to 'countmode1'" , Verilog simulation error
As @Greg pointed out, you are passing more number of arguments to tasks than required.

Also, including a file doesn't mean having access to all the tasks and functions inside the module. You have to instantiate the module inside your main a8bitCounter module as follows:

// `include "countmode_1.v" // include this file outside module will be good.
module a8bitCounter(inp[7:0], ocrn, counter[7:0]);
// ...
// ...
`include "countmode_1.v" // including here is not a common practice
countmode c1(); // instantiate the module
// ...
// ...
c1.countmode1(); // note the hierarchy path to the task
c1.countmode2(); // note the hierarchy path to the task
c1.countmode2(); // note the hierarchy path to the task
// ...
// ...
endmodule


If your countmode module is not required, then remove it and after that, the tasks shall be declared in global compilation unit scope. By, this you can directly use task names while invoking them (no need of hierarchy then,since they'll be in global scope). However, you must provide some input/output arguments to these tasks.

For more information on instantiating module in verilog, refer to this link. Tasks/functions in verilog can be found in this PDF.