JK Flip-Flop 0-9 up/down counter
What did you try?
It is very easy to design a JK synchronous circuit. In fact just draw the table giving the state Qn of each JK representing a bit and its transition on each clock like the following:

and then fill the corresponding JK as follows:

A transition from 0 to 0 is either a reset or a maintain: J=0, K=x
A transition from 0 to 1 is either a set or a toggle: J=1, K=x
A transition from 1 to 0 is either a reset or a toggle: J=x, K=1
A transition from 1 to 1 is either a set or a maintain: J=x, K=0

Where x is a don't care.
At the end, having the truth table of each Jn and Kn depending on all Qn you can simplify the expression and get the circuit of each Jn and Kn using logical gates.
In your case, include the U/D (up or down) input in the logic.