Veriog:How to pass a register to a module?
Your conclusion is not correct. It doesn't matter to the hardware whether you use a reg or a wire, the issues you are discussing are part of the Verilog syntax.

The reason your design gets so much faster when you replace fooWire with a number is that your logic isn't really doing anything and it all gets optimized away. The assignment of fooWire to fooReg requires that signals actually propagate from one part of the chip to another, and that takes time. Changing the assignment of fooWire to fooWire+1 forces the tools to create a 32-bit adder and insert it in the delay path, so of course the design will get slower.

By the way, it's register, not registry.