Is my FPGA out of routing resources?
You can get a detailed report by doing a design analysis in Xilinx Vivado. 
Run the following command in the tcl console : "report_design_analysis" 
It gives you the timing, complexity and congestion report of the implemented design. You can also run this report via going to Tools->Report->Report Design_analysis.

In this report, you can see which areas are causing congestion due to placing. Which Slices are fully used or what is the rent of such slices and/or routes.

I hope this was of help.

Regards,
KWQ