Verilog code for frequency divider
Unfortunately, 16 bits is not enough to convert a 50MHz signal into a 50Hz signal. This is because you need to divide the clock by 1 million. $$2^{16}= 65536$$ Therefore it is not nearly enough. A counter with at least 20 bits would be enough because: $$2^{20} = 1048576$$

To convert the signal you simply count to 1 million clock cycles, and then change the state of the output signal. 

example:

always @(posedge clk_in) begin
   count_20 &lt;= count_20 + 1;
   if(count_20 == 1000000)
   begin
      count&lt;=0;
      clk_out &lt;= !clk_out;
   end
end


Edit:
It turns out that that ^^ would result in a 25Hz signal, so you only need to count to 500000 which needs 19 bits. The question then is where does that 20th bit come from seeing as you do need to divide by 1 million. Well, the clk_out bit serves as that 20th bit.