CPU clock cycles required to execute the following inx?
The definition of "2 cycles per memory access" is a little vague, so I'm not sure if it's 3 cycles or 4 cycles. But here's how I feel that it goes:

Note: to help thought process, it's assumed here that the databus is driven at the clock falling edge and read at the rising clock edge, although it's not necessary to do so. It's just to help you think how the data flows.

Cycle 1: SP->DATABUS on the falling edge

Cycle 2: DATABUS->MAR on the rising edge;
     SP-1 -> SP on the rising edge;
     r -> DATABUS on the falling edge;

Cycle 3: DATABUS->MDR on the rising edge;
     Memory access cycle begins

Cycle 4: Memory wait state (is it necessary or is the addressing cycle 2 enough to satisfy 2 cycle memory delay?)

[Edit] 
The answers sheet here says the correct answer is B (3) so I guess the separate cycles for MAR and MDR satisfy the two cycle memory access requirement.