Why do we ignore parasitic capacitance in dc analysis of transistors?
Parasitic capacitances do not allow any DC current to flow through them. These capacitances are generally in parallel (or a parallel-series combination) across a pair of terminals - for example between Source and Drain on a MOSFET.

Because they are in parallel there are two paths for the current to flow - through the parasitic element or directly through the device. At AC, some current will flow through the parasitic element, and some through the device (if the device conducts between those two terminals in the mode it is in).

At DC, no current will flow through parasitic capacitances, but some current can flow (in parallel) through the device. Again, this is only if the device conducts between those two terminals in the mode it is in.

If you post a diagram of the transistor model you are using with its parasitics labelled up I can better illustrate this for you.