high impedance in rtl verilog
Unless you are using SystemVerilog, you cant declare a constant like that. 

Instead use  the replication operator. {(WIDTH){1'bz}} is a WIDTH bit wise constant of all z's. Just replace the width with however wide you need (can be a parameter).



Furthermore, it should be register[n-1:0] not [n-1:0]register.



The following should work:

assign Data = (RD == 1'b1) ? register : {(n){1'bz}};