Does lexical analysis map well onto FPGAs?
Yes, it would work well. FPGAs contain wide, fast memories that make it easy to implement a state machine that could process one input symbol per clock.

But the question remains, does it make sense to do this in the context of the other things that need to happen when processing languages? CPUs with high speed clocks also execute table-driven state machines very efficiently, and they provide a better environment for implementing the higher-level parsing tasks.