Creating a verilog code for 4-bit multiplier using lookup table
There are two different ways the term "lookup table" are used in FPGA design that might be confusing you. 

First, the main building block of combinatorial logic in an FPGA is called a lookup table, but usually abbreviated as LUT. This is just a small RAM element that takes 4 or 5 or 6 inputs (depending on which type of FPGA you have) and uses that to select a bit from memory to be output. 

Second, more generally a lookup table is just logic that takes inputs and has a defined output for every combination of those inputs, just like a logic table you'd use for paper-and-pencil design. Since a hardware LUT in an FPGA isn't big enough to implement a 4-bit adder, this is probably the kind of lookup table that's meant in your problem.

In Verilog, a lookup table is usually implemented with a case statement. For example, to implement a 2-input XOR gate with a lookup table you might write,

reg out;
wire [1:0] in;
always @(in)
case(in)
    2'b00 : out = 0;
    2'b01 : out = 1;
    2'b10 : out = 1;
    2'b11 : out = 0;
endcase


For your 4-input multiplier, you will probably want to use bit concatenation to form the input bits:

wire [3:0] A;
wire [3:0] B;
...
case ({A, B})
    ...
endcase


And your case statement will have 256 lines in it.