What "bus turnaround" delay should my PSRAM have?
You do not seem to have linked to the correct document, as your linked document doesn't have a page 1250.  Nonetheless, I can guess the general nature of what is happening.  Generally, when an attempt is made to read a memory chip, the device performing the read will keep the read request active for an entire cycle.  The memory chip will continue to output data as long as its read request is active, and for a short amount of time thereafter.  If the next bus cycle is something other than a read of that memory chip, the memory chip may continue to output data during part of that next bus cycle.  This may cause bus contention, resulting in excess current draw, and may also prevent the device which should be driving the bus from doing so successfully.  Turnaround delays of various types are used to allow one device which is driving a bus to stop doing so before another device starts driving it.

I don't know whether the problem you're having with zero delay is caused by the above contention scenario in particular, since many systems have a number of situations in which contention could possibly occur.  The general principle is the same for many of them, however.