Forcing verilator to take loop label given in RTL
I don't think you can. In the manual, under "Language Limitations", it says:


  Dotted cross-hierarchy references
  
  Verilator supports dotted references to variables, functions and tasks
  in different modules. However, references into named blocks and
  function-local variables are not supported. The portion before the dot
  must have a constant value; for example a[2].b is acceptable, while
  a[x].b is not.
  
  References into generated and arrayed instances use the instance names
  specified in the Verilog standard; arrayed instances are named
  {cellName}[{instanceNumber}] in Verilog, which becomes
  {cellname}__BRA__{instanceNumber}__KET__ inside the generated C++
  code.
  
  Verilator creates numbered "genblk" when a begin: name is not
  specified around a block inside a generate statement. These numbers
  may differ between other simulators, but the Verilog specification
  does not allow users to use these names, so it should not matter.
  
  If you are having trouble determining where a dotted path goes wrong,
  note that Verilator will print a list of known scopes to help your
  debugging.