Finding Fmax in FPGA design without adding extra cycle
There are two ways to get the timing: 

1) Create a wrapper for the whole module, that registers the inputs and outputs and have the tools calculate Fmax of system+wrapper. Although I would consider it troublesome for an reusable IPcore to claim a high fmax and then find it unregistered and dumping a load of combinatorial logic either side on the user.

2) Mark the pins of your design as virtual pins. See e.g. Does setting pins as virtual affect timing? Here quartus analyses timing assuming your inputs feed from 'nearby' registers and outputs drive nearby rgeisters, which will let you get a decent timing estimate without being penalised to carry the IO signals all the way into perhiphery I/O pads (and save you writing timing constraints for the same).