Delaying all incoming signals by 2 ms using VHDL
Any time value is not synthesizable by an FPGA, because an FPGA is not aware of the concept "time". Actually no electronic circuit is aware of our concept of time. In computers and such specific libraries were developed to ease programming with time.

However, synchronous electronics -like an FPGA- are usually clocked: driven by an oscillator. This oscillator has a certain intrinsic period: the clock frequency. You can use this frequency to measure a certain time period. I.e. an oscillator of 50 MHz will have oscillated 100000 times in 2 ms.

If you want to delay a signal, you will need to introduce memory into the system, which holds the information for a specific period. In this case 100000 clock cycles. You have a number of options there, one being a column of 100000 n-bit registers. However, using separate FPGA registers is quite inefficient.

Another solutions would be to use a feature of FPGA's that has been introduced not so long ago: it is possible to use the LUTs (look-up tables) as shift registers. This is much more efficient then using separate registers. However, in the case of 100000 clock cycles, this is still likely not so inefficient.

You are in fact making a FIFO (first-in first-out) buffer with a fixed delay. Seeing the delay is on the larger side, it is quite common to use a dual-port RAM block in this case: on the A-side you write the input data in an infinite loop and on the B-side you read this data with an address offset of 100000.

after your edit:

Ok, so it seems you are trying to determine the time between two pulses. That is something different -and much simpler- then determining the time-shift of data. This is actually done a lot in radar and lidar etc applications. The component that does that is a Time-to-Digital converter. It simply determines the time between pulse 1 (start) and pulse 2 (stop), like a stopwatch does.

If you want to determine the time more accurately, i.e. with a sub-clock period interval, I suggest you look at the hybrid solution (i.e. the Nutt method). That one combines a simple counter with a vernier interpolator. A. Aloisio et al. have suggested a nice FPGA implementation in "FPGA Implementation of High-Resolution Time-to-Digital Converter" (I hope you have access to IEEE).