LDO datasheet parameter extraction
The pass element is a PMOS, so when it is fully ON, it will behave as a resistor RdsON whose value depends on temperature and Vgs. This is why dropout voltage graphs are all straight lines.

In dropout mode, when Vin is too low, the "opamp" in the internal schematic will be clipped, its output will be the lowest possible voltage (probably GND) to get the FET to turn on as much as possible. So the FET's Vgs is equal to the input supply voltage.

So the subtlety about dropout voltage in PMOS based LDOs is that it depends on the input voltage since that's what determines the available FET Vgs.

In dropout, the internal error amplifier is clipped, so dropout voltage has no relation to any characteristics of the internal amplifier, except its minimum output voltage. So your method of determining the gain of the error amp from dropout voltage cannot work. You'd have to use the output impedance of the LDO as a starting point instead.

In your model, dependent voltage source E1 is not a good model as its output voltage can go below ground, which is not possible in a real LDO. So it will turn the FET ON more than a real LDO would, which will result in incorrect dropout voltage.

If you want to get the FET's characteristics from dropout voltage, remove the error amp and connect its gate to ground, simulating a clipped error amp.