Memory-mapped I/O address ranges
Pure address decoding logic.

The upper bits of the address bus are routed through logic, usually including things like '3-to-8 decoder' and the like to create a selection of "chip select" signals that connect to the different devices to activate them at different address ranges.

So for your example, the upper 2 bits of address bus could be linked to a 2-to-4 decoder to give the ranges 0x0000 to 0x3FFF, 0x4000 to 0x7FFF, 0x8000 to 0xBFFF and 0xC000 to 0xFFFF

The lower 14 bits will all be connected direct to all the devices (or as many as they need up to 14)

Within those ranges you could further split it down if you desired to make a finer-grained range.