Clearing 4-bit asynchronus counter using T flip-flops doesn't work
That circuit is inherently unsafe, which shows again that you should be careful when watching YouTube videos. 

The reset is asserted if Q1 and Q3 are high.
But that same reset signal will go away as soon as either Q1 or Q3 is reset. 
The reset circuit is what we call combinatorial loop.

So in fact what you generate is a reset spike a pulse which is high only for the time the signal takes to go through the loop. That spike might be just long enough to reset all four register but it might not. The only thing is that it most likely will reset is Q1 or Q3.