ripple carry adder vs carry look ahead DELAY?
Implementing logic on an FPGA is not at all like stringing together AND and OR gates. The FPGA implements logic using look-up tables, and many FPGAs have dedicated logic and wiring to create fast adders. This means that the way you write your HDL can have a huge effect, either positive or negative, on the timing results.

Changing the number of inputs and outputs will also change the placement of logic on the FPGA, which can have subtle and unexpected effects.

In other words, it probably doesn't make sense to try to extrapolate from your gate-level circuits to actual implementation on an FPGA.