External pull-down resistors on Xilinx XC95144XL
The attribute FLOAT does not seem to be compatible with your specific CPLD family, see this. Here it says that

XC9500XL and XC9500XV devices have weak keeper circuits on all I/O pins to prevent them from floating. You can also configure all unused I/O pins as supplemental ground pins by enabling the Project Navigator property "Create Programmable GND Pins on Unused I/O" for the Fit (Implement Design) process. (The PULLUP and KEEPER attributes do not apply to XC9500-Series devices.)

There is another DS054 that sais on page 12 that:
When the device is not in valid user operation, the bus-hold
circuit defaults to an equivalent 50 kΩ pull-up resistor in
order to provide a known repeatable device state. This
occurs when the device is in the erased state, in programming
mode, in JTAG INTEST mode, or during initial
power-up. A pull-down resistor (1 kΩ) may be externally
added to any pin to override the default RBH resistance to
force a low state during power-up or any of these other
modes

So, I may not see the whole picture, but so far it seems like you are stuck with "week keeper circuits" and the default 50k pull up resistor. So, it is possible that your 47k resistor is not "strong" enough to dominate the internal one. Adding a 1k resistor may not be a good solution when you need to drive the pin.  

Do you have an option to add an external buffer/line driver?