How do SRAM bit line "gates" work?
The problem is that you have simplified your system too much, and now you're confusing yourself. There are two major problems, and a third that may be an issue. 

First, it is only useful to think of SRAM as a completely digital system when the data is being stored. When you write or read the bit cell, you have an analog circuit. 

Second, you only have a bit-cell, completely disconnected. You will get a different result with good models and a complete system. The bit-lines in your diagram (with the word-line low) are high-impedance nodes, meaning that something just needs to sneeze in its direction to change the voltage. However, there is nothing in your diagram that actually will change the bit-line voltage (so it stays the same).

Third, the Falstad simulator is a fun toy, but you aren't going to do IC design using it. The MOSFET model is too simplistic, and the solver method isn't accurate either. You won't be able to set a ratio of sizes between the transistors either.

Also, don't confuse "there's zero voltage across this transistor drain and source" with "this transistor is conducting". Your access transistors are probably working just fine.

As for 6T general design, you end up designing a circuit that doesn't change values during a read, but can still be written to. This is achieved by varying the drive strength of the six transistors and simulating it over various conditions to make sure the design is robust.