large inductance compensation methodology in chip power delivery network
Suppose our power delivery network from VDD to the chip has very high
impedance at certain frequency.

Then will likely be the root cause of likely power supply problems and this is what needs to be fixed. Fixing this can mean a series of distributed decoupling capacitors at each node where the chip's VDD pin is. It can also mean using proper ground planes for 0 volts.

i know that we cn use smith chart to design such network.

Well, you could use a smith chart but, these days, you'd use a simulator to mimic the disposition of Vdd and ground and see where the problem frequencies are. Fix with capacitance or increased/improved copper thicknesses and ground plane.

i'll be glad for a recomendation on methodology for these purposes.

Model the problematic power feed within a simulator. Simulators are good and free and will eat this problem up with ease.