STM32F4 pulse generator
With the addition of a little bit of hardware you can reduce the demands on the controller. The main problem (pointed out by Dave) is that the frequencies are not multiples so it is difficult to synchronize them. The hardware syncs the rising edge of the 3.5Mhz pulses to the (asynchronous) output from the uC. The chips can be TTL (7400 series) or CMOS (4000 series) 



The uC produces the 125uS signal (interrupt timer). The 3.5MHz signal could be produced by an external Xtal oscillator and is simply a train of pulses at that frequency. It could also be derived from the uC oscillator through dividers. 

The D type flip flop is positive edge triggered. When the output from uC is LOW the Q output of the flip flop is LOW. The AND gate output is also held LOW by the output pin of the uC (LOW). This means no pulses can get through the AND gate. 

When the uC output pin goes HIGH the Q output of the flip flop has to wait until the next rising edge of the 3.5MHz clock before going high. Only when all three inputs to the AND gate are HIGH will the pulse be  seen at the output of the gate. Because these signals are synchronized with the rising edge of the 3.5Mhz pulse the output will be a full length pulse.

The output from the AND gate is fed back to the uC which needs to detect TWO PULSES. On the falling edge of the second pulse it then resets the OUT pin to LOW which prevents any more pulses coming through the AND gate. 

With the addition of a little more electronics the whole thing could be done totally in hardware.

Metacode

Initialise  interrupt timer for 125uS

set output pin HIGH

check for first pulse going high --> low

check for second pulse going high --> low

Set output pin LOW