Maximum frequency for a FPGA-based square wave signal
You can't generate a frequency higher than the internal clock. If you have access to a Phase Locked Loop or PLL, you might be able to.

Usually the external clock gets fed into an PLL and the internal clock is generated from that.

If your internal clock is 125Mhz and your using a regular counter (counting on only the rising edge), the fastest counting you will see will be at half of 125Mhz or 62.5Mhz.

Counters can be built that work on the rising and falling edge to give you counting at 125Mhz