Can one instantiate RAM with 2 read ports and 1 write port as IP in Quartus?
There's a trick for doing this in Xilinx technologies : instantiate two memory blocks, with their Write ports tied together. (Each block is configured to have 1 read and 1 write port, independently addressable).

I can see no reason why the same pattern wouldn't work in Altera FPGAs. Last time I looked, their memory blocks had similar dual-port (just not 3-port!) capability.