VHDL 'buffer' vs. 'out'
One case, that probably doesn't apply, is if you're using a standard older than VHDL-2002. Before than, buffer could not connect directly to out. So in a hierarchical design, the signal path would need to be declared as a buffer on all levels. Also, when adhering to these older standards, some tools have problems synthesizing buffers correctly. They may or may not warn you about this.

These should no longer be an issue if you're using a newer standard. From the VHDL-2002 Standard:


  a) For a formal port of mode in, the associated actual must be a
  port of mode in, inout, or buffer.
  
  b) For a formal port of mode out, the associated actual must be a
  port of mode out, inout, or buffer.
  
  c) For a formal port of mode inout, the associated actual must be
  a port of mode inout, or buffer.
  
  d) For a formal port of mode buffer, the associated actual must be
  a port of mode out, inout, or buffer.
  
  e) For a formal port of mode linkage, the associated actual may be
  a port of any mode.


I also often see advice stating that a buffer should never be tri-stated. If you need the ability to tri-state a bus, then you would need to use out. I could find no direct reference to how buffers handled tri-stating in the standard. But it is probably good advice to follow. Again, your tools may or may not complain if you attempt to synthesis a tri-stated buffer.