BJT sample and hold circuit for 50 MHz clock
The OP seems to have lost interest in this, but I've been thinking about his basic approach, and would propose the following circuit, which takes the idea and makes it fully symmetric. I have not yet simulated it, however.







simulate this circuit &ndash; Schematic created using CircuitLab

The key concept is that R1 and R2 are actively driven both high and low by the flip-flop. When R1 is high and R2 is low, Q1 and Q2 are active, driving the capacitor voltage to match the input voltage. In the opposite state, they are quickly cut off in order to isolate the capacitor.