Clocking scheme for LAN8720A - Cortex M4
Circuits depicted by figures 3.8 &amp; 3.9 actually work the same way, from the MAC's point of view. The only difference between them is the way the clock signal is generated for the PHY: 3.8 uses the internal crystal oscillator, 3.9 uses an external oscillator. Since 3.8 is demonstrated by the eval board of SMSC, I'd expect 3.9 to work as well.

However, there is a single note in the data sheet that you should pay attention to: "The REF_CLK Out Mode is not part of the RMII Specification. Timing in this mode is not compliant with the RMII specification. To ensure proper system operation, a timing analysis of the MAC and LAN8720 must be performed."

I have never tried to build a circuit with this PHY, so I don't know the exact implications of this note, but I'd expect the problem to lie in the fact that having a common, external oscillator being fed into both the MAC and the PHY can give you a controllable delay between them (you can play with the lengths of the two clock lines), but having the PHY sourcing the clock to the MAC will not give you this freedom, probably limiting the distance between them considerably.