How to check if specific peripheral interrupt is enabled in NVIC?
Quick answer:

I would use the following (ugly) code:

if (NVIC-&gt;ISER[(uint32_t)((int32_t)IRQn) &gt;&gt; 5] &amp;
   (uint32_t)(1 &lt;&lt; ((uint32_t)((int32_t)IRQn) &amp; (uint32_t)0x1F))
{
    // It's enabled!
}


Explanation:

The NVIC_ISERx registers are dual-purpose.  If you write a 1 to a specific bit it will enable the interrupt.  If you read a specific bit it will tell you if the interrupt is enabled:



You are using the SPL and so it is handling the mapping of interrupt sources to ISER registers and bit locations.

In the core_cm4.h file, version 3.00, this is the NVIC_EnableIRQ() function:

__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
    /*  NVIC-&gt;ISER[((uint32_t)(IRQn) &gt;&gt; 5)] = (1 &lt;&lt; ((uint32_t)(IRQn) &amp; 0x1F));  enable interrupt */
    NVIC-&gt;ISER[(uint32_t)((int32_t)IRQn) &gt;&gt; 5] = (uint32_t)(1 &lt;&lt; ((uint32_t)((int32_t)IRQn) &amp; (uint32_t)0x1F)); /* enable interrupt */
}


It's interesting that they commented out the first line (which was identical to the same function in core_cm3.h) and left it there; I'm guessing it was a bugfix and they forgot to remove the incorrect code. I got lost by all the typecasts, but I expect they are necessary.

My answer above is modeled after this NVIC_EnableIRQ() function.



As far as system behavior, the following is taken from ST's PM0056 document (which is for M3, not M4, but the behavior is similar):


  If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.


If the "pending" flag gets set then the interrupt will be served as soon as you re-enable the interrupt.