Understanding requirements for USB 2.0 high-speed
Please note that USB is 480M bits per second, while uPs have their data usually 8 or 32 bit wide. So the rate of system data transfer goes down to 60MHz or 15Mhz only.  USB controllers use hardware access to uP memory (aka direct memory access, or "bus mastering") to transfer blocks of data between the system memory and USB PHY (Physical layer transceiver). The transfers are done in 8 or 16-bit parallel format, and the PHY performs parallel-to-serial conversion. The system usually has plenty of "elasticity" buffers (FIFOs) to provide coherent USB packets in full accords with specified data rates.

The rate of how fast a system can prepare the read/write memory buffers depends on overall processor throughput, so low-performing processors might not achieve maximum USB throughput.