Why is there a maximum time for length of write pulse to write on an EEPROM?
I assume your question relates to parallel EEPROMs.

The Write pulse (time) is a minimum specification and typically has no upper bound. In other words the time specified limits the speed of writing (bits/bytes/words per second), but the chips will operate at any lower write rate. 

For example here is the datasheet for the 26C64 write timing:



Notice there is no upper bound for any of the chip select or write timing. 

Addition:

The 28C16 you raised in the comments shows a limitation of the early EEPROMs ...they needed a higher write voltage for the cell write/erase cycle.
This meant they could not work down to DC (the lowest freq of write cycle possible).