Choosing a MOSFET driver - calculating gate drive current requirement
For LARGE gate_driver ICs, there will be package/bondwire/PCB/VIA/bypass_cap inductance and onchip well-substrate capacitance that will resonate in the 20MHz to 10MHz region. To attempt a 7nanosecond gate-drive event does not buy you any enhanced performance nor any improved reliability.
The various gate-driver ICs will have resistances in the well-substrate capacitances, thus self-dampening..... maybe.
The appropriate Rdampen is sqrt( L / C) = sqrt(10nH / 10nF) = sqrt(1) = 1 ohm.
Given the bulk silicon has resistance, the onchip losses probably are 1 ohm.
You just need to have the external Cbypass (0.1uF?) within 1cm of the Gate Driver IC and Use a GND plane under the IC, Vin, Vout, VDD connections.
Using a Ground Plane will reduce the inductance of that 10mm PCB trace by 5:1 or 10:1, but you still have the bypass_cap inductance, any PCB via inductance, IC leadframe and bond wire.
To predict behavior of this MECHANICAL setup, you must include Inductance of VDD path and GND path, or VDD and Vout (for charging the FET gate), or GND and Vout (for discharging the FET gate). Thus I cheerfully approximate the inductances of those 3 paths as 10 nanoHenries. Achieving speed in switching requires excellent thinking about how to minimize energy stored in all the conductive structures. Knowing the difficulties of this, I use 10nanoHenry to model each of the 3 paths:  VDD_to_GND, VDD_to_Load, GND_to_Load.
As your chosen IC attempts to provide that 8 amps, the surge in current ----- 8 amps  in 8 nanoseconds, through 10nH, will cause this voltage across the 10nH
V = L* dI/dT
V = 10nH * 8 / 8nS = 10*8/8 * NH/nS = 10 volts.
Thus your 15 volt supply will abruptly sag (inside the IC) by at least 10 volts, and maybe more, because the Vout lead also will be 10nH and a similar voltage upset will occur there.
Thus unless you get the inductances DOWN to 1 or 2 nanoHenry (including internal gold-bond-wire inductances) in VDD and RTN and Vout pins on the package, your edge rate will be 20 nanoseconds or so. Partly because the inductances prevent faster output edges.
The silicon processes used likely are old-time CMOS 15volt logic processes ---that is, 15volt NAND and 15volt FlipFlip devices ---- with 2/3/4 nanosecond delay per raw internal inverter. The demand of LARGE output currents is what upsets the VDD and GND (possibly causing oscillation) and causes large voltage drops across VDD/GND/Vout package pins (and the PCB conductive structures).
The Vin pin, with 10 or 20 pF, draws only small charging currents ---- 10pF charging 10 volts in 10nanoseconds, using I = C * dV/dT, ---- such as 10milliAmps.