The total size of 32-bit memory address, 32-bit data words memory arrays?
In ARM architecture, byte-addressing is used. ie., each address location can address a byte.
With 32-bit address bus and byte-addressable scheme, \$2^{32}\$ addressing locations are possible at maximum, and each address location can address a byte.
So the total addressable memory in such a system will be \$2^{32}\$ bytes or 4 GB.
This doesn't always mean that you have a big memory array of 4GB in your architecture.
For instance, the 4 GB address space may be shared by different peripherals and their addressing space, and a memory array.
In your example, the memory array in the ARM architecture is [1024-word x 32-bit array]. It has 10-bit address line (which should be derived from 32-bit address bus), and 32-bit data line. It means it can store \$2^{10}=1024\$ words, where each word means 32-bits. So it's correct in your textbook that its a 32 Kb memory array.