How to Implement Clocking Wizard IP into Vivado Project
In the HDL file generated for the clocking wizard, you would see the entity declaration for the wizard. 

For example:

entity clk_wiz_0
     port (
      clk_in1 : in std_logic,
      clk_out1: out std_logic
     );
end clk_wiz_0;


So, in your code, you can instantiate the clocking wizard as a component. 

Example:

component clk_wiz_0
     port map (
      clk_in1 =&gt; your_input_clk_signal,
      clk_out1 =&gt; your_output_clk_signal
     );
end component;


While this is one method, you can also instantiate the IP in a block diagram and connect the input/output signals of your wizard in the block diagram itself. Once that is done, you can let Vivado generate the output products (VHDL/Verilog files for the block diagram) and create the wrapper/top level file for you.

Hope this helps