Using both edges of a clock
When you assign to a register in an edge-sensitive always block, you're defining a flip-flop. FPGAs do not have flip-flops that can trigger on both edges of a clock.

In order to do what you want, you are going to need to have two separate always blocks, one for each edge of the clock, and then figure out a way to combine the outputs of the two blocks without creating glitches.

For example, one always block could contain your programmable divider. Design it so that the output duty cycle is less than 50% when given an odd number. Use the second always block (on the other clock edge) to delay the output of the first block by 1/2 clock, then OR the two outputs together. Disable the output of the second block for even divider values.