FPGA design rules - Using a Module Output Register Value Internaly
Seems fine.

Three suggestions/recommendations:


Use non-blocking assignments for registers
Use an if-else instead of the case.
You are missing the reset clause - how does it know what value to take when in reset.


So the code would become:

always @ (posedge clk) begin
    if (rst) begin
        Busy &lt;= 1'b0; //Reset busy with the reset signal?
    end else begin
        if (!Busy &amp;&amp; something) begin
            //When not busy and something happens
            Busy &lt;= 1'b1;
        end

        if (Busy &amp;&amp; something_else) begin
            //When busy and something else happens
            Busy &lt;= 1'b0;
        end
    end
end


Worth mentioning in the above it is fine having two separate if statements controlling the same register because it is quite clear that they will never both happen at the same time (one happens on !Busy the other on Busy so they are mutually exclusive).

You can also see here that I have used non-blocking statements. This is the preferred approach for always blocks. Where possible try to use non-blocking, using blocking assignments only in functions and tasks. There are some places where blocking can be useful, but more often than not there is no reason to use them.

If you were doing more stuff, you may find it easier to have it in an if-else format, such as:

if (!Busy) begin
   //Logic when not busy. E.g.
   if (something) begin
       Busy &lt;= 1'b1;
   end
end else begin
   //Logic when busy. E.g.
   if (something_else) begin
       Busy &lt;= 1'b0;
   end
end