VHDL: unknown signal assignment
The outputs flag_out_main and data_out are driven from both processes, and for data_out also the concurrent assign.  Such multiple drivers in a VHDL design are similar to multiple drivers on a PCB, and will result in contention if the driven value is not the same, resulting an a resolved value of 'X', which is probably what you see.

Only drive each signal or output from a single process (but it is OK to have multiple assigns inside the same process) or concurrent assign.

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