TFT LCD pixel clock filtering
Experimentally wrap tinfoil round the cable, and earth it at the driving end. Or the chassis, but not both. If that works, you can find a better way of screening the cable.

Or a series termination at the driving end of the clock signal; this will somewhat slow up the clock edges; in other words reduce the harmonic content. 

I have my doubts about this : if the clock is 30MHz and the peak is at 60MHz that's only the second harmonic. Which means either : the clock is a LONG way from being a square wave (duty cycle is far from 50%) or: the EMI is from other sources (perhaps the RGB data : does the emission go away with the screen black?) Some further information from these experiments and questions may help.

EDIT: If you can scrape up a spare wire in the connector, add a differential driver for the clock at the driving end (the LCD controller) and transmit the clock and its complement down adjacent wires. At the receiving end (the LCD) use a differential receiver to regenerate the clock. This has two advantages : first, the clock waveform will be more accurately preserved despite the cables and EMC filters, and second, the radiation from the two clock lines will cancel each other out, reducing your EMC emissions.