VHDL synthesizing a module doesn't work, but simulating it does. Error: Bad synchronouse description
Your code has two ways to change sig_enable

if falling_edge(tri_output) and sig_enable = '1' then
    if i = 8 then
        i := 0;
        sig_enable &lt;= '0';

...

if rising_edge(SEND) then
    sig_enable &lt;= '1';
end if;


So you are asking for sig_enable to change on either a falling edge of tri_output or a rising edge of SEND. 

There is no off-the-shelf latch or flip-flop that can do this, and that's why the design can't be synthesized. 

In an ASIC design, you might be able to achieve what you want with a SR latch. But you'd need to write code that reflects the actual behavior of an SR latch (level sensitive rather than edge sensitive).

In an FPGA design it would be more usual to use SEND as a combinatorial input to the logic that changes sig_enable when clocked by tri_output or by a fast-running clock (depending on your timing requirements).