Simulating retro hardware on an FPGA
Asynchronous delays are effectively impossible in FPGAs. Running off anything but the system clock as a clock is fraught with difficulty. The correct way to do it, and by correct I mean a way that the timing and PAR tools will work with you rather than you having to fight them, is to use a system wide high speed clock, and use clock enables to qualify when any particular latch has to capture.
You could solve both problems by running a high speed system clock. This then runs a 'CPU clock' state machine, which outputs clock enables with names like 'leading edge', 'falling edge', 'data ready following CAS' and suchlike. If you have a 100 MHz system clock, and a 4 MHz 'CPU' cycle time, then there's plenty of resolution to get sub-cycle timings to be meaningful, even if they're not to the nanosecond. This does require a slight change in abstraction level, but how pure is your model anyway?