Scaling an input in VHDL
You can do this quite elegantly with the new fixed_pkg:

pr_scale : process is    
    constant b : s_fixed(0 downto -15) := to_sfixed(0.8, 0, -15);
    variable x, y : s_fixed(0 downto -15);
begin
    x        := to_sfixed(data_in, x);
    y        := resize( b * x, y);
    incoming &lt;= to_slv(y);
end process;


As a side note I want to comment on the common misuse of types in VHDL: std_logic_vector is an array std_logic, which is a set of variables, signals or constants frequently used to model digital signals. std_logic_vector has no numerical interpretation by default, and therefore has no associated * operator. To do math on std_logic_vector you need to convert it to the correct type in one of the numerical libraries provided by the IEEE: ieee.fixed_pkgand ieee.numeric_std; only you know which one. Since both std_logic_vector and(un)signed are defined as arrays of std_logic they are closely-related types and can be converted with a simple cast. But due to the strong typing nature they are still different types and cannot me mixed.

As a closing remark I want to mention that there seem to be a widespread misunderstanding that you need to convert everything to std_logic_(vector). Most synthesis tools will handle numeric_std types, integers and booleans just fine, so there is no need to discard this valuable tool of abstraction because software twenty years ago didn't support it. To quote Abraham Lincoln:


  The dogmas of the quiet past are inadequate to the stormy present.