Problem with PIPO Register - Verilog
I don't know what a PIPO is but it doesn't matter. I see a few problems.
First, a common beginner mistake: you're doing a bad job defining modules. A multiplexer is one line. If you put it in a module you need many more lines. A register is 2 lines. Also no need for it be a module. There may be times when these do need to be in their own modules but those are advanced edge cases. This can easily be one module.
Then there's your functional problem. You say the register doesn't store anything. You defined it so that if enable is high, you output 0, and if enable is low, you output the data. That's not a register, it's an AND gate (true if data and ~enable are true).
Put back the posedge statement that you commented out. But leave the enable out of it, you can't give a register two clocks.
So what's the enable for? I'm not sure. Is it a load enable for a register? Right now it looks like you're trying to use it as a reset. If you want the register to hold its value when enable is true then say so: use q &lt;= q;. You probably want it when enable is low, not high.
Third mistake, stylistically: if (en==1'b1) is redundant. You can just say if (en). It's a bit, so it has a true or false state naturally.