What factors does the set-up time and Hold-time for an interface IC depend on?
Setup and hold are influenced by the logic speed, the amount of internal skew between the clock input and the destination logic, and the skew between the signal inputs to be sampled.

Faster logic will have shorter setup/hold time since it has less delay, and therefore skew. But this comes at the expense of power.

Chip designers also factor in how difficult it may be for a system to make timing in a given application. As a starting point they will often choose a setup/hold window that is 'reasonable' - say, 20% of the minimum clock cycle, that the data must be stable.

Most standards choose zero hold time for slow logic, but for faster I/O it is beneficial to specify a post-clock hold time to allow for shorter setup time.

I2C timing has a standard, defined by Philips (now NXP) as its benevolent owner. SPI/QSPI has no such standard, benevolent or otherwise. What this means is that if you are designing a system with SPI, you will need to survey various vendors to come up with a worst-case timing model, and design for that case. Fortunately, this isn't as hard as it seems. Choose a couple of leading vendors. You will see that in all likelihood they chose similar specs: 'reasonable' values for the clock speed and application.