Could an ARM (ARM7TDMI) Branch instruction take 6 cycles?
Are you running code from RAM or from flash?  ARM processors that run code from flash often require wait states in at least some circumstances; such processors often include hardware which can eliminate most of the wait states in common code, but such hardware may be as simple as a single-line buffer which allows an access to the same line of flash as the previous access to avoid the wait state.  If the branch target is the last word of a flash line, then the flash would require two or three cycles to fetch that word, and two or three cycles to fetch the following word.  If one of the cycles is performed concurrently with some other CPU operation, that would leave a three-cycle penalty.