Ring Counter Digital Works
I have included an annotated image of your schematic:

First, it is a bit of a mess.  It goes a long way to make the schematic "look clean", especially because wire jogs often cause netlisting errors (or at least does not netlist how you would expect).  Each wire is ideally straight.  The gates are not randomly placed but rather laid out in a fashion that intuitively shows the signal flow.  



I am unfamiliar with what these bottom two ports on the flip flop are.  I am assuming it is some sort of clear?

Regardless, notice the green net.  What is driving this? It looks floating to me.  Generally you want to tie nets to either the supply voltage or ground.  If they are just floating the behaviour can be unpredictable.

Alternatively, the red net (which connected to the left most flip flop) goes to the same port on each flip flop as the green yet does (clear I assume).  But, it is tied to the pushbutton, whereas the green yet is not driven by anything.

So if you want the left most flip flop to act like the other 3 flip flops, connect it with the dotted orange line and cut the wire to the first flip flop coming from the red net (purple dotted line represents cut).

However in practice you would want to make sure all of the input nets are tied.  My guess is that you can get away with it in this case because you are simulating based on verilog, and the reset is something like @rising_edge(clear).  Since a floating net doesn't ever 'rise' this never triggers.  But in real life it would cause very unpredictable results since its voltage could fluctuate based on noise and drift.

Here is an example schematic of how I would build it: