Synthesizeable D Flip flop for FPGA
First: don't use delays in implementations. Delays cannot be synthesized in hardware; they should be confined to testbench code.

Second: the situation you're testing, where d changes at a clock edge, is a timing violation. Failing under these circumstances is perfectly normal; virtually all flip-flops will fail or exhibit inconsistent behavior when subjected to this input. Adjust your testbench to move the transitions of d such that they don't coincide with the clock edges.