Connecting Altera de2 to a sensor via UART
No, a NIOS II is not actually required when using IP components from QSys (the replacement for SoPC Builder), since you may always export the Avalon-MM bus which typically connects to the NIOS II. This breaks out a port which corresponds to the Avalon-MM bus from your QSys HDL module, which you can then directly drive with a state machine in your FPGA that serves as the Avalon-MM master in lieu of the Nios II. You will have to design your state machine to be a Avalon-MM master, refer to the document Avalon Interface Specification for relevant signals and timing diagrams.

With that being said, it may be excessive to implement an entire Avalon-MM interface for a UART. In this case, you should look into the many available open-source UART interfaces (assuming this is not for a class project where you have to implement it yourself). An example is a simple UART found on OpenCores.