How to measure or estimate the phase delay between two analog input channels of this board?
The observed phase delay is artificial, caused by delay in round robin  sampling due to multiplexer reconfiguration and sample settling time, it is an artifact of software they are given same time stamp. A better sampling system would offset time stamps.

As you increase sampling frequency, the phase delay shrinks when in "evenly spaced" sampling mode. 

In "psuedo simultaneous" mode you would expect sample delay to stay consistent, as such we can conclude the internal sampling is evenly spaced but you are pushing the device to it's maximum rate such that the difference disappears. 

In this case there is nothing better to go on besides the published specification and calculating the phase offset yourself (by adjusting the time stamp)



In psuedo simulatenous mode you always sample at the fastest rate, or at a rate much faster than your programmed sample rate, and then wait until the next sample period, this is done at expense of noise in order to get better synchronization. 

The other approach, "evenly spaced" sampling is to set the sample rate multiplied by the number of channels better noise performance, but at expense of synchronization.

As you increase the programmed sample rate these two approaches lose their difference, because you cannot sample faster than the fastest rate, at some point the "evenly spaced" internal periods become as wide as the "psuedo-differential" internal periods. 

It is also possible the device switches in modes when sampling rate passes a threshold 

Since you are measuring internal phase offset, it is not really easy to measure ones own delay to a better degree than you have, certainly you can compare with another ADC sampling without channel cycling.