Phase-locking pixel clock to HSYNC/VSYNC
One way to approach this would be to use your PLL (referenced to HSYNC) to generate a master clock at 3&times; or 4&times; the pixel clock, and then use a Johnson counter to generate new pixel clocks with 3 or 4 different phase values. You can then select the phase that has the desired timing, either manually with a jumper, or electronically with a multiplexer.

There are ways to lock a PLL directly to an intermittent reference (i.e., the video signal itself), but since you already know the nominal dot rate, this shouldn't be necessary. However, you could use the phase detector from such a system to help you automatically select the best phase of the Johnson counter for sampling.