VHDL: Optmize signal comparisons for synthesis
If your circuit can support delays to the trigger_en signal, you can split the comparison (for example 4 8 bits comparators) and pipeline the result over several cycles.
You can use several comparators in parallel with future values, keeping counter_a+1, counter_b+1,counter a+2, counter a+3... pipeline the result of each comparator (as above), then decide which comparison is valid from the value of count_b_en during the last 2 or 3 cycles. Lots of hardware !


"Huge combinatorial delay" : It really depends on your target frequency. FPGAs have fast carry propagation and direct paths between adjacent LUTs, so the delays are not very large for 32bits comparators. (128 bits is a large comparator, 32bits is quite narrow)

The suggestion above with lots of hardware may be theorically faster but practically slower sometimes because the additional hardware add propagation delays, signal load...