digital logic - positive edge-triggered d flip flop triggers when input is on the decreasing edge
No problem with the circuit. The problem is the way you have simulated. When you toggle D at the exact moment of the rising edge of the clock, the HDL simulator will take only its past value. For eg., in your design, you toggled D from 1-->0 @30 ns. But HDL simulator will take it as 1 for the rising edge @30 ns . This will create uncertainity of output even in real world too. In real world, the input D has to arrive and become stable before something called "setup-time" of the flip-flop. It has to remain stable even after the clock edge has appeared, for an amount of time called "hold-time". D should not change within this time window. Only then, the correct output is guaranteed. This is recommended to be followed while HDL simulation too.