ATxmega: reading a register with TWI/I²C
You are not waiting for TWI transfer to complete. If you do not want to use interrupt-driven code, you have to wait for appropriate flag in TWI.MASTER.STATUS being set after each write to ADDR and CTRLC registers.

These flags are WIF and RIF bits in STATUS register (or you can use CLKHOLD bit which should be logical or of these two flags). See, for example, AVR XMEGA AU manual, page 265 for details.

When ADDR is written, either WIF or RIF flag will be set after completion (or on error). RIF is set in case slave was addressed in read mode and one byte was already received then. WIF in all other cases. See pg. 259 in the manual.

In your case (addressing slave in write mode) WIF will be set. You should check that neither RXACK, BUSERR nor ARBLOST bit in STATUS register is set. If all are zero slave have acknowledged its address and you can send data.

Write DATA register and wait for WIF flag. You should check the RXACK bit in STATUS register too when flag is set (bit is zero if slave acknowledged this databyte).

For repeated start just write ADDR register with new value. Writing the CTRLC reg. is not necessary and it results in one extra addressing with original address you do not want.

When slave is addressed in read mode (and it acknowledges the address), AVR will automatically receive first data byte (except when QCEN bit in CTRLB is set), so you have your a databyte ready when RIF flag is set. (But be prepared to see WIF flag instead of RIF too -- it happens in case of any error during addressing.)

Reading DATA register does not affect TWI state machine nor flags (assuming SMEN bit of CTRLB register is not set; note that datasheet is quite unclear on this), so you can read databyte first and issue STOP command (or BYTEREC command in case you want read more) after.