Error in this Countdown module? (Verilog)
Personally, I have had problems with always @(cout) that can be flakey.

I would always use always @(posedge CLOCK_50) . In my opinion, you are guaranteed proper results this way...  

EDIT: added clearer code for above suggestion

always @(cout) -&gt; always @(posedge CLOCK_50)


cout should only change with the positive edge of the clock in theory (or code) but what is actually happening maybe different.  Your timing report will tell you about setup time and slack - and this may be your problem.  change your logic to all "synchronous" and I'll bet you it works.

also, get rid of the inferred latch as good practice.  all this would take is an else statement:

if (cout == 32'h0)
    if (cd == 12'h0)
        cd &lt;= 12'hFFF;
    else
        cd &lt;= (cd - 12'h001);
else
    cd &lt;= cd;


EDIT: suggested working code

module ClockDivider(input CLOCK_50, 
                    output reg[ 0:0] en 
                   );
    parameter clockDivisor = 50_000_000;
    reg [31:0] i;

    always @( posedge CLOCK_50 ) begin
            if ( i == clockDivisor ) begin
                    en &lt;= 1;
                    i &lt;= 0;
            end
            else begin
                    en &lt;= 0;
                    i &lt;= i + 32'b1;
            end
    end
endmodule

//1Hz clock output
wire                [0:0]           en;
//Holds the countdown value FFF-000
reg                 [11:0]              cd;

ClockDivider CLOCK_1Hz( CLOCK_50, en);

always @(posedge CLOCK_50)
    if (en) begin
        if (cd == 12'h0)
            cd &lt;= 12'hFFF;
        else
            cd &lt;= (cd - 12'h001);
    end 
    else 
        cd &lt;= cd;
end