Methods for RAM data setup before clock
You don't need to use the other edge, or phase shift the clock.

Just set the data up on the rising edge, and then the next rising edge will clock it in to the memory (as per option 2). 

Running static timing analysis will tell you of any hold/setup violations. But if you add proper waveform constraints to your clock (i.e. frequency, duty), the fitter will do its best to meet the timing requirements.



This is the fundamental basis of synchronous design. Every register clocks on the same edge at the same time, so theoretically the data from the last cycle at any register input will always be loaded in on the current cycle. This is achieved primarily using low-skew H-tree clock architectures - where the distance from the clock source to any register is pretty much the same length with the same delays - so theoretically every register should clock at the same time. 

The data will take a bit longer to arrive (as it has DFF propagation delay and routing delay) before it gets to the next register, meaning that the input of a register will change at some point after the clock edge that set it up (and hopefully before the edge that is supposed to load it).