Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock
The Instanitation template gives you an example of how to use the core in your project. All you need to do is paste it into your verilog file.

// Instantiate the module
DCM32to50 instance_name (
    .CLKIN_IN(CLKIN_IN), 
    .CLKFX_OUT(CLKFX_OUT), 
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), 
                         ^ Change the signals in brackets to your signals
     ^ You don't need to change the port names
    .CLK0_OUT(CLK0_OUT)
);


To help you match it up with the tutorial, in VHDL, it looks like this:

DCM32to50_i : DCM32to50 
port map (
CLKIN_IN        =&gt; CLKIN_IN,
CLKFX_OUT       =&gt; CLKFX_OUT,
CLKIN_IBUFG_OUT =&gt; CLKIN_IBUFG_OUT,
CLK0_OUT        =&gt; CLK0_OUT);
                         ^ Signal name you can make what you want.
  ^ Port name doesn't change


CLKIN_IN is your input 32 Mhz clock
CLKFX_OUT is the new 25 Mhz clock
CLKIN_IBUFG_OUT is a buffered version of your 32 Mhz clock
CLK0_OUT is your input clock at 0 phase (basically your input clock again).