Inferred latch warning on out port in VHDL
The latch is inferred because your "when" has no "else". 

If there is a reset (RST) o_address is set to zero. Fine.
But when the reset goes away what then?
It has to stay that way according to your code so a latch is inferred. 

So make sure you assign to o_address  in the 'others' section and the latch goes away.



As a side note: you would normally not use a reset signal in a combinatorial circuit. Generally speaking you reset a register.