How to use "AND" statement in Verilog
The conditions in an if-else if chain are evaluated sequentially, and once one of them matches, the other ones will not be checked. So when you have:
else if (start)
    counter &lt;= counter + 1; 
else if (start &amp;&amp; stop)

it sees that start is 1, and runs the counter + 1 assignment. It never checks if stop is also 1.
To fix it, you have 2 options:

Reverse the order of the checks (check start &amp;&amp; stop before checking start alone), or
Change the first condition so that it is false when stop is 1, like if (start &amp;&amp; !stop)