FPGA filter - sinusoidal wave at clock frequency observed in filtered signal
Signals accidentally propagate through adjacent pins and the PCB – that's called leakage, and more or less inevitable in circuits; you can reduce the amount of leakage by good PCB design, shielding and separation.

In the RF regions that your clock takes place, a rule of thumb is that if you've got more than 50 dB power suppression between harmonic signals carried on the same FR4 PCB, you're doing relatively well.

So, that explains you inevitably seeing the clock in your signal at all.

The question why you're not seeing it at 10 MHz is probably simple: 

consider what a 40MHz clock is:

it's ideally a square wave with a period of 40 MHz. I trust you as random physicist know how deal with the Fourier transform, and can easily see that a perfectly periodic square wave signal has a discrete Fourier transform with dirac impulses of decreasing "amplitude" every 40 MHz. 

The main frequency component you should be seeing is the 40 MHz tone itself. Now, that happens to be a harmonic of the 10 MHz signal, and the leakage of the clock into the ADC itself might lead to a "misobservation" of the input 10MHz as Input 10 MHz + 4. overtone – and your 12-tap filter just cancels out both, so that, if observed randomly at a "sweet phase spot", both are simultaneously cancelled out.