VHDL: Component vs Entity
Here's an analogy which helps some people (especially those from a physical electronics background):

A component tells the compiler "there's going to be something with these sorts of pins on it called this at some point, but don't worry for now".  It sort of defines a "socket".  You can go on to describe what "wires up" to that "socket" etc.

An entity is something specific with a name and a set of pins, which the compiler can then "plug in" to that "socket" (and hence be connected to the "wires").  

Note that you don't need a component you can do "direct instantiation" which means the compiler already knows about an entity so the "socket" doesn't need to be defined separately.  In fact, that would be my recommended approach, as otherwise the component is an extra level to be kept in sync.

You need to use components if you are mixing Verilog and VHDL and need to use a Verilog block within the VHDL.  Then the component is the socket and not until much later on can the compiler/elaborator plug the Verilog into the socket.