DDR2 CAS Latency - is it fixed to clock-cycles or time?
CL minimum value is time based, but it is counted in clock cycles. So using it at a lower frequency you can presumably reduce CL - but if so, you must specify the actual CL value in the DRAM's mode register on initialisation; if the data sheet gives a mode reg bit pattern representing CL=5, then you are probably OK.

Also check that your reduced clock frequency is still within the permitted range for the part's internal DLL (there will be a minimum freq specified) but I think 270 MHz will be OK.

These details are from memory, but I did reliably operate DDR2 from a Virtex-5 FPGA at just under 200MHz so there is some leeway.