Why DDRx I/O bus frequency is half effective frequency?
The 4N pre-fetch architecture means that 4 data words are pre-fecthed prior to the read burst from 4 different adjacent columns. This diagram assumes the row address hs already been latched by an activate command.

Here is the read timing:



In the actual data transfer burst, you can see DO n in the first transfer and from the datasheet 

DO n = data-out from column n. where n is between 0 and 3 (the data is not necessarily transferred in the order 0, 1, 2, 3).

We ae using both edges of the clock and therefore 400 MT/s (MegaTransfers per second) equates to a 200MHz clock.

Therefore the 4N relates to the number of transfers done during a burst, not the actual burst rate.