Tips to lower q point of transisitor
There are a lot of things wrong with your design. There are also a lot of tight and workable designs on the web, which combine some ideas but don't really address your question. You said,


  I'm thinking it has something to do with biasing.


and asked,


  How do I bias it correctly?


Let's start there.

The first thing to recognize is that your \$Q_1\$ is set up as a basic degenerative amplifier. Nothing unusual about its topology. Your \$Q_2\$ is also not unusual, but it is set up to maximize the gain (probably in the hundreds) because of \$C_5\$ completely bypassing \$R_6\$. Its gain is temperature dependent and dependent on the emitter current, which varies a lot with the signal's value from moment to moment. So without global negative feedback, that's going to be a potential source of significant distortion. (Yes, you see that schematic on the web. Yes, it can be made to work. And no, I'm not going to address a design using that method here. I'd have to write even more than I did already. Not happening.)

Let's step back for a moment. The basic idea of the two-BJT arrangement is that you have two amplification stages so that the input and the final output are roughly in-phase (each BJT stage adds \$180^{\circ}\$.) I say roughly, because once you add in the frequency-setting network, that won't be exactly in-phase by the time it makes a full circuit. However, the key idea with this design is that the network itself is both a high-pass and a low-pass filter and that the resulting high-Q filter has phase-related slopes that will drive towards and find the right operating point.

If you just set out not to get too fancy (automatic gain control or the combination of more complex networks into simpler ones which aren't quite as obvious), then it is the following closed loop of pieces: stage 1 gain, load loss, stage 2 gain, load loss, a network divider, and then back to the input of stage 1. If you ignore the load losses and just focus on the two stages of gain and the network divider, and if the network divider is based on an R+C+(R||C) design with the two R values and C values (taking into account parasitics) being the same, then the combined amplifier gains must be 3 to account for the network divider's \$v_o=\tfrac{1}{3}v_i\$ behavior. However, you have load losses due to stage 2 loading stage 1 and due to the load of the network on stage 2's output. So you'll actually need more gain than that. How much more depends a great deal on choices you make for your two amplifier stages.

The loading issue is significant, by the way. At least, if you use the amplifier topology you chose. It would really help in a case like this to use bootstrapping. But that would add more parts. It would also be nice to use a gain-setting AC leg in your amplifier emitters, so that you'd have an important degree of freedom in designing your amplification. But we can see if it is avoidable (maybe) and if not, then use it just for one stage and not both, perhaps.

Let's start with the network, itself:







simulate this circuit &ndash; Schematic created using CircuitLab

The above network will load your stage 2 output. If the collector resistor is about \$10\:\textrm{k}\Omega\$ then it will diminish the output amplitude to about 72% to 73% of the designed amplitude, for example. This will then be divided by 3. A \$3.3\:\textrm{k}\Omega\$ collector load will get you almost 90%, though. And provide a reasonable quiescent current. So that's my first step:







simulate this circuit

Already, you can see that we need a gain of at least \$\tfrac{10}{3}\$. We need to set the \$Q_1\$ collector quiescent point, now. I'm going to make a decision and say that the signal voltage will be \$v_o=4\:\textrm{V}_{pp}\$. And I also want at least \$1\:\textrm{V}\$ of comfort margin between the peak and the rail, so I'm setting \$\textrm{V}_{qc_1}=8.7\:\textrm{V}\$ so that I have a quiescent current of exactly \$1\:\textrm{mA}\$. I want the quiescent emitter voltage to be at least \$1\:\textrm{V}\$ (thermal reasons.) Other balancing worries will be the biasing Thevenin as a load on stage 1, and the Early Effect. Mostly, though, I want to get a lower load on stage 1 so I am deciding to make the emitter voltage \$\approx 2\:\textrm{V}\$ and setting the emitter resistor to \$1.8\:\textrm{k}\Omega\$. The resulting design now looks like:







simulate this circuit

This will present a load of about \$21\:\textrm{k}\Omega\$ on the prior amplifier stage. Now, this presents a problem. If I want to not load down the prior stage much, I'm going to have to operate it at about the same quiescent current I'm already using. But this means a load of about the same to whatever is driving it... and that just happens to be our network, which uses \$10\:\textrm{k}\Omega\$ resistor values. The load will change the operating frequency or else will make us have to take it into account when designing the network. This is where I'd really like to use bootstrapping. The other option is to reduce the loading on the network, but then increase the load loss between the first and second stages, meaning I'll have to get some more gain to make up for it, somehow. It's annoying. So let's avoid bootstrapping but add in extra gain by adding an AC gain-setting leg at this stage, and shoot for a biasing Thevenin of about \$120\:\textrm{k}\Omega\$. That will still pull the frequency a bit. But hopefully we can live with that.







simulate this circuit

Lots of compromises here. And this thing will take some time to start up, as shown. But it will get there. And there is no auto-gain control. So you may need to set up a potentiometer arrangement for the AC leg of stage 1 to tweak things. But if all my calculations are right, the gain should be just about right.

Let's go through the design of that first stage, now.

With a decision to limit the loading on the network to \$120\:\textrm{k}\Omega\$, I was forced to set up the biasing resistors as shown. I kept the biasing point used in the second stage, so the operating points are about the same. This led me to have to set up the collector resistor with about 10 times the current flowing in the biasing \$R_9\$ and \$R_{10}\$ divider. \$17\:\mu \textrm{A}\$ in the divider, so about \$170\:\mu \textrm{A}\$ for the quiescent collector current. So \$R_7=\frac{3.3\:\textrm{V}}{170\:\mu \textrm{A}}\approx 19\:\textrm{k}\Omega\$. I chose \$R_7=18\:\textrm{k}\Omega\$ as a near value. Similar considerations led to \$R_8=\frac{1.8\:\textrm{V}}{170\:\mu \textrm{A}}\approx 10\:\textrm{k}\Omega\$.

Now, I needed to work out the needed gain for the stage and set up an AC leg. The gain I needed was \$\frac{1}{0.3\cdot\ 0.92\cdot 0.54\cdot 1.833}\approx 3.7\$. To achieve this, I needed to compute a resistor, which when taken in parallel to \$R_8\$ would yield the needed gain. This means \$R_{11}=\frac{\frac{R_7}{3.7}\cdot R_8}{R_8-\frac{R_7}{3.7}}\approx 9.5\:\textrm{k}\Omega\$. I chose the nearby \$R_{11}=9.1\:\textrm{k}\Omega\$ value.

That's about it. Hopefully, that shows you how to bias things. But also some of the problems you'd face in thinking this through.

This circuit is very sensitive and I can't promise that the design as shown will actually operate, if you built it. You need a way to adjust the gain value. You can do that with the AC gain leg, though, by applying a potentiometer and reasonably chosen nearby resistor values so that you have a way of making adjustments. But it should get you very, very close.

You wanted to know how to bias things. I kept this simple, used standard topologies and standard ways of connecting things up. There are lots of ways to take what you see here and recognize equivalences you could use to reduce parts. But I thought I'd go through a basic design process so that you could see it in operation, each step of the way. Hopefully, this process will let you try your own approach. Hope it helps.

Oh, and an odd note to add. Note that we set up stage 1 for a gain of about 3.7 and stage 2 for a gain of about 1.83. On paper, this would sound like a gain of about 6.8! Yet we might naively assume we just needed a gain of 3, plus perhaps "a little." Well, the "a little" part seems to be more than just a little. So this is what happens if you don't do the calcs and just shoot from the hip. You might be off by a factor of more than 2. That's because it ignores the losses around the loop, which as I said aren't inconsequential.

I finally stuffed this thing into the simulator. I was worried it might not simulate. A long start up time (which might occur because the network is off-balance due to \$R_3\$ adding to \$R_2\$, so it takes a while to track in) and my worries about getting all the calcs right and not missing something important were valid worries. Nice. It just simulated fine. It showed the long start up, too -- two seconds! Frequency came up as \$1440\:\textrm{Hz}\$, which we'd hoped would be closer to \$1590\:\textrm{Hz}\$. But given the impact of \$R_3\$ on \$R_2\$ and the first stage's loading impact on \$R_1\$, I'm not surprised.

So I changed \$R_2\$ so that it was \$6.8\:\textrm{k}\Omega\$ (to compensate for \$R_3\$) and it started right up, fast. As expected. The output was a bit distorted, though. Slightly too much gain, of course. (Keep in mind this is a simulator -- reality may vary.) So I increased \$R_{11}\$ a bit to tweak it in -- at about \$11\:\textrm{k}\Omega\$ it looked nice and sinusoidal. This changes the first stage gain from about 3.7 to about 3.44. So that's not far and, as I said earlier, setting up a potentiometer there to tweak the gain a bit is probably a good idea in a real circuit.

In general, the simulator proved out the basic design calculations, which were able to proceed reasonably and apace and didn't lead one astray. The basic design ideas predicted the issues of gain sensitivity, start-up timing (and why), and then also where to make changes to get things moving in desired directions, too.