How to perform FSK modulation in VHDL
If I am not wrong, this is my idea. You want to change your data stream on base of fsk_data and use counter for selection purpose. Let say you provide the fsk_data to logik. Inside your logik you have counter that select the pins of fsk_data which is 22 bit wide. Use counter of 5 bit &amp; max value equivalent to 21 and fsk_data(counter_value) to point fsk_data respective bit. Use that value as selection line for mux. Try to run the counter negative edge (not gate with clk) to make it advance for output FF.