How to assert multiple concurrent assertions in system verilog?
I am rusty on writing assertions, but, maybe this will help...  Do you expect them to be true on the same clock tick?  If not, use ##[&lt;value&gt;:&lt;value&gt;] to express a range of clock cycles for it to be true. e.g. from_clk |-&gt; ##[1:2] to_clk

And, without knowing more about the clocks, not sure if the &amp;&amp; is going to work as seemingly one happened in the past(?)  Might be more meaningful to use || assuming you only look for either condition for any given clock crossing(?)  Maybe, two separate assertions... actually, one property to which you pass variables, and form two separate assertions (from-to, and to-from), might be better.

Also, a good simulator (e.g. Questa) will have assertion tracing you can use to visually debug the assertion by stepping through.  Powerful and useful, as assertions can get complicated and, in turn, be painful to get right.

There are more details in the IEEE-1800 standard (or www.accellera.org if you don't have access to IEEE).  But, a more direct and quicker example and explanation can be found here: https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/