What are the applications of external feedback for FPGA PLL's?
you want the FPGA to align to the same clock as some other IC's... so you do not to resync inputs to a different clock. e.g a ethernet phy will align to each new frame it receives... and the MII Interface defines both clocks, Rx &amp; Tx to be generated by the Phy. So an FPGA would need to sync to external clocks.