What is the most common logic family in modern CPUs?
Silicon is the most commonly used substrate because it is made from sand, cheap, and easy (grows its own oxide).  It also happens to make great FETs, which naturally form CMOS logic in a digital environment.

The reasons CMOS are used in Silicon:

CMOS is great for modern CPUs, and almost certainly the most common logic family, especially in the lower nm (22nm, 14nm, 10nm). 
There are a lot of reasons that combine to make this true:


Rail to rail logic levels (always either a path to the supply or ground)
Simple to understand and there are few constraints on their usage
Very predictable and nearly foolproof -- there is nothing dangerous about CMOS
When not switching the only power consumed is leakage
Inputs are just a capacitive load
Less power than dynamic logic
Easily consumed by synthesis tools
Ratioed logic.  This means if the voltage scales down (or up), all of the logic gate characteristics scale proportionally.  As an example, the switching voltage of an equally ratioed inverter is half the supply voltage.
In general individual gates do not require a clock (unlike domino).  Flip flops still do.  This makes a huge difference when you consider routing congestion is the biggest issue in newer processes.  The wire delay rises with respect to gate delay in each new technology and there is no reason why this will change anytime soon.
I can't stress enough the benefit of not needing a clock.  Check out this image to see the extraordinary increase in wire vs. gate delay (this is only to 100nm; we are at 7nm these days).  Similar reason makes any type of differential logic less appealing.




Dynamic logic (different implementations) is commonly used for memory/caches.

The fastest will depend a lot on the design and the process.  For example, is it more routing limited or gate limited?  If you can get away with it (more gate limited), domino logic will most likely be faster.  If it is wiring limited, then you will force routing congestion to convert to domino logic, since each gate now needs an extra clock signal.  So, in this case, you may want to go with Mono-Static Skewed CMOS.  This is like CMOS but skewed for only a single edge.  Typically the logic will be duplicated for both polarities, and captured with an SR latch.  This increases the area and power but can provide better speed.

Also, transmission gate logic is faster in a lot of cases, especially for multiplexers/demultiplexers and the high-z element in flip flops.  This is not technically CMOS logic but is pretty ubiquitous at this point with modern CPUs, especially datapaths.  Depending on who you ask some may consider that CMOS logic.

For less power consumption, I still think CMOS would probably be used.  If delay is not an issue you can use weaker gates to reduce leakage current, or stack the FETs.  Or use clock/power gating, but this is more of a technique and not so much of a logic family.