Map error in ISE caused by PLL
This error is related to the RPM grid mentioned in the error message. Next a definition of RPM grid from a Xilinx Link


  A Relationally Placed Macro (RPM) defines the spatial relationship of
  the primitives that constitute its logic. An indivisible block of
  logic elements that are placed as a unit  into a design.


That is, the PLL you have added have her position in the FPGA relatively related to other logic. Mapper have tried to place it but it have failed due to design constraint or maybe because there is more PLLs that need the place of the RMP PLL.

Said that, what can you do about this issue? Some examples:


Disable the RPM grid of the core if possible. Some times can be disabled, but in other cases the RPM grid is needed for the core to work.
Lock the place of the RPM PLL with a placement constraint. Maybe the rest of the core could be placed in the RPM grid locations
Lock the place of the PLL that occupy the place demanded by the RMP PLL
Consider use a DCM instead a PLL. More numerous and less power consumers.
Others strategies.


In conclusion, help to the mapper with some instructions.

Best regards