Preset and Clear in SR Flip Flop
One point of confusion here is that the circuit is not a combinational logic block; you can't exactly have a normal truth table. Instead, you have to somehow say what happens relative to the clock edges, possibly over multiple clock edges. That's what the picture of a pulse in the \$CLK\$ column is supposed to mean in the book. As a first step, instead of making a single truth table for the entire master/slave combination, I would first make two separate truth tables. The slave truth table should probably have \$Y\$, \$\overline{Y}\$, \$CLK\$, \$\overline{PRE}\$ and \$\overline{CLR}\$ as inputs. The master truth table would just have \$S\$, \$R\$, and \$CLK\$ as inputs.

I think what you might find is the \$\overline{PRE}\$ and \$\overline{CLR}\$ function correctly, but only when \$CLK\$ is high.

The last line of your truth table is definitely concerning. When \$PRE\$ and \$CLR\$ are both high (inactive), \$S\$ and \$R\$ don't matter, and \$Q\$ and \$\overline{Q}\$ are both high? Are you sure about that? Try re-casting it in terms of \$Y\$, \$\overline{Y}\$, and \$CLK\$ and see if it's still true.

I hope the rest of the book is better than this example.