Why do cascading D-Flip Flops prevent metastability?
Metastability cannot be 'cured', but if you wait long enough, the likelihood of it occurring can be made arbitrarily small. Once you've got it down to once in the age of the universe, it's probably unlikely to cause you trouble.

It's like balancing a pencil on its point. It's likely to fall over, and the longer you wait, the less likely it is to remain standing. 

There are two problems with waiting a long time, and one of them is fundamental.

The fundamental problem is that if you have a single memory element (latch or flip-flop, they both suffer from metastability) in a clocked system receiving the output from an asynchronous external system, then you physically cannot define a lower limit to the waiting time, sometimes the external signal will make a transition near the latching control edge. You have to pipeline the signal to another flip-flop to let it wait there. This gives you a guaranteed one clock cycle minimum wait time.

The second problem is that often you're trying to run a system as fast as possible, and the system clock rate cannot be slowed down to give enough time in the second flip-flop. The only way to increase the signal latency to what's necessary, without decreasing the throughput, is to pipeline the waiting to more stages.

Some people have trouble visualising what's happening between the flip-flops. There are two ways to induce metastability, and they both involve violating the flip-flop rules. One way is to violate the input setup and hold times, to make a transition when the flip-flop expects the input to be stable. The other is to violate the input logic levels, to make the flip-flop data input sit at an intermediate voltage level. A flip-flop that's being metastable can produce either type of violation on its output, to cascade on to the next flip-flop.