Unsure if this asynchronous D-Flip-Flop Verilog code makes sense
Yes, it is valid. There is no problem to use other signals as conditions inside a combinational or sequential process.  

Just one remark though. You say it is asynchronous because of the reset signal, right? You know the enable will only be checked in a rising edge of the clock, do you?  

Additionally, I agree with Plutonium Smuggler. If you want to verify your design, you should probably write a test bench and look at its behavior in a simulator.