Verilog - Can you `define a bit slice?
You can `define almost any text you want. You would have to use  a[`opcode] with the backtick.

SystemVerilog gives you some other options. 

The let construct declares a name for an expression.

let opcode = a[5:3];
...
if (opcode==someValue)


You can use a packed struct.

struct packed {
   logic [1:0] field1;
   logic [2:0] opcode;
   logic [2:0] field2;
} a;


Now you can refer to a.opcode as the same as a[5:3].