Inferring RAM ALTERA from vhdl of HDL CODER
The Quartus synthesizer has some serious issues.  It's extremely particular about inferring RAMs as well as performing certain constant elaboration (i.e. initializing a RAM with a trig function such as sine).  It's infuriating.  The most annoying thing is most of this stuff will be properly recognized by the Xilinx tools.  I recommend just rewriting it using the provided template instead of using simulink generated code.