Level shifting of 125 MHz clock signal
For reducing the clock voltage from 3.3V driver to 1.8V at receiver, you can simply use a resistor divider, properly designed for your trace impedance. 

Even more, you just need to put a trace impedance-matching load at the receiver end of clock trace, and the voltage amplitude will come down naturally.  

I would recommend to use the free LTspice tool to model your source, trace (transmission line), and input pin model to get proper resistors and tune up the network for nice-looking clock.