Multiplex Seven Segment Display Fast enough to make Solid
Thank you Dave Tweed for finding my small mistake.

I forgot to add the "LOC" in the constraints file.

NET "clock" LOC = "B8";


I also had some pulse width issues(segments partially on) with the full 50 MHz as Dave Tweed also mentioned. So I used a prescaler to tone it back to 500 Hz.

Divide a 50 Mhz clock by 100,000 (base 10) or 11000011010100000 (binary)

Final code looks like:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    port(
        clock       : in STD_LOGIC;
        sevenseg    : out STD_LOGIC_VECTOR(6 downto 0);
        anodes  : out STD_LOGIC_VECTOR(3 downto 0);
        switches    : in STD_LOGIC_VECTOR(6 downto 0);
        dp      : in STD_LOGIC
    );
end main;

architecture Behavioral of main is
    signal prescaler: STD_LOGIC_VECTOR(16 downto 0) := "11000011010100000";
    signal prescaler_counter: STD_LOGIC_VECTOR(16 downto 0) := (others =&gt; '0');
    signal counter: STD_LOGIC_VECTOR(1 downto 0) := (others =&gt; '0');
    signal r_anodes: STD_LOGIC_VECTOR(3 downto 0);
begin

    anodes &lt;= r_anodes;

    -- Given Binary Value print it
    multiplex: process(counter, switches)
    begin
        -- Set anode correctly
        case counter(1 downto 0) is
            when "00" =&gt; r_anodes &lt;= "1110"; -- AN 0
            when "01" =&gt; r_anodes &lt;= "1101"; -- AN 1
            when "10" =&gt; r_anodes &lt;= "1011"; -- AN 2
            when "11" =&gt; r_anodes &lt;= "0111"; -- AN 3

            when others =&gt; r_anodes &lt;= "1111"; -- nothing
        end case;

        -- Set segments correctly
        case r_anodes is
            when "1110" =&gt; 
                if switches(0) = '1' then
                    sevenseg &lt;= "1111001"; -- 1
                else
                    sevenseg &lt;= "1000000"; -- 0
                end if;
            when "1101" =&gt; 
                if switches(1) = '1' then
                    sevenseg &lt;= "1111001"; -- 1
                else
                    sevenseg &lt;= "1000000"; -- 0
                end if;
            when "1011" =&gt; 
                if switches(2) = '1' then
                    sevenseg &lt;= "1111001"; -- 1
                else
                    sevenseg &lt;= "1000000"; -- 0
                end if;
            when "0111" =&gt; 
                if switches(3) = '1' then
                    sevenseg &lt;= "1111001"; -- 1
                else
                    sevenseg &lt;= "1000000"; -- 0
                end if;

            when others =&gt; sevenseg &lt;= "1111111"; -- nothing
        end case;

    end process;

    countClock: process(clock, counter)
    begin
        if rising_edge(clock) then
            prescaler_counter &lt;= prescaler_counter + 1;
            if(prescaler_counter = prescaler) then
                -- Iterate
                counter &lt;= counter + 1;

                prescaler_counter &lt;= (others =&gt; '0');
            end if;
        end if;
    end process;


end Behavioral;