Why does dynamic ram need to be 'refreshed'?
Why refresh?

DRAM uses capacitors as storage cells. These capacitors, being really small and made from silicon, will leak off their voltage over time. That’s the D in DRAM: the cells are dynamic: their charge state changes.

To preserve the logic state of those leaky DRAM cells, their state must be read before their charge has bled off, then written back to bring their state to full, freshly-written charge. That’s refresh, in a nutshell.

To help deal with this, DRAMs implement a special kind of read-then-write cycle, called refresh, that hits multiple cells at once and writes them back. Typically, this is one or more rows of cells, about 1/256th of the DRAM at a time. 

The host refresh operation is a race against time: all the DRAM rows have to be hit in time before their contents leak away. This usually works out to between 8 and 16ms to hit all the rows.

In contrast, Static RAM, or SRAM, uses a latch as a storage element. The latch keeps its state as long as the power is kept on or it’s written with a new value.

What does this mean with power and density?

SRAM can, in theory, have almost no standby power, as it uses a CMOS latch to store data. In practice, fast SRAM will have fairly high standby leakage current and even higher current during activity due to the use of low-threshold transistors to increase speed.

SRAM latches take between 4 and 8 transistors per bit, and all of them can leak.

More here: https://en.wikichip.org/wiki/static_random-access_memory

Meanwhile, DRAM has standby power to deal with refreshes. There’s considerable effort by chipmakers to offer low-power self-refresh modes that both stretches out the time between each refresh operation, and doesn’t require host intervention once that mode is entered. This self-refresh mode gets used in computer ‘sleep’ state, allowing CPU power-down yet enabling near-instant wake up time.

Density-wise, DRAM basically uses one transistor per cell, connecting to the capacitor which is dug vertically as a well into the silicon. This makes DRAM area per bit very small compared to the SRAM 6T or 8T latch cell. With fewer transistors, DRAM standby leakage per bit is also reduced.

More here: http://www.cse.scu.edu/~tschwarz/coen180/LN/DRAM.html#CellDesign

So overall, owing to its density and lower transistor count per bit, DRAM is substantially better power than fast SRAM; but substantially worse than slow, low-leakage SRAM because it requires refreshing.