Sigma-Delta ADC with variable reference DAC
You can find high_resolution (over_sampling) ADCs with descriptions and characterizations for variable VREF.
I recall some promising to function accurately from +5 down to +1v on the VREF, with +5v VDD.
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Regarding the ENOB dropoff of the 10/12 bit 1MSPS AD7450A, after examining the datasheet plots for how DNL (differential non_linearity) varies with VREF, we come to the silicon_area costs of matching.
To accurately implement the binary_search conversion process of modern ADCs, there are arrays of onchip capacitors. Numerous methods are used to achieve nearly perfect charge division for 9 or 10 or 11 or 12 decisions.
But the matching is not perfect. There will be acid_etching errors, and unless the capacitor areas are infinite (costing infinite power from input signal, and from VREF, thus not possible), the slight variations in metal widths and in capacitor insulation_layer edges will slightly degrade the designer's pursuit of ideality.
In Figure 11, we see the DNL at +5v VDD. There are few error points out past 0.3 Vquanta, several(100?) out past 0.2 Vquanta, and about 50% of the errors are past 0.1 Vquanta. Thus there is a cliff of binary_search decision_making at 0.1 Vquanta.
This design and this layout (12 bits) really is a 12+3 = 15 bit ADC. Likely has excellent yield.
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What happens as VREF is reduced?
We expect big reduction in ENOB as VREF is reduced, because of internal &quot;noise&quot;

inherent DNL

Power Supply Rejection

Random Boltzmann/Johnson/Nyquist electron noise and surface charge trap exit/refill

digital Trash from the SPI interface, if running concurrent with track/hold/convert

a constant injection of non_synchronous substrate and VDD trash, from the MCU that continues operating during ADC conversion. Even if SPI 3_wire interface is nominally &quot;quiet&quot;, the MCU continues with its own program_execution and memory fetches and other output_line transitions, thus the MCU substrate and VDD are VERY NOISY/RINGING/SPIKING and the nominal SPI quiescent levels will really be +-0.5 volts (or 0.2 volts) with 2 and 1 and 0.5 nanosecond edges, coupling thru the ADC logic_pin ESD structures. The charges thus injected into the ADC will explore all possible paths back to home. To prevent this charge injection (likely crucial for 24 bit systems, as LT2410 datasheet illustrates), you need an intermediate buffer IC.


We don't know the thermal_Boltzmann noise portion of the design budget. Nor are the timing/interface conditions specified. We can presume the VDD is very quiet for this ENOB evaluation.
Thus the rolloff is predicted by the 0.1 Vquant cliff. We can expect VREF/10 to be the cliff, and indeed we see a full bit degradation at 3.5v/10, as shown in the Figure 18.
I've included link to datasheet, below.
[I'd happily cut/paste those 2 figures, but stackX does not permit that for my browser.]
https://www.analog.com/media/en/technical-documentation/data-sheets/AD7440_7450A.pdf