Decoupling caps in circuit schematics difference
Decoupling caps need to be physically close to the pins they are decoupling.  This also means every power pin needs its own decoupling cap.  Since the values of all your decoupling caps are the same and are small, what you see is probably due to the IC having more than one power pin.  This is common with large digital ICs, like FPGAs and microcontrollers.

Sometimes you see two caps for a different reason.  One of them is a decoupling cap and the other is meant for lower frequency "bulk" storage to ride out short power glitches and the like.  The first will be a small ceramic usually in the 100 nF to 1 &micro;F range and physically close to the power pin.  The other will be a much larger capacitance, often electrolytic, and can be farther away like at the power entry point of the board.  The electrolytic is no good at decoupling because it has poor characteristics at high frequencies, but it does have much higher energy density.

Sometimes two true decoupling caps are used in parallel.  This is usually for RF or other high frequency applications.  No capacitor is perfect, and every real capacitor only works like a capacitor below some maximum frequency.  Smaller capacitors usually work to higher frequencies.  Sometimes you will see 100 nF in parallel with 100 pF or 1 nF.  The extra capacitance from the second capacitor is irrelevant, but it brings lower impedance at higher frequency, which the larger cap can't do.