How to understand the timing report after synthesis?
No it's no error.

Synthesis just estimates timings because you didn't apply any constraint file. In the normal ISE flow, constraints are applied in the translate step. If this is to late and you need earlier constraint checks or optimizations, then you can apply a XST constraint file (*.xcf) with timing information.

The syntax is the same as in ucf files but only timing constraints are allowed. The processing of an xcf file can be enabled in the synthesis process properties.

Edit:

Sorry I overlooked your bold lines as I wrote my answer.

There are 4 types of connections in a design (in order of your reported lines):


clocked element to another clocked element (e.g. flip flop)
Input pin to clocked element
clocked element to output pin
Input pin to output pin


When synthesis reports No path found, it just means this type of path does not exist in your design. And so it can't report any timings.