Strange behaviour of Attiny's ADC
Incorrect 16 bit register access pattern 


  When ADCL is read, the ADC Data Register is not updated until ADCH is
  read.



In C, the evaluation order of the | operator is undefined, so this code is could be reading ADCH first, and then reading ADCL. Once you read ADCL then you have locked the data register until the next pass though the loop, which is certainly not what you want. 

Try changing this line to...

adc = ADC;


(the C compiler should generate the correct access order coding). 


Reading ADC while it is being updated.


This diagram strongly suggests that the ADC register is updating up until ADIF goes high...



I'd expect that new bits are shifted into place with each successive approximation, and the extra delay of the nop could be enough so that the ADC is ready by the time you hit it just by chance. 

Try replacing...

adc = (ADCH &lt;&lt; 8) | ADCL;


...with...

while (! ADCSRA &amp; _BV(ADIF) );
adc = ADC;
ADCSRA |= _BV( ADIF );


...and see if that resolves the timing issue. 

Report back if this fixes the problem. If not, we will move on to next try!