Using Timer0 overflow to gate Timer1 on PIC12F1822
I think your problem is based on confusion over exactly what the TMR1 Gate signal actually does. It does not, by itself, cause the timer to count, it merely enables it to count if there are suitable events occurring on its clock input.

It's subtle, but if you look at "FIGURE 21-1: TIMER1 BLOCK DIAGRAM" in the datasheet (p. 179), you'll see the TMR1H/TMR1L register in the middle. All of the logic above that is related to gating, and all of the logic below that is related to clocking. It all comes together at the flip-flop just to the right of the TMR1 register, where the gate signal drives the EN (enable) input of that flip-flop, and the clock signal drives the D (data) input.

What this means is that the output of the flip-flop will toggle (and cause TMR1 to increment) only if the gate signal is high and the clock signal is toggling.

There simply is no way to route overflow events from TMR0 to the clock logic of TMR1, either inside or outside the chip.

EDIT: OK, digging a little deeper (prompted by the comments below), I notice that you have the T1SYNC bit in the T1CON register set to zero. This causes the clock source to be synchronized to Fosc. If that clock source is in fact Fosc itself, the output of the synchronizer will be a constant level &mdash; always high or always low, but not toggling.

I believe this is the root cause of your problem. Try setting T1CON to b'01000101'. This should accomplish what you want, assuming that the overflow pulse from TMR0 is exactly one Fosc period long.