SR NOR LATCH characteristic
First, I am not 100% sure what your question is, is it about how the gates are arranged or about the logic..

But what I have interpreted is the following:

Present state is stated as Q=0 Q'=1 from the truth table below this indicates that the SR is RESET.

Now S=1 and R=0 (stated) so this puts the Latch into SET state, giving Q=1 and Q'=0. So everything checks.

" I dont understand how, as Q'=1 of ps is my input along with R=0 which gives next state output as 0 but is is supposed to be 1."

Q' is not a input in the normal sense, it is in the question to explain what the current state is so the next state can be determined.

EDIT

From the gate level perspective Q=0, Q'=1 the feedback is keeping it in this state. Then S=1, R=0; it is all in the timing of the events. When S gets pulsed to a 1 Q' flips to 0. This cascades to the other gate flipping it Q to a 1.