How more efficiently can I write the test bench for a MOD 16 asynchronous counter using JK flip flop?
As your waveforms show, your 4-bit counter is not counting properly.  When I run a simulation, I see that only q[0] is toggling between 0 and 1.  The other 3 bits (q[3:1]) are unknown (x) throughout the duration of the simulation.  This is due more to a problem with the design than the testbench.
Module jkff_behavmodelling implements a synchronous reset for your flops.  The q[0] flop is reset properly because it is driven by the testbench clk signal.  The reset signal is properly sampled at the posedge of clk, which sets q[0] to 0.  However, The q[1] flop is not reset properly because it uses the q output of the first flop for a clock, and the simulator is not properly sampling the reset signal.
To fix this, use an asynchronous reset signal.  Change:
always @(posedge clk) begin

to:
always @(posedge clk or posedge reset) begin

In the testbench, you simply need to deassert the reset signal once, instead of toggling the reset signal.  When we make these changes and let the simulation run long enough, we see q counting down from 15 to 0, then repeating the sequence.
initial begin
    // Initialize Inputs
    clk = 1;    reset = 1;  j = 1;  k = 1;
    // Wait 100 ns for global reset to finish
    #100 reset = 0;    
    #4000 $finish;
end