Deriving the Transistor Width for NOR
Design of digital CMOS blocks typically goes something like this:

L needs to be minimal in order to maximize speed (current needs to be large, and gate capacitance needs to be small).

If you make W larger, then the gate capacitance will increase, causing the speed at the input to be slower than before. At the same time, the speed at the output will increase because the current is increasing. Therefore, the most interesting W is the minimum width that still satisfies the output a minimum required rise and fall time. For this you need to know the load capacitance \$C_L\$.

The basic transistor model equations look like this (nmos):

\$i_{DS} = K_n\frac{W}{L}(v_{GS}-v_T)^2\$ (saturation)

\$i_{DS} = K_n\frac{W}{2L}((v_{GS}-v_T)v_{DS}-\frac{v_{DS}^2}{2})\$ (triode)

\$K_n = \frac{\epsilon_{ox}}{t_{ox}}\mu_n\$

For digital signals, the transistor is more likely to be in the triode region due to the high \$v_{GS}\$, making the transistor behave more like a resistor of:

\$R_{eq} = (\frac{\partial i_{DS}}{\partial v_{DS}})^{-1}|_{v_{DS}=0} \approx \frac{2L}{K_nW(V_{DD}-v_{T})}\$

This resistor forms a low-pass RC circuit with the load capacitance. The fall time of this RC circuit is:

\$t_f \approx \ln(9)\cdot R_{eq}\cdot C_L\$

If you assume that the transistor is in the saturation region, then you can also derive a similar approximation:

\$i_{DS} \approx K_n\frac{W}{L}(V_{DD}-v_T)^2\$

In this case, the ramp is linear and you can find that

\$t_f \approx \frac{C_L\cdot 0.8V_{DD}}{i_{DS}}\$

The speed of the input will have an effect on how the output changes, but this probably takes it too far. The equations for PMOS transistors and rise time are identical as long as you replace \$K_n\$ by \$K_p\$.