Designing a State Machine
Input Present St. Next St. Output in Binary
       0      00        01       000
       0      01        11       001
       0      10        01       001
       0      11        10       111   
       1      00        00       000
       1      01        00       001
       1      10        00       001
       1      11        00       111   


I'd rearrange truth-table.  3 inputs, 5 outputs (2 for state).

Lower bit, OR of present state.  Upper bits AND of present state.