How to minimize the size a microcontroller implemented on an FPGA?
I'm assuming that you are performing a data processing operation on 1500 16 bit words.

In general FPGAs allow the trade off of reduced area for decreased speed and increased complexity. 

Let's say your algorithm was autocorrelation which is something that has n2 complexity, and would fly at 100 elements but take forever at 1500 elements (225 times longer). 

In an FPGA you could design a small module that would hold a sample counter, an offset counter, and an accumulator. The sample counter would go up once per every few clock cycles, the offset counter would go up once per loop of the sample counter. The sample counter would be one address into the data, and the offset + sample counter would be the other address. The product of the two would be added into the accumulator. At the end of the sample counter loop, the result would be written into the output data buffer, and the accumulator cleared.

This is probably the minimum area implementation. If it's fast enough, great, but if not you have flexibility that you did not have in the microcontroller. You can pipeline the design to make sure that you get one multiply accumulate per clock. You can make sure you are using block rams and hard multipliers for fastest Fclk from the synthesizer/place-and-route tools. Finally, you can increase parallelism, at the cost of area. You could add an additional multiplier to perform more than one operation at a time. This will double throughput, but also double memory bandwidth.

This is all much much harder than writing microcontroller code, but you have so many degrees of freedom, that you can converge on an optimal solution.