Accessing rows of an array using variable in Verilog
Part selects in Verilog can use variables, as long as the width of the select is a constant.  The solution here is to user a lesser-known part select syntax, where you specify the offset and the size.

DATA_OUT = char_font[2*ROW_NUM+:10]; // +10 due to Big Endian


The above selects 10 bits starting at bit 2*ROW_NUM



Excerpt from the SystemVerilog LRM, IEEE 1800-2012


  An indexed part-select is given with the following syntax:

logic [15:0] down_vect;
logic [0:15] up_vect;

down_vect[lsb_base_expr +: width_expr]
up_vect[msb_base_expr +: width_expr]

down_vect[msb_base_expr -: width_expr]
up_vect[lsb_base_expr -: width_expr]

  
  The msb_base_expr and lsb_base_expr shall be integer expressions, and the width_expr shall be a positive constant integer expression. Each of these expressions shall be evaluated in a self-determined context. The lsb_base_expr and msb_base_expr can vary at run time. The first two examples select bits starting at the base and ascending the bit range. The number of bits selected is equal to the width expression. The second two examples select bits starting at the base and descending the bit range.