Codec in 'master mode' require more than one external clock? (MCLK?) to drive I2S system timing to/from MCU slave?
Generating the other clocks is the whole point of master mode, so that is indeed what an I²S chip is likely to be doing.
But if you want to be sure, read the datasheet of your codec. For example, the CS4245 one says:


  4.2.3 Master Mode
  
  As a clock master, LRCK and SCLK will operate as outputs. The two serial ports may be independently 
  placed into Master or Slave mode. Each LRCK and SCLK is internally derived from its respective MCLK 
  with LRCK equal to Fs and SCLK equal to 64 x Fs.


The I²C bus has its own clock line, and the I²C protocol allows both master and slave to delay clock cycles, so it's impossible to demand that it be synchronous to anything else. But again, read the datasheet, which will say something like this:


  4.12 Control Port Description and Timing
  
  […] The operation of the control port may be completely asynchronous with respect
  to the audio sample rates.


Some codecs might require that a valid master clock is present for the I²C to work.