Getting around two dimensional array prohibition
Two dimensional arrays are perfectly allowed in Verilog. They can be mapped to registers or memories. 

Two dimensional arrays are not allowed in ports. For that I would recommend you switch to system Verilog. 

What is not possible to synthesize, in either language is "column" access. 

// array of 16 register each 4 bits wide.
reg [3:0] two_D [0:15];
...
   // This is fine 
   for (row=0; row&lt;8; row=row+1)
      my_row = two_D[row]; 
   // You can also take a slice from that:
   assign top_right_2bits =two_D[0][3:2]; 
...
   // Column access only works in simulation
   for (col=0; col&lt;16; col=col+1)
      my_col = {two_D[3][col],two_D[2][col],two_D[1][col],two_D[0][col]};


For details you have to look-up packed versus unpacked arrays.