Is it fine to have different number of input/output port in module and module instant in verilog?
When using Port Order connections, the ports are connected in the order declared by the module, and any unused ports are left unconnected (Z). 

Instantiating by Port Name connections helps avoid this kind of problem.

Your code is interpreted as this:

D_ff dff_instance (  
        .q     ( q     ), // first port
        .qbar  ( ~q    ), // second port
        .d     ( clk   ), // third port
        .clk   ( clear ), // fourth port
        .clear ( 1'bZ  )  // fitfh port has no connection
    );


Clearly what you intended was this:

D_ff dff_instance (  
        .q     ( q     ),
        .qbar  (       ),  // unconnected output
        .d     ( ~q    ),  // toggle by driving dff_instance.d input from ~q
        .clk   ( clk   ),
        .clear ( clear )
    );


If you are using an older verilog compiler that does not support Port Name connections, skip the unused port by two commas:

D_ff dff_instance ( q, , ~q , clk, clear); // qbar output port is unconnected


The Port Name connection style does require more typing, but makes the code easier for a person to read and understand, and more robust against connection errors.