How can I make this VHDL code synthesizable and more neat?
change &quot;wait until rising_edge(clock)&quot; into an if statement.  Some synthesizers don't support &quot;wait until&quot;

The code uses a &quot;when&quot; statement inside of a process.  This is only going to be supported in VHDL 2008 or newer.  If your synthesizer even supports VHDL 2008, it may not be enabled by default.

The code uses a lot of &quot;= '1' &quot; in the logic.  This is not necessary.
  x &lt;= '1' when (y = '1' and z = '1') else '0';

Is equivalent to...
  x &lt;= y and z;



I would suggest the following...
process(clock) is begin
    if rising_edge(clock) then
        if state(7) = '1' then
            b(0) &lt;= (a(0) and a(4) and a(6)) or (not a(6) and not a(5)) or (not a(6) and a(5) and not a(2));

            b(1) &lt;= (not a(4) and a(6)) or (not a(5) and not a(6));
            
            b(2) &lt;= (not a(0) and a(4) and a(6)) or (not a(1) and not a(4) and a(6)) or (not a(2) and a(5) and not a(6)) or (not a(3) and not a(5) and not a(6));
        end if;
    end if; 
end process;