Instantiate sub module according to input value
No, that's not how Verilog works. Verilog is a hardware description language. You don't create new hardware based on input values. You specify the hardware that you need and its behavior changes based on input values.

Similarly, all of the parameters needed to define the hardware must be known at synthesis (compile) time. Loops that generate hardware must have a known number of iterations. This is just how hardware synthesis works.