Invalid inputs in a SR Latch & Enabled SR Latch
"Lets consider a SR Latch built with NOR gates. The invalid inputs are S=1, R=1. With enabled latch [gated latch], the invalid inputs are same, S=1, R=1."

That is true only when the gating does not invert the signal (for instance two AND gates).

"Now, lets consider, NAND gates, in SR Latch, the invalid inputs are S=0, R=0. But in enabled SR latch, the invalid inputs are S=1, R=1"

Correct, because the gating inverts the S and R signals.

"So, can I say, invalid inputs with SR Latch with NAND are: S=1, R=1"

Correct

"If enabled, then S=0, R=0"

That is half-true. You should be able to formulate the fully-true answer by yourself.