How does the Intel 8086/88 know when to assert the IO/M signal?
Thanks to my suspicions based on a past (and future?) life in Z80 ASM and a quick search for 8086 io, I found a handy synopsis of 8086 I/O at this page by Dr. Jim Plusquellic (hooray for free lecture notes!) - http://ece-research.unm.edu/jimp/310/slides/8086_IO1.html - which I'll now try to... synopsise even more handily.

As his page explains, the 8086 has two available modes of I/O:


memory-mapped
"isolated" a.k.a. standard


In the latter case, a special set of instructions must be used - IN, INS, OUT, and OUTS. These cause corresponding signals to be output on the M/IO (Memory or I/O) and R/W (Read/Write) pins. That page indicates the difference and how these can be wired up:



As the Prof. explains, using this mode avoids using up normal memory ranges for I/O, with the caveats that:


it increases circuit complexity: you must wire up the mentioned pins to disambiguate between the two possible meanings of an address and direct each to the right destination. In doing so, you conceptually create the 'virtual pins' IORC or IOWC (I/O Read/Write Control) shown in the diagram.
it limits the instructions you can use for I/O to the 4 mentioned, rather than letting you do all kinds of acrobatics with normal memory loads/stores/etc., as you could under memory-mapped I/O (assuming the target device will tolerate them!)


So, the reason the 8086 and friends know when to assert IO/M is... because you tell them when, by using one of their dedicated I/O instructions.