Is there a risk for the HW to debug an embedded software if the JTAG integrity is bad?
It is unlikely that you will damage the part, but you may not be able to successfully or usefully use the connection to debug the device.  You will never be certain that you are seeing a software error or a failure of your debugger, since some failure modes can result in failure of the debug interface in any case.

Signal integrity issues can often be resolved by reducing the JTAG clock rate.  This will effect the performance of software loading and large memory dumps or data watches, but for simple breakpoint and stepping debug will remain usable even at relatively low frequencies.  If you are already seeing 60% error, you will be no worse of reducing from 10MHz to 4MHz for example, and it may drop to zero.  I suggest trying 1MHz as a starting point.  If the performance is unsatisfactory you could try increasing it incrementally to determine the maximum error free rate, similarly if you still get errors reduce it further.

In general the JTAG cable should be as short as possible (&lt;20cm as a guide) - preferably the probe manufacturers original cable without adaptors or extensions.

When this question was posted on SO, you added a comment that the probe was a Blackhawk USB200 - the product has an optional isolation adapter for harsh environments to prevent ground-loop issues.  That may solve your problem entirely.

Finally, are you certain that the error rate is due to noise?  A common enough mistake is to access the pins used for JTAG as GPIO in the software for example.