FPGA temporal partitioning
Yes, these things exist in the wild, but they are nontrivial to use.

The easiest case is full reconfiguration. The configuration memory stores multiple different variants, and you use the on-chip reset logic to restart the chip and load a different programming file. All internal state is lost, and the chip goes into the reset condition for a brief time.

If you can live with that, this is fairly easy to implement -- all you need is a larger configuration flash, and an instance of the dynamic reconfiguration hard IP block -- you tell it which image to load, and give a start signal, and you are done.

Proper partial reconfiguration also exists in mid- to high end FPGAs, here you can create partitions before compiling your design, and the fitter will respect partition boundaries, so you can load individual partitions' contents independently.

That is generally only available with an appropriate license, and not entirely easy to use, but it allows a partition that is not being reconfigured to continue running while another is reloaded.