maximum clock frequency for a sequential circuit
No. Your reference points are the rising edges of the clock signal. Everything starts and ends there.

Therefore, to calculate the minimum clock period, you start with the Tcq of any FF, add all of the logic delays leading to the input of any other FF (including itself), and add Tsu last. Use the maximum values of each delay for this calculation. In this circuit, there are three separate paths you need to consider.

Then, you go back and add up the minimum delay values (sometimes called "contamination delay" in modern texts) to verify that Th is also met on every FF.