prevent metavalues for input ports in VHDL simulation
I'm pretty sure you have to assign the whole record.  In the past I've created initialisation constants for my records which ease this problem.

As a workaround (in Modelsim at least, probably Aldec as well) you can use a small TCL function to start off your simulation.  This function can disable those warnings, run for 1 ps, then re-enable the warnings and run the rest of the simulation.