DAC/ADC lines length matching
How to calculate it.

The DAC expects data with a timing reference with respect to the clock. The data may change before the setup time has expired, but must remain valid afterwards. The data may change after the hold time has elapsed, but must stay valid before. This gives you a 'valid' window, and a 'may change' window.

As a first step, arrange the FPGA to change the data in the middle of the 'may change' window with respect to the clock. Make sure the FPGA uses the correct clock edge. Some FPGAs contain I/O timing modification registers, and clock retiming servos to help (or complicate) this.

Now you've done this, see what effect the FPGA propagation skew has on your timing window, it will have eaten into your timing budget a little.

Now you can see what your setup and hold times are at the start of the interconnect. This will give you an error budget for the tracking skew. Now you can tolerance the lengths of the lines. Remember the speed of light is about one foot/nS in air, about 70% of that on PCB.

Wiggling the lines is the last thing a layout designer should be doing. The first thing is making sure there is an intact ground plane route from the FPGA to the DAC that runs parallel with the clock and data lines to assure data integrity. The zeroth thing is making sure that currents induced by the data transitions do not create voltages across the DAC references or analogue outputs. Most DACs have pinnouts that are pre-thought-out to make this possible.