What is the output when D and C on D flip flop are connected?
If you look at the schematic of a D-Flip flop ...


You can see it is just a simple set-reset flip flop with some logic stuck on the front.

Under normal conditions, only one of those first two Nand gates will generate a 
pulse to the appropriate side of the flip-flop when the clock is pulsed. Which one it is, is determined by the state of the data line. As such, the data line needs to be established AND held while the clock pulse is processed.

If the data changes at the same time as the clock odd things will happen.

Notice the inverter in the circuit above. Because that invertor has an inherent delay, it can mean that BOTH set and reset are applied at the same time to the flip flop. The latter can then enter a metastable state and oscillate. If that happens at the lead edge it will settle out when the inputs have had time to propagate. If it happens on the falling edge of the clock, the outputs can oscillate indefinitely and their final state can not be relied upon.



An edge triggered D-type flip-flop / latch is even more complex and metastability can occur at the clock edge itself and stick around till the next clock and again the output is indeterminate.