Driving ADC's CONV input at the falling edge of SCK
Take a snap shot of the timing diagram and mark it up (in red) with what the data sheet tells you in the timing table is my recommendation: -



The above (I believe) answers all your questions.

I would drive CONV on the falling edge of clock-cycle 34 and ensure that at least 1.2 ns elapses before clock-cycle 1 rises (apologies for this correction).