Design a Counter With an Arbitrary Sequence
If you write down the mapping of count states 0-7 to outputs 

count             oputput
C2 C1 C0          O3 O2 O1 O0
0  0  0           0  0  0  0    =  0
0  0  1           0  0  0  1    =  1
0  1  0           1  0  1  0    = 10
0  1  1           1  0  1  1    = 11 
1  0  0           0  0  0  0    =  0
1  0  1           0  1  0  1    =  5
1  1  0           1  1  1  0    = 14
1  1  1           1  1  1  1    = 15


You see that
O0 = C0
O1 = O3 = C1
O2 = (C0 OR C1) AND C2  

So you can accomplish that simply with a 3 bit counter one OR and one AND gate:







simulate this circuit &ndash; Schematic created using CircuitLab

Note: there is, however, a so-called hazard between count state 5 and 6, 
i.e. there might be multiple edges before the signal settles to the new state. That won't be a problem if you don't care about output edges, only about levels.