How to extend a pulse in system verilog
As we have several people who say that it can't be done here is a behavioral solution :-)
Note that in real hardware it can't be done this way. 

module pulse_double(
   input      pulse,
   output reg double_pulse
   );

time time_rise,time_elapsed;

   always @(posedge pulse)
      time_rise = $time;

   always @(negedge pulse)
   begin
     time_elapsed = $time - time_rise;
     double_pulse &lt;= 1'b1;
     double_pulse &lt;= #(2*time_elapsed) 1'b0;
  end
endmodule


module pulse_double_test;
integer loop;
reg  pulse_in;
wire pulse_out;

   pulse_double pulse_double_inst(
    .pulse(pulse_in),
    .double_pulse(pulse_out)
   );

  initial
  begin
     for (loop=0; loop&lt;10; loop=loop+1)
     begin
        pulse_in &lt;= 1'b1;
        #(($random &amp; 32'h07)+32'h02); // width between 2 and 9 
        pulse_in &lt;= 1'b0;
        #20;
     end
  end
endmodule


With the waveform:



This is a simple solution which works for non-overlapping input/output pulses. If input pulses can overlap with the output you have to define what behavior is wanted and then adapt the code accordingly.