Creating high speed clock by power grid frequency via PLL
I suppose the 50Hz comes from mains. Since mains is rather noisy, the zero crossing point will most likely have substantial phase jitter. It would be better to use the entire wave and run that through a phase detector. Since you are already sampling the waveform, you can easily multiply it with I and Q sine waves in software, this will give you a much more accurate phase estimate. It also gets rid of the zero cross detection circuit.

Now, the PLL. Since you will most likely average several periods and use a low cut-off lowpass filter to extract phase and get rid of noise, you need a PLL with low drift over rather long time spans. Your XO-controlled PLL offers this...

However there is a much simpler way. You could simply run your ADC on a local XO clock, oversample a bit more (say, 40ksps instead of 10ksps) and do everything in software.

Basically you'd keep a phase counter (a kind of software PLL). Said phase counter is updated according to the phase detection done in software. Then use interpolation to resample the signal into what you want (ie, 200 samples per period).