How is clock signal edge detection done / pros and cons of different approaches?
Start with this datasheet of the SN7476/SN74LS6 flipflop
https://www.ti.com/lit/ds/symlink/sn54ls76a.pdf?ts=1606110683154&amp;ref_url=https%253A%252F%252Fwww.google.com%252Furl%253Fsa%253Dt%2526rct%253Dj%2526q%253D%2526esrc%253Ds%2526source%253Dweb%2526cd%253D%2526ved%253D2ahUKEwju3ZnD_JftAhXWIDQIHcmQCaEQFjAAegQIAxAC%2526url%253Dhttps%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fsn54ls76a%2526usg%253DAOvVaw24Im-NlvUeTXtlodaWgNIA
and notice the &quot;CLOCK&quot; input has some transistors hanging off that pin.
You will notice similar input gate routing for the 74LS112 FF.
Realize the propagation delays of those &quot;gates&quot; may not be the same across all the gates. Thus some detective work is needed.