How to use present and previous value of a signal for this VHDL code?
You have to register noisysignal1 once. Here is the resulting code. The register is noisysignal1_r. Then you can use y = noisysignal1*w1 + noisysignal1_r*w2.

I hope I understood what you want.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.all;
use IEEE.STD_LOGIC_Unsigned.ALL;

use IEEE.NUMERIC_STD.ALL;
entity random is
  generic
  (
    width : integer :=  32; 
    nn : natural := 1; --power of the binomial distribution &lt;16
    m : REAL:=0.0     -- mean output value
  ); 
  port
  (
    clk : in std_logic;
    random_num : out std_logic_vector (width-1 downto 0);   --output vector
    RST : in STD_LOGIC;
    DATA_OUT : out REAL := 0.0            
  );
end random;

architecture Behavioral of random is
  type arri is array (0 to 15) of integer;
  type arrr is array (0 to 15) of real;
  signal noisysignal1, noisysignal1_r : real;
begin
  process(clk,rst)
    variable rand_temp : std_logic_vector(width-1 downto 0) := (width-1 =&gt; '1', others =&gt; '0');
    variable temp : std_logic := '0';

    variable s1 : arri := (3,33,333,3,4,5,6,7,8,9,11,22,33,others=&gt;55);
    variable s2 : arri := (5,55,555,50,6,7,8,9,5,6,7,21,33,others=&gt;22);
    variable r : arrr := (others=&gt;0.0);
    variable s : real := 0.0;

    variable noisysignal : real;

  begin
    if rst='1' then
      DATA_OUT &lt;= 0.0;
    elsif rising_edge(clk) then
      noisysignal1_r &lt;= noisysignal1;
      temp := rand_temp(width-1) xor rand_temp(width-2);
      rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
      rand_temp(0) := temp;

      s := 0.0;
      for i in 0 to nn-1 loop    -- nn noise generators
        UNIFORM (s1(i),s2(i),r(i));
        s := s+r(i);
      end loop;
      DATA_OUT &lt;= 2.0*(s/real(nn) - 0.5) + m;
      noisysignal :=real (to_integer(signed(rand_temp))) + ( 2.0*(s/real(nn) - 0.5) + m);
      noisysignal1 &lt;= noisysignal;
    end if;
    random_num &lt;= rand_temp;
  end process;
end Behavioral;