Divide clock frequency by 3 with 50% duty cycle by using a Karnaugh Map?
Part1
A mod-3 counter with output high for only one state will work as a divide-by-3 system. But duty-cycle will be 1/3. The state table for which can be written as:
-------------------------------
PresentState  Output  Nextstate
-------------------------------
    0 0         0       0 1     
    0 1         0       1 0      
    1 0         1       0 0
-------------------------------

This system needs two flip flops for implementation. We need to find out what should be connected to the inputs (D) of these flip flops. This is where K-map is needed. We have the table. Just translate to k-map and solve for Ad and Bd. (You actually don't need a K-map to solve for a 2-variable logic)
Part2
To make the duty-cycle 50%, the output should be high for 1.5 clock cycles instead of 1. If we can make a circuit that can shift the input signal by half a clock period (as BQ and CQ in 2nd figure), then ORing the input and output of such a circuit can give the required 50% duty-cycle.