synthesizable reg assignment + other questions
In verilog, reg does not represent synthesisable storage, it is more of a software construct in the language - its also used in case statements.

If you want an actual flip-flop, you need to follow this pattern:


  always @(posedge clk or negedge reset_n)
    if(!reset_n)
      data_reg &lt;= 4'b0000;
    else
      data_reg &lt;= data_input;


and, yes, you can assign any wire (output or not) from a reg (combinatorial or sequential).

Wherever you have initial, it is very likely you have something which is not synthesisable. Silicon has no concept of when initial should occur, so with initial you are maybe anticipating an earlier operation (like writing an image to FLASH memory), or relying on an FPGA synthesis flow inserting some reset initialisation for you.