What is the difference between an array and a bus in Verilog?
A bus enables you to define values that are wider than one bit. If you want to store or transmit (in parallel) a value between 0 and 15, you need a 4-bit bus. An array lets you store multiple values under a single name.

The difference between "[7:0] data" and "data[7:0]" is that the first is a single 8-bit-wide value while the second is eight single-bit values.

It's totally normal and useful to create an array of busses. They're sometimes called memories, because you can use them to model ROM or RAM. Your synthesis software can usually recognize when you've defined something that looks like ROM or RAM (for example, reg [7:0] data[1023:0] is basically 1K by 8-bit RAM) and synthesize it as actual physical ROM or RAM on the chip.

To understand which construct to use, just ask yourself what you have. Do you have a single multi-bit value? That's a bus. Do you have a bunch of single-bit values that you want to reference using a single name? Then use an array. Do you have a bunch of multi-bit values? Then use a memory.