My VHDL doesn't detect all transitions of a signal
Incoming signals that are asynchronous to your FPGA must be synchronized to your FPGA's clock domain by running it through a chain of at least two flip flops before using it with any synchronous logic. Or else nothing guarantees that the incoming asynchronous edge does not land on an FPGA clock edge resulting in metstability. The chain of flip-flops reduces the chances of metastability so that they are vanishingly small. This does add latency.

That's why it works in your simulation but not in real life.

I recommend you write a separate component dedicated to synchronizing. Also one that outputs a single clock enable pulse for edge detection. Then connects those as components to or within your other entities that youy write. They come up a lot and it saves time and keeps your entities clean.

My edge detector component has an clock enable output for both rising and falling edges and my synchronizing component lets me select how many flip flop chains I want.