Inherent sample and hold in a comparator?
Whoever told you that was mistaken. The papers you cite are talking about "latched comparators" that are specifically designed to have internal storage of their state. These are specifically designed to support ADCs.

The reason most ADCs require sample-and-hold circuits is that they require a certain amount of time to make a conversion, and the analog sample must remain stable for that period of time, or else the output bits will be inconsistent.

Flash ADCs (at least theoretically) take zero time to make a converstion, or put another way, they are converting continuously. If all of the comparators had precisely the same delay, and you didn't have to worry about metastability, you could capture their outputs at any time and directly convert the results to a binary number.

In practice, you do need to worry about metastability, since the comparator outputs can change at any time, and the digital logic that follows has a clock associated with it. Also, the comparators do not all have the same delay. So, either a short sample-and-hold circuit is used ahead of the comparators, or else two-stage synchronization along with an error-tolerant form of thermometer-to-binary conversion logic is used at their outputs.