SystemVerilog FIFO problem with 6 bits in and 4 bits out
What you need is a FIFO with different input and output bit widths. This can be achieved with an array using two index pointers and a register keeping track of the numbers stored bits. The pointers will wrap around. The bit with of the stored bits need to be a common multiple of the input and output widths.

Here is some SystemVerilog code to get you started. Not fully tested or optimized, and I omitted the logic for empty / full / error (overflow) for you to figure out.

always_ff @(posedge clk) begin
  if (!rst_n) begin
    in_idx &lt;= '0;  // input pointer
    out_idx &lt;= '0; // output pointer
    bitcnt &lt;= '0;  // number of stored bits
    out_vld &lt;= 1'b0;
  end
  else begin
    bitcnt &lt;= next_bitcnt;
    if (in_vld) begin
      store[ in_idx +: 6] &lt;= in;
      in_idx &lt;= (in_idx + 6) % STORE_BITS;
    end
    out_vld &lt;= (bitcnt &gt;= 4 || in_vld);
    if (out_vld) begin
      out_idx &lt;= (out_idx + 4) % STORE_BITS;
    end
  end
end

always_comb begin
  next_bitcnt = bitcnt;
  if (in_vld) begin
    next_bitcnt += 6;
  end
  if (bitcnt &gt;= 4 || in_vld) begin
    next_bitcnt -= 4;
  end
end

assign out = store[ out_idx +: 4 ];