Using the PS/2 port of the Papilio One FPGA from VHDL
PS/2 uses a 10 KHz clock, so connecting an LED to the clock or data lines will just result in the LED appearing always on at a brightness corresponding to the signal duty cycle. 

Have you tried simulating the example code with the ISE simulator? That would at least tell you that the clock and data outputs are doing something sensible.  

Update
If I'm understanding the second code correctly:

The CLK signal is a 32 MHz clock
The PS2_CLK signal is a 10 KHz (PS2 allows between 10 and 16 KHz apparently - do you know exactly what this signal is?) which is generated... somewhere?

The second piece of code you posted is going to:


Initiate the counter at 0, PS2_CLK_PREV at 1
On every CLK rising edge (ie at 32 MHz), the process will run


The process you've defined will increment the counter whenever PS2_CLK has changed.

So the counter will be incremented once for every positive and negative clock transition on PS2_CLK (ie at 20 KHz).

The counter will increment until it overflows and goes back to 0. As it's 14 bits, that means it will take 16384 increments, which at 20 KHz increment rate (twice per clock cycle) is 0.819 seconds.

Your LED is only 1 when the counter is 0, which will happen for 5 uS every 0.819 seconds. That's not long enough for you to notice it turned on, and so the LED is essentially 0.

If the LED is appearing to be constantly turned on, it means that the counter is constantly at 0. That suggests that PS2_CLK always equals PS2_CLK_PREV, which suggests that perhaps your PS2_CLK isn't doing anything. I'd suggest looking at what's driving that clock signal (is it a DCM that you've instantiated? A simple clock divider?)