How does the bootstrapping capacitor in this diagram operate
\$V_B\$, is the boost voltage required for dual N-channel half-bridge switches. The high output side, (HO) Nch FET needs a gate voltage higher than Vdd to activate RdsOn.  It generates this voltage from a charge pump using the LO side PWM high-frequency pulses.  THe Cboot cap AC couples this signal then is cathode clamped to Vdd such that the pulses now ride above Vdd. Internal to the IC, they are then rectified by an internal diode Anode and small internal capacitance to create HO +ve pulses.

The +ve current discharge pulses are shown in blue to Q1 below, while the -ve charge pulses are pulled down by Q2 to 0V.
 

More details Ref: https://www.onsemi.com/pub/Collateral/AN-6076.pdf.pdf


My estimate of Cb is >5x the Ciss of Q1, but there are more complex computations of ideal.  
It is also critical that Q2 has a good diode clamp to 0V to prevent -ve pulses on output Vs to load, so that it does not pull down the boost voltage Vs.  This may occur by excessive effective series inductance (ESL) of Q2 source to ground layout.