How would I finish out this mini project (emitting 1 whenever 101 is read)?
Confession

I'm not classroom-trained on Mealy and Moore. I'm only "book-read" and, prior to that reading, only had lots and lots of basic practice from making things work using state machines (obviously finite) without bothering to assign names to what I did. I just knew some thinking tools, is all, which worked well.

Tony's circuit, so far as I understand it, is a Mealy FSM, not Moore. Except that he "registered" the output, which I think allows it to fit the Moore machine definition. I'll explain why I think this, using definitions I find on the web and his schematic to make the point. But keep in mind I may be wrong in my interpretations and I'm very much open to being taken to task about what follows.

State Diagram

I completely ignored your writing about your approach. It's a lot easier for me to use tools I know and understand well. Here is the result of my first step in thinking about what you wrote -- focusing only on the comment about "101."



The labeling of the states shows the prior two bits. The labeling is most recent bit on the right and prior bit on the left.

This diagram includes some states you didn't include, showing the initial transition from "no bits seen" to "one bit seen" and then to "at least two bits seen." You probably want to ignore those initial states that lead into the inner four states shown above. Which is fine. I just wanted to point out how I "think" about these questions when I first face them.

Here, you can see the four states you arrived at but from a slightly different approach. I'm just tracking the prior two bits as a pair and then showing the incoming bit as a transition between states.

Finally, I've included a red star to indicate the important transition where "101" is recognized. (The prior state pair must be "10" and must be followed by observing a "1" as the transition.)

Here is a distilled version:



Which is probably more like what you want to achieve.

State Pair

The pair of D-type FF required for the most recent and also the immediately prior bits are shown on the upper diagram. The lower diagram shows the completed result that Tony pointed out.







simulate this circuit &ndash; Schematic created using CircuitLab

Note that this schematic requires both the current state information (the two FF shown in the upper diagram) as well as the current input (shown in the lower diagram as a wire coming from DATA to one of the inputs of the 3-input AND gate. It is only when the current state and also the input meet some criteria, than the correct output status is latched. Normally, I believe this makes the result qualify as a Mealy machine, not a Moore machine. But the fact that this is a "registered Mealy machine" is what makes it a valid Moore machine.

You could do this more directly as a Moore machine, I suppose. But I think this qualifies.