What options are available to sniff LVDS communications?
Are you pushing the link to its limits (data-rate, noise immunity etc)?  

If not, can you just hang another FPGA LVDS pair off each of the TX/RX pairs?  Use a high-end eval board, some simple code to dump the 1s and 0s into a buffer and then squirt them to a PC over Ethernet/USB/whatever for analysis.

I'm not aware of anything off-the-shelf for this (but I'd also like to hear if there is :)