Having trouble with determining why my XNOR transistor circuit is not behaving
Please review my RTL NOR answer provided a while ago for detailed design and simulation information about RTL gates. In particular, the dual-stacked BJT form of a NAND gate as shown in your drawings is crap. I'm not going to belabor the details why, here. I'll just let you learn from experience on that one, for now. We've other fish to fry.

If you look at the Apollo Guidance Computer Schematics from many decades ago when RTL was used, you'll essentially one and only one kind of gate being used: NOR. There's a good reason for this and you can first read through my RTL NOR answer thoroughly and then attempt to design an equivalent 1-BJT NAND or AND or OR gate and see how well you fare at the problem.

If you want to make a reliable, well-designed XNOR out of RTL, you can do this with six transistors (plus one to buffer your LED and maintain the "sense" (ON when XNOR output is HIGH and OFF when XNOR output is LOW.)







simulate this circuit &ndash; Schematic created using CircuitLab

Using the design from my RTL NOR answer, you'd find the following schematic:







simulate this circuit

That circuit will work fine as an XNOR. And it will do so within managed specifications, too. 21 resistors, with only two different values, and 6 BJTs (only NPNs) for the XNOR. Plus another BJT and 2 resistors and LED for the display output. Probably about \$4-5\:\text{mA}\$ when the LED is OFF and perhaps \$25\:\text{mA}\$ with the LED ON. So, as an XNOR gate itself (no LED) it dissipates about \$100\:\text{mW}\$.

(The inverters above can be further minimized (but with some loss of management) by removing their input pull-downs. But I'd prefer you keep them in place.)