Actual speed of clocks in FPGA?
Your problem is in your choice of test equipment. An oscilloscope is generally not intended to be used as an accurate frequency-measuring tool. An oscilloscope can be used to verify that a signal is of approximately the correct frequency, but because frequency measurement in an oscilloscope is usually done by measuring the period of one cycle of the signal, it cannot be very accurate.

To verify that the clock is operating correctly, using a divider chain, as suggested by Brian Drummond and Dmitry Grigoryev in the comments, to slow down your clock is required to make it visible to your oscilloscope. This should be very easy to implement inside the FPGA and then output the divided-down signal to an I/O port. However, at only 25MSps (I assume, given your question. If this is an input bandwidth of 25MHz, you've got a better 'scope), you have a 4 ns uncertainty in the timing of the slower clock edges.

To verify the exact frequency of your FPGA clock source (frequency accuracy is necessary when sending signals to other devices using e.g. Ethernet, USB), you will need a frequency counter. These devices count the number of transitions a known internal time or measure the period between two transitions, then average the result to produce the resultant measured frequency. If you want to measure the parts-per-million frequency error in your FPGA's clock source frequency, you will need a calibrated frequency reference inside your frequency counter.

The PPM error in crystal frequency is caused by factors such as manufacturing tolerance, temperature, and aging. Generally the manufacturer will specify the typical and maximum errors in frequency for a device. Some devices will come in multiple precision grades where some devices are specified to have lower error.