Why aren't SRAM modules laid out in a matrix?
First, don't confuse the interface (multiplexing the address lines) with the internal arrangement (laying things out in a matrix). 

All RAM chips use a matrix a the the lowest (single bit cell) level, most use a less regular layout at the higher level (for instance two separate banks).

Multiplexing the address lines reduces the number of pins, but it has a cost: supplying the two halves of the address with the associated clock signals takes time. When this time can be matched with things that must be done inside the RAM chip anyway this is OK, but when it would slow the chip down this is a big performance problem.

SRAM can be 'directly addressed': the N bit address is decoded into 2^N select signals, that each activate a word of bit cells. (AFAIK this is not how modern SRAM really works, but it was true some time ago).

DRAM is addressed by row/column, because it eases the refreshing that is required: when you address one row (or was it a column?) all cells in that row are read and written back. Next you can (but don't have to) select one column and you get the values of the selected bit cell(s). So the row/column distinction maps nicely to the refresh hardware and process that must be present anyway.