How do ASIC designers approach designing for extremely low supply voltages like 0.3V?
I think you may have confused energy and power. One major component of power consumption in CMOS digital circuits is the power required to switch signal capacitance, and this power is proportional to \$f\times V^2_{DD}\$.
However, energy is the integral of power over time. If you reduce the power consumption by half but need twice as long to perform the same computation then the energy remains the same.
The trick is to reduce power consumption while keeping the clock frequency high. If you are going to reduce the power supply voltage, you need to also decrease the transistor threshold voltage to be able to switch the capacitances quickly. It's difficult to precisely control the threshold voltage, so in some cases the MOSFET body voltage will be controlled dynamically to adjust the thresholds in real time.
However, at some point the power lost due to subthreshold leakage overwhelms the power gained by decreasing the supply voltage. It is not an easy game to play.