How to wire output buses together
Purely answering how to create a parametrised width zero. hopefully another answer can cover the best practise for multiple drivers. 

localparam DATA_W = 8;
i = {8{'1b0}} ;


or

i = 'b0 ; //RHS width is matched to LHS, early version limited to 32bits


or 

i = '0;  //Introduced in 2012 SystemVerilog simplest way to x every bit : 'x