Why is the source voltage 1/4 of the supply voltage applied to the drain in a voltage-divider JFET circuit?
How is the equation VS = VDD/4 derived?


You need to bias the gate below the source.

And the output amplitude at the drain will only be limited to the difference between Vdd and the bias voltage on the drain.

So you choose your resistors to give you \$V_s \approx V_{dd}/4\$ to roughly maximize the possible output amplitude while allow a reasonable range of input amplitudes.


  What causes the difference between the simulated and calculated values? Is it because of additional factors (like wire resistance) that the simulation software considers when showing the simulated results?


The simulator doesn't consider wire resistance.

But it does use a much more complete model for the JFET than whatever you used for pen-and-paper calculations. This is probably the main reason for the difference between the simulation and the calculation.

In fact, you arbitrarily assumed values for ID, VDS, and VGS, so I'm not sure what model for the FET you were using. Generally you should have to do some calculations to get one of these three values after choosing the other two.


  Is there another way to find the calculated resistance/voltage values without having to use the aforementioned VS equation or the graphical method?


Practically, you can fire up the simulator and do some parameter sweeps to pretty quickly find appropriate resistor values for this kind of circuit.