What is the intended usage of "WE" or "PE/OE" pins on 4517 shift register
The two most basic configurations for this circuit which I can think of are:


Variable length shift register (middle taps are used as outputs)
64 bits serial memory element with x4 write speed (middle taps are used as inputs)


The above two are the most basic, and the middle taps are used for a single purpose in each of them. In 1, WE signal should not be asserted at all. In 2, the logic driving the middle taps should become a high impedance when WE gets deasserted.

We can find the application in which the middle taps will be used as both inputs and outputs: if you are using pins D, 16, 32 and 48 of both packaged registers (total of 8 pins) as inputs, and pins 16,32,48,64 of both packaged registers (total of 8 pins) as outputs - you get a 8-bits wide serial memory element. This memory can sample a Byte of data off the bus and put a Byte of data on the bus. If you are using a single bus for both reading and writing (which is usually the case), the fact that outputs go high Z when you assert WE is very handy - you can connect the bus directly to the inputs/outputs without any additional tri-states. Just make sure you are gating the clocks to both registers when you neither want to sample data off the bus, nor put the next sample on the bus.