How was physical design verification accomplished before CAD?
Too give the best chance of a device working as expected in an asic cell library we used to work in a system of increasing abstraction. 

The spice models for the technology would be written based on mos transistor theory and verified against a test chip which contained a few devices. The Transistor theory always seemed to be fairly accurate but we were not dealing with sub micron technology  with a bunch of secondary effects at the time.

This spice model would be used to develop the rest of the cells in the library. These cells would be put on a test chip. This would be manufactured out at the "corners" of the technology. This involves deliberately introducing manufacturing variation (doping,geometry etc) to give fastest and slowest cases. The test chip would be evaluated to produce the digital simulator models which would be used for individual device design.

I don't go back to the days of rubylith but I can remember doing manual checks of cell connectivity on coloured transparent prints (one per layer) before computer CVS (connectivity verification by computer). Took a few days for a 3k gate asic. 

In the earlier days when the whole thing was done by cutting rubylith getting and measuring the right dimensions was critical, but the devices were very simple. In the early days of CAD the cells were put down as cells in cookie cutter form and by that stage we were able to assume that the computer generated geometries within a cell and for connectivity were correct.