DC/DC step-down regulator destruction because of inductive load?
I think there are two approaches that must be considered;

1) Accurate current detection to simulate the Over-Current-Protection (OCP) design of the chip.
   - Assuming I understand, (big assumption) it consists of a 3 Amp comparator (not sure when/if it is sampled) and a 6 bit binary counter (/64) that must complete before OCP , shuts the regulator off into hiccup mode. However any 2 consecutive clock cycles less than OCP threshold can reset the counter may have some condition that you need to avoid such as the ratio of 2.5MHz and your choice LC resonant frequency for choice of components.  Confirm with the OEM tech forum how the IC actually counts within each cycle.

2) Scope critical points and observe responses in 4 channels before it fails using ideal probing methods ( Low ESL). 
  - Then model and analyze  the actual RLC component parameters for every component including avg RdsOn of switch and cross-talk and analyse in time &amp; frequency domain for gain/phase analysis and look for unstable oscillations. Consider different LC values. ( such as those suggested in datasheet, 470nH for 3.3V)