SPI and ADC timing diagram
From the data sheet (p. 17 at the top) "With DRDYIN low,
a falling edge at the data-ready signal output (DRDYOUT)
indicates that new conversion results are available for
reading in the 96-bit data register."

Delta 2, would indicate sampling frequency, as the data in the register
isn't ready to serve unless the chip sends the signal that the data is ready.