Finding transistor width for equal rise and fall times
They are optimizing the circuit for 'worst case' delays.We need to have nearly equal worst case delays in both pull-up and pull-down networks.

Also you may know that both rising and falling delay varies with varies with various inputs.Ideally we aren't concerned about the transistors in parallel as that would not cause the largest delay.

In pull-up network, the worst case delay would be when B=1,A=C=D=0. Which is where we see three PMOS(mobility nearly half that of nmos) in series. 

In pull-down network, the worst case delay would be when either A=1,B=C=D=0 or A=0,B=C=D=1. Which is where we see equivalent to one NMOS(size 1) connected to ground. 

Hope this helps!