Sample and hold circuit giving distorted output
Using a transmission gate or Analog Switch

The S&amp;H design specs MUST be done before any serious design; e.g.
Vin  range, f range, Zs  source impedance, aliasing filter requirements, sampling rate SNR, N bits accuracy and sampling error  i.e. a total error budget
Here I  will just highlite sampling errors.
For example if Analog Op Amp has a current limit or emitter resistor of 220 Ohms, it will result in a rise time to 64% of target = RC during the sample time

choose the smallest C that does not decay more than dV in dt due to buffer bias current
choose the lowest CMOS  input bias current.
choose non-piezo electric caps like plastic MF or NP0/C0G as all others* have a &quot;memory&quot; effect  (ceramic*, electrolytic)
the sampling ratio and signal resolution in bits of Fs/Fmax  greatly affects the anti-alias (Nyquist filter) steepness so be generous.  (proof not shown)

edit
Problems in your design.

Sampling error time 5% of 2ms (=1/500Hz = ) means in 100us the cap reaches the input voltage. so if dt=100us then choose C = Ic dt/dV  . Unfortunately it is not limited by RdsON but the Op Amp  current limit so this is a poor combination of Op Amp and sample cap.  The output current could be increased by 100 with complementary emitter followers inside the feedback loop.  The cap could be reduced to 100pF  or more  with metal film or C0G ceramic.  The Buffer Op Amp must be changed to CMOS which also may have lower drive current so choose wisely.

Sampling at 2x the maximum frequency means you can capture the correct peak amplitude ONLY if the sampling rate is in sync with the signal. They don't stress that they Nyquest Theory basics of 2f does not include signal quality. So consider a much higher sampling rate with your quantization bits =3x or More fmax.
There exists a mathematical relationship for quantization noise relating to Nyquist Theory and SNR and N bits.
Search for it.

your FET is polarized and relies on Vgs &gt;&gt;2 Vt where Vs includes the signal, so this should be replaced with a CMOS TG. (analog switch 4066 or better low R)



If you are concerned about matching input bias offset voltage consider sample interval ,dt , quantization error =dV , Buffer Input bias current, Ic so that dV/=dt*Ic/C