How do VHDL case statements scale when additional expressions are added?
The only way is to try it and see, in the FPGA technology you need. 

A general answer would be "a few extra LUTs and FFs" (maybe tens) for each additional clause, but occasionally you stumble across a less-than-optimal synthesis tool behaviour that adds many more.

There's no magic involved, a good synthesis tool will add about as many gates as you would by expanding boolean expressions, simplifying the Karnaugh maps and drawing out the logic by hand. Only, in seconds instead of hours...

Since bus_addr is likely to be sparse (here, 4092 unused addresses) I strongly recommend a "when others" clause to define behaviour for unknown addresses. It can be as simple as 

when others     =&gt; 
                   rd_data &lt;= (others =&gt; '-');


i.e. don't cares, giving synthesis permission to do anything it wants, to optimise the logic size. Try (others =&gt; '0') for cleaner behaviour, and compare the resulting  size.

You can also simplify these case arms, for example to

when RX_CTRL    =&gt; 
                   rd_data &lt;= (31 =&gt;rx_enable, 30=&gt; rx_allow_tcp, others =&gt; '0');


Shouldn't affect the logic generated at all.