Explanation of performance graph of FPGA design
By taking a look into the Cyclone II arquitecture description I believe there is no hardware divider in the architecture. This would mean division is somehow implemented in software, potentially in non-constant time; whereas in hardware it should have been constant time.

I tried to find out how division is implemented in Altera boards but I couldn't. This can depend on whether megafuncions are being used or if it is a block such as these.