ISE: Force the compiler to accept long loops
How about creating a massive shift register and clocking that as fast as possible with alternating ones and zeros going in?

signal sr:std_logic_vector(10000 downto 0); -- tune the length of this to suit your device
process
begin
   wait until rising_edge(clk);
   sr &lt;= sr(sr'high-1 downto 0) &amp; input_signal;
end process;


That won't use much much LUT logic though.  Nor test any other embedded blocks like BRAMs and DSPs.