Interrupt in 8085 microprocessor
When an interrupt comes in on the INTR line, the 8085 makes the \$\small \overline{\text{INTA}}\$ line low for two cycles.  This is typically used to enable a tri-state buffer like the 74LS244, so a RST instruction can be placed on the data bus.

The input of the buffer is either hardwired to generate a specific RST instruction (if there is only one such interrupt in the system, e.g. RST 5 would be 0xEF), or more typically wired to a priority encoder (such as a 74LS148) that outputs a number 0-7 on its three output lines which in turn are used to generate a unique RST for each interrupt.



The opcode of a RST instruction is encoded as:

       1   1   I5  I4  I3   1   1   1


where the 1's correspond to the lines hardwired to +5V above, and I5 I4 I3 correspond to the three lines from the encoder.

Note when I5, I4, and I3 = 5, the same instruction 0xEF is generated as before.

Its also possible to put a CALL instruction on the bus, but that takes multiple cycles.