FPGA Frequency Divider
Well, since unfortunately it isn't caught at compile time by your toolchain (which seems strange to me, but oh well):

Your FreqDivider component has an output port adjclk, and it is being driven by your countClock process. This is all very well and fine, no problem here.

However, your stimulus process has a signal called adjclk that is mapped to the adjclk port of your FreqDivider and this signal is being driven by a stimulus process adjclk_process. You cannot assign values to a signal that is being driven by a component. Most toolchains (at least, the ones I am familiar with) would identify this as bad, and complain loudly, but it seems your simulator only indicates this by an X or something in the output.

So, the solution: eliminate adjclk_process. It doesn't make sense to drive the output of a frequency divider that's supposed to be at 200Hz with a 25MHz signal.

Oh, and, as an aside, your math is a bit off on this line:

constant clock_period : time := 40 ns;  --50MHz


\$\frac{1}{50\text{MHz}} = 20\text{ns}\$, and each half-period would be 10ns, not 20ns.