How to control a flag in two different procedural blocks in verilog?
Obviously, you need to pass a signal from one process to the other (either direction) so that all updates to flag can occur in one process.

But what would be wrong with sampling the switches inside the clocked process? Is the clock so slow that it would miss changes on the switch inputs? I would write something like this:

reg [7:0] sw_prev;

always @ (posedge CLK)
begin

  /* Note that flag will be overridden if counter overflows on the
   * same clock cycle that the switches change. To avoid that, put
   * these two statements inside the 'else' clause below.
   */
  sw_prev &lt;= sw;
  if (sw != sw_prev) flag &lt;= 1;

  case (sw)   
  8'bxxxxxx01: x2 &lt;= 13'd1249;
  8'bxxxxxx10: x2 &lt;= 13'd2499;
  8'bxxxxxx11: x2 &lt;= 13'd3749;
  endcase

  if (counter2 == x2) begin
    counter2 &lt;= 0;
    flag &lt;= 0;
  end else begin
    counter2 &lt;= counter2 + 1;
  end
end


Always keep in mind that Verilog is a hardware description language, not a sequential programming language. What hardware do you imagine could be used to implement flag as you've written it? When dealing with asynchronous parts of your design, you need to think at a very low level, and then write code that more or less explicitly spells out that logic.