How to calculate the cycle time of pipeline
No, that's wrong. What about the register output delay in the second-to-last register? And what about the register input setup time?

The minimum clock period of any stage is the sum of:


clock-to-output delay of the interstage register
combinatorial delay of the logic
input-to-clock setup time of the next register (which might be zero, but it needs to be stated)


The overall clock period is the largest period of any individual stage.