CMOS (wrong) OR gate with 4 transistors
That's a pretty bad explanation in the book.
MOSFETs have a threshold voltage. This is the minimum voltage difference between the gate terminal and the source terminal that will allow the transistor to conduct significant current. For an NMOS transistor, the threshold voltage is a positive voltage, and the &quot;source&quot; terminal is defined to be which ever of the source/drain terminals has the lower voltage.
So, in your circuit the NMOS transistor drains are connected to 1.2V and their sources are connected to the gate output. If you bring the gates of these NMOS transistors to 1.2V then the transistors will only conduct current as long as their sources -- the OR gate output -- have a voltage that is not higher than 1.2V minus the transistor threshold voltage. Once the OR gate output rises to \$(1.2 - V_{TH})\$V the transistor stop conducting very well, so the OR gate output stops rising.
The same analysis applies to the PMOS, except that the source is defined to be the terminal with the higher voltage and the gate must be at a lower voltage than the source for good conduction.
EDIT:
When one of the OR gate inputs is at 0V, we have an NMOS transistor with its gate at 0V so it is certainly not going to conduct significant current. We also have a PMOS transistor with its gate at 0V...its source is connected to the OR gate output and its drain is connected to ground. So, if the OR gate output is at 1.2V then the gate-to-source voltage for the PMOS will conduct current, bring the OR gate output voltage lower. When the OR gate output voltage falls to the point that the gate-source voltage of the PMOS is less than its threshold voltage, then the PMOS stops conducting. This leaves the OR gate at a voltage approximately equal to the magnitude of the PMOS threshold voltage.