Amount of Decoupling Capacitance in Integrated Circuit Layouts
It is very normal to add some series resistance with your decoupling to damp the response. You should simulate this WITH your package inductance and determine how much series resistance you need. The exact amount of peaking you can tolerate will depend very much on your circuit. Key parameters to look out for are the affect of decoupling network peaking on noise and jitter.

For example, for 10GHz I suspect you are probably designing RX amplifers? In such an application there is  great benefit by reducing the decoupling response peaking as excessive peaking increases deterministic jitter in the RX chain. But doing this will degrade HF response ofcourse because the series resistance limits its high frequency attenuation , so add some broadband decoupling aswell. So simulate key parameters such as this as a function of decoupling R and C. I am surprised you need to full EM simulate at 10 GHz, so perhaps RCC extraction with bonding wire inductance will suffice for faster runs.

EDIT:
Regarding your comment for MIM vs MOS, you have to be careful as it is not simply a matter of Q. MIMs will give you the most linear capacitors and low voltage dependency so they are always a good choice however, the density is often lower than MOS caps specially in a thin oxide process. It is also not uncommon to have series resistance with MOS capacitors to damp the response.