Dual port RAM on Altera and Xilinx FPGA
I've also now just tried compiling for a Stratix V with Quartus 15.0 which does have M20K blocks, and you are correct - it infers two M20Ks which should not be the case. In fact using the Verilog test code I have just removed from my answer also infers two M20Ks. 



Why? The True Dual-Port Requirements

A single-port RAM of the size you are interested in should be possible to fit into a single M20K as it can support widths up to 40bits. For simple dual-port mode it should also fit - in this mode you have one read port and one write port.



Image Source: Stratix V Device Handbook, Section 2-9

However, in True Dual-Port mode it will not fit. The reason is because the M20Ks have only one 40bit wide read pathway and one 40bit wide write pathway. When operating in True Dual-Port mode, these pathways must be shared between the ports - in other words each port can only be 20bits wide.



Image Source: Stratix V Device Handbook, Section 2-9

Because of these shared pathways two M20Ks are required in order to fit the RAM. If you were operating in single port mode, or simple dual port mode, then it would require only 1.