Mechanism of On Chip Slew-Rate Limiting Mechanism
What chip are you talking about here, exactly?

I'm not sure how it's implemented in all cases, but I highly doubt anything is done with transfer functions.  My guess is they use some sort of adjustable current driver configuration, possibly with multiple stages.  I think a good solution would be to have an adjustable current limited stage followed by a voltage follower, possibly also with adjustable current.  Xilinx FPGAs allow three different slew rate selections and several different drive current selections, so it seems like they may be using something along these lines.  For other chips, I'm not really sure what the implementation might look like.