VHDL code and unintended latches
As Paebbels mentions in his comment, your process works exactly as you intend it.

You get a flip-flop, and not a latch, because of the condition on clk in your if statement, which specifies that a1 is assigned only when clk rises. clk'event means a change just happened on clk, so clk'event and clk='1' means "clk just changed and is now one", i.e. a rising edge.

A default assignment as the one you propose is not necessary because a signal keeps its previous value if one is not assigned explicitly. This simplifies sequential processes as the one you posted, but is also the source of unwanted latches in combinatorial processes.

The following is a latch:

process(wra1, b1) begin
    if(wra1='1')then
        a1 &lt;= b1;
    end if;
end process;


Note that 1) this process has no clock (i.e. no rising edge condition on a signal), just like a process describing combinatorial logic, but 2) no value is assigned to a1 when wra1 is not 1, which means it keep its current value until wra1 is 1 again, even if b1 changes. That's the semantic of a latch.