FPGA: Choose RAM or FIFO for ADC input to be filtered
In most cases I would say a FIFO is preferred. Why?

Because I am assuming (as it is in most cases) that the core clock is different from the ADC clock. The dual clock FIFO solves synchronization between reads and writes for you.

If you use dual port RAM, you will have to invent by yourself the write address vs. read address synchronization mechanism.

Even if you have to process the data twice, I would use a dual clock FIFO and open two paths for processing on the core clock side.