Output capacitors placement in PCB
Considering capacitors having the same chip style, capacitors with higher capacitance have a lower resonance frequency, so the parasitic inductance will dominate at a (relative) lower frequency and therefore work worse for higher frequencies.  



Source: "parasitic inductance of multilayer ceramic capacitors" from AVX  

The parasitic inductance is dependent on chip size as is explained in referred document.
Increasing capacitance sometimes requires a bigger chip size (due to availability/pricing), so a bigger capacitance might increase inductance as well, but not necessarily (compare Table 3 in refered document).

In order to reduce EMI, current loop areas should be as small as possible, especially the high frequent current onces.
Therefore, generally, you should place the capacitor with the lowest capacitance closest to an IC and capacitors with higher capacitance further away.

UPDATE
The explanation regarding smaller current loop areas above applies for input capacitors (C1 and C2 below) as well as for output capacitors (C3, C4 and C5 below). When placing a higher valued capacitor (C4) closest to the output of a device (and leaving out C3) and a smaller valued capacitor (C5) further away, the smaller capacitor (C5) hardly contributes with respect to the output of that device.
Still there can be a smaller valued capacitor further away (shown as C6), but it is more likely that that capacitor serves as input capacitor for the electronics connected after it.  







simulate this circuit &ndash; Schematic created using CircuitLab

In case of LDO's: a LDO may become unstable when placing too small valued capacitors at the output (due to low ESR). Moreover, a LDO is not a switching mode supply, so, there is no need to reduce high frequent current loop areas at its output. So, only a big capacitor at the output of the device will be sufficient.