Implementing 3 to 8 decoder using 4 input NOR Gate
The fact that you were given a NOR gate rather than an OR gate is a significant hint: Look for the patterns of zeros, rather than ones, in your K-map. And remember that don't-cares can be assigned the value zero or one.

Here's the K-map I came up with, based on your truth table:

    A0  0  0  1  1
    A1  0  1  1  0
A3 A2 +------------
0  0  | 0  x  0  1
0  1  | x  0  1  1
1  1  | 0  x  0  1
1  0  | x  x  1  0


If you make all of the don't cares zero, you get this:

    A0  0  0  1  1
    A1  0  1  1  0
A3 A2 +------------
0  0  | 0  0  0  1
0  1  | 0  0  1  1
1  1  | 0  0  0  1
1  0  | 0  0  1  0


Clearly, the left-hand side of the table can be taken care of by feeding not-A0 (using the inverter you were given) into one input of the NOR gate.

The remaining three zeros (Aha!) can be taken from individual outputs of the 3-to-8 decoder, whose A, B and C inputs are connected to A1, A2 and A3, respectively. Specifically, the outputs for "1", "4", and "7" should be connected to the three remaining inputs of the NOR gate.