How can a simple operation such as moving data from one register to another can be encoded into an instruction and executed in a single clock cycle.?
von Neumann's cycle, fetching, decoding and executing (sometimes a separate writeback) cannot be done in a single clock cycle. That is probably what you are referring to.

What is happening is a technique called 'pipelining'. While one instruction is executed, a second one is decoded and a third one is fetched from memory. All three in parallel during the same clock cycle. A single instruction still takes 3 clock cycles, but the parallel mechanism averages to 1 cycle per instruction.

Some instructions like branches/jumps take disproportionate many clock cycles (3 or 3) because they break the pipeline. The instructions being decoded and fetched have to be flushed and the pipeline has to reload.

Some modern processors are even more optimized than this. They can predict what will happen and hence the technique is called 'branch prediction'.