Calculating how long it takes for a circuit to compute the output for a given set of inputs
You failed on two points:

You did not recognize that the prof is playing games with your head.
The delay from register 4 to register 2 contains an adder and a multiplier, which have an aggregate delay of 11ps, and the registers have clock-to-q and setup delays,.

Add these extra delays to the clock-to-q delay for register 4 and the setup delay for register 2, and -- when the temperature and clock frequency are just right and the process hasn't changed lately -- that'll add a reliable 'a bit more than 1 clock delay' to that signal path.