Problem with my 8-to-3 line priority encoder using verilog gate level description
Just to summarize for you what I wrote in comments since it may help others, as well.

Here is the verilog I'd consider:
module prior_otb_enco( Y, D, V );
  output [2:0] Y;
  input [7:0] D;
  output V;
  wire s0, s1, s2, s3, s4, s5, s6, s7;
  wire Y2_temp;
  assign s0 = ~ D[7];
  assign s1 = ~ D[6];
  assign s3 = (D[6] | D[5] | D[4]);
  assign s2 = ~ (s1 &amp; D[5]);
  assign s4 = (s3 | D[2] | ~ D[1]);
  assign s5 = ~ s3;
  assign Y2_temp = ~ (s0 &amp; s1 &amp; s2 &amp; ~ D[4]);
  assign s6 = ~ (s5 &amp; D[2]);
  assign s7 = ~ (s5 &amp; D[3]);
  assign Y[1] = ~ (s0 &amp; s1 &amp; s6 &amp; s7);
  assign Y[0] = ~ (s0 &amp; s2 &amp; s4 &amp; s7);
  assign V = ~ (s6 &amp; s4 &amp; s7 &amp; ~ (Y2_temp | D[0]));
  assign Y[2] = Y2_temp;
endmodule


The equivalent schematic is:


Here are three different behavioral models, all in verilog, that would achieve about the same thing after synthesis:
example 1
module prior_otb_enco_1( Y, D, V );
  output [2:0] Y;
  input [7:0] D;
  output V;
  reg V;
  reg [2:0] Y;
  always @(D)
    V = 1;
    if ( D[7] )        Y = 7;
    else if ( D[6] )   Y = 6;
    else if ( D[5] )   Y = 5;
    else if ( D[4] )   Y = 4;
    else if ( D[3] )   Y = 3;
    else if ( D[2] )   Y = 2;
    else if ( D[1] )   Y = 1;
    else if ( D[0] )   Y = 0;
    else
      begin
        V = 0;
        Y = 3'b X;
      end
  end
endmodule

example 2
module prior_otb_enco_2( Y, D, V );
  output [2:0] Y;
  input [7:0] D;
  output V;
  reg V;
  reg [2:0] Y;
  always @(D)
    begin
      V = 1;
      casex( D )
        8'b 1XXXXXXX:  Y = 7;
        8'b 01XXXXXX:  Y = 6;
        8'b 001XXXXX:  Y = 5;
        8'b 0001XXXX:  Y = 4;
        8'b 00001XXX:  Y = 3;
        8'b 000001XX:  Y = 2;
        8'b 0000001X:  Y = 1;
        8'b 00000001:  Y = 0;
        default:
          begin
            V = 0;
            Y = 3'b X;
          end
      endcase
    end
endmodule

example 3
module prior_otb_enco_2( Y, D, V );
  output [2:0] Y;
  input [7:0] D;
  output V;
  reg V;
  reg [2:0] Y;
  integer N;
  always @(D)
    begin
      V = 0;
      Y = 3'b X;
      for( N = 0; N &lt; 8; N = N + 1 )
        if ( D[N] )
          begin
            V = 1;
            Y = N;
          end
    end
endmodule