ERROR:Xst:827, Signal next_states1 cannot be synthesized, bad synchronous description
I think it would be good for you to do a course in or tutorial on VHDL...
But anyhow: the clock edge detection should not be inside the case statement this way.

Highway: process(CLk) 
    variable counter: integer := 0;    
begin
    if rising_edge(clk) then
        case traffic_states1 is
            when H0 =&gt; 
                if (Input='0') then 
                    next_states1 &lt;= H0;
                    counter := counter + 1;
                elsif (counter &lt;=20) then
                    next_states1 &lt;= H0;
                    counter := counter + 1;
                elsif (Input='1' and counter &gt;20) then
                    next_states1 &lt;= H1;
                    counter := 0;
                    -- else next_states1 &lt;= traffic_states1;
                end if;
            when H1 =&gt;     
                if (counter = 3) then
                    next_states1 &lt;= H2;
                    counter := 0;
                else
                    next_states1 &lt;= H1;
                    counter := counter + 1;    
                end if;
            when H2 =&gt;
                if (counter = 9) then
                    next_states1 &lt;= H0;
                    counter := 0;
                else
                    next_states1 &lt;= H2;
                    counter := counter + 1;
                end if;
            when others =&gt;
                null;