Crossing independent domain clocks (slow to fast)
You can never expect 100% reliability, but you can expect 99.99999...% reliability. 

As you can see in the picture below (from here), the MTBF is proportional to the clock frequency and number of stages.  It also depends on the "metastable resoltuion time", which is shorter for faster logic.

With fast enough logic and enough synchronization stages, you can design for one failure in the lifetime of the universe, on average.  Keep in mind that if you are running more than one device, you have to divide your MTBF by the total number of number of devices.

Also, make sure to stay away from Infinite Improbability Drives.

EDIT:

As for the reliability of a 2X clock, you could be unlucky and be aligned with the rising and falling edge of the slow clock and have both synchronizations settle to the same level, thus missing the high or low portion of the slow clock.  If the fast clock period is shorter than the minimum high or low time of the slow clock minus the setup and hold time for the synchronizing FF, you are guaranteed to see at least one fast clock period at the output of the synchronizer for each level of the slow clock.