Modelling Circuit from FSM using Verilog
You want to use a nonblocking assignment. These assignments change at the clock edge. 

always @ (posedge c)
begin 
    q  &lt;= d;
    q0 &lt;= ~d;
end


In order to illustrate the implications of blocking vs non-blocking assignment, consider the following example.

Two outputs, A and B. A is driven by the input, and B is driven by to A.

module flipflop(
    input c,
    input d,
    output reg a,
    output reg b
    );

   always@(posedge c) begin
      a        &lt;= d;
      b        &lt;= a;

   end
endmodule


That produces this:



As you can see, there is a flip flop between output A and output B.

Now the blocking example:

module flipflop(
    input c,
    input d,
    output reg a,
    output reg b
    );

   always@(posedge c) begin
      a        = d;
      b        = a;

   end
endmodule


That produces this:



There is no delay between A and B anymore.

If you want a delay of multiple cc, it's necessary to use a non-blocking assignment in order to infer the correct number of FF needed. Here's an example of a triple registered signal in hw which creates a 3cc delay:

module flipflop(
    input c,
    input d,
    output q
    );

   reg [2:0]   q_i;

   always@(posedge c) begin
      q_i[0]   &lt;= d;
      q_i[2:1] &lt;= q_i[1:0];

   end

   assign q = q_i[2];


endmodule


It creates this schematic in synthesis:



The tools have inferred FDREs in these cases. See the xilinx libraries guide (page 185) to give you an idea of what primitives are available (altera will have similar ones, probably).

I ran your code in vivado 2015.3 and it worked fine: