how to calculate the tpdhl / tpdlh for any given circuit
Assuming all gates have the same delay, (but the 2 types will have different delays),
then the shortest time from High to Low, or Low to High, will be from C_IN to SUM, as it only goes thru gate 4. 
The longest time will be A or B to Cout when C_IN is involved, as gates 1, 2, and 4 are involved.  

Both require the assumption that the other inputs are in the correct level to allow the signal of interest to pass thru without waiting for the other states to change.