Reading from file in every rising edge of the clock in VHDL
It is pointless to try this approach. Synthesis can ONLY read from a file at initialisation time - there are no "files" on an actual FPGA. Reading data in a clocked process requires a hardware interface ranging from a simple serial UART to an Ethernet MAC or a SD card interface (with an SD card socket on your FPGA board), all these re significant projects in their own right.

If your synthesis tool has performance problems initialising memory via e.g. a function call which reads a file (and I know some do) you have to find another approach.

Test this by adding a "Report" statement each time you start reading a new row from the file. If you're using Xilinx ISE of a certain vintage you'll see it slow down quadratically as it progresses, a sufficiently large array taking hours for a job any other tool can complete in under a second.
(Alternatively the "Report" statements may flash past in seconds, showing you that something else is taking the time.

One simple alternative approach (if the "Report" test shows this is the problem) is to use a small program written in whatever language you choose, to read that file, and write another file consisting of the same data, but preceded by something like

library ieee;
use ieee.numeric_std.all;

package ROM is
   subtype byte is unsigned (7 downto 0);
   type ROM_type is array(0 to 249, 0 to 249) of byte;
   constant My_ROM : ROM_type := (


and followed by

   );
end package My_ROM;


And use that package in your design.

But I suspect the problem lies elsewhere and you're going to have to stop, spend a year or two learning digital systems design, and come back to this problem later.