Nested Vectored Interrupt Controller (NVIC) - Why is it "nested" and "vectored"?
In the old days, a CPU would have one, or maybe two interrupt lines. Maybe one would be Non Maskable Interrupt for critical things, the other shared for everything. 

In this case, either an external peripheral, or just software checking lots of status registers would be used to determine the cause of the interrupt, and look up the location of the relevant handler.

Particularly in a real time system, time to get to the first real instruction of an interrupt handler is important, so Vectored Interrupt Controllers were introduced to provide the right address straight off to the processor, saving a few instructions.

The nested part allows for many interrupts to be enabled and assigned priorities. This automatically ensures that once an interrupt handler starts, it won't be interrupted by a new request, unless that request is even more important. This avoids a lot of the complication around enabling and disabling specific interrupts which could achieve the same thing.

A final feature of the M-class architectures is that since the stack push/pop is handled architecturally rather than in software, back to back exceptions are able to skip a redundant pop/push sequence - but this is nothing to do with the nested or vectored descriptions. Two exceptions at the same preemption level would tail-chain, if you had three at the same time then you would be able to chose the order of starting without needing to worry about one of them actually stopping an already running handler.