Clock distribution for low-jitter audio DAC
For jitter the big thing you want to avoid is noise coupling into the clock lines.  Your clock device is single-ended, so that's a strike against you, but you can still consider routing it with shielding.  That is, route ground traces next to the clock as much as possible, but avoid vias on the clock line (keeping it all on one layer should be paramount).  For skew (also may be important for you), keep the electrical length of the clock lines equal to each converter.

Also, follow these suggestions closely:  A Short Course in PCB Layout for High-Speed ADCs