SPI chip select --> data + clock delay tolerance
Actually the CS timing is not very important -- you usually assert the CS line (bring it low) at the beginning of a bunch of transfers, and then de-assert it (bring it high) at the end.  What is more important is the relationship between the clock (SCK) and the data (SI/SO).

Here is a typical timing diagram for an SPI peripheral, in this case a 2AA1024 1 Mbit serial EEPROM.



In this case, the timing is for writing a byte to the EEPROM.

As you can see, the chip select is brought low at the beginning of the 8-bit transfer and left there.  (In general, it can be left low across as many bytes as needed to be read.)

The numbers refer to the timing specifications, usually at a specific voltage.  I chose the slowest, which is for 1.8v.

2 CS setup         250 ns
3 CS hold time     500 ns
4 CS disable time   50 ns
5 Data setup time   50 ns
6 Data hold time   100 ns
9 Clock high time  250 ns
10 Clock low time  250 ns


The speed is 2 MHz, or a high/low clock period of 250 ns each (Clock high time, 9 and Clock low time, 10).

So the chip select does need to be asserted for 250 ns before the first rising clock pulse (CS setup, 2), but obviously that is very short if being driven from a microcontroller output.

The data must be present 50 ns before the rising edge of the clock (Data setup, 5), and must remain valid for 100 ns afterwards (Data hold, 6); this will usually be handled automatically by the SPI peripheral, and would only be important if the interface is being "bit-banged".

It should be noted that this diagram assumes that the clocking of data is done on the rising edge of the clock.  SPI interfaces can also be configured to clock on the falling edge.

At the end of the transfer, the CS line must be kept low for 500 ns (CS Hold time, 3) after the last clock transition, before being brought high; and must remain high for 50 ns (CS Disable, 4) before it can be asserted again.