H-bridge with optocouplers input not smooth
Schematic 1 is only useful for low voltage motors as the Pch and Nch FETs will both be conducting heavily (shoot-thru) at some Vdd/2 voltage applied to the gates.  E.g. Vdd= 2Vgs(th) and is very device specific. There are only 2 gate drivers here which is a serious limitation for simplicity. It might be improved with the same Rgate divider or better with 4 Opto’s in order to have a 1us deadtime during commutation. Then some snubber or clamp diodes are needed in FETs or outside.

Schematic 2 is better with 4 gate voltages separated by resistor dividers as level shifters to avoid shoot-thru but is still a poor design but simple.

More common is all Nch FETs using high side for direction and low side for PWM which also feeds a Vboost to get a higher gate voltage than Vdd. Dead-times of 0.5us are common and depend on motor inductance.

In all cases the RdsOn must be much less than the motor DC resistance or DCR. 

The concept in all cases is to avoid linear mode and switch OFF faster than ON often to create this dead-time. That is done with IC drivers or a diode+ smaller R in parallel with another R to gate. (not shown in either  example here.)