Is there a preferred order VHDL case/when and rising/falling_edge statements in processes?
While the first example may be syntactically correct, I have never seen clock logic enclosed within anything other than an IF/ELSE that selects between reset and clock.

It is far better from a readability standpoint to have an "if rising_edge" enclosing all of the synchronous logic for the process, so that you can immediately tell that it is indeed synchronous.

Also, your sensitivity list only needs to include the clock input, since if it's truly a synchronous system all of the other variables only matter when the clock changes.  If the process needs an  asynchronous reset, then the reset must also be in the sensitivity list.