Accessing same variables in Verilog on different clocks
In comments you said this is for implementation in an FPGA.

In that case, you should reconsider your architecture.

Instead of dividing down your 50 MHz master clock and having a second 9600 Hz clock, use the 50 MHz clock to drive your 9600 Hz logic, but use a strobe signal to enable that logic.

reg str9600;
reg [12:0] str_ct;

always @(posedge clk) begin
    // Generate 9600 baud strobe
    if (reset) begin
        str_ct &lt;= 0;
        str9600 &lt;= 0;
    end
    else if (str_ct == 5208) begin
        str_ct &lt;= 0;
        str9600 &lt;= 1;
    end
    else begin
        str_ct &lt;= str_ct + 1;
        str9600 &lt;= 0;
end

always @(posedge clk) begin
   // Do 9600 baud operations when enabled by strobe
   if (reset) 
        // reset stuff
   else if(str9600) 
        // do 9600 baud stuff
end

always @(posedge clk) begin
    // do 50 MHz stuff
    // queue management goes here
end


Now your queue becomes part of the 50 MHz logic, with the str9600 signal as an input, telling it whether something can be pulled out of the queue, but able to add to the queue on any 50 MHz clock edge.