How to implement a function using just NAND or NOR logic gates
Although the other answers do explain the process to use deMorgan's to convert to NAND/NOR, they don't really answer the question if you look at the graphic of a half adder.

$$S = A \overline B + \overline A B$$ 
$$C = A B$$

deMorgan's, you get:

$$S = \overline {\overline {A \overline B} \cdot \overline {\overline A B}}$$ 
$$C = \overline {\overline{A B}}$$

The half adder constitutes 7 NAND gates because each of the AB terms is unique.

$$S = A \overline B + \overline A B$$ 
$$S = A \overline B + 0 + \overline A B + 0$$ 
$$S = A \overline B + A \overline A + \overline A B + B \overline B $$ 
$$S = A (\overline A + \overline B) + B (\overline A + \overline B) $$ 
$$S = A (\overline {A  B}) + B (\overline {A  B}) $$ 
$$S = \overline {\overline {A (\overline {A  B})} \cdot \overline {B (\overline {A  B})}} $$ 
$$C = \overline {\overline{A B}}$$
The AB term is reused and now the half adder is 5 gates.







simulate this circuit &ndash; Schematic created using CircuitLab



So to answer the question.

These examples are NOT good for learning how to convert to NAND/NOR gates. 

These circuit are examples of the types of optimizations designers used to go through to optimize designs to minimize gates.