Is there a way to prevent the random state of a shift register when power is applied?
The chip you are using has an output enable pin that allow you to keep the shift register outputs in a high impedance state until you shift in known data. You would probably want to use a microcontroller for this.
From NXP Datasheet:

Additionally you can use the master reset pin to clear shift register contents if you want them to be all 0. If you use this method it's probably doable to set up a resistor and capacitor to keep the pin low for a certain duration of time after power up.