Checking array input value Verilog
Your problem lies in the line of code:

if(op_code==00000)
     Ripple_Adder RA1(data_out, carry, data_1, data_2, 0);


You don't seem to have understood that Verilog is a "Hardware Description Language", not a procedural programming language. It does not execute code line by line, but rather is synthesized into hardware based on what you are describing.

You are trying to use an if statement incorrectly. What your code is describing is that if the op_code is 0, then create some hardware called Ripple_Adder. However, what happens if op_code is not 0? Does it need to infer the adder? Should it delete the adder? 

Simple answer, it can't - the hardware is fixed at synthesis, you can't add or remove bits of it when running. This is why it is complaining about op_code not being a constant - it doesn't know whether or not Ripple_Adder should be included or not.

The solution, is to always include the hardware, and then infer a multiplexer to select whether or not the output of it is used. Something like this:

wire [7:0] ripple_data_out; //Output data for the ripple adder
Ripple_Adder RA1(ripple_data_out, carry, data_1, data_2, 0); //Infer the ripple adder

always @ * begin
    case (op_code)
        5'b00000: data_out = ripple_data_out; //If the op_code matches, connect ripple_data_out to data_out through the mux.
        //... Add more cases here for other op_code values ...
        default: data_out = 8'b0;
    endcase
end