How do I calculate the max pwm frequency my h-bridge can handle?
The gate charge time isn't really that simple.  There's the Miller effect as the FET transitions through the linear region and has negative voltage gain. This causes the gate to drain capacitance effectively to be many times larger than the actual value.  The driver doesn't necessarily put out the peak current throughout the whole voltage range either.  The total gate charge curve on the datasheet can help get a better estimate for gate rise time.

Having said that, 14ns sounds pretty close to what the real gate rise time will likely be.  The question of what the maximum switching frequency can be leads to the question: What's your target efficiency?  How much power are you willing to lose to switching losses?  If your switching frequency is on the order of your risetime your switching losses will be extremely high.  If you want a rough guideline switching an H bridge at 1MHz and above can be done, but starts to get tricky and lossy.  100-300kHz is a good range.  Note that this is many times the risetime, but will allow reasonable efficiency.  

My rule is switch at the lowest frequency possible while still meeting size and system constraints (out of audio band, etc.).  This maximizes efficiency and minimizes EMI.