VHDL functions with generic or "run time variable", synthesis issues
Synthesis tools work very hard to evaluate everything at compile time that they possibly can. For everything else, they synthesize logic -- including function calls, assuming that the function is synthesizable (some are not).

Therefore, the answer to your question is, "it depends". It doesn't matter if the actual parameter to the function is a generic or a signal (port) -- if the value is known at compile time, the synthesis tool will evaluate the function at compile time and use the result. The only difference is that a generic is by definition known at compile time, while a signal may or may not be.

If the function needs to be evaluated at run time, then the synthesis tool will generate the logic required to do that, assuming that no non-synthesizable constructs have been used in the body of the function.