Combining capacitors for multiple chips
One capacitor per power connected pin is a good idea when possible.
Combining values is not the ideal way of calculating needs.




The roles of the decoupling capacitors are


(1)  Stop local peak load effects radiating to other components:
Provide an energy sink adjacent to the IC so that it may draw energy peaks from them rather than drawing the required energy from further away and thereby causing a substantial supply voltage fluctuation which may adversely affect the operation of other ICs and other circuit elements.    
(2) Stop remote peak load affects affecting local operation:
Provide an energy sink adjacent to the IC so that it may supply energy to the bus when some other IC etc draws energy peaks to stop the resultant voltage dip from affecting the IC's operation.    
(3) Stop current pulses and voltage spikes caused by switching inside ICs from propagating across the board and causing EMC (electromagnetic compatibility) issues.  
(4) All of these - connect a pin to the eternal now of a signal-grounded zero impedance noise free nirvana plane [tm] where noise signal sources cannot propagate noise, noise sensitive sinks don't see noise, adjacnet pins are blissfully unaware of the other's existence - OR the nearest thing to it in practice = a ground plane. 


(1) &amp; (3) require the capacitor adjacent to the IC to keep noise off the system bus.

(2) Requires that the capacitor is electrically closer to the IC that may be affected that the pulse generating IC is. You COULD try to second guess the key locations needed to place these, but, why bother unless room or budget are very low and volume produced are astronomical. 

(4) Is the best practice implementation of these in the form of a properly designed ground plane. 

In MOST cases the cost of placing a decoupling cap near every pin that connects to a common bus is small compared to the potential benefits. ie do it if you can.

In most cases the best value to use is the best value for the task concerned. Number of device sharing a decoupling capacitor may affect value but ideally choose a cap that best deals withe the noise present at a point. One upon a time, best advice was to use 0.1 uF ceramics at each pin to be decoupled. The improvement in specs of ceramic caps mean that 1 uF may have as good or better high frequency responses. AND/BUT the increase in clocking signals of top processors and logic families mean that frequencies are often higher, edges sharper and that lower values of caps may be indicated. So, 0.1 uF to 1 uF is a good choice still. At some locations liable to be especially significant the use of a 10 uF solid Aluminum, 1uF + 0.1uF and maybe even 0.01UF all near each other "may help". 

Also note the output cap needs of some LDO regulators to have caps of selected ranges and ER values at their input.