Need optimization advice
I've had some success using a similar technique to what you have proposed above, which is to essentially create multiple registered duplicates of the high-fanout nets. You can use one per destination as you have, or what I have done in some cases is to duplicate them so that there is one registered duplicate for every n destinations.

In theory, you should be able to simply register the signals once, and the tools should automatically duplicate this register to solve routing issues caused by high fan out during optimisation. Unfortunately my experience is that this does not happen. Even worse, the synthesis tool can by default delete any duplicates you have tried to manually create, in order to reduce logic usage!

So to answer your question, my advice is to turn off equivalent register removal in the Xilinx-specific synthesis options, or to place a keep constraint on your duplicated high-fanout signals.

Note the potential downside of turning off equivalent register removal is that any code that is written in a high level manor, under the assumption that duplicate registers will be optimised away, could start using a lot more resources.