Unnecessary (?) loading PC register with following instruction's address in ARM
Those chips can (under software control) re-locate the vectors area to a different place in memory. This applies to a limited part of the memory, which might not include that low-level initialization code. So when the relocated reset vector is activated, the init code is not 'after' the vector. The relocation ara is probably too far away from the init code for a normal jump (IIRC only 24 bits offeset?), so an explicit PC load is used.

To put it in another way: the author knew (or thought, maybe he was wrong...) that the first two lines of the code you show could be mapped (aliased) to two different places in memory, but the following code would be only in one place. The "ldr pc,=1f" jumps from both possible mappings to the one that (also) contains the next instructions.

This is important only when the reset vector is activated (chip is reset) via the remapped vector address.