How does a latch determine its initial state?
There is certainly a lot of stuff taught in school that is not required in the job market.  And, of course, there is a lot that is not taught that should be.  This could probably be said about any job market, since it depends on what specialty the person ends up being employed in.    Unfortunately for you, neither your professors or I can tell you what you will and will not use once you get a real job in your field.

For example, I don't use calculus in my job as an E.E..  But a coworker, who is also technically an E.E., uses calculus almost daily.  I design PCB's and FPGA's, while he writes DSP algorithms.  There was no way our teachers could have ever known what we needed to get the job done.

That being said...  Your question to your teacher, about the initial value of the latch or Flip Flop (FF), was a great question and the way your professor responded shows her ignorance of the requirements for designing practical digital logic circuits.

Simply put, the initial value of a Latch or FF is indeterminate.  Meaning, it will have an initial value but you won't know what it is in advance.  A given latch/FF might even have different initial values from one power-up to the next.  Sometimes it'll be a '0', other times a '1'.  Things like temperature and how fast the power rails ramp up will effect the initial value.

If your circuit requires a known initial value then you must force the value.  Normally this is done using some sort of set/reset/clear input that is driven by a reset signal.  This is also why almost any digital circuit of reasonable complexity has a reset signal.  Reset signals are not just for CPU's.