Cortex-M0 interrupt nesting
The part that handles these things in a Cortex is the Nested Vectored Interrupt Controller (NVIC).


  Question 1: When one interrupt handler is executed, will it be interrupted if another interrupt with the same priority occurs?


No, an interrupt will be acknowledged if it has a higher priority


  Question 2: When one interrupt handler is executed, will it be interrupted if another interrupt with the lower priority occurs?


No, not while the interrupt handler is running.