Asynchronous inputs to timing diagram
As you mention, asyncronous SET and RESET signals are often active low.  To simplify the explanation, let's assume we're doing a RESET.  (PRESET will work the same way.)

The Q output will be driven LOW as soon as the RESET is pulled low.

The Q output will remain LOW as long as the RESET is held low, regardless of other signals.

At the trailing (rising) edge of the RESET pulse, the Q output will remain LOW until the next clock, when it will reflect the state of the flip-flop.