Using too many Modules in Verilog affect timing?
No, it doesn't affect the timing or final netlist. If you take a signal from the top level and assign it to successive modules, the compiler will recognise this is the same signal. Modules are there to allow you to:


Group functionality into logical blocks.
Reuse common designs.  
Keep design elements at a size you, as a human, can keep track of. 


I try to have only assignments and very simple logic (e.g. ORing the output of two modules) at the top level. This keeps the namespace clean, and allows easy traversal of the hierarchy in the simulator.