NAND gate with one pMOS and one nMOS
There are a implementations using "pass-transistor logic". They don't regenerate the logic levels, so they should be mixed with regular CMOS logic.

Google gives a number of different results, one of them:



Update: as noted by Ken Shirriff this implementation shows an AND-gate. A NAND implementation is shown below, but again inverters are required. 



(Source: A general method in synthesis of pass-transistor circuits)