How to define VHDL entity with two architectures?
To use multiple architectures in a single entity, the structure you're looking for (I believe) is configurations. I could never make heads or tails of configurations, and the usage is arcane as best I can tell. Best of luck if you try it. 
The half-assed way of doing it would be to use an if generate statement with a generic parameter selecting which instantiation to use. This requires having seperate entities for each architecture, and third entity to act as a wrapper around the generate statement. 
The really lazy way would be to just directly instantiate your HalfAdder and RippleCarryAdder as seperate modules, and ignore the headache altogether.


I've never attempted any of this, and I haven't used ISE in years. I don't know if it does support funky configurations, and it honestly wouldn't surprise me if didn't. Like everyone else was saying, I'd suggest upgrading to Vivado