What's wrong with my interpretation of what should happen in the circuit and what's happening?
Presumably at the point you expect 1111 you are seeing 0000.

If you look at the truth table in the data sheet for the 7474, you will see that the set and reset pins operate totally independently from the data and clock pins.  As soon as the top bit goes high, the lower bits are reset to 0, which then resets the top bit.

Data sheet -
http://www.ti.com/lit/ds/sdls119/sdls119.pdf

The data sheet says - “A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.”

This answer describes a synchronous reset -
D flip-flop with a synchronous reset, R