Const type array in Vivado HLS
First, FPGAs can't arbitrarily configure single transistors to do things such as making a tie. An ASIC designer can, but an ASIC is not an FPGA.


  
    "Why would HLS implement this array as a ROM and use resources instead of converting it to ties of VCCs and GNDs?"
  


In your mind, what is constitutes a "ROM" bit in an FPGA? Is it a transistor pair in a push-pull configuration that connects the common node to either Vcc or GND? Let's assume it is. So what is driving the gates of those transistors so the stack holds state? An SRAM? Well that's a bit pointless because now you need those two push-pull transistors plus six transistors for the SRAM. You might as well just use an SRAM.

If you don't use an SRAM, then you need to use configure a logic block as lookup table but those use many more transistors per bit, and can be used to do things other than just storing bits so its a waste.

An FPGA is not a sea of transistors you can individually manipulate. It's a sea of logic blocks.