NFET As Voltage Controlled Switch Question
1) I watched the video.

2) In this case, the  term "signalling node" refers to the drain of the NFET. In other words, the output you are trying to design

3) Do not worry about the 4th node until later. For now, ignore it. It is the body node in the MOSFET. Generally you are going to connect it to the source.

4) You are going to have to be a little more patient, watch more of the videos in this series. They are trying to present you with a set of simple rules for designing CMOS digital logic. What NMOS does is short drain to source when the gate voltage is higher than the source voltage. Whether this gives you the switching behavior you want depends on you. You have to design the circuit so that the output behaves the way you want based on the input.

Basically what they are saying in this video is that in CMOS logic, you put NFET on the bottom and PFET on the top. In both cases, the drain is the output (which they also seem to be calling the "signalling node.") The source is grounded for NMOS and connected to VDD for PMOS. A high on the gate will cause the output to be low (for an inverter). Because high turns ON NMOS and turns OFF PMOS.

The fourth terminal is available to IC designers only. That is why you have not encountered it. On discrete MOSFET's, the body terminal (fourth terminal) is always connected to the source. Most likely, you will always connect the body to source in CMOS logic also.

Good luck!