Routing traces of different width onto an IC on a 4-layer PCB in Eagle
The blue traces are gate drives and you will have not any issues with those.  While they reach 2-3A, that is pulsed and the average current (which translates to trace warming) is pretty low. 

Look at the sample layout for the LTC3789 (similar chip) to get some hints on better layout.  I think you are going to have issues with the connection between the low-side switches and the current sense resistor, and possibly the IntVcc bypass cap.

I have done several designs with the LTC3789 and getting good performance from these parts does require reasonably good layout and very careful routing of the high frequency, high di/dt current loop.

You should also be using Kelvin connections around R1 for the current sense, even though the bottom side is ground, you need a separate, isolated trace for the current sense.  The top side of R1 to current sense should not be sampled where it appears to be. 



For the layout, take a look at this:


The current sense resistor is directly above the BB controller and the ground extends horizontally from the input caps to the low side of the current sense resistor to the output caps.  I have found this layout works best.  If you are running at high currents, use that ground pour to connect the input ground to the system ground (don't use a continuous ground plane, or at least don't connect it on the input side.  This will help maintain a clean system ground.

The layout below is incomplete (my project for today), but you can get a general idea of the layout.  The ground and input/output power planes will be extended (and the sense trace below C18 will be moved to layer 3 or 4).  The sense traces from the current sense resistor (sorry, haven't fixed the silkscreen yet) will be run on layer 4 over to R7 and R8.  The LTC3789 has a second current sense loop I use on the output at R2, you can see how to layout the sense connections there.  This is a battery charger BTW, so the output current limit is handy.