VHDL - Inferred Latch With Reset - FSM
Think of it this way

In a process the actual new value of any signal is only assigned when the process is complete.

The process starts when something on the sensitivity list changes and ends at the 'end process' statement.  At this point, all the signals are assigned at exactly the same instant, even if a signal is assigned multiple times within a process it only gets the value of the last assignment.

So follow each signal through, and ask yourself if is it always assigned in all circumstances?

Latches are inferred in VHDL if at the end of a process a signal has not been assigned a new value, it has no choice but to use whatever value it last had, hence the latch.

Effectively what it is doing is adding an invisible line of code just below the clock edge statement for ALL signals assigned in the process.

....
ELSIF RISING_EDGE(clk) THEN
    duty_cycle_triangle &lt;= duty_cycle_triangle;  --The future value is the same as the past (i.e. a latch)
    ...


Indeed you can hide the inferred latch warning by putting exactly that line in.

BTW:


You don't need the brackets for ifs, this is not C.
PWM_enable may also be inferring latches and is only ever assigned a value of '1'