Pin name confusion with Allwinner A20 and DDR3L/2GB
DML is Data Mask Low and is the data mask for DQ[0:7]L on the DDR. DMU is Data Mask Upper and is the data mask for DQ[0:7]H

The corresponding A20 signals (if you are using a single DDR) are SDQM[0] and SDQM1

DQU0 is Data bit upper 0 and would map to SDQ[8]

DQSU and DQSU(with a bar) are the data strobe differential pair (upper) and would map to SDQS1 and SDQSB1 (assuming you are using the upper bye of the memory on DQ[8:15] from the A20

This assumes a 16 bit implementation with the lower byte on the memory mapped to DQ[0:7] at the A20 and the upper byte mapped to DQ[8:15] on the A20.

For a 32 bit implementation, just continue the same technique for data bits 16 to 31.

This requires an understanding of DDRx interfaces to be able to map across different naming conventions (which is very common).

Picture with the names you are confused about:



Note: extra clock signals are often provided to prevent timing skew due to loading. If you intend on using just 2 devices use both clocks (clk to 1 device, clk1 to the other device).