What is the difference between a PLL and a DLL?
A PLL controls a voltage-controlled oscillator in order to bring its frequency (or some derivative of it) into phase (and frequency) lock with a reference signal.

PLLs have many applications, from creating a "clean" replica of a noisy reference signal (with amplitude and phase variations removed), to creating new frequencies through multiplication and division, to demodulating phase- and frequency-modulated communications signals. The input-to-output transfer characteristics of a PLL can be controlled through the design of its feedback network.

A DLL controls a voltage-controlled delay line, which typically has many taps, in order to bring one of those taps into phase alignment with a reference signal. The input to the delay line is usually also the reference signal, so the various taps provide additional signals that are interpolated and/or extrapolated from the period of the reference signal.

DLLs are commonly used in high-speed communications among chips on a board (e.g., between a memory controller and its SDRAM chips) in order to "cancel out" things like input and output buffer delays as well as wiring delays, allowing very tight control over setup and hold times relative to the clock signal. This allows data rates to be much higher than would otherwise be possible.

With suitably-designed phase detectors, both PLLs and DLLs can work with nonperiodic reference signals; a common application involves aligning data signal transitions with a reference clock.

While the mentioned above (i.e. clean version of signal -> PLL) a key aspect of where PLLs/DLLs differ is that PLL's filter and effectively block jitter in the source from affecting the VCO output, whereas DLL's propagate jitter.  At  first this may appear to be a negative aspect of DLL's but it can be used to great effect.  In some cases you need to pull the main sampling point from the signal that is arriving and ignore the jitter in the signal, you would use a PLL.  In other cases, say when a signal and clock signal are subjected to the same jitter inducing effects either at the source or in the communications channel.  You can use a DLL and multiple sampling delay times to reduce/eliminate the relative jitter between the two signals (because they have the very similar jitter) and use the delayed clock to align to an ultimate sampling point.