clk prescaler with possible glitches
(From a Xilinx experience)


You can place a timing constraint to ensure that the propagation time of the combinatorial parts (around the XOR) are kept shorter than the clock high and low states. Ideally, they should be balanced.
Clock buffers are automatically inferred when a commbinatorial signal is used as a clock input. You can check that by reading the synthesis report.
Some FPGA families have special glitch avoidance clock multiplexers, which could be used to select between the 'direct clock' and the 'clock division' paths : "BUFGMUX"
You can use a clock multiplier PLL to generate a 2X clock and achieve 50% duty cycle whatever the input clock shape is.


If you only need low frequencies (maybe up to 50...100MHz, depends on FPGA family), the combinatorial XOR should work. If you need high frequencies, a PLL, and/or clock multiplexers should be better.