How to handle Register output in state machine with verilog
You should probably synthesize your design to be sure, but I expect that your example will result in Out_Reg being generated from combinatorial logic. It could more conventionally be expressed as

wire Out_Reg;
// ...
assign Out_Reg = state ? a : b;


If you want Out_Reg to be the output of a physical register (flip-flop), you could write

reg Out_Reg;
// ....
always @(posedge clock) begin
    Out_Reg &lt;= state ? a : b;
end


But then, of course, the value of Out_Reg is delayed by one clock cycle relative to the state of state. If you need it to be in sync, you would need to duplicate the state logic so that Out_Reg anticipates what the next state of state will be. You could simplify this by using combinatorial logic to create a next_state signal:

wire next_state;
reg state, Out_Reg;

assign next_state = /* logic to determine next value of `state` */
always @(posedge clock)
    state &lt;= next_state
// ...
always @(posedge clock)
    Out_Reg = next_state ? a : b;


However, you should also consider whether this is necessary. Does your downstream logic really care whether the output of this module is physically sourced from a register or from a combinatorial gate?