Design an interfacing circuit/address decoding circuit to interface one 4KB EPROM and two 2KB R/W memory for 8085 microprocessor?
First have a look here: http://searle.hostei.com/grant/index.html . You will see how a decoder circuit looks like. Whatch also for additional I/O devices, each circuit has an enable or chip select active on a range of address:




  1) How to find the ending address for these 2 devices? 2)and how to
  design a proper circuit for it?


Arbitrary selection in the available address space for RAM, while ROM shall be at the reset vector.


  2)and how to design a proper circuit for it?


By doing truth tables, you can separate address ranges so that you have a minimal gate count for decoder circuit. It would be nice, in your project to have RAM addresses contiguous.

https://iemcse.files.wordpress.com/2017/07/cs502snscm4.pdf