Bidirectional assignment in Systemverilog
If you are trying to model a bidirectional mux, the tranif primitives might
be more appropriate/easier, depending on what your end goal is.

tranif1 #(t_on, t_off) ( a, b, ena);

so

tranif1 #(1, 1) ( net1, net2, config );

tranif0 #(1, 1) ( net2, net1, config );