When are meanders necessary? and how to calculate timing differences
SPI is a very different case. 

Here the clock is related to ONE output and ONE input. They are both clocked from the same source, so meandering is not particularly useful or advisable and it may be harmful. In fact the clock to data transitions are so far apart that up to the highest feasible frequency with SPI meander would not add any effect. Once you need to meander, you will be mis-clocking the returning data anyway.

Meandering is for directionally related signals, such as USB is: The D+ and D- signals need to arrive at the same time at both devices on the wire, and since they go at pretty high speed, meandering is very helpful to get very high fidelity data on both ends. The same goes for RAM busses, where there are 8, 16, 32 or 64 data lines that need to arrive at the chip at the same time as well as at the right clock edge.

A general rule of thumb is to use 66% of the speed of light (speed of light =~ 2.9979*10^8 m/s) for transmission speed along a copper trace, some types of plating or post-processing can have some minor effects on that, but 66% is not often far off the mark.

Let's say you have some signal, transmitted at 100MHz and an allowed skew of 1/8th of the data transmission cycle (aka: clock cycle). (Skew is what it is called if two signals get sent out at the exact same time, but arrive at a different time). Then you get a maximum differential delay time of:

t = (1 / (100*10^6)) / 8 = 1.25ns (as t = 1/f and /8 accounts for the 1/8th design rule of the signal)

So in that case you generally try to design for a differential delay of up to half that, but certainly never more than 1ns, because there's also production tolerances and some chip-insides that may play roles and you don't want to get caught out on 100ps.

Let's say you live on the edge and design for 1ns, you get, with 66% of 3*10^8 m/s speed of transmission:

trace length difference limit = 1*10^-9 * 0.66 * 3*10^8 = 198mm

But be aware that this is assuming the clock only needs to deliver data in one direction with this amount of fidelity, if you use the same clock to get the data out of the chip and you want it to arrive in time at that rate of transmission, you need to take that number as the maximum total length of the longest signal path (clock out to longest data trace return) and for the maximum differential you should try to take 1/4th. 

Unless of course you only do bulk transfers with no timing connotation and advanced design, allowing you to predict when the data comes back from the clock you sent out, such allowing you to back-correct the shift in response from 30cm long traces. But that's something one should try to not ever want to do, given half the option.

Some high-speed designs feature a Clock and Return Clock for such reasons, where the "slave device" clocks the data that comes out on a different trace to the original clock (or possibly sometimes even the same trace). If the master then uses that clock to clock in the data, you can reliably transfer at much higher speeds, because you do not need to account for total clock delay as long as all traces are designed to the limits given by the speed and clocking rules.