How to see the content of the SDRAM in my DE1-SOC while running (JTAG Altera cable)?
If you have a working DRAM-Controller, there are several possibilities. Instantiate a NIOS-II with debugging-option, and you will be able to even debug using Eclipse CDT. If I remember correctly, there is also an Avalon-MM master that lets you peek into memory from System Console.

If however your design is the Controller and you want to debug it, there is no option to access the memory by other means, bypassing your design.

BTW: Using QSYS does not force you to start over, you can embed a Verilog component in a QSYS-project and vice versa. I prefer to have a QSYS-component as top-level entity.