Multiplexing low speed SPI slaves with a high speed SPI master (time-division?)
I don't think this is at all practical.

First, how are you going to get the SPI interface to interleave data? I doubt very, very much that you can pull this off with a dedicated synchronous serial peripheral, and as @ThePhoton points out, if you have to bit-bang the interface the effective clock rate will fall dramatically.

You need a separate 2 MHz clock for each ADC, so that each device sees the appropriate clock edge only when its correct data value is present. You can't just demux the data lines unless you add storage for each data line so that it holds the correct value until the clock edge occurs.

For incoming data you need to do the reverse...capture each ADC MISO line on the appropriate clock edge.