How to calculate the bandwidth of a synchronous bus with overlap in bus transfer and reading next data?
A word is assumed to be 1 byte. The bus is 32-bits wide. To transfer 8 words i.e. 64 bits, it needs 2 send data and send address operations.
So it will be
2 x (1 cycle for send data + 1 cycle for send address + 2 cycles idle time) = 2 x 4 = 8 cycles
One additional cycle for the additional memory read is required because during the first cycle, bus transfer can't be overlapped with reading next data.