Synchronising signals of Verilog test bench with RTL clock
Some comments from somebody who has written hundreds of counters:
First off all, control signals should not arrive a-synchronously. However I object to the phrase [control] signals should arrive after the positive clock edge. This gives the impression that digital logic should be controlled by signals with some artificial delay in it. The solution using a hash-tag emphasizes this even more.

In real life the control signals should arrive and be stable before the set-up time of the register. Therefore in ASIC/FPGA engineering the phrase normally used is the signal should arrive before the clock edge.

This is achieved by the clock to Q delay of a register incremented by the wire delay. There may be (often is) additional logic behind the register which increases the delay. 

In your test bench you can do this simple by:

reg  tb_load; // This is the one use use in your test bench
reg  load;    // This one goes to you DUT (Device Under Test)

always @(posedge clk or posedge reset)
if (reset)
   load &lt;= 1'b0;
else
   load &lt;= tb_load; 


Some tips for your code:
1/ The load signal is dominant. Your code becomes simpler and easier to read if you deal with that first:

if (load)
  ...
else
  if (


2/ Do not use the name 'up_down'. Your counter counts up if that signal is high so call it e.g. 'count_up'.