8085; why we can't reduce number of T-states in opcode fetch machine cycle
You also have to take the memory into account. 

Let's assumes the data is clocked into the CPU on the falling edge of T2.
In your scheme the memory must do an address decode and output the data before the end of T2. 

Looking at the diagram it seems the data is clocked in halfway T3. Probably on the rising clock edge in the middle of T3. Your memory than has to be faster. My estimate is that the memory then has to be about four times as fast. 

Also this idea "Then the process of decoding can be done in T2 state" is using non-stable input data. You are describing an input latch. This is not a good idea.
You are also assuming that the data from the memory can go trough the decoder logic and the result is available at the end of T2. Thus you now have pushed all the decoder processing which is done in T4 also in T2.  

Bottom line: Throughout you 'optimizations' you ignore the signal propagation times. But signals need some time to rise, fall, go from/to tri-state, pass through logic and become stable.