impact of removing "+:d" in verilog timing section
A delay between a source and a destination pin of a module is known as module path delay. These delays are modeled using specify blocks.

There can be two types of delay specification in specify block: Parallel Connection and Full connection. 

In Parallel connection, each bit in source field connects individually with its destination bit. As shown in below image:



The syntax is :

(source_bit =&gt; destination_bit) = delay_value


While in Full Connection, each bit in source field connects every bit in the destination field. As shown in below image:



The syntax is:

(source_bit *&gt; destination_bit) = delay_value


In your case, posedge clk =&gt; (q [B]+:d[/B]) = 0; This is a parallel type of delay connection. This means whenever a posedge of clock signal arrives, the value of q[B] shall change with a delay of 0units. 

Since there is no demarcation with respect to rise and fall times, the delay applies equally to both rising and falling edge of q[B]. 

The polarity operator (+:) describes if data passing from the source to the output is inverted (-) or not inverted (+). The polarity operator is used by timing analysis tools and is ignored by the simulator.

Positive polarity (+:) : This is used when a rise at the source causes a rise transition at the destination and a fall transition at the source causes the fall transition at the destination.

Negative Polarity (-:) : This is used when a rise transition at the source causes fall transition at the destination, and a fall transition at the source causes a rise transition at the destination.

But, modern timing analysis tools rely on their own library, I guess. So, it might be safe to ignore that operator. Somewhat information on polarity operator is available at this link.