Integrated Circuit Layout Design - Dynamic Flip Flop?
It's obviously just a start, but if that is your first layout attempt it isn't so bad.  You're obviously missing lots of details like bulk contacts, labels for your rails, labels on your intermediate signals (Inp) and ports so you can instantiate this at a higher level.  I would use a transmission gate rather than just a NMOS pass gate into the bus holder circuits.  It gives a larger control range and balances out the leakage current into the storage node(s) (gate capacitance of the inverter).  It might be easier to put a simple feedback inverter (bigger L to be weaker drive) to have an actual static bus holder like design to be more robust.

In general a dynamic circuit is something should be clocked for most of it's oppertion, it sounds like you're looking at more of a latching operation so I'd recommend going to a static configuration.