Baffling combinatorial feedback loop message in VHDL with ISE Design Suite
Nice self-contained example and I agree with your analysis ... you are going crazy. No, wait ... in the good old days I'd be submitting this as a probable bug on Webcase. Now, you can try asking for comments from Xilinx staff on their own forum.

One not-too-hygienic construct : initialising c to "00" in the declaration is normally supported by Xilinx synthesis tools but possibly not for all architectures : I'd suggest adding a Reset input and assigning c &lt;= "00"; in an if Reset clause, in case XST isn't obeying the initial value here and thus can't infer an initial state.

Other things to try 


for some target devices, XST uses one VHDL parser with one set of bugs, for other target devices it uses a different parser. You can switch between parsers (possibly not for all targets) by setting the "Use New Parser - Yes" tick box (under Synthesis / Properties / Advanced View").
Vivado appears to have yet another VHDL parser you could try.