Can someone help me complete this Verilog code for this sequential circuit?
Your state diagram looks good.

Your state transition table looks fine.

Your Verilog is not at all right. It's so far from right, it's hard to know where to begin fixing it. 

In my experience, the best way to write Verilog, especially for synthesis, is to simply follow templates given by the synthesis tool vendor. For example, Xilinx has a Synthesis and Simulation Guide that shows how to code various kinds of structures in Verilog. The finite state machine examples start on p. 79.

Here's their example of a simple finite state machine in Verilog:

module v_fsm_1 (clk, reset, x1, outp);
 input clk, reset, x1;
 output outp;
 reg outp;
 reg [1:0] state;
 parameter s1 = 2'b00; parameter s2 = 2'b01;
 parameter s3 = 2'b10; parameter s4 = 2'b11;
 initial begin
   state = 2'b00;
 end

always@(posedge clk or posedge reset) begin
   if (reset) begin
     state &lt;= s1; outp &lt;= 1'b1;
   end
   else begin
     case (state)
       s1: begin
         if (x1==1'b1) begin
           state &lt;= s2;
           outp &lt;= 1'b1;
         end
         else begin
           state &lt;= s3;
           outp &lt;= 1'b0;
         end
       end
       s2: begin
         state &lt;= s4; outp &lt;= 1'b1;
       end
       s3: begin
         state &lt;= s4; outp &lt;= 1'b0;
       end
       s4: begin
         state &lt;= s1; outp &lt;= 1'b0;
       end
     endcase
   end
 end
endmodule


This is for a totally different state machine than yours, so you'll have to work out how to express your machine in this format.

Notice the structure: One giant case statement that handles all the state transitions and outputs.  Also, they parameterize the state encoding so that the synthesis tool can reassign the actual codes if there's a reason to. For your assignment, since you had to determine the state encoding yourself, it's equally valid to just use literal values like 1'b00 in your code instead of parameter names like st0.

Another thing to notice is that Xilinx's style requires the output assignments "look ahead" to what the output needs to be in the next state. This does allow the output to depend on both the current state and the prior state, but this is a feature you don't need. For your problem it might be more straightforward to output generation into a separate block.