How to indicate different voltage levels in schematic drawing
Absolutely, absolutely ABSOLUTELY the power symbols. 

Anyone who uses net labels (local or global) for power distribution should be fired.

The entire purpose of power symbols is to allow them to be quickly visually distinguished from local or global net labels, allowing the schematic to be more easily read and maintained.

I have dome a fairly significant amount of work troubleshooting and cleaning up schematics drawn completely with net labels, and it's a nightmare.

Furthermore, if you have to use net labels for some weird reason, strictly follow the local-global hierarchy. Many EDA packages let you set all net labels as global. If you do this, please die in a fire.
Only use global net labels when you have to. Nets should be local by default.  

An even better option is to use an EDA package that enforces hierarchical schematic interconnects. This way, each schematic is represented as a "meta-component" on a higher-level schematic. Basically, every global net-label on each schematic is reflected as a pin on an higher-level drawing. 

This makes the sheet-to-sheet interconnections immediately clear, and lets you trace out where, exactly, a net label routes.

Also, you should only ever have one global net label of every name on a sheet. If you have two devices that need to connect to that global net wire them together with a schematic wire. This is vital in situations where you are not the only person working on a schematic, and useful in all others, because it makes the schematic much more intuitively understandable.



Frankly, net labels are very, very overused as it is. The only situation where you should chose a net-label over actual schematic wires is when it improves readability. Unsuprisingly, this happens very rarely.

I see a lot of schematics these days that are basically a random assortment of chips tied together with net labels. 

This is a ABSOLUTELY HORRIBLE way to do schematics.
If you have ever spent time tring to understand or modify a schematic drawn by someone else, which is based around net labels (particularly if it's complex), you will hate them with the fiery passion of a thousand suns. 

NET LABELS ARE ANTI-MAINTAINABILITY.
They are (rather literally) the GOTO statements of schematics.



 They connect somewhere else, and you have to manually find it (unless your EDA package lets you follow nets, but then, what if you're working on paper documents?). They may completely break out of the local document structure. They may have non-obvious effects, and mis-spelling things can cause errors which the DRC checking will not catch, because enforcing rules on net labels can be difficult. 



One thing of note is that, (as Brian Carlton points out in a comment), that using net-labels to indicate the function of an existing wire is a very good thing to do. 


  Net labels are only GOTO-like if they are connected by name. Otherwise they can just help debugging. For example DATA0 between a uC and SRAM on the same page.