Creating Cadence Virtuoso Layout in Rectangular MOS Power device
The Cadence tool is what you use to draw the transistor with, the requirements for how the transistor is drawn and fabricated is determined by which foundry you will be using and what their Design rules documents require.

Cadence cannot help you with those details.

In a drawn transistor the width is the width of the active area as drawn the STI or LOCOS etch. The length of the transistor is actually the width of the poly line drawn over active forming the channel area.

How much active area you consume for the S/D areas and how you contact the body (Well) is all depending upon that process design document.

In fact the proper way to draw tis would be to draw a smaller transistor that is 1.6u long, and then lay out a mesh of these transistors and connect them in parallel to get the width you need.  This will get you better matching that a single huge piece of active.  Which is usually not permitted in most PDKs.