VHDL internal timer not consistent time
You should know that the kind of initialization you are using for tmr_cnt may not be synthesizable. If you don't explicitly reset this counter it could power up with an unknown value. If that value happens to be greater than C_2SEC_TC then your 12-bit counter will have to count up until it rolls over and reaches 1023 before tc_2sec will go low.

If the problem is occurring on the first pulse after power up then I would suspect this kind of problem. You will need to add a reset signal to your design and use it to clear the counter. It would be helpful if you included a link to the manufacturer's datasheet for your CPLD.