Output Register and pipeline implementation
That statement is too simple.

Following that statement any design can be sped up to run at Terra-herz just be adding more and more registers. But we know that is not the case.

In general if a logic cone (A group of gates with inputs and an output) stage takes X nano-seconds, you can sometimes split the logic in two parts each taking X/2 nano-seconds by adding a register stage in the middle. 
But you do not get exactly X/2 because adding the register comes with it's own timing cost.

To begin with: you have to subtract the set-up and hold time of the register from the time you gain. On top of that you have something called 'clock uncertainty' which you have to subtract. Then you have the delay of the register: clock to out. 

But adding a register stage also upsets all the timing in any feedback path. refer to the diagram above:
If L1 is too slow and you add a register stage, the path from R1 back into R1 suddenly takes an extra clock cycle and the resulting circuit will no longer behave the same. That is why e.g. in a CPU you suddenly have to implement 'register folding' and other techniques to cope with a long pipeline. 

Conclusion:
Yes, you can sometimes speed up a design by adding register stages but it is no panacea, it requires thought and often you have to re-think your design: back to the drawing board.