How to send logic low to LVDS?
The differential input voltage will have a nominal average signal level of 1.2 V.

To supply a constant value, just drop a 100 Ω resistor across each pair, and source 12 mA through each. Make sure you add an additional 100 Ω before the first pair, and after the last so that no input is connected  directly to VCC or ground.

This is from the TI SN65LVDS4 datasheet (the receiver I typically use).




  One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that the output logic state can be indeterminate when the differential input voltage is between –50 mV and 50 mV and within its recommended input common-mode voltage range.
  Open circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, TI recommends to have an external failsafe solution as shown in Figure 20. In the external failsafe solution, the A side is pulled to VCC via a weak pullup resistor and the B side is pulled down via a weak pulldown resistor. This creates a voltage offset and prevents the receiver from switching based on noise.