pull-push gate driver for H bridge circuit
Your question has changed substantially from its original form that I wrote this answer for as it as being closed.  The answer below only addresses driving a high side P channel MOSFET using what you call your "push-pull" circuit that you originally posted:





You sortof have the right idea of how to drive a high side P channel FET, but missed some details:

There is nothing limiting the voltage swing of the gate to the valid range.  24 V is too much for many FETS.

Get rid of R95.  I can't even guess what purpose you think it serves.  It will only slow down the response.



Here is a better circuit using your basic concept:



This circuit is for when the power supply is at least a few volts more than the desired FET gate swing.

Instead of operating Q1 as a switch, it is a controlled current sink.  With 3.3 V on the base, there is about 2.6 V across R1.  That means the current thru R1 is 9.6 mA.  Most of which comes from the collector.  Therefore, when the digital signal is low, Q1 is off.  When high, Q1 sinks a bit over 9 mA, regardless of the power voltage.

9 mA thru 2 k&Omega; would result in 18 V.  The Zener diode D1 will limit this to 12 V.  12 V across R2 results in 6 mA.  The remaining 3+ mA flows thru D1, clipping the voltage to a safe level for the gate.  Most FETs are fine with 12 V on the gate, but as always, check the datasheet for the particular FET you are using.

The remaining transistors, Q2 and Q3, are a impedance buffer at the expense of losing about 700 mV at each end.  The 2 k&Omega; impedance of R2 together with the FET gate capacitance would result in slow rise and fall times.  The double emitter follower buffer reduces that 2 k&Omega; impedance by the gain of the transistors.  If the gain is 100, for example, then the FET gate is driven with about 20 &Omega;.  That's much better.

Generally the 700 mV loss at each end doesn't matter, but you should consider it.  With a 12 V zener, that means the gate is driven to 11.3 V instead of 12 V.  Most FETs are specified with good RDSON at 10 V, but check your datasheet.  On the other end, 700 mV should be well below where the FET does much of anything, but again, check the datasheet.

It is a good idea to put a pullup resistor on the gate so that the gate floats to 0 V eventually.  That also helps with startup.