Altera Quartus Design Assistant Critical Warnings
Care has to be taken when using the asynchronous clear input of flip-flops:


The reset pulse must be long enough as defined in the datasheet, to reliably reset the flip-flop.
Reset pulses shorter than the minimum pulse width may lead to an unknown state. Thus, asynchronous inputs should not be driven from combinational logic because the output of the combinational logic (which drives the asynchronous clear) may toggle several times until it settles to the final value, also known as glitch.
The asyncronous clear should also not be connected to the output Q of the flip-flop because when Q rises (after a clock edge) and reaches the threshold for logic high, a reset is applied and Q falls again. This leads to short reset pulses which may violate the minimum pulse width.


A good design practice is to connect the asynchronous clear only to a global reset signal which is de-asserted synchronously to the active edge of the clock. Then the asynchronous clear of all connected flip-flops are released at the same time, and enough time before the next active clock edge. Timing constraints are required to ensure this.

To de-assert the reset synchronously, you should use a reset synchronizer which is composed of two flip-flops connected in series:

signal reset_ff : std_logic_vector(1 downto 0) := "00"; -- low-active
signal reset_global : std_logic; -- high-active

process(n_Reset, System_Clock)
begin
  if n_Reset = '0' then
    reset_ff &lt;= (others =&gt; '0');
  elsif rising_edge(System_Clock) then
    reset_ff &lt;= reset_ff(0 downto 0) &amp; '1'; -- release reset
 end if;
end process;

reset_global &lt;= not reset_ff(1); -- high-active


More information can be found in the paper Asynchronous &amp; Synchronous Reset
Design Techniques - Part Deux from Cliff Cummings (Sunburst Design) et.al. .

The reset synchronizer would allow to reset the design only globally, e.g., from an external input (button). To reset only some flip-flops, one should use the synchronous reset sclr instead. The timing analyzer will check that all contraints are met.

But, you cannot easily replace aclr by sclr because the synchronous clear will not take place until the next active clock edge. Thus, you have to likely issue the synchronous clear in the clock period before.