CD4006 Behavioral model in LTSpice
At the top of page 6 in the datasheet is a small diagram showing how each flip-flop is constructed from transmission gates and inverters. The transmission gates need both the true and complement of the clock, and it is often easier to generate these globally for all of the flip-flops rather than internal to each flip-flop. So, !CL (or \$\overline{CL}\$) is just the complement of the clock signal.