Same Priority Interrupt on ARM Cortex M0
The core ARM architecture supports two different types of interrupts - pulse sensitive and level sensitive. (See ARMv6-M Architecture Reference Manual, Section B3.4.1) In either case, if two interrupts happen at the same, or one of them happens while the first interrupt is being processed, the second interrupt will be processed when the first interrupt service routine returns and re-enables interrupts.

The source of a level-sensitive interrupt will stay active until the interrupt service routine clears it. If the interrupt service routine does not clear the interrupt source, a second interrupt will be generated as soon as interrupts are re-enabled. The source can be cleared by reading a data register for instance, or in some cases by explicitly clearing a flag.

The pulse sensitive interrupt will set a flag that will generate the interrupt, however the pulse needs to be long enough for the processor to catch it. If the pulse is not long enough, it will not be caught. The interrupt service routine needs to explicitly clear the flag.

I am not sure what will happen in the case where two level sensitive interrupts happen at the same time and the interrupt service routine does something with the peripheral that will acknowledges both interrupts. An example of this would be a USART driver that was handling both Rx and Tx interrupts. I believe that the second interrupt will not be seen since it is no longer active when interrupt are re-enabled. I am right in the middle of an ARM project and unless someone posts the answer, I will do some testing and edit this answer with the results.