How exactly do clock speeds of computers relate to operation speeds?
I am assuming that it will take several clock cycles to complete this


It's rather complicated, but see: https://stackoverflow.com/questions/692718/how-many-cpu-cycles-are-needed-for-each-assembly-instruction

There are basically three factors to consider for a simple explanation:


Cycles per instruction. This will be specified in the manual for the processor per instruction. Can be as low as 1.
Instructions per cycle. Thanks to "superscalar" design and pipelines, you can have multiple instructions in processing at the same time, and potentially "issue" more than one.
Operations per instruction. Thanks to SIMD instruction sets, one instruction can operate on quite a lot of values in a single cycle.


Pipelines complicate timings for "branch" instructions like JNE. You might find that it takes one cycle to not branch and a hundred cycles to take the branch - unless the branch predictor has guessed correctly, in which case those costs are the other way round.

Cache misses take rather a long time as well.