Spartan 6: How do I use my differential clock?
For constraints, do something like this:

NET "clk_P" LOC = "K15" | IOSTANDARD=LVDS_33; ## 6 on U5 EG2121CA, 4 of U20 SI500D (DNP)
NET "clk_N" LOC = "K16" | IOSTANDARD=LVDS_33; ## 5 on U5 EG2121CA, 5 of U20 SI500D (DNP)
NET "clk_P" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 5 ns HIGH 50%;


You only need to constrain the P side, as per http://www.xilinx.com/support/answers/57109.html .  Make sure you get the right IOSTANDARD.  Perhaps LVPECL_25, LVPECL_33, LVDS_25, or LVDS_33, depending on the clock source.  See Xilinx UG381.  You may also need to set DIFF_TERM = TRUE along with IOSTANDARD to enable internal 100 ohm differential termination.  Check the board layout/schematic to see if there is already a discrete termination resistor, in which case you should leave DIFF_TERM off or add DIFF_TERM = FALSE.  

Then you will need to instantiate an IBUFGDS instead of an IBUFG, perhaps something like this:

IBUFGDS ibufg_inst (.I(clk_P), .IB(clk_N), .O(clk_ibufg));
BUFG bufg_inst (.I(clk_ibufg), .O(clk));


Then just use clk as you did before.  Is you're using a DCM or PLL, you should be able to put the DCM or PLL instance in between the IBUFGDS and the BUFG.