Linear Regulator PCB placement
Just consider the inverse load regulation error of the LDO and add the resistance of your trace and return path. It may be negligible, so it does not matter here.
Typically the series output incremental or &quot;knee resistance&quot; is 1 or 2% of the rated voltage/current which is the same thing as your output Load Regulation error.
e.g. 5V/1A = 5 Ω  so 1% of this is 50 mΩ.  Your ESR of your output cap needs to be much lower than this (if you need) to get the  pulse load error much less than Step load Regulation error.
Your trace inductance and resistance may be computed to compute your pulse load response for ringing or noise.    The Zout of the LDO rises with frequency from DC because the loop bandwidth for negative feedback inside the LDO also decreases to unity at the breakpoint.  This is useful, because that also reduces the Q of the pulse noise resonance.
Since RF circuits are generally supply noise sensitive, the impedance of the tracks needs to be compared with the impedance of low ESR cap at the equivalent frequency of the pulse load to compute the peak to peak error in DC amplitude.  But for a known current pulse duration, track resistance and inductance 10nH/cm typ you can compute these easily.  Most likely the location of the LDO is  less important than the choice and location of output Cap recommended by the LDO datasheet.
Always start with Design specs for RF Vdc tolerance, ripple, Idc and Iac vs f and do an impedance or at least a step voltage simulator plot to anticipate problems and non-problems that you are trying to fix. LDO's rise in output impedance with frequency.
If these specs are not known, then breadboard a test circuit to find out unwanted susceptibility and interference and required attenuation. Never assume.