atmega32u4 configure counter in CTC mode
When you comment out the USE_A line, it enables the compare interrupt for channel B instead of channel A. As a result the compare match interrupt vector is now TIMER1_COMPB_vect. 

However you have not defined an interrupt handler for this which means when the compare match occurs the interrupt call results in exception that leads to the program restarting from the reset vector, hence you see it reset at the same rate as when A was used.



In order to get a compare match to occur every 42 cycles, you need to use "CTC" mode. There are two variants to this - the first uses OCR1A as the compare match, and the other uses ICR1 as the compare match. When in the correct mode a match with one of these will automatically clear the counter.

However, you have set TCCR1A and TCCR1B to 0 which in turn will set all of the WGM1x bits to be zero. This selects the "Normal" mode of operation. In this mode a compare match with either OCR1A or OCR1B will trigger the TIMER1_COMPA_vect and TIMER1_COMPB_vect respectively, but won't reset the timer meaning that it has to count all the way to the top (65535) and overflow between each compare - so the interrupts occur every 65536 cycles regardless of what you set the OCR1x registers to.

In order to use OCR1A as the top and get it to interrupt every 42 clocks, you need to set the correct mode. The modes are listed in Table 14-4 in the datasheet. Mode 4 is CTC with OCR1A as the top value. This implies you need to set the WGM12 bit in the TCCR1B register to be a 1.

With that bit set, and OCR1A set to 42, you should then get an interrupt occurring every 42 counts.