Why have two NOT gates in series?
Possible reasons:


Load Balancing

The driver of A has an unknown number of fan-out to drive. Fan-out within the circuit and the parasitic it induces can be calculated for the specific circuits, but we do not know the other circuits that are connected the driver. Essentially the inverters are being used as buffer equivalent. and help manage the parasitic.

Timing and total current

To reduce the transition glitch, the second state inverters can be sized for a faster transition switch. Doing so makes the NAND gates input update near the same time. With the inputs changing less periodically, power can be saved and transition glitches can be reduced.

Signal boosting and power

Lets say VDD = 1.2V but the input is 0.9V. The input is still a logical 1, but considered weak which causes slower switching and burns more power. The first inverters can be sized to handle transitions better, making the voltage more predictable for the rest of the design.
There is also a possibility of the change in the voltage domain. In this case the inverters in the first state can act as a step down, e.g. a 5V input domain to 2V domain.

Any combination of the above