How data movement from large register to small register works in VHDL?
The default behavior is to match up the bit indices, so if you have

signal reg32 : bit_vector(31 downto 0);
signal reg8 : bit_vector(7 downto 0);

reg8 &lt;= reg32;


it is equivalanet to

reg8(7 downto 0) &lt;= reg32(7 downto 0);


However, any decent VHDL compiler should give you at least a warning about the width mismatch.