power from glitches vs power consumed on pinelining
It's a very unusual low-speed design, and I suspect that you're going to have to address these concerns by simulating different implementations and measuring the power used by the simulation.

I would have thought that the low clock frequency also means the maximum number of glitches possible per second is very small, so your power consumption will be dominated by leakage, and therefore you should use the non-pipelined implementation.

This paper describes a technique for glitch minimisation by matching delay. That could equally be applied to CMOS implementation.

It might be viable to apply a set of test vectors to the circuit (after layout!), instrument it with glitch detectors, and hand-fix the most important areas.