VHDL: enumeration types in entities of submodules?
Use a package and include that package at the top of each module.

Here is an example of a package:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package my_package is

    type type_enumexample is (left, right, top, bottom);

end my_package;

package body my_package is

end my_package;


To include it in each module just add this where you have your other use statements:

-- The package is compiled to this directory by default.
-- so don't forget to include this directory. 
library work;
-- This includes the particular package into your program.
use work.my_package.all;


Every module you include the package on, you can use your custom enum type.