What is the use of OFFSET IN/OUT constraint for FPGA design when using register in IOB?
Do OFFSET IN and OFFSET OUT constraints add any "value" to a UCF? Do
  they provide the tools any more information about your design that is
  needed for the I/O timing to be correct?


That is exactly what they are there for.  Although you say in your question "assume the register is in the IOB", my point would be that I don't need to care whether the flipflop is packed into the IOB - if those constraints are accurately specified, complete and met by the tools.

Forcing flipflop packing is often a useful way to get the best possible timing, but I still add OFFSET constraints so that if anything goes awry I find out about it.