Reset circuit for D-flip flop?
The classic POR (Power On Reset) circuit with a 74HC74 looks like







simulate this circuit &ndash; Schematic created using CircuitLab

The R1/C1 time constant is set to be significantly longer than the rise time of the power line, typically 10's of milliseconds. The two inverters are Schmitt triggers because the capacitor voltage rises relatively slowly, and CMOS does not handle slow transients gracefully. The transform the exponential waveform to a nice clean logic signal. The diode protects the first inverter in the event of a fast drop in power voltage by discharging the cap rather than letting the current flow through the inverter.

If you're feeling lucky and/or cheap, you can eliminate the inverters, especially if you can guarantee that the clock input will be inactive during the transition period. And you only need one of these POR circuits to provide a power-on signal for an entire logic system, so the added complexity is usually lost in the wash for larger systems.

Alternatively, you can use a dedicated power supervisor chip such as the TL7705 and others of its ilk.