How to take bank configurations in NAND flash chips into account?
The interfaces are pretty much the same. Usually it's x8 or x16 bits (16 bit more likely given the high density) wide. Some timing might be different.

The addressing is different, however, depending on size of blocks/pages etc. But this is all handled in software, so it's not that big of a difference unless performance was taken into account (sizes can affect it, but usually this is noticeable at high throughputs).