CE# pin pulsed low by ARM when configured
It looks perfectly normal to have \$\mathrm{\overline{CE}}\$ low for an external memory controller. The external memory will ignore all signals if \$\mathrm{\overline{CE}}\$ is high. \$\mathrm{\overline{CE}}\$ is often logically combined with the output of a partial address decoder to avoid several devices simultaneously accessing the databus.

You probably won't have pin conflicts with GPIO as long as you don't change the pin's function from FSMC to GPIO.