How can I avoid a clock glitch?
To avoid the possibility of the glitch, you might consider making the read signal a registered output. This will require some redesign of your state machine, since if you simply put a register in front of your AND gate, the read pulse will occur almost one clock cycle later than without the register. Therefore you will have to change the fan-in to your AND gate to select state 101 rather than what you currently have, which selects state 110. With this done, you may put a register in front of the AND gate clocked from the same clock as the counter. This will generate the read pulse at about the same time in the 8 state cycle as what you currently have but without the possibility of the glitch.