Why a potential divider at high speed LVDS clock outputs?
Those resistors are simply biasing the receiver correctly to a common-mode DC voltage of 0.6V. There isn't enough context to determine why this is necessary; my guess would be that they're connected to an I/O bank that is using the 1.2V supply as Vcc, and the receivers need to be biased to 1/2 Vcc.

The resistors have little effect on the signal voltage, and they're not terminators, either.