Free IDE for VHDL and Verilog
1st of all: welcome to the world of logic design.
2nd you need to understand the &quot;designflow&quot; (important buzzword!) designflow in VHDL/Verilog is :

think about a design you want to implement, e.g. an adder
implement the design in VHDL/Verilog
implement a testbench in VHDL/Verilog
use the testbench for simulating your design (from step 2)
if this works and the simulation is successful, try to synthesize the design
do all the other stuff, like map, place and route
build a .bit file
use your JTAG to program your FPGA
PROFIT! (hopefully)

so, as you can see, these are a LOT of steps. for quite a few of them are open source tools available. Only free would be pretty boring, so I will try to show you what the market has.

for step 1) the most important is Libre/openOffice Calc, paper and a pencil and if you have large FSMs maybe Qfsm
step 2) you need a good editor, grab one you like and everything is fine. there are a few specialized for VHDL, the best is sigasi (you have to google this one, spam prevention). For this task you can already use one of the big vendors IDEs, but trust me, that ist NOT what you want
step 3) -&gt; step 2
step 4) here are a few possibilities: Xilinx ISim, (Altera) Modelsim, (Lattice) Aldec, ghdl in combination with GTKWave. I think there are more Simulators, but this should be enough for beginning. All these tools are Simulators only, although they bring a full IDE (except of ghdl).
step 5) do yourself a favour and use the tool provided by the manufacturer of your FPGA. if you are experienced enough you could try Icarus Verilog, too.
step 6 and 7) no other chance than using the vendortools
step 8) so many tools do that, even the tools provided by the FPGA vendors. i like using commandlinestuff, so i keep using some obscure flashing programs, but vendortools are okay, too.

hope i could help