Ring counter in verilog
First of all, initial commands are not used in synthesizable Verilog code. And I am not sure if I follow why you are using it, given you have already a reset state for it.  

Secondly, in you else statement, you are using a blocking assignment in "tmp = q[0]" which is ok, because it stores q[0] value in a variable internal to the process.  

What is not OK, is continuing using blocking assignments in  "q = q &lt;&lt; 1" and in "q[3] = tmp". It does not make any sense, you are modeling a sequential output, you should model it using a non-blocking assignment like: "q &lt;= q &lt;&lt; 1" and "q[3] &lt;= temp". I don't know what the simulator will do, but probably he will change q signal as soon as it executes this line, and not at the next rising edge clock as you should expect. As the synthesizer won't be capable of doing that, you are going to have hardware behavior which is not modeled by you simulation. (very serious)

I have also noticed you do not perform a reset in your module. This is surely a malpractice, the first thing you should do, before pumping any data into your module is to reset it.  

Lastly, have you checked in you waveform that you have a rising edge at the same time you send a load signal level high? As far as I have read your test bench I do not believe this occurs.  

So you don't reset you module, you don't send a load at a rising edge, and you are complaining your output is at X? Well, you should re-read all the basics of Verilog, and learn how to properly use a simulator.