Pulse on edge of different clock
Your second implementation fails because of what is a common mistake. The code pattern:

if rising_edge(clk_a) then
    signal_a &lt;= '1';
elsif falling_edge(clk_b) then 
    signal_a &lt;= '0';
end if;


Cannot be realised in hardware, because it describes a 1-bit register with two different clock inputs. Such a register does not exist in the FPGA fabric; the closest is a DDR output register which may be present, but even this is intended to be used with a clock and its inverse, not two totally separate clocks.

The first attempt looks more sensible. If you could include the error message that it generates, I will update my answer.



Now that you added the error message, I can see that this has nothing to do with the code snippet you posted. Although the relevant code has not been provided, I think the error here is that you have your GMI clock input connected to an IBUFG, and also to the logic in this module.

The most likely cause of this is that you have created your PLL code using CoreGen. CoreGen will needlessly place a global clock buffer between a clock input pin and a PLL/DCM instance. The result is that when you connect this same pin to something else (i.e. your edge detection circuit), the design cannot be routed because of the structure of the FPGA.

To solve this, all you have to do is remove the BUFG instantiation from the .VHD file that CoreGen created, and then connect what was the input to the BUFG, to the input of the PLL/DCM instance. Synthesis will insert a clock buffer in the appropriate place to allow your design to work.

Per the comment by @TomCarpenter, if the above solves your problem, there is an option in CoreGen to set the input buffer to "None". This avoids modifying the CoreGen output, which could catch someone out later on.

Even better would be to not use CoreGen for something as simple as instantiating a PLL; If you go to Edit > Language Templates > VHDL > Device Primitive Instantiation > Spartan 6 (or whatever) > Clock Components in ISE (it's under Window > Language Templates > etc in Vivado), you can find simple templates for instantiating your PLL, without the hassle / problems of CoreGen (such as the problem that you have seen).