Finding drain voltage for a resistor loaded CMOS inverter with 0V at input terminal
The issue here is that the output voltage is determined by the output impedance of both transistors. In the most simple model, the IV curves of the mosfets in saturation are completely flat.

This figure illustrates the issue (though I shifted the voltages with 2.5V, and ignore the currents as I just used a random model to make my point):



The blue lines are the drain currents of the NMOS for a number of different \$V_{G}\$ voltages. The green lines indicate the current through the PMOS for varying \$V_{G}\$ voltages - remember, \$V_{out} = 5V - V_{SDp}\$.

If you tie the gate voltages together, then as \$V_{GSn}\$ increases, \$V_{GSp}\$ will decrease. You select a blue and a green curve appropriately and find the intersection of the two curves to find the output current and voltage. You can read the output current on the Y-axis and the corresponding output voltage on the X-axis.

The most basic equations assume that the current is constant in saturation. This usually is not an issue, except for the single case where the horizontal lines match up. In other words, the intersection of the blue and green graph is not unique, but can be a whole range of points. And it is exactly in this situation that the exercise is biased. You will not find the output voltage using the "conventional" lowest level equations.

In order to solve it, you will have to account for the output impedance in saturation. This is the slope of the current when in saturation, and is typically modeled with the equation

$$i_{DS} = \frac{1}{2}k'\frac{W}{L}(V_{GS} - V_{T})^2(1 + \lambda V_{DS})$$

This is solvable, but you'd need more information about the mosfets that is not provided.

My advice is not to overthink it too much at this stage. Consider the inverter to be completely symmetric (ie. nmos and pmos are "matched"). If the input is in the middle, then the output is in the middle.