How DDR2 SDRAM works?
Given the lack of detail in your question, here is a brief generic overview.

SDRAM, like SRAM, is a memory. To write to it, you present an address and some data, and to read from it, you present and address and get some data back some time later.

However, unlike SRAM, SDRAM requires both initialization/configuration at startup as well as ongoing refresh activity in order to operate correctly. Also, the internal structure imposes a multi-level addressing scheme involving banks, rows and columns. All of this means that you need to have a controller for the SDRAM inside your FPGA that manages all of these activities while working within the timing and sequencing rules imposed by the SDRAM chip. This controller generally takes the form of a fairly complex state machine that runs at the same speed as the SDRAM interface.

Xilinx provides a SDRAM controller generator as part of its design toolchain, and in some FPGAs, there is a dedicated, or "hard core" memory controller.