Lpc1769 Adc Reading Problem
One possibility:  

The part contains a successive approximation style ADC, which means that the ADC gets an "answer" one bit at a time.  It places a "1" in the most significant bit of a DAC and compares the output of the DAC to the input signal.  If the input signal is higher than the DAC output, it leaves the "1" in this position.  If the signal is lower, it changes the DAC input to a zero.  Then it repeats this operation on the second-most-significant bit and so forth until all bits are done.

This process depends on the signal being the same amplitude all the way through the conversion.  If the input signal changes during a conversion, the process fails. You can see that it will not be able to convert an appropriate peak value (either positive or negative) unless the signal remains at the peak value throughout a full conversion period.  One possible explanation for your problem may be that at higher frequencies, the input value is changing during the conversion period.  A solution might be to implement a sample and hold at the input.