Open-source layout routing tool
No, you can't (with standard tools) do autorouting of transistor-level designs without standard cells. There are many issues that must be addressed when creating VLSI designs that are beyond the abilities of automated routers. The standard cell library is hand-crafted in such a way that these issues are invisible to the autorouter. For example, an efficient VLSI design must carefully plan the location and width of the power lines so that the P-well and N-well contacts (taps) can be made without blocking the routing of polysilicon gates. Unlike PCB design, the minimum pitch of every routing layer may be different and the sheet resistance of some layers may be much higher than others.