Optimize PNP/Diode Schematic
Keeping in the sentimentality of the original question.  Use SPDT switches.







simulate this circuit &ndash; Schematic created using CircuitLab

The digital logic is surprisingly more complex.
$$D_1 = SW_1$$
$$D_2 = \overline {SW_1}\  SW_2$$
$$D_3 = \overline {SW_1}\  \overline {SW_2} SW_3$$
$$D_3 = \overline {SW_1}\  \overline {SW_2}\  \overline {SW_3} SW_4$$


I leave the first because it did lead me to the second.  I don't think it can be done with transistors due to biasing.

Second attempt...







simulate this circuit

Why do I have the feeling I'm not allowed to use MOSFETs?