Need to implement a phase locked frequency converter from 32768Hz to 36000Hz. How would I go about it?
Specifications, specifications, specifications. 

What jitter is required on your divided down signals? 

If they need to be clean enough to run an RF synthesiser from, then you need a synthesiser to make the 36kHz, either integer division to 32Hz (as suggested by Mr Drummond) to lock, or fractional division to do the phase comparison at a higher frequency, which will result in a lower phase noise.

However, I'm guessing that you may be able to tolerate a 30uS tange of jitter on your divided down signals. In which case, you can stick with your 32768Hz clock source, and use an Arduino or PIC to deliver your 24Hz signal by dividing programmatically by 1365, 1365, 1366, repeatedly. It's very straightforward to come up with similar sequences of numbers for other low frequencies.

When you know what you want to make, the options available to make it will become clearer.