How can I transform the code for a read-write register to a read only register in Verilog?
To read its content at the given address... 


I suspect your code has been reduced a bit too much, it is not looking at all like a CPU interface. This might be a school assignment so I only provide an outline of the code. (Which, by the way, has not been syntax checked)

...
input [7:0] read_only;
...
reg [7:0] write_only;
reg [7:0] read_write;


always @(posedge clk or negedge reset_n)
begin
   if (!reset_n)
   begin // set reset value of registers
      ...
   end
   else // clocked
   begin
      if (cpu_write)
         case (cpu_address[2:0])
         3'b000 : write_only &lt;= cpu_write_data;
         3'b001 : read_write &lt;= cpu_write_data;
         endcase
      else
      if (cpu_read)
         case (cpu_address[2:0])
         3'b001 : cpu_read_data &lt;= read_write;
         3'b010 : cpu_read_data &lt;= read_only;
         endcase
   end // clocked
end // always