How to efficiently implement a single output pulse from a long input on Altera?
My usual technique is to implement a 2-stage synchronizer to bring the asynchronous input in to the clock's timing domain, and then use one more flip-flop as the edge detector. Depending on the logic you use in the last statement, you can detect rising edges, falling edges or both.

module control
(
    output logic pcEn,
    input clock, ready
);
    reg r1, r2, r3;

    always @(posedge clock) begin
        r1 &lt;= ready;    // first stage of 2-stage synchronizer
        r2 &lt;= r1;       // second stage of 2-stage synchronizer
        r3 &lt;= r2;       // edge detector memory
    end

    pcEn &lt;= r2 &amp;&amp; !r3;   // pulse on rising edge
endmodule