Is a DMOS potential free? (in case of TPIC6C596)
According to this functional Block Diagram the DMOS will just switch the Drain to GND if powered. So I wondered if this counts as a potential difference in the switched circuit.


What is not drawn in that Block Diagram is that the GND connection is also used for every other block in the circuit. All the latches, AND gates and inverters also use this GND.

There is only one GND pin on the chip.

So no you cannot assume that the DMOS switches are in some way isolated from the rest of the circuit. In your example circuit, the GND of the TPIC6C596 must be connected to the ground of V1 at the left. Without that connection you will get unexpected results. 

Also if you would still do this and create a voltage difference between left and right sides the ESD protection diodes will start to conduct if you make a voltage difference of more than 0.6 V.