What is "Input high voltage common mode range?"
The most positive input of the differential pair must be within that voltage range. 

In the case of this chip, it varies from Vee+2.0V to Vcc, so for a 3.3V Vcc (PECL) it will be 2V ~ 3.3V. 

(the diagram below is for Vcc = 5.0V rather than 3.3V)



I don't see Vpp specified in the datasheet for that chip, but it's usually 150-800-1200mV minimum-typical-maximum. 

See this link for more.