How is the dV/dt of the controller voltage constant?
This is a so-called Miller Integrator, a capacitor feeding back from the output to the input of an inverting amplifier. The zener diode has nothing to do with the inrush limiting.

When the switch is initially turned on, current flows through R1, raising the voltage on the gates, charging C1, whose other end Vcont- is held at Vpack+ through the load.

Once the voltage on the gates gets to Vgs(thresh), the FETs start to turn on, and the voltage on cont- begins to fall. This fall, transmitted through C1, would tend to lower the gate voltage and turn them off again, so you can see it's negative feedback.

To a first approximation, what happens now is that Vgs stays more or less constant while Vcont- falls. As Vgs is constant(ish), so the voltage across R1 stays constant(ish), so the rate at which C1 charges, that is the rate at which Vcont- falls, is similarly constant. This is the dV/dt your source refers to.

Eventually, Vcont- reaches Vpack- and so can't fall any further, and now Vgs rises, until limited for Vgs(max) safety by the zener diode.

The feedback capacitance between drain and gate of a FET, and the collector  and base of a BJT, is the most significant impediment to operating them quickly, this effect was first described by Miller. Enhancing that capacitance is a simple way to slow things down further.