cannot figure what is the gate for this CMOS realization
This circuit has 2 binary inputs, so only 4 possible input states.  That's a small enough number of states to start out by solving them exhaustively, like by using a truth table.

Start with that and see what you get, then report back.

Added

It's good that you've noticed that sometimes the result is high impedance.  Now think what that means for the internal node.  Due to capacitance, the internal node will stay as it was last driven, at least for a little while.

Also note that this is really two identical gates in series, just that each is presented with the opposite polarity of CLK.  This should be a clue you are looking for some kind of latch or flip-flop behavior.

Analyze what happens with the four possible combinations of input high and low, and rising and falling edge of the clock.