I was explaining a transistor to someone, and I realized: I don't really understand several key concepts at a low level. Help?
If current is the flow of electrons, how do they traverse the positively charged channel in the n-type?


Refer to Fig. 1 below. In an N-type enhancement mode MOSFET, \$V_{gs}\$ establishes an electric field through the gate, the dielectric layer, and the P-type substrate. This electric field draws electrons up through the P-type substrate and "induces" an electron channel (an N-channel) under the dielectric layer. When VGS>Vth, the field strength is sufficient to induce (and sustain) under the dielectric an electron layer that stretches between the source and drain terminals, and if \$V_{DS}&gt;0\$ the transistor starts conducting current between its drain and source terminals.



Figure 1. N-type enhancement mode MOSFET

As shown in Fig. 1, the substrate (B) is connected to the source (S), which is connected to the negative terminal of the power supply, which serves as the source of the electrons that are injected into the P-type substrate. In Fig. 2, the three vertical bars represent the drain, substrate (with the arrowhead), and source elements (top to bottom). Note that the substrate is internally connected to the source in both the N-type and P-type MOSFET.



Figure 2. Schematic symbols for enhancement mode MOSFETS


  In the p-type, the body has a lack of electrons anyway, so how does current flow when voltage isn't applied to the gate?


Both the N-type and P-type enhancement mode MOSFETS are "normally off" devices; the transistor turns ON only when the condition VGS > Vth is satisfied. When VGS &lt; Vth, the transistor is OFF (very high resistance between the drain and source terminals).



Figure 3. P-type enhancement mode MOSFET

Depletion mode FETs, on the other hand, are "normally ON" devices. A "Junction FET" (JFET) is an example of a depletion mode device. Consider the N-channel JFET in Fig. 4. When a \$V_{DS}&gt;0\$, current immediately begins to flow through the device. A reverse bias voltage applied to the N-channel JFET's gate relative to its source (\$V_{GS}&lt;0\$) creates an electric field that constricts the current-carrying drain-source channel&mdash;i.e., the field "depletes" the number of charge carriers in the current channel, thereby reducing the flow of current. With sufficient negative gate-source bias, the electric field strength completely "pinches off" the flow of current in the drain-source channel, and current flow drops to approximately zero amps.



Figure 4. Junction field effect transistors


  How are 0V and Z different?


Voltage is potential difference. Given two different nodes within a circuit, nodes A and B, each node has its own electric potential (with units of Volts).

$$
V_{AB} = (potential @ A) - (potential @ B)
$$

If \$V_{AB}=0\$, then \$potential@A = potential@B\$.

When designing a circuit, the circuit designer arbitrarily chooses one node&mdash;e.g., node B&mdash;to be the "reference potential" node, and all voltages (potential differences) in the circuit are measured relative to the reference node (which is often called the "ground" node). The potential at the selected reference node is specified as "zero volts" (0V) so that all other voltages in the circuit are a positive or negative offset from zero.

The high impedance, or "High Z", state refers to a condition within a complementary metal oxide semiconductor (CMOS) circuit where the P-type and N-type enhancement mode MOSFET pair are both turned OFF. 

PMOS  NMOS  Q
-----------------------
OFF   OFF   HIGH Z
ON    OFF   LOGIC HIGH
OFF   ON    LOGIC LOW


In Fig. 5, when both the PMOS and NMOS transistors are OFF, there are very large resistances between the power supplies (VDD and VSS) and the output terminal Q. Consequently, approximately zero current flows into or out of terminal Q when the CMOS device is in its "high Z" state. Note that there could be a non-zero voltage at Q relative to the circuit's reference/ground node; however, in the high Z state the output impedance at Q is so high that there will be approximately zero amps flowing into or out of terminal Q.



Figure 5. CMOS circuit