Gate delay of carry out C and sum S in ripple carry adder
The figure on the right of your image is the carry of one bit position. Given a wordlength of \$n\$ bits and position \$i\$, the carry \$c_{i+1}\$ goes to the exact same circuit, just with inputs \$x_{i+1}\$, \$y_{i+1}\$ and \$c_{i+1}\$. So to calculate the carry of the total summation \$c_{n+1}\$ the signal takes \$2 \cdot t_{Gate-Delay}\$ times the number of bits: \$2 \cdot n \cdot t_{Gate-Delay}\$

Since the sum \$s_i\$ is calculated using two \$XOR\$-Gates it needs \$2 \cdot t_{Gate-Delay}\$ as cascading \$XOR\$-Gates is done by put them one ofter another, so calculating \$s_n\$ also takes \$2 \cdot n \cdot t_{Gate-Delay}\$.