Digital filtering after analog to digital conversion (ADC)
If your wanted band is 3 to 50 Hz, then it will not be possible to notch 50 Hz out with any practical filter without losing some of the top end of your band.
Can you use a digital filter, or must you use an analogue one? It depends on the signal to noise ratio at the ADC. If your 50 Hz interference is at such a level it's causing you to turn the gain down before the ADC such that your signal becomes noisy, then you need an analogue filter before it. If you are getting both interference and signal through at an adequate gain without overloading the ADC, then you can use a digital filter after the ADC.
There is a trivially simple implementation of a 50 Hz notch that you can apply, either in the MCU or in Python, there's no need to use a relatively expensive FFT operation. If you add up samples over a period of 20 mS, then 50 Hz will be notched out. There is no need to do all of these adds for each output sample. It's more efficient to have a shift register that's 20 mS long and an accumulator, add the present sample into the accumulator, and subtract the sample of 20 mS ago.
This simple filter will give you a falling frequency response across your passband. Will it need correction before your analysis? It depends, what is your analysis, what is the specification on flatness across the band?  The correction could range from the simple/bodgy process of adding a bit of slope to the response with a couple of taps, to designing a proper notch filter. The complexity of that task will depend on your sample rate, and your flatness and any group delay specification. IIR filters are good when there's some over-sampling, and no group delay specification.
Should you end up with an FIR filter that's more than a dozen or so taps long, it may be appropriate to use Fourrier convolution to implement it faster than the more naive multiply-accumulate approach.