How the slew-rate and drive strength affect the output signal of the FPGA?
As its name suggest, the slewrate preference is a preference for the rate of change of the signal at the Output Pin. Though seemingly unrelated, this is coupled with the load preference (which limits the maximum output current of the pin). For small capacitive loads, the slew-rate can be achieved with any drive strength. However, as the capacitive load increases, the drive currents kicks into play. For high capacitive loads, if the drive current is too low it can be a limiting factor for attaining fast slew-rate on the pin. 

To illustrate the effect of drive-strength and slew-rate I'll use examples from a project that I was involved in. I was using Lattice XP2-30E FPGA to read the data from an analog to digital converter AD9238. The problem manifested itself as wrong data being read. Measuring with digital probes revealed hold time violations. Namely, the digital probes showed larger clock jitter, with the hold time of 1.5ns (min 2ns specified by the ad converter). 

Measuring with analog probe (with Yokogawa DLM2034 at 2.5GSPS) revealed serious distortion of the clock signal. The following figures illustrate the effect of slew-rate and drive strength on the clock signal.



As can be seen from the figure, even for the fast slew rate preference, the drive current of 4mA prevents the FPGA from attaining the desired slew-rate.

So why one shouldn't set the drive current as high as possible? If the capacitive loading of the line is large, and the FPGA is simultaneously driving multiple lines (typical application when driving a bus), the large in-rush current may cause a voltage drop on the internal supervisory circuit for poorly decoupled FPGA, causing the chip to reset. Once the desired slew-rate is attained, increasing the drive current had the negative effect as it increased overhoot in the signal.