How to choose a right user interface in PCIe DMA subsystem (AXI Memory Map / AXI Streaming)
I would say that it heavily depends on the application.  It's certainly possible that a memory-mapped interface could make a lot of sense even without a CPU or SoC.  It's also possible that a streaming interface could make sense even with a CPU or SoC.  It's also possible both are needed.  

Memory-mapped interfaces are necessary if the target is memory, be it on-chip SRAM, off-chip DRAM, or perhaps HBM.  Streaming interfaces can be convenient for applications that involve streaming data, such as networking, image and video processing, DSP, etc.  You certainly don't have to have a CPU to have a use for a large bank of DRAM.  

However, the design of the DMA core, the interfaces it provides to FPGA logic, as well as the operation of the PCIe bus can possibly cause some problems if very high performance is required.

One major problem is PCIe ordering.  PCIe supports multiple outstanding DMA read operations, but it makes no guarantees about the order in which those reads complete.  This can cause serious issues with cores that provide streaming interfaces, as either the core can only make a single read request at a time (resulting in poor performance) or the core must spool the read data in onboard RAM so it can get things organized, which increases complexity and resource utilization and can affect performance.  

Another problem is alignment.  Data is transferred over the PCIe bus DWORD aligned to host memory.  Inside the FPGA, the alignment will be different - either address aligned on a memory-mapped interface, or cycle aligned on a streaming interface.  Matching the alignment on a TLP by TLP bases can require inserting a large number of wait states, which reduce throughput.  The headers attached to each TLP also affect throughput - even though the TLP max payload size is an even power of two, adding some headers means the overall size is not an even power of two, and this can result in a lot of empty byte lanes between TLPs, decreasing throughput, even more so as the bus width increases.  

I'm wrestling with some of these issues myself in https://github.com/ucsdsysnet/corundum .  There is no processor core in this pure Verilog design, but the (fully custom) DMA core uses a memory-mapped AXI interface to efficiently deal with interleaved completions.  I am currently in the process of moving from an AXI interface to a segmented memory interface to increase the throughput over the PCIe link as the current AXI-based datapath has some serious shortcomings.