Is it inefficient or bad style to build std_logic_vector out of std_logic inputs?
Style

I'd never let this pass through code review, but not because you want to write a lookup table. Combinatorial logic definition using signals was relevant in the 1980s, but we're 4 decades later now.
The whole concatenation/lookup really belongs in a process, like so:

p_main: process(a, b, c)
  variable together : std_logic_vector(2 downto 0);
begin
  together := a &amp; b &amp; c;
  case together is
    when whatever =&gt;
      do things;
  end case;
end process;


Which allows you to write VHDL the way you'd write software, with instant variable updates and no need to take into account delta cycles/update scheduling. The whole thing will run one time each time a, b, c or a combination of them updates, and the sequential order in which everything runs is easily determined, can be easily debugged and whatever you want.

Synthesis efficiency

Your adjustment won't matter for synthesis, you'll get the same hardware whether you do your concatenation or not. (For larger signals, the synthesis tool will even prefer your style because it allows for larger optimization branches, but even then the effect won't be noticeable).

Simulation efficiency

is what you potentially sacrifice, you basically introduce one extra delta cycle of simulation time. A change on a, b, c or a combination will first trigger a change on the together signal and only then trigger your lookup table.

Will you notice this? Probably not.

Is it worth taking into account? No, never, unless it convinces you to write a process.