VHDL - How to reduce signal's dependencies and optimize speed?
In general, the usual answer to this sort of problem is to pipeline. You might consider adding pipeline registers immediately after the 10-bit comparators, before the logic that combines them into the enable signal for the next stage. To keep the resulting enable signal aligned with the correct data in the data path, you'll probably also need a pipeline register for the data, too.

But yes, you can also use the technique described in the other question. For your specific 10-bit counter example, instead of counting from 0 to 1003 and using a comparator to identify state 999 to turn off the enable signal, you could make it an 11-bit counter that counts from -1000 to 3. The MSB of this counter is your enable signal, and when the count gets to 3[1], you reload the counter with -1000 ... and also load an auxiliary 9-bit count-down counter with the value 249. Each time this auxiliary counter reaches -1 (MSB set) is the start of another subframe (in addition to the one that starts at the beginning of the main frame).

[1]Note that detecting "3" is a function of just 3 bits &mdash; the MSB and the two LSBs &mdash; not a function of 11 bits.