ADC Chip Timing Question
Here's a good clue: -

And, if you look at the value for \$t_4\$ it is quoted here: -

So, a new data bit is available between 0 and 40 ns of the falling edge of SCLK. This means you can't rely on the falling edge of SCLK to read valid data.
Of course, if you look at \$t_7\$ it tells you that current data is valid for maybe 7 ns should you attempt to read it but, in all honesty, I'd use the rising edge of SCLK.
Also \$t_6\$ tells you that the SCLK minimum pulse width at full speed (20 MHz) is 20 ns so, it looks like the positive edge is the one to use.