Modern Destructive Readout Memory
How about using two 2x64-bit shift register chips (e.g. CD4517 or MC14517B) cascaded end to end?  That would yield a 256-bit shift register.  Of course, nothing would prevent the contents from being read out and reloaded.  If one wanted to be a bit trickier, one could use three shift register chips and add a multiplexer and latch so that one would clock in three bits at a time, but only clock out two (one could select which two); whatever bit wasn't chosen to be clocked out would be irretrievably lost.  For that to be useful, one would have to prevent someone from physically getting access to the device pins without clearing the device.  I don't know whether killing power would reliably kill the data instantly, but it should probably be pretty effective.  The MC14557 only holds 64 bits instead of 128, but it includes a reset pin which could erase it more quickly.

An alternative approach would be to use a small microcontroller.  Feed it data along with a validation code.  To read out the data, the validation code must be supplied.  Supplying an incorrect validation code would erase the data.