What is the purpose of the following inverter topology?
It somewhat depends on how the specific implementation technology deals with paralleled outputs, but my guess would be that this is supposed to generate a pair of nonoverlapping clock phases, commonly used in systems built using dynamic logic.

The idea is that only one of the outputs is high at a time, with no overlap during the transitions:

       ___________               _
______/           \_____________/
_____               ___________
     \_____________/           \__


Note how each output goes low before the other output goes high.

You can get the same effect (without the output conflicts) with a pair of cross-coupled NOR gates:







simulate this circuit &ndash; Schematic created using CircuitLab

If you switch to NAND gates, you get clocks that don't overlap in the low state.