How do I know how wide the data bus is?
It seems you have an issue far before you start approaching FPGA and its configuration coding.

There's a thing, usually document, called specification, which makes clear statement about outcomes of the project, and describes its design to specific extent.

As you do not know how wide your RAM data bus is, you must have issue with specification, or specification is not elaborate in the interfacing section (including which component base you will be using).


  I'm designing a basic GPU in Verilog.


Do you have clear definition what will be the results and the basic tasks GPU will perform? Is there understanding what is needed to achieve the results, and how much it will cost?


  I can't know how many bits of data the RAM can take at a time ahead of time (since it's supposed to be general purpose)


Do you have understanding of the RAM speeds? Which RAM you use - SRAM, SDRAM, DRAM? Do you use standard memory access IP from FPGA manufacturer, or going to design memory controller yourself?


  The only thing I know for sure is that there is at least 32 bits of address bus.


This sounds strange because, depending on the data bus size, you will have very different RAM sizes - with 8 bit it will be 4GB, with 32 bit it will be 16 GB. Is there any supported configuration information about RAM size in the specification?


  If I send too much data, some RAM chips may not support it.


You are correct if you mean if data bus you choose is wider than RAM chip's, then data will be lost.


  If I send too little data, there may be alignment issues and other problems when sending odd bytes.


This is not correct because if you choose data width lower than RAM chip's some bits of RAM chip will simply not be used. However as you say about bytes here I assume you will convert your RAM data bus to bytes.

Thus, answering your question with narrow mind, you can choose the least supported data bus aligned to 2^n size, e.g. you may be sure that RAM connected to your GPU will never be less than 8 bits, then choose 8 bits. All other RAM data bits above these 8 bits will be unused.

But this approach will severely hit performance, and you must request clarification on the specification to find out which data bus sizes are supported, and as Harry Stevenson said, perform configuration on the initialization (using polling RAM to find out its size, or using configuration switches).

Update:


  If my RAM chip has a 32-bit data bus, ... how would the RAM know how much I am writing at once? 


If RAM's data bus is 32-bit (e.g. D[31:0]), then it will always accept 32-bits. You can write one bit D0, not using all others D[31:1]. RAM does not care what you write into it. Your GPU will care, and must know where its data in RAM is.


  How is this usually done?


Usually designer decides which RAM configurations are supported, and designs circuits accordingly to have maximum speed and minimum waste of resources.