State switches in FSM
What you can do is create an idle state, and when you detect a button press you switch straight to the idle. Then you can have a counter in idle which waits for a while before you start scanning buttons again.

For example:

-- include numeric std
signal idle_counter : unsigned(31 downto 0);

      ...

      when state3 =&gt; 
        case bcd_val is
          when "01" =&gt; 
                Send &lt;= '1';
                scannel_val &lt;= "0101"; 
                fsm_state &lt;= idle;   -- switch to idle
          when "10" =&gt; 
                Send &lt;= '1';
                scannel_val &lt;= "0110";
                fsm_state &lt;= idle;   -- switch to idle
          when others =&gt; 
                scannel_val &lt;= "0000";
                Send &lt;= '0'; 
                fsm_state &lt;= state1;   -- carry on scanning
        end case;
        idle_counter &lt;= (others =&gt; '0');
        ...
      when idle =&gt;
        if (idle_counter &lt; some_timeout) then  -- some_timeout is how long you want to wait (in clock cycles)
           idle_counter &lt;= idle_counter + "1"; -- increment counter
           fsm_state &lt;= idle;                  -- stay here
        else
           idle_counter &lt;= (others =&gt; '0');    -- reset counter
           fsm_state &lt;= state1;                -- go back into checking
        end
        --scannel_val is valid here, so you can do something with it if you'd like.
        ...
      when others =&gt; scannel_val &lt;= "0000";


There is one process in this code you've posted.

It starts with 

scan_fsm : process (reset, clk) &lt;= Sensitivity list
begin  -- process key_scanner


and ends with 

end process scan_fsm;


The clock and reset are part of the sensitivity list. That means that this code is only going to be triggered when either clock changes or reset changes. 

De-bouncing can be done in a separate process. 
Basically, you want to make sure that the button was pressed for a number of microseconds before it triggers. What we want to do is save the value of the input for a number of clock cycles. Then only register a 1 when the history has been constantly 1 for for the past 32 clock cycles.

Example:

-- these are our row inputs (to become bdc_val)
signal row1 : in std_logic; 
signal row2 : in std_logic;

...
-- this is our history vector
signal row1_z : std_logic_vector(31 downto 0);
signal row2_z : std_logic_vector(31 downto 0);

-- debounced signal
signal bcd_val : std_logic_vector(1 downto 0);

-- a whole vector of ones for convenience
signal ones    : std_logic_vector(31 downto 0);
...

ones &lt;= (others =&gt; '1');

-- generate our histories
gen_z : process (reset, clk)
begin  
  if (reset = '1') then
    row1_z &lt;= (others =&gt; '0');
    row2_z &lt;= (others =&gt; '0');
    bcd_val &lt;= (others =&gt; '0');
  elsif (rising_edge(clk)) then
    row1_z(31 downto 1) &lt;= row1_z(30 downto 0); -- shift everything up 1
    row1_z(0) &lt;= row1;                          -- save the most recent input
    row2_z(31 downto 1) &lt;= row2_z(30 downto 0); -- shift everything up 1
    row2_z(0) &lt;= row2;                          -- save the most recent input

    -- we only want bcd_val to be 1 when the entire row history for the past 32 cc is 1
    if (row1_z = ones) then
      bcd_val(0) &lt;= '1';
    else 
      bcd_val(0) &lt;= '0';
    end

    if (row2_z = ones) then
      bcd_val(1) &lt;= '1';
    else 
      bcd_val(1) &lt;= '0';
    end
  end
end