Can SPI slave work with wrong clockphase setting?
By Motorola SPI timing diagram, your ADC's configuration should be 

CPOL = 1, (SCK Normal High)

CPHA = 1, (The data is effective the the second edge, at your case, it's a rising edge)

There also has a TI version SPI:


  Some products use different naming conventions. For example, the TI
  MSP430 uses the name UCCKPL instead of CPOL, and its UCCKPH is the
  inverse of CPHA. When connecting two chips together, the clock phase
  initialization values must be examined to be sure of using the right
  settings.


So, for TI version, it should be

CKPL = 1,

CKPH = 0.

By the naming method in your code, it seems the code use TI mode, and are you using a TI MCU? If it is, then CKPH should be 0.

So, read the code carefully, not just the comment, make sure you understand the code completely.



Update:

Actually, most ADI's SPI based ADC, has a standard write timing, bus use a modified SPI read timing diagram. 

From the write timing you should make the data effective at the second CLK edge. So, for Motorola version: CPHA = 1, for TI version: CKPH = 0.

For the read timing: When the ADC complete the conversion. It first output a "low" level at the DOUT line, to indicate the user, the data is ready. And you send the clock and clock out the remaining data. The remaining data will be clocked out after t2 from your first edge. So, you must avoid the extra low bit, and use CKPH = 0.

Whichever settings you use, given your finally timing (considering the various parasitic factor) don't violate the timing diagram, it will work.