Nesting Elseif, If, Else in VHDL
Can you nest elseif in if, then else statements ?

You are certainly allowed to nest &quot;if&quot; statements inside each-other.  This is perfectly legal code.
if boolean_expression_1 then
    if boolean_expression_1a then
      --some statements
    elsif boolean_expression_1b then
      --some statements
    elsif boolean_expression_1c then
      --some statements
    else
      --some statements
    end if;
    --some statements
elsif boolean_expression_2 then
    if boolean_expression_2a then
      --some statements
    elsif boolean_expression_2b then
      --some statements
    else
      --some statements
    end if;
else boolean_expression_3 then
    --some statements
end if;


Or elseif only check
0 or 1 conditions and not combinatorial conditions like if then else
can ?

The types of expressions you can put after &quot;elsif&quot; are exactly the same as for &quot;if&quot;.
As for your code.  if the type of o_done is a character type that has '1' and '0' as possible values, and State0 and State1 are both booleans then the following should compile without problems.
  if ( State1 ) then
    o_done &lt;= '1';
  elsif (o_done = '1' AND State0 ) then
    o_done &lt;= '1';
  else
    o_done &lt;= '0';
  end if;

This is also legal
if state=s0 then 
    if o_done='1' then
      --some statements here
    end if;
end if;

if o_done='1' then
  if  stateS1='1' then
    --some statements here
  end if;
end if;