Do any flip-flops use separate clock levels for "sample" and "propagate" events
I dunno what the modern chips do internally, but for instance the 8080 used a non-verlapping two-phase clock:



I think the problem with your approach is


the levels at which CMOS logic is active is not easily controlled, and/or controlling it accurately would put extra demands on other aspects (geometry, size, yield, etc.)
there is not realy a level at which a FF samples the signal, rather there is a level 1 at which the first (master?) latch stops sampling, and a level 2 at which the second (slave?) latch starts sampling the master's output. When level 1 &lt;&lt; level 2 (wide band between them) and the clock edge is not too steep you automatically have a 'deadband' as you want.