Constant Bit Signal in VHDL
If sel is an input for the entity then you can set the initial value in the entity's port:

port(
  sel: in std_logic := '1';
  A: in bit_vector (3 downto 0);
  S: out bit_vector (3 downto 0)
);


This will work in simulation, but for synthesis make sure your target technology supports initial "power-on" values (true for FPGAs, not so for ASICs). See Is initialization necessary?

Also note that signal is only used in the architecture body, not entity declaration.