Advantages and disadvantages to loops in VHDL unrolling
From the abstract of your second link:


  Loop unrolling is the main compiler technique that allows reconfigurable architectures [to] achieve large degrees of parallelism. However, loop unrolling increases the area and can potentially have a negative impact on clock cycle time. In most embedded applications, the critical parameter is the throughput. Loop unrolling can therefore have contradictory effects on the throughput. As a consequence there exists, in general, a degree of unrolling that maximizes the throughput per unit area.


To me, this directly answers your question. The idea is basically this: if you have a process which must iterate over many cycles, you can employ loop unrolling to parallelize the algorithm to reduce the number of required clock cycles. 

But this comes at a cost of a larger fabric footprint (more FPGA area), which in turn complicates clock routing leading to more difficult timing closure. 

If timing closure can’t be obtained, the system is forced to use a slower clock frequency, which conflicts with the goal of unrolling. 

Therefore, you have to find a balance between the two to maximize the gain in performance.