logic gates combined with R-C network often violates absolute max ratings, does that hurt?
If you look at the online examples more carefully, you'll see they're not like the schematic you shared.

Here's the online example:


[source]

Notice that in this example, the capacitor is not directly connected to the input of any gate (only to the output of U2). 

The resistor connected between the capacitor and the inputs of the gates means that the current that can be fed through the capacitor to those gate inputs is limited. If the resistor values are 5 kohms, and the U2 output switches between 0 and 5 V, then only 1 mA could possibly flow through the resistors into the input pins of U1 or U2. 

This current limit is enough to prevent damaging the gates. 

(Aside: with older CMOS chips (like 4000 series) you may have to watch out for latch-up behavior if inputs are driven outside the rails even briefly. Luckily for me I've never had to design with such old parts, so I can't give you more details on exactly what is needed to avoid the problem)

Edit

In comments you say these resistors carry no current. That is true when the input voltage is between the supply rails. But consider that the input pins don't just connect to CMOS gates. There are diodes connected between the input pin and the rails to protect the CMOS gates from ESD currents:



[Source]

When the input voltage is between the rails, these diodes are reverse biased, and, as you have said, there is very little current through any resistor connected to the input pin.

But if the input voltage goes above Vdd or below Vss by more than a diode drop, one or the other of these diodes becomes forward biased and you can no longer assume there's no current through the resistor connected to the input. 

Since you're specifically asking about the case where the capacitively coupled signal drives the input voltage above or below the supply rail, you can't ignore these diodes.

If your input source is current limited (by the resistor) then these diodes will also clamp the input voltage to not go excessively outside the rails, and the IC will not be damaged. 

(but there are a number of gotchas with relying on this technique, particularly in low-power circuits, so if you design a circuit this way be sure you know where the current will go after going through the protection diode and that it won't affect the operation of your circuit in some other way)