is it possible to make asynchronous down counter modulo 6 with 3 JK flip-flop?
The counter should have binary state sequence 5, 4, 3, 2, 1, 0, 5, 4, 3, 2, 1, 0, 5, etc... Only 6 states, surely they can be stored in 3 JK-ffs.  A non-optimal way is to make a counter which starts from 0 and counts to 6 which is set to clear the counter. There's a momentary 7th state. But we decode the binary states 0,1,2,3,4,5,6 with a big combination circuit to decreasing series 5,4,3,2,1,0,0. The extra short living seventh state is decoded to an allowed state, too.

The result isn't free of wrong short living states. That would need a cyclic code in the base counter and race-free decoder.