Making a simple 4 bit adder into a 4 bit adder with carry in & out
You don't need the resize function. Just create an internal signal of the correct length, and concatenate 0's to your inputs. Such as:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity four_bit_adder_simple is
    Port ( a    : in  std_logic_vector(3 downto 0);
           b    : in  std_logic_vector(3 downto 0);
           cin  : in  std_logic;
           sum  : out std_logic_vector (3 downto 0);
           cout : out std_logic );
end four_bit_adder_simple;

architecture Behavioral of four_bit_adder_simple is
    signal total : std_logic_vector(4 downto 0);
begin

    total &lt;= ('0'&amp;a) + ('0'&amp;b) + cin;
    sum   &lt;= total(3 downto 0);
    cout  &lt;= total(4);

end Behavioral;


edit 
In hindsight, using the non-standard std_logic_unsigned is not the best approach (When to use VHDL library std_logic_unsigned and numeric_std?). 

See my answer here instead.