How to avoid writing to and reading from 2D array at the same time vhdl
Reading and writing from the same memory position simultaneously is actually not a problem. If you use a dual port RAM this is exactly what you're doing.

architecture rtl of dpram is
type mem_type is array ((2** addr_width) - 1 downto 0) of
std_logic_vector(data_width - 1 downto 0);
signal mem : mem_type;

begin
process (clk)
-- Write memory.
begin
    if (rising_edge(clk) then
        if (write_en = '1') then
            mem(conv_integer(waddr)) &lt;= din;
            -- Using write address bus.
        end if;
    end if;
end process;

process (clk) -- Read memory.
begin
    if (rising_edge(clk)) then
        dout &lt;= mem(conv_integer(raddr));
        -- Using read address bus.
    end if;
end process;
end rtl;


You have to take care tough in case e.g. you're storing 16bit data vectors in a 8bit Ram block. Means one dataset is split up into two cells. In this case you have to check data consistency.