Timing warnings for functional model
Setup and hold timing checks only make sense with post-layout information. A century ago, you could do timing analysis without layout structural information because the the device delays were overwhelming compared to routing delays. You can no longer do accurate timing analysis with RTL code.

Some models are written to be used in both RTL and structural simulations, so you can ignore these warnings. Even better would be to turn of the timing checks which improves RTL simulation performance (maybe not relevant on your project, but that what people do in industry).