Using async SRAM in homebrew CPU
Generally, any real part will have what can be considered to be a contamination delay which is the propagation delay between a change at the address or control input, until the old values of the outputs cease to be valid and begin to transition towards a new value, quite likely through various invalid intermediates.

If you can ensure the the driving of the address and control outputs from the processor happens at a closely related time (or even after) the latching of inputs from the memory, a finite contamination delay will likely ensure that you receive valid values.

However, keep in mind that a typical synchronous memory imposes an extra clock's pipeline delay, while an asynchronous memory will only have propagation delays.  Adding an extra pipeline register on the address lines would make an asynchronous memory act more like a synchronous one - at least as long as it makes timing.