How to trigger at both edges in VHDL?
Explicitly check for both rising and falling clock edges within the process:

process (clk)
begin
  if (clk'event and (clk = '1' or clk = '0')) then
    null; -- Do stuff.
  end if;
end process;


Or using the respective functions:

process (clk)
begin
  if (rising_edge(clk) or falling_edge(clk)) then
    null; -- Do stuff.
  end if;
end process;


However, there are subtle differences between the two variants (e.g. https://stackoverflow.com/questions/15205202/clkevent-vs-rising-edge).
Also don't expect this to be synthesizable.