VHDL read bit from input problem
Looking at the following two lines of code:

regr(0)&lt;=reg;                   
regr&lt;=regr(10 downto 0) &amp; '0';


Since regr has a width of 12 bits, the second line assigns every bit in this signal. Since the last assignment to a particular signal takes priority, your initial assignment to regr(0) is effectively ignored.

In the second example with the two lines swapped, the last assignment to regr(0)&lt;=reg; takes priority over the assignment to '0' on the previous line.

The more readable version would look like this:

regr &lt;= regr(10 downto 0) &amp; reg;


thus performing the whole assignment in one line without potential for confusion.

In your second example, you are seeing 'U' being shifted through, because your signal reg is not initialised. You could initialise your signal to '0' using:

signal reg : std_logic := '0'