Error while implemeting D_FF from JK_FF in Verilog
I get a compile error with Cadence.  In d_ff_from_jk_ff, change:

    output reg q;


to:

    output q;


After I fix that, q is only X for the 1st 5ns, then I see it toggle between 0 and 1 thereafter.

Here is the error I got:

 jk_ff d_converted(q,qbar,clk,rst,d,d_n);
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xmelab: *E,RANOTL : A reg is not a legal lvalue in this context [6.1.2(IEEE)].