I2C slave not pulling down SDA data line for the full clock cycle
The variation in delay you're seeing is immaterial. I2C is a synchronous protocol, so the only thing that matters is whether or not the SDA line is still low on the next rising edge of SCL. As you can see in your first diagram, they all pull SDA low before that happens, so they are behaving correctly.

If this is causing problems on your I2C master, then it is implemented incorrectly.

In fact, the rising edges you've circled are caused when the master stops driving the SDA low itself, and have nothing to do with the slave devices' activity. They haven't yet driven the line at all.

(The timing variation you see is probably due to the asynchronous nature of your logic analyzer's sampling.)