AS6C62256A SRAM Usage
I've looked at the timing diagrams, but have no idea what they mean.
  Could anyone give me some step-by-step instructions on how to write
  data to this chip?


Timing diagrams are precisely the instructions you are looking for. For every operation your memory controller must drive the signals in accord with provided timing diagrams in precisely the order shown. 

As usual, there might be several options how to perform function. Below is the timing diagram for ^G-^E controlled READ operation



The diagram means that your controller must assert an address first, then assert E=low, then assert G=low, all after a minimum delay of Tsu. Then the valid data (memory content) will appear on data bus after time Ta. Before that time (Ta) the data bus can have some garbage (grey area on the diagram), which your controller should ignore.

After G and E are deasserted, your controller can remove/change the address to a new one, but the valid data are expected to stay for Tdis time before the memory IC turns the bus into high-impedance state (there could be several IC on the bus). That's it. For WRITE cycle it is similar, but a little more complicated.