Understand a counter in VHDL
The first and probably most important thing with VHDL is to understand that it's not a programming language but a hardware description language. You're not writing sequential code blocks but rather describe logical and combinatorial hardware.
It depends a little how deep you wanna dive into this topic, but you could read something about counter implementation using logic gates.
What your counter does is it evaluates the value of value with every rising edge of the incoming clock. This is another speciality of VHDL, where in sequential programming language the clock is something you don't really see, it's a crucial part of every VHDL design.
Regarding your example, as already stated by Brian Drummond, that's not really proper code. Your process needs a sensitivity list to be simulated. A sensitivity list tells the simulator what signals it has to watch for re-evaluating the process. In your case this would be clk, load and reset.