VHDL: Metastability check for hold time fails
I am answering because I can't comment.

You have deasserted le before changing the input d in your testbench.

In the DUT, however, 

intern &lt;= 'Z' when oe_n = '1' else              -- high-impedance state
           d  when oe_n = '0' and le = '1' else -- latch input
           unaffected;                          -- else, nothing happens


As intern is unaffected when le is deasserted and oe_n is asserted (0), it holds the previous value of d (in this case 1). When you check for the hold time, no matter how long you wait, the assert will not fail.

    -- check hold time
    wait for t_h;
    assert intern'delayed'stable(t_h + t_su)


This change in testbench (similar to what you have done for setup violation) should solve the problem. By deasserting le after input d changes, the hold check should fail.

stimulus : process is
begin
    -- start in high-Z mode
    oe_n &lt;= '1'; wait for 10 ns;

    -- WARNING: These signal changes violate metastability
    oe_n &lt;= '0'; le &lt;= '1'; d &lt;= '1'; wait for 4 ns;

    -- violate setup time
    -- d &lt;= '0';  wait for 1 ns;
    -- le &lt;= '0'; wait for 1 ns;

    -- violate hold time
     d &lt;= '0';
     wait for 1 ns; le &lt;= '0';

    -- wait forever
    wait;

end process stimulus;