Compatibility of devices with different voltage thresholds/noise margins/static disciplines
tl; dr: you design for the worst-case noise margin as a composite of all your logic types, so that all the receivers will interpret logic low and high correctly.

To arrive at a set of levels that will work system-wide, you take your highest Vi(h) and lowest Vi(l), add some margin on top of each, and that defines your levels your driver must support.

Example: 5V HCMOS vs. 5V LSTTL:


HCMOS Vi(h)/Vi(l): 3.5 / 1.0V (0.7 / 0.2 VCC)
LSTTL Vi(h)/Vi(l): 2.0 / 0.8V


So taking the min Vi(l) and max Vi(h), we have:


composite system Vi(h)/Vi(l) = 3.5 / 0.8V


Add 100mV noise margin:


margined system Vi(h)/Vi(l) = 3.6 / 0.7V


So your system signal driver must be able to swing 0.7V for low and 3.6V for high to achieve 100mV of noise margin. In this case, HCMOS output can do that, while an LSTTL output cannot, at least not without the help of an external pull-up resistor as its Vo(h)(min) is only about 2.4V.

The threshold analysis is similar regardless of the logic types being mixed - or even if they're not being mixed at all but nevertheless have large fan-out loading to be considered (a big problem with TTL, less so with CMOS.)

If, for some reason, a mixed-logic system can't find a workable composite set of thresholds, a technique called level translation can be used to convert the output levels of one logic type to a set of reliable input thresholds for another.

Between using Vi(h)/Vi(l) analysis as shown, and level translation where necessary, there is never a cause to have a system where a signal's level is interpreted incorrectly by a receiver, ever. This is basic to a reliable logic design.