Will BUFGCE get optimized to FDCE ?
What kind of schematic are we talking about?


elaborated design / logical schematic
RTL schematic
Placed and Routed schematic?
Device view
...


At first primitives don't get optimized unless explicitly enabled. I'm not sure if this optimization option from old Xilinx ISE (XST - Xilinx Synthesis Tool) got reimplemented in Vivado Synth. (After 5 years, here are still features missing from ISE ...)

Clock gating achieved by BUFGCE (BUFGCTRL) or BUFHCE are not equivalent to clock enables in slices. Please be aware that not the single flip-flop has a CE pin; it's the slice that has a CE pin. The combination of CLK (clock), SR (set-reset) and CE (clock enable) create a control set. Synthesis minimizes the number of control sets to achieve higher LUT/FF per slice density.