What is the real speed of my system implemented on FPGA? How to check this value?
First, you need to figure out the maximum allowed clocking for both designs (constrained by gates setup/hold-times, propagation delay etc). This will depend on the physical layout on chip (Quartus usually does a good job at this) and on your design, especially on the depth of logic that you put at the input of registers. More logic needs more time to settle and the register needs a settled signal before the next clock edge.

Use Quartus TimeQuest to find that value (it may run with every compilation depending on what task you choose in Quartus). BTW: Modeling the timing of chip-external connections is a bit of a black magic, it also depends on physical properties of the signaling and you should ignore it for a start. You may want to set the Modelsim clock to this value, so your time axis gives realistic readings.

The next question is about throughput: how many clock cycles does it take to process a certain amount of data. The NIOS-II will probably need hundreds of cycles to process one chunk of data while your design may accept one chunk per cycle. The cycle counts must be weighed by the clock speed of course (but again, chances are that your design is able to run at higher speed).

A different but related question is the latency of the computation. How long does it take to yield a result after giving input. Note that you may trade clock speed against latency by inserting registers in your design. This is called pipelining.