Using an array of resistors to give priority on a bus
We just need ohm's law. Let's say we define Io as the output current (source or sink) you allow.

Io has to be lower than 20mA for 74HC, or you'll be above the absolute limits. It also has to be much greater than the input leakage current (which is 1µA max for 74HC), or you'll have voltages levels out of specs.

The greater you set it, the more consumption you'll have, but the faster the chip with the resistors attached will be able to toggle its output states. Setting it to a few mA seems reasonable.

The resistors should simply be Vsupply / Io.



Impact on signal timing

This is also easy to estimate. You need to know the capacitance that exists on the bus line. It is the input capacitance of the reading devices, which is 3.5pF typical for one 74HC pin, plus the output capacitance of the left device in HiZ, which is 6pF typical for 74HC. It makes about 10pF if there is only one reading device. Now, you just have to check the RC time constant of this, using the resistor value that you chose. For example, with a 4k7 resistor, this leads to a 47ns time constant. This gives a rough approximation of the additional delay caused by the resistor. Whether this is acceptable or not depends on the rest of your circuit. If you work on a frequency ten times below this (about 2MHz for this example), you're probably fine.



Note: all the 74HC figures used here can be found in this document from NXP.



If it wasn't 74HC, but TTL LS: You'd have to do more accurate calculations, because the input leakage current is not so small. Moreover, the sink and source leakage currents (Iih / Iil) were different, as well as output sink and source capabilities (Ioh / Iol).

So you'd have to check every detail of every possible case, namely: when the left chip is at 0 and the right chip (with the resistors) is at 1, the opposite (left at 1 and right at 0), left at HiZ and right at 0, left at HiZ and right at 1.

For the two non-HiZ case, you'd have to consider, using the worst case output levels of left and right chip, whether the bus line level is still within specs (accounting for the input leakage, eventually multiplied by the number of chips that read the bus).

For the HiZ cases, check whether the voltage drop across the resistor due to the input leakage (eventually multiplied) does not make the bus line level out of spec.

Hopefully, these days are over.