static Hazard and challenging questions
Static-1 Hazard: the output is currently 1 and after the inputs change, the output momentarily changes to 0 before settling on 1.


Now consider the circuit. Assume that all the 2-input NAND gates have a delay of \$\delta_1\$ seconds and 3-input NAND gates have a delay of \$\delta_2\$ seconds (\$\delta_1 &gt; \delta_2\$). 



Let the initial input be A=B=C=D=1, then P=Q=1, R = 0 and F = 1.

If at time t=0, the value of A and A' are toggled, 

then at \$t=\delta_2\$ seconds,
P=Q=1 and  R=1 which will force F = 0 

then at \$t=\delta_1\$ seconds,
P=0 and Q=R=1 which will force F = 1

According to the logic the circuit's output should remain always at 1. But the output momentarily changes to 0 (for \$\delta_1 - \delta_2\$ seconds) and then comes back to 1. And this is called static-1-hazard.

Doing similar analysis for 0 to 1 transition of A no hazard can be observed. 

But if \$\delta_2 &gt; \delta_1\$, then you can observe the static-1-hazard at rising edge only.

In general it can be said that the given circuit, with B=C=D=1, can have static-1-hazard for change in the value of A. 

PS: This glitch in output happens when the delay offered by different paths in the circuit (from input to output) are different. So the delay difference need not be in the NAND gates. The inverter which produces A' from A can also contribute to it.