How to minimize characteristic impedance mismatches caused by vias?
Well... depending on what you're doing you could use a 3d solver to design a set of vias and return vias to closely match the impedance of your line.   Or you could keep your vias close to other discontinuities such as your source (your chip), destination, or connector.   Usually you want to keep those with in 1/4 Wavelength of your highest frequency of interest.  

Lacking tools but strong in motivation you could try to calculate by hand.   That could be useful if say you're jumping from layer 1 to 3 and layer 2 is your reference plane.  If your two routing layers don't share a reference plane you'll have to consider how the current will return, could be a via nearby, could be  decoupling cap, could be radiated coupling depending on the frequency. 

Really you want to control that return path so try to make it easy on yourself if you can.