Decreasing I2C SDA SCL interference
The easiest solution is to slow down the edges. Reduce the drive strength of the FPGA's pins. Add a larger capacitor. If that makes the signals too slow for 400 kHz, reduce the frequency. (Then, reduce the frequency even further and increase the capacitor even more, to get more safety margin.)
Increase the distance between the two signals, i.e., put a ground line between them. This will probably require a larger cable. (It is common to have every second line in a ribbon cable be ground.)
It might make sense to use an entirely different protocol, such as LVDS.