Implications of dynamic frequency scaling in an embedded system
Yes, of course there are issues. If the new clock frequency is generated by a PLL then you must allow time for the PLL to settle and lock to the new frequency.

If you increase the clock frequency you may also need to increase the operating voltage of the core. On the other hand, if you lower the frequency you may want to decrease the core voltage to save power.

Many peripherals are unable to run at the same frequency as the system clock, so if you increase the system clock you may need to change the divider values used to create the peripheral clocks.

Some peripherals, such as UARTs, use clock dividers to generate specific frequencies. If you change the system clock these dividers may also need to be adjusted.

If you increase the system clock you may need to add "wait states" to accesses of slower memory devices, such as flash memory. Alternatively, you could copy the executable code to RAM and execute from there.

As an example of a microcontroller where these issues are relevant, see the MSP432.