Xilinx ISE - VHDL: Code template to make a ROM
It would be better to use a vendor independent (and therefore portable) pure VHDL approach. Any good synthesis tool will infer a ROM from this code:

case address is
    when 1 =&gt;      result &lt;= 14;
    when 2 =&gt;      result &lt;= 45;
    when 3 =&gt;      result &lt;= 67;
    when 4 =&gt;      result &lt;= 32;
    when 5 =&gt;      result &lt;= 12;
    when 6 =&gt;      result &lt;= 64;
    ...
    when others =&gt; result &lt;= 0;  -- Default
end case;