Clock Domain Crossing for Pulse and Level Signal
You can add an edge-detection to the pulse/strobe synchronizer.

How does a normal pulse/strobe synchronizer work?


If it supports a busy signal, then the input is blocked until the circuit is ready
The signal is transformed from impulse to a level change by a T-FF (D-FF + XOR)
The level/flag signal is transferred to the other clock domain by 2 D-FF
The impulse is restored by another XOR gate and a delay (D-FF)
2 more D-FF are transferring the signal back to the source clock domain, so a busy signal can be derived (XOR).


What can happen to this circuit, if pulses are forming a constant signal?

The circuit will start to toggle and generate many pulses on the output.

Solution:

This toggling can be stopped by adding an edge-detection on the input (D-FF + NOT + AND) or if the sender complies to the busy signal.







simulate this circuit &ndash; Schematic created using CircuitLab

Source: PoC.misc.sync.Strobe