DDR3 bank activation
Every row/column intersection on a DDR3 chip addresses 1 byte wide, not 1-bit. So 1024 columns times 8bytes is 8KB / page (row).
From micron's data sheet, I observe that 8 bytes of data are fetched at a time into a FIFO using the upper-address lines of the column address. Then the lower 3 lines of the column address are used to select the particular byte from the FIFO. This is for x8 design. For x16, it would fetch 16 bytes (128 bits) from the row and place it in the FIFO, and then use the lower 3 bits to fetch one of the 8 16-byte data.