Question about a trigger input of a modern ARB/VSG (Vector Signal Generator)
You say the trigger from the laptop is synchronised to the FPGA clock and the slowest FPGA clock, are these separate syncronisers? 

The thing I am thinking is that two syncronisers (even to the SAME CLOCK) are not guaranteed to transition on the same edge. 

I would be syncronising with the slow clock and then using the fact that that clock is edge is syncronous with the fast clocks to avoid the need for further syncronisers (You would probably have to use some multi cycle path stuff in the constraints file).