What is the difference between a casez and a casex statement in Verilog?
I assume you are able to read the LRM, but are asking for an opinion: Why? 

The problem is that many Verilog features were put in at the specific request of a user, and some of those features wound up not being that useful. And sometimes a feature was put in because it seemed consistent and easy to implement at the time, but in the end turned out to be counter-productive. casex might be one of those features. But much of this is lost history.

You should never use casex.  casex is notorious for causing differences between pre- and post-synthesis simulations.

You use casez to model don't care conditions with a ? in your case item. However, if you can move to SystemVerilog, the case inside statement is even better because it only looks at don't cares on the case item expression, not the case selection expression.