interfacing multiple ADC: sharing master clock
What you need to decide is: Should they convert the same number of bits in the exact same time, or should they sample at the same time. These are very, very different.
(links to datasheets in your question would have helped me be quicker, by the way)
For reference; ADS1191/ADS1192 TI Datasheet and ADS1158 Datasheet
Starting at the same time is easy:
Both chips have a dedicated &quot;START&quot; signal (p10 ADS1191 and p6 ADS1158), which you can trigger simultaneously, and they will start sampling at the exact same time. One running at 16MHz might be done first (depending on the set conversion resolution!!), but does that matter? The analogue signal captured is of the exact same time. That's what that pin is for. ((Edit: One note: The ADS1191 datasheet doesn't specify the START polarity in that table, should look it up further on in the datasheet if you intend to use it. It's probably positive like it says in the ADS1158 table, but best to be sure.))
Converting in the same time has ifs:
If you need them to convert in the exact same time, with the same resolution and both datasheets specify the same number of clock cycles for that resolution (count the if's here!) then, yes, they should be clocked from the same source. But in such a case I would seriously consider using an external crystal oscillator of 2MHz for both, because clearly you have some very specific timing demands that an internal oscillator is not going to give you.
What I'm saying is: If you have reason to be worried about the conversion time mismatch in the order of microseconds (which I think you don't have if you use the start pins to synchronise, but those are details you didn't specify), you don't want to use any internal oscillators. At all.
What I think you meant to be worried about:
If you just want to be 100% sure of the correlation between samples from both, go into the datasheets, look at the START-Signal to Actual Sample/Hold time specifications and see if they match you expectation. I'm thinking they probably will.
What do you lost by clocking a high speed device at a lower speed:
If you do clock the higher frequency capable device with a lower frequency, you will indeed be sacrificing either speed or accuracy or both.
Let's say it can do 16 samples in 1ms at 16MHz (I didn't read that part of the datasheet, so this is hypothetical, not an actual number).
Then, if you clock it at 2MHz, it will only be able to do 2 samples in the same 1ms. If you only need one sample per 1ms and you don't need high accuracy through oversampling: No harm done. If you do want high accuracy, you probably want to over-sample and usually that's done at a factor 4, 8 or 16: Ah, shame: Now it's too slow.
The same goes for needing 4 samples per 1ms. It could do that at 16MHz, but now at 2MHz, it cannot. It's that simple.
Specific timing will come from your datasheet and you have not shared your exact requirements, so checking all of that is entirely up to you.