xilinx schematics to truth table
I wouldn't bother looking for tools and I would bypass truth tables and go straight to VHDL (or Verilog if you prefer). Given the schematic shown and a few coloured pens, this will take a few minutes, maybe up to an hour for a sheet as simple as the one you posted. 

Presumably the whole circuit is many such sheets.

And I am assuming they are all similar to that shown; breaking the design down into simple representable elements, gates and FFs.

The strategy I would take is: 

1) Identify and name each internal net (ignoring buffers, but recognising inverters). Thus S0 is connected to inputs on the top AND gate and the top left INV but the INV output is a separate net (call it SO_n or even N1). A coloured pen along each line as you go will help identify ones you haven't reached yet.

2) Identify and name the gates and registers.

3) Use a VHDL component (or entity instantiation) for each register

4) Use a signal assignment for each gate. These can be labelled with the name you gave each gate.

Then you have something like the following :

entity Sheet1 is
   port (
      S0 : in std_logic;
      S1 : in std_logic;
      Reset : in std_logic;
      Clock : in std_logic;
      F     : out std_logic
   );
end Sheet1;

architecture Netlist of Sheet1 is

   signal S0_n : std_logic;
   signal S1_n : std_logic;
   signal FDR2_Q : std_logic;
   signal AND3_1_Q : std_logic;
-- and one for every named net on the drawing

begin

   AND3_1 : AND3_1_Q &lt;= S0 and S1_n and FDR2_Q;

   FDR2 : entity Work.FDR 
           port map (
              D =&gt; Or4_1_Q,
              Q =&gt; FDR2_Q,
              C =&gt; Clock,
              R =&gt; Reset
           );

end Netlist;


The naming of each gate and net and, the labelling of each VHDL signal, component and concurrent signal assignment gives you the traceability back and forth between VHDL and schematic : more coloured pens to tick everything off, and you can quickly and reliably verify that the VHDL is an accurate rendition of the schematic.

Now you need models of the components like FDR : you can probably find them (e.g. in the Xilinx Unisims library in which case  you would write FDR2 : entity Unisims.FDR ) but they are quick and easy to create by hand.

Now the VHDL version can be simulated (to find out what it does!) or synthesised as you wish.