Trouble with double-buffer structure -- MachXO2 using FIFO_DC from IPExpress
It would seem like the path I was taking is simply "broken".

We actually switched to a pair of RAM_DQ modules acting as circular buffers;  their addresses are simply cycling counters (i.e., 10-bit counters that cycle when they do integer overflow);  have a fast-enough master clock, and synchronize the RD's and WR's to this master clock so that now we can put logic that decides which of the signals (RD or WR) are going to increase which of the addresses (depending on which buffer is being filled, and which holds the saved snapshot.

The solution to the original structure would have been similar, perhaps: synchronize the RD and WR clocks to some fast-enough master clock, and then I could have placed logic to route clocks wherever needed.