Apostrophe in Verilog array assignment
SystemVerilog has the array assignment operator '{...} in addition to the concatenation operator {...}.
Concatentation is for packed arrays - basically you combine multiple signals into a single bus.
wire [7:0] a = {4'd7, 4'd14};

You can nest concatenation operators too. The following assigns the same value to b as was assigned to a in the previous example. Nested concatenations flatten out to a single bus.
wire [7:0] b = {{1'b0,1'b1,1'b1,1'b1},{1'b1,1'b1,1'b1,1'b0}};


Array assignment is for unpacked arrays:
integer c [0:3] = '{0, 1, 2, 3};

Arrays can also be multi-dimensional, in which case you can initialise each dimension (from right to left) by nesting array assignments:
integer d [0:3][0:2] = '{'{0,1,2,3},'{4,5,6,7},'{8,9,10,11}};


You can also combine the two (concatentation and array assignment):
wire [7:0] e [0:3] = '{{4'd7, 4'd14}, 8'd1, {4'd5, 4'd3}, 8'd3};



On to your two examples.
The first example is of array initialisation. This would assign array[0][0] = 0, array[1][0] = 1 and so on, e.g. array[0][1] = 4 and array[3][2] = 11. For example, it could be used to initialise an unpacked array, such as:
integer array [0:3][0:2] = '{'{0,1,2,3},'{4,5,6,7},'{8,9,10,11}}; //Valid

In the second example, you are concatenating twelve 32-bit numbers (*) together, which would result in a single 384 bit number. This could be assigned to a packed array, but not an unpacked array:
wire [383:0] array = {{0,1,2,3},{4,5,6,7},{8,9,10,11}}; //Valid
integer array [0:3][0:2] = {{0,1,2,3},{4,5,6,7},{8,9,10,11}}; //Invalid


(*) Note, these are technically unsized literals, so the concatenation is not strictly legal, though most synthesis tools will treat them as 32-bit values and allow the concatentation (possibly with warnings). Always use size specifiers on your literals when performing concatenation.