Why would the intersection of logic 1 and logic 0 results in logic 0?
The diagram show is a high-level view of the decoding structure, it's not representative of the actual circuit.
The intersection points where it shows a dot are not intended to show that the two signals are physically shorted together (like you would find in an electrical schematic), but rather the dot represents a memory cell - in this diagram a dot seems to show a disabled cell, and a non-dot shows the enabled cell.
In a physical circuit you would have some access logic such as pass transistors on a grid of bit lines. The row decoder would enable the pass transistors for each cell on that row which enable that row to drive each of the column signals. Then the column decoder then routes the signal to/from just one of the column lines, thereby selecting just one active cell.