How to instantiate a FIFO on an iCE40 FPGA?
The Memory Usage Guide for ice40 devices states:


  Using programmable logic resources, an EBR implements a [...]
  First-In, First-Out (FIFO) memory.


The ice40 series doesn't have any hard FIFO blocks, you have to add the necessary logic around the memory blocks (EBR).

In Lattice Radiant software there is a "IP Block Wizard" that allows you to get some pre-written code for FIFOs. In Lattice icecube2 there doesn't seem to be a IP core generator included.

On the other hand, writing a simple FIFO in a single clock domain is a nice exercise and can be done in a few dozen lines of code.