Why are VHDL "external names" that are used to create alias to signal at another level of hierarchy, not synthesizeable?
Because hierarchical names do not use ports. You can refer to a signal in a different level/module, bypassing all I/O ports. 

To physical get to the signal the synthesis tool would have to auto generate additional I/O ports. It might be possible to implement this but I suspect that would open a whole can of worms.   

I maybe very old fashioned because I would not like a design to start routing signals between modules and hierarchies without me having very tight control over them.