what is the difference between logic,reg and wire in system verilog?? explaination with an example would be helpful
There is absolutely no difference between reg and logic in SystemVerilog except for the way they are spelled - they are keyword synonyms. logic is meant to replace reg because reg was originally intended to be short for register. Also note that logic is a data type for a signal, whereas wire is a signal type. Another signal type is a variable.

See this post for a more complete explanation.