Phase shift a data signal by about 200ns
This sounds like another case of a pre-supposed solution.  Explain the problem you are trying to solve one or two levels up.  Wanting a delay line is a red flag kludge alert.  That doesn't mean there are never good reasons for delays, but that usually when I've seen delays proposed they were results of less than ideal higher level design.

What you apparently want is a delay.  This is not the same as a phase shift except at a single frequency.  For example, 200ns is a 90 degree phase shift at 1.25MHz.  That same 90 degree phase shift at 5MHz is 50ns.

However to answer your question in case there really is a legitimate reason for a delay, you can do this cheaply and simply with a low pass filter between two logic gates.  R and C in parallel in the signal path is a high pass filter, not a low pass, although they would not remove the DC component.  You want the resistor in series with a digital output followed by a capacitor to ground.

The switching thresholds of digital gates are not well guaranteed.  You seem to want something cheap and simple, so maybe that's good enough.  The switching thresholds of CMOS gates are usually about half the supply voltage, so you want the R-C filter to decay 1/2 the way to its final value in 200ns.  The log(2) = .693, so you want .693 time constants to be 200ns.  Therefore

R * C * 0.693= 200ns
R * C = 286ns
R = 286ns / C
C = 286ns / R

One example combination is 2.9 KOhms and 100pF.

If you need more accuracy, then the second gate should be a comparator instead of just a ordinary logic gate.  That way the switching threshold is well known and controlled.