How does load affect an RC-filtered PWM DAC?
The analog signal from the filtered PWM will have some source impedance.  You can break that into two parts to understand it more easily.  Think of it as a 0 impedance source in series with a resistor of the actual impedance value.  Now you can see that this resistor and and load resistance form a voltage divider.  This is in fact the basis of Thevenin's theorum.  Use that as a search term and you will find much about it, so there is no need for me to get more deeply into it here.

Any load will make the output sag a little.  At some point it will make it sag to the level you care, and buffering is one way to allow for a lower load impedance than that.  The output will sag to half its unloaded value when the load impdance equals the signal source impedance.