Optimal configuration for PLL on LPC17xx
The best way to look at the issue is that the VCO (Voltage controller Oscillator) can be very sensitive to voltage ripple and spikes which translates directly into jitter.  the key to a good PLL is low output jitter, but there is a a compromise, a low jitter PLL will also be slow to lock.

So contrary to what Andy has to say, you must run the PLL at as high a divide ratio as possible.  The divider/count down circuit acts as a low pass filter and reduces jitter (actually it averages it) making the control of the VCO smoother.

here is a PDF link

Page 5 gives you this nugget "In integer-N PLLs, synthesizing tight channel spacings requires extremely low effective reference frequencies"  


tight channel spacings means low jitter.


and more:

This results in very low loop bandwidths and high divide ratios
• Slow PLL frequency switching time
• Large area passives
• High phase noise at low frequencies

they use these facts to derive the fact that a fractional - N frequency synthesis solves these issues ( the need for high divide ratio)

So yes, your manual is right.