Post-synthesis simulation: Loading a custom standard cell library to a verilog compiler
Verilog simulators usually do NOT allow you to load a standard cell library in their .lib for usage.
If you used a tool like Cadence Liberate for charecterization of the standard cell library, then you can do
write_verilog -specparams -table_style min-avg-max libname.v
You need to have the .v file for the library. Once you have this, you can compile them in the right order.
Library, then the design, then the testbench.