Proper ways to disconnect ICs during low power states to avoid parasitic/backfeed supply
When I do this, I usually use CMOS analog switches on the affected data lines.

Something like the ADG812 has 4 channels of SPST switches that are easily suitable for quite fast logic, and provide a really high impedance between the switch nodes when in the off state.



The nice thing about this is that the technique works for both unidirectional and bidirectional data lines.

These parts also run on a bright smile:



The usual sequence for power down:


Turn off data path switches
Power down domain.


Power up is the opposite, of course.

[Update]

These are indeed known by other names, such as pass gates and transmission gates.

These are significantly different from a true tri-state buffer (as you can see in the diagrame in the link above), but for ordinary logic, the effect is better (this is inherently a bidirectional device) but with lower power.