ESD/EMI Design for CE, Recommendation seems wrong from test lab
I can only speculate on their reasoning.  It's important to take into account that geometry is at least as important as topology or component selection in both EMC and ESD issues.

First, you had an emissions issue.  The reason they moved L1 may have been because they wanted the LC filter (including C1) to be filtering EMI from getting from your processor to your connector.  However, L1 and C4 should (theoretically) give you about 95dB of isolation at 100MHz, although C4 will probably resonate below that--you might want to try 1000pF to get up into the 100MHz+ range (depending on size...see here).  I suspect you're right about the spikes coming from the power supply, and that changing the loading at high frequency changed the behavior.  That can only be verified experimentally.

The splitting of the ferrite into two is less obvious.  They may have been attempting to distribute the current, or isolate the LED and uP.  It seems like a bad idea from an operational standpoint to isolate your chip from your bypass cap, though.  Again, they may have been randomly trying things and hit on just the right geometry.

On your ESD diodes and EMC caps, KEEP LINES SHORT.  Any trace leading to a pad is an inductor, which is not what you want in series with these components.  Ideally, any trace that goes past these devices should go THROUGH the pad, rather than having a T configuration.  Think of it intuitively like this...if you're going to post a guard, you want everyone going in and out to have to go right past the guard.