VHDL Aggregate on Left Side of Assignment : Error in Simulator
Now that we have a testcase, ghdl reports:
ghdl -a --std=08 VHDL_test.vhd
VHDL_test.vhd:26:17:error: can't match 'nxt_cnt_a' with type std_ulogic
VHDL_test.vhd:26:17:error: target is not a signal name

Which is a little less confused than your simulator, that the error is to do with mixing different types within an aggregate. (but see edit below : this is no longer an error in VHDL-2008 : and is compiled correctly by the current GHDL 1.0-dev build.
Now obviously we can do it by brute force : widening the intermediate signal for example...
  signal Count_a: unsigned(Cntr_Width - 1 downto 0) := (others =&gt; '0');
  signal nxt_cnt_a : unsigned(Cntr_Width downto 0) := (others =&gt; '0');
begin
  --(Carry_Out_a, nxt_cnt_a) &lt;= RESIZE(Count_a, nxt_cnt_a'length + 1) + 1;
  nxt_cnt_a &lt;= RESIZE(Count_a, nxt_cnt_a'length ) + 1 ;
  Carry_Out_a &lt;= nxt_cnt_a(Cntr_Width);
  
        -- in synch process
        Count_a  &lt;= nxt_cnt_a(Count_a'range);

so you have a workaround, but it would be nice to get the aggregate working...
Relevant : (from the VHDL-2008 LRM)

9.3.3.3 Array aggregates
For an aggregate of a one-dimensional array type, each choice shall specify values of the index type, and the
expression of each element association shall be of either the element type or the type of the aggregate. If the
type of the expression of an element association is the type of the aggregate, then either the element
association shall be positional or the choice shall be a discrete range.

I think we need to make it clear somehow that the aggregate type is unsigned.
EDIT: My reading suggests that this should in fact work: std_ulogic is a valid element type for unsigned, and the unsigned component of the aggregate should define its type.
Xilinx Vivado (2018.2) reproduces the compile error shown by ghdl(above) in VHDL(old) mode. However in VHDL-2008, it successfully compiles, and (making Clk an internal signal) simulates without runtime error.
Which leads me to suspect we are seeing TWO tool bugs:
ghdl - while excellent - does still have some holes in VHDL-2008 support (as has Vivado, which doesn't even support conditionals on std_logic yet) and this does seem to be one of the points where it hasn't caught up with -2008.
EDIT : Now resolved : the current build DOES compile this case correctly with no runtime error.
your simulator : while it parses this expression, it doesn't appear to compile it correctly, leading to the runtime error you see. The fact that two other simulators run it happily supports this being a tool bug.
Now we see the value of a simple testcase : I think it is worth making the Clk changes to run standalone, and submitting to Aldec tech support for their review.