Violating the minimum clock pulse width of a D-type flip flop
It depends on how short the pulse is.  

If it is extremely short, the transmission gate or tristate element which grants access to the master latch will not have time to even properly turn on, so the bitcell will retain its original value and nothing will happen.

The other case of failure due to minimum pulse width is the case in which the forward element does have time to turn on.  But instead, the feedback loop in the bitcell does not have time to settle, and will become metastable.  So in this case the output will go to a random value after an indeterminate amount of time.

A third situation; though not necessarily of failure, is when the pulse is long enough to complete the feedback loop, and long enough for the feedback loop to nearly settle.  However due to the input getting cut off towards the end, there will be a greater clk->out delay; as it will take longer to settle than with a longer clock pulse.  This is not necessarily a failure unless the next stage of logic does not have enough slack to make up for the extra delay.