Is there application note or white paper with an in-depth explanation or best practices for how to size PCB bed of nails test points?
See 3.5.4.1 in IPC-2221A

0.9mm is the smallest recommended but they say as small as 0.6mm is feasible in boards &lt; 7700mm^2

Clearance required varies depending on adjacent component height (but minimum 0.6mm) and part height on probe side should not exceed 5.7mm. 



Probe centers on 2.5mm grid if possible.