VHDL-AMS simple code but std_logic_vector to quantity issue
If you draw a new schematic with the built-in editor it would be easier to see what is going on.

How will the counter control the voltage and current? It sounds like you will need a DAC and an amplifier if you were to really build it.  

I have to force myself to think about real systems when I'm designing with VHDL.  It's not like a HLL such as Java or C++.  Those languages try to be as far away from the hardware as possible.  

VHDL, however, models real circuits since it is used for synthesis and P&amp;R on an FPGA.

Here are some type-casting examples showing how to change a std_logic_vector into a signed or unsigned int (page 9).

Here's an intro for VHDL-AMS I found from a Google search.