Why we gradually increase size of inverters in buffer design?
Driving a very large inverter from the output of a normal (tiny) logic gate means that a large capacitance will be charged and discharged with tiny transistors. This takes a very long time, causes slow rise/fall transitions on the output pin, and causes considerable power waste in the large inverter.

Depending on the exact process parameters, it usually turns out that the lowest total propagation delay results from having a sequence of inverters. As the signal progresses from the internal logic signal to the output pin the transistors in the inverters get larger, increasing by a factor of 3X to 5X in each successive inverter.