Measuring switching time of 5LN01SP (NMOS)
Rise times typically &lt; 50 ns must be done on 50 Ohm controlled impedance PCB’s with coaxial connectors to/from the DUT.    Wire leads add 500 ns per cm pigtail wire loop into a 50 Ohm load. Then add gate resistance and gate capacitance to the load.
Following the component test schematic is logical and assumes you understand the physical implications and have the necessary test equipment.   In this ultra fast FET case, you would need an Active FET probe with a faster risetime and load &lt;&lt;1pF with a resistive divider from 450 to 50 Ohms.  With AC coupling from Gnd test lead to V+ using &lt; =100pF NPO ceramic.
The sig gen could be 50 ohm coax with a short pigtail soldered to the resistor, if you wanted a make-shift test. Then Gnd’s must be single point short as possible with good RF ceramic cap across the DUT.  ~ 100pF//1nF V+/0V