Is it possible to move VHDL code from the top level of a design to a subcomponent, without changing the underlying logic?
Yes, and it is actually a good practice. It seems like you have already answered most of your own question: turn the registered values into outputs of the lower-level component. This should get you on the right path; if you need more details on how to do that, please show us your source code.

Some other hints that might be helpful:


In VHDL-2008, you can read from output ports, so you don't have to rename your existing signals. In previous VHDL versions, you could use buffer mode ports to the same effect.
IDEs with integrated refactoring (like Sigasi) can rename signals for you automatically, so this is actually less work than it seems.