Erratic behaviour in FPGA based I2s loopback (Verilog + Spartan6)
This looks a lot like issues associated with not synchronizing all of your inputs into the main clock domain.  You should always be running all of the input signals through flip-flops before you use them for anything.  

As for your 12.288 MHz clock out; use an ODDR2 element to drive it like so:

ODDR2 #(
    .DDR_ALIGNMENT("C0"),
    .SRTYPE("ASYNC")
)
oddr_inst (
    .Q(clk_out),
    .C0(clk),
    .C1(~clk),
    .CE(1'b1),
    .D0(1'b0),
    .D1(1'b1),
    .R(1'b0),
    .S(1'b0)
);


Note that the global clock pins are only required to bring clocks IN to the FPGA.  Driving clocks out can be done on any pin, and the recommended way to do so is with a DDR flip flop so that you can precisely generate an inverted clock that exactly aligns with data from IOB flip flops driven by the same clock.