Length of primary polynomial for scrambler
A shorter polynomial has fewer possible states – which becomes quite obvious if you think of it as shift register.

First of all, I'm surprised


your high-order polynomial uses exactly twice the amount of LUTs as your lower-order, and
that even your lower-order polynomial uses 131 LUTs.


In a naive implementation, you'd simply use order number of registers to implement the shift register, and one LUT per feedback path to implement one addition in GF(2). In fact, addition in GF(2) is XOR, and modern FPGAs have cells that can probably do a three-inputs-single-output XOR. So, your polynomial should be possible to implement with 1 or 2 LUTs, and a lot of registers to implement the unit delays.

Your ressource usage points to you possibly doing some actual integer multiplication or exponentiation somewhere in your code. That doesn't make sense.

But, to your actual question:

yes, a shorter polynomial won't guarantee "whiteness" as well as a long one would.

To illustrate: imagine your input data was constant – in that case, every polynomial would repeat itself after its sequence length (and that would in the best case, and usually, if sensibly designed, be \$2^\text{order}\$). So, your lower-order polynomial's output would be very periodic – which might or might not be a problem at all, depending on whether you actually depend on the actual whiteness of your scrambled data.

Now, constant signal isn't the only thing that can make your scrambler output periodic – in fact, there's as many chances to "hit" a periodicity-introducing sequence as there are possibilities to find order-long signals that repeat in your data block.