VHDL don't care for integer
There is no "don't care" for integer; if you are modelling digital logic with X, Z, don't care etc, then numeric_std.signed/unsigned is the right way to go.

But look at the numeric_std package more carefully; most operators including = are overloaded with forms that allow mixing [un]signed and integer freely, so that if my_unsigned_var = 3 just works...