CMOS IC Dynamic Edge-Triggered Flip Flop setup and hold time calculation
I'm writing this answer just in case someone really wants to characterize the setup/hold times of a flip-flop, rather than answer a homework question.

There isn't really a sharp pass/fail boundary that you can use to define setup and hold time. As the changing edge on the data input gets closer to the clock edge (either before or after) you will see that the delay from the clock edge to valid Q output starts to increase. The flip-flop will fail because the clock-to-Q delay becomes unacceptably large, not because it fails to change states entirely.

So, you first need to determine that maximum clock-to-Q delay, by simulating with very large setup and hold times, over the range of temperature, supply voltage, and process variation. 

Now you must decide what maximum value of clock-to-Q delay you want to specify for your flip-flop.

Then you run simulations, again over PVT, slowly moving the data input edge closer to the clock edge until the measured clock-to-Q delay exceeds your maximum specified value...at that point, the time from the data edge to the clock edge becomes your required setup time. A similar approach is used to find the hold time.