Using string type in VHDL
I think you really want an enumerated type. They will show up named in the simulation without the hassle of strings. You will need to check them out to figure out completely how to use them. Here are the basics:

-- declaration   
type my_enumerated_type is ( good, bad, ugly);
signal rating, rating2 : my_enumerated_type;
constant ENCODED_TYPE_WIDTH : natural := 2;

-- helpers - use a function like this to convert between enumerated type and std_logic_vector
function encode ( rating : my_enumerated_type ) return std_logic_vector is
begin
  return std_logic_vector(to_unsigned(my_enumerated_type'pos(rating), ENCODED_TYPE_WIDTH));
end encode;

function decode ( rating : std_logic_vector ) return my_enumerated_type is
begin
  if unsigned(rating) &lt; my_enumerated_type'length then
    return my_enumerated_type'val(to_integer(unsigned(rating)));
  else
    return ugly;
    -- TODO: throw an error instead? like so: 
    -- assert false report "rating out of bounds in conversion to my_enumerated_type" severity ERROR;
  end if;
end decode;

-- conversion
output  &lt;= encode(rating);
rating2 &lt;= decode(input);


These enums can be fun and powerful in VHDL. Enjoy!