Full Adder driven by clock [FPGA/VHDL]
This is hardware design. If you want an adder, it must exist all the time, even if it is only being used some of the time. Therefore, you need to:


instantiate the adder in your counter module
connect the ports of the adder to signals


one input port gets the constant you want to add to the counter
one input port gets the current counter value

in your clocked process, load the counter with the sum from the adder


The adder will be computing the next counter value all of the time, but that value will only get used when the clock edge occurs.