Maximum via frequency
There are several schools of thought about this topic, but I'll put in my experience, but I'm sure others will have a different opinion.

I have designed Automatic Test Equipment (ATE) boards for several years; these boards were meant to fit between the ATE and the DUT, in my case it would be a new Chip out of the fab. Knowing this, the boards I would have to design had to be transparent to the system and signal integrity was the  priority, which meant a lot of layers, anywhere between 16 and 56, and a solid ground plane at every other layer. All traces had to have a 50 Ohm impedance, 100 Ohm differential, or any other impedance required by the specific system.

Most of the devices tested had hi-speed busses, such as DDR3 or Gb Ethernet, which meant that extra care was required. We used 50 Ohm vias, and a very careful use of the layers, in order to avoid stubs, and if that was not good enough, back drilling would help us out.

Because these boards were hugely expensive, we had to take all of these precautions, but there examples that say that any of these are not needed.
This article goes through the paces and might help you out
https://www.ee-training.dk/announcement/high-speed-via.htm

The reason why the max bit rate is twice the frequency is because a bit is a transition between 0 and 1 or viceversa, while the frequency is a whole cycle of 0-1-0, see picture below.