NVIC memory map ARM cortex M3 STM32f103
You're correct -- that looks like a typo. The offset for that register should be 0x350.

The CMSIS header file (core_cm3.h) avoids the issue entirely by defining NVIC-&gt;IP as an array of bytes, not of 32-bit words:

__IO uint8_t  IP[240];                      /*!&lt; Offset: 0x300  Interrupt Priority Register (8Bit wide) */


This documentation error was probably the result of confusion between the byte-wise structure used by ARM and the 32-bit structure used by ST.