Can I slow a CMOS output through an RC filter?
Sure, and it's not as uncommon as you may think.

You use it mostly when impedance matching is not an option, e.g. because you are forced to break your impedance-controlled transmission lines when running them over connectors or wires.

FPGA outputs are often very fast, and if there's a bit of a trace length involved, you can ad a 22...50&nbsp;Ohm resistor in series, and put a small capacitor (10...100&nbsp;pF) between the next chip's input and GND. Also good if done the other way round (capacitor at FPGA input).

Examples include, but are not limited to:


This avoids ringing, and most importantly, it may keep the voltage from swinging below GND or above VCC. Some logic families (or FPGA inputs) are quite sensitive when it comes to under- and overshoot.

Compared to real, impedance controlled traces, it's a nasty hack, of course, but it's still way better than severe ringing on an input.