Has there been any deliberate implementation of combinational logic soft error correction in any consumer-level product, like a CPU/microcontroller?
As you mention, ECC has been available in memory, busses and CPU in by simple parity checking or 8B10B coding and variants.
This is all aside from ECC used in communications links, of course.
An ECC scheme for soft errors is not to be confused with a ECC with soft error decoding. (Thanks to Elliot for the clarification in the comments)
To clarify a &quot;soft error&quot;  as meant by the OP is &quot;a type of error where a signal or datum is wrong. Errors may be caused by a defect, usually understood either to be a mistake in design or construction, or a broken component. A soft error is also a signal or datum which is wrong, but is not assumed to imply such a mistake or breakage. After observing a soft error, there is no implication that the system is any less reliable than before. One cause of soft errors is single event upsets from cosmic rays.&quot; https://en.wikipedia.org/wiki/Soft_error
In contrast, &quot;soft&quot; ECC decoding involves reading signal a level with an ADC, and not a slicer or bit &quot;detector&quot;, in order to assign a probability metric to a reading and improve ensuing maximum-likelihood decoding. This is cumbersome and expensive (and I'd argue mostly of academic interest) if applied within logic processing.
ECC in high-speed busses and high-density memory are not performed with such a &quot;soft&quot; metric, but sometimes the &quot;hard&quot; processing does involve a third &quot;erase&quot; or &quot;invalid&quot; level/flag to convey fault detection from one level of processing (sensing) to another (decoding).
Back to the question: as for ECC outside the realm of storage and transfer, there are logic and arithmetic techniques with built-in redundancy or detection, that deal with signalling errors developed within the logic processing, i.e. within logic cells, registers, CPU, arithmetic units etc. In fact, they are built precisely to deal with &quot;soft errors&quot;, induced by cosmic effects, power supply effects, instantaneous interference ingress etc..
Have a look at fault tolerant computing, fault-tolerant logic, stochastic logic, hardware-redundant logic.
If all of the above was already clear, and you are asking whether fault tolerance against soft errors is built-in with commercial products, I think you are asking a very open and broad question. Perhaps some readers can point to evidence thereof, but for the most part I believe within the internals it's nothing more than simple parity checking.