FT232R TTL Logic Levels
UART communication uses positive logic. In TTL, logic 1 is 5V, logic 0 is 0V. However, in UART, the idle, no data state is 1/HIGH, not 0/LOW. What you are seeing here is not inverted logic level, but simply an idle UART line.

The Wikipedia article on Universal asynchronous receiver-transmitter has a good explanation.


  Data framing: The idle, no data state is high-voltage, or powered. This is a historic legacy from telegraphy, in which the line is held high to show that the line and transmitter are not damaged. Each character is framed as a logic low start bit, data bits, possibly a parity bit and one or more stop bits. In most applications the least significant data bit is transmitted first.


For completeness, here's an example. I'm sending ASCII character "U" (01010101) via UART, 1 start bit, 8-bit data, no parity, 1 stop bit, 9600 baud. 

On an oscilloscope, you will see the following waveform. Because the least significant data bit is transmitted first, binary digits of ASCII U is reversed.