Demultiplexor logic table simplification
You are making a classic error.

You need to list the possible states of the input pins and the resulting outputs: you have listed the outputs as if they were inputs.

As there are only 4 possible combinations for the input pins, the final table you have is what you should have done originally.


  /**
  * Input possibilities | Output result from requirement
  *   in | sel |            a | b
  *   ---------------------------
  *   0  |  0  |            0 | 0
  *   1  |  0  |            1 | 0
  *   0  |  1  |            0 | 0
  *   1  |  1  |            0 | 1
  */


In verilog

    module demux1to2
    (in,
    sel,
    a,
    b);

    // inputs
    input in;
    input sel;

    // outputs
    output a;
    output b;

// I am using registers for the outputs

    reg a;
    reg b;

        always @(in or sel)
        begin
            // find sel
            case (sel)
                1'b0 : begin
                // a output selected
                a = in;
                b = 0;
                end

                1'b1 : begin
                // b output selected
                b = in;
                a = 0;
                end
            endcase
        end
 endmodule