Difference between best/worse-case latency
I don't have much experience with Vivado HLS, but for digial logic in general the latency or delay refers to how long between when the inputs of a circuit are set and when the outputs settle at the right result. 

For a combinational logic circuit (no flip flops or clocks, just computing a boolean function) latency is how long it takes to propagate a changed input through all the cascaded logic. Here we generally only care about the worst-case latency because it determines how fast we can run the circuit and still get the right answer. 

For a sequential logic circuit (which is probably what HLS generates), latency is how many clock cycles are between the input being set and the output being ready. These kinds of circuits are often modeled as a finite state machine, and depending on the data, the FSM could finish earlier or later. Best case/worst case latency describe the shortest and longest runs of the FSM. We mostly care about the worst case latency, but if the worst case is rare, we may be able to gain a performance boost on average by starting the next computation right away.