Clock : CPU clock vs Pipeline Clock Vs Memory Access Clock
No, it would be normal to clock the CPU at 50MHz. Or double the input clock to 100MHz for example, if the design is fast enough. 

Now you know the memory stage takes 5 clock cycles, so you stall the CPU when it can do nothing because it is waiting for memory. Then there is a obvious gain from compiling your code to minimise memory accesses and their associated speed penalty, for example by using registers wherever possible.

At a later stage you can add cache memory, which "snoops" all memory transactions, and satisfies as many as it can from a small fast memory, perhaps in 2 cycles instead of 5. Where the cache memory doesn't contain the data, you have a "cache miss" and the main memory proceeds as normal. Logic in the cache controller decides whether or not to also store data from main memory, so the cache has it next time...