Flip flop asynchronous reset timing
While assertion of an Asynchronous Reset is not an issue, de-assertion can be an issue if it happens near clock edge. Asynchronous signals like Asynchronous Resets hence have to satisfy two timing checks to avoid metastability: Recovery and Removal checks . This is similar to setup and hold checks. 
To avoid metastability condition, de-assertion of Asynchronous Resets are normally made synchronous in designs and the design is then timing verified for Recovery and Removal Timing checks. 


reset synchroniser with active low async reset and synchronised de-assertion: 



Just like clock, reset is also a high fanout signal and hence it has to be properly distributed through out the design with buffers.


Asynchronous Resets are also prone to spurious resetting due to glitches in the line. Hence some glitch-filtering mechanism is also incorporated on this line.