Design a circuit that detects if one input is a delayed version of the other
The concept you're looking for is cross correlation.
You basically need to continually compare B with all of the allowed delayed versions of A, and keep track of which delay value(s) consistently show a match. As long as there's at least one, then Y should be asserted.
Note that there is no upper bound on the time required to detect a lack of correlation -- B might appear to be a delayed version of A for thousands of bits, until suddenly it isn't.

Here's some Verilog code that does what I described above. However, I'm not absolutely sure that this addresses the actual problem, because I don't understand the sentence, &quot;If B is guaranteed to have 1s, then Y should be 1.&quot;
/* Do a cross-correlation between two signals to determine whether B is a
 * delayed versions of A, with a delay in the range of 0 to N.
 */

module xcorr #(
  parameter N = 10
) (
  input         A,
  input         B,
  output logic  Y,
  input         clock,
  input         reset
);

  reg     [N:0] A_delay;
  reg           B_delay;

  always @(posedge clock) begin
    A_delay &lt;= {A_delay[N-1:0], A};
    B_delay &lt;= B;
  end

  reg     [N:0] correlation;
  reg     [3:0] count;

  always @(posedge clock) begin
    if (reset) begin
      count &lt;= N+1;
      correlation &lt;= {N+1{1'b1}};
    end else if (count &gt; 0) begin
      count &lt;= count - 1;
    end else begin
      correlation &lt;= correlation &amp; ~(A_delay ^ {N+1{B_delay}});
    end
  end

  assign Y = |correlation;

endmodule

The shift register A_delay creates all of the allowed delays of A.
We also capture B in B_delay in order to make checking the zero-delay case easier.
Each bit of the correlation register keeps track of whether we have ever
seen a mismatch between B and the correspondingly delayed version of A.
Therefore, it starts out set to all-ones, and bits are cleared whenever
a mismatch occurs.
The counter is used to allow the shift register to fill up with valid
data before we start checking. Once the delay expires, the output remains
asserted as long as at least one correlator is still asserted.