Inherent Pseudo-Randomness in modern FPGA design tools
TL;DR; The answer may depend on the synthesis tools, but most likely the answer is no unless you use randomised seeds.



Certainly for modern versions of Intel/Altera Quartus (since some time before 12.1), if you compile the exact same source files using the exact same software version (including subversion/patch level) for the same device, you will get the same result each time.

The synthesis tools for Quartus do use randomisation when searching for the best fit - they will try lots of different pathways to fit the design. However they make use of a seed value for their PRNG. This value is a constant which doesn't change from compile to compile. You can of course manually change it in the compilation settings.

The net result of using a fixed seed is that no matter how many times you compile the design, you get deterministic results. 

Quartus does have a tool called Design Space Explorer that allows the design to be compiled multiple times with different seed values to try to find one that results in a better fitting. But that will allow you to save the seed value once found for future deterministic compiles.

This is actually very useful behaviour. Say you want to use source control to keep all of your source files safe, but don't want to check in the compiled netlists - you need to be able to recreate the netlists/bitstreams from source without them changing. Or you want to update a memory initialisation file. You don't want the whole design to change just to change a default memory value (e.g. instruction data for a soft processor).