Why do TTL integrated circuits have such complicated schematics for logic gates with so many transistors as opposed to RTL?
Some of the biggest drawbacks of RTL were:


much lower noise immunity ( 1x Vbe bias vs 2x) 
excessive static power dissipation for "0" output state due to low pull-up R for low impedance needed to reduce rise time for "0 to 1" output state to drive pF loads. Such as R2= 50 Ohms.  
Noise immunity and slew rates were very asymmetric if R2 was high ( e.g. 1k)

 

TTL solved these problems with a totem pole output. and raised the input threshold to 2 equivalent diode or Vbe drops (1.35 to 1.4) 


the standards for input and output levels never changed as the TTL family increase speed and reduced static power and lowered the collector resistance from 130  to 50 Ohms for the fastest TTL speed.
The evolution of TTL came from efforts to increase transition speed, noise margin, reduce power,  while retaining backward-compatibility, input thresholds, fanout=10, output levels.





These were the most minimal solutions to reach the specs and lower Pd from 74' to 74LS then for 74S'  reduce slew time to ~ 1/3 for On and OFF into 15pF load, while preventing shoot-thru  with both drivers active.  RTL never had a shoot-thru  problem with only 1 driver and passive pull-up.  A totem pole output impedance is non-linear yet controlled to remain low without large  surge currents.  Decoupling caps were only needed every 10 IC's, unlike CMOS 1 per IC.

Even though TTL appears to be asymmetric for voltage and impedance, the immunity from stray noise and crosstalk is balanced between the logic levels for noise power.