How to model electric power consumption in verilog-a?
Let me list some ways to model power consumption of a circuit:


A resistor between Vdd and GND
A constant current source between Vdd and GND (this can cause an issue when Vdd is off, for example the regulator supplying Vdd is off, then the current source might generate -1 kV for example to make the current flow).
A controlled current source which will only have a current > 0 when the enable input is high and Vdd > 1.8 V (just an example).
A controlled current source which has some complex formula/function to control it for example, it draws a defined pulse of current at every transition of a certain signal


Do discontinuities ...cause convergence or stability problems for the simulator?

They do not have to but they can, personally if I can avoid using a discontinuous functions then I will. But it depends on how often the discontinuity will occur, for an enable signal that switches on/off once per simulation I care less than for the switch in a DCDC converter which is switching continuously.

Is it a lot more costly to compute this?

Of course it will cost more as you add more. Keep it as simple as possible to keep the computing costs low. Only include that what you need.