Circuit MOSFET Pulldown Circuitry
To determine the arrangement of the NMOS pulldown network, you need to think about what the conditions are that will cause the output to go low. You have the equation \$Z=\neg(C(A+B))\$. The nice thing about this is that the negation helps simplify your work. It is already telling you that Z is low when \$C(A+B)\$ is true. \$C(A+B)\$ means "C and (A or B)".

"A or B" can be realized by putting two transistors in parallel, connecting source to source and drain to drain. Then "C AND" can be realized by putting C in series with the previous circuit. Can you draw the circuit I've described?