Can not keep pin LOW during FPGA configuration
This sort of thing is device-specific.  You need to look at the documentation for your device and see what the behaviour of I/O pins is before configuration.   It's most unlikely to be 'some random value' - it's much more likely to be some defined pull-up/down.

As I'm sure you appreciate, nothing you put in your configuration is going to influence the device before the configuration has been loaded...

Update:

Now you've provided some info about the specific device, I'll point you to page 45 of http://www.xilinx.com/support/documentation/user_guides/ug381.pdf, which has a lengthy description of the behaviour of pins before configuration completes.  In summary, they have a built-in pull-up, which you should be able to disable by tying a control line down.

The device's pull-up current is specified in the datasheet, and it's believable that 10K might not be enough to overcome it.

The Spartan 6 documentation is ridiculously fragmented into umpteen separate documents - I wouldn't pretend you need to read them all from cover-to-cover, but you do need to be able to find your way around them - they're all linked from that document you linked to.   I think if I was starting a Spartan-6 design right now I'd download the whole lot and splice them into one big PDF before I started.