Verilog implementation - variable range error for a register assignment
It would really help to show the code you wrote as your attempt and how it is supposed to iterate, as well as the exact error, but I think you just need a logical shift left.
logic [7:0] reg8;
logic [11:0] reg12;
int iterator;  // goes from 0 to 7

// each iteration
  reg12 = reg8 &lt;&lt; 11-iterator;