DM74LS00 Voltage drop
If you look at the output circuitry of a TTL gate you'll find something like this. 



OUTPUT LOW

When the output is LOW then TR3 is turned ON and TR2 is OFF. The Tr3 transistor will be in saturation which means there will be a small voltage, V4, ( about 0.1 - 0.2 volts) at the output when sinking a current (your meter or a ttl 'input'). This voltage will increase with increasing sink current. This ties in nicely with your measurement of 112mV.

OUTPUT HIGH

When the output is HIGH TR3 is OFF and TR2 is ON but we now we have THREE voltages drops before the output. 

(1) A drop across the 130 ohm resistor  -  V1 

(2) A drop across Tr2  -  V2 

(3) A drop across D1  -   V3 

Now V2 is in the region of about 0.1 - 0.2V, V3 will be about 0.6V and V1 depends on the output current. So a loss of 0.9V (mainly V2 + V3) is quite reasonable when the output is sourcing a very small current (your meter) and once again ties in with your measurement of 4.1V.

At no time are both Tr2 and Tr3 turned on together.