How is high impedance state physically different from a logic low state?
Here's a possible implementation of a tri-state output.

If only the top FET is ON then the output is logic level 1.
If only the bottom FET is ON then the output is logic level 0.
If both FETs are OFF then the output is high-impedance, which means this particular output pin doesn't do anything to the actual voltage on the wire. If it is not driven to a valid logic level by some other component, like a pull resistor or another non-tristated output wired in parallel, then it has no defined logic level. Usually it is noted as logic level &quot;X&quot; which means &quot;undefined&quot;. Actual voltage will be &quot;whatever&quot; depending on circuit parasitics like leakage or remaining charge in chip capacitance, and if this is fed to the input of another chip it may be interpreted as any random level, or cause excessive current draw if voltage is close to midsupply and both input FETs conduct.

If so, is it possible to identify whether a terminal is tri-stated or 0 without measuring the resistance of the terminal?

No.
You can use LEDs as you say in the question, here are examples:

On the left, if the gate outputs 1 or 0, only one LED will light up. If it is High-Z then both LEDs will light up if supply voltage is enough for 2 series LEDs, or no LEDs will light up if supply voltage is too low.
On the right, if the gate outputs 0 the LED will not light, if it outputs 1 it will glow strongly, and if it is High-Z the LED is connected to the supply via a high value resistor so it will glow weakly.