What happens when you assign the result of a reduction operator to a multi-bit wire?
After simulating in Vivado, I found that the undefined bits are overridden when the | operator is applied to a vector with a 1 in it, and the result 1 is placed in bit 0. If no 1 is detected (only 0 or X), the rest of the vector is returned as 0, but bit 0, the result, is returned as X.

In other words, Verilog, at least in Vivado's implementation, produces:


|(4'bX010) = 4'b0001
|(4'bX000) = 4'b000X
|(4'bXXXX) = 4'b000X


Per your question, no "error" is caused, because these are all defined values of Verilog's wire data type. This result makes sense because a 1 in the input vector must, by definition, OR to produce 1, but since an undefined value could be anything, we can't say for certain what the result is if we're only ORing it with 0s.