Help with understanding the mechanism of this parallel to serial shift register
Good question!
The diagram is diagrammatic - ie it lacks some detail - one detail is crucial.
The "secret" is that they have left out one vital step.

The missing link: Prior to shifting starting a "LOAD" pulse transfers all the BIT(X) inputs to the mux outputs.  When "CLOCK" is active for the first time it transfers all the bit data into the SR (shift register) as an initial parallel load. 

Now "normality" takes over.
After the initial load, the muxes connect Qn data to Dn+1.
So, once the data is loaded as above each relevant clock edge transfers the output on Qn to Dn+1 so the data shifts right one stage and the far right Q becomes the output data.