Error while simulating vhdl code for 4 bit counter in vivado 2015.2
Use the type system instead of fighting it.

Any time you see an uncomfortable double type conversion, especially to another type and immediately back again, like 

temp := std_logic_vector(unsigned(temp) + 1);


that is fighting the type system, and probably points to a more or less serious mistake in the design.

Instead, think about this:

You want to count - so your data is some form of number, not just a bag of bits.

What range do you want to count? That's not clear from your question, so I'll guess 0 to 15, eliminating negative numbers, covering the 4 bits of output data.

There are 2 obvious choices :

variable temp: natural range 0 to 15 := 0; 
variable temp: unsigned(3 downto 0) := "0000"; 


You are already using the correct numeric_std library for the latter.

Now there will be a suitable "+" operator visible.

What's missing so far is a connection to the output port y.

If you are forced by ridiculous coding standards or a huge existing project to keep all ports std_logic_vector you'll need a type conversion. 

y &lt;= std_logic_vector(temp); -- for unsigned temp
y &lt;= std_logic_vector(to_unsigned(temp,y'range)); -- for natural temp


If you are allowed to fix a broken design, consider what y means in the larger context : if it's an unsigned number such as a memory address, use the right type in the port declaration, then the simplest y &lt;= temp; is the correct approach.