How to obtain the (estimate) equivalent gate count for a FPGA design?
There really isn't one answer as there is so many different ways to instantiate a synthesizable design.

One way would be to use your synthesizable RTL and resynthesize it with another tool and target a different library.

For hand counting, you just need to look at your Mults, FFs and LUTs.  The slices are organization hierarchical blocks and taps are routing resources, neither should affect you gate count majority.

Mults and FFs are easy enough to account, for the main issue is going to be your LUTs as there is often way more capability embedded into a LUT than is used, or the LUTs are cascaded in a particular fashion to prevent a speed impact.  It will be more accurate to look at the logic cloud in your RTL map to the equivalent 2 input gate.