Depth of Xilinx FIFO Generator IP
You can easily cascade FIFOs. So the maximum FIFO depth is more determined by the amount of memory on the FPGA then maximum size of the IP. 

For very big FIFO depths you can add a DDR interface to the Xilinx** and use the DDR as FIFO. It requires an AXI DMA write and read channel each starting with a certain delay between them. 

**Or buy e.g. a Zynq which has a built-in DDR interface. 

Almost forgot: the FIFO depth as specified in the Xilinx IP are related to the data width. I think the maximum depth are for 8 bit wide data.