Forced beta too small
If you use a forced beta smaller than 10,will the transistor still be saturated succesfully?


Yes, if you design for a smaller forced beta than the datasheet recommends the transistor will still be saturated, but you're probably just wasting base current for nothing.

As an aside, saturating a power BJT and keeping it saturated is a bit complicated it you want to do it optimally. The initial base current needs to be higher than the maintenance saturation current for optimal results in terms of minimizing power loss on the transistor while entering and staying in saturation. Likewise when you turn it off, you can actively remove the base charge rather than wait for it to disappear by recombination alone.



(Image from these slides; you should probably watch the course video [or read the book] for more explanation on that.)


  If hFE is too small,can the BJT be damaged?


I'm not exactly sure what you mean by this... But it you drive it a base current that's too high (which can result by designing for a hfe too small) then yeah, you can burn the transistor.



Regarding the BC547C: here's an example of varying the base drive using the BC547C model that comes with LTspice; I chose some 120ohm load (at 12V) since you didn't specify it. The max collector current for BC547 is 100mA, so this is pushing it to the limit.

You want to pick R1 (the base resistor) so that the power dissipated on the transistor (green curve) is at a minimum when "ON". That means somewhere between 1K to 3K here. It doesn't matter that the hfe (red curve) is not 10 there.



Also note that if chose R1 so that hfe is 10, you may have slightly higher power dissipation; but the variation of power dissipation on the transistor over the entire saturation region isn't all that great. You can see that in a zoomed view of the saturation region:



To the left of the curve you can see how you could burn the transistor with a base resistor too small, even though hfe is small there too; the power dissipation is not because the dissipation over the base emitter region starts to dominate. To the far right, the transistor goes in the active region and its collector-emitter voltage drop starts to dominate the power dissipation over it.

Do not assume this simulation is necessarily optimal for Fairchild's transistor. They give no SPICE model, so you'd have to create your own from thei datasheet. Also this simulation is for static dissipation while ON, i.e. assuming you don't do fast switching.