Help me implement the crossroad traffic lights using multiplexers 4/1?
The multiplexers are being used as logic gates. In the case where just 1 or 0 is attached to the input, the multiplexers are essentially truth tables.

S1 and S0 are 2 bit binary selection inputs. For the case of the one on the top left,

C  |  D  |  Dec  |  Selected | Output
0  |  0  |   0   |    I0     |   0
0  |  1  |   1   |    I1     |   1
1  |  0  |   2   |    I2     |   1
1  |  1  |   3   |    I3     |   1


In that case, the mux is essentially acting like an OR gate.

The one below that will only pass a 1 if both S1 and S0 = 1, which makes it an AND gate.

The third multiplexer in that circuit is more complicated because its inputs can vary. You can still model it in terms of boolean logic, but it isn't as simple as the previous two. 

Here's a logic-gate representation of the left hand multiplexer circuit (please feel free to point out any mistakes).







simulate this circuit &ndash; Schematic created using CircuitLab