Select output from Generate in VHDL
You can describe it using a high-impedance output of your RAM. All RAMs, which are de-selected, output all 'Z' on the data signal. Only the selected RAM actually outputs the requested value. Then, the outputs of all RAMs can be connected together without creating a short-circuit. That means, all RAMs "write" to the same signal. Some tools can even synthesize it, by replacing the 3-state driver by appropriate logic gates of the target architecture if required (e.g. ISE 14.7).

Example design:

library ieee;
use ieee.std_logic_1164.all;

entity RAM is
  generic (
    CONTENT : std_logic_vector(7 downto 0));

  port (
    read_enable : in  std_logic;
    read_data   : out std_logic_vector(7 downto 0));
end entity RAM;

architecture rtl of RAM is
begin
  read_data &lt;= CONTENT when read_enable = '1' else (others =&gt; 'Z');
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is
  generic (
    N : positive);          -- number of RAMs

  port (
    read_enable : in  std_logic_vector(N-1 downto 0);
    read_data   : out std_logic_vector(7 downto 0));
end entity top;

architecture rtl of top is

begin  -- architecture rtl

  gRAMs: for i in 0 to N-1 generate
    RAM_inst: entity work.RAM
      generic map (
        CONTENT =&gt; std_logic_vector(to_unsigned(i, 8)))
      port map (
        read_enable =&gt; read_enable(i),
        read_data   =&gt; read_data);
  end generate gRAMs;

end architecture rtl;


If you simulate it using this testbench:

library ieee;
use ieee.std_logic_1164.all;

entity top_tb is
end entity top_tb;

architecture sim of top_tb is
  constant N : positive := 4;
  signal read_enable : std_logic_vector(N-1 downto 0) := (others =&gt; '0');
  signal read_data   : std_logic_vector(7 downto 0);

begin  -- architecture sim
  DUT: entity work.top
    generic map (
      N =&gt; N)
    port map (
      read_enable =&gt; read_enable,
      read_data   =&gt; read_data);

  Stimuli: process
  begin
    wait for 10 ns;
    for i in 0 to N-1 loop
      read_enable(i) &lt;= '1';
      wait for 10 ns;
      read_enable(i) &lt;= '0';
    end loop;
    wait;
  end process;
end architecture sim;


then you get the following result: