Change memory content of FPGA SoC (DE1-SoC) using software while .sof (EPCQ) is running on FPGA
Second answer as the comments are flowing off the page....

First find out how the memory is configured:


Address range on the bus
Data width
Byte enables?


Then the best solution is to simulate accessing your memory.
You may have a problem there. I have used mainly Xilinx but on e.g. the zynq system you have to fork out a decent amount of money to get a simulation model of the CPU system.

Alternative is to build yourself a bus access module!
That is a simple behavioral module that generates AXI read and write cycles. It does not have to do all possible AXI transfer: just the basic single beat read and write. 

If you plan to do any work with AXI it is time well spend as you can use it again and again. Other advantages:  


You don't have to spend hours working through a manual how to connect/use it.
You can expand it in in due time to make more complex cycles.


Disadvantage: It may not be 100% AXI compliant and at some time you will have to find out if the bug you are having is in the module or in the test-bench.

You might want to look at this webpage where there seems to be a free AXI bus model.