Syntax error near variable and range in VHDL
Stripping out the parts of your code that are not problematic, we have:

architecture Behavioral of top_module is
begin
  shared variable total_foul : integer range 0 to 5;
  begin
  if foul = '1'  then
  begin
    case total_foul is        
      when 1 =&gt; LED &lt;= "1001111"; -- "1" 
      when 2 =&gt; LED &lt;= "0010010"; -- "2" 
      when 3 =&gt; LED &lt;= "0000110"; -- "3" 
      when 4 =&gt; LED &lt;= "1001100"; -- "4" 
      when 5 =&gt; LED &lt;= "0100100"; -- "5" 
      when others =&gt; LED &lt;= "0000001"; -- "0" 

end Behavioral;


The first issue is your shared variable. These can only be declared in a declarative region, in this case, it looks like you wanted it in the architecture declarative region, which is before the first begin in the code above.

The next problem is your second begin statement. What was this supposed to do? It looks more like you wanted to start a process here.

There is a 3rd begin after the if foul = '1' line. Again, what is this meant to do? It does not match any valid code pattern, so I suggest you just get rid of it.

Your case statement starts off OK, but where is the matching end case;?

Going back to the if foul = '1' line, it has no matching end if;.



You need to go back and look at some examples of simple VHDL architectures, then carefully write code with these in mind. Per a comment, you should also avoid using a shared variable until you really understand why you are using this, and not a signal or variable.