Sampling data at 5MHz with 50Mhz clock in Verilog
You say you have a frequency divider. But that is just the beginning. Indeed you have to add a synchroniser for the serial input. I looked at the datasheet and you need an SPI interface without the transmit part. That means you also need a chip select, serial/parallel converter, . I am not going to write that for you (After all that is what I earn my money with) so I am going to give you the most important snippets:

  always @(posedge clk or negedge reset_n)
   begin
      if (!reset_n)
      begin
         ser_in_meta &lt;= 1'b0;
         ser_in_sync &lt;= 1'b0;     
      end
      else
      begin
         // Sync input on system clock 
         ser_in_meta &lt;= ser_in;
         ser_in_sync &lt;= ser_in_meta;
      end
   end

         // Divide by 10 counter
         if (clock_div==4'd9)
            clock_div &lt;= 4'd0;
         else
            clock_div &lt;= clock_div + 4'd1;

        // Symmetrical 1/10 system clock
        if (clock_div==4'd0)
           ser_clk &lt;= 1'b0;
        else
           if (clock_div==4'd4)
              ser_clk &lt;= 1'b1;

        if (sample)
        begin
           bit_count &lt;= bit_count + 5'h1;
           // Receive: MS bit arrives first 
           shift_in  &lt;= {shift_in[30:0],ser_in_sync};                    
        end        

   // pick up the data just before the falling clock edge 
   assign sample  = (clock_div==4'd9);


The Maxim datasheet says the data is changing max 40ns after the falling clock edge. So pick it up just before.