(System)Verilog: signal is x or 1 depending on placement of concurrent blocks in the code?
People misunderstand the simulation behavior of always blocks. It does not execute at every negedge. It is a process just like an initial block that executes procedural statements. It the same as if you wrote

initial begin
    nrst = 1'b0; 
    end
initial begin
  @(negedge nrst) // this means suspend the process and wait for a negedge
    signal = 1'b1;
 @(negedge nrst)
    signal = 1'b1;
  ... // repeats infinitely for an always block
   end


This is a race condition because the order that initial blocks start their processes determine if the assignment to nrst in one process is seen by the other process that suspends waiting for a negedge transition. A NBA assignment to nrst as well as moving the assignment after time 0 would solve this race.