Clock constraints for SDC file
Create_clock  [get_ports   CLK_100MHZ]  -name CLK_100MHZ -period 10 -waveform { 0 5 }
Create_clock [get_ports CLK_12MHZ] -name CLK_12MHZ -period 83.33 -waveform {0 41.66}
Create_generated_clock -name CG_GLA -source [get_clocks CLK_100MHZ] -divide_by 1 [get_pins BLOCK/ClockGen/GLA]
Create_generated_clock -name CLK_20MHZ -source [get_clocks CLK_100MHZ] -divide_by 5 [get_pins BLOCK/ClockGen/GLB]
Set_clock_groups -asyncrounous -group {CLK_100MHZ CG_GLA CLK_20MHZ} -group {CLK_12MHZ}