Signal voltage scaling
As a starting point, see Bruce Carter's application report titled Designing Gain and Offset in Thirty Seconds (Texas Instruments, document number SLOA097, Feb. 2002).

For what it's worth, if your power supply voltage is +5&nbsp;VDC, the task of designing a signal conditioning circuit whose output voltage is precisely 0&nbsp;V&nbsp;&ndash;&nbsp;5&nbsp;V is not a straightforward task. The reason is this: an op amp cannot output a voltage that is equal to the voltages at the op amp's power input pins. For example, for an op amp whose power pins are connected to +5&nbsp;VDC and ground, the op amp's output voltage range does not include +5&nbsp;VDC nor ground:

$$
0\,\mathrm{VDC} \lt V_{out} \lt +5\,\mathrm{VDC}
$$

So you might find it easier to design a signal conditioning circuit whose output voltage range is, for example, 0.2&nbsp;V&nbsp;&ndash;&nbsp;4.8&nbsp;V.

See also: 


Single-Supply Op Amp Design Techniques (Texas Instruments application report, document number SLOA030A, March 2001).
J. Heath, "Amplifiers: What do rail-to-rail and single supply mean?" Analog IC Tips: An EE World Online Resource, Oct. 10, 2017 [Online]. Available: https://www.analogictips.com/amplifiers-rail-to-rail-single-supply-mean/
J. Fischer, "Op Amp in buffer configuration is decreasing output voltage", Electrical Engineering Stack Exchange, June 19, 2016 [Online]. Available: https://electronics.stackexchange.com/a/241540/79842