STM32: avoiding DMA & CPU collisions
What this means is that if the DMA and CPU are both targeting RAM, depending on whose turn it is in the bus matrix scheduler, the CPU may be forced to wait for the DMA's turn to be finished. 

e.g. If the DMA is doing a ram-ram copy and the CPU is reading/writing to a peripheral register, then they are using two separate bus channels and no waiting happens. 

e.g. If the DMA is doing a ram-ram copy and the CPU is reading/writing to ram, then the Busmatrix arbitrates access to the ram. Sometimes DMA will wait, sometimes CPU will wait. 

See manual section 3.1 for the busmatrix stuff.

I don't think you'll be able to place your buffers in a memory where the CPU might not compete with the DMA.