Preventing Altium via stitching on the designators
This answer is twofold, answering these questions:

Can you do it?
Should you want to do it?


1. Can you do it?
You most probably can. In the Clearance Rules you can use the keyword &quot;IsStitchingVia&quot;, or the parameter line &quot;IsStitchingVia and InNet('{yourNetName}')&quot; for a specific net for the first object and for the second object you can use &quot;InLayer('{yourLayerName}')&quot; and all kinds of specific keywords to find component labels.
But I have never tested whether this works with Silkscreen specifically, since: See 2.

2. Should you want to do it?
No. You should want to keep the stitching as perfect as your design allows, because if you have a need for stitching, you have a need for it to be good and as complete as possible.
Want to make sure your designators are still readable over a via in your stitch? You have them filled and tented. Or very tiny and tented will also often fill them with solder mask automatically - whether filled and tented or tiny and tented is cheaper depends on your fab, but it's extremely likely tiny and tented is cheaper these days.

Appendix: How to tent stitched vias
To fully tent your vias, in the &quot;Add Stitching to Net&quot; menu click the check-marks in front of &quot;Force Complete tenting on Top&quot; and &quot;Force Complete tenting on Bottom&quot;. In Version 15 that's lower right, I seem to remember the same for 14, for 16 I don't know as I'm in a critical design and can't risk an update right now.
How to get the vias neatly filled is, as far as I know, asking the Fab what parameter to set and how, but to be honest, last design with Altium I had filled vias my colleague did that, making the last time I specifically requested them myself 2007, so I forgot. (It's possible he just phoned them to ask how small a via should be to guarantee it gets filled with solder mask when tented, to be honest)