Relative difficulty between leading zero counting and addition
For a 64-bit leading zero counter, what you'd need is at most a 6-NOR-deep combinatorial chain plus one XOR (or equivalent) ("is the first bit zero, and the second bit one", "are the previous bits zero, using the result from the previous step") and 6 bit LUT. 

That's very little.

A trivial ripple-block carry lookahead adder with 64 bit operands needs six stages, so it might be minimally faster, which is also very little.

In other words: I can't give you a definite answer; actual fast implementations will depend on the standard blocks that the hardware designer can employ: for example, on a modern high-performance FPGA, you'd either just use an arithmetic block (and not care about the design), or build it from 6-LUTs; so, these combinatorial considerations have no relevance to FPGA design. On an ASIC of an actual silicon CPU, neither components will be close to being the most complex things to do during a single clock cycle, and thus, more combinatorial steps in favor of e.g. lower routing overhead or lower switching probability might be favored.