Questions regarding BJT saturation for a circuit
It is difficult to make a single transistor work as a limiter unless there are limits on input signal range and frequency, so you need to define these limits.

But assuming they are only for the values given, we can make it better.  

When your input signal goes low Vbe turns off and the collect current shuts off and Vc is pulled up according the Rc value and ratios.

When your input goes high , collector goes low but it stays low more than half the time so the input is pulled up too much from negative feedback current.  

Solution?

1) Change bias of R2 from 0V to Vcc but with a value of 10x Rc or roughly 20k


Why? Vce(sat) is normally rated at Ic/Ib=10


2) Change R3 from 20x Rc to 50x Rc or ~ 100K
Change Rf 

When Vce saturates , its voltage Vce(sat) depends on the collector current as if there was a small series R, which we can call "Rce". This value controls the Vce(sat) and Rce is reduces as device power rating increases. Then it is affected by temperature and chip design so the default spec is Vce(sat) at some rated current.  Rce is similar to RdsOn in MOSFETs but not as low. You may estimate this as the rise of Vce(sat) for rise in current as long as base current is at least 5~10% of collector.

p.s.

Normally 2 devices working in differential mode give a better result then we move up to comparator designs or use a CMOS logic buffered inverter AC Coupled with high R feedback for self biasing for amazing simplicity. with large R values and much small C coupling values. like 10M and 0.1uF