Xilinx Place Error 1136 - This design contains a global buffer instance that is driving the following non-clock load pins
From ISE, under 'User Constraints', open 'I/O Pin Planning (PlanAhead) - Post-Synthesis'. This should open a schematic where you can follow the signal that drives the PLL reset around your design. Double click a net or component to show all elements that it connects to. Does this signal lead to any register clocks or latch gates? If so you should be able to see from the hierarchy which particular piece of code is causing clock inference.

My bet is that you have inadvertently created a latch by specifying an asynchronous load in one of your reset cases.