Basic Question : RC circuit why Vc node vary like this ?
I do not understand when the input Vn is varying like sinusoidal
  signal with a DC average, the Vc node is varying like the shown in
  Figure


When the switch is open circuit the voltage previously deposited on the capacitor remains at that level until the switch closes again. An open switch prevents charge leaving the capacitor.


  When switch is on, the Vc is suddenly according with the level of Vn,
  I mean, why it is like this ?


When the switch closes the capacitor rapidly charges (via R) to Vn - it has no option to do anything else.


  why the capacitor should not charge/discharge after comparing the Vc
  is lower/higher than the input voltage ?


I really can't understand this question - please rephrase


  The resistance why dont get any voltage distribution ?


There will be finite charge times and small errors in the accumulated voltage on the capacitor when the switch opens but this happens all the time in sample and hold circuits and the error is minimized by trying to reduce the value of R.