Can the same net-list file be used for ASIC design flow as well as FPGA design flow?
Assuming the same logic cells or library cells are available on both FPGA and custom ASIC process and the cells with the same functionality have the same name, then yes, you could use the netlist for either.

If only the cellnames are different you could do a search and replace to translate it.

But I do not expect this to be the case as FPGA library cells are usually more complex to offer more flexibility.

Custom ASIC libraries usually only include very basic logic cells in order to keep things small (in size) because as you know, size = money.

You could in theory make a translation library to use FPGA netlist on an ASIC. But creating a new netlist specifically for the ASIC library and the cells which it has available will usually result in a more efficient and smaller design as you get rid of the overhead which will always be there in a netlist for an FPGA.