MOSFET switching seeing unneccessary pulse during Power ON
A CPLD in reset mode may have leakage resistance and capacitance to Vdd if undefined as an input.  This can be shunted with a 1k resistor or higher or some capacitance to 0V (>1nF) to CLPD output.  

Alternatively the PFET gate can have some capacitance added from Vbat source to Gate but that depends on duration and RdsOn*C of NFET.

However I do not see any low voltage detect circuit to properly control this.