SPI: How does communication work with a device that has multiplexed SDO and SDI signals?
The Microchip device is made with separate MISO and MOSI pins (aka (probably) SDO and (probably) SDI respectively) as well as multiplexed MISO and MOSI pins.  It is always better to call these nets by MISO and MOSI as these names do not need to be reversed at the far end of the SPI bus.  A practice that leads to endless confusion.  

As for what the figures mean:

Figure 6-3 is for a Microchip device with separate MISO and MOSI pins.  Figure 6-5 is for a Microchip device with multiplexed MISO and MOSI pins.  Figure 6-7 is a feature where the master SPI device supplies an abbreviated (command which is only 8 bits long) SPI message to the slave SPI device (for turning up or down the potentiometer).  However as there is activity on what is labeled as the "SDO" line it would appear to apply to the Microchip device with separate MISO and MOSI pins.

As for how multiplexed SPI works:

The MCP41X1 is expected to back drive the MISO net when it needs to send data in the 2nd half of a SPI transaction.  That is, the MCP41X1 is expected to eclipse any MOSI net activity because the MOSI and MISO net are separated by R1.

As for choosing or not choosing multiplexing MISO &amp; MOSI style chips:

The MCP41X1 8 pin package allows access to both sides of the potentiometer as well as the wiper.  It offers this at the expense of multiplexing the MISO &amp; MOSI pins.

The MCP41X2 8 pin package allows for separate MISO &amp; MOSI pins.  It offers this by only offering one side of the potentiometer and the wiper.

(MOSI = Master Out Slave In)
(MISO = Master In Slave Out)