Problems with capture cis simulation
I am not sure how you simulated it, but to me, this is a normal expected result when applying a 40mVp sine to a 0.7V Vbe self-biased voltage with an exponential Ic vs Vbe.  So your transistor Vce is entering saturation (Vce&lt;0.3V) and gets a flat negative peak and reduced voltage gain in the other direction.

Two of  many ways to fix this :


Reduce input from 40mVp to between 1%~2% of Vbe to 7 mV, with expected lower output.
add an emitter resistor to linearize the input impedance such that  Rc/Re&lt; 2*hFE to reduce the exponential effects 


Re=25 Ohms will work, then the input can be increased up to 100mVp 
voltage gain must be less than half of  Rc/Re since you have a HPF with the same load R values as Rc.