Using DDR4 RAM instead of SRAM
DRAM (including DDR) requires the use of a memory controller, which takes care of the low-level details of timing, protocol and refresh management. The FPGA platform you're using likely includes configurable IP for this.
Your life will be easier if you use AXI or AXI-S internally to move your data, as these will be supported by blocks such as DMA and routing, as well as the memory controller you ultimately settle on. (Does not apply if you use Lattice, who, last I checked, only supported Wishbone.)