Crude LTSpice gate driver model of buck converter
You'd be surprised to find out that there currently are some very good behavioural models for various switching controller ICs and they reduce to just what you have there. Also, I see you've avoided the pitfall of setting extremely low/high on/off resistances for the switches. So this deserves a 'well done'. However, there can be some improvements.
There are duplicate .model cards for the switches, so you can trim down some lines. But the cards only include vt, which makes vh to default to zero, which means changing between Ron and Roff and vice-versa is done abruptly. These sudden changes are not very friendly convergent-wise, because the derivative around that point tends to get ugly, which can cause the simulator to cough &quot;timestep too small&quot; errors, or even slow down the simulation. The solution is simple enough: add hysteresis by setting vh&lt;0, which will cause the transition between on-off states to be done smoothly. A good choice is chosing vt to be half the input voltage, and vh=-vt. You could use level=2, too, but that requires the drive to be a bit tricky, so level=1 does it in this case. For the cases where the datasheet specifies a maximum current for the output driver, you can also set Ilimit, but for level=1 it's an abrupt limit, as oppsed to level=2, when it's better recommended. Just don't forget that the driving needs to be much higher (or vt and vh set lower) so that it can come close enough to &quot;saturation&quot;.
Another cause for discontinuity is the if() expression in B1 and B3. It could be mitigated if a current source (bi, bi2) would be used, with Rpar=1 Cpar=10p, for example. But it's also a bit of a waste since those two sources can be replaced by a single A-device, the [Digital]/buf, which has builtin complementary outputs, it's almost guaranteed to converge and, if set with tau=1n tripdt=1n, for example, can provide superior performance. You can also set vhigh and vlow, but if you're driving the switches, it doesn't matter, since then the defaults will be vhigh=1 vlow=0 and the VCSW can be set with vt=0.5 vh=-0.5. Also a bit of a waste is E1, particularly if you're using buf.
The diodes you used are the default, ideal ones, and they can be a bit quirky, but they can be improved by setting vfwd and vrev, together with the very convergent-friendly epsilon and revepsilon. For this case, .model d d ron=10m roff=10meg vfwd=0.45 vrev=1k epsilon=50m revepsilon=10m would do just fine. Don't forget to add anti-parallel diodes across the drivers, too.
One last minor thing: the source, V4, doesn't seem to have its parasitics set, which means it's a stiff voltage source with internal resistance zero, which makes C2 useless. Unless you set Rser for V4, but then, if you're at it, you can eliminate C2and add Cpar=22u to the source, too.
So, all in all, what you've done will do, and quite nicely, while also fitting the saying &quot;make things as simple as possible, but not simpler&quot;.