What adder does the use of the operator + synthesize to when used in creating an adder module?
Depends on the tool and the target architecture.
It will sometimes for example infer a DSP48 (Xilinx) but that is not a given and sometimes you will get something built in the fabric (Which generally has a semi dedicated carry chain up a column, so this is quicker then you might expect).
Why do you even care as long as it meets timing?
If you want a particular design (again, why?) you can build it explicitly as a mess of combinatorial logic but that will generally be slower then letting the tool figure it out.