Multiplex Sigma Delta ADC outputs (AD7401A)
Xilinx has a useful IOB input structure called IDDR / ISERDES. You can use this internally to demultiplex the signal.

Rather than switch every n samples, you could multiplex the data 2:1 at sample rate, and use both-edge or 2x rate input clocking to capture the multiplexed signals. Then your data would be at full rate for all 30 channels with no introduced skew between them.