Simulating iserdese2
As it stands CLKDIV is aligned with CLK.  If you delay it by 1/2 CLK, it would be aligned with the data.  If you put the delayed version into an additional ISERDES2 input and clock it along with the data, you could use the resulting pattern to determine the data phase with respect to CLKDIV.  You would keep slipping bits until the deserialized delayed CLKDIV is aligned such that you know the data is also aligned.  The actual aligned pattern depends on the relative phase shift between your delayed CLKDIV and the data, but the pattern would be a rotated version of 11110000.