Simulating process variations
The usual method for doing this is to use different model files for the transistors. The foundry should be able to supply SPICE models for the "corners of the envelope", which would include three variations of NMOS (fast, typical, slow) and three variations of PMOS (fast, typical, slow).

Combining the fast and slow models for the two types of transistors results in four corner cases. You need to simulate your design at all four corners to make sure it can be manufactured with high yield.