FPGA SDC timing constraints, understanding output delay
No, these constraints don't mean that OUT1 has to transit in that timing window. The output delay is modelling the delay between the output port and an external (imaginary) register.

Delay of the path through OUT1 can be thought as follows.

t_total_delay = t_clk-to-Q + t_comb_delay + t_output_delay - t_clk_skew


The maximum value of t_output_delay (1.4 ns) is simply used for setup time and the minimum value (1.0 ns) is used for hold time.

Let's think about setup time. OUT1 has to transit 1.4 ns before (or earlier) the falling edge of CLK2. Say your clock period is 10 ns and the source register is also negedge triggered. In case t_clk_skew is zero, t_clk-to-Q + t_comb_delay has to be lower than or equal to 8.6 ns (10-1.4) to be able to meet setup time.

For hold time, t_total_delay has to be greater than zero. The critical part here is the clock skew. If t_clk_skew is very small, it is very easy to meet hold time. Even only t_clk-to-Q is usually greater than library hold time, however we don't need library hold time here, because the path is not going to a real register.

If we want to consider that library hold time, we can set a smaller output delay. It is also very common to set a negative value to be on the safe side. For example:

set_output_delay -1.0 -clock_fall -clock CLK2 –min {OUT1}