Trick VHDL Synthesizer to synthesize despite no input signals
It looks like IPSLever has a syn_preserve attribute that can be set to prevent optimization to constant nets. Here is the example from the Lattice Synthesis Engine for ispLEVER Classic User Guide

library ieee;
use ieee.std_logic_1164.all;
entity simpledff is
    port (q : out std_logic_vector(7 downto 0);
        d : in std_logic_vector(7 downto 0);
        clk : in std_logic );
-- Turn on flip-flop preservation for the q output
attribute syn_preserve : boolean;
attribute syn_preserve of q : signal is true;
end simpledff;
architecture behavior of simpledff is
begin
    process(clk)
    begin
    if rising_edge(clk) then
        -- Notice the continual assignment of "11111111" to q.
        q &lt;= (others =&gt; '1');
    end if;
    end process;
end behavior;