Will using AND gate with clock signal cause timing issues?
It's a perfectly valid technique, but unless you're sure the signals are glitch-free you need to do a little extra in order to prevent glitches being treated as spurious clocks.

This page describes clock gating with latches, from which I have lifted these diagrams:





The latches should be the "transparent" type.

In general any signal which is an "enable" can be turned into a clock enable if you account for the effects on timing skew.

(I spent about a decade in a startup built around software for automatically managing clock gates and timing in VLSI design!)