Sources about the working of Intel's new 3D transistors
Short answer: Look at Analysis and Design of Tri-Gate MOSFET with 
High Dielectrics Gate:


  In any normal transistor the drain to source current is defined by the equation:
  
  $$
  I_{DS} = \left( \frac{W}{L} \right) \left( \frac{ \mu C_{ox}}{2} \right)
  \left[ 2(V_{GS} - V_{T})V_{DS} - {V_{DS}}^2 \right]
  $$
  
  The drain to source current in tri-gate transistor isp roportional to \$\dfrac{W+2H}{L}\$ ratio. Here H is the width of the transistor and drain to source current is given by the 
  equation:
  
  $$
  I_{DS} = \left( \frac{W + 2H}{L} \right) \left( \frac{ \mu C_{ox}}{2} \right)
  \left[ 2(V_{GS} - V_{T})V_{DS} - {V_{DS}}^2 \right]
  $$




The reason for 3D transistors, which are being studied under different forms, is to increase the interface between the Gate and the channel, without increasing the size of the gate.

The Gate is the terminal that drives the transistor on and off, and acts like a capacitance where charge is stored making the channel conductive. When the gate is charged, it creates an inversion layer between the Source and the Drain, where electrons can flow. This Layer though, is a superficial (you could say planar) area, because it decays exponentially with the distance from the gate.

Since conductivity is proportional to the trasversal section, and given a channel depth (determined by the gate voltage), designers can only work on the width of the channel, which is about the same of the gate width.

A common parameter used to evaluate the problem is the time constant RC: in CMOS technology, a (logical) gate with output resistance R has to switch the next one which has input capacitance C, so to make this fast, the RC product has to be small. As we said, you can halve R doubling the channel width, but doing this you also double C, and the gate before will take twice the time to flip it.

With 3D Gate, you basically "gain" a dimension for the channel, and you can adjust H and W to increase the channel conductivity without proportionally scaling the gate capacitance. Another advantage is that you don't increase the transistor area, which is a significant factor in device cost.

I'm pretty sure that the device works in the same (conceptual) way, just with better performance (but I would say the same leakage), but I can't give you the technical details, and I think nobody can, because it must be a VERY protected technology.

On Wiki there is some more literature about the topic. And in the references, you can find this, where it's stated:


  Why is the 3D design better?
  
  this continued miniaturization has an attendant problem: as the transistor's source and drain get closer together, and as the channel gets smaller, it becomes harder for the gate to control the formation of the inversion layer. Simply put, the distinction between 'off' and 'on' becomes fuzzier.
  
  Having a 3D structure solves this problem. Because it is in contact with three sides of the channel, the gate has much greater control over the inversion layer. This means that the on and off states are more distinct even when the transistor is shrunk.
  
  Did Intel invent the 3D transistor?
  
  The Tri-Gate design is essentially a variant of a 'FinFET' 3D structure developed in the late 1990s by Chenming Hu and his colleagues at the University of California, Berkeley. Other chip manufacturers such as IBM, Samsung and TSMC are all working on 3D designs, but are not expected to put them into production until at least the next generation of miniaturization, after 22 nanometres.