What do latching operation mean?
In (digital) electronics latching means that the signal "locked" in a certain state (zero or one) unless a clock or other control signal allows it to change.

So for the 8255A the inputs are not latched, this means that the chip will respond immediately (I'm ignoring the effect of delays which are always present) to any change at the inputs.

The 8255A's outputs are latched so that means they will only change when a certain control signal "says so". Look at the datasheet of the 8255A on the first page there's this drawing:



Note how there's a signal from the "Read Write Control Logic" (bottom left)
going to all the Group ports on the right. I bet that that is the latching signal for the outputs.

In general it is convenient to have signals in digital logic only change at the transitions of the clock. Any signal which does not meet this requirement already can be latched (with the clock) and then it will meet this requirement.