In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?
The circuit you cited is a ripple counter, not a synchronous counter. It actually has eleven states, 0000 through 1010, but as soon as the last state is reached, the NAND gate immediately (asychronously) resets the flip-flops to the 0000 state.

In a synchronous counter, all of the flip-flops would share a common clock, and you'd control the sequence of states by driving their J and K inputs. This would require a few additional gates, which would include decoding the 1001 state so that the counter goes directly to the 0000 state on the next clock edge.