For SR timing diagrams, does a bubble on the output of Q' indicate that it is the same as Q?
A bubble on an input or output means 'inverted'.

That is why an inverter is shown as a buffer symbol (no logic state change) with a bubble on its output (then inverted).

The '>' on an input means that is it positive-edge triggered. It will react only to a LOW-to-HIGH transition.

An input with a bubble followed by '>' is negative-edge triggered. The logic gate inverts the input then looks for a positive edge transition. Therefore the gate input will react only to a HIGH-to-LOW transition.

To your example...

You have a negative-edge triggered SR flip-flop with complementary outputs. Your Q output will obey the Set/Reset (SR) function of the gate.

Your Q' output will always be driven with the inverse of the Q output. Its name is has an apostrophe to denote that it isn't Q. The symbol shows that it is inverted. The name and symbol are indicating the single inversion in different places.