Flip-flop feedback timing problem
It means that the input to flip flop must be stable for some amount of time before (setup time) and after (hold time) the clock edge. If the input is changing when there is a clock edge, it cannot sample it reliably as logic 1 or logic 0, and depending on what kind of paths the clock and data propagates inside the flip flop, there might be a short glitch on the output, or the inverting and non-inverting outputs could output same data while they should output complementary data.
The output of the flip flop will update to new state only after some propagation time, so if there is a feedback from flip flop output back to input, it means that the clock edges must not happen too rapidly, so that the output has been stable for enough time to satisfy the input setup time, and the flip flop output must not change too early to satisfy the input hold time as well.