Pull down resistor on logic gate input
The behavior you are seeing is because unlike the high impedance inputs found on CMOS (74HC/CD4k/...) parts, the LSTTL (74LS) input structure, like that of all TTL gates, actually sources current when pulled LOW and sinks current when pulled HIGH (your datasheet will have IIL and IIH values for this).  This makes pullup and pulldown resistor values much more important than they are in CMOS to avoid exceeding the VIL or VIH of the gate and putting it into an indeterminate state.
In general, 1-2kOhm is the maximum used in TTL work (vs CMOS, which can tolerate pull-up resistors in the Megohm range if low power consumption is desired).