Memory Mapped IO and IO Mapped IO
In memory mapped I/O the I/O register is selected at a memory address. To the CPU it looks just like a regular memory location. The advantage of this scheme is that no special instructions are required to perform I/O operations. Disadvantages are that the I/O registers take up space that could otherwise be used for RAM or ROM, and a lot of gates are required to fully decode the small address range required by the I/O registers (or if the addresses are not fully decoded, an even larger 'hole' is created in the memory map). 

In the example circuit below the decoder has a 'granularity' of 16k, so the single I/O register uses up 16k of memory space.  







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'I/O mapped' I/O uses a separate address space that is accessed by dedicated I/O instructions. The data and address lines may be shared with memory devices, but the control bus generates a separate enable signal for memory or I/O depending on the type of instruction. Advantages are that I/O doesn't use up memory space, and minimal decoding is needed to select individual registers. The address range can also be smaller (eg. 5 bits to access 32 registers) allowing to it to be embedded into the I/O instruction for faster execution. Disadvantages are the extra control signal line using up a pin on the CPU, and the dedicated I/O instructions using up opcodes that could otherwise be used for other purposes.

Here's an example implementation. In this circuit the I/O register is enabled via the I/O request signal from the CPU, so it doesn't conflict with memory even though it has no address decoding (if more ports were added then a separate decoder would be provided to decode the I/O addresses). 







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A classic example of memory mapped vs dedicated I/O is the 6502 vs Z80. The 6502 has 64k of address space selected with 16 address lines. If you want I/O (and who doesn't?) then you can't have 64k of RAM and/or ROM. Since RAM and ROM chips usually come in large sizes, one of them may have to be switched out at certain memory locations to insert the few I/O registers you need, which makes the address decoder quite complex.

The Z80 also has 64k of address space with 16 address lines, but has two enable signals - one for memory (/MREQ) and one for I/O (/IORQ). You can install a full 64k of RAM and/or ROM, plus another 64k of I/O registers. Some I/O instructions have an 8 bit address embedded in them which is put on the lower 8 address lines to select up to 256 I/O ports, while others use the BC register to send the full 64k address. In a low-end system the I/O addresses can be partially decoded by simply ORing one address line with the /IORQ line, providing select signals for up to 8 I/O devices without a decoder chip.