Xilinx Virtex 6 Board - ISE gives error [Design Contains no instances]
The problem to the question raised by me was actually an error in the connection of the output port in my case [can also be any i/o port]

Thus in the instantiated module there was a connection made by wire using verilog coding in the top level file but in the module itself that output was not assigned any value.

And since these outputs were supposed to be an input in another instantiated module, Xilinx ISE considered it to be unconnected thereby, during the optimization step these modules were removed, leaving the design with no instances.