what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?
The problem was solved by the FPGA vendors realizing that this was an important thing to be able to do, and they began incorporating the necessary hardware into every I/O pad's logic. The key element is a programmable delay line, and the vendor's memory controller IP includes the logic to calibrate the delays automatically.
For example, look at Xilinx UG388, &quot;Spartan-6 FPGA Memory Controller User Guide&quot;, Chapter 4, &quot;MCB Operation&quot;, where it talks about the startup sequence and self-calibration. The key element is called IDELAY. You can learn more about this primitive in UG381, &quot;Spartan-6 FPGA SelectIO Resources User Guide&quot;, p. 70, &quot;I/O Delay Overview&quot;.