Altera Quartus detects 2 CPLD devices instead of 1
Your main issue is that you are running your JTAG header at the wrong voltage. Your VCCIO pins are connected to 3.3V, which means the JTAG signalling level is set to 3.3V
However, on your JTAG header, you have fed 1.8V to the VCCTrgt pin, which means that the JTAG programmer is trying to run at 1.8V. The signals are therefore getting corrupted because the programmer cannot drive the TDI, TMS nor TCK lines to a sufficient logic level for the Max V to read them.
Routing 3.3V to the VCCTrgt pin should largely solve the problem.
Furthermore, per the pin configuraiton guidelines for the Max V, you are missing necessary resistors on the JTAG lines. The TCK needs a 1k pull down to GND. TMS and TDI need 10k pull ups to VCCIO1.