Common way of describing a "double-sided wait"
One example of such a bus is the AXI bus, which originated with the ARM processor, but is increasingly being used as a standard interface for FPGA IP in general.

The two handshake signals are called TREADY and TVALID, and transfers only occur when both signals are asserted.

I don't know if there is a "standard" name for this protocol. On occasion, I have referred to it as "ready-enable" protocol in my own designs.



The more generic concept is "flow control", and there are many protocols that are used to implement flow control in various circumstances. The IEEE1284 printer protocol that somebody mentioned is an example of a 2-wire, 4-edge handshake that is often used for asynchronous communication at slower speeds. I have occasionally used such a protocol to transfer low-bandwidth data between clock domains inside an FPGA.

For higher-bandwidth transfers among clock domains, an asynchronous FIFO is often used, and its full/empty status signals become the flow control signals to the logic on both sides &mdash; and this is a very close fit with the TVALID/TREADY protocol of the AXI bus.