When should I change a logic level and how long should I hold it?
Logic analyzer (as shown) clearly samples/interprets data on the falling edge of CLK. However, LPC specs never mention clock edge, only refers as "first clock", "second clock", etc. How silly. But again, Figures 5 and 6 in LPC specs suggest that data bus changes around rising edge, and sampling (data evaluation) goes on falling edges. 



There is no timing presented the the entire LPC specs, only a reference to PCI spec 2.3. 

Given these uncertainties, the programmer still looks logically/formally correct, but I suspect that the logic analyzer gets confused with the long delay between LAD to pos-edge_CLK. You might need to tweak the logic analyzer sampling conditions or rates.