Sequence of capacitor's charge and discharge in voltage quadrupler
Your operational cycle definition is the simplified model which is used to understand how the final state of multipliers ends up at the voltages they do. 


Source

In reality, as you imagine, while ramping up it is not that simple and takes more than a few cycles to reach the final charge state.


  On first positive half cycle, can induced voltage VM charged on capacitor C3 or C2 instead?


No.... or rather, only a little. Because D1 is on, the applied voltage across the C2-D3-C3 path is limited to D1's forward voltage. As such, though some current will flow through C2 and C3, it is not much.

Re the second half cycle: Note in your description you mentioned ..


  On first negative (–) half cycle, C1 is discharged, and together with induced voltage provide C2=2VM.


This is where the simplified model breaks down. Since C1 is discharging during the charging of C2, the final voltage on C2 with not reach 2VM on the first cycle. It will be closer to 1.5VM. On subsequent cycles C2 will top up the 2VM.

With no losses at each cycle the voltage on C2 will be...
 (1+1/2)Vm, (1 + 3/4)Vm, (1 + 7/8)Vm, (1 + 15/16) Vm.... ad. infinitum 

The remainder of the multiplier is just more of the same.. and each capacitor charges up at a slower and slower rate due to the discharging effects.

Note in a real multiplier there are also losses due to leakage and circuit resistances. As such there is a limit to how far this circuit can be extended. Eventually the amount you charge each cycle approaches than the capacitors intrinsic leakage rate. The circuit will not gain any voltage past that point.