HDMI clock negotiation
HDMI is a point to point link as far as the video data is concerned, about the only thing that normally goes back the other way is EDID and some stuff having to do with HDCP. 
Generally the nearest thing to clock negotiation is the EDID data but that will not do what you need. 

The usual approach to this is a FPGA with enough IO to handle the video. The FPGA will also need some SDRAM for a frame buffer and usually one of the (typically) SiLabs clock generators to get the appropriate line rates for the various modes.     

This suffices for clean switching and even scaling, but to avoid any dropped frames if doing mixing you need house sync to ensure the frame rate of the two sources are locked. 

The ADV7511 and friends are the easy way to generate the HDMI output, for all that some FPGAs can do TMDS as an IO standard, the general purpose IO pins usually top out at 1.2Gb/s however, so one of the special purpose encoder chips is still probably the way to play, especially if you want HDMI 2.0.

Analog Devices also do HDMI RX chipsets that will give you a parallel bus at reasonable sorts of speeds from a HDMI port that are probably cost effective in that they remove the need for high speed serdes on the FPGA. 

Be prepared for serious NDAs and licensing fees if you want to play with the HDCP stuff.