Calculation of the capacitor value across the base and emitter to avoid unexpected turn ON of transistor
From reading the question, and the operating condition of high dV/dT of collector_base voltage, you seek to understand the value of a capacitive voltage divider.
Ok
With rapid dV/dT across the Cap_ColBase (1.5pF, for example), the charging current needs to be absorbed somewhere, and NOT flow into the base_emitter region of the transistor.
I'd plan to add a large enough cap across emitter_base to hold the delta_V_BE to less than 0.1 volts, or perhaps even 0.05 volts.
Assume 1.5pF needs to be charged as the collector voltage quickly changes by 24 volts, and we want to hold the base_emitter voltage change to 0.05 volts, the ratio is

24volts / 0.05 volts = 24 * 20 = 480X.

Thus we should consider adding 1.5 pF * 480 == 480 + 240 = 720 pF.
For design margin, use at least 1,000 pF.
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Another way is to actively clamp the base_emitter voltage to near zero.
This requires a low R_out driver.
If the 24 volts transitions in 24 nanoSeconds, the peak current is

I = C * dV/dT = 1.5pF * 24volt/24nS = 1.5e-12 * 1e+9 volts per second.

or

I = 1.5 milliAmps

And we need to hold the change in base_emitter voltage to less than 0.05 volts
Thus the output resistance (incremental resistance) of the base_driver circuit  needs to be less than

R_incremental = V / I = 0.05v / 1.5mA = 0.05 / 0.0015 = 5/0.15 = 35 ohms

And you need a design (safety) margin, to be provided under ALL conditions.
I'd plan on 10 ohms, or less.