VHDL coding for FSM not compiling?
First, on line 9 and 34, your use start, but in the rest of the code it is used as start_H.

Second, see https://stackoverflow.com/questions/8109078/addition-in-vhdl-not-compiling for solutions to your + operator not found error on line 43.

Third, you need to make sure that both s_counter and clock_delay_12 are the same type so that you can compare them on line 44. Exactly what type will depend on your solution the + operator not found.

Fourth, line 46, ''0' is of type std_logic, s_counter is of type std_logic_vector(3 downto 0), so you would use "0000" instead. You could also use something like (others =&gt; '0')

There may also be other errors, but this as far as I got.

I also have some style comments.

On line 29, I would use rising_edge(clk_H) instead of clk_H'event and clk_H = '1'. 

Your if statements don't need extra parentheses. 

Like Brian Drummond said in a comment, I would avoid using the 2-process state machine, I prefer the 1-process form.