Data Flow level Programming in Verilog
Your code has many, many problems. Balancing parentheses is among the least of them.

First of all, an if statement can only appear in the body of a behavioral (always) statement/block. This is the cause of the error message you listed.

Secondly, module input ports can't be integers, which is what you seem to be assuming. Multi-bit values need to be given explicit widths.

There are also many other syntax, logic and style issues, too numerous to get into. Try the following code instead.

module LeapYear (year, month, leapOrNot, Days);

input [15:0] year;    // 0-65535
input  [3:0] month;   // 1-12

output leapOrNot;
reg    leapOrNot;

output Days;
reg    Days;

always @* begin
  if ((year % 400) == 0 &amp;&amp; (year % 100) != 0 &amp;&amp; (year % 4) == 0) begin
    leapOrNot &lt;= 1;
  end else begin
    leapOrNot &lt;= 0;
  end
end

always @* begin
  if (month==2) begin
    if (leapOrNot==1) begin
      Days &lt;= 29;
    end else begin
      Days &lt;= 28;
    end
  end else if (month==4 || month==6 || month==9 || month==11) begin
    Days &lt;= 30;
  end else begin
    Days &lt;= 31;
  end
end

endmodule