Leading edge blanking does not depends on primary leakage inductance?
The leading-edge blanking circuitry or LEB is a common circuit found in modern switching power supplies. It is usually built as shown in the below circuit:



When the drive goes high, a short pulse of \$t_{LEB}\$ duration blinds the IC for a small period of time. We are talking about 250-350 ns for ac-dc controllers operating below 100 kHz and around 100-150 ns for high-frequency controllers. This is to prevent the controller from being reset by a current peak happening at the switch closing time:



This peak is contributed by:


the MOSFET gate capacitance current which circulates through the sense resistance when the drive goes high
the sudden discharge of the total capacitance lumped at the drain. This capacitance is made by the MOSFET capacitance seen at its drain (\$C_{rss}\$ and \$C_{oss}\$), the transformer capacitance and the output diode capacitance.
if the converter operates in heavy CCM, then the reverse recovery current (the diode is a short circuit for a small moment of time, half the \$t_{rr}\$) is seen in the primary side as a peak.


The LEB can sometimes be too short and an extra \$RC\$ network needs to be added. I recommend to always include it in designs, with \$R_2\$ and \$C_1\$ very closely located to the control IC and its ground. It will improve noise immunity and attenuate any unwanted negative ringing which can be highly detrimental to a sound operation.