FPGA power usage estimate
In one of my recent project, I worked on a FPGA/ASIC running 10GHz SERDES. Our board comprised of 10 power supplies with various voltage and current requirements. It would be a good estimate to keep the current requirement double than the required unless board space is a constraint. 

More attention needs to be paid on the ripple than any other factor in power supply. Noise plays a big factor on FPGA power supplies. Make sure you put enough ground plane layers to minimize noise. I have seen FPGA boards not working due to noise.

For noise insensitive rails, you can use LTC DC-DC power modules. They deliver a lot of current in a small package.

For noise sensitive rails like SERDES IO, a LDO with low ripple should be used along with a suitable DC-DC module in the back-end. Check your FPGA datasheet for ripple tolerance on different rails.