Will an SPI EEPROM chip have the same issues with non-atomic write operations as a dsPIC's internal EEPROM?
The chip cannot guarantee atomic writes - if the power goes away while it is writing (or erasing), there's nothing it can do about it.

Of course, the chip designers could implement some kind of holding store (as you have done) - but that adds cost that other users won't want to pay.  Also, what happens if the power goes down whilst writing to the buffer instead of the "real" memory?