Is DRAM burst mode compatible with bank interleaving?
First part: No, what you have described is in fact "fast page mode" and not burst mode. This mode only applies to old-fashioned non-synchronous DRAMs (and not all of them supported it), which don't have internal banks, and not to any kind of modern SDRAM.

Second part: Yes, it is possible to interleave burst accesses to multiple banks within an SDRAM chip, and in fact, this allows you to get close to 100% utilization of the data bus. All of the overhead of initiating an access to one bank can be hidden by the data transfers occurring on other banks. I do this all the time when building frame buffers for video processing.

Don't worry about the fact that the data is "non-adjacent" &mdash; that's just a matter of how you assign the address bits. There's nothing that requires data that the CPU thinks is "adjacent" in its address space to be physically adjacent in the memory chips. Think of it like striping in a RAID array &mdash; a block of 256 data words can be split up into four 64-word blocks, each one written to a different bank.