Verilog: Escape non-printable characters in string initialisation
The section you quoted refers to identifiers, so you can have a named item with non-word characters in:

reg [6 * 8 - 1:0] \test"string = {"Hello",8'h01};


Yes, that's a legal identifier; don't do that unless you have to, though. That snippet also shows how a Verilogy way of embedding non-ascii in strings with concatenation.

A little experimentation shows that \xnn doesn't work but \nnn (octal) does. This may be tool-dependant.