Concurrent assignment or output port connection should be a net type
You cannot drive a reg type via a continuous assignment (only a wire may be driven in this way). 

If this is just modelling combinatorial logic, you could use a combinatorial always block:

always @* begin
    mem[in_d0_] = in_d1_;
end


However, this doesn't seem to make much sense to me for writing to a memory module, which is usually something that is written on a clock edge. Perhaps you want to make this a clocked block:

always @(posedge clk)
    mem[in_d0_] = in_d1_;
end