Radix-4 Booth's Multiplier verilog code error
You can't keep both the indices of the range a variable, while indexing an array in Verilog. At least one index has to be a constant for the Synthesiser to be able to resolve the expression.
Verilog has a standard syntax to address your intention:
acc [count +: 3]

This is called part-selecting, where 3 signifies no. of bits of acc being addressed, and the lower index of the range is count.
For eg: if count is 4, then acc [count +: 3] means acc [6 : 4]