What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog
You didn't give us the details on how your memory works, but a general approach is to replace all that fork/join code with Verilog task's and task calls:
initial begin  
   Enable = 0; 
   DataIn = 4'b0000;

    #10 ReadWrite = 0;

    // Write specific data to specific addresses
    write(6'h00, 4'b1101);
    write(6'h01, 4'b1010);

    // Write random data to random addresses
    repeat (10) begin
        write($random, $random);
    end
end

task write (input [5:0] addr, [3:0] din);
    #20 Address = addr; 
    #1 Enable = 0; 
    #2 Enable = 1; 
    DataIn = din;
endtask

task read (input [5:0] addr, [3:0] dexpect);
    #20 Address = addr; 
    #1 Enable = 0; 
    #2 Enable = 1; 
    if (DataOut !== dexpect) $display(&quot;Error addr=%h dout=%h&quot;, addr, DataOut);
endtask