Weird reset problem in FPGA Design
Your circut appears out of sync after reset. You must review synchronization techniques you use, and protocol you use (start/stop and other control bits).

If you carefully look at the correct and incorrect output, you will see that in correct output you have 50 - characters, in incorrect you have about 50 j characters

- code is 2d = 0010 1101

j code is 6a = 0110 1010

You can see that bitstream is the same, just shifted 3 bits left.