What is the difference in VHDL between multiple architectures and multiple generate statements within one architecture?
It all comes down to the modularity and the reuse of your code. In the first case you decision is taken on the top file which in the future, in order for it to be modified, one must know the architectures of the instantiated entity and choose between them (note that in this case you are not limited just to two architecture but you can expand new architecture in the future). In the second case you are limited to max of two architecture but the top file needs to set one generic. In this case you cannot expand as easily as before, since you would need multiple generics for more architectures and usage of asserts to avoid more than one generic is set..., so i don't see it as a very good practice.