4 layer board back bypass capacitor power plane connection guideline reason
It is because in the second case the current travels down each via in OPPOSITE directions. Assuming that:


the vias are placed right beside each other, and...
that the currents are equal (i.e. the capacitor is only decoupling only that component pin and the component pin is only being decoupled by that capacitor), 


then the magnetic fields generated by each current would be equal and opposite, mostly cancelling each other out thereby reducing the effective inductance.

Now that I've said that, note that this is also the case for the long vias in the first example. The take-away here is the cancelling magnetic fields of the currents in the long vias (which would otherwise have higher inductance) is not unique to widely spaced power plane PCBs. The inductance due longer traces in the the horizontal distance is true for any board, not just wide spaced planes so that's not what the book is trying to communicate to you.

You get a similar effect by placing the two vias going to the power and ground plane for a decoupling capacitor on its side (so that they are closer together) rather than its ends.  That's interesting. I've never thought it in terms of the vias between two separate components, just for a single component.

See:
Decoupling cap routing on a 4 layer PCB

That's interesting. I've never thought about it in terms of vias between two components. Only ever between one component.