What is the theoretical throughput limit of DDR SDRAM read only
If your DDR SDRAM has multiple banks, it is often possible to interleave the bank burst transfers in such a way that all of the other overhead is "hidden". And if you're accessing memory sequentially anyway, you can sometimes even forget about separate refresh cycles. This means that you can sustain the raw (peak) bandwidth of the data bus more or less indefinitely.

I work with high-bandwidth video systems, and we do this sort of thing all the time, for external frame buffers attached to FPGAs.

Implementing a DDR SDRAM controller that's sophisticated enough to interleave bank accesses is rather tricky &mdash; we nearly always use the FPGA vendor's IP for the physical memory controller, and then add our own multi-port access multiplexer on top of that.