VHDL test bench for input port assignment
To your question why p3 is not set at 0ns:
Your process in testIO is assigning values at the rising_edge of clk. What do you have at 0ns? No rising edge. So it's undefined what p3 is at the beginning. Look up some vhdl samples and have a look for reset behaviour.

If you look at testIO:


You check if r0 = '1' => T0 &lt;= p3
You check if sel_line = '1' and r0 = '0' => p3 &lt;= ip else p3 &lt;= 'Z'
You check if sel_line = '0' and r0 = '0' => op &lt;= p3 else p3 &lt;= 'Z'


You see what happens here? You assign p3 in multiple paths at the same time. Look at your compiler messages.

So... I would recommend you, to make a truth table and create your logic based on this. You can assign your p3 with one if elsif else statement and not with multiple if else statements to prevent missbehaviour.