How do I make use of multipliers to generate a simple adder?
Use the Altera "Technology Map Viewer" if you want to see exactly how/where those 24 elements are being inferred.

I'm not certain what technology you targeted. For a StratixV it uses 16 regs and 1 DSP slice  and if you need it you'll get the next register stage for free from the mux output.

RTL Viewer



Technology/resource view


You can see the logic elements are used one per bit for the output mux and one per bit for the adder, with the DSP cell highlighted.

You might be able to pack the whole thing into a single SV DSP cell using the various mode bits (pre adders for a/b, set mult stage to x1) to avoid the output mux, but the whole thing is moot on that kind of device!