Why does Camera Serial Interface (CSI-2) have multiple data lanes?
In a parallel bus, each bit of a single data unit is passed on a separate wire and all wires change (source) simultaneously and are taken (destination) simultaneously.
Parallel data transfer happens under control of separate handshaking wires, such as a sync clock with data valid(s), an async write strobe, an async read enable and so on.
Example data units are bytes (8 bits) and dwords (32 bits). 'Simultaneously' means within some defined timing limits.
In a serial interface, each bit of a single data unit is passed on a single wire one after the other.
The serial data unit is modified before transmission, just for the trip across the wires so the receiver can identify the data. The serial receiver will later modify the data back to the original. Examples are UART START/STOP/idle bits, PCIe v1.0 8b/10b encoding, 128b/132b.
In a multi-lane serial interface, each lane is carrying its own data units with its own timing. The data units are received and checked independently then recombined into a single, faster data stream. If fewer lanes are available the link works, just slower.
This is simplistic and general and there's more subtleties and variants in all this. But it gives you some definitions and differences.