Is port map (A => (others => x)) legal in VHDL 2008?
Prior to VHDL-2008:
You cannot perform such action : A =&gt; (others =&gt; x) because this line is seen as an operation and that is not possible in an instantiation.

(like in this post for example: Warning : Actual for formal port a is neither a static name nor a globally static expression)

However, there is a way to work around that, you have to create a new signal y :

library ieee;
use ieee.std_logic_1164.all;

entity dummy is
    generic (
        LENGTH : natural);
    port (
        --A : in std_logic_vector (LENGTH - 1 downto 0); -- #2a
        A : in std_logic_vector (3 downto 0); -- #2b
        Q : out std_logic);
end entity;

architecture rtl of dummy is
begin
    Q &lt;= '0';
end architecture;


library ieee;
use ieee.std_logic_1164.all;

entity modelsim_others_bug_testbench is
end modelsim_others_bug_testbench;

architecture rtl of modelsim_others_bug_testbench is 
    signal   x  : std_logic;
    signal   y  : std_logic_vector(3 downto 0); --New signals
begin

    x &lt;= '1';
    y &lt;= (others =&gt; x);

    dummy_i: entity work.dummy(rtl)
        generic map (
            LENGTH =&gt; 4)
        port map (
            --A =&gt; (others =&gt; x),   -- #1a Does not work
            --A =&gt; (others =&gt; '0'), -- #1b Works
            A =&gt; y,                 -- #1c Works
            Q =&gt; open);

end architecture;


Notice that when copy/pasting your code on Vivado, the error is: Actual for formal port a is neither a static name nor a globally static expression

I let you modify your code so that you can use the generic LENGTH.

With VHDL-2008:

If look in the norm: http://www.fis.agh.edu.pl/~skoczen/hdl/ieee_std/ieee1076-2008.pdf
You can find on paragraph 6.5.6.3 Port clauses:


  If a formal port of mode in is associated with an expression that is not globally static (see 9.4.1) and the
  formal is of an unconstrained or partially constrained composite type requiring determination of index
  ranges from the actual according to the rules of 5.3.2.2, then the expression shall be one of the following:
  
  
  The name of an object whose subtype is globally static
  An indexed name whose prefix is one of the members of this list
  A slice name whose prefix is one of the members of this list and whose discrete range is a globally static discrete range
  An aggregate, provided all choices are locally static and all expressions in element associations are expressions described in this list
  A function call whose return type mark denotes a globally static subtype
  A qualified expression or type conversion whose type mark denotes a globally static subtype
  An expression described in this list and enclosed in parentheses
  


In other word, in VHDL-2008, the code you provided works (I have no error using it with Vivado 2018.1, simulation works as expected)