Memory scheduling in FPGA
Why does the first filter not output all of the pixels? It should. You just need to figure out what it needs to produce for the "edge" pixels.

In my video processing designs, I have a separate module that I call a "kernel generator" that sits between the line buffers and the actual filter. It reads the line buffers and outputs the nine input pixels (in parallel) that need to be operated on for any particular output pixel. At the edges of the frame, it produces replicated pixels to replace the ones that would be "off the edge" in the input frame.

What it does at the edges is somewhat application-dependent, but in most cases, it works well to "reflect" the data at the edge of the image. In other words, when you're working on the first row of the image, the missing input data (for the "zeroth" row) is filled in by using data from the second row. The same logic is used at the left, right and bottom edges.

This way, the output of any filter stage has the same number of pixels as its input, and "edge effects" are minimized.