VHDL - big difference in schematics between integer with and without range
As  Marcus Müller pointed out, the compiler can ignore all logic as if((x+y) / 49 > 200) will never render true with the limited integers. I have made a new test with some logic that the compiler has to respect:

Example A V2:

entity PipelinePoc is
    Port ( clk : in STD_LOGIC;
           led : out std_logic_vector(0 downto 0)
           );
end PipelinePoc;

architecture Behavioral of PipelinePoc is

begin
process(clk) is
variable x : integer;
variable y : integer;   
begin

if rising_edge(clk) then
    -- STEP 0: Adjust pixel if overflow
    if(x = 299)
    then
        x := 0;
        if(y &gt;= 500)
        then
            y := 0;
        else
            y := y + 1;
        end if;
    else
        x := x + 1;
    end if;
    if((x+y) = 70)
    then
        led(0) &lt;= '1';
    else
        led(0) &lt;= '0';
    end if;

end if;
end process;
end Behavioral;


Schematics for A v2:



Example B V2:

entity PipelinePoc is
    Port ( clk : in STD_LOGIC;
           led : out std_logic_vector(0 downto 0)
           );
end PipelinePoc;

architecture Behavioral of PipelinePoc is

begin
process(clk) is
variable x : integer range 0 to 1280;
variable y : integer range 0 to 1280;   
begin

if rising_edge(clk) then
    -- STEP 0: Adjust pixel if overflow
    if(x = 299)
    then
        x := 0;
        if(y &gt;= 500)
        then
            y := 0;
        else
            y := y + 1;
        end if;
    else
        x := x + 1;
    end if;
    if((x+y) = 70)
    then
        led(0) &lt;= '1';
    else
        led(0) &lt;= '0';
    end if;

end if;
end process;
end Behavioral;


Schematics for B v2:



CONCLUSION:

Compiler was clever enough to figure that the logic could be totally left out.