LTspice transformer voltage course problems at low duty cycle
A couple of things:


The transformer is there to provide the required step-down ratio but
also to make the circuit isolated from the input side. If you notice, you've grounded the lower terminal of C2 (an all of the other legs there) on the 
secondary side of the transformer. So, in some way, that is interacting with what you 
have going on on the primary side and you don't have isolation.
As mentioned by Dave Tweed in his answer, if you really want to
control the voltage based on the duty cycle, you need an LC fitler,
which will, in theory, give you the DC component of your wave on the
secondary. That should be D*Vs, where Vs is the peak voltage you get
on the secondary. By just having a cap there for filtering, it will
get charged up the peak value after some cycles.


I know that LTSpice will sometimes complain if you don't provide a ground reference point to compute the operating point, so one way people deal with transformers is by adding a connection to ground through a large resistor (100M, 1G). It would look like this:



See this

Notice the large isolation resistor on the secondary side.

One thing that you may not be seeing now but could be relevant later. When driving the MOSFETs, at low duty cycles, all the blanking (dead-time) you're introducing, may not work as expected. By that I mean, that at the output of the H-Bridge, you should ideally see a replica of the dead-time, that is, you should see: +V (lasts Ton), then 0V (lasts Tdead), and then -V(lasts Ton).

However the way you're driving the MOSFETs, you will see (for sure at light loads) +V and -V, with no dead time in between even when you do add the dead time in the driving signals. The reason being, without going into more details, is that at the dead time, all your MOSFETs are OFF, and the two lower ones have their drain-source capacitance charged up to either V+ and V- (at low light loads it takes a longer time to discharge them). So a better approach is to drive the two lower MOSFETS ON at the intended dead time (Two upper ones OFF), and that way you definitely guarantee that at the dead time, the output voltage of the H-Bridge is 0V. Then, with an appropriate filter (i.e L-C), you can get the desired DC output voltage on the secondary side of the transformer: \$N\cdot D\cdot V_P\$, where N is the turns ratio of the transformer, D is your duty cycle, and Vp the peak voltage of the square wave coming out of the H-Bridge. No dead time or very close to none means (in addition to shoot-through) that D approaches 1, so you don't have much control over the DC output voltage. So ideally you could change D (by inserting different dead times) and therefore get different DC output voltages.

Hope it helps.

QUESTION:


  @Big6 why only the lower transistors capacitances will be charged? Also according to Kirchoff's law even if they would be charged one would be charged to +Vp and the second one to -Vp so the voltage on the primary winding should be 0 V.


You drive two transistors at a time (diagonally). There are two transistors off. It looks like this:



Reference

I hand drew the drain-source capacitances for each MOSFET. If you notice, the transistors you're driving, are shorting their capacitance and therefore the voltage across the capacitance is 0V during that interval. Take a look at the other two transistors that are off, the potential difference across their D-S capacitances, is about +V. Now what happens is that at the dead time, if all transistors are driven off, you don't necessarily get 0V across the bridge outputs, and that is because your bridge output is a differential measurement from the two lower drains (one is charged up to +V and the other is at 0V, so \$V_+-0V=+V\$). Unless you have some load, across the bridge output, during the dead time, nothing is actively discharging those caps. Under normal load conditions, you may not see it but under light loads, you can see it.

Take a look at this simulation of an h-bridge with no load attached:



I am driving those transistors similar to what you're doing, notice there is a 2\$\mu\$s dead time to avoid shoot-through. This is the output I get from the bridge under no load:



The 2\$\mu\$s dead-time I inserted at the input signal is not reflected at the output.

If I add a load (5\$\Omega\$), this is what it looks like:



You see the load is enough to discharge those capacitances quickly enough that I can see the dead time in the output. If I were to increase the load resistance, you notice how the dead-time is reflected at the output of the bridge but you see the round corners (like a cap would either charge or discharge):



Now you may ask why this is important. Well, the dead time, in addition to preventing shoot-through, also allows for having different pulse widths and therefore, after you rectify the output of the bridge, you should get all those pulses in the same quadrant and spaced as you wish. From there things are simple, after filtering, your DC output should be just the duty cycle times the peak voltage of the square wave.

If you drive the two lower transistors ON during the dead time, then for sure the nodes from where you take the output of the bridge, will be at the 0V, since any charge on those lower capacitances will be extracted. There are lots of important details here about timing, etc that I've omitted but just wanted to give you a general idea. One more advantage of turning those lower transistors ON is that current flowing through the inductance will have a somewhat easier path to flow at the dead-time, instead of just the upper MOSFET body diode.