Difference between always @ block and @ statement in Verilog
The always @(posedge clk) statement is actually a combination of two statements:

The always procedural block:

always ... begin
    //Body of 'always' block
end


And a sensitivity list:

@(posedge clk)      - At the positive edge of clk
@(signal or signal) - Any change in listed signals
@*                  - Any change to any signal used as an input to the block


When using Verilog for testbenches/simulation (this is not just SystemVerilog behaviour), you can use the always block on its own, for example

always begin
    #5 clk = !clk; //Create a clock of period 10 units
end


You can also use the sensitivity list on its own, in the form of a Procedural Timing Control:

initial begin
    @(posedge clk);           //Wait for a pos-edge of the clock
    reset = 1;                //Assert reset
    repeat(2) @(posedge clk); //Wait for two pos-edge of clock
    reset = 0;                /Adeassert reset
end


Essentially this allows you to perform a sequence of test events based on say, a clock edge.



As far as I'm aware you can't use the procedural timing control for synthesis - instead a state machine or similar would be built within an edge sensitive always block.