Maximum clock frequency for multi-cycle vs pipeline
Pipelined design: you are correct about 1/14GHz.

Multi-cycle: you can change the denominator. For your second example, you could have the ALU and memory stages take 2 cycles each, and run the whole thing at 2/4 GHz.

However, this affects throughput: if your ALU takes 2 cycles, you can't issue more than 1 ALU operation every 2 cycles. Whereas in your first example you can issue 1 instruction every cycle (assuming no stalls or branch mispredicts).

Multi-cycle designs are also a pain from a toolchain and verification perspective, as you have to tell all the tools "this path completes in 2 cycles, do not complain about paths that are longer than 1 cycle".