VHDL Flip Flop Syntax Error
You have a few issues:

1. endif; should be end if;

2. You already have assignments to ledout within your process, but then you attempt to assign a value to it again in the last line ledout &lt;= led_state;. You can't have multiple drivers for a given signal.

3. Your code is a little over-complicated. You can simplify the toggle of signal ledState like so: ledState &lt;= not ledState; without the embedded if/elsif clause.

4. One of the error messages is pointing out a typo you made in the last line ledout &lt;= led_state;, where I think you meant ledout &lt;= ledState;

Try this instead:

library ieee;
use ieee.std_logic_1164.all;

entity blinker is
    port(
            clk     :   IN  std_logic;
            ledout  :   OUT std_logic
    );
end blinker;

architecture Behavioral of blinker is
    signal ledState: std_logic := '0';
begin
    process(clk)
    begin
        if(rising_edge(clk)) then
            ledState &lt;= not ledState;
        end if;
    end process;

    ledout &lt;= ledState;

end Behavioral;


RTL