In an SDRAM how do address rows/columns and rank width and bank width relate to the total memory size?
We're talking about an SODIMM module here. It has multiple chips on it, and has an overall format of 1G (230) locations of 64 (26) bits each. (Total of 236 bits.)

The module contains 16 (24) chips that contain 4G (232) bits each. (Total of 236 bits.)

The memory in each chip is organized as 8 (23) banks, each with 64K (216) rows and 1024 (210) columns of locations that contain 8 (23) bits each. (Total of 232 bits per chip.)