What references cover DDR3 layout considerations?
In a pair of an MPU and a DDR3 --- it is mostly covered by the considerations listed for the MPU --- generally, in its datasheet and/or related documentation.

For example, take a look on AM437x (see doc, sec. 5.12.8.2), there are many variants (single chip, multiple chip, DDR type, etc) considered and covered by related rules.

You may be surprised but the sufficient set of rules necessary to trace DDR3 memory is frequently (if not always) dictated by the MCU/MPU you select and not by the memory you connect to --- and there is no something strange there because exactly the MCU dictates the parameters (clock freq, bus width, addressable volume, timings and modes, etc) it will (can) interact with the memory, since the MCU is the bus master.