Why does this Verilog replicator statement produce a 64 bit long wire?
Replicators do not zero extend, they replicate. {7{f[2]}} means {f[2],f[2],f[2],f[2],f[2],f[2],f[2]}

You miss read the message. The RHS is 9 bits but is being assigned 64 bits (the LHS width). a and b are 8 bit values, are are used as the initial width to be replicated. the Replicator value (n+8) is 8. 8*8 is 64, which is now the LHS width value.

To extend leading zeros use { {n{1'b0}}, f[2] }, which in this case will evaluate to {7'b0000000,f[2]}

Most synthesizers will generate the proper logic with assign {cOut,sum} = a + b + f[2];, and this is assuming you want unsigned logic.