RAM writing simulation in VHDL
Since your clock signal isn't shown, I assume that it's related to the change in the other signals.

Based on that, the first one seems to work correctly in that the write only works on the rising edge of the clock and the logic high of the *write_en* signal. So, that's why you see the data only being written in one cycle after the enable signal goes high.

As for the second sim, seems like the clock signal is connected directly to the *ram_in* signal. This would explain it. The data is latched on the rising edge of the clock. In this case, the only data that is ever latched is 0. At the rising edge, the *ram_io* is always 0.