FPGA Data Collector - What Specs Should I Look For?
Not necessarily you need 10 times the sampling clock for the core logic. First of all, the FPGA, by definition, is a huge sea of logic gates and everyone works in parallel to the others.
So while in an MCU you'll have, say:

Set up the acquisition
Wait for data
Read the data
Do some calculation
Write the data to the memory

These would be like 5 steps to be done sequentially.
Now, in a gate array you would declare a module talking to the ADC which does steps 1-3 (a state machine), another module which does the computation (step 4) and yet another one that stores data into the memory (step 5) (I'm greatly simplifying here)
These three block now can work in parallel, not only strictly in sequence as in an MCU. So while the ADC module reads data, the computer can do the calculation on the previous value and at the same time the memory interface can store the previous-previous value. The technical name for this is &quot;pipelining&quot;.
As for the required clock depends on your converter interface: if it has some parallel output you only need do implement the parallel circuitry (10 bits data paths and so on), clocked at 80MHz. If your output is serial (something like a JESD204 interface, con pump gigabits on the wire) you will have, as you tought, an 800Mbps bitstream but many FPGA (maybe not the very low end ones) have special circuitry that interfaces with these automatically. Look for 'SERDES' in your spec sheet, when choosing the FPGA.
This is what you called 'declare the data path' in advance, it's actually an hardened interface block.
It's quite complex in details but, in short, you attach you serial stream, declare a &quot;gearing ratio&quot; and logic inside will see a parallel port at 80 MHz.
So while the outer clock will be high, the fabric will only need to go at, like, 160 MHz (there will be some dead time, wait for memory bus cycles, handshaking and so on).
EDIT Woe on me. I didn't read you part number, sorry. Your Maxim is a parallel output converter. Any FPGA these days can interface with it, just declare the parallel logic. However if you want to use SDRAM you'll need an FPGA with a suitable interface.
Take notice that all FPGAs have a (small) amount of onboard RAM, if your events are short you could do without external memory.