Industry Standard for Memory Address Decoder Design
In my experience the dynamic NOR structure is most commonly used, because the individual decoders are very small and will match the height of the memory rows. This requires that both the true and complement version of the address bits is routed through the decoders (usually orthogonal to the direction of the word line) and then each of the NMOS transistor gates is tied to either the true or complement version of one address bit.
While the simplest version of this is dynamic, you can also add a weak feedback path to make it static.