Running JTAG chain over busy backplane
This is a crosstalk question as I understand it. 

JTAG is single-ended typically 3.3V signal swing. 

This can couple to your differential signals (which are most likely LVDS with much lower voltage swing) and create logic errors.

The other way around is also possible (the LVDS signal coupling to the single-ended JTAG signal). As I understand it this is what you worry about.

Obviously there is also the LVDS-to-LVDS coupling.

If your back-plane is an off-the-shelf type, you need to examine those 3 crosstalk scenarios and see if it is okay or not before you start designing something more complex.

If you are designing the back-plane, it should be relatively easy to do this in a way that will make crosstalk a non-issue.

My guess is you will have more trouble with the JTAG line disturbing the LVDS than the other way around, but don't listen to my blind guessing. Let the numbers talk.

We can set up the simulation in SigXplorer like this:



The JTAG is driven here by an IBIS model of the SPARTAN 6 FPGA, 3.3V, 24mA drive strength, Fast. This is likely a slightly more hefty output than your JTAG output driver, but better be on the safe side. The other line is a passive line here driven by a 3.3V LVDS output from a SPARTAN 6 in the low state.

Simulating the crosstalk show this for 5 different trace-to-trace spacings (0.1mm to 0.5mm): 



So you can pick 10mV crosstalk just by using 0.5mm spacing and that will be very quiet for the LVDS lines.

Now let’s try this the other way, where the LVDS driver is active and the JTAG is quiet low.



As you can see, even with the closest spacing of 0.1mm trace-to-trace, the LVDS signal does only couple about 40mV of signal onto the JTAG lines. Increase the spacing a bit and you won’t even be able to see it.

The conclusions are:


Maybe you should worry more about the JTAG line disturbing the LVDS
lines than the other way around.
If you design the back-plane, you should easily be able to arrange
spacing to have very little crosstalk between JTAG and LVDS.


All this is done with an IBIS simulator and I strongly recommend you spend a few hours doing this before committing to layout. Your situation will be different - so you can not just use my simulations, although they should give you some idea. Simulating before layout can save you so much time later. 

Full disclosure: I do conduct training and consulting in signal integrity using this software and the software vendor (Cadence) often sponsors use of software for those events, but other than that I am not affiliated.