Decoupling cap on backside: Create separate via?
I hate rules of thumb, I abolish them wherever I work.  It's far better to understand why.  With that said your goal in a good decoupling strategy should be to minimize the impedance across your frequencies of interest.  This translates into wanting to minimize inductance which usually means reducing the loop area or reducing the impedance of the connecting traces/planes/vias. So you can create a nice low inductance path between your chip pins and that cap by placing them on the same layer and running wide traces to it.

Then you want a nice low inductance path to your power planes.  One set of vias right at the cap seem like a nice idea.  Two sets of vias would of course lower your inductance further since the inductance of each via would be in parallel with each other.  (I often do Via in pad but I have the luxury of using those processes. You may too if you're already at an eight layer board).

So with that said and you being a designer who understands your system you can now make your own tradeoffs. In your structure above it looks to me like your loop area is unnecessarily long so I would look for ways to reduce it.  But maybe you have other reasons for that so just keep in mind that you want to reduce the loop area and impedance between the caps, pins and the power planes.

If you want to know if what you've done is "good enough" or even more difficult optimal before you build it you will have to understand your dynamic current requirements and then do some level of simulation.  Otherwise your options are really to try it, or over design it a bit to give yourself some margin.