How to Simulate VHDL when Using a Vendor's Tool Generated Instantiation Code?
My opinion? Don't instantiate. Infer wherever you possibly can.
Find out how your synth tool infers BRAM and write memory that it can translate into BRAM. (It's just an array; you may need to clock the address and/or data to make it synchronous). Semi-dual port ... limitation on read may only apply when concurrently writing to the same address? Link to the datasheet if in doubt. There should also be a &quot;synthesis style guide&quot; to help.
Mock up a simple testcase and synth it to see if you get the usage you expect.