Lane Reversal on PLX PCIe Switches
According to section 4.2.4.10.1 of the PCIe 3.0 Base Specification:


  Support for Lane reversal is optional. 
  
  • If implemented, Lane reversal must be done for both the Transmitter and Receiver of a given Port for a multi-Lane Link.
  
  • An example of Lane reversal consists of Lane 0 of an Upstream Port attached to Lane N-1 of a Downstream Port where either the Downstream or Upstream device may reverse the Lane order to configure a xN Link.


So according to that second point, either the Downstream of Upstream device can reverse the lane order.

Later on, in section 4.2.6.3.2.2, it discusses example cases for lane reversal. In the main example, it is written:


  A x8 Upstream Port is presented with Lane numbers that are backward from the preferred numbering. If the optional behavior of Lane reversal is supported by the Upstream Port, the Upstream Port transmits the same Lane numbers back to the Downstream Port. 
  
  Otherwise the opposite Lane numbers are transmitted back to the Downstream Port, and it will be up to the Downstream Port to optionally fix the Lane ordering or exit Configuration.


Interpreting this further, as long as at least one of the devices supports lane reversal a link can be established. 

If lane reversal is needed, and the upstream device (closest to the RC) is capable of doing it, then it will always be the one to do the reversal regardless of whether or not the downstream device supports it.



The link process is something like:


The downstream port tells the upstream port its preferred ordering.
The upstream port will try to match that request 


If the upstream was able to match the lanes requirement, either by using its preferred layout, or by reversing the lanes. It will echo back to the downstream port the corresponding mapping.
Otherwise if the ordering cannot achieved (i.e. upstream doesn't support lane reversal), then it is left to the downstream port to try to reverse the lanes. The upstream port will echo back a reversed mapping.

The downstream port will check what lane mapping the upstream port is echoing.


If the echo matches the preferred mapping, a link is established.
Otherwise it is now up to the downstream port to reverse the lane mapping. If it supports lane reversal it will now tell the upstream port a reversed lane mapping and a link is established.
If the downstream cannot reverse the lanes, a link cannot be established.