Improve rise-time of NPN current mirror
EDIT: mkeith pointed out a flaw in my design. The reduced beta could be a problem with Q4 in saturation. I'll leave this here because it has some other good information, but the circuit itself will not work because when Vmod is high, DigIn will be driven backwards by Q4 which is likely highly undesirable. 



Current mirror's don't work very accurately with discrete components because there's high levels of transistor mis-match so I doubt current mirrors are a good idea here. Other issues with your circuit include the high resistance of R3 slowing down how fast current may be injected into Q2 and Q1. The configuration you have is forcing your current value (1mA) to be directly correlated to the switching speed. If you raised the current, you would switch faster, but you've specified that the current needs to remain at about 1mA. That means we've got to somehow decouple these two design parameters.

Here's one attempt at resolving the issues you speak of.







simulate this circuit &ndash; Schematic created using CircuitLab

Q3 is in common-collector (emitter-follower) configuration so there's no miller effect so it's a fast switch.

Q1 and Q4 are in a cascode configuration which reduces the gain of Q1 reducing miller effect and thereby increasing the frequency response of it. Q4 is doing nothing more than pinning Q1's collector voltage to ~2.3 at a maximum by the typical 0.7V Vbe threshold voltage of a bjt. Q1 has two purposes, with it's base at ~2.3V when Vmod is high, the emitter will be at approximately 1.6V. 1.6V/1.6kohms gives you the 1mA current you're after. At the same time, this is the switching transistor. When Vmod goes low, the base of Q1 goes low and prevents any current flowing from Dig_Sig down to ground.

Lastly, R2 should be set to any value of your choosing. The higher the resistance, the slower response the circuit will have. The lower the resistance, the more quiescent current you'll be wasting.