How does the NAND Gate work using Transistors
It might be a little easier to understand if we start with switches:







simulate this circuit &ndash; Schematic created using CircuitLab

Figure 1. Hard-wired NAND gate.

Here it should be obvious that Q will be pulled high unless both SW1 and SW2 are closed. When both are closed Q will be pulled low (to ground).


The transistors in your example behave as switches controlled by current injected into their bases. If no current is injected into the base then no current will flow from collector to emitter and they behave as open switches. 
If enough current is injected into the base (by connecting it to a positive supply, usually through a current limiting resistor) then current can flow from the collector to the emitter. 
I have italicised "can" because it can only flow if there is somewhere for it to go. This would be similar to closing SW1 of Figure 1 but leaving SW2 open. Current can flow through SW1 but can't because SW2 is open and the current has nowhere to go.


I hope that makes some sense.