Logic shutdown for CMOS oscillator
I'd run the sleep line directly into pin 2 of IC2A instead of adding another AND gate. That way you retain the Schmidt trigger and don't add a race to IC2A for the clock line.

NOTE: You could also feed the /SLEEP signal to pin 6 on IC2B instead, but then the clock is still free running and when you wake it you can never know where you are in the clock cycle.

Addition: I'd also consider limiting the extents of R3 by adding another series resistor in there to ensure you can never get zero ohms when the pot is at one end or the other.