VHDL top module problems
As far as I can see, your code looks fine. It's difficult to say what the problem is without seeing the build report files. 

The Xilinx tools need to be told what the clock frequency of your clock is. This can be done by modifying your clock constraint as follows:

NET "CLock"         LOC = "B8" | PERIOD = 50 MHz;


It's possible that the first time you were just lucky that the router met timing spec, and the second time round it didn't.