Setting up data prior to a rising edge - what's best practice?
FPGA's are generally designed with 0 hold time.

That means you can set up the address on clock cycle #1, and the RAM will output the desired data in cycle #2. If the address changes on the transition to cycle 2, it won't violate hold time (because min hold time is 0).


  I could set up the address a full rising edge (edge 'zero') before its needed for latching at edge 'one' - but somehow this feels inefficient as it seems I'm taking at least 3 rising edges to get data out of my RAM.


This is basically what I'm saying to do. 

There is a latency of 2 cycles to set up the address and read the output, but the troughput is potentially one read per cycle, because you can change the address every cycle and get new data out each cycle.