Verilog - Use integer constant to define signal width
Although the terminology sounds similar, there are big differences between a constant expression and a const variable.
A constant expression is an expression whose operands are made up entirely of parameters and literals. Its value gets resolved as part of the compilation and elaboration process, before time 0.
A const variable is a variable that is written once at initialization, and you can never write to it again. The initialization can happen at any time based on the beginning of the variables lifetime, and can include the values of other variables that are not const. The earliest is at time 0 for static variables.
You should write this using a parameter or localparam`
localparam int Ratio = ParameterOne/ParameterTwo;

A localparam is just a parameter that cannot be overridden.