Can fixed point division be implemented using a divider that outputs quotient and remainder?
I don't know anything about that IP block. But since you don't yet have a better answer (mine won't be all that good), I'll offer some general advice. I'll draw on some vague assumptions I'll make:


You can define the width of the numerator and denominator, separately.
You can define the width of the quotient and remainder, separately.


I usually normalize both the numerator and denominator using a barrel shifter prior to any division. This counts the number of shifts required and I save those aside. As a result of this step: \$2\cdot denominator &gt; numerator \ge \tfrac{1}{2}\cdot denominator\$.

Assume that the significant bits of your numerator are the same size as the denominator. But also consider a numerator width to the IP block that is twice the size of the denominator. The above normalized numerator is placed in the upper half of the double-width bus. You make a comparison. If the denominator is larger then shift the widened numerator down by one bit. This will guarantee that your quotient will fit in the same width as the denominator.

The upshot of the above is that the numerator bus width is twice that of the other three. An incoming numerator is placed in the upper half, but may be shifted down one bit. Both numerator and denominator are normalized, prior to division.



But let's say you don't use a barrel shifter and don't care to normalize. Then consider setting the numerator width of the IP block at twice the width of the other three. Your external numerator then goes into the upper half of that width (lane shift) and zeros always go into the lower half (optimize the logic for that case.)

Then the fractional part simply using the same divider but now by taking the resulting remainder and dividing it by the original divisor you used before.



You really haven't provided enough information AND I'm also ignorant of your IP block. So that's the best I can offer. Hopefully, someone else will do better.