VHDL Unconstrained port in a entity
Depending on how the rest of your entity works, you may be able to leave DATA_OUT as an unconstrained array. This means that you don't give it a width in the port map, and that it takes the width of the signal that you connect to it in the instantiating entity. This basically passes the problem up one level in the hierarchy.

You can also achieve this using a function. Create a package for your design, and within this create a function, something like this:

function GetDataOutWidth(Switch1, Switch2 : boolean; Data1Width, Data2Width : integer) return integer is
  constant WidthConstant : integer := 2; -- Or whatever
begin
  if (Switch2) then
    return Data1Width + Data2Width + WidthConstant;
  else
    return Data1Width + WidthConstant;
  end if;
end function;


Your code can then use this function in the port map, something like this:

DATA_OUT : out std_logic_vector(GetDataOutWidth(SWITCH_1, SWITCH_2, DATA_1_WIDTH, DATA_2_WIDTH)-1 downto 0)