Construct an 8k X 32 ROM using 2k X 8 ROM chips
This is a two step problem.

First Step: 

Combine your 2k x 8 ROMs into a 2k X 32 ROM (requires 4 x 2k x 8 ROM ICs per 2k x 32 unit)). The address inputs will be common and need to be connected in parallel. The data outputs are kept separate to for the 32 lines required. Don't forget there are also control lines, usually a chip enable and a read line (usually active LOW) but check the specs. 



Second Step

This involves combining four "2k x 32 bit" ROM units. The input ADDRESS LINES (A0 - A10) are connected together in parallel. The OUTPUT DATA lines are also connected together in parallel. This just leaves the problem of the CONTROL LINES. The READ line is simply commoned as you want the ROM to output the data with a single 'read' signal. The CHIP ENABLE lines are used as an extra ADDRESS signal to ensure that only ONE 2k x 32 bit block is addressed at any given time. We have input addresses A11 and A12 to give the full 8K address for the ROM. We need to add a 2 to 4 line decoder to convert these address lines to CHIP ENABLE selections.