Confusion about MOSFET
Some FETs have special drain implants, to achieve high voltages. Thus a major asymmetry would exist. Doing some on_chip design, I encountered both symmetric and a-symmetric devices, models, and layouts; in my case, these were all horizontal surface layout; that is, there was no useful vertical behavior inside the implants. The heat is dissipated only at the surface or 1 or 2 microns down. Thus Safe Operating Area is very small.
Some power FETs have the substrate be the Drain connection, with the wafer eutectically_bonded to the copper tab (1cm by 2cm or so) that removes heat.
This (vertical) FET construction uses the entire wafer thickness for the dissipation of heat, and the Safe Operating Area is very large.