Recommended dsPIC schematic design and voltage regulator
The presented design has two fundamental mistakes.

(1) it doesn't apply correct hardware RESET (MCLR). This pin is clearly needs to be connected with a RC delay. The delay is usually required to make sure that power-on voltages all reached stable valid levels before the MCLR is deasserted (set HIGH).

(2) The datasheet says, "The VCAP pin must not be connected to VDD". This pin must have a 4.7uF low-ESR cap to make the internal 1.8V regulator stable, and left alone. It must be really stressful to feed all core logic with 3.3V while it was designed for 1.8 V.

There is also a BOR (brown-out) circuit attached to the 1.8V regulator, which is also a part of proper reset sequence..

In short, this design was working by accident, due to some lucky timing of voltage ramp, and the BOR circuit (VCAP being connected to VDD) did provide accidentally correct internal reset. So you are right, it eventually is related to power supply. But after exceeding the core voltage for long time (a month), I am afraid this particular chip is fried now, at least partially.

ADDENDUM: Always follow manufacturer's recommendations. There is absolutely no reason not to follow them, a lot of engineering effort and application field experience usually went into these recommendations.