Need for inverter chain to decrease rise and fall time in a comparator
On chip circuitry is often designed to drive only very small loads. In order to increase the driving strength a buffer is needed.

Adding a single buffer with a high W/L ratio would serve that purpose, but due to its size it would again present a high load to the first stage of the comparator and thereby limiting its speed. 

It can be shown that instead of using a single buffer a chain of buffers with increasing W/L results in a faster circuit, when the size of the driven buffer is only a few times the size of the driving buffer.

For this so-called tapered buffer the optimum ratio between two stages would be e (~ 2.718..), in practive however larger ratios are used to keep the number of stages lower while still achieving a decent speed.