Writing synthesizable testbenches
A general approach is to use more abstracted tests as you progress up the stack in terms of design complexity. Yes, you need to trust the tools (and the checking tools like logical equivalence proofs), but for a whole-fpga design (a) there won't be space for a testbench, and (b) exhaustive coverage will take a long time.

A good approach is to use exhaustive or random simulation testbenches at sub-module level, and more functional or vector based tests at full system level. For an FPGA which forms part of a complex design, you might end up needing to build a system emulator in hardware to drive the ports.

A suitable approach depends on your particular design, and how easy it is to generate test stimulus, capture the result and compare with the model (which might be simulation, or might be a higher level software model).

I think that due to the big variations in application, its hard to come up with a standardised approach. Sometimes FPGA is used to accelerate testing of the design, sometimes its the end product. Generally, you can trust that the resulting netlist (assuming it meets timing) will be honestly reproduced by the FPGA fabric - the abstractions are simpler than the transformations that apply in mapping C code to assembler code in the context of an OS.