VHDL Algorithm state machine output
Some problems with your code:

1) Testbench: You are not initializing the reset signal or driving it to a valid state during the simulation. Fix this.

2) Testbench: Your clock period is 40 ns but your testbench waits for 20 ns to change the inputs. This is faster than the system can respond to changes. Probably not what you want to do for basic behavior checks. I suggest changing your wait 20ns statements to "wait until rising_edge(clk); wait for 1 ps;"

3) ASM Code: Next decoder process needs to have A, B, and current_state in the sensitivity list. Generally, if it's an unclocked process, you want to have all input stimulus in the sensitivity list, else you are creating transparent latches. If you need registers (which you don't in this case), make it a clocked process.

4) ASM Code: In your output decoder process, the only thing you need in the sensitivity list is the clock signal. In general, if it's a clocked process, you only need the clock in the sensitivity list (maybe a reset signal as well if you desire an asynchronous reset, but I avoid asynchronous resets unless absolutely necessary). I believe this is not absolutely necessary, but more of a stylistic thing.

5) ASM Code: Generally, you would want to initialize all output signals to SOMETHING. I suggest creating an internal signal for your output Z port, initializing it in the declaration area, use the signal everywhere you are using Z, and then add a line to the bottom of the file that assigns Ztmp to Z.

6) ASM Code: Also, what asdfex said: Initialize your current_state signal.

Hope that helps.