Best positioning of snubber capacitors for Full-Bridge transistors
The layout solution that gives the shortest loop area will be the best performing one, however by not placing them on the same spot you may also get a little bit higher risk of a small resonance between the snubber capacitors.
Anyway there is power stage solution where you have several of parallel smal value snubber capacitors all over the board close to the switch stage. which usually gives better performance than bigger than due to lower ESL and ESR overall.
But again shortest loop area and inductance path/resistance will give the best performance overall anyway.