Aggregate value error in system verilog
You have the ranges in the declaration in the wrong place. You had an unpacked array of 11 single bits (an aggregate). You want a packed array of 11-bits (an integral)
input   logic signed  [10:0] Player_TLX,     //Current Player Top Left X pos
input   logic signed  [10:0] Player_TLY,    //Current Player Top Left Y pos