How to find efficient hardware implementation of sbox of lightweight block ciphers?
What is the method to find efficient hardware implementaion of a 4-bit
  sbox?


finding efficient hardware implementation is by looking on :


Multiplicative complexity: the smallest number of nonlinear gates
Bitslice gate complexity: the smallest number of operations in {AND, OR, XOR, NOT} required to compute this function
Gate complexity: the smallest number of logic gates required to compute this function
Circuit depth complexity: the length of the longest paths from an input gate to an output gate


There are methods used to find efficient implementation  such as SAT solving [ref][source code]1 (the sat solver has been applied on Piccolo sbox) and Logic Minimization Techniques ref which has been to find bit-slice implementation of AES sbox.
for further reading , I also recommend you to read SoK: Peigen – a Platform for Evaluation, Implementation, and Generation of S-boxes