Controlling high voltage pulsed load
Source Impedance as a function of frequency can be measured that is inverse to load regulation.  The open loop impedance can be defined by RdsOn or Rb/hFE. Closed loop impedance  reduces output impedance less with rising frequency due to a fixed GBW. This is reduced further by a shunt array of low ESR capacitors as long as it results in a stable "servo" voltage.  Some CMOS LDO's have boundary conditions for stability with ESR.

Load regulation error tends to be nonlinear due to internal effects, and to remain practical often a pre-load helps with overshoot or minimum load is expected. This testing and PS specs  is done with useful step loads such as 20~100%, 100~50%.  

For pulse loads that exceed static power ratings, bulk storage reactance (caps) are necessary. 

Where pulse width and frequency have unstable zones of nonlinear error, one has to examine the power Supply Bode plot for gain phase margin with sinusoidal swept frequency current loads.  This is called Spectroscopy.  This can be useful to analyze materials or find design faults in the regulator components that affect error and feedback.


  Has anyone got any advice to effectively regulate the voltage across the load when the output is pulsed in such a way?


That needs to be defined by empirical specs and test results where it fails.