Fixing 1 failing timing constraint in Xilinx
in the ISE project directory, you should see a file with extension .twr. That is the detailed report. Search for keyword ERROR, you should find a detailed route timing on the failing one.

It will tell you how much of the delay is logical, how much is on the path. The way I see it is that logical delays needs design changes to improve, path delays could be improved by different floor planning (eg. I see you use IBUFG, by using a physical pin that is closer to that IBUFG may shorten the path delay). 

I have most of the contraints in .ucf file.

Are you feeding this clk into a DCM before you use it?