Adder Implementation in Verilog?
Do I need to write the module for 'full adder' and added the inputs previous sum and aibi bit by bit and store output in sum. Or simply xilinx will automatically implement the full adder during synthsize.


You can expect any decent verilog synthesis tool to handle addition and subtraction operators. Most modern ones will also handle multiplication operators. Support for division operators is less common (and when they are implemented they tend to synthisize to very large slow blocks).

Most of the time it's fine to just use the addition, subtraction and multiplication operators. For really big adders and multipliers it is sometimes nessacery to break them up into smaller units to meet timing.


  Is it valid to use for loop insted of writing always@(condition) beacause on FPGA we have clock as a control signal. Or in this case also xilinx itself will implement/control the for loop by clock signal.


synthesis tools will not turn a loop like that into sequential logic. Instead they will attempt to unroll it and implement it combinatorially. The result will be something that is both very big and very slow.