How to declare register values as an input in Verilog?
If you want to assign a value to something, then it is a register (reg). If you want to connect two things, then you need a wire. If you want to get a signal from an external block you use an input and if you want to send a signal to an external block you use an output. outputs can be wires or regs, but an input cannot be a reg. If you're trying to assign a value to inp inside your block, then how can you also say the value of inp is determined by another block?

Maybe this is more what you're trying to do: on the clock edge, if reset is high then inp_registered gets 0. Otherwise, it gets the value of inp:

module com(
    rst,
    clk,
    inp
);

input rst;
input clk;
input [15:0] inp;

reg [15:0] inp_registered;

[...]

always @(posedge clk) begin
    if (rst == 1) begin
        inp_registered = 0;
    end
    else begin
        inp_registered = inp;
    end
end
endmodule