Is the registry file made from SRAM?
A SRAM memory which is many kilobytes or megabytes in size will generally be constructed in such a way as to minimize the surface area per bit.  A typical design will have memory cells aranged on a grid.  Each memory cell will have four transistors to hold each bit, and two "access enable" transistors to connect each bit to normal and inverted buses which are used for writing and reading.  Typically, all of the "access enable" transistors on a row will be switched together, and all the memory cells in a column will be tied to the same two buses.  The net effect is that at any given time, only memory cells on a single selected row may be read or written.

Register files are generally tiny by comparison.  The ARM register file is probably somewhere around 200 bits (128 for the main register file, but some parts of various shadow registers as well).  Reducing the physical footprint of each memory bit is far less important than maximizing its speed.  At minimum, it should be possible to read two arbitrarily-selected registers while writing a third.  It should also be possible to simultaneously read the value of a register and write a new value to that register, with a guarantee that the write operation will not affect the value seen by the simultaneous read.  A conventionally-laid-out SRAM will not be able to do those things.  Instead, register files are often constructed using discrete flips flops or latches with hard-wired enable or multiplexing logic.  Chip designers will likely lay out register files in some sort of tiled arrangement, rather than laying out each bit's circuitry independently, but from a functional standpoint the bits of a register file will be implemented using a lot more circuitry for each bit than would be typical in an SRAM array.