Why is ISE / XLS is mapping a signal to the global clock GCK0?
Without knowing more about your design, we can only guess. 

Most likely, you connected the CLK (or XXX) signal to the clock pins of one or more flip-flops. 

That is probably enough for the tool to recognize it as a clock and route it on the global clock routing. 

In a comment, you add: 


  it's hard to imagine how a designer could make the leap that any CLK pin should be connected to a real clock. 


There's no requirement that the signals on the GCK nets be "real" clocks, meaning periodic signals with 50% duty cycle. What distinguishes GCK nets is that they have high fan-out, across the whole chip (not just one region), and they have dedicated routing resources (switches) that can connect them to the clock pins of the flip-flops.

So when you route any signal to the clock pin of a flip-flop, the synthesis tool will see that as a candidate for a GCK net. If you have fewer nets connected to flip-flop clock pins than there are available GCK nets, it will probably route all of them via GCK resources. If you have more nets connected to clock pins than there are GCK nets, it will probably prioritize the ones with the highest fan-out.

The tool might also prefer to route clocks on GCK nets, in order to keep other routing available for logic signals that can't use those resources.

This can actually be a problem in some designs. GCK nets have the best propagation delays for nets with very high fan-out. But if your signal actually has low fan-out it might actually be faster to route it on regular logic routing or a regional clock net (I haven't gone back and looked exactly what kind of routing is available in Coolrunner-II). Nonetheless the tool might choose to route clock signals on dedicated clock nets. A synthesis or place &amp; route directive may be needed to get the best performance in these situations.

Of course, the synthesis tool is extremely complicated and we can often only guess what's going on under the hood. You may be able to concoct a situation where the tool fails to recognize a clock and doesn't use the GCK nets. For example, if you route a signal to both clock pins and combinatorial logic, that might change the tool's understanding of its function.