Test bench when design is pipelined
Assuming you want to delay the driving of a signal a with data by n clock signals, you can use
a &lt;= repeat(n) @(posedge clk) data;
This will drive a with data on the
\$n^{th}\$ rising edge of the clock. For more details refer to the SystemVerilog LRM.
Then you can compare it with the golden reference model's value using an assertion.