Generate one-input pulse in Verilog
Ok, theres a very simple solution which I didn't realize. All instances of this pulse circuit on the original schematics trigger the set/reset signal on a flip-flop. All I needed was one always @(negedge in) block that updated the flip-flop. I feel kinda dumb for not realizing it despite it staring me in the face. Mod can close this thread.