What is an LUT in FPGA?
A LUT, which stands for LookUp Table, in general terms is basically a table that determines what the output is for any given input(s).  In the context of combinational logic, it is the truth table.  This truth table effectively defines how your combinatorial logic behaves.  

In other words, whatever behavior you get by interconnecting any number of gates (like AND, NOR, etc.), without feedback paths (to ensure it is state-less), can be implemented by a LUT.

The way FPGAs typically implement combinatorial logic is with LUTs, and when the FPGA gets configured, it just fills in the table output values, which are called the "LUT-Mask", and is physically composed of SRAM bits.  So the same physical LUT can implement Y=AB and Y=AB', but the LUT-Mask is different, since the truth table is different.

You can also create your own lookup tables.  For example, you could build a table for a complex mathematical function, which would work much faster than actually calculating the value by following an algorithm.  This table would be stored in RAM or ROM.

This brings us to viewing the LUTs simply as memory, where the inputs are the address, and the corresponding outputs are the data stored in the given address.

Here's a snapshot from FPGA Architecture by Altera: