Problem with calculating propagation delay
As the signals take many paths from inputs to outputs in a combinatorial circuit, the propagation delay is the longest path; i.e when the output would remain static following a change in the inputs.

Different gates have different delays. For example, 2 inverters in series may have the same delay as a single 4 input NAND gate with similar drive capability. 

Assuming you're implementing this in a CMOS IC, a very easy way to understand which path is the longest (in general, not just your example), is to use the method of Logical Effort.

In Logical Effort you basically model the delay as $$d=gh+p$$
where 


d is the delay (in comparative units);
g is the logical effort: the ratio of the input capacitance of a gate to an inverter capable of delivering the same output current;
h is the electrical effort: the input to load capacitance ratio of the gate
p is the parasitic delay


For example (from Wikipedia):
The total normalised delay of an inverter driving an equivalent inverter is

d = gh + p = (1)(1) + 1 = 2 


The normalised delay of a two-input NAND gate driving an identical copy of itself (such that the electrical effort is 1) is

d = gh + p = (4/3)(1) + 2 = 10/3