Gates and energy loss
This is note quite clearly forumlated, but I guess what the book meant is that typical gate chips are not drawing current at steady state.

This wasn't true on older days (when TTL ruled the world), but nowadays, this is almost true with the CMOS chips. Take a look at a the implementation of a NAND gate, for example:



Whathever the state of the inputs, you see that there is either a path from output to ground (Q3 and Q4), or a path from Vdd to the output (Q1 or Q2), but current can never go from vdd to ground (More details on how CMOS basic functions work can be found here). Moreover, the inputs being FET gates, the current drawn from the inputs is null.

So, this gate, at steady state, does not draw any current (well, almost).

However, when the output state changes, during the time the FETs change state, there can be a current flowing directly from Vdd to ground (when the FETs are in their linear region, i.e. half-blocking, half-passing). So the more state changes, the more power consumption. Which is why power consumption of processors heavily depends on their frequency of operation.

Now, there is also some tiny leakage current, even when the FETs are blocking. And there is a gate leakage current also, which makes the input currents not exactly null. This leads to a few hundreds of nA wasted, usually.