MIPS pipelining and data hazards
I'm assuming a few things because I'm mot sure that you gave enough info for an exact answer. I will describe a system that will allow me to give you an answer.

Suppose this MIPS chip has an ADD instruction that adds two registers, and stores the result in a third. In the pipeline, the data would be read from the register file on cycle 3, and the result would be written on cycle 5. The assembler code for adding three numbers would generate a hazard:

(Add registers $11, $12, and $13 and store the result in register $10)

add $10, $13, $12   # $13 + $12 -&gt; $10 
add $9, $10, $11   # $11 + $10 -&gt; $9


The code has a Read after Write hazard on register $10. The processor would detect the data hazard and stall the second addition one cycle. This assumes that each cycle begins with a write, and ends with a read. If the order was reversed, then the data wouldn't be in the register in time for the 5th clock reading time, and an additional stall cycle would be necessary to get the correct result. Below is an example time-line for a "Write, then Read" system.


Read first add instruction
Read second add instruction
Read operands for first add instruction
Pipeline stall for second add
Write result of first add, read operands for second add
...
Write result of second add


Wikipedia has a good article about pipeline hazards