New to VHDL, How to start?
Your best bet, may be to start with Xilinx's free web pack located here.  It has tools to synthesize your VHDL into logic and also provides a simulator (limited) to visualize your timing and logic.  

The editor really doesn't matter, just work with what you're comfortable with so long as it has syntax highlighting for VHDL.  Refer to this question on this stackexchange: Free IDE for VHDL and Verilog

I highly recommend you also learn to write "testbench" code for your VHDL you're are writing.  If you're familiar with "unit testing" in software development, writing testbench code is a similar process.  A testbench is basically a separate VHDL file written to test the logic of your VHDL module under design.  You use the testbench "code" to apply various logical inputs to your design.  This is normally used in your simulator where you watch the logic flow in and out of your design.  Normally when you write a design, you know what expected inputs and outputs should be, so that is what testbench code is used to accomplish.