PWM DAC Filter explanation
From the schematics given in figure1 and results in figure2, it is clear that PT0 is the PWM signal to be recovered. What is PT1?


It is a separate sample-hold control signal. It needs to have the same period as PT0, but it needs to have a fixed (50%) duty cycle and its rising edge must coincide with the falling edge of PT0.


  Also, why does the author say that this DAC settling will take 0.1sec,


Actually, he says 0.01 sec, which is the PWM period he's using as an example (100 Hz from a 16-bit counter). If your PWM is at 10 kHz, you need to adjust R1 and/or C1 so that T2 is equal to 100 &micro;s, and you will get one-cycle settling as well.


  The chip used for analog switching is CD4053. This chip selection inputs S1, S2, S3 are active high, but the schematic in figure1 shows these inputs to be active low. Can we simply swap the signal inputs and achieve the same result?


Yes.