Multiple LED outputs on FPGA using Verilog
There was a problem with the top module. I did not declare the wire that is used to connect the display and counter module. 

Here is the revised top.v:

module top ( input wire clock, input wire reset, output wire [3:0] LEDs);
wire [3:0] number;
counter c1 (.clock(clock), .reset(reset), .o_number(number));
display d1 (.inumber(number), .LEDs(LEDs));
endmodule


The LEDs light up correctly according to each state now.