VHDL: a+b+carry_in creates two adders instead of using carry in in the existing adder
Why are cin and cin_r of type integer? You can see in the Altera RTL view that it's trying to synthesize a 32-bit wide signal!

Typically, a VHDL adder would take two unsigned or signed inputs of appropriate width and the cin input of type std_logic or similar one-bit-wide signal. Try changing the two integers into std_logics and seeing if the result_r &lt;= a_r + b_r + ("" &amp; cin_r); (suggested by user8352) can correctly infer an adder with carry-in.

Also, your adder does not appear to correctly handle overflow/carry.