Output Jitter of jittery bitstream through flipflop
Assuming you have a suitable low noise clock source to start with, there are ways to improve a basic flip-flop when retiming your synchronous data stream.
Obviously, read the specs, which you are already doing, and choose the lowest jitter available. These tend to be the higher power, higher voltage swing devices, that need more current available to charge their output and internal nodes.
Modern fast devices don't necessarily give you the best jitter. If they have been designed for speed using small internal geometries and small swings, they could end up quite noisy.
Don't overlook plain old 10K and 100K ECL. They are fairly high power.
Some long time ago doing a phase noise investigation, I built a few gates of ECL logic from discrete BFR90 devices, which allowed me to choose the bias currents needed to charge the huge nodal capacitances. I was unable to measure their noise floor with the equipment I had to hand.
If you have a good device, you can make it 3dB better by putting two in parallel, 6dB for four in parallel and so on. You can't simply take an octal flip-flop and parallel the outputs for 9dB improvement if the input clock path is shared between all of the output bits, you would need to take 8 individual packages for that. This improvement gets power, space and cost hungry real fast, so it's the last thing you do once you've found the best single device.