How to create .VCD file or Simulation activity file of verilog code?
(I show an example on linux, the steps with new names to avoid mixing the names and modules with your filenames.)

If you have a file, let´s say, "counter.v", then you would write a testbench file, say "counter_tb.v" (for the sake of clarity, it is better to name the testbench file "something_tb.v" for the file "something.v"). In the testbench-file, you give the vcd file name, as you mentioned:

$dumpfile("counter.vcd")
$dumpvars(0, counter_tb)   &lt;= Name of the testbench module


In the testbench file, there has also to be the include command for the module under test: 

`include "counter.v"
 module
     counter_tb();
 ...
 ...


Then you would compile (on Linux): 

iverilog -o counter counter_tb.v 


Then this can be processed with the command

vvp counter


which produces the output-file "counter.vcd" which can be inspected by the command 

gtkwave counter.vcd 


If all the steps above where correct, there should be no complain