How to map custom IP to the output pin on FPGA
Are they broken all the way out to your top-level design? If not, you have to define some external ports in your block diagram, and then assign them in your constraints (XDC) file. Otherwise, those pins will remain internal / not-connected.

Right-click in the BD, and create a port (Ctrl+K):



Then, when you auto-generate the wrapper for the block diagram, the new port should be present for you to connect to.