How to improve timing on this design using so much BlockRAM?
Your specification says a &quot;256K-word RAM&quot;, and from the code you appear to be using 18b per word. That makes it a very large memory. An Artix 7 BRAM is 36kbit, so 2kWord. For a 256kWord memory, that means 128 BRAMs are required to be connected together.
The problem is not so much then the number of BRAMs, but the additional multiplexer logic required to connect the data outputs. You are essentially requesting 18 (one per bit) instances of a 128:1 multiplexer to select which BRAM output should drive your data bus. You in fact then need two copies of this structure as it's a dual-port RAM (one for each read port). This is going to be physically large.
If we assume a 6-input LUT (fine for Artix 7) which is enough to make a 4:1 multiplexer (4 data, 2 address), that means for each bit you will need a chain of 32 LUTs (128:32) followed by 8 LUTs (32:8) followed by two LUTs (8:2), and then a final LUT (2:1). You'll have 36 of these (two 18-bit ports).
Chaining four levels deep of lookup tables without pipelining will hurt your FMax. In fact it will be hurt even more as BRAMs typically have a not insignificant delay themselves due to the array decoding logic within them. Furthermore the chain is likely to be longer than this as you'll also need the associated address decoding logic, which means the path of the address signal to the output of the multiplexer will be even longer.
What you are going to need to acheive your desired Fmax is some pipelining stages. I am not familiar with the Xilinx block RAM design tools, but they may have the option to specify additional levels of pipelining, which if the core is well designed should be placed nicely within the external decoder logic.
Failing this, you could design a RAM with, say 72bit wide ports, which you can then pipeline and add your own external 4:1 multiplexer to bring these down to 18bit wide after a pipeline stage. I've used this technique for Altera tools before to improve the Fmax of very large memories.