Flip-flop vs latch: Do flip-flops have an edge detector integrated?
Each digital circuit can only work with a given amount of capacitance load which is given by the logical effort and its fan-out. If you connect too many blocks (latches in your case) at the output of the same rising edge detector, it would not work properly and would lead to lot of setup or hold violations after synthesis. The reason is you need to drive too much capacitance and the transistor drive is not strong enough to charge the node to VDD or VSS within the clock period, violating the static discipline. Thus you cannot use same rising edge detector for &quot;a lot&quot; of flip-flops.
There are different ways to implement flip-flops. The way you mentioned is just one of the many. The rising edge detector creates a &quot;narrow&quot; pulse around the rising edge of the clock and consequently enabling the latch only for the on cycle of the pulse. By narrow, I mean pulse width much smaller than the clock period. You can imagine as the clock speeds increase, it gets very difficult to get this narrow pulse. Hence, this technique is not used in usual implementation of the flip flop.
Instead, the static flip-flops are most commonly implemented using Master-Slave latches, connected in series, which work on the different levels of the input clock. For instance, rising edge Flip-Flop can be created if the Master latch gets enabled by digital 0 and slave latch is enabled by digital 1.
For even faster Flip-Flops, dynamic logic circuits like Strong-Arm latches can be used.