How to use array in Verilog actually?
Then write it into output c in the next clock.


No you don't.
e[i] does not receive that value until the next clock cycle. Thus c &lt;= e[i]; gets the old value of e[..]. 
 But by the next clock cycle you have changed  i, you incremented it: i &lt;= i + 1; so c still does not get that value of e[i]