New (for me) wire range syntax [(1)-1:0] in Verilog
It appears to just be following a general format of [(WIDTH)-1:0] - bascially the same as [WIDTH-1:0] but with parenthases (for clarity?).
If you want to quickly read how wide it is, just read the number in the brackets. If you want to later change the width, just change the value in the brackets.
Its quite possible that it was code generated from some IP wizard, in which case it would be easier for the wizard to make a signal based on the width by using such code. It wouldn't have to subtract 1 from the width value in the generator code, but instead can simply output to file whatever value (be it number or parameter) you enter as the width.