Sampling rate in dacs
Going back to a 1994 databook I have data for the AD565A.

There is no sampling rate specified for this part because it has no clock inputs. 

It is a raw DAC with no digital support logic whatsoever. Each digital input directly connects to a switch between Vref and Ground. You can change the input pins at any rate you like!

What IS specified for it is settling time : 


from 10% to 90% in 30ns (meaning you can get high speed outputs with VERY limited accuracy) and
to 1/2LSB (i.e. full accuracy) within 250 ns.


The latter is the more useful specification. It imposes a useful upper speed limit of 4 MHz sampling rate. But note, to be useful at this speed, you will need an external sample and hold, otherwise you'll see a lot of switching artefacts on your output while the output settles to the new value.

And you need to add the sample time of the S+H to the DAC's own settling time, and this further reduces the useful sampling rate, e.g. with 50ns sample time + 250ns settling time, minimum period is 300ns or sampling rate is 3.3 MHz. (A further note : designing a fast accurate S+H is quite an exercise in itself.)