How to implement a flip-flop with synchronous and asyncronous reset?
The simple answer is that Xilinx, to use your example, did not implement their flip-flops in Verilog. Their flip-flops are full-custom VLSI designs where the logic cells are highly optimized.

However, we can get a notion of how Xilinx would accomplish this. If there is only one reset input signal for the cell, and we know that the actual implementation of synchronous and asynchronous resets is quite different, then it must be the case that this reset input can be used as either an asynchronous or a synchronous reset but not both.

So, inside Xilinx's actual logic cell they have probably implemented the logic for both asynchronous and synchronous reset. There are two internal signals for possible reset functions. A configuration bit is used to choose which of these signals is actually active and which is disabled.