Ignoring setup delay
If your clock period is long compared to other delays in your circuit, parameters like setup times have no effect on circuit operation.

But in the more general case, no, you can't ignore setup parameters.  Neither can you ignore other timing parameters such as hold time, clk->out delay, or combinatorial delay between clock elements.    

Lets look at a simple example - two devices (flip flops or registers) clocked on the same clock edge, with some combinatorial logic in between.

Assume your clock period is Tclk; the clock to output delay is Tclk-q; the prop time through any intervening logic Tprop, and the setup time of the receiving clocked device is Tsu.

You want (Tclk-q + Tprop + Tsu) &lt; (0.80*Tclk).  The 0.80 factor is to give you some margin.

If you're designing with FPGAs, the FPGA tool set will tell you if you have a potential timing violation, given your specified clock rate (period).  If you're designing with old fashioned discrete logic, you have to do that analysis yourself.

EDIT2:

Here's a simple diagram to go along with the above: