Two's complement overflow at a 4-bit adder circuit
Two's-compliment overflow is not very simple when it comes to the logic involved. Have your XOR gates handy.

For an addition operation, the overflow bit should be set if the sign is the same for both operands that were being added, but different from the sign of the result (an XNOR and an XOR).

For a subtract or compare operation, the overflow bit should be set if a positive number (sign=0) is subtracted from a negative number (sign=1) and the result is positive, or if a negative number is subtracted from a positive number and the result is negative (I'll let you do that one).

For the subtract, it might be simpler to involve CARRY in the logic.