Can I2C Master Stretch the clock?
Being the master the clock generator, it's in fact reducing the clock frequency by its own, contrary to a slave, that has the clock generated by the master, but wants to signal the master to hold it.

According to Wikipedia:


  Although the master may also hold the SCL line low for as long as it desires, the term 
  "clock stretching" is normally used only when slaves do it.


But


  To ensure a minimum bus throughput, SMBus places limits on how far clocks may be 
  stretched. Hosts and slaves adhering to those limits cannot block access to the bus for > more than a short time, which is not a guarantee made by pure I²C systems.


So, when using clock stretching be sure the devices support it, as for trademark reasons I2C is implemented as other names and has not all features. But that is more a concern for slave devices.