Parallel binary counter using T flip-flops
Assuming there is a common clock connected to all of the T flip-flops here what will happen when Pt is high:
The T input of the A FF will be 0, so the output (A) will not change, i.e. will be constantly A=0. As it is connected to the NANDs, their output will be always 1, so B, C and D will flip every clock. So it will be like 0000, 0111, 0000, 0111.. Which is not a counter at all. 

If Pt is 0, the outputs of all of the NANDs are going to be 1, so each FF is going to flip every clock cycle. So it becomes like  0000, 1111, 0000... Which doesn't make sense as counter as well. So we can conclude that you have a mistake in your drawing. The correct one would be if we replace the NAND gates with AND like here:


** The image is taken from here.