Problem getting VHDL syntax correct
VHDL accepts the ISO 8859-1 character set, this is UTF-8.

Your VHDL analyzer is having problems with some of the characters as a result of you copying the text directly from a book.  

Your comments aren't delineated by two dashes (e.g. --), your double quotation marks all need to be replaced with ".

After which the VHDL code analyzes.

There's no discernible reason why d3, d2, d1, and d0 can't be replaced with a bit_vector.  There may uses with the present port interface in the book.

Formal ports are associated with actual signals in an association list.  It's possible to associate individual elements of a vector with a base element.

Converting between non-closely related types can be done with conversion routines:

-- bcd_7seg.vhd
-- bcd-to-seven-segment decoder
entity bcd_7seg is
    port(
    d3, d2, d1, d0: in bit;
    a, b, c, d, e, f, g: out bit
    );
end entity;
architecture seven_segment of bcd_7seg is
    signal input : bit_vector (3 downto 0);
    signal output: bit_vector (6 downto 0);
begin
    input &lt;= d3 &amp; d2 &amp; d1 &amp; d0;
    with input select
        output &lt;= "0000001" when "0000",
                  "1001111" when "0001",
                  "0010010" when "0010",
                  "0000110" when "0011",
                  "1001100" when "0100",
                  "0100100" when "0101",
                  "1100000" when "0110",
                  "0001111" when "0111",
                  "0000000" when "1000",
                  "0001100" when "1001",
                  "1111111" when others;
-- separate the output vector to make individual pin outputs.
    a &lt;= output(6);
    b &lt;= output(5);
    c &lt;= output(4);
    d &lt;= output(3);
    e &lt;= output(2);
    f &lt;= output(1);
    g &lt;= output(0);
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bcd_tb is
end entity;

architecture foo of bcd_tb is
    signal d:  std_logic_vector (3 downto 0) := "0100";
    signal output:    std_logic_vector (6 downto 0);
begin
DUT:
    entity work.bcd_7seg
        port map (
            d3 =&gt; to_bit(d(3)),
            d2 =&gt; to_bit(d(2)),
            d1 =&gt; to_bit(d(1)),
            d0 =&gt; to_bit(d(0)),
            to_stdulogic(a) =&gt; output(6),
            to_stdulogic(b) =&gt; output(5),
            to_stdulogic(c) =&gt; output(4),
            to_stdulogic(d) =&gt; output(3),
            to_stdulogic(e) =&gt; output(2),
            to_stdulogic(f) =&gt; output(1),
            to_stdulogic(g) =&gt; output(0)
        );
end architecture;


You can also associate individual elements of an array type port with the base element type or use conversion functions as are shown above for converting between type bit and the element type for std_logic_vector.