How would it be possible to avoid contention for a Network on an SoC (or more specifically an FPGA) from two or more nodes?
usually do not send command or data autonomously.

That's the early 1980's. In the last decades, any microcontroller, SoC, and things usually just sold as &quot;processor&quot; have multiple devices on-package that all have &quot;initiative access&quot; to a shared bus – typically, for DMA purposes.

This seems to be like a great theoretical example of using a network protocol instead of a bus to transmit command/data.

Not really, no. This is still a bus. It's a shared thing – and you'll need arbitration.
Also, usually, that shared thing isn't electrically a connection potentially driven by multiple sources (it could be, but that's usually not how logic cells/routing works), but something where you kind of tap into one line or not. But that's a technical detail.
That can take many forms, from the scheduler regularly asking the bus interface on each of your four cores whether they are ready to send some data, to simply four (that's basically nothing) lines where a bus can signal it's ready to send data and then receive some info (either over the bus or over a dedicated control line) that it now should actually start sending data, to some fixed time slots, to some fair round robin scheduling, to simply detecting whether someone else is already using the bus and if so, waiting till they are done. You can prefix your data with a header with your own address, or rely on some known scheme for the other end to infer the origin of data.
There's really a lot of different bus architectures.
What you describe as a network doesn't sound like a network to me, just like a bus.