Identify the Maximum ESD Clamp Voltage on a circuit
just because a component "breaks down" does not mean the component is destroyed.

ESD circuits are LAYOUT and SILICON_CONTACT critical ---- there is far more going on in an ESD event than what the schematic tells you.

The critical action is to steer the charge DEEP DOWN, so the heat goes DEEP into a big volume of silicon that absorbs the energy. Thus LAYOUT --- and metal widths and the number of contacts/well_ties/active_ties/etc all matter.

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What is DEEP DOWN?

Modern processes (low voltage) operate in the top 1 micron. So there is little silicon volume to absorb heat.

Yet the EPI (if you have that process methodology) is 10? microns deep, so why not craft the metal_active contacts with spacings to "encourage" the ESD transients to mostly use the deeper (1u to 10u) paths to transport the ESD charge??? That mindset, with intentionally_spaced contacts, is part of the ESD design degree_of_freedom.

Given the Bond Pads may be 100 micron on center_center, you have lots of room to encourage the huge transients to "go deep" and heat up the bulk silicon, instead of remaining near the surface and melting the very thin active implants.