SR Latch settles on equilibrium state with lower voltage supply
If 'SET' and 'RST' are 15 volt signals, then these mosfets are designed for a gate voltage of +2 to +10vdc, with a limit of +/- 20 vdc. Full ON voltage is +10 volts to +15 volts, so going below 10 volts on the gates takes them out of saturation and into a resistance (non-linear) much greater than zero ohms.As the voltage lowers down to +2 volts and below the mosfets reach an OFF state with only a few uA of leakage current flowing.Such a condition would prevent it from behaving as a stable RS latch. To work with 5 volt and 3.3 volt logic levels you would need 'logic' mosfets for that low of a gate voltage. If you make that change Vcc can be no higher than +5 volts.