In jfet voltage divider bias how can Vgs be negative with out knowing the resistor values?
A JFET is a depletion device meaning it is normally on, it will conduct current when \$V_{GS}\$ = 0. Therefore in amplifiers a common way to use an JFET is to bias it with a negative \$V_{GS}\$, for example: \$V_{GS}\$ = -2 V so that the drain current \$I_D\$ is such that the JFET behaves in a linear way.

This bias voltage should not be too close to the pinch off voltage where the JFET makes the drain current zero.

So in the book they choose the resistor values such that \$V_{GS}\$ has a negative value. Let's assume that we're going to bias the JFET at \$I_D\$ = 1 mA and that the JFET we're using needs a \$V_{GS}\$ = -2 V for that. If we make then \$R_S\$ = 3 k\$\Omega\$ then there will be 3 V at the source of the JFET. If we then choose \$R_1\$ and \$R_2\$ such that there's 1 Volt at the gate of the JFET then we get \$V_{GS}\$ = -2 V.

So the \$V_{GS}\$ is negative statement should be: We bias the JFET such that \$V_{GS}\$ has a negative value. It cannot be seen from the circuit itself. I can use the same circuit to make \$V_{GS}\$ = + 2 V but then the JFET might not operate like I want.