SystemVerilog Enumerated Multi-Domain Array -> how to declare/define?
To the best of my knowledge typedef enum logic [N-1:0][1:0]{S0,S1,S2,S3} state_t; should not compile, and I was not able to get it to compile on any simulator on EDAplayground. Enums need a simple vector datatype. logic [N-1:0][1:0] is a double packed array and thereby isn't simple.

If you do not specify the data type of an enum, it is assumed to be an int.

typedef enum st_t [N-1:0][1:0] state_t; has a similar problem as your original statement, but now you define an enum as an double packed enums. Plus you never define the enum values.

What will work:

typedef enum logic [1:0] {S0,S1,S2,S3} st_t;
typedef st_t [N-1:0] state_t;


Or as an unpacked array:

typedef enum logic [1:0] {S0,S1,S2,S3} st_t;
typedef st_t state_t [N];




Read more about user-defined types (typedef) and enumerations (enum) in IEEE Std 1800-2012 &sect; 6.18 User-defined types and &sect; 6.19 Enumerations

Try differnet combinations on your SystemVerilog simulator or a one of the many simulators on EDA Playground (Use one of the commercial simulators, the free ones have limit if any SV featurs)