LTSpice Level 2 Simulation CMOS follower
These look like charge injection from the overlap capacitance of gate to S/D. If you overlay the intermediate node output (the output from the first inverter) you will find that these edges are related to the the signal swing of this internal node.

As the Output is swinging from low to high the internal node must first swing from high to low and some of the edge will couple into the output signal.  That 's why it looks odd, it appears to be happening before the the signal switches.

I grabbed this pictures from ITU website in which there is a discussion of capacitances of a MOSFET.



This picture is for a MOSFET when it is turned off, when on, there will be a Gate to channel cap and a channel to bulk cap.


Your simulation is running fine.