Making a synchronized, rising edge reset signal to a decade counter
Your schematic is clearly incorrect. All the clock inputs of your flip-flops should be connected to the same clock. This is required for a synchronous system. And the asynchronous reset must only be used to initialize your flip-flops. Not respecting these rules will lead to serious problems in a real circuit.

What must be done is to compute at every flip-flop, its next state according to the state of the counter.

Here is the state table of a 10 bits counter for D flip flops

3210  next   D3 D2 D1 D0  
........................    
0000  0001   0  0  0  1  
0001  0010   0  0  1  0  
0010  0011   0  0  1  1  
0011  0100   0  1  0  0  
0100  0101   0  1  0  1  
0101  0110   0  1  1  0  
0110  0111   0  1  1  1  
0111  1000   1  0  0  0  
1000  1001   1  0  0  1  
1001  0000   0  0  0  0  


So 
D0=/Q0
D1=/Q3/Q1Q0+/Q3Q1/Q0
D2=/Q3/Q2Q1Q0+/Q3Q2/Q1+/Q3Q2Q1/Q0
D3=/Q3Q2Q0Q1+Q3/Q2/Q0/Q1  

Additionnal simplifications can be done by considering the impossible states 
1010 to 1111.

Adapting it to JK flip flops is left as an exercise.