FPGA RAM / SRAM in VHDL
The most straightforward thing to do (IMO) is to directly instantiate the device primitive in your VHDL. This way you are not relying on the tools to infer block RAM. In ISE, go to Edit -> Language Templates, and you will be able to bring up the template. (You will want to choose Spartan-3E, of course, although I think the primitive is the same in this case.)



The disadvantage of using the primitive, of course, is that your code is not trivially portable outside of the device family. (For block RAMs, this is not such a big deal since they are very similar across vendors and families.)

Another option is to use the Core Generator, which is perhaps more 'user friendly' to set up, but slow during initial synthesis. You can also generate an entire FIFO this way.

Perhaps someone can speak to methods of inferring block RAM.