Achieving low-frequency clocks in FPGA fabric when below what PLL can provide
Do not use Clocking Wizard to generate timing pulses for external use, as SCL serial clocks for I2C or SPI protocol or whatever else. The Clocking Wizard application area is stated in a Vivado Design Suite document Clocking Wizard v6.0 LogiCORE IP Product Guide, page 7:

Applications

The creation of clock networks with the required frequency, phase, and duty cycle, with reduced jitter.
Electromagnetic interference reduction in electronic devices using the Spread Spectrum feature.


The creation of clock networks for use within your FPGA chip, and not of clock pulses/signals that may be used elsewhere.
Read also about clock networks, clock routing and other clocking features, what these do in your FPGA and why these are outright waste of resources to carry your &quot;1Hz virtual clock&quot; signals.
If you want to build &quot;a 1Hz virtual clock&quot; as an exercise in building resource-optimized variable length shift registers, follow instructions from a Vivado Design Suite document RAM-Based Shift Register v12.0 LogiCORE IP Product Guide or similar documents of your choice. The output of your &quot;virtual clock&quot; generating circuit goes to an output IO pin, and not to a clock region; you need not route this signal around within your FPGA.
If you are interested in how the design tools implement your VHDL/Verilog code, read about slice registers/slice LUTs/distributed RAM.
Do not worry about &quot;burning up millions of cycles just to count&quot;: FPGA is made to run millions and even more of cycles; IP cores take care of optimizing power and resource costs to help FPGA do a useful job. Just notice that for tasks similar to your hypothetical task, the hardware solutions sort of RTC chips with 32.768KHz crystals are recommended.