Best way to optimize verilog cpu?
It's hard to be sure from your snippet, but it appears that you have a &quot;single cycle&quot; implementation, in which all of the activity for a given instruction happens in a single clock cycle. A maximum speed of 50 MHz is quite typical for such implementations.
To go beyond that, you need to start thinking at a lower level about the physical structure of your datapath, and the possibility of pipelining the execution of an instruction over several clock cycles.
A common structure for many RISC architectures is a 5-stage pipeline:

instruction fetch
instruction decode
register read
ALU
register write

Of course, now you need to start thinking about what happens when there are dependencies among the various instructions that are in the various stages of the pipeline — do you simply stall the pipeline (insert NOPs) as needed, or do you implement a data forwarding mechanism in order to avoid stalls?
We have a lot more questions about mips than about risc-v, but they are similar enough that looking through them will be helpful to you