Number of gates in series
You must evaluate the longest path any input must traverse, in terms of gates, in order for the final output's value to be resolved.  The textbook is correct in saying that the longest path is two gates in Figure 2.17:  Either input has two possible paths, one is G1-G3, the other is G2-G3, therefore the maximum depth (or delay) of 2.

Perhaps you are being misled by the NAND gate G2, which you may be thinking that is composed of an AND and a NOT, therefore being by itself two gates in series.  But that is not necessarily true, the NAND can be a single gate by itself.  To understand why, it helps to see how it may be constructed in, for example, CMOS technology.