Infinite While loop in Vivado
I mean I will change the frequency of operation of zynq zc702 processor in Vivado using IP block. And I am expecting that the time to count to 1000 will also change accordingly.


Nope! What you have is some vague Verilog code (which by the way does not work) but which has nothing to do whatsoever with what the Zynq processor(s) do. 

Your HDL and processor are two completely different entities and have nothing to do with each other. (Not until you make some hardware which connects the two using e.g. an AXI bus. But you are miles away from that.)

Basically you must:


Instance a Zynq core with a clock coming out.
Write a counter in Verilog which toggles an output. (About a million example out there) 
Connect the clock of your counter to the Zynq output clock.
Connect the counter toggle output to a spcific pin of the FPGA package using placing constraints.
Synthesis and watch the pin with a scope.


Best way to start at all the above is to read-up on Verilog for the counter.
As to Zynq: look at some youtube video's about how to use the Zynq and Vivado. (That is how I started with Zynq too)