Bitwise expression in System Verilog causing Icarus Verilog to Hang
Lets simplify and with a and b as 4-bit values so c_in[0] would be ~(c_in[3]) | carry_in.
Assume a=4, b=3, and carry_in=0. The sum would be 7 and c_in[3] would be 0 (initially). c_in[0] would become 1 per your equations; making the the sum 8 with c_in[3] as one. That means c_in[0] will be re-evaluated back to 0. Hence the feedback loop that prevents the simulator from moving the the next time step.
Since you are running with 64-bit values, the hang has a smaller change of being observed until it picks a condition where a+b == (1&lt;&lt;(width-1))-1 and carry_in == 1'b0
Your c_in[0] and carry_out assignments look very odd for a ripple adder. They can be greatly simplified.