VHDL: How to only update register at rising edge of the clock?
Forget using combinational processes with complicated and error-prone sensitivity lists, until the once-in-a-blue-moon time you actually need them.
Especially when you move on to state machines; but even here, a single synchronous process is cleaner and shorter, as well as much easier to get right. This reproduces the code you have (with the correction to the sensitivity list)
process(clk,reset)
begin
    if reset='1' then
        lastelement     &lt;= (others=&gt;'0');
    elsif rising_edge(clk) then
        if enqueue = '1' then
            lastelement &lt;= lastelement + 1;
        end if;
    end if;
end process;

There is one additional wrinkle in your problem specification however:

At the rising edge of each clock, it should check whether another
signal enqueue is HIGH. If it is, then lastelem_reg will be incremented by 1 in the next clock, otherwise it continues to hold its old value.

This needs an additional single cycle delay:
process(clk,reset)
begin
    if reset='1' then
        lastelement     &lt;= (others=&gt;'0');
        lastelement_d1  &lt;= (others=&gt;'0');
    elsif rising_edge(clk) then
        if enqueue = '1' then
            lastelement &lt;= lastelement + 1;
        end if;
        lastelement_d1  &lt;= lastelement;
    end if;
end process;

and I think lastelement_d1 (lastelement delayed 1 cycle) is what you are looking for.