use of library files in verilog synthesis and decompile original rtl file
I believe "decompile the original rtl in file" is the conversion of RTL coding to gate-level modeling. The RTL style has always blocks and assign statements, while gate-level modeling only contains calls to other modules and/or standard cells. Both are functional equivalent (when written correctly). Big difference is RTL is higher level of abstraction and therefore easier to code (especially complex designs), while gate-level modeling is closer to what the silicon design will actually be and can even simulate with annotated timing.

The library file contains the definitions of all the available standard cells for a particular technology and is used for RTL to gate level conversion. In other words it is the cells that the synthesizer is allowed to use for conversion. Typically it is hold definitions for nand, nor, xor, flop-flop, buffer, inverter, etc. and various flavors of each to support timing, load, size requirements. It usually provided by a vendor or foundry.  

If you do not have Verilog library, but you do have a schematic. Then find out how to export the library as Verilog. Otherwise is it possible to make a fake library by hand (just realize you cannot use it with a real project). Example: fake_udp.v

`celldefine
module FAKELIB_NAND2(output OUT, input IN0,IN1 );
  assign OUT = ~(IN0 &amp; IN1);
endmodule
module FAKELIB_NAND4(output OUT, input IN0,IN1,IN2,IN3 );
  assign OUT = ~(IN0 &amp; IN1 &amp; IN2 &amp; IN3);
endmodule
module FAKELIB_NOR2(output OUT, input IN0,IN1 );
  assign OUT = ~(IN1 | IN0);
endmodule
module FAKELIB_INV(output OUT, input IN );
  assign OUT = ~IN;
endmodule
module FAKELIB_BUF(output OUT, input IN );
  assign OUT = IN;
endmodule
module FAKELIB_BUF_BIGLOAD(output OUT, input IN );
  assign OUT = IN;
endmodule
module FAKELIB_DFF(output reg Q, input CLK, RST_N, SET_N, D );
  FAKELIB_DFF_PRIMITIVE dff(Q, CLK, RST_N, SET_N, D);
endmodule
// ... more standard cells ...
`endcelldefine
primitive FAKELIB_DFF_PRIMITIVE(output reg Q, input CLK, RST_N, SET_N, D  );
  table
   // CLK RST_N SET_N D : Q(state) : Q(next)
       ?    0     ?   ? : ? : 0;
       ?    1     0   ? : ? : 1;
       p    1     1   0 : ? : 0;
       p    1     1   1 : ? : 1;
      (?0)  1     1   ? : ? : -;
       ?    1     1   * : ? : -;
  endtable
endprimitive
// ... more standard cells ...


Now Assume you have the following RTL:

module my_module(input clk, rst_n, input [2:0] in, output reg [2:0] out);
always @(posedge clk, negedge rst_n) begin
  if ( !rst_n ) begin
    out &lt;= 3'b0;
  end
  else begin
    out[0] &lt;= ~(in[0] &amp; in[2]);
    out[1] &lt;= &amp;in;
    out[2] &lt;= in[1] | in[2];
  end
end
endmodule


Synthesizing with the fake_udp.v as your library will give something like this: (Note: Output depends on tool and options. Also this example was done by hand)

module my_module(input clk, rst_n, input [2:0] in, output [2:0] out);
supply0 SUPVSS;
supply1 SUPVDD;
wire syn_0, syn_1, syn_2, syn_3, syn_4;

FAKELIB_NAND2 U0 (.OUT(syn_0), .IN0(in[0]), .IN1(in[2]));
FAKELIB_NAND4 U1 (.OUT(syn_1), .IN0(in[0]), .IN1(in[1]), .IN2(in[2]), .IN3(SUPVDD));
FAKELIB_NOR2 U2 (.OUT(syn_2), .IN0(in[1]), .IN1(in[2]));
FAKELIB_INV U3 (.OUT(syn_3), .IN(syn_1));
FAKELIB_INV U4 (.OUT(syn_4), .IN(syn_2));
FAKELIB_DFF out_0__reg (.Q(out[0]), .CLK(clk), .RST_N(rst_n), .SET_N(SUPVDD), .D(syn_0));
FAKELIB_DFF out_1__reg (.Q(out[1]), .CLK(clk), .RST_N(rst_n), .SET_N(SUPVDD), .D(syn_3));
FAKELIB_DFF out_2__reg (.Q(out[2]), .CLK(clk), .RST_N(rst_n), .SET_N(SUPVDD), .D(syn_4));
endmodule