Understanding signed numbers in Verilog
Only the entire declaration as a whole is considered signed. Selecting a bit or part-select (even if it selects the entire range) would be considered unsigned. That's because the base element data type of the array (reg) is unsigned. 

SystemVerilog allows you to layer your types so that you could take a signed 8-bit type and pack it into a signed 64-bit declarations. 

typedef logic signed [7:0] byte_t;
byte_t signed [7:0] var_name;