Assigning a value to a tri data type variable in Verilog
In SystemVerilog, wire and tri are aliases for identical net types. Section 6.6.1 Wire and tri nets in the IEEE 1800-2017 LRM explains that the driver with the strongest strength will use its value for resolution. There's no way for a net to have different values when connected through a port, but I assume you meant the driving value in each module. So the result is as defined in table 6-2, which is 1'b1.