Sequence detector design demonstration in LTSpice
I was curious to try your circuit and also got spikes, but I avoided spike by adding delay to AND gate with Y output.
Also it seems you are using custom digital library, so it's not clear what parameters the components have.
Seems like comment made about alternative implementation could simplify design.
A2 X 0 clk 0 0 N006 N005 0 DFLOP Vhigh=5 Vlow=0 Td=20n Trise=10n tripdt=5n
V1 X 0 PULSE(0 5 1m 5n 5n 2m 4m)
V2 clk 0 PULSE(0 5 5n 5n 5n 1m 2m)
A3 0 N005 0 N007 0 0 N002 0 AND Vhigh=5 Vlow=0 Td=10n Trise=10n tripdt=5n
A7 N003 N002 0 0 0 0 N001 0 OR Vhigh=5 Vlow=0 Td=10n Trise=10n tripdt=5n
A8 X 0 0 0 0 N007 0 0 BUF Vhigh=5 Vlow=0 Td=10n Trise=10n tripdt=5n
A1 N001 0 clk 0 0 0 N004 0 DFLOP Vhigh=5 Vlow=0 Td=20n Trise=10n Tfall=10n tripdt=5n
A4 N002 0 N008 0 0 0 Y 0 AND Vhigh=5 Vlow=0 Td=10n Trise=10n tripdt=5n
A5 N004 X N006 0 0 0 N003 0 AND Vhigh=5 Vlow=0 Td=10n Trise=10n tripdt=5n
A6 N004 0 0 0 0 0 N008 0 BUF Vhigh=5 Vlow=0 Td=20n Trise=10n tripdt=5n
.tran 20m
* Tfall is by default equal to Trise\nRef is by default (Vhigh-Vlow)/2\nSee &quot;A. Special Functions&quot; in help docs
* Added delay to this input to avoid spikes
.backanno
.end


Edit:
I would emphasis that although one delay at output seemed to fix spike issue. That is not guarantee this circuit works with other sequence of 0's and 1's. I believe the issue here is that when the inputs transition from logic low to high (or high to low) there can be undefined state at transition time. The direct feedback also complicates things as comment suggests.