NPN High side switch
I believe you are talking about this.

You would need a pull-up as shown.







simulate this circuit &ndash; Schematic created using CircuitLab

However, the issue with this circuit is, when you turn off the transistor the clock line will go high, clocking the 374 if the input clock line itself is low. That means WHEN you disable it is critical since the data you are trying to latch must still be presented and held at that time.

Further, the rising edge of the clock is dictated by the resistor so it will not be as sharp as the original digital clock. Timing and hold times will be affected. The source clock signal also needs to be able to sink the pull-up current AND the base current, so you can not make R1 OR R2 small.

Adding a proper logic gate would be much better and will prevent disturbance on the original clock line.