Get_ports vs Get_pins vs Get_nets vs Get_registers
I/Os of the top-level block are called port, I/Os of the subblocks are called pin. So get_ports and get_pins commands must be used accordingly.

If the main clock is an input of the top-level block, get_ports is the appropriate command. For example:

create_clock -name CLK [get_ports clock_main] ...


Since clock_1 and clock_2 are the inputs of the subblocks, get_pins must be used in this case.

create_clock -name CLK1 [get_pins Module_1/clock_1] ...
create_clock -name CLK2 [get_pins Module_2/clock_2] ...


The signals other than the I/Os are called net. The nets may be collected and constrained by using get_nets command, however most of the synthesis tools optimize out them or change the names. It is better to avoid using get_nets if not mandatory. Otherwise most of the synthesis tools require dont_touch attribute or something similar to keep the net.

Normally I don't use get_registers command, because it's not supported by Synopsys Design Compiler, I use get_cells instead. On the contrary, Quartus II supports get_registers according to Altera's SDC manual.

It can be also used to constrain the clock. The manual has the following example:

create_generated_clock -divide_by 2 -source [get_ports clk] -name clkdiv \
  [get_registers clkdiv]


Alternatively you may use get_pins command. It's up to you. 

create_generated_clock -divide_by 2 -source [get_ports clk] -name clkdiv \
  [get_pins clkdiv/Q]


If you have such a clock divider in your design, it's better to constrain it on the register or Q pin than the clock input of a subblock (e.g. Module_1). Otherwise the synthesis tool doesn't know whether the path carries a clock signal between the register and the clock_1 pin. The delay of the path is not included in the timing analysis etc.

Synthesis tools commonly add suffixes to the signal and cell names. Each tool has its own naming rules. For example, my tool adds _reg suffix to the flopped signals.