How does verilog evaluate conflicting assignments?
This code is legal. Within an always block the order of the statements matter; thus in your case assignment of counter &lt;= 0 in case reset signal is set will override counter &lt;= counter + 1 assignment.


  Would the compiler turn the initial assignment into a conditional or first increment the counter, then reset to 0?


Most probably it will be realized as logic with register counter update source select signal.


  If this is executed sequentially, how are these sequential relationships represented in hardware?


No not executed. Verilog is not a programming language, it is describing hardware - electronic circuits. Thus this code you wrote will be converted to logic elements and registers, not to opcodes to execute.

The order of statements in always block are treated by Verilog compiler sequentially. Two examples

always @ (posedge clk) begin
  counter &lt;= counter + 1;
  if (reset)
    counter &lt;= 0;
end


with counter &lt;= 0 overriding counter &lt;= counter + 1 if reset is 1;

always @ (posedge clk) begin
  if (reset)
    counter &lt;= 0;
  counter &lt;= counter + 1;
end


with counter always ending with counter &lt;= counter + 1 because this statement appears after previous conditional statement. I think compiler must throw warning for this code because it must see that previous statement is never in effect.

Even more, this statement order in always is a feature, and you can use it to your benefit having some default action on the register (like in your case increasing register value), and overriding actions in specific circumstances (like in your case - resetting this register).