Verilog "Tick" Generation; Concern over hold time?
There is generally no hold time problem with this approach. What your simulation doesn't show is that there is actually a significant delay from the rising clock edge to the rising/falling edge of the tick signal. If you incorporate this delay into your simulation you'll see that the tick signal doesn't change at exactly the same time as the clock and there is no hold time problem.

This is a good design style, by the way. Most FPGAs have dedicated resources for routing the clock and it's much better to generate these "tick" enable signals than to try to create a gated clock.