How do I setup entity for a 1 to 2^n output demux with n select lines using VHDL?
What function you want to give to Sel signal? 

If this is a top level module you can use package and calculate your constants there as following:

library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;

package dmux_const_pkg is
    constant IWIDTH : integer:= 3; -- for example
    constant SWIDTH ; integer:= 0;
    constant OWIDTH : integer:= 2**IWIDTH; -- 2^3
end package_name;


and include it to your top module as: use work.dmux_const_pkg.all; and in module declaration you can use the constants:

entity DEMUX is
-- Map input, output, selection and enable signal ports
port(
   Inp : in std_logic_vector(IWIDTH-1 downto 0); -- Input pin
   Ena : in std_logic; -- Enable pin
   Sel : in std_logic_vector(SWIDTH-1 dwonto 0);--How to set select lines?
   Oup : out std_logic_vector(OWIDTH-1 downto 0)--How to set outputs?
);
end MUX;


If this is not a top module you can declare all widths in generic and calculate it in up-to-this module:

entity DEMUX is
-- Get the size of an integer
generic(
    IWIDTH : integer;
    SWIDTH : integer;
    OWIDTH : integer
);
-- Map input, output, selection and enable signal ports
port(
   Inp : in std_logic_vector(IWIDTH-1 downto 0); -- Input pin
   Ena : in std_logic; -- Enable pin
   Sel : in std_logic_vector(SWIDTH-1 dwonto 0);--How to set select lines?
   Oup : out std_logic_vector(OWIDTH-1 downto 0)--How to set outputs?
);
end MUX;


Top-level module:

entity top_level_module(
...);
end top_level_module;
architecture arch of top_level_module is

constant DMUX_IWIDTH : integer := 1;
constant DMUX_SWIDTH : integer := 0;
constant DMUX_OWIDTH : integer := 2**DMUX_IWIDTH; 

component DEMUX is
generic(
    IWIDTH : integer;
    SWIDTH : integer;
    OWIDTH : integer
);
-- Map input, output, selection and enable signal ports
port(
   Inp : in std_logic_vector(IWIDTH-1 downto 0); -- Input pin
   Ena : in std_logic; -- Enable pin
   Sel : in std_logic_vector(SWIDTH-1 dwonto 0);--How to set select lines?
   Oup : out std_logic_vector(OWIDTH-1 downto 0)--How to set outputs?
);
end component DEMUX;

begin
    DMUX: DEMUX
    generic map(
        IWIDTH =&gt; DMUX_IWIDTH, 
        SWIDTH =&gt; DMUX_SWIDTH, 
        OWIDTH =&gt; DMUX_OWIDTH
    ) port map (
        ...
    );
...
end arch;