systemverilog structure initialization with default = '1
Yes, it is legal SystemVerilog. Refer to IEEE Std 1800-2012 &sect; 10.9 Assignment patterns

my_struct s = '{default:'1, c:0}; is equivalent to my_struct s = '{a:16'hFFFF, b:16'hFFFF, c:16'h0000};
my_struct s = '{default:0, c:'1}; is equivalent to my_struct s = '{a:16'h0000, b:16'h0000, c:16'hFFFF};

Your version Vivado might not have implemented the default:'1 feature yet or it could be a bug in the simulator. Try to run the latest version.

Try default:16'hFFFF or default:-1 as possible work around.