Can SDA go low by changing SCL from high to low
The code you show makes no sense.  There is no reason SDA is required to go low after some number of SCL pulses.

It's not clear what you are trying to do, but low level IIC master code should never sit in a infinite loop.  If it does, that's really bad programming.  Since the master controls the bus, there is really nothing it should have to wait for.  The only exception is when any of the slaves can do clock stretching.  In that case there should be a timeout.  After that, the code should try to clear the bus, then return with error.

Note that if there is no slave out there, you got the address wrong, or the slave didn't properly receive the address byte, it won't ACK.  However, whether ACK or not, there is nothing to wait on by the master.  The ACK bit is one bit time in length, with SDA either being high (NACK) or low (ACK).

One way or another, you need to use competent low level IIC routines, now what you show.