Why data buses should support 1024 bits, when processor are working with 64bits?
The internal ALU width of a CPU might be 32 or 64 bits, and this represents the amount of data that can be processed per CPU clock cycle. On a modern processor, the CPU(s) are running at clock speeds of several GHz. If each operation involves 1-2 input operands and a result, this represents a raw data bandwdith of tens of GB per second.

Processor chips have internal memories, called caches &mdash; often in several levels, that handle much of that raw processor bandwidth, taking advantage of the fact that data tends to be reused. Caches are used as buffers for the contents of external memory, and so data frequently needs to be transported between the caches and the external memory.

The external memory interface runs at a much slower rate than the processor core, usually by a factor of about 10 (i.e., hundreds of MHz). In order to have as much bandwidth as possible over this interface, burst transfers are used to transfer entire cache "lines" at a time. Since the ability to adderess individual words within an external transfer is not important, it makes sense to make the data bus as wide as practical in order to minimize the number of clock cycles required to complete a burst transfer.

An external bus of 1024 bits (128 bytes) will be able to transfer 1kB of data in 4 clock cycles (DDR). If the bus is running at, say 500 MHz, this represents a raw bandwidth of 128 GB/s, which makes it a good match for a multi-core processor.