1 Byte Register broken into 2 Nibble outputs not working VHDL/ModelSim
In your simulation, you forgot to map LowNibble.

This:

port map(Clk=&gt;Clk,
    LiN=&gt;LiN,
    EiN=&gt;EiN,
    Din=&gt;Din,
    HighNibble=&gt;HighNibble);


should be

port map(Clk=&gt;Clk,
    LiN=&gt;LiN,
    EiN=&gt;EiN,
    Din=&gt;Din,
    HighNibble=&gt;HighNibble,
    LowNibble=&gt;LowNibble);