Does this timer circuit make sense?
I would suggest looking at a 74HC164 shift register as an alternative to the 4017.  Every time the clock goes high, the "and" of the A and B inputs will be copied to the first data output at the same time as each of the other data outputs grabs the state of the one before.  The chip also has a "clear" wire which, when driven low, forces all the outputs low regardless of the state of the clock.

If you use such a chip with A and B strapped high, then on power-up or when /CLEAR is hit, all outputs will go low.  Then when the first clock pulse arrives, the first output will go high.  The second clock pulse will cause the second output to go high, etc. up to the eighth.  If you need more than eight outputs, you can add any number of additional chips; tie the A and B inputs of each additional chips to the last output of the previous one.

For example, using this approach you could if desired use two such chips and hit them with a clock once per minute, thus providing a 15-minute readout in one-minute increments.  Or, if you like, you could use four chips and get the readout in 30-second increments.