How gate voltages are established to turn on mosfets?
The circuit of interest is a simple regulated cascode circuit, the NMOS variant is shown below.



If T3 doesn't conduct, the voltage at the drain of T3 will rise and T2 will deliver more current therefore the drain voltage at T1 increases so that the gate voltage of T3 increases, too. In case the gate voltage of T3 is too high, the feedback loop will cause a reduction.

This feedback action leads to a stable biasing voltage.