LTSpice: active load current generator soft saturation
If you look in the manual at LTspice &gt; Circuit Elements &gt; I. Current Source you'll see this first passage:


  This circuit element sources a constant current between nodes n+ and n-. If the source is flagged as a load, the source is forced to be dissipative, that is, the current goes to zero if the voltage between nodes n+ and n- goes to zero or a negative value. The purpose of this option is to model a current load on a power supply that doesn't draw current if the output voltage is zero.


(emphasis mine). If you simulate the circuit without the load flag, you'll see that the linear ramp current causes the voltage to drop below zero. This means that around that point, LTspice will decide that the voltage across the load (the current source) drops to zero and that cannot happen, so it will try to modify the ramp in such a way that the voltage never reaches zero, or barely makes it, which would mean the end of the road.

If you increase the simulation to 10s. you'll see something like an asymptote, but not reaching zero. That's, most probably, the internal, unseen limit that LTspice imposes in order to avoid going below zero.