TUSB2046B signalling but not enumerated
Hubs must be (at least) full-speed devices, so the 1.5 kΩ pullup must be on the D+ line.

The crystal can be used at any speed; the datasheet says:


  When TSTMODE is low, the output of the internal APLL circuitry is selected to drive the internal core of the device. […]
  the TUSB2046x can use a 6-MHz crystal input. […]
  An internal PLL then generates the 48-MHz clock used to sample data
  from the upstream port and to synchronize the 12 MHz used for the USB
  clock.