Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?
Since the clock will only ever be used a relatively long time before and after the chip select changes state, I'm using them both in the sensitivity list with the chip select being essentially an asynchronous set...


Yes, that's fine. But there are no guarantees. If the SPI master violates the setup/hold timing of CS with respect to CLK, there's nothing you can do about it.


  Is synthesis of code like this vendor-specific?


No, not normally.


  Are VHDL sensitivity lists handled in a markedly different way?


The syntax is different, but in the end, they both represent the same hardware.