VHDL: code warning problems
One of your major problems is in test.vhd. You have no declaration at all for you entity. There are no inputs to that block, nor outputs. test.vhd is all on its own. It is bad practice to not have an entity declaration. I am surprised that it even synthesized.

What it looks like you are trying to do in test is to create a new clock. If that is what you are doing, you are going about it wrong. The best practice for splitting a clock is to use a register and a counter. When the counter reaches its max, have it change an intermediate signal, something not called clock. Maybe name it half_clock or my_clock. 

signal my_clock : std_logic := 0;
signal counter, counter_next : natural := 0; --use a type where addition is easy

process(clk)
begin
if(clk'event = '1') then    --clk is the board clk. My FPGA runs it a 50 MHZ
    counter &lt;= counter_next;
    counter_next &lt;= counter_next +1;
    if(counter = MAX) then   --insert your max counter number into MAX
        counter &lt;= '0';
        --toggle your my_clock signal here
    end if;
end if;
end process;


This sudo code should save you from your gate clock warning.

As for the gated latches, make sure you have covered every case possible. Remember that with std_logic there are 9 different possibilities. Always have an else case that covers the un-enumerated cases. The keyword 'others' is very useful in this case.

Also, what set of tools are you using and what board?