Arithmetic Division in Verilog
You are correct with the guessing the for loop.

The for-loop logic is huge when it after it static unrolls. With your current code, you cannot handle the worst case scenario where n=1023. To cover this with your current code you'd need a for loop with 1024 iterations.

Instead of a up counter, you can use a down counter and only examine a slice of the array, where the index represents lsb of the array slice. For example:

for (i=9; i&gt;=0; i=i-1) begin // lsb index of the slice
  if (out[i+:11] &gt;= cnt) begin // 11-bit slice compare
    out[i+:11] = out[i+:11] - cnt; // 11-bit slice subtraction
    avg[i] = 1'b1; // 1-bit assign
  end
end


This for loop unravels to 10 iterations (9 to 0), each iteration only looks at a 11-bit slice of out and only one bit of avg. You might not be familiar with the +: operator. It is a bit-slice operator introduced in IEEE Std 1364-2001. Left side if the start index (dynamic is allowed) and the right side is the bit with offset (must be a static constant). You can read more about it here.

Since it is a count down, we can can safely assume (proven mathematically) the upper bits of the slice are zeros and we will never have underflow with the guarding if condition. So we now have ten 11-bit subtracters each with 1-bit assigners which is much smaller logic then the original 642 (should be 1024) 20-bit subtracters each with 10-bit adder.

Few other suggestions:


Use ANSI style header (supported since IEEE Std 1364-2001). It is few lines of code and thereby less prone to typos and copy-paste mistakes.
Separate the synchronous logic and combination logic. This does mean declaring more signnals, but generate gives you better control on what is a flop and what is comb logic. It also follows best practices. Your for loop should exits in the comb logic. 
Use non-blocking assignments (&lt;=) in your synchronous logic block. This follows best coding practices and prevents flop-to-flop race conditions in simulation.
out can be simplified to a 10-bit register, assuming you did suggestions 2 &amp; 3. This is because we know the upper bits will always be zeros, so we can save 10 flops.


proof of concept: with a simple SystemVerilog testbench here:

module averager( // ANSI style header
  input              clk, rst,
  input [9:0]        n,
  output reg [19:0]  sum,
  output reg [9:0]   cnt,
  output reg [9:0]  out, // was [19:0]
  output reg [9:0]   avg
  );

  reg [19:0] next_sum, next_out;
  reg [9:0]  next_cnt, next_avg;

  integer i;

  always @* begin
    next_sum = sum + n;
    next_out = next_sum;
    next_cnt = cnt + 1'b1;
    next_avg = 10'b0;

    for (i=9; i&gt;=0; i=i-1) begin // lsb index for slice
      if (next_out[i+:11] &gt;= next_cnt) begin // 11-bit slice compare
        next_out[i+:11] = next_out[i+:11] - next_cnt; // 11-bit slice subtract
        next_avg[i] = 1'b1;  // 1-bit assign
      end
    end
  end

  always @(posedge clk) begin
    if (rst == 1'b1) begin
      sum &lt;= 20'b0;
      cnt &lt;= 10'b0;
      out &lt;= 10'b0; // was 20'b0
      avg &lt;= 10'b0;
    end
    else begin
      sum &lt;= next_sum;
      cnt &lt;= next_cnt;
      out &lt;= next_out[9:0]; // only assign lsb
      avg &lt;= next_avg;
    end
  end

endmodule


If you still experience area issues or performance is not good enough, then you should pipeline your design and/or seeing if there are there is dedicated divider+remainder module defined in your FPGA data sheet that you can instantiate.