Serial Wire Debug (SWD) Enumeration
The same technique of opportunistically scanning pins on a device can be applied, however the scanning sequence will be significantly slower - an SWD target is silent until it receives a valid reset/READ_ID sequence (and potentially the JTAG/SWD switching sequence for a multi-mode target). This sequence is ~80 bits.

In addition, there is nothing directly comparable to the JTAG scan chain or instruction register which you might want to discover - just the AP address space (255 slaves), and the 2/4GB debug memory space provided by each MEM-AP attached to the DAP. There will be a ROM table to declare debug components, but nothing forces a device to fully use this.

You can probably gain most from knowing that both of the SWD pins are (by default) inputs, with a pull-up on SWDIO (or as suggested in the comments, tracing the tracks to potential header/probe footprints).