Question about SR latch timing
The time it takes for the power supply voltage to rise is much, much longer than the propagation delay of the gate outputs. So, both gates are more or less in the process of powering up at the same time. Their behavior during this period of time is undefined and generally unpredictable. If the inputs to the latch are for the HOLD condition (00 in your case) then the initial state of the latch is unpredictable. Having said that, if you build one latch circuit that particular circuit might wake up the same way every time but that doesn't mean that the next latch you build will behave similarly.