What are the CPU activity steps for the fetch-decode-execute cycle
The "AVR CPU Core" section of Atmel's part datasheets has some information on the AVR microarchitecture. (Page 12 of the ATmega640/1280/1281/2560/2561 datasheet, for instance.)

In brief, though, the steps you've written out here are typical of a von Neumann architecture. The AVR's Harvard architecture uses separate memories and buses for code and data, and pipelines instruction fetch so that there is no need to "wait for memory" to load instructions. (Indeed, the AVR will run most non-memory instructions in a single cycle.)