Reset signal for fpga evaluation board
With an FPGA you can make use of the fact that your flipflops will initialise to a known state and create an internal synchronous reset signal which you can "and" with the external one.

When using an external reset, make sure that you synchronise it to the internal clock (with a different synchroniser for each clock if you have more than one) otherwise you may find that your logic comes out of reset in weird ways.  This is because the signal will have different delays to different parts of your circuit and if the reset button is released just before a clock edge, some parts of the FPGA will see it (as the reset signal made it to them before the clock signal) and other parts will see it one clock cycle later (as the reset was slightly delayed and therefore missed the clock edge).