Verilog style: one large always block vs multiple small always blocks?
Without the use of non-blocking assignments, the multiple always block style has race conditions. There no way of knowing in a clock cycle whether counter has the previous or updated value. In the single always, you must write your code in a specific flow order. You should be using non-blocking assignments to any valuables that are read by other block to prevent race conditions. 

Using multiple blocks is likely to make your code more readable, but the only advantage I can think of for combining then into a single block is when you have common expressions and conditional statements. Your reset example is simple, but you don't want to repeat large case statements as that makes maintenance more difficult.