Verilog assigment question
First of all, that's not an array. That's a bus i.e. a bundle of wires. So, input [2:0] would be a 3-bit bus.

Assigning it to 0 would not make much sense as it is an input, not an output. However, if you're assigning any other wire, you need to see what the bit pattern of the number being assigned is e.g.

wire [2:0] B = 3'd6;


That would assign the bit pattern 110 to the bundle of wires, B.

B[2] would be 1;
B[1] would be 1;
B[0] would be 0;