High Frequency Characteristics of Solder-Filled Vias
If a via gets plugged with solder, does this destroy its ability to pass high frequency (RF noise) currents?


No. In the high frequency regime, the current tends to flow on paths that minimize the inductance of the loop formed by the signal current and the return current. This means that current through the via will be flowing on the outer surface of the via, not the inner (hollow) surface. 

As eye candy, I offer this HFSS simulation of a via structure I did a while back, with surface current density plotted (f = 5 GHz):



I was going to use this simulation to make my point, but realized I have modeled the vias as being solid metal anyway. This is common practice in signal integrity EM simulation as far as I know. 

Here's a view of the ground currents in the same simulation as above:

Again the currents are concentrated on the outer surface of the via, near the signal currents that they return.

And here's a view that shows the underside of the ground planes:

This shows the return currents doing just what you imagined in your drawing: flowing around the edge of the antipad for the signal via and then to the nearest ground via.

One thing that is not quite right in your drawing is you seem to show the current flowing on the top side of the signal trace, where in a high frequency situation it will mainly flow on the bottom side of the trace.

To respond to the specific questions you added,


  This image below is the typical trace to via to trace. So according to the discussion, the current travels on the outside of the via. Since current enters the trace from the top (by means of a component lead). Then is the drawing below accurate in that the current must wrap around the edges of the trace to get underneath it in order to reach the outside surface of the via? 


Yes, but it will do so near the component lead, and flow mainly along the bottom side of the trace, so as to minimize the inductance of the trace-return loop. It won't wait until it gets to the via to move around to the bottom of the trace.


  But then consider the scenario below where current is dropped into the middle of a large plane via a wire or component lead. ... I usually run into this in power circuits when I have large current carrying traces that are essentially planes. The planes often connect to planes in other layers to carry the current in parallel.


In a power circuit, you hopefully don't have much RF current running around to begin with. At 3.5 MHz, a typical 1 oz copper layer is only one skin depth thick, so substantial RF currents will be able to penetrate the plane. At lower frequencies, skin depth won't play much of a role. In any case the inductance of the wire will prevent it being very useful for supplying high frequency currents. You'll want to bypass your higher-frequency currents near where they're generated rather than try to supply them from a wire back to your power source.


  Should I be adding little "cutout holes" in the plane so that the high frequency currents don't have to travel to the edge of the plane in order to get from top to bottom?


I'd use adequate bypass capacitors rather than rely on a wire from far away to deliver high frequency currents to a power net.


  That would mean that via stitches for planes should be done close to signal vias?


Yes, if you are running a high frequency signal through a via so that its return current must flow from one plane to another, you will want to place ground vias nearby to give the return current a path to do that.