Problem with opamp stability in DC load
Besides the good PCB layout feedback (NPI) by George Herold:

You have a dominant pole compensated op-amp running open loop in your design.  You have an additional pole added to the response with R30 anc C1, or if C1 isn't installed with the gate capacitance of the FET.  If this pole is inside the open-loop bandwidth of U2 it will add phase shift and cause your whole loop to be unstable.

From the open loop gain/phase plot it looks like this amplifier has 50 degrees of phase margin and crosses 0dB at 2MHz.  Therefore a pole at 2MHz will degrade the phase margin to 5 degrees (45 degrees phase shift at the corner) and anything much lower will make an oscillator.

Unfortunately eliminating R30 may be a problem as well, as these amplifiers probably don't drive pure capacitive loads very well.  

The answer is to provide some phase lead compensation in your loop to try to cancel the additional pole you're adding.

You could try closing the loop around U2, if you can add a network that gives you some phase lead you can achieve stability. You might sacrifice some open-loop gain and accuracy that way.  

Bottom line is that you have to analyze your loop vs. performance requirements and make sure it has adequate phase margin for the job.