What to consider when come to value of capacitor selection for C2
On the left you have a signal source that is assumed to be &quot;low impedance.&quot; (Actually, very very very low impedance.) This drives the circuit through \$C_1\$, which will have a frequency-dependent impedance.

\$C_1\$ also develops a DC bias in operation that &quot;matches&quot; the
signal source to the DC quiescent bias point of the 1st BJT stage's
input. And it will be at some point important for you to see that
fact. Though for now it isn't important.

In the following I'll assume a value of \$\beta=250\$ for \$Q_1\$ and \$Q_2\$. It might be less or more. But that's the value I'm going with, below.
Your first stage is a CE voltage amplifier stage. The DC quiescent bias point for \$Q_1\$'s emitter can be computed to be about \$500\:\text{mV}\$ and therefore the emitter and collector currents are about \$1.1\:\text{mA}\$. This implies that \$r_e^{'}\$ will be about \$23.6\:\Omega\$. Odds are that there will also be a small Ohmic resistance at the emitter of about \$250\:\text{m}\Omega\$. So I'd round all this up to an AC emitter impedance (at its tip) of about \$24\:\Omega\$. So, discounting any attenuation due to \$C_1\$ and ignoring the load on \$Q_1\$'s collector (treat it as unloaded for now), I get \$A_{v_1}=\frac{4.8\:\text{k}\Omega}{450\:\Omega+24\:\Omega}\approx 10.13\$.
However, \$C_1\$ has about \$X_C\approx 160\:\Omega\$ at \$f=1\:\text{kHz}\$. The input impedance works out to about \$2.5\:\text{k}\Omega\$. So only about 94% of \$A_{v_1}\approx 10.13\$ remains, or about \$9.52\$.
The 2nd stage's DC bias point should be about the same as the first, except this one has its emitter resistor completely bypassed by \$C_3\$. \$C_3\$ has about \$X_C\approx 5.31\:\Omega\$ at \$f=1\:\text{kHz}\$. To this we can add \$C_3\$ in-quadrature impedance and get probably about \$25 \:\Omega\$ of AC impedance at the emitter of \$Q_2\$. So I get an input impedance of about \$1.8\:\text{k}\Omega\$ for the 2nd stage. (I'm mostly ignoring \$C_2\$ here.) This means about 27% of the 1st stage's output survives. So now the voltage gain is down to about \$2.6\$, before applying the 2nd stage's voltage gain.
The 2nd stage's voltage gain will be about \$190\$. So now we have a total unloaded output voltage gain of about \$A_v\approx 500\$. Those Darlington output transistors mean that it's not loaded much, so we can probably stick with that value as a rough estimate for the voltage gain of the system.

However, while those emitter followers are great at pulling upward on
the \$8\:\Omega\$ resistor, they are not so good at pulling downward.
The \$8\:\Omega\$ has to do its own down-pulling.

Anyway, that's about all there is to it.
(LTspice reports almost a voltage gain very close to the above prediction.)