Verilog: How to perform Logical operations on a vector with single bit
You can use generate construct and for loop:
genvar i ;

generate

   for (i = 0 ; i &lt;= 7 ; i = i + 1) begin
       assign enabledA [i] = en &amp; a [i] ;
   end

endgenerate

Or you can simply write:
assign enabledA = {8{en}} &amp; a ;

{} is used as replication operator here.