In Verilog, How is a 4:1 Mux made using case statements without creating a D-latch?
First, it doesn't make sense when you say you want to use to use the clock using combinatorial logic. Combinatorial logic has no memory but updating outputs only on the clock implies a type of memory being used since the output must be remembered between clock edges.

If you want your mux to follow the clock then it has to be using the clock for something.

You need to add a clock input to your mux, where every clock edge updates the mux output based on the input. As it is, your mux has no clock so it just operates whenever (whenever an input is changed) so it needs a D-latch.