any 8 bit fast adder designs
The question what makes an adder "fast" is often a technological one – are you implementing (or simulating it) for ASIC, or some specific FPGA?

In either case, you'll have elementary "building blocks" that you'll "plug together"; it's really not like your usually dealing with "AND" and "OR" components when describing a CPU design. 

As an example, take this minimal 8-bit adder Verilog module:

module add (clk, a, b, result);
   input clk;
   input [7:0]a;
   input [7:0]b;
   output [15:0]result;
   always @(posedge clk)
     result = a + b;
endmodule // add


Implemented for an ICE40 FPGA, it would look like this. Notice that the blocks here are the elementary building blocks. There's no AND/OR here – so optimizing an adder for speed with those makes zero sense:



compare that to the more abstract "general" techmap that yosys (which I'm using to generate these trees) generates:



You'll see your AND, XOR, XNOR, NAND "gate" primitives in there, but also things like AOI (and-or-invert) – which the software deems useful, because they might map to something specifically easy and compact to implement on any given architecture, be it an FPGA or ASIC cells.


So, generally, it is important to understand what logic constitutes a complex operation such as "add". However, as soon as your optimizing that for speed, size, power, you'll have to consider the actual thing that will implement that – be it an ASIC, be it something built from 74xx or be it an FPGA – and a general rule like "this is a fast implementation" cease to exist.