Gate Output as a Switch?
To expand a bit on @Barsmonster's answer, if you look at the CMOS implementation of a gate, there is a "pull-up" network of P-type transistors and a "pull-down" network of N-type transistors. The inverter is the simplest case of such a gate and it looks something like this:



When A (labeled "1" in your diagram) is set to Vss (GND), the P-type transistor turns on (and the N-type transistor turns off), and Q (labeled "2" in your diagram) is effectively connected to Vdd. When A is set to Vdd the N-type transistor turns on (and the P-type transistor turns off), and Q is effectively connected to Vss.

The current limit they are talking about is how much the N-type transistor can sink without burning up.