What operations on flash(NOR/NAND) effect Flash Program/Erase(P/E) cycles
Rethink your choice of component selection and design in a FRAM chip instead. These support much better performance than Flash because there are no long operational delays on writes and erases. FRAM chips also have endurance capabilities that far out pace those of Flash or EEPROM.

The FRAM chips that I use also support byte by byte data changing as well. This allows for the design of stored block type data in the FRAM chip to be buffered in RAM and then only needing to update specific bytes that have changed as opposed to whole blocks like in Flash. This performance improvement alone can make the serial nature of a SPI or I2C interfaced FRAM chip not bog down an application.