What is the purpose of this FET load?
Is this an active load to increase gain or something more / something else entirely?


It looks like it.

R4/5 set a nominal DC level on the gate (thanks for providing reference designators, makes this bit so much easier), setting a mean level at Q2 source. 

Q1 is a single-ended amplifier. R3 biasses its gate to ground, so it self biasses so the current through R6 equals its Vgs-th.

C6/R2 form AC feedback, setting the gain in conjunction with the input R1. As it's fed back, it has a low output impedance.

As it draws current from Q2, the change in voltage at the output feeds back via C4/C3, passing almost all of that change in voltage to the gate. The source follows the gate. The effect of this is to get a large change in source voltage with a small change in current, so presenting a high impedance. I suspect C3 is used to reduce the feedback gain to slightly less than unity, to avoid possible instability in Q2.

This sort of feedback to increase impedance is often called 'bootstrapping', a humorous reference to attempting to pull yourself up by your bootstraps.