Enable interrupt but no ISR
If there is no ISR defined, the location for the jump instruction in the interrupt vector will either be null, it may be a jump to an exception routine, it may jump to the beginning of the program, or it may contain a "return from interrupt" (e.g. RTI) instruction.

Here is a disassembly of an interrupt table for an ATMega 16 processor showing three unused interrupts vectored to a routine which handles such cases (it may just go into an infinite loop), and one legitimate vector.

  28:   0c 94 47 00     jmp 0x8e    ; 0x8e &lt;__bad_interrupt&gt;
  2c:   0c 94 5c 00     jmp 0xb8    ; 0xb8 &lt;__vector_11&gt;   // &lt;-- ISR
  30:   0c 94 47 00     jmp 0x8e    ; 0x8e &lt;__bad_interrupt&gt;
  34:   0c 94 47 00     jmp 0x8e    ; 0x8e &lt;__bad_interrupt&gt;


Which of the methods described earlier of handling a missing ISR will depend both on the architecture of the microcontroller and the compiler.  In the case of an RTI or equivalent instruction, it will immediately return to the application.  However if the interrupt is level-triggered rather than edge-triggered, then this will probably cause the interrupt to be triggered again, so you end up in an infinite loop.

I think it may depend on the architecture of the chip whether internal interrupts (e.g. a character being received by a UART) is considered level-triggered or edge-triggered. External interrupts can usually be configured as one or the other.

There is also one other case, sometimes several interrupts are grouped together and use the same vector.  This was particularly true for older processors which might have had just a couple of interrupts.  In that case, the interrupt cause was determined by polling the status of interrupt registers, which is sort of like what you propose.

But it is bad practice in any case to have interrupts in a system and no ISR defined.  Don't do it.