Accessing CPU registers while in reset using DSTREAM & DS5
DS-5 supports accessing the processor registers whilst the non-debug logic of the core is held in reset after a warm reset. This is described in general terms in the Debug Hardware Configuration Guide

For this specific use case, it depends how the boot process is sequenced to achive this internally, and if warm boot is sufficient to provide the debug access in a generic way. With the hold reset bit set, the processor state is held after reset is de-asserted, until the bit is cleared.

Promoting a detail from the comments:


  As it turns out, I had to tell DS5 to use the namespace of the debug
  hardware. This specific SoC had an AHB interface, so the command was
  prefixed as such. e.g. AHB_0:&lt; addr >