Why is D Flip Flop Positive Edge Trigger instead of a Level Trigger
No, your circuit is still a edge-triggered circuit. The pairs NAND1+NAND2 and NAND3+NAND4 lock the state of D when the clock rises from to low to high. Changing D when the clock is high (after the rising edge) does not  affect the output.

Let's start with Clk = 0, then is S=1 and R=1.

Now let D=0 during the rising edge of the clock:


The output of NAND4 will be high.
The output of NAND3 will be low, because S is still high, thus R=0 => Q=0.
The output of NAND1 is low.
The output of NAND2 is high, thus S is high, and R keeps low.


The output of NAND4 will be kept high until the clock is low again because the input connected to R is low regardless of any change on D (after the rising edge).

Please note that the functionality of this circuit relies on the propagation delay of the gates.