What is precharge in terms of Static Ram?
When the word line is asserted during a read cycle, a weak differential signal is induced on the pair of bit lines. Precharging those bit lines to the same voltage makes it possible to amplify that differential signal to a useful logic level.

As your timing diagram shows, the precharge transistors are only active for a brief time before the word line is active.

In other words, the low-level details of the internal design of an SRAM is very much an analog circuit design problem, in which the sizes of the various transistors are carefully optimized to balance the requirements for bit density, read/write speed and noise immunity.