Does CPU pipelining always imply a multicycle datapath?
Many of the old 8 bit microprocessors (before the 8086, let's say) had instructions that took more than one cycle to execute and no pipeline capability. Each instruction would go through fetch, decode, execution, and write-back phases, but each one would run to completion before the next one could start. A bit like having a highway from NY to DC and only letting one car on it at a time.

Pipelining takes advantage of the fact that you could, for instance, be using the instruction fetching logic to get the next instruction while executing the current one. This is know as instruction level parallelism, since you have more than one instruction executing at a time. Now in the highway analogy, you don't have to wait for the 1st car to arrive in DC before letting another one on at NY. This sort of thing started happening around the time of the 8086/8088. (and there were no doubt others, but I offer the 8086 merely as a reference point in time)

So, no, having instructions that require more than one cycle does not imply pipelining.

On the other hand, if all your instructions could be executed in a single cycle, there would be no advantage to pipelining, as there would effectively be no way to run different stages of different instructions at the same time. So pipelining seems to imply that instructions can be decomposed into different phases that can be parallelized.

(It's actually hard to envision what kind of instruction could be done in a single cycle, beyond a simple NOP. Even plain register-to-register transfers would require one cycle to pull the opcode into the chip and another cycle to achieve the effect.)