UART clock into receiver and transmitter
The clock coming from the generator would be (typically) 16 times the baud rate, to allow for oversampling of input data by 16x. So each bit on bus is 16 clocks.
Start bit detection logic looks for incoming start bit to start the reception of a data frame. It typically checks that too short glitches is not considered as start of frame, while long enough logic low is considered as a start of frame, and the reception of data bits is aligned to the middle of data bits.
So as per above, the generated shift clock would load in data bits from middle of each bit.
Parity checking would make sure that when parity is used, a parity bit that matches the data and parity settings is received, otherwise a parity error is signaled along with the received byte.
Stop bit detection would check if the expected stop bit of a data frame is idle, otherwise there is something wrong with the reception and the received byte is signaled with framing error.
Wake logic can wake up MCU from sleep mode when there is a frame being received.