PWM Control using Verilog problem
Compiling the information you added later the following should work:

module pwm_d
(
    input   wire    rst,
    input   wire    clk,
    input   wire    [3:0] cmp_value,
    output  wire    PWM_out,
    //for debugging
    output  reg     [3:0] clk_counter
);

reg [3:0] stored_cmp_value;

assign PWM_out = clk_counter &lt; stored_cmp_value;

always @(posedge clk or posedge rst) begin
    if(rst) begin
        clk_counter         &lt;= 4'd0;
        stored_cmp_value    &lt;= 4'd0;
    end else begin
        clk_counter         &lt;= clk_counter + 4'd1;
        stored_cmp_value    &lt;= clk_counter != 4'd15 ? stored_cmp_value : cmp_value;
    end
end

endmodule


and the testbench:

module simulation();

    reg clk_x1;
    reg rst;  
    reg [7:0] counter_A;


pwm_d UUT(
        .clk(clk_x1),         
        .rst(rst),
        .cmp_value(counter_A[7:4])
    );


initial begin                                         
    rst = 0;  
    clk_x1 = 0;
    counter_A = 0;
    #50 rst = 1;
    #200 rst = 0;
end

always begin
    #1 clk_x1 = ~clk_x1;
    counter_A = counter_A + clk_x1;
end

endmodule


This way the comparsion value will only change for every new cycle. Basically the only real issue with the already tried/suggested solutions is that the compare value is changing "to fast"/ at the wrong time.

EDIT: corrected source. The module does not work for a 100% PWM (so always on) case. 
EDIT2: added testbench.