How does a Successive Aproximation ADC Handle Negative Voltages?
The only real requirement for proper operation is that the DAC in the SAR be monotonic.  So you can have a 2's complement arithmetic path as long as you have a 2's complement DAC.  That means that your binary search also has to be able to handle 2's complement.

Conversely, if you have your DAC span from 0x0000 = -15 V, 0x7FFF = 0V &amp; 0xFFFF = 15 V your counting and search math/control is much simpler.  You then need to do the conversion on the output value.

Another consideration is that the DAC may be simply a binary weighted charge redistribution structure which is inherently fast , low power,accurate and small.  These are easiest to design on a span from 0x0000 to 0xFFFF like the second scenario.

In short, it's hard to know as there are many alternatives available.  But my bets would be on the third scenario.