process timing on FPGA
There's always some propagation delay through the flip-flop. It's often called "clock-to-Q" delay.

That means your inputs are captured on the edge, and you outputs change on the same edge, but just a few nanoseconds later. This few nanoseconds delay is enough (if your flip-flops are designed with "zero hold time" as they are in most FPGAs) that the changes don't affect any downstream flip-flops until the next clock edge.

In functional or RTL simulation (which is probably what you're doing to generate your result) the delay won't be simulated as lasting nanoseconds. In VHDL, it will be a single delta cycle of the simulator clock, which  is technically no time at all. This makes it impossible to see the delay in the simulator output. Nonetheless for the simulated-as-ideal flip-flops, it is enough that the output changes don't affect downstream flip-flops.

If you do post-place-and-route simulation, it should be able to include appropriate delays so you see these effects clearly, at the cost of increased simulation effort.