In an n-channel JFET, why isn't the formation of depletion layer symmetrical?
why isn't it symmetrical?


Take a look at this: -



Because the drain is more positively biased than the source, the depletion around the drain end of the device has to be "more" for any given gate voltage. More reverse bias equals bigger depletion layer. Clearly the picture isn't perfect because there will still be a depletion layer between gate and source but hopefully you get the general idea.

This is probably a more accurate picture: -