What does low-impedance mean in the CMOS inverter circuit?
Mosfets can be used as switches.  In a cmos buffer one of the switches is to Vdd and the other is to Vss.  A switch has two states; open or high impedance; or closed or low impedance.  So when output of the cmos buffer is high, the switch to Vdd is closed.  We can tell that this is low impedance by adding a load and seeing the effect.  At no load the output will be Vdd.  If we add load up to the Ioh specification, the output will stay close to Vdd indicating a low impedance path to Vdd.  Similar for low to Vss.