Do If else have priority in verilog?
An if-else construct infers a priority routing network. Following example is taken directly from a verilog book :

if
 (m==n)
r = a + b + c ;
else if (m > n )
r = a - b ;
else
r = c + 1 ;

The circuit is as shown :



As you can see, the outermost if is given a priority in the sense that it is routed first if a match is found, bypassing others.

Ref : Fpga prototyping by verilog