How does an "if" statement and "always@" statement work in Verilog?
You aren't clocking the stack. That means that every simulation instant that the always block is triggered will cause a write. You are triggering the always whenever write is high, and that occurs for 3 time units, so I'd expect that statement to cause 3 writes. I don't know why you see 7, but more than 1 makes sense.

It's almost always better to use always @* instead of an old-fashioned sensitivity list.

Try putting a semicolon after the pound delays. I forget what a pound delays on the lhs of an assignment does.