Using CCM (Core Coupled Memory) in STM32F4xx
Let me point you to appnote AN4296 (for STM32F3). It talks about CCM in detail. It makes the distinction between Harvard and Von Neumann configurations.

The CCM is intended exactly for executing code at maximum speed. That may be interrupt handlers, but also ordinary functions.

There's a bus matrix. Both the CCM and ordinary SRAM have connections to data and instruction busses. The CCM has no connection to DMA because it's intended for code, which isn't ever supposed to be handled by DMA. It also features per-page write protection.

The thinking is that the core can fetch code from CCM while fetching data from the other SRAM at the same time. Different "busses" are used in parallel, giving you the best performance. If you fetch code and data from the same memory (either), it'll be slower because of contention.

Some STM32 have a thing called Adaptive Real-Time (ART) Accelerator. That's a cache on top of flash so you can execute "from Flash memory, with 0-wait states".

Even more recent STM32 (F7) have actual L1 cache on top of that.