Connecting the following structure of multipliers and adders in an elegant way in verilog
A likely reason is your declaration of w. You have declared it as:

wire [N-1:0] w [1&lt;&lt;ADDER_DEPTH][ADDER_DEPTH+1];

The declaration of the unpacked dimensions ([] after the name) is incorrect. This should be declared as:

wire [N-1:0] w [0:(1&lt;&lt;ADDER_DEPTH)-1][0:ADDER_DEPTH-1];

Otherwise, your parameterisable structure looks fine. Similar to some of the comments, I would consider splitting w into two separate arrays for clarity, i.e. w_mult_add and w_add_add, but that would just be personal preference.