Feedback signal consumed in VHDL
This depends on your netlist.

You have a glitch (should be on S) somewhere, which propagates through S1 and is already compensated for the Q1 but not the Q2 at the time it reaches the latch implementation.

Regarding that beautiful latch:

Since you tag with Xilinx, you're probably synthesizing for FPGA's. These don't have latches but will generally infer a flip-flop with a multiplexer somewhere. That's in case of an RTL latch description though (for example a variable or signal that is changed on a clock flank but not reset). In order to try and conform to the delay nonsense, some tools will try to brute force this with buffer-LUTs. I'm not familiar enough with ISE (which you also tagged) anymore to know what its strategy will be there.