How to simulate ~1ms long power interruption
Your load likely has decoupling caps which must be charged very fast due to contact low R and low ESR of load caps.

Thus Ic= C * ΔV/Δt= ΔV/(R+ESR) for decaying duration Δt.  This can be many Amps if available from 15V supply caps.

So the real task is how to simulate  a 10m Ω typical contact with random interruptions from 10us to 20 ms that simulate typical contact bounce with aging contacts.

You are correct to use a FET . It can be a high side or low side (-) voltage switch around 10mΩ rated at some Vgs like logic levels you plan to use.  Nch FET for low side , Pch for high side rated for your logic level or >2.5x Vgs.

How you mix pulse noise with the DC step voltage depends on your ingenuity and rigor as a Test Engineer . First there should be explicit design specs or some unconditional practical limit. Second you can inject noise with repeatability or random pulse pattern. 3rd you should NOT limit yourself to one condition and search for the worst case.  You can synthesize patterns with a shift register and variable clock with preset and clock inputs and this gives a wide range using a pot controlled Schmitt Trigger Relaxation Osc clock and a PISO register with dip switches and can be rigged up in a couple hours to switch between 15v source and load. If you are using a Pch then a transistor common emitter or CD4xxx 15V logic is needed.

Try to keep power &amp; gnd wires twisted to reduce EMI from surge current or use coax. and make it small neat and professional looking.