Benefit of (logically/virtually) separate I/O and memory bus
My interpretation of what you are describing is to simply sub-divide the address space into two halves - one half for IO and one half for memory.  You're not creating two separate busses there, but only one that is used for two logically different tasks.

While that can make decoding of the address bus simpler, it doesn't improve performance at all.

Many embedded microcontrollers use an architecture known as Modified Harvard Architecture.  In this you do have a number of different physical busses, each with its own purpose - one for RAM, one for ROM, maybe one for IO.  These have the big advantage that it is possible to access different things at the same time which you can't with a single sub-divided bus.  It does make programming more complex though.