Generating frame buffer in FPGA
A framebuffer is basically a big chunk of RAM. Usually far bigger than an FPGA has internally.

So you will need:


Some RAM (your board may have it on-board, otherwise you will need to find some way of wiring it in) - enough to hold your framebuffer at your desired depth
Code to interface to your desired RAM - that code depends on your RAM technology - DDR needs a special DDR driving IP, SRAM is simpler (though more expensive) and has a much more simplistic interface. The ideal RAM, though, would be dual-port VRAM.


Your VGA code reads from an incrementing address pointer in the RAM to display it on the screen indexed by the pixel clock and scan line (those are your COLUMN and ROW values). Only the visible portion of the screen needs to actually read from RAM (the bit that is a coloured square at the moment).

To get data into the framebuffer you then need to write into the RAM. The location in RAM for a pixel is the same as read from for that location on the screen. So if you have a display of 640x480 with 8-bit depth, which is a RAM size of 307200 bytes, the pixel position (200,100), as offset from the top-left corner of the visible area of the screen, would be 200 + (100 * 640) - that is, 100 rows of 640 pixels to get to the start of the 100th row (0-based) plus another 200 pixels to get to the 200th pixel within that row.

Reading from and writing to the RAM at the same time is not possible. So it is up to you to decide how and when you interleave the writes into the reads. You have little control over when it's read from (the VGA interface determines that for you by the pixel clock) but when you write is entirely up to you. Many systems will limit writing to the blanking period only. Some which are fast enough can interleave the writing in between reading of successive pixels. You need very fast RAM for that though. This is why I recommended dual-port VRAM (which is rare and expensive), which allows you to read and write at the same time and it deals with the interleaving for you (the "dual-port" literally means you get two bus interfaces to it).

If you have some block-RAM in your FPGA (Spartans often do IIRC) then you can use that for line-buffering - that is, in the horizontal blanking period of a line you read all the data for that line into fast internal RAM. That then frees up the external RAM for writing to. The VGA then outputs from the internal RAM for the rest of that line. Of course, your RAM has to then be fast enough to read the entire line's worth of data into BRAM in the short blanking period time.

You might want to take a look at the Gameduino for inspiration and examples.