Building a framebuffer
You'd have to set up synchronization registers across the clock boundaries. And as the clocks are out of phase with each others, there's always the possibility of metastability, but I suppose the FPGAs are not very susceptible to metastability.

I would suggest to run your CPU at some "easy" multiple of 9 MHz, perhaps 9 x 4 = 36 MHz or 9 x 8 = 72 Mhz and divide the 9 MHz clock to the LCD from there. It would be much easier and reliable. The clocks would be phase aligned with each other; no possibility of metastability, ever, and normal synchronous design rules could be used. I'd suggest that you consider it.