One-clock increment operation in a three-bus CPU architecture
Turns out I missed a crucial detail in the accompanying text, and the registers are indeed composed out of two (master-slave) sub-registers:


  The Use of Master–Slave Registers 
  
  Note that the contents of the PC are
  incremented within the same clock pulse.  As a direct consequence, the
  PC must be implemented as a master–slave flip–flop; one that responds
  to its input only during the positive phase of the clock.  In the
  design of this computer, all registers in the CPU will be implemented
  as master–slave flip–flops.