Finite State Machine, Verilog Code
First of all, when it comes to instantiating and connecting to modules, any output of the module must be connected to something of type 'wire'. You cannot assign the output to a 'reg'. 

The rule for connecting to a module is:

inputs can be fed with a 'reg' or 'wire' (includes constants)
outputs must be connected to a 'wire' (or unconnected)


When making a module it is the opposite that is true: 

an input can be of type 'wire'
an output can be of type 'reg' or 'wire'




Secondly you cannot mix blocking and non-blocking assignments in an always block. Notice how in the reset clause of the s1 register, you have the statement s1&lt;=0 - this is a non-blocking assignment. But inside the case statement you use a s1=... which is a blocking assignment. 

Use one or the other, not both. In most cases you should use a non-blocking '&lt;=' assignment as it means that if you have multiple registers being assigned in the always block they will all get assigned independently of the others. If you use a blocking assignment it means that you may find that extra logic is inserted causing things you don't intend.

For example, take these two codes:

//Code 1
reg a;
reg b;
wire c;
assign c = (a == b);
always @ (posedge clock) begin
    a &lt;= ~a;
    b &lt;= a;
end

//Code 2
reg a;
reg b;
wire c;
assign c = (a == b);
always @ (posedge clock) begin
    a = ~a;
    b = a;
end


In the first example, 'b' is a pipelined version of 'a'. This means that the value in 'b' will always be the value in 'a' but one clock cycle delayed - essentially the old value of 'a' will be clocked into 'b' on each clock edge. What this means is that the variable 'c' will in this example always be 0.

In the second example, 'b' and 'a' are always the same. The value '~a' is assigned to 'a' on the clock edge, but because the assignment is blocking, it means that the value to be assigned to be should be determined by the synthesiser after it calculation for 'a' has been done. So you end up with the new value that is going to be assigned to 'a' will also be assigned to 'b'. So in this example the variable 'c' will always be 1. (Note: in the synthesized code a and b will still be assigned on the same clock edge, there is no delay, essentially the example is identical to writing b &lt;= ~a;)

Notice how one tiny change can result in completely different behaviour.



Edit:

Now that you've modified the question, most of the above has been corrected. But there are still the things that @Greg rightly noted in the comments section to fix.

You have the issue that you still haven't connected your JK flip flop module up correctly. In your code you instantiate your flip flop as:

jkff i_jkff
( 
.s0(ss0),  
.s1(ss1)
);  


But you declare the module as:

module jkff(
    input clk, r, x1, x0,
    output reg s0,
    output reg s1
);


Notice how the module declaration has 4 other inputs that you haven't connected in your instantiation. How is your module supposed to do anything if you don't give it any input?



Also, in you JK flip flop module you have logic for the output register s1 - an always block which assigns it a value on each positive clock edge. BUT you haven't got any logic for the output register s0. So why do you expect s0 to do anything at all?