FPGA BRAM initialization
It's definitely possible to infer block RAMs directly from HDL.  Depending on the size and the configuration, the toolchain could place them in block RAM or in distributed RAM.  

Here is a very simple verilog example:

module rom
(
    input clk,
    input [3:0] addr,
    output [7:0] data
);

reg [7:0] mem[2**4-1:0];
reg [7:0] output_reg = 8'd0;

initial begin
    mem[4'h0] = 8'h00;
    // ...
    mem[4'hF] = 8'h00;
end

assign data = output_reg;

always @(posedge clk) begin
    output_reg &lt;= mem[addr];
end

endmodule


I have used similar code in both the Xilinx and Altera toolchains, and in general both tools will infer the proper RAM components.  This also works for RAMs.  And it can be used to store values in a look up table that are computed at synthesis time, though Quartus has historically had some serious issues with this, namely with doing floating point/trig at synthesis time.

Example of precomputing ROM contents in verilog: https://github.com/alexforencich/verilog-dsp/blob/master/rtl/sine_dds_lut.v