Xilinx Coregen FIFO as ZeroDelay model
Probably not, but it's easy enough to add a register to your testbench that captures the output of the FIFO only at the relevant clock edges, and monitor the output of THAT for changes.

In addition, this would be the first step toward building a completely automatic monitor for that output that doesn't rely on visual inspection. As your design grows, you will appreciate the value of such monitors.