Phase margin analysis of a [diy] PMOS LDO [with LTspice]
I think the top graph does indicate exactly where instability occurs: -



The phase angle is zero degrees and the gain is still +45 dB. In other words it's "gain margin" that is causing oscillation here.

The transient graph seems to indicate it oscillating at 250 kHz whereas the AC graph tells me it could oscillate at 100 kHz. This doesn't surprise me given the amount of gain margin (45 dB).

The compensated response is borderline unstable in the trough area but not quite totally unstable. I would imagine there would be a fair degree of overshoot/ringing when subjected to transient supply or load changes: -