Question on UART parity check verilog source code
I don't see any particular problem with your code as illustrated.  I would assume that either:


received_data has a 0 time glitch to a non-zero value at the clock edge.  If you know how to enable delta cycles on your simulator you can investigate that.  You have events firing.  Are any of them affecting received_data?
If your simulator behaves like Martin's and treats ^(exp) as !(exp) then your simulator is buggy.


If you run this code the first three columns should be equal

module top;

reg [3:0] a;

initial begin
   for (int i = 0; i &lt; 16; i++) begin
      a = i;
      $display("%0d %0d %0d %0d", a[3] ^ a[2] ^ a[1] ^ a[0], ^a, ^(a), !a);
   end
end

endmodule