Conversion from VHDL to sysgen block diagram
Alright, looks like I've found something you could use. You could create multiple clock domains, each having a different frequency to create your clocks. How you can do this is explained here starting on page 290. Basically you create a subsystem with its own sysgen token. I can't test this unfortunately, but you should be able to get your clock signal pretty easily. Just invert the output of a one bit register and connect it to its input. This should make it oscillate every time the system clocks. Just tune the subsystem's frequency so the resulting oscillation matches what you want to have.

I've been looking around but it really doesn't seem like xilinx sysgen supports falling edge updates. You'll have to find some kind of workaround for that.

Other than that, sysgen does not allow any asynchronous actions, and I feel its rather limited. One of my professors said it's really not an optimal tool, it's sole benefit is that its pretty easy and intuitive to work with.