Condition for negative Thevenin resistance
Let's assume that the expression "Thevenin impedance" means the impedance seen at a terminal pair ideally measuring it by applying a voltage and sensing the current. So, it's the equivalent impedance (or resistance, to simplify) seen at accessible terminals.

Part 1: some considerations on sufficient criteria and history of NIC (Negative Immittance Converter)
Part 2: example

Part 1

An ideal NIC is an active two-port which gives a negative input impedance Zin=-k*ZL, where ZL is a load terminating it at the other port. In the example below R3 is that load, whereas the usual scheme (e.g. to design active filters based on cascaded NIC stages) identifies "Node C" as output.

If expressed in hybrid parameters,

Zin = h11 - h12*h21 / (h22 + 1/ZL)

that gives two necessary conditions: h11=h22=0 and h12*h21=k.

Compensation is also possible for non-ideal NICs to become ideal NICs, so that conditions are relaxed for a non-ideal NIC, provided that compensation is added. Compensating elements are passive: simply speaking they compensate for either h11 or h22 not being zero, or both.

The NIC needs an active element, that in principle may be one among gyrators, negative immittance inverters, or controlled sources. OpAmp or transistors implementing controlled sources are the modern most common solution (e.g. negative resistance oscillators).

Stability is a known problem of NIC, especially when parasitics play a role, e.g. at very high frequency. See RADIOENGINEERING,Segovia-Vargas et al. for a recent paper on stability of NICs for microwaves.

Part2

An example of negative resistance phenomenon is the Negative Resistance Converter, that may be built around an OpAmp exploiting two facts: the use of the positive input terminal for some feedback and the OA output driving the circuit so that the voltage difference between its input terminals is so small to be 0.







simulate this circuit &ndash; Schematic created using CircuitLab

Assumption1: OpAmp input currents are negligible (I+=I-=0)
Assumption2: the voltage difference between OA input terminals is zero, i.e.  V+ = V-

Applying the input voltage V_in we will see current I_1 flow through R1, given by:

I_1 = (V_in - V_B)/R1     (1)

V_B is the output voltage of the OpAmp that will adapt to 

I_2 is given by:

I_2 = (V_C - V_B)/R2     (2)

and I_3 is given by:

I_3 = V_C/R3       (3)

The objective is to determine input current I_in=I_1 by solving the above equations. Using assumption1 we say that I_3=I_2; using assumption2 we say that V_C=V_in.

We can put (3) into (2):

I_2 = (R3*I_2 - V_B)/R2     (4)

V_B is needed to replace it in eq. (1); thus:

V_B = (R3-R2)*I_2      (5)

But, also V_B can be determined from eq. (2) and (3) invoking both assumptions on OA:

I_2 = I_3 => (V_in - V_B)/R2 = V_in/R3     (6)

V_B = (R2/R3-1)*V_in     (7)

Eq (7) into eq. (1) gives:

I_1 = (V_in - (R2/R3-1)*V_in)    (8)

V_in = -R3/R2*I_in    (9)

that by definition shows a negative resistance value when the equivalent input resistance is "measured" as R_in = V_in / I_in.

Of course, a check shall be made that the OA is working in the linear region (V_B is not exceeding is capability, namely supply voltage less a margin), and that the two assumptions hold: assumption1 holds if we do not want to see negative resistance for very very small I_in currents (let's say a JFET OpAmp is satisfactory down to some nA); assumption2 depends on the open loop gain of the OpAmp, so at high frequency some deviations are unavoidable (a JFET good OpAmp might have a hundred MHz of GBW, such as AD8039 or AD8065).