Ethernet PHY Output Driver stage
Below is my guess of what a simplified driver can look like.

When [A1,A2] = 1,1, the output level is positive.
When [A1,A2] = 0,0, the output level is negative.
When [A1,A2] = 0,1 or 1,0, the output level is zero.

The output impedance is determined by the resistors, which are matched to the cable.

What is completely missing in the diagram is the slew rate control. Which I don't have much idea of how that is actually realized in an IC for this application.






simulate this circuit &ndash; Schematic created using CircuitLab