32 x 8 Register file using generate statement for D-flip flops
Flip-flops trigger when the CLK value changes (assuming your flip-flop code is correct here). Your flip-flop component,

component D_FF
    port (
        D_in    : in    std_logic;
        CLK     : in    std_logic;
        Q_out   : out   std_logic;
        QN_out  : out   std_logic   -- Q not
    );
end component;


has the CLK input tied to CLK_vals(ROW), from this line:

DFF_X : D_FF port map(WRT_DATA(COL), CLK_vals(ROW), I0(COL), QN_out(COL));


Yet the CLK_vals never change, as evident by your timing diagram, after the initial 10ns wait when it is uninitialized.

Your CLK_vals is setup here:

CLK_vals(I) &lt;= O_out(I) and CLK;


Yet neither O_out nor CLK change.

O_out stays '00100000', and CLK stays '1'

You need to have an alternating clock.  Something simple, like 

signal CLK : std_logic := '0';
CLK &lt;= not CLK after 5ns;


I have read both sides of the fence as far as needing to initialize values, you can read a little bit about that here. But it would get rid of those ugly red Us

https://stackoverflow.com/questions/6363130/is-there-a-reason-to-initialize-not-reset-signals-in-vhdl-and-verilog