How add delays to everything in Verilog or SystemVerilog outside of .v or .sv file
There is a delay_mode_unit that puts a #1 on every gate level primitive. Depending on the tool, it could be a command line option, or a compiler directive. 

Any tool that dumps waveforms in a format other than VCD usually has a mode of dumping in what's called sequence time. This can show the order of signal changes within a single time slot. So there's no need to add arbitrary delays to move signals away from the clock edge.