Low-pass filter for digital input
Here is a circuit which only lets through pulses with a repetition frequency of less than 1KHz. 

When triggered by the leading edge of each input pulse, Monostable IC1 generates a 1ms pulse which clocks D F/F IC3's output high. IC3 is reset when the input pulse goes low again, so the output follows the input. If the frequency is higher than 1KHz then IC1 is continuously triggered and doesn't produce any clock pulses, so IC3 stays in reset.

R2, C2 and IC2B provide a short delay to ensure that IC3 is out of reset when it receives the clock pulse from IC1. 



BTW this circuit can be simplified down to just one IC by configuring the other half of the CD4528 as a basic flip-flop. Connect pins 15 and 14 to GND, pin 11 to Vdd, apply clock input (from pin 6) to pin 12, and connect the input frequency direct to pin 4 (+TR) and pin 13 (/RESET). Output is on pin 10.