DC compiler, synthesis, terminology
Drive characteristics of cells are mostly related to how much capacitance they can drive and how fast they can charge or discharge. Each cell in a technology library has look-up tables that show the relationship between the load (capacitance) and the timing (e.g. transition times). 

If Design Compiler knows what cells are driving the input ports, it performs timing analysis more accurately and inserts buffers when needed.

In case the driving cells are unknown, it's better (for timing) to define weak cells on inputs to be on the safe side. Probably the circuit will consume more area and power, but DC will perform timing analysis for the worst case.

Strengths (driving capabilities) of the cells are generally comprehensible by the cell names. For example, AND2X1 is a 2-input AND gate with X1 strength. AND2X4 is a larger and stronger 2-input AND gate. Of course, all technology libraries have their own naming conventions, mine is just an arbitrary example.