Declare queue in verilog
Queues are SystemVerilog and they are not synthesizable. Queues are intended only to be used in simulation for verification and behavioral modeling. 

If you want a queue functionality to synthesize, then you must create an fixed sized array and manage the pointer(s). 

SystemVerilog and Verilog have features only usable in simulation. They language itself does provide requirements on what should and shouldn't be synthesizable. It is up the the creator of the synthesizer to decide that it can support. Most synthesizers have very similar support (no one wants to be outdone by a competitor). But some stuff is inherently hard or impractical to synthesize. In general to be synthesizable, the definition and attributes need to be static. A queue has a dynamic size therefore not synthesizable.