what's the correct way to add counter inside flip-flop?
I learn from tutorials that the output value should be assigned for
  all combinations of input.


This is true for combinational logic, but you certainly intend to implement edge-triggered sequential elements (flip-flops).

In case you use always_ff and/or posedge clk, there is no possibility to infer latches. You will certainly have flip-flops.

always_ff @(posedge clk or negedge reset_n) begin
  if (!reset_n)
    counter &lt;= 64'd0;
  else begin
    if (clk_enable)
      counter &lt;= counter + 1;
  end
end


The always block above is safe even if there is no else condition. The counter will increment if clock_enable is HIGH, it will preserve its value if clock_enable is LOW.

The following code has the same behavior, the else part is just redundant.

always_ff @(posedge clk or negedge reset_n) begin
  if (!reset_n)
    counter &lt;= 64'd0;
  else begin
    if (clk_enable)
      counter &lt;= counter + 1;
    else
      counter &lt;= counter;
  end
end