The error "requires SystemVerilog extensions" while declaring an error
Exactly what it says: you have a two-dimensional output port which is an unpacked array.

This is a packed array: output reg [7:0] FIFO
This is an unpacked array: output reg FIFO [0:7]

Therefore your two-dimensional array is an unpacked array.

Verilog allows only packed arrays for ports.
If you want two or more dimensions you need to compile with System-Verilog.