VHDL: Signal vs Port
In this example, none and yes.

There will be one difference : the rotary_in signal will be generated one delta cycle earlier if you make the obvious change. 

If there is something else dodgy in the rest of the design; for example, assignments on a clock signal (delaying it by an unnecessary delta cycle) the two versions may show different results in simulation. 

It would be better to fix the real problem; e.g. clock signal but if you are using IP over which you have no control you may occasionally need to resort to bodges like this. Then it is better to say

rotary_a_in &lt;= rotary_a after 1 ps;


and comment why...