How to assign the same value to a bus in Xilinx ISE (Schematic)?
Since net0 is just a single wire you cannot directly attach it to the bus(7:0) because it would logically short all the bus lines together. So to be able to do what you want you will need to use a series of eight buffers. The inputs of all the buffers you wire to net0. Then the outputs of the buffer wire individually to bus(7), bus(6) .... bus(0). 

Do note that this brings up a much bigger question here. You are not allowed to create tri-state busses inside most FPGAs. This means that the idea to assign the net0 value to the whole bus does not make much sense. If indeed that is really really intended then just purge the bus(7:0) net entirely and replace it with the net0 wire.