Sending a divided clock through a non-dedicated clock pin?
Only some of the input pins are connected to the clock distribution networks inside the FPGA.

The clock routing is specialized because it supports a higher fanout, so large parts of the FPGA can use the same clock signal.

It is possible to use a regular routing interconnect as a clock, but this has so many interesting constraints on it that the compiler will generate a design that uses way too many resources, and will run slowly. When you add more logic, the compiler will generate a clock tree out of LUTs, which will reduce \$f_{max}\$ for your design, so expect it to fail timing constraints once you pick up some complexity. So the workaround will not take you very far.

So, neither of your ideas will work, the problem is on the input side, with the assignment of the clock signal to a specific input pin.