Level shifted PMOS driver operation
Yes there will be a very short time that Q2 will see high power.
The length of time depends on the MOSFET gate capacitance and Q2 collector current. As long as this time is short relative to the PWM frequency it should not be a problem because the average power will be low. Also I think the amount power will be proportional to the charge on the gate of the MOSFET, so a lower Q2 collector current would mean lower peak power, but take longer to discharge the gate so the total power would be the same. In the article you cited the author actually gives a formula for the total power consumption but it does not seem to include the power dissipation in Q2.