VHDL: Converting from an INTEGER type to a STD_LOGIC_VECTOR
As others said, use ieee.numeric_std, never ieee.std_logic_unsigned, which is not really an IEEE package.

However, if you are using tools with VHDL 2008 support, you can use the new package ieee.numeric_std_unsigned, which essentially makes std_logic_vector behave like unsigned.

Also, since I didn't see it stated explicitly, here's actual code example to convert from an (unsigned) integer to an std_logic_vector:

use ieee.numeric_std.all;
...
my_slv &lt;= std_logic_vector(to_unsigned(my_int, my_slv'length));