Verilog Code test bench problem
According to the section &quot;12.3.1 Port definition&quot; in one of the revisions of the Verilog standard, a module includes [ list_of_port_declarations ] ; with the following syntax:
list_of_port_declarations ::=
      ( port_declaration { , port_declaration } )
     | ( )
port_declaration ::=
      {attribute_instance} inout_declaration
     | {attribute_instance} input_declaration
     | {attribute_instance} output_declaration

That means that for your design the ports declaration should be the following:
module test1
(
    input logic A,B,C,D, 
    output reg Y 
);