Sorting of data from instructions ( ARM I-cache and D-cache )
The control logic records why it issued a particular fetch to a particular address, so it can do something sensible with the result. There will be a small queue of outstanding fetches (remember, fetching from DRAM may take hundreds of cycles). On a value arriving, it's written back to the part of the architecture that requested it, and the relevant part of the processor's pipeline is un-stalled.