Identifying a signal in logic analyzer pulse train
can't figure out what this "pulse train" is there for, 0xFF sequence 


Notice how that 0xFF sequence only appears each time on one of the two logic analyser inputs, which you have assigned to a pair of differential signals. Here is the first one:



Notice that the previous byte sequence (0xA0 0x00 0x00 0x10 etc.) is shown properly as a differential pair of signals i.e. opposite polarity on two logic analyser channels:



Compare those two displays. That change in the display strongly suggests that the 0xFF sequence may not be valid at all, and that you may be falling into the trap of believing the logic analyser, when it tries to decode noise or other invalid signals.

If you have an oscilloscope, then it will be easy to confirm this hypothesis, by looking at the analog voltages on both wires of the RS-485 bus, when the logic analyser decodes that 0xFF sequence on only one channel.

It is quite common, for example on a half-duplex RS-485 bus, for the bus to be "undriven" for periods of time. If the system designer did not implement "failsafe biasing" then when the bus is undriven, it is effectively an antenna and will pickup noise.

An interesting piece of evidence for this hypothesis is shown for the second 0xFF sequence:



Notice that this 0xFF sequence appears on the top (only) logic analyser channel, and is therefore likely invalid, as no opposite polarity signal is displayed on the second channel except for an initial glitch (itself interesting). However that 0xFF occurs at the same time as an apparently valid signal is shown for the lower pair of logic analyser channels - i.e. the top (undriven?) logic analyser channel may be picking-up the coupled signal coming from that second RS-485 bus, and trying to decode whatever noise it sees!

Depending on how much you know about the original system design, and how much you can change it, you may have to either ignore those invalid attempts at decoding by the logic analyser, or you could investigate adding "failsafe biasing" to each bus, to force a fixed bus state when it is undriven.

Finally: Personally, I would use a genuine RS-485 receiver for each bus, feeding into one logic analyser channel per bus, rather than connecting two logic analyser channels per bus directly to the individual RS-485 signals as you are currently doing. Those RS-485 signals swing both positive and negative, relative to the common ground. Depending on the input protection in your analyser, that might be a problem (especially the negative voltages), and/or might add unexpected loading to the RS-485 bus. It is also possible to have valid RS-485 voltages which the analyser will not detect as valid logic levels and therefore not display. Again, using a genuine RS-485 receiver does not have that problem.



Update: New oscilloscope screenshot when logic analyser decodes 0xFF:



We can see that:


Approximately equal amplitude on both wires, so not valid RS-485.
Both signals seem to idle close to Gnd, which suggests the system designer has not implemented "failsafe biasing" using resistors on the signal lines (since then the idle voltages for the two signals would be different by at least 200 mV). To improve the accuracy when trying to read only valid data on that bus, while minimising changes and their possible side-effects, trying a modern RS-485 receiver with built-in failsafe biasing would be a sensible test.
Frequency looks to be ~120 Hz so something related to mains power seems a likely source (not surprising for an antenna in a country with 60 Hz mains supply).
This low frequency explains why the bit length doesn't match the RS-485 data rate (which looks like 9600 bps in your example) during valid data transfers.
Amplitude up to around +0.7 V, so depending on the exact logic thresholds used by the logic analyser, it's not a surprise that the analyser believes it is detecting a change of logic levels, and hence something that it should decode.


This is exactly the trap that I have seen many times. Until you have used an oscilloscope to look at, and validate, the signal being used by a logic analyser, you cannot trust that what the logic analyser "decodes" is what is actually happening "on the wire".

A genuine RS-485 receiver should not report any output, with those voltages on an RS-485 interface, as it isn't valid RS-485. That would be yet another advantage of using a genuine receiver.