Model running slower than RTL in SystemVerilog
Thank you for the suggestions.
I used Questa performance profiler. There was an assertion within the testing environment which caused this. Because of the way it was written, the sequence it was asserting, started every cycle. As the time progressed, the simulation time and memory taken by this increased and it made the simulation slower. This in-turn had a knock-on effect to the model which also consumed a lot of memory. This probably gave rise to some memory swapping.
I've fixed this and we're getting a much faster peformance.