Question about sensitivity list in VHDL
Usually, the simulator cares about the sensitivity list.  But the synthesizer does not.  The purpose of the sensitivity list is to let the simulator know that a process only will change its outputs if one of the signals (A, B, C) changes.  That lets the simulator run more efficiently.  However, the synthesizer usually doesn't look at the sensitivity list; it just looks at the process's body.

If you simulate a circuit, but leave important signals out of the sensitivity list, then sometimes the simulator will give you the wrong answers.  That means your final FPGA or ASIC will behave differently than the simulator.

If you put extra signals in the sensitivity list, then the simulator will give you the right answers, but run more slowly.

So, the only thing the sensitivity list is for is to let the simulator run faster.  It's a hint to the simulator, so it can run more efficiently.  But the simulator and the synthesizer can ignore the sensitivity list, since it's just a hint.