Differential Pair Length Matching for DP83848I
Modern serial full-duplex interfaces have built-in synchronization in each direction. The protocol handshakes are asynchronous, and ACKs/NAKs can come back with delays of milliseconds. Thus the Rx and Tx channels are largely independent on the bit-interval scale. As result there is no restrictions on delays between Rx and Tx lanes, and there is no need in trace length matching between differential pairs. However the trace length within each differential pair should be matched as best as you can. 

The Intel layout checklist says, on page 18:


  The pair to pair length matching is not as critical as the in-pair
  length matching but it should be within 2 inches.


These 2 inches give plenty or room for a layout designer to avoid the unnecessary serpentine. I know this for sure in USB SuperSpeed layout, but it looks like the same holds for the Ethernet PHYs.