Linear voltage reducer
Consider this circuit:-







simulate this circuit &ndash; Schematic created using CircuitLab

Where U1 is an ideal op-amp and D1 is an ideal zener. 

The voltages on the op-amp inputs are: 

v(+) = \$V_O \cdot \$ \$ R_2 \over (R_1 + R_2)\$ \$ = V_O \cdot k\$

v(-) = 0               (\$V_O \lt V_Z)\$

v(-)   = \$V_O-V_Z \$      (\$V_O \ge V_Z)\$

For the op-amp to be balanced, v(+) = v(-). 

I think you can see there are two values of  \$V_O \$ that will satisfy the equality. 

We probably want \$V_O =\$ \$ V_Z \over 1-k\$, so we need to prevent the other solution from occurring, so the circuit will start up properly.

(It's slightly more complex because the mathematical undesirable solution above is not a stable solution, but the result is similar- the output voltage is not what you want).