What is traffic generator (while using Xilinx Memory Interface Generator)
A traffic generator in this context is simply something that generates traffic on the memory interface.

It isn't a specific thing, it could be just a counter generating addresses and read and write signals, or test patterns to run memory tests, or random numbers.

In the context of a user design, it is simply that part of the overall design which uses the MIG interface - you could view the entire rest of your FPGA design as a Traffic Generator.

One way to define your own is to build a CPU based system that needs to access memory through the MIG interface.  

As to being necessary; it's the other way around. If you don't have a Traffic Generator in your design, there is nothing that needs to access memory, so you don't need the MIG.