How fast is L1 cache of ARM Cortex-A9 in Xilinx Zynq-7000 FPGA?
The L1 latency is a question for Xilinx since it depends on the implementation, or you can measure it as referenced in this question.

For a general overview of the L1 memory system, you can check the TRM. There is a 64 bit instruction datapath, which means a limit of 2 instructions fetched per cycle. Decode is also limited to 2 per cycle. Dispatch width depends on the instruction type.

For stores, there is a 4 entry store buffer, and being OoO, the pipeline shouldn't need to stall for a store even if the address isn't ready. Loads are the most critical accesses for latency, and you ideally want to be doing 64 bit loads.

Continuous load/store IPC of 1 is certainly feasible if you are not using any registers for data processing. IPC of nearly 2 might require that you pay a lot of attention to the dependancies and ordering if your data throughput is high (rather than mostly ALU operations).