Why is modifying (by adding extra gates) clock inputs undesirable?
There are probably more reasons, but I will list three that come to mind:

As you stated, the propagation time of the gates will affect the placement of the clock edges, and can reduce timing margin of the circuit.  This may not matter with slower clocks like the few MHz you mentioned, but will matter if running in a faster system.

Second, depending on what the other inputs to the to the gates are, the gate outputs may end up being partial clock cycles, generating edges that are far removed from the expected clock edges (or runt pulses or glitches) that can clock incorrect data into the flip-flops.

And third, if the circuit design is used in a production integrated circuit, the design may be modified so that it can be tested for defects using scan test.  In this mode, the clocks of all of the flip-flops on the chip must be tied together.  Clock gating can be problematic in this case.