109 bit tree comparator with generate and for loop
The errors you are getting (g is not a memory) should point you to the issue which is that g is not correctly defined as a 2D array.

You declared your 2D arrays as:

wire [NUMBER_OF_ELEMENT-1:0][ELEMENT_WIDTH-1:0] name ;


Which is incorrect.

In Verilog, arrays are declared as:

wire [ELEMENT_WIDTH-1:0] name [NUMBER_OF_ELEMENT-1:0];


You declare the width of any element in a 2D array, then the name of the array, then the number of elements in the array after the name.