Clock source controlled by the logic that is being clocked by the source
This :
   assign clk = (freq_val=='d0) ? clk_5M : (freq_val=='d1) ? clk_10M : clk_200M
is dangerous. And wrong as you can't get clk_200M out of that but I assume that is just a typo

You must make sure that you do not generate 'runt' clock pulses. (Clock pulses which are too short high or low).

If all those clocks are synchronous and have coinciding rising edges you may get away with that. If they are a-synchronous it will not work.

Beware that your code may work perfectly in a simulation but can fail on real hardware!