Mapping address ranges in Verilog
Verilog can handle the chip select approach - the high impedance state is called Z.

However, whether synthesis can handle it depends on whether whatever you're trying to synthesize to has the necessary tristate drivers available, and whether the synthesis program knows how to use them.

Disconnecting inputs from the bus isn't necessary; just the outputs.

It worked this way back when I specialized in ASIC and FPGA logic simulation using Verilog.

Your mapping the address bus method isn't clear enough that I can say much on that.