Why does my ALU design delay outputting the results for two clock cycles since input of valid data?
If you want immediate results from your ALU, then don't use a clocked process at all:

module alu (
  input [7:0] a,
  input [7:0] b,
  input [3:0] opcode,
  output reg [7:0] y
);

  /* Decode the instruction */
  always @* begin
    case (opcode)
      4'h00 /* OR */:   y &lt;= a | b;
      4'h01 /* AND */:   y &lt;= a &amp; b;
      4'h02 /* NOTA */:   y &lt;= ~a;
      4'h03 /* XOR */:   y &lt;= a ^ b;
      4'h04 /* ADD */:   y &lt;= a + b;
      4'h05 /* SUB */:   y &lt;= a - b;
    endcase
  end

endmodule