Why do FPGA projects always take the same amount of time to compile?
With software ... if we change a single file in the project, everything does not need to be compiled again.

Only if your compilation creates intermediate files to avoid recompiling unchanged files.

FPGAs ... It should take less time to compile after the first time isn't it?

In an FPGA compile, unless you are using incremental compilation (which is a complex endeavour), then it will have to resynthesise everything all the time.
Remember that an FPGA design is not software. You are describing a physical circuit. Any changes to any part of that circuit can have knock-on effects on other parts of the circuit, due to the way the synthesis tools optimise. Furthermore the tools do not and in most cases cannot &quot;compile&quot; each file in isolation, because the files are typically descriptions of small parts of the overall circuit.
When the design is fit into the FPGA, unless you lock down certain parts of it (post-fit netlists and incremental compilation), the fitter will start from scratch each time to try and find the most optimal way of fitting the design. Usually the compile time is heavily impacted by timing constraints as the fitter tries to minimise routing delays to meet your required clock frequencies.