PCB Layout Optimization Regarding VCC and GND
In my opinion, none of those 2 layouts are clean.

Create a +5V_FUSE shape/polygon on top layer
Connect the shape using one (or more vias, if you anticipate current to be &gt;1A) on the north side of the northern capacitor to the L3 +5V_FUSE trace
Connect the +5V_FUSE shape to all capacitors and pads, either by &quot;capturing&quot; them with the shape or running traces from the pad to the shape

This creates a neat power distribution to your chip, the capacitors acting a tanks for high-speed current transients with little to no parasitic to the chip's pads. Having the vias further away from the chip simply creates a shorted power path in your case.
I'm gonna answer your second question with another question. Do you have layer(s) with a lot of copper and others with only a small amount?
If you do, you should know that copper balance between layer is very important in high-volume production boards to prevent boards from warping during manufacturing heating/cooling phases. Unbalanced copper creates disparity in copper expansion and relaxation. Pouring a ground shape on all layers is recommended, accompanied by plenty of ground vias.
It also greatly helps with EMI reduction, as others mentioned. as long as you have plenty of ground vias all over your board and don't miss an isolated island of copper.