Compact multi-cycle adder for fpga: adding 1 to wide counter
You have not said it but it seems obvious that you are accumulating this event counter so that it can be read out of the FPGA for some purpose. That means that you have some provision to bring out register content, presumably under some software control. 

I would simply extend that to allow readout of more smaller counters as opposed to trying to squeeze it all into this huge counter. Place these smaller counters in the design where the individual events need counting and then let software read each out. Software can do a brilliant job of adding the subtotals together. And who knows, there may be an advantage of knowing what the various subtotals were.