What is the dependency of the gate leakage current and the gate voltage?
So I will make the assumption that the measurement will be "quasi static".  A high frequency measurement will also involve displacement current for charging/discharging the gate/channel capacitance, which, from the title you are not interested in.

The gate leakage current for the most part will be linear with the electric field which means it will be linear with voltage until you hit the EOS (Electrical Over Stress) limits of the device.  These are much higher than the Max limits posted in the datasheets.

Any device that has a non-linear characteristics would be considered to be a failed device (if you are within the operational limits).  If you force it enough you will get sudden current increase due to tunnelling effects.  In fact this effect used in Flash memory (called Fowler Nordheim tunnelling).  But that will not be present in a normal NMOS device.

Device to device gate leakage current will be highly variable.

You will need an electrometer to measure this properly.