Suggestions for my fifo arbitration / path merge design
Since your FIFO can probably do only one input operation per clock cycle, then it makes sense to use a FIFO data width equal to your two dwords and input both dwords on each cycle.
On the reading side, I don't think you need a temp register for both dwords.
If you're using a FPGA then the FIFO generator provided by the manufacturer (example) should include an option to have different data widths for the input and output ports, which solves your problem.
If you want to write your own FIFO code then check if your dual port RAM has a &quot;variable aspect ratio&quot; option to get one dword on the output port and two dwords on the input port. If that's not available the simplest would be to use two RAM blocks (one per dword) and a mux to route the output of the correct RAM block to the output of the circuit, plus the usual FIFO code. Note the input pin of the mux which chooses which dword goes to the output is the lower address bit of the FIFO counter, so you probably don't need a state machine for that.