How to constrain a clock signal out from a multiplexer
If the clocks are asynchronous (to each other), there are no meaningful constraints you can place between them.

You need to create a constraint for clk_out that represents the "worst case" for any of the possible clock inputs, and use that to evaluate the rest of the design.

The rest of the design must also be able to handle the timing violations that will occur when you change the control on the mux.

Note that there are more sophisticated (synchronous) clock switching techniques that can avoid creating "runt pulses", etc. that will make the design of the downstream logic simpler. These are usually built into the FPGA/ASIC vendor's clock management IP. You might want to read up on that.