System Verilog generic modules and unused ports
There is nothing in the SystemVerilog language that allows you to specify outputs that are allowed to be left unconnected. And you don't want to globally turn off dead code removal warnings because that could mask much larger problems. I see three possible choices:


Write a script that filters your messages to eliminate the warnings from the dead logic that is OK to remove. 
Create separate versions of your FIFO with different sets of outputs and instantiate the correct version depending on which version is needed. I realize this goes against the generic solution you are looking for, but the use of macros or submodules might make it a little more reusable. 
Live with it the way the messages are now.