Introduce delays of alternating value for synthesis on hardware
From the other question, you already have a way of delaying the signal by between 1 and 4 clock cycles:

reg[3:0] bits;

always @ (posedge clk_27)
begin
    vsync_o &lt;= bits[3]; //this was in the original code but actually makes it 5 cycles! But whatever.
    bits &lt;= {bits[2:0], vsync};
end


So you can easily modify that to have two signals coming out, one with 4 cycles delay and the other with 2 cycles delay (hint: if bit 3 is 4 cycles of delay, which bi is 2 cycles).

Now you have two signals - one with 4 cycles of delay, and one with two cycles of delay. All that is needed then is a way to select which one is which. The word "select" implies you need a multiplixer - 2:1 in fact (two signals in, one out). 

That means you also need something to drive the select line. Given it is 2:1, this is just a 1 bit control signal which you need to toggle every time there is a pulse. What do you know that can toggle? A flip-flop. To you need a flip-flop that toggles every time there is a pulse on Vsync.

The next question is, how do you detect a pulse on Vsync? Well, you see if there is a rising edge (or falling edge, or both). For that you need a rising edge detector. The structure is essentially:

reg delay;
always @ (posedge clock) begin
    delay &lt;= in;
end
wire risingedge = delay &amp;&amp; !in;
wire fallingedge = !delay &amp;&amp; in;
wire bothedges = delay != in;


So you need the signal, plus the signal delayed by one clock cycle. You have vsync, and your bits register has the signal delayed by one clock cycle, so you already have all the signals you need to build an edge detector.

reg whichDelay;
always @ (posedge clock or posedge reset) beign
    if (reset) begin
        whichDelay &lt;= 1'b1; //Start with a delay of 2 because on the first rising edge we will toggle.
    end else if (vsync &amp;&amp; !bits[0]) begin
        whichDelay &lt;= !whichDelay; //Toggle on each vsync input
    end
end

assign vsync_o = whichDelay ? bits[1] : bits[3];


And there you have it.