STM32F769 disco board max frequency
RCC_CFGR is the register that switches the CPU to a different clock. If the MCU stops working after that, there's something wrong with the new clock source.
The clock tree diagram in figure 13 (section 5.2) of the STM32F76x reference manual shows the various clock sources. You're configuring the AHB clock, which feeds into the CPU. Here are some things that can go wrong:

The PLL is set to use an external crystal (OSC_IN) but you only have the internal 16 MHz clock (HSI), or vice-versa.

The PLL dividers are not set correctly, so your AHB frequency is too high.

The AHB prescale divider is not set correctly, so your AHB frequency is too high.

Some other clock divider (like APB) is not set correctly, causing a fault.

Your AHB divider is set correctly, but the PLL output frequency (SYSCLK) is too high (above 216 MHz).


Before the write to RCC_CFGR, you can check whether the PLL is locked by looking at the PLLRDY bit in RCC_CR. If the bit is 0, trying to use the PLL will cause a fail.
I made a simplified version of the clock tree diagram to help illustrate what's going on:

If you post the modifications you made to the code I might be able to tell you more, but this should get you started.