7-segment display in VHDL?
I haven't coded in VHDL in a long time -- I don't know why they still teach it, they should teach Verilog -- but the answer below still applies.

Your counter needs to have the following inputs:


Clock - you already have it
Increment - if that signal is high the counter should increment by one on the next rising edge of the clock
Clear - you already have it, it should reset the count back to zero
Counter Enable - Let's you pause/unpause the counter, make sure 'increment' still works even if Counter Enable is zero.


Your controller takes in 4 button inputs and generates 3 outputs. For buttons 3 and 4 it detects a rising edge of the input and generates a pulse for 1 clock cycle, i.e.

          ____    ____    ____    ____
clock:  __|  |____|  |____|  |____|  |
               ____________________
input:  _______|                  |_____
                  ____
output: __________|  |__________________


The "counter enable" output of the controller is controlled by buttons 1 &amp; 2. A rising edge on button 1 sets it high and a rising edge on button 2 clears it to low. In effect the counter enable is controlled by an SR latch where the S signal is button 1 and R is button 2.

You then connect the 3 outputs of the controller to your counter (Problem 2).