Something is wrong with my understanding of this D-Flip flop design
The diagram is incorrect. The CD4001 is a NOR gate, so both inputs have to be logic '0' for the output to be a logic '1', so your original 'expected' chart is correct. The symbol used in the schematic is wrong. It should have a dot on the output to indicate inversion.

The CD4001 NOR gate is used to make sure only one channel at a time is selected. At power reset, Channel 1 is selected.

This chart is correct, and it is what is taking place in the circuit.

1000 Channel 1

0100 Channel 2

0010 Channel 3

0001 Channel 4