DDR4 frequency decrease if populated with more than one module per channel
I cannot speak for specifics of DIMMs in your case, but I can speak for designing other boards with high speed memory.  I would expect that you would need to either 1) increase the voltage, 2) increase the gain on the inputs by increasing the current, or 3) decrease the amount of memory to keep the same speed.  

When I make ICs, my IO drivers are fixed for current; however, some memory modules IC I can configure with pins to have lower effective input capacitance but burning more power on the input.

In the case of #1, assume that you have a fixed driver strength on the IC, if you add more ICs on the bus, you increase capacitance so you need to slow down the bus to hit timing.

In the case of #2, you burn a lot more current by making the inputs look like they have less capacitance. 

In the case of #3, you will find that there's a refresh penalty on DRAM.  If you have a 2x size of DRAM IC, you need more time to refresh.  Usually, this looks like just slower bus activity in a speed test, but sometimes you actually decrease the speed of the IO and still have a fast "refresh" clock.

I have personally added more DRAM ICs and then had to burn more current to hit timing due to the addition of another IC on the bus.

I think that what you have in the end is just marketing, and that all of the bus transfers must slow down as you add DIMMs.  Micron DDR4 document suggests such as well.