how to reset a memory array in verilog?
Usually large memories like what you are showing are implemented as block RAM type resources - dedicated RAM dotted about in the FPGA. These resources do not usually support reset - you can reset the output register, but not the array itself.

If you try and implement a reset signal, the synthesizer will realise that it cannot use a dedicated memory and try to implement the whole array in dedicated registers - in your case that would be 8192 registers, an 8bit 1024:1 multiplexer, and large quantities of address decoding logic. It would take a huge amount of resources!

If you still want to try the reset and see if it fits, you could simply add a for loop in your always block:

integer j;
always @ (posedge clock or negedge reset) begin
    if (~reset) begin //negative reset clause
        for (j=0; j &lt; 1024; j=j+1) begin
            mem[j] &lt;= 8'b0; //reset array
        end
    end else if (write) begin //write enable
        mem[waddr] &lt;= data; //standard write logic
    end
end


However I would really seriously advise against this. Perhaps ask yourself why you need to do it at all and consider your other options.

One solution, albeit taking as many clock cycles as there are memory addresses is that on reset you have a counter which counts through all addresses and writes a zero to each one in turn (clears one address each clock cycle).