Altera DE1 seven segment display
Your code there doesn't look generally synthesizeable to me, as you're not really following any synchronous design conventions. I expect if you inspect your synthesis logs you'll find several warnings and/or errors. 


An edge triggered always block should model a flip flop, which means that it has one edge triggered clock, and an optional edge triggered preset and/or reset. It should not be triggering on edge of multiple arbitrary signals. @(posedge clk or negedge en) would be more appropriate, assuming that your fpga is provided with a suitable clock signal.
Inside of an edge triggered block, you should generally use non-blocking assignments: &lt;=, instead of blocking assignments: =, as this more correctly models the behavior of a flip flop. If you don't know what this means then do some research between the difference between blocking and nonblocking assignments.


If you want to use memory elements like a counter, then you need to use clocked logic. On every clock edge you can check if in_up or in_down has changed from the previous value, and then use that to decide if you want to increment or decrement your counter value. You may need to debounce the input signals if they are coming from a button or you may get multiple spurious toggles when it's pressed.