Analyzing the SX1276 FIFO implementation
If you refer to the Semtech SX1276 datasheet, this information is pretty clear, at least in the version I have currently. https://www.semtech.com/uploads/documents/DS_SX1276-7-8-9_W_APP_V6.pdf. Should this URL be dead in future, just search for Semtech SX1276 Datasheet Version 6 (or greater).

Section 4.1.2.3. gives a really good diagram of how the FIFO is addressed:


When interacting with the FIFO via the SPI protocol, the SX1276 uses the FifoAddrPtr register to choose which byte to return. You can write to this register (its address is 0x0D) to set the address in the FIFO you wish to read and write to when addressing to the FIFO register (address 0x00).

Further down in the document, under Principal of Operation we see:


  The FIFO data buffer location to be read from, or written to, via the
  SPI interface is defined by the address pointer RegFifoAddrPtr. Before
  any read or write operation it is hence necessary to initialize this
  pointer to the corresponding base value. Upon reading or writing to
  the FIFO data buffer (RegFifo) the address pointer will then increment
  automatically.


The key detail to your question is 


  the address pointer will then increment automatically.


Whenever you read or write from the RegFifo (address 0x00), the pointer register RegFifoAddrPtr (address 0x0D) is incremented. When you next read or write, you are automatically interacting with the next address in the FIFO. Hope this helps.