Why is Floating point non-synthesizable in verilog
It is not that they can't be synthesized (they can, of course!), but tools won't do it combinationally (like they would a fixed point adder) because the resource usage would be unfeasibly large.  So it is done sequentially in multiple steps, and there are many, many ways of doing it with several trade-offs to consider, with division being quite complex.  So your floating point operation needs to be treated like any other module, you can design it yourself or license it from a vendor, and a tool won't synthesize c = a/b for you, for the same reasons it won't synthesize an integral or an equation solver, but it doesn't mean it can't be done in an FPGA!