Xilinx FPGA and DDR3 Memory. Confusing Impedance combinations
Intel spec
Table 4-8: General Layout Guidelines  DDR 2,3,4
Guidelines
Parameter
• All signal planes must be 50-60-ohm, single-ended, ±10%
• All signal planes must be 100-ohm, differential ±10%
• All unused via pads must be removed, because they cause unwanted
capacitance
Impedance
DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines Altera Corporation
Lower impedance demands excessive wide tracks or too thin PCB is only 2 layers for height to width ratio of dielectric H/W.
3.6V logic is a 25 ohm driver +/-25% typ so 40 Ohm was sometimes used to reduce risetime slightly.  PCB tolerances for Zo are typ 10% if certified with Electrical TDR tests on a test coupon then D Codes are scaled to suit the batch to guarantee tolerances otherwise they can be greater.
Here you can see  the effects of a few combinations of 50 ohm traces but different source and loads. I added some lead inductance of 1nH + 1pF for ~ 1 to 1.5 mm over a ground plane.