clock frequency divide by 5 vhdl
If you want to generate a 50% duty cycle divided clock in VHDL, using only rising_edge of clock, the divided clock's period should be multiples of 2. Since 5 is an odd num, you have to make use of falling_edge of the main clock too. You have to generate two 2/5 duty cycle clocks phase shifted by half period of the main clock. Then you can "OR" it to get the required clock which is of 1/5th frequency and 50% duty cycle. 

Something like this:



Code Sample:

architecture Behavioral of divide_by_5_counter is
signal a,b : STD_LOGIC;
signal count_a, count_b : STD_LOGIC_VECTOR(3 DOWNTO 0);
begin

process(clk_in,reset)
begin
if reset = '1' then
a &lt;= '0';
elsif rising_edge(clk_in) then
if count_a = 5 then
count_a &lt;= "0001";
a &lt;= '1';
elsif count_a &gt;= 2 then
a &lt;= '0';
count_a &lt;= count_a + 1;
else
a &lt;= '1';
count_a &lt;= count_a + 1;
end if;
end if;
end process;

process(clk_in,reset)
begin
if reset = '1' then
b &lt;= '0';
count_b &lt;= "0000";
elsif falling_edge(clk_in) then
if count_b = 5 then
count_b &lt;= "0001";
b &lt;= '1';
elsif count_b &gt;= 2 then
b &lt;= '0';
count_b &lt;= count_b + 1;
else
b &lt;= '1';
count_b &lt;= count_b + 1;
end if;
end if;
end process;

clk_out &lt;= a or b;

end Behavioral;