D flip flop in verilog
In Verilog, if you assign to something in a procedural block (a block between begin and end), you need to make it a regsiter type. If you assign to something in a continual assignment (either an assign statement or the output of an instance of a module) you need to make it a wire type.

So you need to declare (You already edited this change into your question)

wire D;


on line 5, and

output reg Dout;


on line 2.

Also, D is somewhat superfluous. You could just have

output reg Dout
...
always @(posedge clk) begin
    Dout &lt;= Din &amp; nRst;
end


Even better, you should not use logic to simulate control features on flip-flops if your architecture makes full-featured flip-flops available. To code a DFF with syncronous reset for synthesis you would rather have

always @(posedge clk) begin
    if ~nRst 
         Dout &lt;= 1'b0;
    else
         Dout &lt;= Din;
end


This will be more likely to use the built in features of the flip-flops in your architecture, resulting in faster and more resource-efficient implementation.

The error you showed doesn't seem to relate to how you defined your DFF_SYNC_RESET module. More likely it has to do with what files you are including in the synthesis or where you instantiated it, either in your testbench or in a higher-level module.