Overdrive Voltage Effect on Cascode Operation
The lowest value of \$v_o\$ where the output current starts to deviate from its nominal value is not \$2*V_{ds,sat}\$ as you calculate.

In that minimum \$v_o\$ situation, NMOS Q1 still needs to be in saturation mode as Q1 needs to set the output current. So Q1 does need one \$V_{ds,sat}\$ which has the same value as the overdrive voltage of 0.2 V.

But cascode NMOS Q2 can be in linear (or triode) mode so it will basically behave as a low-value resistor and the \$V_{ds}\$ of Q2 will be quite small.

The same is true for Q4 and Q3.

Edit:

The above is assuming \$V_{g2}\$ is chosen such that the lowest \$v_o\$ can be achieved. That's not the case here, \$V_{g2}\$ is lower here, at 1 V.

So when will Q2 shut off (and thus lower the output current)?

When Q2's \$V_{gs}\$ becomes lower than \$V_t\$.

That's at about \$V_{s2}\$ = \$V_o\$ = 0.5 V.

This is a bit "1st order approximation" as Q2 will need a bit more \$V_{ds}\$ than zero. In practice the real answer will be about 0.6 V to 1.2 V.