Series pass configuration logic level MOSFET
You could try a circuit configuration like this:



Make sure to tie the GND of the 3.3V GPIO signal source to the GND of the -12V supply. Also when selecting an NMOS FET that you make sure that it can handle the 12+3.3V = 15.5V on its Gate with respect to its Source. Many medium power NFETs with low RDSon should work in this application. It does not need to be a logic level FET.