Output signal is being attenuated after the Biquad filter direct Form 1, why?
If you are using the jack I/O of the Pmod I2S2, then there is a simple RC bandpass that will cripple your signal. You could try to bypass it either by probing directly after the filter -- straight on the input --, or bypassing the series caps with a wire -- which will still leave the parallel one to be a lowpass, but at higher frequencies (it looks like the -3 dB is at ~340 kHz, so you have plenty of bandwidth).
Be careful with bypassing, because those filters are not there without reason. You can't compensate in software since the series cap ensures you have 0 V at DC. You could add another cap in parallel to the 1 uF one, say 10 uF, and that will give you a boost of low frequencies up to 10 Hz for a fraction of a dB.

I tried to model the whole chain of filters and compare it to the readings in your table, this is the result:

V(in) is the output after the input filter, which is a simple resistive and capacitive divider, acting as a lowpass with -6 dB gain, V(df1) represents the output after the biquad (modelled as a direct form I), and V(out) is the output after the second external ADC uC (the AUDIO OUT in your block diagram). V(test) is a frequency piece-wise linear interpolation of the readings you provided (ignore the phase, you didn't read it, I only tried to mimic something close to V(out)).
The overall frequency response is fairly similar, slightly lower frequencies in the model, since it's an approximation -- there are various other I/O impedances that can affect the response. For now, let's assume they come close enough that they can be considered as having the same magnitude response. That leaves the gain. The RC divider at V(in) ensures an attenuation by 2, so 6 dB are accounted for. This can be verified by using a bypass on the biquad, which results in what you have seen before: a roughly 2x attenuation.
The rest of the dB are somewhere else. They cannot be in the biquad implementation, since the coefficients actually give a ~1.133 DC gain lowpass (slightly shelf, due to roundings). They cannot be somewhere on the STM board, since the bypass would have shown it. So that leaves the program, somewhere. At this point, I don't know the software part since I've never used an ARM, but in some of your comments you mention that increasing one of RxBuff, or TxBuff, results in an increased amplitude output. Maybe that's the key? Looking in the datasheet it only says:

All I2S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA capability

However, if the cause is not found, it looks like it's only a matter of overall gain, which means that multiplying by a certain constant would solve the problem. After all, a multiply by 2.0f of all the B[0:2] terms would be necessary to compensate for the RC divider at V(in); making it 3.0f, instead, should compensate for the rest of the gain.