Using Buffer Ports in VHDL?
Yea, you can use the simple solution of creating an internal signal:
signal done : std_logic ;

Use this signal inside your clocked process.
And simply assign it to o_done as a concurrent statement inside architecture definition:
o_done &lt;= done ;

I haven't really had the need to use buffer ports in VHDL codes till now. This is something I extracted from Xilinx Vivado Synthesis Guide:

VHDL allows buffer port mode when a signal is used both internally,
and as an output port when there is only one internal driver. Buffer
ports are a potential source of errors during synthesis, and
complicate validation of post-synthesis results through simulation.
reference: Chapter 5, Xilinx Vivado Synthesis Guide