Verilog problem on Spartan 6 board
This is a very poor code. It has no reset initialization. Your counter[...] is undefined, and thus doesn't increment. So your divider by 320 doesn't run, and the clk is not generated. 

Before starting probing anything physically, make a simple testbench, and run ISim (which is a part of Xilinx ISE) on your code. You will see all red signals. Don't bother to implement the code until you see all signals defined and toggling to your ideas.

Something like this:


  module test00;
  
  // Inputs
  reg M_CLOCK;
  
  // Outputs
  wire [6:0] DAC;
  
  // Instantiate the Unit Under Test (UUT)
  dac7bit uut (
        .M_CLOCK(M_CLOCK),          .DAC(DAC)   );
  
  initial begin       // Initialize Inputs
  M_CLOCK = 0;

  // Wait 100 ns for global reset to finish       

  
  #100;
                // Add stimulus here
  
  end
  
  always begin

 #(100)   M_CLOCK = 1;
 #(100)  M_CLOCK = 0; 

  
  end
  
  endmodule