J/K to D type flip flop strange behaviour
Your basic problem is that you're going about this in the wrong way.

The task is really to design a state machine to implement the different states of the traffic lights and move between them in the correct sequence. For a state machine the flip flops should be all be clocked by the same signal, and the flip flop inputs set up so that the system moves from the current state to the next state when the clock edge arrives.

But instead, you've connected the /Q output of one to the CLK of the other, which is something you might get away with in some situations but not others, partly because there will be a short period when the system may go through a sort of incorrect intermediate state on its way to the correct one.

You then rather missed the point of using J-K flip flops instead of D-types by just trying to convert them into D-types using an inverter. J-K flip flops give you a lot more ability to control the output, and I'm guessing the point of the exercise is to get you to fully understand that and learn how to use them.

Also the 74LS76 is a master-slave device. As it states in the data sheet:


  J-K input is loaded into the master while the clock is high and
  transferred to the slave on the high-to-low transition. For these
  devices the J and K inputs must be stable while the clock is high.


So you can't exactly convert them into D-type flip flops with an inverter anyway.