Clock generation using FPGA
The 50 MHz clock input should be on pin D9, not C9.  You should double check this, as I could be reading the schematics wrong and assuming too many things that you left out of your question.

IF your signal amplitude were close to 3.3v then the not-so-square square-wave would be the result of how you are terminating your signal (probably no termination) and bad o-scope measurement techniques.  But since your "signal" is only 10 mV, I think there are other issues.

I should also mention that I don't know Verilog, so I'm assuming that your Verilog code is good.  I'm more of a VHDL person...

So, my best guess at what is going wrong is this...  You have your clock input on the wrong pin.  Your scope probe is on the correct signal, but there is nothing there.  You're seeing a 50 MHz signal on the o-scope because of crosstalk and other noise effects and this signal is not actually being output from the FPGA.