DDS - find optimal size for LUT, PHACC and sampling freq for application
how i find the most suitable size of Lookup table and phase accumulator for my application?

First of all, you define the requirements of your application.
There are many factors that might be important, including
resolution frequency
maximum frequency (absolute, or as a fraction of the clock)
phase noise
amplitude noise
spurious performance
Generally, a DDS with a lot of accumulator bits will give you good frequency resolution, and a lot of DAC bits will give you good noise and spurious. But how 'good' do you need them?
I had a DDS application where no close-in spurious was permitted, (well, OK, it wasn't none, but it was over 60dB better than a simple DDS, which would have been unachievable with obtainable DACs). Fortunately I could sacrifice resolution, and was working in an FPGA, so could vary the accumulator size depending on the output frequency, so that I was always generating a small rational fraction of the clock frequency. Now I had aliased harmonics in predictable places, rather than unpredictable spurs.
If you know exactly what performance you need, then this will drive the design of your DDS, as it did mine above. If you don't know exactly what you need, set a budget, and with your required maximum and resolution frequencies, choose the most DAC bits your budget will cover. The accumulator will invariably be long enough so that phase noise is dominated by the DAC rather than accumulator. Then use it for a bit, and discover whether it meets all the requirements you didn't realise you actually had.