Interfacing a SAR ADC (LTC2323-14)
I can answer the question now on my own: Yes, the timing is indeed that complicated, unfortunately. The problem is that running the clock at the sampling instant would corrupt the sample, hence it needs to be turned off.

Controlling such an ADC requires complicated logic that's best performed using an FPGA/microcontroller. The signals for this ADC example can be generated with an 110 MHz master clock and 22 cycles (which gives effectively 5 MHz).