Design up counter in VHDL using generate statement
Here is a simple generate statement, which generates 8 TFFs and connects the clock input of the tff to the q output from previous FF. Because you are using indices calculations (i+1 or i-1), you need to wider range for the tff_clocks range or you must shorten the generate loop.

I'm using a loop from 0 to 7 so I extended tff_clocks by 1. Index 0 is connected to the original system clock.

architecture ....
  signal tff_clocks : std_logic_vector(8 downto 0);

begin
  tff_clocks(0)  &lt;= clk;   -- first tff is clock with main clock

  genTFF : for i in 0 to 7 generate
    tff_inst : tff
      port map (
        clk   =&gt; tff_clocks(i),
        t     =&gt; '1',
        q     =&gt; tff_clocks(i + 1)
      );
  end generate;

  async_counter_result &lt;= tff_clocks(8 downto 1);
end;