How does a dual gate MOSFET reduce Miller effect?
I'm going to ignore the reference to tetrode, I have never understood why an exact analogy reveals a fundamental truth.

The miller effect arises in situations from a connecting capacitance across two nodes that that have an inverting voltage gain/relationship between them.  it doesn't have to be in transistors either, but in MOSFET's you have \$C_{GD}\$. How this is traditionally solved is to cascode the amplifier by isolating the offending capacitance so it doesn't appear across the gain stage.  The dual gate Mosfet is basically a cascode stage with the cascode transistor built in (this has a secondary effect, see below), you just have to bias the the transistors so that they are in the active regime. M1 = amplifier, M2 = cascode







simulate this circuit &ndash; Schematic created using CircuitLab

The amplifer transistor converts the input voltage in the output current and the cascode transistor simply transfers this current to the output load.  the output is on the drain of the cascode and the input is on the gate of the amplifier transistor.  There is no capacitance across the two nodes, the miller effect is greatly reduced.

Cascoding greatly helps in gain too. 

An interesting effect from manufacturing comes into play.  The upper device is a longer gate device and the lower is a dual gate device.  The S/D implant to channel capacitance tends to be lower than the S/D to isolation edge capacitance (the S/D's on the outer edge) so the S/D in between the gates will tend to have a lower capacitance that if you were to have designed the circuit using two separate transistors in a cascode configuration (and obviously they take up less area).  This means that the  \$C_{SB}\$ capacitance is less as well making for a higher speed circuit, here SB = Source to Bulk (AKA well).