Design of high voltage MOSFET amplifier
For +/- 300V output, you'll need supplies a bit above that to account for drive voltage requirements, and a bit of margin. Personally I'd use +/-325V DC power supplies since that's the rectified output of a cheap 1:1 mains isolation transformer running on 230V, so you don't have to visit the audiophile shop for a gold-plated, custom tube amp transformer. This is obviously a lethal project, don't sue me.
So, 650V transistors (or a bit more) would be desirable, with a package that can dissipate the required power, and an appropriate SOA.
There are no PNP BJTs that fit the bill on Mouser. There are a few NPNs, but at this high voltage you get SOA problems due to second breakdown. This is FJL6920TU, a TO-247, 20 Amp NPN, and the current its SOA allows at 600V is really tiny.

So it will either have to be a kludge with cascodes, or FETs. PMOS stop at 600V, and there are a few 600V PMOS that would be suitable if you wanted an output of, say, +/-275V, but for +/-300V that won't work.
So, with the PMOS choice narrowed down to &quot;none&quot;, it'll have to be a N-channel job.
You could get away with a TO-220 package but you say &quot;The current needs to be very low for now (about 50 mA)&quot; so, when I read &quot;for now&quot; I just feel it coming: &quot;now that it works how do I get 200mA?&quot;... so let's overdesign it a bit and use TO-247 or TO-3P FETs. Note the whole point of these big packages in this design is to have more thermal interface material area on the back so thermal resistance to heatsink is lower, so when an regrettable event happens like a short on the output, the FET chip has more thermal margin before it blows. Larger thermal mass due to the huge copper slug on the back also helps.
When picking a FET for linear use, the first thing to check is it actually allows linear use, which should be mentioned in the datasheet. Next check that the SOA graph has a curve for &quot;DC&quot; and it is a straight line, without a second higher slope at high voltage that looks like a BJT second breakdown.
FQA6N90C looks good, 900V 6A, and RthJC of 0.63°C/W. Also this QFET series are popular in linear applications, look at that beautiful DC Safe Operating Area, constant power at DC, and your short circuit protection will be easy to design.

If you get a lower current FET in an attempt to get lower capacitance then it will have a smaller chip and thus a higher RthJC so it will run hotter and have a smaller SOA.
This is a FET that is NO GOOD for linear use, notice the much higher slope in the SOA:

You can use a SiC FET too, if you want sexy.
Now, driving transistors. PNPs also stop at 600V, which means the VAS transistor of the amp will have to be NPN, or even NFET. As for the current source at the top, you want DC so it can't be a bootstrap. DN2470 depletion FET will work fine, at 1mA it will stay cool. I was also tempted to use a combo of a photocell isolator for a local isolated gate drive power supply, plus a transformer for the AC part of the gate drive, but that would be slight over-engineering.
So. No semiconductors of the P gender easily available above 600V, which means...

I've used 250V rails because I don't have spice models for the higher voltage FETs.
On the left we have a classic input stage. If we slap the full 300V on the input transistors, then any slight variation of their current will create a large variation in dissipation, and thus a thermal DC offset, and a long settling time to DC. Thus, Q2,Q3 are cascodes. Pick a 400V PNP that is suitable for cascode job (ie, low capacitance).
Q4 Q5 Q6 Q7 can be matched pairs, like BCM850/860, these are cheap.
If there is too much offset variation due to self-heating in the input stage, you can wire the amplifier in inverting mode which will keep the input stage Vce constant, and switch the cascode base voltage to minus a few volts instead of -12V.
X5 is the VAS transistor. I picked a FET because it has high open loop gain at DC, and its SOA is also nice. You can use a 700V NPN but if you want a SOA larger than one milliamp at 600V then you'll have to pick a pretty large, low hFe transistor which means it will need a darlington to have enough gain. Or you can cascode it.
D1 protects the FET gate against overvoltage on negative clipping. R20 protects it against overcurrent. If you use BJTs instead, drop the zener and the resistor and put a Baker clamp diode between B and C. And double check the SOA.
M4 is a DN2470 wired as 1mA current source. I used DN2540 spice model which is wrong, so the resistor value is also wrong.
X2 and X3 are FQA24N50 FETs that are only rated to 500V but I had the model. Use 900V FQA6N90C instead. It should be faster.
X3 is our single-ended drive transistor. D2 protects its gate against overvoltage (both positive and negative) and Q8 protects against overcurrent. Set R19 to a suitable value, Imax = Vbe/R19.
C3+R18 is a zobel for stability, may not be necessary.
X2, Q1 make the current source to bias it in single ended class A. Zener D3 is required to protect the gate from overvoltage on negative clipping. Idle current is Vbe/R6, here 50mA.
With a single-ended class A amp you waste power but there is no need for bias temperature compensation, as would be the case with a push pull. And we can't have a push pull anyway because no PMOS.
C1 C2 R15 are the compensation network, adjust to taste for proper phase margin.
It needs quite a bit of positive headroom due to M4/X3.
Performance is... actually not that bad. You get 2V/µs slew rate and a bandwidth up to about 100 kHz. That's with the wrong spice models, of course. Clipping behavior is pretty sticky, but that shouldn't be a problem in your use case.
Here's another version, that might actually be better. The bottom power transistor is used as VAS and output, directly driven from the input stage. The top one is now the single-ended current source. This time I used output-inclusive compensation, which is a bit risky, but you should adjust the compensation with real transistors anyway, not my wrong spice models. It also depends on the load, notably cable capacitance, and whether you put a zobel on the output to protect against that.

Now, you may ask, &quot;I don't want single ended class A, I'm not audiophile&quot;. Okay...
EDIT: improved

So, no PNP, except if we put them in a position where they can be low voltage, for example in the low voltage local power supply created by zener D4.
In this version, when current through the bottom FET gets a bit low Q11 turns off and via current mirror with gain Q14 Q15, increases the current of the top FET. So, the bottom FET drives the top FET, but since the bottom FET never turns off it stays in control of open loop gain, which means we don't have two different open loop gains and stability conditions depending which FET is actually on, which would be... complicated. Q12 must use a tiny current so it doesn't run out of SOA, hence the current mirror with gain on top. This shows pretty good slew rate and settling, and it will do a lot more current than you need with low idle dissipation, but values of R20-22 need to be just right.
C1 should probably be higher, like 100pF.
Since you have a resistive load, another way to increase available current without a push pull, while keeping the Q8/X3 current source, is to add resistors R22/R23 to tweak Q8 base voltage, which increases current in FET X3 when output voltage increases towards the positive rail. Adjust resistor values to get the current you need. This is just the upper right part of the schematic, and the only change is the two resistors R22 R23.