Verilog - Array of Inputs
Both are allowed.


  [0:3] D


Is the 'big endian' convention.
However 99.99%** of all Verilog code uses the little endian convention when declaring ports and signals even when building a big-endian processor. 

The other convention is that the LS bit has index 0. For example if you have a 32-bit wide address bus the convention is to use:


  wire [31:0] address_bus;


This does not mean you can't use it. You might want to use only the top 30 bits in a module in which case it is perfectly normal to make an input bus: 


  input [31:2] address_bus_top;


In fact when I see that in a module which I get from one of my colleagues (Who all follow these conventions) it tells me that it is a sub-set of a bigger vector.

Last if working with memories (2 dimensional arrays) the index convention is:


  reg [7:0] byte_mem [0:255];


I have seen warnings from Cadence compilers if that convention is not followed. I think it happens if you use it in combination with $readmem...

**Rough estimate.