Tap controller implementation in JTAG
The item in the top left of the graphic looks very similar to the boundary scan register ell from the JTAG standard, IEEE 1149.1 figure 1-1.

Each cell consists of two muxes and 2 D-flip-flops.  A group of boundary scan register cells are arranged into a boundary scan register.  Data moves serially from one cell to the next like a big shift register.

Setting Shift/Load = 0 and toggling clock A will load the left flip-flop in each cell with the pin value.
Setting Shift/Load = 1 and toggling clock A will shift the captured data through each boundary scan cell, and eventually out of TDO so you can read it.  You can also shift new data in via TDI that will can be loaded into the output registers.
Toggling clock B can load right-most flip-flop in each boundary scan cell with the data from the left most one.  This data can then be put onto the pin if the right-most mux selects that it should be put there.
The right most mux selects weather the the pin value is controlled by the device under test, or if it is driven by the output flip-flop.

Per IEEE 1149.1-2001 page 21 in the description for the Shift-DR state,
Clock A is supposed to toggle once every time TCK toggles and the TAP state machine is in the Shift DR-state, and the boundary scan register is selcted.
CLOCK_A &lt;= TCK when state=shift_dr and bs_reg_selcted = '1'  else '0';
Per IEEE 1149.1-2001 page 21 in the description for the Capture-DR state,
Clock B is supposed to toggle once every time TCK toggles and the TAP state machine is in the Capture-DR state, and the boundary scan register is selcted.
CLOCK_B &lt;= TCK when state = capture_dr and bs_reg_selcted = '1' else '0';