Verilog procedural assignment reg guaranteed to keep value when not assigned?
Yes, they are equivalent.  IEEE Std 1364-2005, section 6.2 Procedural assignments states:


  ...procedural assignments put values in variables. The assignment does
  not have duration; instead, the variable holds the value of the
  assignment until the next procedural assignment to that variable.


You do not need to use the 2nd code example.