Pipelined vs Low Latency implementation of cube of a number in Verilog
Logically speaking, you're correct they are identical. However, the first implementation is clocked (note the always @(posedge clk) statements vs the @* statements in the second), so it has a minimum three-cycle latency that is determined from the clock period. The second implementation is calculated completely asynchronously, so its latency is dependent only on the speed of your technology (how fast the multiplications and routing delays resolve).

What this example illustrates is that many digital functions can be implemented in a heavily pipelined manner or in one long logic path, or somewhere in between. Which you choose can depend on many factors. The first implementation is less resource-efficient as it uses many extra registers to store the pipelined values from cycle to cycle. The second is more resource-efficient, but if you plop it in a synchronous system running at a high clock frequency it will be harder to close timing on, because it fits so much logic into one cycle.

Notably, both implementations have equivalent throughput. Both can handle a calculation every clock cycle, it's just that the first implementation will supply the output three clock cycles after receiving the corresponding inputs.