Working of the "Capacitor Reset" block
Definitely, the app note SNVA717 does not discuss a power disconnect condition. Their primary concern is overvoltage disconnect, and most of the document explains the challenges and solution. Let us simulate the Soft-Start and Protection Circuit (Figure 5), part of the Automotive Line Transient Protection Circuit for the case of the Battery Bus disconnect.
I simulate the power disconnect event with a voltage controlled switch OPEN; the voltage source controlling voltage is PULSE(1 0 10m 1u 1u 1000m).

The voltages at BatteryBus, at the QIRL source, and VOUT:

Unlike the power overvoltage condition case, there is no requirement to disconnect SMPS as soon as possible. Capacitor C3 dumps its charge through the series pass PFET QIRL while the latter is in the conducting state (time scale is 30ms, graph I(QIRRL:D) (blue) partly overlaps graph I(C3) (green)).

After that, node S is dangling because it has no conducting path to ground (graph I(Dblk) (turquoise) overlaps graph Ie(Qovs) (red)).

DRST11/DRST12 voltages:

The voltage across DRST11 is V(GDBF) - V(DRSTCP).
DRST11/DRST12 currents:

At 15ms, the voltage across DRST11 is 50mV, the diode current is a few nanoamperes.
At 24ms, the voltage across DRST12 is 385mV, the diode current is 7.8μA, at 30ms, 4.7μA, at 100ms, 450nA.
As you see, the DRST11/DSRST12 currents drop to infinitesimal values early, and capacitor C3 remains charged indefinitely long, because node S is dangling, and the current path is not closed. The DRST block cannot fix it, and there is no need to worry.