PIC - Time to enter the interrupt
There are two things here: the time before the ISR starts and the time the ISR takes.
When you're using C, the ISR execution time may increase a lot: http://www.xargs.com/pic/c-faq.html#isrfunc
However you asked for the time before the ISR starts, which is a few clock cycles. This can be read in section 8.3 of http://ww1.microchip.com/downloads/en/DeviceDoc/31008a.pdf:

Interrupt latency is defined as the time from the interrupt event (the interrupt flag bit gets set) to the time that the instruction at address 0004h starts execution (when that interrupt is enabled).
For synchronous interrupts (typically internal), the latency is 3TCY.
For asynchronous interrupts (typically external), such as the INT or Port RB Change Interrupt, the interrupt latency will be 3 - 3.75TCY (instruction cycles). The exact latency depends upon when the interrupt event occurs (Figure 8-2) in relation to the instruction cycle.
The latency is the same for both one and two cycle instructions.