TimeQuest Timing Analyzer: What is the difference between post fit and post map timing netlists?
The process of mapping implements the specified behavior in the selected technology, but does not assign specific physical resources to the individual elements (e.g., LUTs and FFs). Simulation at this level models the gate delays fairly accurately, but uses statistical averages for the wiring delays.

The process of fitting allocates the specific physical resources for each design element identified during the mapping stage, and also allocates the routing resources required to make the connections. Simulation at this level gets both accurate gate delays as well as wiring delays.

Since fitting is a fairly compute-intensive process, and since post-map simulation is about 90% of the way there in terms of overall timing accuracy, many designers do the bulk of their timing verification using post-map timing.