How can Qsys component configuration be accessed in software?
Several ways spring to mind:

A/ The way I have done this in the past is to add the parameters to the registers.

A (professional) peripheral has: 


An ID register
A version register


I have added to that: 


Parameter register.


If required you can easily pack four 8-bit parameters in a 32-bit register:

case (read_adrs)
4'h0 : rdata &lt;= control_register;
4'h4 : rdata &lt;= 32'h4F495047; // "GPIO" in little endian
4'h8 : rdata &lt;= {VERSION_MINOR,VERSION_MAJOR};
4'hC : rdata &lt;= GPIO_OUTPUTS_COUNT;
...


The CPU can then read the width. The disadvantage is that with a define you can have all compile-time optimizations which are now not possible.

B/ As an alternative to put all that type of parameters in one include file. Then you could make a sed script which converts the Verilog 'include file' format to C include file format and include that. The syntax is close enough to make that very simple. 

C/ Add a define to both make files. But I find that error prone.