Consequences of leaving unused inputs of clock buffer floating. Alternative: best practice
This seems to be covered in section 2.3 of the datsheet:




No external termination is required for unused inputs.
If you want to use external termination to improve noise immunity, pull the true input down and the complementary input up.



  Tie /CLK1 to VDD/2 by connecting it to the same voltage divider as /CLK0 (considering the case of single ended CMOS input) and CLK1 to GND.


I wouldn't recommend sharing voltage dividers between inputs, even if you are using both inputs single-ended. That's likely to allow some coupling between inputs and increase output jitter.


  Tie both CLK1 and /CLK1 to GND.


I wouldn't do this in any case because these are differential inputs. If you need to tie off unused differential inputs, tie one side high and the other side low.


  Tie CLK1 to GND and /CLK1 to VDD.


This is reasonable, but use a resistive connection rather than shorting the inputs to GND or VDD, because LVDS inputs aren't designed to be pulled far outside their normal bias voltages. 5-10k is probably a reasonable value.