DC-DC buck converter controlled by ATTINY - optimize PWM for maximum resolution
(Most calculations that follow are not very precise, just close enough to guide some design decisions).

First off, M1 is driven too softly and therefore is not switching effectively. The driving impedance to M1 gate is around 10K, looking up the gate capacitance of 720pF, that gives a time constant of 10K x 720pF = 7.2us.

Comparing to the PWM period of 62.5KHz, that is 16us, the gate drive is way too slow and should be sped up by 2 orders of magnitude or so. That can be done by changing R2 to around 100 ohms (and R1 accordingly), but that has the undesirable effect of making the gate drive dissipation to be as much as the solenoid main load. The solenoid load current is no more than 24V / 460ohms = 52mA. So a smaller MOSFET M1 with much lower gate capacitance could be a better choice.

For an ideal buck: VOUT5 = V1 x PWM_duty_cycle .

So with V1 = 24V:


100% -> 24V
75% -> 18V
50% -> 12V ...


This do not match your results. The very soft gate drive is a reasonable explanation, such that M1 is never quite turned off by the time the PWM drive signal gets to around 75%.

So by fixing the M1 switching, it gives you 100% -> 24V that you want automatically.

One simple way of getting 5V at 0% duty cycle is to connect anode of D1 to +5V. There is probably a +5V powering the ATtiny already. The average current requirement is around 5V / 460ohms = 11mA, and the peak around 52mA, which are not that much.

By the way, the main deviation of this circuit from an ideal buck is D1 with the effects showing up mostly when the duty cycle is low. The reasons are D1 has a voltage drop and also passes current only one way.