More Energy Efficient 1 or 0
It's completely symmetric and thus, in the terms your looking at it, irrelevant.  Note that I wrote the long post you refer to above. The polarity of control signals are more about how much external logic is needed to enable them.  If you have negative logic then a wired Nand approach with an internal pull up and no external logic makes sense.

Other elements that come into play are power rail ramp up, boot up of the chip and indeterminate states of the chip whist the power is ramping. And this is really about the configuration of the logic, threshold values and switch points.  I tend to design systems that always come up in a reset state even before the rest of the circuit can possibly come alive, and only when the rest of the chip has come alive do I allow  the reset to be deserted. But not everyone does this and you might see chatter and activity before a forced reset and then clean boot up. Which might be fine.

Clarifying my symmetric comment. I wouldn't read too much into the advantages of PMOS vis-a-vis NMOS with this regard as the drain of the NMOS can leak towards the upper rails just as easily as the drain of the PMOS can leak towards the negative rail.  You really need to look at individual designs, processes and details .  A generalized statement doesn't work and more over is not useful.

If you are concerned about efficiency then you'd be best at controlling the edges (or rather the number of edges), that's when CMOS burns energy.