LPDDR2 reference design?
LPDDR2 is more or less confidential and thus not much information is available on it.

If you have routed DDR, it is almost straight forward as there is no termination, you just have to connect signals between them. I'm currently working on a design with a SoC and a LPDDR2 and it was really simple about the schematic, but routing is a bit more challenging.

CA are address lines and should be routed straight (Controller's CA0 to memory's CA0, etc.).

Bit and byte swapping is clearly allowed with other type of DDR and LPPDR but for LPDDR2 some note and appendix in the Jedec standard seem to not allow it. After looking for, some guys on Xilinx forum tried it and it worked fine, I also asked two LPDDR2 supplier and the SoC supplier (for the controller side), what is possible about bit and byte swapping:


Group 0 (DQS/DQSn0, DQ[0...7], DM0) should be routed straigh without swapping to allow support of Mode Register function (but it doesn't seems to be really used)
Group 1 (DQS/DQSn1, DQ[8...15], DM1), Group 2 (DQS/DQSn2, DQ[16...23], DM2) and Group 3 (DQS/DQSn3, DQ[24...31], DM3) can be swapped
DQ bit inside a same group can be swapped. But you can't swap a DQ from a group with a one in another group (i.e swapping DQ9 with DQ12 is OK, but swapping DQ9 with DQ25 is NOK)


Also with turn to the 168-ball PoP package which is clearly easier to route in 32 bits than the 134-ball package. But it will also depend of your PCB manufacturer and assembly as the pitch is very fine (0.5mm and 0.65mm).

You can read some recommendations:


Altera EMIF Design Guidelines (go to Chapter 4 for LPDDR2) 
Atmel AN where you can find a schematif for Vref
Micron's TN-52-02 about LPDDR2/LPDDR3 design and layout


But the best will be to contact a LPDDR2 supplier and ask him for help in your design.