VHDL how to make a redundant case statement simpler?
You're basically coding a whole bunch of 4-input multiplexers, so you could either write a function or create a submodule that you instantiate for each one.

function map4 (sel: in std_logic_vector (1 downto 0);
               constant v0, v1, v2, v3 : in std_logic_vector (3 downto 0))
return std_logic_vector is
begin
  case sel is
  when "00" =&gt; return v0;
  when "01" =&gt; return v1;
  when "10" =&gt; return v2;
  when "11" =&gt; return v3;
  when others =&gt; return "XXXX";
  end case;
end map4;

...

r( 3 downto 0) &lt;= map4 (a(1 downto 0), "0000", "0001", "1100", "1101");
r( 7 downto 4) &lt;= map4 (a(3 downto 2), "0000", "0001", "1100", "1101");
r(11 downto 8) &lt;= map4 (a(5 downto 4), "0000", "0001", "1100", "1101");


If the map values are all the same, then you don't need to pass them as parameters.

Of course, with the specific mapping you give as an example, the logic is trivial: bit 0 of the output is simply bit 0 of the input, bit 1 is always 0, and bits 2 and 3 of the output are bit 1 of the input.