Driving MOSFET/IGBT - Why Miller Plateau is a plateau?
The current through the capacitor is nearly steady since it's related to the (assumed-constant) current that the gate driver can supply. Assuming that other parasitics are insignificant, the gate driver current cannot avoid the plateau, only shorten it. 


  If the driver output current is able to source more current than the Cgd capacitor is able to discharge itself, the current should no be a plateau and inversely... why this plateau is so long ... Did I do a mistake ? 


The \$C_{gd}\$ parasitic can be discharged with arbitrarily high current. It shunts gate current away from the gate, preventing \$V_{gs}\$ from rising appreciably, which creates the plateau. 

Here's a detailed transient response (using a voltage source + Thévenin resistance), and a resistive load:




The input voltage begins to rise, at marker V1. \$V_{gs}\$ also starts rising at this time and so does \$V_{ds}\$ due to feedthrough via \$C_{gd}\$. 
At marker V2, the MOSFET begins to conduct. This causes Vds to fall. As Vds falls, current is conducted via Cgd (which looks like a short circuit to fast transients), drawing current away from the gate. This arrests the fall of Vds. In my simulation which used a large Cgd for emphasis, 99% of the available current was shunted via that cap.
Throughout the plateau, we continue to see high current through Cgd. Vgs can only rise slowly--a small-signal slew rate of Vgs by \$\frac{dV}{dt}\$ requires a current of approximately \$C_{gs}\frac{dV}{dt} + (1 + g_mR_{load}) C_{gd}\$. In this region of operation, \$g_m\$ is quite large since the transistor is turning on and hence in its saturation region (where current is controlled primarily by Vgs).
At marker V3, the transistor is turned on fully. Since the drain voltage no longer needs to slew, the plateau is finished and Vgs can now rise quickly.