Verilog code "always @" block not working as expected
Since CLK and counter change at the same time, you get a zero-time glitch on CLK_inner1, which you can't see in waves. Since the simulator senses a change on CLK_inner1, the always block is triggered, and u1 gets the value of Vin.

You must use glitch-free clocks. You should use the same clock (CLK) for all always blocks, such as:

module inp_samp (Vin, CLK);
    input Vin;
    input CLK;
    reg u1 = 0;
    reg [1:0] counter = 2'b00;
    always @(posedge CLK) begin
        counter &lt;= counter + 1'b1;      
    end
    always @(posedge CLK) begin
        if (counter == 2'b01) u1 &lt;= Vin;     
    end
endmodule