Should FPGA interface an IC using more than one IO bank?
It depends. If you aren't using any specialized hardware features and the bank power supplies are the same IO voltage, then there are usually no issues.

Things you might have to watch out for if you want to split an interface across banks:


Bank IO voltages and IO standards. If you need the same IO standard across the interface, then you'll probably need to have to connect the same supply voltage to both banks. There are some exceptions to this, check the device datasheet to see what IO standards are supported at what IO supply voltages. Devices may have a wider selection of input IO standards and things like LVDS may be supported at multiple bank voltages.
Dedicated IO clocking resources. Things like DDR flip flops and IO serdes blocks can require specialized clock routing resources to bring in high speed and/or low skew clocks. These clocks can usually only be routed within a bank or to an immediately adjacent bank. Usually something to watch out for with source synchronous IO, almost certainly on the receive side, but also possibly the transmit side, depending on bit rate and device primitives. 
Regional clocks. Similar to dedicated IO clocks, but can also clock logic. If you need a regional clock for whatever reason, you may be limited in terms of what IO banks you can use based on where the regional clock is driven from and what it is connected to. Usually something to watch out for with source synchronous IO, almost certainly on the receive side, but also possibly the transmit side. 
Specialized IO primitives. Similar to dedicated IO clocking, but more device specific. See things like Xilinx "native mode" bit slice primitives. Clocks and signals may have to be connected to specific pins in specific ways within a bank.