Single-cycle MIPS processor in Verilog (multiplexor)
As far as I can tell, the part you are looking at is a multiplexer without a decoder.
The decoder portion takes an \$n\$-bit number and converts it into a one-hot \$2^n\$ wide signal. Each of those bits in a typical multiplexer would select one of the possible data inputs.
In your case the decoder is part of the control unit, not the multiplexer. Which means your multiplexer needs to select the output based essentially on a priority basis (if you know the signals are one-hot, this simplifies the logic further).

When PCSrcBeq is high, it will select the beq input
When PCSrcJr is high, it selects the jr input
When PCSrcJal is high it selects the jal input
Otherwise if none of them are high, it selects the 0 input.