VHDL: problem getting into state
test only is 1 when this code is entered:

if switch = LISTEN(pointer-1) and pointer&lt;= top_pointer and test = '0' then --  Checks if the switch match the sequence. 
  test := '1';
  buttontimer := buttontimer + 1;
  errorLed &lt;= "01";   
end if;


In this if statement, switch has a value of LISTEN(pointer-1). Then further down in the same process, switch needs to be "0000" and test = '1' in order to hit this code.

if switch = "0000" and test = '1' and buttontimer &gt; 1  then
  pointer:= pointer +1;
  test := '0';
  errorLed &lt;= "10";   
  buttontimer:= 0;
end if;


So, the above code is only going to be entered when switch = LISTEN(pointer-1) = "0000", and buttontimer needs to meet it's requirement too, and pointer needs to hit it's requirement too (so that test can be 1). 

Another note is that since you reset the value of test to 0 at the beginning of the clock cycle, that the value of test isn't going to carry over from one clock cycle to the next.

if control = '1'  and error = '0' then 
  winLEd &lt;= "11";
  Led &lt;= LISTEN(pointer-1);  
  test := '0'; &lt;&lt; remove this line
  ...
end if;


EDIT:
In order to remember test, in the first block of code, remove the test := '0' at the beginning. You are already setting test to zero when the switch is de-asserted.

The FPGA is operating a lot faster than your finger can move. it's going to have run lots of clock cycles between you asserting the switch and de-asserting it. for that reason, you're going to need to remember the value of test, so that when the switch is de-asserted, the FPGA will remember that the switch was pressed. This is why I'm suggesting the removal of the test := '0'.