How is the DDR3 SDRAM addressing done?
This is addressing for individual chips.  There are 6 different chips listed here, three at 512 Mb and three at 1 Gb.  Two of the chips have 4 DQ pins, two have 8, and two have 16 pins.  The DDR3 standard supports 4, 8, or 16 DQ pins per chip.  When chips are combined into modules, you need to get 64 DQ pins in total.  So you could make a module with four 64Mx16, eight 128Mx8, or sixteen 256Mx4, for example.  The address pins are then shared between all of the chips on the module.  It's also possible to build a 'dual rank' module where each DQ pin on the module is connected to two chips.  This increases the memory capacity at the expense of speed - only one rank can use the DQ pins at a time, and the additional wiring for the shared DQ connections limits the speed of the link (higher loading due to two pins instead of one as well as the trace split creating a stub).