What is the max voltage 74HC4067 IC can withstand on output side when non of the channels are selected?
Unfortunately in the Nexperia datasheet that you link to it is not mentioned in the Limiting values (usually called Maximum ratings) that the voltage on any of the pins cannot exceed the supply voltages (Vcc and ground) by more than ~0.4 V.
Some manufacturers have an &quot;overall&quot; datasheet describing the electrical characteristics and maximum ratings of a complete family of (logic) chips in more detail. I cannot find such a datasheet at this moment.
The reason why (as mentioned in the comments) the outputs will be clamped (to about Vcc + 0.6 V) when you apply 100 V to them is the ESD protection circuit. The datasheet does mention input clamping current (max 25 mA) and that is the maximum current that is allowed to flow through the ESD diodes. This schematic shows how these diodes are connected inside the chip:

I got that image from this document parts of which might be interesting for you to read.
Your 4067 chip, like basically all CMOS chips have ESD diodes connected to all their signal pins. Imagine what will happen if you apply 100 V (even if it is limited to 9 mA) to the pin marked &quot;Output&quot;. Then D3 will conduct and try to pull Vcc to 100 V as well!
If that would happen then you could potentially damage everything connected to Vcc.
If there as a voltage clamp between Vcc and ground and you're absolutely sure that never more than 25 mA will flow (even a small capacitor charged to 100 V will make more current flow!) then what you propose could work and might not damage anything but it's like playing with fire, it is a very bad design practice.
If you need to switch something which can handle 100 V then you must use a transistor for example a MOSFET. The 4000 series CMOS logic chips are simply not designed for direct use with high voltages.
Also of interest might be this: HCMOS Design Considerations document.