FPGA register initialization
the FPGA synthesizer ignores these code parts completely?

Both Quartus (Altera/Intel) and Vivado/ISE (Xilinx) respect initial statements for synthesis (as do some others). You can use them to set default (power-on) values for registers and memories.
There are as ever limitations.

Not all FPGA families support setting a power-up value for a register. In some devices all registers will always power up to zero. For such devices, if power up to 1 is required, the synthesis tools will instead do bubble pushing - the output and input of the register are inverted, such that powering up to 0 will give you a 1 on the output.

Not all FPGA families support initialising memory cells (e.g. block ram). For those that don't, your only option is to effectively store the defaults in some other location (e.g. external ROM/Flash, or in LUTs) and copy the values in one by one after the reset is cleared.

Initial blocks only set the power-on value (where supported), not the reset value. You will still likely want a reset signal, during which you can set the value for the register. In fact if you know you will have a reset signal that is asserted before the registers are used, you can simply forego the initial block, and just use the reset to set a default value.

Some synthesis tools will try to infer the power-on value if a register has a reset signal. If you set the value of the register to 1 during reset, the tool will detect this and try to set the power-on value of the register to 1 if possible.



Note: &quot;power-on&quot; in this context is the point at which the FPGA enters user mode. For CPLDs with instant-on, this is nominally when the power supplies turn on. For SRAM FPGAs this is usually after configuration (with partial reconfiguration the lines can blur).