Analog power pins vs Digital power pins on chips
Assuming you mean that you have an analog voltage at the input to a digital gate, then (as already noted) it will sense a 'low' from Vss (usually ground) up to some threshold and a 'high' between some other voltage and Vdd (some positive voltage for most families of logic). Between these voltages the input is indeterminate; i.e. what the input is sensing cannot be guaranteed. The actual threshold is somewhere between the stated guaranteed levels, and varies significantly across batches and temperature.

The issue does not end here, however: if you are feeding a slow input (slower than perhaps 20 nsec / volt) to a CMOS gate, the part will experience significant class A conduction (i.e. both the input stage transistors are on at the same time) and could burn the part out. This has happened to many a person, some of them quite experienced.

When I have a slow signal that needs to enter the logic domain, I use a Schmitt trigger device.

Do a quick search on the implications of slowly changing inputs on CMOS logic.