I2C slave device model for testing?
I2C specifications define certain timing ranges for every signal edge. If you are serious about verification of your master, you need a model that does include both timing boundaries, worst cases, not just the "golden" middle. 

Quality of the model would eventually determine the quality of product and thus its acceptance in marketplace, so this is business, and no-one would share with you tools that give a product some business advantage. So you would need either to write your own good model, or pay big bucks for a full IP package from someone like Synopsis.

Having a good model is a serious job, and it doesn't come cheap.