Implementing a 8X1 multiplexer using two 4X1 multiplexer
Not really.  You either need enable pins on the MUXes, or you need a 2 to 1 MUX on the output.  Seems like the problem statement explicitly mentions enable lines, so that's probably the solution they're looking for.  If you are targeting a particular architecture (e.g. FPGA) then one of these may make more sense.  For instance, you can't do tristates within an FPGA, so you would need to use a 2 to 1 mux.  On an ASIC, you might be able to use a tristate, but you could pay for it in timing performance.  With discrete TTL logic, tristate is probably the simplest implementation if the muxes have output enables.