Bit-accurate modelling for algorithms (FPGAs)
Not an industry standard, but one personal view : my technique is to model the algorithm with a generic package, which I can instantiate with floating point or any fixed point types I want. 

The floating point algorithm comes from C or Fortran or whatever - after rewriting as a generic, I instantiate it with floating point types and verify its outputs match the original.

Then I can instantiate the same code with any size of fixed point, and verify its accuracy meets my needs - modifying the fixed point types (adding higher resolution ones for intermediate results, etc) as necessary.

Translating it into VHDL code is usually trivial; adapting it further (e.g. pipelining it for synthesis) somewhat less so, but at every stage I have a high level bit-accurate fixed point model sa a reference, so I can track any deviation from that.

This assumes you have a language that supports fixed point and floating point types nicely, and allows generic packages and subprograms (like template classes in C++). 

My choice for this (and most general purpose, i.e. non-hardware programming) is Ada-2005 or 2012. 

Its ease of interfacing with C or other languages makes re-using high level models easy, and its similarity to VHDL makes translation to VHDL relatively pain free (though VHDL only supports fixed point types via libraries). Proper fixed point support is much less painful than faking it using integer types, even in a language that lets you define integers of any size you want, rather than the restricted set available in C etc.

As far as I know, System C aims to provide facilities to allow a similar approach, though via add-on libraries rather than inherently in the language. Maybe someone else will comment on how well that works. I can't, as I've never had occasion to use it.