Not gate dividing voltage
Because R4 is connected to the base of Q2 -- when Q1 is off, it forms a load on Q1's collector (R1), so the voltage there won't rise above about 6 V. 

This doesn't really affect the performance of the NOT gate -- its threshold is about 0.8 V, so any input higher than this will be a '1'.

Given that the transistors have a beta (gain) of well over 50, you don't need to use 10k -- you could use (say) 100k. This would allow the '1' voltage to rise to (approximately) 9V*100k/(100k+4.7k) = 8.6 V