How is a Multi-Bit Delta-Sigma Modulator used to toggle the modulus for a Fractional-N PLL?
All you are really asking is how can a divider divide by more than just M and M+1 ratios. If it is to follow a multi-bit control number, it must also have M+2, M+3 and up to M+n ratios.
In practice, it's just as straightforward to make a many-modulus divider as a two-modulus divider. Consider an HC163 programmable counter for instance. It can count up to 15, or 255 if you cascade two. It just depends on programming it to recycle at lower than the maximum count, some general binary number N, as a function of the number coming out of the MASH.
Now there is a very important subtlety. There are two principal ways to do that.
a) One is to let the counter count up from 0, put the number N-1 into one side of a comparator, the counter into the other side of the comparator, and clear the counter next count when the numbers compare equal.
b) The other is to load the counter with MAX_COUNT-N, let it count up to MAX_COUNT, and reload the counter again with MAX_COUNT-N when it gets there.
If you were building a general purpose frequency divider, or even a fixed modulus synthesiser, it would not matter which route you took. If you were building a fractional-N synthesiser, it may (usually would) have a significant effect on your spectral purity.
The delay through a comparator is usually slightly code dependant. This means a cycle ending in x011 might be slightly, but systematically, a different length to one ending in x100, over and above the expected N difference. This leads to a code-dependent jitter in the clock to output delay, causing a non-linearity which mixes the high offset frequency MASH noise down into the baseband where it can get through the loop filters and cause spurious signals.
If the counter always finishes at MAX_COUNT, then the clock to output jitter is only noise-like, which does not cause spurii.
Back in the bad old days, when there was only ECL to count at 100s of MHz, and TTL to count at 10s of MHz, you would often use a dual modulus ECL prescaler, things like 8/9, 10/11, 20/21 were available, and combine it with a TTL control circuit that would allow arbitrary integer division, as long as the total ratio was larger than about N2. So even if the circuit appeared to be using an N/N+1 divider, it may well be doing arbitrary N division overall. These days you can buy arbitrary N counters to GHz, and implement 500 MHz counters in FPGA easily. Check the architecture for systematic jitter before you use them in a fracN synthesiser though.