Noise margins logic circuits
The noise margin is as you have shown in the diagram. Do be aware that a diagram such as this would be much better to place the output data on the left side and the input data on the right side. This way the data flow is more like how we would envision a schematic where circuit flow should would be from left to right.

The noise margin covers several cases as follows (using your diagram numbers).


For the logic 0 noise margin any noise spikes that appear coupled directly onto to the signal line of the driver can be up to 0.4V above the guaranteed output low level of the driver output before the receiver parts input gets pushed into the intermediate zone and potentially cause a problem in the receiver. 
For the logic 1 noise margin any noise spikes that appear coupled directly onto to the signal line of the driver can be up to 0.4V below the guaranteed output high level of the driver output before the receiver parts input gets pushed into the intermediate zone and potentially cause a problem in the receiver. 
For a localized ground noise spike at the receiver that appears as a spike above the ground level as referenced back to the driver the receiver interpretation of the input signal will remain valid as long as such ground level spike does not go above 0.4V.
To a lesser degree for many logic families, a localized VDD noise spike at the receiver that appears as a spike below the VDD level as referenced back to the driver VDD will remain valid as long as the VDD level spike does not go below 0.4V. (I say to a lesser degree because many logic parts high level thresholds are not so sensitive to the positive supply voltage level, especially for bipolar logic families. CMOS parts are a bit more power supply sensitive but at the same time often have greater high level noise margin).