Understanding the working of a NAND GATE using NMOS Transistors
The resistor you see there is called a "pull-up" resistor. The circuit you show can provide a low level at the output, when the NMOS are ON (in the first circuit). But when they are OFF, the pull-up resistor will provide the high level. The transistors by themselves in that circuit, can't provide a high level, only a low one.

Now, as shown no current flows through the pull-up resistor, and that is why the output node stays high. In practice, if you were to connect something to that output, then some current will flow through the pull-up resistor and may drop the high level accordingly, but in most cases probably not enough to cause the output node to be considerably lower than the high level.

When dealing with CMOS logic, you need a pull-up and a pull-down network such that you can get highs and lows. In this case, the pull-down network has been implemented with NMOS transistors while the pull-up has been implemented with a resistor. More typically you will see a PMOS in the pull-up network rather than a resistor.