Code Error 9 In Modelsim
Your simulator should be giving syntax errors before the memory allocation error.

The always block has many errors. First it delete the line i=0;, it is assigned in the for-loop. This allows the begin block called on the always blocks triggered events. Don't use both for-loop and while-loop. Currently both dependent on i and if the code could run you would see i go 1 to 48 with no step in between, and sip_out_i would equal {48{sipo_in}}. Assuming not what you are intending and inefficient if it is.

Having a @(...) nested statement inside another block is legal verilog, but is a bad coding style. Synthesis tools and linting tools will give errors. Nested @(...) and wait statements are more intended for the test-bench framework, and even that is mostly discouraged.

You should use two always blocks. One running on gsclk and the other on sclk. sclk should fill sipo_out_i. gsclk transfer sipo_out_i to sipo_out. Handshake signals will be needed to synchronize the two blocks.