How do I use VHDL generic parameters when I place a sheet symbol in Altium?
I'm not sure a good solution exists.  You could add a second VHDL file that instantiates your first VHDL file's entity with the appropriate generic map.  Then you could just place that second-level VHDL file onto the schematic.

Not ideal, but it maintains reusability, as you can just make new second-level files for every different size you want, and you only have to change the first-level file to affect all instantiations.