Why are PCIe Completion Timeouts specified as ranges?
I don't know the details of this PCI Express Base specification, but it seems to me that it basically works like every other bus protocol: 

If you specify a timeout range in your driver, this does mean that the master or slave device must be able to meet this timeout. So a configured 50us to 10ms timeout means that "something" must react within this range or the protocol will fail. 

I try to explain it by another "real-life" example: The timetable for bus A says the bus is leaving between 8-12 a.m. and the timetable for bus B says this one is leaving between 9-11 a.m. You must decide which bus you want to take (driver configuration), but you will not be able to tell exactly when each of the busses A or B leave.