LTSPICE Simple MOS-FET Stacked Current Mirror/Cascode saturation threshold less than expected
It is indeed working as expected for level 1. The trick is that you will not see the obvious saturation drops when fully zoomed out. However, if you zoom way in before current mostly flattens out (or look at output resistance), you can see that there is indeed a transition that is an expected number of VGS-VT drops, before both transistors are fully saturated. I used two diode connected transistors here (vt + 2*vdsat min), but the concept does not change. It is a fundamental one related to compliance of devices.