Serial Adder vhdl design
z : out std_logic_vector(n - 1 downto 0));
The output must be std_logic, because it is a serial output

Also, you can use the + operator directly to the std_logic_vectors. Just add the "ieee.std_logic_signed" library
So that you can write z_reg &lt;= x+y; 

if rising_edge(clk) then
            if clr = '1' then --clear all the registers, and flip flop

            c_reg &lt;= '0';
            z_reg &lt;= (others =&gt; '0');
        elsif load = '1' then
            z_reg &lt;= x + y;

        else --execute sum       

            --full adder logic      
            z &lt;=  z_reg(0);
            z_reg &lt;= '0'&amp; z_reg(n-1 downto 1);
        end if;
    end if;