Verilog - connecting multiple bidirectional buses
Think of this in terms of hardware. RAMdataBUS outputs data or is tri-stated. But CPUdataBus is a mux. You can't connect a tristate to a mux. You can connect a tri-sate bus to anther tri-state bus.

Assuming write is the CPU write the CPU bus should be driven when writing, but tri-state when reading:

assign CPUdataBus = write ? CPUdataOut : 8'hZZ;


The memory bus should be driven (by the memory) when reading, but tri-state when writing:

assign RAMdataBUS = !write ? memory_data_out :  8'hZZ;


But that is not correct if you have multiple memories. Then it becomes:

assign RAMdataBUS = !write &amp;&amp; this_mem_selected ? memory_data_out :  8'hZZ;