Why is CMOS fall time faster than rise time?
The answer lies in Carrier Mobility of Silicon. A CMOS stage has a P channel device from Vdd and an N channel device to Vss. Note the much higher mobility of electrons vs. holes.

The rise time at the output depends primarily on how fast the P channel device can turn on, and the fall time is determined primarily by how fast the N channel device can turn on.

The majority carrier in P channel devices is holes, and the majority carrier in N channel devices is electrons.

As electrons are in the conduction band and holes are in the valence band (same link), N channel devices are inherently faster in switching than P channel devices given equal physical parameters.

In many newer logic families, the length - width ratios of the transistors are adjusted to give symmetric switching times.