How does a "standard" ripple carry adder behave?
My doubt is how standard ripple adder behaves?  


The standard gate delay behaves like 2 and that is correct. Adders do not deactivate.
This logic is called asynchronous and the output of the gates do not change until the signal 'upstream' changes. This means that if A or B changes, then Cout will be the last to change. This also means a propagation delay while chaining gates, and the propagation delay gets larger when chaining.


https://allaboutfpga.com/vhdl-code-for-full-adder/

(In the picture above the delays are difficult to see for this simulated full adder because the gate delays are so small, many adders could be chained before the gate delay could be noticed.)

In modern digital logic there are other ways to overcome the gate delay.
First off most gates have a small delay in the nano-second range.
Secondly, by adding more gates, the propagation delay can be reduced. The Carry Look Ahead adder does this:


Source: https://www.geeksforgeeks.org/digital-logic-carry-look-ahead-adder/

The last thing that is worth mentioning is clocks and memory (in the form of flip flops). Usually the logic is stored in memory by a clock, the logic is designed in such a way that the values of the logic are finished changing before a clock edge (when values are stored). This enables better stability and certainty in the logic operations in a microprocessor or FPGA.