Modelsim - Weird verification problem with DDR and Xilinx UNISIM
I finally solved it - problem was in Xilinx unisim library. For some reason, there is 100ps delay (which shouldn't be in behavioral simulation) in IDDR.. So solution is to wait in monitor (I have actually two - for input and output of DUT):

forever
begin
  my_transaction tx;

  @(posedge dut_vi.clock);
  #1ps
  tx = my_transaction::type_id::create("tx");

  tx.ctl   = dut_vi.ctl;
  tx.reset = dut_vi.reset;
  tx.data  = dut_vi.data;

  aport.write(tx);

  @(negedge dut_vi.clock);
  #1ps
  tx = my_transaction::type_id::create("tx");

  tx.ctl   = dut_vi.ctl;
  tx.reset = dut_vi.reset;
  tx.data  = dut_vi.data;

  aport.write(tx);
end


and second one:

forever
begin
  dut_out_transaction tx;

  @(posedge dut_out_vi.clock);
  #101ps   // simulation hack
  tx = dut_out_transaction::type_id::create("tx");

  tx.dv    = dut_out_vi.dv;
  tx.err   = dut_out_vi.err;
  tx.sof   = dut_out_vi.sof;
  tx.eof   = dut_out_vi.eof;
  tx.data  = dut_out_vi.data;
end


In the input monitor, I have to wait 1ps (didn't figure out why) and in output, I have to wait 101ps due to delay inside IDDR (I checked the code). This way, scoreboard gets correct data.