Altera Max10 altPLL slack
Some updates. If it helps anyone:


"Timing requirements not met (inst5|altpll_component|auto_generated|pll1|clk[0] setup slack: -2.197, endpoint tns: -8.124) on the PLL output."
This warning occurred because I was using in the design both the 8mhz PLL clock input and the generated 80mhz PLL output. Possibly generating meta-stable conditions. Solution was to divide the generated 80mhz back to 8mhz using a simple counter so both 80 and 8mhz could be used in the design.
"PLL xxx is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input". This error message disappears when solving the above.