Having issue with draw timing diagram for logic circuit
Normally when doing this you start from the left, identify unique nets (Signals) and work your way right.

In this instance they made it easy for you since A,B and C as defined, though you may want to name and plot the output of than AND gate and also show \$\overline C\$ for completeness.

\$\overline C\$ is actually your first unique net anyway.