How is the assignment squence in Verilog?
The answer to this question is strongly related to Verilog concepts I described in my answer to another question about Verilog non-blocking assignment (NBA).

The straightway answer to your question is very simple: all assignments are performed at the same simulation time slot, i.e. both blocking and non-blocking assignments will be evaluated and assigned before the following time slot (which starts with negedge GCLK in your case).

The details, however, are important!

NBAs are not assigned at evaluation time, but at the end of the time slot. This means that if you use foo for evaluation of other expressions (for example assign blocking = foo; or always @( negedge GCLK ) non_blocking &lt;= foo;), the value used will be the value foo had at the beginning of the time slot. The net result of this behavior is that it seems like foo gets its new value only on the next clock cycle. 

However, the above description is just a simplification. I strongly recommend that you read this SNUG paper thoroughly and make sure you understand the fine details - this will make you much more comfortable with Verilog and may prevent many nasty bugs and mismatches between RTL and FPGA simulations. Specifically, section 2.0 (Verilog Event Queue) contains the information directly related to your question.

Hope this helps.