What accounts for the current vacillation in this JK latch?
Flickering happens when the output changes from 1 to 0 because the two inputs to the NOR gate take different delyas to arrive.  

Consider Q=1.
In this state the two inputs at the top NOR gate are 0,0.
The output will change to 0 if any of these inputs become 1.  

Now put J=0,K=1 and apply clock:
First, it can happen that the clock reaches the top NOR input quickly and turns it off.
Then, the Q output fedback to the top AND gate makes its output low and turns on the NOR gate again.

So far, the Q' output of bottom NOR gate hasn't changed, it remained at 0. When this output changes to 1, the flickering of the top NOR ends and the Q output becomes a stable 0.