4060BE Starts With Output High
If you followed the rules in the datasheet. and your power up Vcc rise time (10% to 90%) is less than than T2= R2C2, then  the initial condition is $0.

Check this assumption and increase R2C2 while satisfying below datasheet requirements to fix your problem.

The capacitor to ground C2 serves two purposes; one for power up reset and the other for steady state 50% control of the RC oscillator duty cycle.


Either input =0 to NAND forces rising edge clock=0 
acts as a low pass filter of the clock to guarantee a 50% duty cycle 


this is a negative feedback loop, DC gain =1 relative to internal gate thresholds for Nch and Pc

gain >= 10x per FET CMOS stage thus astable clock conditions are met



In summary, if you ignore MR=0 the forcing functions that control the counter clock input are the input Cap C2 which is inverted on the 1st CMOS gate and follows the supply cap on Vcc.  Both will rise with Vcc but C2 will settle to Vcc/2 upon which the 1st CMOS stage becomes a linear amplifier and it's output inverts from Hi to Low as Vcc is rising and thus the 2nd CMOS inverting gate gets it's 1st rising edge as the counter clk input. Then the next clock edge is determined by R1C1 time constant so R2C2 determines the latency needed to let power up stabilize. 


There "may" be a glitch or metastable condition where a few xx nanosecond glitch equal to the Vgs threshold , which the older CD4060 family IC's ignored due to bandwidth limits but perhaps the 74ACT4060 responds from some suppliers or your supply has excessive ripple during power up and you learn to understand 



  that ALL LOGIC have ANALOG characteristics.


This compatibility flaw is when the designer learns to follow standard practice of a separate discrete Power On Reset controlled starting condition for all bistable logic to prevent POR race conditions or other undesirable characteristics.