Dual port, serial interface, buffered, shift register
This seems to be an ideal application for an FPGA. Even a relatively small FPGA could support 16 distinct SPI interfaces to the ADCs, and creating a 289-bit shift register is pretty easy. The choice of a particular FPGA will depend on other design constraints, such as available voltages, power limits, physical size, and cost. I've hacked together SPI interfaces for both an ADC and a DAC using Verilog. 40MHz is also not a particularly high frequency for modern FPGAs.