Truth Table for JK flip-flop circuit?
You've already derived the equation for the input to the D input of the flip-flop:

D = (J • \$\mathsf{\small \overline{\text{Q}}} \$) + (\$\mathsf{\small \overline{\text{K}}} \$ • Q)

So you can construct a truth table for this equation:

J  K  Q     D
-------    ---

0  0  0     0
0  0  1     1
0  1  0     0
0  1  1     0
1  0  0     1
1  0  1     1
1  1  0     1
1  1  1     0


Note because it is a clocked flip-flop, the Q and \$\mathsf{\small \overline{\text{Q}}} \$ will not reflect the state of D until after the clock pulse (rising edge of Clk).

Also note that when J and K are both 1, the output toggles, which is the correct behavior for a J-K flip-flop.