Sequential circuit modelling using structural verilog description
Flip-flops and latches are usually implied in HDL synthesis from a behavioural description where a value needs to be stored either between clock edges (flip-flop) or dependant on some other value (latches). It is not really necessary to make them explicit.

If you are using modules to describe basic gates for a structural description these will be vendor specific and you will need to look at the documentation from you vendor to determine the correct names. There are many types of D-type flip-flops all of which might have a different name. 

If it was me I wouldn't try and implement something like the CORDIC algorithm directly with a gate level structural description. I use a behavioural description appropriate for the synthesis tools to do most of the gate level work (such as implying registers) for you.