Multiple DDR3 memory VTT source
I am using a separate VTT LDO per CPU/FPGA&lt;->RAM pair. E.g. if I have a FPGA with two memory chips plus DSP SoC with two memory chips, I use two VTT LDOs. The problem is that if one device does a burst and the current rises, another chip burst could possibly fail if the current is too high. It is expensive, but works good.