What is the difference in assigning output before end process and after end process in VHDL
In a sequential process the signal is assigned with the next event.
If it is not in a clocked process the signal is assigned immediately.

But another thing is you have this block in your VHDL description:

process(clock_50M)
begin 
    if (clock_50M 'event and clock_50M='1') then 
        r_1&lt;= r;
        r_2&lt;=r_1;
    end if ;
    r_delay1&lt;=r_1;
    r_delay2&lt;= r_2;
end process;


This is not synthesised in a way you want.


You should put the r_delay1 &lt;= r_1; and r_delay2 &lt;= r_2; inside the if to determine on which clock edge it should happen. There are no Flip Flops reacting to both.
Do not use clock_50M 'event and clock_50M='1' use rising_edge(clock_50M) it is more readable