3-Stage Shift Register using Blocking assignment in Verilog - Differences among simulators
You din is changing at the same time as the clock edge. This is a race condition and as such the behavior of the simulator is not defined. 

This is because you use blocking assignment here:

always@(posedge clk) begin
   if(rst_n) begin
      din = 4'd15;  // &lt;&lt; WRONG!
   end
end


Change that to a non-blocking assignment:

always@(posedge clk) begin
   if(rst_n) begin
      din &lt;= 4'd15;  
   end
end


But also change all your other assignments to non-blocking :
The only reason it is working at the moment is accidentally because you put the assignments in the order q3..q1.

always @ (posedge clk or negedge rst_n) begin
   if(~rst_n) begin
      q1 &lt;= {(DATA_WIDTH){1'b0}};
      q2 &lt;= {(DATA_WIDTH){1'b0}};
      q3 &lt;= {(DATA_WIDTH){1'b0}};
   end else begin
      q3 &lt;= q2;
      q2 &lt;= q1;
      q1 &lt;= din;
   end
end