Which gate is better in building the Full Adder ? XOR or OR
If I were doing a silicon implementation, I would use an XOR because of the symmetric properties.  Symmetric circuits use much less power because the stack size is the same that does a few useful things: 


Greater effective serial resistance when "off" due to the "stack of 2",
Better matched channels because DIBL is the same on pull up and pull down networks,
More uniform switching time because charge sharing is similar (very dependent on #2),
Usually, better devices as far as lithography so better threshold matching.  


A very complete discussions exist for "mirror adders" if you look out there, but they probably only mention #1 and #2.

If you have it in a package, none of this matters.

One thing that will not be in the discussions will be that at smaller feature sizes, we try to do everything as symmetric as possible because of metal rules and coloring.  Below is an export image of an XOR from a commercially available FinFET process at 14nm that illustrates the metal coloring. The blue/lighblue are different lithography steps.