Resampling with MSB operation
1) Don't mix = and &lt;=, they have different meanings and some tools will object.

2) "assign" is basically wiring one thing to another, it should not be used in "always" blocks.

3) You've not assigned bb_sample.

My version:

// 'reg' by itself is a single bit, need two bits for 0-3
reg [1:0] count = 0;

always @(posedge clk)
   if (ddc_out_strobe) begin
     i_msb &lt;= ddc_chain_out[31:24];
     q_msb &lt;= ddc_chain_out[15:8];
     if(count == 2'd3) 
         bb_strobe &lt;= 1'b1;
         count &lt;= 2'b0;
     end
     else begin
         count &lt;= count + 1;
         bb_strobe &lt;= 1'b0;
     end
   end
   else begin
      bb_strobe &lt;= 1'b0;
   end
end