How Would a CPU Improve if its Logic Circuits were Reduced?
I worked for a decade at a startup doing computerised logic improvement for chip designers; we were eventually bought by Cadence.

We had, among a whole bunch of other tools, a heuristic logic minimiser. It was a fairly simple thing that just pushed "bubbles" (negations) around, and attempted to absorb gates into the slightly more efficient AOI or OAI composite gates. It would then compute a cost function to see if this was a good idea.

What turned out to be far more critical was logic duplication. It seems counterintuitive to add more gates computing the same logic function, but the important thing in ASIC performance is the critical path. The logic path that takes longest to compute determines the speed of the whole chip. Adding additional outputs from a gate slows it down, especially if those outputs are to far-away locations. You could get a noticeable improvement by having two copies of logic to compute f(A,B,C) where one was "fast" and close to where it was needed and another "slow" one to a less-critical destination.

The extreme of this is buffering. A naive logic removal function would take out all your buffers - after all, they're just the identity function - which would save you a lot of area but ruin the speed.

Optimal logic placement is, I think, also NP-complete. It's very similar to subset-sum. Again, this is one of those problems which is easiest to solve in practice by pretending it's linear, throwing it at an LP-solver, and having other bits of program go round tidying up the nonlinearity.