Will this code create a latch?
No, this code should not infer latches. It is the case in all the synthesizers that I saw.

The reason is that a synthesis tool will infer flip-flop for any signal which is assigned inside a sequential block of code (@(posedge clk)). For all the branches which do not have an explicit assignments, the synthesis tool just muxes the output to the input, but since it is initially a flop, there is no concern.

What you're saying about latches applies to conbinational logic. For example, the following code infers latches for both myvar2 and myvar3:

always @* begin
 if (enable) begin
   myvar1[63:0] = some value;
   myvar2[63:0] =some value2;
   myvar3[63:0] = value3;
 end else begin
    myvar1[63:0] =othervalue
 end
end


Synthesis tries to mux the output to the input, but this requires a "memory" element to be in place in order to prevent a "loop". Latches controlled by enable signal will be inferred.

Hope this helps.