How to divide complex number in VHDL?
You've got the right idea with that first equation. You've just got to do some more algebra:

$$
c = \frac{a_r + j a_i}{b_r + j b_i} = \frac{(a_r + j a_i) (b_r - j b_i)}{b_r^2 + b_i^2}
$$

$$
c = \frac{a_r b_r + a_i b_i + j a_i b_r - j a_r b_i}{b_r^2 + b_i^2}
$$

$$
c = \frac{(a_r b_r + a_i b_i) + j (a_i b_r - a_r b_i)}{b_r^2 + b_i^2}
$$

$$
c = \frac{a_r b_r + a_i b_i}{b_r^2 + b_i^2} + j \frac{a_i b_r - a_r b_i}{b_r^2 + b_i^2}
$$

Yes, there are a lot of operations required. Looks like 6 multiplies, two additions, one subtraction, and two divisions. Yes, implementing this in Verilog/VHDL will be rather complex. If you don't need maximum throughput, then you can probably get away with one multiplier and one divider and then sequence the operations with a state machine. Compute the denominator first, store it, then do the numerators, computing the second one while the divider is working on the real part of the output.