50MHz clock level shifting from 1.8V to 3.3V using IC
If the edge speed is 10% of the period, that being 20 nanoseconds, then a 2 nanosecond edge speed up and 2 nanoSecond down seem good. That is 5v/2nS = 2.5 volts/nanosecond, into at least 20pF Cload.
And place a 0.1uf cap within 1mm of the VDDpin. Over a gnd plane, for low EMI and low jitter. You might even insert a series 1 ohm or 10 ohm resistor, between the cap/level-shifter and the other +5 loads, to better isolate the level-shifter current demands from other +5v demands.
Without some series impedance, your 0.1uf is being used to help provide the transient charge needs of all your other ICs on the +5 VDD trace,. So use the series impedance to reduce the effects of that copper trace.