Why N-channel MOSFETs are better than P-channel MOSFETs?
Since you haven't specified I will choose my domain of answer: chip design.
The answer really depends ... NMOS is not always better than PMOS in all areas.
Carrier mobility:

most modern CMOS processes are on &lt;100&gt; crystal orientation wafers.  In this system since the transistors are in a common substrate there will be a ~ 2.2X factor in mobility between electrons and holes.
- however, when they are separate devices like discretes, a different crystal orientation could possibly be used so the mobility argument will be weakened (but electrons will always have better mobility than holes in silicon).


processes around the 65nm node started using stress/strain to more closely match the mobility between the two type of transistors, mainly for size savings.  Intel is a prime example of this approach.


Substrate connection:

Most CMOS processes are on P-type wafers with dual well implants.  That means that NMOS transistors have all of their wells at the ground potential (unless they are triple well processes).  That means that the bulk connection for a unity gain follower using a NMOS device will be at ground and the back gate effect will be present that reduces the gain to ~ 0.8.  When implemented with PMOS devices with the bulk connection tied to the source, the gain can be 1.0.

Noise:

PMOS transistors at process nodes above 0.35u were typically buried channel devices (due to process techniques used at those nodes).  these devices had much lower noise than NMOS transistors in the same process  node.  Simply because the channel was kept away form the Si/SiO2 interface states at the Si - Gate Oxide boundary.  This is particularly true of flicker noise.

PMOS transistors below 0.25u mostly were surface channel devices and as a result they picked up NTBI (Negative Temperature Bias Instability) noise like characteristics.


Process variability:

because of the larger sizes required to match the \$G_m\$ PMOS devices are larger and therefore are better matched with fewer effects from LER (Line Edge Roughness).