For two clocked components in series, how do you ensure that the output of the first is captured by the second?
The address register can be clocked on the same edge as the program counter, depending on the setup and hold times of the blocks involved. Some parts have a zero or even slightly negative hold time, meaning you won't need to worry about the minimum propagation delay of the counter and ROM. Otherwise you have to ensure that the output of the ROM is stable for the hold time requirement of the register, as well as that it is stable in advance of the edge by the setup time requirement of the register. 

Of course, in that case, the register clocks in the value that had a read initiated on the previous clock edge.