Applying negative voltage to CMOS chips
In order to have EOS protection diodes faster than the FET they are protecting they must be small and ESR , Imax, Pd are all related and inverse to speed.

These designed to protect against shoot-thru parasitic SCR effects in CMOS.







simulate this circuit &ndash; Schematic created using CircuitLab

Thus they use 2 diodes for each rail with 10k between them to make a better clamp and often specify not to exceed 5mA.  If you cannot guarantee this then you must add more Schottky or TVS diode protection.

Faster logic may have even lower DC current limits.  TI says 2mA www.ti.com/lit/an/slaa689/slaa689.pdf