How does TTBCR affect low addresses in ARMv8-A?
For Arm cores, and particularly for high-level behaviour, the first reference should be the 'Arm Architecture Manual' for the correct architecture. If you are looking at ARMv8, you will also need to look in the specific section that relates to AArch64 or AArch32 in some cases.

The architecture reference for a specific core will describe if there are implementation defined aspects of the feature. These will them be described in the TRM (Technical Reference Manual) of the specific core. Some new features are sometimes first described as implementation specific features (in a new core), and then later adopted as architected features. You will also observe registers existing in one version of the architecture (or being introduced in a core), and then later version of the architecture widening the possibilities of implementation (e.g. behaviours defined for EL2 or EL3).

For example, ARM DDI 0487C.a ARMv8, for ARMv8-A


  T0SZ, bits [5:0] The size offset of the memory region addressed by TTBR0_EL1. The region size is 2(64-T0SZ) bytes.
  
  The maximum and minimum possible values for T0SZ depend on the level
  of translation table and the memory translation granule size, as
  described in the AArch64 Virtual Memory System Architecture chapter.