Parameterized Instantiations and Module Instantiations
Two objects in C++ are physically two regions in memory of some microprocessor system. Two instances of modules in Verilog are two packs of logic gates and flip-flops with separate connections to the outside world. It's like comparing Sunday to a blue color, are they similar? How would you answer? :)

Try to forget any comparisons between "normal" programming languages (C/C++/Java etc) and HDLs -> hardware description languages (verilog, VHDL). The former are supposed to be executed sequentially on microprocessor, the latter are implemented in hardware (as logic gates, registers, flip-flops, RAM blocks and many more).

The concepts are so much different that it's pointless to compare them. If you try thinking of Verilog code in terms of C++, then it will give you a lot of headaches.

Read carefully some good book on Verilog/VHDL, everything should be explained :) Good luck!