Understanding processor instruction pipeline problem solution
If I'm reading the question correctly, it does not mean that ALU-ALU forwarding is forbidden in an LW instruction but rather the new result from the load will not be forwarded from the MEM stage, thus you now have a data hazard between I2 and I3 in a. (Edit: the MEM forwarding is actually moot here since the EX stage of I3 happens at the same time as MEM stage of I2 so any forwarding will be too late). 

If this is a classic RISC pipeline then you simply need to add (edit: two to account for both MEM and WB) NOP between the LW and the ADD to avoid the data hazard here. 

The solutions you found are true only of ALU-ALU forwarding does not occur.