Putting linear feedback shift registers on FPGA's
Event the very smallest FPGAs, and most CPLDs can do this. Each element of the shift register needs a single FF element, call that 1/4 of a slice, the xor for the tap logic will go into the LUT. Look at your datasheets, anything with > 300 slices should do it. You'll need extra logic to pre-load a value, control reset and sample the outputs, and probably clock enable logic as you would not want it free-running with the global clock while you read the final state.