How to read timing diagrams: ak4554 audio serial interface
In this datasheet it is written that LRCK is clocked at sampling frequency. 


Yes, LRCK is the sample clock.


  data-in is 96 times sampling frequency.


Nope. Check table 1 on page 9: SCLK should be either 32Fs (which is the minimum for 16 bit stereo, ie 2x16=32 bits per sample) or 64Fs.

Page 7 mentions a minimum period of 1/(96Fs) for SCLK, but this is only a timing spec.


  The device is 16 bits so what should I do to data-in in rest of 80 cycles? 


If you use SCLK=32Fs there are no extra cycles. If you use SCLK=64Fs then simply add 16 zero bits as shown on Fig.3 page 10.I suffest using 32Fs since this is simpler.


  In the datasheet it is not written anywhere that the data is latched at certain time... 


Simply send the bits as shown in Fig. 4.


  Can I do other tasks in my processor during that time? 


Of course! Since your micro has an audio I2S/LJ/RJ interface with DMA, simply set it up and it will play your audio.

If your micro does not have this kind of interface, then use a micro that has one!


  What is the easy way to produce sound messages while struggling with other tasks in simple microprocessor-peripheral systems?


If you want super low quality audio, use your micro's PWM and do it in software. If you want to use that CODEC chip then I supose you want higher quality, so you will have several MBytes of flash to store your samples, and a micro with DMA able to stream them.