In which CPUs will write-after-write and write-after-read dependencies cause a hazard?
All pipelined processors are susceptible to this.  There's a particularly good technote on resolving this on the SPARC due to the pipeline and local register windowing with functions.

1: add $1, $2, $3 ;writes to $1
2: mul $4, $1, $5 ;reads from $1


In the code above, the Read-After-Write hazard exists as 2 reads $1 before the writeback.  If you have pipeline of any depth.

Write-After-Read and Write-After-Write dependencies do not cause pipeline hazards.