How to write a counter in verilog for debouncing an input?
If you're going to insist on using three always blocks for every state machine (excessively pedantic and verbose, in my opinion), you need to do it right: Only the process that updates the state variables should be clocked &mdash; the others (marked "next state CL" and "output CL" in comments) should be purely combinatorial; i.e., always @* begin ....

With all three processes clocked in each case, you've got some extra "pipeline" stages going on that are probably messing up your logic.

EDIT:

Although on further perusal, I don't immediately see anything wrong that jumps out at me, assuming that my guesses about how the two modules are wired together are correct. I'd have to see your top-level modules (both versions) to be sure.

When you "use no counter", what are you doing with the wait20 input to the scanner module? If you tie it high, then the next state logic will never run, but if you tie it low, the keyCode output is never set.