Hold Time Violations with Shift Registers/Ring Counters
There are two ways to do this and a lot depends on the technology of the D types. When the D type has a significant hold time then you need to run the clock as you have shown and making ring counters or other circular shift registers will be impossible unless you add an extra flop or latch at the high end of the register to temporarily store the top or end bit until the clock reaches the other end.

Even with this you are faced with a race condition of clock propagation against the last D flop propagation delay+first flop setup time. 

Most technologies today have a low or zero hold time requirement. In this case you can concentrate on getting the clock to the all flops at the same time using a "clock tree". In this you drive multiple flops from one buffer, if you cant drive all the flops from one buffer you use multiple buffers and balance the fan out of each in an attempt to keep propagation times the same.