Why FPGA's have latches when they are almost never used?
Here's a rough list on why latches are in FPGAs:


Sometimes it is the only solution.  Usually when interfacing to old standards and/or equipment.
Despite FF's being better some people insist on using latches.  Those people also are willing to spend money on FPGAs.


And that's all I can think of.  In the past 10 years, I have only used a latch once and it was for interfacing to a PowerPC where the multiplexed address/data bus required a latch to un-multiplex.