Instantiating module inside for loop
There are two problems.


First, you can't use integer as the type of an input port. In fact, iverilog seems to treat it as equivalent to reg, which means you can't use it in assign statements either. You need to replace it with a wire with an explicit width.
Second, the limits of a for loop need to be known at compile time, so you can't base it on an input port. dec_width must be a module parameter instead.
Also, there was a minor problem with declaring an explicit width of 1 bit for your case values.


Here's a version of your code that compiles cleanly with iverilog -tnull ...:

module dec_to_bcd_0_to_9 (dec, bcd);
  input [31:0] dec;
  output reg [3:0] bcd;

  always @* begin
    case (dec)
      'd0:     bcd = 4'b0000;
      'd1:     bcd = 4'b0001;
      'd2:     bcd = 4'b0010;
      'd3:     bcd = 4'b0011;
      'd4:     bcd = 4'b0100;
      'd5:     bcd = 4'b0101;
      'd6:     bcd = 4'b0110;
      'd7:     bcd = 4'b0111;
      'd8:     bcd = 4'b1000;
      default: bcd = 4'b1001;
    endcase
  end
endmodule

module dec_to_bcd_any_number (dec_num, bcd_num);
  parameter dec_width = 5;
  input [31:0] dec_num;
  output [4*dec_width-1:0] bcd_num;

  wire [31:0] temp1, temp2;

  assign temp1 = dec_num/10;
  assign temp2 = dec_num%10;

  generate
    genvar i;

    for (i = 1; i &lt;= dec_width; i = i+1) begin
      dec_to_bcd_0_to_9 a (temp2, bcd_num [(3*i)+(i-1):4*(i-1)]);
      assign temp2 = temp1%10;
      assign temp1 = temp1/10;
    end
  endgenerate
endmodule