How do modern CPUs treat memory operations?
Most modern CPUs (except possibly for some small embedded ones) use multiple levels of data cache between the CPU and memory subsystem.  Possibly write buffers as well.  So single bytes might be written to the a write buffer or inserted into a first level cache line. But then entire multi-byte cache lines are read from and flushed to DRAM memory, level by level, before and after, at times dependent on various cache hit, miss, pre-fetch, and dirty flush algorithms.  For IO, non-trivial PCI and on-chip controllers have different strategies for dealing with on-chip resources and devices connected to external pins that have physical buses with less than cache line or processor register size widths, using shifters and field extractors, etc.
The size of the actual physical buses (wiring) can vary widely within a single CPU or system, from many multiples of the register size, down to single bit serial.  Some are data only.  Some combine data with addressing and control bits.  So there is hardware to decipher, serialize and deserialize, pack and unpack the bits, as needed.
The memory subsystem as well can have physical bus sizes that are very different from either CPU register size, internal bus sizes, or cache line sizes.  All the way down to various serialized connections.