Is XADC synchronous in Artix 7 Series FPGA?
Yes, it is synchronous. The track and conversion processes inside the ADC themselves are synchronous to the clock, so naturally the flags are as well. You can see this in the timing waveforms in Chapter 5 of UG480.

I think you misheard the point about different voltages. The XADC can always sample at 1 MSPS, but you might choose to slow it down to allow for the signal to settle by either slowing the clock, setting the ACQ bit, or using event timing instead of continuous sampling (See the section "Adjusting the Acquisition Settling Time" in Chapter 2).

UG480 - XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter