The control voltage output for a phase locked loop
To properly design a PLL from scratch requires , understanding of Loop transfer functions of each element and closed loop under various conditions.  

Lock-up time, Jitter reduction of clock. Phase Margin. bode Plot, lead-lag compensation filter. 2nd, 3rd or 4th order. ( See Analog devices jitter reducing PLL clocks)

Phase detector gain and limitation with frequency error, test methods of measure phase margin and stress conditions: data patterns, SNR, Temp, voltage

There is more but you have successfully detected your phase error as a control voltage ripple from charge pump filter.  

The first step should be to define your design goals and specs, then validate.

Then you can decide if it is right or wrong!

I think it can be improved. But you can use V/MHz and integrate V to get phase jitter over the time 8n interval of Vc for vco, but don't stop there.