Problem in Clock Gating Control with ARM Tiva C
As I recall this is a known issue with the Tiva processors: you have to wait two or three clock cycles after enabling the clock before you can actually use the peripheral. Some people would, sadly, add a statement that just reads the value in some volatile register to kill time. Unfortunately, sometimes one statement wasn't enough. The situation lead to some very ugly hacks.

TI eventually added the General-Purpose Input/Output Peripheral Ready (PRGPIO) reister. This register has one bit for each port, and you can read the bit to see when the port is ready to use. Similar registers are available for other peripheral devices, such as the Universal Asynchronous Receiver/Transmitter Peripheral Ready register.