Verilog to Logic Diagram
Start by tidying up the code. Whitespace makes it readable.

module CNT1 (Q, QN, To, CLK, D, L, RB, Ti);
    output Q, QN, To;
    input CLK, D, L, RB, Ti;

    reg q, tout;

    function mux;
        input [3:0] in;
        input [1:0] s;
    begin
        case(s)
            2'b00: mux=in[0];
            2'b01: mux=in[1];
            2'b10: mux=in[2];
            2'b11: mux=in[3];
        endcase
    end endfunction

    always @(RB) begin
        if (!RB) begin
            assign q=1'b0;
        end else begin
            deassign q;
        end
    end
    always @(posedge CLK) begin
        q = mux({D,D,~q,q},{L,Ti});
    end

    always @(Ti or q) begin
        tout = Ti&amp;q;
    end

    assign To=tout;

    assign Q=q;
    assign QN=~q;

endmodule


Next you can start breaking it down. Lets look at the three always blocks first. From the bottom up:

always @(Ti or q) begin
    tout = Ti &amp; q;
end


That's fairly straight forward. Just an AND gate. Your diagram successfully identifies this.

Next up:

always @(posedge CLK) begin
    q = mux({D,D,~q,q},{L,Ti});
end


That one is a bit more awkward as it uses a function call. Now looking at the function you can see that it is nothing more than a mux (as the name suggests) that has 4 data inputs, and a 2-bit select. Every time there is a positive clock edge, q is updated with the output of the mux.

This block is one place where your diagram goes wrong. We have the following assignment statements:

assign Q = q;
assign QN = ~q;


Because Q = q, your Q output in your diagram should not be the mux output, but the register output. Additionally you are missing the QN output which is the inverse of q.

Finally we have:

always @(RB) begin
    if (!RB) begin
        assign q=1'b0;
    end else begin
        deassign q;
    end
end


This is ugly in my opinion. It is using something called "Procedural Continuous Assignment". What the block is saying is if RB is 0, force the output of q to 0. When RB goes to 1, release the output q.

The key term here is "release". When a signal is released, it will hold it's value until another block updates it. 

This means it is not inferring a mux, because a mux would immediately change the value back to q after the signal is released, whereas the behaviour we need is to hold the current value until next time q is changed.

This behaviour is actually an asynchronous reset signal. The equivalent code for q, combining both always blocks to make it far more readable is:

always @(posedge CLK or negedge RB) begin
    if (!RB) begin
        q = 1'b0;
    end else begin
        q = mux({D,D,~q,q},{L,Ti});
    end
end


You should now be able to correct and complete your logic diagram.