Does splitting the clock signal into several inputs cause problems with system stability?
Your clocking arrangement is difficult to analyze by inspection. You generate a &quot;clock&quot; signal, pass it through an inverter and use that as the inverted clock for IC10. IC10's output is passed through an RC network, two Schmitt inverters and then IC11. An output of IC11 is then fed all the way back to the reset input of IC3, which is clocked on the original non-inverted clock, and IC5, which gets one of your inverted clocks.
I would be concerned about the timing relationship between the reset input and the clock input of IC3 and IC5. You need to make sure there are no setup or hold problems that could occur. You should draw a timing diagram for this signal path, adding the minimum and maximum delays of each element in the path, and see what the relationship is between the two inputs of IC3 and IC5.