Clock signal Series Termination
I assume you mean 33 Ω
It's a 'reasonable' value, that gives reasonable results even if some of our assumptions are not quite right.
A typical line impedance for a trace on FR4 that's twice as wide as the substrate is thick, is 50 Ω. Logic boards often end up with line geometries in this ballpark, even if they're not designed to be exactly that. Even if very narrow traces are used, it's very difficult to get more than 100 Ω.
The driver will have its own output impedance, which is often in the 10 to 20 Ω ballpark.
For any given board design and driver part number, we can of course characterise the board and driver, and choose the correct value resistor that matches them.
However, most drivers are going to have an output impedance well below that of the tracks on most board designs, so raising the output impedance bit is guaranteed to improve things.  33 Ω is not a bad compromise until we have done the characterisation.
With a zero Ω output impedance driver and no resistor, and a series terminated line, the 'first transit' voltage at the far end of the line is twice the driver's output voltage. This may cause problems by turning on protection diodes in the receiver. The reflected signal will reflect off the driver, and could cause further switch events.
If we increase the resistor value too far, then the 'first transit' voltage at the far end of the line will be less than the driver's output high. A small reduction eats into the noise margin. A large reduction stops the link working. Reflections will eventually raise the far end voltage to the full voltage, but by then it's too late.