Adiabatic CMOS circuits in low power design
They use Transmission gates and bi-phase triangular clocks to reduce Ic=CdV/dt and stagger the clocks. But uses twice the real-estate of CMOS.

The basic buffer element consists of two
sets of transmission gates. Φ1 and Φ0 are both trapezoidal clocks but Φ1 is a
quarter cycle behind Φ0. 

Initially all the nodes are at 0. As the input gradually
raises to 1 (if it is 1) or stays at 0, Φ0 transitions to 1.

On the next step, Φ1 transitions to 1 which sets the output to 1 if the input was one and otherwise leaves it at 0 which in itself reduces the power dissipation because no charge passes through the transistor. 

On the third step Φ0 transitions back to 0 reseting the input to 0. 

Finally Φ1 transitions back to 0 and the output is restored to 0 by the following gate in order to accommodate for full pipelining and thus the circuit is ready to process a new input.