I2S interface ideas for multiple MEMS microphones
One thing that is really key is you want to be sure you sample them together, but you keep all of their clocks rock steady without interruption.  If you had four i2s channels carefully configured that would work.  

I wonder about an fpga design that would divide down a 4x clock from a micro, collect data from the microphones at that rate and pass it on at 4x.  Or possibly 2x if the microphones each only fill in half (probably the same half) of a stereo-length transfer.  

An FPGA assembling parallel words for a USB FIFO Ic could be another option.  

Or with a moderately fast PC you could just generate i2c clocks and run the USB FIFO as a logic analyzer, getting each channel's serial data on a different pin/bit, and decoding i2s in software.