DAC update rate vs ADC update rate?
Suppose its time to get creative, you can actually read and write on an SPI interface at the exact same time. 

You will need to write not 72, but 96 bits to load all 3 DACs, as the DAC's support daisy chain operation, this also means all 3 devices update at the exact same time

Equally the ADC will need to pull in 22 bits, so assuming there was no overlap, it would be 118 cycles per update / sample or about 424KSPS

So lets get crafty, not sure what your host device can do, but you could actually sample the ADC each time your writing to a DAC with a 100% overlap, assuming you don't actually need to read from the DACs, and can use some other external logic chip to interlock the ADC's SDI when you don't need to write to it,

This gets you to a cycle time of 96 cycles to update the output, and 32 cycles per ADC read. or a sample rate of 1.56MHz, there will be some lost time as you shuffle registers in the devices, but this should get you to your goal while making it a bit harder to configure the devices (something like an AND gate of a suitable frequency for the DAC output, and ADC input) 

Edit: I will also add this is easiest if your SPI buffer is atleast 32 bits in size, and you may be able to DMA this as 2 way transfers are quite common in those peripherals.