Verilog Include Statement Error
You shouldn't need to `include the file at all.

Instead, simply ensure all files are in your project ready to be compiled by your EDA tool. Most (all?) EDA tools will happily compile Verilog without header files.



By the looks of it, you have both files being compiled by the EDA tool.


First it elaborates EightBitAdder.v. You have a `include statement that copies the entire contents of fullAdder.v into it. This means when it compiles the file it now finds a definition of the fullAdder module.
It then elaborates fullAdder.v, only to find another module called fullAdder. This results in two module definitions with the same name.