How to model charge leakage in N-Channel MOSFET?
There is a phoneme in which some portion of clock (square wave) penetrates from the Gate to the Drain, which is called Clock Feed Through. As shown in figure below:







simulate this circuit &ndash; Schematic created using CircuitLab

It can be simplified to the below circuit:







simulate this circuit

This only occurs on clock edges or transitions, since the Gate-Drain coupling is through a capacitive impedance. These coupling capacitive impedances are in fact parasitic overlapping capacitors between Gate and Drain and Gate and Source of the MOS transistors and are due to process imperfections. The amount of injected voltage from the clock ( or as you mention square wave) depends on Clock voltage, load impedance and parasitic capacitors as the following equation describe:
$$V_{er}=V_{clk}WC_{par}/({WC_{par}+C_{load}})$$
for more information take a look at "Analog CMOS Circuits Design" by Behzad Razavi, or this link on his webpage in UCLA:
http://www.seas.ucla.edu/brweb/teaching/AIC_Ch12.pdf