For a PLL Clock multiplier, where does the new clock come from?
For a PLL Clock multiplier, where does the new clock come from?


Usually it comes from a voltage controlled oscillator (VCO) - it runs at the higher speed and then there is a digital divider that reduces this frequency to what would be nominally (say) 50MHz to match your reference crystal frequency. The PLL has a frequency/phase (PFD) detector that outputs a dc level when the two frequencies are not in-lock. This dc level drives the VCO and nudges it to alignment so it is exactly producing a mulitple of 50MHz.