Clock Domain Crossing: Is it possible to design an architecture from faster to slower domain and slower to faster domain simultaneously?
To start with, it depends on the architecture of your design. For example, consider streaming 'data' and 'dataValid' from one domain to another.

If the source circuit clock is slower than the destination circuit clock, the dest' circuit can, and will, see 'dataValid' as asserted for more clocks than the source meant it to be. If the source clock is faster than the dest' clock, the dest' circuit can miss 'dataValid' being high altogether or see it as asserted for fewer clocks than the source meant it to be.

The list of concern areas goes on but the point is that the circuit must be designed with dataflow, travel times and handshaking between the two circuits in mind. It's often essential to plan it in from the start but sometimes can be added later with fewer problems. Then there's all the problems of designing out metastability.

It can all be done, all be done perfectly well, but it needs understanding and planning. It's not a trivial task.