How is ASIC design different from FPGA design? Do you write HDL (Verilog, VHDL) to design and ASIC the same way you would for an FPGA?
1) not all ASICs are digital-only. Some have analog circuits as well or are even analog-only.

So your question only applies to digital-only ASICs or only the digital part of an mixed-signal ASIC.

Yes in theory you would think that you could:

1) Write your VHDL

2) Generate the netlist (this describes the actual circuit)

3) Implement that netlist on either FPGA or an ASIC.

But in the real world it is not that simple.

Step 1 is indeed the same but the netlist for an FPGA will be different.

On an FPGA you will only have the gates available which are implemented on that FPGA.

On an ASIC you can choose any gate and as many as you like from the library describing the ASIC's manufacturing process.

This difference means different optimizations might need to be made to either design. For high-speed design it is essential to simulate the netlist so that actual delays are included. This will reveal timing issues that have to be fixed.

So yes, the starting piont (VHDL, Verilog) could be the same but that does not mean you can "blindly" put it on an ASIC or FPGA and expect good results.

What is done in the real world is that first the VHDL or Verilog is evaluated on an FPGA for proper functionality. Then that debugged code is used to make an ASIC. Even then many simulations have to be done to ensure proper functionality.