Why to use signal in this VHDL code?
I think clock domain synchronization if contr is asynchronous to the FPGA clock. Standard practice to reduce metastability of asynchronous signals is to feed it through a chain of flip flops prior to usage by anything synchronous.

But the entire code chunk is not clocked to begin with so I do not see why you would actually need that here since it just adds latency. But this is something you need to be aware of which goes unmentioned when starting out on FPGAs so I will throw it in.