VHDL error: multiple constant drivers for net
Use rising_edge only for signals, that are supposed to be clocks.
You can't assign signal, or output in two different processes.
You didn't specify exactly what are you trying to achieve, but I think that you don't have to (and shouldn't) use buffer for OUTPUT.


This code should work as you expect (if I understand you correctly):

library ieee;
use ieee.std_logic_1164.all;

entity trigger_slave is
    generic (
        OUT_ON_PERIOD   : integer := 10 - 1                                 
    );
    port (
        clk_1MHz        : in std_logic;
        resetn          : in std_logic;

        enable          : in std_logic;
        output          : out std_logic
    );
end trigger_slave;

architecture behavior of trigger_slave is

type state_t is (IDLE, COUNTING);
signal machine: state_t;

begin   

    process (clk_1MHz)  
        variable counter        : integer range 0 to OUT_ON_PERIOD := 0;
    begin
        if resetn = '0' then
            machine &lt;= IDLE;
        elsif rising_edge(clk_1MHz) then

            case machine is

            when IDLE =&gt;

                machine &lt;= IDLE;

                if enable = '1' then
                    counter := 0;
                    machine &lt;= COUNTING;
                end if;

            when COUNTING =&gt;

                machine &lt;= COUNTING;

                if (counter = OUT_ON_PERIOD) then
                    machine &lt;= IDLE;
                else 
                    counter := counter + 1;
                end if; 

            when others =&gt;

                machine &lt;= IDLE;

            end case;

        end if;
    end process;

output &lt;= '1' when machine = COUNTING else '0';

end behavior;