How PCI Express Hardware Interface communicate with device core?
There are many layers of abstraction for PCIe interrupts. Perhaps you'd like to read about it at a low hardware level such as this xilinx core. Perhaps you'd be more interested in how an OS handles it.

Transmission latency and flow control are going to be application specific. I'd like to point out that electrically PCIe is full duplex and so flow control is entirely up to the application.

I would recommend exploring the contents of a Linux device driver.

Perhaps you can be more specific with your question. People spend their entire lives specializing in the creation of PCIe handlers.