SR latch timing diagram or waveform with delay, help!
As Trevor shared the image in the comment, S-R latch contains NOR gates. In the first timing diagram, when S becomes 1, after 10ns QN becomes 0, and 10ns later Q becomes 1. Now, draw the S-R latch with NOR gates, write initial values near corresponding letters (S=0, R=0, Q=0, QN=1), change S to 1, and try to understand what changes you see. If you struggle, look at the timing diagram you shared.