8085 MPU; Stepping through an instruction (Timing diagrams)
it's late here and I may only help a little. But &quot;ADD B&quot; is a T4 type instruction, as you probably know. It also has been many years since I did anything with the 8085A and I apologize for any mistakes in advance. But here goes regarding the four T states of the &quot;ADD B.&quot; (I'm just looking at the datasheet right now to refresh some of my memory.) Note that each T state shown below will have either an 0 or 1 to indicate falling-edge or rising-edge of the clock. (A T state begins with the falling edge.):

T1-0: \$ALE=1\$; \$S_0=1\$; \$S_1=1\$; \$IO/\overline{M}=0\$; \$\overline{RD}=1\$; \$\overline{WR}=1\$; Latch \$PC\$ to \$MAR\$ (which appears on \$A_{15}..A_0\$); Actively drive \$MAR\$.
T1-1: \$ALE=0\$
T2-0: Start PC increment; \$\overline{RD}=0\$; Float \$MARL\$ (\$AD_7..AD_0\$) to allow external circuitry access
T2-1: Continue PC increment (external circuitry may start to provide data on \$AD_7..AD_0\$)
T3-0: Instruction byte stabilizing on \$AD_7..AD_0\$
T3-1: Latch \$MDR\$ from \$AD_7..AD_0\$ and enable \$MDR\$ output on internal bus
T4-0: Address Bus Idle; Latch \$IR\$ from \$MDR\$ and start decoding of \$IR\$
T4-1: Address Bus Idle; Decide if two more states are required for the instruction.

That's the official details and just describes the bus cycle from an external view.
Internally, things are different. The ADD B instruction would need to set up the ALU opcode value and would require addressing the register file to read the B register onto the internal bus and then into the ALU's temp register (it's other register is the accumulator.) That temp register value would then be present at one of the ALU inputs and at some point the ALU output now present on the temporary bus would be stable long enough to start the write-back process into the accumulator latch. All this before the next instruction's byte would need to use the internal bus in order to transfer the MDR latch value into the IR latch.
But the essence of T2 and T3 is to allow the external memory system to respond to the request for an instruction byte and to get that byte value into the 8085A. T4 is for decode and determination if the instruction requires more states (or not.) Though, keep in mind that T1 and perhaps T2 of the following instruction cycle might also be used to complete the prior instruction after decoding (if it doesn't require any added bus operations, such as read/write.)