Microchip PIC18F CAN message reception problem
It's been a while since I last delved into my low level PIC 18 CAN code.  I remember there were a few non-obvious things required to get it working.  I don't remember the details at this point, so here is the source code for my PIC 18 CAN driver that I've used in several different projects:

[Argh!  The system won't let me post the whole source file here, saying that it exceeds some character limit.  So here is the first part of the file, which does the initializing.  I'll write another answer or answers to include the receiving and transmitting parts.]


;   ***************************************************************
;   * Copyright (C) 2009, Embed Inc (http://www.embedinc.com)     *
;   *                                                             *
;   * Permission to copy this file is granted as long as this     *
;   * copyright notice is included in its entirety at the         *
;   * beginning of the file, whether the file is copied in whole  *
;   * or in part and regardless of whether other information is   *
;   * added to the copy.                                          *
;   *                                                             *
;   * The contents of this file may be used in any way,           *
;   * commercial or otherwise.  This file is provided "as is",    *
;   * and Embed Inc makes no claims of suitability for a          *
;   * particular purpose nor assumes any liability resulting from *
;   * its use.                                                    *
;   ***************************************************************
;
;   CAN bus interface routines.  The exported routines are briefly listed here.
;   See the header comments of each routine for details.
;
;     CAN_INIT  -  One-time module initialization.  Must be first call after
;       reset.
;
;     CAN_START  -  Sets up the CAN hardware ready for use, and also starts the
;       CAN receiving thread.
;
;     CAN_SEND_INIT  -  Initialize the pending transmit frame state.  Must be
;       first call for sending any new CAN frame.  REG0 contains flags that
;       indicate standard versus extended and data versus remote request frame.
;
;     CAN_SEND_ID  -  Sets the frame ID in the pending transmit frame state.
;
;     CAN_SEND_DAT  -  Adds a data byte to the pending transmit frame state.
;
;     CAN_SEND  -  Sends the frame described by the current transmit frame
;       state.
;
;   The following global flags must be defined before this file:
;
;     FLAG_CANIN  -  Automatically set by the CAN receiving task in this module
;       whenever a new CAN frame is received.  The CAN frame data will be in the
;       global CANIN_xxx variables.  This state is only valid when FLAG_CANIN is
;       set.  New received CAN frames will be held and will not overwrite the
;       CANIN_xxx state until FLAG_CANIN is cleared.  This flag must be cleared
;       by application code outside this file when done with the CANIN_xxx state
;       for the current frame to allow new CAN frames to be received.
;
;     FLAG_CANIN_EXT  -  Indicates the current received CAN frame is in extended
;       format (29 bit ID) as apposed to standard format (11 bit ID).  This flag
;       is read-only outside this file, and is only valid while FLAG_CANIN is
;       set.
;
;     FLAG_CANIN_RTR  -  Indicates the current received CAN frame is a remote
;       request as apposed to a data frame.  This flag is read-only outside this
;       file, and is only valid while FLAG_CANIN is set.
;
;     FLAG_CANSEND  -  Part of the mutex mechanism to guarantee a single task at
;       a time is building and sending a CAN frame.  Managed in this module, but
;       may be examined by external code to see if the CAN sending mechanism is
;       currently acquired by another task and therefore whether CAN_SEND_INIT
;       will stall for a while if called immediately.
;
;   The following values can be defined before this file is included:
;
;     BITRATE  -  Preprocessor constant, type REAL.  The desired CAN bit rate in
;       bits per second.  Default = 500 Kbits/second.
;
;     CANIN_CALLBACK  -  Preprocessor constant, type STRING.  Name of routine to
;       call from internal CAN thread when a CAN frame is received.  No routine
;       is called when this constant is blank.  Default = blank (no received CAN
;       frame callback routine).
;
;     CALLBACK_EXTERN  -  Preprocessor constant, type BOOL.  Indicates that the
;       callback routine named in CANIN_CALLBACK is external to this module.
;       The default is TRUE (is external).  This constant must be created and
;       set to FALSE if the callback routine is local to prevent the code in
;       this file from generating a EXTERN reference to it, which will produce
;       a assembler error.
;
;     DEBUG_CANCFG  -  Preprocessor constant, type BOOL.  TRUE causes detailed
;       information to be shown about the automatic CAN bit timing
;       configuration calculations.  The default is FALSE, which just shows the
;       final result.
;
;     LBANK  -  MPASM constant.  0-15 bank number for local state of this
;       module.  No default, required.
;
;   This version drives the ECAN module built into the 18F4580.
;
         extern  currtask    ;ID of the currently running task
         extern_flags        ;declare global flag bits EXTERN

;*******************************************************************************
;
;   Configuration constants.
;
/if [not [exist "bitrate"]] then
  /const bitrate real = 500e3 ;CAN buts bit rate, Hz
  /endif
/if [not [exist "canin_callback"]]
  /then
    /const canin_callback = "" ;name of routine to call when CAN frame received
  /else
    /if [not [exist "callback_extern"]] then
      /const callback_extern bool = true ;default to callback routine is external
      /endif
  /endif
/if [not [exist "debug_cancfg"]] then
  /const debug_cancfg bool = false ;default to not show config select details
  /endif

stacksz  equ     32 + ntsksave ;CAN receiving task data stack size
ecanconr0 equ    b'10010000' ;base ECANCON value to map receive buffer 0
                 ; 10------  select enhanced FIFO mode (mode 2)
                 ; --0-----  FIFO interrupt when 4 buffers left (not used)
                 ; ---10000  base value to map receive buffer 0
;
;   Derived constants.
;
/const   fcanclk real = freq_osc ;clock to CAN module, bit rate generator input
lbankadr equ     bankadr(lbank) ;address within local state register bank

;*******************************************************************************
;
;   Global state.  All this state is assumed to be in the GBANK register
;   bank by other modules.
;
         defram  gbankadr

canwtask res     1           ;ID of the task that has the transmit buffer locked
         ;
         ;   Received CAN frame buffer.
         ;
canin_id res     4           ;frame ID
canin_ndat res   1           ;number of data bytes, always 0-8
canin_dat res    0           ;start of data bytes
canin_d0 res     1           ;symbols of individual data bytes for debugging
canin_d1 res     1
canin_d2 res     1
canin_d3 res     1
canin_d4 res     1
canin_d5 res     1
canin_d6 res     1
canin_d7 res     1

         global  canin_id, canin_ndat, canin_dat

;*******************************************************************************
;
;   Local state.
;
         defram  lbankadr
;
;   Info about the current transmit message.
;
wr_flags res     1           ; RTR,  EXT
wr_id    res     4           ;identifier, either 11 or 29 bits
wr_ndat  res     1           ;0-8 number of data bytes
wr_dat   res     0           ;start address of transmit data bytes buffer
wr_dat0  res     1           ;data bytes have individual labels for watch window
wr_dat1  res     1
wr_dat2  res     1
wr_dat3  res     1
wr_dat4  res     1
wr_dat5  res     1
wr_dat6  res     1
wr_dat7  res     1
;
;   CAN receiving task data stack.  Since this is only accessed indirectly via
;   pointer registers, the bank does not need to be known at assembly time.  It
;   is therefore put in a separate section to allow the linker to place it
;   separately from other variables.
;
.can_stack udata
stack_can res    stacksz     ;CAN receiving task data stack


.can     code

;*******************************************************************************
;
;   Subroutine CAN_INIT
;
;   Initialize the hardware and software state managed by this module.
;
         glbsub  can_init, noregs

         setreg  b'00110000', cancon ;disable the CAN module
                 ; 001-----  disable mode
                 ; ---1----  abort all pending transmissions
                 ; ----XXXX  not relevant when module disabled

         setreg  b'00100000', ciocon
                 ; XX------  unused
                 ; --1-----  CANTX pin will always be driven, recessive or not
                 ; ---0----  disable CAN capture into CCP1
                 ; ----XXXX  unused

         leaverest

;*******************************************************************************
;
;   Subroutine CAN_START
;
;   Set up the CAN hardware for operation and start up the CAN reading thread.
;   The rest of the system must not attempt CAN operations before this routine
;   is called.
;
         glbsub  can_start, regf0 | regf1 | regf2 | regf3 | regf4

         dbankif gbankadr
         bcf     flag_canin  ;init software received CAN frame buffer to empty
;
;   Set the CAN module into configuration mode.  Mode changes are requested via
;   the CANCON register, but do not necessarily take effect immediately.  The
;   actual mode is indicated in the CANSTAT register.
;
         setreg  b'10010000', cancon ;request configuration mode
                 ; 100-----  request configuration mode
                 ; ---1----  abort any pending transmissions
                 ; ----XXXX  read-only bits in mode 2
wait_cfgmode unbank          ;back here until entered configuration mode
         dbankif canstat
         movf    canstat, w
         andlw   b'11100000' ;mask in only the current mode bits
         xorlw   b'10000000' ;compare to config mode
         bz      have_cfgmode ;in config mode ?
         gcall   task_yield_save ;give other tasks a chance to run
         jump    wait_cfgmode ;back to check current mode again
have_cfgmode unbank          ;CAN module is in configuration mode

         setreg  ecanconr0, ecancon ;set enhanced FIFO mode (mode 2)
;
;   Configure the bit timing.  The bit rate is defined by the constant BITRATE,
;   and is derived from the clock into the CAN module, which is the instruction
;   clock in this case.  The frequency of this oscillator is defined by the
;   constant FCANCLK.
;
;   CAN bits are divided into time segments, each defined in terms of the number
;   of time quanta.  The length of time quanta is determined by the oscillator
;   frequency and the baud rate divider setup.  The MCP2515 requires a minimum
;   of 5 time quanta per bit, but we require 9 for reliability.  The maximum
;   allowed is 25 time quanta per bit.  The time quanta budget for a bit is
;   allocated between the various bit segments as follows:
;
;     Sync  -  Always 1.
;
;     Propagation  -  1-8, we require at least 2.
;
;     Phase1  -  1-8, we require at least 3.
;
;     Phase2  -  2-8, we require at least 3.
;
;   See the manual for details on the meaning of these segments.
;
/var new tqbit integer       ;time quanta per whole bit, 9-25
/var new tqprop integer      ;time quanta per propagation segment, 2-8
/var new tqph1 integer       ;time quanta per phase 1 segment, 3-8
/var new tqph2 integer       ;time quanta per phase 2 segment, 3-8
/var new bdiv integer        ;Fosc/2 divider to make time quanta rate, 1-64
/var new ferr real           ;CAN bit frequency error fraction

/var new ii integer          ;scratch integers
/var new jj integer
/var new r real              ;scratch floating point
/var new r2 real
/var new r3 real
/var new s1 string           ;scratch strings
/var new s2 string
/var new s3 string
//
//   Determine the bit rate setup.  The TQ frequency is (FCANCLK/2)/BDIV, with
//   BDIV constrained to 1-64.  The BDIV value resulting in the smallest
//   frequency error will be chosen, within the constraint that there must be
//   9 to 25 time quanta per bit.
//
/set bdiv 0                  ;init to no usable BDIV value found
/set ii 1                    ;init trial BDIV value
/set ferr 1.0                ;init to large frequency error so far
/block                       ;back here to try each new possible BDIV value
  /set r [/ fcanclk [* 2 ii]] ;TQ frequency for the divisor value in II
  /set jj [rnd [/ r bitrate]] ;best whole time quanta per bit for this divisor
  /set jj [if [= jj 9] jj 9] ;clip to min usable value
  /set r2 [/ r jj]           ;resulting actual bit frequency
  /set r3 [/ [abs [- bitrate r2]] bitrate] ;make error fraction
  /if [ ferr 0.015] then      ;bit rate error too large to work ?
  /show "  ERROR: Bit rate of " [eng bitrate] "Hz not possible with CAN clock of " [eng fcanclk] "Hz."
         error   CAN bit rate
         end
  /stop
  /endif
/if [> ferr 0.0085] then     ;error more than half allotted total of 1.7%
  /show "  WARNING: High CAN bit rate error from desired."
  /endif

/set r [/ fcanclk [* 2 bdiv tqbit]] ;actual bit frequency, Hz
/set s3 [fp [* ferr 100] "sig 1 mxl 6 rit 2"] ;bit frequence error in percent
/show "  CAN clock " [eng fcanclk] "Hz, bit freq " [eng r] "Hz (" s3 "% err), " tqbit " TQ/bit"
//
//   The bit rate setup has been determined.  There are TQBIT time quanta per
//   bit, which is guaranteed to be in the range of 9 to 25.
//
//   Now divvy up the time quanta to the various segements of the bit time.
//
/set tqprop 2                ;set the configurable segments to their minimum durations
/set tqph1 3
/set tqph2 3
/set ii [- tqbit [+ 1 tqprop tqph1 tqph2]] ;left over availabe TQs.

/block                       ;back here until all TQs are assigned
  /if [
                 ; ---X----  unused
                 ; ----1---  accept standard or extended according to filters
                 ; -----X--  unused
                 ; ------00  acceptance mask 0 bits 

         setreg  b'00000000', rxm0sidh
                 ; 00000000  acceptance mask 0 bits 

         setreg  b'00000000', rxm0eidl
                 ; 00000000  acceptance mask 0 bits 

         setreg  b'00000000', rxm0eidh
                 ; 00000000  acceptance mask 0 bits 

         setreg  b'00001000', rxm1sidl
                 ; 000-----  acceptance mask 1 bits 
                 ; ---X----  unused
                 ; ----1---  accept standard or extended according to filters
                 ; -----X--  unused
                 ; ------00  acceptance mask 1 bits 

         setreg  b'00000000', rxm1sidh
                 ; 00000000  acceptance mask 1 bits 

         setreg  b'00000000', rxm1eidl
                 ; 00000000  acceptance mask 1 bits 

         setreg  b'00000000', rxm1eidh
                 ; 00000000  acceptance mask 1 bits 

         setreg  b'00000001', rxfcon0
                 ; 0-------  disable filter 7
                 ; -0------  disable filter 6
                 ; --0-----  disable filter 5
                 ; ---0----  disable filter 4
                 ; ----0---  disable filter 3
                 ; -----0--  disable filter 2
                 ; ------0-  disable filter 1
                 ; -------1  enable filter 0

         setreg  b'00000001', rxfcon1
                 ; 0-------  disable filter 15
                 ; -0------  disable filter 14
                 ; --0-----  disable filter 13
                 ; ---0----  disable filter 12
                 ; ----0---  disable filter 11
                 ; -----0--  disable filter 10
                 ; ------0-  disable filter 9
                 ; -------1  enable filter 8

         setreg  b'00000000', sdflc
                 ; XXX-----  unused
                 ; ---00000  number of data bits to compare to filter for standard message

         setreg  b'00000000', msel0
                 ; 00------  filter 3 associated with mask 0
                 ; --00----  filter 2 associated with mask 0
                 ; ----00--  filter 1 associated with mask 0
                 ; ------00  filter 0 associated with mask 0

         setreg  b'00000000', msel1
                 ; 00------  filter 7 associated with mask 0
                 ; --00----  filter 6 associated with mask 0
                 ; ----00--  filter 5 associated with mask 0
                 ; ------00  filter 4 associated with mask 0

         setreg  b'01010101', msel2
                 ; 01------  filter 11 associated with mask 1
                 ; --01----  filter 10 associated with mask 1
                 ; ----01--  filter 9 associated with mask 1
                 ; ------01  filter 8 associated with mask 1

         setreg  b'01010101', msel3
                 ; 01------  filter 15 associated with mask 1
                 ; --01----  filter 14 associated with mask 1
                 ; ----01--  filter 13 associated with mask 1
                 ; ------01  filter 12 associated with mask 1

         setreg  b'00000000', rxf0sidl
                 ; 000-----  standard ID bits 
                 ; ---X----  unused
                 ; ----0---  accept only standard IDs
                 ; -----X--  unused
                 ; ------00  extended ID bits 

         setreg  b'00000000', rxf0sidh
                 ; 00000000  standard ID bits 

         setreg  b'00000000', rxf0eidl
                 ; 00000000  extended ID bits 

         setreg  b'00000000', rxf0eidh
                 ; 00000000  extended ID bits 

         setreg  b'00001000', rxf8sidl
                 ; 000-----  standard ID bits 
                 ; ---X----  unused
                 ; ----1---  accept only extended IDs
                 ; -----X--  unused
                 ; ------00  extended ID bits 

         setreg  b'00000000', rxf8sidh
                 ; 00000000  standard ID bits 

         setreg  b'00000000', rxf8eidl
                 ; 00000000  extended ID bits 

         setreg  b'00000000', rxf8eidh
                 ; 00000000  extended ID bits 
;
;   Done configuring the CAN module.  Switch it from configuration mode to
;   normal operating mode.
;
         setreg  b'00000000', cancon ;set up CAN module for normal operation
                 ; 000-----  request normal operating mode
                 ; ---0----  don't abort pending transmissions
                 ; ----XXXX  read-only status bits
;
;   Start CAN receiving task.
;
         task_create can_task, stack_can

         leaverest


Perhaps you can see something you are doing differently.  This code assumes the existance of my standard macro library and that it will be run thru my PIC assembler preprocessor before being passed to MPASM.  You can probably infer most of what it's doing, but the preprocessor documentation is available at http://www.embedinc.com/pic/prepic.txt.htm.