Why is the PMOS in NAND gate in Parallel and NMOS Series?
Static CMOS designs rely on complementary behavior of NMOS and PMOS devices.
So take a look at what will turn the top part &quot;on&quot; - A is 0 or B is 0. What does this do? It makes the output high.
Since the bottom part is in series, for a path to exist to ground, A and B must be 1 (NMOS - so &quot;active high&quot;). What does this do? It makes the output 0.
Put those combinations together:
A B | NAND(A,B)
--------------
0 0 |   1
0 1 |   1
1 0 |   1
1 1 |   0

Do you see how the portion where the output is 1 looks like it is covered by A OR B, and the combination where it is 0 is covered by the bottom half?
TA-DA! That's old-school static CMOS design!