Block diagram of 16:1 MUX using four 4:1 MUX only
You could've easily found it on the internet if you searched. 

The basis: See it this way: You need a combinational logic with 16 input pins, 4 select lines and one output. In a 4:1 mux, you have 4 input pins, two select lines and one output. 

So, at the least you have to use 4 4:1 MUX, to obtain 16 input lines. But you'd then have a logic with 4 output pins. We can use another 4:1 MUX, to multiplex only one of those 4 outputs at a time. Hence, this would be your final design. There might be other designs methods too, but this is the most common. 



Image courtesy: www.slideplayer.com 

EDIT:
Yes, we can implement it without using the last 4:1 MUX; but you have to use an OR gate there and also include enable pins for each 4:1 MUX. It utilizes the traditional method; drawing a truth table and then analytically deciding the design. Here is an example of an 8:1 MUX from 2:1 MUX without using a 2:1 MUX at the output. 



Image courtesy: https://www.youtube.com/watch?v=neXhD9qyQmo

But, to obtain the same for a 16:1 MUX you'll need to make a lot of modifications. Like if you draw the truth table and analyze (compare it with the above 8:1 MUX design), you'll require two enable pins for each MUX, each with different options. For example, the first MUX needs to be enabled only when the two enable pins(say, e1, e0) are low, the second MUS should be enabled only when e1= 0 and e0=1 and so on. 

As the size of the MUX increases, it'll become too complex to design using this model. Hence, the first approach is utilized; the one with a MUX at the end. There may be other designs, but this is my approach.