Absolute difference with logical operators only
As mentioned in the comments, you write HDL code and let the tool sort out the logic.

This is just one of many ways to do this: 

assign bigger_then_one = a &gt; b ? ( (a-b) &gt; 1) : ( (b-a) &gt; 1 );


The example is in Verilog, I am sure there is a one liner for VHDL as well but that varies depending on the type you want to produce, e.g. std_logic or boolean or ....



Just to show what happens I made a top level module and ran it through Vivado:

module ee (
   input    [2:0] a,
   input    [2:0] b,
   output   bigger_then_one
   );

   assign bigger_then_one = a &gt; b ? ( (a-b) &gt; 1) : ( (b-a) &gt; 1 );

endmodule


Result:


A single LUT comes out.