Compromising on placement or routing of decoupling cap with BGA package
For any type of decoupling application, closer is better.

"... the power tracks route pass through this capacitor first and then connect with the digital IC power pins or balls."

That's better than having the power tracks go to the BGA first, then to the cap.  Note that in many applications, the small ceramic decoupling caps are mounted on the back side of the board, directly under the BGA just outside of the ball field.

Like Peter Smith said, a lot depends on the speed/edge rates of what the device is doing.  To really do this right, you would need to build a model of the PDN (Power Distribution Network) and simulate that with your application.

Finally, we could give a more definitive answer if you wold provide some more details of you application, such as:


Clock rate of the device
Device type, part number, etc
Size of the package, how many balls
Number of IO that switch, and at what rate