Why does VHDL not allow to alias slice of an array in this way?
The element type is the same but not the types themselves.

IEEE Std 1076-2008 6.6.2 Object aliases:


  The following rules apply to object aliases:  
  
  
    .. 
    
    c) The name shall be a static name (see 8.1) that denotes an object. The base type of the name specified in an alias declaration shall be the same as the base type of the type mark in the subtype indication (if the subtype indication is present)....
  


and 6.6 Alias declarations, 6.6.1 General 


  An alias declaration declares an alternate name for an existing named entity.


How can a named entity have two different types? The alias has a subtype indication type mark that's different from the thing being aliased.

So how should an alias of array slice be created in this case?

Declare type array_1_t as an unbounded array type so you can constrain it in the aliases:

library ieee;
use ieee.std_logic_1164.all;

package alias_slice_pkg is
    type array_1_t is array (natural range &lt;&gt;) of std_logic_vector(31 downto 0);
    signal my_array_1: array_1_t(0 to 73);
    alias  my_array_1_1: array_1_t (0 to 22) is my_array_1(0 to 22);
    alias  my_array_1_2: array_1_t (0 to 22) is my_array_1(23 to 45);
    alias  my_array_1_3: array_1_t (0 to 27) is my_array_1(46 to 73);
end package;


A package declaration is used here for illustration purposes providing a minimal, complete, and verifiable example.