clock in testbench VHDL
First, note that all processes run concurrently with one another. So to have a clock driving your other processes, you want its code in its own process. The code inside the process runs sequentially, and this is how you are able to generate a clock signal with a specific period (using 'wait' statements). A process with a sensitivity list will run whenever one of these signals changes. However, a process with no sensitivity list will always be running. It is up to you to decide when it runs. This is where 'wait' statements come in handy. As a side note, you can't use 'wait' statements in a process with a sensitivity list. 

You can implement a simple flip-flop by using either of the two codes below.  

process (clk) is
begin
    if clk = '1' then
        Q&lt;=D;
    end if;
end process;


process is
begin
    wait until clk = '1' and clk'event;
    Q&lt;=D;
end process;


Notice how in one design, the process only initiates when there is an event on clk, where it then checks the level. The second process runs continuously, but it waits for an event and level high.

Now, these processes are dependent on the clock. To simulate a clock, we only want the clock to be dependent on time. After half the period we want to toggle the level. So you have a process with no sensitivity list, and the wait statements wait for a certain amount of time before changing the level of the clock.

Hope that helps!

Note:
The syntax might be slightly off on those examples, it's been a while since I generated any code..