CycloneIV PCIe hard IP fixedclk_serdes generation
It is hard to say how exactly the offset cancellation circuitry is implemented in the FPGA, therefore the following is my assumptions only.

A usable method, combing auto-zeroing (AZ) and choppering (CH), is described here, p. 39, figs. 2.19 and 2.20. (Yes, it is about op amps in common, but it is very simple to first-time understand, techniques for high-speed serdes may be found as listed here.) As you can see, AZ and CH work on separate, non-equal frequencies (Faz &lt;> Fch).

A PLL outputs a (clock) signal similar but not exact to the reference applied. They may be considered equal in frequency only over a long time averaging (integration), but not in an instant frequency over a self (or comparable) period given, i.e. with a short-term observation they differ. Also, the output of PLL may have a phase shift related to the reference, what make again the signals different in a short-term observation. (For AZ+CH, i think 90-deg phase shift is preferable, if two physically independent clocks/sources are unreachable.) 

Therefore, i thing there is no error in the documentation. It is the preferred scenario to clock the offset cancellation, but not the only possible one. (In the doc, it is stated by "cannot" but no "shall/must not".)