How do I put a high-speed pulse through a digital logic chip?
Page 1 of the Coolrunner II datasheet says that the pin to pin propagation delay is 5.7ns.  So any signal you put in is likely to have at least that much delay before coming out.

Also in figure 4 in the datasheet on page 10 we see the IO pin output current for VCC=3.3V.  Looking at the curve we see that the IO pin output driver resistance varies non-linearly with the load.  The resistance into a short looks like 3.3V/60mA = 55ohms, and further up the curve at Vout=2.0V it is (3.3V-2.0V)/35mA = 22 ohms.

Lets assume the pin capacitance is 10pF on your CPLD, plus another 10pF of trace capacitance, plus another 10pF at your destination.  The CPLD pin must drive into 30pF of capacitance.  

We can estimate the rise time of the signal using the output resistance of the driver and the load capacitance.  Based on the driver resistances we calculated above we see that the time constant lies somewhere between 22 ohms x 30pF = 660ps to 1.6ns.  Since both 1.6ns and 660ps are a significant fraction of your pulse width, your signal is likely to experience significant rounding.  Also, the peak amplitude is likely going to be less than VCC.