DDR4 DIMM/component, different CL?
The memory controller configures the chip by telling it at startup which CL value is to be used before using it.
It just takes certain amount of time for the data to be ready after sending the read command. Thus different bus speeds need different CL values, to make sure that enough time has passed before data is sent on the bus. So by lowering the clock speed, at some point the CL can also be lowered.
The clock speeds are multiples of 33.33 MHz, a lot of the timing is based on some base clock value that can be multiplied to get higher frequencies. Note that 33.33 MHz is not some mysterious magic value, but one third of 100 MHz, and many motherboards use a 25 MHz crystal clock oscillator to get multiples of 100 MHz to begin with.
A DIMM module is a bit special, as it contains a separate memory chip that contains information about the module timing, and this memory chip can be read by the motherboard to know which speeds and timings are supported by the module, and then configure the clock and memory controller accordingly.
So if you are connecting a DRAM chip directly to an FPGA, there is no way for it to auto-detect the timing, and you must tell the memory controller all the parameters that are relevant for using the memory, including the clock speed and CL timings, and tons of more timings so that the memory chip is used properly within its specifications.