Pass a signal in low-level entities and update it back in top-level entity in VHDL
You can't use the same signal as in- and output.

Don't forget that you're not programming a sequential programming language. In

 entity work.inc(behav) port map(clk, pc, pc);


The first and second pc are actually the same wires! (In fact, I'd expect your synthesizer to even complain about pc being driven by multiple drivers.) 

This might indicate you're not already very familiar with the nonsequential logic of HDLs. Going back and doing a more basic VHDL tutorial might really pay off for you, and save you a lot of time overall.