Boolean function minimization for more than 100 variables
I'm lazy.

I often let compilers and the such do my work. 

Thus, I'd recommend you find a language in which you can formulate logic values, and then optimize them.

This is the core problem of Hardware Description Language (HDL) synthesizers, as used for FPGA and digital IC design.

Hence, HDL synthesizers are exactly the type of program you're referring to.

Thus, I'd simply take my table, and convert it to a set of conditions in verilog (a popular HDL).

Then, I'd use the excellent Yosys to parse, optimize and emit in one of many formats (including graphical representation or a gate level net list) my logic.

That's pretty easy, actually: 

module thing_to_be_simplified (input [399:0] in, output [12:0] out)
    if(in[2:0]==0b'110) then
       out = value;
    else if( ... ) 
       ...
endmodule


Convert your table to such a cascade of else ifs with a simple python script.

Then I'd run yosys, do the read_verilog command on my verilog source code, run a check, run an opt (optimization), and then show (to see a graph of gates) or write_verilog (or write_&lt;otherformat&gt;).