Attiny4 - Possible Errata Found With PWM
I believe, it is a feature not a bug. Citing from the datasheet (page 94):


  The extreme values for the OCR0x registers represents special cases
  when generating a PWM waveform output in the Fast PWM mode. If the
  OCR0x is set equal to BOTTOM (0x0000) the output will be a narrow
  spike for each TOP+1 timer clock cycle. Setting the OCR0x equal to TOP
  will result in a constant high or low output (depending on the
  polarity of the output which is controlled by COM0x[1:0]).


This describes your observation pretty well. With 5 bit PWM (32 steps, right?) the duty cycle should be 97 % (not 95 %), but it is probably good enough for approximately.