VHDL assignment and condition at the same clock edge on parallel processes
Flag state will be sampled on the next clock edge. In the synchronous design, all the conditions are (or must be) "prepared" before clock edge occurs, and when it occurs, circuit transitions to new state within very short timeframe. Thus in situations like yours circuit will see previously "prepared" condition, thus previous state of the flag. On the next clock edge new flag value will be "prepared", and it will be sampled.

You spend whole cycle to get the new propagated flag value; you may consider to trigger one process on rising edge, and another process on the falling edge, this way you will spend only half of the cycle.

Update (as per comments below): when designing circuits driven by both edges of the clock, you must pay close attention to the duty cycle of the clock, not just its period.