What timing constrains would I need to set for a handshake based clock transfer
If the two clock domains are truly asynchronous to each other, then your constraints need to treat them as a false path (set_false_path) to exclude them from static timing analysis. Your handshake logic needs to be designed with appropriate synchronizers, and be designed to deal with the handshake latency (add skid buffers if necessary.)
Regardless, any time you have a clock boundary cross you need to deal with handshake latency and skew. If you're using AXI (and you should), consider using AXI register slices to isolate the clock regions. This will help your system close timing using robust, proven logic.
tl; dr: use AXI register slices for sync clocks, or AXI FIFOs for async clocks. Don't reinvent the wheel if you don't have to.