Why does I2S have extra clock cycle in SCLK that is wasted i.e no data transferred?
Standard I2S does indeed have a one bit offset, I am guessing because in the early days it provided timing to latch the output of the shift register into some sort of parallel input converter (Or maybe the timing for a S/H to get stereo out of a single channel of expensive converter chip or something, yes that was actually done!).. 

A lot of this stuff tends to be a case of formalising what is already being done, and 30 odd years later nobody remembers the original reasoning.