How to plan diagram states of this machine?
First consider the case where your machine is simply comparing x and y. Initially your state will be that x and y are equal. As you receive data LSB first, any bit received will be more significant than bits received so far. So you have three states { x=y, x>y and y>x } which are transitioned between as data is received.

You know that the difference between this machine and the machine you want is that one of the inputs is shifted by one bit. So can you convert this machine so one if the inputs is delayed by one clock cycle using two more states?