FPGA - Synchronous inputs with higher frequency than the board clock
A quick look at the datasheet for your part page 3-16 shows a maximum input clock of 133Mhz.  There are two analog PLLs and the max frequency they can be run at is 275Mhz with the global clock buffer being the same 275Mhz max.  CMOS inputs max out at 250Mhz, and LVDS at 400Mhz.

Now this does not mean your design will run at 275Mhz.  Depending on the complexity you may only be able to close timing much lower than that or not at all. But that's part of the design effort that's up to you to figure out.

Now for say 720p 30Hz I think that's around a 37.125Mhz pixel clock.  So data will come in over LVDS at about 297Mhz over LVDS for three lanes (back of the envelope could be off slightly here).  Your HDMI clock would be half that at 148.5Mhz.  So you might be able to count pixels with it.  As you try to hit higher resolutions or frame rates that clock speed will go up.