How to implement Clock Gating Style RTL into synthesis?
You are trying to sample the clock signal on the rising edge of itself. This violates Nyquist criterion since you are sampling the clock signal at its frequency and not twice its frequency.
As the name implies, clock gating should use a gate, an AND gate.
You need to have the gating signal toggle on the inactive edge of the clock to avoid glitches. You can either use a latch or flip-flop to ensure the clock gating signal only transitions on the inactive edge of the clock.
For latch:
always_latch 
  if (~clk)
    enable_latch &lt;= enable_in;

assign g_clk = clk &amp; enable_latch;

For flip-flop:
always_ff @(negedge clk)
  enable_flop &lt;= enable_in;

assign g_clk = clk &amp; enable_flop;


Also a point to be mentioned: if you are using clock gating in your design, you should avoid driving signals with blocking assignments on clock edges in the testbench as this could lead to race conditions.
Further reading: How to use clock gating in RTL?