Clock divider circuit with flip D flip flop
At a glance to get your circuit, the wiring seems wrong, in halfclk you had:

dff dff1(clk, reset, d, q, qb);
dff dff2(w1, reset, d1, w2, qb1);


Shouldn't it be (renaming a little bit for clarity):

input clk, reset;
output q1, q2;
wire  qb1, qb2;

dff dff1(clk,  reset, qb1,  q1, qb1);
dff dff2(q1,   reset, qb2,  q2, qb2);


However a warning: If you use the q output to the clock, a real circuit will add up a significant delay. That's bad for a number of reasons. In some circumstances it's ok though, if you don't care about the phase relationship. If you do care, then look into designing a synchronous counter. Also, for a real circuit, buffer the output from the counter, otherwise if you just pass out q or qb it might see a big load and your counter will (at best) slow down even more.