Timing closure suggestions
Since you mentioned "par" it sounds like you're using Xilinx.  You should run the static timing report "trce."  Run "trce" with verbose timing: "-v 10."  This will show the 10 worst paths even if the constraint is met.  Sometimes you want to optimize/pipeline/register paths that aren't the very worst ones, because fixing these can help reduce routing congestion, and it lets you meet overall timing closure easier (faster MAP/PAR runs).