How do reduce power supply ripple?
The way to compensate these loops is to add a capacitor across the transistor section OR put a capacitor R21. This may cut your response time, but you can't have both no ripple and response without drastically changing the design. 



If you do it right you'll run a spice simulation (usually I do this for people, but I'm way to lazy right now), usually you'll see a Q resonant point in the higher end of the frequency range like the picture shown below. If you do a spice simulation, make sure you simulate the inductance of any wires or large traces, or your simulation will not match the real world. 

If you don't run a spice simulation, you could run an FFT on your scope data, see the point of resonance and insert a LPF pole before the resonance Q point. Compensating these loops is not intuitive because of their closed loop nature. 

If you plan on using this supply over a large range of DC output values, the Q point will change for each DC value because of the transistors.



Source: https://www.researchgate.net/publication/2983401_A_Low-Dropout_Regulator_for_SoC_With_-Reduction/figures?lo=1