FPGA Routing general criteria
There is a lot that goes into it, but I think it's safe to say the fitter decided the best place to put that block of logic is because it was right next to the FPGA pin. If your project has low timing requirements, it probably could have put that block of logic in a different spot and still had it meet timing requirements. 

So to answer your question, yes there is some optimization that put that block of logic next to the port, and yes in an FPGA distance can equate to delay, because the further it is away the more logic and busses the signal has to traverse. 

Here is a diagram of how logic gets compiled, the fitting takes the sythesized HDL and then decides where to put it. If it meets timing constraints then it can be compiled into a file to program the device with.