verilog coding in modelsim
You create k3 as "clk &amp; k2", but then in your flip flop you have always @ (posedge clk) instead of always @ (posedge k3).

Incidentally, as a design practice you should consider using a flip-flop with an enable signal instead of a gated clock.

Also, your schematic shows one latch and one flip-flop, while your Verilog apparently has three storage elements: one instantiated latch, one instantiated flip-flop, and one inferred flip-flop.