Down counter using 4510 IC
Unfortunately the PE input to this counter is asynchronous. In other words it preloads the registers when it goes to a high level and is not synchronized with the clock.

When the input to your 0 detection gates go from 0100 to 0011 they very briefly go through 0000 producing a glitch on on the PE input which is enough to preload the registers.

Solving the problem for the devices used is not trivial. You need to filter out fast glitches on the output of U4. A RC filter would do this put a 10k resistor between U4 and U3 and try capacitors to ground on that input of U3. Start with 10nF and work up.

This will limit your maximum usable frequency but from the look of your application not to a level where I think it will matter to you. It also violates the principles of good digital design which would dictate setting up a synchronous preload but this is not possible with your parts.

If want this to go from "00" to "59" not "01" to "59" you can avoid the problem entirely by using the Q4 only output of U2 to do the preload. This preloads when the counter counts down from "0" to "9" 1001.