FET - Source follower utilizing current source to lower voltage offset
First, \$v_{in}\$ is an AC signal voltage while \$V_{GS}\$ is a DC bias voltage.  These are treated separately.

From a small-signal perspective, the current source (lower FET) is effectively an open circuit so there is effectively no voltage division for the AC signal.  This is why \$v_{in}\$ appears at the output node unattenuated (assuming the output node is connected to an effectively open circuit).

From a DC bias perspective, the gate of the top FET is at (presumably) zero volts so the source, which must be more positive than the gate, must be at 2.8V (using the values in the book and assuming the FETs are identical).

However, note that this is not \$V_{GS}\$ since, in fact, \$V_{GS}\$ for both FETs is -2.8V.  In other words, the voltage at the source of the top FET is $$v_{in} - V_{GS}$$