Trying to understand how to design the gate of a frequency counter
Usually when I hear the term "frequency counter", I think of a device which measures and displays the frequency one signal with respect to another. The drawing you posted is a start at building one of these. They are also sometimes called "time interval counters".

Since your professor only instructed you to use a crystal and a CD4060, I'm guessing that your task is to just build a simple clock using the 14-stage binary counter. But either way, you start the process the same:

First: Wire your crystal to Pins 10 and 11 like this:


Second: Now you can choose the desired signal from the counter's stage pins. 

A commonly wanted signal is 1 Hz. Did you notice that your 32.768 kHz oscillator is a power of 2? If you divide this number (32,768) by two, 15 times, you will get 1 Hz. 

But since the CD4060 is a 14-stage counter (and we need 15 stages to get 1 Hz), you can only get a 2 Hz signal, on Pin 3 (Q14).

You can, however, add an additional stage manually. For example, this circuit will give you 1 Hz (and beyond):


circuit reference

Finally
To complete the design of an actual frequency counter, you can basically now just repeat the process. Clock a second counter with the signal that you intend to measure, and gate the chip's operation with the 1 Hz signal created above. The gate should serve as both a reset to the second counter, and a latch to send the previous measurement to the display (or receiving circuitry).

The second counter will therefore tell you how many oscillations occurred within your 1 Hz (1-second) time period - and oscillations per second = frequency in Hz.