Count the clock cycle using LTSpice
Building on top of your approach, you can use the following circuit.
The only modification is the addition of an ideal diode to prevent the capacitor, which acts as memory, from discharging. The bevavioral voltage supply increments the voltage across the capacitor whenever there is a rising edge present at the CLK line. 



EDIT #1

In order to add an active high reset to the previous counter, it suffices to change the voltage behavioural statement to:

V=IF(V(RST), 0, IF(buf(ddt(V(CLK))),V(count)+Vstep,0))

and create a voltage source with an output voltage node named RST. 

Here is a more compact version with only one voltage supply and the possibility of being reset.