Maximum frequency of the synchronous counter
The book is wrong. The minimum clock period is 30 ns.


First FF clock-to-Q: 10 ns
First AND gate in-to-out: 10 ns
Second AND gate in-to-out: 10 ns
Setup time to third FF: 0 ns


Total: 30 ns

This is the time required from when the output of the first FF goes high (while the other two FFs are already high) to insure that the third FF goes low on the next clock edge.



EDIT: There's a surprising amount of confusion about this, so here are some diagrams that I hope will make it clear.

The first shows the counter counting from the all-zero state, with each horizontal space representing 5 ns. The FF and gate delays are shown as exactly 10 ns. Note that the J2K2 input to the third FF just barely makes it in time for both the 01x and 11x states.

         __    __    __   |__    __    __    __   |__    __
clock __/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__
           _____    :  _____       _____    :  _____       ___
Q0    ____/     \_____/   | \_____/     \_____/   | \_____/
             _____  :    _____       _____  :    _____       _
J1K1  ______/     \_____/ |   \_____/     \_____/ |   \_____/
                 ___________             ___________
Q1    __________/   :     | \___________/   :     | \_________
                   _:     |___             _:     |___
J2K2  ____________/ \_____/   \___________/ \_____/   \_______
                          |  _______________________
Q2    ______________________/                     | \_________
                          |                       |
10ns  ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^


The dotted vertical line shows the case where Q2 is not supposed to toggle, and the solid vertical line shows where it is.

A conservative design (in the absence of any minimum propagation delay specifications) would assume that the outputs of the FFs and gates become invalid as soon as any input changes. Here's an expanded view that takes this into account:

            _____       _____       _____      |_____ 
clock _____/     \_____/     \_____/     \_____/     \_____
            _______________        :_______________
Q0    _____/XXX/       \XXX\_______/XXX/       \XXX\_______
            ___________________    :___________________
J1K1  _____/XXXXXXX/   \XXXXXXX\___/XXXXXXX/   \XXXXXXX\___
                        ___________________________
Q1    _________________/XXX/       :           \XXX\_______
                        __________ : ___________________
J2K2  _________________/XXXXXXXXXX\_/XXXXXXXXX/ \XXXXXXX\__
                                               |___________
Q2    _________________________________________/XXX/
                                               |
10ns   ^   ^   ^   ^   ^   ^   ^   ^   ^   ^   ^   ^   ^


Here, I've shaved a little bit off the delay of J2K2 to illustrate how it just barely becomes valid in time for the two key clock edges. To summarize, Q0 becomes valid 10 ns after the clock edge, J1K1 becomes valid 10 ns after Q0 becomes valid, and J2K2 becomes valid 10 ns after J1K1 becomes valid, which is just in time for the next clock edge.

Also, as Brian Drummond pointed out, I'm completely ignoring the carry output of the circuit (the third AND gate). The question is only about the maximum clock frequency of the counter itself. If that output needs to be valid, then the clock period will have to be even longer.