Peak power pulse in parallel MOSFETs
In other words, as the gate pins are being driven low, is there some
  property of MOSFETs that would cause one single MOSFET to end up
  taking the brunt of the switching power dissipation? Or will they all
  share the total power dissipation equally?


Your suspicions are correct. The normally nice side of MOSFETs sharing current only applies when the gate source voltage is above a certain threshold called the zero-temperature-coefficient (ZTC) threshold. For the MOSFET you have chosen it is about 6.7 volts: -



Basically I took figure 5 and extended the curves to the ZTC threshold. At gate voltages lower than this a MOSFET will warm to destruction if not prevented in some way. Take for example the situation at 25 degC and the instant application of a gate voltage of 5 volts. Current will be about 40 amps and this will cause the junction temperature to rise rapidly and, within a few milli seconds it will have warmed to 150 degC and now will be taking about 140 amps. The junction will rapidly rise past the 175 degC limit and reach destruction temperature (about 650 degC) in a few more milliseconds.

Not all of the silicon die will warm this way. In modern HEXFETs there are a gazillion parallel small MOSFETs and the most vulnerable are those closest to the centre and farthest away from the "cooler" edge. You wil get hot-spotting and the central 10% of the die will take all this current and destruct unless there are limits to the current flow.

This can happen in less than 10 ms and you wouldn't even notice hardly the slightest external change in temperature on the case. In other words, heat sinks DO NOT prevent this happening.

So hot-spotting can happen in a group of MOSFETs and it can also happen in an individual MOSFET. Some MOSFETs are designed for operating in this area and IXYS make quite a few. The front page of the data sheet will tell you. If it says that the MOSFET is for switching applications then it is likely to be vulnerable; if it says it is for linear applications than it is likely suitable and, if you look at a suitable device's equivalent of figure 5 you will see that the curves are much tighter leading to very little extra drain current as the device warms.

Go google "thermal instability in MOSFETs" and please consider a MOSFET driver that can turn off the gate voltage in less than 1 ms. Those MOSFETs have a gate-source capacitance of 15 nF and 8 of them makes a total capacitance of over 100 nF. It may even be necessary to use several gate drivers.