SPI and clock active low or high
Clocks don't generally have an active "level" per say; in many cases clock outputs will specify that they'll only stop when they're at a certain level, but otherwise clocks have active edges.  Typically, SPI devices will use one clock edge as a signal to output each bit of data, and the following clock edge as a signal that to latch the data from the other device.  In some cases, SPI devices will asynchronously place the first bit of data; the first clock transition will latch that and the second will output the second bit, the third will latch the second bit and the fourth will place the next, etc.  The fifteenth transition will latch the last bit, and the sixteenth will indicate that the device should start outputting the first bit of the next byte sometime before the next clock transition.