(System)Verilog: extracting a smaller bus/vector from a larger bus?
I would use an array with the length of the short bus that maps short bus indices to large bus ones:

// Large Bus Width
localparam int LBW = 8;
localparam logic [LBW-1:0] VALID = {1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0};

// 1. Function returning the width of the short bus
function automatic int get_short_width();
    automatic int si = 0;
    for (int li=0; li&lt;LBW; li++)
        if (VALID[li])
            si++;
    return si;
endfunction

// Short Bus Width
localparam int SBW = get_short_width();

typedef int t_idx_arr[SBW];
// 2. Function returing the large-to-short array index mapping
function automatic t_idx_arr get_short_indices();
    t_idx_arr idx_ret;
    automatic int si = 0;

    for (int li=0; li&lt;LBW; li++) begin
        if (VALID[li]) begin
            idx_ret[si] = li;
            si++;
        end
    end
    return idx_ret;
endfunction

// Large 2 Short Index Array
localparam t_idx_arr L2S_IDX = get_short_indices();

// 3. Assign
logic[LBW-1:0] large_bus;
logic[SBW-1:0] short_bus;

// note: loop on the SHORT bus width!
for (genvar si=0; si&lt;SBW; si++) begin
    assign short_bus[si] = large_bus[L2S_IDX[si]];
end

assign large_bus = 8'b1101_1011;
// short_bus = 4'b1011


This works for non-consecutive valid bit positions on the large bus as well.