Verilog - use a clock signal as a value in its own procedural block
Xilinx recommends in their coding guidelines that clock signal should not have combinational logic on their path. Whenever you write an expression with clock, you are generating a combinational logic with clock as one of the inputs. 

Clocks have dedicated global routing in FPGA, which synthesiser may not be able to utilise if you bring combinational logic on their path.