Should I really prefer to use std_logic type to write sythesizable VHDL?
For external signals that drives pins, std_logic should be used (and derivatives such as std_logic_vector, unsigned, signed). Alternatively bit

For internal signals, integer with range bounds, record, boolean, enumerated types, even character are synthesisable.

Time is not synthesisable except for calculating integer constants, floating point real also only for constants.