CPLD High-Z pin - safe to drive over the high logic level voltage?
It could cause damage. There are still transistors (both for output and input) behind that CPLD pin even if they are not conducting. Think about it. Can a transistor that is blocking block an arbitrarily high voltage? No.

I would not assume a pin that outputs 3V would be able to block anything more than 3V, but you can check your CPLD electrical characteristics in the datasheet to verify.

Also, even if the transistor itself might be able to block 3V it is likely never going to get the chance unless things go really bad and the internal ESD diodes blow. Digital pins almost always have clamp diodes with a forward voltage drop of \$V_f\$ for ESD protection. If the line gets higher than \$V_{dd} + V_f\$ or lower than \$GND - V_f\$, then a diode will forward bias and conduct from the pin to the corresponding power rail.

If you apply a voltage higher than the supply voltage of the chip, or lower than the GND of the chip, these diodes will forward bias and conduct. Via this route, you could be applying 5V directly to the power pins of the chip itself (or your driver chip will be fighting the power supply which isn't good either), not just the blocking transistors behind the pin.

This is why its bad to drive unpowered chips. You can inadvertenly power up the chip partially through its signal pins.







simulate this circuit &ndash; Schematic created using CircuitLab

What this does mean, however, is that you could add a series resistor to limit the current flowing through these diodes and provide something else to drop the extra voltage across. This will, however, slow down your line speed. You can also add external diodes for more power handling. This is a method commonly used to clamp the voltage of a line.