Why isn't my blinky program working for my STM32F446RE Nucleo board?
same family of card/chip. and this code works (this exact binary should work on your board/chip)

void PUT32 ( unsigned int, unsigned int );
unsigned int GET32 ( unsigned int );
void dummy ( unsigned int );

#define RCCBASE 0x40023800
#define RCC_AHB1ENR (RCCBASE+0x30)

#define GPIOABASE 0x40020000
#define GPIOA_MODER     (GPIOABASE+0x00)
#define GPIOA_OTYPER    (GPIOABASE+0x04)
#define GPIOA_BSRR      (GPIOABASE+0x18)

int notmain ( void )
{
    unsigned int ra;
    unsigned int rx;

    ra=GET32(RCC_AHB1ENR);
    ra|=1&lt;&lt;0; //enable GPIOA
    PUT32(RCC_AHB1ENR,ra);

    ra=GET32(GPIOA_MODER);
    ra&amp;=~(3&lt;&lt;10); //PA5
    ra|=1&lt;&lt;10; //PA5
    PUT32(GPIOA_MODER,ra);
    //OTYPER
    ra=GET32(GPIOA_OTYPER);
    ra&amp;=~(1&lt;&lt;5); //PA5
    PUT32(GPIOA_OTYPER,ra);

    for(rx=0;;rx++)
    {
        PUT32(GPIOA_BSRR,((1&lt;&lt;5)&lt;&lt;0));
        for(ra=0;ra&lt;200000;ra++) dummy(ra);
        PUT32(GPIOA_BSRR,((1&lt;&lt;5)&lt;&lt;16));
        for(ra=0;ra&lt;200000;ra++) dummy(ra);
    }
    return(0);
}


Disassembly of section .text:

08000000 &lt;_start&gt;:
 8000000:   20001000    andcs   r1, r0, r0
 8000004:   08000041    stmdaeq r0, {r0, r6}
 8000008:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 800000c:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000010:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000014:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000018:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 800001c:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000020:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000024:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000028:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 800002c:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000030:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000034:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 8000038:   08000047    stmdaeq r0, {r0, r1, r2, r6}
 800003c:   08000047    stmdaeq r0, {r0, r1, r2, r6}

08000040 &lt;reset&gt;:
 8000040:   f000 f80a   bl  8000058 &lt;notmain&gt;
 8000044:   e7ff        b.n 8000046 &lt;hang&gt;

08000046 &lt;hang&gt;:
 8000046:   e7fe        b.n 8000046 &lt;hang&gt;

08000048 &lt;PUT16&gt;:
 8000048:   8001        strh    r1, [r0, #0]
 800004a:   4770        bx  lr

0800004c &lt;PUT32&gt;:
 800004c:   6001        str r1, [r0, #0]
 800004e:   4770        bx  lr

08000050 &lt;GET32&gt;:
 8000050:   6800        ldr r0, [r0, #0]
 8000052:   4770        bx  lr

08000054 &lt;dummy&gt;:
 8000054:   4770        bx  lr
 8000056:   46c0        nop         ; (mov r8, r8)

08000058 &lt;notmain&gt;:
 8000058:   b538        push    {r3, r4, r5, lr}
 800005a:   481b        ldr r0, [pc, #108]  ; (80000c8 &lt;notmain+0x70&gt;)
 800005c:   f7ff fff8   bl  8000050 &lt;GET32&gt;
 8000060:   2301        movs    r3, #1
 8000062:   1c01        adds    r1, r0, #0
 8000064:   4818        ldr r0, [pc, #96]   ; (80000c8 &lt;notmain+0x70&gt;)
 8000066:   4319        orrs    r1, r3
 8000068:   f7ff fff0   bl  800004c &lt;PUT32&gt;
 800006c:   4817        ldr r0, [pc, #92]   ; (80000cc &lt;notmain+0x74&gt;)
 800006e:   f7ff ffef   bl  8000050 &lt;GET32&gt;
 8000072:   2180        movs    r1, #128    ; 0x80
 8000074:   4b16        ldr r3, [pc, #88]   ; (80000d0 &lt;notmain+0x78&gt;)
 8000076:   00c9        lsls    r1, r1, #3
 8000078:   4018        ands    r0, r3
 800007a:   4301        orrs    r1, r0
 800007c:   4813        ldr r0, [pc, #76]   ; (80000cc &lt;notmain+0x74&gt;)
 800007e:   f7ff ffe5   bl  800004c &lt;PUT32&gt;
 8000082:   4814        ldr r0, [pc, #80]   ; (80000d4 &lt;notmain+0x7c&gt;)
 8000084:   f7ff ffe4   bl  8000050 &lt;GET32&gt;
 8000088:   2320        movs    r3, #32
 800008a:   1c01        adds    r1, r0, #0
 800008c:   4811        ldr r0, [pc, #68]   ; (80000d4 &lt;notmain+0x7c&gt;)
 800008e:   4399        bics    r1, r3
 8000090:   f7ff ffdc   bl  800004c &lt;PUT32&gt;
 8000094:   4810        ldr r0, [pc, #64]   ; (80000d8 &lt;notmain+0x80&gt;)
 8000096:   2120        movs    r1, #32
 8000098:   f7ff ffd8   bl  800004c &lt;PUT32&gt;
 800009c:   2400        movs    r4, #0
 800009e:   4d0f        ldr r5, [pc, #60]   ; (80000dc &lt;notmain+0x84&gt;)
 80000a0:   1c20        adds    r0, r4, #0
 80000a2:   3401        adds    r4, #1
 80000a4:   f7ff ffd6   bl  8000054 &lt;dummy&gt;
 80000a8:   42ac        cmp r4, r5
 80000aa:   d1f9        bne.n   80000a0 &lt;notmain+0x48&gt;
 80000ac:   2180        movs    r1, #128    ; 0x80
 80000ae:   480a        ldr r0, [pc, #40]   ; (80000d8 &lt;notmain+0x80&gt;)
 80000b0:   0389        lsls    r1, r1, #14
 80000b2:   f7ff ffcb   bl  800004c &lt;PUT32&gt;
 80000b6:   2400        movs    r4, #0
 80000b8:   4d08        ldr r5, [pc, #32]   ; (80000dc &lt;notmain+0x84&gt;)
 80000ba:   1c20        adds    r0, r4, #0
 80000bc:   3401        adds    r4, #1
 80000be:   f7ff ffc9   bl  8000054 &lt;dummy&gt;
 80000c2:   42ac        cmp r4, r5
 80000c4:   d1f9        bne.n   80000ba &lt;notmain+0x62&gt;
 80000c6:   e7e5        b.n 8000094 &lt;notmain+0x3c&gt;
 80000c8:   40023830    andmi   r3, r2, r0, lsr r8
 80000cc:   40020000    andmi   r0, r2, r0
 80000d0:   fffff3ff            ; &lt;UNDEFINED&gt; instruction: 0xfffff3ff
 80000d4:   40020004    andmi   r0, r2, r4
 80000d8:   40020018    andmi   r0, r2, r8, lsl r0
 80000dc:   00030d40    andeq   r0, r3, r0, asr #26