draw out as frequency divider from circuit
I believe the circuit is a divide by three, as shown below (I modified the timing diagram that Tony drew):



Because of the NOR gate feeding into D1, D1 can only be 1 when both Q0 and Q1 are 0:

Q0   Q1   D1
------------
 0    0    1
 0    1    0
 1    0    0
 1    1    0