Single master I2C with multiple target devices
To expand on the comment from @Oldfart: all I2C transactions starts with a START condition. This signals the bus target devices to listen for a 7-bit address. Once those seven bits, plus the R/W bit are sent, the targets stop listening for addresses and, unless they saw their address, start ignoring all bytes that go by on the bus.
This continues until the master sends a STOP condition. At that point, all of the targets wake up and start looking for another START condition.
(There is also a way to stack transactions to a single target, called a repeated START. This happens when a START is sent without a STOP to terminate the previous transaction. This start is followed by an address but only the targets that was already communicating actually listens for its address. This is used to combine reads and writes within a single transaction.)
I should add that START and STOP conditions are signalled on the bus in ways that will never occur during normal data. This way, it is impossible to mistake data for a STOP, assuming the bus is functioning correctly.