Logisim: timing problems setting register
I've never used Logisim, but I have an idea of what it may be doing:

Some of your circuits lack pull-up/down at the clock input.  It may be that it defaults to one (implicit weak pull-up).  If that is the case, then a floating input is equivalent to a weak one.

With this in mind, in the circuit with the n-gate (or the controlled buffer, which I assume is a tri-state buffer) the register clock input never sees a zero (so it doesn't toggle).  It can't because the n-gate is either propagating a one or disabled, in which case the floating register clock input defaults to weak one.  Without a toggling register clock, data never gets clocked in, so it remains at the default zero.  

Note that the order of assignments is:


input to n-gate
enable/disable n-gate simultaneous with register data input
output of n-gate simultaneous with register clock input.


In the last circuit with the p-gate the same order of events apply, but with different values.  When the clock signal is zero then the p-gate is enabled due to the explicit pull-down, so the p-gate propagates the clock value of zero.  When the clock signal transitions to one it disables the p-gate at the same time that it sets the register data input to one, and a unit delay later the register clock input goes floating (weak one), clocking in the current input, which we said is one.  

So the first behavior is to never clock-in data, and the register output remains at zero.
The second behavior is to only clock-in ones, so the register output goes to one and never returns to zero.