Can a resistor mitigate a maximum input voltage limitation?
5V logic IC's without hysteresis usually have a Vih &gt;=0.70 Vdd which at 5V &gt;=3.5V but at -10% = 4.5V is 3.15V.
To limit Iin(abs. max) to target 3.3V device from 5V to 5mA even though many CMOS ESD protection diodes can handle 20mA, a series resistance may be included of (5-3.3)/5mA = 340 ohms and 1K to 10K may be used with a safety margin unless rise time is a major concern with &lt; 5pF per gate.
Thus a simple solution is to choose a 5V driver with 1k series resistance added.



simulate this circuit &ndash; Schematic created using CircuitLab
Even though adding 1k appears to be redundant, it allows one to verify the action of the ESD protection on the 3.3V interface and Iih input current from measuring the voltage drop if you wish to verify using a 5V driver.
ESD dual-stage diode protection is what allows all CMOS which is universally designed to be protected with the Human Body Model, JEDEC: JESD22−A114  4kV 100pF discharge.