deserializing high speed data
640Mb/s DDR is a bit quick for fabric logic, but may be manageable with a DDR configured IO block in a reasonably fast part. 

However every even semi recent xilinx part has an ISERDES available on the inputs, and these are more then quick enough to deal with 640Mb/s DDR mode data even in speed grade 1. 

I note that your chosen ADC is radiation hardened, if you need it, that may well be a bigger issue then link speed as it will massively reduce your FPGA (And configuration device) options. If you don't need rad hard, there are probably far cheaper ADCs that would get it done.  

What FPGA, depends on what you need, I would go 7 series just because that gets you Vivado as a tool chain that is getting more love then ISE (Also its constraints file format is less annoying IMHO).