VHDL - Can't see why these two architectures produce a different RTL
In the first, y is set to a default value of 1 at start-up time.  In the second, y is set to an initial value of 1 each time the process runs.  

The first carries the resulting value of y over to the next time it runs, the second doesn't but starts with y equal to 1.  Hence the feedback.

In C it's the equivalent of something like this:

int y = 1;
void doSomething() {
    y = y + 1;
}

int y;
void doSomething() {
    y = 1;
    y = y + 1;
}


In the first, each time doSomething() is called y is incremented.  In the second, each time doSomething() is called y is set to 1 and then incremented, so always ends up as 2 regardless of how many times you call doSomething().