How to design the value of capacitor for Capacitive DAC based on noise and mismatch analysis?
The minimal error you need to be comparing against is the performance of an ideal DAC.

If step size is LSB = \$1.2/2^{14}\$ = 73.2 \$ uV \$ 

then the error residue will be

LSB\$/\sqrt{12}\$ = 21.1 \$ uV \$

If you want the noise contribution (RSS addition) to not be noticeable then the kTC noise should be 1/10 of that = 2.1 \$ uV \$

Which means that the capacitor size is 907 pF or ~ 1 nF using the kTC calculation.

The kTC noise is developed across what ever is being reset.  To answer your question you will have to give a schematic. If the Capacitor is being reset from a voltage source or other capacitors, and if there are other Capacitors attached and how that charge equilibrates and the impact of charge conservation.