Handling a multiplexed bidirectional data bus in VHDL
If you have an inout-pin that you use as input (while reading) set its output to tri-state.

Here's a simplified example

ENTITY inout IS
port (
  wr_en : IN STD_LOGIC;
  data_io : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END inout;

ARCHITECTURE struct OF inout IS
  SIGNAL input : STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL output : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
  data_io &lt;= output WHEN wr_en = '1' ELSE 'Z';
  input &lt;= data_io WHEN wr_en = '0' ELSE (OTHERS =&gt; '0');
END ARCHITECTURE struct;


Edit: As correctly stated by Oldfart the assignment for the input vector can be unconditionnal input &lt;= data_io. I leave it conditional in the example code as usually when writing to the port, the incomming (looped) data is not of interest/invalid.