How to define a false path using design entities
If the mux control terms are common, I would expect the synthesis tool to only analyse active paths. You should check this first (look at the timing report and see what the critical path is).

You might be able to re-order your logic so the problem doesn't exist. I wonder if this might make optimisations simpler too (maybe).

If you really need to, its possible to false-path, from in to out, and set_min_delay from in to y, and x to out. False path is really never the best answer though, you'll never know you did it right (and you'll know if you did it wrong).