System verilog instantiation of parameterized module
If I have a mymodule that has parameters and I am instantiating this mymodule inside a top level block which has a few sub module and mymodule is also a submoulde then when instantiating mymodule inside the top level,do I need to define the parameters of mymodule inside the top level?


You need to supply the parameters wherever your module is instantiated. If your module is instantiated in multiple locations, each of those locations creates a separate instance of your module, and each instance has its own parameters. The parameters do not need to be the same in all locations.


  if there are some signal(rem) from mymodule that I do not need its value ,then when instantiating this mymodule inside the top level can I map them like below


If the port is an output, you can leave it out from the instantiation entirely. You don't need to mention the port at all.

If the port is an input, it cannot be omitted.