True single phase clock based flip flop
This is an interesting design, but it looks very sensitive to the process used. Fundamentally, it's a dynamic RAM cell, so the state is stored as charge on the node labeled !Q, using the gate capacitances of M7 and M12. The unusual part is that it also briefly stores charge in two other locations: the gate of M5, and the gates of M3 and M10.

Let's call each column of transistors in the diagram a stage, so for example stage 1 consists of M1, M4, and M8.

Suppose the clock input is 0 and the data input is also 0. In this case, the output of stage 1 is 1, the output of stage 2 is 1, and the output of stage 3 is high-impedance, meaning that its output is not connected to either power rail. As a result, the charge at !Q does not change. Now suppose the clock signal goes high. This causes the output of stage 1 to go high-impedance, so it remains at 1 because of the charge stored on the gate of M5. Stage 2 now outputs 0, so stage 3 outputs 1, which causes charge to be stored at !Q if it was not already. The data value has been latched.

Suppose instead that the clock input is 0 and the data input is 1. In this case, the output of stage 1 is 0, the output of stage 2 is 1, and the output of stage 3 is high-impedance. As a result, the charge at !Q does not change. Now suppose the clock signal goes high.  Stage 1 still outputs 0, so the output of stage 2 is high-impedance, which means it remains at 1 because of the charge stored on the gates of M3 and M10. Stage 3 now outputs 0, which removes any charge stored at !Q.

Stage 4 is the reset: when !R is brought low, M11 turns on, ensuring that !Q is charged. Stage 5 is an inverter, so that Q will be 1 when !Q is 0 and vice versa. It also acts as a buffer, allowing current to be draw from Q without affecting the charge at !Q.

The clever aspect of this design, and the reason it's so complicated, is that it is edge-triggered: a change to D while the clock is high does not affect the output: suppose D is 0 while clock is 1, and then D goes to 1. This will cause the output of stage 1 to go to 0, which will cause stage 2 to go high-impedance, so its output of 0 will be preserved by capacitance and the output of stage 3 will not change. Similarly, if D is 1 while clock is 1, and then D goes to 0, stage 1 will go high-impedance, preserving its output of 0, so subsequent stages will not change.