How to calculate the differential impedance for a stackup design
All results are accurate to the assumptions and parameters you enter in. As I see, you took a liberty to use nearly arbitrary values for dielectric constant, from 2.45, 3.11-12, to 4.5. And 5% or 10 % makes no difference and usually is impossible to meet from first calculations, if ever.

What you need to do is to get your preferred PCB manufacturer, and request their preferable stack-up, copper thickness, prepeg thickness, and dielectric constant. With their guaranteed manufacturing tolerances. Then pick some reasonable trace geometry. Don't forget to notify the house about "impedance controlled design", a good house will correct the width of your traces for overetch, so the final width will be as specified. And include several variants of test coupons, with access points to a VNA. If you really believe that you need traces with better than 10% match (or you have some paranoid manager), you test your coupons for impedance, and if it doesn't meet your expectations, you cut the board and verify trace/stack dimensions, and either talk back to manufacturing house, or make necessary adjustments. And spin another board, until you get your impedance right.