Is it possible to make hierarchy of constants in System Verilog?
I don't really understand your question, but, parameters are used in System/verilog (synonomous with constants in VHDL).  A question was just answered about them:  How do I calculate constant values across several modules at compile time in Verilog?.  

It is possible to reference hierarchy with "dot notation" in the Verification-space of SV (i.e. OOP)... not likely for synthesis (tool dependent, maybe).  

And, I wouldn't recommend trying to synthesize structs... maybe "packed structs" will work, but, it is kind of esoteric in terms of "explicitly defined Hardware". (Just my opinion... there are lots of things you can do in any language, but it doesn't mean you should)

Do you have access to IEEE1800-xxxx?  If not, there are lots of resources online, and you may find a copy of the Accellera version somewhere... looks like   Accellera doesn't have it on their site anymore (Officially graduated to IEEE, I suppose)