NPN Transistor Current Limiting Changes From Collector Load To Emitter Load
In your first circuit, the signal is voltage amplified by Vin * hFE of the transistor, until you reach a level that approaches Vdd to ground, causing distortion. Vbe can never be more than 0.7 volts.

In your second design there is no voltage amplification but current of the signal is boosted. It will appear at the speaker terminals minus 0.7 volts, the Vbe drop. Output volume will be much less, but saturate quicker as the Vbe drop subtracts from your voltage swing across the speaker.

Note that if your signal source is relatively high-impedance, as in a volume control, both designs will give you a boost in sound level. Both designs take advantage of the transistors hFE. The first design you can saturate the transistor fully ON, so more current is consumed.

In the second design the speaker will not let the emitter go to zero volts, even with a strong signal. This mode will cause distortion sooner as you have a voltage range of just ground to Vdd -0.7 volts minus the Vce drop. Putting the speaker on the emitter creates some negative feedback, further reducing the gain.