always @(*) vs. assign
always @(*) is certainly more readable, especially when writing to more than one output signal with a common set of conditions. 

But @* can have time 0 simulation problems. If, because of macros or generate statements, the signals in the sensitivity list do not change at time 0 and resolve to constants, you are left with an uninitialized output. 

SystemVerilog solved this by creating the always_comb block which always executes at least once at time 0.