Set latch and Or gates
When analyzing the behavior of a latch when the inputs are in the "hold" condition you don't know what the stored state of the latch actually is. So, you assume that the stored state is a '1' and verify that all of the other signals in the latch will be consistent with that assumption. Then, you assume that the stored state is a '0' and verify that all other signals are consistent with the new assumption. If so, then you have a valid latch circuit and you've identified the input conditions that cause the latch to retain its state.

By the way, you can't make a latch from two OR gates. You need to use inverting gates such as the NOR or NAND.