Combinational logic delay is greater than clock period
Delaying the clock of the following register would steal time from the next stage in the pipeline, imperiling the setup time of the register following that.

If you know for a fact that the next stage has a sufficiently short propagation delay it could work, but it would be cause for a lot of caution and explicit warnings in the design documents, less someone later revise that next stage on the assumption that they have a normal clock interval to work with.

A more traditional / textbook answer would be to add an additional pipeline stage by inserting a register somewhere in the middle of the long combinatorial path, breaking it up into two paths each of which will meet timing (or, in an extreme case, inserting multiple registers).