Why are the voltages the way they are in this transistor circuit?
Basically it comes down to how logic-level FETs need to be biased to be fully on or off.
FETs have a characteristic gate-source threshold voltage, Vgs, that must be met before they turn on.

N type: the gate voltage must be above the source +Vgs threshold
P type: the gate voltage must be below the source -Vgs threshold

Let's have a look in a sim with what they drew, and compare it to the behavior when N and P are in their 'right' places:

Simulate it here: NAND Gate Sim
The example they show never gives the FETs a fighting change to do their jobs, because the Vgs biasing isn't right. Basically, the Fig. 3.7(a) circuit makes the FETs behave as followers, which means that the source will always be no closer than one Vgs threshold to the gate voltage.
That is, assuming Vgs threshold of 0.7V (as in the sim):

N-FET with source at +1.2, with Gate at +1.2, Drain will never be higher than 0.7V (1.2V - 0.7V);
P-PET with source at 0V, with gate at 0V, Drain will never be lower than 0.7V (0V - (-0.7V))

The sim doesn't show exactly those values. Why? The influence of the two low-side FETs in series, and the exact FET model the sim used.
The point is, the FET needs to have Vgs biased to a useful value to get the result you desire. The second diagram swaps the P and N FETs and voila! gives a functioning NAND gate.