Flip-Flop Made with 74xx Chips not Latching Consistently
WHen you ignore propagation delays with excessive delays from cascaded stages, then you see you had a Race Condition and forced the race with a big fat cap.

The proper design looks like below. note the number of stages from inputs to outputs is symmetrical.



Although the above is the topology for LS TTL and you are using HC CMOS, it doesn't matter for learning but the CMOS FF is made of Transmission Gates (TG)