Is there a relationship between thickness of the oxide gate and the length of the channel in a MOSFET?
No, in a CMOS process I can choose almost any length for a MOSFET I like, within limits of course. More than 100 um is usually not practical and also unneeded.

But if you mean the minimum channel length, that is process dependent. It is determined by the minimum allowable polysilicon width. Which in turn is mostly dependant on the minimum feature size allowed by the masks but also by the process itself. I mean, the minimum polysilicon width which can be made reliably.

The gate oxide thickness sets the "gain" or K-factor (\$uC_{ox}W/L\$) of the MOSFETs and is also a design choice. A thicker oxide results in a higher threshold voltage and slower transistors but less power consumption. A thicker oxide is able to withstand a higher supply voltage.

As such these parameters are interrelated not so much by a formula but more by what the manufacturer wants as an end result. High or low power consumption, low or high supply voltage etc.