An overall PWM system by using FPGA
See code below to combine 3 files together.

--- top.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
port ( 
    clock : in  STD_LOGIC;
    clear : in  STD_LOGIC;
    sel   : in  STD_LOGIC;
    y     : out STD_LOGIC
);
end top;

architecture beh of top is

signal freq1 : std_logic;
signal freq2 : std_logic;

begin

chip1 : entity work.mux2to1
port map(
    freq1 =&gt; freq1,
    freq2 =&gt; freq2,
    sel   =&gt; sel  ,
    y     =&gt; y
);

chip2 : entity work.FreqDivider200Hz
port map( 
    clock =&gt; clock,
    clear =&gt; clear,
    freq1 =&gt; freq1
);

chip3 : entity work.FreqDivider400Hz
port map( 
    clock =&gt; clock,
    clear =&gt; clear,
    freq1 =&gt; freq2
);

end beh;