Delay in 4-bit ripple carry adder?
Your analysis of the single full adder is correct as far as it goes, but it is incomplete.

The delays you show are all based on the Xi and Yi inputs. But the delays from the Ci input are different, since they don't go through the first half adder.

The reason this is important is that when you combine the full adders together to create a 4-bit adder, the Ci to Ci+1 delay is a key component of the "critical path" to the upper output bits and the final carry output.

When doing this sort of timing analysis, you need to consider the delays from each input to each output, and use the appropriate delay when combining modules together to form larger structures.