VHDL: I can port map std_logic_vector to a signed or unsigned port, why?
You can use a type conversion in an association list e.g. in a port map.

Depending on the (port) direction, you need to specify the conversion either on the formal (output), actual (input) or both sides (inout).

port map (
  myUnsigned                 =&gt; unsigned(mySLV1),  -- input
  std_logic_vector(mySigned) =&gt; mySLV2             -- output
);