Level-triggered flip-flops in shift register
If you use level-triggered flip-flops (without a two-phase, non-overlapping clock) then all of the flip-flops will be transparent at the same time. The input to the first flip-flop will propagate all of the way to the output of the last flip-flop whenever the clock input is asserted.

By the way, I think it is better to call a level-sensitive storage element a "latch".