How is the Truth Table of Positive edge triggered D Flip-Flop constructed?
You have to consider that CLK is a toggling signal. If we want to analyze what happens when CLK = 1, we have to consider first what happened before the rising edge of CLK, when CLK was 0.

When CLK was zero the inputs of the upper Set-Reset FF formed by NAND1 and NAND2 where Set=1, Reset=0. Now, when the inputs of that FF pass from 1-0 to 1-1 their outputs are uniquely defined, with S (its negated output) being 1. From this point I guess you can finish the analysis alone.

As a conclusion of your analysis you will also understand why it is important for D to be stable while CLK is toggling.