Shift register parallel in serial out
You questioned as to whether you would ever need to use the "hold" state of the shift register. In your case, since you are using a bit-banged approach to operate the shift register you have the ability to selectively inhibit the clocking going to the register. Under this condition there will really be no need to use the "hold" state because the same thing can be attained by holding the clock pin at a constant level (either high or low).

The real use for the "hold" state could come into play on cases where the clock is a constantly running signal and hardware logic is implemented to produce LOAD and ENABLE pulses to the shift register to permit operation at the desired times. Such logic would have to produce the pulses in proper synchronism to the clock signal to ensure that setup and hold times around the rising edge of the clock are met so that the shift register operates correctly.