How does a PMOS LDO work?
The opamp will settle such that \$V_{gs}\$ for the PMOS is close to its threshold. The FET is almost never fully on or off unless very briefly during startup and step changes.
When Vout drops a little, so will the voltage at the IN+ of the opamp. Therefore the opamp output will drop also a little. This makes the \$V_{gs}\$ more negative, opening the PMOS a little more. That in turn rises the Vout again, compensating the initial drop.
Like any feedback control, this can become unstable if the output changes occur more rapidly then the opamp can compensate or detect them.