Do shift registers refresh?
Your question text contradicts itself a bit:

"2 Shift Registers chained together"


does not match with

"data is written to SR1 and then to SR2 "


From your comment I understand that the SRs are chained, SR1 directly to the uC, SR2 to SR1.

In that case each shiftOut call transfers its data to SR1, and simultaneously trasnfers the content of SR1 to SR2.

Assuming that you use SRs with separate shift and hold registers, the output should not glitch when you 're-issue' the same value for a pin, but do check the datasheet of you chip. Very short glitches around a clock edge are always a possibility, and most datasheets do not completely rule this out.