How to fit RF, power, analog components all together tightly on PCB?
Those large foil layers become magnetic shields for frequencies faster than about 1MHz (just a few dB reduction), with 4MHz getting 9dB (1 neper), 40 MHz getting 27 dB (3 nepers), 160MHz (typical MCU edge speed or VDD ringing) getting
50--60dB attenuation, and 400MHz (sub_nanosecond edges) getting 80--90 dB attenuation (10 nepers or 90dB).

One way to cause lots of problems is to SHARE the +3.3 volt (or +2.5v) or +5volt copper foil, everywhere in your electronic system.


By sharing, rail_trash from one IC becomes rail_trash for all the other ICs, and the PSRR power supply rejection at high frequencies becomes a crucial spec.

By inserting series resistors, 1 ohm or 3.3 ohm or 10 ohms, in selected places, the VDD foil becomes a VDD_TREE. Note that 10 ohms and 1uF becomes a 10uS timeconstant and a 16KHz low pass filter, able to attenuated SwitchReg trash by 100:1, and attenuated MCU VDD ringing by possibly 10,000:1 (limited by the capacitor ESR and ESL). Thus small_value resistors IN SERIES in the VDD traces can significantly clean up VDD trash, for crucial sensor ICs.

For a long time (many decades), I've called the R+C filtering of VDD the &quot;local battery&quot;, which ensures the local fast charges are all locally_provided; this prevents irksome ground loops.
Here is link to design_of_ground_planes
Should I really divide the ground plane into analog and digital parts?