Designing transistor logic gates
Where did you get that diagram? (you copied an NMOS gate circuit??) It has some problems....


You mention that the first (leftmost) ground should not be there (because it would short Q2's input to ground, but what should be there is a resistor to ground that leaks the base cuirrent of Q3 to ground without switching Q2 on. With ~ 0.6mA base current I would take a 330 Ohm.
(not a fundamental problem, but now you could probably leave out R2, because Q2's base can take the maximum current the input stage can supply.)
The output has Q3 as pull-down, but it is shorted to power. You need a resistor between out and power. Its value is a balance between fan-out (the number of inputs that the output can drive) and power consumption. To simplify the disign, I would take 330 Ohm.


Now you have an RTL type gate, but with a somewhat uncommon input stage. The (old) designs I have seen use teh two input transistors in parallel, with or without an output trasistor.