Clock domain cross and metastablilty problem
Yes, if the metastable state occurs, it is equally likely to resolve to either 0 or 1. This really doesn't matter in the grand scheme of things, however.

Let's say that the asynchronous input makes a transition from 0 to 1, and this transition happens close enough to a clock edge to cause the first FF to go metastable.


If the metastable state resolves to 1, then the second FF will also go to 1 one clock later, and all is good.
If the metastable resolves to 0, the second FF will remain at 0 for one more clock cycle, but on that next clock cycle, the first FF will go to 1 (no metastability possible) and the second FF will go to 1 one clock after that.


In other words, the only effect of the metastability resolving the "wrong" way is to simply delay the transition at the output of the second FF by one clock. This is the same result that you'd get if the original input signal had been just a little bit later (with respect to the clock) to begin with. It has no effect on the operation of the system overall.

The point is, the second FF has a tremendously reduced probability of going metastable itself &mdash; this can only happen if the first FF goes metastable in the first place AND that metastability happens to resolve itself within a tight window around the next clock edge.