Absolute minimum delay required to process data across shift registers
Looking at the Ti datasheet of the 74HC595, the 500ns is the maximum rise time at which your input signals should rise. It basically says 'don't clock this too slowly' which your controller will not do.  

The 74HC595 themselves can run at >25 MHz (All for 4.5V).
Your critical path will be the serial clock SCK going through the 74HC138. But if, in your software you set the 'SER' signal first and after that the clock you will be safe.

Some notes:

Why is the 74HC138 in there? You generate two signals from it but use up 5 CPU pins to control it.

Have you thought of using a small FPGA?