74193 stops working after compilation on another PC (QUARTUS)
The difference between the two is not that compilation broke your design, but rather the first case is an RTL simulation (i.e. everything is ideal), whereas the second case is a Gate-Level simulation, which factors in the propagation delays estimated for the actual real implementation.

Your circuit design works in the ideal case, however once you factor in real propagation delays within the circuit, race conditions and logic hazards become a major problem. The same would be the case if you were to build the circuit from actual physical logic ICs.

When designing for FPGA, and even if building out of logic ICs, you need to be very careful in how you design your circuitry - especially when those designs start including asynchronous reset paths. Mixing asynchronous and synchronous logic within the same data path can cause you major headaches like you are seeing.