Quartus/SignalTap: Is there an equivalent to Xilinx's ICON, VIO, ILA IP-Cores in Altera's SignalTap?
Yes, for most of them there are.

You can instance SignalTap into your design adding a .STP file to your project OR instancing and configuring the explicit SignalTap block in your design.

For the first option (the simplest and non intrusive), just use the graphical interface provided
For the second one follow the instruction in this help topic.
http://quartushelp.altera.com/14.0/mergedProjects/program/ela/ela_pro_setup.htm
Look for the item "To use the IP Catalog to create a SignalTap II instance"

In addition to SignalTap (logic analyzer) you can find other debugging useful IP, like Memory Contents Editor, to allow you edit and read the memory blocks instanced in your design while your circuit is running.
And there some additional tools to manamge signal integrity on tranceiver capable dies.