Is it possible to use conditional statements to modify parameters at compile time in Verilog?
You can use the conditional operator condition ? true_expression : false_expression as long as everything within the expression is a parameter or literal constant. 

localparam transitionConst = (transitionConst &lt;=  maxLength) ? x + y + z + offset : transistionConst - maxLength;


You can also use functions to define parameters, as long as all the function inputs are parameters or constants as well.