Which SIPO chip is better, 74HC4094 or 74HC595 or something else?
I hadn't looked at the 74HC4094, having always used the 74HC595, but the 74HC4094 looks like it has a couple of interesting differences:


The load signal is level-sensitive, rather than edge sensitive, allowing the device to be used in a "transparent" mode, where bits from the input are immediately shown on the output.
It has a cascading output which triggers on the same clock edge as the input, as well as a cascading output which is delayed by half a clock.  Use of this latter output will greatly improve sample and hold margins when feeding the output of the device into another one; the former may be useful in some situations when feeding a device which is known to receive the clock before the data.
The 74HC4094 does not have the asynchronous clear function of the 74HC595.  There have been times I would have used the 74HC595's asynchronous clear if the load signal was level-sensitive (so that asserting clear and load simultaneously would clear the outputs), and times I would have used a synchronous clear (wire the cascade output to synchronous clear and synchronous load signals, and reduce communications requirement to two wires), but I don't think the signal will be missed on the 74HC4094.