What's the reason for power-down sequencing in a SOC? Can you damage it in some way?
The same problems as during power on apply to powering off.

A common problem is that in ICs, transistors are placed so that their junctions are reverse biased by the supply rails. If a higher voltage supply turns on slower or shuts of faster than a lower voltage one, that assumption may no longer be true, large currents can flow through the (now) forward biased junctions, destroying them.