Calculate cutoff frequency of a digital IIR filter
With you needing an anti-alias filter for 1/100 of the bandwidth, I'd say that both your single-pole IIR (exponentially weighted moving average) and actual moving averages are out of the question; you'd need suppression in 99% of your band sufficiently high enough to mitigate aliases.

Simultaneously, you need a filter with a steep transition between pass- and stopband, relative to the original Nyquist rate.

Neither filter approaches will achieve such a steepness.

Higher-order CICs can achieve sufficient suppression through offering a very steep (potentiated sinc) impulse response, and their use in decimators (like your 100-fold decimation) is very popular due to the elegant nature of the math: you can drag the decimation stage between the integrators and the differentiators, like

-1 kHz--&gt;(+)------·---&gt;[↓100]---·------(+)---10 Hz-&gt;
          ^       |             |       ^
          --[z⁻¹]--             --[z⁻ⁿ]--


As you can see: extremely low component effort!

In all honesty, though: You're building a massively decimating filter, at a sample rate that is ridiculously low for FPGAs, aiming for a sampling rate that's even lower.

Do yourself a favor. Calculate a proper 1/100-band FIR filter. At these rates, you really need but a single multiplier that you use for all coefficients. And even then it doesn't need to be a fast one. That way, you gain significantly more freedom in designing your filter response.

Found it: You should really read this article of Richard Lyons, whom you can also work with over on our Signal Processing StackExchange sister site.