Analyzing Xilinx Design Summary?
From the virtex-5 product family overview: 



No of Slices: 11,200

No of 36k Block RAM: 148

Each Virtex-5 FPGA slice contains four 6-input LUTs and four flip-flops. So total no. of LUTs &amp; Flipflops is 44,800. 

In Virtex-5 libraries guide for HDL Design, you can see the structures of different LUTs. For example here is 6-input, 2-output LUT:



You can use it as either 5-input LUT or 6-input LUT. O5 output is used when only LUT5 is used, otherwise O6 output is used. So if your HDL combinational logic has 5 or less than 5 inputs, O5 output will be used. Try to use small datatypes (Less than 6bit) in you HDL design to reduces no of LUTs used in your datapath. This is one of techniques used for timing closure in FPGA.

You can also see the 36k True Dual Port Programmable BlockRam  diagram in the same HDL guide.

Slice Registers are probably referring to the 4 flipflops in each slice. The values in the "Device Utilization Summary" reports how many different elements are used in your design. I suggest to read above pdfs &amp; other Virtex-5 guides for more details of different terminologies used in the report.