How does this passive resistor network separate HS and LP signals from MIPI inputs?
HS up to 1.5Gbps and LP upto 10Mbps
HS 340mV into 50Ohms per side using CML current source to get +-340mV
LP uses 1.4V driver unipolar reduced to 0, 340mV by impedance divider as a CM signal while not causing HS imbalance of more than =≈5% differential offset.
So LP is a common mode voltage driver at &lt;10M speed and HS is CML differential up to 1.5G all matched impedances.
2 wire analog phones work ≈this way using differential  current one way and differential voltage the other thru PHY hybrid XFMR.
Any questions?