JK flip flop VHDL code
Process senstivity list should contain only "clock", since its synchronous FF.
end behavoral is enough. No need of end architecture
your first end if should be at the end.
Your Q is delayed by one cycle, so use variable. You missed QB as well.
Try to use elsif to improve readability, instead of else and using if inside else. 
Intend your code always.


useful link