Unconnected port warning on reset port in asynchronous register in Vivado
At the hardware level, nothing is wrong and you can safely ignore those warnings.

Assigning "UUUUUUUU" does nothing in hardware, so it gives the synthesis tool explicit permission to save hardware by doing the cheapest thing possible. As a result, two input signals rst and end_data are unused. 

Then the synth tool gives warnings - because unused inputs, like all dead code, is a code smell and points to a possible design problem. So read them - understand them and if they are "false positives" (the reset value doesn't matter) ignore them.

But your comments do reveal a design problem - you wish to distinguish between invalid and valid inputs, which is not generally possible in hardware - a FF can hold '0' or '1' and that's it - no other choices (except 'Z' which is restricted to I/O pins, and perhaps, other roles in ASICs)

So at the hardware level' what you want to do is impossible : even if you could assign "UUUUUUUU" it would be represented by a pattern of '0' and '1' and thus your equality comparator would return True for some specific valid data.

So your choices are limited to finding an in-band value that the register will never be assigned (like -1 for a positive number, as is often seen in C programming), or adding a "Valid" bit as Jeff suggests.



At the conceptual level, the metavalues 'X' 'U' and so on are to allow you to find and correct these problems in simulation. 

Therefore by the time you synthesise your design, they have all been resolved, and synthesis has permission to optimise the design and save hardware resources where it can. So, what synth does with these values is essentially undefined, and that is OK.