Can an FPGA PLL lose lock if it is supplied with a stable input clock signal?
The PLL has a state machine (logic) as part of tracking phase and frequency.

If you trash the state transitions, or trash your "VCO" dividers, or trash your phase interpreter logic, you may lose lock.

So your team needs to understand the timing, to ensure any metastable operation is robustly handled.

Also you need to keeo the VDD clean and free of dropouts.

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If your "VCO" is not part of the FPGA (I assume this is an all-digital-PLL), then there is risk of some offchip transient event momentarily upsetting the VCO phase and frequency continuity.