Interfacing multiple SPI data input into EBI memory for access in verilog
Depends on what your space and other resource requirements are. I've written state machines and logic to generate the control signals for a SPI block because the design did not have power or space required for an on board microcontroller block (even a small one). The data was then stored in a FIFO memory block and recalled when needed elsewhere in the design by a microprocessor for data gathering. 

If you can change the SPI HDL and GPIO's, you could parallel all the slave data in lines and read the data in parallel, which might make it easier to store data as it will not have to be processed serially. 

Anyway, some ideas. Whatever you do, you have to look at your requirements and decide what gets the job done best, and what is the best use of resources. The resource of your time (the time it takes to write, simulate and test HDL), the resources of the FPGA (size and speed constraints), and power and timing requirements.