PCIe fails on "polling compliance" state
I've recently completed a PCIe design using Altera's PCIe block. I was using the soft core on a Cyclone IV E part. I ended up in the same state and a number of things contributed:


not enough filtering on the PHY power supplies
a timing error caused by one of the SSTL-2-II signal traces being significantly longer than the others
The PCIe trace pair lengths being far too long


In the end the filtering was easy to fix, as was adjusting the SDC file so that P&amp;R could adjust the I/O delays. The nasty part was correcting the excessively long (and out of spec, I think it worked out to something like 11 inches!) PCIe trace pairs. Once this was done through a re-route the core came up immediately and performed flawlessly.

The PHY we were using also seemed to be transmitting "quietly" -- the vendor claimed they were transmitting as per spec but analysis and measurement with some very expensive rental equipment could not verify their claim. If they were transmitting to spec we should have been able to get away with the long PCIe traces.