Design this memory with D Flip-Flops
Alright I give it a shot. Without pretty pictures. What is my thought process here?

The D-Flip-Flop without bells and whistles, clear and preset, tri-state output, etc. it has data in (D), clock in (C), and data out (Q), as you show in your hand writing.

In your sketch, you have all your data inputs listen to the same bus and you use your address logic to route the clock edge to only the flip-flop that you care about. OK.

Now you say you want 4 one bit registers, that means you need 4 of these D-flip-flops. Firstly that isn't clear from your limited photo of your sketch. 

You need a pair of address lines. And you want 2 read or write ports. They are restricted in that you can select 2 addresses and they output immediately, and then you can optionally select the write-enable to also input to them on the rising clock edge. So you need 2 pairs of address lines and two read/write mode selectors (EDIT: not read/write mode selector, I meant write enable line). I think that's about what that diagram above your sketch shows.

Now on your sketch, even if I assume it just shows 2 of the 4 flip-flops you need, you do  seem to be missing the address lines need to be used not only to route not only the clock edge, but also the data output. So you have two 4:1 line selectors also. Since you are using a 2:4 line decoder chip, I am assuming you could use a 4:1 line selector. Say, a 74LS153 dual 4-line to 1-line data selector/multiplexer, non-inverting outputs, should do the trick. 

As your 2-to-4 decoder I can find the 74LS155, dual 2-line to 4-line decoder/demultiplexer, which has inverting outputs. That isn't totally unreasonable as most write-enable lines I have seen were active low, so we may stay in this idea.

Now you lose me completely where you have all those fine output lines from the 2-to-4 decoder join together into a fat AND-gate. That makes no sense! This way you're making sure that the AND gate will always result in ZERO since a decoder by definition has only one output enabled. But wait, OK, maybe you are actually seeing the data sheet and you know the decoders all work in this weird active low logic. But still, one line will always be low, so your AND gate will never open for the clock to come through.

If you actually get to use a 2-to-4 decoder like the 74LS155, what you'll do is you deal with active low, so do your write enable also as active low to stay with the customary use and to not get too confused with negation everywhere. This means you gate exactly one line from the line decoder to each flip flop, and you allow the positive clock edge to pass if the selector line and it's related write enable line is low. So, L - L is the only thing that makes your clock pass, AND the clock with a gate that turns only L * L = H. That's like a NOR gate, isn't it? Yes, it is. 

So your CLK to flip-flop is (clock AND (write_enable_n NOR decoded_address_n)). 

As for your output, you route the decoded address line (remember active low) to somehow gate the flip-flop output. Above I said you could use a line selector, like the 74LS153. You could also do it by combining the 4 outputs with three-state buffers, so that only one flip flop's output will ever actually drive the output high or low. Having a flip flop with a three-state output built in wouldn't be a bad idea, then you don't need anything. But without that you will route your output to a 3-state buffer which then you need to control with that output enable line. Let's say that one is an active high (as it usually is). So your decoded address line would need to be inverted to drive your 3-state buffer to open. Simple enough. The 74LS126 is a handy set of 4 tri-state buffers, of which you would then need 2, one for each output port. 

Since you have 2 ports, it comes in handy that both the 74LS155 line decoder and the 74LS153 selector are dual packages, so you already have one for each pair of address lines. If you use the tri-state buffers (74LS126) you need two of them, as each can handle 4 lines and you need two for selectively routing each of the 4 bits to the 2 output ports. 

However, I would guess your assignment doesn't want you to select existing TTL packages with the line decoders and selectors, but instead draw it out in gates. Probably you guys aren't working hands-on with TTL but rather with FPGA these days. 

Anyway, drawing it out in individual gates is now just designing a 2-to-4 decoder and whatever line selector or three-state buffer, you built from whatever your atomic components are you need to use.