Handling inferred clocks during RTL Synthesis
You have added an FPGA tag, so I will answer from an FPGA perspective. If you are creating an ASIC or using some other flow, a different answer might apply.

1. Why is there an inferred clock on pstate[1] in this design?

offset_val &lt;= ctr1 when pstate = s2;

This line does not describe anything happening when pstate is not s2. This constitutes a gated latch. In any FPGA I have used, this will be implemented by activating a 'latch' mode in a normal flip flop, using the 'clock' pin as the 'gate'. Your gate signal at that point is using clock resource, but ultimately it is derived from another 'data' signal, as opposed to a 'real' clock.

2. Is it alright to have such statements in the design? Does the presence of inferred clocks indicate a bad design practice?

Latches in general should be avoided unless there is a strong reason to have them, because they usually provide poor timing performance, and can more easily result in hazards and races in the design. One example where latches must be used would be if some external interface had to use a level sensitive input of some kind. In your case it looks like it should be quite easy to avoid a latch.

3. If it not ok to have inferred clocks in the design, how can I fix this by coding the logic differently?

Use a clocked process that contains the assignment. This will infer a flip-flop for offset_val. You would have to simulate your design or probe it on board to make sure that the function is equivalent in your particular case, but the basic philosophy in the FPGA should be that any assignment other than simple a &lt;= b and c; or some_vec &lt;= smaller_vec &amp; another_bit; uses a clocked process. Doing this will give you predictable timing results and make it easier to write constraints. There are exceptions, but this should be the starting point.

4. If it is ok to have inferred clocks, how can I let the tool know of it? What period constrain can I provide for such inferred clocks? How can I determine a meaningful period for such inferred clocks?

For the case of an external interface, the level-sensitive input will have some minimum pulse width, and you can use this to create a period constraint that constitutes the worst possible case of how that signal might toggle. For any internal interfaces, I would work to avoid the latch existing at all, but the same technique might apply. By avoiding latches altogether, you avoid having to think about this sort of problem.



In addition to these, the two-process state machine design shown in your code is not necessary. You can put the whole machine and the state transitions into one clocked process. The resulting process would look very similar to your second process above, with everything wrapped in an if (rising_edge(clk)) then, and every occurence of nstate replaced with pstate. You should be able to find existing answers regarding state machine design either here on EE, or over on Stack Overflow's VHDL tag.