VHDL D-type asynch flip flop
I like to keep shift registers defined as vectors. Doing so helps maintain code in the long run. You'll find that this is only 2 lines longer than what you already had (ie. one line for std_logic_vector declaration, and another line to assign the output).

Try this:

entity dualff is
port (
    clk : in  std_logic;
    clr : in  std_logic;
    d   : in  std_logic;
    q   : out std_logic );
end dualff;
architecture Behavioral of dualff is
    signal dffs : std_logic_vector (1 downto 0) := b"00";
begin
    q &lt;= dffs(1);
    process (clk, clr)
    begin
        if clr = '1' then
            dffs &lt;= "00";
        elsif rising_edge (clk) then
            dffs &lt;= dffs(0) &amp; d;
        end if;
    end process;
end Behavioral;


RTL: