Does pin order matter at all for this RAM?
In this case it seems wholly acceptable to interchange data bits and to interchange address bits. This is not universally the case, as you allude to in your question.

In this case the device is a static RAM - a quick flick through the AS6C1008 datasheet did not indicate any ability to do fast acceses of any sort or any address related timing dependancies. 



General:

Some dynamic memories allow data bursting by latching in a high portion of the address and then sequencing low address bits. This may correspond to published logical row and column structure or to some arcane inner mechnism not obviously apparent externally. In such cases you need to stick to what the data sheet says in order to avoid storage failures.

Some early dynamic memories relied on address sequencing and access timing to achieve memory cell refreshing. You are unlikely to meet many of any of these nowadays.

Some memories (flash, eerom, some other) have lifetimes which are dependent on number of accesses, which may be per access (read or write) or more usually only per write, and may be per memory location or per some subset of memory cells. In the latter case, if you scramble address lines you  may interfere with wear-levelling algorithms. This is only going to be a potential problem with fairly specialist devices and data sheets are liable to be reasonably clear on requirements