stack cache instead of registers
Yes, the entire line of Burroughs mainframe computers starting in 1961 with the B5000  used a stack architecture.

In this architecture, managing the data flow to and from the stack is not actually too much of a bottleneck for performance. A bigger issue is the fact that a "zero address" machine needs a lot more instructions to complete a given task than a one-, two- or three-address machine does. Instruction decoding and the execution pipeline become the primary bottleneck.

When I worked there in the early 1980s, there was an effort to build a CPU that could prefetch relatively large sequences of zero-address instructions and translate them on the fly to three-address operations that would be fed to the execution pipeline. (Think of a Java JIT compiler implemented in hardware.) It got rather complex, especially for the implementation technologies available at the time, and I don't know whether this strategy ultimately succeeded.

In case you're wondering, the "N-address" terminology refers to the number of operands that can be specified in a single instruction. All operations on a stack machine are implicitly to the top one or two locations on the stack, so there are zero operands in the instructions. A machine that has an accumulator that is used for all operations in conjunction with one other register or memory location is a one-address machine. A two-address machine can specify an arbitrary source and destination operand in one instruction, and a three-address machine can specify two source operands and put the result in an independent destination.