What's up with the operating voltages 5 V, 3.3 V, 2.5 V, 1.8 V, etc.?
A lower VDD is required as the gate geometry shrinks. This prevents damage to the CMOS gate oxide and minimizes leakage. When the fabs switched from 0.5um to 0.35um, the thinner gates could only handle potentials up to 3.6V. That led to supplies at 3.3V +/- 10%. With the switch to 0.18um the voltage was reduced further to 1.8V +/- 10%. In the latest processes (e.g. 45nm), the gates are made of high-k dielectrics such as halfnium to reduce leakage.