Multicycle : Is it possible?
When using multicycles, you must be careful that the path is indeed multicycle-safe. In your case, the lack of clock-enable on capture_com_rx_packet_counter would make it "unsafe". It should be possible to force the synthesis tool to use a flip-flop primitive with a clock-en, which would be the first step to multicycle.

However, while multicycle is very useful to relax timings, I would only recommend it if it's your last solution. Is that path really problematic? Does it fail timings? Is every other path significantly faster?

You can also cut the timings with VHDL code. An example which does the addition in 2 cycles (input must be stable 2 cycles, output is only valid on the second cycle):

signal s_lo : unsigned(16 downto 0);
signal s_hi : unsigned(15 downto 0);

process(clk)
begin
    if rising_edge(clk) then
        s_lo &lt;= '0' &amp; a(15 downto 0) + b(15 downto 0);
        s_hi &lt;= a(31 downto 16) + b(31 downto 16) + s_lo(16);
    end if;
end process;

s &lt;= s_hi &amp; s_lo(15 downto 0);