vhdl synthesizable code
I am not going to write the whole code but this may help.

Below is a code snippet which detects rising and falling edges. But it is fully synchronous. Beware that the code assumes input4 is synchronous to Clock.

logic input4_one_cycle_delayed std_logic;
logic input4_rising            std_logic;
logic input4_falling           std_logic;

edges: process(Clock)    
begin
    if rising_edge(Clock) then
       input4_one_cycle_delayed &lt;= input4;
    end if;
end

input4_rising  &lt;=  input4 and not input4_one_cycle_delayed;
input4_falling &lt;=  not input4 and input4_one_cycle_delayed;


I normally write Verilog so there may be some VHDL syntax errors in there. However the  principle should be clear.