Which one is efficient verilog code in this if statement?
In Verilog if-else statements basically infer multiplexers.

In both examples you are inferring two multiplexers chained together. 

The only difference between the two code examples is how the control signals are described. However this may or may not make a difference to the efficiency (see below).

ASIC

Depending on the synthesis tools, and whether they are any good at optimising, the first option may be less efficient. If optimisations are not performed, your first code would infer a 2-input AND gate for A &amp; B and a 3-input AND gate for A &amp; B &amp; C to make the control signals of the Mux. The second code would however infer only a single 2-input AND gate for A &amp; B, with C being used directly as a control signal.

FPGA

For an FPGA the whole thing is moot. Your muxes and gates will all just be lumped into lookup tables anyway. Any output that relies on combinational logic of up to N different inputs will end up in an N bit lookup table (LUT), regardless of the way in which you describe the logic (*). Of course the LUT may be composed of several smaller LUTs based on the structure of the FPGA.

In both cases, the output will depend on exactly the same number of inputs, so will result in exactly the same sized lookup table.



(*) e.g. if you tried to describe a 3-input AND gate, and tried to describe a 2-bit MUX, both rely on 3 inputs, so both would end up using exactly the same resources - a 3-input LUT.



IMHO the second example is a better way of writing the code, simply because its clearer to the reader. Once you start going behavioural in your descriptions, making it easier for a human to read is important.