How can I convert the number of DSP48/BRAM to the number of LUTs and FFs in FGPA
How can I generate decimation filter without DSP48 using FIR Compiler. I would like to generate decimation filter only with CLBs using FIR compiler.


Configure your FIR IP core and/or your synthesis filters to not utilize DSP slices. There's constrains that allow you to configure that.

By the way, I doubt this is a sensible thing to do. You're doing DSP, so use the DSP hardware. Comparing things as if that doesn't exist is unfairly favoring the thing that doesn't use DSP slices.


  Is there any criteria convert the number of DSP48 to the number of LUTs and FFs?


Sure. Implement a multiplier in discrete logic. In fact, your synthesizer will do exactly that when you forbid it to utilize your DSP slizes.

As with everything in FPGAs: there's a tradeoff between speed, amount of resources used and latency. Without defining boundaries for all three, you can't tell how you should be implementing something. You can build a thousands-of-LUTs single-clock multiplier; you can build a much smaller multi-clock-cycle one, or you can build a multi-clock-cycle pipelined one. It all depends on what you define to be appropriate.


  In addition, is there any criteria convert the number of block memory to the number of LUTs or Memory LUTs?


This should be answering itself, but: I'm sure you can model a bit stored in block RAM as an FF.