PN532 (SPI) how to get firmware version
want to share solution...

...being affected by "silicon limitations" (we all know what that means...) It seems that following proposed solution it worked.

This is quote from [community.st.com][1]


  Problem resolved (underlined the workaround). STM32F40x and STM32F41x
  silicon limitations, section 2.4.13:
  
  LSB bit of data or CRC calculation can be corrupted for the
  receiveddata in master mode depending on the timing of the
  feedbackcommunication clock respect to the APB clock (SPI or I2S)
  Description
  
  When the SPI or I2S is configured in master mode (in full duplex or
  receiver mode, readingback the data register or CRC enabled), the data
  received may have the last transacted bitcorrupted if delay of
  internal feedback derived from SCK pin is comparable with APB
  clockperiod. The last bit value is strobed too late into the shift
  register, while its content has beenalready either copied into the
  data register or compared with CRC pattern calculatedinternally. In
  case of data corruption, the bit position in the data register
  contains the value ofthe last bit received during the previous data
  transfer and CRCERR flag is asserted in spiteof all the data being
  received correctly.  
  
  The main factors which can contribute negatively to the delay are
  decreased Vdd level,extreme temperature, high SPI bus capacity load
  and low SCK IO output speed. SPIcommunication speed has no impact.
  
  Workaround  
  
  â€¢ Decrease the APB clock.  
  
  â€¢ Set the IO pad configuration for the SCK pin to be faster.  
  
  â€¢ Ignore the lastly transacted bit value
  
  [1]:
  https://community.st.com/s/question/0D50X00009XkfHYSAZ/possible-hardware-bug-full-duplex-spi-incorrectly-reads-last-bit-of-each-incoming-byte