What amount of noise on Vcc is acceptable?
The only way to know if 1 Vpp is too high is to consult the datasheet.  At the very least, the chip must be specified to operate over the resulting supply voltage range.  For example, if the supply voltage is nominally 3.3 V, then the chip is seeing 2.8 to 3.8 volts.  Is the chip specified to operate over that range?

Even if it is, it may still not be OK.  You may not be seeing all the high frequency components, making the total deviation from nominal higher than it appears.  Also, the dV/dt can cause problems, even if the absolute voltage is always within spec.  dV/dt limitations are often not in the datasheet, so it's best not to push things too far.

That all said, 1 Vpp on a 3.3 or 5 V supply is a lot.  Something is probably not working right if you get that much noise.  Leave the 100 nF cap there, but add a 1 &micro;F or maybe 10 &micro;F ceramic directly across the power and ground pins of the chip.  This is assuming the 100 nF cap is already directly across the pins with as small a loop as reasonably possible.

There is something wrong if there is 60 mVpp at the bench supply, and just a short distance away the same nodes have 1 Vpp on them.  This should not be allowed to happen.  The connection between the bench supply and the chip should be very low impedance at low frequencies, and the decoupling caps should provide low impedance at high frequencies.

It would be useful to know what the frequency of this 1 Vpp noise is.  That would give you hints where it might be coming from, and what can be done about it.

Until you have a good power supply, nothing else matters.  This is the first thing you should address.  Everything else is a waste of time until the supply is clean.