D Flip Flop design using multiplexer
The truth-table for a D-FF is
D Q | Q+1
0 0 | 0
0 1 | 0
1 0 | 1
1 0 | 1
So, your circuit does not work. At least my simulation tells me this



Qn gets high while Q is high also
Qn is not high when Q is low
Q is only high when D and C are high... as soon as C gets low, Q also is low - but it should hold the value


Edit 2: added inverters as suggested in comment


So corrected inverters a second time (sorry it was almost 2 o clock in the night).
I still see Outputs changing when clock is low, and Qn not being the inverse of Q
Still wrong... or?