Starting and stopping of a Mod N Counter for a FSM in Logisim
Gating the clock of a synchronous counter is generally a bad idea. It sometimes results in glitches caused by transitions in your decoding logic getting onto the clock line causing unpredictable behavior.

It is better to multiplex a 3 bit signal onto the input the 3 flip flops making up your 3 bit counter. The multiplexers select is your stop signal one input is the normal count input and the other input is the current state. 

In the design of synchronous logic we do not think in terms of micromanaging the clock or reset  signals, reset is used to set the initial state of the logic at power up. We normally think in terms of controlling the input to, in your case, 3 flip flops. A completed if statement is a multiplexer in RTL in your case your counter input can be described as.

if (initialize=1) then input=5 
  else if (stop =1 ) then input=output
  else input=output-1