System verilog synthesis in Vivado
Vivado Synthesis Guide guide mentions about this issue in page 260:

Targeting SystemVerilog for a Specific File
By default, the Vivado synthesis tool compiles  *.v  files  with the
Verilog 2005  syntax and *.sv  files with the SystemVerilog syntax. To
target SystemVerilog for a specific  *.v  file in the Vivado IDE,
right-click the file, and select  Source  Node  Properties.  In  the
Source  File  Properties  window,  change  the  File  Type to
SystemVerilog, and click  OK.
TCL Command to Set Properties
Alternatively,  you  can  use  the following  Tcl command  in  the
Tcl  Console:


set_property file_type  SystemVerilog [get_files &lt;filename&gt;.v]