Limiting the input current with voltage divider
If your goal is to minimize the current drawn from your signal source, then what you are looking for is a voltage buffer.  

Also, you haven't said, but from the +3.3 V supplies scattered around your schematic, I'll assume your ADC has an input range of 0 to +3.3 V.

For your first case, with input signal between 0 and 5 V at 5 MHz, the best way to minimize the input current of your circuit is to place the buffer amplifier first, and then use a resistor divider to adjust the voltage range.







simulate this circuit &ndash; Schematic created using CircuitLab

How to choose the resistors? If the resistor values are too high, then the current in to the ADC input will change the voltage at the "TO ADC" node, causing an error in the reading. If the resistor values are too low, then the op-amp will have to supply a large current, and its distortion will increase. You'll have to work out the balance between these two issues, given the ADC you've chosen and the accuracy you need.

If you find that even the highest resistor values that work with your ADC are causing a distortion problem with your op-amp, you could add a second buffer stage after the resistor divider.

For your second case, a +/- 36 V signal at 100 Hz, you have a more difficult problem. To use the same circuit from above, you'd need an op-amp running on probably +/- 40 V supplies (because high-voltage op-amps aren't likely to rail-to-rail inputs). Which would probably mean adding +/-40 V supplies to your system.

The simplest way to deal with this, assuming your input signal has near 50% duty cycle, is probably by ac-coupling:







simulate this circuit

So in this case, how do we choose the resistors?

Once again, we need the resistors low enough that the current going to the next stage doesn't disturb the voltage divider. If you're using the OPA365, that input current is on the order of 10 pA. Given the values I drew above, this current will cause about 1 uV change in the voltage at voltage divider node. Since this is well below the 100 uV offset voltage of the OPA365, it won't be a noticeable error contributor in your circuit.

And again, you need to increase the resistors to minimize the load on the source. In this case the input current will be 36 V / 2 MOhm, or about 18 uA. If this is too high for your source, you'll want to scale up the resistor values, or find a way to buffer the source before scaling it.

Another thing to watch out for with these large resistor values is whether our circuit will restrict the bandwidth of the signal too much. Our divider has an equivalent output resistance of about 90 kOhms, and it's feeding an op-amp with about 6 pF input capacitance (again, considering the OPA365). This gives a time constant of 270 ns, or a cut-off frequency of 600 kHz. If this had come out below our signal frequency (100 Hz), we'd need to look in to scaling down the resistor values, or finding an op-amp with lower input capacitance.