Maximum resistor values for transistor inverter (NOT gate)
R2 depends on the leakage of the controller when it is high impedance, as the divider created by them  must surpass Vbe of Q1 (around 500mV). You model the controller as tied to 5V when high-Z, but leakage to ground is what matters in this scenario as leakage to the supply only helps in this situation since it is in parallel with R2. Roughly speaking resistance of R2 must be less than 5x the leakage resistance to ground to achieve this 500mV with a 5V supply.

R1 depends on the leakage of the target as it creates a voltage divider when going high. So it must be less than half of whatever the target leakage to GND is to achieve 3.5V from 5V supply.

Check datasheet for leakage estimation as 500k is probably a bit low. I'd guess it is a few megaohms at least. Below is a link to a live online simulation where you can see current flow and play around with values easily. Finally consider how much you care about a few extra uA's vs how much you care about the thing working 100% of the time.

Falstad simulation.