System Generator: How to make a buffer implementation
Is System Generator a graphic tool? (I use different FPGA vendors so not sure, but most have an equivalent tool where you place blocks, or create new ones from HDL and use them) edit - just checked and it seems to be such a tool for creating DSP designs.  

If I understand correctly then:
If it's a small buffer then you can probably just do it in some "glue" HDL with registers, linking the two System Generator generated blocks. Otherwise use a RAM/FIFO block of some sort that will be available in System Generator.  

The System Generator user manual (e.g. page 15-18) discusses memories and implementing as part of a larger design using an HDL "wrapper".