MIPI RFFE software implementation
I can see two problems:


Your Clock signal seems to have some noise in the first couple of
cycles.
The clock polarity is OK but the clock phase is wrong. The RFEE
clock transition from high to low should be in the middle of the
data bit just like SPI MODE 1. This is what shifts the bits in the
receiver. but because the transition is occurring while the data bit
is changing, the received bit will be unpredictable.


If you are using the hardware SPI try changing the mode to 1.

If you are bitbanging the data follow this steps to build the bitbanging routine:


Set the clock high
Set the data line
Wait half Tbit
Set the clock low
Wait half Tbit
Loop