Generate flip-flops using only combinational logic
The JK you have is a latch, not an edge trigger. It is also missing feedback between Q and qn (your first code is also missing this feedback). Combinational always blocks work based on the sensitivity list. The list for auto-sensitivity from always @* and always_comb` is determined by signals used on the right hand side of an expression and not on the left hand side. 

If you declare the sensitivity list it should work : always @( J,K,clk, Q,qn ), This way the Q and qn will re-trigger the always block.

Another approach is to use case statement:

always_comb
  if (clk)
    Q = Qpre;
  else
    case({J,K})
    2'b10 : Qpre = 1'b1;
    2'b01 : Qpre = 1'b0;
    2'd11 : Qpre = ~Q;
    default : Qpre = Qpre; // no change
    endcase


The problem with using combinational logic for flops is it can have hold-time violations. Verilog an indeterminate simulator. This means the order that an always block is evaluated are not guaranteed. Using the below code as an example. Verilog can execute b_combff before c_combff therefore c will be assigned the value of a. This is because we are using blocking assignments. The simulator could also  run c_combff before b_combff and we will get correct value. Both scenarios are legal. 

dff b_combff(.Q(b), .clk(clk), .D(a);
dff c_combff(.Q(c), .clk(clk), .D(b);


A well placed non-blocking assignment (&lt;=) on Q can help. This will separate the evaluation and update into separate regions of the scheduler. This fixes the the hold-time race condition but does not help with synthesize. 

Modern synthesizers are smart, but the are not brilliant. They look for coding patterns to determine how to convert RTL to equivalent gates. When they see always @ it will make edge sensitive flip-flops. They do well with very simple SR, RS, &amp; D latches. Biond that they try to make combinational logic. When you add your own custom flops the synthesizer the will attempt to match it to logic it already knows, which will most likely result in asynchronous latching logic.

In short, is possible to design flip-flops using combinational logic, but outside of learning it is generally not a good idea.