Why aren’t the magnitude comparators cascaded the “more efficient” way?
Because the comparing inputs can dominate/override the cascaded inputs, not vice versa. That means the MSB which should be dominant during comparison must be compared in the last stage prior to output in order to actually be dominant.

Also, even if the IC was constructed so cascaded inputs override compare inputs, your way is less efficient. It's already more efficient this way. The output stage can act directly on the dominant MSB and can ignore the LSBs if they won't make a difference. Your way, the dominating MSB comparison result must cascade all the way through the LSB comparison ICs to get to the output.

Graphically, it might look like MSB is compared last because it is on the right, but that' just drawn so input to output moves from left to right. In actuality, the numerical bits get fed to all ICs at the same time and the cascade lags behind that. So all numerical bits are being compared at the same time and the MSB comparison can act the quickest since it can ignore the cascading LSB results to get the output out the door.



NXP 74HC85 Datasheet