Enable clock for a state machine?
So this code generates a 200 Hz clock based on a 100 Mhz clock.

We note that: 100 MHz / 500000 = 200 Hz

So, we need to take our 100 Mhz clock, and every 500000 cycles, we would have a full cycle of the 200 Hz clock that we would like to generate. Since we want the high time and low time to be the same, we know that we should oscillate the new clock every 500000 / 2 cycles.

From the perspective of the code, we will use hexadecimal, so it's worth noting that 500000 / 2 == 0x3D090.

architecture foo of blah is
    signal clk_200Hz : std_logic := '0';
    signal counter : unsigned(19 downto 0) := x"00000";
begin

    clkdiv : process (clk_100Mhz)
    begin
        if rising_edge(clk_100Mhz) then
            if counter = x"00000" then
                counter &lt;= X"3D090"
                clk_200Hz &lt;= not clk_200Hz;
            else
                counter &lt;= counter - 1;
            end if;
        end if;
    end process clkdiv;

end architecture;