MKP DC-Link capacitor: Why Upp<0.2*Undc?
DC-Link caps are designed to integrate the massive current pulses from voltage ripple and low Dissipation Factor, DF or it's equivalent ESR*Ipk^2*d.f. converted to RMS or using duty factor , d.f. of a pulse.

Historically capacitors have improved and presently, the figure of merit, that I use is 


T=ESR*C 


to "ballpark" choose an appropriate cap.

100us~3ms Alum. electrolyte, general purpose , small to very large
0.5~10us Alum. electrolyte, ultra low low ESR
50~150ns Plastic, self healing , high voltage , lower values with higher V


This range will improve over time with R&amp;D and nanotube processed surface on foil conductors.

Thus when you know Ic=C*dV/dt , the Vpp ripple has a direct relation to power dissipation 


Pd=I²*ESR


This ripple current without chokes or external resistance becomes inversely related to the ripple voltage but duty cycle also reduces so RMS Pd is constant.


But if ripple voltage is too large then rms power self heating will damage the product and fail well before rated hours at elevated temperatures. ( highly stressed Arrhenius Effects or highly accelerated stress screen or HASS)


When high rms ripple current is expected consider 20% margin below rated spec. of the component.


  Bottom line is one uses large uF Alum caps for low frequency 100Hz and smaller value C plastic caps for SMPS off grid switcher at >=10kHz or step up using PFC when required for>100W in IEC std.