How many clock cycles does a RISC/CISC instruction take to execute?
The practical definitions of RISC and CISC are so muddied and blurred now they are almost meaningless.  Now it is best to think of them as more about "philosophy", in the sense that a CISC architecture has a richer instruction set with more powerful individual instructions (e.g. DIV and the like) while a RISC instruction set is bare bones and fast, and leaves it to the compiler to implement complex operations.  Even purportedly CISC instruction sets (like x86) are translated into internal instructions in both Intel and AMD chips and implemented more like RISC processors.  To answer your questions:


The original academic RISC processors (and I think maybe the very first commercial versions) did indeed execute one instruction per cycle, including fetch and decode.  This was possible because the datapaths were super clean because the operations of each stage were simple and well defined.  (the tradeoff here is only very simple instructions can be implemented this way).  Once it hit the real world things got blurred.  Things like pipelining and superscalar architecture make a simple RISC/CISC dichotomy impossible.
The original RISC chips attempted to execute one instruction per cycle and they could if the data was available in the register file.  Of course if the processor had to go to DRAM it would take a (lot) longer.  RISC is about "attempting" to execute an instruction per cycle.
One instruction cycle is the time it takes between fetches.
In depends enormously on the instruction and the instruction set architecture.  Even in a CISC architecture some instructions could execute very quickly (like a shift left or right for example).  Some executed very slowly (10s of cycles or more).  The VAX architecture (probably the pinnacle of the CISC philosophy) had instructions that were really complex.  Incidentally, a CISC architecture is usually easier to program in assembly than a RISC architecture because it is almost like a high-level language!