Why do we use FIFOs and RAM in an image processing scheme?
The incoming video clock is asynchronous to the FPGA clock. That is why it needs synchronization between video pixel clock domain and FPGA clock domain. And it might make no sense to send video data to DRAM at one byte at a time but many bytes at a time, a FIFO makes perfect sense to transfer data in bursts of few bytes at a time.
The DRAM is required for a frame buffer, because video input and output rates are not synchronized, and even worse, they will have different frame rates. Not to mention deinterlacing. So you need to store a whole incoming frame at say 50 interlaced fields per second, take two fields and deinterlave them into progessive frame at a rate of 25Hz, and then output that frame at 60 Hz for the VGA monitor.