Custom-built NAND SR latch not resetting
The inputs to a NAND RS latch are active low, meaning that they perform the desired function when brought to a logic 0. If you force your R input to 0 while S=1 you will see that Q2' goes high and Q2 goes low. If R=1 and you force S to 0 then Q2' goes low and Q2 goes high.

If both R=1 and S=1 then the latch is in its hold state, and it maintains whatever value it previously had.

Setting R=0 and S=0 simultaneously is an illegal input state. In this state both Q2 and Q2' will be high. The big problem is that if you transition from the illegal state (R=0, S=0) directly to the hold state (R=1, S=1) then the state of the latch is indeterminate, and in the real world you could have metastability.