Some questions about a low frequency reed switch interface circuit
Conceptual Schematic and Timing

The following circuit, and similar, has been posted by me for other purposes. For your case, I didn't need to do much to it.

This is the basic concept, which I'll explain shortly:







simulate this circuit &ndash; Schematic created using CircuitLab

(Keep in mind that I intend on following your datasheet's recommendation at the end of my answer and add a series resistor to the reed switch line. But  for now, I'd like to avoid discussing it and focus on the basic details.)

I like to use a BAV99 for \$D_1\$ and \$D_2\$. Single part, easy to get, cheap. But you can use any diode pair you want, I think. The most important of the two is \$D_2\$, through which charge on \$C_1\$ must go when the circuit resets itself. There is little harm I can see if you were to leave \$D_1\$ off the circuit, though. Still, I think it's a good idea to keep it, if possible.

\$R_4\$ is a pull-down. I'd keep it a lowish value to really help in resetting the circuit quickly. But its value is non-critical, too. So don't sweat the exact value much.

The critical timing parts are \$R_1\$ and \$C_1\$. I've set these for the ballpark of \$30\:\text{ms}\$. But feel free to adjust them to different values. The threshold voltage for \$M_1\$ needs to be low enough that the circuit will work, so you need to search for something in the area of around VTO of about \$2.0-2.5\:\text{V}\$ and as little gate capacitance as possible. The BSS145 might work okay, here. But again, this is just a matter of selecting an NFET with a low VTO and low overall capacitance. It doesn't need to have a super-low on-resistance, either. (It's only going to pull a drain current of about \$1\:\text{mA}\$.)



What Makes it Work

The basic concept is that when the reed closes, it pulls upward on \$C_1\$ and this pulls \$M_1\$'s gate on. Once \$M_1\$ goes on, it pulls base current out of \$Q_1\$ and \$Q_1\$ turns on sourcing current into \$R_4\$ which goes HIGH. There is a timing cycle that starts then, with \$C_1\$ slowly charging up through \$R_1\$. As that happens, this pushes downward on \$M_1\$'s gate and eventually shuts it off -- shutting off \$Q_1\$. At that moment, \$R_4\$ pulls down hard on \$C_1\$ (if the reed switch is open) forcing \$C_1\$ to dump its charge via \$D_2\$ into ground and mostly discharging itself, and sufficiently enough to reset the cycle. (A very slight additional drain of \$C_1\$ then takes place via \$R_1\$ and \$R_4\$ to squeeze out whatever remains.)

In effect, it debounces the reed switch for you. You can adjust the debounce period by adjusting \$C_1\$ and \$R_1\$.

There are simpler methods, but I think an active drive will be worth having.



Final Schematic

The datasheet recommends a series resistor of \$100\:\Omega\$ placed inside the box. I think that recommendation is a good one and that you should give serious consideration to the idea. If you do decide to include it, then the above circuit will still work fine.

I'll represent it in the schematic here below:







simulate this circuit

It's use shouldn't impair the conceptual schematic offered earlier. In fact, it significantly improves it by dramatically limiting the peak current through the reed switch.

So I'd recommend that you definitely include the new resistor, as indicated both in the datasheet and in the newly added schematic above, so as to help preserve the reed switch lifetime. Since this schematic actually uses a capacitor for timing and exposes the switch to the capacitor, it's more than just a good idea, now. You really should take the time to add it.



LTspice Validation Schematic

Here's the text. You will need to snap a copy of it and then save it as an .ASC file for LTspice to read up. I hope I didn't use some part you don't already have available in your LTspice incarnation.

Version 4
SHEET 1 1224 800
WIRE 400 -112 352 -112
WIRE 496 -112 400 -112
WIRE 304 -80 304 -112
WIRE 400 -80 400 -112
WIRE 496 -80 496 -112
WIRE 352 -64 352 -112
WIRE -288 16 -288 -64
WIRE 352 32 352 -16
WIRE 496 32 496 0
WIRE 496 32 352 32
WIRE 400 96 352 96
WIRE 496 96 400 96
WIRE 304 128 304 0
WIRE 400 128 400 96
WIRE 496 128 496 96
WIRE -288 144 -288 96
WIRE 352 144 352 96
WIRE -144 176 -144 112
WIRE 352 240 352 192
WIRE 496 240 496 208
WIRE 496 240 352 240
WIRE 32 256 32 112
WIRE 304 256 304 208
WIRE -144 304 -144 256
WIRE -32 304 -144 304
WIRE -144 352 -144 304
WIRE -288 368 -288 320
WIRE 32 384 32 352
WIRE 304 384 304 336
WIRE 304 384 32 384
WIRE 32 400 32 384
WIRE 304 416 304 384
WIRE 560 416 304 416
WIRE -288 496 -288 432
WIRE -224 496 -288 496
WIRE 32 496 32 464
WIRE 32 496 -224 496
WIRE -288 528 -288 496
WIRE -144 528 -144 432
WIRE 304 544 304 416
WIRE 32 560 32 496
WIRE -224 608 -224 496
WIRE -192 608 -224 608
WIRE -288 624 -288 592
WIRE -144 688 -144 624
WIRE 32 688 32 640
WIRE 304 688 304 624
FLAG -144 688 0
FLAG 32 688 0
FLAG -144 112 Vcc
FLAG 32 112 Vcc
FLAG 304 -112 Vcc
FLAG 304 688 0
FLAG 400 -80 0
FLAG -288 144 0
FLAG -288 -64 Vcc
FLAG -288 320 Vcc
FLAG -288 624 0
FLAG 400 128 0
FLAG 560 416 DEBOUNCED
SYMBOL pnp2 -32 352 M180
SYMATTR InstName Q1
SYMATTR Value 2N3906
SYMBOL res -160 160 R0
SYMATTR InstName R1
SYMATTR Value 33k
SYMBOL res -160 336 R0
SYMATTR InstName R2
SYMATTR Value 2.2k
SYMBOL nmos -192 528 R0
SYMATTR InstName M1
SYMATTR Value BSS145
SYMBOL res 16 544 R0
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL cap 16 400 R0
SYMATTR InstName C1
SYMATTR Value 470n
SYMBOL res 288 528 R0
SYMATTR InstName R4
SYMATTR Value 220
SYMBOL sw 304 -96 M0
SYMATTR InstName S1
SYMATTR Value MS1
SYMBOL voltage 496 16 R180
WINDOW 0 24 104 Left 2
WINDOW 3 -471 7 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 {t/30} 1u 1u {t/60} {t/30})
SYMBOL voltage -288 0 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL sw 304 112 M0
SYMATTR InstName S2
SYMATTR Value MS1
SYMBOL voltage 496 224 R180
WINDOW 0 24 104 Left 2
WINDOW 3 -485 5 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 {t/30} 1u 1u {t*0.7} {t*1.8})
SYMBOL res 288 240 R0
SYMATTR InstName R5
SYMATTR Value 100
SYMBOL diode -272 592 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL diode -272 432 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value 1N4148
TEXT -392 784 Left 2 !.model MS1 SW(Ron=.1 Roff=1000Meg Vt=2 Vh=0 Lser=10n Vser=.01)
TEXT -392 744 Left 2 !.tran {t*4}
TEXT -392 704 Left 2 !.param t={30m}


There are two different switches in series in that schematic. One of them is just a fast pulser, which is used to 'simulate' the bouncing effect of the reed. I'm sure it's not even close to the actual circumstance. But it is good enough, I think, to test the circuit. The other one "gates" this fast pulser, so that bursts of about \$20\:\text{ms}\$ of it passes through to the circuit.

See what you think.

Oh, and here's the model for the ZVN3310A you'd mentioned that I got from Diodes Inc.

.SUBCKT ZVN3310A 3 4 5
M1 3 2 5 5 MOD1   
RG 4 2 356
RL 3 5 1E8
C1 2 5 21.5P
C2 3 2 2.5P 
D1 5 3 DIODE1
.MODEL MOD1 NMOS VTO=1.736 RS=2.147 RD=1.682 IS=1E-15 KP=0.157
+CBD=25.5P PB=1
.MODEL DIODE1 D IS=6.12E-13 RS=.629
.ENDS ZVN3310A


Seems okay. But yes, it does distinctly increase the timing. Easily adjusted back, of course.