Overflow detection and efficiency
The overflow logic is just hard wired; however, the update of the flag is ignored for addu instruction.  The last bit just sets the update condition.

add: 0000 00ss ssst tttt dddd d000 0010 0000 
addu:0000 00ss ssst tttt dddd d000 0010 0001


There's virtually no speed difference between them.  Also, considering that the MIPS is a synchronous processor and you clock at the rate of the slowest instruction, that add in any form will not cause you much speed concerns.