Clock domain crossing timing constraints for Altera
Despite being fairly common in the industry to globally cut all paths between two clock groups, I would strongly advise against this practice as it makes it very hard to spot places where you unintentionally re-sampled a signal between clock domains.

You are better off using a common block for transferring data between domains.  Embed the constraints in the common block, or use wildcards in the paths to constrain every instance of the block in your design.  Make the use of a common synchronisation block part of your coding guidelines.

You can then report all clock-domain crossings and find places where you weren't using a safe transfer mechanism. You can also include automatic checking in your flow and quickly locate any accidental clock crossings in your design.

You will also be able to use your set_max_delay constraint and not have it ignored :)