Enable output for 1 clock-cycle?
If input pulses are guaranteed to have high and low times that are at least a clock cycle long, but may arrive arbitrarily close to a clock edge, pass the input through three consecutive flip-flops, and AND together the non-inverted output of the second with the inverted output of the third.  Note that the output would be delayed by a full clock cycle, but one could be reasonably assured of getting a one-clock-wide pulse even if the pulse arrives near a clock edge in violation of setup/hold requirements.  If the first flop were omitted, the output would arrive a cycle sooner, but glitches might appear on it if an incoming pulse violates setup/hold requirements.







simulate this circuit &ndash; Schematic created using CircuitLab

An alternative approach if high pulses may be arbitrarily short, but will be separated by at least three clock cycles, would be to have a chain of three flops fed not by the pulse input, but by a flop which clocks the inverted output of the third flop's state.







simulate this circuit

Note that in this second version, it's necessary to use an XOR rather than an AND-NOT circuit, since an incoming pulse will effectively toggle the state of the signal being propagated through the flops.  Note also that the second version may malfunction if a pulse is received near the third clock edge following an earlier pulse, due to a setup/hold violation on the first flop.