How to use simple generated clock in Verilog Code Vivado 2015.2
Constraints file is only used to apply various constraints on the design.

But the code which generates 50 MHz clock needs to be written by you.You can use a frequency divide by 2 code

wire clk_50MHz;

always @(posedge clk_100MHz)
clk_50MHz &lt;= ~clk_50MHz;


But to let xilinx know that this clk_50MHz is not a normal signal,you need to let xilinx know that this clk_50MHz is a  generaed clock constraint in xdc/ucf