Why are two transmission used gates to make a D Latch?
This is the simplified view of the transistor level implementation of a positive latch, you have in the figure.




When CLK is high, TG1 is ON, TG2 is OFF. So you will get at output Q, whatever input you have in D. The latch is said to be in transparent mode.
When CLK is low, TG2 is ON, TG1 is OFF. Now, the value of Q (which was there just before the moment clock went low) is fed back, inverted and fed to the next inverter. This value is circulated between the two inverters as long as TG2 is ON, and thus the value of Q remains stored. This is how the latch stores the data when the clock is low. The latch is said to be in opaque mode here.