VHDL Simulation bug (am I losing it??)
You have done a very strange thing: The DUT is generating its own clock!

This means that when both the clock and the data propagate out to the testbench, the data will have already changed before the clock edge is processed, effectively creating the "zero delay" effect you're seeing.

While it's true that real hardware wouldn't behave this way, it doesn't at all surprise me that most if not all simulators would do exactly the same thing with this code.

Try generating the clock (and the reset) in the testbench (the usual scenario) and I think you'll see the expected behavior.

The alternative would be to add a nominal delay to the assignment of the output data bus inside the module

app_rd_data &lt;= std_logic_vector(to_unsigned(addr_array(63),app_rd_data'LENGTH));


in order to correctly model this interface.