VHDL Question: Sequential Execution Within a Process
Not knowing all the details, in principle it is not a bug.  This is a process that occurs whenever there is a falling edge on the associated clock.  You can imagine that all signal reads happen right before the edge, and all the writes happen at the edge.

So having inside a clocked process:

a &lt;= b; -- after the edge, a will have the contents of b
c &lt;= a; -- after the edge, c will have the contents of a (NOT THE CONTENTS OF b).


The order of the above assignments does not matter, and can be represented by the following schematic:







simulate this circuit &ndash; Schematic created using CircuitLab

As you can see in the above schematic, each Flip-Flop has a 'queued' value Dand it becomes the output Q at the clock's edge.  a has b queued, and c has a queued.  So in a single clock, b can't propagate all the way to c (it requires 2 clock cycles).  So specifying the signal 'queuing' in code does not need any particular order.

In your specific example, when ADC_Counter is 13, ADC_temp(7) has ADC_Data queued, and ADC_Reg_1 has ADC_Temp queued. ADC_Reg_1 is not getting corrupted with the new data bit, in the same way that our c is not getting corrupted with b.

Note: This would be different if talking about variables (you'd be using the := operator instead of &lt;=), but your code only contains signals.