What does it mean to "gate the clock"?
To "gate the clock" means put a logic gate in the clock line to switch it on or off. 







simulate this circuit &ndash; Schematic created using CircuitLab

The diagrams above show and AND and OR used to gate the clock. One forces the clock low the other high. 

To prevent clock pulses which are 'too short' either high or low ("runt pulses"), we must make sure that:


The control signal for the AND gate should change only when the clock is low.
The control signal for the OR gate should change only when the clock is high.


Gated clocks are very useful for reducing power in CMOS as the logic stays 'quiet' while the clock is stopped. You will find that modern synthesis tools have special option to insert clock gating automatically. 







simulate this circuit

Above are two circuits which safely generate a gated clock. The circuits rely on the fact that there is as a small delay (clock to Q) for the control signal to come out of the register. Thus the control signal changes at the gate when the clock has a known polarity.