How is something level trigger vs edge triggered?
Consider this schematic:







simulate this circuit &ndash; Schematic created using CircuitLab

The input of the AND gate is either L,H or H,L. Never L,L or H,H. So, the output is always L. Right?

WRONG!


Every gate has a propagation delay. A few nanoseconds.


What happens is the following.


Input is L. The AND sees H,L. The output is L.
Input has a L→H transition. The inverter has a delay. The AND sees H,H. The output is H.
The inverter finally propagated the H on its input. The AND sees L,H. The Output is L.
Input has a H→L transition. The inverter has a delay. The AND sees L,L. The output is L.
The inverter finally propagated the L on its input. The AND sees H,L. The Output is L.


So, this circuit is an edge-detector for the L→H transition. It creates a few nanosecond H pulse during that transition.