Does SRAM need PCB track length/impedance matching
I don't think you have to length-match the traces.

In write mode, the critical timing parameter is from when the last (slowest) address or data line is valid, relative to the WE.

In read mode (OE controlled), the critical timing parameter of from when the last (slowest) address line is valid, relative to the OE.

By putting the meander line lengths in, you're just making all of the address or data bits have the same prop time as the slowest one.

Edit 1:

I would use controlled impedance for all the traces.  This is something most PWB vendor can do as a matter of course, meaning that it doesn't take much effort on their part and doesn't cost you anything.