Clock multiplexor fanout buffer
Whatever solution you find, it will involve at least 12 2:1 multiplexers. These could be integrated in an IC or each an individual IC.

With a quick search, the closest match I found is the NB4L7210 2x10 crosspoint switch:



This only gets you 10 outputs. If you have a couple of pairs of outputs that you know will always connect to the same input, you could use a couple of 1:2 fan-out buffers to expand this to 12. Or you could use two of these 2x10 switches (having 8 unused outputs), or you could add a 2x2 crosspoint from a similar family to get the two additional outputs.

At your frequencies (&lt; 200 MHz), for the connection from the PLL to multiple switches or multiplexers, PECL signals can be easily fanned out on your pcb using a multidrop configuration:







simulate this circuit &ndash; Schematic created using CircuitLab

(LV)PECL outputs can also be directly interfaced to ac-coupled CML inputs using DC biasing at the source:







simulate this circuit

The R1 and R2 values are chosen to draw about 5 mA output current when the PECL driver is producing a low output (so the value will depend on your VCC voltage). The resistor values will be higher than 50 ohms. This is an "far-end termination" scheme. You're counting on the 50 ohm termination in the CML receiver to eliminate reflections.