Digital circuit for finding minimum vector index
Why would you need an adder? Each layer determines the value of one of the bits in the final index; you just need to concatenate those bits together.

Here's an example with 4 inputs that shows how the layers generate the index bits.







simulate this circuit &ndash; Schematic created using CircuitLab

If any layer has an odd number of inputs, just pass that value through as another output, and force the index bit associated with that output to 0.

So, for 27 inputs:


Layer 0 contains 13 8-bit comparators and produces 14 9-bit results.
Layer 1 has 7 comparators and produces 7 10-bit results.
Layer 2 produces 4 11-bit results.
Layer 3 produces 2 12-bit results.
Layer 4 produces the final 13-bit result: 8-bit minimum value and its 5-bit index.


If you feed the index bits into the comparators as additional LSBs along with the data values, then you automatically get the lowest-numbered index in the case of duplicates.



Since I am intrigued by your problem, here is some Verilog code you might find useful. I'll leave it to you to assemble this into the full tree structure and test the results.

/* minimum_value_layer.v */

/* This module implements one layer of a tree structure that finds the minimum
 * value in a vector along with its index.
 */

module minimum_value_layer #(
  /* The number of bits in each vector data value.
   */
  parameter VALUE_BITS = 8,

  /* The number of outputs for this layer.
   */
  parameter N_OUTPUTS = 1,

  /* The layer number in the tree, starting with layer 0.
   */
  parameter LAYER_NUMBER = 0
) (
  /* The input bus contains 2*N_OUTPUTS fields, each comprising VALUE_BITS
   * worth of input data, and LAYER_NUMBER bits of an index value from the
   * previous layer.
   *
   * If the previous layer produced an odd number of fields, set the final
   * input field of this layer to all-ones.
   */
  input [(VALUE_BITS+LAYER_NUMBER)*N_OUTPUTS*2-1:0] data_in,

  /* The output bus contains N_OUTPUTS fields, each comprising VALUE_BITS
   * worth of input data, and LAYER_NUMBER+1 bits of an index value to the
   * next layer.
   */
  output [(VALUE_BITS+LAYER_NUMBER+1)*N_OUTPUTS-1:0] data_out

  /* In both cases, the index bits are the LSBs of each input or output field.
   * This makes sure that if the minimum data value appears more than once in
   * the input vector, the smallest index is produced.
   */
);
  /* This is the width of an input field. An output field contains one more bit.
   */
  localparam WIDTH = VALUE_BITS + LAYER_NUMBER;
  genvar i;
  generate
    for (i=0; i&lt;N_OUTPUTS; i=i+1) begin
      wire [WIDTH-1:0] a = data_in[WIDTH*((i+1)*2-1)-1:WIDTH*i*2];
      wire [WIDTH-1:0] b = data_in[WIDTH*(i+1)*2-1:WIDTH*(i*2+1)];
      assign data_out[(WIDTH+1)*(i+1)-1:(WIDTH+1)*(i)] = a &gt; b
        ? {b[WIDTH-1:WIDTH-VALUE_BITS], 1'b1, b[WIDTH-VALUE_BITS-1:0]}
        : {a[WIDTH-1:WIDTH-VALUE_BITS], 1'b0, a[WIDTH-VALUE_BITS-1:0]};
    end
  endgenerate

endmodule


Note that the final assign statement doesn't work for layer 0. The simplest thing to do is probably to create a separate module for layer 0 that uses this instead:

      assign data_out[(WIDTH+1)*(i+1)-1:(WIDTH+1)*(i)] = a &gt; b
        ? {b, 1'b1}
        : {a, 1'b0};