Clock circuit layout techniques
At 500 kHz, you have a 2 us clock period, and you don't have to worry about set-up times.

Assuming you're using a 5 V power, supply the part you referred to has a hold time of 40 ns (min) and a propagation delay of ... well they don't specify a minimum but they imply a minimum of about 93 ns (for no capacitive load). That gives a 50 ns slack between the time the second shift register clocks in its input and the time that the first shift register output changes, invalidating the second shift register input. 

If you just keep your clock lines reasonably short, you should have no problem with this design. 

If you do have problems, then go back and figure out how to minimize the clock line impedance (keep a ground wire parallel to each clock wire), and finally if that doesn't work, start worrying about how to route the clock --- counter-propagating relative to the direction of data flow is probably best, but really with 50 ns slack it shouldn't matter at all.

EDIT

Wouter is absolutely right (in a comment to his own answer) that you must evaluate the "minimum propagation delay against the maximum required data hold time". And that nothing in the data sheet guarantees the circuit will work.

However, we should note also the data sheet gives a (typical) formula for the propagation delay as a function of load capacitance: 93 ns + (0.55 ns/pF)CL (for the worst case: t_PLH at 5 V Vdd). That means 


You'd need have 0 load capacitance to (typically) get a prop delay as low as 93 ns. This number is only typical so you might see slightly lower numbers occasionally. But most likely you wouldn't see the number drop by half.
If it doesn't work you can add a small capacitor to the output to increase the delay. You might not get exactly 0.55 ps per pF of adjustment, but you won't simply get no adjustment at all. 


I'm assuming, since you're using point-to-point wiring, this is a one-off circuit and a manual adjustment is a reasonable choice. For a mass-produced product you would want a much more sure solution than this.

EDIT 2


Somewhere you mentioned using buffers (plural) to drive the clock inputs of your shift registers. Be aware that the propagation delay differences between two buffers will cause much more timing difference between the clocks at your different shift registers than just about anything to do with layout.

If you care about clocking your registers simultaneously, I strongly recommend to use one buffer to drive all of them. But do be sure your buffer is able to drive the combined capacitive load of all the chips it's driving.
Working at 500 kHz and a circuit that's 5" in its longest dimension, transmission effects like stubs and shunts will be utterly undetectable. This circuit can be designed entirely satisfactorily considering the interconnect wires as lumped R L C elements (mostly C).

If you do something so crazy (like run the wire around the room before getting it back to its destination) that transmission line impedance matters, you have a problem because your CMOS outputs are not designed to drive transmission lines. For the love of Sweet Baby Ralph, don't overdesign what doesn't have to be overdesigned.
EMC. Again at 500 kHz and 5" circuit diameter, it's very unlikely to have any problem. The easiest way to cause a problem here is to overdesign your buffer chips so that your signals have faster rise/fall times than they need, in which case you could have an emissions problem. If you just stick to nice slow clock edges (but not too slow -- mind the max recommended slew rate spec Tony pointed out) you'll be good.