How to route a LVDS clock from FPGA input to output?
You can't properly describe an LVDS receiver or transmitter in VHDL. LVDS interfaces have electrical requirements that typically cannot be met by just using plain digital input and output pins. Your FPGA needs to have dedicated input and output macrocells for those functions and you would just instantiate them. Exactly how that is done depends on the exact FPGA and toolset you are using. Within the FPGA, there is just one signal that would come from the LVDS receiver and one signal that would go to the LVDS transmitter.