Can someone tell me what this datasheet is trying to tell me?
N bits of data are  sent starting on the rising clock edge of BCK which occurs 1 clock cycle after the change of LRCK level (= yellow circle). ie there is a 1 x BCK cycle needed to deal with the prior data block before new clocking will start.
 N bits of data are sent MSB first.
 After N bits have been sent the data is latched into the IC by changing LRCK state on a BCK falling edge. The delay between the clocking in of the last data bit by BCK and the latching of the data word by LRCK changing is not specified in this diagram except that  it is at least a BCK half cycle (= blue circle).

A look at fig 1 shows more detail of timings.
 Data and LRCk can change together and BCLK occurs Tsu1 (= setup time) after data and LRCK have changed = 10 ns min.
 Data must be held after BCLK for time = Th1 ( = time hold 1 ) = 10 ns minimum.