BCD adder not seeing output of 9's complementer in verilog
My guess is that you haven't declared F in your instantiation, and as such the synthesis tool is implicitly creating it. Implicit nets can either end up the correct size, or default to a 1-bit wire depending on the synthesis tool.

You should always create all wires and registers explicitly. Additionally using explicit (name-based) port assignments rather than implicit (position-based) is a preferred method to avoid potential issues if you change something down the line.

BCDto9Compl  B9C(B, F);


Becomes:

wire [3:0] B;
wire [3:0] F;
BCDto9Compl  B9C(.A(B), .N(F));


I would also try to use more descriptive naming for nets and registers where possible.