Preventing Verilog module from being optimised away
You can chain your inverters into a huge shift register, then e.g. tie its ultimate output to a pin. This should do the job while being vendor independent. You shouldn't have to instantiate every module manually, it can be done in a compact way using a generate statement, which I believe even XST understands (although I haven't tried it). See e.g. this forum thread for an example.