MT9M001 to FPGA input timing
The half period is not 10.416 ns at worst case. Since the minimum clock duty cycle is 45%, the half period should be lower than 9.374 ns (20.833*0.45). If we consider clock rise/fall time too, 9 ns for min(t_LVS)+max(t_PLH) makes sense.

In case LINE_VALID is captured by a negedge-triggered flip-flop, the bottleneck is min(t_LVS). It can be constrained as below. LINE_VALID rises 2 ns before PIXCLK falls.

set_input_delay -max -2 -clock cam_pixclk_virt -clock_fall \
    -rise [get_ports LINE_VALID]


In addition, LINE_VALID falls 13 ns (t_PLL) after PIXCLK rises.

set_input_delay -max 13 -clock cam_pixclk_virt \
    -fall [get_ports LINE_VALID]


Actually these constraints will not prevent the line lengths from getting messed up. We don't know min(t_PLL), so LINE_VALID has a possibility to fall near the negedge of PIXCLK and it may get metastable. This issue should be handled functionally.

One solution would be using posedge of PIXCLK instead of negedge. If DATA is constrained enough for minimum input delay (it's -1 in your constraints), all signals will be safe to capture at posedge.