Why is the SR Flip flop edge enabled
The only time when SR latches are edge-sensitive is the release of SR input contention.
When both Set and Reset are active then both outputs Q &amp; Q* are asserted &quot;1&quot;.
Then after the 1st input {S,R} edge is removed from the active state, only the corresponding output {S=&gt;Q, R=&gt;Q!} will change.
A clock enabled SR Latch is a MISNOMER if called a Flip Flop as it not a  Flip Flop {D,T or JK}  Also this would cause an unstable output if both S=R=active when Clock enable goes low.

Conclusion:  Youtube video is wrong.