Is the following 8085-based design I/O mapped or memory mapped?
It's I/O mapped. That's really the only thing it could be, with IO/M driving A2 of the decoder.
The piece of information you're missing is that

When 8085 executes IN or OUT instruction, it places device address (port number) on the demultiplexed low order address bus as well as the high order address bus.

from here.
So, this is a perfectly legitimate way to decode I/O addresses.