How is it possible that the reverse transfer capacitance of this FET is so low?
\$C_{rss}\$ is not measured by putting a capacitance meter between gate and drain, and leaving the source open.

It is inferred from the ramping behaviour, which is largely controlled by the Miller capacitance, the gate current needed to charge up the \$C_{rss}\$ capacitor, when the drain is slewing in voltage.

This is equivalent to making a three-terminal capacitance measurement across gate and drain, with a guard terminal on the source. This is capable of measuring all three capacitors in that diagram independently, even for the very different values that are shown.