DDR3 length-matching between signal groups
The minimum length of the DQ lines does not matter because you will just change how you terminate your lines. Depending on how many sockets you have will change the termination load.  You need impedance matched boards for this reason.  I haven't seen the more recent development guidelines, but board layouts are pretty much given to you.  

The control groups are longer due to "cross talk", and this is why you have the WR_DATA_DELAY value in the control registers.  You make the control lines as long as you need to, and then you add some time for the setup.