Sigma Delta ADC for "quasi-DC" signals
DC inputs to sigma-delta modulators naturally produce idle tones because the equivalent DC input can not be resolved to a standard +1, -1 pattern.

For example a 2nd order sigma-delta with a 1 bit quantiser (+1,-1 i.e \$\Delta\$=2) with a DC input of \$\dfrac{1}{256}\$ shows the output sequence repeating every 1024 cycles.

Empirically, the idle tones for a second order sigma-delta have been found to occur at frequencies as follows (where \$|A_{dc}|\$ is the dc input level magnitude): $$f_0=\dfrac{nf_s|A_{dc}|}{2\Delta}$$

In addition to tones for DC inputs; 3rd order modulators and higher can produce idle tones that appear to occur at random, even for dynamic, inputs.

My experience on working with sigma-deltas is that LC/idle tone generation is treated extensivley in the literature. For an authoritative treatment of LC and dithering, and plenty or references (86 relevant ref's), it's worth reading "Quantization errors and dithering in ΔΣ Modulators", S. Norsworthy; Ch3 of Delta-Sigma Data Converters:Theory, Design, and Simulation 

I should also add that discussing this many years ago with a very experienced designer (Bob Adams), the only reliable method to determine the LC / idle tone problems (without actually building it), is to simulate; making sure to include all non-linearities, esp. in the Op-amps and to run the sim for as long as is practicable for your simulation hardware.