Miller integrator ramp generator?
In the first circuit you can assume the voltage at the base is (roughly) fixed and ignore base current, so use KCL to sum the currents at the base, and we get (Vcc - Vbe)/Rb2 = C * d/dt (Vc).
In reality the current gain is finite, and Vbe changes with collector current etc. so that equation is only an approximation. Higher values of Rc mean that the time to reset is longer but less base current is devoted to pulling current through Rc.



simulate this circuit &ndash; Schematic created using CircuitLab

This might be a circuit that you could use to split nanoseconds (for example to avoid having an excessively high clock frequency yet maintain high resolution in a time counter). You could use a transistor with GHz ft in place of Q1 (all designators refer to original schematic).
To get a ramp time ~8ms, about 1000x longer than my example, you could use RB2 = Rc = 80K and C1 = 100nF.