TTL input ouput logic
That is a defined Margin for transient ringing, and standards are based on load current for recommended layouts with decoupling on each IC. 

The actual TTL threshold is two diode drops or 1.5V input and output depends on logic family drive current for a fanout of 10.  Fast forward 40 yrs to 74HCTxx and we have the same in/out threshold as TTL was but with rail to rail output.

If you can read schematics, it is clear how 3 TTL familiies 74, 74LS and 74S each with different speeds and output R current limits are designed differently to achieve the same voltage specs.

Remember that unless it has hysteresis like Schmitt Trigger inputs each logic device is a linear gain and behaviour during transition within these limits which are subject pn junction thermal offsets and potential ringing on transition.  These input levels are meant to be also what is TTL compatible, even if design is using CMOS with T in the prefix, like 74HCTxxx



Ringing is inevitable when prop. delay in trace length exceeds rise time due to impedance mismatch.