sequence detector in verilog
Your regs are defined wrong.

reg presentState ;
reg nextState ;


should be

reg [1:0] presentState ;
reg [1:0] nextState ;


.

By default, regs only have 1 bit so only states a and b can ever be reached.

Also, you should do your testbench a bit differently.  Try

initial
begin
@(posedge clk);
@(posedge clk);     sequence &lt;= 1'b1 ; 
@(posedge clk);     sequence &lt;= 1'b0 ; 
@(posedge clk);     sequence &lt;= 1'b0 ; 
@(posedge clk);     sequence &lt;= 1'b1 ; 
@(posedge clk);     sequence &lt;= 1'b1 ; 
@(posedge clk);     sequence &lt;= 1'b0 ; 
@(posedge clk);     sequence &lt;= 1'b1 ; 
@(posedge clk);     sequence &lt;= 1'b0 ; 
@(posedge clk);     sequence &lt;= 1'b1 ; 

$finish;

end


instead.

With those couple of changes, I am getting a pulse on the 'tick' output when I run this in Icarus Verilog.