Practical ESD protection without latchup
Do you know how long a pulse will trigger latchup?

Depends on the layout of the silicon around the ESD structure.

Latchup typically requires a bipolar-snapback, or a 4-layer-diode SCR behavior.
The bandwidth of these structures depends on vertical or horizontal feedback, thus the "time to latchup" is not predictable.

ICs are tested for latchup, prior to getting permission to proceed to high volumn production.

Clamping diodes will add capacitance, and slow down the signals. Are some series resistors not acceptable? 10pF and 100 ohms is 1 nanosecond risetime.