Can anyone help me to understand what these capacitors do in this design?
U2a's output feeds back to its input through the opto coupler.  There are very high resistance values of 1M and 4.7M ohm with capacitors in parallel.  This indicates to me that these are for timing and is either for a one-shot or oscillator.  So when U2a input is low, the output is high which turns on NPN U4 which provides power to the opto-coupler input.  The opto output turns on and drives U2a input high so U2a output goes low and NPN U4 turns off. When U2a output is low the capacitors discharge through the resistors, U2a input goes low and its output goes high, etc.  U10 seems to be a reset as it kills power to the Quad NAND gate.  It is a very strange circuit.

Thanks for the info about the switch.  When the circuit powers up C11 is discharged and the MOSFET is off.  When the switch is closed, C11 is charged and the MOSFET turns on. After releasing the switch, C11 discharges through R24. When voltage falls below the threshold of U2a the MOSFET turns off.  If you press the switch, turn off power and power up, there is still some charge on C11.  To ensure the MOSFET is off at every power up the reset circuit should discharge C11.  You could put a diode from C11 to the collector of U10.