What is the difference between \$V_{CC}\$, \$V_{DD}\$, \$V_{EE}\$, \$V_{SS}\$
Back in the pleistoscene (1960s or earlier), logic was implemented with bipolar transistors.  Even more specifically, they were NPN because for some reasons I'm not going to get into, NPN were faster.  Back then it made sense to someone that the positive supply voltage would be called Vcc where the "c" stands for collector.  Sometimes (but less commonly) the negative supply was called Vee where "e" stands for emitter.

When FET logic came about, the same kind of naming was used, but now the positive supply was Vdd (drain) and the negative Vss (source).  With CMOS this makes no sense, but it persists anyway.  Note that the "C" in CMOS stands for "complementary".  That means both N and P channel devices are used in about equal numbers.  A CMOS inverter is just a P channel and a N channel MOSFET in its simplest form.  With roughly equal numbers of N and P channel devices, drains aren't more likely to be positive than sources, and vice versa.  However, the Vdd and Vss names have stuck for historical reasons.  Technically Vcc/Vee is for bipolar and Vdd/Vss for FETs, but in practise today Vcc and Vdd mean the same, and Vee and Vss mean the same.