Self-clocking driver / transceiver
Self clocking serial protocols exist in a thousand variations everywhere magnetic recording to primitive ethernet communication, telephony to industrial and SCADA communication. These protocols and their designs have existed for over 40 yrs in my use as well as others.

There are many implementations depending on the bit rate, and expected BER, SNR.

The simplest encoders use 1T,2T transition intervals where 2T = is the 1/f,  baud rate and have been defined as Bi-Phase or Manchester codes for Mark, Space and Invert define the toggle on centre bit transitions or Bi-Φ{M,S,I}. Early Hard Disk drives and present day Floppies conserved bandwidth using MFM which used 2T,3T. This expanded to Run-Length Limited (RLL) codes used in ethernet and many other serial comm. links which stretch the interval between clock transitions.

Once you choose a bit protocol, for clock and data sync, you must choose a frame sync, byte sync and bit orientation and message protocol , of which there are thousands , so why reinvent the wheel?



Encoding uses the Clock and Data into an XOR gate for Mark (1) or Space (0) ( from early telegraph terms) to use a normal or inverted clock. Depending on the frame length and number of 0's, 1's or transitions, one chooses the best approach.

Simple Decoding uses a clock recover with a pulse edge created from every edge with XOR gate delay of &lt;5%T and then a 1shot of 3/4T to sample the data value. Sophisticated Rx discriminators will integrate the entire bit energy over 1T interval.

Filtering is essential to avoid group delay in the signal band which causes bit shift and Intersymbol Interference.  Critical Rx use Raised Cosine filter, while non-critical Rx use LPF 5xf approx.  Differential signalling is better for CM noise immunity when signal are low compared to EMI.

There are many implementations freely available in HDL, AVR and programmable logic as well as discrete "old technology" one shots and XOR gates. Filters may be analog but some use more sophisticated digital filtering to minimize ISI and maximize SNR to get highest Bit Error Rate (BER), which as we know from Shannon's Law is directly related to SNR.

Volumes have been written on this subject decades ago , so it you seek, ye shall find.

Remote Controllers at low f use a pulse stretch or delay or duration modulation for 1's &amp; 0's which compromises SNR/BER ratio but can work in a low noise environment.

Don't forget to include error detection, (Parity, or Hamming Code or CRC, or ECC ) and Clock loss of sync detect. Then you need frame sync detect, byte sync clock Error Detect logic etc.

Although not cheap or well stocked, this uses a 16x or 32x clock up to 1Mbps https://www.digikey.com/products/en/integrated-circuits-ics/specialized-ics/686?k=manchester&amp;k=&amp;pkeyword=manchester&amp;v=20&amp;FV=ffe002ae&amp;mnonly=0&amp;ColumnSort=0&amp;page=1&amp;quantity=0&amp;ptm=0&amp;fid=0&amp;pageSize=25

> Is this to decode CANBUS ISO 11898 signals?

If so then look at SCAN921226H Receiver chip $10 with 8bit parallel out and timing signals.