Hardware test of FPGA, thousands of combinations?
When done in simulation, this type of testing would be called "directed testing".  In other words...

If I put in data A, I expect result B.

If I out in data C, I expect result D.

etc...

(where all of the sets of data (A, C, ...) and results (B, D, ...) have been determined beforehand.

Normally one would try to find a way to eliminate the human (that's reading and checking the result on the monitor) from the loop - partly because humans are less reliable than computers, and partly for speed reasons.

However, the "constrained random testing" mentioned by others is generally the way to go if possible.  In this, you generate randomised input, work out what the result should be for that input (using an independent model of the design), and check that the result from the FPGA matches what you expected.  You will generally get much better coverage this way than by directed testing (although directed testing can still be useful for "hello world"-type bringup tests and for hitting specific corner cases.

For constrained random testing, you really need an automated mechanism for checking the result.