Two different 3-AND gates: correct implementation?
The problem here is that you're misunderstanding (or not having the basic understanding) of how MOSFETs work, in particular the \$V_{GS}\$.

On an N-channel MOSFET the gate voltage has to rise a certain amount above the source pin.  On a P-channel it has to fall a certain amount below the source pin.

In your schematic the N-channel's source is connected to \$V_{CC}\$ and the P-channel's to GND.  If the threshold is, say, 1.2V (a reasonable logic level threshold), then the input logic HIGH would have to be at least 1.2V above \$V_{CC}\$ and the logic LOW would have to be below -1.2V.

That, as you can see, just isn't practical.