Clock Implementation Design Warning on Spartan 3E
Because you are using the CoreGenerator wizard, most of the low level stuff can be selected as part of the wizard meaning you don't need to instantiate them manually.

For the outputs, as you have selected auto, you don't need to add a BUFG. Otherwise the DCM will probably instantiate a BUFG for the output which then has to feed your BUFG (i.e. two in a row). Two global clock buffers shouldn't be placed in a row, firstly because there is no need to, and secondly because it means the signal has to leave the global clock network it is on from the first BUFG to get to the input of the second BUFG, hence your warning.

You should also be able to select that an IBUFG be used in the DCM wizard for the input, which means again, you need not instantiate it manually.

From the comments you also mention a warning about CLK0_OUT being unused. You have connected this output to a wire, and I can only assume that you are not then connecting it anywhere. CLK0 is used for feedback as you say, but according to the Xilinx App Note XAPP462 (pg10) you don't need feedback if using only the CLKFX output port, which in your case is true.


  "No feedback. Allowed if using only the CLKFX or CLKFX180 outputs."