VHDL : Can New Operators be Defined?
The problem is operator precedence : allowing adding genuinely new operators like Ralph the Wonder Llama would require some means to allocate a precedence level for them.
So, VHDL simply restricts you to the predefined set of operators. You can overload existing ones, (and they retain their original precedence) but you can't extend the set.
I have only used one language that allowed you to define new operators : it solved the operator precedence problem by having only one level of precedence!
Thus 1 + 2 * 3 = 9 : if you wanted the conventional semantics you enforced it with parentheses : 1 + (2 * 3) = 7.
Too freaky for VHDL!