STM32F7 Discovery LTDC unit - changing system clock
Probably the problem is related to insufficient SDRAM memory bandwidth. Changing system clock to 120 MHz causes SDRAM controller to work at 60MHz. That may not be enough for ltdc to fetch data from frame buffer especially if double layering is enabled. I had similar issue after changing TFT display to higher resolution one. At 25MHz pixel clock, memory bandwidth requirement is roughly 100MB/s per layer. With double layers enabled it is twice that. SDRAM bandwidth at 60MHz and 16bit bus is less than 120MB/s. Try disabling second layer in ltdc although even then bandwidth is barely enough.