FPGA, accessing data in RAM
Two things:


there're Altera documents on embedded RAM describing how you access the RAM - for read and write; in your image processing circuit you will need state machine which would track address needed to be read, and waited for specific time to capture data outputted by the RAM;
it seems that you are currently hard-coding the data into the FPGA RAM (and RAM will be initialized with this data image after FPGA configuration). If you will develop your applications further when image can be loaded "outside" of the FPGA, I recommend you considering using 2-port RAM - one port is used for loading image (and connected to one state machine), and another port is used for processing the image (and connected to another state machine).