Code of an FPGA program
There's an easy reduction based on reading your truth table. 

    G &lt;= Car and (Z_A or Z_B);


I noticed when typing your truth table in as a constant to show a method of checking your code using VHDL.

For your design (sans superfluous parentheses):

library ieee;
use ieee.std_logic_1164.all;

entity parking_sys is
    port (
        Z_A:    in  std_logic;
        Z_B:    in  std_logic;
        Car:    in  std_logic;
        G:      out std_logic
    );
end entity parking_sys;

architecture arch_parking of parking_sys is
begin
    G &lt;= '0' when Car = '0' and Z_A = '0' else
         '0' when Car = '0' and Z_A = '1' else
         Z_B when Car = '1' and Z_A = '0' else
         '1' when Car = '1' and Z_A = '1';
end architecture arch_parking;


A simple testbench:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity parking_sys_tb is
end entity;

architecture foo of parking_sys_tb is
    signal Z_A:    std_logic;
    signal Z_B:    std_logic;
    signal Car:    std_logic;
    signal G:      std_logic;

    type table is array (0 to 7) of std_logic;
    constant G_table: table  := ( -- OUT      Car ZoneA ZoneB
                                     '0', --  '0'  '0'   '0'
                                     '0', --  '0'  '0'   '1'
                                     '0', --  '0'  '1'   '0'
                                     '0', --  '0'  '1'   '1'
                                     '0', --  '1'  '0'   '0'
                                     '1', --  '1'  '0'   '1'
                                     '1', --  '1'  '1'   '0'
                                     '1'  --  '1'  '1'   '1'
                                 );
    signal CAB:         std_logic_vector (2 downto 0);
    signal table_index: integer range 0 to 7;
    signal g_tab:       std_logic;
    signal g_express:   std_logic;
begin

DUT:
    entity work.parking_sys
        port map (
            Z_A =&gt; Z_A,
            Z_B =&gt; Z_B,
            Car =&gt; Car,
            G =&gt; G
        );

STIMULUS:
    process
    begin
        wait for 1 ns;
        for i in G_table'range loop
            CAB &lt;= std_logic_vector (to_unsigned(i,3));
            table_index &lt;= i;
            wait for 1 ns;
        end loop;
        wait;
    end process;

    Car &lt;= CAB(2);
    Z_A &lt;= CAB(1);
    Z_B &lt;= CAB(0);
    g_tab &lt;= g_table(table_index);
    g_express &lt;= G and (Z_A or Z_B);

CHECK:        -- check parking_sys asgainst G_table
    process
    begin
        wait for 1.1 ns;
        for i in G_table'range loop
            assert G = g_tab
            report "G /= g_tab G = " &amp; std_logic'image(G) &amp;
                   " g_table(table_index) = " &amp; std_logic'image(g_tab)
            severity ERROR;
            wait for 1 ns;
        end loop;
        wait;
    end process;

end architecture;


And it would tell us if the G output doesn't match the g table.

You can verify the test will report an error by injecting an error. I set one of the '0's in the constant g_table to a 'X' to demonstrate:



And got an assertion:


  ghdl -r parking_sys_tb --wave=parking_sys_tb.ghw
  parking_sys.vhdl:81:13:@7100ps:(assertion error): G /= g_tab G = '1' g_table(table_index) = 'X'  


Putting that 'X' to it's proper '1':



reports no assertions.

(I threw in the expression shown at the top of the answer)

Anyway the point was that you can use VHDL to validate the signal assignment to G.