FPGA Frequency divider with linear regulation
At the moment, you are considering using a preloaded counter. This means that each clock cycle you get a fixed increment, in a variable accumulator length that you control, hence the frequency is reciprocal to your control value.

If instead you use a controllable variable increment in a fixed accumulator length, your frequency will be linearly dependent on the control value.

This is how a DDS works. A fixed length accumulator, typically a power of 2, for instance an 18 bit accumulator that counts up to 2^18 (250k-ish long) is incremented each clock cycle odf the system clock. In pigHDL, you would write

int count [17 downto 0];
process(on sys_clock rising):
_  count &lt;= count+freq;
_  output := count[17];

This may, or may not, give you what you need.  The MSB of the counter will give you the output, but unless freq is an exact power of 2, the output cycles will not be exactly the same length, they will vary by one count.

The average output frequency = freq * fs / accumulator length.

You can get increased resolution for the frequency by increasing the length of accumulator and frequency word, to the right.

There is no way to remove this one cycle jitter, if you are going to use the clock as a digital source. Bear in mind that for an FPGA, it is bad form to take the MSB output and use it as the clock line to other elements. Much better to turn it into a one cycle ClockEnable, and use that to condition the clock into downstream elements.

If it's for an external source, you can take the top several bits of the accumulator into a DAC, filter the waveform, and use a comparator, this will reduce the jitter considerably.