Effects of restricting most significant bits
So i have calculated the settling time for the capacitor C in an RC
  circuit.


The settling time is infinity so you don't really need to do any calculations - you just need to understand that a capacitor will never perfectly charge to the full value on a simple RC circuit: -


(source: gsu.edu)  

However, for each time constant (R*C) it will get closer by 63%\$^1\$ so, in the first RC time period the cap will attain 63% of the value of the input voltage. At the end of the 2nd RC time period, the gap will close by another 63% and the cap will attain a voltage of 86% of the input voltage.

Hint - You have to work how much of an ONLY error 6 bits gives you and how much that represents in RC time periods.



\$^1\$ the 63% comes from \$1-e^{-1}\$