Data transfer from Cortex M1 to AHB slaves
(note: I'm addressing the general case of a moderately advanced processor interacting with FPGA fabric, rather than the details of this specific core in this vendor technology)

If I understand correctly, you want the slave to access array elements in true parallel fashion, ie, not just bypassing the processor core and using DMA to access them sequentially.

Clearly a conventional sequential access memory cannot support access at greater than it's actual physical width times number of ports (ie, if you had a 64 bit memory, and it was dual port, conceptually you might be able to arrange for parallel access to 4 32 bit elements.  If your memory is FPGA block rams, it's possible you could set things up to have a very wide access width on the 2nd port side and get all 10 values at once this way)

If constrained to more common "memory", what you could do instead is utilize memory mapped IO to map a series of "hardware" (as in LUT) registers into the processor's memory space, and have them also directly feeding your peripheral in parallel.  With some careful coding you can set up the program to use this as a storage location - though it may take additional work to get it integrated in a way that's as fast as access to main memory, and you will need to make sure it is both declared volatile and that any caching does not apply.

You might also want to think about how often the program needs to update these values - do you want to have working copies in ordinary memory and programmatically copy to the memory mapped IO at certain times?  Or do you want to use the memory mapped IO as working variable storage?