ADC sampling problem using FPGA
The problem is that SignalTap is not applying the correct reconstruction algorithm when displaying your waveform. Instead of using a brick-wall low-pass interpolation filter, it's simply using a zero-order hold, which turns each sample into a horizontal line segment.

The sample points themselves really are proper samples of your 440 kHz sinewave. You can prove this to yourself by working it out on paper: draw several cycles of a sinewave that has a period of 2.27 &micro;s, and then show where samples taken at 0.8 &micro;s intervals would fall. Draw a horizontal line from each sample to where the next sample is taken, and you should end up with something that looks very much like what SignalTap is showing you.