How to calculate latency of a circuit?
\$t_{pcq}\$ is the clock to Q propagation delay of a flip-flop. That is the amount of time to propagate the value at D to its Q, after a rising edge clock edge has appeared. Known as simply propagation delay or clock to Q delay.
\$t_{ccq}\$ is the amount of time needed for an initial change in output Q, due to the input D, after a rising edge clock edge has appeared. Known as contamination delay.
\$t_{cd} \$ and \$t_{pd} \$ are same things. But the terms used for combinational gates.


So \$t_{pcq}\$ = sum of \$t_{ccq}\$ and the amount of time for the output Q to become stable and valid, since the initial change occured. Same for \$ t_{pd} \$ and \$t_{cd}\$.
Suppose a flip-flop A launches the data and flip-flop B captures it.

For no setup violation in the flip-flop to flip-flop path,
$$ t_{pcq(A)} + t_{pd} + t_{setup(B)} &lt; T_{clk} + t_{skew} $$

For no hold violation in the flip-flop to flip-flop path,
$$ t_{ccq(A)} + t_{cd} &gt; t_{hold(B)} + t_{skew}  $$


In your circuit, skew is taken zero.
To check for hold violation, consider the shortest path. It is from Q through AND and OR:
Like:

To check for setup violation, consider the longest path.

Now from the above expressions, I think the answer is self-explanatory.