What is the setup/hold time of the RMII receive interface of the TI DP83630 phy chip?
From the RXD line on the drawing, data goes invalid (grey) an undefined time after RXCLK, and becomes valid at T2.27.2 between 2 and 14 ns after CLK.
Thus there is no explicit spec on hold time; but it cannot reasonably change BEFORE the clock, so take hold time as 0.
Then setup time is simply the clock period minus the maximum data valid time, or T2.27.1 - max( T2.27.2)