What is the worst-case PSRR of an LDO?
Here is a LDO internal schematic from this article. It doesn't matter whether the pass device is a BJT or a FET, the mechanisms will be similar.




PSRR is defined as the AC transfer function Vout/Vin for small variations of Vin. It is, of course, frequency-dependent, and it also depends on dropout voltage and current.
Dropout is Vin-Vout.


When dropout is high enough, the pass transistor works well (in linear mode) and acts as a voltage-controlled current source, which helps to improve PSRR, as the current going through the transistor only depends on Vin due to second-order effects like Early effect or its FET equivalent. (You asked for a LDO, in an oldskool regulator where the pass transistor is an emitter/source follower, things are different).

However, as dropout voltage gets lower, the pass device gets squeezed between Vin and Vout, and will begin to operate in ohmic mode (for a FET) or in quasi-saturation (for a BJT).  Its transconductance will lower drastically. The increased capacitance will further degrade AC performance and increase gate drive current requirements.

At lower dropout voltage still, a PMOS becomes a simple resistor, and a BJT saturates. Its transconductance becomes zero, as it no longer responds to gate drive. The pass transistor is basically useless, and so is the error amp which at this moment is simply clipping, its output stuck to its limit. Regulators do clip, just like any opamp. 

The LDO's control loop (error amp and pass device) adjusts the pass transistor's drive voltage to control the output voltage. More open loop gain results in more feedback around the loop, and thus more correction and better PSRR (along with lower output impedance and overall better transient responds). In fact, PSRR is proportional to open loop gain, and the important thing to note is that open loop gain is also proportional to the transconductance of the pass device.

The operation modes cases above correspond to very different transconductance values for the pass device, from maximum (transistor operating in linear mode) to low (FET in controlled resistor mode) to useless (FET is just its own RdsON). 

Thus, PSRR degrades as dropout voltage gets lower. The worst case occurs just as the regulator's error amp clips and it loses regulation.

This also applies to most dynamic characteristics of the regulator: output impedance and transient response are dependent on the control loop gain, so they will also degrade when the pass transistor doesn't have enough dropout to work properly. This may also influence stability.

The dropout voltage when this transition occurs depends on current (higher current require larger dropout).

Additionally, the pass device has some parallel capacitance which increases as dropout gets lower (this is a characteristic of silicon capacitors) so HF PSRR will also suffer a bit at low dropouts. This isn't very important, but I'll mention in passing that larger transistors have larger capacitance, thus a 1A LDO will have more input-to-output capacitance than a 100mA LDO, for example.

More details and nice graphs in this article.

If you want realy worst-case, there may even be some corner cases where a regulator actually amplifies input ripple. For example, if it becomes unstable and oscillates.