system verilog 3d array ,cant insert data , what am I doing wrong?
After some time of debugging and simulation I can say that you must move result initialization into the conv2d module:

module conv2d (
    input clk,
    input logic [7:0] img[3:0][3:0],
    input logic [7:0] kernel[2:0][2:0],
    output logic [7:0] result [4:0][4:0]
    );//#(parameter img_size=16,kernel_size=4)()

int i,j;

initial begin
    for(int i=0;i&lt;5;i++) begin
        for(int j=0;j&lt;5;j++) begin
            result[i][j]=8'b0;
        end
    end
end

always_ff @(posedge clk) begin
    for(i=0;i&lt;5;i++) begin
        for(j=0;j&lt;5;j++) begin
            for(int k=0;k&lt;3;k++) begin
                for(int l=0;l&lt;3;l++) begin
                    if ((i-k &gt; -1)&amp;&amp;(j-l&gt;-1)&amp;&amp;(i-k &lt; 3)&amp;&amp;(j-l &lt; 3))begin
                        result[i][j] &lt;= result[i][j] + kernel[i-k][j-l]*img[k][l];
                    end
                end
            end
        end
    end
end


I actually wonder how you were able simulating your original code because my ModelSim just gives the error written by continuous and procedural assignments on the result (as you try initializing it in test and then modify in conv2d).