How output signals connect when they are from different chips and banks
I can't find a datasheet for a 2012 memory, but I would expect it to have one or more Enable or Read inputs, and tri-state outputs.  

If the outputs are not enabled, they would be in a high impedance state - the memory chip would not be driving the outputs either high or low.  This would permit the outputs of several chips to be connected in parallel.  Only one chip at a time would have its outputs enabled, so there would be no need for a selector to choose which chip to read.  

You would, however, need an address decoder (like a 74LS138) driven by the upper address lines to select which memory chip will have its outputs enabled.