Verilog BitSet Circuit
You can simplify your code greatly by not trying to shoe-horn everything into procedural blocks.

Think about how you would implement this with actual logic components.
You'd have a decoder and 4 multiplexers. 

You can represent that in Verilog with just 4 assignments along the lines of

assign y[0] = (index == 2'b00) ? value : x[0];


As for the errors in your code, I suspect they come from assigning to y in a procedural block when y was not declared as a reg.

Also, your code has a functionality error, because it doesn't implement the requirement "Every other bit in y should match the corresponding bit in x."