Verilog assigning wire by iterating over array
For a mutlibit wire the reduction operator &amp; can be used:

wire [row-1:0] ready;
wire allready = &amp;ready;


However this will not work with unpacked arrays (multi-dimensions).

One solution is to create a loop to index the dimensions ANDing the values with the result so far. This could be achieved with some thing along the lines of:

output reg allready; 

always @* begin
  allready=1'b1;
  for (int i =0; i&lt;col; i++) begin
    allready = allready &amp; (&amp;ready[i]) ;
  end 
end