Cascade shift registers driven by single-cycle microcontroller
Be aware that the 595 used in this way has a problem: The daisy chain output changes at the same clock edge as the input of the next chip samples. A chip that is really designed for this kind of use (IIRC there is one in the CD series) has a delayed daisy chain output.

You can mitigate this problem by:


delaying the daisy chain output data a tiny bit (RC)
applying the clock in reverse: wire it first to the last chip in the chain


I don't understand why you are using that 4538. If you just want to always have the last (shifting!) data on the outputs, you can just wire SCK and SLK together. You will get some ghosting, depending on your update/idle ratio.