Voltage Doubler design parameters
I don't know anything about the zener-noise portion of your circuit, but having used voltage multipliers, I can offer some experience.

The point is to fully charge the capacitors, and then reverse the polarity as soon as they are charged. So you would size the capacitors based on your voltage and switching frequency (necessary, if you use 60Hz line frequency), OR select your switching frequency based on your voltage and the size of the capacitors (your best bet, since PWM is an MCU). You can watch the capacitors charge on a scope while you tweak the frequency, to optimize performance.

A square wave charges faster than a sine wave, because the charge voltage stays at its peak. Assuming a 50% duty cycle, the current that your doubler will deliver will be less than half of what the PWM pin can provide (because it's half-wave).

However, I don't think that your circuit is configured correctly (yet). I can see caps charging when PWM is high, but nothing when it is low (I'm assuming PWM swings between Vcc and GND). Normally, a doubler's input would swing both positive and negative, and C4 would then charge to the opposite polarity when PWM is negative. That charge would then be pumped into the next capacitor stage (C1).

A solution would be to remove the ground from the circuit, and instead drive that node with PWM/ (an inverted form of PWM). Of course, then "sense" is only valid when PWM is high and PWM/ is low. 

BobU has the best fix: tie the anode of D3 to +5v.

In the discussion to follow, I'm ignoring the diode drops. However, when operating at such low voltages the diode drops would have a significant effect on the final voltage. Schottky diodes would be appropriate. 

Regarding the capacitor size, there is a relationship between the cap size and the switching frequency. The GPIO pin needs to charge the first capacitor, and we'll assume the the charging current is constant, at the maximum that the pin can source and sink. So the energy in the capacitor will increase linearly. If you wait until it is fully charged before switching polarities (and dump that charge into the next stage), you will get maximum voltage (real "doubling", ignoring diode drop). The available current comes from the GPIO pin, but will stop flowing once the capacitor is full. If you switch polarities before the cap is full, you won't get the maximum available voltage. If you switch later, then you won't get the maximum available current.

An estimate of the available current would be:

[(GPIO max source current) + (GPIO max sink current)] / 2

That would assume a 50% duty-cycle. If the source and sink current are very different, it would be worthwhile to adjust the duty-cycle to balance them.

Here is a handy formula:

1 mA constant current increases the voltage on a 1 microfarad capacitor by 1 volt in 1 millisecond.

Since you have .02 uF caps and 5 volts, then 1 mA will charge the cap in 100 microseconds. That would equate to a 5 kHz PWM frequency. Your frequency will probably need to be faster, as your GPIO pin probably provides more than 1 mA. If you double your cap size, you would halve your frequency (double your charge time).

The actual charge current from the GPIO pin won't be specified with any accuracy, so you may need to optimize dynamically. Since you have a "sense" pin, one approach would be to start the switching frequency too high, and watch the voltage rise as you bring down the frequency. You would then stop decreasing the frequency once you sense your desired voltage.