misunderstanding of a Computer Architecture
The timing of the "Second ALU Input" depends on three things:


the delay through the sign extender to the "1" input of the mux
the delay through the control logic to the select input of the mux
the worst-case propagation delay through the mux from either the "1" or select inputs


Yes, the labeling on the timing diagram is a bit unclear, but this is all they're saying. Either the path through the control logic or the path through the sign extender will be the long path that determines the final settling time for the second ALU input.

In static timing analysis, you need to take the worst case combination, and they seem to be implying that the worst case is the path through the control logic.