How power dissipation in a transistor is less when signal is present?
For the BJT in Common-Emitter configuration the power dissipation in the BJT is always equal to:

$$P_D = I_C*V_{CE}+I_B*V_{V_{BE}} \approx I_C*V_{CE} $$ 

In Saturation when the BJT is fully-ON the \$V_{CE}\$ reach the lowest value and the collector current reach the maximum value. But overall the power dissipation is small. We have the same situation when BJT approaches cut-off. 
Hence the maximum power dissipation must lay somewhere between saturation and cut-off region in the active region.

Let us exam this circuit: 







simulate this circuit &ndash; Schematic created using CircuitLab

And let us plot Ic vs Vce and the power dissipation in the BJT



As you can see the worst case scenario is when:

\$ V_{CE} = \frac{Vcc}{2} \$ and \$ I_C = \frac{I_{Cmax}}{2}\$ 

Where \$ I_{Cmax} = \frac{Vcc}{R_L}\$

So finally we can find:

$$P_{Dmax} = \frac{Vcc}{2}*\frac{\frac{Vcc}{2}}{R_L} = \frac{Vcc^2}{4R_L} = \frac{20V^2}{4*500\Omega} = \frac{400}{2000} = 0.2W $$