Verilog assign result of module
As the other answers say, your problem is declaring x and out as register type. 

When you assign to something in an assign statement, or by connecting it to an output port of a module instance, you need to declare it as a wire instead of a reg.

I'd also add that your out variable is redundant. You can use one variable to connect to the output of one module and the input of the other:

   wire [1:0] x;

   moduleA mA(.in(SW), .out(x));
   moduleA mB(.in(x), .out(LED));


Saves you declaring and keeping track of an extra variable and an extra assign statement.