register allocation on iterative cycles
I don't have enough reputation to comment yet, so I am posting another answer.
Is there an end to the process?  I mean you incrementally pick off and process bits from 1 to 8 (I assume).
When you get to 8, what happens on the next clock cycle, start over?
Here is an example, showing only F2, doing what I think you are trying to do (although I am not sure what should happen after reaching the 8th iteration.)  It is possible, I am sure, to write this more elegantly.
always @(posedge Clk or posedge Reset) begin
    if(Reset) begin
        iterator &lt;= 1'b0;
        A        &lt;= 8'b00000000;
        B        &lt;= 8'b00000000; 
    end
    else begin
        case (iterator)
        0: F2 &lt;= (Bplusone[0]   &lt;&lt; 2) - 9'd1;
        1: F2 &lt;= (Bplusone[1:0] &lt;&lt; 2) - 9'd1;
        2: F2 &lt;= (Bplusone[2:0] &lt;&lt; 2) - 9'd1;
        3: F2 &lt;= (Bplusone[3:0] &lt;&lt; 2) - 9'd1;
        4: F2 &lt;= (Bplusone[4:0] &lt;&lt; 2) - 9'd1;
        5: F2 &lt;= (Bplusone[5:0] &lt;&lt; 2) - 9'd1;
        6: F2 &lt;= (Bplusone[6:0] &lt;&lt; 2) - 9'd1;
        7: F2 &lt;= (Bplusone[7:0] &lt;&lt; 2) - 9'd1;
        endcase

        if (iterator &gt;= 7) iterator &lt;= 0;  // Reset iterator after 8th iteration
        else               iterator &lt;= iterator + 1;    
    end