VHDL: value isn't assigned immediately
Looking at the following code:

process(clockDivided)
begin
    opcode &lt;= data(15 downto 12);
    regC &lt;= data(11 downto 8);
    regA &lt;= data(7 downto 4);
    regB &lt;= data(3 downto 0);
    if rising_edge(clockDivided) then
        --
    end if;
end process;


The process sensitivity list only has clockDivided present. When data changes as part of the ROM being read, the process is not run; only when the next event on clockDivided occurs does this happen, so your opcode won't change until that point either. This is what causes your delay.

The easiest thing is to move the concurrent assignments like opcode &lt;= data(15 downto 12); outside of the process. you could equally add data to the sensitivity list, but there is really no need for those statements to be in the process in the first place.



Additionally, from my experience, it is a good idea to move the extraction of various program word fields from a std_logic_vector into a function. The function accepts the program word as a parameter, and returns a record type that contains your 'decoded' instruction. Something like:

type INSTRUCTION_type is record (
    opcode : std_logic_vector(3 downto 0);
    regA : std_logic_vector (3 downto 0);
    regB : std_logic_vector (3 downto 0);
    regC : std_logic_vector (3 downto 0);
end record;

function from_slv(v : std_logic_vector) return INSTRUCTION_type is
    variable rv : INSTRUCTION_type;
begin
    rv.opcode := v(15 downto 0);
    rv.regA := v(7 downto 4);
    rv.regB := v(3 downto 0);
    rv.regC := v(11 downto 8);
    return rv;
end function;


Then in your entity:

program_word &lt;= from_slv(data_out);


...

case (program_word.opcode) is


etc

This allows you to have the interpretation of the program word in one easily changeable place in a package. The record allows the various program word elements to be easily connected between entities, pipelined, etc. this technique also makes it very easy to add more elements to the program word, without having to change entity port declarations and instantiations.