Trouble understanding Loop Filter in a PLL
The purpose of a PLL is to make the VCO track the reference at DC and low modulation frequencies, and to be unaffected by the reference at high modulation frequencies.

You can make a PLL from a PSD, a VCO, and some gain, nothing else is needed. Because the VCO is controlled by frequency, and its phase is detected, that makes the loop behave as an integrator. This makes the gain infinite at DC, so it tracks the reference, and falls to insignificance at very high frequencies, so rejects the reference modulation.

Adjusting the gain in the loop sets the frequency at which the closed loop gain becomes unity, which sets the loop bandwidth.

Now for the loop filter. Although this loop is stable, tracks at low frequency, rejects at high frequency, it's not very good. Most people who use PLLs want better low frequency tracking and better high frequency rejection than the single integrator of a PLL can achieve. So we add a loop filter.

The loop must remain stable. The VCO integrator gives us 90 degrees phase shift. The phase shift added by the loop filter must stay strictly below 90 degrees at the loop bandwidth, and ideally less than 40 degrees to maintain reasonable dynamics, we don't want too bouncy a response. This means that any low pass poles have to have break frequencies well above the loop bandwidth. These low pass poles improve the rejection of reference modulation at high frequencies.

To improve tracking at low frequencies, we use an integrator below the loop bandwidth. By itself, an integrator would add 90 degrees phase shift, guaranteeing instablity, so it's 'broken' with a zero (that's the resistor in series with the integrator capacitor) to reduce the phase shift at the loop bandwidth back into the stable region.