Component instantiation in VHDL
I've just had a look at the testbench so no comments on functionality but your port map is wrong. Essentially what you're doing with a port map is connecting signals to various ports, the signals can have any name you like but like many coders you have named your signals the same as your ports which makes a lot of sense although is not always practical. I think your instantiation should read something like this:

DUT: arith
port map ( 
                A       =&gt;  A,
                B       =&gt;  B,
                opcode  =&gt;  opcode,
                Sum     =&gt;  Sum,
                Carry   =&gt;  Carry,
                mult    =&gt;  mult

            );


Which is basically saying connect port A to signal A, port B to signal B connect port opcode to signal opcode and so on.

If you are just starting out, consider getting a good textbook with examples, I would recommend VHDL: Programming by Example, I don't agree with all the examples given as being optimum but it is a really good reference book, I haven't found a better one.

Hope this helps,

Gipsy