Bad synchronous description - simple vhdl program
I reworked your code into a full synchronous description:


Synchronous designs need a clock-signal, but a button signal is no clock. So every process is triggered on a positive edge of Clk.
I changed the type of state to spare some type conversions.
If A is active, then the counter is reset to zero.
Otherwise if B is active, it increments.
I assume your led_debug process should be clocked to, so I added a rising_edge condition.


This solution does not solve the following problem, if A and B are wires from a external button:


External signals need to be synchronized with at least 2 FFs, to avoid metastability problems.
External buttons mostly need a debounce circuit, because button inputs bounce. There are also electrical or mechanical solutions possible to solve the problem. Have a look into your board descriptions and board schematics.
In most cases you want to count button presses. Your current solution measures how long you have pressed the button (this needs also a bigger counter). This problem can be solved by an edge detection circuit.


Here is the rewritten code:

entity simple is
  Port (
    CLK : in std_logic;
    A : in std_logic;
    B : in std_logic;
    debug : out std_logic_vector (7 downto 0)
  );
end entity;

architecture rtl of simple is
  signal state : unsigned(7 downto 0) := (others =&gt; '0');

begin
  increment : process(Clk)
  begin
    if rising_edge(Clk) then
      if (B = '1') then 
        state &lt;= "00000000";
      elsif (A = '1') then 
        state &lt;= state + 1;
      end if;
    end if;
  end process;

  led_debug : process(CLK)
  begin
    if rising_edge(Clk) then
      debug &lt;= std_logic_vector(state);
    end if;
  end process;    
end architecture;