How does asynchronous and synchronous reset signal affect the setup and hold time in a Flip Flop?
An async reset doesn't have a setup or hold time. Setup and hold are relative to a clock, an async input doesn't use a clock.

It will have a minimum active time, a propagation delay before the reset is reflected in the outputs and also a minimum idle time after being released. i.e. If you get a clock edge at exactly the time the reset goes away does it count as a clock or are you still in reset?

A sync. input will always have setup and hold times. For a reset these may be the same as for the data inputs or they may be different.

As with any timing, what happens when you violate the reset timing is undefined. It may reset, it may not reset or it could (and this is a long shot) change to some other non-reset state.