PWM Solar Battery Charger for 192V battery
MPT chargers hunt for max VI generated but the open loop method of setting PV voltage to ( I recall ) 80+/-5% , where it drops with solar E input and changes with ambient temp.

You indicated "The PV array has a maximum voltage of 370V and maximum point at 300V. The actual controller connects the PV directly to the battery until the voltage reaches 232V. Then it cuts the connection until the voltage drops to 216V when it connects the PV back"

Thus Voc=370Vdc  est. Vpmt=80% of 370 = 296V is a convenient duty cycle to use for a Fixed PWM. A tracking design senses the dv/dt while sweeping PWM and has a control loop to track peak.

Then you need another buck charger regulator that has CC and CV controls with UVP protection in case Vpwm drops from excess demand-supply current. This regulates the CC target level with a 50mV current shunt R or high side current sense IC.

Often each PV panel has its own PWM incase of partial shadows, as the effective Series impedance of series PC cells will rise rapidly when a solar shadow occurs.

Let's see what your minimum PV impedance is.

What we know.


Vpmt= 200V


What we don't know


Pmax of PV array, RdsOn of MOSFETs, battery technology, capacity etc.etc.
Let's pick a number like 40kW then ESR of the "quasi-current source" PV panel is Pd=V^2/ESR 


so ESR= 1 Ω and Imax = 40kW/200V=200A

how to choose RdsON of MOSFETs for CC mode ?


You don't want massive heatsinks or excessive Tj rise so a rule of thumb is &lt;1% loss per device. or RdsOn of 10 mΩ



These are just guidelines.

Burp mode charging (on-off)
Using a smoothing Choke in series, this is basicially another method of DC-DC conversion using hysteresis and a choke that is rated > Imax and impedance of choke determines the switching frequency you need such that it is much greater than the ESR of the PV This ends up being in the 10kHz to 1MHz range. If currents are too high then a boost regulator is used to raise PV DC-DC to a higher voltage like 800V, for the intermediate level then Buck to battery in order to minimize conduction losses in cables and MOSFETs but at the expense of higher performance HV Silicon Nitride FETS or IGBTs.