What's wrong with my Verilog multiplexer?
Instead of

assign m[3:0] = (~c &amp; x) | (c &amp; y);


you should use a ternary operator like so

assign m[3:0] = c ? y : x;


Alternatively, you can expand c to be the same width as x and y like so:

assign m[3:0] = (~{4{c}} &amp; x) | ({4{c}} &amp; y);


Noe that the ternary operator is much more concise.