Documenting Digital Design - Schematics and Figures
Here is a better way:  Don't!

The best way to document the design is by using the original code (VHDL, or Verilog).  This is the most accurate, and will always be up to date.  For simple designs, schematics might be more readable but that is not true for medium to large FPGA designs.  At that size, schematics become hard to follow, large, cumbersome, difficult to modify/update, and are impossible to debug.  So just don't use them.

When I have to document an FPGA design with schematics, I do it with Visio and make it more of a high level block diagram than schematics.  Doing anything with more detail is a frustrating and fruitless task.

I would also argue that VHDL/Verilog are not difficult to follow.  If someone can't follow them then the problem is the person, not the code.  I have some FPGA designs that if printed out would take up about 800 pages of standard paper.  That same design, if shown using schematics, would require 2,000+ large pages.  It is easier to get proficient at reading VHDL/Verilog than to transcribe 800 pages of VHDL code into schematics (and then keep it up to date and accurate).