The idea behind using a pull-up resistor
As modern chips use CMOS technology, so an input consists primarily of FET gates so virtually no current will flow in or out of a input. Therefore as current is virtually 0, there will be virtually no drop over any resistance.
In practice there can be some leakage currents in the order of 1 to 10 microamperes, so if you use pull-ups with maximum of say 100k it can be pretty sure that there is not too much voltage drop.
The same does not apply to other chip technologies like TTL, as their inputs will sink or source current based on inout voltage. So the pull-ups or pull-downs have to be significantly stronger (lower resistances), and they also use different voltage levels for determining a logic 1 or 0 state.