PIC datasheet is unclear on clearing framing error
There is a subtlety here which the datasheet does not clarify but one of the application notes does (AN774).

The FIFO, as far as it goes, is RCREG + a 1 byte buffer. Plus RSR - the receive shift register.

FERR is never updated unless RCREG is. The act of reading RCREG allows any waiting buffer byte to move into RCREG - this simultanously updates FERR (always) and RX9D (if appropriate). Thus we have three error type scenarios:


One bad byte in RCREG and one ok byte in the buffer: FERR is set, RCIF is set.  Reading RCREG causes the good buffer byte to move into RCREG along with its framing status. 
Now FERR is clear, RCIF is set.
One bad byte in RCREG and no bytes in the buffer: FERR is set. RCIF is set.  Reading RCREG causes RCIF to clear. No action is set on FERR. It remains set until a good byte arrives into RCREG.
One bad byte in RCREG and one bad byte in the buffer: FERR is set. RCIF is set.  Reading RCREG causes the buffer byte to move into RCREG along with its bad framing status.  Now FERR is set, RCIF is set. Buffer is clear. Situation is now as per (2) above.


For situation 3, repeated reads of the RCREG will not clear the FERR bit. Which is exactly what the note says.

Edit: Note the implication of scenario (1). If you read RCREG in this case, FERR is not valid for the byte you just read. You must check FERR before reading RCREG.