MSP430 8 vs 16 bit memory/bus?
So from the datasheet/books im reading, the data/address bus is 16 bits wide (2 bytes). And a Word size is 16 bits (2 bytes) (although im still not sure what word means in this context).

An address is conceptually a pointer to a location in memory, this location in memory is usually defined to hold one architecture word.
For most purposes the the word size represents smallest addressable unit . And the address size dictates the maximum number of addressable units. Address size also can be defined as the size of the register holding a pointer to address some memory.
Instruction vs Data:
On many modern CPU's there is a seperate and distinct instruction bus and data bus with their own instruction bus width and data bus width (instruction and data word size) as well as instruction address width and data address width. Additional memory buses may exist as well (with their own addressing schema)
For convenience these sizes may be chosen to coincide so that mixing data and instructions (Modified Harvard Architecture ) in the same physical memory hardware is simplified. In the case of the MSP430 series, they use a von Neumann architecture where words and instructions are loaded and executed from the same address space.

However the memory addresses are only 8 bits in size (1 byte). So everytime we send a word? or Opcode, are we storing it in 2 memory addresses? (I read that the MSP430 only looks at the lowest significant BYTE and that it has to be even)

In this cpu, the word size is in fact 16 bits. However, there are multiple addressing modes available depending on opcode, in most addressing modes the address points to a word of memory or an offset. Certain instructions may allow subaddressing into the word (and you can implicitly extend the address width of the architecture in this mode), often for optimization purposes (instruction packing and vectored instructions).
Physical Memory Geometry
The layout of physical memory may not necessarily match the architecture width. So the transaction between the physical memory and the instruction cache of the CPU may happen in a variety of ways and it is not necessarily important if it loads a word at a time or not.

So if were storing a word or instruction (Im not sure if they mean the same thing in this context). Were storing the LSB in the lower memory location (like 0x0200) and the MSB(byte) in 0x0201 for example. But the CPU is only actually reading the LSB? Is this correct?

Conceptually the instruction occupies one word of memory and is read from instruction memory in a single piece, the instruction occupies a single address 0x0200 points to a 16 bit word, due to byte addressing the next word begins address 0x2002, if you simply mask the last bit this is a 15 bit address that increments by one. The extra byte index bit is masked for all word address  operations.
It is also possible that the physical SDRAM or Flash Memory is organized by single bytes or even several hundred bytes and that the ram controller (a hardware device) translates the architecture address to an address that makes sense for the physical memory, but this is an implementation detail and not an architecture detail and does not dictate the Address and Data Width
Memory addressing in opcodes
Some instructions will require you to reference a an address in memory as part of the instruction (add, etc). If you have 16 bit addresses and 16 bit instructions, then there is now way to both store operation information and an entire address in a single op-code/instruction.
In this case a masking or offset scheme is used.
It is very common that the interacting with instruction addresses (branch and jumps) are defined as offsets to the given instruction pointer or masking it with the . This allows you to store an offset as 4/8/12 bits and lets you use 16 bit opcodes with memory inside the opcode.
An alternative is an op-code that uses a register or an address of data memory storing a full memory address.
In this case the CPU architecture is designed to operate on byte or word addressed modes.