Simulation is the same as my thinking,but different from the pape r(charging loop)
The previous answer didn't seem to help, as I see you stil are using pulse widths that are too large for what's described in the paper, and their periods are different. 


  SPG and SG close at the end of the positive half-cycle across a quarter resonance period 0.25\$\tau_{LC}\$


The names are from the paper, fig. 6. I'm not sure why you made up that control pulse like you did (also from a previous answer), I couldn't find specifications like those in the paper. Since L=300\$\mu\$ and R=1, 0.25\$\tau\$=75\$\mu\$, so the pulse width should be about 75\$\mu\$s and the period 10ms. The current source has a period of 20ms, and the amplitude is small, I chose 5\$\mu\$A.

I didn't read all the paper, so I didn't find the timings for the second switch (SP, same paper, same figure), but, judging by the waveforms, it's offset by half a control period, 5ms, and the width kept short enough to allow discharging and charging with ease, here ~1ms. Rise and fall times are 1\$\mu\$s for both.

The diode here is a quasi-ideal one, you can concoct one from a PMOS, or similar, controlled by the discharge of the L, above SG (not by directly tying the gate), or maybe a switch like the other three, but you'll need a separate control pulse.

Here's what came up in LTspice:





I am not good with CMOS modeling, but here's my tinkering based on your updates:



Two things to note: first, the voltage does not swing as in the pdf, and I blame my MOS switch for that, feel free to improve it as you see fit, and second, the supply voltage for the switch is referenced to a negative rail, with which the switch is supplied as its VEE -- to allow for the negative values of the waveform, V(Vpz).