Why there are two or more PCIe Hard IPs in some FPGAs?
You need several HardIPs for:


PCIe bridges
PCIe Switches
custom designs that use PCIe as a board-to-board communication
...


Common cores support up to 8 lanes and Gen2. More lanes are possible but need a Soft-IPCore. Also Gen3 is mostly provided as a Soft-IPCore.