Effect of power supply ripple on ADC readings?
PSRR always reduces with frequency, but let us put this in context:

The converter has a very low maximum sample rate, and you care about noise in this band so switching artefacts are unlikely to cause issues (check out the filterung done within the device); it is possible that the ripple of the switch mode device may give some intermodulation products at the reference, but they will be uncorrelated with the sample rate of the converter (i.e. they are highly unlikely to be synchronous).

Note that from DC to &lt; 20kHz (the maximum available sample rate), PSRR is unlikely to change in any meaningful way for the reference.

Using multiple samples and averaging will eliminate such noise; that said, it might be a good idea to feed the Avdd pin through a ferrite to eliminate the majority of the noise.

I am not sure a post linear regulator is actually necessary when you consider that the reference has a tolerance (absolute) of +/- 0.2%