High Frequency Square Wave Generator
500-600 MHz will need rise/fall times in the sub-1ns range. You will need to consider advanced driver techniques like differential HSTL, LVDS, HSCL, etc to achieve this. These kind of clock rates are what you find on DDR3.
TI and others make a range of clock generators that can do this. An FPGA that’s DDR3-capable can do it.