generating 40 mhz clock from 50 MHz
You need something like this. However, the device must have a VCO in order for this to work.

The circuit works by changing the frequency of a voltage controlled oscillator (VCO) based on the phase difference of two clock signals. The first signal of the two, \$F_I\$ in the diagram, is the reference signal and in the case of a PLL it is generated by dividing the main oscillator's output by an integer value. If the gain of the feedback loop \$N\$ was to be unity, the control voltage of the VCO would change appropriately until the output of the VCO exactly matched the reference input. In order to get an integer multiple of the reference clock signal as the output, all that needs to be done is to divide the signal fed back by that exact integer.



So, in order to get 40MHz from a 50MHz oscillator, the 50MHz signal first needs to be divided by 5. This 10MHz signal will be the PLL reference signal (\$F_I = 10MHz\$). This now needs to be multiplied by 4 and so by selecting \$N = 4\$, the output of the PLL will be \$F_O = 40MHz\$.

If the FPGA device you are using doesn't have embedded PLLs, you can use a ADPLL (all digital PLL).

Here are a few application notes:

Silicon Labs intro to ADPLLs

Xilinx DPLL reference design