FDCE flip flop primitive on altera quartus?
Newer versions of Quartus have wrappers for different basic flip-flop types. A list of all primitives can be found here: Primitive List for Quartus 15

Here is the DFFE component:

COMPONENT DFFE
  PORT (
    d    : IN  STD_LOGIC;   -- Data input
    clk  : IN  STD_LOGIC;   -- Clock
    clrn : IN  STD_LOGIC;   -- Clear (Reset, low-active)
    prn  : IN  STD_LOGIC;   -- Preset (low-active)
    ena  : IN  STD_LOGIC;   -- (Clock) Enable
    q    : OUT STD_LOGIC    -- Data output
  );
END COMPONENT;


Source: http://quartushelp.altera.com/15.0/mergedProjects/hdl/prim/prim_file_dffe.htm



Outdated Altera documentation:

There is the Quartus Low Level Primitive Guide.

Here is the basic flip-flop cell:

COMPONENT DFFEAS
  PORT (
    d      : IN  STD_LOGIC;
    clk    : IN  STD_LOGIC;
    clrn   : IN  STD_LOGIC;
    prn    : IN  STD_LOGIC;
    ena    : IN  STD_LOGIC;
    asdata : IN  STD_LOGIC;
    aload  : IN  STD_LOGIC;
    sclr   : IN  STD_LOGIC;
    sload  : IN  STD_LOGIC;
    q      : OUT STD_LOGIC
  );
END COMPONENT; 


Quartus has only one primitive, whereas Xilinx offers different wrappers for the same primitive.