PCIe riser card: Does it generate a local PCI clock on riser board?
Using the reference clock on the PCIe connector is pretty much optional, the actual clock is recovered separately for each lane and the only requirement is that parallel lanes are derived from the same base clock so data can be interleaved and de-interleaved reliably.
The USB cable has one transmit and one receive pair, and no separate clock connection exists.
The card must contain a PCIe bridge to allow all slots to work, and that bridge IC will have to recover the link clock in order to receive data. Whether it reuses that clock or generates its own for the downstream connections is unspecified.
The bridge IC contains clock domain crossing FIFOs anyway to allow device-to-host and device-to-device communication so there is no way to tell whether powering this device would generate a clock and feed it to an FPGA board.
Since your FPGA board should have an independent clock source anyway (the state machines for link training need an independent clock), I suggest you use that one and run it through a PLL to generate the frequency you need.
Most likely this will be some 40 or 50 MHz source, so you can easily derive 100 MHz from it with good stability.