Verilog syntax question
a = ( | b[10:8] ) ? 8'hff : b[7:0];


When | is used as a prefix, it is a reduction operator. That means it operates on all the bits of the vector that follows it. So what's happening here is the bits of the vector b[10:8] are being or'ed together to get a single bit result. 

That result is used to choose whether to assign the constant 8'hFF, or the lower 8 bits of b to a.