what should be the aspect ratio for 32nm and 45nm technology?
As a designer of a digital circuit you generally do not have to worry about the W/L ratio of the transistors.

Actually a schematic and a netlist describe the same thing ! They both describe how all components are connected to eachother.

A schematic is easier to read for humans, a netlist is what a computer program expects as input. Fortunately almost every schematic drawing program offers an option to generate a netlist.

For digital circuits the netlist is usually generated from the RTL code which describes what the circuit looks like in terms of gates.

These gates are mostly pre-defined with transistors having a certain W/L and a layout of these transistors and their connections.

So if you designed a digital circuit consisting of gates then you can use ready-made cells for that so you do not have to worry about W/L.

Selecting the W/L ratios of the transistors in these cells is usually trivial, Length is set to the minimum so 32 or 45 nm.

The Width for the NMOS is set to a workable minimum like 200 nm, that depends on the process. As PMOS transistors are intrinsically weaker they need a wider Width compared to the NMOS. Usually 2x wider is a good start so 400 nm for example.

You could also make a much slower/low power version by increasing the value of L. But that increases the size of the transistors !

If you want a gate with a more powerful output, capable of driving many inputs, you would keep L at the minimum but increase W.