Carry Ripple Adder - VHDL
I assume that you want to use a whole bunch of one-bit adders to create (what looks like) a 16 bit adder. 

So your top level entity should have 16 bit signal inputs and outputs, and you should instantiate the 1-bit adder. Here's an example image showing 4 bits of adder:



In the case of the above, your inputs to your entity should be 

A    : in std_logic_vector(3 downto 0);
B    : in std_logic_vector(3 downto 0);
C_in : in std_logic;


and the output should be

S     : out std_logic_vector(3 downto 0);
C_out : out std_logic;


Instantiate the one bit adder, connect as in diagram for as many bits as you need, and you're done.