SDRAM problem with LPC1788
This is not an answer but more a long comment.

I think you may have some signal integrity and layout problems as some people noticed in comments:


First of all : you don't have a continuous GND plane under your SDRAM lines.


Your SDRAM lines need to have a controlled impedance. To do this we usually put a GND plane under traces and adjust the vertical distance to have the right impedance.
When you have a GND "hole", you are making an impedance change and your signal will be altered. Also having via makes some impedance changes.

Here is your PCB layout with most impedance change highlighted, on some lines there is way to much impedance changes.




Second thing: it seems you haven't balanced the length of your traces.


Some are shorter than others. SDRAM specs should specified an authorized skew or length difference between traces.

As some people suggested, you should look at your signals with an oscilloscope. And maybe a logic analyzer to check the validity of your timings.