Xilinx ILA to start recording after triger + Xnum clock cycles
Not sure if there is a way to do this with the ILA directly.  My guess is probably not to keep the complexity of the ILA logic down.  What I would recommend is writing a little bit of additional logic to generate a new trigger signal based off of this specific condition that you're looking for, and then use that signal to trigger the ILA.  Should only take a few extra lines of HDL to generate the trigger signal you need; either a one-shot timer setup to generate a delayed trigger or something to swallow the first (or perhaps every other) tuser pulse.  Probably the simplest circuit would be to simply toggle a level on every tuser pulse, then you can pick which one you want by changing the trigger slope (rising or falling).