How can ground bounce be simulated by lumped elements?
Like this







simulate this circuit &ndash; Schematic created using CircuitLab

Notice the onchip 1 Ohm is a valuable dampening agent.

As are the Rout of the two FETs, as they strive to charge and discharge the 100pF CLoad.

As are the ESR of the offchip VDD capacitors.

There should be lots of ringing in the 100MHz to 200MHz region. Why? Because companies ADD more VDD and GND pins when Fring is LOW; low frequency ringing causes SHMOO holes, where the MCU will fail to properly clock at some clock frequencies and VDD combinations.