Split JTAG Interface
I have successfully used a technique similar to &quot;Idea 2&quot; in the original post.  I used Xilinx Application Note XAPP058 as a basis for the design.  The diagram that follows was cut and pasted from the app note.

This should work out of the box if you are using a Xilinx device and programmer.  Simple adjustments may be necessary if you are using other FPGAs or programmers.  I used a common quad 2-1 mux for this (74xx157, maybe).  For your case, the block shown as &quot;Processor&quot; would be your FT2232 chip.
A couple of notes:
Your diagram shows TDO running through the &quot;mux/switcher&quot;.  This is not needed, and will not really work with a 2:1 mux chip, as the signal path is not bidirectional.  You can attach the TDO directly to both the header and the FT2232.
Also, note that the circuit shown in the Xilinx app note can use either the PGND pin on the header or a jumper (J1) to control the mux.  If the PGND pin is grounded by plugging in the programmer, or the jumper is shorted, the mux select pin will be pulled to ground to connect the FPGA to the programmer. (If left floating, the select input is pulled high with the attached pullup resistor.)