Verilog syntax question: z=&{x,y};
This is the AND reduction of fslip_lock and dslip_lock. It's concatenating the two together ({fslip_lock, dslip_lock}), and then taking the AND of the resultant three bits to reduce it to a single bit, slip_lock. slip_lock will be 1 when all three bits of fslip_lock and dslip_lock are 1 and 0 otherwise.

See the SystemVerilog 2012 LRM, §11.4.9 Reduction operators for more information about reduction.