Verilog design decision - where should my counter be located?
If you have two modules, and you want to use one in the other then you instantiate and connect the desired ports together.  

For instance, if you have a top module with the signals clk, rst_count, inc_count and count_out and you are wanting to instantiate a (already written) Counter module with the name "MyCount" and with port names clk, rst, inc and data_out in it:

Counter  MyCount (.clk(clk), 
                  .rst(rst_count), 
                  .inc(inc_count),
                  .data_out(count_out));


An excellent starting book that will take you through Verilog for synthesis (as opposed to the large part of the language which cannot be used in this way, and is primarily for simulation) is Pong Chu's "FPGA Prototyping with Verilog Examples".