Does SystemVerilog support conditional compilation based on the tool analysing the file?
Yes, it is called the conditional compile construct `ifdef or `ifndef. For examples
module foo(...);

`ifdef SYNTHESIS
  // code to be synthesised
`else
  // code not to be synthesized
`endif

endmodule
 

See https://stackoverflow.com/questions/58996919/how-to-determine-that-synthesis-is-done-in-quartus