Using BRAM instead of SRAM in Virtex-5 FPGA
Good news. This is a really common application for ADC interfaces. It's actually very easy to set up the block RAM in Xilinx devices. 

You will want to run the "Block Memory Generator" Coregen by Xilinx, which will generate basically a black-box VHDL module that you can instantiate in your top level VHDL module. In the coregen, you can customize your block RAM so that it "looks" just like your existing external SRAM. The only difference will be that you will be connecting signals in your top-level module to the new black-box module that you've instantiated instead of to your external pins. 

I'm not sure that you can get a data width of 256 (did you really mean 8?), but I think that you could get a depth of 128K on most Virtex-5 devices. The datasheet showing the Virtex-5 resources table (how much BRAM is available) is available here.

The datasheet that explains Block Memory Generator is here. It can explain the settings, etc. 

To launch the block memory generator in ISE 14, right click in the project heirarchy and select "new source". Then select source type as "IP (Core...". Then select Block Memory Generator as the IP type as shown below. 



Once the "Block Memory Generator" opens, select whichever options you want, then click configure. It will add the black-box core to your project. You will have to instantiate it in your top level module. You can usually see the "instantiation template" by clicking the core in the project heirarchy and selecting the "View HDL Instantiation Template" in the processes window.