CMOS tri-state buffer internal structure
Since I just explained this to my daughters.

The bottom transistor is an NMOS transistor (an N-channel CMOS transistor). It works as a voltage-controlled switch. If the gate (the middle pin) is high (> 1V or so), it acts as if you pressed a push-button. It is ON. Otherwise, it is OFF.

The upper transistor is a PMOS transistor. It works in the opposite way. It is OFF when the gate is HIGH, and ON otherwise.

For the lower logic, the output is connected to ground when the NMOS is ON. It is ON when NOR(d, NOT(e)) = !(d + !e) = !d !!e = !d e = AND(NOT(d), e). I.e., the output is LOW (connected to ground) when the data is LOW and enable is HIGH.

For the upper logic, the output is connected to VDD (HIGH) when the PMOS is ON. It's ON when the gate is LOW. The input is NAND(d, e) = !(de). So, it is ON when both data is HIGH and enable is HIGH. 

So, as far as I can see:

| enable | data | output |
|   L    |   L  |   Z    |
|   L    |   H  |   Z    |
|   H    |   L  |   L    |
|   H    |   H  |   H    |


Notice the Z output. When the enable-pin is low, the output pin is not connected to anything, i.e. it is floating.