Reading data from register file in system verilog
I get a compile warning:


  implicit wire has no fanin (test_partC.clock)


You should connect the clk signal to the design instance in your testbench:

register_file dut (clk, write_enable, write_reg, data_in, read_reg0, read_reg1, data_out0, data_out1);


When I run the simulation, I see non-zero values on your outputs.