Using '$display' in Xilinx (verilog)
I made the necessary change and put the '$display' inside the modules. But this the output i am getting: 0 alumod A_in=xxxxxxxxxxxxxxxx, B_in=xxxxxxxxxxxxxxxx, ALU_out=xxxxxxxxxxxxxxxxx Why am i not getting the output? 


because you haven't provided any test input values. For example, in your testbench A_ALU and B_ALU aren't initialized. Since nets that are driven get the default value of 'x', you are getting A_in &amp; B_in as x's.

I've simplified your code here. See the testbench code where A_ALU &amp; B_ALU values are provided. The '$display' is used in the 'alumod.sv' file. After simulating you'll get output like this: 

#                  100 alumod A_in=x, B_in=x, ALU_out=x
#                  105 alumod A_in=1010, B_in=1010, ALU_out=10100
#                  110 alumod A_in=1010, B_in=10100, ALU_out=11110
#                  115 alumod A_in=1010, B_in=11110, ALU_out=101000
#                  120 alumod A_in=1010, B_in=101, ALU_out=101
#                  125 alumod A_in=1010, B_in=100, ALU_out=110


See, for 1st 100ns the values are x since they aren't initialzed yet.