Using register retiming to pipeline a module
Well there are at least two scenarios where I would opt for manual retiming:


Where I know there is a specific optimal geometry, for example, a logic tree, and I don't want the synthesizer to do this alone since it could make a suboptimal election.
Synthesis running times can be long. I may prefer to make these decisions alone instead of letting the tool take them, where I may have to check what it did and possibly rerun synthesis.