Sine signal generation using PWM
On the bottom of page 350 of the microcontroller datasheet, it mentions that writing a small value to the timer value register during the overflow interrupt might cause the next interrupt to be triggered only on the next pwm iteration, since the timer continues to count while the interrupt routine is being executed.  


  An unsynchronized write to the TIM channel registers to change a pulse
  width value could cause incorrect operation for up to two PWM periods.
  For example, writing a new value before the counter reaches the old
  value but after the counter reaches the new value prevents any compare
  during that PWM period. Also, using a TIM overflow interrupt routine to
  write a new, smaller pulse width value may cause the compare to be
  missed. The TIM may pass the new value before it is written.


This is confirmed by the fact that the pwm value is held high for one entire pwm clock period + what looks like the timer length (based on the surrounding lengths). The value being written to the timer length register is probably close to 0 at the time of error, so it is quite viable that the counter has passed the smaller value during the interrupt, and would only trigger on the following cycle.

This could be fixed by increasing the sinusoid minimum level to a level higher than the time it takes to execute the ISR, or changing the mechanism by which the new level is set. The top of page 351 details how this may be done.