How to use LVCMOS18 (1.8V I/O) on Artix 7 (Arty evaluation board)
The short and the long of it is: you can't.

The voltage used for I/Os on a Xilinx FPGA is controlled on a bank-by-bank basis, and is set based on the VCCO pin for the bank. For instance, if VCCO is powered at 3.3V, then all pins in the bank will use 3.3V I/O.

Setting an I/O standard that mentions a voltage does not make the FPGA use that voltage -- the FPGA does not contain voltage regulators! Instead, it informs the synthesis tools what voltage to expect for that bank, which may affect the drive and termination options used for I/Os. For more details, see the 7 Series FPGAs SelectIO Resources User Guide.

Anyways, all of the I/O banks available on the Arty have the following fixed VCCO inputs, which cannot be changed. In practical terms, this means that all of the I/Os you can access are 3.3V; you will need an external level shifter if you need to interface with a 1.8V part.


VCCO_0 - 3.3V
VCCO_14 - 3.3V
VCCO_15 - 3.3V
VCCO_16 - 3.3V
VCCO_34 - 1.35V (for DDR memory)
VCCO_35 - 3.3V