How to convert from "with 'argument' select" to if else statment in VHDL
For anyone searching for the answer, I wrote something which works:

FullAdder: OneBitAdder port map (InputSignal(1),InputSignal(0),CarryIn, ArithmeticModeOutput(1),ArithmeticModeOutput(0));    

process (Sel,J,K, LogicModeOutput, InputSignal)

begin

if(Sel = "00") then

LogicModeOutput &lt;= (J and K);
InputSignal &lt;= (J &amp; '0');
elsif(Sel = "01") then

LogicModeOutput &lt;= (J or K);
InputSignal &lt;= (J, K );
elsif(Sel = "10") then

LogicModeOutput &lt;= (J xor K);
InputSignal &lt;= (J, not K);

elsif(Sel = "11") then

LogicModeOutput &lt;= (J xnor K);
InputSignal &lt;= (not J, K);

else 

LogicModeOutput &lt;= '0';
InputSignal &lt;= "00";

end if;

end process;

process (Mode, UnitOutput, LogicModeOutput, ArithmeticModeOutput)

begin

if (Mode = '0') then

UnitOutput &lt;= ('0' &amp; LogicModeOutput);

elsif(Mode = '1') then

UnitOutput &lt;= ArithmeticModeOutput;

else

UnitOutput &lt;= "00";

end if;

end process;


--Our output signal was 2 bit, we seperate the bits for the function.
CarryOut &lt;= UnitOutput(1);
Foutput &lt;= UnitOutput(0);