Expected SDRAM access speeds?
No cache - it is like knocking the turbo off of a F1 car.
With SDRAM there is an 'entry' cost to read the first bit/byte/word (depending on the chip configuration), but subsequent reads are much faster up to the length of a memory line.  So you tend to read a burst of data into cache.
When the processor gets a cache miss (ie an address that was not cached), it reads another burst of data from the SDRAM. Without the cache, each access to the SDRAM incurs the 'entry' cost. Thus the performance is freakin slow. Even with the cache, you wont be getting equivalent single cycle access so the cpu won't be running flat out (compared to have single cycle memory).
Back to the expected performance - this is highly dependant on the code and how it interacts with the cache. You can easily write code that will cache miss more than hit - so performance will be abysmal. Conversely you can write code to ensure more cache hits. 'Normal' code will fall somewhere between those two extremes. You'd normally expect &gt; 90% cache hits on average.
Read up on the specs of your ram to get an idea of the timing. Read up on the cche line size and how that compares with the length of a line in your ram. Based on this information you should be able to get an idea of what the best case memory bandwidth would be, factor in the cache efficacy and that should give a hint as to what you might expect. If I were to guess, I'd say the overall performance would be equivalent to a 220MHz cpu. If the cpu has ITCM/DTCM (tightly coupled memory) you can run some code in that, count the cycles then compare with the same code running in SDRAM.
Why do you want to use SDR sdram as opposed to DDR?