Xmos MCU implementation on PCB
On the datasheet for the Xmos it says that ecoupling capacitors should
  be as close to the IC as possible. How close would a minimum be? I
  have put the capacitors as close as I can, with tracks coming out,
  will this be enough?


It's the parasitic inductance that creates problems between the caps. You can either calculate the trace inductance and resistance (with a PCB calculator) and calculate how it affects the bypassing of the cap. Or just place the caps as close as possible. For most applications, under 50mil is fine.


  3) On P. 72 the datasheet says that RST_N should be fast enough for
  USB timing. But RST_N is just a signal to hold the IC in reset, what
  does this have to do with USB timing?


They probably mean the reset is fast enough when powered from USB that the processor will be ready because the reset is short enough. 


  4) The datasheet states that the clock signal should rise/fall
  monotonic. However I do not find this in this datasheet for
  oscillators. Should I just assume that the oscillator is usable?


This means the clock signal, once the clock signal starts moving it should go straight down or straight up. If the signal does not (is noisy or has weird harmonics) this could lead to digial logic problems or problems with the PLL if the IC has one.  It should look like a clean clock signal.


  On the datasheet for the Xmos it says that the USB-standard dictates a
  differential impedance of 90 Ohm between the lanes. I find it hard to
  find information on this, and I have not found any specific
  implementations of this. What is to be done, to have this, and is it
  even needed? Is it implemented in the IC?


My personal favorite calculator for differential traces is Saturn PCB toolikit. Another tools is found here. Differential traces are simply transmission lines so you may want to brush up on transmission line theory if you haven't done so. Lines need to be matched to reduce attenuation\reflection. 


  5) Should the tracks for the xsys header be same length? The datasheet
  do not say anything about this.


I don't see anything labeled as XSYS on your schematic
If they are not impedance controlled or run under 50Mhz then I would say no.


  6) The datasheet says that I should minimize the amount of vias around
  the IC. Do I have too many, and how could it be done differently? By
  using longer tracks to the surface mounted components?


Depending on the signal it can be bad to run signals through many vias. The design looks fine. You may want to consider using smaller vias (check your PCB manufacturer to see what they support) 


  7) The PLL filter should, according to the datasheet, be as close to
  the IC as possible. Is my filter close enough? This is basically the
  same as question 1, but is the requirements the same?


I would be more concerned about the PLL ESL, you could probably rotate C89 and move some other components out of the way to get it closer.