DDRx timing analysis
The manufacturer of the DDRx controller should provide design constraints for PCB layout, covering the clocks, address, control, data and DQM signals. If not, you may be able to infer them by putting together the DDR controller's DIMM routing guidelines with the appropriate JEDEC DIMM spec. Follow these guidelines to achieve the required impedances, path lengths and spacings in your routing between the controller, the board-to-board connector, and the memory devices.

Verify your design by performing IBIS modelling of the whole interconnect (this will require signal integrity expertise) and comparing results with your design constraints, and with known good layouts (usually based on standard DIMMs).

The controller's calibration/levelling is built on an assumption that PCB layout constraints have been followed exactly. It may provide diagnostic registers to allow you to verify the levelling outcome at runtime. I have found ECC to be very useful for design proving.

A good PCB layout tool will enforce constraints as you go and will simplify the serpentine routing that is usually necessary to meet path length constraints. I have seen many right-first-time DDRx layouts done quite quickly with Cadence tools.