Inferred latch occurence in verilog
It's a latch because you allow q to be updated when ena goes high or any time d changes when ena is high. This is exactly the behavior that describes a latch. This is how you should code a latch if you intentionally want to produce one.

To generate a flip-flop you should make the block triggered by a change in ena (i.e always @(posedge ena)) rather than by any change in the inputs.