CMOS Gates, I can't understand when we use those negation bubbles
That bubble stands for P channel MOSFET transistor. See the following equivalent symbols.



See the picture for structure of a P channel MOSFET.
In CMOS technology the main substrate is P:



For example in the NAND gate in  the question making both A and B HIGH will cause the upper transistors to be OFF and lower transistors to be ON, therefore  F is connected to the ground and will be LOW.