Thermal Vias Specification Design
The datasheet shows the thermal resistance for different packages on different mounting setups: 1 layer PCB without vias, 2 layer PCB without vias, 2 layer PCB without vias, etc.  

Because there are thousands ways to measure thermal resistance under another thousand different conditions the datasheet specifies which standard has been used to measure the thermal resistance:  


  Thermal impedance simulated values are based on a JEDEC thermal test board. See JEDEC JESD51.  


When using a 2-layer PCB as described in JEDEC JESD51 with vias placed like the picture shown below, the thermal resistance for the 8-lead LFSCP package is 55°C/W.

Make sure to connect these vias to the correct power plane as per datasheet's note:


  Exposed Pad. It is recommended to connect the exposed pad to the V+ pin.