VHDL unranged integer input ports bad practice?
I basically want to know if the 64 supporting points (or any other 2^n value defined by interpol_steps_exp_g) will allways consist of a 32bit wide bus, or if Vibado is able to limit the bus width to 12bit if every one of the 64 buses holds a constant value smaller than 2^12-1.


I am not familiar with tools you use, but any modern compiler is able to optimize the design, and if it sees at the stage of compilation that higher bit are not used, it will remove related parts of registers/wires and all other supporting logic.

Look into the optimization settings of your compiler.

Finally, I think it should be correct if you define interpol_steps_exp_g's size of appropriate number of bits at the source level; if compiler will see that some instance uses inexisent indexed of the vector, it will throw the error.