Figuring out mininum/maximum clock frequency [VHDL]
You don't discover how many cycles it takes, you design that into the circuit. 

You set your maximum clock speed target via a "timing constraint" (useful search term), and the synthesis tool will try to achieve that, or report which bits of the circuit fail to meet that timing. If you are using proper synchronous design, there will be no minimum speed.

If there are failures, you rewrite those bits so they are faster - if necessary, adding a clock cycle and splitting them across both cycles. 

If you meet your speed goals with ease, Place&amp;Route will proceed smoothly. If they don't, you go round the same loop again.