How to interface an ADC with FPGA through the CLKOUT signal in verilog?
I think you need to go a little further than your proposed solution.
I would suggest that you have the data read from the ADC into a register using the ADC clock. The register should be long enough to hold the entire integer value from the ADC. Once that register is full with a reading the associated state machine logic would generate a signal to indicate that the value was valid and not going to change and can be read by the main FPGA logic.

From the point of view of the logic driven from the main FPGA system clock the register complete signal would be asynchronous, however you could use it as an enable signal to copy the data in one system clock cycle to another register on the next system clock edge. Thus you would now have the data available synchronous to the FPGA system clock.

The only restriction with this scheme that I can forsee is that the FPGA clock would need to be at a higher rate than the ADC clock to ensure that the data was available for sufficiently long.