Verilog Generic Multiplexer - synthesis warning and simulation compile error using Xilinx ISE 14.7 "Port must not be declared to be an array"
Can ports not be declared an array in Verilog as they can be done in SystemVerilog ?


The simple answer is: No. You can't.

If you really need, you can concatenate and split:


Make the input a vector which is big enough to hold all the data.
Concatenate your array of vectors into one big vector.
Pass the vector through the port.
At the other side split into an array of vectors again.


This is how I learned to cope before System Verilog came along.