Is it possible to remove the write back stage in 5-stage pipeline?
Yes, you could eliminate the WB stage.
In fact, if you really want to trade complexity for performance, you would bypass the ALU output (EX stage) back into the input to the EX stage and skip the MEM and WB stages.
The pipeline shown in the original post is dramatically sub-optimal -- it wastes two ticks on many instructions.
Consider an ADD followed by an AND, for instance.  As soon as the ADD result pops out of the EX stage, it is ready to be used in the next instruction. But the pipeline above sends it through two more pipe stages.  So if this were a real processor, you'd have to stuff at least one other instruction between the ADD and the AND.  Back when Babbage was a little boy, I saw a study that said most input operands were generated within the last two instructions.
So all the processor designs that I've seen have implemented a bypass path from EX out to EX in. Perhaps there are lower-power/performance designs that leave out the bypass, but it seems like a bad trade.