clkp and clkn inputs in Intel MAX10 FPGAs
The guide you want is the &quot;Intel Max 10 Clocking and PLL User Guide&quot;. This discusses the clock networks and PLLs including what inputs can be used for what.
To answer your question, yes in the Max 10's each differential clock input can also be used as two single ended inputs.
In the case of PLLs, either of the P and N pins can be used as a dedicated clock input - note that each PLL is specced for 2 differential inputs or 4 single ended inputs.
In the case of clock networks, the P and N pins drive different GCLK lines. This is generally not an issue as the synthesis tools take care of this, but if you have multiple clocks, it is generally best to double check in that user guide that all of your clocks can drive their own GCLK line.