User defined data type in Verilog
SystemVerilog has enumerated types, and most synthesis tools now support this:

typedef enum {C0,C1,C2,C3,C4,C5} Command_Byte_state_type;

Command_Byte_state_type Command_Byte_state;


And you will be able to select the encoding options in your synthesis tool the same way you do when writing VHDL.

If you insist in staying with Verilog, you will have to assign a default encoding 0/1/2/3/4, but you can still tell the synthesis tool to remap it.