CMOS gate logic switching time based on input vectors
@sanjay: A standard CMOS NAND gate has two PMOS devices in parallel to pull the output (to supply) and two series NAND gates to pull the output down (to ground).  If either input is zero, then at least one PMOS is on pulling the output up and at least one of the series NMOS FETs is off preventing the output from pulling down.  

So the output will not "lose its state."  There can be small glitches seen in the output voltage when the one input changes from 0 to 1 due to gate overlap capacitance in the FETs, but any glitches like this should be small enough that they do not cause the next gate or stage to see a change in the NAND output.

Note we don't usually consider a combinational logic gate as having a "state."  In digital design, a "state" implies some sort of memory or latched condition as in a flip-flop or latch.