Mystery circuit with a functional description
That mystery circuit is a  8-bit NAND Structured String from a SLC (Single Level Cell) NAND flash. Additionally to the NAND Structured String, which is actually a in-series connection of 8 NFETs, of which 4 are missing in the picture, there is a pull-high structure (the PFET transistor on top) and also the column decoder (DEC8) is shown on the left.

A NAND Structured String is a transistor topology which stores the data in a NAND flash. It's a series connection of enhancement-mode N-channel MOS transistors, e.g. the drain of the topmost transistor is connected to the source of the next and so on. The last transistor's source is connected to ground and the first transistor's drain is connected to a MOS load transistor, which generates pull-high for the output of the string. 

So the upper-right transistor is a MOS load transistor. There are several configurations for MOS load transistors.. this one looks a little strange because if the gate with the circle is a PFET as is usual for this drawing technique, then that would mean that the source of the PFET is towards the high voltage and thus the PFET is always at least somewhat conducting. It could be made to work by making the drive capacity of the FET limited. And when the drain voltage (output) goes low, the FET's field effect from the ground-connected gate to the substrate gets substantially weaker as the field only forms around the VCC-connected source end of the channel, so with careful design it might work pretty well, actually. But usually MOS loads' working principle is that their source is towards the output, and thus their VGS threshold voltage changes with the state of the output, making the MOS load more energy efficient, faster, and easier to manufacture than resistive pull-highs.

The last thing that remains to be explained is the NAND structured string itself. As said, it is made of eight transistors instead of only the four which are present in the picture. The missing four transistors indicate transistors which have have their floating gate programmed with such a charge that blocks any electric field that would be generated from the gate towards the substrate. The effect of blocking the field is that the transistor is always conducting no matter what the gate voltage is, so for the purposes of circuit analysis, the transistor can be substituted with a short circuit (wire) as has been done in the picture. 

The state of an individual bit in a SLC NAND string structure is read by having all gate voltages set to high, except for the one bit which is being read. That transistor is then the only transistor that controls whether the output is pulled low or not. All the other transistors are conducting, so that one transistor is the only transistor that might break the string. And that depends on whether a charge has been pushed into that transistor's floating gate or not. Changing which transistor is selected, we can choose which bit we read. And that selection is made by the column decoder, DEC8 based on the low 3 bits of the address input.



Edit: Answers to your questions :)


What is DEC8(blue)? Standard component?


That's a three-to-eight decoder, also called a one-in-eight decoder. It's a standard component. Internally, it s similar to a one-in-eight multiplexer with the input signal pulled low, so in some literature they're also called multiplexers, a little incorrectly in my opinion.

010 triggers line 4(green), why? Should it maybe be 100?


Yes. That most certainly looks like a typo. Perhaps the schematic is changed, but the description carried from a component that has inverted inputs; thus inverted 010 would be 101 (five) and counting from the bottom, the fifth line is the green-dotted line, which is the fourth one from top. I've made my share of such typos when writing exams...

What function does the inverted gnd behind a transistor serve? (red)


That's the MOS load transistor (pull-high). If I just read the schematic without wondering if it is correct or not, then that "inverted gnd" means gnd connected to the gate of a PFET, keeping the PFET always conducting. And the proper operation of the circuit depends on the PFET being weak enough to give in when the NAND string says it's time to go low.

If current flows from vdd to gnd(orange) is f considered 0 or 1, why?


Well, to be precise, current doesn't flow into the gate, it's the electric field from the gate voltage that makes the transistor work. But if the gate (orange) is "0", then that transistor is not conducting, which breaks the string and lets the MOS load transistor pull the output (f) high (to 1).