Addition of 2 unsigned values in VHDL IEEE numeric_std : why this choice?
This "choice" allows the hardware designer to only handle overflow if it makes sense:


Ignore the overflow

function add_ignore_ovf(a : unsigned(7 downto 0), b : unsigned(7 downto 0)) return unsigned(7 downto 0) is
begin
    return a + b;
end function;

One time this makes sense for implementing modulo 2 counters.
Handle the overflow

function add_with_ovf(a : unsigned(7 downto 0), b : unsigned(7 downto 0)) return unsigned(8 downto 0) is
   variable a_ext, b_ext : unsigned(8 downto 0);
 begin
   a_ext := '0' &amp; a;
   b_ext := '0' &amp; b;
   return a_ext + b_ext;
end function;