Calculating pull-up resistor value for CD4078
Considering strictly static DC operation for these CMOS gates...
Input current at maximum temperature tops-out at one microamp. So a large-value resistor of about 3 MEGohm will ensure a logic high, if no other current paths are present.
So why might you use a smaller-value pullup? A few reasons:

Noise pulses from nearby traces might momentarily yank a high-resistance pullup low.

If an open-collector (or open-drain) is to drive this input low, its leakage current would require a smaller-value pullup resistor.

A large-value pullup resistor pulls up rather slowly in the presence of capacitance. The capacitance of the input alone might be about 7pf. A slow transition time can cause logic gates to go squirrelly, and oscillate as the input slowly transits from low-to-high. A clean logic transition is often required.


The logical solution to these problems is to lower the value of pull-up resistance.
Consider that an input pin that spends most of its time &quot;pulled-up&quot; to logic high causes almost no current drain. You can choose a smaller-value pullup resistor, with almost no down-side.
If the pulled-up input spends most of its time low (pulled down by some other source) then current does flow, and a large-value pull-up resistor value should be chosen to reduce battery drain.