Unable to understand Verilog syntax
Very strange example, not sure what this example was intended to do. There's only the module declaration and a localparam declaration, nothing else.

Defines a module which is named test, which has no input nor output ports (because the port list is an empty set of parenthesis). However it does take a single parameter named p (this is inside the hash-parenthesis list #(p) part of the module declaration ). The default value of the parameter p is 1 unless otherwise specified.

Inside the definition of the module, there is another parameter declared, which is named lp, which is defined as the constant expression ~(p)'(1'b0).

The unary ~ is the bitwise negation operator, and the literal integer expression (p)'(1'b0) is a constant that is "p" number of bits wide, and all of the bits are 0.  So ~(p)'(1'b0) is all bits 1.  Note in verilog, we always care exactly about the bit width of every constant, wire, and net; literal constants use that infix apostrophe ' to indicate the bit width.

This is a very strange example, because with no ports and nothing making any use of the parameters, there's nothing for a simulator or an HDL compiler to do.

Usually verilog modules have input and output ports, with the exception of a test bench that is used to simulate and test other modules. But that's not the case here, because this module doesn't instantiate any other modules -- it literally does nothing.