Generation of non overlapping clocks on FPGA using VHDL
All the lower bits in your transition points are zero (not counting the instance where you clear phi2 twice, so you can divide the clock a few times and use a smaller counter.

You can also split up generation of a continuous train of pulses of the desired length (lower order bits of the counter) and routing to an output (higher order bits), e.g. 16 pulses with an \$\frac{1}{8}\$ duty cycle and two outputs could be achieved with an 8-bit counter (not even compile tested, but you should get the idea):

pulse &lt;= '1' WHEN counter(2 downto 0) = "000" ELSE '0';
output &lt;= counter(3);
phi1 &lt;= pulse AND NOT output;
phi2 &lt;= pulse AND output;


Have counter run upwards and stop after "11111111".

Depending on what else is going on in the design, I'd probably also use a PLL to derive a slow (1 MHz) clock and divide from there.