Why are registers being turned on to 1 before reset/on button is hit on FPGA?
There are two possibilities (at least)


Your FPGA has an automatic global reset at start up. Since your code resets led to 0 and start to 1, these are the values they will get when the global reset is applied.
Your FPGA doesn't have an automatic global reset. In that case, the initial value of led and start are unpredictable. They just happen to be coming up as 0 and 1 respectively as a matter of chance (and the operating temperature, timing of the power supply ramp up, etc.)


If you want to know what value your start signal will have at power up (for example, you want it to be 0 until the ron signal goes low), then you should code it to reset to 0, and implement a global reset, or choose an FPGA that automatically performs global reset. In this case you need to code the reset behavior of start as going to 0, and use ron as an ordinary signal (not routed on the dedicated reset inputs of the flip-flops) that causes a state transition of start from low to high.