Is this design legal in verilog
Yes, direct assertions are legal in Verilog. However, this is a very bad design practice to design main RTL code using direct assertions.

The direct assertions in Verilog are usually used in verification environment, in test benches, to "hot wire" some initial states and change timing parameters, mostly in order to accelerate verification process. In this way the verification environment doesn't interfere with main RTL during debug.