VHDL Clock Divider Problem
I've rounded up all the good advice from the comments into an answer.
Clock Strobe
Generates a slower strobe from a faster clock.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ClockStrobe is
    generic
    (
        CLOCK_PERIOD : time := 20 ns;
        STROBE_PERIOD: time := 2 ms
    );
    port
    (
        reset : in std_logic;
        clock : in std_logic;
        strobe: out std_logic
    );
end entity;

architecture V1 of ClockStrobe is

    constant MAX_COUNT: natural := STROBE_PERIOD / CLOCK_PERIOD - 1;
    signal counter: natural range 0 to MAX_COUNT := 0;  -- Specify the range to reduce number of bits that are synthesised.

begin

    process(all)
    begin
        if reset then
            strobe &lt;= '0';
            counter &lt;= 0;
        elsif rising_edge(clock) then
            if counter = MAX_COUNT then
                strobe &lt;= '1';
                counter &lt;= 0;
            else
                strobe &lt;= '0';
                counter &lt;= counter + 1;
            end if;
        end if;
    end process;

end architecture;

Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity ClockStrobe_TB is
end;

architecture V1 of ClockStrobe_TB is

    constant clock_period : time := 10 ns;
    constant STROBE_PERIOD: time := 2 ms;
    -- constant CLOCK_PERIOD : time := 10 ns;
    -- constant STROBE_PERIOD: time := 40 ns;

    signal halt_sys_clock: boolean := false;

    signal reset: std_logic := '0';
    signal clock: std_logic := '0';
    signal strobe: std_logic;

    component ClockStrobe is
        generic
        (
            CLOCK_PERIOD : time := 20 ns;
            STROBE_PERIOD: time := 2 ms
        );
        port
        (
            reset : in std_logic;
            clock : in std_logic;
            strobe: out std_logic
        );
    end component;

begin

    ClockGenerator:
    process
    begin
        while not halt_sys_clock loop
            clock &lt;= not clock;
            wait for CLOCK_PERIOD / 2.0;
        end loop;
        wait;
    end process ClockGenerator;

    Stimulus:
    process
    begin
        -- Do reset.
        wait for CLOCK_PERIOD / 4;
        reset &lt;= '1';
        wait for CLOCK_PERIOD / 2;
        reset &lt;= '0';

        -- Wait for a couple of strobes.
        wait for 2.1 * STROBE_PERIOD;

        -- Halt simulation.
        halt_sys_clock &lt;= true;
        wait;
    end process;

    CS:
        ClockStrobe
        generic map
        (
            CLOCK_PERIOD =&gt; CLOCK_PERIOD,
            STROBE_PERIOD =&gt; STROBE_PERIOD
        )
        port map
        (
            reset =&gt; reset,
            clock =&gt; clock,
            strobe =&gt; strobe
        );

end architecture;

Simulation Results

Figure 1 – Clock strobe simulation results: 100 MHz clock; 500 Hz strobe.
Using the Clock Strobe
And here is how to use the clock strobe for slow logic.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity SlowLogic is
    port
    (
        reset : in std_logic;
        clock : in std_logic;
        strobe: in std_logic
        -- Slow inputs and outputs here.
    );
end entity;

architecture V1 of SlowLogic is

begin

    process(all)
    begin
        if reset then
            -- Reset slow outputs, etc.
        elsif rising_edge(clock) then
            if strobe then
                -- Do slow logic on inputs and outputs.
            end if;
        end if;
    end process;

end architecture;