12F675: ICSP: /MCLR internally tied to Vdd
First, read the manual.  "MCLR internally tied to Vdd" doesn't mean that the pin is tied to Vdd, but that internally the MCLR logic is driven as if it were always tied to Vdd.  In other words, the voltage on the MCLR pin won't effect whether the processor is reset or not.  The processor always starts running when power is applied, after startup timer and brownout detect, if any, are applied.  In all cases, the MCLR pin is a input.

Second, the MCLR/GP3 pin is always a input and therefore always high impedance.  How you deal with contention between a programmer and whatever circuit function you have driving that pin is your business.  I usually put 20 k&Omega; in series with the external circuit in cases like this.  That won't get in the way of driving a high impedance CMOS input.  The programmer is then directly connected to the MCLR pin, when it is connected at all.  Most programmers can overcome 20 k&Omega; impedance when trying to drive the MCRL pin.

For more circuit design considerations relating to ICSP, see my writeup on that topic.