Glitches in clock gating cell
The issue stems from the fact that in the first case, gating the clock causes it to go high, but in the second case, gating the clock causes it to go low.
To illustrate the problem, consider the situation where the fourth clock gate circuit is used but the clock gate signal is registered in the riding edge. In this case, the clock gate register output changes right after the clock goes high. Since the fourth circuit is used, the gate causes the output clock to go low, causing the clock to return low almost immediately after it became high.