Use of coupling capacitors in transistor biasing
Here's the equivalent circuit of your output:-



simulate this circuit &ndash; Schematic created using CircuitLab
Initially the FET is on (M1 closed) so C1 is discharged and has 0 volts across it. Now consider what happens when M1 opens:- C1 momentarily acts like a short circuit, so R15 is effectively in series with R17||R18 creating   a voltage divider with ratio of 4.68k / (1k + 4.68k) = 0.824. Therefore the output voltage will momentarily jump to 24 * 0.824 = 19.8 V.
However the capacitor now charges through the resistors, causing a voltage to develop across it which makes the output voltage sag.
A little while later M1 closes again and pulls the input side of C1 to ground. Since C1 has a voltage across it the output now goes a little bit negative, causing C1 to discharge through R17||R18 (very slowly because the voltage is small). Over time this trend continues until the charge and discharge cycles equalize, with the output going from ~ -10.8 V to +10.8 V and C1 having ~ 10.8 V across it.
You can see the beginnings of this in your graph. If you run the simulation for a long time (eg. 100ms) you will see that the capacitor has removed the DC bias from the output, with the RC time constant that you would expect (average of C1 * (R15 + R17||R18) when charging and C1 * R17||R18 when discharging) of ~ 11.4 ms.
If you plot the voltage across C1 you should see something like this:-