D Latch Design and Implementation
BJT,
My schematic is a bit disjointed due to my unfamiliarity with the drawing tool. Here are the  basics:

A. The flip-flop is a 74HCT74 or 74HC74 D-Type Flop.

B. The diode is any signal type diode similar to a 1n4148.

C. Capacitor can be tantalum, ceramic, electrolytic.

D  Resistor is 1/4 watt or smaller.

E. Supply voltage is 3.3. or 5, it depends on which family of 74 logic you use for the flip flop.

F. The "1" on the D input to the flip flop denotes a pull-up (Logic 1) to the supply voltage. A 1K resistor or direct connection.

G. The clock input of the D-flop is connected to your FAULT signal. Which I assume to be high-active.

H. The RESET- signal is connected to the RESET-input of the D-flop (74HC74, etc. 

I. The 74x74 also has a SET- input, you should connect this to a Logic 1 (just like the D input described above).

J. The 74x74 IC has two sections. If you are only using one section, all of the inputs on the unused section must  be connected to circuit ground (DC common). Just the inputs, not the outputs! Leave these unconnected.

The D,R &amp; C form a rudimentary power on reset circuit. You can find an explanation of how this operates on the web. The essential operation is that the RESET- node is held low when power is first applied and eventually (i.e. within a fraction of a second) rises to a Logic 1 level due to the time delay of the R &amp; C. The effect is to hold the flop in Reset while power is applied. Once it is reset like this it will stay reset until the FAULT signal goes active momentarily, which will SET the flop where it will remain until the next power cycle (OFF then ON).







simulate this circuit &ndash; Schematic created using CircuitLab

This very popular power-on reset circuit has a number of issues. A few are listed here:

A. The power off time between power down and repowering up can be finicky and somewhat erratic. Meaning you need to ensure a long enough power off time between repowerings for it to act reliably. Say, a few seconds. You'll experiment and find out.

B. The behavior of your FAULT signal during power-up can thwart the operation of this circuit. You must make sure the FAULT signal is indeed inactive (assumed to be LOW) while  the power is applied. 

C. The selection of the R &amp; C can improve performance. I suggest making the value as large as practical to get as long a power on delay as practical for your application. However, longer power-up delay (Reset pulse generation) also produces a longer turn-off time requirement. Don't make the Resistor much bigger than 47K, the cap can go to 100 uF, depending on the type of cap, ceramic and tantalum a re best for this application. Electrolytics will work as long as capacitance is "not too large" - meaning something like 100 MFD. 

D. The "profile" of the power/voltage application tot he circuit can cause erratic operation of this circuit. For example, whether the power "snaps" on very quickly. Or, it ramps up relatively slowly. E.g. power is applied from a battery thru a mechanical switch. This is a snap-on case. In contrast to power is supplied thru a solar cell, where the voltage rises very slowly into the operating range of the circuitry. The latter is a problem for this reset circuit.

The most common wiring error for beginners with this circuit is getting the polarity of the capacitor and diode correct. Double check these when you assemble the circuit.

You can observe operation of this circuit by monitoring the RESET signal with an O-scope or analog voltmeter (needle type). A DVM might work, but the readings may change to quickly to follow visually. Remember the RESET signal  will start at GND and rise towards your supply voltage as power is supplied to your complete circuit.

The alternative is to use a dedicated power-on reset IC such as those made by Maxim &amp; Dallas. However, these require a certain level of  engineering expertise to apply properly to your circuitry. 

Good Luck!