Test_bench in Verilog using Task
It would be helpful if you could clarify this statement :


  How should I define input in argument in task so that input should be given independently?


A task defined as:

task display_redux
  input [31:0] a_number;
  begin
    $display("display_redux was sent : %d", a_number);
  end
endtask


Can be called with :

display_redux(20);
integer ii = 6;
display_redux(ii);


To me the input here is independent from anything else, and you can not assign value to the input so it does not have side effects from of modifying inputs from where it was called.

Taking one of your tasks:

task exp_case_2b
  input data_i;
  input reset;
  input read;
  input dcsel;
  input xlat;     
  output reg [47:0] data_o;
  begin
    repeat(47)begin @(posedge clk)
      data_i = 1;
      reset  = 0;
      read   = 0;
      dcsel  = 0;
      xlat   = 1;
      data_o = Data_out;          
    end
    #5250 compare_data_2(data_out_tb);
  end 
endtask


Youve declared many inputs which you are not driving when you call it with exp_case_2b(data_out). You have defined inputs then are trying to drive values on to them. You need these to be regs and not inputs so they are local to the task. Or not defined at all and use hierarchical references to the top level reset, aka tb.reset = 0;.

I think this might have been what you were trying todo:

task exp_case_2b
  input      [47:0] data_i;     
  output reg [47:0] data_o;
  begin
    repeat(47)begin @(posedge clk)
      data_i = 1;
      reset  = 0;
      read   = 0;
      dcsel  = 0;
      xlat   = 1;
      data_o = Data_out;          
    end
    #5250 compare_data_2(data_out_tb); //No idea where this variable comes from
  end 
endtask


Then call :

 exp_case_2a(data_i_t, data_out_1);