Linear Feedback Shift Registers on FPGA's
Your problem can be solved "easily" - that is, in a straightforward manner - but it will suck up considerable resources and cut down maximum frequency. What you do is to feed each input to the XNOR gate from a 256:1 multiplexer, with each register stage feeding one input to each of the two muxes. A 256-bit mux will have several levels of gates, so the total propagation through the mux will be relatively slow. Since I don't know your desired clock rate, I can't predict if this will be a problem.

Each mux will require an 8-bit control byte, and this can be done in various ways, the most straightforward being a total of 16 parallel inputs. Or you can have 8 inputs feeding 2 8-bit registers with 2 clocks (or a single clock and an enable address). Or you can have a pair of serial inputs feeding 8-bit shift registers. Or, or, or, etc. Depends on your taste in control interfaces. If you really want to get creative you can use an Ethernet/TCPIP link. Or an RS232 interface.