Why is de-assertion of an asychronous reset a problem compared to its assertion?
The assertion timing doesn't matter because the whole point is that all the elements of the circuit enter a valid/known reset state.  It generally doesn't matter what order they do it in, only that the final state is predictable.

De-assertion is a problem because if some flip-flops come out of reset before others, they may start changing state while others are stuck in the reset state.  This can lead the entire system to be in an invalid state.