pull-ups between logic gates
This is a case of interface between logic families (from LS-TTL -to- CMOS). Although both are powered from +5v supply, logic levels differ:


Logic low output for the 74LS93 is compatible with logic low input for CMOS 4002. No problem here.
Logic high output of 74LS93 is marginal compared to logic high input for CMOS 4002.


This is a matter of noise immunity: pull-up resistors ensure that a logic high is closer to Vcc of +5V rather than a \$V_{be}\$ lower than +5V.

Worst case \$V_{OH}\$ for 74LS93 is 2.7V
Admittedly, that's with Vcc at minimum 4.75V, and loaded with maximum current (0.4mA). When lightly loaded with high-impedance CMOS, far less static current flows.

Minimum acceptable \$V_{IH}\$  of 4002 is 3.5V
Clearly, the 74LS93 needs some extra help to pull up to 3.5V. 10k pull-up resistors do the job. Even so, at higher speeds, capacitance may slow the rising edge.