Is there possibility for a race condition in the following circuit?
The situation you describe is not a problem, because after that "very short time" the R and S inputs will be valid. It is possible that both of the latch outputs will have the same value for a short period of time, but that is always a possibility during the time when the latch is changing state. However, the final state of the latch is deterministic and not dependent on the gate delays so there is no race condition.