How can RDA5807M get away with very high PLL multiplication?
In some applications there would be huge phase noise but, the synthesizer here does not have to rapidly (or dynamically) set the down-converter frequency - the output from the phase comparator can be highly slugged so that the VCO control voltage is very smooth with barely any ripple. 

It's LPF could be 1 Hz or even a bit lower and, it could even speed up when changing stations so as to minimize delay when re-tuning.