Is it possible to know what % of routing resources are used in an FPGA
For Altera/Intel (Quartus II), the best information you will be able to get is from the compilation report.

If you open the report of the fitter step (in the tasks window, expand "Fitter", then double click "View Report").

The report contains information about the resource usage of the design, which includes a global routing average under "Resource Selection -> Resource Usage Summary", and then a breakdown of the full routing resource utilisation under "Resource Selection -> Logic and Routing Selection -> Routing Usage Summary". Those will show you the % of routing resources used by the design.

Additionally if you constrain your design in a LogicLock region (you can create them in the Chip Planner), you can get view statistics on the LogicLock region which include resource and routing utilisation.