Large Frequency Divsion
A 57.5 MHz clock frequency is going to be a challenge for you. First, you will have to take your clock and run it through a high-speed comparator to give you a signal of about 0 to 5 volts. Fortunately, this doesn't have to drive a terminated line as long as the load line is less than, let's say, 1 foot.

For this frequency, a 74HC4040 will simply not work. It's only guaranteed to work to 30 MHz, and for this sort of thing you do not want to depend on "typical" numbers, even though the data sheet gives this as 82 MHz.

What you can do is provide a 2-step function, using a prescaler to drop the clock frequency to something more convenient. Along this lines, you should analyze your divider ratio in terms of the accuracy you actually need, and work within that range, rather than taking your nominal ratio as set in stone.

In your case, for instance, if you go to a divider ratio of 25352 (which will give a nominal output of 2268.02 Hz - close enough?) this equals 8 times 3167. You can use a high-speed counter such as a 74AC161 as a divide-by-8, which will then feed a slower, longer divider which handles the 3167 part. It can do this since $$\frac{57.5 MHz}{8} = 7.19 MHz$$ and this is well within comfortable limits.

Secondly, DO NOT TRY TO USE A 4040 for the long divider. 4040s are very useful as a compact source of factor of 2 division. For this usage, a 4040 of any family is a truly horrible choice and a disaster waiting to happen unless you really know what you're doing - and with all due respect you don't. For a divider ratio in the range of 2049 to 4095 I would not recommend trying to use it at a frequency of more than about 4 MHz with a tricky design and not more than 2 MHz for a relatively simple design. The problem is that a 12-bit count will need about 240 nsec maximum to complete the count, and during this period will provide false values to the reset circuitry. Depending on the exact divisor selected you'll either get a stable wrong division ratio or a weird, inconsistent mish-mash of wrong ratios. Neither is good.

The following circuit ought to work. It uses 5 ICs and is about as compact as you'll get.







simulate this circuit &ndash; Schematic created using CircuitLab

EDIT It is also possible to do away with a separate decoder, but not an external gate. This will take a little bit of thinking. Let's start with a single 4-bit presettable counter such as the 74HC161/163. The general connection is 







simulate this circuit
and the question is, what should happen to the presets? Note that when the counter reaches 1111 (15 in binary), the next clock will preset it. So, let's say that you want to create a divide by 3. If you preset to 13, the count sequence will be 13,14,15 (issue preset), 13,14, etc. The preset code will then be 1101. Now, here's the trick. If you take 3 (the desired ratio), and subtract 1, you will get 2. The binary code for 2 is 0010. If you invert each bit, you'll get 1101, which is the desired preset code.

So the rule for calculating preset values is 1) find the desired division ratio, 2) subtract 1, 3) invert all bits. Oh, and then there's 4) determine the largest bit which toggles, and use that as your divider output. Here the rule is, find the leftmost (most significant) bit in the binary ratio which is set to zero, and use that. So in the case of a divide by 3, you would use QB out of the counter.

The reason that you need the inverter is that the toggle carry is active high, but the load input is active low. There are some counters, such as the 74HC/AC191, 169 and 669 which have an active low TC output, and you can look into them if you like. 

For dividers with more than 4 bits, you just connect each TC output to the ET output of the next stage. 

For your use the circuit will look like







simulate this circuit
and I will leave the calculation of the preset inputs up to you.