D flip flop with asynchronous reset circuit design
The wire in red is to make sure that the D input is overridden with a logic 0. This makes sure both sides of the master FF are reset at the same time. This also overrides the state of the clock input.
Now S and R will clear the slave latch so it is in the proper state. S is forced to '1' and R is forced to '0' at the same instant, thus Q is forced to '0' and Q\ is forced to '1' at the same instant. Q and Q\ can NEVER have the same state at the same time.
Since the rising edge of clock is used to load in the value at the D input which briefly causes both master R-S latches to toggle states (They are cross-wired so the value of D is sampled and locked into the latches in nanoseconds, or even picoseconds), both master R-S latches must be cleared at the same instant or a glitch could appear at R and S that briefly makes the slave latch put out glitches.
The operation of the reset pin should be clean and glitch free at the Q and Q\ outputs. If Q is set to 1 then a reset should clear it to 0 and Q\ becomes 1 with almost no skewing.
That is another reason for the extra reset connection. Data is supposed to be loaded in with almost no skewing in time between Q and Q\ changing states, so RESET has to work the same way, or downstream logic could be confused. These  flip-flops are often used to sync data from a asynchronous source by using 2 in series with a common clock, so internally created glitches would never be tolerated. This could cause havoc and miss-counts in ripple-carry counters where many FF's are daisy-chained in a row.