Why is my Verilog code for Mealy-type sequential circuit not working?
The real problem is that in a Mealy machine, the output(s) need to be registered, too — in addition to the state variable(s), that is.
Also, the assignment S0 = 2'b01 &amp;&amp; 2'b10 works, but not in the way you expected. The &amp;&amp; operator is true (one) if both of its operands are true (nonzero). Since both 2'b01 and 2'b10 are nonzero, this assigns 1 to S0. Since S1 is 0 and S2 is 3, it all works out.