Verilog - Referencing Flattened Busses in Module Instantiation
It seems like you are running into Verilog's Escape identifiers gotcha:


  §2.7.1 Escaped identifiers
  
  Escaped identifiers shall start with the backslash character () and
  end with white space (space, tab, newline). They provide a means of
  including any of the printable ASCII characters in an identifier (the
  decimal values 33 through 126, or 21 through 7E in hexadecimal).
  
  Neither the leading backslash character nor the terminating white
  space is considered to be part of the identifier. Therefore, an
  escaped identifier \cpu3 is treated the same as a nonescaped
  identifier cpu3.


So not only you need to properly write down escaped port name, but you also need to make sure you don't forget to put a whitespace at the end. For example:

DES_SBOX1 feistel( .CLK(CLK_tb),
                 .\ptext[5] (ptext_tb[5]),
                 .\ptext[4] (ptext_tb[4]),
  ...


Hope it helps. Good Luck!