Impedance mismatch as internal signal layers cross multiple power planes
What you can do is something roughly like this:


Top Copper
2.5 mil dielectric
GND
z mil dielectric
Signal
x mil dielectric
PWR
y mil dielectric
PWR
x mil dielectric
Signal
z mil dielectric
GND
2.5 mil dielectric
Bottom copper


Minimize y and maximize x. Pick z to get 50 Ohms with a 4 mil trace on the inner signal layers. If x is much larger than z then the inner signal layers will be referenced more strongly to GND than they are PWR. If you don't need 50 Ohm traces (if you can accept lower than 50 Ohms), you can make the 2.5 mil and z mil dimensions even smaller.

You should find an online stackup calculator and play with it a bit. There are also constraints on total board thickness. The "standard" thickness is 0.063" which is more or less 1.6mm. If you deviate from this too much, it may make board assembly more difficult for the assembly house (check before you commit to doing it).