How does the current pass through FET when its gate is unbiased/grounded in AC analysis?
why drain voltage increasing with source voltage.

That (I assume) refers to the plot. It seems Vsource is swept from 0 to 1 Volt.

The gate voltage is kept constant at 5 V.

=>  That means Vgs decreases from 5 V to 4 V so the NMOS is (gradually) turned "off" (not fully off but "less conducting").

That means less drain current will flow. That means that the voltage across R3 decreases. That means that the drain voltage of the NMOS must go up.

when the gate is at ground it means the FET is at cut off.

Not always! What if I ground the gate (= 0 V) but bias the source at - 5 V. Then Vgs = 5 V right? Is the NMOS off or not ? (I'm assuming that the bulk of the NMOS is connected to the source).

So the FET isn't off when Vgate = 0, it is better to remember that the FET is off when Vgs = 0. (only true for enhancement, "normally off" FETs)

But that's not what is happening here. Indeed the gate is shorted to ground for small signal. But don't forget that the gate is also biased at + 5 V DC (note the "5" near Vg).

Here the signal isn't applied at the gate but at the source ! This is the same as in the DC simulation where Vsource is swept. So yes, the gate is grounded (for signals) but the source voltage directly follows the signal!