Why would a designer choose to use two AND'ed input shift register such as the 74HC164?
The 1st scenario that comes to mind is capture/compare for 2 signals over 8 stages.
Such device can be used in a quadrature decoder, allowing the MCU to have 1/8 interrupt rate compared to a single AND gate.

At each clock pulse, a new comparison is made, after 8 pulses, you have your result. With some extra logic, you can implement states where at least m comparisons out of n are 0 (n&lt;=8) and so on. 

There is already an input enable signal, the CP pin.