How to split Analog and Digital GND planes for a TQFN device
Sorry, my bad. I posted this image from the CY8C32 datasheet into my answer to the other question:  



but didn't copy the caption. "Figure 2-8. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance". This is for the TQFP100 part, which doesn't have the thermal pad, and doesn't apply to the QFN48 you're using.

For parts with a thermal pad the split makes no sense, and you should connect the thermal pad to digital ground.


  The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
  ground, it should be electrically floated and not connected to any other signal. (page 6)


Note that when you use a thermal pad on your PCB that you shouldn't apply solder paste all over it, but use a windowed stencil to avoid the IC being pushed up by the solder paste:




  "The solder paste pattern area should cover 35 % of the solder land area. When printing
  solder paste on the exposed die pad solder land, the solder paste dot area should cover
  no more than 20 % of this solder land area. Furthermore, the paste should be printed
  away from the solder land edges. This is illustrated in Figure 9; the solder paste pattern
  area lies within the boundary indicated by the red line and it is divided by the entire solder land area." (from here)



Further reading
CY8C32 datasheet
HVQFN application information, NXP application note