Will the High-Level Synthesis (HLS) design approach for FPGAs reduce the demand for RTL designers?
Eventually, the compiler more or less wiped out the assembly programmer. But it took a long time, and there are still a few paid ones about, optimising high speed functions to the Nth. There are more hobby ones about, doing it the hard way for the fun of it.

Eventually, HLS will more or less wipe out the RTL level designer. But it will take a long time, and there will still be a few paid ones about ...