Does modelsim support shift right arithmetic in verilog?
It does, however you need to make temp a signed value and do not specify the range when using the arithmetic shift. Specifying the range in the arithmetic shift casts a unsigned value.

reg signed [31:0] temp;

always @* begin
   temp = 32'hfff00fff;
  result[31:0] = temp &gt;&gt;&gt; shamt[4:0];
end


Alternatively, you can cased it as signed with $signed

reg [31:0] temp;

always @* begin
   temp = 32'hfff00fff;
  result[31:0] = $signed(temp[31:0]) &gt;&gt;&gt; shamt[4:0];
end


Working example(s) here