Is $realtobits synthsizeiable?
Simple answer. No, I don't think it is.

There is a very useful online reference/help document which has pages describing Verilog constructs and syntax. It has a page on the $realtobits function, which state


  Conversion functions are not synthesizable.


I can't vouch for the accuracy of the source, but it makes sense. The Verilog $... functions tend to be helper functions for things like memory initialisation, displaying in simulation, etc. as opposed to actually synthesisable constructs. This isn't always the case - things like $signed are synthesizable as far as I know. 

Furthermore, the complex data types, like real, time, and event are also not synthesizable. From that standpoint it therefore makes sense that anything involving converting to and from them cannot be synthesized.



As @PeterGreen points out in the comments, whether a construct is synthesizable comes down as much as anything to the synthesis tool. As you specify Xilinx as a tag, you can refer to the XST User Guide. 

Table 7-33 on page 518 of that document - in a section titled "Verilog System Tasks and Functions Supported in XST" - it is clearly stated which system functions are supported and which are ignored.

$realtobits is not listed specifically in that table, so it falls under the final entry which says: All others: Ignored, indicating that it is not supported by the tool.