vhdl port declaration with different sizes
It uses an array of sizes to specify the individual sizes of EntityB. The port of EntityA has the size calculated by sum.

The matching bits are sliced by high and low.

global function:

function sum(SIZES) is
  variable count : integer := 0;
begin
  for i in SIZES'range loop
    count := count + SIZES(i);
  end loop;
  return count;
end function;


Example:

entity EntityA is
  genierc (
    SIZES : integer_vector
  );
  port (
    data(sum(SIZES) - 1 downto 0)
  );
end entity;

architecture rtl of EntityA is
  function high(SIZES, idx) is
  begin
    for i in 0 to idx loop
      pos := pos + SIZES(i);
    end loop;
    return pos - 1;
  end function;
  function low(SIZES, idx) is
  begin
    for i in 0 to idx - 1 loop
      pos := pos + SIZES(i);
    end loop;
    return pos;
  end function;
begin
  genB : for i in SIZES'range generate
    instB : entity work.EntityB
      generic map (
        N =&gt; SIZES(i)
      )
      port map (
        data =&gt; data(high(SIZES, i) downto low(SIZES, i))
      );
end architecture;


Usage:

signal input : std_logic_vector(13 downto 0);

ex : entity work.EntityA
  generic map (
    SIZES =&gt; (2, 3, 4, 5)
  );
  port map (
    data =&gt; input
  );