A-D conversion: effect of adding more bits
Whenever a continuous signal is encoded into a finite number of bits, there will be some quantizing noise.  This is the error introduced because not all possible input values can be accurately represented by the digitized signal.  For example, assume that an analog signal ranging from 0V to 5V is digitized using a 2-bit ADC. Using equal step sizes, this might be done as shown in the table below:
$$
\begin{array}{cccc}
  {\bf voltage} &amp; {\bf binary} &amp; {\bf code} &amp; {\bf output} \\
     0 \le v &lt; 1.25  &amp; 00 &amp; 0 &amp; 0.0 \\
  1.25 \le v &lt; 2.50  &amp; 01 &amp; 1 &amp; 1.25 \\
  2.50 \le v &lt; 3.75  &amp; 10 &amp; 2 &amp; 2.50 \\
  3.75 \le v &lt; 5.00  &amp; 11 &amp; 3 &amp; 3.75 \\
\end{array}
$$

If voltage of 2.0V is digitized, it is encoded as 01 binary, but so would voltages of 1.26V or 2.48V.  If we convert back to analog, all of them would result in an output voltage of 1.25V according to the scheme above.  The difference between the sampled voltage and the corresponding output is quantizing noise.

It's easy to see that adding bits adds resolution and reduces quantizing noise.

As for sampling frequency, there is a thing called the Nyquist-Shannon sampling theorum that states to be able to successfully reproduce any digitized signal, one must sample at no less than twice the highest frequency you wish to reproduce from the input.  This is independent of the number of bits one uses to digitize.