VHDL: case when using constants constructs
I'll turn my comment into an answer (Last night it was very, very late).

The case statement itself will do the comparison. Thus another comparison is too much. The correct syntax is:

if spi_ctr = 9 then
        case spi_op is
            when op_get_r_count =&gt; spi_reg_out &lt;= ref_count_i;
            when op_get_s_count =&gt; spi_reg_out &lt;= sig_count_i;
            when op_get_g_limit =&gt; spi_reg_put &lt;= gate_limit_i;
        end case;


If this code is inside a rising_edge(clk) section it is fine as it is.
However if it is outside a clocked section you can get latches. (Not only from the case but also from the if).
In that case you should add a when others =&gt; spi_reg_put &lt;= ... but also an else ... section.

Last remark: it is useful to be able to distinguish constants from variables. 
There are several methods.   

Using something like 'const', 'cnst' or 'c_' in the name:
constant    const_op_get_r_count: std_logic_vector(7 downto 0)    :=  "00000001";

Or follow the Verilog and C convention to use capitals:
constant    OP_GET_R_COUNT: std_logic_vector(7 downto 0)    :=  "00000001";

A colleague of mine prefers both:
constant    C_OP_GET_R_COUNT: std_logic_vector(7 downto 0)    :=  "00000001";