Should the vias for decoupling capacitors touch the pads of the capacitor or not
If you don't want the solder to be sucked into the via, then the via has to be a bit away from the pad, and a solder mask sliver between them, but you could:

move the vias so they're closer together to reduce via pair inductance, they don't have to be aligned with the pad centers

widen the trace from the via to the cap pads to reduce trace inductance, I mean the trace can be as wide as the via and the pad, that doesn't cost extra ;

widen the trace from VDDA pad to cap pad (again, lower inductance, although it's very short)


Here's a FingerPaintCAD example, a bit ugly but you get the idea, just apply a wider trace width...

If it is super important that this pin has a very low inductance to ground you can also use a lower inductance cap (LLL, NFM). But I don't see a GND pin next to it, which means the manufacturer of the chip didn't think there was a need to create a low inductance power/ground pair, so most likely it does not need any fanciness.