Bandwidth and Data Rate FSK Demodulations
Without focusing on the circuit design, Is there any limitation on the
  rate at which I can transmit and receive this signal correctly?


The detector may take some time to reach 0.11 volts from 0.10 volts - this may be nano seconds, tens of nano seconds or hundreds of nano seconds etc.. Given that you have proposed no detailed design, then you have to decide what that factor is and, if you change the data too fast you may have a scenario where the DC output is slewing (say) between 0.104 volts and 0.106 volts for a continuous stream of ones and zeros. 

At this point you ask yourself if any occurrence of noise could force 0.104 volts to be closer to 0.106 volts and produce an error in the received bit-stream. Then you ask yourself what bit error rate you can tolerate.