Significance of -1 slope in CMOS inverter transfer characteristics
This seems to be the standard textbook definition of VIH and VIL. Using a slope of -1 as the limit makes more sense if you think of inverters as amplifiers and remember that the input will have some noise:







simulate this circuit &ndash; Schematic created using CircuitLab

Going back to your graph, if the input voltage is between VIH and VIL, any noise will be amplified. If the signal passes through many gates (which it probably will), the noise could be amplified enough to flip a bit. This leads to the definition of the noise margins for the inverter:

$$NM_H = V_{OH} - V_{IH}$$
$$NM_L = V_{IL} - V_{OL}$$

Or at least, that's my understanding. I found some sources that said choosing a -1 slope as the threshold maximizes the sum of the noise margins \$(NM_H + NM_L)\$, but I'm not sure how that works.

There seems to be a lot of debate among textbooks and academics about how best to define \$V_{OH}\$ and \$V_{OL}\$. Some sources define them as the extreme limits of the output voltages, while some use the same -1 slope definition as the input thresholds. (The latter seems to be more formally correct.) I even found an IEEE paper which claims that all of the definitions are wrong, including the input thresholds! 

I don't have a resolution to all this except to say that the significance of the -1 slope definitely has to do with noise margins. I believe that answers the original question.