Type bit does not match with the integer literal while converting integer into bit_vector
To answer your specific question: the to_bitvector() function from std_logic_1164 only takes one input, a signal of type std_ulogic_vector or std_logic_vector. If you search for the function name you find documentation like this which gives the interface

function to_bitvector ( s : std_ulogic_vector ) return bit_vector;


So change your code to this and it should work (though I haven't tested):

for i in 0 to 5 loop
    x_std(i) &lt;= conv_std_logic_vector(x_int(i),14);
    x_bit(i) &lt;= to_bitvector(x_std(i));  --should compile
end loop;




As to why the functions take different inputs, the conv_std_logic_vector function requires a length parameter as the integer type has no specific length. The length parameter tells the synthesiser how wide a std_logic_vector is created by the function. VHDL is strongly typed and the length of the signal returned from the function is then checked against the left hand sign on the assignment (x_std(i)) to ensure they match. 

Conversely, the to_bitvector function simply goes through each element of the array in turn performing a mapping from std_logic to bit and the returned array width is therefore defined by the width of the input array.

It's also worth looking into using VHDL attributes as the length input to conversion functions. This code won't break if you decide to change the width of x_std() and x_bit() later:

x_std(i) &lt;= conv_std_logic_vector(x_int(i),x_std(i)'LENGTH);