Quick digital receiver for Manchester encoded data?
Sampling asynchronously is probably not the best way to deal with this because the sample rate is only a few times higher than the data clock rate. It's Manchester encoding and the main bonus is that you get the clock for free (well, almost) and it's dead easy to make an edge detection circuit from an exor gate and a small delay: -



Here you get a pulse for each edge present in the signal and, if you set a counter running that is maybe 16 times higher than the data clock rate you can position your sampling point at count number 8.

At that point carry on counting and if you don't receive a counter reset (due to lack of a clock pulse) you sample the data at count 24 for the next bit. Manchester encoding is more accurate than asynchronous UART data because clock is embedded into the data and you get far more transistions than can be expected with plain ordinary asynchronous data.

Here's what you are proposing and note the error you can get if your fast clock is only 4 or 8 times the data clock rate: -



I've drawn a red arrow where asynchronous data timing starts to hit a problem - UARTs will sync up their clock on every edge detection thus always minimizing this error.

I've implemented this type of system in FPGAs running non-manchester encoded signals (no embedded clock and thus far fewer clock edges) at speeds up to 50 odd Mbpsec. I've used data scrambling to enhance the number of clock edges but manchester decoding should be a breeze.