How should entites and architectures in VHDL be commented?
In VHDL and in everything, there is never too many comments. Comments save a lot of time when somebdy else needs to continue your work, or interface it, or just understand it. Thus, each entity, signal and process needs to be explained. 

There are also others convention, such as naming and make your code as clear as possible by indenting, align the entity port etc.

[EDIT]

You need to explain the entire module (entity + architecture) : what is it for, how does it work, how does it interface with other modules. Then you can specify the program developement unit, file, device, and autor of the module. You can inlcude an history, and what Tools do you use for simulation, synthesis, routing, how long should you simulate.

For the entity you explain what is it for and how does it work.