Error: HDL-Complier-661 Non-net port cannot be mode of input
Verilog does not allow input ports declared as a variable with a data type (SystemVerilog does).You can remove that line. I also suggest using a simpler form of port declarations that only mentions each port name once instead of up to three times (called ANSI style in the IEEE LRM)

module right_shifter(
    input [3:0] small_mant,
    input [2:0] shift_amt,
    output reg [5:0] shifted_mant
);