Asynchronous Cascaded Counters Problem!
When the bottom counter gets to "8", it'll send a positive edge to the upper counter's clock\ input. That won't do anything, however, because the upper counter is negative-edge triggered. Then, as soon as the bottom counter gets to "9", it'll reset itself and the upper counter, so "Z"s output frequency will be 0Hz and its duty cycle will be 0%.

Update:

Just for fun, I redrew your schematic with the RESETs wired to make a divider, added a power-on RESET to make it start up in a known state, and simulated the circuit. The schematic and the "Z" output plot are shown below, and if you want to simulate the circuit so you can play with it, (LTspice) here are the files you'll need.

Just copy them all into the same folder and left-click on the .asc file. 

If you have LTspice installed on your machine, it'll start and automagically bring up the schematic editor with the timer schematic already loaded.  If you don't, you can get it, free, here