How to find the Nyquist-/sampling frequency of a Sigma-Delta-ADC
This Sigma Delta converter uses over-sampling to obtain the resolution then decimation to reduce the signal BW which is \$f_{ADC} /2\$ maximum Nyquist rate. It has a built in SINC filter to notch desired grid e-field noise from unbalanced signals.

Analog and digital anti-aliasing
A typical choice might be 64x oversampling, in which case the ADC will sample at 64 x fADC kHz.  Then the digital Nyquist frequency is 1/2 of that .  However the Analog anti-aliasing filter still needs to have its -3 dB rolloff at fADC/2 , but it does not need to be -97 dB down until 32 x fADC.  That is a much easier filter to design.  In fact, a 3-pole filter, easily and cheaply implemented with an op amp, is sufficient.
So the answer is the fADC /2 Nyquist Rate is your 3rd order Analog Filter. This is how almost all SD ADC 's work with oversampling and decimation with simpler requirements for the Nyquist filter. (Some RF types use the above Nyquist BW as the passband like old GHz scopes with stable sub-nanosecond samples to achieve GHz BW in a lower sampling rate than the signal..)
Enabling certain sampling rates with Zero Latency On achieves twice the signal BW while using the built-in SINC filter creates a harmonic notch filter at 4x the SPS (sample per second) ADC net rate. Certain combinations allow for notches at 50,60 or both line frequencies.
Therefore when you specify your signal BW and noise BW attenuation requirements with Passband ripple and group delay flatness BW, you can choose any filter to meet these requirements.
e.g. if fADC = fCLK/(4 × 32 × FS[10:0]). and you want a Bessel flat group delay response to fADC /2 or /3 choose that and the order, n  of the filter depends on the n x 6 dB/ octave rejection slope in your Bandstop noise rejection to prevent aliasing.
If you need more rejection above ADC/2 rate use Chebychev and decide on acceptable PB ripple.  There are other variations of filters that compromise ripple and GD determined by your specs.
Consider 20 SPS as your fastest fADC if you want to reject 60Hz and enable Zero Latency.
Define your S/N input and output spectral requirements first include. GD flatness and ripple. (Before designing anything)