Why do dual-rank DIMMs have twice the bandwidth of quad-rank DIMMs?
I believe this is due to higher electrical loading on the data lines (more capacitance).  It is more difficult to drive data over the memory bus with the extra load, so it has to slow down.  This is also why putting more DIMMs per channel limits the speed.  

Edit: take a look at page 15 of this PDF: http://www.nanya.com/NanyaAdmin/GetFiles.ashx?ID=493

All of the DQ pins (data) from all of the chips are connected in parallel, increasing the load capacitance on the data lines.  The increased load capacitance slows the rise time of the data lines and limits the maximum rate.  The only registered lines are those that drive the address, control, and clock pins on the chips.  Registers are not used on the data lines because the data bus must be able to 'turn around' very quickly.  The address control, and clock pins only run in one direction.