implementation on write-first single-port ram
Here, how can we assure that output do is changed after RAM[addr] &lt;= di; is executed?


Because  assign do = RAM[read_addr]; will be executed when any of its signals change. Thus it will be called when either read_addr changes or if RAM changes. 
This makes that the do output follows both the address but also reflect any writes which happen. 

The reg read_addr makes sure that the data of the last read stays on the output if addr changes. That is needed because addr must be ignored if there is no enable and if there is no clock.

The whole code builds a memory with a certain behavior. It may just not be the behavior you where expecting. 



I hope the code formatting is not the original one. It is very sloppy. Also nowadays you should use modern port definitions:

module raminfr (
   input clk, // Memory synchronous clock
   input we,  // Write enable
   input en,  // Enable for both read and write
   ....


Adding the comment makes clear what each signal does. Thus it tells the user that the en is required for read and write. Otherwise she/he has to go working through the code to find out.

Final remark: just because you find some code which works don't assume it is the best there is.