What is the critical path in the design?
Where did these diagrams come from? If the white trapezoids are meant to be ordinary 2:1 multiplexers, then this is not a correct implementation of a carry-bypass adder. The carry input to each 4-bit stage needs to be the logical OR of the mux output and the carry output of the previous stage.

The actual longest path through the whole design is from the inputs of the first stage (on the left) to the sum output of the 16th stage (on the right), following most of the orange path, but not through the final mux.

The logic after each stage should look like this:

$$C_{o,stage} = C_{i,n}\cdot P_{n}\cdot P_{n+1}\cdot P_{n+2}\cdot P_{n+3} + C_{o,n+3}$$