Why 60% overshoot with 55° phase margin?
I would go with Hypothesis 2.

I think, you have simulated the loop gain correctly. The input impedance at the inv. input seems to be much larger than the combined source impedance of the remaining network.
I recommend to make another test and select another point for placing the test signal source: Between the opamp output and the common node of C2 and Riso. The result should be (nearly) the same as in your first simulation.

However, I tend to Hypothesis 2 because the known relation between overshoot and phase margin applies to second-order systems only. However, your system is of higher order (opamp 2nd order, FET 1st or 2nd order, two external capacitors).
More than that, the simulation results clearly show an enhancement of the phase caused by C1 (improving stability). The mentioned relation between time and frequency domain does not allow such a zero.

UPDATE: I think, the form of the step response confirms my analysis: It does not show a typical "overshoot" (which should exhibit some ringing for such a large peaking). Instead, it shows the typical form for a step response of a highpass (caused by the capacitor C1)