FPGA power input isolation
One possible technique is to take advantage of a commercial test instrument.  Specifically, I'm referring to something called a "Leak Seeker" from Electronic Design Specialists (EDS).  If you do your PCB layout such that the power pin(s) for each FPGA is available on a via as close as possible to the chip, finding shorted chips is relatively easy.  If the FPGA chips are fed from a power plane in the PCB, ensure that the plane feeds this via from a short trace and that the via is what feeds the power pins for the chip.

The Leak Seeker is a device that is used for finding shorted components on PCBs.  The original version is a primarily analog design that injects a small test current into a node on the board, then uses a sensitive voltage-controlled oscillator to guide the user to move the test probe along the trace searching for the short.  I have one and it works very well.

The unit has been recently updated and I don't have any experience with the new version.  However, the original version was capable of finding shorted chips even if those chips were being fed from a dedicated power plane in the PCB.  Leek Seeker page

The reason for having a dedicated via for each chip is that gives you an easily measured point when tracking down damaged chips.  The real advantage to this technique is that no extra components are required.