Maximum cells in a row in a SRAM memory array
You also have to worry about driving long bit lines that run orthogonally to the word lines, and the delay of a long wire is proportional to the square of the length.

Therefore, memory arrays are typically designed to be more or less square so that neither the word lines nor the bit lines cause unacceptable delay. The number of bits in a row may be much more than the number of bits in the output word, and the actual desired bits are then demultiplexed from the wide row.