Separating Two High Speed Digital ICs
40 MHz corresponds to a wavelength of 7.5 meters. So long as you limit your driving rise and fall time to avoid exciting high harmonics, you should be able to transmit over 10 inches (~25 cm) without thinking too much about transmission lines and controlled impedance.


  Are IDC ribbon cables sufficient at 40MHz? 


For this distance, I'd say yes. Provide as many ground lines as you can afford to to avoid cross-talk between lanes and reduce radiation and interference.


  Will my FPGA (and especially the ADC) even be able to drive the 10" cable?


You can work out the capacitance of the line and check it against the FPGA datasheet to see.

Or you can just buffer with a 74LVC244 or other logic buffer part and you'll be good. I would provide a location for a series resistor at each output to allow you to increase the rise and fall times if needed.


  However in the timing section they specifiy 100Kohm load outputs.


In this case (for the ADC outputs), buffering is probably a good idea.