what exactly is single cycle instruction architectures?
The only way I know to make read and write happen in the same clock cycle is for register reads to be triggered on positive edge and register writes to be triggered on negative edge(or vice versa), and then to make it so that your data path logic fully propagates within a half clock period. In a single cycle architecture, it's really just a semantic difference, a bit of trickery.

In more sophisticated clocking schemes, you might actually have multiple clock phases, so the 'edge triggering' relationship need not be symmetric as I've described it.  When your core is pipelined, this actually matters for correctness purposes so that you don't have a race between your register read and writeback stages.

I think you are justified in being confused about how reads and writes are related in the register file, but that requires you to dig a bit deeper into the transistor level implementation of a single-bit register. I think you will find that there is a race if both events (read and write) are triggered by the same clock edge and your combinational logic can propagate a change before the register state is fully latched. Have a look at this webpage for a logical deconstruction of an edge triggered D flip flop.