Implementing a simple counter using VHDL
I have just corrected your syntax errors.
From design point of view in a synchronous process you must have just one member in the sensitivity list. (here its name is CLK)
remember that you are not allowed to use risingedge for a signal that is not in the sensitivity list and it is not a good practice to have more than one clock pulse signal in a process.
It is the corrected code:

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity lab5 is
    Port ( Abbreviate : in  STD_LOGIC;
           Halt : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           LED_left : out STD_LOGIC_VECTOR(6 downto 0);
           LED_right : out STD_LOGIC_VECTOR(6 downto 0));
end lab5;
architecture Behavioral of lab5 is
type State_type is (two, three, one, six, zero, seven);
signal state : State_type := two;
signal state_right : State_type := six;
signal first_time : integer := 1;
begin
process(clk)
begin 
  if (rising_edge(clk)) then
     if Abbreviate ='1' then
        first_time &lt;= 1;
     end if;
  end if;
  if(rising_edge(clk)) then
      case state is
        when two =&gt;

        if (Halt = '1') then
          state &lt;= two;
          LED_left &lt;= "1111001";
        else
          state &lt;= three;
          LED_left &lt;= "1101101";
        end if;
        when three =&gt;

        if (Halt = '1') then
          state &lt;= three;
          LED_left &lt;= "1101101";
        else
          state &lt;= one;
          LED_left &lt;= "0100100";
        end if;
        when one =&gt;

        if (Halt = '1') then
          state &lt;= one;
          LED_left &lt;= "0100100";
        else
          state &lt;= six;
          LED_left &lt;= "1011111";
        end if;

        when six =&gt;

        if (Halt = '1') then
          state &lt;= six;
          LED_left &lt;= "1011111";
        else
          state &lt;= zero;
          LED_left &lt;= "1111110";
        end if;

        when zero =&gt;

        if (Halt = '1') then
          state &lt;= zero;
          LED_left &lt;= "1111110";
        else
          state &lt;= two;
          LED_left &lt;= "1111001";
        end if;
        when others =&gt; null;
      end case;

      case state_right is
        when six =&gt;
        if Abbreviate ='1' then
          if (first_time = 1) then
            if (state = two) then
              state_right &lt;= six;
              LED_right &lt;= "1011111";
              first_time &lt;= 0;
            end if;
          else
            state_right &lt;= seven;
            LED_right &lt;= "1100100";
          end if;
        else
          state_right &lt;= six;
          LED_right &lt;= "1011111";
        end if;

        when seven =&gt;
          state_right &lt;= six;
          LED_right &lt;= "1011111";
        when others =&gt; null;
      end case;
  end if;
end process;
end Behavioral;