Why is there a limit on the number of inputs a logic gate can have?
Repeat that line of reasoning with a 4 input gate...

So if I compare 4 input vs 2 input, delay for 4 inputs would be 4N, while using three 2 input gates would result in 3*2N = 6N

As shown on the left here.



simulate this circuit &ndash; Schematic created using CircuitLab
Arrange them as a tree; 2 gates processing 4 inputs, the third combines their results. Each 2 input gate has delay 2N, the overall delay is 4N matching the 4 input gate (middle example)
Now repeat for 5 and more inputs : 5 inputs has a tiny advantage, 5N delay with a direct implementation, or 6N with the structure on the right. But perhaps you can see that at 8 inputs, the direct implementation is actually slower (8N) than the 6N implementation on the right.
So it's not that higher gates are difficult or impossible; it's that there's no general advantage, and in many cases the result is slower than a tree of 2 input gates.
Incidentally I can buy an 8 input gate (74LS30), but I can't recall seeing anything larger (though a 13-bit gate, 74LS133, is mentioned in the comments)