DDR4 clock termination
Let's assume you're referring to this type of clock termination (simulate it here):

This provides 50 ohm single-ended termination for each signal as well as 100 ohm differential impedance. So all good stuff.
So, why AC clock termination at all? It reduces power consumption somewhat vs. DC termination: the only power it uses is in the termination resistor network itself, there is very little current flowing in the cap (only imbalance.)
AC termination also gets voltage dividing out of the picture which reduces noise (more below).
As far as which voltage to tie the AC cap to, my opinion is that ideally you want the quietest, lowest-impedance connection to achieve the best clock signal integrity.
Looking at your choices, and my takes on them:

Ground: very low impedance, low noise. Best choice
Vtt: medium-low impedance, low-ish noise, convenient. Good choice
VddIO: medium-low impedance, high DQ I/O transients: Not a good choice
Vdd: low impedance, very high core transients. Not a good choice, probably the worst

Note that a voltage-divider DC clock termination (50 ohm single-ended Thevenin type) using VddIO or Vdd will inject supply and transient ripple into the termination voltage. While the differential clock input will reject some of this noise, it's still not desirable.