Constraining a 7 segment display in VHDL
An example constraint would  be

inst "led0" LOC=A1;


You have to lock down each of the 7 bits separately.

p.s. This is vendor-specific. It isn't part of VHDL.

More detail on UCF files: http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/cgd.pdf