Why Positive-going clock transitions used in certain ICs
Note that in the specific example of the '174 that you show, the flip-flops themselves are shown with inverted clock inputs (falling edge), so the net effect of the inverting buffer is to make the chip overall work on the rising edge of the clock.

As Tim Wescott mentioned in a comment, this sort of detail is normally related to the internal implementation technology. The only thing you care about when using the chip is the behavior relative to the signals at the pins.

As a historical oddity, D flip-flops normally work on the rising edge, because that's how most users prefer to think about their data registers. But J-K flip-flops normally work on the falling edge. That's because they were often used to build ripple counters (tie the J and K inputs high to create a T flip-flop) and you want the next-more-significant bit to toggle on the falling edge of the previous bit. In general, you'll find that ripple counters ('90, '92, '93, etc.) work on the falling edge, while synchronous counters ('160, '161, '162, '163, etc.) generally work on the rising edge. This allows both types to be easily cascaded with themselves.

But in the end, there's no technical reason to pick one convention over another. There's nothing "more natural" about either one &mdash; it's just an arbitrary choice.