How do you determine what the circuit that determines the next state looks like?
The truth table does not imply a sequential input, just a combinational input

The logic design method is simply Karnaugh Map reduction or boolean simpliciation.

You can use Q=1 or Q'=0  since there are 9 rules where Q=1 and 7 rules where Q=0. 

I chose the fewer Q'.  Using Q=0 s in the output gate uses Q' output = 0 implies using a  NOR gate which is preferred to OR gate since it has lower latency with 1 less inverter.

Since there are 4 groups a 4 input NOR gate is one possible solution.  There may be further simplication, but there is no sequential input implied.

This result could be implememnted with programmable logic or many gates in discrete form.

A 1st cut graphical simplication looks  like this.