Add with carry in VHDL + operator
ieee.numeric_std will provide a result the length of the left operand. You could concatenate a leading sign bit or zero bit (for unsigned) with the left operand to produce your 65 bit result. 

A look through the source for Synopsys' std_logic_arith shows it's "+" does the same thing. 

Library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
use ieee.std_logic_arith.all;

entity adder65bit is
    port (
        a,b:    in  unsigned(63 downto 0);
        carry:  out std_logic;
        sum:    out unsigned (63 downto 0)
    );
end entity;

    architecture foo of adder65bit is 
    signal temp:  unsigned(64 downto 0);
    begin
        temp &lt;= '0' &amp; a +  b;
        sum &lt;= temp (63 downto 0);
        carry &lt;= temp(64);
end architecture;


You didn't specify signed or unsigned, this is unsigned, the operands and the results can be ether signed or unsigned instead.

This code analyzes, elaborates and simulates. It works be setting the left operand to be 65 bits long. You mentioned carry so it's shown with one in a method compatible with earlier VHDL tool implementations.

Note the "&amp;" and "+" operators have the same priority, they will be executed in the order they are found left to right.