Pipeline design and timing issues
After talking to quite a few people, I think we found the proper solution to the problem.

The stage B, which has its own state machine, should not have a VHDL process activated on rising edge. It should have the state of the state machine as a signal that is stored on register R.

In more detail, these new signals should be added:


stat: current state of the state machine, output from R, input to B
state_next: next state of the state machine, input to R, output from B


Which means that state is changed for state_next each rising edge, and B can now work without a process.