What is the meaning of fault_reg = ram [address] in verilog?
Here, address is four bits wide and ram is declared as reg [3:0] ram [7:0];. This declares a memory as nibble (4-bit) wide and such 8 nibbles. 

As shown in below figure. 



In order to fully address all the 8 memory addresses, only 3 address bits are sufficient. So, there is an unused bit in address variable. This will not give any simulation issues, but synthesis tool shall give warning about the unused bit of address.

Also, declaring reg [3:0] data gives 0 as Least Significant bit (LSB) and 3 as Most Significant bit (MSB). So, for your question:


  What is the meaning of fault_reg = ram [address] in verilog?


This assigns/copies value from memory ram at address of address to fault_reg.


  If the value of ram is 1010 and the value of address is 100, what is the value of data[0], data[1], data[2] and data[3]?


In this example, ram[4] = 4'b1010 so, ram[4][0]=0,ram[4][1]=1,... and so on.
Hence, data[0]=0, data[1]=1, data[2]=0, data[3]=1. 

Refer to Verilog Array Input question for unused address bit and Verilog Memory, Simple RAM Model links for further information.