Minimum Clock Period from setup and hold time
If the flip-flop is being analyzed strictly on its own with regard to the CLK and the D inputs then the minimum clock period approaches the sum of the tsetup and the thold times. The propagation delay only comes into play if the outputs of the flip-flop determine the next state of the D input.

Now with that said most systems being analyzed will have an array of multiple flip-flops that all have their CLK inputs connected to a common clocking source. In addition the outputs of the various flops will be interconnected in some way, possibly including other combinatorial logic, to determine the next state values to the D inputs to the flops. In this case it is necessary that the propagation delay always be included in the analysis and that delay has to include more than just the delay, CLK to Q, of the flip-flop. The extra delay of additional combinatorial logic paths has to be added and in the cases of very high speed clocks the delay of the signals along the routing paths also has to be added. 

In system level or state machine type analysis for minimum clock period it is common to consider the delays of all the flip-flops to be the same worst case specs so that each and every path through the logic tree does not need to be computed individually. This is also a reason that robust logic design always wants to be synchronous with respect to a common clock source so that analysis can be confined to clock to clock behavior.