Systemverilog - Register Chain Simulation Problem
Perhaps there is a bug in your simulator.  This testbench works on edaplayground:
module register_chain
#(
    parameter NUMBER_REGISTERS = 31 ,
    parameter WIDTH_REGISTER = 12
)
(
    input INPUT_CLOCK ,
    input [ WIDTH_REGISTER - 1 : 0 ] INPUT_DATA ,
    input INPUT_ENABLE ,
    input INPUT_RESET ,

    output logic [ 0 : NUMBER_REGISTERS ] [ WIDTH_REGISTER - 1 : 0 ] OUTPUT_DATA
) ;

logic [ 0 : NUMBER_REGISTERS - 1 ] [ WIDTH_REGISTER - 1 : 0 ] array_registers_data ;

    assign OUTPUT_DATA = { INPUT_DATA , array_registers_data } ;
    
    always_ff @ ( posedge INPUT_CLOCK )
    begin : registering
        if ( INPUT_RESET == 1'b1 ) begin
            array_registers_data &lt;= '{ default : '0 } ;
        end else if ( INPUT_ENABLE == 1'b1 ) begin
            array_registers_data &lt;= { INPUT_DATA , array_registers_data [ 0 : NUMBER_REGISTERS - 2 ] } ;
        end
    end : registering

endmodule

module tb;
    parameter NUMBER_REGISTERS = 31;
    parameter WIDTH_REGISTER   = 12;

    bit INPUT_CLOCK;
    bit [WIDTH_REGISTER-1:0] INPUT_DATA;
    bit INPUT_ENABLE = 1;
    bit INPUT_RESET  = 1;
    wire [0:NUMBER_REGISTERS][WIDTH_REGISTER-1:0] OUTPUT_DATA;

register_chain #(
    .NUMBER_REGISTERS(NUMBER_REGISTERS),
    .WIDTH_REGISTER  (WIDTH_REGISTER)
)
dut (
    .INPUT_CLOCK   (INPUT_CLOCK),
    .INPUT_DATA    (INPUT_DATA),
    .INPUT_ENABLE  (INPUT_ENABLE),
    .INPUT_RESET   (INPUT_RESET),
    .OUTPUT_DATA   (OUTPUT_DATA)
);

always #5 INPUT_CLOCK++;

always_ff @ ( posedge INPUT_CLOCK ) begin
    INPUT_DATA &lt;= $urandom;
end

always @ (negedge INPUT_CLOCK) begin
    if (!INPUT_RESET) begin
        $display($time, &quot;  OUTPUT_DATA [0]='h%x, [1]='h%x&quot;, OUTPUT_DATA[0], OUTPUT_DATA[1]);
    end
end

initial begin
    #23 INPUT_RESET = 0;
    #100 $finish;
end

endmodule

Here is some sample output I get, where [0] and [1] are different:
              30  OUTPUT_DATA [0]='h57f, [1]='h997
              40  OUTPUT_DATA [0]='hf4c, [1]='h57f
              50  OUTPUT_DATA [0]='h1a9, [1]='hf4c
              60  OUTPUT_DATA [0]='he0a, [1]='h1a9
              70  OUTPUT_DATA [0]='he5d, [1]='he0a
              80  OUTPUT_DATA [0]='h445, [1]='he5d
              90  OUTPUT_DATA [0]='h941, [1]='h445
             100  OUTPUT_DATA [0]='hbfc, [1]='h941
             110  OUTPUT_DATA [0]='h08b, [1]='hbfc
             120  OUTPUT_DATA [0]='hca1, [1]='h08b