Need help with the logic gate circuit
It depends on what you mean by right. Sure, they all do what the expressions say, but are they optimized?

If you want to minimize the number of gates (which is related to the physical area of your IC), keeping the same fan-in for each gate, you have to simplify the second circuit so that it contains 4 gates, rather than 5, as @jonk suggests. 

In general,if you want to only use AND and OR gates, and want to minimize the number of gates, you may want to use something like Karnaugh maps. However, this cannot be easily 
done on the first two circuits by hand.

If you want to only use one type of gate to make the circuits more modular and easier to analyze, you have to choose either NAND or NOR gates, since they're universal sets. This is done in many integrated circuits. In this case, you have to use the De Morgan's laws.

If you want to minimize the delay, you have to perform a timing analysis and see, for example, whether it is convenient to replace the two 2-input AND gates in the first circuit, AB and (AB)C, with a single, 3-input AND gate.