ERROR:HDLCompiler:806 Syntax error near "port"
Forgive any wrong interpretations but your terminology (code, call) suggests you may see VHDL as a 'program'. It is instead a descriptor language for describing a digital electronic circuit. Recognising that distinction is paramount and you'll get confused if you don't see it clearly and unambiguously. Try to see VHDL as what it is at its heart: a glorified circuit diagram. Avoid mental comparisons with software and computer programs, which are very different.

Describing VHDL further for what you need is beyond this post. But your source file should instantiate ('connect up the wires of') your component outside of any process within your architecture.