I2C PCB Layout Considerations
Wihtout knowing the constraints of your board real-estate and existing layout (i.e. is this a new design where you have free-reign, or must you shoehorn in I2C).

One technique I've had success with is separating on either side of SDA/SCL with a guard trace (ground). This way any emissions from the edges of those signals would be greatly attenuated and would be much less likely to couple into each other or into other signals. (Think the boyscout rule).

The other thing you'll have to evaulate is how much parasitic capacitance there would be in total from end to end. The I2C spec has an upper limit on capacitance to ensure the proper rise/fall/setup times, depending on the data rate. To calculate this you'll need to at least have an estimate of the trace length and a lookup table depending on your board layer stackup, the PCB material (FR4?), and the dimensions of the traces. 

If there are any ESD susceptibility parts near the I2C now, move them!, or be prepared to either re-spin/engineer or add I2C retries in your code.