How to calculate the area that a chip occupies in a design system
Assuming analog circuits, take the gate area and scale up by 5X.

Add in the resistor area scaled up by 5X (precision resistors needs lots of same-doping surround-regions, to sustain matching)

Add in the capacitor area, scaled up by 1x (that is, one-for-one).

Add in rails, sized to handle the current.

Add in 10,000 square microns per bond pad. Yes, yours may be smaller than 100U^2, but wide metal needs routing area. And where are your ESD structures?

This is for 2 or 3 layer metal. With more layers, some of the scale-up can be eased, but then you have all sorts of interferers atop the sensitive components, and you'll have to back off the coupling distances in Rev2 and Rev3.