Systemverilog size attributes
The IEEE Std 1800-2017, section 20.7 Array query functions, describes all that you need:

module tb;

logic x [0:3][7:0] ;

initial begin
    for (int i=1; i&lt;=$dimensions(x); i++) begin
        $display;
        $display($size (x, i));
        $display($left (x, i));
        $display($right(x, i));
        $display($low  (x, i));
        $display($high (x, i));
        $display;
    end
end

endmodule


Outputs:

      4
      0
      3
      0
      3


      8
      7
      0
      0
      7


See also System Tasks And Functions Part-II