Verilog - variable number of inputs/outputs
Use a parametrized bus width:

module FIFO #(WIDTH=8) (
  output [WIDTH-1:0] out,
   /* other ports */
);


Then overwrite the parameter when generating the instances.

module top #(NUM_FIFO=4,WIDTH_FIFO=8)(
  output [NUM_FIFO*WITDH_FIFO-1:0] FIFO_data,
   /* other ports */);
/* ... other code ... */
genvar i;
generate
    for(i=0; i&lt;NUM_FIFO; i++) begin : gen_fifo
        FIFO #(.WIDTH(WIDTH_FIFO)) fifoI (
          .out( FIFO_data[i*WIDTH_FIFO +: WIDTH_FIFO] ),
          /* args */ );
    end : gen_fifo
endgenerate
endmodule : top