Best way to structure Verilog module to allow for simulation clocks
In our designs, we normally divide the design into two layers, like an onion. We call the outer layer the "pad ring" (e.g., taco_io), and it contains everything that's specific to the physical interfaces of the chip &mdash; I/O buffers, on-chip clocks, etc.

The inner layer is the "core" layer, and contains all of the actual application functionality. In other words, the functional hierarchy is implemented with taco_core as its top level. The functional simulation testbench instantiates taco_core only, where it has access to drive those clocks you're talking about.

Your taco_top is used for synthesis only. It just instantiates two modules: taco_io and taco_core and connects them together. It also connects taco_io to the actual external pins of the device.

Note that you could put all of those I/O bits right into taco_top, but we find that it's generally cleaner to put them in their own submodule (taco_io).