Connect PCIe x1 port to an ASIC PCIe x4
In terms of connecting a x4 endpoint to a x1 host, that is perfectly doable. It is required as per section 4.2.4.10.1 of the PCIe V3.0 Base Specification that:


  The ability for a xN Port to form a xN Link as well as a x1 Link (where N can be 32, 16, 12, 8, 4, 2, and 1) is required.


Emphasis mine

Therefore you will have no problem connecting Lane 0 of your ASIC to the MCU.

However, the question is whether or not you can connect to any lane other than Lane 0 on the ASIC. The answer to your question can be answered as nothing more than "maybe" due to lack of any specific documentation on the devices. From the same section of the standard:


  Support for Lane reversal is optional.
  
  • If implemented, Lane reversal must be done for both the Transmitter and Receiver of a given Port for a multi-Lane Link.
  
  • An example of Lane reversal consists of Lane 0 of an Upstream Port attached to Lane N-1 of a Downstream Port where either the Downstream or Upstream device may reverse the Lane order to configure a xN Link.


Emphasis mine

Some PCIe devices support lane reversal, which typically allows Lane 0 to be mapped to Lane N-1, keeping all lanes in order (e.g. 0,1,2,3 connect to 3,2,1,0). However this is not required by the specification so is completely device dependent.

If your ASIC supports lane reversal, then you can connect your MCU to Lane 3 of the ASIC. However if the ASIC doesn't implement the optional feature, then connecting the MCU to anything other than Lane 0 will fail.