VHDL port map: connect only some bits of a vector
I think if it was me, and since the data in this case is just a vector with no direct meaning (as in, it is not a signed or unsigned number), I would make std_center_height have a width of C_S_AXI_DATA_WIDTH, so that it could be connected to the instantiation in a 'normal' way. I would then only use the constant that defines the width of std_center_height when using this vector. Something like:

constant C_STD_CENTER_HEIGHT_WIDTH : integer := 19;
signal std_center_height : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal some_other_vector : std_logic_vector(C_STD_CENTER_HEIGHT_WIDTH-1 downto 0);


...

port map (
  center_height =&gt; std_center_height
);

some_other_vector &lt;= std_center_height(C_STD_CENTER_HEIGHT_WIDTH-1 downto 0);


Note that some_other_vector is not an alias of std_center_height, but is just used as an example of 'making use of std_center_height in some other bit of logic'.