Coolrunner2 GSR Global Set/Reset
As Nick Johnson says, the toolchain should automatically use the Global Set/Reset nets if it thinks it is optimal to do so. All you have to do is use a single signal as an asynchronous reset in all of your logic.

However, if you for any reason do want or need to use the GSR nets directly it is possible:

On the CoolRunner-II devices the GSR pin is a specific input pin. Look at the specific part datasheet (available from the Xilinx website) to find the pin. You must still declare a top level signal which will represent the connection to the GSR pin.

You can then instanciate the Xilinx primitive BUFGSR module to explicitly use the input through the special GSR input buffer. Documentation of this is in Xilinx UG606 - CPLD Libraries Guide, page 82.

Here is a minimal example using the GSR directly:

library ieee;
use ieee.std_logic_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;  --BUFGSR and other primitives are defined in the Xilinx VComponents library

entity gsr_test is
    port ( CLK : in std_logic;
           Reset : in std_logic;
           Inp : in std_logic_vector (3 downto 0);
           Outp : out std_logic_vector (3 downto 0)
          );
end gsr_test;

architecture Behavioral of gsr_test is

signal s_gsr : std_logic;  --signal which will represent GSR internally

begin

--instansiate a BUFGSR to get direct access to the GSR net
i_bufgsr : BUFGSR
    port map ( I =&gt; Reset,  --signal/port which supplies the GSR net (this will need to be connected to the GSR pin on the device
               O =&gt; s_gsr  --bring the internal signal out
              );

pass_through : process (CLK, s_gsr)
begin
    if (s_gsr = '1') then
        Outp &lt;= "1010";  --when GSR is high set to specific value
    elsif rising_edge(CLK) then
        Outp &lt;= Inp;  --otherwise pass out the value of Inp
    end if;     
end process pass_through;   

end Behavioral;


This generates simple logic with flip-flops for each element of the Outp signal with either their PRE or CLR inputs connected to the GSR net.

Here is a technology schematic of the resulting logic: