What is a recycling counting sequence?
Any M counter that has less than 2^N(flipflop) valid states it cycles through, must have a set of 2^N - M invalid states that could possibly occur (at power on, after noise pulse etc)

A Johnson or Walking Ring counter has a count of 2*N, whilst the number of possible states is 2^N. e.g a divide by 10 has 10 desirable states, and 22 invalid ones.

The counter is reset into a valid state. 

If say, a noise spike forces it into an invalid state it will proceed from that invalid state, on a different count sequence.(This new sequence might be endless too) 

The feedback logic has to ensure that 


The counter normally cycles through valid states
If it enters an invalid state, it will re-enter the valid states sequence eventually.
It must not remain locked in an invalid sequence. (but invalid states are not prevented)


SO, I would take "recycling count sequence" to be that normal sequence which normally clocks through, and recycles endlessly. [I have however, never heard the term]

This generally is an issue for all flip-flop feedback sequencers e.g. pseudo-random binary sequences. Often those sequences used in practice, are the small subset of possible sequences, with only a very simple gate needed for feedback.

It can also be an issue for something as simple as a BCD ripple counter, without feedback. You might implement this with a 2 input AND gate to detect 1010, and force a reset. In this case 1101 could exist.

CD4017 datasheet shows this logic feeding D input of FF3. Surprisingly, web references don't mention this. Read "CMOS Cookbook, Don Lancaster" to learn about practical logic.