PCB design for Altera FPGA
First understand the chip's general pinout requirements due to fixed pin functions, I/Os with limited physical alternatives, and banked resources.

Understand the limitations of the total number and physical location options of specific resources like power supply pins, ground pins, clocks, transceivers, configuration pins, et.al.

Understand your design at the implementation level and how its I/Os and clocks can optimally map according to I/O protocol, I/O voltage, routing to nearby LUTs, sharing clocks, et. al.  Ideally you'll fix few arbitrarily selectable I/Os for particular design signal usages until you've completed the synthesis, implementation, and simulation / testing of your design.  Constraining given internal signals to given external I/Os just limits the efficiency of the implementation and routing of your design, so let the synthesis and implementation tools proceed with relatively few constraints dictated by arbitrary I/O assignments.

Once you have a proposed pinout then check how well it might work considering timing and other analyses, PCB layout / routing concerns, et. al.  Pin swap / rearrange as needed to optimize the pinout appropriately balancing PCB concerns and FPGA routing / timing / resource concerns.

Then lock your design to the chosen I/Os and design the schematic and layout accordingly.

http://www.altera.com/education/univ/materials/unv-overview.html

http://www.altera.com/education/univ/software/quartus2/unv-quartus2.html

http://www.altera.com/support/design-support-resources/spt-index-guide.html

http://www.altera.com/products/software/flows/fpga/flo-fpga.html#fpga

http://www.altera.com/products/software/quartus-ii/subscription-edition/design-entry-synthesis/qts-des-ent-syn.html

http://www.altera.com/literature/lit-dpcg.jsp