Confused as to how implement ALU using structured VHDL
If the bitshifter and adder are already provided for you, it seems all you have left to do is connect them together. Build a module that directs the proper inputs given a control signal. If you have six possible operations you'll need at least three bits for a control signal, right? You might want to choose the various operations to have a similar bit in common, and you can use that bit to mux the outputs from each component block to the output of the block you're building. I'm going to use some pseudo code because, first, this is your homework and, second, I haven't written VHDL in years.

  case control_signal is
    when 1 =&gt;   -- Control=1 means add inputs
      adder_input_A &lt;= top_level_input_A;  -- Move inputs of top lever to the adder
      adder_input_B &lt;= top_level_input_B;
    when 2 =&gt;   -- Control=2 means shift the bits left
      bit_shift_input &lt;= top_level_input_A;  -- Move input to bitshift block
      bit_shift_value &lt;= top_level_shift;    -- This one can more likely be always connected
    when 3 =&gt;
      do another one, like shift right
    when others =&gt;
      null;
  end case;


So, it's you're basically creating a mux that switches the inputs depending on the operation being performed. Obviously, I have no idea what your current blocks look like and how they're implemented, but I think the general concept should still apply.