How to generate signal with glitches in VHDL?
For generating test bench stimulation signals generally the code is based on using "after" or other not synthesizable keywords.

By the way, you can use the hazardous circuits for generating the glitches at the real world.

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    entity glitch is
        Port ( CLK       : in  STD_LOGIC;
               HazardOut : out STD_LOGIC;
             );
    end glitch;
-- simulate it with component delays. functional simulation 
-- will not show the glitches 
    architecture Behavioral of glitch is
    signal dly     : STD_LOGIC;
    signal CLKdly  : STD_LOGIC;
    begin
      dly    &lt;= not CLK;
      clkdly &lt;= not dly;
      Hazardout &lt;= CLK xor  clkdly;
    end Behavioral;