FPGA CPUs, how to find the max speed?
The speed of a design is limited by several things. The biggest will most likely be the propagation delay through the combinatorial logic in your design, called the critical path. If you use a fast FPGA and write your HDL very carefully, you could probably hit 700 MHz on something like a Virtex Ultrascale+.  On a lower end FPGA, for example a Spartan 6, a reasonable figure is probably more like 250 MHz. This requires pipelining everywhere so you have the absolute minimum amount of combinatorial logic between stateful components (minimize levels of logic), low fan-outs (minimize loading on logic elements), and no congested rats-nests (efficient routing paths).

The fabric logic of different FPGAs will have different timing parameters. Faster, more expensive FPGAs will have smaller delays and as a result can achieve higher clock frequencies with the same design, or run a more complex design or design with less pipelining at the same frequency.  Performance within a particular process can be similar - for example, Kintex Ultrascale and Virtex Ultrascale are made on the same process and have similar cell and routing delays.  It is impossible to say how fast a given design will be without running it through the tool chain and looking at the timing reports from the static timing analysis.

When doing toolchain runs to determine maximum clock speed, bear in mind that the tools are timing-driven: they will try to meet the specified timing constraints.  If no timing constraints are specified, the result can be very poor as the tools will not try to optimize the design for speed.  Generally, the tools will have to be run several times with different clock period constraints to find what the max achievable clock frequency.

If you can optimize your design so that the critical path is not the limit, then you'll run in to limitations in the clock generation and distribution (PLLs, DCMs, clock buffers, and global clock nets). These limits can be found in part datasheets, but getting near them with a non-trivial design is difficult. I have run stuff on a Virtex Ultrascale at 500 MHz, but this was only a handful of counters to provide triggering signals to other components.