working voltage and output levels of a logical gate chip
Most CMOS logic chips have specifications for 5v, 10v, and 15v operation, but you can use them at any voltage inbetween. (Note some "high voltage" CMOS versions can be operated from 20v or so.)


For an inverter like the MC14060UB, the specifications are condensed into a table. For just these highlighted lines:


In orange, when the input is "0" or low, the output is 9.0v (guaranteed, perhaps higher.) This is when powered from Vdd=10v. For \$V_{IL}\$, at all temperatures, the maximum input voltage that will be read as a "0" is 2.0v. The typical (note 2) value "is not to be used for design purposes but is intended as an indication of the IC’s potential performance." So this chip can potentially interpret an input voltage up to 4.5v as a "0".
In Yellow, when an input is "0", the output is 13.5v or more. This is when powered from Vdd=15v. The maximum guaranteed "0" input level is 2.5v, but it will probably accept 6.75v as a "0" input.


So 12v is slightly less than half the difference between 10v and 15v ratings (12.5v would be exactly half), so a quick interpolation should give you values. i.e., for Vdd=12v, \$V_{IL}\$ should be ~2.2v, with a typical "0" voltage of ~5v.

About CMOS in particular, typically, they operate faster at higher voltages. And they can be powered from less than 5v, but they slow down significantly and nothing is guaranteed.  

When using any digital logic chip, always pull unused inputs either high or low. There exists a "no-go" zone between a "high" and "low" input level, where the chip will consume too much power. If any input is left unconnected, they typically float in this zone and even oscillate, destroying the chip. 

And some CMOS chips are very static-electricity-sensitive; best to work on a grounded mat with an anti-static wrist strap.