Delay in Combinational Logic Circuits/Stability
Yes, you've got it right. In digital logic, the circuit is stable after it's stopped changing due to a change in the inputs.


  the time delay for the signal to reach the output is directly proportional to the number of gates the signal must pass through?


Except for the fact that the delay of different gates might be different, this is correct. For example, an AND gate might have a longer propagation delay than a NAND gate.

edit

As Michael points out in the comments, there are other factors affecting the delay. I answered the question thinking mostly about discrete TTL or CMOS logic designs. Even then, factors like the fan-out from each gate will affect the path delay.

In FPGAs the situation is much more complicated. First because there's no 1-to-1 correspondence between the basic gates (AND, OR, etc.) and the implementation in the FPGA. Second because the speeds you can achieve in an FPGA are much faster than in discrete logic, so relatively small effects start to have a more significant impact in the overall design.