Verilog : Combining sequential logic with combinational logic
First, in Verilog an instantiated module is always considered "combinatorial" logic even if it contains sequential logic inside it. For the purposes of the module that contains it, it's just a black box with inputs and outputs, so the containing module considers it combinatorial. That means the outputs of an instance are declared as wires.

Second, in Verilog sequential logic happens within always blocks. Anything that's assigned to inside an always block will be declared as a reg. The only way for (physically) sequential logic to happen inside an always block is on the right-hand side of an assignment statement.

So you just need to move your instance outside the always block.

Here's a much simplified fragment:

module demo(clk, in, out)
   input clk;
   input in;
   output out;

   wire some_result;
   reg some_state;

   always @(posedge clk) begin
       case (some_state) 
           1'b0: begin
               out &lt;= 1'b0;
               some_state &lt;= /* calculate next state */
           1'b1: begin
               out &lt;= some_result;
               some_state &lt;= /* calculate next state */
        endcase
   end

   my_module inst0 ( .IN(in), .OUT(some_result) );
endmodule


With this structure, the output of the instance is available to the state machine, but the instance itself is instantiated outside the always block.

If you are trying to save power by having the instance only operate when it needs to, you can give the lower-level module an ENABLE input, and generate a signal in the state machine to control that input. However I wouldn't recommend doing this unless you really know you need to save power and that disabling the lower-level module will significantly reduce power consumption.