Verilog module to read/write a register
When read is HIGH, I expect y to be initialized to the value of x. 


The only thing your code actually does when read is high is to make y output the value from a. As soon as read goes low again y goes back to being an input (because you assign it the value z).


  When read is LOW, I expect to output the value of b (which can be decremented or incremented by using minus or plus).


Since b is not an output, and you never use b to set any other wire or register, it's not clear how you expect that to happen.


  Currently however, plus does not do anything


Are you sure? In your code, if plus is high at a rising edge of clk, then b will get the value y+1.


  and read toggles y between 0xFFFF and 2 


Are you sure the value is 0xFFFF and not 0xXXXX? Because when read is low, this code is not assigning any value at all to y. It sounds like your testbench is applying a pull-up or a weak high value to the bits of y.