What can the dsPIC do which the humble PIC microcontroller cannot do?
Some of the advantages of a dsPIC over earlier-architecture PICs, like the PIC 16 and 18 families:

16 bit wide data paths and ALU, as apposed to 8.

Ability to directly address (later versions of both architectures extended this in various kludgy ways) more data memory.  A basic PIC 16 can address 128 bytes directly, 512 with banking.  The newer PIC 16F1xxx have extended banking to allow addressing more data memory.  The PIC 18 architecture is limited to 4k bytes.  The dsPIC architecture can address 64k bytes or 32k 16-bit words directly, although for various reasons only half of that is available for RAM in the basic architecture.  A banking scheme in some of the later models has extended that.

Faster.  The original 30F could run at 30 MIPs, with 40 MIPs parts the norm now.  The new E series can run up to 70 MIPs, although there are more reasons it might stall waiting on something than the earlier slower models.  They are still significantly faster on average.

DSP capability.  The DSP engine has two 40-bit accumulators and the usual hardware to perform a sequence of MAC operations on arrays one MAC per instruction cycle (see Dave Tweed's answer).  The MAC and related instructions overlap array indexing and loop termination with the actual multiply-accumulate.

15 software-usable 16-bit "working registers" instead of the single 8-bit W register of the 8 bit PIC architectures.

Barrel shifter.

Single-cycle 16x16 --> 32 bit multiply.

Hardware divide.  A 32 div 16 --> 16 bit operation takes 18 cycles.

Lots of 3-operand instructions.  For example, you can add the contents of two working registers and put the result into a third, all in a single cycle.  This applies to most math, logic, and shift operations.

Overall more regular and symmetric instruction set.

Vectored interrupts.  The PIC 16 has a single interrupt vector, and the PIC 18 has two.  On the 16 bit parts (PIC 24, dsPIC 30 and 33), each interrupt source has its own vector.  This reduces latency in the interrupt routine because it doesn't have to spend cycles figuring out which interrupt to service.

This also allows for better software architecture.  The interrupt routine for a particular peripheral can be in the same module as the other code handling that peripheral, instead of having to have one global interrupt routine.

Various other advantages that fall out from the wider architecture.