VHDL: What does STD_INPUT and STD_OUTPUT appearing in std.textio mean?
Short answer: Yes :)

Unfortunately not every simulator supports it.

Currently, I know only GHDL and ModelSim / QuestaSim. I have no info on iSim or xSim.

I don't know any synthesis tool which supports STD_IN and STD_OUT. Xilinx XST has file I/O support but I think no support for STD_IN/STD_OUT.

Vivado has no file I/O support and Quartus does not support std.textio.