how to design a pattern detector state machine in vhdl
I'd suggest a more general approach (without counters) that needs some more gates but is much easier to understand and to debug and it can be adapted for more complex patterns.
Drawn as classical logic gates:


The VHDL implementation is very straight forward:


implement a 32-bit shift register
check whether output vector equals reference vector


EDIT1:
If you absolutely want (have) to use counters:


one counter that increments with each 0 at the input.
another counter that increments with each 1 at the input.
prevent wrap-around of both counters, e.g. by disabling if they reach a count above the required value (15+1 and 17+1).
reset both counters if a 1 is followed by a 0 at the input
compare the outputs of both counts whether they show the required values


EDIT2
BTW: also the shift register solution could pass as solution using "two counters": a shift register can be seen as a unary counter. The part with the inverters is a unary counter that counts the 0s. The part without the inverters is a unary counter that counts the 1s.