Why Xilinx ISE can't get access to my custom package?
Unfortunately not until VHDL-2008 were unconstrained arrays of unconstrained elements allowed.

In other words, for pre VHDL-2008:

type Matrix is array (natural range&lt;&gt;) of std_logic_vector(natural range&lt;&gt;);


Would have to become either something like:

type Matrix_n_by_8 is array (natural range&lt;&gt;) of std_logic_vector(7 downto 0);


Or use 2d arrays:

type Matrix is array(natural range&lt;&gt;, natural range&lt;&gt;) of std_logic;