Parallel 4221-BCD counter on D-triggers
If you are not sure what the teacher is expecting from you then you really should ask the teacher. However, my guess is that the values in the flip-flops themselves are supposed to represent the counter value in 4221. So you need to design a logic circuit that properly determines the next state of each flip-flop, given the current state of each flip-flop.

If the counter is supposed to be synchronous, then the clock input of every flip-flop must be connected to the main clock input signal, not to the output of another flip-flop.

Is it possible? Sure.