Verilog: Check for two negedges in always block
The always@ is a sensitivity list and generally not a checking list i.e. it doesn't work as an if-else block.

Instead, it indicates when the register/latch specified in the block needs to change states, typically on a clock edge (register) or level change (latch).

If you're trying to detect an edge on an input, such as for an interrupt detection, the recommended way is to synchronise the edge to an internal shift register.

It could be as simple as this:

reg [1:0] det_edge;
wire sig_edge;
assign sig_edge = (det_edge == 2'b10);
always @(posedge clk)
  begin
    det_edge &lt;= {det_edge[0], input};
  end


Then, you can do whatever you want with the edge signal, possibly as an enable signal to a state machine or other block that does something with your device (such as flagging the interrupt).

So, for your application, you may want to do the above twice and then use the two edge detect signals to control some other device/block.

The key point to remember with all HDL work is that HDL stands for Hardware Description Language. It is a replacement for schematics, not software.

For starters, I would recommend starting with the hardware and then translate that into code i.e. draw the schematic and then write the HDL that describes that circuit schematic.