CMOS implementation of D flip-flop
This is an example of dynamic logic. Instead of using feedback to store a 0 or 1 like a normal flip-flop, it relies on the fact that a floating node will retain its previous state due to the capacitance. However, the leakage current will cause it to lose state after a certain amount of time. Thus, it must be clocked at a certain minimum speed.

If you read the section of the article near where the image is shown, it gives a general explanation of the idea:


  Edge-triggered dynamic D storage element
  
  An efficient functional alternative to a D flip-flop can be made with
  dynamic circuits (where information is stored in a capacitance) as
  long as it is clocked often enough; while not a true flip-flop, it is
  still called a flip-flop for its functional role. While the
  master–slave D element is triggered on the edge of a clock, its
  components are each triggered by clock levels. The "edge-triggered D
  flip-flop", as it is called even though it is not a true flip-flop,
  does not have the master–slave properties.
  
  Edge-triggered D flip-flops are often implemented in integrated
  high-speed operations using dynamic logic. This means that the digital
  output is stored on parasitic device capacitance while the device is
  not transitioning. This design of dynamic flip flops also enables
  simple resetting since the reset operation can be performed by simply
  discharging one or more internal nodes. A common dynamic flip-flop
  variety is the true single-phase clock (TSPC) type which performs the
  flip-flop operation with little power and at high speeds. However,
  dynamic flip-flops will typically not work at static or low clock
  speeds: given enough time, leakage paths may discharge the parasitic
  capacitance enough to cause the flip-flop to enter invalid states.


Source: Wikipedia - Flip-flop (electronics)

I've done some analysis of this specific circuit to try to figure out how exactly it works.

First, consider the two cases of CLK=0 and CLK=1. Replacing the CLK transistors with ideal switches, we get the following two cases:







simulate this circuit &ndash; Schematic created using CircuitLab

$$ $$
\$\text{CLK low:}\$


\$ A = \overline{D} \$
\$ B = 1 \$
\$ Qb = \text{hold} \$
\$ Q = \overline{Qb} \$


$$ $$
\$\text{CLK high:}\$


\$Qb = \overline{B}\$
\$Q = \overline{Qb}\$
\$\text{if } D = 1:\$


\$A = 0\$
\$B = \text{hold}\$

\$\text{if } D = 0\$:


\$A = \text{hold}\$
\$\text{if } A = 1, B = 0\$
\$\text{if } A = 0, B = \text{hold}\$



$$ $$

Does this match the normal behavior of a flip-flop?

First, notice that changes to D cannot affect Q when the clock is static high or static low. 

On the low-to-high transition of CLK (assuming D is steady), we can examine the two cases based on the state of D:

\$ CLK = 0 \rightarrow 1, D = 0 \$


\$ A = 1 \$
\$ B = 1 \rightarrow 0 \$
\$ Qb = Qb' \rightarrow 1 \$
\$ Q = \overline{Qb'} \rightarrow 0 \$


\$ CLK = 0 \rightarrow 1, D = 1 \$


\$ A = 0 \$
\$ B = 1 \$
\$ Qb = Qb' \rightarrow 0 \$
\$ Q = \overline{Qb'} \rightarrow 1 \$


So, yes, this does appear to function as a normal flip-flop. As stated before, there is a minimum speed below which the leakage current will discharge the capacitors and break the "hold" functions (also notated as \$Qb'\$) in the above analysis.



I've found this paper that gives some insight into the design philosophy of this circuit. It discusses 4 types of dynamic stages, "precharged p- and n-stages and nonprecharged (static) p- and n-stages." It looks like this circuit is made of a series of SP + PN + SN stages. Please see the paper for more details (I'm not sure how much of it I am allowed to reproduce here).

J. Yuan and C. Svensson, New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings, IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 62-69, Jan. 1997. Retrieved from https://ieeexplore.ieee.org/abstract/document/553179