Changing frequency of input clock port (FPGA)
This is not possible as you have drawn your block diagram; the IBUFDS_DIFF_OUT is an input buffer and as such it may only be connected directly to the proper IO pins; it cannot be driven from within the FPGA.  What you need to do is edit the reference design to use a 50 MHz input clock.  This could be as simple as changing the settings of an existing MMCM or PLL.  Or maybe you need to add an MMCM or PLL instance.