What is difference if Floorplanning for FPGA, ASIC (Standard Cell Based) & Gate Array?
Well the difference is that FPGAs and Gate Arrays do have already existing physical design. In some cases you don't bother to do floorplan for FPGAs. 

Imagine that you need to use a RAM in your design. Most of the FPGAs have their dedicated SRAM, so you can assign your RAM to it or just use many cells to do the same job.