Multiple driver error for SystemVerilog initial value
Get rid of the end before the else. The compiler is confused about where the first if ends.
Also,

always_comb doesn't allow outside processes to write left-hand side variables (vs. always @ *, which does)
regardless, more than one driver the same wire type is not allowed. The always_comb boils down to an assignment for z, so trying to assign it again outside results in the multi-driver error.

More about all that here: https://www.verilogpro.com/systemverilog-always_comb-always_ff/
And here: https://stackoverflow.com/questions/23101717/difference-among-always-ff-always-comb-always-latch-and-always
Finally, if your intention is for z to have some default value, careful coding style would include it in the body of the if-else statement as the final else. This is clearer for someone else reading your code (or yourself, later.)