Writing a VHDL Module
I'm pretty sure you accidentally clicked "Verilog Module" instead of "VHDL Module":



The code generated should look something like this:

   COMPONENT mymodule
   PORT(
      clk    : IN std_logic_vector(3 downto 0);
      enable : IN std_logic_vector(3 downto 0);   
      output : OUT std_logic_vector(3 downto 0)
   );
   END COMPONENT;


Delete the accidental Verilog Module and try again paying close attention to which Source Type you choose.