Why is my seconds counter in verilog jumping values behaviour?
Yes, there is "bouncing" &mdash; but in this context, we call them "glitches". The comparator (count &gt; 26'd24999999) represents a rather large amount of combinatorial logic, and there's no chance that all paths through this logic (and the associated FPGA interconnect) will have exactly the same delay. Therefore, the output pulse will experience one or more glitches before it settles down.

If you are using pulse directly as a clock to other logic, that logic will experience extra clock edges.