How does the hardware realize adding 8 values in 1 clock cycle?
Since your tags indicate you're looking for a VHDL solution:
you'd just literally type
result := a1+a2+a3+a4+a5+a6+a7+a8

in your VHDL design and let the synthesizer and technology mapper take care of it – &quot;how does one do this in hardware&quot; is answered by knowing what kind of hardware is available; you'd almost never do the obvious undergrad-homework approach of building a tree adder for hardware: FPGAs don't contain &quot;two-input adders&quot; at all (aside from DSP slices, which you really don't want here, I guess), and ASICs are made from standard cells, some of which might be really useful here.
However, synthesizers and technology mappers differ in quality. Do try placing parentheses to help the synthesizer partition this in smaller problems and see whether a 2-partitioning or 4-partitioning helps.
Anyway, you really can't tell how the design will look like in hardware without specifying for which kind of hardware you're doing this, so your second question only has the answer &quot;you'll know after elaboration of the design, and no earlier&quot;.