Reseting a 128 adress* 16 words memory
The loop is perfectly synthesisable, except for the fact you are counting to 256 when you only have 128 addresses.

However what you are going to infer is not a memory, but rather 2048 discreet registers. If that's what you want, then you should have no problems, but it probably isn't. Memory blocks in FPGAs don't have array reset signals (they have reset signals for the address and output registers, but not the data array). If you want to reset the contents of a memory block you can't do it in one go. 

You have two options if you want to infer a memory rather than registers.

The first option would be to have a counter and over the course of 128 clock cycles set each address in turn to zero. That takes a long time.

The second option would be to have 128bit wide register (one of each memory word). You use that register to indicate whether or not the memory word is valid. To reset the memory you clear the 128bit register to indicate none are valid. You can then use the valid bit to determine whether to output the value in the memory or zero. The advantage of this approach is you can clear the data in a single clock cycle by clearing the valid bits.