What exactly is or how does a weak signal come into play in VHDL?
VHDL had by default a 2-valued logic known as types bit and bit_vector. With IEEE Std. 1164, which was incorporated into VHDL itself, it got a 9-valued logic. In comparison, Verilog has only a fixed 4-valued logic (X, 0, 1, Z).
VHDL's std_ulogic type has:

U - uninitialized
X - strong unknown (error)
0 - strong low
1 - strong high
Z - tri state
W - weak unknown (error)
L - weak low
H - weak high
- - Don't care

All objects are initialized with type'left if no default value is given. There are multiple subtypes like x01z with are compatible to the Verilog logic system.
Weak signals are intended to model pullups and pulldowns. Thus it's possible to simulate OneWire, I²C and similar busses with pullups and pulldowns.
Using strong and weak signals makes mostly sense when signals are driven by multiple sources. In such a cases, the type use should be based on std_logic, which adds a resolution function to the base type. A resolution function computes the effective values from multiple sources.
Example: H and 0 results in 0 (pullups and ground is ground).