Unspecified I/O Standard value 'DEFAULT instead of User defined value. But I can also not assign a value
Thats a wrong conclusion you are leading to , whenever you have designed the verilog/vhdl module in the constraints file you need to provide the following information,


Physical constraints 
 -- Pin  location constraints, IO Standard of IO pin(you can see the VCCO,VCC_AUX values in case of xilinx fpga similarly you can see for other FPGAs too),Slew constraints, Equalization of IO for high speed transceivers
Clock constraints (create_clk constraints)
False paths or MCP paths or Max delay paths (CDC)
any other constraints

module top (input nota, input b, output c) ;

example u_example (
  .a (~nota )
 ,.b (b     )
 ,.c (c     )
);

endmodule 


module example (input a, input b, output c); 
//...definition of module ...//
endmodule 


Constriants


set_property PACKAGE_PIN AM17     [get_ports "nota"]   ;
set_property PACKAGE_PIN AM16     [get_ports "b"]      ;
set_property PACKAGE_PIN AM15     [get_ports "c"]      ;
set_property IOSTANDARD LVCMOS12  [get_ports "nota"]   ;
set_property IOSTANDARD LVCMOS12  [get_ports "b"]      ;
set_property IOSTANDARD LVCMOS12  [get_ports "c"]      ;