Implications of having duplicate case statement in verilog/system verilog design module
The implications will show up when you get to a real project.
It will show up when you get into code coverage. It's one of many ways you can create unreachable statements. SystemVerilog has a unique case that flags multiple matching case items during simulation.
BTW, It's also a bad idea to have q &lt;= q; statements—leave that behavior implicit. It gets in the way of debugging or what called backdoor access. You try to set a register when you don't think it's being used, and your setting gets overwritten with the previous value.