ALU once compiled giving errors of missing source signal?
The error log references these two instances, and from the screen shot of the schematic it looks like there are indeed some problems with those connections.

No connection on port D of inst6:



Looks like port Cin on inst14 isn't right either, that connection doesn't line up. Even though visually it looks close, trust the netlist. Better delete that wire and re-connnect it, just to be sure.



One of the reasons we use VHDL and Verilog instead of schematic capture, is that it's very easy to miss these kinds of connection errors. A missing tie-dot, an unconnected port, an irregular or misleadingly routed trace just doesn't stand out from an array of nearly identical boxes. This isn't just due to inexperience: I've seen professionals make the same type of mistake in schematic entry.

(Another reason is since VHDL and Verilog are text, these file formats work well with source code control tools like Subversion or Git. For larger projects this becomes very important.)