AC-coupling capacitors for high-speed differential interfaces
The coupling capacitors are usually placed close to the transmitter source.

Going along with Dr. Johnson, we need to figure out the distance. The propagation velocity of signals on most FR4 types of board is about c/2. This equates to around 170ps per inch for internal layers and more like 160 ps per inch for external layers. 

Using a standard interface running at 2.5Gb/sec, the unit interval is 400ps, so according to that, we should be much less than 200 ps away from the transmitter. If this interface has been implemented in an IC, then you need to remember that the bond wires are part of this distance. Below is a slightly more in-depth look at the issue.

In practise, coupling devices are placed as close as possible to the transmitter device. This location naturally varies depending on the device.

Now the capacitor. This is an RLC device at these speeds, and most devices are well above self-resonance in multi-gigabit applications. This means you may well have a significant impedance that is higher than the transmission line.

For reference, the self inductance for a few device sizes:
0402 ~ 0.7nH
0603 ~ 0.9nH
0805 ~ 1.2nH

To get around high impedance device problems (a major issue in PCI express due to the nature of link training), we sometimes use so-called reverse geometry devices because the self inductance of the parts is significantly lower. Reverse geometry is just what it says: An 0402 device has the contacts 04 apart, where an 0204 device uses the 02 as the distance between the contacts.
An 0204 part has a typical self inductance value of 0.3nH, significantly reducing the effective impedance of the device.

Now to that discontinuity: it will produce reflections. The further away that reflection, the larger the impact on the source (and energy loss, see below) within the distance range of 1/2 of the transition time of the signal; beyond that makes little difference. 

At a distance of 1/2 the transition time or further from the source, the reflection can be calculated using the reflection coefficient equation ([Zl - Zs]/[Zl + Zs]). If the reflection is generated closer such that the effective reflection is lower than this, we have effectively reduced the reflection coefficient and reduced lost energy.
The closer any known reflection may be situated with respect to the transmitter, the less effect on the system it will have. 
This is the reason that break-out vias under BGA devices with high speed interfaces is done as close to the ball as possible. It is all about reducing the effect of reflections.

As an example, if I place the coupling capacitor (for the 2.5Gb/sec link) at 0.1 inch from the source, then the distance equates to a time of 17ps. As the transition time of these signals is usually limited to no faster than 100 picoseconds, the reflection coefficient is therefore 17%. Note that this transition time equates to 5GHz signalling artefacts.
If we place the device further away (beyond the transition time / 2 limit), and use the typical values for 0402 100nH, we have Z(cap) = 22 ohms, Z(track) about 50 ohms, and we therefore have a reflection coefficient of about 40%. The actual reflection will be worse due to the device pads.