Why does Flash and SRAM have a "hold" signal?
As well as what the other answers have stated, the pin also has a use in DMA transfers. In one design I had an SPI based MP3 codec IC which required data to be copied from Flash memory (could also be SRAM) to the IC using the same data bus (due to having only one hardware SPI bus on the MCU I was using).

The process here is essentially: (1) set the start address in the memory, (2) read a small chunk of data, (3) put the memory is suspend mode, (4) write the chunk of data back out to the MP3 codec, and (5) bring the memory out of suspend mode and jump back to 2.

The advantage of this process is it is a lot faster to toggle the suspend pin between each chunk of data than it is to start a new read from the memory. To start a read you usually have to send at least 3 bytes (command + address) to the memory which takes many, many more clock cycles than just toggling the hold pin between data chunks while you use the bus for something else.