What should I use to make this MOSFET drop the gate-voltage even faster?
Your wire is not defined on the schematic.   Typically Delays are made for Half Bridges to delay turn-on to avoid short circuit or shoot -thru and depend on load inductance and FET Capacitance which I modelled here for a power FET with Ciss.
The Turn-ON delay is circled and OFF is assumed to be x ns with low diode resistance.

You must define more details on FET parameters and load. I simply chose beta=1 and logic level FET with Vt=1.