Inferring Latches warning in VHDL
As others have pointed out in the comments, you should use a synchronous (clocked) process for a counter. The fact that your message references count_reg leads me to believe that you have not included all the relevant code.

Any asynchronous process such as the one described by your code will infer a latch for a signal that does not have an assignment in every branch of that process. In your example, the signal count is not assigned in the second branch (elsif control = "000" ...).

In some cases, there may be only one branch that assigns a value other than 'not asserted', usually '0'. In these cases, instead of cluttering every branch with assignments  to '0', you can make this assignment right at the start of the process (before the first if), which will serve as a 'default', unless contradicted in one of the branches.

Your counter process should more conventionally look like this:

process (clk)
  variable count : std_logic_vector (3 downto 0) := (others =&gt; '0'); 
begin
  if (rising_edge(clk)) then
    if control = "001" or control = "010" then 
      address &lt;= count;         
      count := count + "0001";
    elsif control = "000" or control = "011" then
      address &lt;= count; 
      --count := count; 
    else 
      count := (others =&gt; '0'); 
      address &lt;= count;
    end if;           
  end if;           
end process;


It is also clear that you are using the package std_logic_arith. This non-standard package should not be used. Instead, use numeric_std, and declare your count to have type unsigned.