Timing Diagram question
When CLK first goes high, A is high and B is low, so the first flip-flop is set, and C goes high as you indicate.  In your diagram, you show C going high slightly before the CLK goes high, this is just sloppy; it will actually go high a bit later due to whatever propagation delay there is in the flip-flop.  (I assume you should be taking these into consideration.)

You then assume the second flip-flop will also be set, because A · C would be high, and in fact show D going high at the same time C does in the diagram.  But again you are forgetting about propagation delays; by the time A · C goes high there have now been two propagation delays (first the flip-flop, and second, the AND gate), so the rising edge of the CLK has already passed and nothing will happen at the second flip-flop (D will stay low).

I'm not going to continue and correct the rest of the diagram for you; next time take more care in drawing it so the cause and effect of each signal is clearly shown.