Characteristics of built-in Zener protection on FET gates
The zener protection on Mosfet gate is against ESD (electrostatic discharge) damage. In this case the Mosfet is tiny and you could damage it just touching the pin, without the Zener. 

Please note that specific datasheet says nothing about the ESD protection level, so I assume is not very strong. Unlikely is 2kV HBM, may be just 500V.
Usually if the Zener is present the ESD resistance capability is reported on the datasheet; this specific datasheet is unusual on that.

Most mosfets, specially the larger, have no Zener ESD protection. The absence is due to cost, a version with zener needs 1-2 masks more so the die is a bit more expensive (~15%). 

ESD pulse are low energy short pulse;  but the gate oxide is thin: 500 to 1000 Å and damages are catastrophic.
Without the Zener, the capability to sustain the ESD stress depends by thickness and area of the gate oxide.
Logic level (Vgs-th ~ 1.5) are more sensible than standard gate (Vgs-th ~ 3)
On big Mosfets the gate capacitance is able to handle the ESD pulse without damage.

The Zener voltage is few volts more than the max rated Vgs. It protects the 
gate oxide but it will be destroyed itself by DC or long pulse overvoltage.
The ESD Zener also introduce a current path between gate and source so the 
Igss leakage is orders of magnitude larger then the gate capacitance itself.

Some reading:
http://www.jedec.org/sites/default/files/IndustryCouncil_HBM_January2014_JEDECversionMay2014.pdf

and one of the test methodology 
http://www.aecouncil.com/Documents/AEC_Q101-001A.pdf.
Same than JESD22-A114