Designing a latch with no constant power supply
While a well-balanced back-to-back pair of inverters is powered on, it will have a strong tendency to drive itself toward one of two states; by "overpowering" one of the inverters, it's possible to switch it to the other state.  If power is removed, internal node capacitance will cause its internal circuit nodes to hold a significant portion of their charge for quite some time; re-applying power will cause the device to power back up in its previous state.  If the circuit is powered off for a long time, it's possible that enough charge may dissipate that the next power-on cycle will be in the wrong state, but that may take many minutes or even hours.

If the circuit is perfectly balanced, the power-on state after a long time being powered off may be unpredictable.  If one unbalances the circuit slightly, one can ensure that the circuit will "drift" toward one state or the other, at the expense of reducing the amount of time the circuit can "remember" the other state.  Note also that it's important to ensure that the circuit is free from disturbance while the remainder of the circuit is powered on and off.  That's the reason for using inverters rather than the more "usual" NAND or NOR gates.

If one uses two inverters, fed back to each other through resistors, and then has N-channel MOSFETs which can pull either inverter's input low, then provided that outside circuitry does not put positive voltage on the gates of those MOSFETs, the latching circuit will be free from outside influence.  If the inverters are on a chip by themselves, it is diode-isolated from the system's main power supply, and there are capacitors from each inverter input to ground, it may be possible to extend the "memory" time to days or weeks, though I've not tried such a thing.