Designing a testbench for a multi-cycle circuit?
This is a bench pattern that will do as you want.

The procedure is not necessary, just there as an illustration.

You can fill in the procedure body, code and signal list as required.

You'll need to change do_test1 to match the edge of the clock you want to examine.

If you are using VHDL2008, you can use the sub-module 'External Names' signal access syntax to make the test run on some buried clock, as shown in the example.

library IEEE;
use IEEE.std_logic_1164.all;

package tests is
  procedure other_tests(sigs : types....);
end package;

package body tests is
  procedure other_tests(sigs : types....) is
  begin
  end procedure;      
endd package body;

library IEEE;
use IEEE.std_logic_1164.all;

entity TB is
end entity;

architecture bench of TB is

component some_entity is
  port (
    clk : in std_logic;
    op  : out std_logic
  );
end component;

signal op : std_logic;
alias clk is &lt;&lt; signal.tb.uut1.clk : std_logic &gt;&gt;;

begin

  do_test1 : process
    for n in 1 to 100 loop
      wait until rising_edge(clk);
    end loop;

    other_tests();

  end process;  

  UUT1 : some_entity port map (clk =&gt; clk, op =&gt; op);

end architecture;