designing a state machine to detect a certain bit
Before getting to whether or not it is functional, I have some suggestions. They may seem trivial at the moment, but if you learn to do them properly now, you will have a much easier time later on.


Indent your code properly. It may seem a chore, but it is worth it
Use the begin and end keywords. They are your friends, and only 8 characters.
Give nets proper names. It makes debugging stuff far easier as the code starts to read as English rather than gibberish.
Give constants a length. It will make mistakes more obvious when you synthesize - rather than simply ignoring the compiler warnings about constants being truncated, you will be able to use them to spot mistakes.
Add comments! Anything that is not obvious from the code, write a comment to explain why it is happening.
Give state machine states names using the localparam keyword. This again makes it easier to read, and if you need to change the value that represents a state, you only have to change it in one place.


This is a bit of your code that I have applied the above to.

localparam IDLE_STATE = 2'd0;
localparam FINAL_STATE = 2'd3; //I'm not saying these are good names, just an example

reg [1:0] stateMachine = IDLE_STATE;
always @ (posedge clk) begin
    case(stateMachine)
    ...
    FINAL_STATE:
        //At this point we have the sequence 101
        if(bitIn) begin
            //A 1 does not make the sequence 1010
            stateMachine &lt;= SOME_STATE; //Go back to ... state to start the sequence at 1xxx again.
        end else begin
            stateMachine &lt;= SOME_OTHER_STATE; //Go to SOME_OTHER_STATE;. &lt;-- This is a *bad* example of a comment as it doesn't tell us anything useful.
        end
    ...
    endcase
end




A cursory glance at your state machine diagram, and it does appear to make sense. It should indeed be able to detect streams of 1010. For example 101010 would be detected as being two valid 1010 sequences (that overlap) - I presume this is what you are trying to do.

The state machine representation in Verilog (aside from the above coding suggestions) does appear to be a valid representation of your state machine diagram. 

What I do notice is that your state machine doesn't have a reset signal. It is correctly initialised at power up, but what happens if you, say, reset your incoming data stream, but the state machine is still in the final state, you may spuriously detect a valid pattern with only 1,2 or 3 bits depending on where your state machine was when the data stream started. A reset signal would help cure this.

Also you do not have a default: state - which basically says if the state machine is ever not in a valid state, go to whatever state (e.g. IDLE_STATE). This is not necessarily required when you have a full case (i.e. you have an entry for every possible value the register can take) which is true for your code. But bear it in mind.

Again I only gave it a quick glance. You should run a simulation to make sure it is correct.



Your simulation results have revealed an issue - I didn't spot that in the always block that drives y, your if statement is inverted. It should be if(!x).

But that brings up another point, for that bit of code, doing:

if(!x) begin
    y = 1'b1;
end else begin
    y = 1'b0;
end


Is a very long winded way of saying:

y = !x;