CMOS Integrate circuit with output in Open Drain Technology
A wired or circuit is rather like that string they used on buses and trains to tell the driver to brake and stop.



The string is a common signal line that just hangs there till anyone decides to pull down on it.

In a circuit, a wired or connection is a signal line held up by a pull-up that one or more open-drain or open-collector gates are attached to. Each gate can only pull the voltage down on that signal line.







simulate this circuit &ndash; Schematic created using CircuitLab

You can see from the above that the output, "signal",  will be low if any of the switches is closed. 

That is:

SIGNAL is low if SW1 is closed OR SW2 is closed OR SW3 is closed.

Why We Need Open-Drain Drivers

Since the tops of those switches are shorted together, when you use gates to drive that line, the gate outputs also need to be shorted together.

If the outputs were able to source current as well as sink it, you would create the conditions where one gate is trying to push at the same time as another is trying to pull. This would result in a large destructive current in both gates.

As such we use open-drain, or open-collector gates for this function.

What use is it?

Now you may be wondering when we would do such a thing.

The nice thing about the wired or circuit is, unlike an integrated logic circuit, you do not need to know in advance how many devices are going to take part in the OR function.  Just like in the bus-string where any number of passengers can pull it, any number of gates can be theoretically attached to the or-line. 

A good example of this it the I2C communication bus that allows you to hook up an indeterminate number of slave devices to a single master device.

So why aren't all gates open-drain?

You may be asking that question and it is a valid one. 

The major downfall with wired or connections is the pull-up. 


Since it is not an active current source, when the line is released the voltage on the line rises at a slower rate dictated by the parasitic capacitance of the signal line. That means, there is an upper limit on how fast you can pass transitions on that line.  
Since the line has a higher rest impedance it is much more susceptible to noise than an actively driven line.


Additionally, other inter-gate interferences can occur, especially with open-drain outputs which have internal capacitive effects.