Designing a Silicon Photomultiplier Read-Out circuit
Does this idea seem reasonable, or is there something I'm not taking
  into consideration?


Notice the 3 pF capacitor across the feedback resistor? This is normally chosen to counter the photodiode parasitic capacitance in order to constrain the noise gain of the opamp.

With four photodiodes in parallel, the feedback capacitance would need to rise four times in order to keep the noise back to where it was previously. That means you will also reduce the signal bandwidth to one-quarter.

Maybe you can live with this or maybe you can live with four times the background noise. Only you can say.