Is the FET gate resistance counted on the RC time constant?
Your model doesn't make a lot of sense. You probably want something more like this







simulate this circuit &ndash; Schematic created using CircuitLab

The buffers here represent ideal devices, with the non-idealities modeled by the R and C elements.

Notice in particular the capacitors are not in series with the signal path.

I'd also say that your capacitance values seem quite high. Values in the 5-10 picofarad range are more common, even for discrete logic ICs. Consult the datasheets for the parts you want to model to get reasonable values.