3 Input AND Gate with RTL Logic
simulate this circuit &ndash; Schematic created using CircuitLab

Figure 1. One simple test.

The circuit isn't very good.


(a) With the bottom transistor on you'll get a potential divider between R3 and R4 of about 1/3 through the base-emitter junction of Q3 so Y1 would be about 5/3 V = 1.66. With the transistor B-E junction the simulation shows that the actual output voltage would be 1.44 V. This messes up your LOW signal.
(b) With all three inputs pulled high you'll get Y2 = 4.13 V. Again this is a bit low for a HIGH.


The big problem with this is that your Y2 output can't drive another AND gate properly as the logic levels are deteriorating with each additional gate.







simulate this circuit

Figure 2. Another simple test.


(c) Y1 -= 2.1 V. This is a terrible result as it's almost in the middle between an acceptable HIGH and LOW. This sinks any chance of it being a working gate.
(d) Y2 = 0 V. At least this works.