DDR3 pcb design routing
So, i've finally assembled board with this design and DDR3 portion ended up working @ 333MHz. Although now i think traces is way too close to each other. W/3W rule must be kept.
EDIT: Keep in mind that this design have very short(relatively) clock line. Some calibration algorithms on some systems may not work.
EDIT: Yeah, my trace impedance is ~60Ohms. And there is no VTT/Vref ic on those images of mine OP.