How to assign a hexadecimal value to integer type in VHDL?
VHDL supports arithmetic values but it has to know if they are signed or unsigned. I recommend using the numeric_std library to support these types. 

VHDL is strongly typed. For your first question, I would use:

EDIT: I have erased a prior more complex form and used this simpler one after Brian Dummond's comment

constant mem_size   : integer := x"FFFF_FFFF";


The second, supposing address is an std_logic_vector, has to be written:

if unsigned(address) &lt; x"3FFFFF" then