LC filter - how to deal with additional inductor
The intuitive way is to use an impedance nomograph. 


My simple conclusion is you dont have a handle on your specs yet.  What is your signal impedance, track impedance ( too inductive) and load Z? 
I use 10nH /cm and 100nH is way too much 10cm) for 2% track width, so you better couple the track to ground and get a distributed impedance or a good "transmission line" or a   "controlled Impedance".


  This assumes you have some understanding of Transmission Line theory with mismatched impedances for step response.


It's hard to give a complete answer in 100 words or less , but your model is incomplete and you need to add larger and smaller caps to extend the bandwidth of power/gnd and lower the Z to match the DCR of the power plane which may be in x to xx mOhms. THen use 25 Ohm for ARM stripline/microstrip for clock signals.

As it stands you can add 1 Ohm in series and get critical dampening, but then your load regulation is poor. So you need to move towards an ideal voltage source with low Z over the whole spectrum of noise e.g. down to x ns rise time for CMOS. with fBW=0.3/tR

But 1st you need to memorize the real equivalent circuit of all capacitors and inductors and the values of track inductance for a given width/length ratio ( e.g. 2%) per mm or per cm like 10nH/cm.  There are lots of answers to this on this site which I and others have given.

Next you need to understand that %Overshoot or decay cycles of ringing is the inverse of Q where good speed and dampening is Q= 0.7~1 and Q=10 is bad like your signal with some unknown ESR in your model.

Next you need to understand that self resonant frequency ( sometimes called SRF ) but more accurately called PRF for parallel resonant frequency and SRF is series resonant frequency. (ignore this confusion  for now)

SRF can be a factor on any inductor, track or scope probe ground lead  due to inductance and conductor capacitance unless it is a well designed controlled transmission line with distributed RLC and matched load. ( or really short probe ground lead)

Next all cap. materials are different, where NPO ceramic and plastic film are about the best and ultra low electrolytics will have an ESR*C =T value &lt; 10us while gen. purp. (G.P.) will be > 100us.

Lastly when doing a transient analysis examine the step load impedance ratio to source impedance. THis means if using a CMOS or MOSFET with an equivalent C and RdsOn value, compare that to your power/gnd track impedance and decoupling cap ESR and SRF (plots of Z vs f avail from many suppliers) and beware of complex interactive resonance. ( look for my answers with ref to Murata Caps)

I could write a book about this, so this is just to wet your appetite on how to analyze any RLC circuit in seconds.


All inductors have DCR or ESR or series resistance and thus a ratio of T=L/R
All capacitors have an ESR . read up on my relevant answers or a good book.


most important for logic design


  
  controlled impedance stripline and microstrip is your friend for high speed signal design.  
  Memorize the (gap to gnd)/(track width) ratios to ground for a rule of thumb like roughly 1:1 for near 50 Ohms with e=4 or whatever which is the RdsOn of most 5V CMOS and 25 Ohms (+/-25%) for 74ALVCxx and ARM chips. ( your rule of thumb may be slightly different....)
  


- inductance factor is due to L/W ratio geometry only.
   -  So a 1mm x 1mm cap has the same inductance as a 10cm x 10cm ground plane.