Verilog - A line stays high, I need it to go low after a while
The best way (depending on how complex your final design will be) would probably be to use a separate fast CMOS oscillator for your CPLD system clock, and have it process the input pulses and output the stepper pulse.
This way, the clock is running all the time when the system is on, and it can time the period from the last input pulse - if it's above a certain limit, set the stepper line low. 

This is the way a typical synchronous design works, you have an independent system wide clock and this is used to "read" (i.e. into a register) and process external asynchronous signals (as opposed to the external signals clocking the logic directly)   

Another simpler way would be to have another input "reset" line that sets all the registers and outputs to a certain state when it goes low. You could then use a simple RC low pass filter on the input pulses so when they stop, the line drops low and the CPLD resets.