Truncate and other operations on the constant in Verilog
You're better off using localparam rather than 'define.

For example:

module blah (

);

localparam MY_YEAR = 16'd2017; //This is a local parameter which cannot be seen or changed outside the module

wire [7:0] w_year_byte = w_current_byte ? MY_YEAR[15:8] : MY_YEAR[7:0];

...

endmodule


Remember that with Verilog you are not working with computer programs, you aren't doing things in a procedural fashion, but rather describing hardware. If you want to access the MSB's or the LSB's, you can simply describe that - access them directly with the range selection operator ([MSB:LSB]) or part selection operator ([LSB+:WIDTH]).

Local parameters have the advantage over `defines in that they can be treated as constant wires - you can access the value of them in the same was as you would access the value of a wire.

Additionally you could easily change your localparam to a parameter which would then allow you to change the value of the parameter when you instantiate the module - this is one of the building blocks of reusable parameterised modules. If your goal is to have the parameters at the top of the file, this can sort of be accomplished with Verilog 2001 ANSI style module declarations:

module blah #(
    parameter MY_YEAR = 16'd2017
)(
    input whatever,
    output bob,
    input cheese
);
...




If you have your heart set on a `define, you can access it by converting it to a wire. For example:

wire [15:0] my_year_wire = `MY_YEAR;


Once assigned to a wire you can then access it in the same way as the parameter version above:

wire [7:0] w_year_byte = w_current_byte ? my_year_wire[15:8] : my_year_wire[7:0];