Confused with the output resistance of the CMOS inverter
&quot;What does it mean for the inverter (a digital circuit) to have low output impedance?&quot;
Inverters has 2 output states:

Vout ≅ VDD     (logic 1)

or

Vout ≅ GND     (logic 0)


Hypothesis: Vout ≅ VDD
Attach a resistor R to Vout.
R will draw current out of Vout.
Low output impedance mean that you can lower R as much as you want (*) without Vout dropping.
(*) Within certain limits

Example:
Vout = 3 V
R = 30 Ohm
If the inverter has 0 Ohm output impedance, than it will be able to deliver 100 mA to the load R and Vout will remain at 3 V.
If the inverter has 10 Ohm output impedance, than it will able to deliver 75 mA to the load R but Vout will now drop to 3 * (3 / 4) = 2.25 Volt.

Output circuits stages are designed to show low output impedance in order to set/impose the output voltage to the load.