State Space Average Model of Non-Ideal Buck Converter
If you examine all the parasitics of an IC_implemented regulator, including Feedback Node and Power Device drain/substrate capacitance, etc etc, you have about 12 order system.

How do you chose which of those to ignore?

I recall a guy hired to implement battery charger designs on silicon.

He had a PhD in switching regulators.

Two years after hiring, he still could not avoid "chaotic" behaviors in the circuits, ON THE BENCH.

Which of the 12 L or C elements are you ignoring? Do you care? Should you

=============================

The reason I mention these (numerous) parasitics is the need for quality mindset in design.

To produce a product that becomes very respected, known as trouble_free, and works well in many situations, despite silicon_process variations, seems to require AWARENESS of the design margins.

And design margins are not easily verified ON THE BENCH.

Design margins are a task for your brain, and possibly for a simulator.

For your reading delight, examine almost any issue of IEEE "yellow rag" Journal on Circuits and Systems in the 2000 --- 2005 era. Switcher stability was discussed in just about each of the 12 issues each year.