What is the purpose /name of this CMOS gate configuration?
Drawn as logic instead of transistors, it looks like this:







simulate this circuit &ndash; Schematic created using CircuitLab

The bottom branch is A &amp; !B &amp; C, the top branch is !A &amp; B &amp; !C, so the final expression is

$$OUT = A \overline{B} C + \overline{A} B \overline{C}$$

It isn't clear why this was implemented as multiplexers rather than a more conventional SOP circuit.