Memory chips, are the bits of a long word stored contiguously?
Does it actually read a byte at the same offset within each chip from 4 separate chips at once, and then merge the result?


Merge is the wrong term. A 32 bit system has a data bus that contains 32 wires. Each x8 chip feeds it's own set of eight from least significant byte to most significant byte.

For memory it's more about area than width or depth. 

If you want a 32 bit system, and can find a single 32 bit wide memory chip with enough "depth" to supply your application you may get away with a single device.

If your system has an address space of 1 meg and you can get 1meg by 8 bit devices then four of those is less parts than 32 1meg by 1bits. 

For similarly speed rated devices, it really all boils down to cost and real-estate.

Addition: 

Interestingly one of the major factors when designing a memory chip isn't so much how much memory you can get on the wafer but how big the footprint of the device needs to be to have enough pins to access all those data and address lines. 

In the old days when DIPs were king that meant large memory devices were aircraft carriers.. 



The above is a simple 64K by 8 device. Note the size of the wafer vs the device size. Most of the chip simply routed the pins to the wafer.