Multiple SRAM on one MCU
This would work fine. The gate propagation delay for the cs line will be in the datasheet for the part you use but they are normally small enough to not be an issue. Worst case you can add an extra wait state to the memory controller in the CPU.

Alternatively you could put the two memory chips in parallel rather than series. 
Instead of using 2x 512K x 16 SRAM you could use 2x 1M x 8 SRAM. The price is the same, which makes sense since it's the same amount of memory.
You then connect all of the address lines to each chip. D0-7 go to the first chip, D8-15 go to the second.
You still have to route all the address lines to both chips but each data line only goes to a single location so in theory layout is a little bit easier.

The down side is that if you later decide you only need half the memory you can't simply remove one of the chips to halve the RAM fitted.