Why I do not need to ensure I have no latches in sequential process [VHDL]
When we say it's bad practice to infer latches, what we are talking about is transparent latches, which are level sensitive, and generally have poor timing performance in an FPGA.

A sequential design infers flip-flops, which are edge sensitive on their clock input (and possibly level sensitive on set/reset inputs). Unlike latches, the FPGA is specifically designed to have good performance when implementing sequential designs using flip-flops.

The reason that not assigning an output in certain branches in a sequential process is not harmful, is that doing this will in general infer 'enable' logic for the flip-flop. As a result, its performance is not degraded, as it still operates in an edge sensitive mode, based on the clock.

Latches are not 'bad' per se, they are just not the intended design method in an FPGA. There are scenarios where an external interface mandates the use of latches. They are not always a mistake, you just need to understand when and where they might be appropriate.