Why putting more logic seems to increase working frequency?
One can only guess and you probably guessed correctly.

The real question is does it matter?  If you were okay with 112Mhz then it should not matter.

When I was doing chip design the simulator used the track capacitance from one corner of the die to the opposite corner to calculate worst case delay. A smaller die would have shorter delays.   

My guess is when more real estate was available the maximum delay was longer. Now your logic will be routed in a smaller area so the delay times will be less.

If it matters, ask Xilinx.

There is also the possibility that the ILA introduced some relaxed time constraints.  The ILA is supposed to inherit your time constraints. Maybe if you had none your timing defaults to constraints defined in the ILA.