Procedure tips for connecting traces between DDR3 SDRAM and FPGA
You may wan't to route those signals with a controlled impedance, which makes it almost mandatory to have an uninterrupted plane on an adjacent layer. Xilinx suggests IIRC 40 Ohm routing impedance for DDR3 on Zynq, which will create fairly wide traces if you are not using very thin laminates.

Concerning the pin-out on the CLG400 package you are right, it's quite a pain for DDR3 routing, especially when comparing with SoC optimized for low-cost 4-layer boards.

You may also want to check if you can route two tracks on the outer layer between two BGA balls. With the 0.8mm pitch, this leaves you with something like 0.3-0.4mm pad diameter and 0.08-0.1mm track/space. Something which probably not every PCB manufacturer will do.

I suggest you to have a look on the layout of the MicroZED to get some inspiration.