Divide By 5 Up Counter 6 to 10
This circuit should provide what you need.  It uses a 74HCT191 counter, with binary presets so the counter can be initialized to 6 with a reset pulse.  It then advances on each clock pulse, 7,8,9,10 and 11, but because of the decoding of the output for 11 (binary 1011) using the four-input AND gate, it resets back to 6 again.  The count of 11 will temporarily -- and we're talking nanoseconds -- appear on the output before it changes back to 6; that could be avoided with more logic if it is a problem.

This circuit could also be implemented using a 74HCT163 counter, since it also has preset inputs.

It would also be possible to do this with a 4-bit counter and a 4-bit full adder (such as a 74HCT283), as someone else suggested, but this would require an extra IC.  The problem with the very short race condition would still be present, as the counter would have to reset from 5 to 0 instead of 11 to 6.



The inverter could actually be eliminated, and the 4-input AND replaced by a 3-input one, as it is not actually necessary to decode bit 2 (QC).  The counter can be reset using the output 1x11, where x is either 0 or 1, this works because the counter will be reset at 1011 (11) and never reach 1111 (15).

If you need to implement this circuit using discrete flip-flops rather than a using timer chip like the '191 or '163 chip, I suggest looking at the logic diagram for the 74HCT163. It is a little simpler than the 74HCT191.  There are also plenty of circuits on the web; for example the beginning of this article has a binary 4-bit synchronous up counter; you would just need to add the preset logic.