Verilog inital value for flip flop
You are using c as an active high reset, then setting the value to c rather than  1'b0. It is active high so c is always 1 when this code executes. The solution to this is the reset condition to 0 not c:

always @(posedge clk or posedge c) begin
  if (c) begin
    x &lt;= 1'b0; //Reset Condition
  end else begin
    //x &lt;= ...;
  end
end 


Your code makes use of an initial and asynchronous reset. This does not really represent any type of hardware you have to choose one or the other, you can not have both.

The waveform in the question does not show the async reset being applied at the start of the simulation. you should apply it for at least 1 clock cycle and release it on the posedge of your clock.