Splitting a ~100 MHz clock on a PCB
The input impedance of the clock inputs is usually high (like CMOS
  inverters).


An input with a parasitic capacitance of 5 pF presents a reactive impedance of about 318 ohms at 100 MHz.


  it enters multiple ICs (say 3 for now)


Ignoring transmission line effects that's about 100 ohms reactive input impedance.


  Can I just make a star connection from the SMA connector to the
  various destinations or do I need some sort of buffers?


It all depends on the driving impedance of your 100 MHz source - if it is low enough and the sensitivity of the 3 receiving chips are low enough it should be OK without buffers. Buffers have input capacitors too!


  Is it enough to terminate once at the connector and use simple PCB
  traces to the destinations?


It might be; 100 MHz has a wavelength of 3 metres and a general rule of thumb is you can avoid nterminations if the track/cable length is less than one-tenth.


  Should the traces be such that the characteristic impedance is 50 Ohm,
  50/#consumers or just as thin as possible?


It's probably not going to be a big problem given track lengths but if it were you would match to the impedance of the source and this might not be 50 ohms. You didn't state what it was.