Verilog intermediate bit precision
No, using an intermediate assignment does not solve your problem. 

HDL languages do not work like C. There still is a continuous timing path from seek_address to address_delta.

To break the path you must e.g. insert a register. But that may stop your design from working as seek_end will arrive one clock cycle later.

Your calculation will not be done in 32 bits. Maybe in a simulator but the synthesis tool will remove all superfluous bits. 

You do not tell us how fast your design must be, but as Elliot Alderson already suggest in the comment: three 16 bit adders are rarely critical. (The rx_address_in &lt;&lt; 2'd3 does not cause any delay.) Unless this expression is part of a logic cone.