How to output downsampling bus in single stream on fpga? (verilog)
I dont want the 'dov' flag to behave like a clock once up and once down.


Yes, you do.
You need a data valid flag and your 'dov' is just what you need. You can then use that as enable in the following stages of your design. The only issue is that at the moment it is out of phase with your data: shift it back one clock cycle. 


  once the data is ready I want all the data to out continuously.


You can't and honestly you don't want to. 
You are discarding X out of Y samples thus your data is no longer continuous. There is nothing wrong with having gaps. 

Why do I go against your wishes?
The only way to get what you want is to re-clock the data into a new, slower clock domain. For that you will need to make that slower clock. That is most difficult and very error prone. Even more so if it is programmable. We had users twice this week who made a slower clock and both had major problems in the implementation (The simulation was all fine, the FPGA did not work!).

A good, simple design has one clock and one clock only. If your data is not continuous, just use an enable.
You should avoid multiple clock domains like the plague and definitely not generate them yourself if there is an alternative.