Learning how to do DC and AC operating point biasing for a single transistor amplifier circuitry
Your circuit is a pulsed sine wave from the negative bias and saturates the collector hard, so it acts like a switched diode rather than a linear amplifier.
A CE amp is high impedance  with no R load LC will have very high Q &gt;&gt;100. But when driven by a low impedance switch, has a very low Q.  The result is the average of these two Q resonant load conditions.
Neither a voltage source nor a current source but a switched current source determined by input bias and signal voltage. With a large time constant on the input cap the base will act as a positive clamp and the average DC voltage thus reducing the conduction time.  Then at resonance the output saturates hard again and increases input current and LC current theoretically rises to 37A with an ideal transistor with hFE=100 just below 15.6MHz
You would likely achieve greater than Q=100 with a 10 Ohm load becuase of DCR and ESR of L,C parts and your AC source has ZERO impedance, driving Vbe into excessive Ibe.
You can play with it here

When you compute LC resonance , look at the Impedance and understand why Inductor I/ Cap V is always 10 here.

Above changing sampling time Options&gt;Other options&gt; from 5n to 5p (s)