Verilog - Using 'define' to declare a constant created by a 'parameter'
There's usually no need to do this in Verilog. (You must be coming from VHDL) Numeric literals get implicitly padded with 0's or truncated to fit into the assignment LHS variable. This also happens when used in most expressions.

someReg &lt;= 'h8f;


There are a few exceptions that require the exact size, like in the middle of a concatenation. For that you can use a bitwise OR.

biggerReg &lt;= {prefixReg, {BUS_SIZE{1'b0}}|8'h8f, suffixReg};


SystemVerilog has a bit-sizing cast that makes this a little simpler

biggerReg &lt;= {prefixReg, BUS_SIZE'('h8f}, suffixReg};