VHDL - Why does frequency divider counter max at one less than half period?
0 to 124999 is exactly 125000 counts. Starting at zero is a simple convention that can make some code a bit simpler (like working with lists and pointers), but it means that you increment to one less than the number of iterations you need.

Generally when you build a divider like this, you are interested in the half period so you can invert once every half period and get a waveform with a perfect 50% duty cycle.