How to theoretically determine max clock speed for a circuit?
--- prop delay of gate? At what voltage, what Cload, what inputSlewRate? Is gate crafted for minimum shootthru charge, or min delay?

--- yes, the fab's secrets produce different timing results

--- reference results? sure. You can always tweak the W/L in older processes. In newest, the optics of the exposure machines may constrain your choices, what with diffraction-limited layout.

--- How simple? The fanin, the fanout, the length of metal, if poly (HighR) is used, the # bulk ties to constrain charge upsets (jitter).

--- How big a variance? In older processes, between 1volt and 6 volt VDD, the delays easily are 100:1. In some cases, you want ~~ zero rail upsets (for AutoZero opamp internal clock generation), and very slow gates/FFs are fine.

---  Can I determine the # gates------lotta other factors: bus fanout, for example.