Generating i2s Clock Signals
For a delta sigma converter, MCLK is actually the critical one (It feeds the modulator), with the other two derived from it. 

The common options are to use a PLL to derive this from LRCLK or (better) BCLK, or derive all three from a rock and divider chain (This usually gives the best quality, but you will need two rocks to accomodate the 44.1 and 48kHz derived rates unless you use a PLL like the 1708), in this case you run both interfaces in slave mode. 

The PLL1708 plus a rock will get you an MCLK for all three possible rates, but you then need to divide this down to generate the serial and frame clocks, and you will need to run both sides of the interface in slave mode.
Note that the LS294 is a 5V part!