Question about forcing verilog netlist signals in simulation
Put the signal name within curly braces, and include a space after the escaped signal name.

force {/tb/inv_dual_tb/GF_INV_8_tb/\pmul/himul/abcd } 0 0ns


Another option, or simply as a way to check the proper TCL syntax, is to apply the force in the GUI and see what is echoed to the transcript window.