Input / output behaviour of dynamic latch
Presumably the &quot;in&quot; signal is being driven by a source that is strong enough to overcome any remaining charge on the input of &quot;1&quot;.
The diagram you are showing is only a partial depiction of the system and there is no indication of what is to the left of &quot;in&quot;.  But in an actual circuit that would be the output stage of a logic device or circuit that is designed to overcome the input capacitance of the &quot;1&quot; block.