HDLCompiler:251 - Cannot access memory directly Error
Verilog does not support two dimensional arrays or unpacked arrays as ports; SystemVerilog does. Verilog does support a packed array (also referred to as a vector) as a port.

For verilog, you need to pass the index. Examples: .packet_size(packet_size_temp[0]), or .packet_size(packet_size_temp[reg_or_wire_of_index]),.
If you need to pass the whole array, then you will need to flatten it to one big vector and slice it on the other side:

...
reg [NUM_QUEUES*IN_FIFO_DEPTH_BIT - 1:0] packet_size_temp__packed;
always @* begin
   for(idx=0; idx&lt;NUM_QUEUES; idx=idx+1) begin
     packet_size_temp__packed[idx*IN_FIFO_DEPTH_BIT +: IN_FIFO_DEPTH_BIT] = packet_size_temp[idx];
   end
end
...
Deficit_Round_Robbin_algorithem
  #(
    ...
  )
  algorithem_module(
    ...
    .packet_size(packet_size_temp_packed),
    ...
  );
...


Review on +: stackoverflow: Indexing vectors and arrays with +: and 
What is +: and -:?

Enabling SystemVerilog is alternative, it does support arrayed ports. To do so, it is recommend the change the file extension from .v to .sv. Most simulators and synthesizers will properly parse the file with only the correct extinction. Another approach is to set a compiler flag which is tool dependent (usually -sv or -sverilog), but this will typically force all Verilog files to be treated as SystemVerilog which may have naming conflicts with SystemVerilog keywords.