ALD1106/1107 transmission gate "off" state behaviour in LTSpice
These transmission gates are built with 4-pin MOSFETs for a reason: the 4th pin must be tied to the lowest (NMOS) or highest (PMOS) voltage potential. With these in mind, here's a reworked version:

Notice where the 4th pin of each MOS is tied up to. Also, there is no need for a loading resistance in this case: R is .stepped between 10k (on) and 1g (off), and the output is virtually the same. In real life, you would have some sort of load, though.