How I can enable and disanable a verilog module
Most likely what you want to do is instantiate both modules and then select the output that you want and ignore the output that you don't want.
Something along these lines:
module TopModule(
    input wire clk,
    input wire reset,
    input wire [7:0] aci,
    input wire sel,
    output wire [15:0] sonuc
);
    
    wire [15:0] sonuc1, sonuc2;
    
    assign sonuc = sel ? sonuc1 : sonuc2;
    
    CosLut CosinusLookUp(
        .clk(clk),
        .reset(reset),
        .aci(aci),
        .sonuc(sonuc1)
    );

    SinusLut SinusLookUp(
        .clk(clk),
        .reset(reset),
        .aci(aci),
        .sonuc(sonuc2)
    );
    
endmodule