State of mutli-cycle processor during execution of instruction
Indeed, the start of the next instruction is blocked.

The usual way to model multi-state systems is using "finite state machines" - it is a HW logic which switches between numerous states based on:


The current state
The inputs


The outputs of a module controlled by FSM is also defined by the FSM's state and the inputs.

What happens in our case? New instruction may only be fetched in the initial state - lets call it IDLE. Once the instruction was fetched, the FSM starts to switch between operational states (for example: IDLE->DECODE->EXECUTE->WRITE-BACK->IDLE). When in a state which is not IDLE, the logic is forbidden from fetching new instructions. Therefore, the new instruction will start to execute only after the previous one ended.