Initialising FPGA internal RAM from file
I'm still not fully understanding your question, so I'm answering what I think you want.
What you can do is read a different file for each ram. You do that by constructing the file name dynamically.
Example:
in 0.txt
0101
1010

in 1.txt
0110
1001

the VHDL(-2008):
library ieee;
package array_types is
    use ieee.std_logic_1164.all;
    type slv_array is array (natural range &lt;&gt;) of std_logic_vector;
end package;

use work.array_types.slv_array;

entity ram is
    generic(ram_init : slv_array);
end entity;

architecture rtl of ram is
    subtype ram_data_type is slv_array(0 to ram_init'length-1)(ram_init(0)'length-1 downto 0);
    signal ram_data : ram_data_type := ram_init;
begin
end architecture;

entity init_ram is end entity;

library ieee;
architecture rtl of init_ram is
    constant ram_width : positive := 4;
    constant ram_depth : positive := 2;
    use work.array_types.slv_array;
    subtype ram_data_type is slv_array(0 to ram_depth-1)(ram_width-1 downto 0);
    
    use std.textio.all;
    use ieee.std_logic_1164.all;
    impure function load_file(index:natural) return ram_data_type is
        constant file_name : string := integer'image(index)&amp;&quot;.txt&quot;;
        file file_pointer : text;
        variable line_data : line;
        variable line_value : bit_vector(ram_width-1 downto 0);
        variable ram_data : ram_data_type;
    begin
        file_open(file_pointer, file_name, read_mode);
        for line_index in 0 to ram_depth-1 loop
            readline(file_pointer, line_data);
            read(line_data, line_value);
            ram_data(line_index) := to_stdlogicvector(line_value);
        end loop;
        file_close(file_pointer);
        return ram_data;
    end function;
begin
    gen_rams: for i in 0 to 1 generate
        inst_ram: entity work.ram
            generic map(
                ram_init =&gt; load_file(i));
    end generate;
end architecture;

Result:

edit
of course you could also create the random value inside vhdl.