adding dc bias to my signal
Analyze the circuit with the capacitor C6 open (DC analysis) and you will see that it is a unity-gain buffer connected to the junction of R10/R11. 

So, if they are both value R the voltage at the non-inverting input will be 10V with S1 closed, and the voltage at the output will also be +10V, ideally. 

To the extent the circuit is linear (pretty good approximation until the op-amp saturates) the output will be the sum of the +10V and the AC-coupled input through C6. The gain from the latter node (right-hand side of C6) is -1, of course.



Note: from the left side of C6 it may have a gain of almost -1 or not, because we don't know what frequency the AC sine-wave input is nor the value of C6. If C6 is very large the gain will be close to -1. If the reactance of C6 (which is \$\frac{1}{\omega C_6}\$) starts to get comparable to the resistance of R9 the gain will become smaller in magnitude and the phase will lead the input by more and more, until at very low frequencies you have almost no AC voltage at the output and a phase shift of +\$\pi/2\$.