When might a standard cell optimized for zero wireload capacitance be used?
This is one of those nonsense areas you run across.  Inside an IC there is very minmal inductance, so you end up with delays that are dominated by RC's and not RLC's.  If you have RLC you get wave equation propagation and thus must deal with transmission lines and reflections etc.  But the same PDE's (Partial Difference equations) when used with RC result in the diffusion equation and you don't get transmission lines (except in very rare cases with very long runs).

In fact pop by this page and look at the V4 driver which is "optimized" for zero wire load.  The O/P drivers are identical to the the other minimal drive device, which indicates that there is no matching taking place.  The only real difference is that they've reduced the P Widths in the logic cell so that the \$T_{rise} T_{fall}\$ is no longer matched.

The lower cell is the "optimized" one (snip taken from that link):



Having a cell like that might be useful, but not for the stated reasons.  Capacitance is capacitance is capacitance wrt to how you drive it.

I would look into the cell and check out the transistor sizing's to make sure they haven't done something funky.