Controlling MAX31855 via SPI with Verilog from FPGA
My plan of attack was to have two clocks, one for SCK and one for CS.


I think this is not a good idea:

Looking at the data sheet you can see that the clock signal must be low when there is an edge in the CS signal.

I would use a counter - for example a 6 bit counter driven by the clock. Depending on the counter value I would do:


0: SCK=low, CS=low
1...32: SCK=clock, CS=low
33: SCK=low, CS=low
34...Max: SCK=low, CS=high


The shift register would shift on the falling edges of the SCK signal; the value in the shift register would be evaluated on the rising edge of the CS signal.