Enhanced 16F PIC: How many instruction periods does automatic_context_save require?
The information I was looking for is in the datasheet - just not quite where I expected it.

Section 8.2 of the PIC16F1782 datasheet (page 75 of document DS40001579E) states:


  Interrupt latency is defined as the time from when the interrupt event
  occurs to the time code execution at the interrupt vector begins. The
  latency for synchronous interrupts is three or four instruction
  cycles. For asynchronous interrupts, the latency is three to five
  instruction cycles, depending on when the interrupt occurs. See Figure
  8-2 and Figure 8.3 for more details.


This information allows me to determine the maximum time that will elapse before my ISR is executed.