How to determine rise time from a datasheet?
TL;DR you should get sub 2nS rise times from this device, into practical loads

Most of your assumptions and some of your sums are wrong.

To deduce the risetime, that's relevant to the logic situation, you would use the output current into the output capacitance.

The total output capacitance is likely to be the 4.5pF you've identified, plus extra for the pads, traces, and the input of the next load (or loads), so could be much higher. Reckon on 20pF. Buffers that are intended to drive loads are often specified into the loads of 15pF and 50pF.

Charging this output load is your gate output current. On page 3 of the data sheet, the high output is specified to be at least 24mA output, when the output voltage is 2.2v, with a rail of at least 2.7v. This is the minimum, you can expect the current to be higher when the output voltage is lower, say slewing through the critical mid-rail point. How much higher? Some data sheets give graphs of output voltage and current, this one doesn't. So we just know it's higher.

What matters to your downstream logic is the time from a valid logic low to a valid logic high voltage. Traditional RC measurements are not relevant, like 2.2RC, totally meaningless. The low and high input values are specified as 25% and 75% of rail voltage, so you need to time the output voltage through a 1.65v swing, let's say 2v for easier sums and a more pessimistic case.

Let's say your load capacitance is 24pF (so I can do the sums in my head, and also a more pessimistic case). This is being charged at a minimum of 24mA, so at a minimum rate of 1V/nS. This will give you a risetime across 2v of no more than 2nS.

We have to do the down-going sums as well, a gate that swings fast in one direction and slowly in the other is no good to us. Top of page 4, low level output current at 0.55v output, at least 24mA. 0.55v is beyond the valid low logic level, so we can use the same numbers, and obtain a 2nS maximum fall time.

However, is risetime what you should be worried about?

The data sheet does give the propagation delay, and if you look at the timing diagram figure 2, this is specified to 50% output voltage, so includes delay through the gate
plus half the risetime
and has a maximum guarrantee
and is into a practical load capacitance of 30pF with a resistive load as well

I think the reason the data sheet gives a well-specified figure for propagation delay, and is mute on risetime, is it's the propagation delay that designer's use when they are designing a system. 

Pro tip. If a datasheet doesn't have figures for what you think you need, and does have figures for something you don't understand, then ask yourself why.