How does CPLD propagation delay work?
The delay specification in a CPLD is the maximum (i.e. worst case) pin-to-pin delay. That is, the maximum delay it takes for a signal "edge" to propagate from any pin to any other pin through the internal (combinational) logic.

Saying that a CPLD doesn't have a clock is misguided; you can use a pin as a clock input to feed sequential logic. Comparing it to a microcontroller is also not really suitable, since CPLDs implement hardware, not software.