Xilinx Design Summary
In general: If your design does not meet timing, this is bad. You might see errors on the FPGA that you will not understand. So always get rid of such warnings before you start evaluating on real hardware.

The timing constraint that has not been met indicates that you have a 100 MHz clock. Is this the case? What is your target FPGA? What kind of design entry method do you use (Schematic or HDL)?