VHDL: Real addition leads to 'bound check failure'
I'm sorry for my late reply, I got caught up in other stuff yet again. I managed to update my code the way @user8352 suggested to get it to run, so here are the working versions:

entity floatALU is
    port ( x, y : in real;
           f1, f0 : in bit;
           z : out real );
end entity floatALU;

-- behavrioal body
architecture behav of floatALU is
begin
    calculate : process ( x, y, f1, f0 ) is
    begin
        -- I combine if and case statements on purpose here
        if f1 = '0' then
            case f0 is
                when '0' =&gt; z &lt;= x + y;
                when '1' =&gt; z &lt;= x - y;
            end case;
        else
            case f0 is
                when '0' =&gt; z &lt;= x * y;
                when '1' =&gt; z &lt;= x / y;
            end case;
        end if;
    end process calculate;
end architecture behav;


And the test bench:

entity floatALU is
    port ( x, y : in real;
           f1, f0 : in bit;
           z : out real );
end entity floatALU;

-- behavrioal body
architecture behav of floatALU is
begin
    calculate : process ( x, y, f1, f0 ) is
    begin
        -- I combine if and case statements on purpose here
        if f1 = '0' then
            case f0 is
                when '0' =&gt; z &lt;= x + y;
                when '1' =&gt; z &lt;= x - y;
            end case;
        else
            case f0 is
                when '0' =&gt; z &lt;= x * y;
                when '1' =&gt; z &lt;= x / y;
            end case;
        end if;
    end process calculate;
end architecture behav;


Thank you all for your help!