Viewing verilog enums in iverilog + gtkwave
This is a workaround:

Steps:

Create a file with the extension gtkw. This file contains how you want the state variable to be displayed on the waveform. For your example it would be:

00 STATE0
01 STATE1
10 STATE2

Because you have used logic type which is 2 bits wide and have not encoded the state variables, SystemVerilog assigns the state variables the default values in ascending order. In this case the default binary values would be from 00 to 10 since you have 3 State variables.

Open the waveform and dump the signal. Do  Right-Mouse -&gt; Data Format -&gt; Translate Filter File -&gt; Enable and Select. The Select Signal Filter Dialog Box opens. Then left click on Add Filter to List button. Select the gtkw extension file that you created. This file will then be displayed in the Select Signal Filter dialog box. Select your file in the Select Filter Dialog Box, make sure it is highlighted, then left click on the OK button. The binary signals in the waveform should be replaced with the enum values.