Generating Asymmetric AC PWM with MOSFETs
First of all is not that a gate driver will necessary blow the MOSFETs… depending on the part the 'logic level' indication is simply to say that the Vgs(th) is low enough to do some useful switching even with a logic level signal. Many of these are in fact rated at both 4.5V and 10V gate drive. Of course there are MOSFETs with Vgs(max) of 8V and maybe even less so it's wise to check the datasheet.
You can also do a simple gate drive with a trivial class B transistor pair. The issue is if you need a push-pull gate drive (recommended for PWM) or you only need a pull down and let it go back with the pullup resistor (for the high side, the converse for the low side). That's difficult to evaluate without the exact specification, gate charge and at least an estimate of the dissipation in the MOSFET (switching losses will be predominant in this case).
The top side is usually the difficult part but not in this case. Your schematic will potentially apply the 30V to the GPIO (altough thru a 10k resistor); in practice if will probably work but it isn't wise (neither it is good practice). Also you will be applying 30V of Vgs to the P-channel MOSFET and you probably don't want that. A zener would fix that.
Just pull from somewhere an 'adequate' gate drive voltage (the power rail with a zener) and a pair of transistors.
The low side is somewhat tricky, but remember that 'ground' is a subjective term. You can simply anchor your drive circuit to the -10V as ground. Your original ground will then become a +10V supply, which is great for driving gates (or use some regulator to get a -5V rail, if you are Vgs constrained).
Now the problem is shifted: you have a correctly driven low gate but you need a -10V to -5V (assuming a 5V logic) driver control. However, this is not so critical as timing so you can use a pullup resistor (as an aside: real translating drivers use a latch and two translation lines, but they are ICs). Either use a suitable optocoupler (easiest way) or use a current line to translate the level.



simulate this circuit &ndash; Schematic created using CircuitLab
Something like this should more or less work; the drive pair are often implemented as BJTs, it doesn't really matter at these power levels. Be careful with the low side drive polarity: the translation line will invert it! Also verify biasing extremes, I didn't really thought through all the circuit, it's most like an idea to work on.