Understanding (PVT) Corners
Mostly PVT (Process, Voltage Temperature) variations are corners that are considered.  Most other variation is swallowed up in the process part - like stress etc.

Not every foundry does a Slow, Typical, Fast corner.  Many do a FF, SS, SF, FS  (Fast Fast, Slow Slow etc. for NMOS/PMOS) and some even do power corners, current consumption and perhaps leakage current splits also (it depends upon the focus of the process, low power high speed etc.)

In every case however, the corners are set by statistical analysis of actual silicon runs.  What is typical is a 3 Sigma limit but that sometimes varies by fab too.

The factors that govern corners is the product specification and mainly the operating conditions. I've had systems that the temperature was actively controlled so we only did P variation (after tightening up the Voltage spec.) but we needed to understand the process spread across the die, which is typically wrapped up in the 3 sigma limit. This entailed a separate analysis of the process modules on wafer.