Two voltage internal power plane
There is one reason why not to do this - If you route high speed signals over the gap between +12V and +3.3V planes, you're getting a double dose of signal integrity issues and EMI transmissions. 

As long as you're aware of that, there's indeed no reason not to split power planes. There are ways around that problem such as using a capacitor next to the lines to "stitch" the power planes together at RF or perhaps by adding GND copper to the power plane where possible.

Note that "high speed" is highly fuzzy term. In today's gigabit clock speed environment 10MHz may appear to be more or less DC. However the clock edges contain far higher frequencies that won't be happy about discontinuity in reference plane.