T-type Flip-Flops with state-dependent switching times
Let me just start by saying that really, using a &mu;C is infinitely easier. Tiny10, for example, would even be cheaper than many other chips you'd need in any of the solutions and be as small as a transistor. But hey, here goes:



If you don't mind it "flip-flop'ing" every 5.5seconds, this will do:







simulate this circuit &ndash; Schematic created using CircuitLab

Say Output is Low, NOT1 is pulling up the capacitor through R3, to compensate leak and such, when you press the switch you discharge C1 through D1 and R1 at a rate dictated by R1. At some point the output will toggle high.

Now NOT1 keeps the capacitor discharged, just as it kept it charged before. It will also re-charge the cap if you happened to hold the switch 2 seconds, then waited a while before trying to turn it off.

If you now press the switch, you will charge the capacitor through D2 and R2 at a lower rate dictated by R2.

The pressence of NOT1 and R3 will mess a bit with the standard NE555 rule of t=1.1*RC, so some tweaking of the cap or resistors will be needed, but in principle, these values should be close to what you need.

As said though, keeping SW1 pressed will toggle on/off repeatedly until you let go.

If there's instability when no button is pressed R3 might be too weak to compete with input pin currents, that depends on how old your NE555 is, most likely, in which case decreasing the Resistors and increasing C1 accordingly should help.

You could even get rid of the NOT1 by:







simulate this circuit

(and then add the rest of the earlier schematic)

Since the 100k on 3.3M will not make any difference to the tuning to any noticeable extend.



If you need a single-ramp-up, you can also do something like this:







simulate this circuit

When you press the switch C1 will charge through R2 and eventually pass the threshold of OA2, which will trigger the SET output, if you keep the button pressed it eventually passes the OA1 threshold, triggering the RESET output, which then also resets the SET to low.

You can feed that into your fevourite R-S-Latch/FlipFlop. If you need to feed it into a J-K Flipflop with R and S, you will probably need active low outputs, so you will need to flip the op-amps' inputs, to get inverted operation and then make the transistor a PNP connected to VCC in stead of GND.

When you let the switch go the capacitor will discharge through R1 and D1, which will go much more quickly. The residual charge left by the diode voltage drop will eventually be eliminated by R2 and R1 together, but with a BAT54 type the residual will be below 0.25V.

First you tune the set-time with R2 and C1 or by fiddling with R5, then you can tune the reset-time by fiddling with the balance between R3 and R4 (keeping R4+R3 approcimately the same, else you will also again change the set-time).

Some R-S latch/flipflop types do have a Last-Signal behaviour when both Set and Reset are active, then you won't need the R7 and Q1. They are only needed if the chosen latch has "Undefined Behaviour" when both S and R are active.

Check that the final op-amp choice reaches close enough to both supply rails to be able to give reliable coupling to the logic. Very old fashioned ones (uA741, for example) may not even manage that when powered with only 5V. But most moderny ones will probably do so.