VHDL "can't match slice type array type"
Your ports are of "std_logic_vector" type but the internal signal Out5bit is unsigned.

Numeric_std doesn't provide an "+" operator that adds the first type and returns the other, so no matching "+" operator is visible.

Three approaches to fix this:
1) Type conversions from std_logic_vector to unsigned and back again. Ugly, but clearly describes what you are doing - interpreting a std_logic_vector (essentially a bag of bits) as an unsigned number.

2) "use" certain non-standard libraries that provide such operators. Can cause ambiguities especially if you also have signed data...

3) Declare the ports unsigned. In addition to just working, it clarifies the design intent - this unit operates on unsigned data (not signed, or arrays of boolean flags, or character data etc)

You also have to coerce "Cin" to an unsigned number as Elliot points out...

Cin is a std_logic 

(0 =&gt; cin) is a 1-bit array of std_logic (which should be compatible with unsigned). Note the syntax uses "named association" ... the "positional association" version of a 1 bit vector would be (Cin) which the compiler cannot detect as a vector unlike the 3 bit vector (Cin,Cin,Cin) 

unsigned'(0 =&gt; cin) is explicitly unsigned.