How is this simple counter implemented on an FPGA without a clock?
You're right in thinking that you will have to use something for a clock for the counter. Otherwise there is nothing to tell it when to count. Either the clock is missing from the diagram, or you will have to edge-trigger on the enables, in which case the circuit you think it should have synthesized to is impossible, as you can't drive the same register with two different clocks. You might try something like:

en_either &lt;= en_up or en_down;

process (en_either, rst)
begin
  if rst = '1' then
    count &lt;= (others =&gt; '0');
  elsif rising_edge(en_either) then
    if en_up = '1' then
      count &lt;= count + 1;
    else
      count &lt;= count - 1;
    end if;
  end if;
end process;


There may be better ways, but if you really can't have a clock, I suppose that will work. If the enables overlap in any way, of course, this may not work as intended.

As the error message indicates, your two-process version will not work because you're driving the same signal from two different processes. There may be ways to work around this, but it would be much more trouble than the 1-process version.

As David points out in the comments, this will not work properly unless your enables are bounce-free. The source of the enables isn't clear from your post.