difference between using reset logic vs initial values on signals
Some comparisons I can think of quickly:


Initial values on flipflops only work in FPGAs (not ASICs)
You have to reinitialise the whole device to get back to the FPGA initial values (at least until you start dabbling in partial reconfiguration.)  This takes time, whereas a reset takes a single clock cycle.
You can have a variety of reset signals which allow you to set different parts of the device back to their original setting.
In FPGAs, you can use initialisers to set the values in a ROM or RAM block - you can't do that with a reset clause.


In the olden days, some FPGA synthesisers just ignored initial values and set everything to initialise to '0', so some FPGA design guidelines still frown on explicit initialisers.

As Joe commented, initial values can seem not to work on signals which are not flipflops, which can cause confusion.  This is because (usually) non-flipflop signals are driven by pure logic, which means they take on a value as soon as the simulation starts running based on the inputs to that logic:

 s &lt;= x and y; -- any initialiser will be overwritten by x and y immediately.


An example where this doesn't happen (which is sometimes useful in testbenches, but not synthesisable):

signal s : std_logic := '0';


then

s &lt;= '1' after 100 ns; -- s will be '0' to start with and '1' after 100 ns