Question about VHDL instantiation
For simple setups, you can get away with directly instantiating entities:

entity aaa is
    port( ... );
end entity;

architecture foo of aaa is
begin
    ...
end architecture;


And then in the other source file:

architecture foo of main is
begin
    AAA : entity work.aaa
        port map( ... );
end architecture;


That is the quickest way to not repeat yourself too much.

Separate component declarations inside a package become useful if you have exchangeable parts and multiple different configurations that combine them in different ways. Unless you need that, go with direct entity instantiation.