AVR: why reading data have some delay from writing it in SRAM (Timing diagram)
The delay is the read access time of the RAM.

In the case of writes the data comes from the ALU or other part of the CPU and is destined to be stored in RAM.  The data has to be maintained until it has been stored in the RAM memory cells.

For reads the RAM logic does not start operating until it has the address as shown in the second waveform.  First the address has to be decoded to enable the specific bit cells that contain the data.  Then the data has to be sensed and communicated through the RAM data buffers.  For the ATmega 328 this probably takes a few 10's of nanoseconds.