Automating test vector in Verilog HDL
'for' loops exist in verilog, but they look like this:

for(i = 0; i &lt; 2000; i = i + 1) begin
 A_t &lt;= i;
 #1 $display("F_t = %b", F_t);
end


There is no ++ operator and you have to use begin and end.

It's a very reasonable way of automating the inputs. Of course you have to get the timing right, which in your case is done with that #1 there.