Can we reduce power consumption of digital interfaces by using high impedance transmission lines?
While, in theory, high impedances would reduce power dissipation for the same voltage swing, there are several important issues in practice.

1) It's the power, not the voltage, of a signal that determines signal to noise ratio. If you must swing the full rail, then you'd win by increasing the impedance. However if you launch a specific power, then low impedance is not so much of a problem, just reduce your swing.

2) It's not physically practical to get impedances of much more than 100 ohms on a board. The signal conductor needs to get unmanufacturably thin, the space to the ground plane space-consumingly large. The impedance goes as the log ratio of spacing to centre, so you rapidly run out of improvement.

There are other reasons we like a fairly meaty centre conductor, as well as the fab being able to make it. The copper losses vary inversely with the conductor surface area (all the RF flows in the surface), and in fact 75 ohms is the lowest loss geometry (which it why it's used for receive antenna feeds). The highest power handling geometry is around 35 ohms, dependant on heating and surface electric fields. These two figures are why 50 ohms was chosen as a compromise between the two competing criteria as the 'standard' impedance for test gear.

3) In a high speed detector, input impedance is a critical parameter. It's easier to handle with a lower impedance line, for much the same geometrical reasons that you can't make a high Z line on a board, you can't really make a high Z line receiver IC.