When are MIPS control signals generated?
The control signals are generated by the Decode stage.  If I remember correctly (it's been like seven years...) the control signals are then passed through the pipeline registers between each stage, so they propagate down the pipeline with the rest of the instruction's data.

I think the question is actually asking how many cycles it takes to generate the control signals.  For a single-cycle and pipelined implementation, it only takes one cycle to decode the instruction (for the pipeline, the results of the decode are passed to each stage in succession once generated).

However, the multi-cycle processor will generate different control signals during each cycle.