FPGA Synchronized Digit Counter goes Asynchronous!
Add an else branch to fix the broken combinatoric process description:

process(pulse, digit_reg)
begin
    if (pulse = '1') then
        if (digit_reg &gt;= 9) then 
            next_digit &lt;= (others =&gt; '0');
        else 
            next_digit &lt;= digit_reg + 1;
        end if;
    else
        next_digit &lt;= digit_reg;
    end if;
end process;


Your implementation will not fit good to any existing FPGA hardware because it uses an asynchronous and synchronous reset.

This is how to describe a fully synchronous counter modulo 9 with synchronous reset and clock enable (pulse):

process(clk)
begin
    if rising_edge(clk) then
        if ((reset = '1') or (digit_reg &gt;= 9)) then
            digit_reg &lt;= (others =&gt; '0');
        elsif (pulse = '1') then
            digit_reg &lt;= digit_reg + 1;
        end if;
    end if;
end process;