100 Ohm diferential impedance microstrip PCB traces geometries in two layer board
Your signal tracks for the 10/100 PHY with 3ns rise time are overly fat compared to the data signals which you have carefully matched the lengths yet ignored the crosstalk effects.  This shows you do not understand what rules to follow in your layout.
Although your layout may work, it is always best to follow the supplier's recommendations for layout, Vdd decoupling, cross-talk track separation, ground planes (do's and don'ts) , supply plane decoupling , ethernet AC coupling the terminations to AC gnd and trace bevels on corners to reduce E-field gradient emissions.
A thinner board dielectric makes it easier to achieve lower impedances so that you do not need such a narrow gap.
Also since the min. rise time of your chip is 3ns for the ethernet port, or just over 100MHz BW transmission line impedances are not that critical since it 100MHz has a wavelngth of 1500 mm on FR4 and mismatched impedances for 1% of the wavelength will not degrade the signal integrity , however other factors above may add to noise if not followed.

Since I had to guess which IC you were using and none of the other details &gt; which I commented on were mentioned, consider this bonus info.
If my assumptions were wrong, just let us know with more details in question.

BTW, Earth ground via the caps on either side of the magnetics serve to shunt the common mode noise with centre tap to Vdd with proper decoupling.  If you have no Earth ground and just a chassis and STP shield gnd, then use that, which may work depending on proximity of noisy SMPS etc.