Design essentials when working with 12bit ADCs
For a medium-precision, low-sample-rate mixed-signal application such as yours, the main problems you face are having an accurate enough reference and keeping digital switching noise out of your ADC.  There are several steps to this, starting at the design phase and continuing through board layout.

During circuit design

First, at the design phase, a proper reference, correct decoupling, and a low-impedance signal drive must be supplied to the ADC in order for correct conversions to occur.  Also, the signal must be filtered (low-pass filtered in an instrumentation app like yours) to prevent the ADC from effectively downconverting higher frequencies to baseband (RF apps can use a slow ADC + bandpass frontend filter to Nyquist-downconvert a signal, saving on a dedicated mixer and LO).

Stabilizing your reference

References range from the trivial and pathetic (a jellybean discrete Zener, good to oh, 4 bits) to the insane (ovenized IC buried Zeners, used in high-performance instrumentation applications) -- and the specifications are often not clear, mixing units in ways that confound novices.  The chart in LTC AN82 is a useful antidote for this -- given your application, where your ADC is a 12bit unit capable of 11+ ENOB given a stable reference and a 5V supply, I would specify the reference to be accurate to 0.02% or better across the temperature range of interest, and RMS noise is not a concern as it's about an order of magnitude less than your accuracy specification.

Unfortunately, 0.02% initial accuracy without a trim is about where things start getting rather...hard.  Using a 4.096V reference given that the ENOB performance desired means that I want to run the ADC on a quiet 5V supply with a logic-level translator to the 3.3V I/O of the Pi, and that 4.096V gives you a nice, handy 1mV/count relationship, we're limited to the ADR4540, the X60003, the MAX6126AASA, or perhaps the LTC6655B although the last part cuts it close as it has a 0.025% initial accuracy.  While tempco and hysteresis are not concerns as this is a bench application I presume, and line and load regulation are not major problems as this is powered from the same regulated 5V supply as the ADC and only driving the ADC's Vref pin, long-term drift is also a concern here due to the lack of a trim -- for this, the ADR4540 and MAX6126AASA are the clear winners at 25ppm/root-khr and 20ppm/root-khr typical, respectively -- about at the 10-1 ratio needed to consider long-term drift insignificant.  (The other two parts have long term drift around 50-60ppm/root-khr typical.)

Decoupling everything

The MCP3208 datasheet recommends a minimum 1&micro;F capacitor for decoupling, connected from Vdd to the ground system -- AGND and DGND should be tied back to the same ground system as well.  A minimum 10&micro;F/10V ceramic or polymer tantalum bulk decoupler should be used on the board 5V rail as well.

On top of this, the reference should be decoupled as per the datasheet -- this is often 100nF on the output with 100nF on the input in addition to any bulk decoupling capacitance present, but the LTC6655 requires a much larger output capacitor (using the same P/N as the bulk decoupler works), and the X60003 is picky in the opposite direction due to its low power design.

Input drive/buffering/filtering

This, thankfully, isn't hard -- 0.02% accuracy translates to 800&micro;V of maximum input offset, and I can get a couple orders of magnitude better than that with GBWs in the MHz range while running on the single 5V supply available with today's zero-drift and internally trimmed amplifiers.  The AD8630 supplies a low-noise auto-zero option, while fast internally trimmed low-offset amps include the OPA4350 and the OPA4192.  Either way, the two-pole Sallen and Key low-pass anti-aliasing filter from the MCP3208 datasheet can be used, with the corner frequency set to about 5kHz or so -- other filter designs may work as well.

Power supply and digital interface

The MCP3208's ENOB (effective number of bits) specification is supply dependent -- it performs better with a 5V supply than it does with a 2.7-3.3V one; it also must be running off of 5V to use a 4.096V reference. This raises the problem that the Pi uses 3.3V logic and isn't 5V tolerant, requiring a logic level translation IC such as the TXB0104 -- the A side goes to the Pi while the B side goes to the ADC.

In addition, the 5V supply should be reasonably clean -- a linear regulator should be used to generate it on-board from a higher supply voltage.  If no higher supply voltage is available in the application, an existing 5V rail can be used provided a LC decoupling network is used to keep large quantities of digital noise off the ADC and op amp supply rail.

Layout time

There are two keys to an effective mixed-signal layout: partitioning and supply/return layout.  I will touch on those in turn.

First, I would split the board layout neatly into two sides -- a digital side and an analog side.  All digital traces (the SPI interface, in the case of the MCP3208 you are using) go on the digital side of the board -- this side of the board also contains the logic level translator chip and the I/O connector to the Pi.  The analog side of the board contains all the analog traces and circuitry -- the voltage reference goes here, and so do the input filters, input protection, and analog input connectors.  The ADC (and filter inductor if you are using 5V from the Pi) is the only component that bridges this gap -- in fact, I would recommend putting a silkscreen line on the board topside to remind myself where the boundary between the two sides is (it will come out L-shaped or slightly zig-zagged as the Vref pin on the MCP3208 sits on the same side as the digital I/O pins).

Note, also, that all the parts I linked are available in coarse pitch SMT packages -- a single-sided layout with the backside as a continuous GND plane is highly recommended if a double-sided board is to be used here.  If cost is not an objection, a four-layer board will provide a continuous analog Vdd plane in addition to the ground plane, as well as room for a "power puddle" for the 3.3V logic side of the logic level translator IC.  However, there is no need for a ground plane split in this application -- proper routing of the signal traces will keep the return currents where they belong.