Verilog: Are there some basic rules for port settings?
Just to start out, at the top of your spi_master module, you have rx_data declared as an input. Then at line 74 (I assume, I didn't count) you have

#1 rx_data[rx_counter] &lt;= miso;


If rx_data is an input to spi_master, then spi_master should not be assigning any values to it. The values should be assigned by the instantiating module (or test bench) and given to the spi_master instance as inputs.

If the intent is that your receive data on the miso line (because you're the master) and then make it available in a parallel word to the code where your module is instantiated, then rx_data should be an output from this module.

I also see an issue where you have tx_data and mosi both declared as outputs. If the intent is to take tx_data in parallel, and convert it to serial data on the mosi line, then tx_data should be an input to your module.


  I really did not understand why we should not use registers as inputs. Why is that? Where will I store inputs? How will I read them?


You can't make an input a reg because you aren't going to assign to it in the module where it is an input. 

You will assign to it in the higher-level module. Whether you declare it as a reg or not in that module depends on how it's assigned to. If it's assigned in an always block, it must be a reg. If it's assigned in an assign statement, or it's the output from another module, then it must not be a reg.

Generally, I'd say you need to think more carefully about what's an output and what's an input to your module. Think about if you were drawing a block diagram of your design, and each instance of your module were represented by a block. If the the signal would be flowing out of the block, that's an output. If the signal would be flowing in to the block, that's an input.