Cycle-Time/Latency optimization in synthesis of digital circuit question
Consider you have an application where to get the answer, you need to pass through 10 gates in series, and each gate has a delay of 10nS.

If you ask for a 150nS cycle time, then you can string all the gates together sequentially in one clock cycle, and your latency will be one cycle.

If you ask for a 80nS cycle time, you must break the sequence of operations into two, and register the intermediate results. Now your latency is two clock cycles.

If there is some other way to arrange the resources, perhaps into two parallel chains of 5 gates, with further logic to split and combine the answers (so more area) or higher power components that have smaller delays (so more power), we may be again able to fit all the processing into one cycle.