Why do we declare the inputs of our design as reg in testbench and outputs as wire?
Inputs are declared as reg and outputs as wire only in Verilog. In SystemVerilog, we use logic for 4-state simulation and bit for 2-state simulation.
In Verilog, inputs are declared as reg because they are variables which store values during simulation. The value is stored in the inputs of type reg till it is overwritten by some other value.
The datatype wire is used for outputs because outputs in the testbench are driven by the DUT (Device Under Test) continuously, and they don't store any value during simulation.
In SystemVerilog, declare a signal as wire only if you expect it to have multiple drivers.
Further reading: Mr. Dave Rich's excellent blog on wire and reg on Siemens Blogs