What does "pins-out view" mean?
Quite simply, it allows (provided a test port at each end is provided) to test an interconnect.

Consider a complex processor that has a large flash memory; we want to know that it is both properly soldered and can be accessed for both read and write to enable in-system programming, to name but one use case.

JTAG permits a view along the signal chain that cannot be physically probed.

This can extend in almost unlimited ways - if a test port exists at both ends of a digital signal chain, the a set of signals asserted at one end could be read (quite possibly having had some gating between test ports) to verify both the interconnect and functionality (at least at low speeds, although test port frequencies are now achieving 50MHz bit rates).

So we are looking at an entire signal chain from the edge pins of a function, through a number of PCB nodes on other logic in the signal path.

The pins out view is simply looking at the edge pins to verify solder joints and functionality through an entire path.

Interestingly, there is a push to get the same test capability for analogue