Time complexity of carry look ahead adder
We could think of a carry look-ahead adder as made up of two &quot;parts&quot;

The part that computes the carry for each bit
The part that adds the input bits and the carry for each bit position

The \$log(n)\$ complexity arises from the part that generates the carry, not the circuit that adds the bits.
Now, for the generation of the \$n^{th}\$ carry bit, we need to perform a AND between (n+1) inputs (if why this is so is a doubt, you may see this link)
The complexity of the adder comes down to how we perform this AND operation. If we have AND gates, each with a fan-in (number of inputs accepted) of \$k\$, then we can find the AND of all the bits in \$(log_{k}(n+1))\$ time. This is represented in asymptotic notation as \$ \Theta (log \  n)\$.
Hope that helps