Ethernet Phy Rx developed in a FPGA to send data to an ethernet Mac
First, what interface are you using?  You said MII, but MII uses tx_en/tx_er or rx_dv/rx_er instead of tx_ctl/rx_ctl.  Unless you're actually using RGMII, which muxes those two into one signal on opposite clock edges, with er inverted to reduce the number of transitions.
Second, this could be a problem:
assign rxd0 = d[1];
assign rxd1 = d[0];
assign rxd2 = d[2];
assign rxd3 = d[3];

But presumably the MAC should still count dropped packets.  Although perhaps not if the switched bits screw up detection of the start of the frame.
Also, assuming you're using RGMII, that interface can use the data signals to transfer status information between frames.  See the RGMII spec.  The MAC may be looking at this status information, so you should could try generating that.  Looks like you might want to set the data at idle to 4'b1011, to indicate full duplex link, 25 MHz clock, link up.