Design a 8 - 6 - 4 - 2 - 0 - 1 - 3 - 5 - 7 - 9... Counter
Given it is an assignment, I'm not going to work through the logic. However in all such questions you can boil it down to a circuit with two steps:


You have a binary 0 to n-1 counter, where n is the number of required states (13 in your case). This can be a bog standard synchronous binary counter that starts at 0000 and then when it reaches n is reset back to 0000.
A combinational logic circuit that maps the values from the counter to the output values. The structure of this can be discrete logic gates, the circuit for which can be derived using Karnaugh Maps - one map per bit in the output. Alternatively it could be a simple ROM with the mapping stored in it, where the address lines go to the counter, and the data lines are your output.


This approach will be far simpler and far more generic (think flexible) than using hundreds of shift register bits.