Theoretical Clock Question
Your clock signal is edge-triggering, in your examples on the positive edge. You can tell because the data has to be stable a short time before the clock edge (setup time), and if the clock would latch on the falling edge it would coincide with your data changing.

Except for the setup time there are few constraints: the clock may stay high as long as it wants. You will have to have a minimum low time however, before the next rising edge.