Delay digital signal using Flip Flip
Your clocks/signal are probably already synchronized. As such it's being clocked in on the first edge (The setup delay in the flip flop is likely zero in the simulation too). Try adjusting the phase of the signal to change how that appears in the simulation.

However, even then, the delay of this circuit will be almost zero to 1 clock period.

You may want to consider two stages instead of one with the data for the second state fed from Q of the first and the clocks common. Your delay will then be 1 to 2 clock cycles.







simulate this circuit &ndash; Schematic created using CircuitLab