Interfacing 62256 SRAM to low pin-count AVR via latches
Sounds OK. You are correct, don't put a latch on the Data lines as these are bidirectional. As long as you make sure OE is deasserted when you are programming the address, and you your latch enable lines are never asserted when OE is asserted, then you shouldn't have any problems. It will take additional clock cycles to access the memory, but that's the price you pay for saving pins.

It would basically be something like:


Ensure OE and WE are deasserted
Load address 0..7 onto data lines
Latch into the lower address latch
Load address 8..15 onto data lines
Latch into upper address latch
Either load data onto data lines (for write), or set to input (for read)
Perform operation using OE and WE pins.




Swapping the address lines to the SRAM would be fine - it just means stuff will be stored in a weird order inside the SRAM, but as far as the uC is concerned it will be contiguous. For flash this can be an issue as page accesses would no longer be possible, but SRAM like the 62256 doesn't have that issue as it doesn't use paging.