How to improve the system verilog testbench for JK flip flop
It may seem absurd to replicate your DUT code in your testbench. But there's little else you can do for such a trivial design. But jump up to a counter or a multi-stage multiplier and it's much easier to see the benefit of predicting your design's output versus having to manually look at file or waveform and see if the test is passing or falling by inspecting every time. You want a "PASS" or "FAIL" at the end of running the test.

Your predictor does not have to fit into the confines of synthesizable RTL. You can write code that takes the current values of q,j, and k and predicts what the next value of q should be. 

logic q_prev;
always @(posedge clk) begin
    q_prev = q; #1;
    case ({j,k})
      2'b00: assert (q==q_prev);
      2'b01: assert (q=='0);
      2'b10: assert (q=='1);
      2'b11: assert (q==!q_prev);
    endcase
end