How can I turn a clock signal into a logic high that also goes low when the clock drops out?
Taking the TLDR at its words, "I need a logic high if the clock is present and a logic low if it is not":

Send the clock into a low pass filter.  It should have a voltage of half the maximum clock voltage (assuming 50% duty cycle) when the clock is running.  When the clock cuts out this will drop to 0V.  Feed this into a comparator at like 1/4 of the supply voltage (tweak this value for drop-out time).  One more inverter and you have both polarities.

I am assuming that this "When certain conditions are violated, the IC will send the differential signal to ground which will disable the driver and the FET will turn off." means the clock won't freeze high.  If it does, this circuit wouldn't work properly without some tweaking (just brainstorming, you could add another op-amp, this time comparing to 4/5 of the supply voltage; which would check for a frozen clock at high logic w/ an AND, will update post).

The simulation is shown below.  Add more sophistication as needed I suppose:



Just in case the clock could freeze high, here is a modification which checks for the clock frozen at either low or high (and w/ a bleeder resistor in case clock goes high-z):