Clock domain crossing between OV7670 interface and AXI4-Stream
Asynchronous FIFO
Asynchronous FIFO is an ideal approach to consider implementing between for crossing data safely across the two clock domains.
If you are doing this in Vivado, I suggest you use the dedicated Vivado IP instead of designing one.
If you are interested to design one, it would be useful to go thru this paper:
Cummings's paper on FIFOs
Choosing the depth of the FIFO
You have to choose the depth of the FIFO based on:

What are the frequencies of write and read operations at the enqueue and dequeue sides respectively.
How many bursts of data you are going to enqueue to the FIFO.

Here is a simple guide I used in the past for depth calculation
EDIT:
Full handshake bus synchronizer which you are trying to use has less throughput, but it serves for your purpose consuming lesser resources; especially if you don't need to send many bursts of data in one go. If I remember well, FIFO generator demands a minm. depth and hence can be an overkill when it comes to resource utilization.