System verilog: check if logic signal changes at posedge
I want to monitor a signal and take some action if it value changes @ clock posedge.


I know you don't want to use a register but it can be test-bench register. You have to make a copy at the clock edge and compare it against the old value:

logic [31:0] new_var_signal
always @(posedge clk_i)
   new_var_signal &lt;= var_signal;

assign signal_changed_at_clock_edge = (new_var_signal != var_signal) ? 1 : 0;


There is a caveat: if the signal can also become 'z' or 'x' you should use:

assign signal_changed_at_clock_edge = (new_var_signal !== var_signal) ? 1 : 0;


Note that you are in an ideal simulation environment and there is no such moment as @(posedge.. That moment is infinitely short. 

In a real digital design the signal has to be stable around the clock edge. The time before the clock edge is called the setup time and the time after is called the hold time.