does this ensure i am reading from the ram?
You should be able to use your design tools to check what the synthesizer has done with mem.

Check the RTL schematic first, and make sure it looks 'sane' (i.e. make sure mem appears as some form of RAM). The RTL schematic shows you the non-architecture specific synthesized HDL.

Then check the "Technology Schematic" (I think that's what Xilinx calls it, at least in ISE), which shows you what the optimization/architecture specific synthesis has done with your design. This should show a mem mapped to block RAM(s), or explain what the synthesizer has decided to do with your construct.