What is the purpose of pre-synthesis simulation?
The main purpose of pre-synthesis simulation is to verify the logical functionality of your design, without worrying about the specific timing details of a particular implementation.

This saves a lot of time in the functional debugging cycle, since you don't need to wait for the synthesis process to complete before simulating again after making a change.

Once you have the design working correctly with "nominal" or "unit" delays, you can then run the synthesis tools and verify that it continues to work with actual timing delays. Fixing the issues at this stage and dealing with long critical paths usually takes fewer iterations, which is good since each iteration takes longer.

But in fact, many designs are never taken through post-synthesis simulation. It is often sufficient to use pre-synthesis simulation to verify the functionality, and the static timing analysis tools to verify the post-synthesis timing.



Regarding your subsequent edit, if the order of blocking statements ever matters, then you're probably not doing something right.

One of the key differences between simulation and reality that I frequently trip over is the specification of sensitivity lists for processes. The simulator will always take the sensitivity list literally, because this is important with regard to making the simulator run efficiently. However, the synthesis tools and the actual hardware don't really care about sensitivity lists (although some synthesis tools will give you a warning if there seems to be a problem) &mdash; if a signal changes, those changes will propagate through the logic regardless of what the sensitivity list might say.