Where MOSI is triggered low or high
The system is single buffered in the transmit direction and double buffered in the receive direction. This
means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle
is completed. When receiving data, however, a received character must be read from the SPI Data
Register before the next character has been completely shifted in. Otherwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct
sampling of the clock signal, the minimum low and high periods should be longer than two CPU clock
cycles.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and 
SS pins is overridden
according to the table below. For more details on automatic port overrides, refer to the IO Port
description.
Table 23-1. SPI Pin Ove

http://ww1.microchip.com/downloads/en/devicedoc/atmel-42735-8-bit-avr-microcontroller-atmega328-328p_datasheet.pdf