Shift registers, understanding parallel-in serial-out
Refer to the datasheet (better if you provide a link to the datasheet you're consulting in your question, but from the colors I assume it's NXP). 



This particular shift register has an input latch as well as the PISO shift register. Some (eg. 74HC165) don't have the input latch. 

In answer to your questions: 

1) When you are shifting the shift register, something will get shifted into the serial input. That pin allows you to choose to shift in logic '0', '1', or perhaps cycle the contents around, or whatever else you choose.  

2) Rising edge on SHTP clocks the shift register. 

3) Rising edge on STCP loads the input latches from the inputs.  

Note a low level on /PL loads the shift register from the input latches. If /PL is low, then a rising edge on STCP loads the shift registers from the inputs. 

/MR resets the shift register (not the input latches) and it is considered 'invalid' to have /MR and /PL active at the same time.