Is my circuit hitting a limitation of the AND gate on IC 74HC08N?-- How does PWM frequency affect performance?
First, you need to tie unused inputs (2A, 2B, 3A, 3B, 4A, 4B) to ground. Leave unused outputs floating. HCMOS inputs tend to float to a mid-level "metastable" voltage which causes much higher power consumption in the chip because the input transistors are staying in their active region.

Second, you're just using the AND gate as a buffer, while you have a perfectly good 74HC04 (which probably has a better output driver) right there. Why?

Third, PWM is a digital signal. It alternates between 0 and 5 V in this case. You need a scope to see what it's doing; a multimeter is right out. What you're doing is you're expecting the meter to somehow average the PWM signal for you. Any nonlinearities and bandwidth limits the meter has will get you false results.

If you want to convert PWM to an analog voltage, you have to pass it through a low-pass filter of some form, where the corner frequency of the filter is set higher (preferably much higher) than the highest analog frequency you want to output, and lower (hopefully much lower) than the PWM switching frequency. 5 kHz and 20 kHz are probably too close.

For a 5 kHz max analog signal, your filter should have a corner frequency of 10 kHz or more, and the PWM should be at least 8X the max frequency (40 kHz).

For filter design, please see TI's WEBBENCH or FilterPro.