VHDL SLV dynamic width slice assignment
As of right now, X and Y are generics, but I would like to make them, or the ratio between then, or the log2 of that ratio a signal, so that I might change my operation at runtime via a register write or something.


Well, since you're implying that you're pretty flexible on how to get this done, then certainly the simplest approach would be to just have a register mask which you simply set to have 1 bits in the appropriate spots -- for example "0000000000001111" or "0000000000111111". Then just apply the mask exactly like @JonathanDrolet suggests, i.e.:

raddr_short &lt;= raddr and mask;


Advantage: super-simple to implement and to understand. Disadvantage: possible to set mask to values that could result in weird operation (but do you really care about "guard against bad user input" in your application)?

If you wanted to get fancier (but again, why?) then you could try the approach suggested by JonathanDrolet, but I'm doubtful that a synthesizer would be able to synthesize the construct std_logic_vector(to_unsigned(2**Y-1, mask'length)) into a reasonable circuit, if it would synthesize at all. But you could use a hybrid approach: you say you have "4 of these things running at once" but if they all share the same Y value then you could calculate the mask once and apply it to all of them:

mask &lt;= "0000000000111111" when Y = 6 else
        "0000000000011111" when Y = 5 else
        ...
        "0000000000000011" when Y = 2 else
        (others =&gt; '0');

raddr1_short &lt;= raddr1 and mask;
raddr2_short &lt;= raddr2 and mask;
...


If it were me, I'd still just go with the simpler programmable mask register, though.