How this for loop could be translated efficiently in vhdl using for generate statements?
If you use for loops within a process, you can use a variable.  This (translated into valid VHDL) should synthesise fine (assuming n is a constant or generic).

The resulting hardware may be large or slow, but the same would be true if you used generate statements. If it doesn't meet your size or speed goals, you get to play with clocked processes, and pipelining.

The obvious way to do it using if ... generate would be to make Val a 2-D array signal, which makes the "unrolling" into parallel hardware absolutely explicit. (or an n * n sized 1-D array) But that is more complex and error-prone than the simple process approach.