Reason for power on sequence requirement in SoC
Normally SoC's are all CMOS and all CMOS devices cannot have any low impedance input voltage exceeding a diode voltage outside either supply rail, Vdd,Vss,  otherwise an inherent substrate PNPN = "SCR effect" causes latchup and shoot-through or short circuit when power is applied.   You can search for this effect for more details.

Normally 0.2V is permitted in Absolute Maximums and inputs are  protected with Schottky diodes and 10 k series current limiting Rs on inputs. 

But the effect is in the substrate between power rails and the input or output is a trigger that must be avoided by a controlled power sequencing.