Use of passive filter in oscilator circuit
EMI issues are separate from resonance tuning error and crystal uW power limits.

C4 might affect all 3. I suggest using a series 1k R instead, or nothing if you don't care and just want a clock.

Details

The crystal is a 3rd order resonator acting as a parallel resonant bandpass and not a series mode. if you search for my RLC impedance nomograph you can understand the impedance vs RLC for the crystal model and shunt caps added like 10pF and perhaps come to the conclusion that all you need is a series R like 1k to attenuate square wave harmonics while not reducing the fundamental using RC just below the operating point. This also reduces crystal power absorption of harmonic power as many are limited to 10uW.

Normally an unbuffered CMOS inverter builtin has at least a linear gain of >>10 but you can verify for your chip by increasing the R until itfails to oscillate due to the Barkhausen criteria.  ( and Gain>>1 for stable starting oscillation to full square wave)  Using a 10pF scope probe instead of a load cap you can scope the square wave input after R4 in place of C4. An inductor of same impedance may shift the frequency but yield 2nd order atenuation of crystal currents for extreme reduction to EMI egress froma square wave driving a tiny cap in a loop.