What is supposed to happen in Verilog if a signal of one width is assigned to another signal of a different width?
Verilog's rules are:


if you copy a narrower value into a wider target, it is zero-extended (zero MSBs added to the left), or sign-extended into the target. Whether it is zero or sign-extended is determined by the signedness of the right-hand-side expression.
if you copy a wider value to a narrower target, it gets truncated (MSBs removed on the left).


So it means, in your case:

assign A = C[3:0];
assign D = { 1'b0, B };


Note that most synthesis tools will issue a warning in these cases. And they should because it's then unclear you're doing things correctly.