Unable to flush TX FIFO queue of NRF24L01+
After I had invested many, many hours into problem analysis, I wrote the above question – only to figure it out about one hour later.

The problem turned out to be the SPI timing, more specifically the time between the falling edge of the SPI clock (SCK) for the last bit of the transaction and the rising edge of the chip select (CS). It was 0 but should be at least 2ns.

Invalid SPI timing for NRF24L01+:



Fixed SPI timing:



In the code, it's just one additional line, namely the line setting cs_ena_posttrans:

spi_device_interface_config_t device_config = {
    .clock_speed_hz = 1000000,
    .mode = 0,
    .spics_io_num = CSN_PIN,
    .command_bits = 8,
    .cs_ena_posttrans = 2
};


This not only fixes the FLUSH_TX command; transmitting packets works as well.