Warning!! Latch has unsafe behavior (vhdl)
You just wrote sloppy VHDL as mentioned by Brian Drummond in the comments, there's state in your unclocked process, which leads to latches (both next_state and out1 get latched on flanks of I). Try the following:

p_main:process(clk, rst)
  variable r_current_state:
begin
case r_current_state is
    if(rst='1')then
        r_current_state:=T0;
        out1 &lt;= '1';
    elsif(clk'event and clk='1') then
      case r_current_state is
        when T0=&gt; if (I='0')then
                        r_current_state:=T1;
                        out1&lt;='1';
                    end if;

        when T1=&gt; if (I='1') then
                        r_current_state:=T2;
                    end if;

        when T2=&gt; if(I='0')then
                        out1&lt;='0';
                        r_current_state:=T3;
                    else
                        r_current_state:=T0;
                    end if;

        when T3=&gt; if(I='0')then
                        out1&lt;='0';
                        r_current_state:=T4;
                    else
                        r_current_state:=T0;
                    end if;

        when T4=&gt; if(I='0')then
                        out1&lt;='0';
                        r_current_state:=T5;
                    else
                        r_current_state:=T0;
                    end if;

        when T5=&gt; if(I='0')then
                        out1&lt;='0';
                        r_current_state:=T6;
                    else
                        r_current_state:=T0;
                    end if;

        when T6=&gt; if(I='0')then
                        out1&lt;='0';
                        r_current_state:=T0;
                    end if;

        when others=&gt;NULL;
      end case;
    end if;
end process;

Z1&lt;=out1;
Z2&lt;=I;


Also, forget two-process state machines. They mess things up way too quickly.

Keep in mind that the code I gave is functionally different from what you wrote, since out1 will only change on the rising edges of clk, rather than on every change of I.