SystemVerilog: How to give different parameters to modules in the same array?
Use a generate loop

for(genvar ii=0; ii&lt;4; ii++) begin : counter_loop
  my_counter #(.INIT_VALUE(ii)) my_cnt (.clock, .reset ... );
end : counter_loop


If the values you want to override cannot be computed by a simple loop expression, you can use a parameter array.

parameter int ARRAY_VALUE[4] = {1,3,5,10};
for(genvar ii=0; ii&lt;4; ii++) begin : counter_loop
    my_counter #(.INIT_VALUE(ARRAY_VALUE[ii])) my_cnt (.clock, .reset ... );
end : counter_loop