ARM Cortex M3 (ATSAM3N4B) IACCVIOL Hard Fault
Once again, it seems I did not utilize google enough.

Section 10.6.7 of the given datasheet also described on this ARM information center page describes the Exception entry and return process. 

So the answer to my question is that faulting instruction address resides on the stack at an offset of +0x18 after entering the exception handler.