Choosing the proper value for a pulldown resistor in a logic circuit
The input impedance of a CMOS logic gate can be over 100 Mohms, but you do not want a high resistive value unless this is battery powered. Normally to keep sensitivity to noise down the resistor would be from 10 K ohm to 100 K ohm.
A 10 K pull-down means when the switch is closed the resistor is draining 500 uA of current, and the 100 K would drain 50 uA of current. 1 megohm would draw just 5 uA of current but the high impedance would make the input sensitive to local noise and at elevated temperatures gate leakage could be an issue.
If you have a choice in the matter the 10 K is the best option, but if this is battery powered and every uA counts then use 100 K pull-downs. To cut way down on noise sensitivity you can parallel a 10 nF or 100 nF capacitor with the pull-down resistor.
The following is a basic digital input filter / clamp with pull-down resistor. Theses can be tiny SMD parts that take up little space.



simulate this circuit &ndash; Schematic created using CircuitLab