Are SPI slave select lines hardware enhanced?
It depends on the microcontroller. In most SPI peripherals that I have seen the slave-select management is doing the exact same thing as a GPIO. I tend to use the GPIO interface in these cases as it allows for more flexible routing.

But I've also seen SPI controllers that do more advanced stuff like managing the SS lines per transfer packet. That comes in very handy if you communicate with multiple slaves on the same SPI bus via DMA. You just send out the data via DMA and the controller will do all the switching between slaves at the correct time without needing any CPU attention.

Other notable things I've seen:


Slave Select logic which just latches the state-change and delay this request it until the internal transfer FIFO is empty. This is very useful if you're just doing writes and don't care about the MISO data. You just write out your bytes to the SPI bus, de-assert the Slave Select and you're done. No risk in breaking the last byte because you've switched Slave Select to early.
Slave Select logic that allows for various SPI related protocols like TI-SSI, I²S etc.
Slave Select logic that automatically inserts an idle-bit between each transfer unit. Not sure why they do this as it makes SPI unusable for lots of SPI flash chips (Yes, I'm looking at you, NXP).