Would a parallel EEPROM ever output a value that it does not contain?
If the output is latched, and if the timing constraints (address stable before latch) are observed, then that should not happen. 

If there’s no latch, then allowing the minimum delay to occur after the address lines are stable before enabling the chip will typically suffice. 
Eg. see the timing diagram for the 28C64 (Fig.3)

If you’re just wiggling the address lines around, the the output may not do what you don’t want, but it certainly could.