How does design compiler constrain combinational paths?
Generally the timing analysis is done register-to-register.  The analysis should check all possible paths - it doesn't try to figure out which one is critical, it just calculates all of them and then sorts the list by the path length.  It is possible to have timing constraints against I/O pins which are not registered, but this is more of a special case.  The timing requirement should not be getting ignored unless there is an issue with how the software determines the paths.  It is possible, for example, for the critical path you're interested in to get optimized away.  Also, note that the timing of a particular block will vary depending on how it is placed.  You could get different performance when you place the block by itself vs. as a component of a larger design.