Verilog reset example within clock domain crossing example
This code doesn't really need to be reset. If you do want to reset it, it has to be done properly, most likely with one reset signal for each clock domain. But this isn't really necessary, all you really need to do for simulation is initialize all the internal registers to something other than x, and then it should work properly. So, replace

reg FlagToggle_clkA;


with

reg FlagToggle_clkA = 0;


and you should be good to go.