What is the relation between noise margin and impedance in a CMOS circuit?
This typical MOSFET is intended to demonstrate the characteristics similar to 74HCxx family logic with a complementary Pch being the inverse such that the admittances add then inverted to define the Zout where nominal at 4.5V is near 50 Ohms. and at Vcc/2 is slightly higher. 


Thus there is a wide margin but it is well controlled to prevent shoot-thru.  
Also when self biased when Vout=Vcc/2 with no input as a linear amplifier ac coupled, the power drain is not excessive.
This ignores the substrate PNPN structure that causes latchup if Vin goes outside the supply rail by 0.6V but internally clamped by 2 stage ESD diodes with 10k in series limited to 5mA by diode ESR, which I have documented on this site.
Historically this std design has migrated from 300~1kOhm for CD4xxx series used from 15V-3V then for 3V logic 74ALCxx, Zout is 22~33 Ohms @25'C .


This can be examined by Vol/Iol or (Vcc-Voh)/Ioh at various Vcc values to be consistent across most logic devices in same family and  all suppliers 
e.g. 74S,74HC,74AL, etc and 50 more different CMOS families all have similar Zouts that are dependent on the max Vcc spec but with smaller lithography and lower rise times possible with lower input capacitance gives improve transition speed as well as similar Noise margin.  
when noise margin is inadequate Schmitt Input NAND Gates or Inverters are chosen which have ~ 50 % input hysteresis