Assigning the different value to parameters in Generate block in Verilog
You can do this easily in SystemVerilog as you can declare a parameter that is an array and then select index of the parameter array inside the generate loop. Most simulation and synthesis tools already support this. 

If you need to stay in Verilog, you can pack values into a parameter and then select a slice of parameter

module top_module ();

    wire clk;
    wire rst;

    parameter N = 5;
    // assuming width can fit in 4 bits
    parameter [(N*4)-1:0] D_WIDTH = {4'd1,4'd2,4'd3,4'd4,4'd5};
    parameter [(N*4)-1:0] S_WIDTH = {4'd6,4'd7,4'd8,4'd9,4'd8};

    genvar j;

    generate
        for(j = 0; j &lt; N; j = j+1) begin : GEN_BLOCK
           gen_module #(.DATA_WIDTH (D_WIDTH[j*4+:4]), .SIZE_WIDTH (S_WIDTH[j*4+:4])) i_gen_module (
              .clk (clk),
              .rst (rst)
          );

        end
    endgenerate 
endmodule