Is it good to clear the state on 'posedge enable' in verilog
always @(posedge clk &amp;&amp; enable == 1) begin


That's not the way to do it. I'm not even sure it's a valid syntax. Furthermore, you can only control a reg or integer type variable from a single always block, so having the first always block that is sensitive to enable means you couldn't control any of those signals in any other always block.

What you are looking for depends on what the logic connects to. For example if you want to do calculations while enable is high, but then don't use the values when it is low, then you can simply use the enable signal as a negative reset. If this is the case then really the signal should be called just that, "reset" not "enable".

always @ (posedge clock) begin
    if (~enable) begin
        //Reset the values ready for next time
    end else begin
        //Do stuff when enabled

    end
end


This may not be what you want. For example if you need the registers to hold their value when the enable signal is low, and then clear them just before a calculation. This can be done too, but only if you don't mind it taking one clock cycle. This approach can be accomplished using a synchronous reset and an edge detection circuit.

reg enableDelay;
always @ (posedge clock) begin
    enableDelay &lt;= enable; //Keep track of the previous value
end

wire enableRising = enable &amp;&amp; !enableDelay; //enableRising will be high for a single clock cycle at the rising edge of enable

always @ (posedge clock) begin
    if (enableRising) begin
         //Clear stuff on rising edge of enable
         data &lt;= 1'b1; //Maybe we set the register 'data' to 1 or whatever
    end else if (enableDelay) begin
         //While the delayed enable signal is high, do stuff.
         data &lt;= something;
    end
end


The code above will produce the following output:




There is a rising edge of the enable signal. Notice how the enableRising signal also goes high at the same time.
The enableDelay signal goes high as it is always one clock cycle delayed from the enable signal. At the same moment, the second always block detects that the enableRising signal is high and performs the "reset" operation. This is indicated by the data signal going high.
On the third clock cycle, enableRising is now low again, so the data signal is set to whatever calculation you do in the else part of that block. It will keep executing the else part each clock cycle until the enableDelay signal goes low again.


Basically the block will clear on the rising edge, and then do n calculations (where n is the number of clock cycles that the enable signal was high).



The trouble with your question is a classic X-Y problem. You are describing Y when really you should be telling us X. Y is what you think is the way to do something, X is what you actually are trying to do. Please clarify in your question.

Directly answering the title of the question: "It depends". Some signals you might want to clear - maybe a counter needs resetting to zero, or something. There may be others which don't matter - say the output of a calculation that doesn't affect the input.

Tasks that require doing a sequence of events are best organising into a state machine, such that when some trigger occurs (e.g. rising edge of a signal), your state machine starts running through each state. Once the task is complete, it then returns to an idle state waiting for another trigger. This way you don't need to reset stuff on the trigger as the state machine if designed correctly would leave all the signals it controls in a default state when it returns to idle.