soc clock domain questions
One common way is the following:


Use a crystal oscillator to create a stable input frequency, perhaps 25 MHz.
Multiply the input frequency using a PLL (phase locked loop) with a VCO (voltage controlled oscillator) to get a frequency as fast or faster than all of the required frequencies.
Use several frequency dividers (typically arranged in some kind of tree) to produce all the required slower clocks.


For example, if you need a 500 MHz clock, a 300 MHz clock, a 10 MHz clock, and a 1 MHz clock, you could have something like this:

25 MHz --&gt; PLL(x60) = 1500 MHz --&gt; / 3 = 500 MHz
                               +-&gt; / 5 = 300 MHz --&gt; / 30 = 10 MHz --&gt; / 10 = 1 MHz


The exact arrangement of the clock tree often depends on which blocks can be used independently. E.g., in the example above, you could turn off the 500 MHz clock while still running the other slower clocks, but you couldn't turn off the 300 MHz clock without also turning off the 10 and 1 MHz clocks.