Long enumeration in VHDL to recognize a state machine
Unclear what you are trying to achieve.
First, it seems like an odd restriction for Quartus to restrict state types to enumerations instead of other discrete types like integer or unsigned. But...
Do you really have 231 discrete states?
Or is range 34 to 50 a single state?
If you need to remain in that state for 17 separate events, consider a state and a separate counter. You could implement that as a pattern similar to a state machine with multiple delays.
If you need to translate a numeric input to a state, write a to_state(int) function returning your enumeration type.
If there is similarity between groups of states, you might look at a hierarchical state machine or even decompose the state machine into one central SM controlling several others via handshaking.
EDIT from the relevant manual section aaah...

&quot;VHDL state machines that do not meet these conditions are converted into logic gates and registers that are not listed as state machines in the Report window.&quot;

So you can use another discrete type like a ranged Natural, and it'll synthesise, probably to the same logic, you just don't get the nice report. I'd be tempted do that (write it in the most natural style) just to use the (speed/size) results as a benchmark to compare with the &quot;Altera approved&quot; style.
Project or company coding style rules may prohibit that, or require the pretty report artefact for verification, so I'm not pushing this as a solution, just as a way to calibrate the &quot;official&quot; solution ... possibly as a golden model for simulation (verify both SMs remain in step).