In Verilog, does an event control always execute once at the beginning?
Variables of the type 'reg' start simulation with the value of 'x'. 

Any assignment after that, also an initial assignment, will be seen as a change and will  trigger the always @(r) statement. Thus your c can change at time 0. 



Having said al that: you code is behavioral and can not be synthesized as you have multiple drivers for `c. 

Additionally the behavioral code is open to race conditions: if clk rises and r changes at the same time it is undefined in which order the two statements will be executed.

Besides all that your c is reset if r changes. Thus not only from 0 to 1 or from 1 to 0 but also any x or z change. There is no actual logic which can implement that in reality.

There are standard code templates in Verilog how to make a register with an asynchronous reset:

always @(posedge clk or posedge reset)
   if (reset)
      c &lt;= 1'b0;
   else
      c &lt;= ....


Last but not least:
Do not post picture of code. Paste the actual code. A prime example is this one where I would have had one hell of a time spotting the back-quote if the the user had not, correctly, pasted the original code in the question.