NAND Gate Logic Optimization
This sounds like a state machine with 4 states; let's call them READY, STARTED, STOPPED, and FAIL. And make your inputs level-triggered rather than edge-triggered if possible, it's a lot easier to understand.


READY -> STARTED when (enable and safety).
STARTED -> STOPPED when not enable.
STOPPED -> READY when not safety.
STOPPED -> FAIL when (enable and safety).


It's not specified but you probably want STARTED -> FAIL when not safety (ie someone disengages safety while system is running) and some means of getting out of FAIL.

Actually mapping those into gates, deciding whether you want binary mapping or one-hot and Moore vs Mealy machine is left as an exercise.