Trouble understanding Verilog decoder logical left shift
binary_in is 4 bits, so can hold a decimal value anywhere in the range 0-15.

If you left shift 1 by between 0 and 15, you get a number with at most 16 bits.

16'b0000000000000001 &lt;&lt; 0  = 16'b0000000000000001

16'b0000000000000001 &lt;&lt; 1  = 16'b0000000000000010

16'b0000000000000001 &lt;&lt; 2  = 16'b0000000000000100

...

16'b0000000000000001 &lt;&lt; 15 = 16'b1000000000000000