Modelling a positive edge triggered T flip flop with asynchronous clear
This is a common way to combine the always blocks:
module t_flip_flop_exam (q,clk,clear,t);
    input t;
    input clk;
    input clear;
    output reg q;

    always @(posedge clk or posedge clear) begin
        if (clear)
            q &lt;= 0;
        else if (t)
            q &lt;= ~q;     
    end
endmodule

It is better to make assignments to a signal from a single always block.
Trigger the always block on the posedge of clear so that synthesis can infer the desired logic (asynchronous clear, synchronous toggle).
Use nonblocking assignments (&lt;=) for sequential logic.
There is no need to explicitly do q=q because it is implied.