CD4017 Count up to 8
You have a few problems.


CKEN should be labelled CK_INH. When high it INHibits the clock rather than ENabling it. It is, however, wired correctly.
CO is the Carry Out output pin. It turns on for outputs 0 to 4 and off for outputs 5 to 9. It should not be short-circuited to ground. This may be responsible for some of your troubles.
On power-up the counter will assume a random state unless you do a power-up reset.




Figure 1. A divide by two implementation with a power-up reset. Source: Zen.

How it works:


On power-up C2 is discharged so when the supply ramps up from 0 V to 12 V the bottom of C2 does too. This applies the reset to pin 15. Output 0 will turn on.
R3 charges C2 (by pulling the bottom terminal to ground). The reset pulse time period can be calculated from \$ \tau = RC \$. When the RST voltage falls to about 1/2 or 1/3 of Vdd the reset will be released and the chip will respond to clock pulses.
In this application output 2 is wired via a diode to C2 / R3 so every time it goes high the chip is reset to zero. (You will be using output 8.) Note that the chip won't respond to clock pulses again until the reset signal falls low again. For this reason your \$ \tau \$ needs to be shorter than your fastest clock period.