Clock frequency of FPGA circuit and 4-bit counter
as you know if you have 4bit_counter, you can see the fourth bit(most left bit) of this counter becomes one after counting eight rising_edge_clock, it means 2^3 ;

so in your case, 24th bit becomes one after finishing (2^23)-1 counts and since the clock period is 0.02 milliseconds it takes (2^23)*0.02 milliseconds.
this rule is applicable to the remaining three LEDs of course:

25th bit : (2^24)0.02 ms ;
26th bit : (2^25)0.02 ms ;
27th bit : (2^26)0.02 ms ;