Worst-Case propergation delay in a full adder
Initially your carry outs are as follows 

\$C_0 =0\$ 
\$C_1 =0\$
\$C_2 =0\$

\$P @ t=0\$ is '001'  \$P_0=1\$ \$P_1=0\$ \$P_2=0\$  At t=1 it becomes '010' as in  \$P_0=0\$ \$P_1=1\$ \$P_2=0\$

\$Q=4 =&gt; '100'\$ so if we were to look at the additions at the carry outs they do not change. 

Since you are adding You are going from 
\$P_0+Q_0=0+0=0 \rightarrow C_0=0\$ (No carry change ) 
\$P_1+Q_1=1+0=1 \rightarrow C_1=0\$ (No carry change) 
\$P_2+Q_2= 0+1=1 \rightarrow C_2=0\$ (No carry change) 

Since there are no carries the result of each adder goes to straight to the sum and there are no interactions between the adders since all your carries unchanged throughout the transition.



It takes 3 gate delays to get from Input of a value(Q or P) into the adder to the output(S or C) of it hence the answer is 3 gates.