STM32: Performing a software reset
Why don't you use the CMSIS library? There is a specific function for that.

Moreover, This is the Code taken from CMSIS Library for System Software Reset:

/******************************************************************************
 * @file:    core_cm3.h
 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
 * @version: V1.20
 * @date:    22. May 2009
 *----------------------------------------------------------------------------
 *
 * Copyright (C) 2009 ARM Limited. All rights reserved.
 *
 * ARM Limited (ARM) is supplying this software for use with Cortex-Mx 
 * processor based microcontrollers.  This file can be freely distributed 
 * within development tools that are supporting such ARM based processors. 
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 ******************************************************************************/

/* memory mapping struct for System Control Block */
typedef struct
{
  __I  uint32_t CPUID;                        /*!&lt; CPU ID Base Register                                     */
  __IO uint32_t ICSR;                         /*!&lt; Interrupt Control State Register                         */
  __IO uint32_t VTOR;                         /*!&lt; Vector Table Offset Register                             */
  __IO uint32_t AIRCR;                        /*!&lt; Application Interrupt / Reset Control Register           */
  __IO uint32_t SCR;                          /*!&lt; System Control Register                                  */
  __IO uint32_t CCR;                          /*!&lt; Configuration Control Register                           */
  __IO uint8_t  SHP[12];                      /*!&lt; System Handlers Priority Registers (4-7, 8-11, 12-15)    */
  __IO uint32_t SHCSR;                        /*!&lt; System Handler Control and State Register                */
  __IO uint32_t CFSR;                         /*!&lt; Configurable Fault Status Register                       */
  __IO uint32_t HFSR;                         /*!&lt; Hard Fault Status Register                                       */
  __IO uint32_t DFSR;                         /*!&lt; Debug Fault Status Register                                          */
  __IO uint32_t MMFAR;                        /*!&lt; Mem Manage Address Register                                  */
  __IO uint32_t BFAR;                         /*!&lt; Bus Fault Address Register                                   */
  __IO uint32_t AFSR;                         /*!&lt; Auxiliary Fault Status Register                              */
  __I  uint32_t PFR[2];                       /*!&lt; Processor Feature Register                               */
  __I  uint32_t DFR;                          /*!&lt; Debug Feature Register                                   */
  __I  uint32_t ADR;                          /*!&lt; Auxiliary Feature Register                               */
  __I  uint32_t MMFR[4];                      /*!&lt; Memory Model Feature Register                            */
  __I  uint32_t ISAR[5];                      /*!&lt; ISA Feature Register                                     */
} SCB_Type;

#define SCS_BASE            (0xE000E000)                              /*!&lt; System Control Space Base Address    */
#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!&lt; System Control Block Base Address    */
#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!&lt; SCB configuration struct             */

#define NVIC_AIRCR_VECTKEY    (0x5FA &lt;&lt; 16)   /*!&lt; AIRCR Key for write access   */
#define NVIC_SYSRESETREQ            2         /*!&lt; System Reset Request         */

/* ##################################    Reset function  ############################################ */
/**
 * @brief  Initiate a system reset request.
 *
 * @param   none
 * @return  none
 *
 * Initialize a system reset request to reset the MCU
 */
static __INLINE void NVIC_SystemReset(void)
{
  SCB-&gt;AIRCR  = (NVIC_AIRCR_VECTKEY | (SCB-&gt;AIRCR &amp; (0x700)) | (1&lt;&lt;NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
  __DSB();                                                                                 /* Ensure completion of memory access */              
  while(1);                                                                                /* wait until reset */
}