SDC constraints for two flop sychronizer
A two flip-flop synchronizes can be constrained with the follwing XDC lines. XDC is a Xilinx flavor for the commonly known Synopsis Design Constraint files (SDC).
set_property ASYNC_REG true [get_cells -regexp {gen\[\d+\]\.Sync/FF2}]
set_property ASYNC_REG true [get_cells -regexp {gen\[\d+\]\.Sync/FF1_METASTABILITY_FFS}]
set_false_path -from [all_clocks] -to [get_pins -regexp {gen\[\d+\]\.Sync/FF1_METASTABILITY_FFS/D}]

Source: sync_Bits_Xilinx.xdc
FF1_METASTABILITY_FFS is the first flip-flop (the meta stable one) and FF2 is the second flip-flop.

A generic 2-FF synchronizer implementation can be found in our PoC-Library as  PoC.misc.sync.Bits, as well as two vendor optimized implementations for Xilinx and Altera. The above XDC code is relatively applied to all instances of PoC.misc.sync.Bits by setting the file property SCOPED_TO_REF to sync_Bits_Xilinx.