SDRAM timing confusion
After more research, it looks like the values could be negative. Relative to the clock, the data valid window can slide all around. To overcome this interfacing difficulty, the part includes a "data strobe" which has matched latencies with the data. Relative to this data strobe, the valid window has a much more consistent and reliable timing. Interfacing with this part would most likely require using the data strobe the clock in the data into the receiving registers.