Maximum capacitive loading for DC-DC converter - how to calculate?
It's hard to guess what is going on inside the black box, but I think you are right in the first sentence; the concern is to keep out of overcurrent protection.

I believe this is a buck converter.  We don't know what the high-side FET is but the concern is that the voltage across this FET is not significant so that it does not dissipate any power.  Because the "on" resistance varies between devices, I believe this type of regulator current limits by measuring the voltage directly across the high-side FET when it is in the "on" state.  To keep this a low value, we must avoid high peak currents.  The device will truncate each pulse and count a fault each time the FET voltage exceeds the limit before the PWM period is complete, and go into shutdown if a small number of consecutive pulses register this fault condition, stay off for a while, and then restart (hiccup).

Although your GRM21BR61C106KE15L (10 uF) has a low ESR, it has a relatively high reactance at 500 kHz of .03 ohms.  The capacitance dominates the impedance, and you can ignore the real (ESR) component when determining the current contribution from the applied voltage.

For the 3300 uF capacitor specified in the data sheet, the reactance of the capacitive component is about .0001 ohm, so the specified ESR of the data sheet of 0.01 ohms dominates.  From this I would conclude that the impedance seen at the output from all of your capacitors' impedances in parallel should not be less than .01 ohms.  I think your decoupling capacitance distributed around your circuit is less of an issue, because the trace resistance and inductance will come into play.