Understanding DAC specs
Each sample is 12 bits, giving one of 4096 possible values. There are 4 additional bits attached to each sample for control purposes.

With an input clock rate of 50 MHz, that means the maximum sample rate isn't 5 MHz, (I don't know where you got that from) but 50MHz/16 = 3.125MHz.

And your MCU needs to feed it at that rate : 16 bits, 3.125 million times per second, if you want to achieve that sample rate. It's perfectly OK to run it at a lower rate, of course. There are 2 ways to do that : either use a slower clock on the SPI interface, or by only asserting SYNC less often.