CMOS output voltage depending on Vss and Vdd
A CMOS logic gate only sees the difference between its Vdd and Vss pins as the power voltage.  It doesn't know nor care whether you consider those to be +5 V and 0, +7 V and +2 V, or +3 V and -2 V, for example.  The output driver stage either connects the output to Vdd for a logic high or Vss for a logic low.