Need help with sequential element being partly removed from the module even if I am using completely
What you are seeing is completely expected.

In your code for row_start_r, you do:

always @(posedge clk)
begin
        if(rst) begin
                row_start_r &lt;= 64'd0;
        end
        else if (fifo_wr_en) begin
                row_start_r &lt;= row_start_r + 64'd32; //skip_offset ;
        end
end


So you set it to 0 during reset, that's fine. Then when not in reset, each cycle you add on 32 (64'b0100000) when fifo_wr_en is high. Also fine.

However in all of this, look at the lower 5 bits. They are initially set to 0, and then you either add 0 to them, or let them keep the same value. Never will they be set to anything other than 0, so the synthesiser will optimise them away.

Removing these bits will not affect the behaviour of what you described, it is simply the least resource consuming way of achieving your requirement - after all, that's what the synthesizer is there to do, optimise.