Need help for a Dflop implementation in LTspice
For help with LTspice DFLOP, see this shackexchange topic. Likely some logic thresholds are not set properly. The default voltage levels for logic elements are 1V, and your input never goes below 1V; thus the output is always High.

However, the bigger problem is with the "recommended" circuit. If the input has an accidental glitch and the bouncing garbage coincides with latching edge of 555 clock, the circuit output might produce a solid signal for the full clock duration. Normally all debouncing circuits work on integration principle, not just by bare sampling by flip-flop.