Running VHDL process off an input clock higher than the FPGA clock?
For Cyclone II you can easily apply a 60MHz clock input via the EXT_CLOCK SMA.
I take it this is what you are doing? Make sure you synthesize for this clock rate.
It is not the flops to worry about, but rather the combinational logic delays. The compiler will make sure that internal logic meets the delay requirements, and it will re-configure your logic to make it work. To understand this better, read up on &quot;set-up and hold&quot;.
If you are using external memory, other restrictions apply as well, but with 60MHz you are well within the maximum.
Beware, you still have to meet the setup &amp; hold timing conditions at your I/O, if you are running a synchronous interface. You'll need a scope to verify.
At 60MHz and short wires/traces there should be no issue, so you could be lucky without further testing, but I would not recommend you rely on luck.
I haven't used your board, but for a possible clock input see https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_cii_starter_board_rm.pdf