VHDL nested generate statements: how to refer to label?
I found an old comp.lang.vhdl post that led me to the FAQ.

Section 4.2.3 seems to suggest that you can use one or more additional for loops to assign your attributes, by referring to the instances of your FDCs using the syntax outer(index).EX_do1.

I'm not set up to verify this myself &mdash; let me know whether or not it's helpful.