PLL design VCO and RC filter connection in real sense and not in block diagram level
Your third diagram shows a very good method of controlling a VCO's frequency with varactors.
The output of the loop filter would be connected to the common point of the two varactors.
Ideally, the reference for the PSD, and the ground point for capacitors in the loop filter, would be VDD, not ground, so using the same point as the reference for the varactor voltages in the VCO. This would minimise the tendency of any noise on the VDD line tending to modulate the frequency of the VCO. This can matter if you're trying to design a low phase noise system.
While the frequency of the VCO is not stable with respect to changes in the tail current, this is not the ideal way to try to control the frequency, as the effect is fairly weak, using the bias dependent parasitics of the FETs.