Use Xilinx Primitive elements in Verilog inside ISE
Primitives with prefix "X_" don't look like normal primitives.

I tried once to hide pins from top-level. So I instantiated IPAD and OPAD primitives in VHDL by hand.

Results:


Synthesis XST -> complained about black-boxes
Translate     -> complained about black-boxes
Map           -> was very happy
P&amp;R           -> run as normal
BitGen        -> run as normal
test on FPGA  -> all as expected


Xilinx has several primitive libraries:


UNISIM
UNIMACRO
UNIPRIM
...


I don't know if there is also a documentation for XST/iSim, but I found this for Synth/xSim (Vivado): Vivado Design Suite User Guide - Logic Simulation (UG900). Have a look at pages 14 ff. It lists all libraries and when they are bound in simulation (post synth. / post impl.)