Propagation delay of a gate
The propagation delay is a conservative estimate for the analog settling time after modification of an input on the worst case path. You cannot draw any more conclusions about the part from that number alone.

Important points:


it's a conservative estimate, so it has been adjusted by engineers so that only a negligible number of parts will even come close to it and parts that do not perform to this specification can be discarded without incurring heavy costs.
it describes the behavior of an analog circuit. After the settling time, interpreting the analog signal as a digital signal is safe, but before that, this needn't be the case.
there are multiple signal propagation paths of different lengths. For gates with multiple inputs, that is obvious, but even a NOT gate uses two transistors, which might not switch at the exact same time.


Especially the bit about seeing gates as analog devices on the lowest level is important for power consumption estimates when cascading gates. During the settling time, the output is essentially undefined and might also be at an intermediate level. A gate using this as an input could then have transistors in half-conductive states, drawing more power than normally, and in turn outputting an invalid signal that causes the same down the gate tree.

So, both answers are allowed as well as anything in between, or a voltage that corresponds to neither 0 nor 1.