Does not the wire signal affect in sequencial logic?
done is probably being updated before the always block is executed within the same time-step (i.e. zero-time). 

A wire can only be assigned with a continuous blocking assignment. Non-blocking assignments (&lt;=) can only be done to reg. If the assignments of the regs that drive done are changed from blocking (=) to non-blocking (&lt;=), you should be the desired result. 

A non-blocking assignment does an immediate evaluation with an delayed update. This allows the correct values to be evaluated without impacting the evaluation of a depended expression. Note: the delayed update is in the verilog time-step scheduler; it will not have a visible delay in waveform.

Use non-blocking assignments on reg you want treated as a flop. Any reg used for combinational logic or clock generation should use blocking. There will be race conditions if non-blocking is used for combinational logic or clock.

...

reg clk;
reg a,b,c;

always #10 clk = !clk;

assign done = func(a,b,c);

initial begin
  clk=0;
  a &lt;= 1'b0;
  b &lt;= 1'b0;
  c &lt;= 1'b0;
  #10;
  a &lt;= 1'b1;
  #20;
  b &lt;= 1'b1;
  a &lt;= 1'b0;
  #20;
  a &lt;= 1'b1;
  c &lt;= 1'b1;
  #20;
  a &lt;= 1'b0;
  b &lt;= 1'b0;
end