The intrinsic differences between H/W tasks (executable on FPGA) and S/W tasks (executable on CPU)
Pretty much any calculation you can do on an FPGA in hardware you can do on a CPU in software - that is of course how simulation tools are able to simulate your design. Similarly anything you can do on a CPU you can also do on an FPGA (even if that is just by building a soft CPU).

The only difference between them is time and efficiency. As a quick example, you can run a CRC algorithm on a CPU, but it is almost always faster to use a hardware implementation to do the calculation, however depending on the size that might use more power (it might use less) and space.

However the same cannot be said when it comes to interacting with other hardware. When it comes to connecting to external devices such as high speed ADCs/DACs or PCIe, the FPGA is king. With high speed serial and parallel interfaces, it is impossible to interface directly to a CPU because it is simply incapable of big-banging the interfaces unless run at a impossibly high speed. (As a side not dedicated hardware includes PLLs, but for low speed CPUs can do away with them by big-banging in software).

There is another case when the FPGA is king and that comes down to very timing critical events. If your main CPU is busy handling things like a user interface or other bits of hardware, it could easily miss an event or not be able to process it in real time. This even could for example be some timing critical trigger to start recording data from an ADC or sending data to a DAC. For these sorts of cases having dedicated hard on an FPGA waiting for the event and then handling it immediately would allow for things to happen at exactly the point they should even if the CPU is busy doing lots of other things.

So really it comes down to timing critical vs not. If you have a task which has to be done at an exact point in time, or an interface which is of higher speed than the CPU can handle, or even just a very large calculation that would use up too much CPU time, then dedicated hardware in an FPGA can solve that.