Problem getting correct output of filter in VHDL simulation
I guess you are starting in VHDL.
Many points make that it will be difficult to synthesize and meet timings: There is a lack of pipeline in your code.
Still, here is a functional bug I see
This part is wrong:
shift_data    &lt;=  signed(sample_input)    &amp; shift_data( 0 to ( taps - 2));
if FirIn = '1' then
  -- count = 0, data_in 
  shift_data(0)    &lt;=  signed(sample_input);
else 
  -- (M-1)-zeros, count = 1:3
  shift_data(0)    &lt;=  (others =&gt; '0');
end if; 

I would write it like this:
if FirIn = '1' then
    shift_data(0)           &lt;=  signed(sample_input);
    shift_data(1 to taps-1) &lt;=  shift_data(0 to taps-2);
end if;

After correcting the previous stuff, it is possible that you don't see anything at the output as you select bit 22 to 11 from add_data
sample_output   &lt;= add_data (22 downto 11);