When should I use negedge on a clock signal?
If you are a novice in digital design, I would recommend that you only use negative edge-triggered register for interfacing to other circuits where this is required to get the timing right. An example of this is a DDR interface as @Paebbels mentioned in his comment.

Of course, if you are an experienced digital designer you could use a negative edge-triggered register in an otherwise positive edge-triggered design to interface between aligned clock domains.

The main point to remember is that you should not mix positive and negative edge-triggered registers in a design unless you are absolutely sure you know what you are doing, otherwise this may cause bugs that can be very hard to find.

P.S. The code you show will by most synthesis tools not be implemented as a blockram because of the clear signal setting the content to zero. It will most likely be implemented in discrete registers and be very slow.

Edit:
Another possibility of using a negative edge-triggered clock in a positive edge-triggered design is on a synchronous block ram.
If you have a synchronous block ram in between two positive edge-triggered registers and you clock the block ram on the negative edge, you circumvent the one clock cycle delay of the otherwise synchronous block ram.