clearing out voltage of a synchronous circuit
At some point, we say (i think) that the circuit is settled, and the
  output voltages are correct representations of the computation. So we
  store them in a memory cell and it's time to run the whole process
  over again.


This is what clocks are for, the circuits are designed so the logic settles before the next round of clock cycles. 


  How exactly do we drain the voltage of a reusable circuit to ensure it
  has the same start conditions every time?


This is what resets are for, every computer has a reset line. This resets the digital logic to a known state before computation. Without resets, digital logic can be metastable (in between 1 and 0), resets force memory elements in logic to go to a known state (either 1 or 0) which is determined by the hardware design. If your circuit does not have resets, perhaps you should consider resets in your design. Resets come in two "flavors" asynchronous and synchronous