VHDL Block RAM Inference
Move the take lookup right next to the increment so the output is registered.

That is a gigantic lookup table, though. You may want to consider using a compressed lookup table to save on the block RAM. The trade-off is you may need a couple of multipliers.

Here is an example of a pipelined, compressed sine lookup table: https://github.com/alexforencich/verilog-dsp/blob/master/rtl/sine_dds_lut.v .  By default, this one has an 18 bit phase input (2^18 = 262k equivalent entries) with a 16 bit output width.  It consumes 3 block RAMs (two are 512x16 and one is 256x8) and two DSP slices.