Is there a way of conditionally triggering a compile-time error in verilog?
I'm sure there is some way to bind in a C/C++ compile time callback. However, as long as your supports generate blocks (introduced in IEEE Std 1364-2001), then you can do something like the following:

generate
if (CONDITION &gt; MAX_ALLOWED /* your condition check */ ) begin
    illegal_parameter_condition_triggered_will_instantiate_an non_existing_module();
end
endgenerate


If the condition is true, then the compiler will give an error because there is a request for something that doesn't exist. If the condition is false, then the operation is skipped. The only requirement is the code for the illegal condition follows legal Verilog syntax and the illegal condition will never accidentally become valid (hence the long and verbose non-existing module name).

If your simulator and synthesis tools support IEEE Std 1800-2009 (SystemVerilog revision released in 2009) or newer revision, then you can use $error() and give a more meaningful message to go with the error. I'm not sure if any venders has implemented this feature yet. It should become the preferred method once most venders implemented, therefore I will give an example:

generate
if (CONDITION &gt; MAX_ALLOWED /* your condition check */ ) begin
    $error("%m ** Illegal Condition ** CONDITION(%d) &gt; MAX_ALLOWED(%d)", CONDITION, MAX_ALLOWED);
end
endgenerate