Why do DDR RAMs have both xDQ and xDM signals?
The UDQS/LDQS strobe signals are strictly for timing; they are not optional, and they must make a transition for every byte transferred and cannot be gated. Remember, data is transferred on BOTH edges of these strobes. The reason there is one for each lane is to relax the constraints on PCB trace skew to just a byte at a time, rather than across all of the bits of a wide interface.
The UDM/LDM signals are mask signals whose timing is the same as the data itself — indeed, these signals are themselves clocked by UDQS/LDQS just like the data is.
When doing a burst transfer where only some of the bytes are being written, it wouldn't work to omit some of the UDQS/LDQS transitions on only some of the bytes.