Max switching frequency of GPIO pins of modern cheap FPGA
Short answer: yes, you can achieve 400MHz IO on the general user IO on the Cyclone V depending on your speed grade.  For example the hard memory controller can run at a 400MHz.  Note also that the fastest speed-grade parts can support an internal global clock of 550MHz.  I'm not sure where your 100-150MHz value comes from but that's not a device limitation ;)  In practice the top-end of the device capabilities will be very difficult to achieve but you should be able to get close.

If you are trying to maximise bandwidth between FPGAs the number of IOs will be limited by your package choice, however there are a number of other factors to consider when estimating bandwidth:


Layout and signal integrity.  To achieve the memory interface speeds you need to have well matched, relatively short traces.  If you are unable to match the traces and keep them short then you may experience signal integrity issues that reduce the frequency below what the device can actually support.  If you must use long traces you might consider sacrificing IOs for integrity by using LVDS rather than SSTL or similar.
Bus skew. If you're trying to maximise bandwidth by bundling lots of IO onto a wide parallel bus you may have difficulty keeping all the bits synchronous and without some form of calibration this will drastically reduce the frequency.  External memory interface have a calibration phase that dynamically adjusts the delay on each bit of the data bus to compensate for skew between bits, you will likely need to do something similar.  For example on Cyclone V you can adjust the output delay from 0 to 150ps in 50ps increments but be aware that these values aren't always changeable at run-time so check the datasheet carefully.
Clocking.  You'll almost certainly want to use a source synchronous clocking architecture rather than sharing an external clock.  This will affect your choice of pins.


Another gotcha when using wide interfaces is the mismatch in internal routing delays to get to the pins - even if your traces are perfectly length matched the internal delays may skew the bus more than you can compensate for on the receiver so always run your design through the tools and feed this information into your board design.  Sometimes it's better to have deliberately mismatched PCB trace lengths to compensate for delays in the device!