How is a VHDL variable synthesized by synthesis tools
I would distinguish three possibilities:


A VHDL variable has no hardware representation at all. Assume the following example 

signal a,b,c : integer;  
...  
process ( clk ) is  
variable var : integer := 0;  
begin  
if ( rising_edge(clk) ) then  
var := a + b;  
c &lt;= var;  
end if;  
end process;


The variable var is not really synthesized as combinatorial logic at all (assuming this is what was meant in the question). It's rather the right hand side of the assignment a + b that is synthesized into hardware. Strictly speaking a variable never is synthesized into combinatorial logic.  
A variable merely holds an intermediate result, which is either evaluated in the same clock cycle -> no hardware synthesized ( this is 1) again ), or is evaluated in the following clock cycle -> a flipflop is synthezised.  
One of those dreaded latches is inferred in such cases where conditional branches exist in which the variable is assigned neither a new value (depending on some signals) nor a default value. Usually this case happens unintended :-)