My design is not meeting timing. What can I do?
Run design assistant and try to optimize design for speed if Your timing constrains doesn't help You to reach the required times. What frequency do You need and how much do You get? What's the worst path? Give us more information.

What You can do is to optimize all combinatorial logic plus always remember to add several pipeline stages if possible. You can also half the internal clock and transfer required data DDR internally. Tell us more about Your application and critical paths, it would be easier to help You. E.g. I recently had a problem to meet timing of MII/GMII mux for Gig-E.