pmos transistor acting as pull down device
A PMOS can be used as a pull-down device, but it isn't because of its poor performance. In books like Rabaey Digital Integrated Circuits they refer to this phenomena as the PMOS passing a strong 1 but a weak 0.

The reason behind this is the regions of operation during pull-up and pull-down.
To synthesize:


Pull-up The PMOS is mostly in linear region
Pull-down The PMOS is always in saturation region


Let's start from case 1, when the PMOS is used as a pull-up device.
In that case: 







simulate this circuit &ndash; Schematic created using CircuitLab

Initially the Out node is low and In is at Vdd. When In is lowered to gnd, the PMOS starts to charge the load capacitor CL.
At this initial moment, the source S is to Vdd, the gate G is to gnd, and the drain D is to gnd as well (the capacitor is initially discharged).
With these voltages, the PMOS is in saturation region. It stays there until Out goes above In by exactly Vt, where Vt is the threshold voltage. Since In is to gnd, hence 0, the PMOS goes from saturation to linear region when Out = Vt. From now on, the PMOS behaves like a resistor, and keeps charging the capacitor till Out = Vdd. Please note that throughout the whole time, the source to gate voltage of the PMOS, Vsg, is constant and equal to Vdd.

For case 2, when the PMOS is used as a pull-down device, we have:







simulate this circuit

Here the load capacitor CL is initially fully charged with a voltage of Vdd, and the input In is at Vdd. When In goes low, the PMOS start to discharge the capacitor. In this case though, as initial condition we have S to Vdd, G to gnd, and D to gnd. Since the drain and the gate are at the same voltage, namely 0, the PMOS is always in saturation region. As you know, the current of a MOS in saturation region depends solely on the gate to source voltage, in the case of a PMOS the Vsg.
The problem here is that the source pin is the output node (Vsg = Out), which is dropping from Vdd to 0. When Out reaches Vt the PMOS does not conduct anymore, since when Vsg = Vt the device goes in cutoff region.
For this reason, the PMOS can't pull down the output node all the way to gnd, but only to Vt, hence the term weak 0.

In reality, the PMOS conducts a little bit when Vsg &lt; Vt, so it eventually pulls down the output node to gnd, it just takes a long long time to do it.

A perhaps easier way of seeing this is through the IV curve of a MOS, as shown in the picture available on wikipedia:


When the PMOS is used as a pull-up device, you're moving along one of the blue lines, from right to left. The Vsg = Vdd decides which one of these lines to use, while the varying output voltage varies the Vsd. As you can see, if you stay on a single blue line there is a continuous path to 0. No matter how little Vsd is, the PMOS is still conducting current.

When the PMOS is used as a pull-down device, you're moving across the blue lines, from top to bottom. The output voltage is the Vsg, so you go from one line to the other, while Vsd is constant. As you can see, there isn't a path to zero here, because for Vsg &lt; Vt there is no blue line: the PMOS is in cutoff.

Everything I just said can be applied, with duality, to a NMOS. A NMOS is an excellent pull-down device but a poor pull-up device.