Design a NMOS with low drain-source resistance
Achieving a resistance lower than 10 ohms should be no problem at all.

First figure out what resistance a single transistor has considering the worst case conditions (process variation, temperature, voltage) that might occur. Then put as many of these transistors in parallel to lower the total resistance to the desired value.

Before doing that, check the available devices in your technology and try to single out the one that has the best properties for this application.