newbie: comparator adjustable level shift
For making a logic analyzer, the main speed bottleneck is going to be your voltage comparator.  Even the super fast ones are typicaly not as fast as a normal digital logic buffer.  A comparator with a propagation delay of 4 ns is considered to be super fast for analog but not very fast for digital logic.  4ns would work for an analyzer that runs somewhere in the 50-100 MHz range, which is just barely suitable for a lot of the things I do.  

If I were doing a logic analyzer I would just use the normal FPGA inputs along with some protection features to prevent damage from 5v inputs and ESD-- mostly a current limiting resistor and some ESD protection diodes.

But let's move on to the voltage comparator threshold.  I would create a DAC.  The easiest way is to output a PWM signal from the FPGA and run that through an RC filter.  The RC filter output should be an analog voltage whos voltage is related to the duty cycle of the PWM signal.  Start with 3.3K ohms and 1 uF, and go larger if there is too much noise on that signal.  Then buffer the RC output using a simple Opamp.  The output of the opamp goes to the voltage comparators.  You might need several buffers, or a cascade/tree of buffers if you have a lot of comparators.

Another thing to consider is that many opamps/comparators do not handle rail-to-rail inputs.  This is more important when your inputs are low voltage signals, like 1.5 and 1.2v.  But could be an issue even with 3.3v logic inputs if you do not carefully select the comparator.  One way around this is to power your comparator off of something other than GND and +3.3v (or whatever).  Maybe -1.0 and +5v is more appropriate.  Beware, however, that you give the FPGA valid input voltages otherwise you risk blowing that up.

Good luck!