Can Nios II read addresses in increments of 1 or only increments of 4?
Your inference that a 32-bit data bus prohibits byte addressing is incorrect. The ARM Cortex-M, for example, has a 32-bit address bus and a 32-bit data bus but it is capable of byte reads/writes at any 32-bit address, half-word reads/writes at addresses where the least significant bit is zero, and full-word read/writes at address where the least two significant bits are zero. It's not clear from your example code, but the NiosII might allow accesses to either half-words and full-words.

The hardware knows what size object is being accessed and shifts the bytes around as necessary.

Edit: The Nios II processor uses an Avalon-MM master port for the data bus. The bus has separate enables for the four bytes in a word. A given peripheral might be designed for 16-bit registers but that does not mean that byte accesses are not possible in general. From the processor reference guide:


  The processor’s data bus is 32 bits wide. Instructions are available
  to read and write byte, half-word (16-bit), or word (32-bit) data.