Confusion: Lock range of PLL
If input frequency and feedback frequency (after dividing) are the same then the PLL is potentially going to fall into a state of in-lock because the phase detector doesn't care about phase differences that are multiples of 2\$\pi\$: -



As the "wandering" clock leaves perfect phase alignment with the static clock (left side), the EXOR output starts to produce thin pulses that become wider as the the wandering clock leads the static clock by greater amounts. At perfect anti-phase between the two clocks the EXOR output is a constant "1" and as the leading extends even more, the EXOR output repeats itself as the phase difference between wandering clock and static clock is 2\$\pi\$ (right side).