Can I create a CMOS AND gate with 2 serial n-type and 2 paralel p-type CMOS transistors?
The logic is correct, that does implement the AND function.   However, the output impedance is dependent on the input state (sinks more
current when inputs are F,F than when they are T, F).  This
results in odd behaviors that made timings uncertain, and
modern CMOS (CD4000B series) gates are almost all
two-stage (with a buffer inverter added) gates.

That reasoning does not apply to one-input (inverter) circuits,
and a few of those (CD4049UB) are still available,
but the two-stage gates have superior gain, so the general
run of off-the-shelf CMOS is all buffered.   Internal to
a complex device, the unbuffered variants are still useful
subcircuits.