how to implement a low pin count stereo display (FPGA)
Aggregating RGB 4:4:4 video with other data down Aurora is eminently doable.   You'll need to multiplex the data yourself - come up with a simple wrapper which has a header stating the data type and length, and then packetise it yourself.  I'd also recommend putting a very simple checksum or CRC on the end of each packet.  This is not a rigorous "proper comms" type error detector, but it's a good way of catching the gross "oops, my fault" kind of errors in your HDL code, or in parsing software.  Things like FIFOs being read whilst empty, bytes being dropped, frame lengths being reported wrong etc.