Very intermittent power MOSFET failure
FET gates MUST NOT float.
Nothing can be guaranteed in that state.

Miller capacitance will happily couple large drive signals onto the gate from drain transients.  A gate driven above its Vgsmax value will often enough puncture the gate oxide and any combination of hard shorts between GDS can result. I have seen DS short with G open, GS short with D open, GDS all short and perhaps GD short with S open but I'd not be 100% sure of that.  

For ANY power FET with an inductive load I add a GS zener mounted as close to the FET as possible, with a voltage rating above Vgs_drive_max and comfortably below VGS_abs_max. This transforms circuits which fail in minutes to hours into circuits which fail never.