DRAM Rank-Level Allocations
Haswell supports approx 32 GB if memory serves.
And the traditional wisdom is, that channel interleaving only happens if the DIMM modules are identical, channel to channel (mirror style). If the DIMMs are not identical, the BIOS won't engage interleaving.
If you have just two DIMMs, 1x 4GB + 1x 8GB = 12 GB total, your RAM controller is likely running them in consecutive / concatenated mode. (The effect of double RAM bandwidth does not happen.) Some BIOSes report interleaved mode somewhere in the POST screen - in your BIOS, try suppressing quick POST, disable graphical bitmap logo / welcome screen, some BIOSes allow you to add an extra delay after POST - to read the POST messages. PauseBreak also tends to work during POST. To know for sure if your BIOS reports interleaving or not, you'd have to plug in two identical DIMM modules and try to find the message in the POST screens.
If your memory controller does in fact run in interleaved mode, you probably should not try to change this from your running OS, even if the hardware would allow you to (which it likely won't allow, as these chipset config registers tend to be locked against modification by the BIOS at the end of POST, irreversibly to the OS).
Guess what would happen if your BIOS and OS were all started up with the RAM interleaved, and you'd remove the interleaving. I mean the effect would be fun to think about - like an office shredder. On the computer screen it wouldn't actually be all that interesting, probably. The OS would likely just freeze hard. Unless the GPU framebuffer would also get shredded, which could yield some interesting visual effect after all...
If you'd like to access just one DIMM at a time, and they're interleaved, and you know the &quot;stride&quot; of the interleaving, how about this: The interleaving &quot;stride&quot; length is likely a power of two (number of bytes). You could as well allocate a chunk of memory, sized as you see fit. For a good measure, I'd either try to ask the OS (or libc) for the allocation to be page-aligned, or if this is not possible, I'd allocate 2^N + 1 pages, and find the boundary inside the allocation. Memory mapping from kernel to user space (VM) is definitely granular at page boundaries, so you just need to mask some bottom number of bits in the address to make this page-aligned (12 bits for a 4 kB page?). Modulo huge pages, but I don't think these would hamper your practical outcome, even if used by the kernel's memory management.
Next, access the allocated buffer by an algorithm that only ever touches the odd or even strides in your expected interleaving scheme.
You could probably try to measure if it works by timing some large transfers. Large enough to trash the cache. Try a transfer that should interleave, and then a transfer that should only hit one RAM channel.
If you do in fact need to have 4kB chunks allocated continuous in a DRAM channel, your only practical chance probably is to derail interleaving on purpose, either by populating just one RAM channel, or by using two (four?) DIMM modules with unequal sizes.