lpddr2 interface differences between different memory controllers?
The bits involved are all address bits in the first command phase for MRW (which simply therefore changes what logical address is used for a given physical address), although these are also column bits in the bank commands during both first and second phases.

These bits are also used in writing the mode register (data for mode register), so certain bits are out of order, but as that is a driver dependency, it can be catered for.

The truth table is in JESD209