VHDL error during synthesis, declarationa and syntax error
All the error messages are due to the signal o_count not being declared in this module. You need to declare a signal called o_count.
I can see that you have declared a component called counter that has a signal o_count as an output. This signal will not be automatically associated with a signal with the same name in this module.
What you need to do is instantiate your component and then connect the lower module signal with a signal in the upper module via the port map.
As an aside, I'd be very surprised if this synthesises even when you have fixed the errors. You are using the math.real package to use a Sine function. Typically the math.real package contains functions that are not part of the synthesiseable subset of VHDL.