VHDL many .ucf files or not
All components are usually integrated into a single top level entity. It would be the final "wrapper" VHDL file which defines all ports, generics and all of the entire design. This is the HDL file which is then synthesized. So one UCF file is enough, which is defined only for this top level module. 

You can refer to synthesis guides from Altera or Xilinx website.