How to bring out internal signals of a lower module to a top module in VHDL?
What you are looking for is called external names (or hierarchical names) in VHDL. They can be used to circumvent scope/hierarchy visibility. The syntax is like the example below.

&lt;&lt;signal path_name : std_logic_vector(7 downto 0)&gt;&gt;


You can also access constants and variables with external names. You have to change the type in the external type though. You can use external names directly for read/write access. However you should use aliases to improve readability.

alias signal_name is 
    &lt;&lt;signal path_name : std_logic_vector(7 downto 0)&gt;&gt;;


The external name has to contain the path to the element you want to access. The path can be either absolute or relative. The individual elements in your path are separated by dots. Note that you have to provide the labels of the instance/process/entity/... and not the name. Absolute path start with a . followed by the name of your top level. For relative paths you can use ^ to move up in the hierarchy. When using constants/signals from some package you can also use @ to move to a library.

An example for an absolute path is

.tb_name.instance_label.sub_instance_label.signal_name


To access the same element from the testbench with relative names you can use

instance_label.sub_instance_label.signal_name


When you want to access some testbench signal/constant from the sub_instance you can use

^.^.constant_name


To access some other constant in a config package located in the config library you can use

@config.pkg_name.other_constant_name


You can use your simulators design/library browser like David pointed out to find the correct path name.

This feature was added in VHDL-2008 so it should be supported by all tools that already have VHDL-2008 support (including ActiveHDL I think). Most simulators do not use VHDL-2008 by default but provide a command line argument or configuration option to enable it.