Handling of temporary signals in concurrent environment
As per the "concurrency problem", you need to have clear in mind that VHDL can execute instruction concurrently, but that not all instructions are executed concurrently at all times. 

In practice, what VHDL does is executing an instruction as soon as one of its arguments changes (e.g. an assignment var1 &lt;= var2 is executed as soon as var2 changes). Getting to your problem, HA1 will be executed when A or B vary, it will produce c1 and s1 as outputs and then, when s1 is produced (varied), HA2 will execute.