What is flash memory wait states?
Wait states are added to the memory access cycle initiated by the CPU. So it's indeed the CPU which has to wait for the slower Flash. The memory controller signals "not ready" to the CPU for a number of cycles (0 to 3), and while it does so the CPU remains in its current state, i.e. having written the Flash address, but not yet reading the data. Only when the memory controller signals "data ready" the CPU will read from the data bus and continue its instruction (latching the data into a register or into RAM).