vhdl - convert a signal to integer
Please do not use the  ieee.std_logic_arith library. It is outdated and makes problems when combining with others. 

You can convert your signal as following:

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.ALL;

signal counter: std_logic_vector(4 downto 0);

counter&lt;=std_logic_vector(unsigned(counter) + 1);
            ...

   if (unsigned(counter) &lt; to_unsigned(4, counter'length)) then

  -- do something

  end if;


If you plan to use a signal as a number most of the time, try to use type unsigned or signed if possible. You can always convert it to a std_logic_vector if needed.


Source: http://www.bitweenie.com/listings/vhdl-type-conversion/

EDIT:

I made a complete codesample that compiles and simulates in Vivado (should also work in modelsim):

library ieee;
use ieee.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;


entity test is
--  Port ( );
end test;

architecture Behavioral of test is
   signal counter: std_logic_vector(4 downto 0) := (others =&gt; '0');
   signal bigger: std_logic;
   signal clk: std_logic;
begin

make_clk: process
begin
    clk &lt;= '0';
    wait for 2 ns;
    clk &lt;= '1';
    wait for 2 ns;
end process;

test: process(clk)
begin
    if rising_edge(clk) then
        counter&lt;=std_logic_vector(unsigned(counter) + 1);
        if (unsigned(counter) &lt; to_unsigned(4, counter'length)) then
            --do something
            bigger &lt;= '0';
        else
            bigger &lt;= '1';
        end if;
    end if;
end process test;
end Behavioral;