Using arithmetic operations in systemverilog
My guess is it requires more than one clock to calculate ((l_count * 68) / 100000) + 1. There should be a warning about this in the synthesis/timing report.

First thing that can be done is reduce the 68/100000 to 17/25000. The synthesizer should have done the same optimization.

Then split the calculation across multiple clocks. Notice in the CatchEchoState state when next_state = CountState;, next_count is not being updated. Some of the distance calculation can be move to this condition. 

In the example below I moved the multiplication to the CatchEchoState and kept the division in the CountState. Check the timing report. If the timing can be meet for partial calc and not the final calc, then include a division of factor of 25000 (ex 40 is a factor of 25000, which then becomes next_count = (l_count * 17)  / 40; ... next_distance =  (l_count / 625) + 1;). If timing still cannot be meet, consider to increment next_count by 17 instead of 1, thereby eliminating the dedicated multiplication logic.

...
CatchEchoState:
  begin
    next_trg = 0;
    if ( i_echo == 1 )
      ...
    else
      begin
        next_count = l_count * 17; // &lt;-- partial calc
        next_state = CountState;
      end
  end
CountState:
  begin
    next_distance =  (l_count / 25000) + 1; // &lt;-- final calc
    next_state = IdleState;
  end
...   


If there is still an issue, then it likely has to do with your top level module or your synthesis configurations.



FYI: o_distance and next_distance need to be at least 24-bits wide to store the maximum unsigned value (assuming max l_count value is 11,999,999). Looks like this is what is going on in the screenshot, but it is 8-bits in the provided RTL.