DRAM3 memory fetch time
In general, DRAM access time depends on many factors:


actual DRAM timings and frequency
bus width
whether operations access open or precharged rows and whether they are "pipelined"
page and power policies of the DRAM controller
internal details of the DRAM controller


If an order of magnitude estimation is okay, worst-case random access latency should be somewhere between 50 and 100 ns assuming no power saving modes are used. 

ADDED: this also assumes the DRAM controller in the FPGA does not introduce its own latencies.