How to implement derivative, and create a delay of dozens of clock cycles?
This will do the function you asked about. You may have to adjust the '51' constant to get your precise timing.

  signal delayCtr       : natural range 0 to 51;

  Delayed : process(RST, CLK) is
  begin
    if (RST = '1') then
      delayCtr     &lt;=   0 ;
      delayedEn    &lt;=  '0';

    elsif rising_edge(clk) then

      if (data_stream_out_stb = '1') then
        delayCtr   &lt;=  51;

      elsif (delayCtr &gt; 0) then
        delayCtr   &lt;=  delayCtr - 1;

      end if;

      if (delayCtr = 1) then
        delayedEn  &lt;=  '1';
      else
        delayedEn  &lt;=  '0';
      end if;

    end if;
  end process Delayed;


You'll obviously have to wire it into the rest of your VHDL yourself, providing clock and reset. Otherwise we'll have an eternal comment exchange. But it shows the operating principle of the solution.