How does cache coherency and DMA work together?
AJN pointed out, that in many cases, the entity controlling the DMA controller is the same as the entity with the caches - namely, the CPU. In that case, of course, one can write software that first flushes the affected cache regions before initiating DMA transfers.
However, that's not always the case, and when there's multiple CPU cores involved (which is rather the norm these days), you need coherency protocols and measures.
This can involve &quot;snoop&quot; units that simply listen in on cache controllers, and DMA engines.
But that can also simply mean that you need to be careful with the memory your devices can DMA to and from. In fact, this is a very practical problem e.g. in things like the Xilinx Zynq; solutions involve not writing into the &quot;proper&quot; RAM but directly into cache, if you know that the data is going to be used very soon, anyway, and hacking together memory barriers for other cases.