What is Verilog Output (.vo) file? When it is created?
A .vo file is a "verilog output" file.  It should be generated in the $PROJECT/simulation/modelsim/ directory.  It contains your top level verilog module plus annotations that specify the timing constraints for the IO pins of your actual device so that the simulator can verify the setup-and-hold times of the IO.

You can generate it from the menu Processing >> Start >> Start EDA Netlist Writer, then you can add it to your simulation.

I think you can do functional (rather than timing) simulation by simply using the original .v source file, but honestly I don't have it working yet either.