VHDL : how to write data in FIFO (first in first out) and read data with diffrent clocks for the writing and reading?
It seems like you're thinking of the FIFO as a shift register.  It isn't; it's more efficiently implemented as a circular buffer.  Keep your data in a memory location, and use two independent pointers for read and write.  Those pointers can be updated in different processes.

As others have said, use vendor IP where applicable, especially for synthesis.  If you're looking for a behavioural model, or for some other reason can't use the vendor-supplied model, the circular buffer is the way to go.