Why there is no shoot-through in CMOS logic gate?
I've guided design teams, to produce control logic with minimal upset to VDD caused by logic transitions. The key

use long channel CMOS --- may be 5nanosecond Tpd instead of 50pS Tpd

operate the CMOS gates/FFs at reduced VDD (not 5 volts)

have an RC filter between global VDD and the LOGIC VDD: 100 pf and 100 ohms

have controlled_slew output driver(s)


Result? passed FCC emissions on first_test.