Simulating PMOS differential amplifier in Cadence
The solution to the problem was not to use ideal current generator for biasing the input differential pairs since that would always keep the mosfet with fixed current.
Another problem that was described was an issue while simulating the whole setup for rail-to-rail simulation of the input stage (a PMOS and NMOS differential input branches).
The problem was in the voltage generator providing the input common voltage (ICM) that was not wired correctly. The negative terminal of the voltage generator was connected to VSS and not GND (as seen in the testbench picture in the Question Post).
For completeness I am posting the correct testbench with good simulation results. Enough to get anyone started for the rest of the discussion on rail-to-rail opamp design.