Why computers can be modeled as sample and hold system
With sampling you convert an infinite variable (time) to a discrete one.
Hold is just a helper for quantization of amplitude values as we haven't invented an converter which needs zero time.
I guess your book tries to emphasize that a computer &quot;transfers&quot; its results to the inputs, fetches other values, then the state is virtually &quot;on hold&quot; while the compute core (ALU) samples and processes the values. When ready, the next cycle starts. So a computer partitions its cycle in 2 or more phases, which is similar but not equal to a AD Converter...
That said we must keep in mind, modern CPU's are much more complex and much more parallel. So while a single CPU Core and its associated Input Registers might be in a &quot;hold&quot; state while computing a result e.g. a division which needs several clock cycles, the instruction fetchers, memory interfaces, DMA, other CPU Cores,... all might be pretty busy.