How does the OR gate work?
simulate this circuit &ndash; Schematic created using CircuitLab

If your OR gate were something as crude as Figure 1 the output voltage would be the average of the input voltages. This might be good enough for an application that just needed to know if either input was greater than zero volts but it's not good for logic circuits.

Figure 2 shows a better OR gate in that either input going high will provide current to the output. The problem is that there's a voltage drop because of the diode and if we were to propagate this signal through several stages the voltage drops would add up making the signal unusable. While not advised for proper logic circuits this can be a handy trick where an OR gate is required in a circuit that doesn't suit logic level chips or where, for some reason, the designer can't fit in a full 4-gate chip.

Figure 3 shows a logic chip OR gate. Internally some transistors are used to detect the input signals and, if they exceed a certain threshold voltage the output transistor is switched. This has the advantage that the output can now switch rail-to-rail and that the drive signal has no (or manageable) voltage drop. Each logic family has a 'fan-out' capability that tells you how many inputs an output can drive reliably.



Figure 4. CMOS OR gate.

Consider how the CMOS OR gate of figure 4 works.


If A and B are both low Q1 and 2 will be off (open-circuit) and Q3 and 4 will be on (short circuit). Notice the 'o' invertor symbol on the gates of Q3, 4 and 5. Point 'C' will be pulled high to Vdd. This will turn off Q5 and turn on Q6 giving a low resistance path between Q and Vss.
If either A OR B turns on one of the Q3 / Q4 transistors will turn off while one of the Q1 / Q2 transistor turn on pulling 'C' low. This will turn on Q5 and turn off Q6 giving a low-resistance path from Vdd to Q.


The point is that the output is 'driven' high and 'driven' low resulting in clean switching and the ability to provide enough current to reliably switch any downstream devices.