how to get a fixed clock frequency from range of clock frequency input in verilog
You shouldn't be re-generating clocks in FPGA fabric. They are unreliable and have skew and routing issues. If you truly need a clock, use the hardware PLLs and clock dividers present on the FPGA. I doubt you actually need a second clock in your case though. You probably just need a a clock enable that fires every N clock cycles to trigger events to happen, but only use it as a trigger. Do not clock anything off the clock enable. Still clock things off your main clock, and still clock your clock-enable generator off the main clock.

Also, note that keywords like "posedge", "negedge", "rising_edge", and "falling_edge" in Verilog and VHDL are interpreted as clock signals by the synthesis software which means they are all given their own dedicated special clock routing network on the FPGA. These are there to run everywhere efficiently and prevent clock skew. That's why you don't want to re-generate clocks in FPGA fabric. You want to use these networks but you also don't want to waste them on pointless clock signals or things that are not clock signals (like asynchronous resets).