How can a transceiver pin be used if its clock is so much faster than the FPGA clock?
The external clock input(s) to an FPGA is typically in the range of 10 to 100 MHz, depending on the application. However, all FPGAs include some number of PLLs (phase-locked loops) that can be used to multiply the clock internally to a much higher value. It is these high-speed clocks that are used to drive the SERDES (serializer-deserializer) logic in the IOBs (I/O buffers &mdash; i.e., pad drivers and receivers).