Difference between LVDS and "Low Power LVDS"
As shown on page 4 of the datasheet, the voltage over the 100 Ω load resistor is smaller in low-power mode, i.e., the current is smaller:



LVDS is a standard (TIA-644).
You can use low-power mode if your FPGA has a more sensitive receiver that is able to cope with 75 mV (the datasheet would tell you this).