High speed memory interface between 2 FPGAs (Virtex 6)
Implement a DDR controller on FPGA B.
Attach the DDR controller to a shared memory interface controller.
Attach shared memory interface bus A to FPGA B internals.
Attach shared memory interface bus B to FPGA B I/O pins.


You may need to make some compromises, of course - 32 bits for data, 31 bits for address, 1 control line probably isn't going to work; you really need more like 70 I/O.  If you can live with 16-bit data then happy days.