Continuous assignment during SystemVerilog simulation
I figured out what was going on. The assign combine statement needs time to pass before it takes a new value.

logic [7:0] foo;      // Signal 1
logic [7:0] bar;      // Signal 2
logic [15:0] combine; // Final signal
assign combine = {foo, bar};

task SendSPI;
    begin
         foo = 8'hFF;
         bar = 8'h00;

         SendToSpi(combine); // combine is undefined.

         @(negedge clk);     // let some simulator time pass.

         SendToSpi(combine); // combine now equals 16'hFF00
    endtask;