Latch-Up in CMOS-Devices
Why do input voltages more than one diode drop above VDD or below VSS cause latch-up?

Because nearly all CMOS chips have ESD protection diodes, and those diodes are part of the latch-up process.

See figure one of this app note from TI.  It shows the parasitic thyristor in a typical CMOS gate, including the ESD protection diodes.