CC110L strange clock signal
The signal "CSn" really seems to be the chip select signal but what you see is not the truth:

If I interpret the dots in your logic analyzer window correctly you have a sample rate of 25 kHz.

The frequency of the CC110L's SCLK signal can be up to 10 MHz.

If I interpret your screen shot correctly the CSn line is low for more than 40µs but less than 80µs. The CC110L uses 16 clock edges per SPI transfer.

This means the clock frequency actually used is somewhere above 400 kHz - maybe 500 kHz. If 500 kHz is true you'll need more than 1 MHz sample rate to see anything (depending on the duty cycle of the SCLK signal even more). And you should use at least 2 MHz sample rate to see a correct SPI signal.

Using a sample rate of 25 kHz (0.025 MHz) you can see nothing.