How x86-64 Intel CPU understands how many bytes load into a register
Most real world CPUs today fetch multiple bytes from the instruction cache at the same time (many cases, up to a full cache line, which is 64 bytes long). Multiple parallel decode engines then figure out the instruction boundaries of 1 or more instructions in that single cache read and proceed to issue several instructions in the downstream stages of scheduling and execution. 

In other words, cache reads, decode, issue, scheduling and execution happens for multiple instructions at any given time for most superscalar processors (which most of mainstream processors are).