Verilog Parallel-to-serial register works only with if statement
The Verilog that does not work is having trouble because you're trying to edge-trigger a register with two different clocks.  That's Simply Not Done -- I suspect that the Verilog spec says that the simulator can do whatever it wants with that (because -- don't do that).
The Verilog that does work is done properly, as best as I can tell.  I'm not sure why you think there's &quot;an extra byte&quot;, unless you're a bit confused about the fact that the load is synchronous, which means that the load needs to be active when the clock goes high.  Looking at the waveforms for load and clock may illuminate what's going on there.