Partial Reconfiguration in FPGAs
The idea behind partial reconfiguration is that you can basically swap out a portion of your design on the fly without having to reconfigure the entire FPGA.  I have not used partial reconfiguration myself, however.  And you may need the System Edition of ISE to get access to PlanAhead.  

The bitstream is the configuration information that informs the FPGA how to configure all of its interal logic and routing elements and block RAMs to implement your design.  The idea with partial reconfiguration is you don't specify a configuration for the entire FPGA, just for some portion of it.  There are certainly limitations on how much of the chip can be reconfigured on the fly and how the reconfigurable portion needs to interface with the rest of the design.  

As far as how to code the dynamic portion, well, it's not really 'dynamic' per se, just reconfigurable.  So you would have to generate probably a separate project for each configuration, and each project would have the implementation of that configuration.  The outputs of those would be partial bit files.  When you load one of the partial bit files, it would replace the implementation of the configurable block accordingly.  

Let's say you had a design for a software defined radio that can speak several different wireless standards.  You can have a common interface to the data path and ADCs and DACs and maybe even a softcore or two in the non-reconfigurable part.  Then you implement the specific modems in the reconfigurable section.  On the fly, you can load up a partial bit file and shut down the radio and swap out the modem while the softcores are still running.  

I'm afraid I can't be of much help on the specifics, though, as I have no experience with partial reconfiguration.