Why are DRAM cells laid out in a square with regards to demux size?
Mostly collated from comments.
The explanation is garbage. The size of the MUX and demux in the square array is NOT half the size! It's log2 * sqrt(N) the size, versus the size of the linear storage array (vector) which is log2(N).
This is ONLY half the size for the special case of N=16, sqrt(N) = 4 and log2(4) = 2, versus a 16 element linear array whose decoder size = log2(16) = 4.
Redraw with 1 million cells! you now need mux/demux of 10 bits (1024 in/outputs) each ... MUCH smaller than a single 20-bit demux with a million inputs!
The crucial point (which gets lost in the linked explanation thanks to its unfortunate choice of 16 elements) is that two structures of size O(1024) are much smaller than a single structure of size O(1 million), which would be required to access 1 million elements in a single vector. This structure would be at least as large as the memory array itself!
Incidentally Elliot's point that the capacitances also increase (reducing speed) as the structure size increases is also true; that is definitely a design consideration but not the only (and probably not the main) one.