Is this memory card circuit designed properly
The Address and CE# pins are quite heavily loaded, as are the data pins during a write. Even though only a single device is active at any time, the capacitive load of the pins is present from all devices at all times.

From the datasheet, A0 to A19 will have up to 48pF load plus any track capacitance and the data pins will have up to 64pF during write. CE# has a slightly heavier load (by virtue of driving the '38 decoder as well as all the memory devices).

That is a bit hefty (equivalent to about 40 inches of 4 thou track for the address pins and almost 60 inches of track for the data pins), so you may wish to consider Address and Data buffers. The track capacitance assumes a 4 thou PCB core to plane.

As noted, you will also need decoupling: a couple of bulk capacitors and two 100nF per device (one for each power pin as they are on opposing sides of the memory devices) would be my starting point. The decoder would probably be ok with a single 100nF part.

You may not need all of the decouplers, but if the pad positions are there, you can always choose to simply not fit the parts.

You may be ok with a single power pin (only one device will be active at any one time), but I would normally provision at least 2 if I have enough pins available.

Update: Use of CE# signal.

As the second SRAM CS signal is being gated by CE# already, it seems redundant to take it to the SRAMS as it is doing the same thing and layout can be simplified.

I would just tie off that CE# signal low at the SRAMS and use the gated and decoded CS.

This has an added benefit: as the capacitive loading on CE# has been significantly reduced, a great deal of timing uncertainty has been removed.