Hardware debouncing of key matrix with minimum passive components
Let's be clear about this. If you have a keypad matrix you are already using processing power to apply sequential logic voltages to the rows or columns then reading the columns or rows back in order to determine the button pressed.

So, each time you get a "result" i.e. you detect that a button has been pressed, you mark that event as "pending" and some time later (10 to 20 ms) you check again to see if the button press you marked as "pending" can be judged to be "actual".

How much more processing time this needs is very little in the bigger scheme in my opinion and if you are so close to the limit at which your CPU can operate then get a bigger/faster CPU or increase the clock speed.

Using Rs and Cs can work but, in all cases it will produce a "slow" output that would need to be schmitt triggered to clean up the slow edge to a fast edge that is suitable for the logic that follows. You might get away with it of course but then you have a fixed solution with no flexibility.

Having said all the above, you might also need capacitors from each matrix line to ground to avoid ESD/EMC issues.