How to group >4 variable k-maps
You've extended a 4x4 k-map into an 8x4 k-map by putting the a and a' cases next to each other. It looks to me like you've gotten all the terms correct. I think it might be a little easier drawing a single 8x4 or 4x8 k-map. The indices for larger k-maps still follow Gray code, so if you put a, b, and c along the vertical edge of your map, then you'll see 000, 001, 011, 010, 110, 111, 101, 100. Try that and see if you find it any easier. For three bits or more, a single boolean term may appear as multiple islands of ones (or zeroes).

Karnaugh maps only work up to a certain point. Imagine trying to work with a 4096x8192 k-map. For bigger situations, give each boolean variable a meaningful name. Then when you have a moderately complex boolean expression, hopefully its meaning will be obvious by inspection. Instead of gathering terms using a graphical technique like a Karnaugh map, you can simply do some algebra.

Karnaugh maps make historical assumptions about what kinds of logic gates are cheap and available, and those assumptions aren't always valid for modern FPGAas and CPLDs. Tools from Xilinx, Altera, or other manufacturers will know what optimizations are most helpful, and do them automatically. So don't beat yourself up too hard developing a knack for giant Karnaugh maps.