How to use an H-clock tree in a pipelined adder
Part of the disconnect may be coming from the "H-Tree" clock distribution network being a physical layout concept in addition to a schematic level concept. The key part of the H-tree is that since every branch is physically similar, and has the same number of clock loads, that the actual clock skew will be minimized. Another key point is that you would include inverters even if the outputs are not used just to keep the distribution network balanced.

You need clock buffering on anything other than a small design, as each flip-flop clock pin will "slow down" the clock transition time to a point that your flip-flop runs slower and has a more ambiguous switching time. Significant clock skew in your design can cause you to pull your hair out during static timing analysis and verification.

If I were implementing this design in an ASIC, I might instruct the place and route tool to generate the clock network with a "H-tree" layout. If you have to turn in a (hand designed) physical layout, then you have a guideline to work from. If you just have to turn in a schematic... I guess show the clock buffer tree.