Concatenating from Block RAM in Verilog
I figured this out. I didn't really need block RAM at all for my purposes.

To describe the purpose of this exercise (for those interested), I am trying to send data from a text file through a serial communication to an FPGA. Every time the serial connection signals there is data to be sent, the FPGA logic should accept data and write it to an appropriate location. Basically, this amounts to a register file:

reg [15:0] RAM [0:63];  // 64 x 16-bit (128 byte) RAM
reg [5:0] addr;         // 6-bit addressing to 64 elements
always @(posedge clk)
begin
    if (write_data_flag == 1'b1)
    begin
        RAM[addr] &lt;= data_from_USB;
        addr &lt;= addr + 1'b1;
    end
end


When synthesized, this results in distributed RAM (implemented as an LUT), which eats into the available resources I have for synthesizing other logic. Since my RAM array is rather small, I think this is OK.