SRAM and D-flip flop instead of transistor
The most common form of DFF uses six 3-input basic gates (NAND or NOR). In CMOS, a 3-input gate requires 6 transistors, so the total for the DFF would be about 36 transistors.

In an SRAM cell, four of the transistors do the actual data storage, while the other two connect the storage cell to the bit lines under control of the word line. The DFF would require at least one more transistor to accomplish the latter function.

A simpler (not edge-triggered) D latch would still require four 2-input gates, or at least 16 transistors.