Do I have to explicitly connect all pins of the ethernet chip in the FPGA when designing a new controller?
The data sheet usually has a table of pins which indicates pin function and if it can be left not connected. See page 11 of the datasheet. Page 13 shows test0 and test1 may be left floating, as an example.  

Vdd and Vss are required,  since those are supply pins. Mode pins are usually pulled up or down to select the mode of the device, and oscillator is required in most cases in my experience.  Read the datasheet from back to front. The vast majority of pins need to be connected to something, not always the FPGA.

Also, you can connect the mode pins to a couple of the FPGA gpio pins to set the mode from the firmware. Check your bank voltages first, though.