Daisy-chain SPI modules current consideration
Only SCLK and CS are connected to more than one chip when you are daisy chaining.
But they can be buffered as long as the timing constraints allow this.

Typically an input pin does not leak a lot of current. However, you have to be able to drive the capacitance of the line and all the pins.

The relevant numbers for your circuit are:
- Digital Pin Capacitance: 10pf.
- Input leakage current: 1 uA.
- Pull down resistor to pull the signals to a known state in reset.

The absolute maximum ratings only apply when you don't convert the voltage levels properly and are putting a higher (or lower) voltage on the pins than the Vcc (or gnd).

Be cautious not to drive the lines too quickly (slew rate too fast) because that will cause reflections and emissions. Eg: don't buy 1 GHz buffers for a 20 MHz SPI CLK line.