Why two Xilinx scripts with different bitgen options yield correct and incorrect behaviors?
Xilinx has a good build-in help on synthesis, map, P&amp;R and bitgen options. You can open them by opening syntheses/map/P&amp;R or bitgen properties and then clicking on help. This help gives a short overview on every selectable option, it's values and the commandline name.

There is also UG628 - Command Line User Tools which explains the bitgen options (see page 227 ..)


binary:yes -> I think this could be relevant if you are using partial reconfiguration technques
DriveDone:yes -> many boards connect a programming done LED to this pin, which is actively driven, rather then pulled up by a resistor - impact uses this pin to read back the programming state for the gui
StartupClk:Cclk -> Xilinx FPGAs have a startup component which can be accessed from the FPGA fabric and this should be the selected internal clock signal. See the manual for your Startup component for more details