VREF of FPGA should be grounded if not needed?
I believe you only need to connect to the Vrefs on the bank with your single input.

Here is a quote from the Xilinx web site:


  Input Banking (VREF) Rules The low-voltage I/O standards that have a differential amplifier input require a voltage reference input
  (VREF). The VREF voltage source is provided as an external signal to
  the chip. • Any input buffer component that does not require a VREF
  source (LVTTL, LVCMOS2, PCI) can be placed in any bank. • All input
  buffer components that require a VREF source (GTL*, HSTL*, SSTL*, CTT,
  AGP) must be of the same I/O standard in a particular bank. For
  example, IBUF with I/O standard (SSTL2_I) and IBUFG with I/O standard
  (SSTL2_I) are compatible since they are the same I/O standard.
  
  
  If the bank contains any input buffer component that requires a    VREF source, the following conditions apply. 
  One or more VREF    sources must be connected to the bank via an IOB. 
  The number of VREF sources is dependent on the device and package. 
  The locations of the VREF sources are fixed for each device/package. 
  All VREF ources must be used in that bank. 
  • If the bank contains no inputbuffer component that requires a VREF source, the IOBs for VREF sources can be used for general I/O. 
  
  • Output buffer components of    any type can be placed in the bank.