What affects the design of a SOC or uC to offer XIP or RAM for code execution
This is a cost/performance trade-off, with sometimes some system specific design considerations too. Small RAMs can operate at full CPU speed, with low latency (cache, for example), but flash is slower (still varying with process, but slow). 

For a slow CPU clock, flash can keep up with the instruction fetch rate, and XIP makes clear sense (particularly if the flash is in the same package).

Push up the performance a bit, and maybe more tricks are needed to allow the flash to keep up (maybe costing area and power, same as the alternative of adding RAM). This is (not suprisingly) the realm of high-end MCUs, and is ever edging upwards.

Eventually, flash has no chance to keep up with the full system performance potential (but still might be OK for bootloaders, where simplicity is key).

As for selecting a device based on its memory architecture, that depends on your code/data sizes, and required workload throughput. Once memory accesses cease being single-cycle, you're in the realms of benchmarking and guesswork.