Determining maximum load
From the specifications provided in the question you know that Q6 &amp; Q5 have a drain current of 1 mA. You have previously shown that this circuit does behave as a 1 to 1 current mirror. Thus, Q{1,2,3,4} also all operate at a drain current of 1 mA. Since they all have the same geometery they all operate at the same overdrive voltage.

The current of an NMOS in saturation is,

$$ Id = \dfrac{k_n'}{2}\dfrac{W}{L} \left( V_{gs} - V_t \right)^2$$

The overdrive voltage is,

$$ V_{ov} = V_{gs} - V_t $$

Rearrange and solve for the \$V_{ov}\$,

$$ V_{ov} = \sqrt{\dfrac{2(1\textrm{mA})}{8 \textrm{mA/V$^2$}}} = 500 \textrm{mV}$$

Saturation of an NMOS is achieved when the gate-drain voltage is less than the threshold voltage \$V_t\$, i.e. \$V_{gd} &lt; V_t\$. This is also equivalent to stating,

$$ V_{gd} = V_{gs}-V_{ds} $$

$$ V_{ds} &gt; V_{gs} - V_t $$

$$ V_{ds} &gt; V_{ov} $$



For your question, Q3 &amp; Q2 both require at a minimum 1 \$V_{ov}\$ for \$V_{ds}\$. Q1 requires the same \$V_{ov}\$ as Q4 for 1 mA operation, which is Vgs = 1 V. So the minimum output compliance is the sum of the each minimum \$V_{ds}\$ as,

$$ V_{o,min} = 0.5 + 0.5 + 1 = 2 \textrm{V} $$

The maximum permissible load resistance tied to Vdd is one which drops the output to its minimum compliance.

$$ R_{L,max} = \dfrac{5-2}{0.001} = 3 \textrm{k}\Omega $$