what is difference between pass by ref and pass by val in systemverilog?
Consider an example scenario as below:
A person needs to hand over a degree certificate to an organisation.
Either a photocopy of the document or original by itself can be submitted.

Scenario 1: Submitting photocopy:
Lets imagine a scenario where photocopied document gets damaged. Since, the original document remains unaffected, as many photo copies can be made. Whatever damages or changes happen to photo copy , the original stays intact.

Call by value follows a similar approach. It just passes the copy of the object.The original memory location of the object is never shared. Therefore, whatever changes is made in copy is never reflected back in the original. All copies will be having a different address than the original object.

Scenario 2: Submitting Original:
Suppose, the original certificate gets accidentally damaged, there can be no recovery from it.

In call by reference, the address of the original object {degree certificate} itself is shared. Here, a reference to the memory is passed. Thus, all objects will be sharing a common memory and any changes made will affect the original object.

In c,c++ languages, call by references are implemented using pointers. They just point to some memory location. System Verilog draws inspiration from these languages and implements the same features. In system Verilog, the "ref" keyword symbolically means that an address of the variable itself is passed as reference. 

I have tried compiling a simple program explaining the concepts of call by value &amp; call by ref. Go through it.

https://learnwithvm.wordpress.com/systemverilog/functions-tasks/bcall-by-value-call-by-reference/