Synchronous Incomplete Assignment or How is Register Retention achieved
When there is no assignment, the last value of the FF is kept in a synchronous process, in an asynchronous process a latch is inferred.

When there are several assignments to the same signal in the same process, the last one is applied.

if rising_edge(clk) then
   if X then
      if Y then
         reg &lt;= '1';
      else
         reg &lt;= reg;
      end if;
   else
      reg &lt;= '0'
   end if;
end if;


Can be rewritten as :

if rising_edge(clk) then
   if X then
      if Y then
         reg &lt;= '1';
      end if;
   else
      reg &lt;= '0';
   end if;
end if;


Or :

if rising_edge(clk) then
   reg &lt;= '0';
   if X then
      if Y then
         reg &lt;= '1';
      else
         reg &lt;= reg;
      end if;
   end if;
end if;