Reverse Current Protection using two PMOS in back to back configuration
You cannot expect Q1 &amp; Q2 to turn off when all of the bias paths to their gates pull them towards ground (I.e., |Vgs|>0 always). 

You have to explicitly pull up the gates to their source voltage to turn them off. Although it is a useful approximation, it is a misconception that |Vgs|&lt;|Vt| turns a FET completely off, its current will be relatively small, but it actually enters what is known as the subthreshold regime. You are applying around 0.6V, depending on the diodes you are using.

The “leakage” current in this regime might be more than enough to justify what you are seeing.