Multiplication Gate Delay
If you are talking about a general, clocked, shift-and-add multiplier then the total delay will be \$NT_p\$, where \$N\$ is the number of bits and \$T_p\$ is the clock period.The clock period has to be higher than the time it takes for one N-bit addition to take place so in summary Delay = \$NT_p \geq NT_N\$ where \$T_N\$ is the time for one N-bit addition to be completed.

For carry save multiplication, Delay = \$NT_1 + T_N\$, where \$T_1\$ is the time it takes for one 1-bit addition to be computed.So comparing the two multiplication schemes we can see that carry save addition will be faster than shift-and-add multiplication for \$N &gt; 2\$.Shift-and-add multiplication is resource efficient whilst carry save multiplication is time efficient.