Would this be a legal VHDL architecture?
I prefer this solution

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bcd2xs3 is
  port (bcd : in std_logic_vector(3 downto 0);
        xs3 : out std_logic_vector(3 downto 0));
end bcd2xs3;

architecture behav of bcd2xs3 is
  signal bcd_int: integer;

begin
  bcd_int &lt;= to_integer(unsigned(bcd));

  process (bcd_int )
    begin 
      case bcd_int is
        when 0 to 9 =&gt; 
          xs3 &lt;= std_logic_vector(to_unsigned(bcd_int + 3), bcd'length);
        when others =&gt; 
          xs3 &lt;= X"0";
      end case;
  end process;
end architecture behav;