Resetting Ram problem in VHDL
One thing is that 
    if address_rom  = conv_std_logic_vector((PICTURE_WIDTH_HEIGHT*PICTURE_WIDTH_HEIGHT),16) then is never true at this point due to the nested if statements.
You might wanna change your second if-statement into an else condition of the first one.

  if address_rom &lt; 
        conv_std_logic_vector((PICTURE_WIDTH_HEIGHT*PICTURE_WIDTH_HEIGHT),16) then
        write_enable &lt;= '1';
        data_in_ram &lt;= data_rom;
        address_ram &lt;= address_rom;
        address_rom &lt;= address_rom + 1;
       else
          address_rom &lt;= (others =&gt; '0');
          write_enable &lt;= '0';
          done &lt;= '1';
      end if;


Is address_rom initialized somewhere?
For more detailed help we might need your whole code...

Can you explain what the second part of your code does, if done = '1'?