PN sequence generator using linear feedback shift register in VHDL
Xilinx application note 052 describes how to implement such circuits => XAPP052

Besides that, here are some hints and questions for your code:


Your Xilinx ISE 10.1 is very outdated. It's from 2008 or so. Current (and last) version is 14.7 from 2013.
Please use the ieee.numeric_std library instead of ieee.std_logic_arith and ieee.std_logic_unsigned
You aren't using any Xilinx primitives, so you don't need to use unisim.
Why are you using self instantiated flip flops (sd) on the one hand and a generic code description on the other hand?
Why is your output double registered? Your process describes 13 flip flips. The output of a LFSR is normally registered by it-self.
Why are you using odd indices in qout?
Have you checked that your polynomial is a generator polynomial and that your init value is a generating element?