using ram verilog instantiation
You'll need to use the clock to break up the write and read operations. Here is an example of a test bench that writes data to two addresses then reads them back.

wire [DATA_WIDTH-1:0] data = we ? wdata : {DATA_WIDTH{1'bz}}; // tri-state write output driver
ram i_ram0(clk,we,addr,data);

initial begin
  clk   = 1'b1;
  data1 = 'h0F;
  data2 = 'hF0;
  addr1 = 0;
  addr2 = 2;
  we    = 1'b1;
  addr  = addr1;
  wdata = data1;
  @(posedge clk) #1;
  addr  = addr2;
  wdata = data2;
  @(posedge clk) #1;
  we    = 1'b0;
  addr  = addr1;
  @(posedge clk) #1;
  if(data !== data1) $display("ERROR data:%h != data1:%h @ addr:%h", data,data1,addr);
  addr  = addr2;
  @(posedge clk) #1;
  if(data !== data2) $display("ERROR data:%h != data2:%h @ addr:%h", data,data2,addr);
  @(posedge clk) #1;
  $finish;
end


FLY if data is an inout, then you need a tri-state driver in your ram module:

assign data = we ? {DATA_WIDTH{1'bz}} : rdata; // tri-state read output driver


Full working example here: http://www.edaplayground.com/s/6/221