SMPS controller duty cycle resolution
I can see that they operates around 1MHz


No, it can operate at any frequency between 50kHz and 1MHz, including a freewheeling mode where the frequency varies with load/input voltage. It is up to the user to choose which frequency is best, or if constant frequency mode should even be used.  I make a point of saying this because it sounds like you might be thinking that the regulator is doing some sort of sampling or something at 1MHz, which is not the case.  This is not a digital IC.  


  nowhere we can find their duty cycle resolution: 8bits, 12bits, 16bits
  
  I guess the proper answer is something analog instead of digital, but nowhere I can find the "corresponding" resolution.


It can't be found because it doesn't exist. You are correct that the answer is that it is analog and not digital.  But you need to really let that sink in for a moment.  It is analog.  There is no "corresponding" resolution.  Resolution does not have any meaning in this context.   Switch mode voltage regulators are not digital, they do not use bits, and no aspect of their operation has resolution at all.  

You can't find the resolution of the duty cycle because the duty cycle doesn't have a resolution.  It is continuous and determined by a physical process.  You're asking for the voltage resolution of, say, a capacitor being charged by a current source.  Ultimately, the resolution is determined by the capacitance, and how much a single electron will change the voltage.  For a 50pF capacitor, for every 312075453 (give or take) electrons that are forced onto its plates, 1V will appear across the terminals.  So I guess the 'resolution' is about 3.2nV.  In reality, it will be a fair bit less due to shot noise, thermal noise, the angle of your cat's tongue, all sorts of various other quantum mechanical effects.  I suppose you can assign that an ENOB, but I don't see any reason to do so.  

Here, let me explain.

As far as I know, all switching regulators that use PWM control share the same fundamental operation, though there might be some exceptions.  This regulator has a bit of unusual aspects added in, but fundamentally, the PWM still works just like any other switching regulator:


There is a constant current source inside the regulator that is connected to a capacitor.  Since farads are coulombs per volts, or simply charge per volt, and current is charge per second, that means a constant current into a capacitor will result in a linear increase in the voltage vs time.  If you're pumping 1 coulomb of charge into a capacitor per second, and it is a 1F capacitor, then the voltage across its terminals is going to increase by 1V per second as well.  What this ultimately means is that if you charge a capacitor with a constant current source, you get a consistent linear/triangle like wave form.  
If we discharge this capacitor as quickly as possible with each clock cycle, then immediately begin charging it again but with the constant current source, we get a sawtooth wave.  More importantly, this wave will begin with each clock cycle, and linearly increase in voltage over the span of an entire clock period/PWM period, and reach the same peak voltage at the end of the period each time.  What we now have is a ramp generator.  It generates a voltage that ramps up linearly with the percentage of a PWM period that has elapsed, only to reset and do it all over again with the next PWM period.

So what we have is a voltage that represents the exact point within a given PWM period the regulator presently is for any point in time.  And there is nothing digital here, no bits, no resolution.  It is literally just jamming electrons into a capacitor smoothly over time, it is a physical process, not a digital one.  
Now that we have this ramp, it becomes trivial to handle PWM duty cycle:  an analog comparator, which compares one voltage to another, and swings high if the input voltage is higher, or low if lower (or vise versa depending on the polarity), is all we need.  If we feed it the voltage from our PWM ramp along with a voltage proportional to the % duty cycle we want, there you have it.  The comparator will turn the switch on at the beginning of each duty cycle, then turn it off as soon as the ramp voltage exceeds some other set point voltage.  If our ramp reaches a peak of 1V, and we want a 1% duty cycle, then it is simply a matter of feeding the comparator with 1% of 1V, or 10mV.  


This is, unfortunately, a bit of an oversimplification.  There is a lot of analogy loopy regulaty wiggly stuff involving setting the ramp voltage each cycle, usually using either the output voltage (voltage mode regulation) or the inductor current (current mode regulation) that I've left out completely, but I don't think it is particularly important to this discussion.  A bit more on point, comparators have things like hysteresis.  It is a 'deadzone' where they won't actually change their output until the difference between the two compared voltages exceeds whatever the hysteresis is.  If the hysteresis is 10mV, then obviously one would not be able to accurately regulate such low duty cycles as in the earlier example.  But don't worry about that for now - my main point is that throughout this entire description of how this aspect of a switching regulator functions, nowhere is there anything that could be called resolution, nor is there anything we could measure in bits.  It's all real, physical processes happening smoothly over time without discontinuities.  

Back to the bit of information you are actually concerned about, while there is no such thing as a resolution for the duty cycle, there is generally a minimum on time (ton) and off time (toff).  But this is not the resolution, as above these minimums, there is no discrete stepping.  If the minimum on time is 500ns, that doesn't mean that the duty cycle can only vary in 500ns increments.  It simply means that it must be longer than 500ns, and nothing more.  501ns is fine, 502ns is fine, it can vary smoothly as long as you meet the minimum time requirement. 


  So I'm asking myself this question: - for a 1% duty cycle


Why?  Why are you asking yourself this?  Is a 1% duty cycle somehow important or necessary in your application?  More importantly, why are you asking about a duty cycle that is completely irrelevant to this regulator?  The duty cycle of a buck regulator is:

$$ D=\frac{V_{out}}{V_{in}} $$

This regulator has a maximum Vin of 42V, and minimum Vout of 1.215V, so the lowest possible duty cycle this regulator is capable of is \$ 1.215V / 42V \approx 2.9\% \$, so you're asking about a completely irrelevant duty cycle, as this regulator cannot reach anything below 2.9% at the most extreme, nonetheless 1%.  

But, the duty cycle period is always the period of the clock, so for 1MHz this would be 1µs, and 1% of that would indeed be 10ns.

But all of this is irrelevant.  The above is strictly for continuous conduction mode.

When the duty cycle needs to fall below the minimum on-time, the regulator goes into discontinuous conduction mode.  The duty cycle in this situation is much more complex, and is determined by ripple current in the output inductor, the output inductance, switching frequency, as well as the voltage ratio.  

Discontinuous conduction mode ultimately deals with too-low duty cycles by increasing the the discontinuous time (time when there is no current at all flowing through the output inductor) in between each period as needed, while the on time simply stays locked to the minimum on time, ton.  In other words, in discontinuous mode, the switching frequency of the regulator effectively gets lower and lower, as it needs to increase the time through which no current is in the inductor to make the average output voltage stay in regulation.  

Which finally brings us to the conclusion:  why do you think you need to know or care about the duty cycle 'resolution'?  You don't.  It isn't important.  All it determines is, for a chosen frequency, ripple current, voltage ratio, and inductance, when the transition from continuous to discontinuous conduction mode will occur.  You have a large amount of freedom in tweaking this by inductor selection and frequency selection.  And at the end of the day, it isn't like the world ends if it goes into discontinuous mode.  You get a bit more ripple and a bit lower efficiency, but how much does that really matter when your load is at such a low value to begin with?  

If you actually do need to worry about this for your application, then you have even more options by using more advanced buck regulators, ones that can employ a variety of superior strategies than discontinuous conduction mode.  

They can use forced continuous conduction mode, which resolves the minimum on time requirement by letting the current in the inductor actually reverse direction, effectively just vertically shifting the entire waveform beneath 0A as needed to meet the minimum on time requirement.  

Another strategy is pulse skipping, where the regulator will achieve regulation by exceeding the desired duty cycle, but skipping some cycles entirely, such that the average duty cycle will be what it needs to be, thus keeping the output in regulation without having to reduce the frequency.  Instead of increasing the off time between each pulse, it merely skips some instead.   

There are other ways as well, many get arbitrarily complex and clever (and expensive).  They all have different trade-offs, usually between output ripple and efficiency.  Pulse skipping is efficient, but increases output ripple somewhat.  Forced continuous conduction keeps the ripple low but you lose a little bit of efficiency.