Reduced clock speed with flip flop
Assuming your input clock is reasonably symmetric, you can use both edges of it, like this:







simulate this circuit &ndash; Schematic created using CircuitLab

As long as the input duty cycle is close to 50%, the output will have two pulses for every three input pulses. The top part is a simple divide-by-three with a 1/3 duty cycle, and the extra FF on the bottom creates a second set of output pulses that happen midway between the first set. They get combined together by the final NOR (or OR) gate.