Full bridge inverter failing after given input voltage
Your deadtime and Vgs are not shown which must be done with proper &gt; 100MHz probing techniques to eliminate probe ground inductance of ~1nH/mm into the probe cable capacitance using a spring coil on tip/ring or FET diff probes. For this reason , your xx ns risetime test points ought to be twin vias for the sig.+gnd. to match the gap of the spring probe. Improvise for now.
Possible causes of failure are;

excessive Vgs from parasitic mutual  inductance in ESL with positive feedback from source to Vgs max. exceeding breakdown voltage on high left side FET with PWM on low side Drain from parasitic mutual coupling of V= ESL*dI/dt
Excess heat rise from turning off same FET while Vds rises and inductive current continues (or lower than resonant load coil/cap frequency from reducing capacitive loads (or tuning error at high voltage) or high Miller currents during switching (record Temp rise vs Power output vs Vin and try a 4kW or a 16kW WPT design now achieved for WPT.
the main deadtime control comes from the 26 ns nominal deadtime in the IR2110 and the difference in rise fall times from the diode RD * C diode (1000pF) time constant much lower than the 3R * Cdiode both in shunt with Ciss of the power FET.

thermal effects on lowering Vt or Vgs(th) and wide tolerances may not be significant if the risetime is &lt;10ns, but verify.



FWIW there are thousands of published works on kW level WPT on Google Scholar and Microsoft Academic (over 21k articles, some which may be useful to cite)