In verilog code, what happens when repeat statement exists inside always statement with posedge?
A 'posedge'  (or other) condition only becomes effective (can be triggered again) if the events triggered by it have finished.

Thus the first posedge will start the repeat condition. After 20 "posedges" the one at the top can be triggered again. 



A question popped up:
Yes, it is complete legal Verilog and can be used in test benches. 

This is probably a more useful example:

always @(posedge signal)
begin 
   &lt;do something&gt;
   // ignore any posedges of signal for the next 20 clock cycles
   repeat (20)
      @(posedge clk);
end