NMOS transistor: how does its structure relate to two interconnecting diode?
The diodes in a MOSFET are from the source to the bulk and from the drain to the bulk (often called source/drain diodes for short).  

These are not really part of the ideal MOS transistor structure. Rather, these are parasitic devices that are not helpful to MOS operation, and they exist in all "bulk" CMOS processes. They add undesired parasitic capacitance and leakage. [For comparison, SOI CMOS processes have oxide isolation around and below the device and the parasitic diodes are minimized to just the region under the channel and the inner sidewalls of the source/drain regions.  In fully depleted SOI processes, the region under the channel is fully depleted and there are no parasitic diodes.]

Current flow in a MOSFET is by majority carriers from source to drain (or drain to source, if you prefer) through the inversion region under the gate, called the channel, when biased properly. (The diagram provided by TM90 is not correct:  The current from source to drain does not flow through diodes and when inverted there are no junctions in the way of the current flow.)

This is unlike a bipolar transistor, which is a minority carrier device and where the currents do flow through diode junctions. 

You do keep these junctions reverse biased to minimize any leakage current through these diodes.  They do add capacitance and leakage, and are accounted for in MOS SPICE models.  For an NMOS FET the bulk terminal is usually tied to ground and the source and drain are kept at or above ground.  (The diodes don't forward bias until the source or drain are about 0.6V below the bulk potential.)  A PMOS FET has n-type material under/around the device (an n-well, usually) and p-type source/drain regions.  Here the n-well or n bulk is kept at the power supply voltage, usually, and the p source/drain terminals are kept at or below the supply voltage.

To form the inversion region, the gate must be biased one threshold above (in an NMOS) or below (in a PMOS) the source voltage.  This creates a conducting channel from source to drain by inverting the carrier concentration under the gate from the unbiased condition.  In an NMOS FET, the region under the gate is p-type material.  When inverted the region under the gate is filled with electrons, with a depletion region (no free carriers) underneath and then the rest of the p-type 'bulk' material below that.  So the channel has the same 'majority carriers' as the source and drain (electrons in an NMOS).