All Digital Phase Lock Loop
Can you post more details regarding the target frequency, jitter and loop bandwidth (required settling time)? Also, what kind of oscillator do you want to use (external with a DAC, with/without dithering?, an on chip digital counter/accumulator)?

If you're happy with a digital "oscillator" (i.e. an overflowing accumulator) and its jitter then the rest of the circuit can be fairly simple:


a counter (PFD) counting number of cycles between the reference and the (optionally divided) PLL output,
a digital filter - anything will do assuming it does the integration (an accumulator) and it has a zero (minus (or plus?) a scaled PFD output) to stabilize the loop, optionally one or more poles above the loop bandwidth to reduce the control value "ripple" at reference frequency (only matters if fref
most significant bits of the digital filter output (DVCO control value) are given as an input to the overflowing accumulator (DVCO).


As for the loop bandwidth, if not enforced by settling time, decide it based on the noise contributions of all components.


If the jitter comes mainly from the reference or from PFD - use a smaller bandwidth,
If the noise comes from the oscillator - increase it.


In case if the reference signal is phase or frequency modulated - use a loop bandwidth lower than the smallest frequency of the signal modulating the reference.

Trickier techniques are used if the output frequency is close or equal to clock frequency and/or if the low jitter or very fast locking range is required. Maybe in your case they are not needed, besides they may not be well suited to an FPGA implementation.