How does a device's physical size affect its parasitic capacitance?
To answer the questions in sort of reverse order

The parasitic capacitance depends mostly on the semiconductor junctions in the device, and has little to do with the package. It is proportional to the ratio of the junction area/spacing. The area is driven by the current handling the manufacturer wants to achieve, the spacing by the voltage (more is more in both cases)

Therefore the power handling of the device, and the size of the silicon, which are both proportional to the product of those, are only weakly related to the capacitance. 

For most devices, the package is way bigger than the speck of silicon inside that does the work, even devices that look very small.

What governs the capacitance more strongly is the impedance of the system that the device is intended to work in. High impedance (high voltage, low current) means big spacing, small junction area, so low capacitance. Low impedance means high capacitance.

Why is the device small? Several factors, only some related to performance.

a) A small device will have a lower inductance. This is almost entirely driven by the bond lengths in the package, and has little to do with the silicon. This means it is able to work in higher frequency systems, where it's also good to have low capacitance.

b) It's cheaper, a smaller package means less stuff for the manufacturer to buy

c) Finished systems are getting smaller, there's no room to design in a package 1000x the size of the silicon, when 30x will do.