High Voltage NMOS layout design in UMC130nm process using Cadence Virtuoso
To handle &quot;high currents&quot;, you will need numerous (10+ contacts at source and drain and at any metal_to_metal layer changes.
There may be special rules about enlarging the wells around the active/source/drain regions.
And control signals (to the Gate) may be constrained in how they overlap active regions.
These rules will be in the Layout Manual.