SPI: Clock Delay Time
There must be the 50ns time period (11) for the clock pin to be stable to let the high level of CS pin to propagate internally through logic elements before further transitions on clock pin are safely ignored again. 

It is drawn like that because sometimes the bus clock can be continuous or there might be a need to start communication with another device. It does not add much delay as 50ns is only half a bit period for the maximum of 10 MHz clock the memory chip supports at 5V.

So there is no need for the extra clock on the bus, but if there is one for some reason, it must appear only when it's safe.