Interrupt Service Routines and I2c together
The processor won't execute any foreground code during the interrupt.  If the IIC is strictly handled in hardware, then that won't matter.  If this processor is the IIC master, then it won't matter either since you own the clock and can go as slow as you want (most slaves allow this).

However, a interrupt routine taking 2 ms with other things going on, like IIC communication, at the same time sounds like bad overall architecture.  The right answer is to step back and understand what all the processor needs to accomplish, what limited set of things really are low-latency that it must react to, and re-architect the firmware from there.  Propagating a bad design by working around previous mistakes just makes things even worse.