What is meaning of active low input in combinational logic circuits?
There are two things:


The signal level
What the signal means, ie assertion


The signal level is either digital Low or High

The signal meaning is attached to either Low or High, so we say the signal is asserted low or the signal is asserted high. Usually a bar or a slash indicates a low signal assertion level. 

In the case above the reset is asserted low, so "reseting" happens when the signal is brought low. Since we could also reset while the signal is brought high, it is important to track the assertion. 

It is especially important in HDL's to track the signal assertion level. Which is why you should label all of your signals. I've typically seen adding a _L or _H suffix to signal names to indicate the assertion level. In the case above it would be RESET_L. Even adding assertion suffixes in schematics can be helpful