How many pins does a PCI x4 connection needs in a FPGA?
One transceiver per lane (four pins, differential TX and RX) plus a differential 100 MHz reference clock and the PCIe reset line. I think that's pretty much the minimum for a PCIe add-in card. If you're connecting to external PCIe devices as a root complex, the lane requirements are the same, but you'll need to provide reference clock and reset signals to all the devices, which can be done externally (clock buffers, etc.)