Can `ADD` create a control hazard while in the `MEM` stage?
If the memory is a single port memory, i.e. you cant read and write (from/to different locations), IF generally can't occur during MEM phase. This problem can be addressed in several ways:


build a dual port memory: that costs a lot but eradicates the problem
bubble the pipeline: there's some more circuitry that determines if a control hazard can occur and insert some delays around to avoid that. That's somewhat costly and difficult do design
you manually insert a lot of delay states in the pipeline. No "smart" circuitry needed, some registers are needed but it's really simple. Please note that in this way each instruction will require two memory accesses, IF and MEM, and that becomes a limit for speed.


In a RISC von Neumann architecture though the second option is probably the most used: the only two instructions that actually use the MEM status are load and sto so "bubbling" the pipeline should be, if not trivial, quite easy.