Range must be bounded by constant expressions - Verilog
Use part-select (-: and +:). A description and examples can be found in IEEE Std 1800-2012 &sect; 11.5.1 Vector bit-select and part-select addressing. First IEEE appearance is IEEE 1364-2001 (Verilog) &sect; 4.2.1 Vector bit-select and part-select addressing.

Example:

SF_D &lt;= RAW1_i[ 124 - (8*bytes_cnt) +: 4];
SF_D &lt;= RAW1_i[ (8*bytes_cnt)-1 -: 4];


Also discussed on stack overflow:
https://stackoverflow.com/questions/18067571
https://stackoverflow.com/questions/17778418