Developing corner CMOS models from a typical model
I will make a quick detour to point out some flaws in the question:


A mature process implies that they've been running wafers on that line for years, including any pre-production testing. Implying that the foundry has not gotten any statistical data on devices that they're willing to share with users (who will be under an NDA) is hard to believe. 
Analog design doesn't benefit from the concept of process corners as much as digital design does. Some variation is better than none, but it certainly isn't full coverage.




Without any information from the foundry other than a typical model, all you can do is identify how sensitive your design is to various parameter changes, not to really estimate potential yield. Even though corner models are better than nothing for analog design, you really want to be able to run Monte-Carlo analysis with options for including local mismatch. Also, corners are hard to apply to on-chip capacitances and resistances, as "worst case" depends on your circuit.

To understand what goes into process variation, lets use transistor width and length as a starting point. These parameters are manufactured to a particular tolerance (that the foundry should know). Foundry A may have their lithography tuned in so that on your hypothetical 0.25µm process you could expect ±0.02µm tolerance on transistor W and L. Foundry B might have a W and L variation that has a 3-sigma of ±0.05µm. Every parameter has some tolerance based on a doping concentration, mask alignment, or layer thickness, and it's often easier to attack the problem from that perspective.

If your foundry won't tell you (and you can't switch to a real foundry with real information), then you are purely guessing at the extents of the variation. Your "worst case" might be a fraction of the real variation, or many times greater. This is why you will get the response of "Go ask your foundry". 

It's also worth mentioning that there are different classes of variation. Wafer-wafer variation is usually the greatest, followed by same-wafer variation, followed by two transistors right next to each other. Local variation is usually lower than other levels, so your single differential pair input may have low variation compared to two different input channels on a large ADC chip.

Your modeling depends on your circuit design environment and your comfort with making model files. Assuming you don't even touch the model files, you could make a SPICE subcircuit for tweaking the model. You can probably get most of the first-order variation by modeling the Vt offset, conductor mobility variation, and W/L tolerance. Depending on your topology, capacitance and leakage may also be important. Below is an example subcircuit you could use for tweaking worst-case scenarios.







simulate this circuit &ndash; Schematic created using CircuitLab

Tweaking W, L, and VT allow you to get variation without opening up the model files. You can certainly make models that are Monte-Carlo ready, that incorporate statistical variation into the each device, but that's a good amount of work. Try just having a voltage source in series with each gate, and vary that in order to get your Vt variation.