Beginner with fpga and timing issues
Have I understood that situation
  correctly?


Yes - if some part of your output data is available later than other parts, you have to delay the other parts so they line up.

It's not a fudge, or a "bad" thing to do - it's just what has to be done to make the outputs right.


  I could probably buffer the sync pulses too and delay them in the same way. 


That's what I'd do.  (EDIT: And as Yann reminded me, delaying signals can be very cheap in Xilinx FPGAs - 16 ticks can fit in a single look-up table + 1 more in the flipflop that's next to the LUT)


  Or I could pre adjust the calculated memory address to compensate in advance.


That's another option, but will probably take more logic.