Why does splitting a FPGA critical path work to improve performance?
Good question! It does seem a little odd at first blush, but I assure you it makes sense.

In the first version, counter(14:0) must be all-ones before the carry can propagate all the way through to bit 15. With the path split, you test against "111111111111110", so you can tell one clock cycle earlier that the next cycle is going to generate a carry. If you examine the simulation output in a wave viewer, you'll see that incHighNext becomes 1 during the same clock cycle that counter(14 downto 0) becomes "111111111111111". At the end of that cycle, you can already tell that the high-bits-counter is going to have to increment, so you don't have to wait for the carry to propagate all the way from the lsb.