Capacitor after Voltage Reference "for stability"
The reference has a low dropout, so as you can see on the internal schematic (datasheet page 10) it is implemented as a bandgap reference followed by a rail to rail buffer opamp. 

Notice the polarity of the output devices, the PMOS is on top and the NMOS on the bottom, which is a rail to rail output stage.

Both transistors behave as controlled current sources. It is possible to make such an opamp stable without a capacitor on the output, like most opamps, but here it is expected that the reference will have a cap on the output.

Making such a rail to rail output stage (which is very similar to a LDO) stable both with and without capacitance is difficult. Since the output transistors are controlled current sources, the output cap's value controls the open loop gain. Also its ESR adds a zero.

So, the designers settled on a particular value of capacitance and tuned the circuit for it. If you look at "output noise spectrum" page 10 on the bottom, you'll see that 10µF is optimum... this isn't a magic value, simply the designer tuned the circuit for that.

Now, datasheet page 11 gives hints on capacitor selection, so you should also read it...