detector in logic gate design
You first have to write down the truth table, get the logic function f(x1,x2,x3,x4) and minimize (if possible, but I think in this case is not) it with the Karnaugh Maps method. Then you can draw down the circuit using some AND ports (with 4 inputs) and a OR port (with 6 inputs if the f() is not minizable). Let's try. 

Edit: I say 6 inputs because you have 6 multiples of 3 in 0-15 range