Designing lookup table(LUT) for half adder in FPGA
You have a Zynq-7020 device, which contains an Artix-7 FPGA chip. The CLB for this FPGA is described here. It is much more complex than what you imagined. The CLB contains two slices, and each slice has 4 LUTs and 8 storage elements (flip-flops or latches).
The slice looks something like

Furthermore, each LUT has two outputs, O5 and O6. O5 is connected to a &quot;carry chain&quot; which provides a very short connection to a neighboring look-up table, slice, or CLB. This is specifically designed to be the carry output of an adder or counter.
As mentioned by Chris in comments, rather than try to manage all this complexity yourself, with modern synthesis tools (i.e. tools developed in the last 20 years), you'll usually achieve better results by just writing assign X = A + B; in your Verilog than by trying to configure the CLB yourself.