Does msp430 UCSWRST = 1 also reset the bit clock genetator?
It seems it depends if you are in master or in slave mode.

16.3.5 SPI Enable
When the USCI module is enabled by clearing the UCSWRST bit it is ready to receive and transmit. In
master mode the bit clock generator is ready, but is not clocked nor producing any clocks. In slave mode
the bit clock generator is disabled and the clock is provided by the master.
A transmit or receive operation is indicated by UCBUSY = 1.
A PUC or set UCSWRST bit disables the USCI immediately and any active transfer is terminated.