Can anyone explain to me how a carry select adder works?
Consider the gate depth (worst case delay path) for an N-bit Ripple-Carry Adder = 3*N (ref), because it's just a sequence of N Full Adders. The claim in its Wikipedia entry is that the Carry-Select topology gate depth is on the order of sqrt(N). The advantage is only realized in "blocking" the computation, and calculating parallel paths in each block under the assumption that the carry in has a particular value. Each block can do its sums and have stable results ready to choose from without having to wait for the carry inputs from the preceding block. Since each block is calculated in parallel, so you only have to wait for the carry values for each block to be calculated, and for those effective carry outputs to propagate "ripple style" through the blocks. For a 16-bit adder with 4-bit blocks, you only suffer the worst case path of 3 * sqrt(16) gate delays for each block to calculate all possible outcomes, and an additional sqrt(16) delays for the block carries to propagate to make the correct selections, so you end up with something like sqrt(16) + 3 * sqrt(16) delays = 4 * sqrt(16) = O(sqrt(N)) delays. I think that's about right, give or take a constant multiple here or there.  Good luck with your exam :).