CAS Latency and static RAM (SRAM)
Both Static and Dynamic RAMs contain arrays of memory cells with rows and columns, and in theory, there's nothing to stop you from implementing a Static RAM using a multiplexed address bus and hence needing the RAS/CAS signals to manage access. But in practice, nobody does this for two main reasons:


The vastly greater complexity of an SRAM cell means that SRAM chips have much less storage than DRAM chips and there is no great saving to be achieved in multiplexing the address lines because there aren't as many of them.
SRAM is often used when a faster speed is needed than can be achieved with DRAM, such as on-chip caches, and the use of a multiplexed address bus would slow down the memory and lose most of the advantage of using SRAM.


RAS and CAS are also used by the refresh process required by DRAM where a whole row is refreshed at a time. The row address can be supplied externally in some refresh modes while the column address remains latched.