Inferior limit of output voltage in op-amp low-pass inverting amplifier circuit
For low input current reasons the Op Amp you selected is designed for +/-5V minimum due to the 4V FET biasing and the common mode rejection ratio or CMRR input range is 4V above the negative supply rail. (which you show as 0V)

Meanwhile, you are supplying +3V, 0V supply and driving it with 4Vp sine, so you can expect errors when you violate the specs. How the faults are simulated may not  be handled well, but you must be aware of the requirements for supply voltage and CM input range.