Effects of input capacitance on propagation delay (with Logical Effort analysis)
From Wikipedia


  ...electrical effort, h, which is the ratio of the input capacitance of
  the load to that of the gate.


Take this equation, and lets consider what it means:

\$h=\dfrac{C_{load}}{C_{input}}\$

If a gate, such as an inverter, is driving an identical copy of itself (e.g. same drive strength), and wiring capacitance is neglected, then \$C_{load}=C_{input}\$. The only way to reduce the delay is to drive a smaller load than the input. This can happen if you have a 2x drive strength inverter driving a single 1x strength inverter. 

The other issue is that you need to build up to that drive strength. That means that the previous stage now has a larger load, or you are maintaining larger gates throughout the design to take advantage of this in a few specific places. 

You can have a h value less than 1, but you will not be able to use that for many gates in any real application.