Why can't I declare and assign a logic type in one step in SystemVerilog?
The difference is in the timing of of the assignment on the RHS.
When declaring a wire the RHS represent a continuous assignment, so it's a shortcut for
wire y_and;
assign y_and = a &amp; b;

But when declaring a variable, the RHS represent a procedural initialization assignment, and that assignment happens once at the begining of the life of that variable. For static variables, that happens once before time 0. For automatics, the assignment happens once when the entering the procedural block