Why prescaler doesn't give 50% duty cycle pulse
You're only showing half the diagram there, and you're completely missing the context.  Let me show you the whole diagram:



And then you have the context for the diagram:


  The following figures show the Timer/Counter in synchronous mode, and the timer clock (\$clk_{T2}\$ ) is therefore shown as a clock enable signal.


So this is a counter, yes?  Ok.  So it counts up every time the incoming clock toggles.

Now, you could then pass that incoming clock through another counter block as a prescaler and then attach your counting up to that.  That gets complex though, with various multiplexers and such, and it's also very inefficient on power, since there is a lot of switching going on there.

So instead a technique called Clock Gating is used.

The counter is still connected to the main incoming clock, and it counts up every time it sees that clock toggle.  However now, because of the clock gating, it only sees every 8th cycle.

If you had a 50% duty cycle then your counter would count up rapidly at \$clk_{IO}\$ for half the prescaler period, and then not count up at all for the other half.  So it would be like:

0 1 2 3 . . . . 4 5 6 7 . . . . 8 9 (etc)


Which really isn't what you want.  So the gate signal has to be 1 clock cycle in width, which gives you:

0 . . . . . . . 1 . . . . . . . 2 . (etc)