Signal response and settling time graph analysis
Settling time, as opposed to frequency response, is a very complicated issue, and is best addressed experimentally.

The problem is that, in effect, every differential amplifier has a pair of transistors, one for each input. When you first apply a difference, the two transistors heat up to different temperatures. This causes them to have different leakage currents, which produces a voltage offset which is an error term, and the time required to equalize temperatures is a major component of settling times, particularly for very small target changes such as .01%. Since the die is very small and the separation of the two transistors even smaller, equalization takes place very quickly - but in tens of 
microseconds rather than nanoseconds.

For high-precision, high-stability analog ICs, layout of the circuit on the die which minimizes the effects of temperature gradients is critical, and some early IC designers were lauded for their clever solutions.

Settling times to something like 1% are much, much shorter, as the thermal effects on the die are much less significant.

ETA - Oops. As laptop2d mentioned, and I forgot, settling time is measured with a step input on one input, which obviously makes a worst-case situation for the effect I've described.