Is this the correct way of calculating the typical propagation delay?
The trick to this question is understanding how an XOR is constructed. V.V.T had the correct answer.
The blue path is the longest when &quot;A&quot; is low, the leftmost NAND output is high regardless of the &quot;B&quot; input.
The red path is the longest when &quot;A&quot; is high.
I can't find any documentation that indicates that this is how a 74LS86 is constructed, but a NAND gate is a basic building block for TTL so it is likely. I am guessing that this gate implementation is buried in the textbook somewhere, or was included in datasheets back when this textbook was written (old textbook).

image from: https://en.wikipedia.org/wiki/XOR_gate (annotated by me)
Edit: Here is a spec from a TI 74LS86 datasheet. The numbers don't match what the OP posted, but the fact that the prop delay is dependent on the state of the other input is clear. I admit that the NAND implementation is a guess, but in any case, there are 3-levels of gates, transistors or whatever; and one of them is bypassed when the other input is low.

https://www.ti.com/lit/ds/symlink/sn54ls86a.pdf