Is it possible for a VHDL component to have multiple architectures?
To supplement @vermaete's answer:

An entity defines an interface to a box; an architecture defines what's inside. If you don't have the same interface, you don't have the same entity. If you have the same port names, but each architecture uses them for different purposes, well, that's legal, but maybe not advisable - it depends on the specifics.

If you want to use multiple architectures simultaneously, an alternative to configurations is just to use direct instantiation:

U1 : entity my_lib.my_comp(arch1)
   ...

U2 : entity my_lib.my_comp(arch2)
   ...


If you want to use only one at a time, some sort of configuration is probably the way to go.