Memory mapped peripheral on NAND bus
The NAND interface ought to be able to operate at 2 cycle latency, and should be the limiting part in that data path. Assuming you have a 8 bit wide NAND interface, the NAND hardware ought to be faster.

You have the potential to use address and data on the NAND interface, possibly compressing command and data in a single CPU transaction (1 or 2 external accesses).

There might be other complexities that affect either port, but it should be a safe assumption that using NAND will be better for latency and bandwidth.