Is there a more optimized way of making an incrementer than a full adder?
Hmmm,  this all depends on what exactly you are trying to learn.  A counter or adder in VHDL is super easy:

  signal count  :std_logic_vector (7 downto 0) := (others=&gt;'0');
  . . .
  process (clk)
  begin
    if rising_edge(clk) then
      if count_enable='1' then
        count &lt;= count + 1;  -- could be +2 also
      end if;
    end if;
  end process;


And that's it!  The VHDL compiler will normally synthesize a full-adder for this, and them optimize out everything that isn't needed-- ending up with some sort of half-adder.  The nice thing about doing it this way is that your code is readable and easily understood and the compiler deals with figuring out the best way to implement it.

Now, if you are trying to learn about adders and counters and such then my little code snippet isn't going to help you much.  In that case you should implement a half-adder the manual and hard way.