Another solution for all MOS are in cutoff saturation region
I guess you mean the triode region by cut-off. (In my environment it is called so) Here the VDS is smaller than the threshold needed for high output resistance. There is no channel pinch-off due to the small VDS.

It is very strange that you write that all mos is in this region. I do not believe it. If you have a high common mode input, than the input nmos could be in this region, because the diode drop on the pmos. But in this case the current sink at the bottom should have enough VDS to be in saturation.

You can reduce the threshold of saturation for VDS if you use smaller current densities, i.e. use wider transistors for the same current. For longer channel devices theoretically you can pus this treshold down easily. I think the channel length is long enough to reduce VDsat significantly. With a dcOp simulation you can check the operation poit parameters, like vdsat.

Other notes: 


use multiple fingers, not just one wide finger.
you will have systematic offset due to the current density difference between M10 and M7.
use a unit channel length and width for the transistors if possible. Otherwise you will not have matching and the currents will differ from what you might simulate. Only the relative values are certain in IC design.