Looking for High Speed Parallel DAC IC without data latch
If you're using a Xilinx FPGA, use an ODDR output buffer to generate an output clock signal at the same rate as the internal clock.  Other FPGAs should have similar features.

ODDR oddr_dac_clk (
    .Q                (dac_clk),
    .C                (clk),
    .CE               (1'b1),
    .D1               (1'b0),
    .D2               (1'b1),
    .R                (1'b0),
    .S                (1'b0)
);


Or you could just forget the DAC, and build an R-2R network yourself.  Definitely would be a lot cheaper.