Clock skew? Good or bad?
Clock skew happens when clock edges happen at different times in different blocks of the circuit. This may be due to physical distance, clock buffers or parasitic reactances. Skew can be positive or negative (clock anticipated or delayed), depending on which signal is taken as reference.

Normally, in a synchronous network clock skew can generate errors in the data: an example are dynamic gates, where the output is pre-charged in a phase of the clock and elaborated in the other. Skew may cause the propagation of the pre-charge state instead of the right one.

In synchronous logic, skew is considered together with latency, setup time and hold time of gates and registers to determine the maximum clock frequency that can be used. If skew is not known a priori, it must be considered as a tolerance and will contribute negatively to the speed of the system.

Skew can also be used to delay the clock to a register, providing more time for the logic before that register to elaborate. Therefore a faster clock can be used still satisfying the requirements of setup and hold time of the register.

This is a brief explanation and may not be clear, but you can always google or check on wiki for more details.