Can a micro operation pass multiple pipeline stages with a single clock cycle?
Yes and no.

You could make a processor core that might do the equivalent to your above sequence in one clock cycle, but it would happen at the cost of higher propagation delay, which would drive your clock rate down.

As a simplistic example, say that the propagation delay at each of your nine steps is the same.  You've adjusted your clock so that each step is completed with some safe margin in propagation delay.

If you can keep your pipeline full all the time (which can't be done -- but let's say you can) then at each clock cycle an instruction starts and an instruction retires.

Now combine those pipeline steps in groups of three.  Woo-hoo!  Your pipeline is shorter!  But your propagation delay has gone up -- so now you have to divide your clock rate by three, or nearly so.

So -- if you keep your pipeline full -- you issue an instruction each clock cycle, retire an instruction each clock cycle and your clock is three times slower than it was.

Which executes programs faster?