Input and output impedance of a circuit with a BJT
You can determine the input resistance offered by the circuit after the dc-block capacitor \$C_1\$ by using the extra-element theorem or EET already applied in this answer. The extra element is still the feedback resistor \$R_1\$ that I call \$R_f\$ in my calculations.

I am going to first determine the input resistance when \$R_f\$ is set to infinity or simply removed from the circuit. How do you determine a resistance or an impedance from a connecting port? You install a test generator \$I_T\$, the stimulus, which is going to generate a voltage \$V_T\$ across its terminal, the response. Express \$V_T\$ as a function of \$I_T\$ to obtain the ratio you want which is \$\frac{V_T}{I_T}\$.



The input resistance in this mode (you look at the upper right sketch) is obtained quickly as \$I_T\$ imposes the base current.

Then, you turn the excitation off (open-circuit the current source) and determine the resistance offered by \$R_f\$s terminals in this mode. A few lines of algebra and you have it.

Finally, you null the response and determine the resistance offered by \$R_f\$s terminals in this mode. You are looking at the right low-side sketch. The cool thing of nulling the voltage across a current source (this is the response from the beginning) is that it becomes a degenerate case: you can replace it by a short circuit. If you do that, the base is grounded, the base current disappears and all what is left is the collector resistance. We say the null propagates and by inspection, \$R_n=R_C\$.

This is it, we can now assemble all the pieces according to the EET: \$R_{in}=R_{inf}\frac{1+\frac{R_n}{R_f}}{1+\frac{R_d}{R_f}}\$. This is what I have done in the below Mathcad file with arbitrary values. What is cool is that you can verify all your intermediate steps by looking at the dc bias points via a quick SPICE simulation:



If you look at the result I found analytically - please note the low-entropy form meaning a well-arranged formula - it exactly matches that of the SPICE simulation. You can then add the other resistance in parallel with \$R_C\$ if you want, \$R_4\$ in your circuit. Voilà !

Addendum:

While enjoying the view on the Pyrenees this morning, I looked at the output resistance. Nothing insurmountable with the help of the EET once more. The circuit is shown below where the input capacitor isolates the source from the  transistor for \$s=0\$:



First, you install the test generator \$I_T\$ across \$R_C\$, the port at which you want \$R_{out}\$. The circuit is that of the upper right corner and you see that in absence of \$R_f\$, there is no base current and \$R_C\$ remains alone: \$R_{inf}=R_C\$.

Then, open-circuit the test generator and determine the resistance \$R_d\$ "seen" from \$R_f\$'s connecting terminals. We can reuse the calculation already done for the input impedance where we found \$R_d=r_{\pi}+(\beta + 1)(R_E+R_C)\$.

Final lap, determine the resistance \$R_d\$ "seen" from \$R_f\$'s connecting terminals when the current source is shorted or when its response is nulled. This is a null double injection or NDI. The equation to determine the resistance is the first equation used in determining \$R_d\$ because node c is conveniently grounded. This is it, we have all we need to assemble the pieces and unveil the output resistance:



You can check the calculations with the dc bias points and that is a convenient way to chase mistakes. Finally, I can simulate the entire circuit and use a .TF SPICE statement to obtain the output resistance:



The EET is part of the fast analytical circuits techniques or FACTs that I described in the book I wrote on the subject. The idea is to split a complicated circuit into smaller pieces you can individually solve and check. That is the strength of the approach which, at the end, leads to a well-organized expression where each contribution is clearly seen.