Generate an 40MHz Clock on an FPGA with 100Mhz clock
The simple prescaler you've implemented follows the formula $$ fout = fMaster \div (2 * (1 + prescalerN)) $$ where fMaster is the 100MHz master clock input and prescalerN is the prescaler reload value.
There's not a whole-number divisor of (100MHz/2) that produces 40MHz. This is a limitation of implementing the prescaler in general-purpose programmable logic.

Many FPGA include specialized clock generation blocks such as PLL (Phase-Locked Loop). This is a specialized analog circuit implemented in FPGA silicon, which can be configured to run at a faster internal clock than the applied master clock. So the external 100MHz clock might be doubled to 200MHz or maybe up to 400MHz. The PLL uses a control loop principlie similar to what an op amp uses, to accomplish generating a stable higher internal frequency, from a stable lower frequency external reference.

Some Xilinx FPGA have DCM (Digital Clock Manager). Altera calls this kind of thing a "megafunction" if I remember correctly, there should be a megafunction for PLL. Depends on exactly what FPGA you are using. Consult the FPGA's main data sheet.