Prevent EPROM powering from IO pin
It is out of specification of the part to have the SCIO pin be more than 1 V higher than the VCC pin.  From the "Absolute Maximum Ratings" section of the data sheet:


  SCIO w.r.t. VSS ...... -0.6V to VCC+1.0V


Therefore it might damage the part if you apply 3.3 V to SCIO while VCC is at 0 V.  But either way, if it breaks, you get to keep all the pieces since you violated the Absolute Maximum Ratings.