what happens when the carry bit is zero in addition/subtraction algo for hardware
What is happening is:


A is inverted.
A has 1 added to it.
A is inverted again.


This generates what is called the "Two's Complement" of the number in A.

Two's Complement is a way of encoding negative numbers in binary.

You can read more about Two's Complement here: http://en.wikipedia.org/wiki/Two%27s_complement