What does parallel connection of TTL circuits look like
Ok, the assignment is not too clear about how the other NANDs should be connected, and it is open for interpretation ("should one input be connected to GND?" like your drawing implies would make perfect sense). If you were to ask me, I would short circuit their inputs like so below.







simulate this circuit &ndash; Schematic created using CircuitLab

This makes more sense to me when thinking about the application of such circuit. When a NAND input is tied to GND, it will always output 1, and therefore it is a "dead" gate - its output will never change. NANDs with both inputs tied together behave as a NOT and are commonly used in NAND only systems.