What does Vivado HLS logo on the following blocks indicate?
Because HLS means High Level Synthesis. [1] In other words, these blocks take advantage of Vivado's special cores that are hardware optimized for those operations (like doing fast or parallel addition and multiplication in your example). The preceding blocks, as one might surmise from the flowchart you have provided, indicates these are adapter blocks. Since IP blocks usually cannot be used directly with your code blocks, you need some translation "glue" logic. 

You could of course implement adder and multiplier logic on your own using the general logic cells of your board but that may consume resources you could otherwise be spending on other logic. Additionally, the cores are already sitting in your chip so you would be under-utilizing your chip in some sense.

IP Cores are special because they don't use the generic FPGA cell (The lookup table, the adder, the flipflops) but baked in circuitry specialized for the task. They are closer to ASIC hardware blocks. Their inclusion of these specialized cores are often proprietary and hence Intellectual Property (IP). 

[1] https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html