Realizing logic gates with transistors: AND and OR gate in parallel, trying to understand different behaviours
In your second circuit you have the Base-Emitter diodes of the lower two transistors in parallel. The division of the current between both will heavily depend on small variations between the two transistors. This might not show up in your simulation, but it is not a good situation.

The situation with the top two transistors is even worse. The right one will take almost all of the current, because the emitter of the left transistor is at a slightly higher voltage than the emitter of the right one.

That second circuit would work OK with MOSFET transistors, it is in fact the way ports were commonly made in the NMOS days (before CMOS became dominant). MOSFETS are voltage-controlled transistors, hence the problem of how the base current is split between the two transistors does not arise. Bipolar transistors are (base-) current-controlled, hence they each need at separate base resistor.

A potential problem with your first circuit can arise when you use its output to drive subsequent gates. When the output is not pulled down all the way below the Vbe of a transistor (which can happen in the NAND because two Vce's are in series) a subsequent transistor might still receive some base current. Two solutions:


add (for each transistor) a resistor from base to ground of ~ 100k. this would also make the circuit faster.
avoid the two-transistors-in-series circuit, use only the NOR gate as building block (you can still get an AND gate at the cost of two extra transistors by inverting the two inputs).