Possibility of SMBus/PMBus device with I2C Master?
SMBus is a definite subset of the I2C standards.
See http://www.smbus.org/specs/index.html
For I2C specs (maintained by NXP) see this: http://cache.nxp.com/documents/user_manual/UM10204.pdf  

The major differences for SMBus:


SMBus only uses 7 bit addressing (this is defined in concert with the ACPI spec) although SMBus does define an extra register for 10 bit address it is not currently used on any ACPI PC's I know of.
For ACPI (PC) usage SMBus use a minimum 10k bps and a maximum 100k bps data rate. There is a new standard (not yet ratified that increases the speed, but this is not yet introduced as part of ACPI). I2C specifies the bus clock to DC (stopped) and can run much faster, with the new standard up to 3.4 Mbps.
SMBus supports a low power bus pullup specification of 350 uA and a high power mode of 3 mA, I2C species a 4 mA bus pulldown current capability. This results in much shorter line length and power capability for SMBus.
SMBus slaves must implement an auto reset timeout of 35 mS. You don't find this on I2C chips so have to monitor timeouts in the whatever drives the master. This impacts clock extend times, since if the clock is held for more than 35 mS the SMBus will reset, whereas I2C can technically clock extend indefinitely (not a good thing of course). 


To get better coverage  of the differences read Appendix B in the SMBus spec and section 4 of the NXP U10204 spec. 

You can mostly use I2C peripherals on an SMBus, but the reverse is not true. SMBus peripheral implementations may fail because of 'clock extend' problems (causing resets) or at low speeds &lt; 10k bps.