8 bit counter verilog
You define module as tff0(T, Clock, ClearN, Q); but feeding it with tff0 u1 (SW[0],KEY[0],S[7]);, where  SW[0] is used as T, KEY[0] is used as Clock, S[7] is used as ClearN, and output Q is unconnected.

Of course, as you messed wires for tff0, array S, as used only as an input, does not change, and is always a default value as it was at the start (0).