Create multiple clocks on FPGA or create clock dividers
There are different reasons why someone wants/needs to have different clocks in a design. 
Most of the time I try to keep all my design running with the same clock. 

When working with several clocks, we talk about different clock domains. Each signal has its home clock domain. These clock domains are needed by the routing tools to find a layout that meets the timing (= maximum acceptable delay).

If a signal crosses from one clock domain to the other, it is highly recommended to use some crossing logic in order to avoid problems like metastability. Most of the time this is done by FIFOs or Dual-port-BRAM. (More informations about this topic can be found here: http://www.gstitt.ece.ufl.edu/courses/spring11/eel4712/lectures/metastability/EEIOL_2007DEC24_EDA_TA_01.pdf)

Often external interfaces are driven by theire own clocks. In this cases we can not avoid having different clock domains. Use the interface clock to sample the data and maybe do some preprocessing and then migrate the data to the system clock.

Clock Enables: In FPGA designs, clock enables lead to gated clocks and should be avoided by all means. Clocks are routed on special nets. These clock infrastructure takes care of delivering the clock signal to each gate at the same time. After adding logic into the clock path (for example an enable) the clock signal will be routed on normal signal paths. The place-and-route process will have a hard time to make sure, all timing requirements are still met. 
Better than enabling the clock,  would be to make an ENABLE entry to your logic. The clock stays untouched, but the logic knows if it has to react or not. In VHDL this would look something like this:

enable_example: process(clk_C)
begin
if rising_edge(clk_C) then
    if enable_DI = '1' then
        &lt;&lt; write your logic here&gt;&gt;
    end if;
end if;
end process enable_example;


Resources: In therms of resources we need to specify a little bit what kind of resources. There are mainly 3 types of resources we could talk about:


Time:
Running everything with the highest clock makes your design easy to read and understand but may lead to bad timing. High frequencys allow only short routing and logic propagation delays. The lower your clock, the better the chance of achieveing timing constraints.
FPGA Resources:
Modern FPGAs have enough clock nets that you don't need to worry about running out of nets in most cases. But crossing clock domains may need quite some space (FIFO in BRAM or different logic). 
Energy: (I don't have enough knowledge to give a good answer to this)