By what factor would gate geometry have to be enlarged when VDD increases by some factor?
Just increasing gate geometry does not allow for a higher VDD. In CMOS integrated circuits Gate oxide breakthrough is usually the parameter which places a limit on the VDD that can be used.  What happens with smaller processing nodes (for example 40 nm vs 22 nm) is that not only the smallest gate length is decreased but also the gate oxide becomes thinner resulting in lowering the value of VDD at which breakdown occurs.