Doubt in non-blocking statement verilog
The two pieces of code are identical in simulation and synthesis; their values will be swapped. Assignments to x and y use their current RHS values and the order of assignments does not matter because the LHS updates happen after both statements have completed.
If you were to print the the values right after the assignment like
always @(posedge clk) begin

                      x&lt;=y;
                      $display(&quot;x &quot;,x);
                      end

always @(posedge clk) begin
                      y&lt;=x;
                      $display(&quot;y &quot;,y);
                      end

Then there is a race as to which $display statement you will see first, but both will print the current values of x and y, not their updated values.