Xilinx CPLD Pull-Up Issue
You're using the N-FET as a source follower, which is fine, but you've wired the P-FET up in such a way that it will invert the pulses &mdash; i.e., when the opamp is high, the CPLD input will be low, and vice-versa. Did you account for this in your CPLD design?

However, it isn't clear to me why you have the drain of the N-FET connected back to the noninverting input of the opamp, which creates a certain amount of negative feedback.