How do I study the effect of body bias on threshold voltage with a plot of Ids vs Vgs for different values of Vbs using LTSpice tool?
You need a 4-terminal MOSFET model / symbol (not sure if LTSpice comes with that, if not you could make one if you have a suitable MOSFET model)

I would use this schematic testbench:



(since the schematic drawing tool doesn't include a 4-terminal MOSFET, I edited the schematic by hand, I removed the short between bulk-source, so now it is a picture)
You can use the left or the right schematic, it depends on personal preference.
The MOSFET is configured as a &quot;MOS-diode&quot; and biased at a small current (start with 1 uA for example).  Then Vgs will be roughly equal to the threshold voltage, so you can just plot Vgs.
A more accurate method would be to plot the actual threshold voltage value that is used inside the MOSFET model. For that you might need to perform many DC operating point simulations and combine the results in one plot (I am unsure of LTSpice can do that, I use a more advanced simulator: Cadence Spectre).
Left circuit:
Do note that Vbody &lt; 0 V so you need to give Vbody a negative value!
(Bonus question: what &quot;goes wrong&quot; when Vbody &gt; 0 V ?)
Right circuit:
Vsource can be positive, when Vsource = 1 V then Vbs = -1 V.
Start with a DC simulation where you sweep Vbody or Vsource and plot the resulting Vgs.