VHDL Error: Coudl not Implement register on this clock edge
D-Flops are only sensitive to the rising edge of one clock. In your case, you don't actually want it to change on the rising edge of i_pulse_run because the rest of your circuit is clocked off i_clock; what you should do is have another register saving the value of i_pulse_run on each clock cycle, and then when the input value of i_pulse_run != saved i_pulse_run, you are on the rising edge.