Detection of simultaneous edges of two asynchronous clocks
The simplest pure-hardware way would be the circuit below.  







simulate this circuit &ndash; Schematic created using CircuitLab

This works because there's a propagation delay through the inverters.  During that propagation delay, the bottom two inputs will still be high, pulsing the output of the NAND gate.  You just have to make the propagation delay long enough to satisfy the setup and hold times of the NAND, but short enough that it will completely discharge between clock cycles.

It's timing sensitive but definitely doable.  People do it by accident all the time.