How to prevent tombstoning using via-in-pad with small SMD discretes
I would say that this is a valid concern. 0201 passives will be especially susceptible to thermal issues during manufacture. The solid via will represent a very low thermal resistance between the pad and the ground plane due to its shape. Thermal resistance is the length of the material over the cross sectional area multiplied by the thermal conductivity. So it stands to reason that with a fairly thick board you may be okay... but dont quote me on that, there are many other variables at play. Thermodynamics is harder than steel and personally I would rather defer to the experts or an finite element analysis.
This seems like a reasonable choice. However if the components of your design allow for it, I would assume this could be compensated with a longer soak before reflow. I would consult your manufacturer, they may have better advice than myself.
What is the bandwidth of your design? The added inductance you are talking about could very well be within acceptable limits. Do you have access to any sort of PDN analysis software? You may be able to determine the impact on your decoupling effectiveness with a tool from CST or Ansys. Word around the water cooler from Altium Sales dudes is that Altium may be getting AC PDN analysis, but it looks like you are using OrCad which has its own PDN tool I believe.