Resistance on Vcc and input pins CMOS
Are external resistances required for input/outputs/Vcc pins, or are there internal resistances? 








simulate this circuit &ndash; Schematic created using CircuitLab

Figure 1. Various CMOS input configurations.


(a) If the input voltages stay within the power rails - \$ 0 \leq V_{IN} \leq V_{CC} \$ then no series resistance is required.
(b) If the input voltages can go outside the power rails then a series resistor on the input is required to limit the current through the parasitic input protection diodes.
(c) and (d) If the input can be disconnected then a pull-up or pull-down resistor should be used to pull the input to \$ GND \$ or \$ V_{CC} \$. See "Floating Inputs" below for more.


Adding resistance to the \$ V_{CC} \$ pin would be most unusual and never done in standard circuits.


  If internal resistances are used, how much current are the chips designed for?


Internal resistances generally are not used. The input resistance is that of the insulated FET gates and this is > 10 MΩ.


  Does it depend on the chip itself? 


It depends on the logic family as each family will use a standard building block for an input.


  Then what specification should I look for? Why are there max current on output pins and not min currents too, if the internal resistances are huge?








simulate this circuit

Figure 2. A simple CMOS inverter. When the input goes high M1 turns off and M2 turns on pulling the output low. When the input goes low M1 turns on and M2 turns off pulling the output high. Note that the parasitic input protection diodes are not shown.

The input impedance (resistance, if you like) is very high. This is indicated in the FET symbol by the gap between the gate and the conduction path: there is no direct current path.

The output impedance is much lower. Again, we can see that the only resistance on the output is that of M1 or M2's fully on resistance. This low output impedance is a characteristic of most amplifiers. A small input signal drives a stronger output signal. This is a requirement for "fan-out" too so that one output can drive the inputs of multiple other gates.

To answer your question, the maximum output current is limited by the current carrying capacity of M1 and M2 transistors. There is no minimum current. The outputs can be left open-circuit.

Floating inputs

CMOS inputs should never be left floating. This is because the input impedance is so high that the input could float to an undefined level between 0 and \$ V_{CC} \$ and the logic state would be undefined. With reference to Fig. 2 again, the danger is that at some input voltage both M1 and M2 will be turned partially on simultaneously. This could result in passing a significant current through the chip via M1 and M2 causing heating, waste of power and possible destruction. The solution is to pull up or down as shown in Figs. 1c and 1d.