adc-fpga interface guidelines for vhdl
You'll have to supply a pulse to CONVST_A, CONVST_B, CONVST_C and CONVST_D for all three ADCs to start their conversions. Use an external clock (XCLK) to synchronize the conversions. Check the BUSY/INT output for end-of-conversion:  


  When bit C27 = 1 (BUSY/INT in CONFIG), this pin is an interrupt output. This pin transitions high after a conversion
  has been completed and remains high until the next read access. This mode can only be used if all eight channels
  are sampled simultaneously (all CONVST_x tied together). The polarity of the BUSY/INT output can be changed
  using bit C26 (BUSY L/H) in the Configuration Register. (page 16)  


You then can read the data of the different ADCs into several registers. At that moment timing is no longer relevant to the synchronicity of the conversion.