D Latch Timing Diagram
G is indeed a voltage that was at a higher level and then drops to a lower level. This is dependent on the logic level of the D-latch, for example if it is 5V logic then "high" or "1" is 5V and "low" or "0" is 0V. It's a ramp because voltage levels don't change instantaneously in the real world.
The V1/V2 boxes are indeed voltage levels, however notice that they contain two horizontal lines rather than one like the G signal. This represents the fact you don't really care about the voltage levels, you just know they are some level for the latch to store. The cross between V1 and V2 represents transition between the two pulses; notice that when D transitions it is not immediately reflected on Q because of propagation delay, represented by Tpd.
The XXXXX's basically says that with G being "low", whatever changes you make on D will not be reflected on Q; in other words Q is "latched" to V2.