How to terminate switching transistor for level change?
You have a few choices.


Make \$R_2=Z_0\$. This does consume more power, but it is essentially how a CML driver works. (CML reduces the logic swing to 1.0 V or less to mitigate this).
Add an RC circuit in parallel with R2 to make the line match at high frequencies, while keeping the low static power dissipation when the output is low.
Don't match at all. With 1 MHz fundamental, the wavelength is 300 m. Even if you take the 10th harmonic, that's 30 m, so if the length of the line is less than 3 m, your system is likely to work well without matching. 

A simple common-drain inverter like you have drawn typically doesn't have particularly fast edges, so you may not even need to worry about so many harmonics, and you may be able to get away with not matching for longer paths. The rising edge is easy to slow down, simply by making R2 larger. To keep the falling edge slow as well, you might add a series resistor at the output, or deliberately slow down the signal reaching the gate of the FET.