Converting gates in XOR circuit to NAND gates
That's just a trick to save one NAND gate. The output of the top leftmost NAND gate in the second picture is \$Z_1=(x.y')'\$ and of the down leftmost is \$Z_2=(x'.y)'\$. Now \$Z_1\$ and \$Z_2\$ can be re-written as \$(x.x'+x.y')'\$ and \$(y.y'+x'.y)'\$ respectively. Simplifying the two yields \$Z_1=(x.(x.y)')'\$ and \$Z_2=(y.(x.y)')'\$. The latter two expressions for \$Z_1\$ and \$Z_2\$ are what can be inferred from the third picture.