DDR: Is the real maximum speed half of what is advertised in datasheets?
A 200 MHz DDR chip has a maximum bus bandwidth of 400MT/s. It does not mean it can transfer data constantly at that speed. The commands what to read are also sent on this bus, and the requested data is available after the latency period. When the data is available, a block of data can be transferred at full 400MT/s rate.
Usually the maximum memory speed is stated but the chip can be used at lower bus speed. In this case the latency has less clock cycles and the data transfer is just slower.
Edit: So what was missing from my answer was that the burst read commands can be arranged so that the data bursts can be transmitted consecutively.