Determining AXI4-stream Data FIFO size, understanding Packet Mode?
PG085 doesn't say a whole lot about packet mode, but what it does say only applies to the master (output) port of the FIFO. There is no indication that the FIFO will only accept one packet at a time.
It seems to me that what you really want is a second FIFO (also in packet mode) to hold the information that you're calculating on the input side of the main FIFO. This FIFO can be much shallower,1 since it only needs to hold one block of header information for each packet in the main FIFO.
You have one FSM on the input side that computes the length and the checksum, and then pushes this information along with the source and destination bytes into this second FIFO.2
On the output side, you have a second FSM that waits until the second FIFO is ready, reads the packet header information out of it and serializes it, and then reads the corresponding data from the main FIFO and serializes that.
This eliminates the need to have only one packet in your module at a time, and also the need for the input and output processing to run in lockstep.

1 Unless you're expecting a lot of short data packets, in which case, the sizes will be similar.
2 The second FIFO could either be very wide and use only one word per header, or you could make it one byte wide and push the header information in one byte at a time, with TLAST asserted on the final byte.