How to calculate voltage gain with bypass capacitor?
The author’s formula and your variations are close enough but there are reasons to expect up to 20% errors.

Vbe errors.  We are taught to assume 0.7 because it’s easy to remember. Yet this affects Ic and re max gain. For low currents near Ic=1mA, Vbe is more universal to be 600mV as the re drop is less significant. But this formula of re=26/Ic is inaccurate as processing methods for each design adds a bulk resistance that is not included which can raise Vbe for high base currents. So at a few mA it might be more nominal to choose 650mV but beware max/min Vbe @ different base currents might go as high as Vbe 2V @ 50mA base currents which is not the same re that is controlled by Ic. Also thermal rise can drop Vbe by 200mV with a 100’C rise in junction temp. The bottom line is H bias of Vbe is good but still adds error corrected by better designs with current sources and negative feedback with R ratios.
Impedance of capacitors is accurate with the assumption of 0 ESR. Usually electrolytic caps are chosen for 10uF. However, general purpose e-caps have an ESR * C = T =&gt; 100 to 200 us thus 10 to 20 ohms make re inaccurate for max gain. Low ESR caps are found to be T&lt;10us or 1 to 2 Ohms which increases the low frequency low ESR circuit gain. For the input, it won’t matter.   Also voltage bias on caps can reduce their values, so a much higher V rating improves this as well as ESR but may increase component size.
hFE has a very wide tolerance unless you get binned parts and this affects Ic with gain.
Their rule of thumb of a capacitor impedance ratios of 1/10 does not apply to this H bias design because the gain depends on a much higher re/Re ratio of approximately 7/700 or 1%. This means this part of the circuit has two breakpoints between flat gain frequencies.
The high pass effects of 10uF on 560 Ohms attenuates at a higher frequency than the input impedance. These can be easily looked up on an RLC nomograph to get the entire Bode Plot using the intercept for cap impedance at both 7 ohms, ~ 700 ohms and the net input impedance
In the end this circuit is basically a differentiator and a low frequency square wave 10mVpp pulse will produce inverted spikes with the gain that you expect when the impedance C is much less than re  to achieve the gain of roughly the 4800/7 that you expected. But if re is much lower, the gain could be much more.
When you learn about Fourier components you will find the fundamental sine signal peak is actually 2.1dB higher than the +/-  peak square wave at the same frequency as odd harmonics clip the sine wave.
It is always good to understand the assumptions in a schematic and determine all sources of errors that may differ from theory and simulations for any given “Real circuit”.
These are some of the reasons, GBW is another.