FPGA Synthesis = 0 LE (Altera Quartus II)
Without the code, you can only expect general advice.

However the most likely scenario is that the outputs don't actually depend on the inputs, so that optimisation eliminates all the logic in between them and hardwires the outputs to '1', '0' or 'Z'. 

This can often be due to a mistake in your logic, or a reflection of the fact that you are trying out an incomplete design, and the missing portions contain logic that would prevent the optimisation from deleting what you have done so far.