Mod-3 asynchronous up counter using T flip flop in verilog
If you simulate rst without any delay then you have a race condition.  To see what I mean put a delay into your rst:

assign #1 rst = a &amp; b;


and rerun your testbench.  It might synthesize ok, im not sure.

In general, I recommend that if you don't have a specific reason to, you should not run different parts of your design with different clocks, and you shouldn't run asynchronous resets from anything that isn't a dedicated reset circuit.  These are not hard rules, they are general recommendations.