Using FPGA specific hardware components when writing RTL
For the most part, the synthesizer is good at inferring primitives. However, there are primitives that cannot be inferred. Sometimes it as simple as a dual port RAM with different port widths or a FIFO with no extra fabric logic. There are also things like DCMs and PLLs for generating and managing clocks that can't be inferred with pure HDL.

FPGAs in many cases also contain much larger and more specialized primitives such as serializers, PCIe endpoints, Ethernet MACs, or hard processor cores. These must be  specifically instantiated and configured in order to be usable.