clock oscillator substitution, jitter question (audio DAC)
Read this.


"DSC1001 is a silicon MEMS based CMOS oscillator offering excellent jitter and stability performance"


Forget it. It's a MEMS oscillator, not a XO, thus audio band phase noise will be horrendous. It only specifies cycle to cycle jitter, not period jitter, which is a tell tale.


FOX XPresso uses an internal fractional PLL. 


This is awesome, because they actually only stock one model and it can be programmed at the factory to give any frequency you want... but the phase noise graph isn't as pretty as a real XO.


Crystek C3XX specifies "Jitter RMS: 12 kHz~80 MHz" which is a much more useful spec than cycle-to-cycle! 


It is the RMS jitter based on phase noise integrated over the specified bandwidth. Unfortunately, for audio you'd need it specced lower than 12k, but it's a start.


The Kyocera one has similar specs, but they also give phase noise depending on frequency.


So you can enter the values in a conversion tool to have an idea of your RMS jitter over the audio band. Unfortunately, since Crystek does not give the phase noise values, you cannot compare the two.

Among your list, I'm voting for Kyocera or Crystek, then.

I'll put on my audiophile hat for a second: we did some blind tests on $1-2 canned clocks, and did hear quite a bit of difference between them. XPresso was one of the worst. My fave is Vectron VCC1 which is not available in your frequency. Results correlate with phase noise/jitter which I did measure also. No tests were done on expensive clocks mind you, this was just a fun experiment, and I'm not audiophile enough to use a clock worth 20x more than the dac chip, thank you very much!!!

Now, as pointed out by analogsystemsrf (he knows what he's talking about)...


Supply noise on your oscillator will wiggle its frequency. In terms of phase noise, this means the oscillator integrates supply noise into phase noise. Thus a noisy supply will destroy lowish-frequency phase noise performance (ie, audio). So please don't power the damn thing from your MCU's 3V3 rail, I mean at least invest $1.5 into an ADP151 or a LP2985, ferrite beads, and some caps... 
Noise picked up on the clock trace (or the GND, always mind the GND) between clock and DAC also counts, but it is not integrated, therefore problems are easier to avoid unless your layout is criminally bad (like no continuous ground plane under all the high speed stuff... or the clock goes through a ribbon cable next to the DATA line... huge crosstalk... or there's a switcher in the vicinity).
Noise on DAC DVCC modulates its clock input gate voltage threshold and also adds jitter, so don't blindly connect it to a noisy DVCC...


Also if you use a sigma delta DAC high freq jitter also matters: the noise shaper makes huge efforts to push quantization noise into HF... and then HF clock jitter can fold that noise back into the audio band.

Note that many things other than jitter influence dac performance, but a reasonably low jitter is surprisingly easy to get right, so there is no reason to screw it up: good layout, good grounding, clean supplies... and the rest of the design also benefits from this.

(by "reasonably" I mean... you know, reasonably low, not down to bullshitium levels)