Verilog: Change a Certain Delay According to the Current Output
An array of 16 floating point elements: real delay [0:15];. 

Within the always block, a wait statement is needed to allow the delay values to be populated. Because it is a clock, I suggest adding a condition checker to terminate the simulation if it fails. This safeguard is to catch 0-time infinite loops while the simulation is running. 

reg clk;
integer i;
real delay [0:15];

always begin
  wait( ^i !== 1'bx); // This gives us a change to populate delay
  if (delay[i] &lt;= 0.0 || i &lt; 0 || i &gt; 15) begin
    $display("FATAL @ %0t :: Something gone honorably wrong. i:%0d range 0 to 15, delay[%0d]:%0f",
      $realtime,i,i,delay[i]);
    $finish(1);
  end
  #(delay[i]);
  clk = ~clk;
end


Working example