MOSFET W/L ratio limits: what's (un)reasonable?
It clearly depends on the application. Such ratios would be rare for digital designs, but they would be quite common for analog ones.

I have done low-noise AVLSI designs with 12 paralleled transistor fingers that add up to a 2280&nbsp;µm/1.8&nbsp;µm (that is >2&nbsp;mm width in a 0.6&nbsp;µm technology) i.e., W/L = 1266. And I would have gone bigger if size had not been one of the main optimization criteria. Note that these large transistors are actually operating in subthreshold with currents as low as 5&nbsp;µA, and these transistor sizes were increased 50% from the previous design revision that had yield issues due to popcorn noise.

Even in digital designs you can see this. I vaguely remember an old processor in which the main visual feature was a central set of transistors used to drive the clock throughout the IC.