Low energy arithmetic/logic gate level design
Independently of full-adder design (which is very important as BarsMonster says), objectively, the most power efficient adder would be the one with the least number of transistors. 

Using the same kind of full-adder unit (same quantity of transistors in each FA) in the Adders that you mention, the "smallest" would be the Ripple Carry Adder. All other adders have some sort of extra circuitry to lower the critical propagation delay.

Check out this link: http://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/Lecture_2_Slides.pdf @ pages 40 - 48.