Inverted inputs with CMOS transistors
Well, in CMOS usually all functions are inverting. The most simple logic function you can implement is a NAND or a NOR (besides the inverter).

OR an AND Gates in cmos logic are basically NOR and NAND with an inverter behind.

Use De Morgan's law (https://en.wikipedia.org/wiki/De_Morgan%27s_laws) and the rules of boolean algebra to convert your formula:

$$Y=(¬A∗¬B)+¬C+¬D$$

$$Y=¬(A+B)+¬(C*D)$$

Now it depends on your hardware constraints, if you want to have a solution with minimal gates or with more gates but a smaller "fan in" (more input gates make your circuit slower).

A solution with minimal fan in would be 







simulate this circuit &ndash; Schematic created using CircuitLab

This can be translated to cmos 1:1 by using the standard layout for cmos gates.

Now if you want to have a single gate, it gets trickier.
Convert the formula one step further to get an inversion as the outermost operator:
$$Y=¬((A+B)*(C*D))$$

You can see that the basic structure is a NAND gate. 
Now you have to design the pull up network and the pull down network.

For the pull down network, an AND in the logical formula means to connect the transistors in series and for an OR you have to connect them in parallel. For the pull up network it is vice versa.

The pull down network would look like this:







simulate this circuit

And complementary the pull up network:







simulate this circuit

Now combine them and you are done.
If you have inverted inputs in the last formula, you have to invert the inputs with an separate inverter before connecting them to the gate.