VHDL JK Flip-Flop with logic gates
Let's look at one example:


In your entity JK, we have an output signal named Q.
In older versions of VHDL, you are not allowed to read from output signals.
You tie Q to one of the inputs of C12.
You can't do that, because we can't read the value of Q because it is an output signal.


Here's an example of how to fix it:

library ieee;
use ieee.std_logic_1164.all;

entity JK is port(
    J,K: in std_logic;
    Q, NQ: out std_logic;
    CLK: in std_logic
    );
end entity;

architecture JK of JK is
    component nand3 port(
        A,B,C: in std_logic;
        D: out std_logic
    );
    end component;

    component nand2 port(
        A,B: in std_logic;
        C: out std_logic
    );
    end component;  

    signal s1, s2, s3, s4: std_logic;

begin
    C11: nand3 port map(S3,J,CLK,S1);
    C12: nand3 port map(S4,K,CLK,S2);
    C21: nand2 port map(S1,S3,S4);
    C22: nand2 port map(S2,S4,S3);

    NQ &lt;= S3;
    Q  &lt;= S4;
end architecture;


I'm sure we could create better names for these S[1234] variables though.