Ethernet MII Timings MACPHY
You have highly unconventional representation of bus timing. The "BitX" etc. are not happening/asserted valid at transitions, as your pictures imply, but BETWEEN the transitions. And your pick the wrong clock edge for your analysis. Please try to use standard bus timing representation, it will help. 

According to MII timing diagram in LAN8740 datasheet, all actions are occurring on posedge of MCLK:



So, clock rises, data follow in 28 ns max (could be faster, but no less than zero). When the signals reach receiver side (MCU), the data will be arrive  of in ADVANCE of RXCLK posedge by (Tclkp - 28 ns), which is quite longer than the required 1 ns by MCU receiver (shown in RED). 

Thus, there is no contradiction. Transmit timing is usually one thing, receive timing is a different thing, the difference is in allowing the communication channel have delays/ringing etc. settled before receiver sampling point.