SPI interface on Xilinx FPGA, clock domains and timing constraints
The usual approach is to cross MOSI, CS and SCLK to the internal FPGA fabric clock (running at a far higher rate then the SPI bus) domain and do all the actual work there. 

Crossing a clock domain with a parallel register output has at least the inherent possibility of an invalid state where doing it with a serial bus really does not. This is because it is possible for your metastability filter to register different levels on different bits if several bits change state within the setup or hold window. 
Also, taking the serial stream into the core clock domain lets you do things like implement glitch filters easily, which can be worth having.