problem with verilog testbench
I get 2 compile errors when I run your code on 2 different simulators.  Did you try your code on edaplayground?

You didn't define REFCLK_PERIOD and you declared i_SysCLK as a wire.  After making these 2 corrections, and assuming some value for REFCLK_PERIOD, I get output which clearly demonstrates that all 3 clock signals are toggling between 0 and 1.  Un-comment any ONE of the $monitor lines:

`timescale 1ps/100fs

module sim_tb_top;
    parameter REFCLK_PERIOD = 1000;
    parameter CLKIN_PERIOD  = 5000;
    reg sys_clk_i;
    reg clk_ref_i;
    reg i_SysCLK;

initial sys_clk_i = 1'b0;

always sys_clk_i = #(CLKIN_PERIOD/2.0) ~sys_clk_i;

initial clk_ref_i = 1'b0;
  always
    clk_ref_i = #REFCLK_PERIOD ~clk_ref_i;
  initial
    i_SysCLK = 1'b0;
  always
    i_SysCLK = #(REFCLK_PERIOD/2.0) ~i_SysCLK;

initial begin
//    $monitor($time, " %b", sys_clk_i);
//    $monitor($time, " %b", clk_ref_i);
    $monitor($time, " %b", i_SysCLK);
    #10_000 $finish;
end
endmodule