VHDL - passing through INOUT ports
Inouts can exist internally or externally.  Indeed in reality they don't exist as physical gates, in both cases they are two gates in oposite directions in parallel.

Internally inout is usually imlememnted as an array of OR gates for the driver and multipel connections to AND gates for the receivers.  There is no tristate internally.

Externally inout is usually two gates, the output one being able to be tristated by some common select signal.

VHDL does not care about 'internal' or 'external' signals. 

So long as the VHDL syntax inferrs some means of deciding which device is being selected for access to the inout, the same code can be used as a top level or lower level module.
e.g. Within your module(s)

bus&lt;=myoutdata when RD='1' else (others=&gt;'Z');
myindata&lt;=bus;


The else others bit suggests to VHDL that the bus is shared if bus is an inout.  The shard signal, a version of which must go to every module that has access to the bus arbitrates who has access.