how to implement Ethernet with PIC, PIC18F97J60, PIC32MX(795F512L), ENC624J600, LAN8720A
As far as I know there are no 32-bit versions of the PIC18F97J60 chip. I believe Luminary Micro (now TI) did have one, but I am not sure if they are still available (I think I read somewhere they went EOL).

The ENC424J600/624J600 chips provide MAC+PHY in 1 chip, and communicate via SPI or parallel interface to any microcontroller. However you need to haul all of the frame data over this SPI/parallel interface. The SPI interface can only run at 20MHz or so, so the SRAM buffer will overflow at medium to high throughput. It's nice the chip can communicate on 100Mbps networks, but it cannot sustain that data rate.
To avoid this you could run the interface via parallel (that can transfer up to 80/160Mbps between MCU and Ethernet controller), but that will involve a dozen or more connections between the chips. 

The LAN9220 chip looks very similar to the ENC624J600, but only supports parallel.

I would suggest looking into the "MII/RMII Phy chips" if you can specify one of the higher-end PIC32MX6xx or 7xx series chips (or alternative ARM part). They include the MAC controller inside the microcontroller, with frame buffers allocated inside your MCU RAM. You only need a cheap external PHY chip, which basically translates the MAC data to compliant Ethernet signals. Best of all, RMII/MII is not exclusive to Microchip. Many ARM microcontrollers support RMII/MII ethernet interfaces as well.
The biggest advantage is that the major data movements are all handled by hardware or DMA. Once the software/ethernet stack is prompted about a new packet, it's already in the MCU RAM ready to be processed. This yields very decent/good throughput and the lowest latency of the bunch.

MII is basically two seperate 4-bit data busses running at 25MHz. You just tie them together to the MCU and off you go. RMII halves the 4-bit bus to 2-bit (less signals), but runs at 50MHz.