How do IC's know when there is a downward or upward transition of a clock pulse?
By comparing the signal in two points of time.

Given that real gates have a non-zero propagation time, this shows a simplification of such:







simulate this circuit &ndash; Schematic created using CircuitLab

At rest state, IN is low and hence the inverter output is high. This results in a low at OUT. When IN switches to high, the high reaches both the inverter and and gate within picoseconds of each other. The inverter is still outputting high at this time, so the and gate switches to outputting high. The propagation time of the inverter then elapses and its output switches low. This propagates to the and gate, which then switches low. This low-high-low transition at OUT indicates that we have detected a leading edge.