How to reason about this 'adder with memory' circuit?
This is from chapter 14, where it introduces the 8 bit ripple counter:

You'll notice that it refers to this circuit as a frequency divider. It then goes on to point out, via the timing diagram, that this makes up a sort of binary counter:
0000
0001
0010
0011

So, as a counter, it works!
But we can't use this counter with other logic blocks, because they can only sample the counter on the rising clock edge, as that's the point of a synchronising clock. However, if you only look at Q1-Q3 it works as a counter that is able to be sampled on the rising clock edge. I've made this timing diagram showing a &quot;real&quot; counter at the top and the not-clock line and how it varies all over the place.

The following bits of texts that follow this circuit then talk of it being ripple counter:


You'll see that the author then goes on to point out that synchronous counters are more sophisticated and all of the outputs change on the rising clock edge.
I would say that in Chapter 17: Automation, when the author starts talking about a 16-bit counter (now with a new CLR signal) that he's transparently started to use the term &quot;counter&quot; to mean &quot;synchronous&quot; counter that counts for each rising clock edge, rather than the original frequency divider/ripple counter.