Do chained I2C address translators also act as buffers?
No that will not buffer. Look at the block diagram on pg 6.



It is virtually a complete pass through for SCL/SDA with nothing to isolate and then repeat the signal for both lines nor both sides of each line. It does have the capability to isolate both lines, but definitely no capability to re-drive the signal. The only drive capability that exists is to pull the line low on SDA line only (in order to modify the address).

Interesting IC and the way it intercepts and middle-man-attacks the address.
When intercepting and modifying the address, N3 can always override any pull-up to change a HI to a LO, but in order to change a LO to a HI the pull-down drivers on the bus side (left-side) need to be taken out of the picture so that's where N2 comes in. It just completely disconnects the device-side SDA line from the bus so that N3 and the pull-ups on the device side have complete control over the device's SDA line. Then that XOR detects if the incoming address matches the address to be modified. Any address bit that matches gets modified accordingly by the AND gate and injected into the SDA, and any address bit that does not match is forced to zero by the AND gate. The result is either the  modified address gets put on the SDA line or some garbled nonsense address which is just be ignored by the device.