What is happening when I am adding a load capacitor in CMOS inverter?
When you add a capacitor, it charges via the pull-up PMOS to output a logic '1'. If the PMOS has a definite ON-Resistance, R and if the capacitance of the capacitor = C, RC time constant will decide the rise time while driving output '1'. That's why that slope is there. Similarly the capacitor discharges through through the pull-down NMOS to drive the output to logic '0'. The ON-Resistance of NMOS will decide the RC time constant this time, and hence the fall time to reach logic '0'. The dimensions of the transistors will decide its resistances. W/L ratio of PMOS to NMOS is kept 2.5 to achieve equal rise and fall times.