Byte-addressable RAM as opposed to word-addressable RAM
Most architectures that encounter this situation have two (or more) different instructions for accessing Bytes or Words. If you have a 16bit datapath (word size), that means the hardware outside the memory can accept/deliver 2 bytes in a single cycle. How the memory handles this is up to the memory. If you only have an 8-bit databus within the memory unit, then you will have to do one of the techniques you suggested (2 cycles, 2 register transfers, etc). 

However, I've never seen that in modern hardware because it's silly when cost and technology do not practically require it. As a historical note:   


  The very first PC processor - the 8088 from intel - was a 16-bit
  processor with an 8-bit memory bus. And there were 386's [32-bit data bus] with 16-bit [external memory]
  bus (386SX). -- TurboJ


Now, almost all practical hardware has memory (L1) width = processor width. The instructions will simply pick what to do with the mapping. Load word instruction = 1:1. Load byte = 2:1 (usually there is a range of instructions that determine what to do with the other byte in the datapath that isn't being loaded from memory).