Target  of concurrent assignment or output port connection should be a net type
When the target is assigned as a wire and not as a reg, then it works fine


When you say assigned I assume you mean changing (in the fft module):

reg [15:0] tr0;...,reg [15:0] tr31;
reg [15:0] ti0,...,reg [15:0] ti31;


to 

wire [15:0] tr0;...,wire [15:0] tr31;
wire [15:0] ti0,...,wire [15:0] ti31;


Which is the correct thing todo. The types reg, wire only apply in the current module and are not carried over port connections.

Remember the choice of wire or reg is for the simulator not indicative of the hardware. In SystemVerilog the majority of wire/reg can be replaced with logic. The only place this does not work is for tristate busses then you should use tri.