VHDL/FPGA Should I block down an array into arrays of dimensions with powers of 2?
I read your question as: should I (a) imply a 640 x 480 x 8-bit frame buffer RAM using an array and let the synthesis tool resolve it into Block RAMs; (b) directly instantiate Block RAMs to build the frame buffer RAM and have to yourself choose the bit-width or size of the Block RAMs to construct it.

First off, with FPGA RAM being so flexible in bit-width, you can choose a width that can be read and written conveniently and at good speed. A frame buffer is shared between at least two bus masters: the CPU/DMA/GPU that puts images into it and the display driver that reads pixels and sends them to the screen (I'll call them Draw and Display).

The more frequently each accesses the frame buffer, the less time each master gets overall. It makes sense to make the Draw interface at least as wide as the Draw's data bus. For the Display interface, the more bits it gets in one read, the more pixels it gets and the longer it can keep going on its own until it needs to read again. If Display gets 64 bits per read, it'll read eight times less often that if it gets 8 bits per read.

So your first calculations will start with Draw and what you're trying to display (if you're putting infrequently-changing text on display, you won't need such a super-fast interface as for games). If Draw has a 32-bit interface, you can consider Display with a 32-bit interface. Then, on the basis of one read per logic clock CLK, you can work out how many reads Display will need to read the frame buffer per, say, frame (or per line...or per 'n' CLKs...whatever seems relevant to you). You then know how many read/writes are available to Draw in that period. If it's not enough, consider making the RAM twice as many bits wide so Display needs to read half as often. (That may complicate the Draw interface to need read-modify-write for writes if the FPGA RAM doesn't support byte writes at that width, but one thing at a time). Calculate for that and if insufficient, consider four times as wide...and so on.

So all that was to get you to a point where you have your frame buffer arrangement..

To implement the frame buffer RAM in VHDL, I would personally create an entity called FRAME_BUFFER_RAM with an interface for Draw and another for Display. This keep the technology-specific part within that one design file, so if you change FPGAs, you only have one file to consider changing.

Within that entity, I would instantiate the Block RAMs directly because I would want direct control over how much RAM is used and in what arrangement. Block RAM is normally a precious thing and, not knowing what devices this might be put into in the future or what else they'll contain, I always keep it as little-used as possible.

Hope this helps and addresses the question you were asking.