Variable frequency for sine wave in Verilog
You never initialized clk_out, so the initial value is x.

Then you keep toggling clk_out, but since the simulator doesn't know the initial value, the value after toggling is still x.

You can resolve this by initializing clk_out, either in the declaration, in an initial block, or by defining a reset condition in the always block that controls it (which will work for synthesis but I'm not 100% sure it will work in simulation).

Also, I noticed another issue,


//At every positive edge of the clock, output a sine wave sample.
always@ (clk_out)



Your comment says you want to respond to positive edges, but your code says to respond to all edges. 

The code is probably not synthesizable.