Logism: Rising-Edge J-K flip-flop outputs 0 when J = 1 and K = 0
There is no contradiction. The behaviour of the simulator is correct. If you drive the inputs of flip-flop EXACTLY at the clock edge, then those values are not guaranteed to be sampled at that clock edge. It will be sampled only at the next clock edge. At least that's what I have observed in many of the logic simulators. You can confirm this if you see that the expected output for J=1, K=0, has indeed appeared in the next clock edge in your timing diagram (last column).
In real world, driving flip-flop inputs at the exact clock edge is a timing violation of setup/hold. You might want to delay the J, K inputs by small amount, say half clock cycle or so, so that the behaviour won't be confusing anymore in the timing diagram.