Effect of swapping positive and negative traces in a LVDS differential pair, for both clock lines and data lines?
For clock signal, swapping positive(+) and negative(-) at the receiver inputs leads to 180 degree phase shift. Depending on the signal transmission lines delays it may lead to improper data sampling, you may fix this by changing active edge of the clock signal (if it is possible with the system you work on), the situation may be worse when double data rate is used.

For data signal you are right, '1' will be received as '0' and vice versa.
Some SerDes'es, for example Xilinx GTY transceiver offers hardware mechanism for swapping bit values.


  If RXP and RXN differential traces are accidentally swapped on the PCB, the differential data
  received by the GTY transceiver RX are reversed. The GTY transceiver RX allows inversion to
  be done on parallel bytes in the PCS after the SIPO to offset reversed polarity on differential
  pair. Polarity control function uses the RXPOLARITY input, which is driven High from the
  interconnect logic interface to invert the polarity.


Source: UltraScale Architecture GTY Transceivers User Guide UG578 (v1.3) page 238, September 20, 2017