Voltage on Source Node
Let's consider the circuit at time t&lt;0. Here's the circuit and the current flow:



At time less than 0 the gate source voltage is +3V. Hence \$V_x\$ is at -3V. Therefore the drain-source voltage becomes 3--3=6V. The transistor then starts off in saturation and the current flows all the way to ground. Note that in saturation, we have \$I_D=k/2.(Vgs-0.7)^{2}\$. As capacitor discharges Vgs decreases further and further until it gets to 0.7V. At this time the mos is off and the capacitor has +0.7V across it. 

Now the supply makes a transition to +3V at time t=0. Therefore the voltage on the gate rises to 3V. Applying KVL, we get: -3V + 0.7 + Vx=0 or Vx=2.3V.