Discharging a capacitor with an analog switch
There is an absolute maximum of 100mA 10ms that you must not exceed.
I believe this is based on ampacity before fusing the xx nm CMOS junction by exceeding the current density.
\$E=0.5CV² = 0.5 * 0.1uF * (10V)² = 500uJ    \$
Although the discharge energy is much lower than ESD.
e.g. \$ESD = 1kV @ 100pF = 0.5 * 100pF * (1kV)² = 50 mJ\$
This is conducted in the ESD Diodes, not the CMOS junctions.
There is no good reason for exceeding ABS. MAX levels.

The wirebonds are a little more robust and use AW-29 or 29 μm wire.
Design Changes:

define specs. for better choices, you don't need 0.1uF
reduce your cap value by 1~2 orders of magnitude
reduce your signal input current (increase R) to maintain dV/dt by 1~2 orders of magnitude
reduce the input bias of your Op Amp selection by &gt;= 2 orders of magnitude or acceptable level
reduce your input offset to the acceptable level = TBD
never use ceramic caps unless C0G type ( memory effect is bad for S&amp;H and I&amp;D mode) instead use a film cap. ( any plastic)
measure logic dV/dt crosstalk between signal and logic input to minimize stray capacitance with 3mil gnd. guard tracks on either coplanar side of logic signal  or reduce slew rate.