ARM SWD Response On SAM D09
If I rewrite it horizontally I get:

             4 5         6         7         8         9
             8901234567890123456789012345678901234567890123456
host:  rrr...rrr  SARaaPpK                                
hi-z:                     t                                ???
trgt:                      AAA?????????????????????????????
swdio: 111...1110010100101x10111111001100100001111100001111xxx


Your whole transaction seems strange.

Three first bits shifted out by the target (62-64 in your trace) are Acknowledge bits. They should have only one bit set (either Ack, Wait or Fail). You get 101, which is not defined at all by SWD spec.

Then if low impedance really happens on bit 94, you have too few data phase bits. There should be 33 (32 data + 1 parity). You have only 30.

Some leads:


you may have some ringing on SWCLK line, and target interprets one rising edge as multiple (this would shorten the transaction like this),
you may be running this too fast (I would suggest to avoid running above 1MHz for enumeration).


In all cases, hook-up some logic analyser (or even better, a scope, to see Hi-Z) to understand what happens.