Verilog - Weird blocking/nonblocking problem
nextState should be combination logic (i.e. no clock). What it have infers a mux with a 2 stage flip flop. To correct your design remove nextState &lt;= State_IDLE; and replace always @(posedge clk) begin with always @(*) begin

The reason a non-blocking is delaying the state has to do with scheduling. Example:

a = 1;
b = a;
#1; // a is 1 and b is 1 (a is updated before assigning b)
a = 3;
b &lt;= a;
#1; // a is 3 and b is 3 (a is updated before sampling for b)
a &lt;= 4;
b &lt;= a;
#1; // a is 4 and b is 3 (a is NOT updated before sampling for b)
a &lt;= 5;
b = a;
#1; // a is 5 and b is 4 (a is NOT be updated before assigning b)