Should I use a buffer or a simple output with a signal?
I'd go with solution 1 and add an explicit flip-flop for the output.

The sole reason is, that using buffer ports is not recommended by some synthesis tools and in literature. If there is a real reason behind this, or if this has become cargo-cult programming - I don't know.

One upside of using a buffer instead of a dedicated signal is, that you save the signal. That is one less identifier to care about. In complex designs with lots of signals that makes your code easier to read and understand.

By the way, you can optimize your code a little bit:

if Clock'event and Clock = '1' then
    if Counter = 155 then
        Counter &lt;= 0;
        CurrentState &lt;= not CurrentState;
    else
        Counter &lt;= Counter + 1;
    end if;
end if;


Using a equal compare operator instead of a less/greater operator will likely use less FPGA resources because comparing for equal can be done with a hand full of inverters and a huge AND gate. This gets absorbed into a few FPGA lookup tables. Comparing two numbers for less or greater needs more resources like carry chains as it is basically a subtracter that is needed.