Data during AHB Busy state
The busy signal is part of the address bus and therefore relevant during the address phase, not of the data phase. 

Thus it is your first case where no data is written to address 0x02 which happens.  There is an example in the AMBA specification (I have rev 2.0 on page 3-10):



The busy cycle in T2 is ignored. Consequently the data in T3 is drawn as blank.