Can I use custom data types to exchange data between modules in VHDL?
To use a user defined type in a port declaration, you need to specify the type in a package and use that package in the context before the entity.

Utilities.vhdl

library ieee;
use     ieee.std_logic_1164.all;

package utilities is
  type MyRecordType is record
    x : std_logic_vector(2 downto 0);
    y : std_logic_vector(2 downto 0);
  end record;
end package;


Test.vhdl

library ieee;
use     ieee.std_logic_1164.all;

library myLib;
use     myLib.Utilities.all;

entity Test is
  port (
    clk    : in  std_logic;
    input  : in  MyRecordType;
    output : out std_logic
  );
end entity;


Top.vhdl

library ieee;
use     ieee.std_logic_1164.all;
use     ieee.numeric_std.all;

library myLib;
use     myLib.Utilities.all;

entity TOP is
end entity;

architecture SIM of TOP is
  constant period : time := 20 ns;

  signal clk      : std_logic;
  signal result   : std_logic;
  signal myRecord : MyRecordType;

begin
  dut : entity myLib.Test
    port map(
      clk    =&gt; clk,
      input  =&gt; myRecord,
      output =&gt; result
    );

end architecture;




Further hints:


Don't use package std_logic_unsigned, use numeric_std instead.
Declaring the some type twice create two independent and incompatible types. VHDL is here more strict than C, because type equality is not based on structure, it's based on names. When you define a type twice, the fully qualified name of both types is different, thus you have incompatible types.
You can omit component declarations and spare lot's of doubled code, when using direct entity instantiations.
If you want to initialize myRecord at the beginning of the simulation, then initialize it when you declare the signal. Using myRecord.x &lt;= "000"; has a delay of one delta cycle!
This expression will not work: result = 0, because result is no integer, you need to compare with '0'.
You shouldn't wait for 20 ns;. Use wait for period;.