Op- amp input stray capacitance?
The need to reduce the C_virtual_ground (Vin-) capacitance depends on the total phaseshift of the feedback circuit. For low values of resistance, the capacitance can be huge and the circuit still has no peaking. For high values of resistance (in the simulation below, I used gain of 10x, with 1Meg input R and 10Meg feedback R), the C_virtground and the phaseshift of Cload and Rout, and the opamp's phase_margin, all contribute to peaking.

When these 3 causes of phaseshift sum to near 90 degrees, expect massive peaking.

Again ---- low values of Rfb make everything operate without peaking,

And many circuits that should peak ---- do not --- because of stray capacitance (stray electric field coupling) across the two PCB pads of the Rfeedback resistor. Notice the SMT resistors likely have much more of this
lead-lead coupling than will axial feedback resistors. Thus the SAME opamp, using the SAME value of resistors, will have the PEAKING determined by the choice of resistor package: SMT or axial.

In addition to resistor values and parasitic C across the resistor PCB SMT pads, the opamp's differential_mode Cin (Miller Effect can be a killer) will matter. And as you already know about, the VirtualGround node (Vin-) capacitance.

Here is a 45MHz opamp (MCP655) modeled with 3pF on the virtualground node, Rin of 1,000,001 ohm and Rfb of 10 Million Ohms.

Notice the 20dB peaking at 500,000Hz. And notice NO parasitic C across Rfb.



Your opamp will have finite phase margin, often included in the datasheet. This, the phase margin, is characterized (tho not likely being production tested) at Unity Gain Bandwidth. If you have gain of 10X, then divide that by 10; if you have gain of 100X, then divide by 100; this works because for small angles (in radians), the angle is approx. tangent(angle) is approx. sin(angle). Thus if you have 45 degrees phase margin, and you have gain of 10, then the opamp contributes another 4.5 degrees phase shift (assuming ONE POLE is contributing that excess phase shift inside the opamp).

Your opamp is also driving some load capacitance. Assume that is 10pF in series with Zout of the opamp. In this simulation, I included NO Cload. The opamp's output ESD diodes will provide 1pf or 2pF, if not more. Thus some cload is always there.

I would explore the inclusion of 0.1pF or 0.5pF across 10Meg Rfb. Some is inevitable; model it.