How does Pass Transistor Logic work?
A PMOS passes a perfect 1, but a degraded 0.

An NMOS passes a perfect 0, but a degraded 1.

This comes because in pass transistor logic the source and drain nodes are not fixed.  The source and drain switch whenever the transistor is either charging or discharging the load capacitance.  

So, when the NMOS is charging up the load capacitance, the source is the input signal and the drain is the output signal.  In this situation the drain cannot charge up past Vgs - Vth because at that point the transistor turns off (Vgs is not greater than Vth).

But, whenever the NMOS is discharging the load capacitance, the source is the load and the drain is the input (which is at ground).  In this case the Vgs is always greater than Vth (since the input is at ground).  And the cap discharges all the way to 0V.

PMOS work in a similar way, but opposite of the NMOS (passing a solid '1' but a degraded '0').

For this reason PMOS and NMOS are combined into "transmission gates" which pass both a solid '0' and '1' (the selects are inverted).