ADC voltage divider calculation
What you're describing is a passive attenuation circuit as a stage prior to your ADC, probably because you expect there to be some voltage exceeding the accepted range of the ADC and you want to either (1) protect it from damage, or (2) scale the data so that you can still perform ADC measurements on large voltages.

For aim (1), this is not sufficient. It is very important that you have TVS (transient voltage suppression) and/or over-voltage zener protection on every input line to your system. If it is a 5V-tolerant input at the MCU, you can connect every input line after your 10k resistor bank to a Shottky diode, each connected to 5V. This is what I consider a bare minimum for circuit protection.

For (2) (scaling your data), it seems you have two attenuation modes - the first, where you have a 20k/10k divider scaling to an equivalent 66%, and the second where you have a (20k||1k)/10k divider scaling to an equivalent 8.7%.

In the first mode, your maximum input voltage would be 7.5V. In the second mode, your maximum input voltage would be 57.5V.

You probably also want to consider stability - get some idea of how fast you expect your input to vary, and then add stabilization capacitors to all of your inputs, likely across your 20k resistors, to filter out noise.