(Basic) BGA Multi-layer stack-up/PCB layout question
In these images, everything that's not black is something - either a via drill, a copper trace or pour, or a silkscreen mark.  Unfortunately, it seems that the via drills are not displayed in all of the images - namely the power layer - which makes it a bit confusing.  The two dark green circles near the center of the chip on the ground layer are two vias connecting to the ground plane.  All of the interconnected black circles are clearances between the plane and other signal and power vias that do not connect to the ground plane.  

This particular chip requires one ground and two power supplies, vcccore and vccio.  Layer 5 gives the best picture of the vias.  Mentally scoot this over on top of the power planes and then you can see which pins are connected to the planes and which ones pass through holes in the planes.  For example, the group of vias in the lower left corner on layer 5, two of them are connected to vcccore.  They also appear to be connected to bypass capacitors on layer 6.  For the little group in the center, two pins go to ground, two to vccore, one to vccio, and one is a signal pin of some sort that's routed out on layer 2.  I'm sure this would make more sense if you could play around with the layout in the CAD software instead of just looking at some pictures.  

Planes are nice because they can act as isolation between the signal layers.  Interestingly, it doesn't matter if a plane is power or ground, they both provide the same isolation properties.  Large power and ground planes placed close together also provide a small amount of high frequency decoupling.  Planes also have lower impedance than traces and as such don't require as much bypassing while also being able to carry quite large currents, which can be required for large ASICs and FPGAs where core supply currents can be 10A or more per chip.  

Here is a picture of another BGA footprint with several different copper pours and more obvious vias:



Image source: http://techdocs.altium.com/display/ADOH/Unused+Pad+Shape+Removal

Many of the vias in that image do not have pads as they are not connected on that particular layer.  This provides more clearance for the copper pour to go between the padless holes.  

Here is a screenshot of the same PDF file with the vias highlighted in white on all layers:



From this picture, you can plainly see that two vias connect to ground, two connect to vccio, and 4 connect to vccore.  You can also see that the two vias that connect to GND pass directly through the vccore and vccio planes without connecting.  No blind or buried vias are used here, the vias pass through all 6 layers, all the way from layer 1 on the top of the board to layer 6 on the bottom of the board.  You can also see the ground vias that connect the bypass caps on layer 6 to the ground plane, though I did not highlight these vias.  

I do note that it is very strange that the chip has 6 power pins but only 2 ground pins.  Generally chips (especially in BGA packages) will have at least as many ground pins as power pins.