Resetting reset to zero after one clock cycle in verilog
I'm guessing you are trying to do something like below. Note the #1 for guarding against the negedge Clock from x to 0 at time 0.

initial begin
  Clock = 1'b0;
  forever begin
    #20 Clock = ~Clock;
  end
end

initial begin
  Start = 1'b1;
  #1; // little delay so x-&gt;0 transition does not trigger negedge Clock
  @(negedge Clock);
  Start = 1'b0;
  // @(negedge Start); // not needed as we know Start fell
  X = 3'd5;
end