Clock Divider in VHDL Code
This will &quot;work&quot; in simulation, for a bad definition of &quot;to work&quot;.
Assuming a normal clock, this are the process invocations:

Clock rises, if(rising_edge(clock_in)) is taken, you increment Count
Clock falls, the elsif is checked, if you reached the limit on the previous rising edge, you will toggle Temp and then update the out clock.

As you can see, you rely on the sensitivity list for logic, that's never a good idea. Both because it's more obscure code and because it likely won't do what you want post-synthesis, where most toolchains just ignore sensitivity lists alltogether (as they should).
A cleaner solution for a clock divider would be:
p_clock_div : process(clk_in)
  variable r_count : integer range 0 to c_count_max := c_count_max;
  variable r_clk_out_i : std_logic := '0';
begin
  if rising_edge(clk_in) then
    r_count := r_count - 1;
    if r_count = 0 then
      r_clk_out_i := not r_clk_out_i;
      r_count := c_count_max;
    end if;
  end if;
  clk_out &lt;= r_clk_out_i;
end process;

Or, if you want that falling edge update, then show so in your code:
p_clock_div : process(clk_in)
  variable r_count : integer range 0 to c_count_max := c_count_max;
  variable r_clk_out_i : std_logic := '0';
begin
  if rising_edge(clk_in) then
    r_count := r_count - 1;
  elsif falling_edge(clk_in) then
    if r_count = 0 then
      r_clk_out_i := not r_clk_out_i;
      r_count := c_count_max;
    end if;
  end if;
  clk_out &lt;= r_clk_out_i;
end process;

Note that some (mainly ASIC targetting) synthesizers don't like the clock_out &lt;= r_clock_out_i line to be outside the if tree.
Also note that clock_out has an undefined startup state and this whole block would be cleaner if you had a clk_in-synchronized reset input signal.