Verilog - instantiation input port not connected in top level design but design is working?
Two things:


Are you sure that this original Verilog module design is finished, and expected to work properly?
If input of the module is not connected, it may be tied to specific logical level by the compiler, and all circuits related to it are removed during optimization.


Simulation expects you to define all the input signals; thus if there's any 'X' in the equation resulting signal will be 'X'. Try forcing this latch_clk as 0, and watch the result.

Update:


  I looked at all messages. But please tell me what will the code (latch_clk or tc_data) in the sensitivity list do? Can I not type (latch_clk, tc_data) . Is the OR in this case really nessecary?


If they change their state, circuit is "activated". Why OR is there, and why latch_clk takes place please ask developer of the code. As I said if compiler sees some signal defaulted to some value, compiler just removes this signal substituting a constant instead, thus you get 0 or tc_data (with 0 never triggering), thus it is just optimized to tc_data, and if(~latch_clk) being if(~0) or if(1) thus having it always true.