How to detect the rising edge of a pulse that is not in sync with the clock
Here is the way it works. If you have a pulse, assuming voltages are OK, it will be detected at clock N if it meets the setup and hold time for clock N. If it is too late to be detected at clock N, it will be detected at clock N+1. If the timing is marginal, it may be detected either at clock N or clock N+1, there is no way to know ahead of time.

Please note that there is a minimum detectable pulse width. If the pulse is too narrow, it may not be detected at all. Generally, "too narrow" means less than one sample clock period (but you need to work it through with the setup and hold time specifications to fully understand the minimum pulse width). So if the minimum pulse is less than one clock cycle, then there is the possibility of missing a pulse. Welcome to the joys of asynchronous design.

Depending on what you are interested in, there are all kinds of things you could do. You could have the pulse enable an analog integrator so that pulses can be counted in an analog way, then occasionally sample and reset the integrator to avoid overflow.

If pulse timing is what you are most interested in, you can start an integrator on the pulse rising edge, then sample the analog voltage output of the integrator with an ADC synchronous to the digital sampling. Then you convert the ADC voltage to elapsed time. This will allow you to figure out the time of the pulse with sub clock accuracy and precision.

Have fun!