Are present state and next state equal between two clocks?
In a topology like this, the present state is read from memory and passed through combinational logic to compute a new state. Until the clock ticks, that new state is sitting at the write port of the memory waiting to be written. As soon as the clock ticks, the new state is written to the memory, and for a brief instant the present state and next state are equal. This brief instant is the propagation delay of the memory (time from clock edge to availability on read port) plus the propagation delay of the combinational logic. After this time, the NEW new state is sitting at the output waiting to be written, and the cycle continues.