VHDL - Flip Flop inferring on a signal
Remove the carry from the process (it's declaration is also unneeded unless accarreo is read in another process or concurrent statement ):

architecture Comportamiento of ej11 is

    signal aux  :   unsigned (N-1 downto 0);
    -- signal acarreo : std_logic;

begin
    Cuenta:
    process (clk_i, nmr_i)
    begin
        if nmr_i='0' then
            aux &lt;= (others =&gt; '0');
            -- acarreo &lt;= '0';
        elsif rising_edge (clk_i) then
            if e_i = '1' then
                if aux &lt; M-1 then
                    aux &lt;= aux + 1;
                else
                    aux &lt;= (others =&gt; '0');
                end if;

                -- if aux = M-2 then
                --    acarreo &lt;= '1';
                -- else
                --    acarreo &lt;= '0';
                -- end if;
            end if;
        end if;
    end process Cuenta;
    q_o &lt;= std_logic_vector (aux);
    -- a_o &lt;= acarreo;
end architecture Comportamiento;


Either add a concurrent assignment or a new process with an assignment to a_o (conditional concurrent assignment shown):

    a_o &lt;= '1' when aux = M-2 else
           '0';


Including the assignment to accareo inside the if statement is inferring sequential logic inferred the flip flop.

A process would look something like:

Acarreo:
    process (aux)
    begin
        if aux = M-2 then
            a_o &lt;= '1';
        else
            a_o &lt;= '0';
        end if;
    end process Acarreo;