Design a 3-Bit Up Synchronous Counter Using JK Flip Flop (odd vs even numbers)
You are assuming that the even counter "wakes up" in the 000 state and the odd counter wakes up in the 001 state. Those assumptions are not valid, so some of the don't care values in your state table should actually be 0 or 1.

Other than that, take a look at the columns for the Q values in each counter. If the Q values have a similar behavior you would expect the logic design to be similar as well.