How do you choose the exact width for PMOS/NMOS in your design?
I think it depend on the target rise time, fall rime, power, Cload. 


Begin with min W and min length of NMOS and make PMOS 2-3+ times of that.
Simulation with your cap. load


--> RESULT: rise time, fall time, power --> Match your target  or not? After that, you can make decision for design with some of changing of device size.


Sometime, logical effort method will help you make decision how many stages of your circuit. But this method will take time for calculation.


Example: 


Block function --> connect cap. load.
Block function --> inverter 1x --> cap. Load
Block function --> inverter 1x ---> inverter 2x --> cap. Load. 


Hope it help you.