4 port 12 bit mux is consuming 48 macrocells!
Instead of implementing the mux as a gate-level logic, which may confuse the synthesizer, try to use some behavioral or RTL description, that will allow the synthesizer to choose the way to implement it optimally.  I am pretty sure the device has some built-in macrocells for implementing such a mux in minimal resources, that you are not aware of, but the software is. For example you can use the following code to infer the 12 bit 4-to-1 MUX:

module muxing( selecting, d1,d2,d3,d4, q );

input[1:0] selecting;
input[11:0] d1;
input[11:0] d2;
input[11:0] d3;
input[11:0] d4;
output[11:0] q;

wire [11:0] d[3:0];

assign d[0] = d1;
assign d[1] = d2;
assign d[2] = d3;
assign d[3] = d4;

assign q = d[selecting];

endmodule


As a side note - both implementations, the given in the question, and the proposed one resulted in 12 macrocells usage when tested on my machine (Xilinx ISE 14.1).