Dual edge triggered D flip flip CMOS implementation. Less than 20 transistor
If I wanted to implement this on 0.35 um I'd just copy the W/L as they are in the paper and try to get it to work in the simulator.

The W of 4 or 8 um is most likely chosen to make the W = 8 twice as strong as the W = 4. The L = 2.6 devices must be weaker even than the 4/1.6 devices.

Normally I would expect PFETs to have 2 to 3 times the width of it's counterpart NFET, this is to compensate for the weaker PFETs. PFETs are always weaker because hole mobility is less than electron mobility. I do not see that 2 to 3 ratio here which I find odd.

Maybe to get the circuit working the PFETs need to have their W increased a factor 2 to 3.

Once the circuit is working I'd try to scale it down to minimum size L and W but keeping the W/L ratios.

You could take one huge step and scale everything down in one go but my experience tells me that most often this results in a design that doesn't work so you will have to get back to the original anyway and take small steps. So I do that right from the start ;-) and use the simulator a lot of course.

A quick search reveals that you need at least 20 transistors for this function so I think it doesn't get simpler than this.