Can we connect both ASIC and an FPGA both to the same physical output Ethernet ports at the same time?
There are ways to do this, but you'd quickly end up fiddling with tristate buffers and the like. Just putting the wires together will create multiple drivers on lines and blow up pins in no time.

A nicer solution would be to route the ASIC output through the FPGA and implement both the block that you would have in the FPGA and the arbiter there. Then the FPGA has the only output towards the Ethernet. Assuming your arbiter is already synthesizable, this is a small change in code. This probably requires some redesign of the rest of your project, though, so consider other solutions.