Still confused about SPI implementation FIFO to buffer
The implementation details aren't provided because they are not visible to the user and thus do not matter to the user.  To hazard a guess, the transfer is probably done in parallel.
As each bit is shifted out of the shift register and transmitted a bit is read and pushed onto the opposite end of the register.  Once 8, 16, or 32 bits have been written and read the user is notified and another word of data can be written/read.