Why is the timing diagram of combined SAR ADC more efficient?
This is a &quot;ping pong&quot; configuration, or a degenerate 2-instance case of &quot;round robin&quot; where the ADC's take turns.
Each ADC takes two sample periods to produce a result.

As I see it we should give &quot;N+1&quot; to SAR1 and &quot;N&quot; to SAR2 simultaneously

Samples N and N+1 are not available at the same point in time, but rather in successive sample periods.
So you start each conversion at the sample period in which the input becomes available, and you get each result two periods later.  The two chips toggle between their two modes out of phase, so you always have one sampling and other other searching.  Each clock period ends with one ADC producing a new result, and the other only halfway to having one.
To actually run the two converters in lockstep toggling phases together rather than in opposition, you'd need some sort of analog delay for the earlier sample period input of one side, so that it could be sampled a period later with the second.  That would add complexity, and error, and wouldn't really make any sense, since then the system would produce two results every two clock cycles, instead of one result ever clock cycle that merely happens to be delayed by two clock cycles.

Incidentally, this is typically what today's bench scopes do, only with flash ADC's.  They'll have say four chips, which engage in a four way round robin producing a sample at four times the rate any given ADC could, with the data stream recombined by an FPGA or ASIC that then compensates for chip-to-chip differences.  Switch to dual channel mode, and you have two ping pong modes and half the sample rate.  Switch to four channel mode and each ADC takes a single input at its own sample rate only.