How to remove this warning in Verilog?
If you know that you don't need the signals, ignore the warning. But why would you declare a 9 bit bus whilst only needing one signal? That's bad practice.

Generally about such warning:

You should definitely worry about it!

This warning means that you're not using signals that you've declared so synthesis -- being the clever thing that it is -- optimised those away. This usually suggests that there's something logically wrong in your implementation and that your output will not be what you intend it to be.

Only ignore warnings that you fully understand.

Finally, don't switch off that warning type as you will not see it when it actually matters!