Debugging simulation error in Xlinx for VHDL
Without resorting to what Xilinx is reporting in their GUI, your VHDL code is not valid.  "Half-Subtractor" is not a valid entity name:

token_test
Half-Subtractor
00001 IDENTIFIER_TOKEN        (128) Half
00001 DELIM_MINUS             ( 14) -
00001 IDENTIFIER_TOKEN        (128) Subtractor

An identifier in this context is a basic identifier:

basic_identifier ::=
letter { [ underline ] letter_or_digit }


And a minus sign delimiter is not allowed.

Your entity name  comprised of two identifiers separated by a delimiter.  Running into the minus sign token then another identifier before the reserved word is will guarantee it won't analyze, it will fail in the entity declaration:

 entity_declaration ::=
      entity identifier is
          entity_header
          entity_declarative_part
  [   begin
          entity_statement_part ]
      end [ entity ] [ entity_simple_name ] ;


Where entity_simple names should be read as entity_simple_name, a predicate tested simple_name for the entity that must match the declared name.

If it doesn't analyze it doesn't show up.  If it didn't analyze that should show up somewhere as an error, and that it isn't bound could get reported as well.

Change from:

entity half-subtractor is
end entity;


Which get's an analysis error along the lines of:

ghdl -a half-substractor.vhdl
half-substractor.vhdl:2:12: missing "is" after identifier
half-substractor.vhdl:2:12: (found: -)

telling you the syntax is non-conforming, to something conforming to the VHDL standard:

entity half_subtractor is
end entity;


and:

ghdl -a half-substractor.vhdl

(Analyzes without error).

Your view of what is happening here appears to be obscured by all the visual noise provided by the GUI.  Somewhere Xilinx's tools should be telling you your VHDL is syntax deficient besides not showing up as elaborated in some little window pane.