DDR4 column width v/s burst size
The column width is the size of the Data Bus on the DRAM chip. 
Ex. reading from row 1, column 1 returns 'column width' bits. On DDR4 column width is 64 bits and the row size is 64 Kbits meaning that the row buffer contains 64 Kbits. 

A cache line is typically 64 Bytes and not 64 bits. A burst size of 8 means that 8 data words are transmitted. 

8 data words x 64 bits = 64 Bytes 

that is the cache line size.