Why do some microcontrollers have such huge synchronization delays?
That's a different way of doing things to me, I'm used to my architectures where my registers are either on my CPU clock or at least 1/2 of that clock.  So you write your registers and they're ready right away.   Perhaps they're doing it this way for power savings?  If they're putting peripheral registers in their own separate really slow clock domain maybe they don't have to wake up and run the main oscillator or CPU clock but can keep updating values on the peripheral.

If that's the case then you could write a register in your super slow peripheral block, then disable the power island for the whole CPU or clock gate it, and let the slow synchronizer read it until it's happy and then interrupt the CPU to bring it out of sleep.

Alternatively it could let you cram the maximum amount of instructions into your awake time, instead of spinning six cycles and waiting for every write.

As to why they use so many synchronization cycles, could be paranoia, or they could be meeting some high reliability standard for one of their customers.  I can't say for sure but I know I've seen customers with demands like every ram shall have ecc and be preloaded to a set value, etc.

I guess that's not a definitive answer but those are my thoughts after looking through the datasheet a bit.