Hold-time Violation and timing diagrams
There are a few possibilities but can never predict with so much certainty as to be able to provide a reproducible scope shot. You see there are factors that influence the outcome of such event at the flip flop which include:


Rise time of the clock signal
How much the hold time is violated
Noise in the signal lines to the flip-flop
Noise level on the ground bus
Noise on the Vdd/Vcc bus
Loading in the flip-flop output
Chip type of the flip-flop
Stray circuit capacitance
Circuit characteristics change when poking a scope probe to monitor the behavior


The flip flop output may exhibit one of these behaviors


The output may start to change state but then return to the pre-clock level
The output may change state normally even in the event of a spec violation
The output may go to some state where the voltage level goes to value part way between the Vdd and GND and stay there for a good amount of a clock cycle
The output may not change at all at the violation clock edge but then pickup the valid output level at the next clock edge.