ALU using Component and Process
You're missing some sensitivity elements on the RegIn process (LE, Input), the RegOut process (OC, INPUT_OUTPUT) and the ALU process (TEMP_3_OC, TEMP_1_OUT, TEMP_2_OUT).

Once you have fixed the sensitivity list elements your ALU works for the available operation ("01", C &lt;= A + B ).



The test bench I used:

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end entity;

architecture test of tb is
    component ALU is
        Port (
            TEMP_1_LE: IN STD_LOGIC;
            TEMP_2_LE: IN STD_LOGIC;
            TEMP_3_LE: IN STD_LOGIC;
            TEMP_3_OC: IN STD_LOGIC;

            TEMP_1_IN: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
            TEMP_2_IN: IN STD_LOGIC_VECTOR (7 DOWNTO 0);

            C: IN STD_LOGIC_VECTOR (1 DOWNTO 0);

            CF: OUT STD_LOGIC;
            ZF: OUT STD_LOGIC;
            SF: OUT STD_LOGIC;

            TEMP_3_OUT: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
    end component;
    signal LEA:         std_logic := '1';
    signal LEB:         std_logic := '1';
    signal LEC:         std_logic := '1';
    signal OUTENAB:     std_logic := '0';
    signal A:           std_logic_vector(7 downto 0) :=X"21";
    signal B:           std_logic_vector(7 downto 0) :=X"21";
    signal OP:           std_logic_vector(1 downto 0) := "01" ;
    signal CF:          std_logic;
    signal ZF:          std_logic;
    signal SF:          std_logic;
    signal C:           std_logic_vector(7 downto 0) ;
begin
DUT: alu port map (
            LEA,
            LEB,
            LEC,
            OUTENAB,
            A,
            B,
            OP,
            CF,
            ZF,
            SF,
            C);
STIMULUS:
    process
    begin
        wait for 20 ns;
        OUTENAB &lt;= '1';
        wait for 20 ns;
        wait;
    end process;

end architecture;


For it's limited simulation, the only sensitivity list requiring patching was for RegIn.