variable should not be used in output port connection
Even if the c output of bottom1 is produced by a flip-flop, in top_ver you are not assigning intsig in a procedural block (an always or initial block).

Therefore you must declare intsig as a wire rather than a reg.

Regardless of whether the signal is actually produced by a flip-flop or combinatorial logic, in Verilog you declare a signal as reg when you will assign to it in a procedural block (again, always or initial) and you declare it as wire (or one of the variants like wor or wand) when you are going to assign to it in a combinatorial statement (assign or as the output of an instantiated module).