Is there any 8080 Series Parallel Interface standard?
In this case it means seperate RD_ (read) and WR_ (write) lines rather than an E (enable) and R/W_ (read high, write low) line. Both RD_ and WR_ are active low. See page 10 of ST's AN2790. And CS_ is chip select, active low.

For clocking, CS_ or WR_ rising, whichever comes first, is the end of the write. For read either CS_ or RD_ rising tri-states the bus.