Metastability Deserialization and clock crossing domain
You say that TXCLK and INCLK both come from the ADC, so they shouldn't be asynchronous with respect to each other. They should be derived from a common internal source, which means they really belong to the same clock domain, and there's no reason to expect any issues with metastability. See whether the ADC datasheet (which you haven't provided) confirms this.

You do need to be careful not to introduce excessive skew between the two clocks, either in the PCB wiring between the two devices, or inside the FPGA.