Register file in Verilog, How to make it so reads only happen on negedge
Reading from a register is inherently asynchronous. I think what you really want is for rdDataA and rdDataB to be updated only at a falling clock edge. To accomplish this, just put their assignments inside an always @(negedge clk) block and use non-blocking assignments instead of the concurrent assign statement.

always @(negedge clk) begin
    rdDataA &lt;= regfile[rdAddrA];
    rdDataB &lt;= regfile[rdAddrB];
end