BPSK modulator with DDS on FPGA
1) The reference clock can go as fast or as slow as you like.  Most FPGAs have built-in PLLs that can convert an external reference clock into whatever frequency you need (within reason).  So you could take an external 10 MHz reference and multiply it up to 100, 150, 200 MHz, etc.  

2) No, FPGAs do not contain DACs.  It may be possible to build an R-2R DAC, but if you want to run at a high sample rate, then it may be advisable to use a high performance external DAC with a wide parallel or even high speed serial interface (not SPI, high speed as in >1 Gbps per lane).  Obviously a DAC will need a sample clock, and generating this in the FPGA is certainly possible.  If you use a DDR flip flop to generate the clock, then it should exactly match the samples that get clocked out in parallel. 

3) Adding a phase offset after the phase accumulator is simple - just add an adder between the two and add the offset you need each cycle.  

As far as a LUT is concerned, that symmetry is only one thing that you can exploit.  If you are OK with using a couple of DSP slices (multipliers), it is possible to compress a very large (18 bit phase, 16 bit amplitude) equivalent table into 3 small LUTs (~512 entries).  This uses the trig identity sin(A+B) = sin(A) + cos(A)*sin(B) to reconstruct the sine wave at high resolution. See https://github.com/alexforencich/verilog-dsp/blob/master/rtl/sine_dds_lut.vfor an example.  The LUT values only have to be calculated for the required bit depth, you select what frequency you want with the frequency control word.  

4) It is possible, but it is not generally very efficient.  FPGAs are mostly optimized for fast fixed point and integer math.  There are a few which support hardware floating point, but these are relatively rare.