Compensating for unbalanced via count in DDR3 routing
The big advantage of DDR3 over DDR2 is that it allows the address/ctrl bus to use fly-by topology instead of balanced T.
Fly-by is the recommended and easiest topology for DDR3.
Balanced T is still possible for DDR3, but it is discouraged.

Write leveling and read leveling should indeed be able to handle your mismatched delays. That is not the problem here. You problem will instead be mismatched reflections, which will affect your signal integrity.

I recommend you solve the problem by switching to fly-by topology. It is explained a bit here:
https://www.youtube.com/watch?v=7sxBBvF12JY