Confusion regarding Timing Diagram of 8085 microprocessor
When do the transistions actually occur? 


Roughly where they're shown on the diagram.  But that's just to give you a general idea -- if you want to know where they actually occur, get your hands on a board and look with an oscilloscope.


  I mean do the various registers used in 8085 are edge-triggered or level-triggered? 


That is immaterial, unless you're designing an 8085.  At the beginning of a sequence the part is in one state, and the end it is in another.  As long as the way that it transitions is known, whether individual parts are edge- or level-triggered does not matter.


  Say, for example, The address value stored in Program Counter is passed on to the address bus but when? At the falling edge , rising edge or level triggered??


The address value stored in the program counter is passed to the address bus at exactly the times shown, with the complication that the low byte is multiplexed with the data bus.  So as the diagram shows, the low byte of the program counter is present on address/data bus when ALE is high, and continues valid long enough to latch it as ALE goes low.


  Why do we make read signal low for two clock cycles? Why not one?


Because the part is designed to give slow memory as much time as it can to respond.  The processor needs time to respond anyway, so why make the signal lower for less time than it needs to be?  That would just demand more expensive memory to do the same job at the same speed.