What is affected by DC/DC converter frequency selection?
The choice of frequency is usually constrained by 4 primary factors:

1 Inductor size (as you mentioned). A higher frequency requires a smaller inductor with lower copper (\$I^2 R\$) losses as there are fewer windings for a smaller inductance with equivalent saturation current.

2 Higher frequency operation increases switching losses in the switching FET. In synchronous buck converters we usually choose the switching FET for lowest total gate charge and the sync FET for lowest \$R_{DS(ON)}\$.

3 Compensation. This can be a bit more challenging with a higher loop cutoff but is often worth it as the output error response time will be faster which can make ripple easier to deal with.

4 Switch minimum on time; at higher frequencies this may be more difficult to meet the datasheet parameters. You can read an excellent application note from TI on this subject.

Those are the primary issues that require a compromise as they have competing interests. Whether there will be higher EMI or not is very device and layout dependent.