Timing inside a shift register
You are correct in your gut feeling that there is a potential problem. Within a chip, the chip designer chaps have taken care of it. When you connect a chain of let's say 74x595's you can indeed run into trouble, especially with a long chain, a weak driver, and clock wiring that starts at the 'first' chip (the one that receives the data). A 'standard' solution is to feed the clock starting at the last chip.

A better solution is to use a chip like the CD4094 that has a delayed output. It has an extra flipflop, that is clocked on the opposite edge. Using this output to feed the nect SR eliminates all setup/hold problems (but it does reduce the maximum clock frequency).

I think you can achieve the same effect (sort of poor man's implementation of the delayed output) by clocking the even 595's with the plain clock, and the odd 595's with the inverted clock. But I never really worked this out.