Class D amplifier - Offset voltage
You are trying to get zero out for zero in by dead-reckoning.

Any imbalance anywhere will give rise to a DC offset. Although all the components in the two sides are nominally the same, you cannot assume exact matching.

You use seperate comparators for the H and L FETs, which will have different offsets and speeds, level translators with different speeds, the high and low channel in the 2110 driver will be different, two physically different FETs, and a power supply that may or may not be balanced accurately. The elephant in the matching of course is the high/lowside driver, that uses a bootstrap high voltage supply, and two FETs of the same polarity to do a job that should (for balance) use opposite polarity FETS.

It is a wonder that you get as close to zero offset as you do. 

Do not change the output topology to filter the FETs separately, keep the single inductor from the FET junction as you have it.

If you need a zero output offset, then it may be worth closing a low frequency filtered DC correction loop around the whole amplifier.