Trouble Understanding Bitstream Frame Addressing
What I do not understand is how the address we see in blue in the above image relates to the frame address. The Xilinx Documentation (XAPP452) provides tons of information about the structure of the frame address but where is it actually used?


Note that the document you're referencing is for Spartan-3 devices, not Spartan-3E. The overall bitstream format is identical, but some of the details of the registers may differ a bit.

Anyways, though -- there's no relation. The address in blue is an offset within the bitstream, which isn't used by the target device at all. A write to the frame address register does appear in the part of the bitstream you included in your question, but (spoilers!) it's just zero.

Keep in mind that a Xilinx bitstream (or, at least, this type of Xilinx bitstream) fundamentally consists of a series of write operations performed on various device registers. The frame address register is one of these registers; it sets the physical location in the device where data written to the FDRI register will go. Since most uncompressed bitstreams will write to the whole device, they start with a FAR of zero, and let it increment automatically as they write to FDRI.

A disassembly of certain "interesting" commands in your screenshot follows:

00000000: ff ff ff ff    &lt;-- standard synchronization header
          aa 99 55 66

00000008: 30 00 80 01    &lt;-- write 1 word to register 04 (CMD)
0000000c: 00 00 00 07    &lt;-- value - 07 = probably RCRC (reset CRC)

…

00000020: 30 01 c0 01    &lt;-- write 1 word to register 0e (IDCODE)
00000024: 01 c1 00 93    &lt;-- value - 01C10093 = XC3S100E

…

00000038: 30 00 20 01    &lt;-- write 1 word to register 01 (FAR)
0000003c: 00 00 00 00    &lt;-- value - it's just zero

…

00000048: 30 00 40 00    &lt;-- write 0 words to register 02 (FDRI)
                             this is actually just setup for
                             the next instruction...
0000004c: 50 00 46 a1    &lt;-- write 18,081 words to that register


All of the data following that write is the data written to FDRI. Your bitstream is uncompressed, so every part of the FPGA will be represented in that following blob of data. Enabling bitstream compression will make bitgen compress long runs of zeroes using multiple-frame writes. This may actually be a little easier to analyze; I'd recommend you try that.