Why do DRAMs retain their state better when they are cold (when powered off)?
It's basically because the leakage current of a transistor in a DRAM cell is temperature dependent. Here's a typical DRAM cell schematic (taken from that book):



And here's a generic graph of how the leakage current varies with temperature for IC-level FETs



The latter graph is from another book. This is in fact an exponential dependence on temperature (note the semilog plot), well-approximated simply by using the Shockley diode model. The book says that "a common rule of thumb is that leakage current doubles for every 10C increase in temperature".