VHDL subtype constrained by specific values (not range)
I dig into the norme of the VHDL 1076-2008 : http://www.fis.agh.edu.pl/~skoczen/hdl/ieee_std/ieee1076-2008.pdf
It is not possible in VHDL 2008 (and prior to this standard) to do whay you would like: on paragraph 5.2.3 Integer types:

An integer type definition defines an integer type whose set of values includes those of the specified range.
...
An integer type definition defines both a type and a subtype of that type. The type is an anonymous type, the range of which is selected by the implementation; this range shall be such that it wholly contains the range given in the integer type definition. The subtype is a named subtype of this anonymous base type, where the name of the subtype is that given by the corresponding type declaration and the range of the subtype is the
given range.

The norm always talk about a range of elements, a list like you suggest does not seem possible.