How to ignore simulation only ports when mapping to FPGA pins?
There is a useful option to use a Virtual Pin assignment. It is often used when compiling a design with a number of pins that exceeds the available physical pin count of a target device. For example, this can be useful to make preliminary estimations for some module, which is only a part of a whole design.
Making a pin virtual can be done via Assignment Editor (Ctrl+Shift+A) like this:


[Assignment] Specifies whether an I/O element in a lower-level design entity can be temporarily mapped to a logic element and not to a pin during compilation. The virtual pin is then implemented as a LUT. This option should be specified only for I/O elements that become nodes when imported to the top-level design.

Here is a related video on Using Virtual Pins from Intel FPGA website.