Understanding @(posedge) in Verilog
You have a race condition between the falling edge of decode and the rising edge of clock.
Zoom in your wave viewer and you’ll probably see composite going high very briefly at that edge.
To fix it, make sure that decode goes low some nonzero time before clock goes high. Or, even better, instead of using a gated clock (google this term if you don’t know it), use decode as an enable signal, and clock as a clock.