Level transformation 0/+5 V TTL logic to +/-9V how to maximize gain and frequency range (DC to 4 MHz)
An inverting level shifter can be made with an NPN and PNP bipolar transistor, like this:-



simulate this circuit &ndash; Schematic created using CircuitLab
Q1 is configured in Common Base mode with a bias voltage of 2.5 V. When the TTL signal pulls down below ~1.8V the transistor turns on and (almost) the same current flows through both R3 and R4, causing the voltage at R4 to go down from 9 V to ~5 V. This then turns Q2 on via R5, causing it to pull the voltage at R6 up from -9 V to +9 V.
It's a simple circuit, but getting good performance at 4 MHz is tricky. Parasitic capacitances in Q2 cause charge to build up on the Base, which normally prevents it from turning on and off quickly. This problem is solved by adding C3, which bypasses R5 at high frequencies to get charge in and out of the Base quicker. This also requires that R4 (and therefore R3) have a low value.
R6 has a low value to improve the output fall time. R5 has a high value to avoid turning Q2 on too hard, as this would cause more charge to accumulate on the Base, slowing down the turn-off time.
Although this circuit is 'TTL compatible' it requires about 18 mA of driver sink current, so you may need to pass your logic signal through a high current buffer if you driver isn't strong enough.