External interrupts in stm32f10x
I/O ports on the STM32F10x are organized into 7 groups of 16, designated PA0, PA1, ...PA15, PB0, ... up to PG15. Typically, only a subset of these are brought out to pins.  

To trigger an interrupt, a port must be configured in Input mode. 

PAx, PBx, ...PGx (x=0..15) are muxed into External Interrupt Line x, so only one of these ports drives Line x.  That port is selected by the EXTIx bit field in the AFIO_EXTICRy (y=1..4) register. The other ports on Line x are ignored as far as external interrupts are concerned.  

Line x is unmasked by writing a '1' to the appropriate bit in the EXTI_IMR register, and rising and/or falling edge trigger is selected in the EXTI_RTSR and EXTI_FTSR registers.

For example, to have an external interrupt on PC4 rising, set the EXTI4 bits in the AFIO_EXTICR2 register to (binary) 0010 to select port PC4.  Write a '1' to the MR4 bit in EXTI_IMR to enable Line 4, and to TR4 in EXTI_RTSR to select rising edge.  (In this case, PA4, PB4, and PD4-PG4 are not available as external interrupt sources.) 

The EXTI_PR register can be read to determine which lines have pending interrupts.

The NVIC must be configured to accept and process the interrupt request. External interrupts 0 through 4 have individual interrupt vectors, but 5 through 9 share one vector, as do 10 through 15.