Verilog and XST - large LUT long to synthesize
This is more of a comment than an answer, but I want to include a code snippet that formats correctly, so here goes...

Show us your actual code. I have had no problem generating large LUTs (program ROMs for soft CPUs). I have an assembler for the CPU that generates hex files, and then a Perl script that turns those into simulatable/synthesizable Verilog code that looks like this:

/* tb_cpu_rom.v */

/* This is a generated file. Do not edit directly.
 */

module tb_cpu_rom (
  input           [8:0] addra,
  output reg     [35:0] douta,
  input                 clka
);

  always @(posedge clka) begin
    case (addra)
    9'h000: douta &lt;= 36'h000810069;
    9'h001: douta &lt;= 36'h020001234;
    9'h002: douta &lt;= 36'h820000000;
    9'h003: douta &lt;= 36'h020005678;
    9'h004: douta &lt;= 36'h024020000;
    9'h005: douta &lt;= 36'h024040100;

    /* hundreds of lines snipped out */

    9'h1FD: douta &lt;= 36'h000000000;
    9'h1FE: douta &lt;= 36'h000000000;
    9'h1FF: douta &lt;= 36'h000000000;
    endcase
  end
endmodule


Perhaps your LUT has no clock? That could be causing a problem in synthesis.