contribution statements in verilog-A
This can be explained with the help of the following example:
analog begin
V(in) &lt;+ 2;
V(in) &lt;+ 3;
end
Initially the simulator sees the value 2 and assigns it as a voltage of port in. Then it sees the value 3, but the simulator will add the previously stored value for in i.e., 2 to the present value so final value assigned will be 5V.