Number of machine cycles in microprocessor 8085
The \$3\$ machine cycles are:


Opcode Fetch Cycle 
Memory Read Cycle
Memory Write Cycle


Internally, depending on the opcode, each machine cycle takes from \$3\$ to \$6\$ T-cycles (or T-states) to accomplish the \$1\$ machine cycle. 

T-states are one clock period long, and the instruction length is measured in T-states.

For example, a typical Opcode Fetch has \$4\$ T-states: the first \$3\$, T\$1\$-T\$3\$ are used to fetch the instruction, and T\$4\$ is used to decode it. 

Instruction cycles take from \$1\$ to \$6\$ machine cycles.

The 8085 also has some external status pins that can be used to identify which machine cycle it is currently in.  These are the \$\mathrm{IO/\overline{M}}\$ signal, the \$\mathrm{S0}\$ and \$\mathrm{S1}\$ signals.

Opcode Fetch: \$\mathrm{IO/\overline{M}} = 0,\$ \$\mathrm{S0} = 1\$ and \$\mathrm{S1} = 1\$

Memory Read: \$\mathrm{IO/\overline{M}} = 0,\$ \$\mathrm{S0} = 0\$ and \$\mathrm{S1} = 1\$

Memory Write: \$\mathrm{IO/\overline{M}} = 0,\$ \$\mathrm{S0} = 1\$ and \$\mathrm{S1} = 0\$

There is also I/O read and write cycles, which are not part of this DCR M instruction, but when those cycles are active in other opcodes the control/status pin \$\mathrm{IO/\overline{M}} = 1\$