Why bother using RESET# line on AVR?
SHORT ANSWER:
After you disconnect power it can take a little while for the voltage to the chip to drop low enough for the chip to reset. During this time, it is possible for uncontrolled things like glitching and corruption to happen.
Pulling the RESET line low will almost instantly put the chip into a known state where all IO pins are set to input mode and the processor is halted.
If your application is sensitive to unknown states, then it is probably better to use the reset line.
LONG ANSWER
When I first saw this question, I brushed it off as trivial. As I thought more about it, I realized it is actually a great question!
I can only think of two functional differences between a power on reset and an external reset (pulling the RESET pin low)...

After an external reset, the EXTRF bit in the MCUSR register will be 1 and any of the other bits will still have their pre-reset values. After a power on reset, the PORF bit will be 1 but the other reset flags will be 0.

Internal data SRAM will be filled with undefined data after a power on reset, whereas after an external reset it will still contain whatever data it had before the reset. Note that IO registers are set to their initial values either way.
While I can imagine cases where you might want to reset the processor but still keep the contents of SRAM, they are contrived. In normal use, if you want to reset then you probably want to reload what ever data you had in SRAM as well.

If (a) the WatchDog timer is not enabled via fuse, and (b) the WatchDog timer is enabled via software prior to the reset, then after an external reset the WatchDog will still be enabled, whereas it will be disabled after a power on reset.
It is generally good style to turn off the Watchdog immediately after a reset (assuming no fuse is set), so this should not be a practical difference.


So, the main reason I can think of to use the RESET pin rather than pulling power might be that you want to reset in a controlled and (nearly) atomic way. When you pull the RESET line low, the I/O pins all go into input mode and the processor halts and these happen very quickly and cleanly.
When you pull power, thanks to capacitance and inductance (some inherent in the chip itself and its connections) it can take a tiny but significant amount of time for the chip to see the Vcc drop down to the cutoff voltage. During this time, it can continue to execute instructions. There can be a time when the voltage is too low to support the current clock speed, but still above the power on reset threshold. During this time, the processor can glitch and generate corrupt outputs. (You could use the brown out detector to potentially mitigate this case, but there are still cases where you can get into trouble.)
So I guess it comes down to what your chip is going to be doing at the moment you want to reset it. If you are connected to a bunch of buttons and blinking LEDs, it really doesn't matter if one of the LEDs blinks incorrectly for a microsecond as the chip fades out. If, however, you are connected to a software-reversible high current motor driver, there is a chance that the chip could create a dangerous short on the way out.
ESOTERIC CASE:
I think there is also a case where an external reset while the chip happens to be in a deep sleep mode skips the start-up timeout delay, so in this case the startup after the external reset is released could be faster than a startup after a power up.
If anyone else knows of any other relevant differences, I would love to hear them!