non-blocking assignment does not work as expected in Verilog
It is all about the scheduling rules of Verilog simulators, which may be confusing for both newcomers and experienced engineers.

If you read "Verilog Nonblocking Assignments With Delays, Myths &amp; Mysteries" (here) carefully and make sure you understand everything it explains, you will not experience this kind of issues in the future, or, at least, you'll know what to look for when debugging.

The answer to your question is rooted in the following diagram:



What it shows is that evaluation of RHS of non-blocking assignments (&lt;=), and evaluation and assignment of blocking assignments (=) have no ordering rules.

What it means is that in your case, where both posedge gclk and div_valid scheduled to the same time slot , both following outcomes can happen:


div_valid changes before the RHS of non-blocking assignment is evaluated
div_valid changes after the RHS of non-blocking assignment is evaluated


#1 above leads to a behavior observed by you - both div_valid and var seem to change on the same clock cycle.

#2 above leads to a delay of 1 clock cycle from div_valid to var change.

In practice, all the simulators I saw behaved according to #1 (seems that they place all the events triggered by @(posedge signal) at the end of the Active Events Queue). However, it is not advisable to rely on this consistency.

I believe you'd prefer to see the delay between these signals, right? It is more consistent with the way a real HW behaves. There are two ways to achieve this:


Change the states of the signals driven with blocking assignments (=) from the testbench at time slots when there is no positive edge of the clock (see the answer by @Travis for waveform example)
Use sequential always blocks with non-blocking assignments (&lt;=) to drive signals from testbench (at positive edge of the clock).


If you want to understand why will the approaches I suggested work, you are welcome to read the paper I referenced above.

Hope this helps.