delay on cmos inverter while increasing W of nMOS and pMOS
I'll assume you are reffering to the charging/discharging delay.
Let's take the discharge  time delay. That is TpHL (H-L) trasition.
This happens when you are applying Low-to High input, your Output changes from High to Low.

This is the image of a regular CMOS inventor.


Now to calculate for TpHL, it is by definition the times it takes the capacitor to discharge from Q such that the output voltage changes from VDD to VDD/2.
During this period, a High input is applied, therefore, the PMOS acts as an open circuit and we will only need to analyze the NMOS.

When C is fully charged "at the beginning of the discharge", the N-mos is in saturation.

Therefore; you can apply the saturation current equation.
When the the output voltage reaches VDD/2, the NMOS is in linear and you have to apply the linear current equation.

Now you've calculated the currents.
we find average current Iavg = (I(0) + I(at Q = Q/2) /2

Therefore; TpHL = C * (V2-V1)/2 /Idn av

Note now, increasing W will increase the current>> which will therefore decrease TpHL.



In short words: Increasing the W, will increase the average current either in saturation or linear, which will increase the charging/discharging rate >> which will decrease the delay