thoughts on reading only one changing GPIO with accurate time amoung huge number of digital Inputs
A microcontroller with lots of pins as an intelligent I/O expander could be more cost-effective than an FPGA.

An STM32H743BIT6 has for example 168 I/O pins, let's say 8 of them are needed for communication and debugging, leaving 160 inputs for the application. These pins are arranged in 11 ports of 16 bits each. The controller runs on 400 MHz, so there'd be about 72 clock cycles to read and evaluate each port. There is 64k code memory with 0 wait state even at full speed, it seems plausible with some careful assembly coding.

You can connect a couple of these controllers as SPI slaves to a master MCU.







simulate this circuit &ndash; Schematic created using CircuitLab

Each slave would scan its inputs continuously, and signal on the INT output whenever there is a change, then the master can poll that slave for the pin number(s). As a crude means of avoiding race conditions, the slave could suspend processing the inputs  until the master acknowledges it by reading the SPI buffer.