Concurrency concept in VHDL
The short answer :
a will be updated in the delta cycle after either b or c changes.
b will be updated 5 ns after either d or e changes.
(Which triggers an update of a)

The longer answer :

These statements are not sequential, because they appear in the concurrent region.

Formally, each is equivalent to a process sensitive to all of its inputs. Therefore whenever an event occurs on any of its inputs, the process wakes up, performs the operation, and suspends.

The operation results in a "postponed assignment" on its output signal : that is, when this process has suspended, and ALL other active processes have suspended, THEN the assignment happens (or is scheduled to happen at some later time, as in 'after 5 ns`. 

When the assignment happens (either in the next delta cycle, or 5 ns later) it causes an "event" on that signal, which schedules all processes sensitive to it to wake up...
So, signals are not just like variables, they are the inter-process communication and scheduling mechanism in VHDL.

More detail here... https://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant/13956532#13956532