What is the use of 'event in vhdl?
The sensitivity list is mainly a concept used by simulator to schedule the execution of processes. A synthesis tool will usually discard the sensitivity list.
What are the results when running the above code snippets through a synthesis tool? The implementation without 'event will infer a latch, because that's what a synthesis tool "sees" when looking at the code.

Results of Xilinx XST for if clk'event and clk = '1' then:  

Adders/Subtractors : 1  
8-bit adder        : 1  
Registers          : 1  
8-bit register     : 1 


Results of Xilinx XST for if clk = '1' then:  

Adders/Subtractors : 1  
8-bit adder        : 1  
Latches            : 8  
1-bit latch        : 8


The results above where obtained by synthesizing an 8 bit up counter.

EDIT (2015-06-11): In IEEE-1076.6-1999 "IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis" the expressions which "shall represent a positive clock edge when used as a condition in an if statement" are explicitly defined as:


RISING_EDGE( clk_signal_name )
clk_signal_name'EVENT and clk_signal_name = '1'
clk_signal_name = '1' and clk_signal_name'EVENT
not clk_signal_name'STABLE and clk_signal_name = '1'
clk_signal_name = '1' and not clk_signal_name'STABLE