Why is the gate drain capacitance in a mosfet zero when in saturation?
This is mainly a question of definition. For sure there will be some capacitance between source and drain in saturation (--> Miller effect). Yet, it is true that Cgd is zero in saturation, at least according to a common definition.

When dealing with parasitic capacitances of MOSFETs the parasitics are divided into intrinsic and extrinsic capacitances. The intrinsic part is the part of the MOSFET with a source and drain region of zero width. For this intrinsic part the gate has a capacitive coupling to the channel. In the linear region the channel connects to drain and source, consequently the gate is capacitively coupled to drain and source. In the saturation region the channel is only connected to the source and separated from the drain by a depletion region. Therefore the gate to drain capacitance is zero.

The extrinsic part includes the drain and source areas. Overlap and fringing capacitances are the main reason for capacitive coupling between source and drain. They are present in the linear and saturation region.