VHDL delay mechanism
VHDL has two delay mechanisms: Transport and Inertial Delay mechanisms.

delay_mechanism ⇐ transport | [ reject time_expression ] inertial

If you simply write:

delay_mechanism &lt;= time_expression

The VHDL translator will assume it's a "inertial" delay mechanism.

Transport delay mechanism is used to model an ideal device with infinite frequency response,  what in what out. The waveform only is delayed, no matter how short your input pulses are.

Inertial delay mechanism mimic the real world. In reality, most electronic circuits don't have infinite frequency response, so model them using 'transport delay mechanism' may not be appropriate. Just imagine a RC filter, if your input pulse is very short, you may not see the pulse from the output. So, inertial delay is the mechanism used by default in a signal assignment. Your first model will 'filter' any pulse shorter than 3ns. For pulses wider than 3ns, it will delay them. 

In the second model, if 'waveform' is in your process's sensitivity-list, every time 'waveform' has a change event, a new transaction will be scheduled, and the output changes after the delay time. It's just when 'waveform' changes, a new change is scheduled.