OrCad issue: Logic circuit simulation....ambiguous output
The problem is the 'VCC' element.



I intended to use 'VCC' to set input to permanent '1' logic state, but that's not the right way to do this.(Using 'VCC' element, the output of simulation, in my case y, will be two parallel red lines, one for '1' logic state and the other for '0' logic state).

As I already mentioned in this post, "The 'PULLUP_1k' part in 'DIG_MISC' library, will provide 'permanent high to an input '". 

So, after I had put 'PULLUP_1k' part instead of 'VCC', the simulation result was correct.