Designing a SMPS for low noise
The 60Vdc input from wains transformer is Valid .This means a 60 volt switching waveform and not a 360Vdc switching waveform.Linear post reg is good ,if there are concerns about HF rejection then extra LC filter before the reg is good.The coils and caops for this are not a drama at an average current of 5A .Synchronous will as orthodoxely implemented will be much more noisey at HF .If you still want synch then run the bottom switch in "FIODE " mode .This means that the switching regime makes the fet behave like a diode but with a lower volt drop that is dictated by RDS on .I think that a schottky diode rated at say 100V will be more sensible.Now deal with your turn on by whatever means because turnon into a conducting diode makes lots of HF and VHF noise which is more difficult to filter because capacitors look inductive and inductors look capacitive.I have used a S trap buck     for Variable volts off inputs up to 820VDC so 60 wont be a problem . The S trap is a second cousin of a valley switch. Use lots of MLC caps because they are better at HF ripple suppression than ALIMINIUM ELECTROLYTIC CAPS.Sure you need thousands of microfarad on buck input due to 50/60Hz power but your output wont need much electro .Most importantly the ceremics deal with the switchmode ripple .Your design should be doable in SMD.