Output in unknown state even though specified in verilog
detected is a function of signal prev_data which is undefined at the clock instance that you indicate.

Upon reset, you have to set prev_data to something. That's what the reset is for.

I don't think that prev_data == 'bx has any practical meaning at all... 'bx is not a value, so it cannot be compared to a value. This cannot be synthesized. If you are trying to do something behavioral only, change the type of your variable and assign something different. Say you make it an integer, then use -1 for "undefined", 0 for 0 and 1 for 1.