Current mirror design - gate to drain feedback
This is most succinctly explained in Carver Mead's 1989 book on neuromorphic engineering, Analog VLSI and neural systems.  In the two circuits above, the top one is a current mirror and the bottom one a current conveyor.  The both assume saturation of the devices.  In the current conveyor, the assumption is that the voltage across M1 is larger than \$4U_t\$ for saturation.  Firstly, you also need to "untie" the bulk from the source of M2 and M1 and not assume that the source is tied to GND.  You then can setup the two current equations for the devices.