STM32F20x ADC Two Sampling Delay Tconv
Well the conversion time is: \$ T = T_{SH} + 12\text{ cycles} \$ (in case of 12 bit resolution) so in your case it is 40 cycles.

The ADC_TwoSamplingDelay_5Cycles is only interesting if you are doing multiple ADCs interleaved mode, which you are not, so it has no effect, thus no 5 cycles to add.

40 cycles of the input clock, which is divided by two (ADC_Prescaler_Div2). That would mean in theory you are running on 19,2 MHz. That sounds a bit odd. What's missing is the time you need to read the data register and thus clear the EOC bit before the next conversion starts. You are already using DMA, so probably you are running on 20 MHz and the DMA is doing the best it can to get the data out of the ADC.

Other incarnations of the ADC have a settable wait bit to control this behavior, so they just start right after they finished, which will get you pretty close to the theoretical value - but the F2xx doesn't seem to have this.