Why do block RAMs have synchronous reading instead of async reading?
To put it bluntly, because that is how Xilinx have implemented block RAM in the 7 Series FPGAs.

The data sheet is here:

https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf

This in extract from the datasheets showing how the ports work:



As there is no asynchronous read block RAM in Series 7 FPGAs, when you write an async block RAM it will be synthesised as logic.