Why is wave pipelining so rarely used?
It's difficult to implement.

I made a FPGA on 14nm SOI which could be asynchronous.  It had reservation stations and a significant amount of synchronous logic in actual implementations between clock zones.  I used tools tried to match the paths, but when it was unsure, it used RAZOR techniques to be sure that things were not too far behind instead of completion trees.  I got the idea for this from the PA-RISC, but implemented checks using RAZOR for basically the reasons that you described.  I'm rather sure that it'll never be used in prime-time implementations because the complexity that you will burden in academia is not practical for most commercial products.