Verilog Ring Oscillator problem
Check your compiler logs. You will almost certainly find something saying "Combinational loop removed" - the synthesis tools will not allow this unless you specifically tell it to preserve each as a separate LUT. Have a look at the post-fit netlist and see what the synthesizer is producing.

Oscillators are not good for FPGAs as depending on the length of the chain and propagation delays, you can easily get several hundred MHz if not GHz signals which can burn out the device with excessive switching currents.

Even if it does keep the loop, you will almost certainly get odd behaviour. The oscillator will toggle so fast and with so much jitter that you will violate the setup and hold times of your counter which will result in weird behaviour. 

Then if you are comparing it with a clock (which is also not good) of 10MHz, that means the counter is going to get reset for 50ns in every 100. Because this oscillator and the external clock are both asynchronous with no synchronisation, you will end up again violating setup and hold times of the output register and cause it to go metastable 0 - who knows what it will output then.