VHDL Plus operator `+` and Downto syntax
If a, b, c are of type std_logic_vector(31 downto 0), 

then,  c := a + b;
will give the 32 bit answer in c (without carry) as you required.

If you want 33 bit answer in c (where c is std_logic_vector(32 downto 0))

Then c := ('0' &amp; a) + ('0' &amp; b) will give the 33 bit answer.

But you will need ieee.std_logic_unsigned package for adding std_logic_vector using + operator.