SR Latch Understanding
First a slight correction to your diagram. The NOT Q output is the output of the NOR1 gate, not the input you have shown.



When both inputs are LOW (0) the latch holds it state.

With S, R = 0, 0

If Q = 1, then NOR1 input is 0,1 and its output (NOT Q) is 0 keeping Q = 1
If Q = 0, then NOR1 input is 0,0 and its output (NOT Q) is 1 keeping Q = 0

i.e. NO CHANGE

If S = 1 (R = 0) then the output of NOR1 (NOT Q) will be 0 and the output of NOR2 (Q) will be 1 - the latch is SET, Q is HIGH

If R = 1 (S = 0) then the output of NOR2 (Q) will be 0 and the output of NOR1 (NOT Q) will be 1 - the latch is RESET, Q is LOW

The problem comes when both S and R inputs are taken HIGH at the same time and forms a race condition. This logical condition (S = 1, R = 1) is to be avoided as the output cannot be determined.