I'd like to know if this MOSFET switches design is okay
If you connect the drain of Q2 to the source of Q1, then Q1 will be disabled when the gate of Q2 is pulled low. (assuming they are N-MOSFET's). If this is your intent, then S2A must be at logic zero to disable the relay. (It's not very clear what else you wish to disconnect.)

Also I advise you to increase the resistors between the gates and ground to between 100K to 470K because 10K will reduce voltage a bit and as it's already only 3V, it's better not to reduce it. Better not to see less than 3V at the gate when you want the MOSFET to conduct optimally.
100K to 470K will ensure that  the gate is at logic zero if the output is high impedeance (not pulled low neither high) without acting too much like a voltage divider as 10K would.

If you can, try to apply more than 3V to the gates. You can use 12V to the gates. But it may complicate the circuit... or simplify it. I don't know.