Can a Spartan-3A / AN / E implement edge detection for a 5MP camera
In terms of interfacing to the camera and clocking data in, that will be fine it can handle it.  It may not handle the speeds you are interested in.

5MP * 3 (colours, RGB) * 15 (times per second) = 225*e6.  (assuming 24 bit colour depth)

So that means you will need a clock speed of at least 225 MHz assuming you can move data on every clock signal, which you may not, depending on the sensor, so you may need to double this figure to circa 450-500 MHz

The Spartan you are looking at has a clock signal of 50MHz.

So the short answer is no, not at those speeds.

The other consideration you need to apply is how many logic blocks does your logic require?  to work this out, write out your implementation in VHDL/verilog, simulate and then synthese.  Read the outputs from the tool and it will tell you how many logic blocks you need, then select an appropriate FPGA which has 50% more logic blocks to allow for unuseable blocks due to routing constraints and gives you some room to grow.

Also you need to consider RAM or some other sort of memory and how your will store these bursts.  If you are shooting at 15 fps for 1 second then you need 225 MB which is a lot or RAM for an embedded system.

After storing in RAM you will need to flush into ROM of some sort (for example compact flash).