Designing an 8 x 3 memory chip given 2 4 x 3 chips
If the requirement is 8 bit by three words, it sounds as if the word size is 8 bits (the data), and there are three individual location for that data (the address).(This address range is unusual in practice, but theoretically there is nothing to prevent it).

Using your 2 four bit by three word devices, you must 'address' the words (you will have some address inputs somewhere). You should connect the addresses together on your two devices. This forms what is known as the 'address bus'.

The two individual 4 bit data should go to separate connections for your 8 bits of data. This forms what is known as the 'data bus'.

This means you will address the same location in each device at all times, with half the data from/to one device and the other half from the second device.

Changing the address changes which word you can write or read.

Cheers

PJS