In which cases should I use Z as output in HDL?
When you don't care about an output value given a set of inputs, use '-' which means "don't care".  The synthesizer will simply assign values that optimize resources/performance.  Note that a  simulator however has the option of keeping '-' as an actual value, and this will actually help you in making sure that having a "don't care" in there will not impact the relevant parts of your design.

'Z' or "high impedance" in FPGAs is only used for tri-state outputs, which nowadays are only available at the actual pins of the chip, not for internal logic.  Modern FPGAs manufacturers simply don't allocate internal routing resources for them, and are only intended for interfacing with external chips/components.  For internal logic the same functionality (such as bus arbitration) can be achieved with regular logic gates instead.

These definitions can be found in the IEEE std_logic_1164.vhdl library: http://standards.ieee.org/downloads/1076/1076.2-1996/std_logic_1164.vhdl