VHDL ieee.numeric_std: Division by zero defined?
In simulation:


The VHDL IEEE Std 1076.2-1996 standard defines division by zero as an error condition. So this should immediately terminate the simulation.
The Verilog IEEE Std 1364-2005 standard, on the other hand, says that division by zero should return xxx and not trigger anything spectacular (see chapter 5.1.5 Arithmetic operators in the standard). 


Of course on real hardware, anything could happen, because neither of these outcomes are implementable (there is no builtin mechanism in the chip to stop running - or should "stop the simulation" translate to "blow the chip up"?, and xxx values would require tristate logic which is not there). So the decision is up to the synthesis tool you're using (and the decision could be "it's undefined"). Maybe it is specified in the documentation of the specific tool you're using.

But in reality, you certainly won't manage to properly synthesize such a construct without bloating your design anyway (and some synthesis tools aren't even able to produce a general-purpose divider block that can take any value for the divisor: they will be restricted to power of two). So just don't do that in a real hardware design.