PCB trace length matching for High Speed signals with known frequencies
Jesus' comment is right, you need to look into your FPGA's and driver's datasheet to learn how much skew is admissible.

For 165 MHz signals, it's not unlikely that the signal is actually transported as low-voltage differential signal – thus, a single signal is not a single trace, but a pair of traces, which need to be more tightly matched. Rule of thumb says 10° – how much trace length difference that is depends on your trace design, PCB substrate thickness and material.

Many FPGAs do have some feature they call "IO delay calibration" or similar, which allows, within boundaries, to add an adjustable delay to IO lines.