Measure duration of a non periodic message on FPGA with VHDL
Assumptions:


A "message" is a collection of transitions, with some sizable gap between messages that contains no transitions.
The clock period is smaller than the shortest gap between signal transitions.


Here's a block diagram; I'll leave it to you to convert it to your favorite HDL.







simulate this circuit &ndash; Schematic created using CircuitLab


U1 is a two (or more) stage synchronizer that makes sure the input signal is synchronous to the clock.
U2 is a synchronous edge detector that outputs a 1-clock pulse for every edge at the output of U1.
U3 is the "timeout" counter. It gets reset on every edge, and the message is over when it overflows.
U4 is a simple set-reset FF that keeps track of whether we're "in a message" (output is low) or "between messages" (output is high). It gets set when U3 overflows, and cleared whenever U2 detects an edge.
U5 is the "duration" counter. It needs to have enough bits to count the duration of the longest message. It starts counting on the first edge detected, and keeps counting until U3 overflows.
U6 is a simple N-bit register that captures the value of U5 for each detected edge. When U3 overflows, it contains the count for the last edge that occurred in the message.


Each of these blocks is just a couple of lines of code in either VHDL or Verilog.