PCIE Trace Length Matching Between Tx, Rx, and Clock
From Wikipedia


  While the lanes are not tightly synchronized, there is a limit to the
  lane to lane skew of 20/8/6 ns for 2.5/5/8 GT/s so the hardware
  buffers can re-align the striped data


The allowed skew between the databytes in one direction is 6ns for 8 GT/s. Rx and Tx length matching is not critical as there is wide allowed duration. Assume it as a full duplex communication. How much exactly depends on the data link layer but definitely okay with 3 inch or so. Assuming 160ps per inch of propogation delay, the the 3 inch propogation delay will be about 0.5 ns. (Less than 2 ns)


Most important is to match and route the intra differential pairs well.