Part select in verilog
Using the convention variable[expr1:expr2] is correct as long as expr1 and expr2 are constant expressions. The defined range can be little endian, big endian or have expr1 = expr2 as in the case variable[0:0]. Although variable[0:0] is less readable than variable[0].

If your synthesis tool, simulator, etc. is crashing when you use this convention, it is not because you are using bad syntax, but because the tool has a bug in it. Tools are expected to give at least an error and a line number for unsupported code. A seg fault is not expected behavior. You should submit a bug report to the developer and either change tools or remodel your code so it does not crash the tool.