layout of SPI and analogue signals
If the signal Trise and Tfall are 10:1 longer than the time-of-travel along the PCB path (and the wiring path), you do not need controlled-impedance design.
[Note some people use 20:1. ]

What this means is: with 100 nanosecond Trise and Tfall, the electrical length of the trace/wire can be 10 nanoseconds (about 5 feet), if standard FR-4 (with Er of 4.5) is used. People will debate about using one-way or round-trip delays.

Also read this answer: 
Distance between SPI traces to prevent cross talk

Note I edited this (about 5 feet) is correct, since sqrt(4.5) for FE-4 is ratio of 2.2 slower than speed-of-light. Thus 5 feet of PCB trace, atop FR-4 where most of the energy is in the underlying FR-4 and NOT up in the air, becomes 2.2X longer or 11 nanoseconds. I use 1 nanosecond/foot as good working number.