How can I design this pull up without wasting current/performance?
One way would be to add a CMOS buffer driving stage. If you have small but high voltage transistors/mosfets in an inverter setup driving the main PMOS, there will be virtually no ON or OFF current, only transition current. The buffer cmos transistors will have a much smaller gate area than your main PMOS and therefore won't take nearly as much current to turn on and off. In that way, you'll be able to use a much larger driving resistor for the input stage while still achieving the same performance.

The setup should be something like this:







simulate this circuit &ndash; Schematic created using CircuitLab

The reason for two cmos inverters is to maintain the state of input low = output off rather than input low = output high.

The Zener's are added to prevent the Vgs's of the MOS's from getting too high.

Alternately, you could just add a Zener. It would eliminate the high voltage on the PMOS gate source voltage. When the input is high, you'll get a significant reduction in current because you'll only have (Vdd-Vzener)/R rather than Vdd/R. This will be balanced with the reduction in voltage swing you need to turn on/off the PMOS.







simulate this circuit