Discrete LDO Drawbacks
The pfet/pnp acting in common emitter mode has a high impedance node which acts with the regulator's load at low load currents (high impedance load) to create an additional low frequency pole which has the potential to cause instability. A capacitor which has an ESR within a particular range is added across the output to add a zero to the loop which cancels out the extra low frequency pole and creates stability. with low impedance loads (high load currents) the extra pole moves up in frequency and makes the regulator more stable.