Clarifying an article on switch debouncing - something about leakage current causing trouble
Mr. Ganssle is saying that the worst-case leakage current (if it comes out of the input) multiplied by the R2 resistor value could result in the input voltage not getting close enough to ground when the switch is closed, in fact getting close to the switching point in the pathological case of using an HCT gate (with TTL rather than CMOS switching thresholds) for some reason, and worst-case leakage.

It's a bit of a misspeak because the gate input does not &quot;dribble&quot; anything like 1uA under normal conditions. 1uA is the maximum at 85°C (2uA at 125°C). At room temperature it's no more than 100nA and the typical current is much, much less than that (&lt; 1nA) and that is mostly due to the input protection network.
However if your circuit must operate at very high temperatures then you had better use the guaranteed number. They do not test to a current closer to the actual leakage because it costs more time in the test procedures and that would increase the cost (and usually nobody cares).
His comments about capacitor tolerances are also a bit off, the typical 1uF aluminum electrolytic capacitor these days will have +/-20% tolerance, not the very wide +80/-20% tolerances that used to be common on larger parts many years ago. Ceramic capacitors are a bit more of a dog's breakfast because of voltage coefficient, but the tolerance of an X7R part under rated conditions is usually +/-10% not +/-30%.