What is the control Input of the small signal current mode PWM switch
In a circuit like the UC384x but also in many other controllers, the maximum peak current voltage setpoint is limited to a certain precise level. It is 1 V for the UC but can be of lower value in other controllers like 0.8 or even 0.5 V in more modern ac-dc PWM circuits. In recent low-voltage dc-dc controllers, it is no longer uncommon to encounter maximum voltage setpoints as low as 50 mV but then you can imagine the sensitivity to switching noise in this case and good layout with adequate components choice are paramount.
This upper limit is there to protect the converter against peak current runaway when the loop is open. This happens during the start-up sequence, before the output voltage reaches the target, but also in fault conditions such as short circuits or optocoupler failure. With a 1-V maximum voltage setpoint and a sense resistance \$R_{sense}\$, then the maximum permissible current is: \$I_{p,max}=\frac{V_{max}}{R_{sense}}+\frac{V_{in}}{L_p}t_{prop}\$ in a flyback converter where \$t_{prop}\$ represents the delay incurred to the IC internals plus the driving time to effectively turn the MOSFET off.
In the UC348x picture shown below, the control section starts at the COMP pin of the error amplifier:

The voltage first undergoes an offset subtraction of 1.2 V roughly and this is to ensure a true zero-current setpoint when the COMP pin either rails down to 0.8 V (typical) with the op-amp or is externally brought to ground via an optocoupler. In reality, the \$V_{CE,sat}\$ of the opto is around 200-400 mV depending on various factors and owing to the diodes, you truly have zero volt at the current sense comparator. This interesting feature brings 0% duty ratio at no cost and allows operation of unloaded converters without output power runaway. The division-by-three is there to augment the op-amp dynamics. Without it, the op-amp output would move between 1.2 and 2.2 V to bring 1 V as a maximum setpoint. However, this would restrict the op-amp on a low voltage range but could also compromise the noise susceptibility. For that reason, the divider forces a higher voltage on the op-amp output (4.2 V to obtain 1 V) and naturally expands its output dynamics.
If you now want to model this controller with the CM PWM switch model, it is important to properly build this op-amp sub-circuit. The circuit in your post uses a simple voltage-controlled voltage-source with a 60-dB gain and it looks like the simplest option. It has several drawbacks:

the circuit output is unclamped meaning that during bias point operations the &quot;op-amp&quot; can peak to several kV. Yes, libraries don't burn but SPICE can't compute a proper bias point in this case.
if you run transient analyses, you may have totally abnormal voltage values across the compensating elements.
you have to reproduce the circuitry in the current-mode PWM controller you have adopted which is to limit to 1 V max the bias at the control pin of the CM PWM switch model.

The below circuit shows a first possibility to model the UC384x and this is a very first approximation which does not work with an optocoupler pulling the COMP pin down but it is good enough to obtain a first ac response with the PWM switch model. A more comprehensive model with a 1-mA maximum output is given in my book.

In this circuit, the output voltage is clamped to 5 V and 0.8 V via perfect diodes (N=10m) and there is no convergence issue considering the 100-µS source involved when the diodes clamp. So if you connect this op-amp to your model, you need a add a 1-V Zener diode and you should be ok:

You could also use an in-line equation (analog behavioral expression) and clamp the error voltage between 10 mV and 1 V. You could even group the 1.2-V offset subtraction and the divide-by-3 operation in the same line:

You read the expression as:
IF V(err) is less than 10 mV THEN V=10 mV
IF V(err) is greater than 1 V THEN V=1 V
ELSE V=V(err)
Hope this helps your model converge!