Clock Oscillator - Topology and PCB Layout recommendations
R25 and R26 are 50 Ohm terminator resistances placed there I suppose because they where present in an example of the oscillator datasheet.


Notice that in the datasheet they show the termination at the far end of the line, near the receiver, not near the oscillator. Your tracks appear to be short enough that this isn't going to break the design, but it would probably be better to put these resistors near the far end of the line.


  Are R25 and R26 terminator resistances really necessary?


The datasheet isn't clear about the oscillator's output equivalent circuit. I would guess that they aren't needed, but I would put locations on the PCB anyway to be able to place them in case they are. If you don't place them, you'll likely get a 2x larger signal at the receiver, due to the reflections.


  Is 10uF for C_TA13 too high value for its purpose?


It's not too big, but check its Z vs f curve. It's likely that a 10 uF cap will be beyond resonance at 150 MHz. 

I'd add 0.1 uF 0402-size (chosen with SRF at least 200 MHz) as close to the oscillator power pin as possible, and probably 1 uF 0603 or 0805 sized somewhere nearby as well. Smaller values (also close to the power pin) might even be helpful to keep the higher harmonics of the clock frequency from getting in to the power lines and causing radiation.

Decoupling near the termination resistors is also probably a good idea. Again I'd probably start with 0.1 uF 0402 placed as near as possible to where each of those resistors connects to 3.3 V.


  I've tried to connect all supply and ground pins together before going to the ground and power planes with vias only at one point. Do you see any problems with this layout?


I'd probably just give each VCC connection its own via to the power plane, but your design will probably work okay too. 


  Should I connect the oscillator ground with the DDS ground on the top layer and then connect to the ground plane only at the thermal pad of the DDS?


Again, I'd rather just have a via (or more) for each ground pin of each device/chip. The idea is to minimize the inductance connecting the chip/device to the "true" ground net. 

Other Q&amp;As on the site make a big deal about power and ground islands for each chip. The one I remember is related to a microcontroller. In that case you're trying to protect sensitive analog circuits from switching noise generated by the uC. Here you have equally noisy and (more or less) equally sensitive parts (oscillator and DDS), so I wouldn't privilege one over the other, I'd just give both of them the lowest possible inductance in the power and ground connections.