How is the lh (load halfword) instruction implemented in MIPS?
You are mostly right.  When in doubt, read the source material (in this case, the instruction set reference).
Where you may not be right is that according to MIPS, only 16 bits are read from memory.  This doesn't matter much if you're reading from RAM, but for memory-mapped I/O, some peripherals will change state when a &quot;memory&quot; location is read from or written -- for example, a FIFO read will read the top of the FIFO and then pop.
Where this makes a difference is if two such memory locations are packed next to each other in a peripheral's memory map, or where a FIFO is packed next to a general-purpose register (i.e. a stack register).