How to carry out signal integrity simulation with IBIS models
In signal Integrity analysis, power-aware IBIS 5.0 model of controller IC and memory  are used for transient simulation. IBIS(Input/output Buffer Information Specification) models are a behavioral model using I-V and V-t look-up tables that make simulations extremely fast. 

More details:
https://anilkrpandey.wordpress.com/2016/10/16/power-aware-signal-integrity-analysis-of-ddr4-data-bus-in-onboard-memory-module/