Why would you need both a pullup resistor and a capacitor to ground on an IO pin?
As this is related to an FPGA, any pin can have pretty much any imaginable function. It depends on the software in the FPGA what the pin will be used for.

In this case the pin is most like used as INPUT, possibly as RESET-pin or similar. If the pin was used as an OUTPUT, the output driver would have a hard time charging the capacitor and is easily overloaded, hence OUTPUT config is quite unlikely. 

What happens during power on of the circuit, is the pin is pulled low by the uncharged capacitor long enough for the logic circuit programmed in the FPGA to be used as a RESET signal while the power supply stabilizes. I expect the pin logic level to toggle LOW to HIGH after about (order magnitude) 10kΩ × 10µF =~ 100ms after power on.

The only thing that does not make sense to me here is how the cap will discharge when the circuit is powered off. Probably the internal protection diodes of the FPGA are used for that purpose.