Avoiding crosstalk between makeshift wires
Some things I'd try:


Use the slowest drive you can get away with.  At these clock rates, you should be able to use very slow drivers.  You don't mention a specific FPGA type, but if it were Xilinx, I'd be using the "quiet" drivers, or "slow" if not available, and a 4mA drive current.  See how it looks on the scope, increase the drive current if necessary.
Twist a ground wire with each of your signals, or at least with the clock signals.  Or if using ribbon cable, put a ground on either side of both the clocks.  Keep the clocks well away from each other.  In the extreme, use coax for the clocks (but be careful to use a very short connection to ground for the shield, otherwise you stand a good chance of not gaining anything)


You have to think about how the current is flowing - both "out" and "back" - any time the current of one signal mixes with another (say using a single ground return wire), you will have potential for problems.

Another suggestion - in order to understand what's going on so you can predict these problems next time, read (and inwardly digest :) a book on signal integrity