AXI Stream write and read not synchronized
First, changing the clock frequency to something the design wasn't synthesized for, might produce wrong results (having negative slack and so on).
To fully answer your question, there are a few things that require some clarification from your side:

First: what do you mean by sending an empty buffer? Your IP expects to read a packet for each one produced (since the fifo read() method is blocking).
Second: what's the code you're running on the PS? It's unlucky, but you might setup the DMA wrongly (and forwarding the side channels, like TLAST, on the stream is correct here).

Regarding your IP code instead, the ports that are in the feed-back loop have an ap_none interface type, so I believe VIVADO HLS doesn't put any register there. Thus, you might be reading something not clocked. There's an option on the interface to add a register to the port (something like: -register), that might be a starting point.
On a side note, I would avoid using bool types (so switch to ap_uint&lt;1&gt;) and try the PIPELINE directive.
Finally, always check that the simulation and cosimulation pass (even though the feedback connection might be tricky to do, since HLS behaves strangely with feedback loops).