Why does the clk not appear on the device under test?
I modified the testbench by declaring the component, instantiating the DUT properly, used std.env.stop(0) and simulated the design long enough. Now it works fine!
You need to simulate your design long enough to see the output.
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity counterEx_tb is
end counterEx_tb;

architecture arch of counterEx_tb is
   
component counterEx is 
generic( 
    M : natural := 6;
    N : natural := 4 -- N bits are required for M
    );
port(
    clk, reset : in std_logic
);
end component counterEx; 
   constant M : integer := 10;
   constant N : integer := 4;
   constant T : time := 20 ns; 

   signal clk, reset : std_logic;  -- input
begin

    unit : counterEx
        generic map (M =&gt; M, N =&gt; N)
        port map (clk=&gt;clk, reset=&gt;reset);

    -- continuous clock
    clock_proc: process 
    begin
        clk &lt;= '1';
        wait for T/2;
        clk &lt;= '0';
        wait for T/2;
    end process clock_proc;


    -- reset = 1 for first clock cycle and then 0
    stim_proc: process
    begin
    reset &lt;= '1', '0' after T/2;
    wait until falling_edge(clk);
    wait until falling_edge(clk);
    wait until falling_edge(clk);
    wait until falling_edge(clk);
    wait until falling_edge(clk);
    wait until falling_edge(clk);
    std.env.stop(0);
    end process stim_proc;
end arch;