Do FETs have a Maximum Gate-Drain voltage?
First of all, the oxide layer that separates the drain/source from the gate in the source/drain-to-gate overlap regions1 is not thicker than the oxide layer over the substrate (i.e. where channel forms). That would require at least an extra step in the manufacturing process. Instead, in integrated IC MOSFETs, an extra thick-oxide "spacer" is then grown (as a lateral separator), but the breakdown voltage is still determined by the "thin" oxide layer in such overlap (and channel) regions.

MOSFETs in ICs

In a planar MOSFET, i.e. typically found in digital and analog ICs, the MOSFET is symmetric. Therefore \$V_{GS,max} = V_{GD,max}\$ and \$V_{GS,min} = V_{GD,min}\$ (this latter formula is for negative gate-to-source or gate-to-drain voltages2).

Discrete/Power MOSFETs

Discrete/power MOSFETs are different, and conduction occurs vertically. There are many variants (V-MOS, U-MOS, etc.), but the principle is the same, so let's analyze one of them:



Don't be fooled by the symmetric design! This is not a conventional MOSFET! The source is both on the left and on the right! The drain is at the bottom!

The thin oxide layer still determines the low gate-to-source breakdown voltages. 

Why is \$|V_{GD,max}|\$ much larger than \$|V_{GS,max}|\$ then?

For the sake of simplycity let's consider an nMOSFET only.

The drain is (almost3) always polarized positively with the source/substrate. Therefore there will be a depletion region in the drain-to-body junction. Since the body is p+ and the top part of the drain is n-, such depletion region will extend mostly in the n- layer. This will create a large voltage drop (which of course depends on \$V_{DS}\$) between the drain contact and the interface between the gate and the drain contact. Therefore the voltage between the gate and the very top part of the n- layer does not exceed the SiO2 breakdown voltage.

This (and not the different oxide thicknesses) determines the different \$V_{GD}\$ and \$V_{GS}\$ maximum ratings.

The weak point now becomes the body to drain junction breakdown voltage. By choosing the doping and the layer thicknesses (and also the "shape" of the regions, to avoid point effects), the \$V_{DS,max}\$ can be determined. 

tl;dr

Planar MOSFETs (ICs) have maximum \$|V_{GD}|\$. In discrete MOSFETs, such value is larger than the maximum \$|V_{DS}|\$, hence no specification is given, as reaching such limit would imply that you already reached a catastrophic drain-to-body breakdown.



Notes:


There must be an overlap between source and gate (and drain and gate), to allow an efficient injection of charge. Othewise, there would be a very high series resistance (and the MOSFET would not work).
The positve and negative breakdown voltages are not always necessarily the same value. This is due to the different barrier heights (i.e. different charge injection efficiencies) and different band alignments between the two electrodes with the silicon dioxide.
You can have the drain at a smaller voltage with respect to the
source, in a power nMOSFET. However, such difference will be at most
"0.7V", because the body diode then starts conducting.