How does the DDR clock compensation capacitor improve signal quality?
This capacitor is related to jitter compensation and improving VIX threshold..

I can give few references.


there is a discussion regarding this on si-list


http://www.freelists.org/post/si-list/DDR3-Clock-differential-signal-termination.


www.jpier.org/PIER/pier121/04.11080302.pdf‎
"the timing jitter can be reduced by placing a capacitor to compensate for
the velocity difference caused by different propagation modes"


Altera mentioned Ccomp should be added to increase the signal quality

For DDR, there are few app notes from micron and freescale which will demonstrate the compemsated Bus topology to improve timing margins.
TN-46-07

I didn't find any SI waveforms which will demonstrate with or without Ccomp differences.