How would parasitic capacitance changes happen in a crystal oscillator?
A parasitic capacitance happens anywhere that there's two conductors and a dielectric.  Because a parasitic effect is, by definition, uncontrolled, parasitic capacitances are uncontrolled.
The parasitic capacitances on a circuit board are going to depend on the physical spacing between the conductors involved, and the properties of the dielectrics involved.
In general, the spacing is set by the position of chips and traces, and the dielectrics are chip package material, the board material (i.e., FR-4), and air.  You can probably ignore the air and treat it as vacuum, but that leaves other dielectrics.
From board to board, components may end up in slightly different places, because soldering processes are optimized for electronic reliability, not exact placement.  The thickness of the board will vary, and the actual trace edges may vary slightly.  The material that the board is built out of may vary in dielectric constant, even if it is from the same manufacturer.  In addition, the actual components may vary in size and composition from lot to lot, and is almost guaranteed to do so if your product is in production for years.
Over temperature, the dielectric constant and size of your board material will change, as will the dielectric constant and placing of the leads on your chip and crystal holder.  Similarly, humidity may cause dimensional changes in most materials, and a board that is subject to vibration may undergo dimensional changes either over a period of vibration, or permanently as pieces bend.
All of this means that your parasitic capacitances will change from board to board and over temperature.  If you're good at board design, you can minimize the parasitic capacitances -- and, hence, the change they undergo -- but this ends up being a bit of a black art, and you're still only minimizing them, not making them go away.