How to get a 1 clock period pulse from a constant signal clock input on every 64 clocks?
I have assumed that you just want a high pulse out during the high phase of the clock
every 64th clock pulse.

4024 is a negative edge triggered 7 stage binary counter. 4068 is an 8 input Nand gate. 4013 is a Dual D-Type flip flop.
Output of nand gate is usually high holding D type flipflop in reset. On a certain falling edge of the clock, the counter will increment to all ones output. The nand output goes low releasing the reset on the flipflop. The next rising edge of the clock clocks a one through to the Q output of the flipflop. The next falling edge of the clock makes the Q1 to Q6 outputs roll over to all zeros, the nand gate output goes high reseting the flipflop.