Selecting an external crystal for FPGA
If you want to use a DCM to generate the necessary frequencies inside the FPGA, then it is more dependent on the divider ratio in the DCM than the crystal itself - the DCM is going to generate more phase noise than a decent crystal oscillator.  Also, above a certain point, you need to use LVDS or LVPECL or similar to connect the oscillator to the FPGA with controlled impedance traces, otherwise you can get reflections.  For example, for 10G ethernet, you need a 156.25 MHz crystal, a clock buffer, and controlled impedance differential traces to all of the transciever clock input locations.  A 40 or 50 MHz crystal will cause fewer issues if the phase noise is not a major issue - it generally isn't unless you're multiplying it up to a very high frequency, like 10.3125 GHz for 10G ethernet.  The PLL phase noise is generally dependent on the lowest frequency that you have to divide down to, so you may get better performance if you select a crystal size that allows smaller PLL coefficients - 50 MHz just needs to be multiplied by 3 to get 150, 40 would need to be divided by 4 and then multiplied by 15.  283 MHz is a fun one, though - you may need to do some screwing around in Excel to get that one figured out.  It may be a good idea to pick an oscillator that gives you a small rational fraction for both of the frequencies you need.  Alternatively, it might be a good idea to use two different oscillators.  

Generally all of the boards I have worked on have used 50 MHz or 100 MHz oscillators for the core and 156.25 MHz oscillators with clock management circuitry for the transceivers, and then we have just ignored the 50 MHz oscillator and connected everything to one of the transceiver clocks.