What are the rules for combining transistors to form digital circuits?
Can it be boiled down into a list of rules that I could explain to, say, my grandmother?


Depends on your grandmother.
And you. :-) . 

The aim of a given logic family is 


To implement a series of mathematical and / or logical abstractions in a real world context 
while adhering to a set of predefined rules which are essentially independent of the logical/mathematical implementation but which affect the practicality and cost effectiveness of the implementation in real world contexts. 


That may sound somewhat waffly and vague (and indeed it is) BUT it also is a fair description of what is being achieved.

The transistors themselves are essentially independent of the functions being performed but play a part in allowing the rules to be met.

The rules of how to use transistors in this context boil down to "should produce the desired logic function and meet any level and loading conditions which have been defined for the system being built, at speeds and power levels that meet objectives."

If the output uses an N and P channel part working in unison you can be essentially certain that it allowed some design constraint to be better met than was possible by using only an N or a P channel part plus a resistor. 

Look up, in the context of logic circuits and electronics, the terms   


"RTL" (also R.T.L.)
"DTL", (also D.T.L.) 
"TTL", (also T.T.L.)
"ECL", (also E.C.L.)
"MOS", 
"CMOS", 
"Open collector", 
"totem pole", 
"push pull", 
"differential pair", 
"long tailed pair" 


then report back.

These should help vastly:

Note that EVERY result is a link to a webpage  - usefulness will vary greatly but you can see at a glance what is liable to be of relevance.   

A few minutes study of these should make your grandmother's eyes glow. And yours.

RTL, DTL, TTL are in order of historical development and sophistication. RTL has the advantage of low complexity at the cost of rice pudding skin performance levels. 

R.T.L. logic

D.T.L. logic

T.T.L. logic

These will be familiar in the context of your original questions:  

MOS
NMOS
PMOS
CMOS &lt;- the modern motherload for practical purposes.  

Then a useful spin off road that largely ultimately was not mainstream
Schottky  aka Schottky TTL

And, of course, ECL &amp; friends - A parallel universe - amongst the very first and still going strong in modern versions for super high performance niche applications.
E.C.L. logic - WARNING - this is a somewhat unusual system. Very fast, power hungry, quirky. Older versions use multiple and unusual power supply levels. Newer ones use fewer supplies and are at the leading edge for super high speed logic. 



I wrote the following initially but decided that while it is valuable it is also "somewhat hard going" [tm]. I added the searches above as an easier path.

For interest I Gargoyled on a string of many of the above and obtained one 'hit'.

It was https://archive.org/stream/CircuitDesigns2CollectedCircards/WilliamsCarruthersEvansKinsler-CircuitDesigns2CollectedCircards_djvu.txt
This is a text rendition of the complete 1972 Wireless Worlds Circuit Designs 2 "CIRCARDS" collection. By searching this file for the above keywords (probably with added "."s where relevant you will find many useful snippets. 

The original CIRCARDS have diagrams which are absent from this files, alas, but it provides many clues liable to be of value to your grandmother. 

eg just this index paragraph gives hints of headier stuff to come:


C.m.o.s. amplifier/shunt-peaked amplifier/high-gain amplifier/voltage followers/bipolar cascode  amplifier/e.c.l. amplifier/f.e.t. cascode amplifiers/amplifiers using t.t.l., r.t.l., d.t.l./d.c. feedback pair/gated 
video amplifier/high-speed op-amps/c.b. amplifier/up-date circuits. 


And this is "pay dirt" for you, although it may not at first be obviously so:


Simple r.t.l. 

The simplest resistor-transistor 
logic (r.t.l.) gate, which performs 
the positive logic NOR 
function, is shown left. A 
positive voltage applied to any 
input turns Tr x on, causing Vout 
to fall from V cc to a value that 
depends on the base drive. If 
sufficient base drive is applied, 
Trx saturates making F ut= 
FcEsat, representing the logical 
state. Positive voltages applied 
to the other inputs increases the 
degree of saturation and only 
change Vout by a small amount. 
If logical voltages (VcEsat) are 
supplied to all inputs the base- 
emitter juction of T^ will be 
only slightly forward biased 
( FcEsat » 0. 1 to 0.4V) and 
Pout ~ + Kcc. For useful logic 
functions the gate must feed 
some load, causing an additional 
current II to flow in Re and 
hence reducing the logical 1 
value of Vout below Fee. The 
gate is also a negative-logic 
NAND gate. 

Improved r.t.l. 

Inclusion of a base bias resistor, 
Rk in the middle circuit, returned to a negative supply 
ensures that Tr t is definitely 
turned off when all inputs are 
below the input logical 1 
threshold and reduces the 
transistors turn-off time. 
Speed-up capacitors can be 
placed in parallel with each input 
i?B to produce resistor-capacitor- 
transistor logic. However, if all 
inputs are at logical 1 voltages 
and one of them rapidly switches 
to the 0-state, its speed-up 
capacitor couples the negative- 
going transition to the base- 
emitter junction of Tr x which can 
cause the transistor to 
temporarily switch off. For this 
reason r.t.l. gates are normally 
only used at fairly low switching 
speeds. 

A clamping diode D b shown 
right, can be connected to a 
supply + Vv> &lt; + Kcc to make 
the logical 1 output voltage less 
dependent on the load current, 
provided that the drop across Re 
does not cause D,. to become 
reverse-biased.




Note that "combinatorial" and not combinational is the correct term in this context (don't blame me :-) )