How to protect P-MOSFET from excessive gate voltage
Would that work? other ideas?


In the 2nd circuit I would make R3 much lower than R2 or you will be naturally reducing the drive voltage to the gate under normal conditions and this will result in higher on resistance in the MOSFET.

I say this because the CTR of the opto may be 50% (for example) and this would mean only about 1 mA flowing into the collector. Peak loads may far exceed average load currents as well so getting a few more volts driving the MOSFET isn't a bad idea.