Speed difference between SRAM (Static RAM) and DDR3 RAM
Cycle as used on that web page means "clock cycle": the time taken for one pulse of the clock signal used by the ram. So the 100MHz clock corresponds to a 10ns cycle.

Internally, this corresponds to selecting a row within the chip and reading the corresponding column lines; this brings out a set of values (let's say 256 bits = 8 bytes), for each of the 8 chips on the RAM.

There then follows a response burst where the values are transferred back to the processor. The bus is 64 bits wide, so there will be several transfers. Usually this fills an entire cache "line".

(Note that there is an implicit pipeline: you can send out another request before the first has finshed)

For an FPGA project, you'd use onboard SRAM in preference, but if there isn't enough or you need to share it, you would use external DDR RAM.