Std_logic_vector to unsigned conversion problem
The problem is almost certainly that 2147483648 is not representable as Integer in the simulation tool you are using. The danger is that, being outside the Integer range, it is representing -2147483648, and the comparison is being performed against that!

Express the number as X"80000000"  (a bit vector literal) or if necessary, unsigned(X"80000000")  and it should work.
This form is not limited to 32 bits!

16#80000000# is another numeric literal so may or may not work. There are differences between simulators in this area, and again between sim and synth sometimes.

I am quite disgusted if a simulator just lets this happen without warnings or range errors; note that some sims (Xilinx ISIM) have range checks that are by default turned off. Turn on and try again perhaps...