Is the output clock correct?
This is a bit of a generic answer rather than anything specific to that particular chip to help you understand some of the issues. When you have a piece of code like this:

while (1)
{
    GPIOA-&gt;ODR ^= GPIO_PIN_2; //toggle GPIOA2
}


It won't be a single instruction / cycle in assembler, a branch will be used to keep repeating the same instruction sequence and they'll also be an instruction to perform the exclusive-OR operation. As Matt Young suggested in a comment the only way to know the assembler output for sure is to look at the output from the compiler to see how many machine instructions are actually being used.

Another likely issue is the FLASH_LATENCY_1 which is inserting a delay while reading the FLASH that's probably not necessary at that fairly low speed. I think if you replace that with FLASH_LATENCY_0 you should see a speed improvement (depending on any caching) but it's worth double-checking the datasheet so see at what speed it's required. Many ARM cores can operate at speeds above what code can be fetched from FLASH which is the reason for that feature.

I've never used the Keil compiler so I'm not sure how to get the assembler output but often it's described as a listing file. Just searching Listing (MDK-ARM) looks like it may cover it. 

Now you've found how to view the assembler output you can see there's a total of four instructions involved, the instructions between addresses 0x80009C8 and 0x80009CE are that part of the code and the last instruction is the branch that goes back to the start.