Verilog Reg File: Cant mix blocking and non-blocking assigment
Ok i fixed it...

Turns out the error message was from a typo.

I changed:

if(reset)
begin
    for(i = 0; i &lt; 32; i = i + 1)
        registers[i] = 0;
end


To:

if(reset)
begin
    for(i = 0; i &lt; 32; i = i + 1)
        registers[i] &lt;= 0;
end