Simple 1 bit register
Looking at these two lines:

shiftout : out std_logic_vector(1 downto 0)


and

shiftout &lt;= shiftreg(31);


The first declares shiftout as being two bits wide. The second tries to assign to this a one-bit value. Your two options are:

Redfine shiftout to be one bit wide:

shiftout : out std_logic


or change the assignment to match the output width:

shiftout &lt;= shiftreg(31 downto 30);


I suspect you want to do the first of these two options.