How to view a detailed resource utilization report on an FPGA design when implementation fails in Xilinx Vivado?
The Xilinx support page has a Q/A for this: Vivado - How to get resource utilization of one sub module?
When button to get the utilization report is greyed out, you can't get to the reports via the nice GUI. But you can still have it dumped to a file using the TCL console command:

report_utilization -hierarchical  -file path_to_output_text_file

Navigate to the output file you specified and you'll see a nice hierarchical resource utilization report.