Verilog odd behavior with multiple edge detect
Learning Verilog is one thing.  It also good to learn digital design.  Modern designs use clocks.  The synthesis tool doesn't want to make something sensitive to two different edges.
You should us a clock and either count or reset depending on the input.  You should digitally detect the edge to count up.


  always @(posedge clock) begin
    KEY3_d1 &lt= KEY[3];
    if (!KEY3_d1 && KEY[3]) begin
      mSEG7_DIG &lt= mSEG7_DIG + 1;
    else if (KEY[2]) then
      mSEG7_DIG &lt= 0;
    end
  end