What's an idiomatic way to detect posedges inside a FSM in Verilog?
(what happens if syncsignal goes high when I'm not in STATE_WAIT?)


That is a more matter of specification. What are you building? What do you want to happen when?

What you have build is a that the rising edge is only detected when you are in the WAIT state. 

If that is not what you want you should make an independent edge detection which remembers that there was at some time a rising edge. You then also have to somehow signal that, yes you have seen the rising edge and the 'there-was-a-rising-edge' flag can be cleared again:

reg there_was_a_rising_edge;
always @(posedge clock or negedge reset_n)
begin
   if (!reset_n)
      there_was_a_rising_edge &lt;= 1'b0;
   else
   begin
      if (syncsignal &amp; !oldsyncsignal)
         there_was_a_rising_edge &lt;= 1'b1;
      else
         if (state==STATE_WAIT)
            there_was_a_rising_edge &lt;= 1'b0;
   end // clocked 
end // always

....
   case (state)
   STATE_WAIT:
      if (there_was_a_rising_edge  )
         state &lt;= STATE_CONTINUE;
   ...


But that is not the end of it.
(Here is where a experienced HDL designer earns her/his pay)
The above code is such that if a new rising edge comes just when the FSM is in the WAIT_STATE, then there_was_a_rising_edge signal does not get cleared. Thus it will remain set for the next time you get into that wait state. 

If that is NOT what you want you have to change the order of the conditions:

      if (state==STATE_WAIT)
         there_was_a_rising_edge &lt;= 1'b0;
      else
         if (syncsignal &amp; !oldsyncsignal)
            there_was_a_rising_edge  &lt;= 1'b1;


Now the there_was_a_rising_edge signal always gets cleared in the WAIT_STATE and any rising edge arriving just at that time is ignored/lost.