Different voltage characteristics of CMOS NAND gate for different connections
It's a normal effect.

in a), T1 is 'on', and you sweep the gate of T2. At say the midpoint of the sweep, T2 is partially on (say 5 V on the gate), and some current is flowing through it and T1. T1 being on doesn't mean it has zero resistance, and so T2's source is not at 0 V. Therefore its gate-source voltage is not the same as Uin.

conversely, in b), T2 is 'on', and you sweep T1. Now, the Uin value is equal to T1's gate-source voltage, and so, for a given Uin value, T1 in configuration b will be more 'on' than T2 would be in configuration a.

Now, When T1 is partially on, it has the fully on T2 in its drain connection. However, when you look at the general characteristics of FETs, you'll see that the drain current saturates when the drain voltage gets to a certain level -- basically meaning that further changes in drain voltage (e.g. from a R in series with the drain) have no effect. What this means is that T2's impact on T1 is smaller than T1's impact on T2, and this is what gives the asymmetry in the curves.

Geerally, this also means that the speed of NAND gate is different for the A and B inputs. 

If you needed a perfectly symmetrical characteristic, you could add another copy of T1 &amp; T2, but interchanged and still connected between Y and GND.