3 PCB Design Question about Length Matching, Trace Position and Signal on Layer
1) It all depends on signal speed. For most JTAG, SPI, and I2C communication it is probably unnecessary, as these speeds tend to be fairly slow. USB, depending on the version, may require length matching (USB 3.0 is faster than 2.0, for example) but I have never had problems with unmatched USB traces. You could just run the signals as a differential pair to keep them roughly the same length. That way you can also control the impedance.

2) As long as you have a solid ground layer around and directly below the crystal (a pour on the same layer as the crystal, flooded around the entire connection to the processor, and a ground plane on the layer directly under the crystal) then you should be able to put signals on the other layers. Just make sure they're separated from the crystal by a ground plane.

3) I wouldn't anticipate any issues with placing some GPIO traces on the power layer. The important thing to watch out for is make sure that the traces don't cause the power plane to neck way down in any area. You also want to make sure that the pour is not forced to "detour" around your traces. You want the flow-through of your power plane to be direct and unbroken.