Decoder Expansion. Constructing a 6-to-64 decoder from 3-to-8 decoder
The input of the decoders is A[5:0]. A[5:0] has 64 possible values "000000", "000001", "000010", ..., "111111". The first three binary digits A[5:3] go to the first decoder. The last 3 binary digits A[2:0] go to the second row decoders. Each of the second row decoder would activate one of its output for each A input, but only the one whose Chip Select (CS) is activated by the first decoder actually will activate its output. Thus only one output in total is activated at a time.

Consider for example the case of A=10. In binary that is A[5:0]="001010". Split that into two parts, you get A[5:3] = "001" and A[2:0] = "010". The first decoder gets "001" (1 decimal) in its input and activates output 1. This is routed to the chip select input of decoder (2). Decoder (2) has "010" (2 decimal) in its input and activates output 2. None of the other decoders activate their output because their CS is inactive. And what a surprise: there's "10" (ten) marked at the output pin 2 of the second decoder.