On RS Latches (or Flip-Flops), NOR or NAND, via Duality Principle
Duality principle is a very powerful tool for analyzing dual circuits
in digital circuits.  Here we apply them to sequential circuits in
general and RS latches and flip-flops in particular.  The same concept
also applies to combinational circuits as well. Duality also find its
applications in analog circuits such as RL circuit and RC circuits.

I believe the appoach is the first of its kind in using duality principle to analyze sequential circuits.  The contribution of this post is to show how one can cleverly use duality principle to simplify the analysis of correspondence problem in its dual circuit.  The beauty of this approach is analysis is only done once to obtain its state table in the original circuit.  The state table of its dual is obained by simply invoking the duality principle.  It's as if we can get dual results for free.  Hence this approach enjoys a 2 to 1 advantage in terms of results to efforts. It may even become trivial once you get the hang of it.  But it's the side by side comparison for a circuits with its dual as presented in Figures 1 to 3 that actually does the dirty work.

Consider NOR gate implementation of RS latch: labeling which inputs is
R or S is completely arbitrary. Once it was decided, try to decide
which output is Q. Let's choose R on the top gate and S on the bottom
gate. NOR gate is an active high circuit, a high input uniquely
determines its low output. Suppose R = 1 which clears the top gate
output so the corresponding output in the top gate must be Q, not P.
Otherwise, it clears P contradicts to the definition of R which clears
Q. Similarly, S = 1 clears the lower gate output. The lower gate
output must be P, not Q. Otherwise, it clears Q contradicting to the
definition of S which sets Q.

Once we understand the NOR operations, NAND gate operations can be
argued similarly. But there is an easier and more elegant approach.
The idea is to use duality principle and De Morgan's Law to convert
from a latch in NOR/NOR configuration to its dual in NAND/NAND
configuration or vice versa.

Duality Principle: Switching a circuit to its dual, you simply swap
the inputs and outputs with their complements.

Therefore, a latch in NOR/NOR configuration with R and Q on top gate,
S and P on bottom gate corresponds to a latch in NAND/NAND
configuration with R' and Q' on top gate, S' and P' on bottom gate.

To show duality, I have deliberately chosen to replace Q' by P in Fig.
1 so that correspondence becomes quite obvious. Standard textbooks,
for some reasons, unintentionally have NAND gate configuration drawn
upside down (relative to NOR, see Fig. 2) which makes duality very
obscure (see A1 below).  The fact P = Q' makes a lot of people even
more confusing (see A2 below).  Shall R correspond to R' and S
correspond to S' (as shown in Fig. 1) or shall R correspond to S' and
S correspond to R' (as shown in Fig. 2 or Fig. 3)?

However, Figures 2 and 3 are indeed duality principle in disguise. In
applying duality principle, you would normally keep their positions
FIXED relative to the original circuit.  If someone hand in a possibly
dual circuit with inputs and outputs upside down and ask you to
comfirm if it is indeed a dual. You will need an alternate forms of
Duality Principle.

(A1) Alternate Duality Principle in general

Switching a circuit to its dual while simultanously making its
inputs and outputs complemented and upside down (relative to the
original circuit).  The tricky part is an up input in the original
circuit now corresponds to a down input in its dual and vice versa.
The same statement holds for its output. Please check Fig. 2 to verify 
the statements in (A1) are indeed true.

(A2) Alternate Duality Principle for circuits with complementary
outputs (to which both NOR and NAND belong):

Switching a circuit to its dual while simultanously making its
inputs complemented and upside down and leaving outputs unchanged
(relative to the original circuit). The tricky part is an up input
in the original circuit now corresponds to a down complementary input
in its dual and vice versa. Any output in the original circuit remains
unchanged and uncomplemented in its dual.
Please check Fig. 3 carefully to understand where the issues and confusion are.