Place Design error when using if/else statements in verilog
The tool is trying to turn some of your signals into clocks (as indicated by its attempt to infer a BUFG), based on your always blocks. If you're not doing sequential logic (e.g., with clocks), you shouldn't be using such blocks at all. Instead, write what you want directly:

assign led[0] = r_sw[0];
assign led[1] = r_sw[0];

assign led[7] = !r_sw[0] &amp; !r_sw[1] &amp; !l_sw[14] &amp; !l_sw[15];
assign led[8] = !r_sw[0] &amp; !r_sw[1] &amp; !l_sw[14] &amp; !l_sw[15];


etc.

In general, whenever you find yourself writing if (x) then y &lt;= 1 else Y &lt;= 0;, you should replace it with y &lt;= x;. I see this all the time, and it drives me up a wall!