Switching external clocks for an FPGA
By the sounds of it you need to split your design up a bit more. Here's how I would do it:


Run the logic that does the clock configuration on a different clock domain entirely. FPGAs frequently have some low quality internal oscillator which will be available after power on. Use this clock for driving the logic that configures the clock generator.
Feed the logic that runs off the clock synthesiser directly from the synthesiser - don't put a multiplexer in the path (well you can, but you don't need to). 
At power on, keep everything in reset except the logic in (1). Once the clock generator has been programmed, bring the rest of the logic out of reset. 


As long as you remember to add a clock resynchronisers for signals/flags that go between the two clock domains, you should be fine.

It's frequently the case in FPGA designs that you will essentially have a "management" section of the design that runs off a free-running clock source which is always available. The management hardware is there to get everything ready after the FPGA is configured - things like preparing clock sources, PLLs, and so forth. You can then use that core to bring everything else out of reset once everything is prepared.