Is the initial block in Verilog sythesizable?
Xilinx Vivado can synthesize initial blocks in some cases. For example, Vivado Synthesis Guide (page 145) shows how to initialize RAM contents.

reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
integer i;
initial for (i=0; i&lt;DEPTH; i=i+1) ram[i] = 0;
end


According to page 147, $readmemb can also be used to initialize a RAM.

reg [31:0] ram [0:63];

initial begin
    $readmemb(“rams_20c.data”, ram, 0, 63);
end


If we talk about ASIC, Design Compiler doesn't synthesize* these blocks.