Distinguishing clock domains in designs
First part of the answer: Clocks coming from the same oscillator and produced in an internal PLL have a known phase relation. The tools know this and do check that transfers from one of these clocks to another do not end in a timing violation. Make sure that you have all appropriate constraints in the design and check output of the timing reports. 

Second part of the answer: Don't do it this way. The best way is to use a single clock - 48 MHz in your case. All other clock domains can be replaced by your 48 MHz clock and a clock enable signal. For example, the 12 MHz domain is using a clock enable signal that is high in every fourth 48 MHz clock cycle. This saves a lot of trouble with clock domain crossings and even saves resources.