SMPS stability near and above switching frequency
The unity gain BW must have good phase margin at all load ranges and also good harmonic ripple attenuation which are design tradeoffs that increase complexity of the component selection.
e.g. Dissipation Factor or low ESR, Q or low DCR in the choke and FET RdsOn. The load current range affects the loop gain margin due to the impedance ratios, component values, lead-lag loop compensation filter and series-resonant frequency (SRF) of big reactors. (LC).
Although the curves are often benign well above the unity gain frequency, they are captured to ensure no spurious behaviours.  That is defined by the yellow bar on your Figure B2 on p33.
Also some switchers operate in the low MHz to reduce reactor sizes but can make it more layout critical.