VHDL Error (Simple Expression Expected)
with input select 
    led &lt;= table(to_integer(unsigned(d &amp; tmp)))
    when "0000" | "0001" | "0010" | "0011" |
         "0100" | "0101" | "0110" | "0111" |
         "1000" | "1001" | "1010" | "1011" |         
         "1100" | "1101" | "1110" | "1111"
         and ob = '1',
    ...


The syntax error occurs at the "and" clause which is not part of a valid "select" choice list.

However note that the "when" expression is equivalent to ignoring the "input" altogether so 

 with ob select 
     led &lt;= table(to_integer(unsigned(d &amp; tmp))) when '1',
     ...


You may be under the misapprehension that explicitly specifying all combinations of '0' and '1' values for "input" excluded any input values containing 'X', 'U', '-' etc (of these symbols, only one is a "don't care"). 

Indeed in simulation it may actually work; however a little thought will show that there is no synthesisable hardware primitive that can reliably do so, and unless you are writing a testbench, this is certainly the wrong approach altogether and the simple syntax error is the least of your problems.

EDIT : here's one way (untested) using both a table and a selected signal assignment, using don't cares to reduce the table size. Some further simplification may be possible.

architecture myarch of pitch_decoder_2 is

        type tbl is array (3 downto -4) of std_logic_vector(9 downto 0);

        constant table : tbl := (  
        "0111100000",  --  3
        "0011100000",  --  2
        "0001100000",  --  1
        "0000100000",  --  0
        "0000110000",  -- -1
        "0000111000",  -- -2
        "0000111100",  -- -3
        "0000111110"); -- -4

        signal sel : signed(3 downto 0);

begin

        sel   &lt;= (d xor ob) &amp; c &amp; b &amp; a;

        with sel select led &lt;=
           "1111100000" when "01--",
           table(to_integer(sel)) when "00--" | "11--",
           "0000111111" when "10--",
           "----------" when others;

end myarch;