wrong operation result in shift right arithmetic in verilog
Your problem is down to simple typos. 

In your second code you have places where you use singed_a, and others where you use signed_a. If you check the warnings from your compiler it will actually tell you this.

Basically your code ignores the input A because you are assigning it to a non-existent variable.

Secondly, your second code uses a bit shift (&gt;&gt;), not an arithmetic shift (&gt;&gt;&gt;) so will not perform sign extension (see below).



The result your second module calculates is exactly the correct result for the hardware you have described.

&gt;&gt; is the bit shift operator, which performs zero filling. It doesn't matter whether the number is signed or unsigned, it will shift in zeros to the MSBs.

The &gt;&gt;&gt; operator on the other hand is an arithmetic shift. This will perform sign extension, shifting in the MSB of the original number into the MSBs.