CMOS analog output buffer
You cannot design anything without full specs.
In this case R load and load regulation tolerance X%, voltage linearity error, BW, gain error, offset error, temp range. Vdd tolerance. Etc.
From this you choose RdsOn at some power % of load R and use complementary high gain buffered inverters (3 stages) then R ratio of 1:1 as an inverting amp like that done for 4000 series CMOS.  Excess gain lowers Zo, phase margin needs integration.
Otherwise the obvious solution is an OP Amp that does what you want or with complementary emitter followers with negative feedback and excess Vcc to increase headroom.
You are defining a problem called load regulation error which is just due to R ratio’s or active current limiting.