How do you reduce an 8 output ALU to a 4 or 3 output ALU?
Addition and subtraction have inverted constants \$C_{in}\$, we can be connected to \$(I_3 \vee I_4)\$. Then invert the subtracting value before passing to a full adder. ADD/SUBR/SUBS can be expressed as :

$$
(R \forall I_3) + (S \forall I_4) + (I_3 \vee I_4)
$$

Using the same xor inversion method you can mearge:
AND/NOTRS : \$ (R \forall I_3) \wedge S\$
EXOR/EXNOR : \$ R \forall S \forall I_3\$

This make 4 possibilities that can be decoded using three 2-to-1 muxes.







simulate this circuit &ndash; Schematic created using CircuitLab

Hint: Gate count can be reduced further by share logic with the gates inside the fulladder.