(7,4) cyclic code encoder in VHDL
You’ve actually done the hard part by drawing out your block diagram. It’s a good diagram and you’ve derived the equations that you need to perform. Unfortunately you seem to have got stuck on the implementation at the register level, so your second diagram is very incorrect, although i can see you’re thinking on the right lines as you’re showing a shift register.
What you need to implement for this application is a linear feedback shift register. I’m not going to dwell on whether your base design is right, I’m going to answer your question on how.
You need the take advantage of the fact that VHDL allows you to abstract from the hardware. If you use the right packages (ieee.numeric_std) then all you need to do is write a process containing your equations.
Something like this will work:
Q(0) &lt;= m + Q(2)
Q(1) &lt;= m + Q(0)
Q(2) &lt;= Q(1)
Don’t forget the multiplexor you’ve got in your diagram. That’s implemented with an if statement.