Parametric stabilizer circuit optimization for reducing ripple
The "trigger" behavior needs to be removed, and a smooth behavior implemented.
The fast bandwidth of the AP432SRG-7 caused oscillation. And the high loop gain
1) the Pch FET
2) the NPN with its grounded emitter
3) the AP432 with 10,000Hz bandwidth
means this loop will skeg/flip from one state to another.

Try a HUGE cap on base of NPN, to ensure the oscillation will slow down.

Then implement a VERY LOW GAIN error amplifier, such as PNP, base tied to top of ShuntReg, with 100Kohm from Emitter to Vout, and collector tied to base of NPN. You need VERY LOW gain in the error amplifier, because of the high gain in PChan and in the NPN.