VHDL debouncer circuit
I'm not familiar with VHDL, but it seems to be doing this: output Deb_Sig is 1 only when input Sig has been 0->1->1 (time grows to the right), sampled at the rising edges of CLK. Otherwise, Deb_Sig is 0. So, the module detects rising edges at the input, and only those ones that are followed by a high level that, after sampling, turns into at least two logic 1 samples. That way, it will ignore pulses that are high during only one sampling instant, which will be considered noise.

I would say that your code synthesizes something equivalent to this:



Curiously enough, it may ignore high pulses that last 2T-epsilon (where T is the sampling period), and detect high pulses that last T+epsilon (which is shorter than 2T-epsilon), if the sampling is such that it sees only one logic 1 in the former pulse, but two logic 1s in the latter one.