what is critical in handling Heat dissipation of mosfet - Source or Drain!
You will want a similar number of vias on both source and drain pad.  I would also recommend having a similar pad size.  For the most part, all the current passing through one will pass through the other.

The best method would be to figure out what the maximum current this FET will provide.  From here, you can consult the design rules or process design kit (PDK) to find what the resistance per via is for each layer.  You would want to make sure you have enough vias (at each layer, and for all layers in series up to the final port) so that the combined resistance in parallel is low enough to only cause a negligible voltage drop.

A lot of the heat in planar technology, especially in this case, is caused by choking around vias.  I would always err on the side of having too many rather than too few, unless you are severely area constrained.  There are all sorts of failure mechanisms for vias under high current -- electromigration, 'peeling', etc.

I don't know what sorts of design software you have access to but there are quite a few vendors that can provide 'heat' maps for a given layout and set of stimulus.  If you have this sort of tool you can simply add vias to the layers which are more red, iteratively, until the voltage drop to the top level is acceptable.