What kind of hardware multiplier do modern processors use?
FPGAs have hardware multipliers on them these days (for example, the DSP48 MAC block in Xilinx architectures.)

That said, it probably depends on the size of the MPY. Back when I was working on this stuff (1980s, at Weitek) modified Booth's algorithm was all the rage for 16, 32 and 64-bit sizes. Now? Not sure. Since then there's the Carry-save architecture and other proposals. It's probably secret sauce beyond that.