How can an input signal to an FPGA be determined as the clock signal?
By definition, any signal whose edges are used to trigger other activity is a clock. This can be denoted in HDL by creating a process that is controlled at least in part by a signal's rising or falling edges. In a schematic diagram, this is denoted by connecting the signal to the clock input of one or more edge-triggered flip-flop primitives.

Most FPGAs are optimized for synchronous design techniques and have a limited number of signals (maybe 8 or 16) that can be used as clocks, driven by the fact that special on-chip resources are used to distribute clocks with low skew across the chip. If your design has too many signals used as clocks, the synthesis tools will complain.

What exactly are you trying to do?