How to implement a Muller C-element in a LUT4 of a FPGA?
Looks like it should be possible to implement up to a 3 input C element on a Spartan 3. On a Spartan 6 with 6 input LUTs, you should be able to implement 5 input C elements. Now, I'm not entirely sure if the synthesizer will handle the feedback path correctly or not. I would recommend synthesizing a single gate and then check the mapped schematic to ensure that it is implemented correctly. If that doesn't work, then you may have to directly instantiate LUT primitives for your C elements. This probably won't be so bad if you just do it once for a C element module that you can use many times. The other problem could be the routing of the feedback path. Not sure that could be done about that though. Maybe setting maxdelay would help. Maybe not. You'll just have to do some experimenting.

Now, timing driven place and route is an entirely different animal. I have no idea how that will work with an asynchronous design. The result could be very sub-optimal.