Reset the configuration of FPGA without reprogramming
If you unplug the DDR3 SDRAM module, the configuration insided the module is lost. After the DDR3 SDRAM is plugged in again, the RAM itself must be reinitialized. For example, the desired CAS latency and burst length must be configured (inside the module!) and the DCM (of the module) reset (if used).

This configuration is done by the memory controller, typically after power-up or reset. The FPGA boards from Xilinx etc. typically have a button CPU_RESET (or like) to assert a reset of the whole Microblaze-based system. If pushing this button helps, then you can also trigger the attached signal by your own to restart the system. EDIT: Just restarting the Microblaze is not sufficient, the memory controller must be reset too.

Just restarting the memory controller might also be an option, if the appropiate reset signal is accessible in your design. But, the state of operating system / application would be typically lost anyway.