What will a pin-header connection do to my voltage supply integrity?
Assume 10nH motherboard PCB + 10nH connector + another 10nH daughterboard PCB + 5nH in package/bondwires (not socket, right/).

Thus your system has to handle 10 + 10 + 10 + 5 = 35 nanoHenries.

Assuming 100 milliAmps switch in 1 nanosecond.

The inductive kick Vbounce = L * dI/dT


Vbounce = 35nH * 0.1 amp/1nanoSecond == 3.5 volts.


What size cap?  Assume you want only 25 millivolt rail sag.

Using I = C * dV/dT, and rearranging to have C = I * dT / dV


C = 0.1 amp * 1nSec / 0.025 volt == (nano) * 0.1/0.025 == 4 nanoFarads at least.


So I suggest the oft-bantered 0.1uF, at least, on your daughterboard.

And why not place a bulk storage cap also, so bursts of clocking don't cause VDD
sags on the daughterboard. Remember the 35nH is not your friend.

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I'm glad the 35 nanoHenries makes you nervous, the 3.5 volts is scary, so you decided to place large capacitors very near the IC under test.

Regarding the use of 0.1uF ---- intense switching activity will demand much more charge, as you know. If that is your usage, then LARGE caps are needed.
Its your call.