How Verilog decides upon simultaneous events
The Verilog standard guarantees that all events within a begin..end block scheduled for the same simulation time will be processed in the order they are declared. Other than in this specific scenario every other event may be taken out of the queue in any order.

With this said, any behavior can be expected because both events are scheduled for the same simulation time in different code blocks.
Nevertheless, the behavior you have is what is generally accepted as correct, because data is not sampled in the same simulation time where it is generated.

Things you could do to improve predictability:


Generate your clock using a blocking assignment.

always #10 clk = ~clk;

Generate stimuli on clock events.

initial
begin
    repeat (2) @(posedge clk)
        x &lt;= 1;
end



This coding will, in general, guarantee that the RTL simulation will behave as the final gatelevel netlist without requiring data delays. In an RTL simulation, data must not be generated and sampled in the same simulation time.