Designing circuit with a FIR filter with feedback
There are fundamentally two approaches to FIR in an FPGA and they trade area for speed (This is the general tradeoff in an fpga).

You can build a FIR as a mess of registers (1/z), multipliers and adders that will produce a result in one clock cycle, the cycle may be fairly slow because of the adder tree and the area will be large because of the DSP block and adder chain usage but it will work. For higher performance you can pipeline the adder tree, still one result per clock but now with latency, but you can clock it faster.

The other (and far more common approach) is to have a clock running at a significant multiple of your sample rate, then one ram (Historical data), one rom (coefficients) a few counters, a single multiply/acc core and a state machine gets you a result in one sample clock, but it takes approximately one high speed clock cycle per tap.  

There are obviously hybrid approaches that trade speed and area, but those are the common ways you see this done.

Obviously, very long filters can favor fourier based approaches, but that is a whole other can of worms.