PLL placing fails on Lattice 5LP1K
I remember that I had some trouble with the PLL instantiation (SB_PLL40_CORE) for a ICE40UL1K-CM36A. IIRC it was the combination of "which input and output to use". In my case the solution was to avoid PLLOUTCORE and use PLLOUTGLOBAL instead. I think I let the tool decide where to place the clock and locked that pin (F2) later.

So my recommendation: check if different combination of CORE vs GLOBAL make any difference if this does not help let the tool decide where to place the clkin pin. Maybe you are lucky and there is another pin which is not G6 and the tool is fine with.