Is it ok to use both rising and falling egde in this VHDL design?
Yes, you can, but it's not recommended. You will need to have the hardware synthesize at twice the clock rate now - a 100MHz bus needs to be set up at 200MHz because the data only has half the time to propagate. You have effectively made it DDR.

It seems that you are actually misunderstanding how a process works. All outputs within a process are scheduled to be presented on the output upon the next clock cycle. So everything you code within that process is actually happening in parallel and must stabilize before the next clock comes along, which is when the outputs will be posted.