MIPS Pipeline Forwarding to MEM
Remember that the result of ADDI is known by the end of cycle 2 -- specifically our new value for R1 is going to be available:


at cycle 3 (M stage) in E/M, and
at cycle 4 (W stage) in M/W 


(where E/M and M/W are pipeline registers). 

It is available at both these places because we must continue to carry it along until we reach the write-back stage.

Then, looking at just an SW instruction by itself, there are two places we could forward the word data in time for SW:


at cycle 4 (E stage) superseding the value of R1 that was in D/E
at cycle 5 (M stage) superseding the value of R1 that was in E/M


Your problem constraints permit for M->E forwarding and E->E forwarding. M->E works out here when you look at cycle 4. This is because cycle 4 is not too late to forward for the SW, and our R1 value is available at that moment from register M/W.