Verilog Testbench with Pipelined Modules
Create a pipeline for the results in your testbench:

   parameter PIPE = 5;
   reg [63:0] result [1:PIPE];

   always@(posedge clk) 
    begin
     Aj_d &lt;= i_Aj;
     Ak_d &lt;= i_Ak;
    end

    always@(Aj_d or Ak_d) 
    begin
      result[1] &lt;= Aj_d*Ak_d;
      for (int i=2; i&lt;=PIPE; i++) result[i] &lt;= result[i-1];
    end  

   always@(result[PIPE]) 
    begin
     $display("CLK=%t,Aj=%d,Ak=%d,result=%d,actual=%d", $time,Aj_d,Ak_d,result[PIPE],o_Ai);
     if(result[PIPE] !== o_Ai)
      $display("ERROR: %t,sj=%d,sk=%d,result=%d,actual=%d", $time,Aj_d,Ak_d,result[PIPE],o_Ai);
     end