SystemVerilog randomization for a fixed sequence of values
You can use the post_randomize function to increment the count:
class packet;
 rand bit [3:0] start_addr;
 rand bit [3:0] end_addr;
 int count=0;
 constraint start_addr_c { 
    if (count &lt; 3) {
        start_addr == 0;
    } else {
        start_addr == 'hf;
    }
 }
  
 function void post_randomize;
   $display(&quot;count = %0d&quot;,count);
   count++;
 endfunction
endclass

module func_constr;
 initial begin
   packet pkt;
   pkt = new();
   repeat (5) begin
     void'(pkt.randomize());
     $display(&quot;\tstart_addr = %0d &quot;, pkt.start_addr);
   end
 end
endmodule

Prints:
count = 0
    start_addr = 0 
count = 1
    start_addr = 0 
count = 2
    start_addr = 0 
count = 3
    start_addr = 15 
count = 4
    start_addr = 15