Does dividing a clock increase its jitter?
As long as the divider is using only one edge of the input clock, and only one edge of the output clock is being used by the ADC, then no, there will be no significant increase in jitter.
The output edges will have the same peak-to-peak jitter as the input edges, in terms of absolute time (ps or ns). But expressed as a fraction of the output clock period (% UI), the jitter will be reduced by the division ratio.