register enable line usage in `case` block (verilog synthesis for altera cpld)
Isn't this much less space-efficient than the design I was expecting?


No; it's actually better.

Consider the structure of the LE in the MAX II CPLD (from MAX II Architecture). I've highlighted an important detail:



The input to the register's clock enable does not pass through the LUT. It must be driven by one of the two clock enable signals which are shared across the LAB.

Your design would require each register to be implemented in a separate LAB, which will run you out of space very rapidly. The synthesizer's design allows each of the registers to be implemented within a single LE, probably all within a single LAB.