BlockRAM location constraints (Xilinx)
OK, so after some try and error, here is how I managed to do it: 

First an AREA_GROUP which spans the part of the design which shall be constrained must be declared (in the projects UCF file). 

INST "my_module/*" AREA_GROUP="pblock_my_module";


This creates an AREA_GROUP containing everything in the design hierarchy "below" my_module. 
Now a range for the block RAMs within this AREA_GROUP can be defined.

AREA_GROUP "pblock_my_module" RANGE=RAMB8_X0Y0:RAMB8_X4Y12;


The values for the range can be obtained from the vendors floorplanning tools (e.g. Xilinx ISE FPGA Editor). In the example above, all block RAMs (either inferred or instantiated) within my_module will be placed in the lower left corner of the FPGA. Since there are much more block RAMs available in that region (RANGE=RAMB8_X0Y0:RAMB8_X4Y12) than are required, this is no "hard" placement of the block RAMs, like achieved by the LOC constraint, but more flexible.

For details see http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/Floorplanning_Methodology_Guide.pdf