Differential Impedance vs length matching vs IC manufacturer requirements
You should not minimize the impedance, but minimize the places where the impedance is uncontrolled. In other words: avoid vias and accordions.
If you have vias, minimize their stub length. TI's High-Speed Interface Layout Guidelines say:

3.6 Via Discontinuity Mitigation
A via presents a short section of change in geometry to a trace and can appear as a capacitive and/or an inductived iscontinuity. These discontinuities result in reflections and some degradation of a signal as it travels through the via. Reduce the overall via stub length to minimize the negative impacts of vias (and associated via stubs).
Because longer via stubs resonate at lower frequencies and increase insertion loss, keep these stubs as short as possible. In most cases, the stub portion of the via present significantly more signal degradation than the signal portion of the via. TI recommends keeping via stubs to less than 15 mils. Longer stubs must be back-drilled.


Also see the entire rest of this document.
The 3W rule applies only to the distance between a single-ended signal and other, unrelated traces. The two traces of a differential signal should be near each other.
And for differential signals, there is a 5W rule, and adjacent clock signals require an even higher distance: