Xilinx FPGA Input data timing constraint
I do understand, that you have an internal clock SYS_CLK, which you use to drive the state machine generating SPI_CLK.

The flip-flop which generates SPI_CLK should be located in IOB, to ensure  deterministic timing between SYS_CLK and SPI_CLK (you can specify the required maximum delay for SPI_CLK, using the OFFSET OUT).

Then you can specify your constraints using OFFSET IN (for MOSI) and OFFSET OUT (for MISO) with respect to SYS_CLK, considering the delay between SYS_CLK and SPI_CLK.