In SystemVerilog, must nets be declared with the **logic** data type?
I used to have that book (left it at my old job). You can definitely use wire still in SV. Stu's book is great, but it sounds like this is a mistake (RIP Stu) or there's surrounding text that you omitted that makes it clear. Go to the LRM to be sure.

Edit : Just realized this was about bit vs logic. Stu's book is specifically about synthesizable code. Maybe that's why he says only logic is OK?