Do smaller transistors improve computational efficiency because they decrease the duration of signal transfer?
less surface area per transistor means less signal travel time between transistors, so more compute per transistor.


This is basically true; the other important factor is that smaller, narrower gates have a lower gate capacitance. The time taken to switch a transistor is approximately(+) the time taken to charge its capacitance through the resistance of the wires and driving transistor.


  smaller transistor size means less heat production per operation


Only partly true - they take less energy to drive on the input, but all other things being equal a smaller transistor will have a higher on-resistance and emit more heat. This is increasingly a problem and why Intel is building chips where you can't have all the parts of the processor on at once.


  less surface area per transistor means less raw material cost per transistor.


Raw material cost is pretty trivial. Processing cost for materials is huge, and is where most of the non-design costs come from. The silicon wafers are expensive to make and very expensive to process, especially in the newer, narrower processs. Costs of the order of $10k - $20k for an eight-inch circular wafer. So the more chips you can fit on a wafer the better.

There is also the yield issue. If you imagine manufacturing defects being randomly distributed, put (say) ten spots on the wafer. Those ten spots will be failures. This means that doing 100 chips/wafer will waste 10% of them, but 1000 chips/wafer will waste 1% of them.

(+) yes I know Elmore delay is a simplification