K50-HC0CSE25.0000MR Clock signal not being driven to correct logic levels
It appears you have excess load on the clock signal at 2.8V for 5V logic.

The Kyocera spec indicate Vo="1" at 0.9Vcc @ 16mA so for Vcc=5V this drop represents 0.1*5V=0.5V @16mA Zout = 0.5V/16mA = 31Ω, which is  good.

This means if you also had external clk input with 50Ω terminator which loads your Kyocera output , it should reach 50/(50+31)*5V=3.1V unless reduced by excess capacitive loading. Threshold nom is 2.5V. 

You could offer more design details if you want a better answer:


schema,  layout, waveforms, probe method, DC Voltage on each DC pin.


the series R on design kit schematic are DNI but 25 Ω might improve clock symmetry.  Pullup/down 100~330 Ω each also might improve integrity instead of 50Ω for ext. clock ( if used), Otherwise look for problems, this is not normal.