Generation of square wave using Veilog
For a 4 MHz input clk and a 1 kHz output clock dac_out, we need a counter which counts 

$$n=\frac{f_{in}}{f_{out}} = \frac{4\,MHz}{1\,kHz} = 4000$$

cycles of the input clk and then wraps to zero, i.e. it counts from 0 to \$n-1\$ . This defines the period of the output clock. A duty cycle of 50% (x%) is defined by setting the output to high for the first

$$m = \frac{x\%}{100\%}\cdot n = \frac{50\%}{100\%}\cdot 4000 = 2000$$

cycles, and low for the rest of the period.

I have improved your code for a better understanding:

module square_wave(clk,rst,dac_out);
   input clk; // assuming 1 MHz
   input rst;
   output reg dac_out;
   reg [11:0]  counter; // 12-bit for numbers up to 3999

   always @(posedge clk)
     begin
        if (rst == 1'b1  ||  counter == 12'd3999) // period, count from 0 to n-1
          counter &lt;= 0;
        else
          counter &lt;= counter + 1'b1;

        // synchronous output without glitches
        if (rst == 1'b0  &amp;&amp;  counter &lt; 12'd2000) // duty cycle, m cycles high
          dac_out = 1'b1;
        else
          dac_out = 1'b0;
      end
endmodule // square_wave


By changing the marked counter checks, you can adjust the period and the duty cycle of the output clock.
For example, a period of \$n=2000\$ cycles and duty cycle with \$m=800\$ gives the required output clock.