$random in Verilog doesn't seem to be working
If you output all 5 random values you generate you can see that you get different values: EDA Playground.

The point of a seed is, given the same seed you can generate the same sequence. This allows you to have randomised tests but when one instance fails you can plugin the seed that was used and rerun the same test.

module tt;
  integer kk;
  integer seed = 1; //change this for different sequence
  initial
    begin
      repeat(5) begin
        kk=$random(seed) % 10;
        $display("%d",kk);
      end
    end

endmodule