What is the diference between concurrent 2 "when-then", sequential 2 "if-then" and "if-elsif" statements in VHDL?
Why aren't these 3 ways of doing this the same in this case?


The behaviour of the three codes is NOT identical.

Number one:

R &lt;= R + 1      when (rising_edge(clk))          else
 "00000000" when (rising_edge(btn_center))   else
 R;


R has to change on a rising clock edge, but if there is no rising clock edge it has to reset on a rising btn_center edge.
There exists no hardware with this behavior. You have register with asynchronous reset and/or set but the asynchronous input is level sensitive, not (rising) edge sensitive. Also the rising_edge of the clk has to override the reset. 

Number two:

process(clk, btn_center)
begin
    if rising_edge(clk) then
        R &lt;= R + 1;
    elsif btn_center = '1' then
        R &lt;= "00000000";
    end if;
end process;


R has to change on a rising clock edge, but if there is no rising clock edge it has to reset on a btn_center being one.
There exists no hardware with this behavior. It is some sort of register with asynchronous reset and/or set but the asynchronous behaviour is overridden by a clock edge. 

Number three:

process(clk, btn_center)
begin
    if rising_edge(clk) then
        R &lt;= R + 1;
    end if;
    if btn_center = '1' then
        R &lt;= "00000000";
    end if;
end process;


This one we have to deal with differently. You have two independent 'if' statements so the second one overrides the first one. Hence we have to start with the second one:
If btn_center is one R is set to zero, else if there is a rising edge R is incremented.
This is a typical register with an asynchronous reset