Need help understanding how to calculate tpd while static hazards are involved
There are 2 paths for X and 3 paths for Y to F. You can see it both in schematic and functional equation.

\$F= (X!+Y!)\cdot ((X+Y!)\cdot Y)~~~\$    or
\$F=(X!+Y!)\cdot (X\cdot Y+Y\cdot Y!))\$

If input = LH we use the inverted delay tHL for the inverter output and same polarity for OR,AND.

Thus the metastable transition times may be added up as follows. 


We see the stable F=0 but transitions for X,X! and Y,Y! may be added up to determine the worst case glitch with F=1. 


  A better version of this could be an edge detector and often done with edge-type logic phase-detectors used in PLL's.  Can you compute the Y glitch?  What about X?


FYI... The transitions are based on a fixed load capacitance like 15 pF for tLH or tHL due to the min/max R=RdsOn  results in dV/dt=Vdd/T(~RC) due to PFETs used for tLH and NFETs used for tHL in addition with internal delays.