First attempt at DFF VHDL
You could try ghdl which is available for Windows, OS X, Linux and likely Free BSD.  (And you can comment out the -- USE ieee.std_logic_arith.all; )

library ieee;
use ieee.std_logic_1164.all;

entity dff_tb is

end entity dff_tb;

architecture behaviour of dff_tb is
-- component instantion leaves the possibility of a configuration specification
component dff   
    port (
        d:      in  std_logic;
        clk:    in  std_logic;
        -- rst:    in  std_logic;
        q:      out std_logic
    );
end component dff;

     signal d:      std_logic := '0';
     signal clk:    std_logic := '0';
     -- signal rst:    std_logic := '1';
     signal q:      std_logic;
begin
DUT: work
       port map (
         d =&gt; d,
         clk =&gt; clk,
--         rst =&gt; rst,
         q =&gt; q
       );

-- Stimulus:

CLOCK:           
    process     
    begin        
        wait for 20 ns;
        clk &lt;= not clk;
        if Now &gt; 400 ns then  -- stop clock after stmulus expires
            wait;
        end if;
    end process CLOCK;

-- RESET:
--     process
--     begin
--         wait for 60 ns;
--         rst &lt;= '0';
--         wait;           -- done with reset
--     end process RESET;
--     
DATA:
    process
    begin
        wait for 80 ns;
        d &lt;= '1';
        wait for 40 ns;
        d &lt;= '0';
        wait for 80 ns;
        d &lt;= '1';
        wait for 120 ns;
        d &lt;= '0';
        wait for 40 ns;
        wait;
    end process DATA;
end behaviour;


I borrowed this from a nearly identical effort with a reset.


  ghdl -a dff.vhdl   # includes appended test bench code above
  
  ghd -e dff_tb
  
  ghdl -r dff_tb --wave=dff_tb.ghw
  
  gtkwave dff_tb.ghw


( setup signal display), yields:



There's nothing wrong with your D flip flop.