Index into std_logic_vector using signal
Yes, it is possible for every reg bit to be fed by any of the input bits as long as upper1, lower1, upper2 and lower2 are within the range of the respective vvectors.

Note that any reg bits that aren't specified by the range between upper1 and lower1 will be unchanged (forming a latch in a combinatorial implementation e.g. concurrent assignment or an unchanged output of a flipflop in a sequential design e.g. clocked process) and any of the input bits not covered in the range of upper2 to lower2 will be ignored.

As Eugene_Sh commented, it will be done using multiplexers.