At both posedge and negedge in Verilog?
Easily.

Schematics:



Code (CLK50 is clock to be doubled):

reg r_clk50=0;

wire w_xor_clk50=(r_clk50 ^ CLK50);

always@(posedge w_xor_clk50) begin

r_clk50=~r_clk50;


// your code on both neg/pos

end