verlilog simualte a port pin with switchable pull up
There certainly is a pullup in Verilog

pullup(signal);


This will drive a "pull" strength 1 on the signal when no other drivers are on the net.

Another way is to declare the signal as a tri1 instead of a basic wire. This puts an implicit pullup on the net, but you need to be careful when making port connections of dissimilar net types. See tabe 23-1 in the 1800-2012 LRM.