What is the standard way to halt a VHDL testbench after a certain time period?
Two ways are commonly used:

Stop the clock (or clocks). That way there are no more events, and the simulation stops. Sometimes, there is a signal (for instance called done) that turns of the clock generator. The testbench asserts the done signal when all tests are completed.

Report a failure. This is not so elegant, but many people use it. A severity of failure will cause the simulator to stop.
report "simulation finished successfully" severity FAILURE;

Stop procedure A third way, only available since VHDL 2008 is to call the procedure stop, in the env package of the std library. For instance, like this: std.env.stop;