Passive reset circuit for multi-chip game design
Bulking the cap to a few 10s of uF (at least 3us of low reset pulse is expected during power on.. Currently, it looks like it is marginal.. ) should improve reset timing. 

I would short both reset pins together (by replacing diode with 0 ohm resistor) and I don't see any negative effect of the same. What is the reason for D2? It is also avoiding press switch reset to provide reset to this display by keeping the reset pin above forward voltage drop of the diode. 

If possible, I would use a dedicated reset generator ICs too but I am not sure about the constraints you have. 


Place a 100nF cap if possible near VCC pin of the display module.
10k pull up for MCU is missing currently. It will not hurt to have it pulled high to VCC via 10k.


Please also share the waveform shape for first power on subsequent power on. 

When Reset button is pressed:
The capacitor immediately discharges through the switch. The reset pin of both MCU and the display module will be held to ground.

When reset button is released:
The capacitor slowly charges to 3 V via the 10k resistor. 3RC time is roughly 3 * 10k * 100n which is 3 mili seconds.

Hence, the current capacitor resistor way too small to generate a low pulse of 3us. Increasing capacitor value to higher value will help.

When power is removed:
The charge in this capacitor is discharged via diode which is in parallel with the Resistor in KiCAD schematics version. Hence, discharge happens faster.