Line Decoder Logic Race
It's quite uncommon for inputs to arrive in-phase with the clock.  The usual design is for inputs to be sampled at the rising edge of the clock.  You see this in the 7474 you use; it triggers on the rising edge.  See, for instance, https://commons.m.wikimedia.org/wiki/File:SPI_timing_diagram2.svg .

If you allow inputs to come in at the same time as the clock, you're going to have hazards.  If nothing else, there's the race of the input vs the clock!  As you try to design around that, you usually introduce hazards in other stages - as you've seen here.

That's one reason that you often see timing diagrams showing rise and fall times (as in the above-linked example).  It makes it more clear when your timings are introducing hazards.

You may want to draw a Karnaugh map for your circuit to identify hazards and make sure that you're ok.