FPGA - synchronise “very close” clock from signal
No two clocks will ever perfectly match.  The method of determining the true clock frequency from the data is called &quot;clock recovery&quot;.
If you know the nominal bit rate, then one straightforward method that doesn't require use of a PLL/DCM block  is to over-sample the data and look for edges.  Normally you would need to over sample by at least 4X the bit rate.  Here is how it works...

Create a clock in your part that is 4X the bit rate.  In the case of a 65MHz bit rate this is a 260MHz clock.

Using the 260Mhz clock double or triple register the incoming bits to avoid meta-stability issues.  These types of issues can occur if an input signal changes very close to a clock edge.  This is almost guaranteed to happen when sampling data using a different clock from which the data was generated.

Optionally do an extra two register stages and do a 2 out of 3 majority vote on the last three stages.  This will reduce false detection of edges due to noise, which becomes important in the next step since you are using edges in the data to find the clock rate.

Make a two bit free running counter that counts from 0 to 3 and then rolls over back to 0.  The counter is clocked by the 260MHz clock.

Whenever you see a 0 to 1 or 1 to 0 transition on the input data then assume you are at a clock edge and reset the counter to 1 (cnt &lt;= &quot;01&quot;).

Whenever the counter has a value of 2 (cnt = &quot;10&quot;) use the output of your majority vote as your input sample.  And if you are keeping a pixel count, also increment that.


I have personally used the above method to successfully recover the clock on serial data up to 100Mbps.
Depending on whether the incoming data is slightly faster or slower than your clock the counter will skip one tick or hold an extra tick to adjust the count rate to match the data.
For a slower data rate you will see something like... ...0,1,2,3,0,1,2,3,0,1,1,2,3,0,1,2,3,0,1,2,3...
For a faster data rate you will see something like... ...0,1,2,3,0,1,2,3,1,2,3,0,1,2,3,0,1,2,3...
There is another method where you can do the 4X over-sampling using two clocks that are the same rate as your pixel clock but 90 degrees out of phase.  By sampling into four registers (one on rising and one on falling for each clock) you can achieve the same effect as is done with the counter based setup above.  The maximum possible pixel rates are higher for that method, but the logic is a little more complex.