Efficiently calculate \$-x-y\$ using a single adder
Premature optimization is the root of all evil.


--Donald Knuth

If you want to do it efficiently, let the synthesis tools choose the best implementation. Just use an HDL to describe the behavior you want. Most FPGAs include some kind of optimized structures for addition, and if you try to force the synthesizer to use some bizarre method that looks good on paper you may get very poor results.