Want to output data on GPIOs in parallel, what is the delay between each pin?
Depends on how you wire up the shift registers.  Usually shift registers will have three input pins: data, clock, and latch.  Rising edge on clock will shift in/through a data bit, rising edge on latch will transfer the contents of the internal serial registers to the parallel output registers.  So if you tie all of the latch pins together and drive them at the same time, all of the shift register outputs will update at nominally the same time (within a few ns).  If you want the least skew between the outputs, this is the way to do it.