Verilog outputting specific bit from register to output; getting constant 1's
I think the issue is most likely down to a combination of not setting the correct bit widths for constants, and using blocking assignments.

Generally it is important to set the width of any constants you use. Not only does this eliminate warnings from the synthesiser from truncation of signals, but it also helps give the synthesiser a better impression of what you are trying to infer. Remember, you are not writing code like you would for an Arduino, you are describing hardware.

Because you are describing hardware, it doesn't actually matter how many lines of code you take up - reducing the number of lines doesn't necessarily have any impact on the size of the design, it just makes it harder to read for both you and the synthesis tools. To that end, split up your design into blocks - use multiple always blocks for different signal groups. If you have a counter, use a separate block for it so it is clear what code is for the counter - you can even put it in a separate module if you want to make the RTL output easier to read.

It is also good practice to stick to non-blocking assignments. I'm not going to go into details on the differences as there are questions both here and on StackOverflow that describe them nicely. But suffice it to say, there are subtle differences that can catch you out if you are not careful. Using all non-blocking helps to keep these subtleties at bay, but I accept it also takes a little extra thought because it reinforces the fact that this is an HDL language not a procedural one.

With the above in mind, I have tidied up your code based on the above. The counter is separated from the other signals, only non-blocking statements are being used, and I have fixed the constant widths:

module fpgaread(ARDUINOclk, FPGAclk, FPGAdata);

input ARDUINOclk;
output reg FPGAdata;
output reg FPGAclk;


reg [15:0] count= 16'd0;
reg [127:0] t = 128'd3542638353836;

//Counter
always @ (posedge ARDUINOclk) begin
    if (count &lt; 16'd256) begin
        count &lt;= count + 16'd1;
    end else begin
        count &lt;= 16'd0;
    end
end

//External interface
always @ (posedge ARDUINOclk) begin
    if (!count[0]) begin //see if it is even by checking the LSB. You can use %2 if you want, but in complex cases it can infer horrid logic.
        FPGAclk &lt;= 1'b0; //Falling edge
    end else if (count &lt; 16'd256) begin
        FPGAclk &lt;= 1'b1; //Rising edge
        FPGAdata &lt;= t[count[15:1]]; //data goes out on rising edge.
    end
end

endmodule


As a result, the inferred RTL is now this:



Much better.