Is inverting the output of a CMOS network a bad practice?
When implemented in CMOS, simple inverting logic gates take one stage, that includes inverter, NAND, NOR.

Non-inverting logic gates take two stages. For example, a buffer would actually be two inverters back to back. An AND gate would actually be a NAND gate plus an inverter...

I assume your professor did the following:
\$Y = A + B * C = \overline{\overline{A} * (\overline{B * C})}\$
So the actual logic required are one inverter (for A), one NAND (for B,C), one NAND (final output).

If implemented as you suggested, it would actually be like:
\$Y = A + B * C = \overline{(\overline{A + \overline{(\overline{B * C})}})}\$
So it would be an inverter+NAND (for B,C), an inverter+NOR (final output).

So it takes one extra inverter -- not so bad in this case. But there is a big speed disadvantage, 4 levels vs 2.

This quote "he said there won't be any sense in using CMOS if used that way" may have lost something in translation. But I am guessing that your professor was trying to convey the fact that inverting logic gates are the natural building blocks of CMOS logic and are in general more efficient than the non-inverting counterparts.