FPGA Simulation - VHDL Testbench
It all depends on what you want to simulate. 

It is pretty easy to create a test bench to create a clock, set up a few IOs etc, but it gets much more complicated if you want to simulate USB or other protocols.

This web page will give you a pretty good overall understanding on how to do this:

FPGA programming step by step

There are some commercial tools to help you with creation of TBs, but there are also free tools such as "The VHDL Test Bench" to help you creating the TB faster and easier.

For a large project like yours (I assume it is large since you have 4 FPGAs in your design and lots of IPs), I would suggest you sit down and decide WHAT you want to test, what is your goal with the simulation and how much time do you want to spend on doing this. Then make a list of the blocks you want to test and either find stimuli files for them or write them yourself.