What options do I have when synthesising control registers?
You have to pay attention EVERY time you cross clock domains.  For each signal, you need to analyze it to see if special logic is required or not.  If you don't then you will eventually get burned, and probably burned badly.  It's possible that much of your logic doesn't need special synchronization, but you can't just assume that nothing is needed.

One thing that is super important, but often overlooked by even experts, is that you cannot just double-register (or double clock) busses (std_logic_vector in VHDL).  Doing so would eliminate metastability issues, but not data errors due to skew between bits in the bus.  Special logic is required for these cases.