RISC-V Arithmetic Shift vs Operator "<<<"
The RISC-V implementation explicitly creates a barrel shifter. A good Verilog compiler would create the same implementation from the &lt;&lt;&lt; operator if that operator were used in a combinational procedural block. Since you didn't show us the entirety of the block I can't be sure about this. It's possible that this code could be part of a synchronous block, even though the code doesn't use non-blocking assignments, but I doubt it.

The code that you suggest is a synchronous block requiring that the shift be performed in a single cycle.