Xilinx PCIe Integrated Endpoint - Using the other transceiver on the tile
Looks like there is an option for doing that on the last page of the wizard, according to the manual. Is there some reason you can't reconfigure the endpoint IP core to use the correct transceiver channel?

Edit: Just used coregen to generate a PCIe core for xc6slx75t-fgg676 and I had no issues selecting that specific transceiver.  The example design lists the PCIe transceiver pins as B8, A8, D9, and C9.  So just reconfigure your core with coregen and you should be good to go.  

Edit 2: NVM, just realized that you want to use one channel of the GTP transceiver for PCIe and the other channel for something else.  It looks like you may need to go tinkering in the bowels of the coregen generated code, but it seems like it should be doable.  The generated code seems to use transceiver wizard generated code for the GTP portion, so it very well could be possible to either connect the hard core to a properly reconfigured transceiver wizard core OR to bring out the required interfaces of the transceiver in the coregen generated files for the PCIe core.  The PCIe hard core is just an instantiation of the PCIE_A1 primitive, so I don't think there will be any issues with reworking the coregen output to do what you need.