PCIe - EqualizationPhase
PCIe introduced the Equalization state in the LTSSM (Link Training Status State Machine) in version 3 due to the fact it is expected to run in the same environment (physical tracks) as versions 1 and 2. (Infiniband introduced this in 2003 for the 10 Gb/sec part of the standard).

Another issue is that at link--up, each of the link partners has no way of knowing how far apart they are and equalization is necessary in any link, but the amount to apply is distance dependent - too much equalization is as bad as too little so a receiver can ask for the other end to either increase or decrease the amount of transmit equalization as necessary.

Here is the LTSSM with the recovery block highlighted:


Image credit - LeCroy

To establish an 8G link, the link partners come up at 2.5G and provided each end advertises 8G, enter the recovery state and go through this 1 or more times to establish a low error rate link by requesting new equalization settings (which may be either up or down); this is where the receivers at each end of the link request new settings from the link partner transmitters - once it is established the LTSSM moves back to L0.

The number of equalization requests can be quite high, incidentally; it is not unusual to see in excess of 20 before the link partners agree on a link setting.

The recovery block also re-establishes timing lock.

To move to 16G, the same procedure is used.

Moving to 16G from 2.5G may fail as the link might drop out completely; moving to 16G via 8G is less of an issue which is why for PCIe V4 the speeds go from 2.5G to 8G and then to 16G (assuming both ends support it).

The link may not need to actually change any equalization, but it is a necessary part of the state machine if both ends of the link advertises 8G or 16G.

A more detailed discussion can be found here

Pre-emphasis is actually what is used and is present in all versions of PCIe. V1 has a default of 3.5dB, V2 has a default of 6dB (settable prior to link up via registers in most cases).

Both under and over equalization can cause excessive jitter and therefore a relatively high bit error rate.

For PCIe (and numerous other link standards) the requirement is \$10^{-12}\$ on a point to point basis.