What is a 3-state storage register on a shift register?
3-state simply refers to the ability to disable the outputs, in this case using the OE pin for output enable. It really has nothing to do with the registers themselves, but only the output drivers. Doing it this way allows to set up a bunch of devices on a common bus; for example, a shift register like this could receive the current state of a NES controller, and be read out at a later time. 

Page 3 of the datasheet shows the functional steps very clearly; there's one shifting chain, fed by SER and SRCLK (with output into QH' so you can chain it wider, as for a SNES controller), a second 8-bit register that is updated using RCLK, and buffers to read that out using OE. This setup allows one set of counting hardware to load new values without risking a partially shifted version of data on the outputs. 

So yes, RCLK will copy the shift register contents into the parallel output register. From there the only readout available is using OE to enable the output pins QA through QH. That makes the 74*595 a serial to parallel shift register.