VHDL FSM Moving Average
A few problems I can see right away:


You don't [re-]initialize temp anywhere.
You don't have any limit checks for count (is it a subtype or just a natural/integer? What happens with pattern(count+i) when you approach the limit? How do you roll over?)
Your for-loop is 0 to len - are you sure you didn't mean 0 to (len - 1)?
Since your entire state decode process is clocked, you don't really need n_state at all. Note that you're not even initializing c_state (but you're still decoding it). Either make your state decode a separate combinational process or just get rid of n_state and assign to c_state directly.


Otherwise, it depends on your design goals. If you don't care about throughput but need to run at a very high clock rate, you might want to perform your addition sequentially instead of in parallel, for example.