JK Flip-Flop as a frequency divider by 3 with a Duty cycle of 50%
The only way to divide by an odd number and get a 50% duty cycle output is to use both edges of the clock signal, and this requires that the clock itself have a 50% duty cycle as well.

For example:







simulate this circuit &ndash; Schematic created using CircuitLab

There's no advantage to using J-K flip-flops for this; the circuit is exactly the same, with the J inputs connected where the D inputs are, and the K inputs tied high.