Static Timing Analysis for I2C
To fully analyse a I2C bus timing wise, you need to know the physical differences between the clock and data channels, the value of the pullup resistor and the impedance of the driver driving the bus. If the channels for the clock and data are not the same, then you need to consider skew due to differences. 

As I2C is open collector, with a pullup on the lines, the speed at which the line is charged and discharged varies, depending on the resistor values and the capacitance on the physical layout. This means that to get precise results in your analysis you need to have a fully routed board with a known stackup.

Your bus will charge the line up through a pullup, perhaps with a value of 2.6k to 10k (usually stronger the faster you need the bus to go) and discharge it through a mosfet in the MCU to ground. The mosfet might have a series resistance of 40 ohms, this is usually given in datasheets. If you know the logic trigger levels Vol, Voh, Vih, Vil you can find the timing at which you have valid logic levels. 

You should notice that the information you have given is missing some of the most critical values that will decide whether your bus works or not. Any intentional or parasitic capacitance on the lines and the values of the pullup resistors are needed, along with the timings from the datasheets of the components.