Clock failure detection on FPGA
The only simple way you can detect if a clock is running is if you have a clock to test with. Typically this would take the form of some free-running clock that should always be present.

Most FPGAs have an internal oscillator or external clock source used for configuration logic, without which they cannot configure (and so are blank slates). It is typically possible to use this clock source in your design as a free-running clock for general purpose use.

If you have this clock available, you simply need three counters. One counter increments on the free-running clock from 0 to a known value, and acts as a reference counter. The other two counters increment on the 48MHz and 64MHz clocks respectively. 

When the reference counter reaches a known value, it checks the values of the other two counters to see if they are at a value that indicates the correct frequency (+/- some tolerance). All three counters then reset, and the process happens again. If at any point one or both of the clock counters are not in the correct range, it means that said clock is either intermittent, dead, or the wrong frequency.



Without a reference clock, you can only really do this reliably with analog circuitry. For example something to measure the RC time constant of the clock signal, or to see if it is toggling. 

If your FPGA has a PLL (which is basically just an analogue circuit) with a locked signal, you can use this to indicate that the PLL is out of lock, which could indicate a reference clock failure, but could also indicate power supply issues, incorrect duty cycles, etc.