VHDL Programming error. “couldn't implement registers for assignments on this clock edge”
I encourage, that you start with a simpler example to learn VHDL.

If you want registers for trans, Speed, Accand so on, then you must group all assignments for each signal into a if(rising_edge(Clk)) block. You can use also such a block for all regarding signals at once; e.g.

PROCESS (Clk) -- just Clk now required 
BEGIN
  if(rising_edge(Clk)) then 
  -- all following assignments are now synchronous to the clock edge

        if (up = '1') hen
            trans &lt;= trans + '1';
        else 
            trans &lt;= trans; -- not needed, saved anyway if not assigned elsewhere
        end if;

        if (down = '1') then
            trans &lt;= trans - '1';
        else 
            trans &lt;= trans; 
        end if;

    case trans is
    when "000" =&gt; 
      if (gas = '1') then
        Speed &lt;= Speed +4;
        Acc &lt;= "11111";
      end if;

      if (gas = '0') then
          Speed &lt;= Speed -4;
          Acc &lt;= "00000";
      end if; 

    -- and so on
    end case;
  end if;
END PROCESS;    


EDIT: corrected code.

Furthermore trans must be defined as a signal in the architecture, so that, it can be initialized to "000":

ARCHITECTURE Behavior OF GearCounterFirst IS
  signal trans : std_logic_vector(2 downto 0) := "000";
BEGIN


But, now you also need a new name for output, e.g.: trans_o and an assignment after(!) the process:

trans_o &lt;= trans;


The output should now be declared as out instead of buffer:

trans_o : out STD_LOGIC_VECTOR (2 downto 0)


Same signal declaration and assignment is required for Speed and Acc.