RS-485 network with multiple masters
Is there any risk of damaging chips if one is sending a high bit (0v because it's UART) when others are staying high (idle or low bit)?
  


My understanding is that multi-master RS-485 (at least one possible scheme anyways) has every node also has its receiver enabled when transmitting so it can monitor what is actually being put onto the line. If whatever it is trying to put on the line is not getting on the line, then it knows there has been a data collision. In the event of collisions, all transmitters back off for a randomized amount of time (with some fancy schemes randomizing that time too) before re-trying (and obviously don't try to transmit if something is already happening on the line).  Therefore, I think it's fine though I've not noticed any obvious datasheet info that says this is okay. It might be something in the hardware protocol that's omitted from the datasheets.


  
    Do I need to turn off DE pin of my MAX485 chips when I'm not sending data to let others masters talk?
  


Yes, or else the transmitter continues to hold the line at whatever level you are inputting into the chips. I made the mistake of not implementing the DE to only be enabled during a transmission and just tied it high in a system I was working on. The result was that I could not use a PC to tap into the line to send my own commands during debugging. I could only listen in to what the boards were doing because the boards would not relinquish drive control of the line.


  
    If yes even if I have an Arduino next to each MAX485, it's not this one that is sending data (TX on the schematic, it's a serial sensor) and so I don't know when it's going to "talk", should I follow the SAE J1708 wiring? Are the capacitors and the resistors necessary for a short network?
  


I looked into what actually J1708 is and it appears to be an RS-485 hardware workaround to allow dominant/recessive scheme where one bit overrides the other, similar to CAN and I2C.

So unlike what I described in my first answer, where all all transmitters backoff in a data collision, not all transmitters back off in J1708. Instead only some transmitters back off. When messages collide, a dominant colliding bit will override a recessive one in a "pull-up with open-collector" scheme or 
"pull-down with open emitter" scheme to produce an ORing effect, using the DE pin as a data pin since it can put the transmitter to the required high-impedance state (while the regular data pin can only output a definite HI or LO which would not allow for a dominant and recessive bit scheme).

Therefore, messages with the most, earliest, dominant bits can "override" all other messages without getting corrupted. The messages with the earliest recessive bits "lose" and back off while the more dominant message continues to transmit, in a "last man-standing" scenario.

Therefore, the Rs and Cs are mandatory for J1708 since they are what bias the line to the appropriate logic level to be transmitted when the driver goes high impedance when the DE is used as a data pin. Like before, this still means that if you have the DE pin set to the dominant bit state, nothing else can be transmitted on the line because the line will be held at that and nothing can override it.