What are some of the basic FPGA synthesis algorithms mapping to LUT?
A LUT is a memory (Look. Up. Table).  It implements logic truth tables by using the memory address as the input bits, and the memory data output as the output bits.

By way of example, for a 4-bit up counter: at address 4'b0000 is stored 4'b0001; at address 4'b0001 is stored 4'b0010; ... ; at address 4'b1011 is stored 4'b1100; and so forth.  The outputs are registered and fed back to the inputs, so on every clock the cycle repeats and the counter output increments.