output pin overvoltage protection
There's a very clean technique for level shifting that you could use here. You place a low-voltage FET in line with your I/O signal from the processor (Drain to the processor and source to the outside world), and drive the gate with the highest voltage you can stand-off -- in your case you'd tie your VDD(3.3V) supply line to the gate. 

The FET will stay on for any ground current (since the g-s voltage is high), and would be less and less conductive as the source voltage approached the gate, until, once the source voltage goes above the gate: then it turns off. Note this allows logic levels to go both directions as long as each side has a pull-up to their respective regions supply voltage. 

Here's a link of how someone else did something similar, and a drawing of how to do it.







simulate this circuit &ndash; Schematic created using CircuitLab