Question on timing diagram of a SR Latch with different gate delays
The problem is caused by what is known as the Inertial Delay Model used by HDLs like Verilog and VHDL. The output of a continuous assignment or primitive gate cannot change faster than its propagation delay. Another way to think of this is an output can only have one scheduled change pending at any point in time.
At simulation time 500, Q gets scheduled to go to 1 at time 505, and Q_L gets scheduled to go to 1 at time 510. Then at time 505, Q goes to 1 as scheduled.  Because of the change to Q, the continuous assignment to Q_L gets another evaluation at time 505 to go back to its current value, and the previously scheduled assignment to 1 at time 510 gets cancelled. Now there is nothing scheduled until R or S changes again.
In contrast, the Transport Delay Model allows the output to change as fast as the inputs, regardless of the propagation delay. It can queue up as many pending changes as needed. Module path delays in a specify block, and non-blocking assignments use transport delay models.