Simple questions about synchronizer
The input signal needs to be stable in order to avoid issues with meta stability. Consider the timing diagram taken from this article:

C1 and A are in your source clock domain and C2 and B are in your destination clock domain. If the clock edges violate the timing constraints, the B flip-flop may not detect the high A input. If A changes before the next C2 edge, the high A signal will be missed. This is why you need to hold A stable for two clock periods.