How to implement a continuously scanning multi-channel system in Verilog
One simple approach would be to have a free-running counter that measures time in units of its clock period. Each channel, when it receives a pulse, captures the value of the counter into a register. The counter must be big enough so that it doesn't overflow in the expected total time between the first and last pulses. Once all of the channels have triggered, you just need to sort the captured values into ascending order and take the differences between adjacent values.
A variation on this would be to feed the counter value into a FIFO along with flags for all of the signal channels, and trigger a FIFO write whenever any channel gets a pulse. Now the timestamps are already sorted, so the differences are easy to compute, and you can see what order the channels fired in by examining the flags.
I would start with something like this. Note that this just covers capturing the data; doing something useful with it is up to you.
module pulse_timestamp (
  input   [7:0] channel,
  input         clock,
  input         reset
);

  /* Total elapsed time from last reset.
   */
  reg    [31:0] time;
  always @(posedge clock) time &lt;= reset ? 0 : time + 1;

  /* Bring the asynchronous channel signals into our clock domain and do
   * rising-edge detection on them. Note that since all channels experience
   * the same delay through this process, it doesn't affect the relative time
   * measurements.
   */
  reg     [7:0] channel_a;
  reg     [7:0] channel_b;
  reg     [7:0] channel_c;
  reg     [7:0] rising_edge;
  always @(posedge clock) begin
    channel_a &lt;= channel;
    channel_b &lt;= channel_a;
    channel_c &lt;= channel_b;
    rising_edge &lt;= channel_b &amp; ~channel_c;
  end

  /* Write the timestamps and channel flags into a FIFO
   */
  reg     [3:0] wr_addr;
  reg    [39:0] fifo [0:15];
  wire    wr_enable = |rising_edge;
  always @(posedge clock) begin
    if (reset) wr_addr &lt;= 0;
    if (wr_enable) begin
      fifo[wr_addr] &lt;= {rising_edge, time};
      wr_addr &lt;= wr_addr + 1;
    end
  end

  /* NOTE: reading out the fifo and doing something with the information
   * is left as an exercise for the reader.
   */

endmodule