In Verilog Synthesis, Creating several Instantiation of a Module is the same than instantiate several modules with same content?
In the first case, one of the modules will get 'optimized away' as the outputs are equivalent and can simply be connected together (same module, same inputs, same parameters, so outputs will be the same).  In the second case, this will also happen if the module contents are identical.  If the module contents are different or if the inputs/parameters are different, then the result will be two different sets of logic (well, it could be optimized such that some parts are shared, but the outputs should be distinct).  

If you want things to happen sequentially, then I think you will have to put them in the same module and use a state machine or similar to sequence the operations.  If they are in two separate modules, then you could use enable signals of some sort and sequence that externally, but you might not get any area savings from logic that could be re-used for the sequential operations.