Unexplained interrupt behavior in AVR ATMEGA324P Timer Counter ISR
With the help of the comments and the below post I was able to determine the cause of the issue.

https://stackoverflow.com/questions/24128926/what-happens-when-an-isr-is-running-and-another-interrupt-happens

The cause of the problem is not an extra interrupt as I had originally thought it's that one is being missed because the global interrupts were disabled to handle another ISR. I was able to verify this by adding an sei(); instruction at the beginning of all the other ISR handlers and the inverting issue went away. Re-enabling global interrupts in every other ISR is not an ideal solution and causes more issues especially with the UART. The best solution would be to use the OCR1A/B pins on PD4 and PD5 however these pins are used for something else so that's not really an option. The solution I came up with is to use the Timer 1 Overflow interrupt to clear the output pin which fires on BOTTOM in Phase and Frequency PWM mode. So regardless if a toggle is missed when the counter is at the bottom the pin will be cleared and the error will only exist for a few cycles at most. 

#define SS_Hi() PORTB |= _BV(4)
# define SS_Lo() PORTB &amp;= ~_BV(4)
# define SS_IN()(PINB &amp; _BV(PINB4))

void init_TCNT1(void) {
  // setup timer counter 1
  // PWM, Phase and Frequency Correct 8-bit. TOP = ICR1

  TCCR1A |= _BV(WGM11);
  TCCR1B |= _BV(WGM13);
  TCCR1B |= _BV(CS11);

  ICR1 = 40;

  TIMSK1 |= _BV(OCIE1A);
  TIMSK1 |= _BV(OCIE1B);
  TIMSK1 |= _BV(TOIE1);

  OCR1A = 10; //Set the top value
  OCR1B = 10; // Set the compare value 
  TCNT1 = 0; // intitilize the start value 

}

ISR(TIMER1_COMPA_vect) {

    if ((EnA_1() != 0) &amp;&amp; (EnB_1() != 0))

  } // End Timer 1 Compare A ISR

ISR(TIMER1_COMPB_vect) {
    // ISR For Motor 2

    if (SS_IN() == 0) SS_Hi();
    else SS_Lo();

  } // End Timer 1 Compare B ISR

ISR(TIMER1_OVF_vect) {

  SS_Lo();
}