Implement AND gate multiple ways (positive & negative logic)
read negative logic and positive logic gates

With NAND gate it works the same way - you implement AND gate in the NAND gate as OR gate with both inputs and output negated, then you negate the result as NAND is AND followed by NOT gate.

NAND:
x y z
0 0 1
0 1 1
1 0 1
1 1 0

OR:
x y z
0 0 0
0 1 1
1 0 1
1 1 1

OR with both input/ouput negated (so it is AND)
x y z
1 1 1
1 0 0
0 1 0
0 0 0

OR with both input/ouput negated (so it is AND) and then negated again (so it is NAND)
x y z
1 1 0
1 0 1
0 1 1
0 0 1


so if you rearrange the last table, you get the same as NAND