How to view the implementation on Vivado
Yes - you can select either &quot;Open elaborated design&quot; or &quot;open synthesized design&quot; followed by selecting the &quot;schematic&quot; option.
The elaborated design shows the result of RTL elaboration - your input HDL is parsed and lightly processed, but the schematic remains in terms of blocks such as wide muxes, wide logic functions, multipliers, etc. These do not necessarily represent physical elements -- e.g. there's no physical RTL_SUM in the FPGA fabric even though your arithmetic operation might sum a few numbers using the + operator in your HDL.
In contrast, the synthesized design shows the implementation using the FPGA elements themselves -- you will see LUTx, mux, and other FPGA fabric BELs (basic elements). This is still not a precise match -- e.g. an artix-7 will not have LUT4s (4-input lookup tables), but the implementation step will easily map the LUT4 onto the physically-present LUT6s in the fabric.
However, if I recall correctly, not all elements will still be present in the synthesized design. It will contain IBUF and OBUF elements used for the I/O pins, but implementation will perform a little more mapping, configuration, and so on.
Finally, you can use a device-level view -- open the implemented design and go to the device view. You can enable viewing routing resources using a button in the top toolbar that looks like:

You will see all of your device elements, represented on a view of the FPGA fabric itself. Note that it is likely not to scale with the physical silicon in the FPGA chip.