How do I make an unsigned 8 bit adder in VHDL ? And an unsigned 8 bit subtractor?
Just for completeness, answer is already in the comments
An entity of a VHDL component has to match the filename. Therefore you should either rename the entity to adder1 or the file to signed_adder.vhdl.
As mentioned there are other potential issues in your code
a_sig &lt;= UNSIGNED(a);

The compiler should complain here because you try to assign an 8bit vector to a 4bit vector. Your internal signal a_sig should have the same size as your input. Another thing is that when you add two 8bit numbers, the result might be 9bits long. Therefore your sum should be of type std_logic_vector(8 downto 0).
And as a side note, there's no benefit of adding the internal signals in your case. Technically you could directly do
sum &lt;= std_logic_vector(unsigned(a) + unsigned(b))