Using Memory values in Verilog / VHDL
See the Xilinx AXI Reference guide
and the AMBA AXI protocol reference.

In particular, see section A3.2: "Basic read and write transactions" which details how the valid/ready handshake protocol works, and details the channel protocols for reading and writing.

You need to write an axi master which creates AXI write/read requests on the AXI bus and processes the response. You can use the DMA core to generate these requests for you, but in my experience the DMA core command interface is practically the same as the AXI address bus. 

For an example AXI master, you can use Vivado to create an example AXI master IP. See this guide for details.

In short, you open create an empty vivado project and run the "Create and Package IP wizard" (page 27)


  To run the Create and Package New IP wizard, from the Tools menu,
  select Create and Package New IP.


Then select "Create a new AXI4 Peripheral" and see page 39 for how to parameterise your new peripheral. You want to add an AXI Memory-Mapped Master interface. Once you've gone through this wizard, vivado should generate example code for your AXI peripheral and you can edit it as you please.