16-bit Byte-Addressable RAM Interface
SRAM chip with 16-bit data word bus and two Byte Lane Enable signals literally have a word of two bytes at each address, the upper and the lower byte.
For example a chip with 2 Mbytes (2^21) of memory has 20-bit address space. For each of the addresses, you can say which bytes you want to access, and the choises are both bytes for the 16-bit access, or either the higher or lower byte only for 8-bit access.
So it is up to the memoy controller to translate a 2 Mbyte byte addressable accesses from CPU  to 1Mbyte word addressable chip. You only have to look at A0 and determine if that even or odd address means high or low BLE being active.
It even works when the CPU wants to do a 16-bit access on an even memory address, as it means both BLEs are active.
The problem is that if CPU wants to access a 16-bit word at an odd memory location, it must be converted to two SRAM chip accessess, one at odd memory address X with only one BLE active, and one at even memory address X+1 with the other BLE active.