Altera Cyclone V: Timing issues with routing (interconnect)
Are you sure there are real violations? Do you need to set false paths, or separate clock groups? STA tools are only smart as you tell them; if you don't think there's a real logic path / problem after reading the violation, I would modify my SDC to let the tool know to not worry about it. This could potentially also remove unnecessary restrictions on the synthesizer and router.

If it's a real problem and it's all coming from interconnect delay, I would wonder why the router is not placing appropriately for it. You could try adding regional constraints or investigating why the router thinks it's ok to place them so far apart -- perhaps some other constraint is missing.