Why Verilog doesn't introduce a FF for reg type variable in always@* block and why reg is allowed in combinational circuits
However, I don't know why Verilog allows using register and register-files inside the always @* block which is a combinational circuit.


Because designating a signal as reg or wire has nothing to do with whether it is implemented as the output of a register or a combinatorial circuit. It only relates to whether the signal can be assigned to by a procedural assignment (assignment in an initial or always block) or by a continuous assignment (assignment by an assign or instance output). 

Reg signals can be assigned to in procedural blocks. Wire signals can be assigned by continuous assignment. That is absolutely all the different signal types mean, and this is simply something you have to get used to when working in Verilog. 

The names seem to imply a different meaning because Verilog was originally intended to be a tool for modeling hardware that was designed by other tools rather than a tool to synthesize new designs, and so using it for synthesis has a few warts that reflect the inherent kluginess of doing that.