VHDL simulation shows 'X' for input
You have multiple drivers for the signals A and B here:
 A&lt;=&quot;0000&quot;; B&lt;=&quot;0000&quot;;

and here:
PROCESS BEGIN
  WAIT FOR 23 NS;A(0)&lt;='1';B(0)&lt;=NOT B(0);
  WAIT FOR 23 NS;A(3)&lt;='1';B(3)&lt;='1';
  WAIT FOR 23 NS;A(2)&lt;='1';B(2)&lt;='1';A(0)&lt;='0';B(0)&lt;='0';
  WAIT FOR 23 NS;A(1)&lt;='1';B(3)&lt;='0';A(0)&lt;='1';B(0)&lt;='1';
  WAIT FOR 23 NS;A(3)&lt;='0';B(2)&lt;='0';
  WAIT;
END PROCESS;

The signal assignments at the first place continuously assign &quot;0000&quot; to A and B. These are not an assignment of an initial value.
Then your process assigns something to the same signals, thus, you have multiple drivers which are resolved. But, if you drive 0 at the first place and 1 in the process the resulting value is undefined shown as X in the simulation.
If you just want to initialize A and B, then move the first assignment into the process:
PROCESS BEGIN
  A&lt;=&quot;0000&quot;; B&lt;=&quot;0000&quot;;
  WAIT FOR 23 NS;A(0)&lt;='1';B(0)&lt;=NOT B(0);
  WAIT FOR 23 NS;A(3)&lt;='1';B(3)&lt;='1';
  WAIT FOR 23 NS;A(2)&lt;='1';B(2)&lt;='1';A(0)&lt;='0';B(0)&lt;='0';
  WAIT FOR 23 NS;A(1)&lt;='1';B(3)&lt;='0';A(0)&lt;='1';B(0)&lt;='1';
  WAIT FOR 23 NS;A(3)&lt;='0';B(2)&lt;='0';
  WAIT;
END PROCESS;