SPI flash bit-banging access over memory-mapped IO
I just recently did something very similar - bit banging both a 16 bit parallel interface and two QSPI interfaces from userspace over PCIe.  In this case, an FPGA was on the other end, not an ASIC, but the interface is the same: a few bits in a couple of MMIO registers.  In this case, the device advertised the BAR as 32 bit non-prefetchable, though I'm not sure if prefetchable vs. non-prefetchable makes any difference for writes.  At any rate, writes are posted, and as such the PCIe spec requires them to traverse the bus in-order, so there were no special considerations required as far as ordering is concerned.  However, timing was a slightly different story, and in a few places I had to perform dummy reads of the register to slow things down a little bit.  Reading is non-posted, so presuming things are not being cached, performing a read can be used as a barrier, ensuring that all writes initiated before the read will complete before the read itself completes.  

The general method is exactly what you might think: For writing, set CS and MOSI in one write, then set SCK high in the next write, then set SCK low and update MOSI in the next write, then set SCK high in the next write, etc.  For reading, the idea is similar, read MISO, set SCK high, set SCK low, read MISO, etc.  For the QSPI flash I was interfacing with over a PCIe gen 3 x16 link, I did not have to do anything more than that - no sleeps, busy loops, or dummy reads required.  For the parallel flash, I did have to add a couple of dummy reads, namely one dummy read to extend the high period of the signals during a write, and one dummy read before the actual read to give things time to settle.  

I would recommend figuring out how to read the flash ID registers reliably first before moving on to writing the flash.