FSM for predesignated process (How to draw the state diagram)
State machines that cycle through a loop of states are implemented in exactly the same way as state machines that have idle states.  There is no difference at all.

The decision about which state to go to next (including the option of remaining in the current state) is exactly the same; in your traffic light example, it's as simple (in somewhat incomplete Verilog) as:

case (state)
 STATE_RED:   if (cnt &gt; RED_CNT) nextstate = STATE_GREEN; else nextstate = STATE_RED;
 STATE_GREEN: if (cnt &gt; GREEN_CNT) nextstate = STATE_YELLOW; else nextstate = STATE_GREEN;
 STATE_YELLOW: if (cnt &gt; YELLOW_CNT) nextstate = STATE_RED; else nextstate = STATE_YELLOW;
endcase


and the synchronous assignment of state:

state &lt;= nextstate;