Why setup time is greater than hold time?
Why setup time is greater than hold time?


Who says that it is? It depends very much on the design of a particular sequential circuit.

However, it is often desirable for setup time to be greater than hold time (or put another way, for hold time to be as low as possible), because this means that you can cascade FFs directly to create shift registers, etc. without having to worry about metastability.


  How can hold time be negative?


You can trade off between setup and hold time by adding a delay in either the data input path or the clock input path. If the delay that you add to the data is greater than the FF's actual hold time requirement, the overall hold time requirement for the combination can be negative.