Removing optimization changes I2C timing
Finally figured it out. Just had to reduce SCL frequency. I noticed that the clock line was a low for a lot longer between bytes for the -O0 optimization waveforms, so I figured it had something to do with the slave clock stretching. I found a note in the MCP9600 datasheet that mentioned if the master doesn't have features to detect slave clock stretching you should reduce SCL frequency, and that worked out.