how to get a random seed value at that randomize simulation time in SystemVerilog?
As far as I know, at least there is no direct method to find the root seed set by the simulator ahead of the simulation run. The value set by sv_seed flag is usually found in the log generated by the simulation. If not used, it's defaulted to 1 in some tools.

Because I'd like to make a directory each simulation by SVSEED value. and If I can get a SVSEED value in simulation time, it will be handy.

A work-around I have done in Questa-Sim in the past is generating a random root seed \$ R \$ in a script/makefile, and then create necessary simulation folders corresponding to this generated seed. Finally, invoke the simulation command from the script, and pass \$R\$  as argument using -sv_seed R flag.