LDO layout: position of output cap relative to load
The main criteria for placement of output capacitor when using LDOs is what it needs for stability of the LDO rather than what the load needs. Read the datasheet carefully. (LM1117 Datasheet)

The LM1117 requires a minimum output capacitance of 10uF with an ESR of 0.3 to 22 Ohms. LDOs can have bad transient response or even oscillate if you don't adhere to these recommendations.

The 200mm of trace will have a resistance of ~0.25 ohm if you are using 0.5 oz copper - less if the copper is thicker (PCB trace resistance calculator).  This is not much and actually will ensure that you meet the minimum ESR.

You say you are using an electrolytic capacitor - what sort? What is its ESR? Normal aluminum electrolytics are not very good and probably has quite a few ohms ESR, it may not meet the 22 ohm requirement of the LM1117.

In general it doesn't matter where on a PCB the electrolytics are placed but it is important that the 0.1uF cap is close to the load. I think either A or B would work.

If I was doing the design I would use much larger than 10uF, maybe 47uF or 100uF placed close to the LDO.  I would also use a tantalum capacitor.  These days ceramic is also feasible but you have to then be careful about the ESR being too low as a ceramic cap may only have 0.01 ohm ESR.  Some trace resistance can help then