Can I make power consumption analysis much harder by temporarily disconnecting the power supply?
If you're not using custom silicon, I don't see any way to achieve really good security against power monitoring without adding some sort of battery (which you may want anyway for time-keeping) that's mounted in such a way one cannot get access to the electronics without breaking the battery connection (the board would have to receive its crypto keys after the battery is installed, and removing the battery would erase them).  Once the board is protected in such fashion, there are many ways of guarding against power-supply monitoring.  A simple approach might be to wire in series with the supply a PFET with source and drain "reversed" so that when the gate is high or floating it will behave as a diode.  Driving the gate low momentarily, before a cryptographic computation, would then cause VDD to rise by a diode drop; if one raises the gate, the micro would be powered by the bypass and filter caps until their voltage dropped by 0.5 volts or so.  External monitoring could ascertain the total current consumed by a computation, but that would likely not be meaningful.