Using multiple DDR3 controllers on FPGA
Does anybody have any experience in using multiple controllers on an FPGA?


Yes, I've helped out on a design for an HD video pipeline that used two DDR memory controllers, but I don't know whether they were DDR3 specifically. One 32-bit wide memory held the main frame buffer, and the other 16-bit wide memory held overlay information. Worked quite well.


  Or would the single controller be the safer bet?


That's really a separate question altogether. Depending on the bandwidth requirements of the different "users" of this memory, the overall recurring system cost can be lower if you can funnel everything through a single memory controller and a single set of memory chips. But the design time and risks (NRE costs) will be higher. I have also taken this approach on a different (SD) project.