Registered signal and Fmax in Timing Analyzer from Quartus II
That isn't a shift register, it's just a register. The only flip-flops are the 32 that implement the register y, and all of their inputs and outputs go directly to I/O pins. Since there are no paths that go from one flip-flop to another, the timing analyzer can't compute the minimum time required for a clock period.
If your module had a mode in which it computed, say, y &lt;= {y[30:0], x[0]};, then you'd have a shift register, and such paths would exist, allowing the computation of the minimum clock period and the corresponding \$F_{max}\$.