Verilog nested for loop not behaving as expected
You have problems with the Operator Precedence.

The comparison ( &lt; ) has higher precedence then you EXOR operator ( ^ ).

Thus first j &lt; 2 is calculated as true (1) or false (0).
Then that is EXOR-ed with 7, which gives either 6 or 7.
But it never gives 0 (false) so the loop does not finish. 

Try: j &lt; (2^(N-1)) or what you probably want: j &lt; (1&lt;&lt;(N-1))