VHDL elegant way of implementing a select with don't care condition in the input
In VHDL-2008 or newer you can use a &quot;-&quot; as don't care in a select statement if your synthesizer implements this feature.
See UG901 (Vivado Design Suite User Guide) page 217.
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf
process(clk) begin
  if clk’event and clk=’1’ then
    with my_reg select?
      out1 &lt;= 
      in1 when “11--“,
      in2 when “000-“,  
      in3 when “1011”,
      in4 when others;
  end if;
end process;

Here is the results of running the above select-statement code through the synthesizer in Vivado 2018.2

If your synthesizer doesn't support using don't cares and your number of cases is reasonably small then just use an if statement to achieve the same result.  The above example could be transformed into the following.
process(clk) begin
  if clk’event and clk=’1’ then
    if my_reg(3 downto 2) = &quot;11&quot; then
      out1 &lt;= in1;
    elsif my_reg(3 downto 1) = &quot;000&quot; then
      out1 &lt;= in2;
    elsif my_reg(3 downto 0) = &quot;1011&quot; then
      out1 &lt;= in3;
    else
      out1 &lt;= in4;
    end if;        
  end if;
end process;

Here is the results of running the above if-statement code through the synthesizer in Vivado 2018.2

As you see, the Vivado synthesizer on default settings generated the exact same result for both sets of code.  This is not surprising because they are logically equivalent.