Finite State Machine in Verilog
always @ (posedge clk_slow or posedge rst)  //state changer
begin
    if(!rst)
        state &lt;= S0;
    else
        state &lt;= state_n;

end


If you want an asyncronous active-low reset, this always block should be sensitive to negedge rst instead of posedge rst. 

If you want an active-high reset, then the condition in your if statement should be rst instead of !rst.

Edit

Other minor issues I see in the code (that shouldn't make your system nonfunctional):


Your comment says cnt is a 21-bit register, but the actual code makes it a 22-bit register. This should just make the LEDs blink half as fast as you expected.
There is no reset logic for cnt. This will make the code difficult to simulate (because cnt will be stuck in the 'x' state).