Gilbert-Cell Operating Point
Look at two DC biasing extremes. One starts from Vcc and works down, the other starts from Vee and works up.

Working from the top down:
If voltage drop across RL is set at 0.4V, then peak AC voltage (max) would be 0.4V as well, setting peak-to-peak voltage at 0.8V. In that case, base voltage of T1, T2 should be no higher than Vcc - 0.8V. You might want a little more headroom to stay out of saturation region, so base voltage T1,T2 should be no higher than 4.0V above Vee. This sets T1, T2 emitter at 3.4V above Vee.
T5's base (to stay away from saturation) should be no higher than 3.2V. T5's emitter would then be 2.6V.



Working from the bottom up:
Leave a generous 0.6v for the current source bias resistor (which could be as low as zero ohms). This leaves lots of headroom for the current source biasing at the bottom transistor. This is an arbitrary decision. Current source Vbe is 0.7V, and again, to stay out of saturation, current source collector voltage adds 0.2V, putting collector at 1.5V above Vee.
T5's base adds 0.7, and should be biased no lower than 2.2V. T5's collector (to avoid saturation) should be no lower than 2.4V.
T1&amp;T2's base adds 0.7V to 2.4V, and should be biased no lower than 3.1V.



These two biasing scenarios define a biasing window for T1&amp;T2, and for T5. T1&amp;T2 bases could sit anywhere between 3.1 - 4.0V. If biased at 3.1V, little headroom is left for T5. It might be wise to split the headroom evenly, and bias T1&amp;T2 bases mid-way in the window at 3.55V.