Question about particular powerup seq
If your wires/traces are thin little buggers it might happen that one voltage leads on the other in your implementation with 10uF to the order of tenths of volts. But I do mean thin and long.

On a 3.3V source voltage a charge differential of 0.4V (smallest maximum difference between the two in the constraints) on two 10uF capacitors each with 1 to 10 100nF caps parallel to it means a comparatively huge difference in resistance (and/or inductance) of the tracks/wires going to it.

Since VDDIN is allowed to be slightly below VDDIO and VDDIO is allowed to be slightly below VDDIN for all the given constraints, that makes the problem sort of balanced, so you need not look one way or the other.

Just make sure your traces can support the current requirement, keep your capacitances sane (which 10uF still is) and try to keep the large capacitors the same type and physical size, if the specifications allow for that, to make sure ESRs and such are in the same neighbourhood. If your traces are "fat" enough to support the current requirements of the MCU without a noticeable voltage drop, they're going to be "fat" enough to charge 10uF caps quick enough.

However, the best solution is always to do what they say in the datasheet examples, if they drive it with a single 3.3V -or similar- source (which I think would be likely), use their connection example and guidelines. If they want Cap X and Inductor Y for filtering, use those unless you know for sure your solution will work too.