Verilog: Can I omit the length of a register that is initialised to a string?
In SystemVerilog, we can simply use the string data type:

string hello = "Hello world!"


But in Verilog your first line is still the best option:

reg test [12 * 8 - 1:0] = "Hello world!";




EDIT:
For synthesis, even in SystemVerilog, it is much safer to do something like this:

parameter CSIZE = 8;
parameter CCOUNT = 80;
reg [CCOUNT * CSIZE – 1 : 0] heythere = “Hello, world!”;