How to think while working with VHDL or Verilog
With HDL languages, you have to understand you are describing hardware, not software. I think this is fundamental to "getting the hang of it". The order of the code in your module doesn't matter, it all happens at once.
It's not so bad once you get going - after you have designed a few simple modules (e.g. counter, adder, mux, etc) your mind should adapt naturally to the process.

The best book I have read to get going with HDL is Pong Chu's "FPGA protoyping by Verilog examples" (I use Verilog, but there is also a VHDL version of this book) It mostly focuses on the synthesisable stuff, which is what you want to know for FPGAs, aside from e.g. testbench code which has a chapter devoted to it also. (I'm assuming that you are interested in using HDL for FPGAs/CPLDs)

Aside from that, a couple of good 'net resources I have bookmarked over time are:

FPGA4Fun.com

Edaboard PLD forum

ASIC World

With the above links (particularly the first) and the book, you should be "up to speed" in a short time.