How can assign a synthesizable string to a byte array in SystemVerilog?
You should be able to do this without using string types. Just use a bit-stream cast

string_t str = string_t'("abcdefg");


This works because a string literal (what is enclosed in "") is interpreted as a 64-bit integral value, and as long as the target variable has the same number of total bits, the bits will be streamed from the 64-bit integral to the fixed array of 8-bits X 8-elements array.