How to estimate chip area from verilog design
The only way to get a really good estimate is to actually run the design through the proper ASIC flow for the process in question.  Yes, this requires extremely expensive software, component libraries, proprietary fab data, etc, etc.  

You might be able to get a ballpark estimate by synthesizing to gates (not LUTs) with some other toolchain (perhaps even an open source one) and then multiplying gate count by the cell size for the process you're interested in.  Note, however, that certain optimizations to utilize FPGA LUTs and other features won't necessarily work well/at all in an ASIC.  This also won't work for designs that use FPGA block RAM or large ROM lookup tables without doing some extra work to exclude the RAMs/ROMs from synthesis as gates and then work out the area of each RAM/ROM individually and add it all up.