4-bit memory serial to parallel memory register circuit question
Your circuit is basically correct. You just didn't find the right pin at the bottom edge of the J-K-flip-flop. If you hover with the mouse cursor over a pin Logisim will in many cases show a little description.


The pin labeled "en" you connected your CLR line to shows Enable: When 0, clock triggers are ineffective.
The pin labeled "0" I'm using shows Clear: When 1, pin state to 0 asynchronously.


Nice, eh?

Since you are using J-K you can drop the inverters between the stages and connect J and K directly.