What noise frequencies is an oversampling ADC susceptible to?
In any non-josephson-junction ADC, you will have analog comparators; their bandwidth likely will set the noise floor. 

How to estimate the noise of the Comparator? simply use the input FET gate capacitance.

Using sqrt(K * T /C), the math behind switched-cap-sampling-noise, you'll find a 10pF capacitor produces 20 microVolts RMS noise. And a (more likely to get the C_gate_oxide value) 1pF will produce 20uVrms * sqrt(10pf/1pf) or 20uV * 3.16 = 63 microVolts RMS.

The over-sampling behavior has the effect of reducing the 63uV RMS to a value suitable, such as 2uV, for a 24-bit ADC.

One thing you may find interesting is the digitization of a 5uVPP sinusoid, or any well-described just-a-few-quanta input. Will the ADC produce the properly-binned code density? And how can we tell, in the face of 63uV dithering?