Verilog: XOR all signals of vector together
Binary operators like &amp;, |, ^ and some others can also be unary in verilog, which is quite convenient. They perform bitwise operations on the operand and return a single bit value. See e.g. reduction operators on asic-world.com.

reg [63:0] large_bus;

wire xor_value;
assign xor_value = ^large_bus;