Rising Edge-Triggered Truth Tables
Using the TI datasheet sdls119.pdf description section (sheet 1) and schematic analysis on sheet 3, if the clock is high or low the D input is ignored.  

BTW the TI datasheet is the only one so far that I've found that doesn't explicitly mention this, old Motorola and Fairchild datasheets specifically say once the clock is high or low the outputs are frozen.

If outputs follow a static "clock" signal then it's referred to as a transparent latch.