VHDL: Convert std_logic to std_logic_vector
You need to cast cin to an unsigned, then add it in.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity four_bit_adder_simple is
    Port ( a    : in  std_logic_vector(3 downto 0);
           b    : in  std_logic_vector(3 downto 0);
           cin  : in  std_logic;
           sum  : out std_logic_vector (3 downto 0);
           cout : out std_logic );
end four_bit_adder_simple;

architecture Behavioral of four_bit_adder_simple is
    signal total : std_logic_vector(4 downto 0);
begin

    total &lt;= std_logic_vector(resize(unsigned(a),5) + resize(unsigned(b),5) + unsigned'('0'&amp;cin));
    sum   &lt;= total(3 downto 0);
    cout  &lt;= total(4);

end Behavioral;


You'll end up with this:


Note that resize returns an unsigned here.