Mixing reset and non reset registers
When FPGA/CPLD is being configured, every FF is set to defined state of 0 (however it may happen that this behavior can be tweaked).

I think that having digital signal or register in X (undefined) state is not what you want, and actually incorrect in real life, thus this X will not synthesize, however may work for simulation.

Furthermore, in your sample code you have synchronous reset, triggered by clk. If you do not want to change FF's state on posedge of clk when reset is high, just do not write assignment clause there.

Actually this Verilog code synthesizes into electronic circuit; it is not a program, and subject to different execution terms than usual computer program.