Bit compression in Verilog
The problem is that you're writing code that would be appropriate for a software programming language in a hardware description language.

Remember, in a HDL, a for loop describes parallel hardware constructs, not sequential processing steps.

In your case, the outer for loop is appropriate, since you want to build logic that handles each column independently. But within each column, you want to count the number of ones and then output a bit vector that has that many bits set in a row. The easiest way to specify this might be to simply enumerate all of the possibilities with a case statement or a lookup table.

If you really want to do it with logic, this answer may offer a clue. (You're basically sorting a list of 1-bit values.)