How to modify D-FF Setup/Hold Times using Verilog?
You will need to add delays to the clock and/or data signal to the specific flip-flop in question. Adding delay to the data input increases the effective setup time, while adding delay to the internal clock signal increases the effective hold time. The clock-to-q delay is controlled by delays added to the input clock as well as to the output q.

Of course, this assumes that you are specifying the behavior Verilog for the flip-flops yourself, rather than synthesizing to some target architecture. This technique will work for simulations only, not for static timing analysis.