Improving PWM by using comparison to LFSR instead of counter
An improvement certainly. But it does not improve it to the point where there are no signals at a frequency of f_clock/resolution, they are still present, reduced by the first order of the frequency ratio. If the small improvement is adequate for your application, then go for it. For typical audio application, the improvement would not be enough, neither would it be for generating DC calibration signals for instance.

You can achieve better suppression of f_clock/resolution frequencies by one of two techniques.

Noise-shaped sigma delta fractional N. There is much published matierial on this subject, much of it fairly opaque. I'm not going to do a literature review here. In this method there are still signals at fclk/resolution, but they are suppressed by the nth order of the ratio for an nth order modulator.

Chinese remainder theorem synthesis. This uses two (or more) conventional PWMs in parallel, each with a shorter accumulator. The two counters are of the form MN and MP, where M, N, and P are mutually prime, and M is a few more than the number of PWMs, say 5 for two PWMs. If N=63 and P=64, then the lowest repetition rate is 1/320th of fclock (1/5x64), but the resolution that can be achieved is 1/16128 (the 63 and 64 work together to create 1/4032ths, and there's an addition 1/4 from 1/(M-1)). In this method, there are truly no signals at fclk/resolution. The method is limited for monotonicity by the degree of analogue balance that can be obtained, but this equality should be easier to achieve than the ratio between a most significant and least significant PWM, if you tried to combine two that way. Why is it called Chinese Remainder Theorem Synthesis? That's what you use to determine the numbers to load into your PWMs, given the output fraction that needs to be achieved.