Howcome I can't use assign operator on multiple bits?
Looks like I'm too new to comment here, but I wanted to expand on the previous answer. With one-hot mux selects, that you want to synthesize into an and-or tree, you can't use the ternary conditional operator. You have to use the replication operator. This is one thing that vhdl (I think) does better than verilog.

assign foo = in1 &amp; {WIDTH{sel1}} | in0 &amp; {WIDTH{sel0}} ;


If the original questioner tries something like this to replicate the select, it should work. But ternary conditional is preferred. So is if/else inside an always block.