Using a Counter to Determine next MSB position in polynomial division
I assume that ctr_reg is of type (un)signed because it's a counter.

VHDL expect normal indices to be of type integer (natural, positive are subtypes of integer). See the definition for std_logic_vector:

type STD_LOGIC_VECTOR is array (NATURAL range &lt;&gt;) of STD_LOGIC;


So you must convert your counter from (un)signed to integer:

if (numerator(to_integer(ctr_reg)) = '1') then


If ctr_reg is of type std_logic_vector (slv), then you must also convert slv to unsigned:

if (numerator(to_integer(unsigned(ctr_reg))) = '1') then


If this construct is to long, write a function (let's say to_index(..)) which hides these conversions :)

if (numerator(to_index(ctr_reg)) = '1') then


A definition for to_index(..) can be found here.

Edit 1:

List of commonly used packages in VHDL:

library IEEE;
use     IEEE.STD_LOGIC_1164.ALL;  -- common std_logic(_vector) operations
use     IEEE.NUMERIC_STD.ALL;     -- defines signed and unsigned and their operations