74HC161 carry look ahead
Fortunately I have the books on the 74HCxx and 74ACxx series, which show the internal logic of the 74HC161 IC's. As a single IC, the CET (count enable toggle) pin must be high for a clock pulse at the CEP (count enable pulse) to be counted. 1) Pin TC is high at full count only, and for multiple counters connects to the CET input of the next stage (IC). Internally the CET gates the CEP input and goes to a 5 input AND gate who's output is the TC pin. This AND gate outputs a logic high only if the count is full and the CET input is high due to a previous stage being at full count.2) Since the clock is common to all CEP pins only the stages with CET = high will count.  It is a carry look-ahead scheme in that the internal logic of each IC makes sure the next stage counts up by one if the preceding stage is at full count.3) Since the CET pin feeds a signal to all downstream stages, any 'next stage' counter that is at full count will roll over to '0000'. This 'roll-over' action stops at the first counter that is not at full count. Instead it will count up by one. Because it does not have CET = high, the following stage will not count up, but maintain their current value.4) This way a string of these IC's will count up from zero properly, and when all of them reach maximum count, will all roll over to zero at the same time, and count up again as long as the clock pulses continue.5) This carry look-ahead scheme works because as the next stage is counting up (or rolling over to zero), the previous stage which was at full count with the TC pin high will also roll over to zero. That is why the TC pin is set high before the next clock pulse (at full count), hence the 'look-ahead' description and method.