FPGA Synthesize - Xilinx ISE - Removing most all FF from FSM
"any insights please"


Test reasonably fully in simulation. Preferably with a self checking testbench which reports whether or not what ought to happen, actually is happening.

Almost always - as here - if synthesis is trimming away your code, it is because your code isn't actually doing anything, so it can safely be removed without affecting the result.

Proceeding to synthesis without testing reasonably well in simulation is doing things the hard way.

On quick projects I don't always test everything ... at first.

But if I see something suspicious in synth, as you did here, I revisit the testbench and add tests for it, so that 


  If you look below - bit 3 of RedRam_Data3 is clearly set.


... is actually demonstrated ... and then if it isn't, further tests to reveal why not (e.g. is that counter counting?)