Verilog counter does not work!
When I run your code on 2 different simulators, I get compile warnings about port size differences for d and qd.  Your counter declares them as 8-bit wide, but you connect 1-bit signals to them.  Don't you get warnings?  If not, try it on edaplayground.

In test_b, declare them as 8-bit:

module test_b;
 reg clk,clear,load,up_down;
 reg  [7:0] d;
 wire [7:0] qd;


Now I see qd[7:0] count up from 0 to 0xa when load=0.