How does assignment work in Verilog?
Let's consider the timing of the sum output (the timing of the carry output will be analogous).  You have 3 sum signals in your code:


Sum_wire
S
S_out


Let's assume your clock period is 10ns and you drive all inputs at the posedge of clk in your testbench.  When you run simulations, you will see S and S_out change at the same time as each other, and they will change 10ns after Sum_wire.  That is what the always block does: adds one clock cycle delay to the Sum_wire signal.  The always block will infer 4 D-flip-flops when it is synthesized, with Sum_wire bits as the D inputs and S bits as the Q outputs.

Regarding visibility, when you run simulations and dump waveforms, you can see all of the sum signals.  If you really want to use the internal sum outside of the four_bit_hca module, you can add it as another output in the module port list.