556 dual timer circuit not clear to me
The voltage on pin 2 is pulled up by the base current from an internal PNP transistor, maybe 500nA. So when the output of timer 1 is high, the other side of the capacitor is also high. When the output of timer 1 goes low, the voltage across the capacitor (call it zero for the sake of discussion) does not change instantly (that's what capacitors do) and thus the trigger input is pulled low and the second timer starts. 

Incidentally, that's not very good practice, though it probably works, there should be a resistor of 20K or something like that from the trigger input to the supply. It might even sort-of work with a CMOS 555, depending on the frequency vs. leakage currents, but a resistor will make it work for sure.

Internal schematic from here: 



The capacitor charges from the base current at pin 2 (Q10). When the output of timer 1 goes high again, the capacitor is discharged again.. I think initially by two diode drops above the supply voltage through the well used to isolate the lateral PNP, then it drops a bit to supply the bias current. Note that this usage breaks the absolute maximum input voltage spec on the trigger input, but hey, lots of folks do it.