VHDL loop not updating output
Your process experiences the following stages:


An event is observed on clk.
clk has a value of '1', so the execution proceeds through into your loops
Your loop tries to assign various values to y. Only the last value assigned will be scheduled, this execution of a process with a sensitivty list happens in zero time.
The process ends.


You will not see the value of y counting through different values, because all the 'changes' happen in zero time. You will only observe the final value, which is 9.

Your explanation of what you want the code to do does not really make sense. Are you trying to implement your code in a real FPGA device? In this case, what would it mean for a counter to cycle through the values 0-9 on a rising clock edge? You may need to broaden your description; why do you want the output to do this?



If you just want a counter to count through the values 0..9, you could use something like this:

signal counter_s : integer range 0 to 9 := 0;  -- Initial value of zero


...

process (clk)
begin
  if (rising_edge(clk)) then -- Better to use `rising_edge` function
    if (counter_s = 9) then
      -- The counter should loop back round to zero
      counter_s &lt;= 0;
    else
      counter_s &lt;= counter_s + 1;
    end if;
  end if;
end process;

counter &lt;= counter_s;


You need an intermediate signal counter_s, because a port of mode out cannot be read.