Signal Generation with duration in VHDL?
Write a separate process for generating a mono-shot of 75ms delay triggered by key press. Then use this mono-shot signal in the sensitivity list of the process in which the output signal is assigned with required values. The code will be something like:

process(any_key) -- process for mono-shot of 75ms delay
begin  
  if (any_key = '1') then
    temp &lt;= '1';
    wait for 75ms; -- replace with a counter
    temp &lt;= '0';
  end if;
end process;

process(temp) 
begin
    if (temp = '1') then
        out &lt;= required_signal;
    else
        out &lt;= '0';
    end if;
end process;


Before synthesizing you have to replace that wait for statement with a counter to implement 75ms delay.