Is one of the inputs in this discrete H-bridge driver schematic inverted?
When Q2 is on, V0 is off.
For Q2 to be on, Q1 must be on. (pnp, negative base current)
For Q1 to be on, H_BRIDGE_HI must be high. (npn, positive base current)
When Q5 is on, V1 is off.
For Q5 to be on, H_BRIDGE_LO must be high. (npn, negative base current)
They're both inverting.
Missing from this circuit is shoot trough prevention and dead time insertion.
And I think you can't turn on V0 on at all since all bootstrap voltage in C1 is being shorted as long as Q0 and Q2 conduct. Which they both do when Q1 is on.
I think Q2 should be an NPN, to conduct when Q1 is off. But maybe I'm wrong with this.
Next time use a half bridge gate driver chip.