Why route signals orthogonally in adjacent layers?
Parallel lines of high impedance can couple dV/dt and dI/dt according to the gap and loop impedances.  So it can be L or C or both.  Saturn PCB design exe helps compute crosstalk and impedances in nH/mm and pF/mm for RF which includes fast risetimes in logic.
More important for low EMI boards is orthogonal layouts permit easier connections with fewer vias.
This is also why decoupling caps are placed near Vdd Vss to reduce the loop area of current spikes drawn by CMOS switched pF logic.
Thus traces can be considered single turn transformers very loosely coupled or capacitively coupled. Also interleaved thin ground tracks or layers shunt this crosstalk considerably when required. In analog high impedance circuits, the active common-mode signal can &quot;guard &quot; tracks where the signal comes from to reduce the differential voltage and thus capacitance between the wires and reduce the coupling to outside wires.