PC serial communication with FPGA
I would suggest either writing a UART module from scratch or finding one online.  Then all you would need to do is write a wrapper that interfaces the UART to your registers.  Here is one possible open source Verilog UART module that I wrote a while ago:

https://github.com/alexforencich/verilog-uart

This particular module uses the AXI stream interface, so it should not be very difficult to interface with your design.  

The AXI stream interface has three signals: tdata, tvalid, and tready.  tvalid indicates that tdata contains valid data, and tready indicates that the sink is ready to receive the data.  Data bytes are transferred only when tvalid and tready are both high.  

What I would recommend doing is defining a simple serial protocol that supports some basic framing.  Say, to send A and B to the FPGA, you would send some sort of start indication (e.g. 0 or perhaps ASCII S or W), then the MSB of A, then the LSB of A, then the MSB of B, then the LSB of B.  Then you can write a state machine that looks for the start indication, then loads the next four bytes into the appropriate registers.  Then once the operation is complete, the state machine can send the result back to the computer.  If you want to use ASCII instead of binary, you can do that too, but it's a bit more complicated to convert everything.  I would recommend using hex if you want something human readable as it is much easier to divide by 16 than it is to divide by 10 (bit shift/bit slice instead of an actual division operation).