Output on Pass-transistor NAND gate lower than expected
Remember that for an NMOS transistor to conduct you must bring the gate voltage above the source voltage, and we usually expect the difference to be at least equal to the transistor's threshold voltage if want significant current.

The sources of your two NMOS transistors are connected to the NAND gate output, so the NAND gate output (the sources) must be at a lower voltage than the transistor gates when the transistors are conducting. If the highest voltage in your circuit is 1.5V, and you drive the transistor gates to 1.5V, then the NMOS transistors can not bring the NAND output voltage any higher than (approximately) \$1.5\,\mathrm{V}-V_{THN}\$

EDIT, after Figure 4 was added:

You can't do this with real transistors. The source voltage for an NMOS must be lower than the gate when the transistor is conducting. If you try to manipulate the transistor threshold closer to 0V (either with a body bias or by changing the doping) then the transistor will not turn off properly, and subthreshold leakage will make it impossible to get a proper 0 logic level. That's why pass transistor logic is so rarely used.