Will 2 always@ blocks that run at the same time in verilog use old or recent values of outputs?
Always keep the circuitry/schematic in mind when coding HDL. The code you wrote is just a description of the circuitry you want.
*** ---&gt;|    |--aout--***--&gt;|    |--bout--&gt;
        |    |              |    |
        |_CK_|              |_CK_|
          ^                   ^
  clk-----+-------------------+

(I omitted other signals for simplicity.)
I assume the above is what you want to design. The 2 DFFs function in parallel. So the idea is: for the same active clk edge, bout register update its output using aout which is generated at the former clk edge. The same is done for aout register. Although this still has to be guaranteed by timing analysis to avoid any hold time violation.