Memory alignment is always power of 2
Modern computer memory is conceptually addressed as bytes, but the real hardware transfer is done in a multiple (a power of 2) of bytes. To do this, the last few bits of the address do not take part in the actual transfer, but are (optionally) used inside the CPU to select one (or more) of the transferred bytes.

A consequence of this scheme is that what is transferred is a block of bytes (the size is a power of 2) that is aligned at a multiple of the block size. If the CPU wants a data block that does not fit this constraint, more than one block read is needed, and the CPU must reshuffle the content of the blocks to get the data it needs. A CPU can do without such reshuffling hardware (and the associated loss of time) by requiring that data is suitably aligned. 

In short: 2^N alignment matches what is easy and fast in hardware.