Identifying decoupling capacitors in schematics and routing them properly to ICs
Why aren’t the caps connected straight to the chip in the schematic? That’s up to whoever draws the schematic. However, with larger chips with multiple pwr/gnd pins (eg: bga), it is common to divide the schematic symbol into multiple parts with one part being pwr/gnd pins.
As for routing bypass caps - there’s been plenty written about this. Recently the same question was asked here and there were useful links. Basically you want to minimise the loop size between the chip and the cap. Placement of vias, track length/thickness all play a part. Choice of  the actual capacitor can be critical - read the fine print on the likes of X7R and YUV caps. Just because it is a 10uF cap doesn’t mean you’ll actually get anywhere near that.
Generally bypass caps on analog is less critical - peak currents and frequencies are usually less. So putting 4 caps on a LM324 is probably not necessary.