How to determine lock time of PLL/VCO vs frequency change?
Look at the components in the loop: -



You have a VCO that might have some small time delay or lag and it will likely be a constant delay, Then you have a frequency/phase detector that normally operates at a digital level so this can be easily simulated. The output of the F/PD goes through a low pass filter that may also have gain. This drives the VCO towards the "lock" position.

The above is a classic control system and can be easily simulated or equations formed mathematically. I've simulated one myself a few years ago to see how long it took to lock but, the devil is in the detail and, when you pick a PLL chip you have to go through the data sheet line by line to avoid missing details that could produce an error in the analysis.

I urge you to build a model in your favourite sim tool.