Limiting input frequency to a specified value
You basically need an MCU or FPGA that reads the input signal and monitors the frequency, zero cross and missing teeth.

Then it producess an output signal with a 24V DAC so that it is either a copy of the input, or a 7kHz sine wave where the first zero cross lines up with that of the last input signal befire it exceeded 7kHz and where and a new missing tooth is generated in a free-running mode every 34 cycles counting backwards to the last missing tooth detected before the input signal exceeded 7kHz.

When switching from &lt; 7kHz to >7kHz you would start the generate 7kHz limited sine at zero when the input crosses zero to align the zero-crossings for smooth transition.

It will be inelegant switching from >7kHz back to &lt;7kHz unless you program it to quickly sweep the >7kHz generated output back toward the &lt;7kHz input frequency until zero-crosses align at which pont you switch to just making a reproduction of the input.