"expecting endmodule" error, can't understand why?
I see two problems:

The semicolon at the end of the first always line means the whole if structure that follows isn't inside the always block.

You have a second always block nested insider your first one. There's no need to do that. Since you already are inside an always block, a multiplexer will be inferred from your case statement even without another always.
The always @(*) construct is used when you want to produce a combinatorial multiplexer --- meaning you want to be able to access the unlatched multiplexer outputs. Since you're immediately latching the mux outputs here, there's no need for this.

You can't (AFAIK, but I'm not up on the latest Verilog revisions) declare new signals (reg or wire declarations) inside an always block. Move your declaration of SevenSeg to the top of the module.


Style note: Use begin and end inside every always, even if you will only have one statement in the block. It makes it easier to follow the code, and avoids mistakes when you edit the code later.