LTSpice: Silicon diode substitution improves Schottky clamp simulation
Here is the real behavior of almost the same circuit, installed in a real device. 

The differences are that the driving source impedance is unknown (V1 is ideal in the simulation), and the load impedance corresponding to R3 in the diagram is unknown.

The behavior is nowhere near the rosy picture painted by the simulation.
(On the other hand it is good enough that the everything works in the DUT).



The horizontal divisions on the graticule represent 500 nS intervals.  The upper trace is the transistor's collector: one division is 5V. The bottom trace is from the base: one division is 2V. As can be seen, the rise time is quite slow, taking over 500 nS to rise to more than 90%. What might be considered a solid high logic level is probably not established for some 250 to 300 nS.