How to use "Arbitrary" Vref in FPGA?
You don't do it in the Verilog code.  

If you assign a Vref-using IOSTANDARD to the pin in question in the UCF file (either by writing the text, or using Planahead to create the constraints), then the FPGA will use the Vref pin.

The "Spartan-3 Generation FPGA User Guide", Table 10-16 shows the IOSTANDARDs you can choose from to make use of Vref - in summary, it is HSTL, SSTL, GTL and their variants.



Edit: You might be able to achieve an arbitrary Vref for inputs by using an HSTL/SSTL/GTL input and the Vref as you have it (even though that's not the "right" vref for the standard).  I've never tried it.

Alternatively, can you use a differential input instead and connect your reference 1.8V to the _N pin of the differential pair?  That involves the PCB being laid out differently, so it might be too late!