Quartus Gives Undefined Signal For the State of a Finite State Machine. Supposed to Be Showing Enum of the State_type
This is definitely a Quartus II issue. I'd suggest you you delete state from the simulation display and re-add it insuring it matches Figure 29 on Page 29 of the tutorial you provided the link for, above.

I wrote a test bench that reproduces the waveform from the book. You can use it to insure the arbiter works as intended even if you can't display state:

library ieee;
use ieee.std_logic_1164.all;

entity arbiter_tb is
end entity;

architecture foo of arbiter_tb is
    signal clk:        std_logic := '0';
    signal reset:      std_logic := '0';
    signal r:          std_logic_vector(1 to 3) := (others =&gt; '0');
    signal g:          std_logic_vector(1 to 3);
begin
CLOCK:
    process 
    begin
        wait for 50 ns;
        clk &lt;= not clk;
        if Now &gt; 1150 ns then
            wait;
        end if;
    end process;

DUT:
    entity work.arbiter
        port map (
            clk =&gt; clk,
            reset =&gt; reset,
            r =&gt; r,
            g =&gt; g
        );

STIMULUS:
    process
    begin
        wait for 51 ns; 
        reset &lt;= '1';
        r &lt;= (others =&gt; '1');
        wait until rising_edge(clk) and g(1) = '1';
        r(1) &lt;= '0';
        wait until rising_edge(clk) and g(2) = '1';
        r(2) &lt;= '0';
        wait until rising_edge(clk) and g(3) = '1';
        r(3) &lt;= '0';
        wait;
    end process;

end architecture;


And this is as close as I could get with ghdl and gtkwave:



If re-adding state didn't work you'll need to find Altera specific help.