How to implement SRAM sense amplifier?
To answer your question, yes you can use a LM339 as a sense amp, and all you need to do is wire the + input to the non-inverting bit-line, and the - input to the inverting bit-line. BUT...

Since we're talking about reading a SRAM, the basic sequence of events during a READ is: 


Pre-charge both bit-lines to VDD.
Assert the desired word-line
The selected bits will now pull one of each complimentary bit-line pair towards VSS
The sense amplifier will sense a difference between the bit-line voltages (one will stay at VDD, the other will be falling towards VSS)


If you look at the schematic for a 4T or 6T bit-cell, then you can see that the falling bit-line will eventually reach VSS. In typical IC designs, where density is very important, the bit-cells have very small transistors. Additionally, they are typically built into large arrays, which have very large bit-line capacitances. This results in a very slow (relatively) discharge of the bit-line by the bit-cell. This is the motivation for the speed aspect of a sense amplifier. It probably doesn't apply to you because you can use large transistors (since they're discrete, or in an array), and your array is small.

The isolation aspect of the sense amp is also very important. If you don't use a sense amp, your bit-line will have an unknown load based on whatever you hook up. Also, any noise on the signal will be broadcast to all your bit-cells. Some isolation is always a good idea here. Something as simple as a CMOS buffer/inverter will work just fine.

I don't think you're going to see a major benefit from using a comparator to sense the bit-lines. Instead, I would recommend that you use a CMOS inverter or buffer. It will be simpler, just as fast, and denser.