FPGA proper SDC constraint for hsync pulse
Synchronize and edge detect the hsync input with something like this:

reg hsync_reg = 0;
reg hsync_delay_reg = 0;
wire hsync_posedge = hsync_reg &amp; ~hsync_delay_reg;

always @(posedge clk) begin
    hsync_reg &lt;= hsync;
    hsync_delay_reg &lt;= hsync_reg;
end


Then count the pulses of hsync_posedge with something like this:

reg [7:0] count_reg = 0;

always @(posedge clk) begin
    if (rst) begin
        count_reg &lt;= 0;
    end else if (hsync_posedge) begin
        count_reg &lt;= count_reg + 1;
    end
end


In this case, everything is timed by clock and you don't need any special timing constraints.  This is also known as using hsync_posedge as a clock enable, since it's roughly equivalent to routing the signal to the 'enable' input on a flip flop.