How to assign physical pins of FPGA to Xilinx ISE Verilog modules?
Xilinx uses (user constraints file) UCF to bridge the physical pin connections to TOP signals.
This file is added to a Xilinx project

the format looks like:

NET "CLK_40Mhz" TNM_NET = CLK_40Mhz;
TIMESPEC TS_CLK_40Mhz = PERIOD "CLK_40Mhz" 25 ns;
########################################################
#8+2 LED's for indication
########################################################
NET "FPGA_LED&lt;0&gt;" LOC = B21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED&lt;1&gt;" LOC = B22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED&lt;2&gt;" LOC = C21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED&lt;3&gt;" LOC = C22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED&lt;4&gt;" LOC = D21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED&lt;5&gt;" LOC = D22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED&lt;6&gt;" LOC = E22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED&lt;7&gt;" LOC = F21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED&lt;8&gt;" LOC = F22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED&lt;9&gt;" LOC = G22 | IOSTANDARD = "LVCMOS33";
#######################################################
#6 FET/IGBT gate-drive FET-outputs
#######################################################
NET "FPGA_Gate1" LOC = V22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate2" LOC = W22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate3" LOC = W21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate4" LOC = Y22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate5" LOC = Y21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate6" LOC = AA22 | IOSTANDARD = "LVCMOS33";

NET "CLK_40Mhz" TNM_NET = CLK_40Mhz;
TIMESPEC TS_CLK_40Mhz = PERIOD "CLK_40Mhz" 25 ns;


This is a snapshot from one of my UCF's