Verilog router design and best way to handle variable size packets in verilog?
Supposing that multiple input ports may receive data at once, you can't guarantee that you can transmit from one port to another in real time.  Because two ports could try to route to the same destination at the same time.

Therefore you will need a packet buffer for each input port.

You certainly don't want a 2000 byte x N FIFO because that would waste a lot of memory.

The consequence of wasting memory of course is that you can't buffer as many packets.  In situations where there is a lot of traffic this could lead to dropped packets.

Instead of using a FIFO with each element being a packet, use a circular byte fuffer.  That way you won't have wasted space when storing smaller packets.

To implement the circular buffer just keep a few indexes.  

Let index P1 point to the start of the first packet in the buffer.
Let index P2 point just past the end of the last complete packet in the buffer.
Let index P3 point to the last byte received.

As the packets come in process their header in real time.
Only put them in the buffer if you have space (which can be calculated from the P1, P2, and your buffer size).

If you can fit the packet then put its bytes into the buffer as they come in.  P3 is incremented for each byte.

If a packet is only partially received and a timeout occurs you can reset P3 back to P2.