VHDL: Is it possible to have a "variable length" string in VHDL like in programming languages?
A string is an array of characters with a fixed range. As for any other array type in VHDL, strings can be concatenated using the &amp; operator resulting in a new string (with a new size).
For variable length strings you could use an access string type which can point to a variable length string. Similar questions were asked before.
If you need to handle arrays of strings, the easiest way is probably to define an array of fixed size strings along with a couple of trim() and pad() functions.