VHDL multiplication for std_logic_vector
To get straight to the error:

You try to multiply two 4-bit-signed without putting the result into a 8-bit-signed.

Example (leads to your error):

architecture multiplicator_test_arch of multiplicator_test is
    signal input_1: signed(WORD_SIZE - 1 downto 0);
    signal input_2: signed(WORD_SIZE - 1 downto 0);
    signal result_sig : signed(WORD_SIZE - 1 downto 0);
begin  
    result_sig &lt;= input_1 * input_2;
end architecture multiplicator_test_arch;


Example (doesn't lead to your error):

architecture multiplicator_test_arch of multiplicator_test is
    signal input_1: signed(WORD_SIZE - 1 downto 0);
    signal input_2: signed(WORD_SIZE - 1 downto 0);
    signal result_sig : signed((WORD_SIZE * 2) - 1 downto 0);
begin  
    result_sig &lt;= input_1 * input_2;
end architecture multiplicator_test_arch;


The result-signed-type has to be double width from the two input-signed-types.

So what you have to do is:


Declare another signed-signal with the double width from your multiplication  
put the result from the multiplication in there 
formate the new signal into a std_logic_vector


Moreover your code is not realy readable. You do a lot of formatting in one row.
What do you have to ask yourself: Is it necessary to work with std_logic_vector as input, or can you maybe use signed-types. If not so - ok. But then I would try to keep the signals as signed and do the calculation with this signals. After this you formate your result from signed into std_logic_vector. But this is a question of coding style.