Sequence detection in sequencial logic
You have a register. Connect its output to two comparators - one that outputs 1 when your register matches the "target" pattern and one that outputs 1 when your register matches the "all zeroes" pattern (i.e. an OR-tree followed by an inverter, e.g. implemented with alternating NAND and NOR gate planes).

Lets set up a truth table based on "previous output" (that is a flopped version of your output), and the output of your two comparators.

Previous Output     Pattern Compare      Zero Compare      Next Output
0                   0                    0                 0
0                   0                    1                 0  
0                   1                    0                 1
0                   1                    1                 1
1                   0                    0                 1
1                   0                    1                 0
1                   1                    0                 1
1                   1                    1                 0


You should be able to synthesize the logic that drives your output flip-flop from  that table, but my take is it's a multiplexer selected by the Previous Output. When the previous output is 0, choose the Pattern Compare output. When the previous output is 1, choose the Inverse of the Zero Compare output.