How to make a negative flank to a negative pulse from normal state not connected?
Use an AND (assuming negative RESET!) or OR (for positive RESET) gate to combine the signal used for the debugging interface with the one used to for the usual RESET function.

Or use open-drain buffers with wired-AND connections.

For better control of the RESET pulse, use a one-shot like SN74LVC1G123 instead of just an RC circuit for the reset function.

None of these chips should cost more than a few dimes in volume, or a dollar or so onesy-twosy.