SPI flash memory doesn't work without huge delays
What concerns me is your disregard for EMC issues in your design when it uses 2" of 24AWG wire for signal wiring without mentioning any ground planes.   

A systematic approach must be considered in communication of all signals to determine, which need shielding, common mode filter, ground plane, star ground, radial ground and impedance control on high speed signals. 

Can you obtain some low capacitance FET probes or better yet, Tektronix differential FET Probes and scope the clock &amp; data signals at both ends?

Also remember the specs only say 80MHz is MAX and THERE IS NO MIN.
Also Maximum clock frequency for Read Instruction, 03H, is 33 MHz in the fine print for this 80MHz part. (darn those marketing guys)

THings to do to improve performance;


Use AWG30 twisted pair 12 turns/ft for every signal to this chip where you need better shielding and less overshoot ripple.
Have a dedicated regulator @ Vdd @ 3.6V for both IC's.  Notice there is no spec for the 80MHz part yet the 66MHz part says VDD = 3.0 - 3.6 V, CL = 15 pF, so I would use Vmax=3.6 to get as much performance as possible. (darn those ambiguous specs)
Verify all voltage levels, rise times and setup times.