Creating SystemVerilog module using for loop and separate custom module
The SystemVerilog generate statements are elaborated at compile time, they are not procedural code. That means they are processed much like a macro or `ifdef statement, except that they can evaluate parameters, understand scope, and create new scopes. You need to get rid of the always_comb construct. The if/else if/else is also a generated block that produces only one row instance per iteration. Assuming n=8, then you will get three generated for-loop blocks named label[0], label[1], and label[2]. Your code get elaborated as if you could have written something like the following(assuming n gets overridden to 16.:

module barrel
    #(parameter n = 8; parameter control = $clog2(n))
    (input logic[n-1:0] data, input logic [control-1:0] select,
    output logic [n-1:0] result);

            logic [n-1:0] logic[0].tempResult;
            logic [n-1:0] logic[1].tempResult;
            logic [n-1:0] logic[2].tempResult;
            row #(n,1) logic[0].shiftLevel(
                    data,select[0],label[0].tempResult);
            row #(n,2) label[1].shiftLevel(
                    label[0].tempResult,select[1],label[1].tempResult);
            row #(n,4) label[1].shiftLevel(
                    label[1].tempResult,select[2],label[2].tempResult);
            row #(n,8) label[3].shiftLevel(
                    label[2].tempResult,select[3],result);
endmodule


Note that you could not declare identifiers (the variable names or the module instance names) with the label[x]. prefix without using the generate block construct.