Using synchronous input along with asynchronous input at the same time in a flip flop
There are several ways to deal with this. You could, for example, ignore the \$\overline{Q}\$ output and use only the \$Q\$ output. If you really need the complement then add an inverter.
You could also design the logic around the latch to eliminate the possibility that the asynchronous inputs could be asserted while the enable is also asserted. A better idea might be to prevent the enable from being asserted while either of the asynchronous inputs is asserted. The best approach depends entirely on how you intend to use the latch, and which inputs you want to be prioritized over the others.
By the way, the circuit you present is not an edge-sensitive circuit, it is a level-sensitive circuit. That's why it has an \$enable\$ input rather than an actual \$clock\$ input. I think most of us here would call that a latch rather than a flip-flop.