Verilog: including one module in another module
Sure, if you couldn't build up a hierarchy, HDLs would be rather limited.

For example, you could have:

module ic2323(
  input p0, 
  input n0, 
  input p1, 
  input n1, 
  input clk, 
  output q0, 
  output q1, 
  output x
);

  // Instantiate a pn for p0, n0 and q0.
  pn pn_a(
    .p   (p0),
    .n   (n0),
    .clk (clk),
    .q   (q0)
  );

  // Instantiate another pn for p1, n1 and q1
  pn pn_b (
    .p   (p1),
    .n   (n1),
    .clk (clk),
    .q   (q1)
  );

  // XNOR the two outputs together
  assign x = ~(q0 ^ q1);

endmodule