Synthesis Error Reading and Output Port
Why don't you create a signal to use internally:
signal temp_a : std_logic ;

And use that signal in your logical expressions:
temp_a &lt;= '1' when x &gt; y        else '0'   ;    
b      &lt;= c   when temp_a = '1' else B&quot;000 ;

And finally assign it to a concurrently in the architecture:
a &lt;= temp_a ;