how does bi-directional differential signalling work?
How exactly does this work? Particularly line arbitration


From p. 10 of the datasheet, "DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs"

Timing diagrams on p. 78, p. 82, and elsewhere show more details of how the signals are used. Basically the DQS lines are kept in high-Z until the type of transaction has been determined and it's known which chip will drive the line.


  How does termination work? I'm inclined to think the same resistors on both ends won't work? Does the resistance on either end have to be switched in or out dynamically depending on who is driving?


From p. 81 of the datasheet, see that there is a programmable on-die termination provided, and that this termination is required to be turned off for some states of the memory chip.

100 Ohm differential (or whatever matches the line impedance) at each end of the line should work for a point to point link. When one end is driving, the driver will be a low impedance source, so the termination resistor on that end won't affect signal propagation on the line, though it will force the driver to source more current in order to drive the line.

Where things get hairy is if you want to have multiple memory chips connected to the same signal lines. I've seen this done, with the two memories belly-to-belly on either side of the PCB, to minimize the stubs when either memory was driving the lines. I don't recall if that was a DDR2 or DDR3 design, and I have no idea whether the design was marginally functional or total overkill.  If you need 3 or more memories on the same bus, I have no idea how to proceed.