I understand how D flip flop works but still not understand how it "store" a bit of data in a register in a running computer
The circuit you show in Fig. 3.19 is (in my opinion) mislabeled as a D flip-flop. It is actually more clearly identified as a gated D-latch.
Gated D-latches are sometimes also confusingly labeled 'level-triggered flip-flops'. Again, better to use the term latch to be more clear.
Back to the diagram. The 'clock' would more correctly be called 'write' or 'enable'. You would not normally use a free-running clock to control a latch, but instead gate it with a write-enable signal.
Whatever you call it, the gated D-latch will hold its data as long as the 'clock' (really, enable) is held low, and follow the input while enable is held high, so at least that description is correct.
While D-latches or their equivalents (like SRAM cells) can be (and often are) used for storage, flops used for registers are typically of the ‘master-slave’ D-flip-flop type. That diagram looks like this:

Simulate it here: Master-slave D flip-flop
Master-slave flops are sometimes called edge-triggered registers because they only change state on the clock edge. Master-slave flops are made up of two D-latch stages, with each stage gated on opposite clock phase.
For a positive-edge flop like the one shown above, the clock controls the stages as follows:

clock low: first stage open, second stage close
clock rise: Data transfers from first to second stage
clock high: first stage closed, second stage open (= held first stage)
clock fall: no action

In a system then, the main difference between a latch and a flop is this:

master-slave D flop timing is only referenced to one clock edge.
D latch timing also includes the latch-open time (clock high in your diagram).

This means that with the D flop, clock-to-Q is only related to the clock. This simplifies timing.
One more thing. You can construct D flip-flops from multiplexers. In CMOS this is the most common method. Here's an example:

Simulate it here: Master-slave flop using muxes
Looking at it this way, you can see the follow-hold behavior of each latch more clearly.