Nucleo F401RE ADC sampling Time
The datasheet for STM32F401 says in Table 66. ADC characteristics (continued) for Sampling rate (fADC = 30 MHz, and tS = 3 ADC cycles) and 12-bit resolution Single ADC 2 Msps, so yes, it could achieve 1µs/sample.

However, that uses a sampling time of 3 ADC-clock cycles, a 30MHz ADC-clock, and relies on a relatively low impedance source (under 1k IIRC)

For an 84MHz clock, the ADC-clock will be 21MHz.
The maximum ADC-clock is 30MHz, but it is derived from the main clock by dividing by 2, 4, 6 or 8, and 4 is the smallest divider that keeps it within 30MHz.

So, it's going to get about 2/3rds of 2Msps, specifically \$2 \times 21/30 = 1.4\$Msps, which is still better than 1µs.