FSM 4x7 segment displays Verilog
I think i understand your problem , i had similar problem when starting making circuits in HDL (verilog or VHDL) and coming from programming C++ , python or other languages.

What you need to understand is that in verilog , your variables represent wires(bits) or group of wires (vectors).... so you cant assign same variable as output from 2 parts of your circuit... this would be as weird as having a lamp with 2 plugs ...

Just "somehow" put both machines in same process and it will work.