VHDL parallel execution of statements using variables
When there is no dependance between two assignments in a VHDL process, as in your second example, the synthesiser can choose how to infer the logic from the code as long as the output is equivelent and meets the supplied constraints.

In practice the two statements will be executed in parallel as the synthesiser will work out that they are not connected and create separate logic to deal with the two assignments.

The best way I find to understand how the synthesiser is inferring logic from your VHDL code is to look at the schematics representation of the tool's output after the elaboration and synthesis steps for a simple design and tweak things to see how it changes.