MOS Cascode Bias Quesiton
Essentially,  what's happening in this circuit is something like this:

The bias on the gate of Q2 is holding its source roughly at a constant voltage. Because this is also the drain of Q1, then the Vds of Q1 doesn't change much and it is in the saturation mode. But because the gate of Q1 is varying, the current is also varying. 

But of course the current through Q1 is also through Q2, which has a roughly fixed gate voltage, so that variation appears as a changing Vds for Q2. Hence you get your voltage amplifier. (Q2 is not in saturation mode)

There is negative feedback between the Q1 drain voltage and the gate of Q2 so that if Q2s Vgs gets too big, the current drawn through Q1 pushes it towards linear operation where it will start to increase Vds and reduce Q2s gate voltage. 

To see all this, have a look at this graph:

https://upload.wikimedia.org/wikipedia/commons/thumb/1/18/IvsV_mosfet.svg/220px-IvsV_mosfet.svg.png

The red line separating saturation from linear curves to the right, so for a fixed Vds, increasing current will move towards linear operation. 

The reason that this is shown with a current source is to illustrate that the Vout is controlled by the Fets. The current needs to come from somewhere and a voltage source would prevent amplification. Notice it's not a constant current source. In reality this may be a resistor to a voltage source, but this would also influence and set limits on the output so confuses the issue if your trying to understand the circuit.