Why can't I connect a std_logic_vector signal to a port of type signed or unsigned
Although in your example unsigned and signed are both arrays of the same element type std_logic, this is not the same as a subtype. A subtype is when one type is a limited subset of another type, for example:

subtype my_type is std_logic_vector(3 downto 0);
subtype eight_bit_int is integer range 0 to 255;


A feature of a subtype is that it can be automatically converted to and from the parent type, so I can do:

signal a : std_logic_vector(3 downto 0);
signal b : my_type;
signal c : integer;
signal d : eight_bit_int_type;


...

-- These should both work fine
b &lt;= a;
c &lt;= d;


If you want to connect differing types in a port map, you might have to use type casts or type conversions, or both. Using your example entity, you might write something like this:

signal a_actual : std_logic_vector(3 downto 0);
signal b_actual : std_logic_vector(3 downto 0);
signal c_actual : std_logic_vector(3 downto 0);
signal d_actual : std_logic;


...

-- Converting from std_logic_vector to signed or unsigned only requires a cast 
dummy_inst : dummy
port map(
    a =&gt; a_actual,
    b =&gt; std_logic_vector(b_actual),
    c =&gt; std_logic_vector(c_actual),
    d =&gt; actual
);


If you wanted to connect an input, for example b to an integer, you would have to use a type conversion and a cast, and the line would look like this:

b =&gt; std_logic_vector(to_signed(b_integer, 4)), -- 4 is the length of the port