Is it safe to leave floating the low voltage supply of a logic level shifter?
It's a pretty straightforward circuit design, I have used it before, and I understand it reasonably well.


When you should already be able to work out what happens when LV is at 0V.

Since LV will be pulled down LV and Vin will be the same voltage. With a VGS of zero the FET will be off. If the FET is off the high voltage side is blocked from reaching the low voltage side until you hit the transistor breakdown voltage which is around 50V.

In other words it'll be fine.