sdf generation using prime time
You need to push your design through the synthesis flow to get path timing information and generate the SDF file. Synopsys flow includes Design Compiler (dc_shell) for design entry synthesis. I’d recommend running in topographical mode to incorporate some interconnect delays. You can use the write_sdf at the end of the synthesis to generate an SDF file. 
More accurate timing data can be obtained after place-and-route (PnR) and physical synthesis. You can use Synopsys IC Compiler or IC Compiler II (icc_shell or icc2_shell) for that purpose and generate a post-PnR SDF at the end. Even more sophisticated Static Timing Analysis (STA) can be performed using Synopsys Primetime. 
You can refer to Synopsys documentations and their respective Reference Methodologies (RMs) available through Synopsys Solvenet.