Digital logic design of given scenario
Now that we've cleared up what the scenario is, I'll give you an answer.

Your circuit should produce the correct output.

It uses more gates than needed, though, and is overly complicated.

Specifically, the way you carry the result from the previous test into the next test is strange.

You can add the circuit diagram directly into the question using the schematic editor.

The schematic editor also includes a simulator so that you can test your ciruit directly.



Suggestions in response to comments:

You are using the output from the first test twice as an input to the second test. Think about how you could rearrange that to only use the output from the first test once. You should only need two AND gates for the second test. Whip up a diagram in the editor and see what you can come up with.

HINT: You have two stages of AND gates for the second question. Move the output from the first question to the input of the AND gate on the right. Now you can use just one of the AND gates to the left.

Now, look at the third test and see how you could simplify its use of the output from the second test.