Implementing circuit with d-flipflop in verilog
In your simulator, the initial value of the D flipflop is undefined, hence the behavior of your circuit is undefined. You can take one of two approaches:


Add an initial assignment to the flipflop:

initial q &lt;= 0;

Add a reset signal to the flipflop, and toggle it from your simulation. Your always block should then be:

always @ (posedge clk) begin
    if(reset) q &lt;= 0;
    else q &lt;= D;
end