Why am I getting a red wire for my out?
My first time doing verilog here is the code

The mistakes were as follows: 


Your count, wasn't initiated, so it was adding uknown with a +1 which returned an unknown; i also took the liberty initiated state as well.
It did not know what to do when the state was 3'b000, you had the following covered 1,2,4; (you could use the "default" in case statement in verilog and set it to a known state? )


Suggestions :


I separated out the reset from the case logic, makes more sense to me that way
Might want to add a reset toggle to your test bench, within the first 10 ns or so as was suggested


the code is as follows 

`timescale 1ns / 1ps


module clocksignal(
    input clk,
    input rst,
    output out
    );

    reg [5:0] count =5'b00000;
    reg [2:0] state =3'b000;
    reg w_output;

    always @(posedge clk, posedge rst) begin
        if (rst == 1) begin
            state &lt;= 3'b000;
            count &lt;= 5'b00000;
            end
        else
            case(state)
                3'b000 : 
                    state &lt;= 3'b001;
                3'b001 : 
                    state &lt;= 3'b010;
                3'b010 : 
                    if (count &lt; 29) 
                        count  &lt;= count + 1;
                    else if (count ==29 ) begin
                        state &lt;=3'b100;
                        w_output &lt;= 1;
                        count &lt;= 0;  
                    end                     
                3'b100 : 
                    if (count &lt; 42) begin
                        count &lt;= count + 1;
                        w_output = 1;
                    end 
                    else if (count == 42) begin
                        count &lt;= 0;
                        w_output &lt;= 0;
                        state &lt;= 3'b001;
                    end
             endcase
    end

    assign out = w_output;
endmodule