Gigabit transceiver with MHz reference clock
As mentioned in comments, the transceivers in FPGAs (and elsewhere) usually use a [phase-locked loop] to generate a high frequency clock that is phase-locked to the lower-frequency reference clock.
Very roughly, that means they have a high frequency voltage-controlled oscillator (VCO). They divide the output of the VCO with a clock divider circuit. They then compare the phase of the clock divider output with the phase of the reference clock. If the clock divider output is running a little ahead or a little behind the reference clock, they adjust the control voltage of the VCO to compensate.
This generates an output clock that is a multiple of the reference clock equal to the divide ratio in the feedback path divider.
More elaborate circuits can do &quot;fractional division&quot; to produce an output clock that is a rational number multiplied by the reference clock instead of an integer multiple.