Negative components appearing in total gate capacitance in nanowire
Disclaimer: I have no personal experience with the CAD software you're using.

Searching the internet however, does give some clues.

Reference 1

Reference 2

I believe that the most plausible reason for your results, is that the definition TCAD is using is the following:

$$C_{xy,TCAD} = \frac{dQ_x}{dV_y}$$

Where \$dQ_x\$ is the total amount of charges that are added on the capacitances at the \$x\$-terminal when terminal \$y\$ changes voltage (\$dV_y\$).

So this means that

$$C_{gs,TCAD} = \frac{dQ_g}{dV_s}$$

Which is not the same as the typical definition of capacitances

$$C_{gs,typ} = \frac{dQ_{Cgs}}{dV_{gs}}$$

Where \$Q_{Cgs}\$ is the charges stored on the capacitance between gate and source, while \$V_{gs}\$ is the voltage over that capacitance.