How can the Vss or Vdd pins of a MCU handle sink or source current?
All this is saying it that the maximum current, either sinking or sourcing, is 150 mA for the entire chip..  This is probably dictated by heat considerations.

If you had all 51 GPIO pins drawing current, the average would have to be just under 3 mA (150/51) to avoid going over the 150 mA limit.  (Actually you could nearly 6 mA per pin, if half were sourcing current and the other half were sinking.  But that would be pretty unusual.)

But rather than limit each pin to 3 mA (or 6mA), the spec allows each pin to draw up to 25 mA.  But if you have six pins sinking 25 mA each, then you have used up your total of 150 mA and all other pins must not be sinking any current (although they could be sourcing some).