Purpose of divide-by-2 (or CLK/2) on a video pixel clock generator ICs
It looks like there's a couple of reasons. 

From the MC44145 datasheet:



First off is to adjust the clock to a better range for the VCO that drives the pixel clock PLL so that the VCO control voltage stays within a usable range.

The other reason is to provide a square wave with a 50% duty cycle for the pixel genetator.