SPI design traces for a PCB
Consider this: -



Outward bound from master to slave (left to right) - MOSI and SCLK should have delays that are preferably identical but this isn't the fundamental problem with SPI.

When it comes to inbound data via MISO (from a slave) you witness the fundamental problem with SPI because, the master is clocking-in MISO data synchronous to its local SCLK but, the slave is clocking data out against a delayed version of SCLK due to the length of the wires/traces.

Added to this is the delay incurred by MISO data getting back to the master from the slave. So you have: -


The delay (t\$_d\$) in the slave receiving SCLK. This causes the slave to output data onto MISO at time delay t\$_d\$
The delay in the slave data reaching the master (another t\$_d\$)


If those two delays add up to the half the time period of the SCLK clock then it all fails. If SPI clock is running at 20 MHz then half the period is 25 ns and therefore the line/trace delay should be significantly less than 12.5 ns. 

A delay of 5 ns is approximately equivalent to 1 metre of 50 ohm cable just to put it into context so, you'd have to really try hard purposefully to make out-bound transmissions fail by totally mismatching line lengths.

Thus, outbound data is always going to be a winner compared to slave in-bound data. And, no matter what you do, accumulated time delays can cause in-bound data to fail if the clocking frequency is too high.

Having said all of that, do try and keep tracks/traces/lines as short as possible because at some point transmission line effects will also defeat SPI due to reflections.