PLL with input depend output CLK
The lock range is dependent on the VCO inside the chip. altpll allows you to tweak the PLL VCO lock to a larger capture range than usual. I would not expect more than about a 2:1 range however.

Output phase shift is independent of this. Phase shift is generated by the PLL output divider logic choosing different digital delays on the output referenced to the VCO frequency. Therefore the phase you select will track with the VCO frequency, and thus, will follow your input if you're choosing a net 1:1 clock ratio.

So if you configure the PLL for a 45-degree shift and a capture range of 50 to 100MHz, there will be 2.5ns delay at 50MHz output and 1.25ns at 100MHz output.

You will also need to make sure the PLL is in a zero-delay, or even better, external feedback mode so that the delay can track the input more precisely without skew.