FT2232H - FT245 Synchronous FIFO mode read timing
It's been a while (2007) since I worked with the FT245 — I had an FPGA (coded in VHDL) passing bidirectional data to/from a host PC using it.
Note that RXF# is a bit of a misnomer. It doesn't mean that the Rx FIFO is full, only that it is not empty. Similarly, TXE# doesn't mean that the Tx FIFO is empty, only that it is not full. I'm not sure why they picked those signal names — I found it rather confusing at first.

This seems to indicate that the positive edge of CLKOUT sampling OE#
low and RD# high reads the first data word from the RX buffer
(assuming RXF# is low). In contrast, all subsequent data words are
made available by sampling both OE# low and RD# low (also assuming
RXF# is low).
Is this correct? Or, is the first word available after RD# is sampled
low? Or, something else?

The first word is available as soon as you drive OE# low. But it doesn't change until the chip sees RD# low on a rising clock edge. In other words, you should capture the data whenever RXF# and RD# are both low on a rising clock edge.

Can OE# be kept low if RXF# temporarily goes high, and then reads
after RXF# returns low would follow RD# being sampled low?

Yes, you can keep OE# and/or RD# low even if RXF# goes high.