Spartan 6 DCM unstable clock output
I am new to FPGAs, but I do not think this is the way to do it. From what I know, the main clock frequency should not change. If you want to use a part of FPGA as a asynchronous logic block, try to implement the clock divider by yourself toggling the slower clock on the rising edge process of the faster clock. Thus,

architecture
signal mainDiv2: sdt_logic;
signal mainDiv4: sdt_logic;
signal mainDiv8: sdt_logic;
begin
proc1: process(mainCLK)
begin
  if rising_edge(mainCLK) then mainDiv2 = not mainDiv2;
  end if;
end process proc1;

proc2: process(mainDiv2)
begin
  if rising_edge(mainDiv2) then mainDiv4 = not mainDiv4;
  end if;
end process proc2;

proc3: process(mainDiv4)
begin
  if rising_edge(mainDiv4) then mainDiv8 = not mainDiv8;
  end if;
end process proc3;


I have no idea if this will work. You should explore more on how to implement an FPGA for your particular application instead of trying to fix something that might be wrong to begin with.
Let me know how it goes.