Implementing a counter using multisim
First circuit using FFs looks strange:


!CLR pins of the FFs are on the ground, thus both of them must be in state 0;
second FF, when first goes 0, will have its !PR input also in low state, and this is race condition for the reset state and the FF's state will be undefined;
why D1 is connected to !Q of first FF and D2 is connected to Q of second FF?


There're a lot of "shift register circuit" circuits on the internet, reuse their design instead of inventing the bycicle.

Regarding your gated circuit: I suspect you must add propagation delays to the components for simulation to take place properly. In ideal conditions, when each gate propagates the signal immediately, the device will not work.