Driving Logic Level NMOS and PMOS
With the PMOS device you'd limit the gate-source voltage (Vgs) to a safe value, say -10V. To do that you have to translate the gate drive up to near the 50V rail, so that gate voltage swings between 50V and 40V (assuming -10V max Vgs).

A way to do that is to use an NMOS driver like you've shown, connected to a resistor voltage divider up to 50V, configured such that when the FET is 'on' the divider is 40V to turn on the P-FET. When off, it will pull to 50V and shut the P-FET off.

This approach has a drawback of having a slower switching time due to gate capacitance, but for a simple load switch would work fine.