Impedance matching on FPGA IO
Drive strength and output impedance are only weakly related.

Reducing drive strength is used to reduce rise times and therefore reduce overshoot and ringing when used with mismatched transmission lines. This is adequate for 'short' lines, or with 'slow' edges.

Controlling the output impedance by DCI is used to accurately match transmission lines. This can be used for any line, and is essential for high speed serial transmission.

All outputs will have some inherent uncontrolled finite output impedance. In general, higher drive strength goes with lower inherent output impedance.

According to the first document, series 7 Xilinx FPGAs have DCI, digitally controllable output impedance. This controls the output cell to have an output impedance equal to an external reference resistor (or half that in another option). If you want an accurate output impedance, this is the mode to use.

According to the second document (page 44), LVCMOS outputs set to 6mA drive strength have a crude approximation to a 50ohm output impedance. Later references say 6 to 8mA for the same impedance. From that you can infer that a 12mA drive strength output is likely to have a lower inherent output impedance than 50ohms, but not by how much lower. You can also see that if you want a better match to a specific impedance, you should use DCI and not drive strength control.