Where in the instruction pipeline is machine code to microcode translation?
Instruction-to-instruction translation can take place anywhere between the (documented ISA machine code) instruction fetch unit and the microcode dispatch logic into the scheduling and (often these days, N-way) execution pipelines.  “Code cracking.” Perhaps over or within several pipeline stages. Simple instructions map close to one-to-one.  “Complex” or “non-RISC-like” instructions, one to possibly many. Thus, (documented ISA) instruction fetch and (different, implementation dependent) instruction dispatch are further decoupled in time (number of clock cycles per instruction or number of “instructions” per clock) as well as space (number of instructions fetched versus executed, and their bit widths).

Read more about computer architecture (history), as this was standard implementation practice in many (most?) computer systems designed between the IBM 360 and the Berkeley RISC, Stanford MIPS era.  Except Cray.  MC68000 even used more than just one level of translation.

Often done because processor logic and data path could be clocked faster than memory bandwidth.  And with wildly varying ratios over an ISA family.