Does it make sense to use a clock input for combinational logic?
The only way this would work (i.e output is provided on the same cycle as the input is seen) if there are no flip-flops in the module.

Well, there could be a flop triggered on the falling edge of the clock and if we split enough hairs it could be argued the output is still in the same cycle, just delayed a half cycle...
But from the module and input/output names it appears this is a little endian to big endian converter, which means it will contain no combinatorial logic at all, just wires. And even then, the wires are virtual since all this does is tell the compiler that some virtual input wires are connected to some virtual output wires, which makes them the same virtual wires. So this module doesn't contain any actual circuitry, just information to tell the compiler what you want to do with the signals.