Getting Started With Verilog
Quartus by Altera has a free "web edition" that I've been using and linked earlier availvible for both Windows and Linux.  It can build for a variety of FPGAs and then comes with a built in RTL viewer which is a good way to visualize you netlist.  If the RTL viewer isn't enough, ModelSIM (which comes with Quartus) allows you to force inputs and simulate outputs.  

Your example code compiles correctly and the built in RTL viewer shows the following image (an and gate):