FPGA s with MUX and D flip flop
Try finding a truth table that describes the mux.

Then, split the table so that each of the subtables fit into the FPGA's tables, and connect the LEs so that the complete circuit works.

The flipflop can be mapped by simply configuring the output path of the last table combining the intermediate results to go through the register, while all the previous stages skip the register.

More details:

Your problem is a truth table with seven inputs, i.e. 128 entries. The technology mapping needs to reduce this to 16-entry tables with four inputs.

The simple approach is to generate eight tables that implement a part of the truth table each, then route the output of these tables to tables that implement a selection between two inputs:







simulate this circuit &ndash; Schematic created using CircuitLab

You will need seven of these to combine the outputs from the eight tables, and these will also need to be implemented using tables. Since you have only three inputs on these, you only populate half of the table and fix one of the selection inputs to zero.

There is probably also potential for optimization here, by looking for patterns in the truth table (when doing this by hand) or transforming the expression, but that is a lengthy topic that would now be counterproductive.