What does it mean for a MOSFET to be fabricated in a 0.4nm (or any length) process?
Usually when a CMOS manufacturing process is described as having a certain length, such as &quot;a 14 nm process&quot;, they mean that the transistor physical gate length (the &quot;drawn length&quot;) is 14 nm. Usually, this is also the smallest manufacturable feature in the process...wiring, contacts, vias, and implants will be larger.
The source and drain implants may diffuse a bit so that they spread under the physical gate and make the electrical gate length smaller than the physical gate length. I suppose there are also electrical effects that could come into play here. However, if the physical gate length is large compared to the expected deviations in gate length then we would just use the drawn gate length as the minimum gate length.