Design 8X1 MUX with enable using three state buffers and any logic blocks you need
Look at it this way. A digital signal MUX allows selection of one of several inputs gated to a single output. Such logic normally has to include an OR stage in the logic path to bring the selected input out to the output path. Now note that tri-state buffers can be used to make a wired-OR type bus (i.e. one on at a time). 

Take that information and see what you can do with it to produce the MUX required by what sounds like homework. 

I do not want to take away from your learning opportunity by showing a direct solution. Hopefully others here will take that same consideration!!