Slow clock edge causing issues with D flip flop behavior
Is this truly metastability?  I would rather call it a race condition within the FF master and slave cells at or near the FF switching point.

Using a RC for cleaning up the switch chatter is good, but it does slow down the \$ \dfrac{dV}{dt}\$ of the clock which means that it transitions slowly through the switch point.  You may or may not know this but you can use logic gates as high gain amplifiers if you bias them around the switch point.  Any noise or ripple will cause down stream rapid signal swings. "cleaning up" the signal by filtering it more will only just exacerbate the situation.

Your solution?  put a Schmidt trigger after the RC to drive the clock input.

Want to test out my hypothesis? put a inverter in place of the FF, connect your de-glitched switch and look at the output from the inverter.