How to specify a value for each bit of the reg in Verilog?
First, you need to put the index after the register name, like

value[counter]


not

[counter]value


However, I'm not sure if using a variable as an index into a register will be simulable and synthesizable. 

If not, you could use something like 

always@(posedge button_1 or posedge button_2)
    begin
        if(button_1)
        begin
            value &lt;= value &amp; ~(8'b1 &lt;&lt; counter); 
            counter &lt;= counter + 8'd1;
        end
        else if(button_2)
        begin
            value &lt;= value | (8'b1 &lt;&lt; counter); 
            counter &lt;= counter + 8'd1;
        end
    end


However you should also be aware that this is likely not synthesizable because you are trying to make logic that is edge-sensitive to two different signals and if you consider all the subtleties, the actual logic in your FPGA or CPLD doesn't do that. You can probably make an SR latch, but that doesn't work exactly like your code because it will behave differently if, for example, button_1 is still asserted when the rising edge of button_2 arrives.

The usual way to code these things for an FPGA is to have a clock available that runs much faster than you expect button_1 and button_2 events to arrive, and use that to clock logic that detects edges on the input signals and responds to them.

For example (sorry, code not tested),

reg b1d; b2d; // delayed button signals

always @(posedge clk) begin
    b1d &lt;= button_1;   // Notice: non-blocking assignment
    b2d &lt;= button_2;
    if (button_1 &amp; ~b1d) begin 
        // A rising edge on button 1 happened
        // ...
    end
    else if (button_2 &amp; ~b2d) begin
        // ...
    end
end