Layout of doubled SW pin on buck converter IC
you say no other pins are doubled, but I see the PGND under two pins as well, possibly even four. 

This is a synchronous buck chip with internal switch, it's very possible the low-impedance path is (, as Plasma says in the comments,) between the three pins closely put together:
 VIN, SW and PGND;
where the top SW is more of a looped-around after thought. The power path should definitely include the other pin with least amount of impedance possible (few vias in series or many in parallel and thickest trace as you can get).

It is possible the SW pins are in direct parallel on the chip and they both jump over the bulk VIN with wire bonds of the same or similar description, but in matters of chip design it seems less likely. If they both offer a same or similar path, the only thing I can think of would be one pad being closer to the high-side switch and the other closer to the low-side switch, which would then again mean both need to be connected as low-impedance as you can.