Last resort debug: Voltage limiter
It looks to me like M1 will always prevent M2 from conducting, because M1's gate initially has a path to ground and it won't get a chance to rise to a higher voltage.

I'm no expert on FETs, but it seems to me that your transistor arrangement isn't robust; it tries to pull itself in two different directions and has no clear stable point to settle to. Additionally, the exact gate threshold voltage depends on temperature and that could upset any balance it might attain.

How about this modification: replace R4 with a simple comparator circuit (e.g. LM393) that compares the voltage of C1 (divided down using a voltage divider) with a voltage reference (e.g. a red LED would work, though there are much better references too). If the voltage goes above the reference, the comparator's open-collector output would pull M1's gate down, cutting off the voltage supply.







simulate this circuit &ndash; Schematic created using CircuitLab