VHDL if generate in the preamble, is it possible?
You can't put statements in (formally there is no "preamble" so) the declarative region.

However you can wrap statements and their associated declarations in a block statement. This keeps the declarations and their statements closely scoped together, avoiding bugs where statements are associated with the wrong declarations (which would be possible in your example.

So do that : 

architecture arch of my_entity is
-- declarative region

begin
-- concurrent statement region

   flag_true : if flag /= 0 generate
      -- a block statement
      true_block : block
         constant K1 : integer := 32;
      begin
         y(K1 - 1 downto 0) &lt;= not x(K1 - 1 downto 0);
      end;
   end generate flag_true;

end architecture arch; 


And an observation :

if /=0 means true there is probably something very wrong with the design : you have true booleans in VHDL, you don't have to obscure the meaning so you can do everything with an integer. Then you can write

if flag generate ...