CPU Cache implementation in VHDL
To test your cache implementation, you need a simulation testbench. A testbench is additional VHDL code that drives the inputs to your module and optionally monitors its outputs and/or collects statistics on its behavior.

Testbench models are not typically intended to be synthesizable, and can use coding patterns that make the simulation as efficient as possible.

Yes, you could use an actual CPU model and execute real software on that CPU, but it is often more effective to write a simpler "memory access generator" in purely behavioral code whose access patterns you can control. It could be based on pseudorandom numbers, with some parameters that control things like "locality of access", an important factor in cache effectiveness.

Note that you will also need an actual memory (the memory whose contents you are caching) as part of your testbench. Since the point of simulation at this level is to verify the correctness of your implementation, this could be a simple read-only memory model that returns some sort of fixed pattern based on address, which will allow your CPU model to verify that it is getting data from the correct address for each access.