Verilog: Writing to a Register Happens A Clock Cycle Late
Your code is doing exactly what you have described in your HDL.

At every positive clock edge (always @ (posedge CLK) begin), do the following:


Update the output registers to show the value of r that was latched into the register on the previous clock cycle (RegA_Out &lt;= r[RegA_Name];)
If the write enable signals are high (if (RegA_WrtEn)), then update the value of r to the incoming data.


As a result it takes two positive/rising clock edges after the WrtEn is asserted for the data to appear at the output. This is exactly what you are seeing in your simulation.

I've numbered the clock cycles in your simulation output:




On clock cycle 1, you assert the WrtEn and RegA_In signals. 
On the next rising edge, cycle 2, the first data word is latched into the r register (you would see this if you probed it). 
Next, on cycle 3, the data in the r register is latched onto the RegA_Out register, and the second data word is latched into the r register. 
Finally, on cycle 4, the second data word is read from the r register and latched onto the RegA_Out register.