Test cases for a calculator test bench in VHDL
Its a bit unclear what your opcode is supposed to be, do you mean operands? What for do you need opcodes? Did you build some kind of cpu?

I would suggest to test all calculation modules on their own, especially for overflow and underflow (not for the mentioned operations) . Then I would also test your input module on its own and afterwards all modules together to make sure the bus system works correctly.

The reason is, that by doing it this way you can test a lot more thorough, because if you would simulate the whole system at once (so input together with the calculation modules) its takes a lot longer. You can therefor check a lot more different calculations in the same time when you test all modules seperatly.

If you want to get more specific input, you might want to add a schema how your system is set up.