FPGA CAN Bus Test Bed
First of all: I suggest to use dedicated CPUs for this problem as Oldfart commented before. But to answer the question:

Two steps


Get the estimated resource usage of one complex block. (the MCU plus CAN plus etc)
Divide the available resources with the one block usage. Note that FPGA cannot be fit 100%. I suggest to keep the utilization &lt;80%.


Get the estimated resource usage of one complex block:

A lot of core has estimated resource usage on one or more particular FPGA. Choose your FPGA and summarise the estimation.

OR

Implement one block, synthesise and read the used resources.

Note that this will be just an estimation the final design can optimise some resources or run out because of timing problem.