Designing a sequence detector(0110)
You need to come up with a state diagram (your very first step) that actually does what you want, before going through all of the detailed logic design.

With a Moore-type machine (outputs associated with states), it requires 5 states to recognize the sequence and then output a "1". Then, you need to replicate 2 of the states in order to output a "1" for a second clock while continuing to search for another copy of the pattern. Therefore, a total of 7 states is required.

I hope this is enough of a hint to get you on the right track.



Just for completeness, following your third edit, here is my version of the state diagram:



I find it helpful to label each state with what part of the sequence has been recognized so far. Some notes:


S0 represents finding 3 or more ones in a row. Since the pattern we're looking for starts with a zero, this also becomes our "start" state.
S1 represents finding any number of zeros, the last one of which could be the first bit of our pattern.
S4 represents finding the full pattern. The last bit is zero, which could also be the first bit of another pattern. Therefore, if the next bit is also zero, we go to state S1a, which is equivalent to S1, but with an output of "1". Similarly, if the next bit is "1", we've got the first two bits of a new pattern, so we go to S2a.
The transitions out of S1a are the same as those from S1, and the transitions from S2a are the same as those for S2.