VHDL - testbench hangs due to a problem with nested for loop
Transferred and expanded from comments

ModelSim uses event-driven simulation. Reference page 22 of this presentation. It processes all events (changes in signals) at a certain point in time, then advances to the next point in time where there are events to process, and repeats this loop until there are no more remaining events to be processed. This means two things related to your simulation:


It should have never stopped.
...but if it did stop, then yes it should have stopped at 70ns instead of 80ns.


It should have never stopped

Your statement clock &lt;= not clock after 3 ns; creates an infinite sequence of events. Each time a clock &lt;= not clock event gets processed, there will be another one waiting 3ns later, and that will go on forever.

But, for some reason, your simulation did stop. I suspect there is something else in the portion you did't post in your question. So, ...

But if it did stop, then yes it should have stopped at 70ns instead of 80ns

So the simulation time only advances when there is another event to process. If you walk through the logic of your simulation code (and unwrap the loops), then the final few steps are "drive reset high", "wait for 10ns", then "done". This means that the last event occurs at 70ns. That final wait for 10ns; statement does nothing to advance the simulation time.

On your waveforms we do see R transitioning to a high level right at the very end of the simulation. The only thing that didn't happen in the simulation is the signals sitting in an idle state for another 10ns, but per the above that's not supposed to happen anyway.