Are there special rules for voltage division of a high speed clock?
The rules are that you must take into account impedance requirements and consider the effective RC network created by a voltage divider when considering track capacitance. See this excellent application note.

Dividers even at 33MHz are not going to work well, if at all, and I say that from personal experience where I advised against it but it was done anyway with the attendant pain of rework when the clock was not good enough any more. Remember that it is the clock edge you need to preserve.

It might be possible if you use a buffer immediately after a voltage divider, but you are likely to have duty cycle and phase issues relative to the original clock signal.

Track capacitance for a 100 micron track spaced 100 micron from the ground plane is about 1pF per 25mm of track. Even with short tracks and using a 50 ohm divider there is a low pass filter of 530MHz for a 6 inch distribution track and the attendant extra drive requirement on the source. Note that a low pass filter adds deterministic jitter to a high speed signal. PCB tracks (including differential pairs) are low pass filters as well so adding another filter simply adds more attenuation to the overall clock signal.

I would usually use a clock system where the various levels are generated from individual ICs; there are a number of such offerings.

There are translation products available should that actually be necessary.

For an FPGA, I would normally feed a lower frequency clock and use the (commonly available) internal PLLs to generate any really high frequency clocks.