pseudo dual port RAM in verilog
I assume your 'pseudo dual port' is what I often hear as &quot;simple dual-port&quot; i.e. one write port and one read port.
Since I see you tagged with 'ASIC' I doubt this will be complete nonetheless I think it would be useful to consider FPGA solution as proposed by Xilinx (UG901) as an example. There are many possible variations you are encouraged to check, especially when it comes to read-write ordering.
Simple Dual-Port Block RAM with Single Clock (Verilog)
module simple_dual_one_clock (clk,ena,enb,wea,addra,addrb,dia,dob);
input clk,ena,enb,wea;
input [9:0] addra,addrb;
input [15:0] dia;
output [15:0] dob;
reg [15:0] ram [1023:0];
reg [15:0] doa,dob;

always @(posedge clk) begin
  if (ena) begin
    if (wea)
      ram[addra] &lt;= dia;
  end
end

always @(posedge clk) begin
  if (enb)
    dob &lt;= ram[addrb];
end

endmodule

I have just dumped the code from the original documentation. I'm not particularly fond of the indentation, the use of reg or the i/o declaration but that's it.
As far as I know in ASICs you should be using foundry cells (I honestly hope those basic constructs can go through).