Effect of output capacitance
The analysis of the effect of a capacitor placed across the output terminals, in parallel with the resistive load, can be done by considering the load to be the parallel combination of the capacitor and load resistor.

Without the "output capacitor", your circuit has an output impedance, \$Z_O \$ and an open-circuit phasor output voltage, \$V_{oc} \$.  Your load is an impedance, \$Z_L\$.

The phasor load voltage is then:

\$V_l = V_{oc} \dfrac{Z_L}{Z_L + Z_O}\$

Now, let's assume that the output impedance is real:  \$Z_O = R_O \$

If the "load" is a capacitor in parallel with a resistor,

\$Z_L = \dfrac{R_L}{1 + j \omega R_L C_O}\$

Then:

\$V_l = V_{oc} \dfrac{R_L}{R_L + R_O}\dfrac{1}{1 + j \omega (R_L||R_O)C_O} \$

So, yes there is a pole due to the parallel capacitor.