Why is the input voltage of transistors in the CMOS circuit set to Vdd when calculating the equivalent resistance?
We assume that the input to a CMOS gate is driven by another CMOS gate, and that the output of a CMOS gate is either at \$V_{DD}\$ for a logic 1 or at ground for a logic 0. We also (usually) assume that the sources of all NMOS transistors are tied to ground and that the sources of all PMOS transistors are tied to \$V_{DD}\$.

Another simplifying assumption is that the inputs of the logic gate that you wish to analyze are stable and at either \$V_{DD}\$ or ground. If the input is at \$V_{DD}\$ then the PMOS transistors are cut off and we are only interested in what the NMOS transistors are doing. Since the NMOS source is at ground we use
$$V_{GSN} = V_G - V_S = V_{DD} - 0 = V_{DD}$$
If you assume that the logic gate input is at ground then the NMOS is cut off and \$V_{GSP} = -V_{DD}\$.

Of course, that's a lot of simplifying assumptions. The dynamic behaviour is much more complex, and the effective \$R_{DS}\$ changes as the logic gate's output voltage (and hence the transistor's \$V_{DS}\$) changes. If you really want good answers, simulate in SPICE with accurate input rise/fall times and parasitic capacitances. For back-of-the envelope calculations you could approximate \$R_{DS}\$ with something like twice the effective \$R_{DS}\$ when \$V_{DS} = V_{DD}\$ but this would be really crude. The \$R_{MID}\$ in your first graph is another approximation using \$I_{DS}\$ when \$V_{DS} = V_{DD}/2\$.

The bottom graph that you provide illustrates dc behavior and isn't very relevant for transient switching behavior.