state transfer in FSM, written in verilog
There is race condition in the testbench. NewPacket is updated and triggers an update to state_n all before the clock is ever updated. This all happens within the same time step. To help visualize this race, change the time of the first #20 to #19 or #21.

The testbench should use non-blocking assignments to all signals going to the uut; except clk. Clocks should have blocking assignments. 

initial
    forever #10 clk = ~clk; // Blocking

initial
begin
    // blocking is okay here for initialization
    clk = 1;
    rst_n = 1;
    NewPacket = 0;
    DataIn = 0;

    // From here on, use non-blocking assignments to signals going to uut
    #20 rst_n &lt;= 0;
    #60 rst_n &lt;= 1;

    #20 DataIn &lt;= 8'h73;
    NewPacket &lt;= 1;

    ...

    #20 $finish; // tell the simulator to end
end


Working example here



Suggestions to improve demux:


Data_temp1, packet_size, and outport should have a reset value in the if(!rst_n) block.  
packet_size and outport are also assigned in two always blocks which is illegal for synthesis. For synthesizable code, a variable should only be assigned in only one always block. Creating two new variables for calculating the next values; like the state_n-state relation. FYI: *_n is often a coding style for active low. *_next, next_*, or *_ns are more common prefixes/suffixes for next calculations.
It is recommended to use @* or @(*) for combinational logic blocks instead of specifying signals in the sensitivity list. Therefore, replace @(state, NewPacket, packet_size) with @*