Application of set_clock_latency
Your assumption on network latency is correct. If a tool is handling clock tree synthesis (CTS), we don't need to specify "ideal" network latency.

When do we need then?

Note that CTS is performed by a P&amp;R (place and route) tool such as Synopsys IC Compiler. There is no clock tree in synthesis or post-synthesis STA (static timing analysis), the tools can't know actual clock latencies.

We specify ideal latencies, therefore synthesis/STA tools have more accurate input and give more accurate output. These ideal values usually come from past experience or previous P&amp;R results.

Using the set_clock_uncertainty command for that purpose wouldn't be a good idea. Ideal network latencies are not needed in P&amp;R (after CTS stage) or post-P&amp;R STA, but clock uncertainty is.

If you define your clocks propagated in post-P&amp;R STA, ideal network latencies are overridden1 and actual values are used. This brings more flexibility.

set_propagated_clock [all_clocks]


I have never needed to specify source latency, so my answer is about network latency only.

1: Valid for Synopsys tools, the behaviour can be different for other EDA vendors.