Pull up resistor in NMOS logic value
The timing would depend primarily on the capacitive load on each logic gate, which would include both the wiring capacitance and the capacitance of the MOSFET gate(s) you're driving.

For example, the 2N7000 has an input capacitance of 20 pF typical (50 pF max). If your average fanout is 3, plus some wiring capacitance, that gives you a typical load of 100 - 200 pF. With a 10K pullup, that gives you an R-C time constant of 1 - 2 &micro;s. You'd probably need to allow at least two time constants for one "gate delay" for reliable switching, so we're talking about 2 - 4 &micro;s per gate.

To get useful work done, you'll need to allow some maximum number of gate delays per clock period. This will depend on your specific design, but a number like 6 to 10 would be typical. So now we're talking about a clock period of 12 - 40 &micro;s, or frequencies in the range of 25 - 80 kHz.

Switching to a 1K resistor would allow the frequency to scale up by roughly a factor of 10.