Output voltage ripple
In a PFC (in contrast to a conventional DC-DC converter) there will always be substantial ripple at twice the mains frequency.  

The reason for this is that the control loop is attempting to force the input current to follow the input voltage.  

Because of this the output voltage loop bandwidth has to be very low, or it would interfere with the input current shaping, causing the input current to be different from the goal. (By forcing the output voltage ripple to minimum).

For a discussion of the challenges you can see this paper:

Steady-state dc voltage ripple discrete analysis
of PFC with estimated second-order harmonic
compensation for achieving satisfactory
performance