Doubt about counter implemented in VHDL
The only advantage to writing it the first way that I can see is that, I suppose, it's type-independent. Maybe the original coder wanted to be able to copy and paste the code without modifying it (though one would think the signal name would need to be modified anyway), and depend on the synthesis tool to optimize it (or not). Personally, I do not think this is a good justification - it's less clear, and copying/pasting code without looking at it carefully is never a good idea.

Your assignment statement will change depending on your type. Pre_Q &lt;= 0; for integer types, Pre_Q &lt;= (others =&gt; '0'); (or equivalent) for vector types, etc.

(I see you've updated the question, and given that you're using a std_logic_vector, you'd want the latter)

response to comment

You wrote:


  I do not understand the assignment for vectors. Can't I just use Pre_Q &lt;= '0'?


A std_logic_vector is an array of std_logic, each one of which is an enumeration of 9 possible values/states (including '0' and '1'). They're not technically 0s and 1s to the language, odd though that may seem. So a std_logic_vector is not inherently a numeric type, and can only be treated as such with function overloads. If you try to assign '0' to Pre_Q, you are attempting to assign a scalar (in this case, technically a character literal) to a vector, and these types are not compatible in this way. Nor can you assign the integer literal  0 - while it may be obvious to almost anyone what you are intending to do, VHDL's strong typing does not allow this.

When you use (others =&gt; '0'), you are using an array aggregate. others is a keyword that refers to all indices of the array that have not been explicitly assigned in the aggregate (in this case, all of them), and so when you map the "other bits" to '0', you're zeroing the entire vector. (You can also use a conversion function, but (others =&gt; '0') is the more conventional idiom)