What is meant by Input clamp current/Output Clamp current in micro controller datasheet?
It is an ESD circuit triggering limit specification.

Here is a snip from page 369 (labelled as 367):



Since these numbers are so low it's clearly not the current during the ESD event. Why would an ESD event be clamped at currents less than the maximum current rating of a driven output?  Additionally once an ESD event is underway you're not going to be limiting it to just 20 mA!

Take into account that these are absolute maximum specs and the fact that these "clamp currents" are specified under the conditions that \$V_I&lt;0\$ and \$V_O&gt;V_{DD}\$ the logical conclusion is:

"Thou shall not take the pins below ground or above the upper rail IF you are capable of driving more that 20 ma.  If you do so then the ESD circuits are going to trigger"
- i.e it's the trigger conditions under which the on chip ESD circuits are going fire.

Some datasheets specify dv/dt rates as well.

Modern semiconductor pins have the challenge of protecting against ESD at lower voltages.  The only real way of doing this is to have all the pins connected to an internal ESD rail via diodes (often in a half bridge configuration and sometimes a full bridge).  You can't use a zener or clamping diode circuit as you can't control the breakdown voltage accurately enough for the lower voltages - below 3.3V.  The solution is to have active circuitry that monitors the ESD rails and then clamps them together.  This also allows an any-pin to any-pin clamping action.

These pins will be designed for currents that are well in excess of 100's of mA but they also have to be low capacitance to prevent undue loading of the drivers.

There is also an alternative explanation that these are the limits at which if exceeded will trigger latch up in the substrate.  While possible in older processes this is not likely in modern processes.  However, I don't know the process details so for completeness, this should be mentioned.