Issue on reset on RingCounter in Verilog
You use synchronous reset, thus reset high will only be effective on the following clock positive edge.

Why do you need this for here? Consider the following:

module Ringcounter # ( parameter LENGTH = 8) (
input wire clk,
input wire rst,
output reg [LENGTH-1:0] f
);

always @ (posedge clk) begin
    if (rst) begin f[LENGTH-1] &lt;= 1'b1; f[LENGTH-2:0] &lt;= 0; end
    else
        f &lt;= {f[0],f[LENGTH-1:1]};
end

endmodule


Note changed I made: (1) removed q completely, instead outputting f as register; (2) changed blocking assignments to non-blocking ones.

Edit: ok, if you do not like output reg, then the following:

module Ringcounter # ( parameter LENGTH = 8) (
input wire clk,
input wire rst,
output wire [LENGTH-1:0] q
);

reg [LENGTH-1:0] f;
assign q [LENGTH-1:0]  = f[LENGTH-1:0];

always @ (posedge clk) begin
    if (rst) begin f[LENGTH-1] &lt;= 1'b1; f[LENGTH-2:0] &lt;= 0; end
    else
        f &lt;= {f[0],f[LENGTH-1:1]};
end

endmodule


but it changes nothing, result is the same.

If such modification will not help, then you, most probably, simply stop clock when reset is active.