Why does my synchronous up counter count enable not function properly?
The rising clock edge forces the first stage of the first flipflop to respond. Then INC goes low but the second stage of the first flipflop will still respond to the trailing (falling) edge of the clock pulse making Q0 change state. Q0 should then freeze at this new state because J &amp; K have both been taken low.

You need to add some circuitry which will freeze the CLK in its current state when required to prevent the next falling or rising CLK edge.

A T-Type flip flop should do that made from a D-Type flipflop and an EX-Or gate.