The accurate time latency for 'lw' instruction in a single-cycle datapath
Draw it out. Graphviz is great for this sort of thing.

The clock cycle starts with the PC and ends with the Regsiter Write operation, shown here as square boxes. Everything else (ovals) is combinatorial.



Note that there are two paths between I_memory and ALU (we can assume that the WriteRegisterMux isn't in the longest path). It can be argued that since SignExtend doesn't really involve any logic (it's just wires), and that a simple mux is faster than RegisterRead, that the latter is the critical path.

Therefore, the clock edge to clock edge path delays are:


PC clock-to-output
I memory
Register Read
ALU
D memory
Write Data mux
Register Write setup-to-clock time


The answer that you found that puts the ALUmux in the critical path is confused about which register read port is being used for this instruction.

The other answer omits the Register Write setup time, which they may simply be assuming is zero.