8284 Clock Generator Output wave
The 100 pF load on the CLK signal shown in the data sheet is a test load used to verify worst-case timing. You don't need to have it in your circuit, and the waveform will probably look a lot better without it.

But actually, given that load, that waveform looks fine. Those old clock drivers didn't produce particularly "square" waves &mdash; and in fact, you wouldn't want them to, because it would just add to EMI and other bad effects. The key things are that the edges are monotonic (no glitches or "hooks" near the logic thresholds) and that the spacing of the crossings (about halfway between the peaks, third line down on the 'scope graticule) has the right timing (frequency and duty cycle), which it does.

BTW, your reset wiring is incorrect. R4, C5 and U1 should connect to the RES- pin, which is an input. The RESET pin is an output intended to drive the CPU's reset input.

Also, the PCLK pin is an output, and should not be tied to Vcc. Just leave it open if you're not using it.