USB Super Speed I/O signalling
5 or 6gbps USB3.1 uses voltage differential pre-&amp;post equalized logic. Adaptive pre-emphasis in mV to vary the driver levels at VHF levels or beginning bit pulse shape followed by the remainder of the bit.  De-emphasis is done in the spectral domain to maximize the eye patterns with test patterns.  The pre-emphasis is controlled by amplitude and pulse width while de-emphasis is controlled in a DSP in 100MHz increments (vaguely like CATV  cable signals do to equalize the spectrum in +x dB/decade of the amplifier to offset attenuation. )

However data spectrum has different slopes for the low band and high band around 1GHz thus two different generator patterns G1 &amp; G2 are used for "training" and characterizing the link spectral characteristics before transmission can occur using loopback error rate testing.   Low speed data is randomized digitally while the high speed algorithm is sufficiently encoded to guarantee enough transitions for the PLL to capture the data rate.  Skew and phase lock are critical elements of the PHY interface.  The burst rate is isochronous. 

Group delay distortion can also be equalized in the DSP receiver according to patterns used with a variable frequency pulse or PFM, as any distortion would be seriously affect the eye pattern. I did not find this in the spec, so each Mfg can develop their own method of optimization in the receiver.

If you tried to probe with 0.5 pF FET buffered probe  you might get an idea but affect it would alter the channel characteristics and affect the signal error rate, so test jigs are quite complex.   Signals are equalized separately to define the common mode and differential mode is controlled to offset cable tolerances  , which must be quite rigid in both mechanical and electrical response. EMI control is a challenge to say the least.

Any attempt to monitor it must not disturb the signals therefore a wideband -10 dB custom stripline directional coupler may be considered with sampling DSO's to monitor the interposed signals with &lt;1dB loss.

This is not something you can generate with an FPGA nor are the following excerpts adequate to design an interface, but I extracted part of the big 3.1 spec just for giggles.