Are AVR multi-cycle instructions pipelined?
Simple answer is nope. An instruction taking 2 cycles to complete will block any further instructions until it is done.

Obligatory quote from ATMega328P datasheet:


  Instructions in the program memory are executed with a single level
  pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory


The pipeline is only single level, so the instruction being fetched cannot start execution until the one currently being executed is finished.