Voltage graph of capacitor with AC source
Let's approach this by analyzing what happens as Vclk cycles between 0V and 1V. Assume you just turned on Vin and Vclk, so no charge has been built up yet. Namely, the two capacitors are "empty", meaning they have 0V across them. We'll also assume the diodes are ideal.

Step 1:
Vclk is initially low. If the left capacitor has no voltage across it, both sides of the capacitor are at the same potential: 0V. The left diode is forward biased because there are 2V at its anode and 0V at its cathode. Therefore current begins to flow through the diode and charging the left capacitor (initially, the current flows through the right diode as well and charges both caps, but that's not important right now). Since there's no resistance in this circuit, the capacitor charges very fast. By the time Vclk jumps up to 1V, the capacitor is fully charged to 2V across its plates.

Step 2:
Vclk jumps up to 1V. A useful property of capacitors is that the voltage across its plates will be preserved even if the source it's connected to suddenly changes. So if the voltage on the bottom of the capacitor suddenly jumps to 1V, the 2V difference across the capacitor is preserved, and the top plate jumps up to 3V. The left diode is now reverse biased, so Vin gets cut off. The right diode has been forward biased this whole time, so current is flowing through it charging up the right capacitor. Current flows out of the left capacitor into the right capacitor until they equalize.

Step 3:
Vclk falls back to 0V. The top of the left capacitor falls back down too, allowing the left diode to be forward biased again. Current again flows from Vin into the left capacitor, charging it back up to 2V. The right diode is reversed biased now, so the right capacitor stays charged at 3V.

Step 4:
Vclk rises back to 1V. Left capacitor bumps up to 3V, again charging the right capacitor to 3V.

And so on and so on, repeating steps 3 and 4 forever, maintaining 3V on the right capacitor.

In real life, the components are non-ideal. So there are forward voltage drops across both diodes. This means the total voltage on the right capacitor, after steady-state is reached, will be:
$$V_{cap}=V_{in}+V_{clk_{high}}-2*V_d$$
Where Vd is the forward voltage drop of the diodes. Also, there is resistance in the circuit, which slows down the charge time of the capacitors, which affects the design choice for frequency and duty cycle.