Decoupling capacitors on bottom layer in non-BGA packages?
As I said in my comment, decoupling GHz frequencies is hard. It requires a proper power integrity strategy including:

a range of capacitor values to achieve your target impedance profile;
said capacitors being chosen such that resonant peaks are minimized; and
additional capacitors on the planes to suppress the plane resonances at the appropriate locations.

This is because decoupling capacitor become inductive at high frequencies. You need to use high value capacitors for the low frequencies and multiple low value capacitors for the high frequencies in order to achieve your target impedance profile.

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In addition, at such high frequencies the planes can resonate at specific locations. This means that your planes start behaving like antennas. The high frequency currents can excite the planes, if you do not suppress the resonances. This depends on the geometry of the power planes. You really need a field solver, like SI Wave from ANSYS, to do this properly.

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Having said that, there are a few things you need to keep in mind. The point of the decoupling capacitors is to provide a low impedance path for the high frequency currents between the power planes. The problem is you need to have a relatively high impedances traces and vias in order to reach said planes in the internal layers. So you want to minimize the via-pad distance, as can be seen in the following figure.

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The measured inductance, as given in the source, is (nH) 0.61, 1.32, 2.00, 7.11, 15.7, and 10.3 for configuration A, B, C, D, E, and F respectively.
As you can see, it is best to put the vias as close as possible to the pads. Multiple smaller vias are better than one large via. The smaller vias may have higher inductance, but this is more then compensated for by having multiple connections in parallel.
It is generally better to put the vias closer to the capacitor while having the capacitor further away from the power pin than vice versa, since traveling on the ground plane is significantly less costly from an impedance perspective. As long as the capacitor is relatively close, the high frequency current will use it as the lowest impedance route to the ground plane.