What is going on with this zig-zag trace connected to the processor?
The point is not to connect to the ram, but to provide a reference for the timing delay caused by the signal propagating to the ram. The thing probably drives startbust at the same time it dispatches the read burst command to the ram, but does not try to actually read until shortly after the startburst in pin becomes asserted. 

It is a way to avoid having the configure the memory controller timings for each specific board layout. 

I kind of wish more high speed memory interfaces did this, it would cut out a lot of annoying faffing about.