Why does unaligned memory read require extra clock cycles?
In the case of word-aligned reads, the upper address bits (A1 .. A19) are the same for both bytes.  So the upper address bits don't change, and the whole word can be addressed in one read operation.

In the case of byte-aligned reads, the upper address bits must change, because there's a carry out of that least significant address bit.  Because at least one upper address bit does change, the read needs to happen in two operations.

Work out, on paper, the transactions needed between the CPU and the memory to do an aligned word read, and a non-aligned word read.  The issue should be clear at that point.