The problem about active low ,and how can i know it from the waveform
but how do i know it is active low from this picture?


You know the SET and RESET signals are active low, because when they were both high, the input was transferred to the output with each rising clock edge. This means SET and RESET must have been de-asserted when high. Meaning they must be active low signals.


  so for this active low reset and set,if you feed reset and set low signal,the D-flip flop can't operate normally;but for active high reset and set,it can operate normally.Is my thinking correct?


An active-high RESET and SET could be implemented by just putting an inverter in front of each of the existing RESETn and SETn inputs. If you did this nothing about the behavior of the circuit would change except the RESET and SET behaviors would happen when the corresponding inputs are high rather than low (and there would be a slight delay in the flip-flop recognizing these inputs). In case both SET and RESET were asserted (which would now mean they were high), you would still see both outputs go high.

Edit 

In a comment on another answer you said,


  When Set and Reset are both active,you mean both active high? or active low?


I think you misunderstand what "active high" and "active low" mean.

These terms indicate how the circuit is designed, not the state that they are in at an instant in time.

"Active low" means the circuit is designed so that a low voltage (for example, 0 V) indicates a logical "true" value, or a logical "1" or an asserted state; while a high voltage indicates "false", "0" or the de-asserted state.

"Active high" means the opposite. The circuit is designed so that a low voltage indicates "false", "0", or de-assertion, while a high voltage indicates "true", "1" or the asserted state.

To put it in a table, an active-low design might have 

voltage    1/0     meaning
--------------------------
0 V         1      asserted
5 V         0      de-asserted


while the complementary active-high design would have

voltage    1/0     meaning
--------------------------
0 V         0      de-asserted
5 V         1      asserted


Given a circuit, you can't change it from active high to active low just by changing its input voltages. You have to change the circuit design to change it from an active low circuit to an active high circuit.

(Caveat: Due to De Morgan's rules, the same physical gate might be used in either an active-low or active-high circuit. But a circuit that implements a NAND gate in active high logic would implement NOR in active low logic)