Initializing a variable with the input of a process
With the code as is sel will take the initial value of sel_slv and never change. Moving the variable initialization statement after the begin makes the process respond to changes in sel_slv as expected.

entity control is
  port (
    sel_slv       : in   std_logic_vector (1 downto 0);
    in0, in1, in2 : in   std_logic_vector (31 downto 0);
    out           : out  std_logic_vector (31 downto 0))
end Control;
architecture rtl of Control is 
begin
  mux : process(sel_slv, in0, in1, in2, in3)
    variable sel : integer;
  begin
    sel := to_integer(unsigned(sel_slv));
    case sel is
      when 0 =&gt;      outp &lt;= in0;
      when 1 =&gt;      outp &lt;= in1;
      when 2 =&gt;      outp &lt;= in2;
      when others =&gt; outp &lt;= (others =&gt; '-');
    end case;
  end process mux;
end rtl;


Reminder for next time: Variables initialized in a process are initialized during elaboration (compile) time. 

From the VHDL spec:

IEEE Std 1076-2008 14.6 Dynamic elaboration para 2 b): Execution of a subprogram call involves the elaboration of the parameter association list. That doesn't include the variable declaration, see 14.4.2 Elaboration of a declaration, 14.4.2.2 Subprogram declarations, bodies and instantiations and 14.4.2.5 Object declarations. A declaration here can be thought of as reserving space and providing an address for a stack variable.