System Generator: Problems with CORDIC block at getting the bitstream file
The error means that your design can not run as fast as you are telling the tools it needs to. There are a few possible strategies:


If you are doing this as an experiment without specific requirements, you could try a smaller divider, that is more likely to work at the clock frequency you have.
If your board allows you to select a different clock frequency for the FPGA, you can do that, and update the constraints with the lower frequency.
You can add registers to your design to reduce the length of the critical path, as described here.
You can add a clock divider to your design. There is an example in Pipelining and clock frequency issue.