Why in 8085 microprocessor, the clock frequency is divided by two?
One reason to divide a clock by two is to obtain an even 50% duty cycle square wave. It may be that the 8085 internally uses both clock edges, and wouldn't function if one half of the cycle happened to be much shorter than the other. 

In the days when the 8085 was new, those nice canned oscillators weren't common, and people often cobbled together clock circuits out of discrete crystals, capacitors, and logic gates. Dividing by two ensures that you have equally spaced rising and falling edges.

As for 6.144MHz, you will find that it can be divided by an integer to get common baud rate values, at least up to 38400. 



follow up ...

Looking at an Intel data sheet for the 8085, there are three interesting statements



  The 8085 incorporates all of the features that the 8224 clock generator and 8228 system controller provided for the 8080A


  X1 and X2: Are connected to a crystal, LC or RC network to drive the internal clock generator. The input frequency is divided by 2 to give the processor's internal operating frequency.


  CLK: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input period.



So, speculations about using the odd edges of the clock to move stuff around internally aside, it becomes apparent that when they designed the 8085, Intel was replacing the need for a special clock controller by integrating that feature into the chip. Dividing the X1-X2 timebase in half before outputting it as CLK ensures that the system gets a nice even duty cycle, if nothing else.