How to test synthesizability and time characteristics of an isolated Verilog module?
Timing characteristics can only exist after your design has been applied to a specific FPGA – an Ice40HX will have a different timing than a LatticeSC ; not even mentioning that the two of them have different logic units and the same verilog would be synthesized to two different netlists.

However, you should be able to synthesize your code for specific FPGA without placing it on an actual bitstream.

On top of that: The number of pins on the package has absolutely nothing to do with the architecture that you implement inside the FPGA. I don't know how you've got that idea.