Why can't I implement a frequency divider using a mux in this way?
Think about what each part of your circuit does.

MUX3

All this is doing is saying if CLK1 is high, then output 1. If CLK1 is low, output 0. What is the purpose of this mux? Simply MUX3 = CLK1

MUX2

Again, if MUX1 is high, output 0, if MUX1 is low, output 1. So basically MUX2 = !MUX1

MUX1

What for example happens when CLK1 is low? It selects In0 of MUX1. In0 is simply the inverse of the output of MUX1. 

So in other words MUX1 = !MUX1 - you've made an oscillator that will toggle at whatever the propagation delay of the not gate is. Uncontrolled inverter loops like this are almost never a good idea.

What happens if CLK1 is high? Well, you get MUX1 = MUX1, so basically the output will hold whatever state it had previously.



I think the theory of the interview question lies in the fact that a 2-input MUX is functionally complete - you can use multiple muxes to make any logic gate.

One of those is that a mux can be configured as an AND gate with one input inverted by simply tying the IN1 pin to GND. You can then simply use two of these to create an S-R latch.

Once you have an S-R latch it is very easy to build registers, and then counters.