Fatal Error for simulation of Full Adder in ModelSim
With modelsim you need to make sure your are compiling all the files, and that your simulating the correct module. In this case you need to make sure that your testbench is the 'toplevel' module being simulated. 

You need to eliminate all errors before you can reliably run your simulation. I'm not positive, because usually I keep most of my wires the same name, but I think you have your port map wires backwards. Since you haven't posted the error (you should always post the error) I can't tell you what is going on.

You may want to go out and do a few vhdl tutorials to learn how modelsim works before you start rolling your own stuff. There are many others if you google.