How does a computer know when to "get" the output from the ALU?
Let's say that you work out the worst-case propagation delays through the ripple-carry adder and all associated logic as being \$178\:\text{ns}\$ (this includes both subtraction and addition, let's say.) Then you might choose to arrange the minimum clock period to be \$250\:\text{ns}\$ so that you are certain there is enough time. If so, then you might latch the inputs to the ALU on the prior clock period (assuming you can latch both inputs on the same clock, which may not be true) and latch the output of the ALU on the current (following) clock period. That's fine, because you know for sure that there has been enough time for the ALU output to stabilize.

That's not the only way, though. You might have a system which, for other design reasons, has a minimum clock period of \$100\:\text{ns}\$. So, to be safe you arrange things so that you latch the inputs on \$c_0\$ and then only latch the output of the ALU on \$c_3\$ (\$300\:\text{ns}\$ later.) The faster clock may serve other uses well, despite causing the addition/subtraction to take even longer than it might had the minimum clock period been longer. Of course, you could also consider latching the output on \$c_2\$ in this case because \$200\:\text{ns}\$ is longer than the required 
\$178\:\text{ns}\$.

The above is for clocked CPUs. There are also asynchronous CPUs where the reasoning and methods mentioned above are handled differently. That's a whole different area of research and the answer would be very much different than I gave above. But I don't know much about these, so I'll hold short of saying more about it.

These are all design choices, though. It's not left to the electronics itself to "guess at." (Not in my experience, anyway.) The designer works out the details and makes decisions. Where I was involved some, the design is simulated first. Then it is placed on a huge cube of FPGAs that can run the design almost at full speed. A little "pod" reaches out from the cube to plug into a CPU socket on a real board for further testing. All this before committing to an ASIC and an IC FAB run.