Easier way to implement a large look-up table in Verilog?
Since the angle data exists in excel/MATLAB, you could export it as a file of hex/bin values, then load it with $readmemh()/$readmemb(). For example:
angle1.hex :
1753D // hex for 95549
DCD03 // hex for 904451
...

Then load the file in Verilog:
reg [31:0] angle1, angle2, ..., angle8 [0:7];
...
initial begin
    $readmemh(&quot;angle1.hex&quot;, angle1);
    $readmemh(&quot;angle2.hex&quot;, angle2);
    // ...
    $readmemh(&quot;angle8.hex&quot;, angle8);
end

You could put all 64 entries into one file in a single hex file. Doing thins means you will need to adjust your indexing to map correctly (ex:angle3[i] would probably become angle[16+i]).
EDIT 19 Dec 2020:
If the synthesizer does not support initial or $readmemh then modify the excel/MATLAB export to prefix the assign angel#[#] = and use the `include feature. This will allow you to separate the file management of your angel values and RTL with the compiler seeing it as unified. If the synthesizer support SystemVerilog, you use reduce the line of code of the generated file with the unpacked array construct '{}, but it is basically visual differnce.
angles.txt:
assign angel1[0] = 95549;
assign angle1[1] = 904451;
...

Verilog:
...
wire [31:0] angle1, angle2, ..., angle8 [0:7];
...
`include &quot;angles.txt&quot;;
...

)ther alternative: Emacs has verilog-mode which has a AUTO_LISP and AUTO_PERL expansion templates. There also an embedded Perl, Ruby, Python, and probable other languages that can be used to read excel/MATLAB and generate/expand the necessary code, All depended on what language(s) you are accustom to. Here is a link to an old answer I did on Stack Overflow related to these options https://stackoverflow.com/a/34230970/1959732

Other thing with your code:
Synchronous logic should be assigned with non-blocking (&lt;=) assignments. This will help with simulation vs synthesis mismatches.
Having if (i == lvl_select) in the for-loop eliminates the need for the for-loop. You can just get the index of the angle from lvl_select directly. Depending on your synthesizer, this might reduce the overall area/gate-count.
always @ (posedge clk)
begin
    h &lt;= 0;
    mh &lt;= 0;
    z &lt;= 0;
    ml &lt;= 0;
    l &lt;= 0;
    if (theta &lt; angle1[lvl_select])
        z &lt;= 1;
    else if (theta &lt; angle2[lvl_select])
        mh &lt;= 1;
    else if (theta &lt; angle3[lvl_select])
        h &lt;= 1;
    else if (theta &lt; angle4[lvl_select])
        mh &lt;= 1;
    else if (theta &lt; angle5[lvl_select])
        z &lt;= 1;
    else if (theta &lt; angle6[lvl_select])
        ml &lt;= 1;
    else if (theta &lt; angle7[lvl_select])
        l &lt;= 1;
    else if (theta &lt; angle8[lvl_select])
        ml &lt;= 1;
    else
        z &lt;= 1;
end