What is wrong with this SPI implementation
You have a very long SPI bus running across several PCBs. Not only is this not recommended for SPI &mdash; it was originally designed for chip-to-chip communications on a single PCB &mdash; you have it connected directly to your CPUs without any electrical buffering.

Any induced transient (which could include ESD while hot-plugging) on any of the bus lines could easily drive any of your CPUs into "CMOS latchup", in which a parasitic SCR is activated that essentially shorts Vdd to ground. Physical damage from the resulting temperature rise can be permanent.

SPI is particularly easy to buffer, since each of the lines is unidirectional. You should include such buffers on the next revision of each of your PCBs.