How do I route many FPGAs in JTAG chain?
You should read through the relevant Xilinx documentation; for Spartan-6's that would be UG393 (Spartan-6 FPGA PCB design &amp; pin planning guide), UG380 (Spartan-6 Configuration), and possibly others.  No doubt Xilinx have similar documentation for their other product lines.

With regard to your particular problem, there is some fairly specific advice in those documents on how to lay out the JTAG clock.  I also strongly recommend that you use a series termination resistor (22-100 ohms) on each TDO->TDI link, as close as possible to the TDI pin.