What does it mean to sample a clock?
If besides the clock you have some signals to sample as well, you have what is called a clock boundary crossing. There are various techniques for doing this reliably. Most often it involves the use of a FIFO with two clocks, with handshake logic between the FIFO ports specially designed to be resampled into each clock domain (for example, using Gray code FIFO counts.)

More about this here: https://www.eetimes.com/document.asp?doc_id=1276114#

And here: http://www.ece.utep.edu/courses/web5375/Notes_files/ee5375_asynch.pdf

And here: http://www.fpga-faq.com/FAQ_Pages/cdc_wp.pdf

If you are only sampling a clock signal, your sampling clock needs to be at least 2x the input clock rate (that is, the Nyquist limit) to capture all the state transitions. As a practical matter the sampling clock will need to be even higher than Nyquist rate to account for less than perfect 50% input duty cycle: your sample clock period has to be no less than your shortest input clock high or clock low period.

Finally, part of clock domain crossing is the inevitable issue of metastability: the failure of a sampling flip-flop to properly resolve to a valid state because its input sample/hold timing isn't being met. Using two flop stages will reduce failures to acceptable levels in most cases.

More about metastability here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01082-quartus-ii-metastability.pdf

Now, what happens to the duty cycle of the re-sampled clock? It will vary depending on the frequency ratio and cycle-by-cycle phase relationship of the two clocks. You will need to account for that in your logic, for example by using edge detection.