FPGA dsp-slices highest sampling rate possible
Are there any techniques that would allow processing in even higher rates?


Exactly! Several. Generally, you could just accept some processing delay and have multiple multipliers that "serve" the same coefficient, say 10 per coefficient. While the first one is still multiplying, you could feed in the new value to the second one and so on. Effectively: you build 10× the filter coefficient multipliers (but only one time the delays/storage). That way, you need 10 times the multipliers, but can let them run at 1/10 of the rate.

For specific use cases of the filters, you can become a lot more efficient than that.
Let's take a very common problem: you want to filter to a partial band, before you decimate.

Assume you have a filter with \$G\$ taps; naively, you'd for each incoming sample (at rate \$f_s\$)have to shift the contents of a register set by one step, add the new sample in front, and have a multiplier for each coefficient and an accumulator for the result. That means \$G\$ multipliers running at \$f_s\$ each.

Now, after you've done that, you throw away all but the 0., G., 2G., 3G., sample (that's your decimation). Seems wasteful, doesn't it?

Instead, you could say, hey, let's do a polyphase decomposition of the filter: Say, in \$K\$ phases. That means that the 0., \$K\$., \$2K\$.,  … coefficient go into "subfilter" 0, the 1., \$K+1\$., \$2K+1\$, … into subfilter 2, and so on up to subfilter \$K-1\$.

Now, you just take your input, and deinterleave it to these subfilters.

That means you now have only \$H/K\$ multiplications that run in every clock cycle.

You calculate the result of these filters, and only once your deinterleaver is trough with one full cycle, add up the results.

But wait, you're on an FPGA; so while you're already filling the next sub-filter, it's totally OK to pipeline your multiplications, since it's not important to have the multiplication done when the next subfilter starts being shifted; it's important that at some point in time, all values have been added to the final accumulator. 

This allows your multipliers to run at a significantly lower rate than the input: at the output rate.

The same trick exists for interpolating FIR filters and thus even for rational resamplers: the filter can always run at the lower of the input- or output rates. Nice!