Transition state between 0 and 1 in logic gates
It's not the mystery other comments are saying. Consider the standard CMOS inverter:



There are two FETs, one n-channel and one p-channel. Normally one is on and one is off. What happens in the intermediate voltage range? Both of them are partly on. This connects the power rail to the ground rail and a substantial current can flow. This is called "shoot-through" and can damage the gate if left in that state for more than a very short time. Unfortunately every time you want to change between 0V and 3.3V or vice versa you have to go through the intermediate voltages - it's therefore important to change quickly for a nice clean transition. The transition looks like a "slope" when plotted against time. A particular input slope will produce an output slope as the gate swings in response to its input. (It would be nice if someone found a graph of this and added it to the answer).

What if there are two inputs? Suppose you have a NOR gate with A=1 B=0 output=0. Then consider transitions A: 1->0 and B: 0->1. At the end the output will still be 0, but it may go high for a very short time in the middle. This is called a glitch.

Another interesting case is having an intermediate value on the input of a DFF when its clock input is triggered. This can put it into a metastable state until the next clock input arrives. This is a real problem when transferring signals between different clock domains and needs special design consideration.