Difference between Gate Instantiation and SystemVerilog operator
There are actually different concepts.
When you use AND gate it means that you have two ( or more) &quot;one bit&quot; inputs and the output is zero unless all of them are high.
On the other hand the operator &quot;&amp;&quot; means bitwise &quot;and&quot;. It means that if you have two ,let's say, four bits binary numbers &quot;a&quot; and &quot;b&quot;, &quot;a &amp; b&quot; will be also a four bit binary number,in which each bit is the result of and operation on respective bits.
For example :
A = 4'b1001

B = 4'b1110

then : 

A &amp; B = 4'b1000

If you want to use &amp; instead of AND gate you have to remember that you have to assign the value to it:
assign out = a &amp; b

above line is equal to:

AND(out,a,b);

Conclusion:
as far as we are working with one bit inputs, it doesn't make difference but we have to remember that the concepts are different.
*By the way for the above example if you use &amp;A the result will be 0. It actually ands all of the bits in A. These kind of operators are called Reduction operators. So &amp; operator has two usages:

Reduction operator : ands all of the bits
Bitwise operator : ands the bits of two different input respectively and returns the result.

We can model these two usages with AND gate:
For example A =4'b1010
&amp;A = AND (out,A[0],A[1],A[2],A[3])