How can I improve my testbench for testing a 1024x4 RAM memory in Verilog
Uncommenting your read code, your ReadWrite signal was 1 for all your read and write calls.
You could combine your loops to interleave the writes and reads, dynamically changing ReadWrite.
integer  i, j;

initial #28830 $finish;

initial begin  
    Enable = 0; 
    DataIn = 4'b0000;
    ReadWrite = 0;
    X_Address = 0;
    Y_Address = 0;

    for(i = 0; i &lt; 32; i = i + 1) begin
        #5 X_Address = i;
        for(j = 0; j &lt; 32; j = j + 1) begin
            #5 Y_Address = j;

            ReadWrite = 0;
            write(X_Address, Y_Address, $random);

            #10;
            ReadWrite = 1;
            read(X_Address, Y_Address);
        end  
    end                
end 

You could simplify it by moving ReadWrite inside the tasks (like Enable).