SystemVerilog in ModelSim ignores negedge/posedge when monitoring
IEEE Std 1800-2012 § 21.2.3 Continuous monitoring:

When a $monitor task is invoked with one or more arguments, the simulator sets up a mechanism whereby each time a variable or an expression in the argument list changes value—with the exception of the $time, $stime, or $realtime system functions—the entire argument list is displayed at the end of the time step as if reported by the $display task. If two or more arguments change value at the same time, only one display is produced that shows the new values.
Only one $monitor display list can be active at any one time; however, a new $monitor task with a new display list can be issued any number of times during simulation.

In other words, A $monitor task is executed it creates a singleton process that displays the value of the listed variables at the end of the time step when ever one of those variables change.
For your purpose, you should use $display or $strobe instead of $monitor.
$display prints the immediate value of variables, while $strobe prints the final value in the time step. Neither start an automatic triggering process like $monitor.  For details refer to IEEE Std 1800-2012 § 21.2.1 The display and write tasks and § 21.2.2 Strobed monitoring