Error (10536): VHDL Loop Statement error at InstructionMemory.vhd(31): loop must terminate within 10,000 iterations
It looks like you are trying to synthesize.  File access is not synthesizable.  "Compilation" in Quartus (and Vivado and similar tools) tries to convert the RTL, such as your VHDL, into hardware resources.

What you have might be applicable to simulation, but it is not appropriate for synthesis.