Designing a Combination Lock FSM: Converting State Diagram to Logic Gates
You can either do it the traditional way with pen, ink, state tables, the TTL Data Book, or simply write it directly in VHDL or Verilog, following the partial example below.
Which approach is best depends on circumstances.
If this is homework, you probably have to do the former.
If you're being paid to get things done, and you don't do the latter, start looking for a new job.
   type State   : State_Type is (Start, Red_1, ..., Wait);
   signal State : State_Type;
   signal argb  : std_logic_vector(3 downto 0);

   argb &lt;= a &amp; r &amp; g &amp; b; -- simplify condition testing...

   Process(Clk) is
   begin 
      case State is
      when Start =&gt;
         if argb = &quot;1100&quot; then
            State &lt;= Red_1;
            u     &lt;= '0';
         elsif a = '1' then
            State &lt;= Wait;
            u     &lt;= '0';
         end if;
      when -- and so on for all the other states 
      end case;
   end process;