What is the difference between reg and wire after synthesizing?
Neither of your examples will contain any latches or flip-flops. The always block in your second example is combinational, not sequential (if it were to synthesize a latch, what clock would control that latch?). You have to use a reg type for y simply because it appears on the left side of an assignment statement inside an always block. Many people consider this a disadvantage of Verilog, which is hard to argue with. In VHDL, a signal type would be used instead of both wire and reg, removing the confusion.