APB PENABLE stays only for one PCLK regardless of PREADY signal
This is no a complete answer but too big for a comment:

I have designed countless AXI, AHB and APB modules. From what I can see the response to your RDY is wrong. The application note you mention clearly shows the support for wait cycles.

What I can think of is:


The Cortex APB module is broken or does not support pready.
The RDY you generate is not the one the core sees.
The waveform does not correspond to what is really happening (which is more or less a variant on 2. above.)


My next step in debugging would be to try:


Remove the peripheral and tie pready low. Your processor should then 'hang' when accessing any APB address. 
Make a APB peripheral which returns e.g. the address bits on reading and see if the read access for that works.