verilog module inside an if-statement
It is important to remember that with Verilog you are describing hardware, not writing software. Modules are instances of hardware. They can't be called and they don't return a value.

You can't instantiate a module conditionally within an if statements (*), and you definitely can't instantiate them within procedural blocks. If you consider what such a statement would describe it becomes clear as to why not. With a module instantiation within an if statement you are basically saying:


  If signal is high, make some hardware appear; otherwise delete the hardware.


FPGAs can't work like that. All hardware is described and fixed at synthesis.

Instead what you need to do is instantiate your hardware (in this case right shift module) not within the if statement or procedural block. Connect the output of that module to a wire. Now your hardware is always present, regardless of the control signals. So how do you make use of it conditionally?

This is quite simple. Within the if statement you can use your wire. If a condition is met assign the wire to whatever signal you are controlling. Otherwise assign some other signal.

wire module_output_wire;
...
always @ (...) begin
    ...
    if (some_condition) begin
        some_signal &lt;= module_output_wire;
    end else begin
        some_signal &lt;= something_else;
    end
end
...
your_module (
    .whatever(module_output_wire)
);


The reason this now works is because rather than trying to infer transient hardware, you are now inferring a simple multiplexer. The inputs to the multiplexer are the module_output_wire and something_else, the select signal is some_condition, and the output of the multiplexer is some_signal. The hardware always exists, but you don't always need to use the output value.

As an alternative, you could make your right shift code a function. A function in Verilog can be called in the way you show on the commented out line in your code. In the case of the function you are inferring hardware that is always there and the output of the hardware is a wire (the return value of the function) which you can then use in an always block.



(*) With the exception of in Verilog 2001 Generate statements, but in that case the condition is known at compile time, it doesn't depend on the value of a signal.