How to debug FPGA designs
The key to reduce the simulation time is splitting the design into smaller sub-modules which can be simulated or even verified much faster. Thus, you will identify and fix bugs even faster. 

Of course, at some point you have to simulate the overall design (or larger parts of it). But, if you design the interface of the sub-modules carefully, then only a small number of bugs will usually need to be fixed. And every indentified bug in the larger design can be used to improve the testbench for the sub-module.

Yes, the simulation of the Xilinx Memory Controller takes up a lot of time, but it is worth. Debugging a design by using the on-chip logic analyzer (Xilinx Chipscope, or Xilinx Vivado) is also possible, but you will have to place &amp; route your design every time, you are adding a signal to the logic analyzer to identify the bug at first. Then to fix the bug, you have to synthesize it again. This is often more time consuming, then simulating even a compelx design.