Is it possible to generate internal reset pulse in verilog with machxo3lf fpga?
The datasheet on MachXO says that


  The MachXO registers in PFU and sysI/O can be configured to be SET or
  RESET. After power up and deviceconfigured, the device enters into
  user mode with these registers SET/RESET according to the
  configuration set- ting, allowing device entering to a known state for
  predictable system function.


Therefore, the simplest thing you can do is to configure all regs that need to be initialized with initial verilog construct or the equivalent understood by the tools.

If you still need a 'traditional' reset pulse, you can do it like this:

reg [3:0] rst_cnt;

wire rst_n = rst_cnt[3];

initial rst_cnt=4'd0;

always @(posedge clk)
if( !rst_n )
    rst_cnt &lt;= rst_cnt + 4'd1;


This code again relies on the ability to set initial (power-on) values for the flipflops of MachXO.