How do I observe a PLL's frequency tracking once the lock has been acquired?
how the output frequency tracks the input say for a step change in
input frequency

If you look at the control voltage into the VCO, its average value (ignoring ripple) is representative of the output frequency produced: -

If this filtered control voltage is stable (not end stopped) then the PLL is in equilibrium or has settled to a constant steady state error (ignoring noise).
So, if you made a step change to the reference frequency, you would see the classic 2nd order response of the control voltage: -

Picture taken from here
But, because there are many, many types of loop filters and amplifiers you could get variations rather like you would with a PID controller: -

Picture taken from here
In other words, with a simple proportional control (kp), there will be a frequency lock error because the loop gain is finite. If the gain were made too high then it could become unstable. So, the integral term becomes useful (ki) and this can reduce the frequency error to zero without necessarily causing instability. The differential term (kd) can act as a &quot;brake&quot; on the control loop and significantly reduce overshoot.
I'm stating all this because it is not 100% clear what your control loop actually is.