Forming synchronous SR flip flop from asynchronous SR flip flop
Two is correct, 4 is wrong. 4 should have S at the top, R at the bottom.

If, in 4, input to top left nand gate and E are both high then input to top right nand gate goes low setting the Q output. Q has been set by input to top left nand gate going high so this input should be called S and the signal between the top two gates should be called !S.