BJT one stage amplifier with current source
The corrected circuits diagram looks like this 







simulate this circuit &ndash; Schematic created using CircuitLab

For CE amplifier \$R_L\$ >> \$R_C\$ Do you know why? 

The \$Q_2\$ in the current mirror need some voltage "headroom" (\$Q_2\$  cannot be saturated). I Assumed 1V of a headroom. 

Therefore \$Q_2\$  base voltage needs to be around \$1.7\textrm{V}\$. And \$R_1\$ and \$R_2\$ voltage divider do just that. The voltage divider current should be at least ten times larger the base current. Which is not the case here.

To get the maximum voltage swing I decided to pick the \$V_{Rc}\$ value as: 

$$V_{Rc} = \frac{(V_{CC} - V_E)}{2} = \frac{10\textrm{V} - 1\textrm{V}}{2} = 4.5\textrm{V}$$ 

So, if \$R_C = 1\textrm{k}\Omega\$ we have : 
$$I_C = \frac{4.5\textrm{V}}{1\textrm{k}\Omega} = 4.5\textrm{mA} $$

\$R_3\$ resistor bias the current mirror and we need \$4.5\textrm{mA}\$.  

$$R_3 = \frac{10\textrm{V} - 0.7\textrm{V}}{4.5\textrm{mA}}= 2\textrm{k}\Omega$$ 

Now we can choose the voltage divider resistors values. 
Since \$I_C = 4.5\textrm{mA}\$ and the \$\beta_{min} = 100\$ I decide to pick  the resistor values this way. 

$$R_2 =\frac{V_B}{5\cdot I_B} =\frac{1.7V}{5\cdot \frac{4.5\textrm{mA}}{100} }= 7.5\textrm{k}\Omega$$ 

$$R_1 =\frac{V_{CC} - V_B}{6\cdot I_B} =\frac{8.3V}{6\cdot \frac{4.5\textrm{mA}}{100} }= 30\textrm{k}\Omega$$

Also, as you can see I add \$C_E\$ capacitor to increase the gain. 

Without this additional capacitor, the voltage gain is very low. Why? 

The CE stage gain is \$\Large\frac{R_C||R_L}{r_{e1}+r_{o2}}\$ where \$r_{o2}\$ is \$Q_2\$ output "resistance" seen from \$Q_2\$ collector into \$Q_2\$. And of because this gain is small. The\$r_{o2}\$ "resistance" is large so, the stage voltage gain will be very small.    

By adding \$C_E\$ capacitor we are bypassing (shunt) this large output resistance by a very small \$X_C\$ capacitive reactance. 

$$A_v = - \frac{R_C||R_L||r_{o1}}{r_{e1}} \cdot \frac{\beta}{\beta+1}$$ 

And now you can play with this circuit in your circuit simulator program.

Do you see any advantage of this topology?