OLA adder and signed digit vhdl design problem
Is there a special conversion happening?!

Your image for slide 25 corresponds to figure 9.10 found on Page 506 and slide 27 corresponds to table 9.3 found on Page 507 in the book "Digital Arithmetic" by Miloŝ D. Ercegovac and Tomás Lang, 2004, ISBN: 1-55860-798-6.

If you look in the book the text below figure 9.10 (b) on Page 506, Example 9.2:


  The signals in Table 9.3 correspond to Figure 9.10(b) and signed bits
  are encoded using 9.18.  
  
  Note that during cycle 0 the result digit z0 - 1 is produced. Although this might be interpreted as an overflow, the range of the result remains less than 1 since the next digit is -1. See also Exercise 9.10.


9.18 is given on Page 505 -  


  


These are not present on your not shown slide 26.

And under 9.5 Exercises, MSDF Addition/Subtraction, Page 537:  


  9.10 Consider radix-2 online addition with operands satisfying x + y &lt; 1.   
  
  
    (a) Perform the addition algorithm to show that if z0 = 1, then the next nonzero result digit must have a value -1.
    (b) Devise a
    modification to the online addition algorithm to produce z0 to 0 and
    develop the corresponding design.
  


A check of the ERRATA shows nothing affecting these pages under Chapter 9.

You're not demonstrating any VHDL code. Why the vhdl tag?