Help on defining the 8-layer stack-up for a high speed design
To me, option C provides no advantage over a 6-layer stackup. So it seems like a waste of money. Option C might make sense if you included two or more POWER planes (and if those power planes were actually needed). So I am inclined to rule out option C.

I don't care for option A, because it will be difficult to get desirable results for the breakout traces on top and bottom. Either the breakout traces will be excessively wide, or the impedance will be quite high compared to signal 2 and signal 3. But it could work OK if trace impedance is not a significant concern.

So of all your choices, I guess I like option B the best. It has the same problem as A, but the magnitude of the problem should be less.

But I would also urge you to consider using 6 or 10 layers (unless the board is not really sensitive to impedance issues).