Z80 Binary Front Panel Design
I would suggest using a CPLD or FPGA to interface the bus to something like a 16x8 LED matrix.  Such a design would make it possible to switch among different display modes (e.g. it could have a mode that captures the address of /M1 cycles and would thus display a program counter in addition to the address bus).  If you use a multiplexed LED, it would be good to have the CPLD/FPGA keep a count of what fraction of the time each light should be on, and adjust the brightness of the LEDs accordingly.

Another possibility would be to use a fast ARM chip to watch the bus and handle things in real time.  It's possible for an inexpensive ARM7-TDMA to sit on a 1.19MHz 6502 bus and emulate a RAM chip (even without access to any signals other than A0-12 and D0-D7!); a 4MHz Z80 bus might be a little harder, but Z80 doesn't do things on absolutely every cycle the way a 6502 does.