IR2101 high side internal structure
The path thru the lower OR gate is DC_coupled.

The purpose of the various modules in the upper path is to produce behavior that appears as DC_coupled, but also achieves level translation, with low propagation delay, that draws low standby or quiescent current.

Accordingly

----- logic changes from the upper OR gate are differentiated in the "pulse generator"
 and converted into 50? nanosecond pulses; 

----- the narrow pulse will turnon one of the FET/resistor level-translators, and the "pulse filter" (possibly AC_coupled thru a high-voltage on-chip capacitor) validates the incoming level-translated pulse, and then generates another pulse to control the Set_Reset latch

For really high voltages, the pulses travel thru Fiber Optic pathways.