DC coupling - How can I reduce low frequency noise?
As said in the comments and edit: Shorting \$V_{out}\$ to ground reduces noise.
Capacitive Loads

Because the LTC6228/LTC6229 is designed for high bandwidth applications, the output has not been designed to drive capacitive loads directly. Load capacitance at the output creates a non-dominant pole in the open loop frequency response, worsening the phase margin. When driving capacitive loads, a resistor of 10Ω to 100Ω should be connected between the amplifier output and the capacitive load to avoid ringing or oscillation. The feedback should be taken directly from the amplifier output. Higher voltage gain configurations tend to have better capacitive drive capability than lower gain configurations due to lower closed loop bandwidth.

Choose at least 50 Ω. Also in the application notes: feedback resistor on the other side of \$R_s\$:

When feedback resistors are used to set up gain, care must be taken to ensure that the non-dominant pole formed by the feedback resistors and the parasitic capacitance at the inverting input does not degrade stability. For example if the amplifier is set up in a gain of +2 configuration with gain and feedback resistors of 1k, a parasitic capacitance of 7pF (device + PC board) at the amplifier’s inverting input will cause the part to oscillate, due to the pole formed at 45MHz. Adding a capacitor of 7pF across the feedback resistor as shown in Figure 2 will eliminate any ringing or oscillation. In general, if the resistive feedback network results in a pole whose frequency lies within the closed loop bandwidth of the amplifier, a capacitor can be added in parallel with the feedback resistor to introduce a zero whose frequency is close to the frequency of the pole, improving stability.



Last, decoupling/bypassing \$U_1\$ In+ with a a 680uF capacitor did improve.

For single supply applications, it is recommended that high quality 0.1µF||1000pF ceramic bypass capacitors be placed directly between each V+ pin and its closest V– pin with short connections. The V– pins (including the Exposed Pad) should be tied directly to a low impedance ground plane with minimal routing.


For dual (split) power supplies, it is recommended that additional high quality 0.1µF||1000pF [9.9e-10 = 0.99 nF] ceramic capacitors be used to bypass V+ pins to ground and V– pins to ground, again with minimal routing.