CMOS inverter with gate of PMOS transistor always grounded
If the circuit that you show is for a conventional CMOS type inverter you will probably not want to analyze the lower FET transistor in the ON state when the upper FET is also in the forced ON state. The typically available commercial CMOS type parts can often source as much current via the upper FET as the lower FET can sink in the high and low states of the output respectively. Forcing both FETs on at once in the analysis will make the output go to some level toward the median between the VDD and GND as opposed to pulling the output toward GND. On some logic parts this type of operation could end up damaging the device. Note that this very thing can happen on a real circuit board if two logic signal drives are shorted together with one driver trying to pull the shorted net high whilst the other is trying to pull it low.

You can note the characteristics of a buffer part such as a TI 74AHC125 part from its data sheet at: http://www.ti.com/lit/ds/symlink/sn74ahc125.pdf
Note in the data sheet that the part has symmetric source/sink capability of +/-8mA in normal operation at VDD=5V. Also note that the abs max current ratings for the output are also specified symmetrically at +/-25mA. This indicates that the conduction characteristics of the output upper and lower FETs are nearly the same. 

When considering that the upper P-FET could be acting as a pullup or current source it is necessary that the conduction characteristics of the FET be adjusted so that the lower N-FET will be able to easily sink all of the current from the P-FET as well as any external load so that the output can pull down to a valid low voltage level. Without that the output would, as indicated before, go to some level in the no-mans land between a valid low level and valid high level.