FPGA maximum frequency : limiting factor
I suspect the difference is due to the negative coefficient in the 2nd case (according to the order of your diagrams).

Because your multiplying coefficients are all powers of 2, your multiplies can all be done by simple bit selects. For example, assuming you're doing 16-bit math, x*0.25 can be calculated as simply {2'b0, x[15:2]} (using Verilog notation). 

This means your multiplications with positive coefficients are essentially free, and require no time at all.

Multiplying by a negative coefficient, however, means making a 2's-complement calculation, requiring inverting the bits and adding 1. That "adding 1" step implies a carry chain with delay equivalent to an adder of the same width.

So now you're effectively comparing two systems that both have a critical path equivalent to two adders, and it's down to luck which one happens to synthesize with less delay.

If you're using SystemVerilog or some other higher-level synthesis tool, the tool might even notice that one of the sums in the first version can be pipelined (calculated one clock cycle in advance) and thus reduce the critical path to a single adder.