PCI based system debuging
PCIe is peer to peer so it's not possible to snoop on traffic to another card, unless you physically connect something to a PCIe link that the data traverses.  I'm not sure what those POST cards are doing, but presumably it's not sniffing.  

It is possible to use an FPGA that doesn't have a hard PCIe endpoint, it just requires building a PCIe endpoint in soft logic.  The main thing the FPGA needs are the high speed serializers that support operation at the PCIe link rate - at least 2.5 Gbps so you can bring up a PCIe gen 1 link.