Vivado LOC constraint via Verilog code
You should begin with reading the Xilinx constraints guide.

I did that for you and found this as example code:

// synthesis attribute loc [of] {instance_name|signal_name} [is] location;


The document is not very clear as where exactly you should place that code but I remembered that it should be just before the closing semicolon. In which case you should use /* ... */

INVERT inverter_instance1(in, out) /*  Here */ ;


I tried it on the following code and the inverter moved from location X0Y5 (without constraints ) to X4Y4 (with constraints).

module invrt(input in, output out);
   INV inverter_instance1(out, in) /*  synthesis BEL="A6LUT", LOC="SLICE_X4Y4" ; */;
endmodule