Interview Question, what's limiting the output frequency for the FPGA circuit?
They are most likely referring to the design failing the timing constraints (I.E., the FPGA compiler reports that things are going slower).  So, the solution would be to look at the timing report file and try to narrow things down from there. 

It's hard to say anything beyond this first step because it is very design dependant-- and that info wasn't given in the interview question.