PCB 6-layer stackup problem
3 basic rules
Rule #1: Bandwidth is not the clock speed rather the rise time f-3dB=0.35/Tr (10~90%) so you probably  want thinner dielectric than normal for lower impedance tracks

this helps keep track/gap &lt;= 5 mil  (127 um) and &lt; matched via impedance which raises L but thinner dielectrics raises C to maintain Z^2=L/C   Also  3 mil (64um) track/gap is doable by good shops.

Rule #2 avoid crosstalk with adjacent SS layer parallel tracks.
Rule #3: Use lots of microvias for PS layer connections to other layers grids and appropriate decoupling cap per IC. If a Microvia is 50 Ohms on a power supply that is 50 mOhms, how many do you need?  ( not depends on decoupling caps and rise time and ringing tolerance)
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