Controlled impedance traces necessary between line driver and series termination resistor?
The 10 ns rise time you mentioned seems rather slow for a part that specs the prop times as 6 ns (max), and 1 ns (min).  The data sheet does not give a rise/fall time spec, so let's use the prop time as a surrogate for rise/fall time.  That means we need to design the interfaces to properly handle a 1 ns rise or fall time.
1 ns in a typical board material translates to 0.5 feet, or 6 inches, assuming 2 ns/foot prop time in the board.  Any interconnect length greater than 10% of this length needs to be controlled impedance.  That means that any trace longer than 0.6&quot; needs to be controlled impedance.
This is critical for clocks and other edge sensitive signals.  If it's a data line you could probably cheat a bit on the 10% rule, up it to 20% (which would give you a bit more ringing, undershoot, or overshoot, which would mean 1.2&quot; max interconnect length before you would have to impedance match.
Note, most PWB vendors do 50 ohm trace impedances as a matter of routine.  If you just specify 50 ohm (single ended) impedance +/- 10%, you should be fine.
EDIT 1
One more thing.  You should take your post-route PWB information (stackup, trace width/thickness/length, etc) and import them into you favorite SI tool, like Hyperlynx Board Sim (or Line Sim) and do the SI analysis.
EDIT 2
You also might want to look at the answers on this thread:
Does matching impedance connectors matter in non-RF signals? Why?