3.3V IC  2.5V FPGA IO Bank
If I'm reading your question correctly, it sounds like you plan to set the pins on the FPGA as outputs and configure them with the LVCMOS33 standard. That won't work. If you take a look at Table 1-5 in your question, you will see that LVCMOS33 is not compatible as an output with a Vcco of 2.5V. Only as an input. With a Vcco of 2.5V your outputs need to all be LVCMOS25.

If I remember correctly, the I/O standard, drive strength and slew rate are on a per bank basis. So you may want to separate your inputs and outputs into separate banks so that you can use the LVCMOS33 standard on your inputs.

That being said, fast slew rates and high drive strengths are not always the best option. They can cause problems of their own. Slower transitions reduce the effects of reflection and lower drive strength will reduce ground bouncing.

To start with, I would just leave it at the defaults of LVCMOS25, Slow Slew Rate, and 12mA Drive Strength. Only adjust if you have problems. Personally, I've rarely had to change these in practice when communicating with chips. And only rarely when driving discrete transistors. But I've also never really done anything that can be considered high-speed.

From the Spartan-6 FPGA SelectIO REsources:


  High output current drive strength and FAST output slew rates
  generally result in the  fastest I/O performance. However, these same
  settings can also result in transmission line  effects on the PCB for
  all but the shortest board traces. Each IOB has independent slew rate
  and drive strength controls. Use the slowest slew rate and lowest
  output drive current that meets the performance requirements for the
  end application.


Besides that the TFP401 seems to be designed to handle a certain amount of skew on the data channels:


  In addition, skew between the three data channels is common. The
  TFP401/401A uses a 4× oversampling scheme of the input data streams to
  achieve reliable synchronization with up to 1-tpix
  channel-to-channel skew tolerance. Accumulated jitter on the clock and
  data lines due to reflections and external noise sources is also
  typical of high-speed serial data transmission; hence, the TFP401/401A
  design for high jitter tolerance.