Can size of a module's port be input as a parameter in Verilog?
You need to add parameter to the front of the line declaring maxBit. Also remove the integer after genvar. After that I was able to synthesize and simulate on https://www.edaplayground.com

FYI, I would discourage bit as a variable identifier. It is legal for Verilog but it a keyword type for SystemVerilog. All modern Verilog simulators are SystemVerilog simulators. For the most part you can mix the two by keeping the Verilog files as .v and SystemVerilog as .sv, but most simulators have a option to force all .v files to be read as SystemVerilog. There is also an potential issue when you mix the two with `include statements. To keep your Verilog forward compatible, avoid using SystemVerilog keywords as identifiers (net names, register names, module names, genvar names, etc.)