SRAM vs DRAM against single-event upsets
The most significant factor is the physical (die) size of the transistor geometries (smaller means less SEU energy required to trigger them) and then the number of them (more devices/area = higher susceptibility).  So really, reliability per bit is more related to how many bits per silicon area.  

If reliability is a concern, always include ECC and design the system &amp; software for good error checking &amp; graceful error handling.