STM32F4 Independent Watchdog (IWDG) not triggering as expected
Your init-function is probably not doing what you want.

Currently you only call the set functions if the bits are in a certain state. What you want to do is wait until the bit is in the correct state and then execute the set function.



Wrong guess:

So my guess is that the second statement is never executed and the reload register stays at the standard value of 4095 which would result in a ~8 s timeout (RC oscillator can vary quite a bit, so 6 s is in the range of what's possible).



Correct guess:

The reference manual states this:


  When the independent watchdog is started by writing the value 0xCCCC
  in the Key register (IWDG_KR), the counter starts counting down from
  the reset value of 0xFFF. When it reaches the end of count value
  (0x000) a reset signal is generated (IWDG reset). 
  
  Whenever the key
  value 0xAAAA is written in the IWDG_KR register, the IWDG_RLR value is
  reloaded in the counter and the watchdog reset is prevented.


So the first time the watchdog will start counting down from 0xFFF which results in a time of around 8 seconds with a divider of 64 in place. To prevent that, we have to "reload" the value right after enabling the watchdog.

So try this (also corrected the waiting for the bits):

//Initialize Independent Watchdog
void init_independent_wdog(void){

    IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
    while(IS_BIT_SET(IWDG-&gt;SR,0))
    {
        // wait for PVU bit reset
    }
    IWDG_SetPrescaler(IWDG_Prescaler_64);

    //Set counter value
    while(IS_BIT_SET(IWDG-&gt;SR,1))
    {
        // wait for RVU bit reset
    }

    IWDG_SetReload(256);

    IWDG_Enable();
    IWDG_ReloadCounter(); // load the wanted value
}