Spartan 6 bidirectional pins how to use
Nearly all I/O pins on nearly all FPGAs/CPLDs can be configured as either bidirectional, an input or an output. Without bidirectional pins, you couldn't implement bidirectional data buses for memory chips like RAMs and Flash EPROMs.

The general case for the I/O pin interface buffer circuit within an FPGA is: an output buffer that can be tri-state or driving; an input buffer.

When you configure an I/O pin as an input, the drive/tri-state control for the output buffer is tied to 'always tri-state' and just the input buffer is used.

When you configure an I/O pin as an output, the drive/tri-state control for the output buffer is tied to 'always drive', the output buffer is used and the input buffer is not used.

When you configure an I/O pin as bidirectional, it's all used.



Have a look at Xilinx document UG381 'Spartan-6 FPGA SelectIO Resources'. This explains all about how the I/O pins work. It includes the above diagram which shows the tri-state driver and input buffer. You'll find plenty more text on FPGA pin drivers on the internet.

To implement this in VHDL, create some internal signals called 'dataToPins', 'dataFromPins' and 'dataDriveEnable'. Then for your data bus 'DATA_BUS' you can use:


  DATA_BUS      &lt;=  dataToPins  when (dataDriveEnable = '1') else  (others =&gt; 'Z');
  dataFromPins  &lt;=  DATA_BUS;

The first line implies the tri-state output driver. You could use DATA_BUS as your input signal but using the second line and 'dataFromPins' as your input signal highlights to others what you're doing.