Is the HSync and VSync signal level kept high after data period or are they present only during single cycle
According to HDMI Specification Version 1.4a, the length of Vsync is 5 lines. Each line has Hactive + Hblank clock cycles (e.g. 1920+830 for 1080p/24Hz fp). The length of Hsync changes between 40 and 44 clock cycles for the 3D video formats.

Indeed, designers should not rely on the lengths of Vsync and Hsync signals. A common approach is to internally generate single cycle pulses when the incoming signals are asserted or deasserted. In addition, some devices don't send Hsync signal. This is not compliant to the standard, but a reality.