VHDL code compiling on quartus II
I wouldn't say it is a bug, it is more of a limitation, and in a way it makes total sense.  You want it to infer a dual port ram, the compiler wants to infer a dual port ram, however the process in the problem snippet does not properly describe the address input of the read port of the ram, because not all paths are covered, so it would have to infer a latch, while what you really want is a don't care.  So you are basically making it hard for the compiler.  

Realize that to infer the ram, it must also infer a few signals and their values, one of which is the address input.  In the synchronous process, the value for this inferred signal is not defined for the case that ends up in PIXOUT &lt;= x"111".  So it would have to infer a latch and the warning would be an awkward "inferring latch on inferred address signal of inferred ram".  It ends up being a bit too much, so it probably gives up, but then alternative solution does not fit the device.  I'm not saying that this is the exact reason why it is giving up, but it should be clear that the compiler would have difficulties filling in the blanks for the inferred ram, given the way this process was coded.

All the solutions that work cover all the cases for the address signal, inferred or not.  You could test  declaring the signal and then coding it the same way so that it has to infer a latch, and it may even compile because now at least would have an explicitly declared signal it can refer to.

The coding styles for inferring ram blocks for Altera can be found in http://www.altera.com/literature/hb/qts/qts_qii51007.pdf#page13

This is one of the reasons why it is strongly suggested that if you wish to use existing hardware blocks, either instantiate them as such to avoid ambiguities, or follow the appropriate coding styles so that it can be easily and adequately inferred.

Also note that a simulator would not have to deal with this, because it would not have to infer a ram block per se and deal with the ambiguous don't care vs latch of this phantom signal, because in simulation it does not exist.