Is there a compact way to connect these two ports?
Disclaimer: I normally use Verilog so please follow the principle of what I write, not the exact syntax.

An important part of programming is to analyse your data before you do anything.

In this case you should observe that 3 LS bits select which A(..) you take so the first improvement is to use 

A( sel(2 downto 0) )


Next I have small problem because that leaves 4 select bits which is 16 combinations but you have only 8 B(...). So for now I'll ignore the MS sel bit.

The second optimisation is that you can now use select bits 5..3 to determine which B you want. But before that you give it a default value:

PB &lt;= (others '1' );
PB( sel(5 downto 3) ) &lt;=  A( sel(2 downto 0) );


But that means you do two assignment to the same variable and that only is allowed if you do it in the same process.

Last but not least is to convert the above code so that the types are all correct. 
I always struggle with that in VHDL so that would require about an hour of my time. I leave that to you.