5 cycle instruction forwarding - MIPS
If I understand your question correctly:

You shouldn't have to forward from writeback to decode, WB happens in the first half of the cycle and ID in the second.



This is the best image I could find on short notice, give me a minute and I will try and find the relevant image from a textbook. Alright, here are some relevant figures from Patterson &amp; Hennessy (a pretty darn good text on computer organization, focusing on the MIPS architecture. I would recommend you get a copy):





In writeback, the register file is written to in the first half of the cycle; in instruction decode, the register file is read from in the second half of the cycle. As I understand it, this text's description of MIPS is fairly accurate. In hardware, this might be implemented with two clocks: the EX/MEM/WB stages would be driven by clock A, and IF/ID would be driven by clock B, 180º degrees out of phase (inverted). Careful design of the logic ensures that IF/ID/WB are "complete" in less than half a clock cycle.

In a simulator, you simply have to update the register file from writeback before decode is executed.

Figures from Patterson &amp; Hennessy, Computer Organization and Design, Chapter 4.