How to hold a data during N clock cycles using DFFs?
The way this is done is by using a D flip-flip with an enable signal. If the enable signal is brought high, the flip flop keeps it's value if the enable signal is low then it holds its value.


Source: https://www.eeweb.com/quizzes/verilog-flip-flop-with-enable-and-asynchronous-reset
Here is some pseudocode :

if enable== 1 then
output &lt;=input;
else
output&lt;=output;
end;*emphasized text*