Why is there a wait at the end of a VHDL test case?
A process can have two basic forms:

The first uses a sensitivity list, for example process (clk) would be the first line of a synchronous process which should respond to clk. The process will only run when there is an event on the clk signal, so this forms a control for the execution of the process.

The second has no sensitivity list, as per your example, and so there is nothing to 'trigger' the process into action. Instead, the process forms an implicit loop, whereby it will jump back round to the top once it reaches the end.

Without the wait; statement, your example process has nothing that takes time; the delayed assignment will be scheduled, but execution will immediately proceed to the next line. The process would therefore form an infinite loop, running over and over again, without allowing time to advance. With the wait; statement, your assignments will happen, and the process will then wait forever on the wait; line.

If your process did have statements that took some time, you would not have to have a wait; at the end. for example:

process
begin
  a &lt;= '1';
  wait for 5 ns;
  a &lt;= '0';
  b &lt;= "0101";
  wait for 15 ns;
  b &lt;= "0000";
  wait for 100 ns;
end process;


This process will keep repeating over and over, but since it has wait statements within it, the implicit loop does allow time to move forward in each iteration. The sequence of assignments will repeat again and again, until something else stops the simulation. Crucially, the above process allows time to advance within each sequence.