Motors and H-bridge - High current on PCB
There are a number of considerations and depending on what is applicable is whether you plan to PWM this bridge or not.

No PWM, pure directional control BrushedDC

Assuming this topology was simply to drive a brushed machine and occasionally change direction... The main concern is how to deal with 70Amps

irf3205-n is rated for 110A for a case temp of 25C. It will not stay at 25C for long  ( 100C has a current recommendation of 80A)

irf4905-p is rated at 74A  at a case temperature of 25C &amp; 52A at 100C 

Issues #1  the devices would appear to be underrated for their current capability &amp; this is before any form of de-rating (say 80% on the current)

With an \$R_{dson}\$ of 8m\$\Omega\$ this put the Ntype loss at 39Watts. This could be ok (within the devices rating) but this is dependent on how you plan to heatsink this. 

\$R_{\Theta JC}\$ = 0.75

\$R_{\Theta CS}\$ = 0.5

\$R_{\Theta CA}\$ = 62

\$R_{\Theta SA}\$ = TBD

ASSUMING no derating and pushing the device to the point of destruction. you will require a heatsink with a thermal resistance of: 2.65 C/W.

You would not want to run the FET's at 175C junction (peak say... 150C) and thus the heatsink will need to be better than that. 

You are going to have suitably sized copper traces to carry 70A via all connections on the H-Bridge. Again this is assuming NO SWITCHING. 

Do you size for 70Amps continuous or based upon load-duty information, size for the rms? This will come downto specifics of the duty, thermal capacitance to slew the temprise &amp; point of fusing ( Onderdonk's equation). Assuming it is for 70Amps continuous: 

The IPC-2152 provides some guidance on how to choose the copper trace width with regards to copper weight and current:

If we assume a two sided powerCore card and the current can be shared TOP and BOTTOM. allowing for a 10C  temprise and an ambient of 25C, the tracewidths will need to be:

35mm for 3oz copper

53mm for 2oz copper

105mm for 1oz copper.

Could a multi-layer PCB be used and thus less than 35A per layer be achieved (and thus thinner traces)? Yes but the inner traces will be heated by the encasing traces &amp; equally cannot radiate into free air. There is an associated de-rating when using internal traces. 

They would need to be run parallel to each other to minimise the associated loops. Equally to facilitate in current sharing they would need to be "stitched together" via a number of filled via's 

The 70A connection's on and off the PCB will need some special care and attention. The barrel of any via's used will be the thinnest point &amp; thus will experience the highest current density. See previous statement about a number of via's; this is true about any through-hole connection you shall be making.



PWM involved: BLDC machine or Speed controlled brushedDC

If however you intend to PWM the FET's there are a number of immediate concerns


No local DClink capacitor to decouple the inverter from your supply. Assuming you are feeding this from a battery, any small harness will exhibit a reasonable amount of inductance and thus this H-Bridge will be presented with a "current source" and not a "voltage source" &amp; during switching events there will be additional ringing, possibly to the point of avalanche.
the Gatedrive topology you have chosen has ... issues. The Ptypes are being turned off via 10k. If you are not introducing a dedicated dead time period and instead relying on a difference between switching speeds to mitigate a shoot-through at the point of switching you would want


Fast-OFF &amp; Slow-ON.  

You N-Types are following this but not the P-types. 


Again with the "gate drive". There is no gate resistor and thus you are running the risk of creating a Pierce oscillator. As a bear minimum consider 10R. Correct value choice will depend on your desired switching speed, specifics millar characteristics, power available etc... 
Under PWM operation any strays will be a problem. Just like for the Battery &amp; the DClink capacitor, there are key places where the copper interconnects should be as short as possible. This does not mean "I can only get then 5cm apart so that is as short as possible" I mean 5mm (to put a number to it). If you cannot achieve that, redesign your powercore layout otherwise you will run into:


overheating due to additional switching losses, 
Ringing due to all the inductance
Avalaunch due to overvoltage transients



Key area's are:  


DRAIN's of the FET's as short as possible to either DC+ or DC- (the nearest device)
Diode-Anode to Ntype-SOURCE, Ptype-DRAIN
Diode-Cathode to Ntype-DRAIN, Ptype-SOURCE 
Ntype-DRAIN to Ptype-DRAIN
DC+ to Battery
DC- to Battery


Minimise any loops where current is flow. A key point is the DC+ and DC- from the inverter to the capacitor. laminated busbar.