How much is VLIW power- and area-efficient then superscalar anyway?
I don't have any reliable sources, but I do have experience of designing a very simple processor that took the approach of leaving avoiding pipeline hazards to the programmer, because that did provide a significant simplification for what was intended to be an as-simple-as-possible pipelined processor design.  

That said, I don't believe that the savings scale: I may have saved a handful of flip flops and several gates that would have been necessary to avoid those hazards, and with only ~60 flip flops (excluding the register file) and ~100 gates in the entire design that was a significant percentage, but for a more complex processor the difference would, I think, have been trivial.

Instruction scheduling for an order-of-order processor is a little different, but even then the costs are small relative to the complexity of the processor, particularly as by the time you start looking at these kinds of optimisations you're likely to have added some comparatively big chunks of silicon for parallel multiply/divide operations, not to mention cacheing, which is likely to be more beneficial in most designs.

There's a reason almost nobody's designing VLIW or EPIC machines commercially any more -- it's an architecture that was only beneficial for a brief period of time[1] back in the 90s, and processor design has moved beyond the point where it makes any significant improvement.

[1] - at least for high performance general purpose systems.  For embedded processors and specialist systems like DSPs and GPUs it may still have some benefit (because they usually have designs that are towards the simpler end, only repeated many times in order to achieve parallelism, the tradeoffs for them are much closer to the tradeoffs for 90s era general purpose CPUs), but even there I'm not sure.