SAR Circuit in Analog to Digital Converter
It is essentially a sort of parallel-set / serial-in / parallel-out shift register with a twist.

It starts with 1000 (assuming four bits). When the comparator deems this value too low, a 1 is shifted in at the high side, when it is deemed too high, a 0 is shifted in. In both cases 1 bit of the result (the MSB) has been determined.

Now the value is x100, and the cycle is repeated three more times to determine the next 3 bits, but those bits are shifted in at positions 2, 1 and 0 instead of at the highest bit.