High EMI PCB track under transistor or diode package
There are two transients to consider:


High dV/dt: these occur on the switching node (emitter of high-side IGBT and collector of low-side IGBT), each time you switch either IGBT. A high dV/dt can couple to neighboring traces capacitively. If the neighboring trace terminates to a high impedance node (eg. the input to a comparator for current sensing), the capacitive current spike would cause a voltage spike. For a comparator, that could mean a spurious trigger. 


A solution is to minimize the overlap area of high dV/dt nodes with sensitive nodes.  

In your PCB layout (top image), the upper and lower blue traces are the nodes that see high dV/dt. Since these overlap with nothing, I don't see any issue. It doesn't matter whether they are on the top or bottom planes. 


High dI/dt: this happens when the current switches from the high side to low side or vice versa. High dI/dt can result in a couple of issues:
a. Result in a voltage drop across parasitic inductance that is in the path of the current
b. Induce a voltage in neighboring traces.  


A solution to (b) is to minimize the area of all high current loops, and hence minimize the side-by-side trace lengths of high dI/dt nodes and sensitive ones. 

Given your configuration where the TO-247AC package (plastic/mold compound) contacts the solder mask, the closest electrically conductive nodes to your PCB traces are the bondwires inside the package that loop over from the leadframe to the die. These wires are tiny, and depending on the metal type no more than 10's of mils in diameter,  coming close to the surface of the package [1]. So the overlap area is negligible. 

[1] Nice photo of the pre-molded TO-247: http://www.power-eetimes.com/imf/c/eyJtYXNrIjoiNDMyeDI4OCJ9/images/01-edit-photo-uploads/2014/2014-06-june/onsar2662_fig-1.jpg