ModelSim wave window showing zero time transitions
Move to SystemVerilog. Declare all your clocks with the 2-state type 1 bit. That eliminates the time 0 X-to-0 transition.

module dff(input logic d, bit clk, logic reset,
           output logic q);
`define DFF_DLY 5

always @(negedge clk or posedge reset)
   if (reset)
      q&lt;=#`DFF_DLY 0;
   else
      q&lt;=#`DFF_DLY d;

endmodule 




If you cannot use SystemVerilog, then set the reset signal to 1 before making any changes to the clock. Keep reset active until after the clock as a full period.

module dff_tb;

reg d,reset=1,clk;
wire q;

initial begin
    d=1'b1;
    #1 clk=0;
    #20 reset = 1;
  end
...
endmodule