Instanciating blocks in VHDL, asignment of clock and reset signals
First of all you need to differentiate entities definitions and entities instantiations. 
What you try to do here is defining an entity and instantiate it in the same file. Your architecture of your entity can't use your entity ...

So I advise you to create a TOP level, that you can call top, stack_top or whatever you want and an entity stack separately.

Your main entity called stack will look like this :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity stack is
     port(
        D : in std_logic;
        TS : out std_logic;
        clk, rst : in std_logic;
        SOp : in std_logic_vector(1 downto 0)
    );
end entity;

architecture structural of stack is


begin

... -- do whatever you need to do

end architecture;


This is you stack function. Now the top level will instantiate as many instances of you stack entity you need.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is
     port(
        D : in std_logic_vector(4 downto 0);
        TS : out std_logic_vector(4 downto 0);
        clk, rst : in std_logic;
        SOp : in std_logic_vector(1 downto 0)
    );
end entity;

architecture X of top is

-- call you entity
component stack is
     port(
        D : in std_logic;
        TS : out std_logic;
        clk, rst : in std_logic;
        SOp : in std_logic_vector(1 downto 0)
    );
end component;

begin

-- instantiate your entity
stack0 : stack 
port map  (D =&gt; D(0),
           TS =&gt; TS(0),
           clk =&gt; clk,
           rst =&gt; rst,
           SOp =&gt; SOp);

stack1 : stack 
port map  (D =&gt; D(1),
           TS =&gt; TS(1),
           clk =&gt; clk,
           rst =&gt; rst,
           SOp =&gt; SOp);

...

end architecture;


(I assumed that you wanted to map one bit of each of your vector to each stack, that's why I'm using std_logic ports for each stack)