Can you use an FPGA / verilog to accelerate SAT / SMT solving?
Yes, you can certainly use FPGAs to do this kind of work, there’s lots of literature pointing to it. Examples - [1] [2] [3] [4]

SMT = Satisfiable Modulo Theory

SAT is Boolean Satisfiable Problem, nicknamed a ‘SAT’ for short.

More about this stuff here: https://people.eecs.berkeley.edu/~sseshia/pubdir/SMT-BookChapter.pdf

My suggestion is to address the bitstream loading time. Some FPGAs support what Xilinx calls ‘tandem’ configuration, where a large FPGA first has a smaller bitstream loaded locally that’s enough to light up PCI Express, then the rest of the bitstream is loaded at high speed over the PCIe link.

More here: https://www.xilinx.com/Attachment/Xilinx_Answer_51950.pdf