What is the penalty for using vias?
At this frequency, as several people said in comments, 5 vias is not a problem. 

The problem could be:


mismatching impedance between output of clock and inputs connected to the clock line. For this you can use series resistor of about 50-100 Ohms as close to the source of clock as possible;
too high fan-out. You must ensure that under no circumstance clock signal is being overloaded, causing its shape to deteriorate, and thus causing clocking malfunction or false positives. Buffer clock signal within the circuit;
type of output for the clock. I would choose to have HC or HCU chip generating the clock to ensure the signal is almost rail-to-rail (in contrast with TTL logic which could be 0.4 V to 3 V).


It seems your question is caused by higher-order issue, and you say


  My concern is that I receive unstable boards and have to redo it all over again.


and the clock signal, while most vital for the circuit, may not be the cause of instability. Small timing violation of the read, write, memory or I/O request lines relative to each other or relative to clock may cause malfunction. Example: I was dealing with malfunctioning i8255, and it turned out that /CS should be removed after /RD or /WR are deactivated. Deactivating /CS with read/write signal causes chip not to latch data properly.