pausing d flip flop output
To do this with minimal changes to your design, consider using a tri-state buffers at the output of each counter.

This is a buffer with an ENable pin. When the enable pin is asserted, the buffer produces an output like normal. When the enable pin is de-asserted, the buffer puts its outputs in high-impedance (or high-Z) state. This not only means there's no output, it also means the output won't interfere with other gates trying to produce outputs onto the same wires.

For example, consider 74LS244. This has two sets of 4 tri-state buffers, with each set of 4 controlled by a common enable pin. Note the enable pin is active-low, so "asserted" means a low voltage and "de-asserted" means a high voltage. You'd need two of these to complete your design.