What is the synthesizable VHDL method for loop or memory module?
I assume your video data is going to be streamed in, pixel by pixel.
This means that each pixel comes in one value after the other, and is processed one by one in a row. This is usually the way video data is transmitted and received.

No matter if you store your data in memory or not, you will need to use a loop in order to iterate through the data (as it comes in, writing into and reading out of the memory). 

Usually memory is used for the following reasons:  


Your write clock and read clock rates are different.
You need a number of clock cycles to perform your processing operation and a buffer gives you this time.


The requirement of memory is very much situation dependant, so I can't tell you if you should use it without know a bit more detail about your exact requirements.

However, the loop. 
In VHDL, you don't need to use a for loop statement in order to loop through data sample by sample. By including a clock in the process sensitivity list (the bracketed part after the word "process"), the process will run every single clock cycle. So for example, if you wanted to threshold a stream of data (very basic, out of my head example):

threshold_data : process(clk,reset) -- sensitivity list, with clock
begin
    if (reset = '1') then           -- here I say what my signals should be during reset
        threshold_data_out &lt;= '0';
    elsif (rising_edge(clk)) then   -- detect a new clock cycle
        -- This is where the thresholding happens:
        -- threshold_data_in is the current sample 
        if (threshold_data_in &gt; threshold) then -- if above threshold
            threshold_data_out &lt;= '1';        -- make this whatever number you want.
        else 
            threshold_data_out &lt;= '0';
        end if;
    end if;
end process;


But where is the loop?
This is the trick, the process statement is being triggered every time the clock changes (because it's in the sensitivity list), so essentially the process is looping once each clock cycle. We are using the inherent property of the process sensitivity list to create a looping behaviour, without actually explicitly calling a loop.

What if I want to access memory?
Then you can add this to your loop

    -- in your reset section:
    memory_address &lt;= (others =&gt; '0');

    -- in your process proper
    memory_address &lt;= memory_address + "1"  -- make sure memory address is an unsigned! 


now every clock cycle you are accessing the next block of memory. 
For a square of pixels stored in memory, you need a scheme of mapping each pixel's vertical and horizontal coordinates to the memory blocks. 

Also, remember to take into account any latency through memory, you might write in the address now, but the valid data for that location might only be available 1 or 2 clock cycles later. It's usually 1, sometimes more depending on how you've set up your memory.