Access elements randomly in RAM based FIFO VHDL FPGA
Yes it is possible to use an SRAM as a FIFO. Have a write pointer and a read pointer. That way you won't have to shift all the SRAM data when you push or pop a new data.

signal read_pointer : unsigned(log2(WIDTH) -1 downto 0);
signal write_pointer : unsigned(log2(WIDTH) -1 downto 0);
signal full : std_logic;


Incrementer the write pointer when you write. Increment the read pointer when you read.

when read_pointer = write_pointer and full = '0', then fifo is empty. When write_pointer = read_pointer and full = '1', the fifo is full (obviously). Otherwise the size = write_pointer - read_pointer.

You could adapt this model

http://www.eng.auburn.edu/~strouce/class/elec4200/vhdlmods.pdf

Edit :

It is not a good idea to internally shift the data inside of the RAM. You don't need to do it... Like I said, a read pointer and write pointer is all you need.

Beginning:

Read ptr = Write ptr = 0. Full = 0. No data in the RAM

Operation 1,

Write 0x1234 ---> Write ptr = 1, read Ptr = 0, Full = 0; 0x1234 at address 0x00

Operation 2,

Write 0xCAFE ---> Write ptr = 2, read Ptr = 0, Full = 0. Ox1234 at address 0x00, 0xCAFE at address 0x01

Operation 3,

Read operation. Output = 0x1234 since read ptr = 0. After read is completed, read ptr = 1. Write ptr = 2. 0xCAFE at address 0x00

Operation 4,

Read operation. Output = 0xCAFE since read ptr = 1. After read is completed, read ptr = 2, Write ptr = 2. The Fifo is empty.