VHDL:CLOCK DIVIDER with duty cycle
The simplest thing is to have count counting the full period of the output clock, and then you can assert temp for any fraction of that period, like this:

entity clkgen is
    Port (
        clk_in  :  in  STD_LOGIC;
        reset   :  in  STD_LOGIC;
        clk_out :  out STD_LOGIC   
    );
end clkgen;

architecture Behavioral of clkgen is
    signal temp: STD_LOGIC;
    signal count : integer range 0 to 3 := 0;

begin
    Clock_out : process (reset, clk_in) begin
        if (reset = '1') then
            count &lt;= 0;
        elsif rising_edge(clk_in) then
            temp &lt;= '1' when (count &lt; 1) else '0';
            count &lt;= count + 1;
        end if;
    end process;

    clk_out &lt;= temp;     

end Behavioral;