Is designing SDR SDRAM controller a difficult task?
A very crude description of SDR SDRAM is here. In fact there is very little difference between the earlier Single-Data-Rate and modern Double-Data-Rate memory in terms of control.

SDRAM is a pain simply because you have to write a controller which has to handle access of the memory in terms of sequencing read and write commands, refreshing the memory, control of the various row/column addressing and pre-charge commands, adding the correct latencies into the control lines, and so on.

This is in contrast to SRAM where in many cases all you do is simply set the address lines and toggle a line to read/write the data.

Give the lower data rates of SDR (100MHz vs. modern DDR3/4 which are 800MHz+), implementing and testing an SDRAM controller is made somewhat simpler in that the physical layer of things is simplified - you can probably get away without the various DLLs and link training that is needed for the ultra-fast speeds of DDR3/4.

However it is still likely to be a tedious task, and one which, given the abundance of perfectly serviceable and in some cases free SDRAM controller IP cores, there is very little to gain by doing it yourself.