Is there a proper way in VHDL/Verilog to access block RAM given a multi-hot vector?
A circuit that can identify a particular set bit in a vector in a fixed amount of time is called a &quot;priority encoder&quot;. The general concept is that you use the priority encoder to find the first set bit in your vector, use its number to address your memory, and then you clear that bit in the vector so that the priority encoder can find the next set bit in the next cycle.
An 8176-input priority encoder would be a large circuit,1 but since you're expecting to find 32 set bits in your vector anyway, you could break the problem up so that you scan only part of the vector at a time. For example, you could build a 64-input priority encoder2 and scan your vector in blocks of 64 bits at a time, using 128 clock cycles. If you ever find more than one bit set in a given block, you'll need extra clock cycles to process them, but even in the worst case, you'll need no more than 159 clocks to complete the job.

1 Roughly 13,640 4-input LUTs.
2 If your FPGA has 4-input LUTs, such an encoder would require just 99 of them.