What's the best way to debounce a slider switch?
You really have two issues to deal with here. First, you need to deal with metastability. To do that, you'd typically connect up an inverter to one of the inputs of your SR flip flop (creating a D flip flop), so you can drive both the inputs to your SR from your single switch:



simulate this circuit &ndash; Schematic created using CircuitLab
Then you normally want to run that signal through another flip flop to synchronize it with the clock on the rest of your system.



simulate this circuit
Just to be clear, both of those will be clocked with your system clock.
After that, you do your debouncing. Typically, you do this with a counter that starts running when you see (say) a high signal, and resets when you see a low signal. Then you produce an output when (and only when) the counter reaches some upper limit (long enough to cover bouncing).
I've never actually tried to implement it, but I think you could probably sort of reverse the order of those things if you wanted. Instead of sampling and then counting down to cover switch bounces, you could probably do a count on your clock to produce a clock for the flip flops with a very low duty cycle. For example, if you're using a 10 MHz clock for the rest of the system, feed the flip flops with a clock that has one high pulse every 50 ms, so it samples the signal from the switch for .1 uS every 50 ms.
It seems like this could have at least some advantage with an FPGA, by allowing you to do more of the work with dedicated clock management resources, and reserve the fabric for your other logic.
But as I said, I've never actually tried that, so I wouldn't call this a recommendation, just a thought you might find interesting.