How can I execute multiple for loops sequentially in Verilog?
A few things to keep in mind about writing HDL:


HDLs are not programming languages.  Your code ultimately describes a schematic, it is not executed or interpreted.  Whatever code you write has to correspond to some physical element on the target device.  Things like nested if statements become AND gates operating on signals that represent the conditions, mathematical and logical operations become the corresponding hardware (adders, subtractors, logic gates, etc.), array operations can become RAMs and ROMs, etc.
Delays are in general not synthesizable.  You have to find some other method to create the functionality you are after.  Delays can be useful in simulation for various purposes, but they are ignored by the tools when creating the actual FPGA configuration.  Some parts have special primitives for performing delays on individual IO pins, but these are very specialized components with delays on the order of nanoseconds, only usable for signals passing through specific IO pins, and must be manually instantiated and configured as necessary (see Xilinx IODELAY).  
Loops are shorthand for replicated statements.  Loops in HDLs are very limited as the synthesis engine unrolls them.  Therefore, you cannot use things like while loops, break and continue, loop limits based on signals, etc.  Everything must be constant at synthesis time (module parameters are OK as they are constant during synthesis).  


For your application, it would make sense to build some sort of a state machine that can turn the LEDs on and off in a specific sequence, then add some rather large cycle count delays so that the changes are visible.