vhdl "wait until" in a loop
You loop doesn't work because loops are executed in one clock-cycle and therefore multiple WAIT-Statements exist at the same time.

This is how you could do it:

process
    variable i : natural := 0;
    constant N : natural := 42;
begin
    wait until tx_busy = '0';  -- step 1

    if i &lt; N then              -- step 2
        i := i + 1;            --   |
    else                       --   |
        i := 0;                --   |
    end if;                    --   |

    tx_data &lt;= data(i);        -- step 3
end process;


The code has three steps:


wait until tx_busy is '0'
increase i as long as it's smaller than N, otherwise reset it to 0
write out data(i) to the target signal