How to know if a verilog code is sequential or combinational?
This will synthesize to sequential logic. If b is 1, then output  will become 01. Consider the case when both the inputs a and b are 0. No condition of your code is satisfied, which means that the output will be unchanged. This implies that we are storing previous value, for which a latch is required. This occurs due to incomplete if else statements, that is, all the cases are not covered.