Help me understand this shift register timing diagram
There is quite a lot going on in this diagram.


The up arrows on the clock are telling you that things are sampled on the positive edge of the clock
DS is the data going in, you can see that it is sampled on the positive edge of SH_CP. (sample and hold clock, positive edge)
It the comes out of Q0 on the first positive edge of ST_CP (shift register clock, positive again)
The pulse then appears at Q1 on the next clock and so on


So the diagram is showing that it is shifting the serial input from one output to the next to the next.  

It also shows that bringing MR low resets the internal memory, but outputs Q0-Q7 remain at their state until the next state.   The last output, Q7*, seems to change on the negative edge and be reset immediately.

Last of all, if OE(bar) goes high the the outputs all transition to high impedance.

Does that help?