Testbench using Task operation
Two problems.
The first is you are driving all_out from an output of your module and making a procedural assignment for the task call. That is illegal. What you want to do is create a separate variable and then compare the result from your module and testbench.
The second problem is you are not giving any time for the results to propagate and be observed. You need at least a unit delay.
So modify your testbench like:
  logic [7:0] alu_out_actual, alu_out_expected;

 alu uut(
    .a(a), .b(b), .alu_out(alu_out_actual), .alu_select(alu_select)
  );
...
initial begin
   ... 
   addition(a,b,alu_out_expected);
   #1ns;
   if (alu_out_actual != alu_out_expected) $error(&quot;mismatch&quot;);

A few other comments:

in SystemVerilog, even though they are synonymous, prefer using logic over reg keywords. Avoids confusion with register.
It's poor programing practice to declare things outside of a module. It creates problems as your code gets larger. Move your task declaration inside your module, or declare it inside a package to be imported.
You should not be using a task for a routine that does not consume time. Use a function with a void return type, or make c the return value.