Cannot extract expected values in VHDL at first clock cycle
and create a new value at every clock but this is not happening


The reason this isn't happening, is because your code has a clock cycle where no output is assigned:

if(clk'event and clk='1') then
    if(i &lt; 4) then
        y &lt;= x_3(i)&amp;x_2(i)&amp;x_1(i)&amp;x_0(i);
        i &lt;= i + 1;
    else 
        i &lt;= 0; -- here you have no assignment to y
    end if;     
end if;


Also, your code would be simpler if you declared  i as a  variable instead of a signal, which is probably what you mean to do anyway. See this for some discussions on the differences.

This code is probably what you're looking for (as a simulation):

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity gen_input is
end gen_input;

architecture Behavioral of gen_input is

    signal y   : std_logic_vector(3 downto 0);
    signal clk : std_logic := '0';

    constant x_0 : std_logic_vector(3 downto 0) := b"1100";
    constant x_1 : std_logic_vector(3 downto 0) := b"0100";
    constant x_2 : std_logic_vector(3 downto 0) := b"0010";
    constant x_3 : std_logic_vector(3 downto 0) := b"1011";

begin

    clkgen: process
    begin
        wait for 10 ns;
        clk &lt;= not clk;
    end process clkgen;

    inst_process : process (clk)
        variable i : natural range 0 to 3 := 0;
    begin
        if rising_edge(clk) then
            y &lt;= x_3(i) &amp; x_2(i) &amp; x_1(i) &amp; x_0(i);
            i := i + 1;
            if i = 4 then
                i := 0;
            end if;
        end if;
    end process inst_process;
end Behavioral;


Note that, since i is declared as a variable within the process, you can increment i and then immediately check it to see if it should be reset to 0. You could also do this:

if i = 3 then
    i := 0;
else
    i := i + 1;
end if;


but it's more typing and not necessary. Either way, you will end up with the exact same RTL.

Here's the sim: