Maximum input frequency of 74HC Logic gates
No, it's not in the datasheet, it's in the HCMOS user guide, as it concerns all HCMOS components.  

On page 4:


  D-Flip-Flop: 30 MHz minimum, 55 MHz typical
  Counter: 25 MHz minimum, 45 MHz typical


For gates this will probably be in the same ballpark, since for those only rise and fall times are relevant, and not propagation delay.  

If you want something faster, then NXP's Advanced Ultra-low Power series (AUP) quotes frequencies up to 619 MHz.