R_on for inverter gate
Suppose we're talking about the falling transition time of an inverter. We assume that the PMOS transistor is completely cut off and that \$V_{GS}\$ for the NMOS is equal to the supply voltage. Now, for most of the range of voltages that the output will swing, from \$V_{DD}\$ to ground, \$V_{DS}\$ will be large enough that the NMOS will be in saturation. The real definition of "most" depends on the switching points that you use to define the "transition time"...20% to 80% of \$V_{DD}\$ is typical. So, the transition time for the output is mostly dependent on the \$I_{DS(sat)}\$, and it's only as the output voltage gets close to its final value that the triode region \$R_{DS}\$ becomes significant.

Of course, this is all just a rough approximation. The input transition time can not be ignored in practice. Your best answers will come from a good SPICE simulation.