Problem with 2G Modem's supply power
The ESR of input and output Caps is important since a step load can have a rise time shorter than the bandwidth, BW of any high speed linear loop.  0.35/BW = 10~90% rise time.

Consider a 0.1A/us as slow and 1A/us and >1A/us as faster than what the loop can regulate without help from a low ESR cap.  This controls the step load voltage drop Istep*ESR. Thus for 2A and say 200 mV error you need an effective series resistance, ESR of 100 mΩ max at all times.

Decoupling the load from the LDO also has an impact since the value of a step load drop in voltage becomes ΔV=L dI/dt  Thus you can estimate your dI/dt from the effective ΔV and L you chose.

These ESR impedance ratios and their slew rates impact the Step response directly.

In 8.2.2.4 "The TPS7A7300 is evaluated using an X5R-type, 10-μF ceramic capacitor. TI
highly recommends the X5R and X7R type capacitors because they have minimal variation in value and ESR over temperature. Maximum ESR must be less than 1 Ω."

Your problem appears to be excessive ESR in caps.