dsPIC33 ADC: Why is the minimum TAD interval such an oddly-specific number (117.6ns) for 12-bit conversion?
There are some clues in the datasheet.

For instance:


  The AD12B bit (AD1CON1&lt;10>) allows each of the ADC modules to be
  configured by the user as either a 10-bit, 4-sample/hold ADC (default
  configuration) or a 12-bit, 1-sample/hold ADC.


Then this:


  • In the 12-bit configuration, conversion speeds of up to 500 ksps are
  supported 
  
  • There is only one sample/hold amplifier in the 12-bit
  configuration, so simultaneous sampling of multiple channels is not
  supported


I agree the unusually precise value is odd, but if you convert that to a sample rate it yields about 607K samples per second (a bit above the maximum stated rate) (14 ADC periods are required for a 12 bit conversion).

In the ADC reference manual there is a schematic of the effective ADC input in the two modes;



Note the difference in the input capacitance; this is necessary as the sample capacitor has to hold the charge for a longer period of time for the conversion to be accurate and will therefore require a longer time to actually charge up during the sample period.

Looking at the values, it appears that the effective capacitance for 12 bit mode is formed of all 4 sample and hold capacitors (4 * 4.4 = 17.6, 18 when rounded) and that makes sense of the statement that there is only one sample and hold in 12 bit mode. Probably achieved by switches isolating the other channel sample and holds from their caps and switching them in to form a single effective device.

Hence a longer ADC period (longer charge time and a longer hold time). 

The value in the datasheet may be from calculations or experimentation (I do not know which).