PMOS and NMOS Current loads in Common Source Stage
In general analog CMOS IC design (general normal speed opamps, comparators, circuit where noise is not a problem, so on) it does not really matter, if only you do not have such design that needs to be extremely noise aware, RF or of other reasons. In reality, for example during opamp design (where such CS stages are used), you get other requirements that you need to satisfy as input voltage range. That determines you the NMOS or PMOS input differential pair what then determines you the PMOS or NMOS Common Source Stage which is 2nd stage in opamp class A architecture:



Source: https://payhip.com/b/5Srt ("Preview" button in top right corner)

Second stage (marked green) of above opamp architecture is Common Source Stage with NMOS current source load. NMOS current source load of 2nd stage was determined by using opamp classical class A architecture with NMOS input differential pair M1-M2.
If PMOS differential pair is used in the above architecture, the 2nd stage is constructed by Common Source Stage with PMOS current source load.