Designing FSM using Verilog
You really need to include an actual link to the website in question — I finally found it here.
Did you read any of the warning messages that the site spits out about your code? They make the problem rather obvious. For example:

Warning (10199): Verilog HDL Case Statement warning at top_module.v(15): case item expression never matches the case expression File: /var/www/verilog/work/vlgNC2KRa_dir/top_module.v Line: 15
This case can never occur. One common bug is that you declared the wrong size for a signal (Also look for warnings about truncating values). For example, case(a[0]) 2'b11: something; endcase never matches because a one-bit signal can never be 2'b11.

Fixing that one problem allows your code to pass all tests.