ATmega crystal setup and and power routing
VCC/AVCC - one power run, and connect them under the chip. 0.1uF (100nF) next to VCC, AVCC, Aref. Do not connect Aref to VCC.

Crystal/caps.  Layout 1 with crystal next to chip and the caps on the outside of the crystal.  Don't separate the Gnd plane. Don't run any signals under the crystal/caps and their traces except Gnd.  Static signals (like Reset, which rarely changes) are okay also. Best practice is no signals tho.