Interval measurement in Verilog
There are a few "obvious" problems here, try these first.


You are using blocking assignments (=) in sequential logic, where you should be using non-blocking (&lt;=) assignment. Have a look at this question here.
You have no reset mechanism as you've pointed out. This means that variables are undefined (at times), so your if-else structure may not work the way you think it will. For example on the very first edge, what will the result of counter == 0 be?
You do not resynchronise your pulses. You should convert your input "pulse", which may actually look like a level as it's asynchronous, into a pulse in the local clock domain. For example, if your driving domain is clocked at 10 MHz, but your receiving domain is clocked at 100 MHz, a single cycle pulse in one domain is a 10-cycle long pulse in the other.
Your sampling frequency is too low. A 150 ns pulse is 6.66 MHz, which means you need a clock of at least (6.66 * 2) MHz to reliably capture your inputs. EDIT: This is to reconstruct, rather than capture, so you should be ok.
As mentioned in the comments, there's a problem if the overflow happens, then the next cycle the pulse comes in. You should ideally store your outputs in a FIFO that is drained by the system when it can.
This sort of system is perfect for a state machine. This way, you can drive your outputs based on the state of the system - it's a form that's less liable to error**. For example, see below. Note, the sample_sync_i input comes from another module, will leave you to implement that :)

typedef enum bits [1:0] {
    IDLE  = 2'b00,
    COUNT = 2'b01,
    OVF   = 2'b10,
    LATCH = 2'b11,
} fsm_t;

module counter (
    input  logic       clk          ,
    input  logic       reset_n      ,
    input  logic       sample_sync_i,
    output logic [7:0] result_o     ,
    output logic       interrupt_o
);

fsm_t fsm, fsm_nxt;

logic [6:0] counter      ;
logic [6:0] counter_nxt  ;
logic [7:0] result_nxt   ;
logic       overflow     ;
logic       interrupt_nxt;

// Move to next FSM state based on inputs
always_comb begin
    case (fsm)
        IDLE  : fsm_nxt = sample_sync_i ? COUNT : IDLE;
        COUNT : fsm_nxt = sample_sync_i ? LATCH : (overflow ? OVF : COUNT);
        OVF   : fsm_nxt = sample_sync_i ? LATCH : COUNT;
        LATCH : fsm_nxt = COUNT;
    endcase
end 

// Update FSM flops
always_ff @(posedge clk or negedge reset_n) begin
    if (~reset_n) begin
        fsm &lt;= IDLE;
    end else begin
        fsm &lt;= fsm_nxt;
    end 
end

// outputs depend on FSM
always_comb begin
    interrupt_nxt = 1'b0;
    counter_nxt = counter;
    case (fsm_nxt)
        COUNT : begin
            counter_nxt = counter + 1'b1;
            overflow = (counter_nxt == 0);
        end 
        OVF : begin
            counter_nxt = counter + 1'b1;
            interrupt_nxt = 1'b1;
        end 
        LATCH : begin
            counter_nxt = 7'b000_0001;
            interrupt_nxt = 1'b1;
        end
    endcase
end

assign result_nxt[7]   = overflow;
assign result_nxt[6:0] = counter;

// drive FFs from FSM
always_ff @(posedge clk or negedge reset_n) begin
    if (~reset_n) begin
        result_o    &lt;= {8{1'b0}};
        interrupt_o &lt;= 1'b0;
        counter     &lt;= 7'b000_0001;
    end else begin
        result_o    &lt;= result_nxt;
        interrupt_o &lt;= interrupt_nxt;
        counter     &lt;= counter_nxt;
    end
end

endmodule : counter



** - so, I said it's less prone to error, but I haven't simulated this! If anyone spots anything, I won't be offended.