VHDL Synthesis Warnings
As BrianDrummond pointed out in the comment section, I was driving the same pins in my source file multiple times. Although this is only in simulation as it is during the test phase, and not on a FPGA board, I am relatively new to FPGAs / VHDL.
I have around 15 instances of the same component in my top level file and I copy and pasted each instance declaration in the top level file to save time.
However I forgot to change the output signal assignment so the last 3 component instances were trying to drive one signal vector at the same time.
I changed the component output signals to unique vectors and the warning messages are gone.
Thanks Brian for your help!