What are these gaps in PCB polygon pours near vias of the same net?
Go to Design -> Rules, look for a Polygon Connect Rule (NOT a Plane connect rule).

In that rule, make sure that "Direct Connect" is selected. Confirm, then leave that dialog. Repour all polygons (T->G->A). Now, check if you can still see those holes.

I have a feeling that these come from a thermal relief connect (which is setup in said rule),  overlapped by tracks.