Question on Timing Analysis
The minimum clock period is determined by the worst case propagation delay plus the setup time. In the example, this is the path from flip-flop A through 3 gates to flip-flop Y.  The total propagation delay is 80ps for the flip-flop, plus 3 times 40ps for each gate, or 200ps. Adding 50ps setup time for flip-flop Y gives a minimum clock period of 250ps.  

The minimum contamination delay is from flip-flop D through 1 gate to flip-flop Y.  The minimum contamination delay is 30ps for the flip-flop plus 25ps for the gate or 55ps, so the input to Y may change as soon as 55ps after the clock, violating the hold time requirement of 60ps.