Verilog Case Statement evaluating all combinations of a 10-bit ADC sample
I am sampling an incoming signal, which is returned as a 10-bit value, can I evaluate that sample in a case statement and assign a result value for the output register based on every one of the 1024 cases? Would this eat up LUTs in the FPGA fabric?


Yes, the syntax of Verilog allows this.


  Would this eat up LUTs in the FPGA fabric?


It depends entirely on the actual truth table you're implementing and how many bits the output value is. The synthesis tool will optimize its output as much as it can. It's possible it could be optimized down to 2 or 3 LUTs per bit of output. Or it could be 10's of LUts per bit of output.

You can check the synthesis report and see exactly how many LUTs your design consumes.


  But now that my design has gotten bigger and I've done that now for 4 different inputs, now the fpga only works when I flash the fpga, but if I power cycle it it boots up to some weird unknown state.


This shouldn't have to do with the actual design you implement but just with whether you've correctly flashed the NVM that the FPGA loads from on power cycling.

If you're using a compressed bitstream (I don't recall if Spartan 6 supports this) then it's possible that a small design fits in your NVM, but a complex design does not. You can check the report from the bitstream generator to make sure the size of the bitstream is not bigger than your NVM supports.