output won't work verilog
In decoder4_16 you declare o to be a reg type, but then you connect it to an output of a module instance. For a net that will be driven by a module instance output, you need to declare it as a wire type (for an output of the module being written, just remove the reg qualifier).

Other than that I don't see any glaring errors.

Make sure you test decoder3_8 and make sure it is working correctly before starting on decoder4_16.