Is it always good to have positive slack in STA?
... in case of a positive slack, the Actual signal always comes earlier
  than expected.


This is not true. The expected time for a signal is a window between min type (hold) and max type (setup) timing requirements.

Modern P&amp;R tools (e.g. IC Compiler) try to fix both hold and setup violations. If a data path is very fast, the tool inserts delay cells and/or buffers to meet hold timing. After it succeeds, there is nothing to worry about the positive slack for setup timing.

For synthesis, hold checks are not much accurate, because clock tree synthesis (CTS) is not performed yet (done by the P&amp;R tool). It's very common to see hold violations in post-synthesis STA. They are negligible to some degree and expected to be fixed by P&amp;R. If I catch a real hold issue in synthesis, it's mostly (to my experience) caused by level-triggered cells (e.g. latches).

The final checkpoint is post-P&amp;R STA. If there is no hold and setup violation, forget about the positive slacks. If hold violations exist, there must be something wrong with the timing constraints and/or the design. Positive slacks (of setup checks) are not the root cause of hold violations themselves.