PLL (Phase Locked Loop)
A PLL locks the phase error to zero.  This is the base concept of a PLL.

A PLL that has a divide-by-N in its feedback path locks the phase error to zero, and as a result it generates a frequency N times higher than its reference frequency -- then it is called a "frequency synthesizer".

A PLL that detects the difference in timing between its oscillator and the bits in a bitstream is called a "bit timing recovery loop"

A PLL that detects the difference in timing between its oscillator and the carrier of a digital signal is called a "carrier recovery loop".

There are all sorts of ways to use the PLL concept, and sometimes authors just call the result a "PLL" -- so you need to pay attention!