Implementation of AES algorithm using Systolic architecture
There have been papers published on AES implementation using systolic arrays, e.g. "The AES in a systolic fashion: Implementation and results of Celator processor" (2008), but it does use some memory. Another is "An 8-bit systolic AES architecture for moderate data rate applications" (2009), basically a mix column design. Whether any of those approaches meet your other (rather unclear) design requirements, I don't know.