0.1 uF in parallel with larger >1 uF to reduce noise from IC
It is recommended to decouple with multiple caps but it depends on the circuit, chips overall design.
Higher caps, even MLC have higher SR, thus their filtering ability at higher frequencies drops significantly.

from here.
As an example, typically ADC for instance, which has a high-speed logic side and a low noise analog side often requires 0.1uF and 10uF decoupling on both their analog and logic supply. Same goes for some opamp, clock sources, etc..

Back in the day when we would use an electrolytic capacitor across the
supply of a IC we would always put a 100nf Ceramic in parallel because
(if I remember correctly) electrolytics had inherent inductive
properties that would not suppress the HF noise on the power rails.
However, these days, high value ceramics exist (I regularly use 47 uF
SMD in an 0805 package).

It is true, caps got better and today's Ceramic has much lower SR than old electrolytic. But, as electronics has evolved, we now deal with much higher frequencies than in the old days, with microcontrollers often running in the 100Mhz range, clocks in the Mhz, and other buses in the Mhz range as well, without talking about CPU, RAM, etc.. Only using large ceramic caps will probably give you some issues and EMC problems.
If you look at reference schematics, IC will almost always have a 0.1uF decoupling cap, sometimes a 1uF or 10uF caps on some chips, and a few bulk caps.
Example from an opamp datasheet:

The EEVBlog has a very nice video about decoupling caps.