Is this the correct way to AND two signals?
First of all, it is not clear to me why you are using unsigned type for one bit vectors. Nevertheless, your if statement will generate a compile-time error if you write it that way. The correct way of writing the same if statement using unsigned type will be,

IF (in_adc_1 = "1" and in_adc_2 = "1") THEN


The "1" (in double quotes) here represents a vector of only one bit.

The second if statement provided by you in the comments section reads IF (in_adc_1 and in_adc_2 := 1). Again this will have to be modified in the following way, for the statement to compile correctly.

IF ((in_adc_1 and in_adc_2) = "1") THEN


Both ways of AND-ing are correct as far as the compile tools are concerned.

However, you could use the types std_logic or bit to achieve the same functionality (as pointed out in the comments). In this case the above if statement should be re-written as,

IF (in_adc_1 = '1' and in_adc_2 = '1') THEN


or as

IF ((in_adc_1 and in_adc_2) = '1') THEN


The '1' (in single quote) is a single bit when the signal is of type std_logic or bit.

Note: In VHDL, := is used for variable assignments or for providing initial values