Is it easier to implement sigma delta modulator in FPGA by filter or state space model?
By looking at digital filter on Wikipedia, I would guess that using the digital filter would be easier to implement and use less resources than the state space one, specially if you do not design the state space form into having a very sparse form. 

The complexity of a filter might be analyzed as how much memory it needs to work, or how many operations (multiplication, addition, exponentiation and so on) it has to do to get a result, or many other metrics. 

Since you can easily design a filter using the Direct Form I (this is a fact from signal processing, if the filter has order N it can be expressed in this form using some amount of memory and many multiplications and additions). A filter in that form can be made using \$2N+2\$ memory (data), parameters, multiplication and additions. Or design it using the Direct Form II, you will get the same filter using \$N+1\$ memory and \$2N+2\$ parameters, multiplications and additions. That itself seems easier to be done than the following state-space implementation.

In case you make a naïve implementation of the state space filter, you will use \$N^2+2N+1\$ parameters for (A,B+C,D), \$N+1\$ memories (for X) and \$N^2+2N+1\$ multiplications and \$N^2+2N+1\$ additions. 

A single-input single-output filter/transfer function with the following form:

$$ \frac{Y(s)}{U(s)} = \frac{ c_1 z^3 + c_2 z^2 + c_3 z + c_4}{z^4 +a_1 z^3+ a_2 z^2 + a_3 z + a_4 }+c_0,$$
 has the equivalent representation:
$$ x(k+1) = Ax(k) + Bu(k), ~~y(k) = Cx(k)+Dx(k), $$

$$ A = \begin{bmatrix} 0 &amp;&amp; 1 &amp;&amp; 0 &amp;&amp; 0\\ 0 &amp;&amp; 0 &amp;&amp; 1 &amp;&amp; 0\\ 0 &amp;&amp; 0 &amp;&amp; 0 &amp;&amp; 1\\ a_1 &amp;&amp; a_2 &amp;&amp; a_3 &amp;&amp; a_4\end{bmatrix} ,~ B = \begin{bmatrix} 0 \\ 0 \\ 0 \\ 1\end{bmatrix},$$$$ C = \begin{bmatrix} c_1 &amp;&amp; c_2 &amp;&amp; c_3 &amp;&amp; c_4 \end{bmatrix},~ D = \begin{bmatrix} c_0 \end{bmatrix}.$$

From signal and systems, you can do manipulations on all of the \$ \bar{A}\bar{B}\bar{C}\bar{D} \$ matrices that lead to some \$ ABCD \$ that is still equivalent to the same transfer function I showed before, but has some \$ A \$ very sparse. If you do manage to get the matrix \$A\$ to be very sparse you will probably be able to get something close to the controllable canonical form, the one I show on the equation above (I am from control systems not signal processing). 

Since you can use \$ ABCD \$ to represent any transfer function that is proper, you can just use that matrix form and reduce a lot the amount of operations you need to use to calculate each iteration of the filter, and calculate all the state updates with just \$2N+2\$ multiplications and having \$N+1\$ memory usage.

Also, you can take a look at these implementations of filters in Verilog and see that they use mostly the filter approach, and also give some very insightful explanation of the way they designed the code for it
github Verilog filters.