How resolve "logic" is an unknown type error in Vivado synthesis?
logic and bit are added in SystemVerilog 2012.

You need to tell Vivado the file is in SystemVerilog.  It's documented
in chapter 8 of UG901 - Vivado Design Suite User Guide: Synthesis and
Appendix B of UG900 - Vivado Design Suite User Guide: Logic Simulation.


  Targeting SystemVerilog for a Specific File
  
  By default, the Vivado synthesis tool compiles *.v files with the
    Verilog 2005 syntax and *.sv files with the SystemVerilog syntax.  To
    target SystemVerilog for a specific *.v file in the Vivado IDE,
    right-click the file, and select Source Node Properties. In the Source
    File Properties window, change the File Type to SystemVerilog, and
    click OK.
  
  Tcl Command to Set Properties
  
  Alternatively, you can use the following Tcl command in the Tcl
    Console:

set_property file_type SystemVerilog [get_files &lt;filename&gt;.v]



Depending on your taste, you may want the suffix to be .sv since it's
SystemVerilog.  If you are creating the file from Vivado, you should
select SystemVerilog instead of Verilog.

You may also want to make sure the file's library property is not
empty.  It usually defaults to xil_defaultlib which works.  But on
some occasions (I don't know the exact conditions for this to happen),
it defaults to empty, and you get a strange error like "Incorrect
project file syntax" when you try to simulate it.  It's next to the
"Type" property in the GUI.