What happens with a parallel EEPROM data bus when the address is changed?
tl; dr version: If you were counting on the EPROM outputs for asynchronous logic, that’s a very bad idea.

The EPROM data bits change more or less at the same time after some delay from address stable. Emphasis on that weasel-phase, more or less. Strictly speaking, there is a period of unknown data state as the EPROM logic propagates the address through decoding, reading, then output.

This period of unknown data is the access time. There is no guarantee that the data will change only once after an address change. It could glitch through multiple states before it settles down.

The safer way to use EPROM output as logic would be to register it (use a clock to capture the output).

On the other hand, if you require an asynchronous, glitch-free output for logic, consider a programmable logic device instead.