Sampling (reading) a digital data signal?
The preamble in POCSAG is designed exactly for receiver to synchronize itself to the transmission data rate. At this point you can use well-known DPLL techniques to synchronize your internal clock with transmitted data.

The following blocks always begin with standard sync codeword, which means you can fine-tune the clock at the beginning of every payload.

Even though the data rate might drift between the blocks it is highly unlikely it will change within the block. You should be able to keep in sync by correcting the clock using sync codeword - that's what it is there for.

After receiving each block you can use hamming distance and parity bits to detect errors and use error-correcting codes if necessary.

As a side note, oversampling with sufficient frequency is too heavy for this MCU, considering required additional processing. Tasks like DPLL are better done using IRQ on data line. This would also separate synchronization from error processing, making code more efficient.