Do open source libraries exist for VHDL the way they do for C++ or python?
I'm a developer and maintainer at 'The PoC Library'. We try to provide such a library composed of packages (collection of new types and functions) and modules. It comes with common fifos, arithmetics, cross-clock components, low-speed-I/O components and a Ethernet/IP/UDP stack (next release).

As @crgrace described, it's quite complicated to design modules, which:


work on many platforms
support most vendor tool chains
add no/less overhead


Our library has an internal configuration mechanismn (PoC.config) to distinguish vendors, devices and even device subfamilies to choose the right code or an optimized implementation. It also distinguishes between synthesis and simulation code at some points.

For example PoC.fifo_cc_got is a FIFO with an 'common clock' (cc) interface and put/got signals to control the fifo. The fifo is configurable in widths, depths, fill-state bits and implementation type. It's possible to choose a LUT-based RAM or On-Chip-RAM (ocram) implementation type. If this fifo is synthesized with ocram option for Altera, it uses altsyncram; if Xilinx is chosen, it uses a generic BlockRAM description and implements the pointer arithmetic by explicit carrychain instantiation (Xilinx XST does not find the optimal solution, so it's done manually).

There are 2 other fifo types with 'dependent clock' (dc) and independent clock (ic) interface. So if it's required to switch from an normal fifo to a cross-clock fifo (PoC.fifo_ic_got), change the entity name and add a clock and reset for the second clock domain, that's all.

I think this proves, it's possible to write common modules, which work on multiple platforms and compile in different tools (Spartan->Virtex, Cyclone -> Stratix; ISE, Vivado, Quartus).

Besides PoC, there are other open source libraries:


VHDL-extras
libc in VHDL
PCK_FIO from easics
VHDL GitHub repositories from Martin J Thompson
noasic from Guy Escheman
open-vhdl
general-purpose-fifo
vhdl-examples
vhdlbyexample
vhdl-libs-pro
hdl4fpga
OpenCores
Aeroflex Gaisler
Stefan VHDL
...




The "Discover Free and Open Source Silicon" (FOSSi) projects on GitHub offers a browsable database of all GitHub projects that mainly use vhdl, verilog, systemverilog, or any other important hardware description language (hdl).

See also:


Discover FOSSi
FOSSI Foundation
LibreCores