Synchronise SPI: options? Dedicated reset line? Series of reset bytes not allowed in data? Long break?
The SPI master and slave sync based on the slave select signal. They should stay synced by always counting the bits in lock step after the initial slave select. 



The SPI protocol depends on master and slave being able to remain in sync. If they get out of sync, then there is a deal-breaker problem someplace that needs to be fixed. Good places to look are noise and level problems on the signal lines, or software implementation bugs, or buffer overruns.