AND gate design using MOSFETs
It would sort-of work, however the logic levels on the output would be so poor ('1' wouldn't be high enough) that the next stage wouldn't see good logic levels... 

Depending on the MOSFETs used (specifically their threshold voltage), this problem might be solvable, but in practice the standard solution is much easier despite the extra stage.

This is why earlier logic families used NAND gates instead of AND gates - they eliminated the inverter stage and inverted the logic levels for the second stage. 

Since the second stage was usually an OR stage (implementing (a and b) or (c and d)), and 'OR' with inverted logic is just 'AND', this meant that "AND-OR logic" was implemented with two levels of NAND gates, and the outputs were right way up again!