Trying to optimize simple PLL phase discriminator - Isn't there an off-the-shelf equivalent?
According to the 1984 National Semiconductor CMOS databook, Phase Comparator I is a simple XOR gate, which maintains a 90&deg; relationship between its inputs. Phase Comparator III is a simple S-R latch (level-sensitive, not edge-sensitive), which maintains a 180&deg; phase relationship between the two inputs. It requires that the signals be conditioned externally to narrow pulses, so the schematic in your question is pretty much it.

Phase Comparator II is the true edge-sensitive logic that drives the inputs to be in-phase (0&deg;). The full implementation (from the databook) is reproduced below. I guess most people today would implement this as part of their CPLD or FPGA.







simulate this circuit &ndash; Schematic created using CircuitLab