Is sytem level testcase different from block level testcase? And what is a test vector?
A test vector is a sting of bits that are used to represent the state of the system or an input stimulus to the system. If you registers are tied together on a scan chain then this long string of 1's and 0's can be used to exercise the system at different states.

Block level is typically more complete and explores all or most of the corner cases for rigourous coverage.  The system level may not be able to put each block into all of the blocks possible cases.  The system level will need to be less complex and have less coverage.