With IP-Cores without handshake protocol, how can I verify (VHDL assert?) their latency?
If you need a guarantee that the design will not change with a future tool version, then don't use an IP core for this sort of relatively simple functionality. You can quite easily instantiate one or more DSP slices with a fixed configuration that will not change between tool versions. The DSP slice user guide has everything you need to know. Depending on your use case, you might be able to infer an optimal implementation using a simple x &lt;= a * b;

You might find that in your application, you can time domain multiplex the inputs and mode for one set of DSP slices in order to achieve the same functionality with fewer resources; for example, do you need to multiply and accumulate at the same time? The IP core can never be aware of this.

If your primary goal is to get a design working quickly, then the IP cores will give an effective result.