What is the proper methodology to create portable FPGA designs?
HDL portability, like portability of software, is an unattainable ideal.  Every synthesizer has different strategies and different bugs, and vendor specific libraries will come into play.  However, it's worth striving for, as actual portability is like actual immortality...you'll never get there, but closer is always better.

Synthesizers can infer latches, and they usually do it in the same way--triggered by a block with a sensitivity list.  The primary rule of portable RTL is to write processes that trigger from common clocks.  If it's clear from your RTL where the latches are, it should be clear to the synthesizer.

Combinatorial logic can be included in your latching processes to allow the synthesizer freedom to use it at input or output.  Keep it outside the latching process if you want to make sure that a specific internal value is latched.

In general, don't partition combinatorial blocks if you don't have to...the compiler may find optimizations you won't.  However, if there's a clear and obvious architectural choice (such as a highly optimized algorithm), you might wish to impose that structure implicitly.  Further, unusually large blocks of combinatorial logic may send some synthesizers down a rabbit hole; repartitioning could give it guidance.