Setup and hold in flipflops
There are two situations to consider, D-flops closely coupled to each other on a board, and a D-flop each end of a long interconnect.

With the first, careful examination of the minimum propagation delays and the hold times usually results in it being OK to simply connect the clock to all D-flops. Q data stable at the active edge will usually remain stable long enough (non-negative) to meet the (often zero) hold time of the receiving flop. Being tightly coupled on a board means that little further skew occurs between clock and a data.

With a long interconnect however, we cannot rule out clock and data skew, and being either side of zero is not good enough. We need to generate two clock phases, one to capture the stable data in the receiver, and the next a guarranteed time later to clock the source, so that the source data hold time is met.

This is usually done by inverting the clock signal, and using one polarity for the source, and the other for the receiver. This is robust against varying the clock rate, and doesn't need any timing components. It is however very conservative on timing, as you often struggle to meet propagation and setup, and meet hold time with ease.

It's my personal opinion that it's probably better to think in terms of extending the hold time of the source data, rather than trying to meet the receiver's setup time. This is because most hold times are zero, so you only have to extend it further a little to meet your interconnect skew. You then have nearly all of the clock period available for propagation and setup. Of course, you still need to do worst case addition of all delays to make sure both setup and hold are met, you're just starting off from a different mindset.