How to modify input wires before sending them as input in another modules?
what I feel as the mistake in your code is assign #3 num2[0] = (num2[0] ~^ cin) and other similar expressions. Try changing the name of the net 'num2[0]' on the left-hand side. It will then work. Further, there is a mistake in your code for the expression series that involves 'num2'. All such expressions should be assign #3 NUM2[i] = (num2[i] ~^ cin), i = 1,...,7. You may find my version of the Verilog code for the problem below.

Verilog Code:

`timescale 1 ns / 100 ps
module FullAdder (
input a, b, cin, Clk,
output reg s, cout
);
    always @(negedge Clk)
    begin
        s = #7 a ^ b ^ cin;
        cout = #7 (a &amp; b) | (b &amp; cin) | (cin &amp; a);
    end
endmodule

module AddSubtract (
    input [7:0] a, b,
    input Cin, Clk,
    output [7:0] sum,
    output Cout
);
    genvar i;
    wire [8:0] C;
    wire [7:0] B;
    assign C[0] = ~Cin;
    generate
        for (i = 0; i &lt; 8; i = i + 1)
        begin   : AddSubArray
            assign #3 B[i] = b[i] ~^ Cin;
            FullAdder FA (.a(a[i]), .b(B[i]), .cin(C[i]), .Clk(Clk), .s(sum[i]), .cout(C[i + 1]));
        end
    endgenerate
    assign Cout = C[8];
endmodule