ESD protection: clamp to 12V or derived 5V?
The logic can only be clamped to 5V, any higher and you risk damaging those interfaces, any lower and you risk collapsing the signal.

Power input

The input to the regulator... Why not "shape the packet" with series R-L and an input capacitor. This would limit what the input of the regulator would actually see as well as help with the power dissipation of the regulator







simulate this circuit &ndash; Schematic created using CircuitLab

Maybe also a TVS rated at say 15V to 0V on the 12V line. 

Below is a crude simscape model to show the intent. The IEC 61000-4-2 (voltage not the current as I reduced the equivalent source impedance to 0 from 260R to emphasis the waveform) profile was superimposed onto a 20Vdc rail



Logic lines

The topology to use depends on the nature of these 5V logic lines: high or low speed, impedance matching. 







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One method is to place a TVS on the dataline. This will need to take all the energy BUT also imposes leakage &amp; capacitance on the dataline... something your datalines might not be able to tolerate









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The use of a series diode helps reduce the capacitance on the line BUT the energy involved may still result in a relatively large TVS









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A stearing diode to Vcc &amp; some series impedance will protect the dataline. However, the additional series resistance may upset your signal &amp; the charge flowing through the shunt diode may still be too high









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By using a higher voltage TVS at the input the voltage is limited such that the remaining energy being shunted into Vcc is reduced.

What topology is suitable is dependant on the energy involved, sensitivity of the lines and other aspects of the circuit.