Verilog: sampling data in both posedge and negedge of the clock
Use the negedge of the clock to sample the "right" data and store it to a register, then use  the posedge to sample the "left" data and the register.

reg r;
always @(negedge clock) begin
    r &lt;= right_data;
end

always @(posedge clock) begin
    // use left_data and r here
end