pipeline and verilog
Anything that follows the always @(*) if(condition) reg_type=value; will infer a latch. You most likely do not want to have a latch. 

If you want the result quickly, then you can separate the combination logic from the synchronous logic. 

always @(*) begin
    // set default : acts as a catch-all else statement. No latch is inferred.
    next_out = out; 
    if (state_5) begin
        next_out = ....
    end
end
always @(posedge clk, posedge reset) begin
    if (reset) begin 
        // reset stuff;
    end
    else begin
        out &lt;= next_out;
    end
end


Just remember there is still propagation delay.

Note: output is a Verilog keyword. Make sure you use a different name, such as out, output_reg, or something more descriptive.