Concatenation in port mapping
The warning is displayed because other VHDL tools, like the ModelSim VHDL simulator, do not support this type of port mapping (for signal B).

Another solution would be to use a sliced port mapping for B, e.g.:

ADD1: Adder_32_33
PORT MAP (
A =&gt; a1,
B(32 downto 1) =&gt; a1,  -- assign upper bits of B
B(0) =&gt; '0', -- assign (single) bit 0 of B only
CLK =&gt; clock,
S =&gt; s1
);


This assumes, that port B is declared with a range of (32 downto 0).

Please note, that always all bits of a port must be assigned.