How interrupts handle does work on a physical layer
The details depend entirely on the CPU, so you're best to pick your favorite CPU and study it in detail. For more general knowledge, there are books on computer architectures, like those by William Stallings.

In one of the simplest, traditional designs, the CPU simply does not "know" at all which device interrupted it. The CPU has a single interrupt line. If there are multiple devices, they are all tied to that single line: for instance, with a big OR gate. When the CPU handles the interrupt, the top level of the interrupt handling routine has to interrogate all of the devices by peeking at their respective status registers, to determine which one, or which ones, require service. When they are properly dealt with, they de-assert the interrupt signal.  Blocking specific interrupts can be implemented by making the external circuit sophisticated so that it can be programmed to selectively ignore some of its inputs.

This design can be improved upon in a myriad ways. For instance, there can be protocols whereby an interrupting device has to invoke a special bus cycle, and place its ID (8 bits or whatever) on the data bus, such that the CPU picks it up. The ID can then be used to index into an interrupt vector to dispatch an appropriate interrupt.

A processor doesn't even have to have interrupt pins; in one possible design, an interrupt is simulated when a device makes a write to some special memory location. Effectively, the address and data pins of the CPU serve as the interrupt inputs. See Message Signaled Interrupts.