STD_LOGIC_VECTOR to INTEGER VHDL
Why do you paste your code as an image?! This makes it harder for us to help you.
Please don't do that next time.

The answer is given by TEMLIB. You have two options:

1) Make a triggered process, with the internal value as variables.

begin
    process(divident)
        variable divident_int : integer;
        variable modulo_1_int : integer;
        variable modulo_int : integer;
    begin
        divident_int := to_integer(unsigned(divident));
        modulo_1_int := divident_int mod divis_1;
        modulo_int := divident_int mod modulo_1_int;
        modulo &lt;= std_logic_vector(to_unsigned(modulo_int, modulo'length));
    end process;
end architecture;


2) leave out the process (and keep the signals)

begin
    divident_int &lt;= to_integer(unsigned(divident));
    modulo_1 &lt;= divident_int mod divis_1;
    modulo_int &lt;= divident_int mod modulo_1;
    modulo &lt;= std_logic_vector(to_unsigned(modulo_int, modulo'length));
end architecture;