how to assemble SI7021 I2C command sequence
As @justme noted in his comment, clock stretching is defined that the slave may hold SCL low to pause the master. This is required to give the slave time to do the D/A conversions and have the data ready to send back to the master.
The alternative, as noted in the manual, is for the master to send the command and then to poll the slave until it is ready to send back the data. The slave will NACK the slave-reads from the master until the data is ready.

Assuming your master supports clock stretching, I suggest you go that route. This avoids having to poll in a loop.