FPGA/SoC - System Architecture: Independent Block Enables/Resets
Yes, what you just described is called Clock Gating. A popular technique used in the SoC Industry to disable peripherals to reduce dynamic power (especially when using a generic SoC for a specific usecase). You will find a lot of resources on this by looking up the term "Clock Gating". Here's one for example. The mechanisms to handle FIFO are also discussed in various resources such as 1, 2 and 3


  For a uProc controlled FPGA design (SoC), there may be SPI/I2C peripherals, there may be DMA engines, memory banks, Ethernet controllers, DSP IP cores etc. If there was an issue with an SPI controller for example, I want to be able to reset this without a full global reset.


What kind of issues are you referring to? When dealing with digital logic peripherals, there are usually programmable registers within each peripheral that allow recovering from known issues (such as DMA/Security errors) etc. Although special cases do have a reset separate from a Global Reset. For example: In a multi-core system you would want to keep the system reset independent from the individual core resets, so that the current state is not lost when one of the cores need a reset.