What happens if we use non-blocking assignment <= inside of always @* block?
For this particular example, you are right. Both synthesis and simulation yield the same results. However, since you were using non-blocking assignment, the simulator had to enter the always block twice, as an event was triggered by x. This may degrade the simulation performance. This could have been avoided if it was x = a &amp; b ;
This is one of the reasons why using blocking assignment for combinatorial logic has become a coding guideline in Verilog.
Reference: Section 11.0 of this Cummings Paper