ADC with parallel DDR LVDS interface and also a parallel CMOS interface
Do ultra low power DSPs exist that can interface with an ADC that has a parallel DDR LVDS output?


Define &quot;ultra-low&quot;. obviously, your DSP needs to deal with nearly 2 Gb/s of sample data, so this can only be relatively low power, right? Sounds like a laptop CPU to me...


Is the CMOS output intended for DSPs and the DDR LVDS for interface with ASIC or FPGAs?


yes. And no. You'll find either on either.


Is the ADC not capable of same maximum data rate when used with CMOS output? It does seem like it from the datasheet but it is not


Well, then trust the datasheet!
Driving CMOS takes a lot of power, and thus implies a limited switching speed. Thus, it'd be an unusual design decision to have a CMOS receiver for 160 Mbd.

mentioned in the front page that this is so.

What is the purpose of giving the Standard Swing, Low Swing, Default Strength and 2x Strength of the DDR LVDS interface on the
front page?


Well, guess what: defining the voltage swing and drive strength to suit your application!


Why is it important that we may able to control the default strength and output strength of the DDR LVDS output?


For longer, lossy traces on a PCB a higher voltage swing might be necessary for the signal to still be well-defined at the receiver.
To drive a lower load, e.g. for noise reduction, a stronger drive is desirable, which is not desirable when you drive with the normal transmission line wave impedance.