Why ARM cores consumes relatively lower power than x86
The original ARM architecture is designed so that even a relatively simple instruction decoder would be able to operate at the maximum speed permitted by the architecture.  Later ARM versions have slightly more complex instruction-decode logic, but every instruction is either one or two words long.  On the x86 architecture, instructions can be anywhere from one byte long to something like fourteen bytes long [e.g. within a 16-bit segment, LOCK ADD DWORD ESI:[EBX+4*EAX+12345678h],87654321h].  When the original x86 architecture was being designed, instructions were executed sequentially and it was expected that each instruction would take multiple cycles to execute.  If it would take three cycles to execute an instruction, it wouldn't matter if finding the start of the next instruction also took three cycles.  On the other hand, nobody nowadays wants x86 code to run that slow.

It's possible to design hardware that can run x86 instructions blazingly fast; 20 years ago, I would have thought that the complicated instruction decoding would have limited the x86 speed, but it really hasn't.  What it has done, however, is require Intel and other chip makers to include some rather complicated translation and caching logic so that the first time a piece of code is run it gets converted into an easier-to-decode form and cached; if the code is run again, the translation can be skipped.  All this logic makes for some very fast chips, but it also consumes power.  Many of the lower-power ARM chips have much less front-end logic; they don't achieve the same performance as an x86 that includes such logic, but they achieve much better performance than an x86 could get without it.