How does this expanded memory bus work?
Looks like address bits A14-20 are multiplexed with A4-10. The MCU probably puts out the higher address bits first to give an external decoder time to select a memory block, then puts out the lower address bits when reading or writing to memory. This also suits the multiplexing required for DRAM, which expects row and column addresses on the same address pins as RAS and CAS are activated.
A21-23 might also be multiplexed with A11-13, which would give a 24 bit address space (16 MiB, same as the 68000) in 8 bit data bus mode. This might explain why address lines A4-A10 were chosen rather than A7-A13. In 16 bit mode A0-A22 would represent A1-A23, with upper and lower data strobes substituting for A0.