Generate clock jitter in a testbench
random generates pseudo-random numbers between -jitter/2 and jitter/2 but as far as I know there is no constraint on the distribution of the numbers. So the "randomness" of the numbers might be crappy, i.e. there might be an obvious pattern for the random numbers generated.

dist_uniform as the name implies generate random numbers uniformly (uniform distribution) between -jitter and jitter.

What kind of jitter are you expecting? Gaussian jitter? In that case you should use a normal distribution.

Secondly, why do you need to simulate jitter? You want to test potential race conditions due to sampling?

I'm not sure that a Verilog simulation is the best tool for that problem...