Why double synchronizer alone is not enough for multi byte transfer between two clock domains?
Transferring a single bit is simple. It has only two states, and when a transition occurs, it can only be either in the previous state or the new state. Therefore the ONLY concern is metastability, and the two-flop synchronizer is normally sufficient to address this issue.

However, a multi-bit bus has an additional issue &mdash; when crossing a clock domain boundary, different bits might be perceived as changing on different clock edges because of tiny differences in delays in the logic and in the wiring. Some bits might go metastable while others won't, and they might take different amounts of time to resolve themselves. Now you don't have just the previous state and the next state &mdash; you can have any number of intermediate states in which only some of the bits have their new values, and some of the bits still have their old values.

This additional issue of data coherence is why the additional handshake logic is required. And this is why the dual-clock or asynchronous FIFO is a key building block in digital systems that involve multiple clock domains &mdash; it collects all of the required elements together into one neat package.