Systemverilog to Verilog translation
Not aware of any tool that will automatically do the conversion. You could do it by hand or write your own script. Here is a list of common SystemVerilog to Verilog-2001 (or vice-versa)


Easy conversions:

always_comb --> always @*
always_latch --> always @*, may want to add a synthesis directive for latch
always_ff --> always
int --> integer or reg signed [31:0]
shortint --> reg signed [15:0]
longint --> time or reg signed [63:0]
bit/logic --> reg
byte --> reg [7:0]
unique --> remove and add synthesis directives full_case parallel_case
priority --> remove and add synthesis directives full_case

More challenging conversions:

var = '0; --> var = {PARAM_VAR_BITS{1'b0}};
'1/'X/'Z --> same as '0 and substitute all 0 with 1/X/Z respectively 
function void --> if not called by any other function then task else function reg any calls should assign a dummy bit.
interface --> either add each net to the respective module port list or create `include files.
enum --> make each item a parameter, make the variable of packed array (aka IEEE 1364 vector) of reg
struct --> either separate out each item or make one bus with parameters as position keys
union packed --> same as struct plus some intelligent bus connections (ex: {dest_0[3:0],dest_1,...,dest_n[1:0]}={src_0,src_1[1:0]...,src_n[9:0]} )