'1011' Overlapping (Moore) Sequence Detector in Verilog
Your state variable is too small.  You have 5 states, but your variable is only 2 bits wide.  It must be at least 3 bits wide.  Change:
reg [1:0] PS,NS ;

to:
reg [2:0] PS,NS ;

Now I see z go high 3 times.

Now that you have unused states (5-7), you should add a default to your case statement.