What is the application of capacitor between Vcc and GND
MCUs often have multiple pairs of GND/VDD pairs, to provide charge to the MCU core with lower inductance; adjacent leadframe metallic structures for GND/VDD are the standard method; adjacency of conductive paths produces the minimum loop area and thus the smallest STORED ENERGY and thus the quickest way to rebuild the on-chip charge just consumed by MCU ROM/RAM/ALU/BUS activity.

That charge is best re-plenished if a reservoir of change (those  bypass capacitors) are located extremely close to the MCU GND/VDD pin twins.

Notice the schematic shows two GND pins and two VDD pins, hence the two capacitors.

======  added VDD dampening, for lower EMI =====     

To avoid failing the EMI radiated emissions, the VDD capacitors should be dampened; the internal ESR may be adequate IF YOU GET LUCKY. If you fail EMI, confusion reigns and people worry that the "magic" has vanished, when the previous design was executed with a punt-and-hope we-are-unaware of how to design well dampened VDD systems.

Using the math Rdampen = sqrt( L / C ),

with 4" (10cm of wire) between the 0.1uF cap installed at the MCU and the 10uF cap centrally located as bulk bypass for all the +3.3 volt users, you have 100nH (10 cm of wire at 10nH/cm, the wire NOT over a plane) and 0.1uF cap (Ignore the larger cap, for computing resonance).

The resonance of 100nH and 0.1uF is 1.6MHz.

The appropriate Rdampen, for zeta = 1 if I recall, or Q of 2, is sqrt( L / C).

Rdampen = sqrt( 0.1uF / 0.1uF) = ONE OHM.

I'd implement this as shown here







simulate this circuit &ndash; Schematic created using CircuitLab