Question about 74LS164 8-bit serial in parallel out shift register
The logic diagram shows the internal logic circuit of the device - inside the chip.

Once the underlying logic circuit is known, practically any question on the device logic state behaviour can be answered. And in conjunction with full device voltage and timing specifications, practically all questions on the device behaviour and operation can then be answered.

That's the ideal case. In reality, not all datasheets are of good enough quality. Here, it's a matter of opinion but I've found the various 74xxyy datasheets to be pretty comprehensive most of the time.



The 'Typical clear-shift-clear sequences' diagram (page 2) shows exactly that. It's not a 'Single 8-bit serial-parallel transfer' diagram.



The shift register in this device can shift in any number of bits. All but the most recent 8 bits will appear on the parallel outputs. The rest would have tipped off the end of Qh.

It's not uncommon to daisy-chain the devices to produce more than 8 parallel outputs, with the Qh output of one device connected to the A or B input of the next device. Some bits would pass through earlier devices on their way to later devices and the diagram makes it clear how each device would behave in that situation.

So there's more for that diagram to show than just a single byte transfer.