If a flip-flop D is given in input D = 1 when the clock is C = 1
For DFF to function as described in the datasheet, there're specific timing requirements must be met. Refer to the 7474 DFF datasheet, in particular page 6. It defines the following requirements:


tw, pulse duration. This is minimal duration of the respective signal in specific state (high or low);
tsu, data input setup time before CLK transitions from low to high;
th, hold time. Data input must remain in its state after CLK transitions high for the declared amount of time.


If your circuit using DFF complies with these requirements, declared functionality is guaranteed by the manufacturer.

However if something gets out of these requirements (out of specification), then behavior of the DFF - its state and level of its output signals - are not guaranteed, most probably causing malfunction of the whole device.

Next, about output levels. The same datasheet I linked to above shows Function table on its first page. It identifies the states and outputs of the DFF given specific input conditions. You must find answer for any scenario in this table.