PCIe Channel Multiplexing
The card is effectively a Serializer/Deserializer (SerDes for short). One possible implementation is there's a clock for the parallel bus running at PCIe 3.0 speed, which latches the incoming 8 bits of data. Then internally there is a shift register running at a faster clock (10Gb ethernet speeds) which just shifts that out. The process can be performed in reverse to convert ethernet data into PCIe signals.

There is a strong correlation between which PCIe pin corresponds to which bit of the parallel buffer, which is what guarantees the correct ordering in both transmit and receive mode (ex.: pin 0 is always bit 0, pin 1 is always bit 1, etc.). Parallelism is exposed at the bit level.

There is more complications when dealing with the actual PCIe/10G ethernet protocols, (10Gb ethernet uses a 64b/66b encoding), but this basic picture mostly sums up the broad idea.