How exactly does CPU set C/BE lines on a PCI bus?
The CPU cannot directly control those pins.  Those pins are driven by whatever device is the current bus master, which could be a PCI switch port or PCI device.  In the case of an operation initiated by the CPU, this will be a PCI port on some sort of bridge chip.  A bridge chip essentially performs a protocol translation.  The bits will be set based on the type of operation that the CPU performs.  For instance, if the CPU executes IO or memory read or write operations against the address space that corresponds to that PCI port, then the bits will be set appropriately as part of the requested operation.  Config read and write operations are a bit different - either Configuration Access Mechanism (CAM) which uses IO operations, or Enhanced Configuration Access Mechanism (ECAM) which uses MMIO enables the CPU to access PCI configuration space.