Work library is empty after compiling Verilog source file in Modelsim
From your screenshot it seems that you haven't saved the file - are you sure you saved your file before compiling? Else ModelSim might be simply compiling an empty file - which would, of course, yield nothing to add to a library.

If that's not the case, try this:


Delete old work library.
Use File &gt; Change Directory to change to your working directory. 
Go to File &gt; New &gt; Library and create a new library named work. This should create a new directory called work. 
Re-create your Verilog file/project and make sure it is in the same directory as the library you just created (not the work directory created in step 3, but your working directory)
Compile, and it should work