unwanted time delay in latch-circuit with diode
You have over 78 mA of base current through Q1.  That's a lot.  For only 24 mA of collector current, that's a whole lot.

You don't say how long &quot;to(o) much time&quot; is.  What is your timing requirement.


Instant analysis / mystic vision / inspired babble:
Both Q1 and Q2 are heating up due to the excessive Q1 base current.  This decreases the Q2 Vbe because a silicon transistor base-emitter junction forward voltage has a well-documented negative temperature coefficient.  But while D1 has a similar Vf and tempco, it is not subjected to the same internal heating.
There is no reason for D1 in the circuit, and in this case I think it is the problem.  When its cathode is grounded, its Vf is greater than Q2's Vbe, so it is not shunting away 100% of Q2's base current; there still is some current from R2 into the base of Q2.  R2 is so large that Q2 is being &quot;dangle-biased&quot; very slightly on, enough to supply Q1 with a very reduced base current.  As Q1 cools down, its Vbe increases, reducing its own base current even more, until it is starved into non-conduction.
Increase R3, decrease R2, Delete D1.
Reduce the Q2 collector current to 3-5 mA.
Increase the R2 holding current to 0.5-1 mA.