Declare signed numbers in Verilog
To declare a negative number in 2's complement form, you place the negative sign in front of the width specifier, for example

-8'H10


Would be the value of -16, and would have the same bit pattern as the unsigned value 8'HF0

You do indeed need to include the sign bit in your width considerations, and it is of course essentially up to you to keep track of which vectors are to to be interpreted as signed and which as unsigned.