How FPGAs offer Deep pipeline parallelism ?
Fundamentally, FPGAs have lots and lots of registers.  And lots of tiny RAM blocks also which can be useful for some pipelines.

If you can break down your algorithm into many tiny steps with a register at the end of each step, you can feed in a new data value on each clock tick.  During each clock cycle, the whole algorithm is performed, but each part is done on a different "piece" of the input data.  After the clock has ticked enough times to cover the number of register stages in your pipeline, the answer for the data which went in that many ticks ago comes out.

Adding register stages to run multiple threads is also called c-slowing.