How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?
Suppose the router runs that reference clock input alongside some 2.5 volt FPGA signals that transition in 50 picoSeconds, and the parallel-distance is 1mm and the separation is 1micron. Assume the dielectric constant Er is 5.

Let the reference clock be 10MHz with 1nanosecond edges, and also 2.5 volts swing.

How much jitter will be created? Or another way of thinking, at the zero-crossing of the 10MHz input, how much timing upset will occur. Assume the input clock line has a total capacitance of 10pf.

We simply compute the coupling capacitance between the 2.5v 50 picosecond logic signals and the 10MHz clock with its 10pF, modeling the two series capacitors as a voltage divider.

First: what is the capacitance? Use the parallel-plate model, assume the plates are 1mm by 1micron, and the plate spacing is also 1micron. C = Eo * Er * Area/Distance. We chose to ignore any fringing.

C = 9 e-12pF/meter * 5Er * (1millimeter * 1u)/1u

C = 45 * 1e-12 * 1e-3 = 45 femtoFarad = 0.045 pF

The voltage division ratio is 0.045 pf / 10pF, or 1/222.

The upset voltage at the zero crossing is 2.5v/222 ~~ 10 milliVolts.

Using Tjitter = Vnoise / SlewRate, we have

Tj = 0.01volts / 2.5v per 1nS = 1nS * 0.01v/2.5 = 1nS * 1/250

Tj = 4 picoSeconds

Is 4picoSeconds of deterministic Jitter a problem?