How to interface to a HyperRAM with a microcontroller
This HyperBus can only be found on a few Spansion/Cypress microcontrollers, it seems (the Traveo range, with Cortex R5F). So unless you planned to use MCUs from this specific family, you'll have to bit-bang the HyperBus interface using GPIOs.

Bit-banging would be a big performance hit for the CPU. It seems you have to toggle the CK/CK# lines 17 times for a single read cycle (and you, of course, also have the D0-D7 and other control lines to set appropriately all along this cycle). Now, let's say you have a 20MHz CPU and you need, on average, four CPU cycles per CK/CK# toggling (very optimistic, since you also have to manage the other bus lines within this budget), it means you need at least 50ns*17*4 = 3.4µS to achieve a read cycle.

Ax DoxyLover mentioned, there is a maximum Chip Select low time (certainly to allow the chip to manage the refresh timings internally) that is specified at 4.0µS. Our optimistic estimation is too close to this to be realistic. So, in addition to be a performance hit, it will most likely fail to work.

What makes much more sense, if you need that much RAM, is choosing a MCU that has a dedicated SDRAM interface. There are lots of Cortex-M that have it, now (LPC18xx/43xx, STM32F427/429/469, STM32F7, ...). The bus requires routing more signals, but it will give you much more flexibility in the choice of components, will be cheaper, and will run much faster.