SDRAM chip selection
You can do a little better than this; because burst transfers only use the data paths while in progress, you can overlap bursts with address signal transfers.

So you can get ready to transfer the next burst while the current burst is in progress; likewise you can open the next bank and set RAS for it before the current bank's transfer is done. Start the next actual transfer, then come back to precharge this bank.

It's more complex, and you'd have to read the Spartan-6 MCB docs in case they don't allow this stuff; I was rolling my own controller when I did this. 

In any case it sounds like you won't need it, but its nice to know it's there.

A bigger problem is that it will want to stop every 8 us and spend a chunk of time generating a refresh pulse (and precharges around it). I could tell it not to in my own core, (until a convenient break, but no longer than 70 us) and later added a similar hack to the Virtex-5 MIG core for this purpose but I don't think you can control refreshes on Spartan-6. So, if this is a problem, you'll need an elastic buffer somewhere to take up the slack.