Questions about MMIO
SPI doesn’t have a notion of address by itself. Memories that are attached to SPI (NOR flash especially) can be mapped to system memory addresses using a layer on top of SPI to translate IO accesses to SPI accesses. One mechanism to do that is execute-in-place, or XIP, which is supported by some microcontrollers.
Hyperbus is an evolution of SPI, and supports more general memory I/O, with PSRAM and DRAM as well as flash devices available for it. It, too, would use a translation layer for memory-mapped access.
If the system supports virtual memory, a more general mechanism can be used to manage memory attached to SPI or other slower external buses. When a page fault occurs, the kernel loads or unload pages from or to the slower device as needed. This would be more efficient than stalling the whole system while a memory request is satisfied by SPI. Further, it doesn't need a memory-mapped hardware translation layer, and can allow other processes to move along while the faulting process waits for its pages.