Need help with Verilog Card Counter
Your problem is here:

begin: Lights
  // ...
  if (count &gt;=5)
    led_big=1; 
  else
    led_big=0; led_light=0;  // &lt;---- Problem here


Verilog doesn't care how you indent or space your code.
Just because you put  led_big=0; and led_light=0 on the same line doesn't make them both part of the else clause. Without a begin and end around them, as far as Verilog is concerned your code is the same as

begin: Lights
  // ...
  if (count &gt;=5)
    led_big=1; 
  else
    led_big=0; 
  led_light=0; 


Now is it more clear that led_light is assigned to 0, regardless of the value of count?

Avoiding this kind of error is why you see many Verilog code examples that use begin and end for every clause in an if statement, even if there is only one statement in a clause.