Improving a processor design in VHDL
It is really difficult to respond your question.

You are looking for a methodology that could help you to solve your system issues, but this point is unclear due to the flexibility of HDL. You can plan a high optimized system but with a lot of interactions between parts or you can optimize each part isolating them from the rest of the system and well-defining their interactions with the rest of the system.

I have seen how the HDL system architectures have been changed through the last years. The tendency is create isolated modules and connect them with memory mapped interfaces as Wishbone or AXI. In your case, I think you can't use this kind of buses but you can apply the strategy of isolate parts and limit and well-define their interactions. This way will help you to simulate parts independently of the rest of the system and find localized bugs and bottle necks to improve them.

I wish this response could help!

Best regards