Altera III Cyclone FPGA input synchronization problem
For synchronisation you need at least two flipflops between the pin and the logic that uses it.  Those flipflops need to be very close together (in terms of the delay between the first Q output and the second D input).  You also have to ensure that the second flipflop does not get replicated (which it might if it feeds various other logic) - if it does you get race conditions as one flipflop sees an edge just before the clock and the other sees it just after.