Sampling a +/- 12v signal with a 0-3.3v micro pin
Your method needs a Vee that is negative with 1st stage inverting and the output range needs to reach Vdd=3.3V

Design  spec

Gain = +3.3/24V    (you have 3/22)
Offset=+3.3V/2
Inputs > 0 and outputs 0 to 3.3V

It's a little tricky to use a single supply Rail-to-Rail CMOS Op Amp 0 to 3.3V but your above requirements are simply is the ratios of Out/In reduced down to GAIN &amp; OFFSET specs.... to satisfy your "equation" or design specs,  "as we say in the biz."

But since the non-inverting gain \$Av+ = 1+ |Av-|= 1+Rf/Rin~~~ \$the Offset must be lower so that gain >1 and the output offset reaches 1.65V= Vdd/2. So the actual R Ratio for offset is not Vdd/2 but \$Vdd/2+3.3V/24V =1.451V\$ results an output offset of the new midscale point @ 1.65V.