Solve setup time violation when CLK is same as data input in shift resistor
That design should be okay. 74194 has a 5nS setup time, while 7432 has a 10/14 ns propagation delay.  If you use a more modern logic family like 74HC194 &amp; 74HC32 you might find the times are comparable while being much less power hungry. Or perhaps you follow the OR gate with another OR gate to slow it down some more - there are typically 4 in package.