Is there a way to convert BSDL format to synthesizable verilog?
BSDL is Boundary Scan Description Language. It describes, as it says, the boundary scan architecture of a chip/die, i.e. mapping between pins, internal IO pads and boundary scan cells in a way you can drive an internal test or an external test.

From IEEE-1149.1 § B.3:


  BSDL is not a general-purpose hardware description language—it is intended solely as a means of describing key aspects of the implementation of this standard within a particular component. A BSDL description is not itself a simulation model.


BSDL is a subset of VHDL in the sense its designers reused entity declaration and attribute statements from VHDL (mostly), and specified another language actually embedded into string literals. To me, this is another language. VHDL reuse is only useful when it comes to custom BS Cell definition that can be embedded in VHDL packages (IEEE-1149.1 B.10), something nearly nobody uses.

For board-level testing, an ATE cannot do anything useful with only BSDL of chips. It also needs the netlist. Alternatively, an ATE may use test vectors that were generated from BSDL and Netlist and saved to a test vector format, like SVF or HSDL.

So, for your initial problem: as there is no real synthesizable information in BSDL, there is no point in converting it to Verilog.