Unexpected behaviour of data memory in modelsim testbench
As the commenters to the question observe, there are a few things that don't make much sense in this code. First of all, the data &lt;= &quot;00000000000000000000000000000000&quot;; drive should not happen, as the signal is an output. What this drive intends to do should be achieved by initializing the memory in its architecture.
Also the read process sensitivity list is to long, it should only contain data address.
With these changes it works:
main code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.NUMERIC_STD.all;
use ieee.NUMERIC_STD_UNSIGNED.all;

entity data_memory is

    port(
         data_address: in std_logic_vector(4 downto 0);
         clk : in std_logic;
         we : in std_logic;
         write_data : in std_logic_vector(31 downto 0);
         data : out std_logic_vector(31 downto 0)
        );

end data_memory;

architecture data_arc of data_memory is
   
    type ram_32x32 is array (31 downto 0) of std_logic_vector(31 downto 0);

    signal mem: ram_32x32 := (others =&gt; (others =&gt; '0')); -- initializes memory to zeros
    begin


        write: process(clk)
        begin

        if rising_edge(clk) then
            if (we = '1') then
                mem(to_integer(data_address)) &lt;= write_data ; 
            end if;
        end if; clausulas catch all

        end process write;


        read: process(data_address)

        begin

            data &lt;= mem(to_integer(data_address));

        end process read;

end data_arc;

testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.NUMERIC_STD.all;

entity tb_data_memory is
end tb_data_memory;

architecture tb of tb_data_memory is


    component data_memory is -- registrador de 32 palavras
        port(
        data_address : in std_logic_vector(4 downto 0);
        clk : in std_logic;
        we : in std_logic;
        write_data : in std_logic_vector(31 downto 0);
        data : out std_logic_vector(31 downto 0)
        );
    end component;


    constant clock_frequency : integer := 10e6; -- 10Mhz
    constant clock_period : time := 1000 ms /clock_frequency;

    -- inputs

    signal we : std_logic := '0';
    signal clk : std_logic := '0';
    signal data_address : std_logic_vector(4 downto 0) := (others =&gt; '0');
    signal write_data : std_logic_vector(31 downto 0) := (others =&gt; '0');

    signal data : std_logic_vector(31 downto 0);

    begin


        uut: data_memory port map(
                                     data_address =&gt; data_address,
                                     clk =&gt; clk,
                                     we =&gt; we,
                                     write_data =&gt; write_data,
                                     data =&gt; data
                                   );

        clk &lt;= not clk after clock_period / 2;

        test_bench: process

        constant period: time := 200 ns;

            begin

                wait for period;

                we &lt;= '1';
                write_data &lt;= &quot;00000000000000000000000000000100&quot;;
                data_address &lt;= &quot;00001&quot;;

                wait for period;

                write_data &lt;= &quot;00000000000000000000000000000001&quot;;
                data_address &lt;= &quot;00010&quot;;

                wait for period;

                we &lt;= '0';
                data_address &lt;= &quot;00001&quot;;

                wait for period;

                data_address &lt;= &quot;00010&quot;;

                wait for period;

        end process test_bench;
end tb;