SystemVerilog: Sensitivity list of always_comb
Because simulation does not do the same kind of data flow analysis that a synthesis tool does to know that b is just a temporary variable. The LRM was written thinking that you always write to variables before reading the same variable in the same block. An always_comb block should be written as if it were a function called whenever an input to the block changes. To have the block re-trigger can be very bad for performance. 

The same style is used for a sequential always_ff block: a read before write within the same block is a flop, a write before read is a temporary variable.