Why are rise and fall times of a wave going through series inverters not dependent on first inverter?
Here is the input/output behavior of a 74HCU04, which is deliberately made without buffering (for linear applications such as crystal oscillators): 


Even with the unbuffered output you can see that the slope of the output voltage is much steeper than the slope of the input voltage. The more normal digital circuit is the 74HC04, which has a much sharper transition, such that almost in change in input voltage above or below the threshold will cause the output to go from one state to the other. 

At DC these transfer curves are multiplied by stages in series. So the curve gets even sharper for multiple stages (in fact the 74HC04 is rather similar to the 74HCU04 with added stages inside for buffering). 


For AC, the switching will be dominated by the characteristics of each inverter and the loading of the output, not by the input signal rise or fall times. As each stage output slews quickly through the threshold of the next stage, that inverter will begin to switch. 

TTL and CMOS inverters behave as above. ECL inverters have relatively low gain, so input rise and fall times could affect more stages.