Dividing a clock in Verilog - is it OK?
Theres a few things to consider


The chip needs to actually have the routing to bring a clock signal from a register output into a clock net. Most FPGAs i've worked with can but do check.
Clock nets are a limited resource, while some chips can clock flip flops off normal nets doing so is likely to have worse timing behaviour.
You are likely to need to manually tell the timing analyser what you are doing to get proper timing behaviour/analysis, the details of this are likely to be chip specific.
There is likely to be substantial phase-skew between the original clock and the generated clock.
To ensure the clock is clean it should come  directly from a register output, not from combinatorial logic.


Overall you can do it but I would consider it a last resort. Most of the time you can get similar results with a lot less headaches by using enable signals and/or by using multiple outputs from the chip's pll.