Using the ROM megafunction in VHDL code
You have two solutions, the first is to use components to define rom, place this code in your architecture's declaration, between architecture and begin.

component rom is
port (
    PC: in STD_LOGIC_VECTOR(7 downto 0);
    data : out STD_LOGIC_VECTOR(7 downto 0);
    clock : in STD_LOGIC
);


The second solution uses VHDL-93 syntax instead. Simply replace your instantiation with:

rom_inst : entity work.rom PORT MAP (PC, clock, data);


I prefer this syntax, but components are more flexible. You need components when instantiating block from Verilog, an IP core or a netlist. Components can also be binded differently trough configuration blocks.