Get more AS-attached flash chip information from ALTASMI
After several hours of searching in the dark of ASMI code and trying several ways to understand and inject into existing code I have the following code working properly added into asmi_altasmi_parallel_* module:

// Added circuit to shift all 24-bit data within stage 3 (transfer after opcode shift)
reg [23:0] r_mfr_and_id;                                // should contain all 3 bytes: manufacturer's code, ID[15:0]
reg [23:0] r_mfr_and_id_out;                            // output latched byte
always@(posedge clkin_wire or posedge reset)
    if(reset == 1'b1) r_mfr_and_id[23:0] &lt;= {24{1'b0}};
        else if((stage3_wire &amp; do_read_rdid) == 1'b1)           // stage 3 in progress (3 bytes after opcode sent)
        r_mfr_and_id[23:0] &lt;=
            { r_mfr_and_id[22:0], data0out_wire };              // capture all 24 bits shifting left

always@(negedge clkin_wire or posedge reset)
    if(reset == 1'b1) r_mfr_and_id_out[23:0] &lt;= {24{1'b0}};
    else if(rdid_load == 1'b1)
            r_mfr_and_id_out[23:0] &lt;= r_mfr_and_id[23:0];


It appeared that state stage2 is sending opcode to the AS device, stage3 is used for both sending address or receiving data (3 bytes after opcode), and stage4 is for data I/O.

And I decided, instead of injecting into existing code, to make additional registers and two always statements, partially duplicating already existing internals. Good thing that I do not depend on any intricate logic within existing code, and that the modification is just an addition of code. Bad thing is that I add some registers and logic already existing in the project - but let compiler optimize, I am more interested in reliability rather than small footprint overhead.

Additional task is to ensure r_mfr_and_id_out[23:0] wires go up to the ASMI high level module which then can be used in upper level module.

By the way, Altera/Intel proposed to use Generic Serial Flash Interface Intel FPGA IP, but it is not supported for Cyclone III family.