74AS TTL to CMOS pull up resistor and maximum speed (or lowest delay)
1) which is the lowest safer pull-up resistor for a 74AS piloting a
  CMOS device? Websites recommends from 10K to 2.2K from TTL to CMOS. I
  would use 1Kohm. Is it 470ohm still safe and better?


Check the datasheet of the device, there is a maximum output current for ViL (when the device is high ViH will pull little addtional current through the pull up). You should not exceed the IoL recommendation, for a SN74AS30, IoL is 20mA. That means at 5V you could go as low as 250Ω, it would probably be wise to not go quite that low and burn up lots of power, but maybe 1k. Since CMOS draws nA's of current the input stage for CMOS is negligible. 


  2) 74HC74 run at 30Mhz, 74AS74 run at 100Mhz. But which is the maximum
  speed (or propagation delay) of a 74AS74 with a pull-up resistor? Does
  the pull-up resistor jeopardize the 74AS speed advantages vs 74HC?


A pull up resistor can also introduce more noise if you have a noisy Vcc, to accurately determine the phase noise a simulation would be best.


  3) at the end: to minimise jitter driving a CMOS is correct that any
  74AS with pull-up resistor is better of any 74HC device?


There is no specification for jitter in the datasheets of these devices, so it will need to be measured. You can however understand the sources of jitter and work to eliminate them:


  These jitter sources include:
  
  Thermal noise
  
  
  kTB noise, which is associated with electron flow in conductors and increases with bandwidth, temperature, and noise resistance
  Shot noise: electron and hole noise in semiconductors in which the magnitude is governed by bias current and measurement bandwidth
  Pink noise: noise that is spectrally related to 1/f
  


Source: https://www.radio-electronics.com/articles/circuit-design/understanding-measuring-jitter-in-electronic-194