SPI software select not staying low
One part which is pretty obvious:

Do not leave chip select unconnected or low all the time. In most slave devices the chip select is an essential part of the state machine of the slave. In EEPROMs for example the write to the actual cells is often performed after the chip select goes high.

Now your logic analyzer captures do look very wonky. My guess is that you have some noise on your lines (coupling from the other lines, ground loops) so that you aren't actually seeing what's really going on there. I've also had reports from colleagues that the logic analyzer itself was injecting a fair amount of noise.

You haven't mentioned if you actually looked at what the software is telling you - do you get the read buffer to be the same as what you have written? That's the prime thing you should be worried about, if that is not the case then you can start looking at the bus, but before that I'd try to see what I can get in the debugger.

If your analyzer supports analog mode, it might be worth looking at analog signals to see if some of the edges cause significant noise on the other lines. Or use an oscilloscope of course.