Xilinx clocking wizard - How to connect clkfb_in and clkfb_out
The additional feed-back ports (clkfb_*) are visible when you select something other than the default "Automatic control on-chip" for the "Clock Feedback Source" (Page 3 of Clocking Wizard, version 3.6). It has nothing to do with the selection of "No Buffer" for the input clock.

If you just want to get a 50 MHz internal clock out of the 100 MHz external clock select the default "Automatic control on-chip". And on the first page select for the input clock:


either "Single ended clock capable pin" if the external clock is connected via a single wire to the FPGA (most common for 100 MHz),
or "Differential clock capable pin" if the external clock is connected via LVDS.


The other feedback options are only required for more advanced control of the phase relation-ship between the original and the generated clock. For this, the clkfb_in and clkfb_out ports provide access to the feedback loop of the PLL. 

An example scenario is the Zero Delay Buffer, where the generated clock is outputed again by the FPGA. If the original clock (at the input clock pin) and the generated clock (at the output pin) should now be in phase, the feedback loop must also encounter the delays of the input and output drivers of the FPGA pins. Thus, one must feed back the generated output clock (at the output pin) to another (clock) input pin of the FPGA via the PCB, and connect these input pin to the clock-feedback input port of the PLL (clkfb_in).
If the generated clock has a different frequency than the original clock in this scenario, one must bring out the clock-feedback output signal (clkfb_out) and feed this back via the PCB. A picture of this setup can be found in the user guide UG382 Spartan-6 FPGA Clocking Resources in Figure 3-13 on Page 111.