7405 TTL Chip outputting nothing when given low input
74xx05 ICs have open collector outputs. Therefore, when the input is high, the output is pulled down, but when the input is low, the output is in high impedance.



To get an high level output, you should connect a pull-up resistor between the output and VCC (5V). Or, use the push-pull (totem pole) output version, i.e. 7404.







simulate this circuit &ndash; Schematic created using CircuitLab

The value of the pull-up resistor R1 mainly depends on:


The speed you need to achieve (the 74LS05 datasheet of one supplier indicates that with a \$2\ k\Omega\$ resistor you achieve a 32-ns low-to-high propagation time, if the loading capacitance is 15 pF).
The current that R1 must provide to "what you are connecting to the output of the gate" (e.g. another logic gate), while maintaining the correct high-level value. If you are connecting another gate (or an input of a digital IC), then you must check its high level voltage and its input current. The high level voltage and the input current (input load) depend on the particular logic family you are using. For instance, let's assume you will connect the circuit above (74LS05+R1) to another 74LS05. The 74LS05 datasheet indicates that at 2.7V, the input current is \$20\ \mu A\$. This means1 a maxmimum resistor value of \$(V_{CC}-V_{IH})/I_{IH}=(5\ V-2.7\ V)/20\ \mu A = 115\ k\Omega\$. (NOTE! A standard TTL - i.e. not Low-power Schottky "LS" - has a high-level input current which is \$40\ \mu A\$. There the maximum pull-up resistor value is half the value previously calculated!) 
Furthermore, the output of the 74LS05 is not ideal, therefore it has no infinite impedance, when the input is low: some current might leak into the output. In the datasheet this is indicated as \$I_{OH}\$ - which is positive for the 74xx05, indicating that this is a sink current. The 74LS05 has a \$I_{OH,max} = 100\ \mu A\$ (see note 2). This drastically reduces the \$115\ k\Omega\$ value calculated above! In case you want to connect the output of the circuit above to another 74LS05, the upper value is now \$(V_{CC}-V_{IH})/(I_{IH}+I_{OH,max})=(5\ V-2.7\ V)/120\ \mu A = 19\ k\Omega\$.


In practice, what dominates is the first constraint. 

The considerations above set the upper bound resistor value. The lower bound is determined by:


The maximum current consumption you can accept.
The output drive capability of your logic gate (i.e. the maximum current it can provide, while maintaining a low level voltage compatible with your load - e.g. another gate). For instance, the 74LS05 has a \$I_{OL}=8\ mA\ @V_{OL}=0.5\ V\$, which results in a minimum pull-up value of \$560\ \Omega\$.


Typically unless you want to go at "high speed" (> 1 MHz) and unless you must connect this output to many inputs (high fanout), a classic \$10\ k\Omega\$ is enough. 



Bonus fact

You can create a "wired-nor" gate, by connecting the outputs of two or more inverters of the 7405! Take a look at the circuit below: when A="1" OR B="1", the output is pulled low. When A="0" and B="0", then the output is pulled high by R1.







simulate this circuit

Don't do this with regular 7404 gates!



Notes:


Actually the high level input voltage \$V_{IH}\$ is 2.0V, but the datasheet indicates only the value of the maximum input current \$I_{IH}\$ when it's at 2.7V. This adds some safety margin.
\$I_{OH,max} = 100\ \mu A\$  is shown with \$V_{OH}=max\$ (5.5 V). It will be smaller at lower output voltages. Using this value, also adds some safety margins.