Multiple Transistors (FinFET) sharing a gate?
Since the channel width is determined by the height (and also by the thickness, which you want to keep small) of the fin, if you want a large W/L ratio (to achieve, for instance, a larger drain current), then you need to create multiple-fins finFETs, resulting in many finFETs in parallel. 



In the picture above, the distance between drain and source (i.e. the width of the blue gate, along the fin axis) is channel length. The quantity \$2\cdot H_{fin}+T_{fin}\$ defines the channel width.

You might also want to share the gate (without connecting both the sources and drains in parallel) in other applications, such as memories or logic functions. 

Here is a electron microscopy of many finFETs sharing the same gate.



As a last remark: I know that this would be quite difficult to render graphically, but in your picture, the thin dielectric layer, which separates the substrate from the gate, is missing!