Process statement in vhdl
The statements inside a process are indeed executed sequentially, but they are all executed each time the process is activated (as defined by its sensitivity list).

Typically, the entire process will be executed once per clock edge, which means that any outputs (signals or variables) that get assigned within the process can all be updated on any given clock edge.

In this case, "sequential" refers to the relationships among the statements inside the process, but it has no bearing on its interaction with the rest of the design.