Why do we need to use transistors when building an OR gate?
What you describe is called a wired OR connection. It is possible in some logic families, particularly ECL (emitter coupled logic), but not in the most common ones (TTL and CMOS).

In CMOS it isn't possible because when a CMOS output is low, it creates a very near short from the output pin through the chip to ground. And when it is high, it creates a very near short from VDD through the chip to the the output pin. 

So if you tied two CMOS outputs together and one output high while the other output low, you'd have a very near short from VDD to ground, which would draw a large current and likely overheat one or the other of the two chips involved.

For TTL, there's a similar issue, but the "shorts" from the output pin to VDD or ground aren't quite as near short as they are in CMOS.

There's a variant output style, called open drain for CMOS or open collector for TTL, that allows wired AND connections rather than wired OR. These outputs are designed to only be able to sink current to ground, not to be able to produce any output current when they're nominally in the high state. These are normally used with an external pull-up resistor so that the output voltage will actually reach the "high" voltage level when required. 

Note: Open collector or open drain can be used for wired OR if you use active-low logic (low voltage represents logic 1, high voltage represents logic 0).