How to simulate a n-p-n bjt using Cadence Virtuoso?
The NCSU PDK has a circuit symbol for a BJT for schematic design, but not for simulation.  You did not mention the version that you are using of the NCSU PDK, but as of 1.4.x, the lateral BJT could not be simulated.  I assume you are trying to make a lateral BJT because of two things:  the model ami06n, and the NCSU tool kit targets the C5 process, which is now owned by ON:  http://www.onsemi.com/PowerSolutions/content.do?id=16693 that does not have an explicit BJT.

If you want to lay these out, this will get you started:
http://users.ece.gatech.edu/phasler/Courses/ECE4430/Unit3/BJTTechnology.pdf
I use a ploy ring structure that is different from what is in those slides.  Also, you need to be mindful to keep the lat-BJT in a guard ring and away from t-gates or you will likely make a parasitic SRC.