What do HDLs compile/synthesize to?
Just like a procedural programming language goes through several steps (compile, assemble, link) to produce an executable, HDLs must pass through several processes before a usable configuration file for the FPGA is generated. These include


Synthesis --- convert the HDL code into a netlist describing connections between logical elements.
Mapping --- Convert the netlist into a more refined netlist that uses resources actually available on your FPGA device.
Place and route --- select which of the actual resources on the device will be used for each of the required elements in the mapper output, and choose which routing resources will be used to interconnect them.
Bitfile generation --- convert the place and route output to the format actually used to program the device.


So if, when you ask what is the output of synthesis, you mean what's the output of the first step of this process, then it's an intermediate file used as input to the mapper. If you mean what is the output of the whole process, it's a bitfile that the FPGA can use to configure all of its logic and routing resources.