Finite State Machine and Reset Signal
If you are talking about the simulation of a state machine then this is usually true. Without a reset signal the state register wakes up with an unknown value. The next state logic can do nothing but produce an unknown output from an unknown input, so the machine never reaches a stable state.

For a real, physical state machine the answer will depend a great deal on what the machine is supposed to do. Is it possible to wake up in an undefined state for which there is no transition to a defined state? Is it possible to wake up in a state that would cause the rest of the system to malfunction? Does the system require that the machine transition in an orderly fashion from some initial state? These questions cannot be answered in general.