AND gate output when inputs are open
The answer depends on the design of the AND gate.

A traditional TTL gate will treat an unconnected input as a logic high, so the AND gate with two unconnected inputs will output high.

For a CMOS gate, the result is much less predictable. The unconnected input might drift either high or low, depending on nearby static fields. Worst case it drifts to an intermediate voltage and only partially switches the output, leading to excess heating of the gate. Or the output could oscillate between high and low (again leading to heating up the circuit).

A high-Z output is unlikely in either case, although it could be the result for something like a simple wired diode logic.

Edit:

Th 2-transistor AND gate at your linked site is neither a traditional TTL design nor a CMOS design.



This circuit will treat an unconnected input as low, since it is current flowing in to the transistor bases that defines a "high" input for this circut.