Readying a New Design, would appreciate som feedback
When I review schematics/PCB during my day job, for a design like this, I would spend about 8 to 16 hours going over it.  Clearly I cannot do that here.  Further, I cannot give you a lesson in EE for each thing that is wrong in the design.  And to make things worse, EE.SE is not really suited for a back-and-forth dialog that is normally required for a review like this.  So here's what we'll do.  I'll do a quick review of the design and put the issues that I spot in this answer.  You read that, do some studying on your own, and if you still don't understand then you need to post a new question (not a comment on this answer).  Here goes:


You need some EMI filtering on the +3.3v to the center tap of the Ethernet transformers.  Some sort of ferrite bead + cap(s).
You need ESD protection diodes on the Ethernet signals to U4.
10 pF decoupling cap on X2 is astonishingly small.  Use 0.1 uF.
Ethernet termination resistors, R42-45, must be at least 0805's to handle the wattage required.  I can't tell what size you are using.
Something doesn't look right with the Ethernet TX CLK signal.  I don't think you should have it connected to three chips (Oscillator, Phy, and MAC).  Double check that in the Phy/Mac reference designs.
Put a 0.1 uF cap on the "input" side of your ferrite beads.
The note "crystal oscillator needs to be 12 mm away from the phy" is a HUGE red flag to me.  It makes me think that something is not right, but I don't know what.  If this were a normal design review I would grill you over this.
You should filter or buffer reset signals that go over connectors (like SHIELD_RESET).  This is a huge way for an ESD event, even 6+ feet away, to cause the PCB to reset.
You should have a 0.1 uF decoupling cap(s) at every connector to reduce the AC signal return path for signals on the connector.
It doesn't look like you have enough input caps on the DC power input.  I could be wrong, however, since I can't read your schematics that well (stupid web-app).
You might need more caps on the output of your voltage regulators.  I didn't check, however, because I don't have time to read the datasheets.
It is hard to really judge the PCB layout without looking at the design in the CAD software (Altium).  But I see enough issues that the whole design needs to be scrutinized before being send out.
Vias need to be spread apart so they don't cause slots in the power/gnd planes.
Additional gnd planes on the top and bottom layers is not adding much to the design.  It is worth it to just remove those.
Do you have proper signal termination on the MII signals between the MAC and Phy?
Have you verified that the PCB layer stackup is correct for the trace impedance you want and the signal termination that you have>
You have signals crossing voids in adjacent power/gnd planes.  This is a HUGE no-no.
Your signal GND plane and your chassis-gnd planes overlap.  Never, ever do this.  (Disclaimer:  I could be looking at the plots wrong.)


So there you go.  Good luck!