Sensitivity list rule in HDL
Forget that rule. Here's a simpler one:


If you want sequential logic, use always @(posedge clock) (or negedge). You don't need to mention any other signals in the sensitivity block.

(You can sometimes also use sensitivity lists like always @(posedge clock or posedge reset) for reset signals, but don't try to get too fancy. It's very easy to create something that won't synthesize.)
If you want combinational logic, use always @(*).

This is a shorthand (introduced by Verilog-2001) that makes the block sensitive to every signal that's used in it. There's no reason to name every signal anymore -- that syntax is obsolete and unnecessary.