Net type, variable type, data type and data objects
No wire is not a data type; it is a net type. SystemVerilog has some confusing implicit declaration defaults to be backward compatible with Verilog. 

When you write the following in Verilog:

wire w;


it's the same as this following in SystemVerilog:

wire logic w;


This means w is a net with a 4-state data type (0,1,x or z). And the wire kind of net  means it can have multiple drivers with different strengths. When there are conflicting states with the same strength, the net resolves to the X state. Other kinds of net types use AND or OR to resolve conflicts. Net types cannot have procedural assignments.

When you write the following declaration in Verilog:

logic v;


it's the same as this following declaration in SystemVerilog:

var logic v;


This means v is a variable with a 4-state data type (0,1,x or z). And being a variable means it is allowed to have only one continuous assignment, or any number of procedural assignments. It cannot have both kinds of assignments.

Whether a variable gets synthesized into a Register/flop or physical metal wire depends on its usage.

You may also want to read http://go.mentor.com/wire-vs-reg

BTW, there are slight differences in the defaults for module port declarations. For example (input logic w) defaults to a wire net type,  not a variable.