Why are n-channel MOSFETs at high-side position and p-channel MOSFETs at low-side position on many push-pull circuits?
Right: common drain, push pull, source follower
This simple circuit with a NMOS and a PMOS is quite common. Being a follower, it has gain close to unity.
Switching applications: this is almost never used because to make the output swing to both rails, you need the NMOS gate to be driven higher than the power supply, and the PMOS gate to be driven to a negative voltage, which would add extra complication for no benefit. Also, in buck converter applications, when the output voltage is lower than half the input voltage then you want the lower FET with lower RdsON (so it should be NMOS) since it will be on most of the time.
Linear application: this is your standard follower output stage. It is easy to bias into classes AB or A or B, has high input impedance, it's pretty good. However if the drive voltage can't go above or below the power supply, then the output can't swing closer to the rails than one FET threshold voltage. If zero threshold voltage FETs are available (or JFETs) then it can be close to rail to rail if the driving stage is. If it is implemented with discretes and components like large capacitors are available, the driver can be bootstrapped to the output and generate voltages above VCC and below GND, so it can be close to &quot;rail to rail&quot;. However, capacitance of FETs increases massively when Vds gets close to zero, so while it is very fast when Vout is away from the rails, it gets pretty slow and crummy when Vout is close to VCC or GND. So you must compensate the whole loop for that.
Why do I emphasize rail to rail? CMOS opamps are popular at low power supply voltages when a rail to rail output is a very important feature to have, and you won't find this structure in these opamps.
Middle: Common source complimentary
Switching: This can have both FETs ON continuously (not at the same time of course) without needing any boosted supplies, which is convenient if you want a buck converter or any other switching circuit that can do 100% duty cycle. Also, if the output/input voltage ratio is low, the lower FET will be on most of the time, so a higher RdsON PMOS on top is less of a problem.
Linear: This is your typical CMOS opamp output stage. It is rail to rail, and that will work down to a pretty low supply voltage. However it is more complicated to drive than the simple follower on the right, because it has two inputs instead of one. To bias it in Class A-B-AB properly, the sum of both Vgs must be constant and thermally compensated. In the follower configuration this is easy because there is one bias source labeled &quot;V8&quot; connected to both gates. In common source configuration, the sum of V5 and V4 must be held constant. Likewise the follower is easy to drive: it has one input. The common source requires a circuit to split the input signal into two complimentary halves to drive each FET.
Left: two NMOS
Switching: Since NMOS are faster, have lower capacitance, lower RdsON, etc, than PMOS, this circuit generally gives best performance for switching if you care about speed, RdsON, or cost. However it requires a boosted supply for the top FET. If you don't need it to be on continuously, this means a bootstrap, but if you do it means a charge pump. Since bootstrap requires a &quot;large&quot; cap, it can't be done in an IC without external capacitor. A charge pump can be done in an IC without external cap, but its output current will be tiny, so if you need speed... you'll need a decoupling cap. This is not the case for the NMOS/PMOS common source, which can switch fast without any help.
Linear: Basically the same characteristics as the previous one, with the same drive complications, except it's more linear (due to both FETs being identical), the NMOS is faster than the PMOS, and it's not rail to rail unless the top driver has a boosted supply. So this can be used for discrete amps, but not in opamps.
Cross-conduction: All of them can have cross-conduction.
The common source stages will cross-conduct if the gate drive signals turn both FETs on, or if high dv/dt on the output, through Cds, pulls the gate of the FET that is supposed to be off in the direction that makes it turn on, and whatever circuit is in charge to keep Vgs=0V has too high output impedance.
The common drain stage will cross conduct too, when it comes out of clipping, if the gate resistors values are too high and the driver slew rate is too high. If you use bootstrapped drive to turn one FET fully on, it will have a much larger capacitance than the other. When it tries to come out of clipping, this means the FET that was off, which has high Vgs and thus low capacitance, will charge its gate much quicker than the other through the same value gate resistor, and they will both turn on for a brief moment every time it comes out of clipping. If this goes on for enough cycles, the FETs will blow.
Note the issue is the same with the other circuits in linear mode if they are used in rail to rail mode: the FET that is fully on turns off slowly, the other turns on quickly. BJTs have the same issue in common emitter if you let them go in saturation, they take forever to come out of it.
Other linear considerations:
The middle one (common source) is voltage in, current out, which means it is a transconductance stage. The transfer function is not Vout/Vin, but Iout/Vin instead. To get Vout/Vin, you must take into account the load impedance. If it is unknown when designing the circuit, then potential stability issues arise, so something needs to be done to keep the whole loop stable, either compensation or a HF load impedance stabilization (Zobel) network on the output. On top of that, it is inverting, which means at frequency low enough that the FETs still have gain, for constant AC output voltage you get a drive current proportional to frequency due to Miller effect through Cgd. Since Cgd depends heavily on Vds, and gm depends heavily on Id and Vgs, and transconductance when driven from a finite impedance is proportional to gm/Cgd your loop gain will be all over the place.
But when the FETs run out of gain due to all the drive current being sunk into Cgs and Cgs, all you have left is Cgd which pumps the drive signal into the output, which means... it stops being an inverter. It's just a cap between gate and drain. So you get a 180° phase shift, at a frequency that depends on which FET is ON and how close to the rail the output is. This absolutely needs to be taken into account for loop stability.
The follower is... a follower, so Vout/Vin is close to 1. This makes it simpler to compensate the whole loop. At high frequency, it also becomes a capacitor, but since it was not an inverter at low frequency, you don't get the 180° phase shift. Again, easier compensation.
With discrete FETs, lead inductance will also mess it all up.
The one on the left will switch between both modes depending on which transistor is on, if you make the mistake to think it is a follower.
Note the drive current for all these is the same (ignoring differences between NMOS and PMOS). If you want an output voltage V, the load will want a corresponding current I to reach it, which means the Vgs of both FETs have to be brought to the same value no matter how they are wired, which means the driver will have to provide the same current to charge Cgs and Cgd in all cases.