Propagation delay in 4 inverter w/l ratio
Since you are working with Cadence you could use simulation to find an optimum.

Use a design variable WP for the width of the PMOS and WN for the width of the NMOS. Define a parameter k.

For the first inverter specify the width of the PMOS as WP and for the NMOS as WN. For the second inverter use k * WP and k * WN, for the third k * k * WP and k * k * WN, and so on.

Perform a parametric sweep for k from say 2 to 10 with an increment of 0.1 and evaluate the delay of your buffer. Plot the result and find the minimum.

For a more theoretical approach you find some information here.