Bus isolation circuit
For the first schematic if the POWOK is low it will turn off the NPN transistor allowing the collector resistor to pull the two FET gates to the positive voltage and thus allow the SMBus isolator to function between the VCC3 and the 3VSB power domains.

The second schematic is used to allow SMBus level conversion for the IPMB interface between the 3V3SB domain and the 5VSB domain. No particular power gating is intended by this circuit. It is just that typical off board interface for IPMB has been 5V signalling levels since legacy times and most modern on-board controllers (SOC, chipset or BMC) will be using 3.3V signalling for SMBus.