Is there a rule for DDR4 CA signals reference plane?
If I remember correctly there's two reasons.  One it's an attempt to make sure you could route it densely on only four layers.  So your dq are on top, gnd below them.  Then other signals are on the bottom referenced to VDDq.  Since you want a plane for both of them.  Then I think I've seen that is also the way it is done in the Dimms so following that convention in your board would let you match their design.