When should I use SR, D, JK, or T Flip flops?
In discrete logic (like 74xx series), you use whichever choice lets you design your circuit with smallest number of parts and without violating timing requirements.

In FPGAs, you mostly design in HDL (VHDL or Verilog) and the synthesis tool works out for you what to use. But the underlying technology basically just provides D flip-flops, so the synthesis tool figures out how to implement what you code with D flip-flops.

In ASICs, a high level designer again designs with HDL. But probably (ASICs aren't my area) the ASIC vendor's library may provide other options beyond D flip-flops, and the synthesis tool will figure out how to implement the code using the available library components. It could choose one or the another to optimize either circuit speed or chip area.