VHDL - D flip flop simulation goes wrong
The problem is that my teacher told me that, when using D flip-flops, if the clock and data signal rises at the same time, the flip-flop state does not update till the next rising edge of the clock.


This is a highly idealized description, and not even a very useful one.

A much better model for the behavior, which is still quite simple, is that


  If the input is stable during the clock edge, for a "setup time" beforehand and a "hold time" after, that same stable level will emerge from the output after a "delay time".


And no guarantees are made if, as in your simulation, the input is changing within the setup-and-hold window.

In actual circuits, clock distribution is designed to be faster than signal distribution, so that changes happen after the clock edge.  And the hold requirement in modern logic is very nearly zero.  In such cases things work.

But if the delays in the logic producing the flip-flop's input add up to nearly a whole clock cycle, you can get into trouble with setup time violations.

And if you are doing your own PCB layout and not careful to make the clock the shortest trace, then signals synchronized to the clock in one part of the circuit can outrace it and be seen to transition in another part before the clock edge, which also violates the setup&amp;hold requirement.