Verilog Down Counter Logic Implementation
counter2 is reset to state 11. When the trig rising edge occurs, it starts counting down. 

Your code shows no way to ensure that the trig edge is syncronized with your clk signal. In your simulation, trig goes high very shortly before a clk rising edge. So on that edge, counter2 starts counting down --- going to the 10 state. But in between the trig edge and the clk edge, you did have a brief period where counter2 was in the 11 state. So you did in fact have counter2 in 4 different states after the trigger edge.

If you want to be sure to keep the counter in the 11 state for at least one full clk cycle after the trigger, you could  either syncronize trig to clk, or delay the input to the counter en input for one cycle after the trigger is seen (essentially the same thing, but making a new syncronized signal).