Synchronous serial interface in verilog
You have three clocks, your FPGA (50MHz) clock your ADS1672 clock and your shift clock. In a case like this where your system clock is much higher the best approach is to run a fully synchronous system and use a sort of 'oversampling'. 

If you make your SCLK identical to you ADS1672 clock, you have only two clocks to cope with: FPGA and 12.5MHz.

You still generate the ADS1672 12.5MHz clock, but you don't use that signal in your FPGA as clock. Instead you sample all the inputs just before you set the ADS1672 clock high. That gives the ADS1672 the maximum time to get the signals out en into your FPGA. 

I can't write all the code but it comes down to this: (Not tested!)

reg [1:0] clk_div;            // Divide by four
wire      ADC_clk=clk_div[1]; // FPGA clock/4 
reg       ADC_sclk;

always @(posedge clk or &lt;your reset&gt;)
begin
    if ( &lt;your reset&gt;)
      ... clear all your registers
    else
    begin
       clk_div &lt;= clk_div+1;
       if (clk_div==2'b01)
       begin
          // Next cycle ADC clock goes high
          // At this moment we can read the inputs
          // They have had maximum time to get stable
          // ALL code to do with the interface (except shift clock) comes here.
          ........
       end

       // Here is you shift clock
       if (sclk_on)
       begin
          if (clk_div==2'b01)
             ADC_sclk&lt;= 1'b1;
          if (clk_div==2'b11)
             ADC_sclk&lt;= 1'b0;
       else
          ADC_sclk&lt;= 1'b0;