Can someone explain what this line means in the code for a D Flip Flop written in Verilog
First of all the '&lt;=' is a type of assigning value to the variable. It doesnt mean less than; but instead the value zero is assigned to variable 'q' when the condition is met
Summary of verilog syntax : http://ee.sut.ac.ir/People/Courses/142/Summary%20of%20Verilog%20Syntax.pdf

if(~reset) - this means the condition is fulfilled when reset = 0 (~ is a bitwise negation operator, check the above link in the operator section), meaning when reset is zero the statement q&lt;=1'b0 is executed other wise the input is passed to output which is given by 'q&lt;=data'. This is the functionality of D flip-flop.