Could you please validate this sine to square circuit?
R6 and C2 form a 33.8 kHz lowpass filter that reduces high frequency noise and slows the rise and fall times of the output squarewave.  Because R2 is the collector load, the actual filter corner frequencies are 33.8 kHz for the trailing edge, and 3.08 kHz for the leading edge.  You can see this in your sim image, where the output square wave has three steps in the rising edges and only one or two steps in the falling edges.  If the uC input can take the 5 V waveform directly, I don't see any need for R6-C2.

Without the transistor installed, the R5-R7 node sits at 2.08 V.  If the purpose of R7 is to remove the 0.6 V threshold of a transistor, I think you overcompensated in the other direction.  Consider increasing R7 to bring the threshold down to either 0.9 V or 0.4 V, but be aware that the closer the bias point is to 0.6 V, the more susceptible the circuit is to noise causing false output signals.

With a network of only V1, V2, R3, R5, and R7, you can calculate the instantaneous V2 voltage necessary to pull the node below 0.6 V and create an output transition.  This assumes the V2 output impedance is significantly lower than R3.  If not, add it to R3.

Whatever the transition level is, a drawback of this circuit is its relatively low gain.  There will be a small range of low input voltages where the transistor is conducting but not saturated.  With a single inverting stage and a grounded emitter, there is no way to add hysteresis to clean up low and slow input voltage changes.  If this turns out to be a problem, your solutions are either a second transistor stage or changing to a comparator IC.

ak