FPGA buffered and unbuffered clocks
FPGAs have pre-placed and pre-routed clock trees in order to deliver high fanout clocks to large parts of the FPGA with low skew.  This is a buffered clock, and it's the normal way of using a clock in a design.  These nets are driven by one of the clock buffer primitives (BUFG, BUFGMUX, BUFGCE, etc.).  There are a limited number of global buffered clocks, but there are also regional clocks that can be used for smaller synchronous blocks.

An unbuffered clock would be a clock that is routed through the fabric, the same way design nets are routed.  These nets have lots of delay and should not be used for clocks unless there is a good reason.  Using them for clocks will almost certainly lead to hold time violations that the tools may or may not be able to clean up.