Why does this high side MOSFET go pop?
You're at the limit of gate-source voltage (Vgs). You can reduce this by adding a series resistor between the NPN collector and the FET gate.
Make R37 10k, and add the second 10k. Then the gate will swing between +12V (Vgs = 0V) and +6V (Vgs = -6V). Then the FET should be happy.
Try it (simulate it here):