Intel FPGA equivalents of Xilinx IBUFDS Primitives?
For differential inputs it is sufficient to create a mapping for the port to the positive pin of the pair, specifying a differential I/O standard. This automatically creates a second mapping for the negative pin, and the I/O buffer IP is inferred from that during place&amp;route by pattern matching.

You can make that explicit if you like, but the result is identical.