length matching impact in ADC chips
From your previous question, you are using a sampling rate of 125 MSps i.e. data is presented at the output every 8 ns. If the data were oscillating between 1 and 0 it represents a square wave of frequency of 62.5 MHz. For a reasonable rule of thumb I'd be interested in making sure that the 7th harmonic of that square wave (437.5 MHz) were passed to the FPGA reasonably unadulterated.

This means that the total track length should be no more than (here comes another rule of thumb) one-tenth the wavelength of 437.5 MHz. Wavelength of 437.5 MHz is 0.685m so max track length (without needing terminations) is about 70mm.

Now to your real question; can you see from the above rule of thumbs that providing you clock the data into the FPGA at somewhere near the middle of each symbol you are going to get a decent result. This means that track length variations of up to a few millimetres are not going to affect things very much at all. Clearly you do your best to equalize lengths but to no-better than (say) 5mm.

If you are using a much higher data rate then do the calculations based on above.