SPI SS line gets raised to ~3.7V on custom PCB
Hard to tell a lot without the schematic that you used to drive the net list into the layout package. You did use a schematic to derive the net list did you not??

Things that are obvious problems.


Distributing the 5V rail around the board on an 8 mil trace is not good. Your prototype has a lot more copper than this and a bus bar in the plug board.
No bulk filter capacitors on the 5V to GND busses.
No bypass capacitors for the two port expander chips. 
Ground plane stitches using 8 mil traces.


You should be doing some debug of this with an oscilloscope. Try to see if you have serious sagging of the 5V bus due to the overly small trace size used without any capacitance to hold it up.