How to represent Negative real numbers in Fixed Point representation
As Entepreneur tries to say in his comment (at least think that's what he means), and as I read the code, they use sign-magnitude, not 2s-complement. 

2s-complement addition doesn't have to distinguish between positive and negative numbers (thats one of the big things in favour of 2s-complement).

I don't see what scaling factor is used, so I can't say how to represent - 1.5, but you seem to know how to represnet 1.5, so just flip the sign bit of that.



response to comment




  Sign Bit =0, All integer part bits are 1, and all fractional part bits are 0, when I add -1.5 to 0.5.(-1.5 is represented as suggested by Wouter. Also now, i have added Testbench of module, you can simulate it on your PC.


I'm no expert in this language (VHDL? Verilog?), but that is what this code should produce, specifically due to line 

res[N-2:0] = a[N-2:0] - b[N-2:0];


This generates an underflow (because |b| > |a|). I think that section should be

else if(a[N-1] == 0 &amp;&amp; b[N-1] == 1) begin

   if(a[N-2:0] &gt; b[N-2:0]){
       // |a| &gt; |b]
       res[N-1] = 1;
       res[N-2:0] = a[N-2:0] - b[N-2:0];

   } else {
       // |b| &gt;= |a]
       res[N-1] = 0;
       res[N-2:0] = b[N-2:0] - a[N-2:0];
   } 


(And you might want to check the last section.)