Running functions on FPGA on startup
Yes, this is possible.  When the configuration is loaded onto the FPGA, all of the registers are initialized to initial values.  In verilog, these can be specified when the reg is defined or in an initial block.  All you need to do is have a register, say 'initialized', with initial value zero.  First clock edge where it is clear, you run your init routine and then set the initialized register when it's done.  The same can be done with a state machine that starts in the 'reset' state and ends up in an 'idle' or 'init complete' state.