Output capacitance effect on stability of DC/DC Buck Converter?
It depends on many factors. The load (ohmic or others), the state variables, the operation mode (CCM/DCM) and others. After you decide these factors you can formulate the state matrices (A,B,C,D).

Following is a simple Matlab code may help you studying any converter poles position with different capacitor values. The state formulation is taken from this paper. The capacitor varies between \$5 \mu F\$ and \$50 \mu F\$ with step change of \$5 \mu F\$.

L=1e-3;  
R=10;    
c=5e-6;   
d=0.5;
B=[d/L;0];
C=[1 0;0 1];
D=[0;0];
hold on
for i=1:10
    A=[0 -1/L;1/c -1/(R*c)];  
    sys=idss(A,B,C,D);
    pzmap(sys);
    c=c+5e-6;
end


And the result for this particular case,



So for this particular formulation, the increment of capacitor drag the poles of the system to the right hand side of the poles map.