T-trigger: minimum transistor count
Most people think of this in two layers of abstraction, the logic gate layer and the transistor layer.
To minimize total transistor count, you need to (a) minimize the number of logic gates, and (b) minimize the number of transistors per gate.

You might get some ideas for (a) at Wikipedia: flip-flop.

For (b), my understanding is that resistor–transistor logic and integrated injection logic and diode-transistor logic uses fewer components per logic gate than other logic families.
In order of number of components:


You can make a 4-input NOR gate out
of 4 n-channel FETs and a single
resistor (5 components) with one
style of RTL, which requires 2 power
supply rails.
You can make a 4-input NOR gate out
of 6 carefully-chosen resistors and a single
transistor (7 components) with another
style of RTL ("threshold logic"), but
it requires 3 power supply rails.
You can make a 4-input NOR gate out
of 6 diodes, 3 resistors, and a
single transistor (10 components)
with one style of DTL, which requires
2 power supply rails.


Have you seen "The Transistor Clock"?
It's on Youtube and Make Magazine and the transistor clock web site.

p.s.: Does anyone know what happened to the MT15 CPU, built out of individual discrete transistors?