Phase Frequency Detector without dead zone
The delay does not eliminate the deadzone, and it does not eliminate metastability. However, it does make the circuit a lot less prone to their effects.

The problem comes about because the PFD is trying to align the logic edges, one from each channel. A logic gate will only have a constant propagation delay when it's starting from a settled state. As Div and Ref jitter with respect to each other, sometimes Div comes first, so the Ref signal propagates through a network that has already been disturbed by Div, sometimes Ref comes first, and Div has not yet disturbed the network, settled from the previous clock edge. This means that the propagation delay of each signal is data dependent, which introduces a lot of non-linearity in the transfer function of the PFD.

To add insult to injury, without the delay gates, as soon as the second edge comes along, a third signal is generated internally immediately to clear both latches.

The delay gates delay this third clear signal to let the latches settle somewhat before being cleared, which improves the non-linearity on the back edge of the pulses.

Unfortunately, this does nothing to fix the nonlinearity on the front edge, which means this type of PFD is not very good in most loops, and unusable in fractional N loops. However, it's simple, and integrates well with charge PLLs, so gets used a lot.