Effect of parasitic capacitance on an ideal signal?
This is an example of what happens, not intended to be overly realistic but to simply provide a visual.  Actual effects can vary quite a bit depending on the circuit and where the parasitic capacitance is as well as how its interacting with other components.  

In short this is a heavily simplified example for illustration purposes only.

Test Setup:



A 1us duration 1V square pulse with 1ns rise and fall time is generated, i've added 5 ohm of output impedance to the source and the values of R3 and L1 should be ballpark reasonable for a 5cm PCB trace.  C1 is representative of parasitic capacitance on the trace / from the receiving end.  Load was randomly chosen to be 1k ohm.

Then we do a transient analysis (time) from 0 to 3us and check the response with 5 values of C1 from 10pF to 100nF.  Ultimately these values are high for this given situation but it will more easily let you see the effects.



And here is the response at Vout.  The most square of the bunch is with C1 = 10pF and the most rounded C1 = 100nF.  You can also see the ringing caused by the interaction of the parasitic inductance (L1).

In the general case additional parasitic capacitance creates a low pass filter when combined with the resistances present.  

This causes the signal's rise and fall times to becomes longer as C1 takes longer to charge and discharge.  

In reality changes in parasitic capacitance can have a number of different effects depending on their interaction with inductances and other factors.

Here is another example of what can happen, same test setup just zoomed in on the rising edge and showing C1 = 10pF and C1 = 50pF.  While the rise time is longer with 50pF the real issue is the massive increase in ringing caused by the interaction with L1.