Why is the cache size identification register on ARM CPUs accessible from privileged modes only?
It is to support the abstraction of user privilege level tasks from the hardware they are running on.

An Operating System can run at a higher privilege level and access the cache size data along with other data about the hardware it is running on. It is the responsibility of such an OS to deal with the hardware and abstract it from the user-level programs.

As far as possible, User-level tasks/processes should not be aware of the CPU they are running on. This prevents the writing of user-mode software that is 'tuned' to the particular hardware it is on. Such software may then not run correctly on a different CPU, reducing re-use and portability. Details such as the cache size are below the interest level of many programs.

The OS usually allows user task/processes to obtain hardware data that the OS/system designers think relevant or useful through the API (function calls to the OS).