Difference between reading data from fifo and the register
It does break the timing path the same way a register does (presuming the FIFO is proerly designed), but you also have to take the setup and hold times of the FIFO itself into consideration.  Usually the setup, hold, and clock-to-output times of standard flip-flops are much better than for the block RAM modules usually used to build FIFOs.  This means that you may still have timing issues if, say, the clock-to-output delay of the block RAM in the FIFO is large.  You may still need to add flip-flops to the input and/or output of the FIFO module to improve the timing performance.