Is this switching power controller compromise wise?
I started this as a comment but the diagram was needed and you asked for critique as part of the answer


Place a ban on Olin coming within 10 miles of your diagram or he will kill you/it. 
Your circuit diagram has much unnecessary non-functional mess on it that makes it much harder to read than is necessary. There are little marks and annotations everywhere that have no meaning to most readers and no place on a diagram that is meant for others to inspect for circuit design analysis purposes. 


Consider this extract. Most messy stuff is marked. R25 value is very hard to read/ Large circles at component ends are very detrimental to appearance. Dot where vertical line from C3 meets grounds is OK and others should be like that or disabled for presentation purpises. It is fine for a drawing to look like this when you are working with it as long as it is not allowed to escape from captivity.





Depletion mode FETs have their place but it is very uncommon to need them and you should try hard not to do so. They are relatively old tech in most cases and have poor specs (as you found). As you note, a P Channel FET will do what you want about as well in most cases and biasing an N Channel on at all times as its default setting via a whisper of gate drive is acceptable if needed. 

A boost converter may never have Vin > Vout + 1 diode drop unless you are happy for Vin to flow to Vout via the output diode. You may be.

If you rely on a processor to terminate a LiPo charge cycle, when the uC crashes the battery will too in due course. 

Using a regulator's inbuilt current limit as a max chg regulator for a LiPo is OK only if allowable max I is >> Ireg max as reg max I out varies widely.
 1A charge - what size cells? 

More can be said.
 Olin may choose to say some of it. 
 Flame suits on :-).