SPI: Can MOSI and MISO line be shorted for data verification
While you may conduct such a test barring anything else attempting to drive MISO in conflict, and an observed failure could be meaningful, success in such a loopback test is of limited meaning.

Even aside from analog issues, an SPI interface is fundamentally stateful logic.  For the slave to produce bits in response to the master clock, one of two things must happen:


The slave receives the master clock after propagation and analog delays, and directly uses a buffered version of this to clock a data register which replies to the master after internal, analog, and propagation delays.
The slave samples the master clock with a faster, internal clock, and uses that to enable an internally clocked data register which replies.  Thus in addition to the delays above, there is a sampling jitter and possibly one or more internal clock periods of state advancement needed to generate a reply.  This is particularly common for MCUs operating as SPI slaves.


Either of the above could at a high clock rate be sufficient enough to cause reply data to arrive after the clock edge on which the master will sample it, or insufficiently in advance of it to satisfy a setup time requirement.