generating 40 MHz clock from 50 MHz in VHDL
It depends on the capabilities of your specific FPGA, but for Xilinx parts at least, you can use an MMCM or PLL to multiply the clock up, then divide it back down. For example, you might multiply by 20 then divide by 25. Xilinx coregen can generate paramaters for an MMCM or PLL that match the VCO bandwidth capabilities if you give it your input clock speed and desired output speed. If you're using an Altera (or other) brand of FPGA, they will  have some kind of similar clock manipulation unit, but I don't know what they are called.