Wired AND, OR gates and compatibility with TTL/CMOS fan-out?
I use just 1 kΩ normally. But I am wondering about contention by current flowing back into the inputs.

You need to look at the datasheets for the gates whose inputs you are driving. For example,
a typical 74LS04 datasheet specifies 20 uA input current when high (\$V_I = 2.7\ {\rm V}\$) and -0.4 mA input current when low (\$V_I = 0.4\ {\rm V}\$).
So for a pull-up holding up a single LS family load, assuming a minimum supply voltage (4.5 V), the maximum resistor value \$\frac{4.5-2.7}{20\times10^{-6}}= 90\ {\rm k\Omega}\$.
For a pull down you need \$\frac{0.4}{0.4\times10^{-3}}= 1\ {\rm k\Omega}\$ or lower (actually a fair amount lower is better since you can't count on the driving gate to pull absolutely all the way to 0 V). Once you've done a couple calculations, though, you'll probably find the results are re-usable for similar combinations of gates in the same family.
For a different logic family, or for multiple gates loading the circuit, you will need to calculate new values based on the total leakage current into the gates.

The question is if G4's input is not by accident pulled high by this diode? Or is there a magic R1 value that might prevent this from happening?

No. When G1's output pulls low, it pulls G4's input low, regardless of R1 (assuming R1 isn't so low that G1 can't provide enough current to pull it low). When G1's output is high, the diode is reverse biased and so R1 is irrelevant to the voltage at G4's input.

But are there common values considered safe for 74LS* and 74HC* respectively?

Many people do sloppy designs. If you want to get it right, you should review the datasheets of the gates you're actually using and determine the appropriate resistor values.

I suppose the bigger the fan-out of the upstream outputs, the less it will matter.

The bigger the fan-out of your wired gate, the lower your pull-up/down values will have to be.