High side MOSFET problem
You have bumped into a very common problem. The NMOS needs a certain Vgs and and since your gate is at VCC the source must be at a much lower voltage. To have a very low drop across the NMOS (low Vds) you must "lift" the gate voltage. For example to VCC + 5 V as shown in the circuit on the left:






simulate this circuit &ndash; Schematic created using CircuitLab

An alternative that does not need an extra VCC + 5 V is to use a PMOS, see the circuit on the right. Do note that in the right PMOS circuit the PMOS is on when the NPN is off, then the input signal is low. This is inverted behavior from the NMOS circuit on the left.

You could also "flip" the PMOS circuit upside down and use an NMOS. Then the load would be between VCC and the NMOS drain meaning the circuit and the load do not share ground but they share VCC.

But the simplest solution is a single NMOS:







simulate this circuit