For gates of same drivestrength, what does gate delay depend on and how?
Given two gates that are physically identical, the gate delay (as measured from 50% of input to 50% of output) can vary due to:


Input rise/fall time and shape
Input '0' and '1' levels
Capacitive load on the output pin
Resistive load on the output
Output transmission line effects
Local power supply voltage
Local transistor temperature
Radiation exposure (gamma, neutron, x-ray,...)
Long-term electrical degradation effects
Other stuff I haven't thought of


Answering "and how" is more difficult and is dependent on the particular transistor parameters and operating conditions, which are not specified.