Data bus between uC and SRAM: what happens when both are writing concurrently?
Yes, there may be physical damage. The longer the situation persists, the more the chance for damage. In case this is a problem you foresee happening often in your setup, you should probably work out a better scheme, or at the very least include a series resistor in each of the data lines. The resistor should be chosen such that in the worst case (both sides driving to opposite logic), the current through the resistor should be less than the current drive capability of the IC with the lower current drive capability. Note that in doing so, you will most definitely sacrifice in the speed the data bus is capable of operating at without the series resistance.