How to use LFSR to generate random numbers as per this Xilinx application note?
That is just an example how to parallelize 1-bit wide and 32-bit deep shift register into an implementation that suits better for programmable logic devices, in this case 2-bit wide and 16-bit deep as an example, and then extends it to many bits wide and many bits deep register.

For 12-bit shift register, there's 144 different tap configurations to achieve a maximal length output, and for 16-bit shift register, there's 2048 different tap configurations to achieve a maximal length output. Just select a configuration from a list, the Xilinx appnote has examples for which taps to use. Each configuration of taps generates a different sequence. However, 12-bit and 16-bit configurations are not that widely used, as they require four feedback taps. 11-bit, 15-bit and 17-bit registers only need two taps for feedback.

Of course, it's exactly the same code as calculating a CRC, except you are feeding no data in and let the shift register feed itself back. It seems that the XNOR configuration has exact same taps as the usual Galois configuration, where you just XOR with the polynomial. A 32-bit integer is a 32-bit shift register, so even if you use code for CRC32 algorithm, you will get a maximal length pseudorandom bitstream with 2^32-1 bits. As long as the shift register is initialized to something that is non-zero.


Don't think about the RAM blocks, unless you must implement this on a PLD of some sort.