VHDL IF statement not behaving as expected
In VHDL (and in Verilog, for that matter), an if statement can only appear within a process (initial or always block in Verilog).

Outside of a process, you must use the with ... select like you did before, or the when ... else syntax.

sum &lt;= &lt;expression alpha&gt; when &lt;boolean expression&gt;
  else &lt;expression beta&gt;;