Timing Constraints for Forwarded Generated Center-Sampled Clocks?
We want to be able to set the output delay of this forwarded
  clock/data so we can specify the setup and hold times of the ADC.


From the above explanation, You need generating delay on the data and clock lines,
I have two solutions for this problem.

1) using
Input Delay Resources(IDELAY) or ODELAY
https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf 

in high-speed design, some delays in PCB compensated with delay buffers.(these are have some tab of delays)

2) the second solution is synchronizing FPGA clock with feedback of ADC clock(it generate in PLL) I think, it's not easy and helpful for your case!

Edited:

I think in FPGA you should first consider which circuit you need, then tell the compiler to generate that. the Xilinx said "logical path that requires more than one clock cycle for the data to stabilize at the endpoint. If the control circuitry of the path start point and end point allows it, Xilinx recommends that you use the Multicycle Path".

Now in your example where you have two signal from FPGA side to ADC, ( you don't say low-power requirement, the multi-cycle help this goal) the Xilinx said "data to stabilize" because this may generate metastability. with clock and data pin from FPGA to ADC then the delay between clock edge and stable data has two cases, the first bigger than one cycle of the clock or less than, for the latter case IDELAY is ok but if you have bigger than one cycle delay( where you may concern about it) you compensate your delay, by setting a data in last clock cycle or two clock or higher, then the sub-clock delay compensate with(IDELAY). 

I think your case does not need "set_multicycle_path". If you want low power then you may concern about "Multicycles in Single Clock Domain". If you have a pin receives a signal from ADC side, when the ADC not stable less than clock cycle you should try "Multicycles in Single Clock Domain" for metastability reason.