how do I implement a start timer in a digital circuit
As long as you can ensure that the trigger signal is high for at least one full clock cycle, you can do something as simple as this:



circuit built with www.falstad.com

The trigger doesn't need to be synchronous with the clock, but it does need to be held high for at least a full clock cycle. Otherwise, the trigger may not be registered by the flip-flop (DFF).

You can also add a reset to the DFF if desired, to disable the enable and allow the circuit to be retrigger.

If you're concerned about metastability, just add a second DFF stage.