Trying to find out the voltage threshold for input of a GPIO pin in an FPGA development board
Cyclone V pins are configurable for numerous different standards. Look into Cyclone V Device Handbook Vol.1 in chapter 5. Specifially, JEDEC Standard JESD8-5 (that is "2.5V low voltage CMOS") is supported.

From the De1-SOC-Schematics (download CD.zip from Terasic) you can see, that all banks have \$VCC_{IO}=3.3V\$ (except the HPS-banks which use \$1.5V\$). Pins on these banks will correctly detect 2.5V CMOS input (see "I/O Standards Voltage Levels"), but they will not be able to generate 2.5V output.

In general, Alteras Device Handbook (at least Vol.1) is a recommended read, if you want to put your board to use.