Will using a CMOS OCXO as extrnal oscillator for the XTAL input for LPC1114FN28 work?
According to Page 97 of the Datasheet:


  The input voltage to the on-chip oscillators is limited to 1.8 V. If
  the oscillator is driven by a clock in slave mode, it is recommended
  that the input be coupled through a capacitor with Ci = 100 pF. To
  limit the input voltage to the specified range, choose an additional
  capacitor to ground Cg which attenuates the input voltage by a factor
  Ci/(Ci + Cg). 
  
  In slave mode, a minimum of 200 mV (RMS) is needed. In
  slave mode the input clock signal should be coupled by means of a
  capacitor of 100 pF (Figure 49), with an amplitude between 200 mV
  (RMS) and 1000 mV (RMS). This corresponds to a square wave signal with
  a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this
  configuration can be left unconnected.


This basically answers your question (1). You can use an external clock to drive the XTALIN pin as long as you limit the voltage swing to between 200mV and 1000mV RMS. The (NXP) recommend doing this using two capacitors to AC couple the clock and act as an attenuator. See the diagram on page 97.

It also goes on to say you should leave XTALOUT unconnected - i.e. don't connect anything to it, not ground, not a resistor, nothing.



As for question (2), the job of a PLL is to produce a clock which is at a higher (or lower) frequency to the reference clock, but one which is phase locked to it. In other words if you were to have a x2 PLL, you would have an output clock of exactly 2x the input clock assuming the PLL has locked.

It is possible you will get some drift in the clock, but this will be limited by the PLL as to how far it goes before being corrected. The maximum drift determines how much jitter you get on the clock - something which should be specified in the datasheet somewhere (haven't looked) doesn't appear to be specified in the datasheet though. The jitter is basically a small variation of frequency as the rising and falling edges of the clock are not at exactly the right moment due to the PLL bandwidth and drift correction.