Do I need to use thermals on vias for reliability?
Reliability is a somewhat slippery slope, once you start chasing after after it, sort of like the 'in the interests of national security' in contemporary media plotlines. It helps to know what you're protecting against - are you going to vibrate it? Will it experience mechanical shock? Thermal shock? Thermal cycling? Environmental effects like the weather? Direct exposure to sunlight?

Different kinds of risk exposure call for different methods of risk mitigation. All the while, you also have to keep in mind the requirements for performance. For instance, tell an RF designer he has to do that and he'll laugh you out the room - they use vias to build walls to copper. They won't let you break the plane for it, because it defeats the purpose.

However, in a general setting, thermal vias are definitely mechanically forgiving. When in doubt, take the safer route as long as it isn't more expensive. Cost could be as money, performance, or design time. 

With low end fabrication vendors, it also gives you a cleaner way to target the drills if it's done by hand and eye(not a problem in the first world as much). 

And as for not soldering the vias, I had to use very high reliability fabrication protocols in the past that involve filling every via with solder. Someone literally sits down with a microscope and pours copper into every single via, atleast those big enough for solder to go through, with special dispensation for the smaller ones. Those are used in a very high vibration, extended thermal cycling sort of environment with many other headaches. I don't know how widepread the practice is in regular electronics. We certainly dont do it for lab instrumentation.