Modeling FPGA logic element responses
A Logic Element (LE) is made up of a number of gates. Exactly how long it takes to propagate data from the inputs to the outputs depends just on the combination of gates that the signals pass through, and that depends on how the LE is programmed.

The main controlling factor of the LE is the Look-up Table (LUT).  This has 4 data inputs and 4 data outputs, and is basically a little block of static RAM (16 nibbles).  The RAM is loaded when the device is programmed by the configuration chip.  The incoming data signals are the address lines of the SRAM, and the output data signals are the data bus of the SRAM.  A change of address (incoming data) yields a pre-set change of data value (outgoing data).

For modelling the timing you would really need to know which gates are in use for which values of the LUT and factor the propagation of those into your calculation.  For the LUT itself, it's just SRAM, so you can just model that as a small piece of SRAM.

The actual layout of a LE in different modes of operation can be found in the document Logic Elements and Logic Array Blocks in Cyclone IV Devices.