simplify external I/O memory access with small micro
As I read the Cypress 62256 datasheet, the chip does not have an internal address latch - it expects the address bus to be stable, with the full address, during a read or write operation.  Look at the Switching Wafeforms drawing on page 8 and 9 of the datasheet.

To comply with this, you will have to write both bytes of the address into separate latches which drive the address bus.

To read the RAM, you write both byes of the address into the latches, then set CE and OE low, then read the data, finally set OE and CE high. ( think CE and OE can be toggled together.)