3 input XNOR gate operation
The misunderstanding is that, given XOR as a logic gate, XNOR is defined as being always its negation. 

Having defined your XOR-3 as an odd parity checker (by accepting the minterm \$xyz\$ - otherwise it would be a one hot checker), the correct interpretation of a XNOR-3 would then be an even parity checker (as pointed by Bradman175). This simply means that the expression for your algebraic XNOR-3 is not correct in this context. 

In other words, \$x \odot y \odot z \ne \text{XNOR-3}\$.

Let's observe an implementation through logic gates.

A three way XOR gate can be implemented with a XOR-2 itself XORed with the remaining input, and remember that any XNOR has then to be rendered as a XOR in series with a NOT gate. 
Therefore, a XNOR-3 implementation would be:







simulate this circuit &ndash; Schematic created using CircuitLab

This yields a truth table coherent with the functionality expected above (1 when there are an even amount of input at 1). This also shows that a triple XNOR is algebraically rendered as

$$
\text{XNOR-3} \buildrel def\over = \text{NOT} (\text{XOR-3}) = \overline{(x \oplus y \oplus z)} = \overline{(xyz + \overline{x}\overline{y}z + \overline{x}y\overline{z} + x\overline{y}\overline{z})}
$$

by carefully expounding all terms, you eventually get to the even parity checker expression which is

$$
\text{XNOR-3} = \overline{x}\overline{y}\overline{z} + \overline{x}yz + xy\overline{z} + x\overline{y}z
$$

It follows that:
 $$\text{XNOR-3} =(x \oplus y)\odot z \ne x \odot y \odot z$$
as mentioned in the beginning.