Make FTDI 2232D do SPI mode 1 properly? Data seems 1/2 clock cycle off
I got a response from FTDI technical support:


  The FT2232D and FT2xxH MPSSE devices only support SPI Modes 0 and 2.  Some customers have tried using 3 phase clocking, but have not been successful.
  
  We have a new USB to SPI/I2C device – FT4222H.   This chip supports all SPI CPOL/CPHA  (clock polarity/clock phase) modes.
  
  Note:   “Quad SPI” in the FT4222H datasheet refers to a 4 bit wide SPI interface option, not 4 independent SPI channels.


That appears to definitively answer the question of how to do this.

We are looking at possible workarounds such as inverting the clock signal in hardware.  I'll update this answer when we determine feasibility.



Edit:  We got it working.  It required two areas of modifications compared to a straightforward implementation.

Added a hardware inverter to the SPI_CLK signal output.  This allows the clock and data to transition 180&deg; out-of-phase preventing sampling errors.

The software is changed with adding slightly odd but careful ordering of chip select and clock transitions.  At the end of a message, it does produce a tiny clock glitch, but none of our devices (Saleae analyzer and TI A2D converters) care.

The sequence to enable chip select is:

1.  SPI_CK = 1  &amp;&amp;  SPI_CS = 1
2.  SPI_CK = 1  &amp;&amp;  SPI_CS = 0
3.  SPI_CK = 0  &amp;&amp;  SPI_CS = 0


To disable chip select:

1.  SPI_CK = 1  &amp;&amp; SPI_CS = 1   # causes slight glitch


The glitch is an extra (but short) clock pulse produced as the MPSSE engine finishes clocking out the data where it concludes by setting SPI_CK zero but since we hardware invert it, it appears as a one.  The disable CS step then corrects this, ready for the next CS enable sequence (when it is eventually time).