hexadecimal seven segment display verilog
You need to assign the output value to some wire or register and then connect that net to an output pin.

Typical code (not tested) is

wire [3:0] num;
reg  [6:0] out;
always @num begin
    case (num):
        4'b0000 : out &lt;= 1111110;
        4'b0001 : out &lt;= 0110000;
        4'b0010 : out &lt;= 1101101;
        4'b0011 : out &lt;= 1111001;
        // ...
     endcase
end


Declaring out as a reg type doesn't actually make it into a register or generate a flip-flop. It just allows you to assign to out inside an always block.