adjust clock frequency using Timing Error Avoidance Technique
I take it that the delay line in the upper box labeled "tracking logic and safety margin delay" somehow models the delay in the "combinational logic" block in the lower box.

At equilibrium, the output of the "timing checker" flip-flop will be a 50-50 mix of ones and zeros. BTW, this should be at least two flip-flops, since the D input needs to be treated as an asynchronous input &mdash; indeed, the operation of the circuit is to drive it as close to metastable operation as possible!

So, the output of the XOR gate will be '1' if the clock period is a little too short, and it will be '0' if it is too long. This means that if it is '1', you need to decrease the VCO frequency, and if it is '0', you need to increase it.

It sounds like you're on the right track, but just make sure that the up/down behavior of the counter driving the DAC is correct.

Actually, the whole counter+DAC thing is probably overkill anyway. If you just took the inverted output of the timing checker flip-flop and sent it through a simple R-C low-pass filter and then to the VCO, it would probably work just as well!