Why the mismatch between frontend and backend width?
When I originally asked the question I was interested in learning how this mismatch could affect the performance, meaning: will the backend would be sitting idle waiting for decoded instructions? Of course not, but what was the explanation for that?

Apparently it doesn't happen because:


ARM instructions are very easy to decode (fixed-length) [1]
Decoded instructions take variable amount of time to execute in the backend, as pointed out by @pjc50.


[1] http://www.arm.com/products/processors/instruction-set-architectures/index.php?tab=A32+(ARM)