Generating error condition randomly inside a digital design inside FPGA
There are other sources of noise inside the FPGA that could exploit and even combine with your other sources, provided that you can modify the design.
There are methods of using the jitter of the FPGA's ring oscillators or using High Fanout Nets to accomplish true randomness. This paper discusses the implementation a TRNG of high fanout nets. Full disclosure, I have not implemented this myself, but I have seen a similar implementation.
Alternatively, I have found this pseudo random number generator that it somewhere in between LFSRs and a TRNG. Its stated purpose is the following:

The PRNGs in this library are useful to generate noise in digital
signal processing and to generate random numbers for monte-carlo
simulations or for games.