SPI Bus Termination Issue
It's difficult to answer this without all the details, but here is a generic look at the problem which I believe may also be the more useful type of answer for this site.

Multi-node-nets should always be simulated. They are so difficult to predict. And it took about 3 minutes to see that your design was maybe not optimal.

Here is the simulation setup for the clock from the master to all the slave devices (values are just rough estimates, as would be the case if you did this before building anything):



And the resulting simulation plot (we ignore what is what, units etc. as it obviously is not worth building):



The first idea that comes to mind is a daisy chain of all the inputs and a simple parallel termination. A fly-by scheme if you want. This looks like this in the simulation setup:



And the result plot looks a lot nicer:



If you can live with the increased power consumption of the thevenin termination and the reduced voltage swing on the clock inputs of the various devices and... (only you know the actual constraints)... then some variation of this may actually be worth building.

There are other solutions that would work, but the key is to understand that multi-node nets are not easy to predict. The 5 minutes of simulation here before you build something can save a lot of time later. Unfortunately this type of simulators do not come cheap.

I am using Cadence SigXplorer here. The usual disclaimer apply: I do teach classes in signal integrity and often have Cadence or Mentor sponsor software licenses for those classes.