register without clk
You "can" do it but it would be highly discouraged. The correct thing to do is to learn how to design your logic so that everything (or at least large separate partitions of the logic) run on a common clock rail. Then learn to use clock enables to allow the "load", "clear", "increment", and "shift" type operations to happen on the next clock edge. Design these clock enable terms to be one clock wide pulses. 

There is no real downside to this type design because virtually all FPGAs that you would target your design to have global clock networks that distribute the clocks to all the logic cell flip-flops that is separate from the allocatable logic routine resources. 

The up side to this type design is that it greatly simplifies the analysis and meeting the setup and hold timing. If timing does get tight it is much much easier to convert fully clocked designs to use either a slower clock to meet timing or to pipeline critical logic sections to split delay paths across two clocks.

Do it from the outset and it will be something that will be valuable experience for every future design that you would do.