In VHDL what is a data operator type "variable" when it is translated to circuit?
Variables may or may not represent physical wires.
Variable assignments are order dependent
Variable assignment under a clocked process may or may not be translated into registers.
I also have examples.

CASE 1 : variable temp
process (clk)
If (clk’event and clk = ‘1’)  then 
   temp  := a and b; 
   y &lt;= c and temp;
end if; 
end process;    

CASE 2 : variable temp
process (clk)
If (clk’event and clk = ‘1’) then 
    y &lt;= c and temp;
    temp  := a and b; 
end if;
end process;

both cases create different hardware.