Does an ALU always do add and sub, but only returns one of the results?
Look up the age of the 8085. It dates from the era when every part of a circuit was hand optimised, and hand layout with tape and razor blade was still common (though likely Intel was using CAD systems). So it would have been designed to aggressively minimize the number of gates used. And as Tom says, you can add and subtract using the same circuit with a little care - so I think that gives you your answer.

From GBulmer's comment:


  Can you see a way to produce multiple results (for example add and
  subtract) simultaneously, and select the correct answer with the fewer
  gates (or transistors) than logic producing only one result?


Personally, I can't. If you produce both answers, you need additional logic in the form of multiplexers to select the one you want.

Now I'm not going to run the experiment, but I suspect that if you write an ALU in VHDL, which follows this approach, a modern synthesis tool will spend a very long time (several seconds) and optimise it down to something close to the hand-optimised version. 

To test this hypothesis, generate A+B, A-B, and a 2:1 multiplexer as separate modules, synthesise them separately and note resources. Then roll them up into a single design and re-run synthesis (you may need to enable optimisations, "optimise for area" and "flatten hierarchy"). The latter will be smaller : how close it is to a hand-minimised version I don't know : the challenge is set if anyone wants to add another answer!