How to create a design that uses specific % of DFF and LUT count in FPGA to measure power dissipation?
FPGA vendors have some Excel files to make a preliminary power analysis. They give a rough idea.
Here link to the following files:

Xilinx: https://www.xilinx.com/products/technology/power/xpe.html
Intel: https://www.intel.com/content/www/us/en/programmable/support/support-resources/operation-and-testing/power/pow-powerplay.html
Microsemi: https://www.microsemi.com/product-directory/design-resources/1748-power-calculator

FPGA power consumption has a static and a dynamic component.
About designs to test power:
One stupid design is a chain of inverters: Here you can fill LUTs and FFs and steer them on IOs. You need attributes so the not of the not of the not... is not optimized away by the synthesis tool. (ie DONT_TOUCH attribute described in the Xilinx Vivado Design Suite User Guide - UG901)
If want to include RAM and DSPs to the power estimation, generate a kind of stupid pseudo noise generator. The random bits stored in RAM blocks and their outputs filtered by a long   FIR using all FPGA multipliers.
This gives a VHDL design possible to port from one device to another but time spending to create the first code.
It is also good to know that some devices need a lot of PC memory to compile the design. (https://www.xilinx.com/products/design-tools/vivado/memory.html)