Implementation of Decoupling capacitor
Firstly look at the eval board gerbers and copy them, not always perfect but usually a reasonable guide to how to decouple such things.

Secondly those packages look huge, (0805? 0603? something like that), for at least the smallest values you really want 0402 or even 0201 to get the package parasitic inductance down low enough. 

How you ground the caps is REALLY going to matter, think LOTS of stitching vias. 

Were I doing a from scratch design I might bury the RF feedback lines on layer 3 done as stripline with a local ground pour on L4 and L2 (And LOTS of stitching), so I could put the caps on L1 right above the rf lines, but it makes board stackup very important so you would not be able to use the cheap PCB pooling services.