Reducing the memory address bus by adding banks
I'm going to assume that you're talking about parallel memory, and that when you say "use two banks instead of one" you are using two chips that have the same total memory, but each are half as large.

Here's the thing: you can't actually remove that address line from your CPU. It might not go directly to the memory chip, but if you remove it there is no way to distinguish between the two chips. The missing ingredient is the "chip select" function. Most memory chips will have a pin or set of pins that are used to basically tell that particular memory chip that the processor want to talk to only that chip.

Lets consider a simple example: 256 words of memory. This results in an 8-bit address bus. 


One chip with 256 words: then we are always using only one chip, and it has an 8-bit address. 
Two chips with 128 words each: Only one memory can be active at the same time, so we will be using the "chip select" pin. The MSB (Most Significant Bit) of the 8-bit address bus will go to the chip select pin on each chip, and the rest of the 7 bits will go to the 7-bit address bus on both chips.
Four chips with 64 words each: Only one memory can be active at the same time, so we will be using the "chip select" pin. Some memory chips have multiple chip select pins, but for this example we will assume there is only one. In order to generate the chip select signals for all four chips, we will need a 2-to-4 decoder (also known as a $n\mbox{ }to\mbox{ } 2^{n}$ decoder, row decoder, address decoder - all the same things). This decoder takes the first two MSB from the address bus, and determines which chip select signal should be active. The lower 6 bits of the address go to the 6-bit address bus of all 4 memory chips.




This is a really simple example, but it scales fine. This is basically the procedure for making multiple memory chips work together to increase the address space.