How is the signal assigned to a pin by default
For CPLDs:

When you run the Xilinx ISE design flow, reports are generated.
The report summary page, contains an item called Pin List.

I don't know how to distinguish located and unlocated pins in this
report.

Here is an example report with one LED output, driven by a T-FF.


(clickable)

For FPGAs:

When you run the Xilinx ISE design flow, reports are generated.
The report summary page, contains an item called Pinout Report.

Here you can see located (specified in UCF) and unlocated pins. An pin with a signal name, but not located is a pin, which was located by the mapper.


(clickable)

The map report contains also a section for I/O resources.

IO Utilization:
  Number of bonded IOBs:         22 out of     218   10%
    Number of LOCed IOBs:        22 out of      22  100%
    IOB Flip Flops:               6


What is what?
- bonded IOBs => all pins
- LOCed IOBs => pin specified in the *.ucf file
- IOB Flip Flops => I/O cells using the embedded flip flop