Packing register pairs on Lattice FPGA slice. How?
If you want an asynchronous reset, separated for each registers, it's probably impossible since both registers share a single LSR input.

If you are looking for synchronous operations only, as your code show, you could try some of the latches primitives form this library. That would make synthesis unambiguous and map directly to a hardware latch without extra logic or constraints.

Another options is to make a script that generate placement constraint files for you. I did for some timing circuit with microsemi's tools, it can be easy if you have repetitive structures. I had plenty of margin on resources so I'm not sure if that could work for you.