Capturing data at 500MHz
One solution is to use a demux to reduce the ADC sample rate, and take advantage of the large number of pins on the FPGA.

For example, the ADC could be clocked at 500 MHz, and the FPGA at a more reasonable 125 MHz. Then a 4:1 demux can be used - collecting 4 ADC samples for each tick of the FPGA. The bus becomes 4 times wider, so at each tick the FPGA needs to ingest 40 bits, not 10, but that's not difficult to deal with.

In my application, the 2Gsps ADC and 8:1 demux are sold as a pair, so its output becomes 88 bits at 250 Mbps. There's no other way to use the ADC. 

I assume you won't be sampling for very long, at that rate. The processing requirements will be determined by how many samples need to be used, and how quickly you need answers. For example, you could use 10GbE fibre to transport the data from your robot to a regular PC, for offline processing, no exotic hardware or software required.

Regular off the shelf wireless links only work to maybe 100Mbps, and only in ideal conditions, not found on a moving robot. Something will need to buffer the whole signal before you download it. DRAM on the FPGA? Embedded PC? Good luck!