Clock Phase Shift Not Working on FPGA
When there is a 90° phase shift between two 5MHz clocks, that means there is a 50ns skew between them.
If you divide those two clocks by 5000000 using two instances of the same counter structure, you'll get two 1Hz signals with 50ns skew between them (which is roughly 0° at 1Hz). I doubt you can see this with bare eyes.
So to me, this test gives you no indication about the actual skew between your two 5MHz clocks.
It could be far more interesting to forward the two 5MHz clocks on IOs (through ODDR blocks) and use a scope.