Reset pulse generated by UART break condition
Your original circuit is rather close to what you need. I have revamped it some using an LTSpice simulation. The one thing different from what you said you wanted was that the RESET_N pulse lasts as long as till the end of the UART break signal. That should not be a problem since your external system can adjust timing and COMMs cannot take place during the break period anyway.

I recommend changing the output inverter to an N-FET so that you get a higher threshold than the NPN transistor that you used.

You will also have to work out some type of bias pullup resistor for the TXD/RXD line so that when the external UART source is not connected that the transistor will stay ON. I did not show it since you did not describe the internal supply your circuit. 

In the end it will probably be advantageous to power the circuit from your internal supply because when the external 5V is removed it would force the reset circuit to output a low. As a minimum have the drain pullup on the output FET tie off to the internal supply.