What is holding the SS pin high in SPI master mode on AVRs?
The SS line ( of this devices or others ) is completely ignored in the example since it is supposed to controlled by the software ( you have to do it ) as it states that in page 163 of that datasheet:


  When configured as a Master, the SPI interface has no automatic control of the SS
   line. This
  must be handled by user software before communication can start. 
  W
  hen this is do
  ne, writing a
  byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the 8 bits
  into the Slave.


I now this is about the other device SS but it implies that you should take care of this line on both sides ,So even in the sending part it is supposed to drive the SS of the slave low but it is not included

    void SPI_MasterTransmit(char cData)
{
    /* Start transmission */
    // set slave SS line to low is missing here
    SPDR = cData;

    /* Wait for transmission complete */
    while (!(SPSR &amp; (1&lt;&lt;SPIF)));
}