Is there some flag / pragma which can help me in detecting bogus variable names in a module definition?
Verilog by default will treat any undeclared variable as a single bit wire. Since IEEE Std 1364-2001 (aka Verilog-2001) you can override the default with the `define_nettype macro. By setting it to none all nets must be explicitly declared. This is a universal solution that works on all modern simulators; the base line is IEEE Std 1364-2001 compliance.

Add the line `default_nettype none to the top of the first file being compiled and the rule will apply to all files. If you want some modules to have explicitly declaration and others to allow implicit, then for all modules needing explicitly declaration have `default_nettype none above and `default_nettype wire below those modules.

You can get more details on default_nettype by reading IEEE Std 1364-2001 &sect; 19.2 `default_nettype or IEEE Std 1800-2012 &sect; 22.8 `default_nettype