Copper overlapping via and when to use thermal relief (Eagle PCB Design)
The problem I seem to encounter now is that from the polygon fill, the copper pour overlaps the via completely (but is shown in a light red color). Is this allowed or will it cover the hole?


No, it will not cover the hole. Assuming that you want to connect the 'via' with your polygon pour, you don't require to put anything on tRestrict.


  One other thing - is it okay if the ground plane on the bottom runs to the edges of the board (with no spacing)?


Well! you ideally should leave some space from the edges, how much space is your decision to make.