Xilinx ISE Synthesis taking too long
I finally solved my problem and I post my answer here for futur generations.

Consistently to the advice of Brian Drummond, I created a small testbench for each module of my system and I ran the synthesis as well as the post-synthesis simulation on each on of them. Everything was working fine, none of the synthesis were taking an excessive amount of time.

Subsequently, since my device contains a large number of loops, I have made the following modifications:
- removing some input/output pins by using serialisation instead
- configuring the IP cores to use DSP instead of the fabric

My design could finally synthesise after a large amount of time.

I hope this may help someone else