Problem compiling verilog
One possible cause: Synthesis is merging vga_g, vga_b, and vga_r into a single net, because they are all equivalent. Then the translate step can't put them in different locations, because there's only one net in the synthesis output. 

Solution 1. Explicitly instantiate your OBUFs.

 OBUF obuf_vga_g ( .I ( on ), .O ( vga_g ) ); 
 OBUF obuf_vga_b ( .I ( on ), .O ( vga_b ) ); 
 OBUF obuf_vga_r ( .I ( on ), .O ( vga_r ) ); 


This makes it explicit in your code that the output nets are buffered from the on signal and attached to output pins. Obviously the tool should already know these nets are connected to output pins because they're outputs of the top level module. Having to do this kind of thing is just one of the quirks of using a tool originally designed to describe logic for the different purpose of designing logic.

Solution 2. Use constraints to eliminate merging of duplicate logic.

Depending on which synthesis tool you use, there should be a constraint available that you can attach to your vga_b, etc, signals to prevent them being merged in the synthesis step. In Synplicity, I believe you would use syn_keep to prevent removing redundant combinatorial logic.

As Apalopohapa noted in a comment, you might also need to turn on a flag to enable Synthesis to automatically generate the OBUFs you need. This should default to 'on', but it doesn't hurt to double-check it.