I am trying to instantiate few modules to work in top level design, but even though there is no error but I am not getting proper output
The mistake I did was using same status signals for multiple instances. I sincerely thank @toolic for helping me out. The italicized signals in the code should have been distinct for each module, because of using same variables it caused contention.

module check(x, in2, err, start);//x and in2 are inputs for this module and //err is the output.Start is the signal given from testbench for starting this module
    parameter N = 32;// This is the bus width for all the variables.
    parameter es = 3;// This is the parameter required for calculating 
    input       [N-1:0]x;
    input   [N-1:0]in2;
    output  [N-1:0] err;
    wire        [N-1:0] x1;//These are nets declared for intermediate calculation
    wire        [N-1:0] x2;//Same as that of x1
    wire        [N-1:0] oru = {{(3){1'b0}},1'b1,{(N-4){1'b0}}};// This is "1" in //posit number format
    posit_mult #(.N(N),.es(es)) m1(x, in2, *start*, x1, *inf*, *zero*, *done*);//x1=x*in2, where the rest of them are status signals(1-bit)
    wire        [N-1:0] x1tmp = -x1;//To get 2's complement of x1
    posit_adder #(.N(N),.es(es)) a1(x1tmp, oru, *start*, x2, *inf*, *zero*, *done*);//x2=x1tmp+oru
    posit_mult #(.N(N),.es(es)) m2(x, x2, *start*, err, *inf*, *zero*, *done*);//err=x*x2
endmodule


This can be solved either by using distinct variables or by removing them(if they are not useful) as:

module check(x, in2, err, start);//x and in2 are inputs for this module and //err is the output.Start is the signal given from testbench for starting this module
    parameter N = 32;// This is the bus width for all the variables.
    parameter es = 3;// This is the parameter required for calculating 
    input       [N-1:0]x;
    input   [N-1:0]in2;
    output  [N-1:0] err;
    wire        [N-1:0] x1;//These are nets declared for intermediate calculation
    wire        [N-1:0] x2;//Same as that of x1
    wire        [N-1:0] oru = {{(3){1'b0}},1'b1,{(N-4){1'b0}}};// This is "1" in //posit number format
    posit_mult #(.N(N),.es(es)) m1(x, in2, , x1, , , );//x1=x*in2, where the rest of them are status signals(1-bit)
    wire        [N-1:0] x1tmp = -x1;//To get 2's complement of x1
    posit_adder #(.N(N),.es(es)) a1(x1tmp, oru, , x2, , , );//x2=x1tmp+oru
    posit_mult #(.N(N),.es(es)) m2(x, x2, , err, , , );//err=x*x2
endmodule