Analog/Linear PLL or DPLL or ADPLL?
FIRST, go for a type_1 PLL, where there can be frequency locking, but not phase locking. The VCO is the only integrator.
Have your &quot;phase detector&quot; be an Exclusive Or gate, and the Loop Filter (just an RC low pass filter) is NOT an integrator, thus phase_error is not accumulated and not nulled. False Locks will abound. You will learn.
NEXT go for a type_2 PLL analog, building your Phase_Frequency_Detector out of 2 FlipFlops and a NAND gate and (possibly) some variable delay in the 'reset' path.
This lets you examine the effect of sloppy on/off times in the Up/Down paths to your
--&gt; CHARGE PUMP.
One major step in Charge Pumps in stand_alone Synthesizer ICs was taken by National Semiconductor, the circuitry/design provided by a Portland Oregon design house in the 1990s.
That ChargePump was extremely simple (just one or two transistors) and injected very little extra phaseNoise of its own.
That IC Synthesizer (and the simple Charge Pump) had 18dB lower phase noise than the existing competition, allowing National Semi to take over the existing $50,000,000 market for such ICs. As cellphones came to require lower phase noise, the markets grew to $400,000,000 a year (massive profits in that, if you understand the methods of low_phase_noise circuit design).
Then, after implementing an Analog PLL, and characterizing its Phase Noise, including opamp contributions, and the PFD contributions, and the Charge Pump contributions, and your VDD trash affecting the propagation delays of all your logic gates, so you learn the various sources of phasenoise, then you are ready for  &quot;All Digital PLL&quot; design.
I recall reading (at ISSCC) the Texas Instruments description of their ADPLL. The phase_comparison occurred at 500,000,000 Hz, or every 2 nanoSeconds. For a 2GHz (or 5GHz) synthesizer.
When your phase_updating (VCO &quot;tuning&quot; or division_ratio selection) occurs every four cycles of the VCO, you have a game_changing system design.