Quartus FPGA migration issues
Looks like you might be using an input pin for the clock that isn't a clock capable pin.  Take a look at the datasheet and make sure you're using a valid clock pin.  This is one of the few things on an FPGA that you really have to watch out for specifically what pin you're using.  Other signals can basically be placed wherever it is most convenient, but clocks must be connected to pins capable of driving the clock networks and PLLs.  

Not sure about the second error, though.  See: http://quartushelp.altera.com/13.0/mergedProjects/msgs/msgs/efsac_fsac_too_many_non_global_control_signals_for_lcell_ff.htm .  Might be a clock routing issue if the clock is not going over the proper clock network.