In verilog is legal to implement a reset using assign?
As pointed out in comments, in your code rst is always 0, therefore it will never affect the value of detect. If you want the reset to happen, you should make rst an input to your module, and then set it high at some point in your test bench.
But you should also notice that this isn't really a reset behavior. Setting rst high will force the detect output of the module to go to zero, but as soon as rst goes low again detect will return to its previous value as stored in detect_aux. If this were a proper reset, we'd expect the counting to start anew from 0 after rst is released.