Is there a proper way to enable a digital counter?
[...] is there a practical reason to favour the second circuit over the first one?

Yes. The first approach is known as &quot;gating the clock&quot;, and one of the cardinal rules of robust synchronous logic design is to avoid this practice. There are many helpful answers and comments about this in the related topic What does it mean to &quot;gate the clock&quot;?  For example:

Not gating clocks is good advice. It can be done, with care and thorough understanding of the possible consequences. These include metastability when taking clocked signals into the gated clock domain and worse results from timing-driven synthesis/layout.
But there are nearly always other ways to achieve the same control over a circuit as gating the clock, without all such risks and penalties.

As these answers (and others) hint, a designer certainly can gate the clock, and some designers will do it for reasons of reducing power draw and the like. But unless there is a compelling reason otherwise, the preferred approach is to always keep the clock signal itself pristine. This is the easiest/simplest approach to get a solid, stable, robust design.