Is it necessary to have a finite state machine for every filter you write in VHDL?
Ultimately when writing HDL (whether VHDL or verilog) you have to remember that you are writing code as a way of desinging hardware.

Your synthisis tool will often give you tools that let your view what it has done with your code at different stages in the processing. In quartus for example you can find these under "tools -> netlist viewers". These (especially the "rtl viewer") can be very handy for getting a feel for how code turns into hardware.

Designing hardware is a game of tradeoffs. 

A state machine lets you reuse the same logic blocks for different things (or the same thing with different inputs, for example in a filter your state machine might use a single multiplier to multiply the input data item by all the different filter taps) but comes at the cost of throughput. The throughput is limited as the state machine has to work through different states for each data item.

A combinatorial design gives you results "immediately" but can create timing problems. When you write multiple processing steps in sequence in a process what happens in synthsis is that each of those steps becomes part of a chain of combinatorial logic with the final values of the variables being stored on in registers for use in the next iteration of the process.

A pipelined design can give high throughput and run at high clock speeds but typically requires the most logic and is the most mind bending to work with.