How can a high-voltage transistor be in such small packaging?
Hmm, it does seem tight.  The pin pitch is 2.3 mm, and the maximum pin width is .85 mm, leaving 1.45 mm minimum space between pins.  The transistor is specified for 1.4 kV C-E, which are on adjacent pins, so that's just about 1 kV/mm.  As I said, that seems tight, and you'd have to be careful in designing the PCB footprint to not make this worse.

Usually I make PCB pads a little wider than the pins, but in this case I wouldn't.  Even if you make the pads the same width as the pins, then any alignment error cuts into the spacing.

Overall, I'd prefer a larger package with more space between pins to get somewhat below 1 kV/mm.