Intuition for stability differences between PMOS and NMOS linear power supplies
with the NMOS, a +1 V step on the the input doesn't directly affect VGS, hence the source current is not directly affected

Yes

with the PMOS, a +1 V step on the the input directly affects VGS, hence the source current is directly affected (increased)

Yes

the NMOS provides a direct negative feedback for load changes (VGS increases with a reduction in the load resistance), which is not present with the PMOS configuration

Er, I'm not sure what is meant by &quot;direct&quot;, here. Perhaps this. In the NMOS circuit, the FET appears in what is essentially an source-follower configuration, which has very low small signal impedance. In the PMOS circuit, the FET appears in  what is essentially a common source configuration, which has higher small signal impedance. If the gate voltage were kept stable in both circuits, then in the circuit with lower small signal impedance (NMOS circuit) a change in load will cause a smaller change in voltage than in the circuit with larger small signal impedance. If that is what you mean by &quot;direct&quot; feedback, then &quot;yes&quot;.