Detecting glitches in a sync signal
Use the 1MHz input as a clock also.

Use the 20MHz clock to generate an enable of known length that gates a counter using the 1MHz clock.  The 1MHz counter value at the end of the enable should match the expected number of counts (20MHzCounts/20) within a couple counts (based on clock tolerance and the asynchronous relationship of the two clocks, the best you can do is +/- 1).  If it is higher than you have glitches on your 1MHz clock.

Note: Make sure you correctly resynchronize the enable from the 20MHz domain to the 1MHz domain.