How VDB JFET circuit reverse-biases the gate-to-source voltage?
it shows that the Q point in this VDB circuit will have a negative
  voltage at either Q1 or Q2, how is that suppose to happen if VDB
  produce positive voltage at the gate?


I think you are getting confused between the absolute voltage at the gate with respect to ground (0 volts) and the voltage between gate and source. Consider this scenario: -



With 2 volts applied to the gate node, current will start to flow into the JFET drain and raise the source voltage thus cutting-off the channel. Equilibrium will be found with a source voltage (with respect to ground) that is more positive than the gate voltage with respect to ground i.e. \$V_{GS}\$ is negative a couple of volts for instance.