Driving state machine in FPGA directly from input
The problem is that you are clocking an asynchronous signal (rx) into multiple registers (rx_shift and rx_state) at the same time.  If the input signal transitions close to the clock, it can be read as a 0 or 1 depending on particular delays from the asynchronous input to the register input.

Adding an additional register to clock the asynchronous input (rx_latch in your case) is called synchronizing and it assures that the internal registers see the same value for the external signal.

Note that at very high clock rates, you can run into metastability problems, but for UART rates this should not be an issue.