Why isn't this decoder being inferred as a LUT?
The RTL schematic shows you how it has interpreted your code. As you can see, it has the exact combination of AND gates and multiplexers that your code describes. If you want to know how it has mapped this into the FPGA resources, you need to look at the 'technology schematic'.

Note that the technology schematic is hard to navigate unless you set the synthesis option 'Netlist hierarchy' to 'rebuilt'. Also note that the tools are likely to optimize your code in a ways that can be hard to understand when looking at the technology schematic. You may not easily be able to find the LUT that corresponds to just a particular line of VHDL code, as opposed to that line combined with previous and subsequent (in terms of the logic flow) lines.