Non overlapped implication(|=>) used in system verilog assertion
There needs to be a clock declared somewhere. It can be declared in the sequence itself, the property calling the sequence, the assertion calling the property/sequence, or a default clocking block in the module/interface where the assertion/property/sequence resides. 

You don't usually put assertions on conbinational logic. With RTL combinational logic you usually should not consider delay. Assertions are intended for flop to flop checking.