An error in using FIFO block in system generator
You are geting the error because you can't connect clock probe to a system generator block. But appart of that, what you are doing in this scheme, is the same of getting the WE and RE connected to '1' ! If your idea is connect 2 different clock domains, this is done with the clock signal inputs, that dont appear in sysgen blocks on simulink. But you can simulate this with constants in WE and RE, with diferent Rates.