Why a newer TOP value in the Atmega328p Timer1 has to be greater than the values in all The compare registers?
The counter will increment until it reaches the TOP value, it will then be cleared and start again.
The value in the compare registers are constantly compared with the current counter value and when they are equal an event occurs (such as set the PWM output or create an interrupt). For that to occur the counter must be able to reach the value stored in the compare register.
Any compare values that are greater than TOP will never be reached.