Capacitances in a PMOS transistor: what about the n-well?
In general, the nwell and p-substrate (or pwell and n-substrate) will be connected to ground and to the power supply voltage. (I am assuming that we are talking about conventional CMOS logic circuits here.)
Since both ground and the power supply voltage are assumed to be d.c. there will be no current flow between a well and a substrate. In other words, this capacitance has no effect.
Of course this a model of reality and it may not be the most appropriate model if you are changing the voltages of the wells, or if you are relying on the well/substrate capacitance for some reason. However, for typical CMOS logic design this model is the most useful model.