Verilog -- how to assign mux/selector output to module's output
It would be simpler to just declare the output port as reg (instead of the default, which is wire):

output reg [15:0] out;


But you don't really need the always block anyway, so just write:

output [15:0] out;

assign out[15:0] = (selected ? fifo1.Q[15:0] : fifo0.Q[15:0]);