SDC constraints for source clock and derived clock
Since we know the phase relation, those clocks are synchronous. The only thing we need to do is telling this relation to the synthesis/STA tool.

create_generated_clock -source clk1 -edges {2 3 4} -combinational [get_pins pll/clk2]


I would use the -edges option to define the phase. The following waveform explains the edges. Basically clk2 rises at the 2nd edge of clk1, falls at the 3rd edge and rises again at the 4th edge.

edge    1    2    3    4    5    6
         ____      ____      ____
        |    |    |    |    |    |
clk1    |    |    |    |    |    |
    ____|    |____|    |____|    |____
              ____      ____      ____
             |    |    |    |    |    |
clk2         |    |    |    |    |    |
         ____|    |____|    |____|    |____


The 1-bit data has a half clock cycle to arrive the target FF. By the help of our constraint, the tool will perform setup/hold timing checks accordingly.