Capacitor weird behavior
Emitter and collector for Q2 in the first block (Q6 in the second), Q4 in mine  are inverted. Try to put higher potential points upper. 

Also the discharge transistor seems to be open before the latch triggers making a negative feedback that keeps C voltage at the ref voltage. Added a resistor from the base to emitter that keeps the transistor closed until the latch triggers. 

Also, please, use OA with power rails otherwise the output voltage can go up to kV orders when used as comparator. 

With that tweaks the schematic and  works as intended. 







simulate this circuit &ndash; Schematic created using CircuitLab

The quality of the simulation software also doesn't help to much.

Update, the pull down resistor must be even lower to be less than 10k || 2k2, maybe 1k as the latch to trigger before opening T8 and a capacitor to delay Q2 opening a bit