Delaying a logic level by some ms
The DIR9001's /RST line is a Schmitt-trigger input with nominal 51k&ohm; pullup. Therefore a reliable reset delay should be obtainable by simply wiring a capacitor to Ground. 

To control it from your MCU you either need an Open Drain output, or a diode to isolate the capacitor from the high output (which will also isolate it from anything else the MCU might be driving). 







simulate this circuit &ndash; Schematic created using CircuitLab

When the MCU output is low it holds the capacitor voltage down to ~0.5V (voltage drop across the silicon diode). When the output goes high it allows the capacitor to charge exponentially through the pullup resistor. Reset will be removed when it reaches 2.0V. 

The formula for the required capacitance is:- $$C = - \frac{t}{R \times ln(\frac{V_s-V_c}{V_s})} $$

where \$V_s\$ is the supply voltage and \$V_c\$ is the capacitor voltage at time \$t\$. Since the diode produces an offset of ~0.5V the effective charging voltages are 3.3 - 0.5 = 2.8V and 2.0 - 0.5 = 1.5V. Plugging those numbers into the formula we get C1 = ~260nF.