How does the BSRR register work?
There is a sort of read-modify-write but it is done in logic/hardware without any time between the read and the write.  The statement in Verilog would be:

GPIOA &lt;= GPIOA | cpu_write_data;


This generates logic where there is an OR gate before the register and the new data is OR-ed with the old data and stored in the register. The data bits which you write and which are SET (high) will create a 1 at those locations only. All bit which you write which are clear (low) will remain unchanged. If the bit was set it remains set, if the bit was clear it remains clear.







simulate this circuit &ndash; Schematic created using CircuitLab

Equivalent you can clear bits by using:

GPIOA &lt;= GPIOA &amp; ~cpu_write_data;


The data bits which you write and which are SET (high) will create a 0 at those locations only. All other bits remain unchanged.

It gets a bit more complex to have all these bit-set and bit-clear operations implemented in parallel on the same register but that is just a matter of more logic (multiplexers, address decoders etc.)