flip-flops vs logic gates
It boils down to efficient use of FPGA resources.

There aren't actually gates in a FPGA (in the usual sense of the term). There are, however, a lot of LUTs (Look-Up-Tables), multiplexers, adders, and flip-flops.

Here is a typical FPGA slice:



Now, you have to understand that, using very few LUTs, you can build rather complex combinatory logic. A single LUT can achieve the same result as a combination of multiple AND/OR/NOT gates.

On the other hand, a flip-flop is a flip-flop. There is no trick to lower the number of required elements, here.

So, usually, complexifying the combinatorial logic (the "gates") is not much of a problem (and, in some situations, it may not even lead to an increase of resources used). However, if you use more flip-flops, you will necessarily use more FPGA resources.

Also, the syntesis tools have much more ways to optimize combinatorial logic than optimizing the flip-flop usage. If you did your design right (e.g. there is no flip-flops that are duplicated or whose output isn't actually used), the tools can't do much to reduce flip-flop usage.