Why does the PWM signals amplitude drop once connected to low-side n-mosfet switch?
Can you get at 3.3V with 50 Ohm gen using 3.3V no load?
Your 3.3V signal looks like a 35 ohm load on 100 Ohms or ~1/2 of your driver impedance thus 1/(1+2)=1/3 the voltage


~1.15/3.3V = load/no load


clean up your measurement skills , so GND waveforms are a flat line with no noise and get textbook waveforms.
your driver must be 0.65Ω to 6.5Ω depending on slew rate needed and 2~3x Vgs(th)



You cannot even conduct properly when the threshold for conduction Vt = VGS(th) Gate Threshold Voltage = 1 to 2V @ ID=250uA or RdsOn = 4kΩ to 2kΩ when you are expecting &lt;0.1Ω

my Rule of thumbs


use gate drive voltage = 2 to 3 x Vgs(th) max or 4 to 6V as the Minimum Vgs and 15V max.
use gate driver impedance = 10 to 100 x rated RdsOn = 0.065 Ω @ Vgs=10V


your driver must be 0.65Ω to 6.5Ω depending on slew rate needed and 2~3x Vgs(th)
- If switching slow, Driver ohms can be > 1000 RdsOn but not fast.

although not in datasheet Rg internal resistance is also voltage dependant like RdsOn which is why I use these ratios.  
if you are using 5V logic @ 3.3V they have a driver RdsOn of 50 Ω +/-50%
if you are using 3.3V logic @ 3.3V they have a driver RdsOn of 25 Ω +/-50%


Assuming 5V logic uC with 50 Ω and an output loaded to 1.1 to 1.2V,  your apparent gate load a tad more than 1/3 of your driver resistance ~ 17 Ohms at this voltage which will probably drop to 8 Ω or so during switching edges only in series with Ciss which also changes with Vgs.  See Q vs Vgs chart in your datasheet. fig 13a