Negative voltage ADC and op-amp
Also, can anyone tell me when I have a 0.02V reading all the time?


This is likely the basic error in the ADC when connected to a source of very high impedance (1Mohm in parallel with the piezo). It is likely that ADC "doesn't like" high impedance signals and also any input bias currents will create a sizable DC error as you have seen. This is what the data sheet says: -


  For the A/D converter to meet specification, the charge holding
  capacitor (CSAMPLE) must be given enough time to acquire a 10-bit
  accurate voltage level during the
  1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram, it is shown that the source impedance
  (RS) adds to the internal sampling switch (RSS) impedance, directly
  affecting the time that is required to charge the capacitor, CSAMPLE.
  Consequently, larger source impedances increase the offset, gain, and
  integral linearity errors of the conversion. Ideally, the impedance of
  the signal source should be near zero. This is achievable with an
  operational amplifier such as the MCP601 which has a closed loop
  output impedance of tens of ohms. The adverse affects of higher source
  impedances are shown in Figure 4-2.


As for centralizing the signal, and assuming 1Mohm shunt resistor, split it into 2x 2Mohm resistors; one to ground and one to the reference voltage used by the ADC. You might also consider putting a 1 kohm resistor in series with the ADC input pin because, from what you said in your question, there could be significant voltages produced by the piezo and the 1 kohm would off some protection.