DDR2 decoupling/bypassing - 100nF or 10nF?
The "new rules" for decoupling with modern small MLCC X7R caps is to use the physically smallest cap with the larger capacitance, i.e. 0402 100nF.  I'll try to find a reference for this assertion (something I stumbled across a year or two ago, but the gist of it was that, because of the shrinking scales of smaller MLCCs and the lesser impact of parasitic inductance (so long as they're located/placed in ideal locations) a single smallest-possible-size large-capacitance cap performed better.

This is in contrast to through-hole &amp; even larger-scale SMT, where conventional wisdom (and moreso for particularly sensitive designs that warrant it) was (still is) to have 2 or more decoupling caps (i.e. 100n, 10n &amp; even 1n), which is appropriate due to the parasitic inductances of their larger physical size.

Again, I'll try to dig up the research I read about this, as I'm sure some here will dump upon me from a great height for suggesting this :)