PCIe Data clocked refclk question
In the case of PCIe, there is a 100MHz reference clock distributed to every device, including the Root node (generally on the CPU).

Because every root, switch, and endpoint share the same reference clock, they can use PLLs to multiply the frequency up to the required clock rate (1.25GHz for Gen 1, 2.5GHz for Gen 2, and 4GHz for Gen 3).

Each device will also contain transceiver logic which deserialises the incoming data, using some form of phase alignment which will account for any small differences in phase of each data line relative to the clock and each other. There is then word alignment which ensures that the correct bit is in the correct place in the recovered parallel data stream.