How to determine phase shift for clock being generated for SDRAM connected to FPGA?
This is most likely related to meta stability. The output of the controller needs to be stable for the hold time. Otherwise you can have a situation as shown in the figure below.



If your signal from the controller (A) is not stable for long enough before the memory clock (C2), the latched signal at the memory (B) can be meta stable. It can be high, low, or a voltage between high and low. The behavior is undefined.

To determine the delay required you need to complete the timing closure analysis with the memory (SDRAM) timing constraints using your tool chain.