Scanalogic DIY Logic Analyzer, Extending Sample Time
Looking at the design this makes sense, the LA uses an ATmega16, which only has 1kB internal SRAM.
The link says it can sample at up to 4 million samples per second, with 4 channels. So if you do the math (1kB can be used to store 8000 logic states):

8000 / 4MHz = 2ms -> divided by 4 channels = 0.5ms, which is what you are seeing.

One way to lengthen the capture time would be to adjust the sample rate (e.g. reduce clock frequency or adjust code) but obviously you may miss certain events if you reduce it too much (you will have to judge this based on what your signal frequency is)