"Dynamic" shifter in priority queue implemented on FPGA (SystemVerilog)
I would definitely verify how the synthesis tool implements this that but here is my attempt at reducing the line number count:

always_ff @ (posedge clk)
if (wr) begin
   dataInQueue[trigger] &lt;= dataIn;
   for(int i = 0; i &lt; 7; i++) begin
      if (trigger &gt; i) begin
         dataInQueue[i] &lt;= dataInQueue[i + 1];
       end
    end
end