Avr-gcc using repeated addition instead of MULU instructions
Assuming that you want to optimize for speed:
Unless you really find out how many cycles it takes if you use mul, you can't compare.
So let’s try:

If you use the mul instruction, you need two of them (the operand is 16 bit). So that already costs 4 cycles.
You have to load constant 10 into one register: 1 cycle.
Then you have to add both 16 bit results. That costs another 2 cycles.
Then you have to consider, that the results of both muls always go into register pair r1:r0, but in order to add both results you have to move one of them to some other place: that costs 2 more cycles.

So that makes it already 4 + 1 + 2 + 2 = 9 cycles, just one cycle less than what you got with repeated addition, but you've used more registers. That alone may justify repeated addition (depending on what else is done, having used one more register may cost you more than one cycle).
EDIT:
The calculation above was a back-of-the-envelope calculation; further analysis (cf. 2012rcampion's answer) shows that moving a register pair can be done in 1 cycle (there's a special instruction) and for adding the two multiplication results one add is enough (because we are not interested in a full 3 byte result but want to do a wrap-around with 16-bit width); on the other hand additional measures are required: e.g. clearing the zero register (I guess r0).
Note also that the variant with mul uses much more registers: 7 instead of only 4; a high price because it may cause several more cycles (and code size) at other places.