Propagation delay in case of synchronous counters
The propagation delay will be 2ns because that is the time between the changing input (clock) and outputs (Q0-Q3). Propagation delay of the AND gates not relevant because their outputs should be stable when the flip flips are clocked. However they may limit the maximum frequency that the counter can be clocked at, because their outputs need to be correct when the clock occurs.  

The JK input to the fourth flip flop (FF3) is determined by the states of Q0-Q2. These outputs are stable 2ns after the clock, but then pass through up to two AND gates. If the next clock occurs too early then FF3's JK input will not have had enough time to stabilize and the counter will malfunction. 

The total delay between clock input and FF3 JK input is up to 2+3+3 = 8ns. Therefore the minimum acceptable time between clocks is 8ns + JK setup time. So long as this timing is met the counter should work correctly, and the propagation delay will be 2ns because Q outputs only change in response to clock inputs.