When is proper to use <= or = assigments in Verilog
The rule is simply:


  If one process writes to a variable synchronized to an event, and another process reads the same variable synchronized to the same event, you must write using an NBA ensuring that the reading process uses the old value of the variable. 


If you don't use an NBA writing process, there is a race condition in the reading process in that you don't know if it reads the old or new value. 

Note that each always block in your example is both a reading and writing process depending on which variable we are considering synchronized to the posedge clk event. Also consider the processes that write to the module inputs and read the module outputs.

If you have a variable that is local to a process, it is your choice to use either assignment depending on the functionality you desire. But for combinational, blocking assignments are recommended.