Interfacing FPGA to an external chip and timing constraints
Basically what you're trying to do is create a delayed clock to capture your input, and thus allow more setup time for the return signals. While treating the return signals as 'source sync' with a clock that flies with them seems logical, it's not so well controlled: the return clock signal integrity adds another variable to your timing.

You could instead use a phase-shifted clock that captures your input. This is much better controlled and totally dealt with inside the FPGA.

A safe amount of phase shift is at least the output hold time of your far-end device, plus your best-case (fastest) calculated round-trip flight time, entered as your set_output_delay -min value (entered as a negative number for hold time.)