8085 μp; Why does Read cycle take 3 T-states and not 2?
The "extra" T state is designed into the cycle in order to give the external memory sufficient time to respond. Remember, when this chip was designed, the memory chips used the same basic technology as the processor, and were just as slow, plus additional time was required for external address decoding and bus buffering.

The designers wanted to make it easy to put together a "minimal" system without requiring external logic to generate wait states.



Here are the details of the read cycle, from the datasheet, on page 1-25.



Keep in mind that tCYC is 320 ns (3 MHz, 8085AH), but could be as short as 167 ns (6 MHz, 8085AH-1).

tAD is the total memory access time from the CPU's point of view, from the time the address is stable to when the data must be valid. It is given as 575 ns for the 8085AH. If you shaved off a T cycle, this would drop to just 255 ns.

As I said, this is from the CPU's point of view &mdash; the address lines become valid at the pins of the CPU and the data must be valid at the pins of the CPU. This total time must include the time for the address signals to propagate through address buffers, address decoders and possibly across some sort of system backplane before it gets to the pins of the actual RAM chip. This is the point at which the RAM read cycle begins &mdash; tAA is the time from when the address is valid at the pins of the RAM chip to when its data outputs are valid, and this is usually the slowest parameter on the chip.

Then, when the data becomes valid at the pins of the RAM chip, it must still propagate through one or more bus buffers (and another trip across the backplane) before it gets back to the CPU itself.

All of that overhead could easily add up to something on the order of 200 ns. With a 2 T-state cycle, that would leave only 55 ns for the RAM chip access time. With a 3 T-state cycle, you get more like 375 ns, which is a much more reasonable value for the chips available at that time.