Why does my AND cmos gate have less dissipation than my NAND gate?
I like schematics so you're comparing:







simulate this circuit &ndash; Schematic created using CircuitLab

And you expect that the left circuit with NAND1 would consume less power than the right NAND2 + INV circuit.

If you assume that the complexity of the circuit is the only factor in determining the power consumption then you would likely be correct.

But more is / could be happening!


The power dissipation is related to charging the capacitor. In the
NAND1 circuit there are 2 PMOS in parallel that can charge the
capacitor.

In the NAND2 + INV circuit it is the single PMOS in the inverter
charging the capacitor.

When those 2 PMOS in NAND1 are both switched on, the capacitor is
charged more quickly but that could require a bit more power.
Are the Width and length of all PMOS the same? To me it looks like they might be different, that can also affect how fast the capacitor is charged.


If you really need to know what is going on then this is best understood when using an Analog circuit simulator like LTSpice. That might be taking this too far though.