Output setting time for shift register (74HC595)
To shift out 3 bytes with a 1MHz SPI clock would take 24usec. Say you have a 50 usec overall granularity in your timing including setup and clocking the data to the output. 

That means your error could be as much as +/-25usec out of 1/120 second half cycle for 60Hz mains or about 0.3%. The error in terms of power will be different depending on where in the cycle the 'on' occurs, but it's not very much. 

Seems feasible to me, maybe. You might well have trouble shifting that data out every 50usec without pauses because of other things going on the firmware (such as servicing the stack) but that's not directly relevant to your question. You'd probably have to set a high(est) priority timer interrupt and service it with your own bespoke ISR doing both the timing (counting down some registers and setting bits) and shifting out the data.