Using smaller ram to make a larger ram unit?
You are right for the 4 parallel connection. The the amount of rows, I'm not quite sure your calculus is right, though.  1G is 1'024*1'024*1'024, not 1'000'1000, but apart from that, you would use multiplexers.

The first 11 lowest address lines would be pinned directly to all chips' address bus.  Then, you link the data lines of all chip that contain the same data "byte". (i.e. All Data 0 to 7 together, all Data 8 to 15, etc.)  That would result in 32 data lines linked to 128K chips each (assuming 128k is the amount you intended at first).

Finally, the upper address bits (12 up to 31) would be used as the select lines of a super-duper gigantic demultiplexer which would define which "rows of chips"' ChipSelect (typically CS) line would be tied low to enable the chip's output.