Base addresses and offset values for registers, STM32 documentation
I believe that offset referred to in Table 4.3.2 is from the bottom of the M4's System Control Space. This is defined as part of the M4's Private Peripheral Bus (as mentioned in your document). It is a 1 MB address space from 0xE000E000 to 0xE00FFFFF. So, when it says Offset 0x100, that is 0xE000E000 + 0x100 as you've found.
You can read more about the M4's memory mapping in the technical reference manual on page 3-39, and in the ARMv7-M architecture reference manual, section B3.