Frequency range of interest in PCB decoupling network
It all depends on the analog noise specs for Vcc or Vdd or Vca or Vcd and also the return path with load current specs. This can be understood by impedance ratios for range of frequencies from DC to 0.35/Tr.


Both conditions may apply depending on what the IC needs and uses.

1) external ripple and bandwidth, load current and attenuation needed, which implies an impedance ratio or transfer function s12(f)  for any RLC network and breakpoint.

2) self generated ripple. Any dI/dt from CMOS switched capacitance into a R=ESR+Z(f) supply generates V=IR for duration t.  At low f, an LDO at DC a load regulation spec which rises in frequency due to declining GBW feedback where several shunt caps are used to flatten the Zo response. Parasitic inductances and ultra low ceramic ESR can cause spurious resonace, if not careful so wide low ESL caps are used often UHF or in combination with lossy ferrite beads.  For low current applications an RC filter may be adequate with suitably small cap with high SRF.  

Generally I would recommend impedance or spectrum analyzers to verify a design and calculate by dynamic impedance ratios for source and dynamic load to determine what noise is self induced by each source and if necesary model with s-parameters for each passive part with traces for UHF.  Noise pulse currents with small duty cycle with pulse width with &lt; 1/2 fmax if possible to inject noise currents into the design to analyze effective absorption from C, ESL and ESR.

Search TDK low ESL caps with higher ESR to prevent spurious resonance.

You can use f-3dB =0.35/tr for range of interest vs rise time.


  For some designs, embedded capacitance PCB power gnd planes make sense which requires high quality thin dielectric.
  https://www.google.ca/search?q=buried+capacitance+pcb&amp;ie=utf-8&amp;oe=utf-8&amp;client=firefox-b-ab&amp;gfe_rd=cr&amp;dcr=0&amp;ei=mkKTWsriHfDQXsjWupAN