Generate State Diagram from VHDL Code?
Look into doxygen + graphviz to document your design. The graphviz / dot package lets you describe directed graphs (nodes + edges) which can be useful for drawing state diagrams. (If you're using verilog instead of VHDL, check out doxverilog.) I've recently started using this tool to document state machines in code I've inherited from another engineer.

However, I don't know of any tool to automatically reverse-engineer (recognize and extract) "state machine code" as distinct from just plain RTL code and localparams not meant to be a state machine. Even if you could reliably extract the possible states and their transitions, understanding what each state is intended to do still requires a human. So it's still up to you to understand the HDL code you're trying to document.