How to simulate VHDL program without FPGA
One of the more commonly used simulators (as far as I'm aware) is ModelSim, and therefore it's a good choice when you're starting out. If you install the free Web Edition of Quartus, ModelSim will be installed as well (and ModelSim also comes with ISE WebPack IIRC).

What you are wanting to do is known as a testbench and it consists of writing stimulus code that creates in the input signals for the design under test (DUT) and can also verify the outputs. So, you typically want at least two files: the design you are testing and the testbench for that design.

There are many online resources that will help you write a basic testbench. Here is a reasonable starting point, but you'll want to do a whole lot of searching online; there's a lot to learn.