What features should/must be present inside a prototype FPGA board to aid in debug?
If the memory chip is connected with FPGA, like SDRAM or DDR or others, I'd like to allocate some extra sampling memory space for debugging. This is especially useful when you want to sample a large chunk of data, like a frame or a package, which is larger than signaltap's sample capacity. Some more advanced features can also be designed based on this sample memory like sampling only the packages whose header match a specific value.