Amplifier circuit with clamping output signal
The problem is the following. In your first simulation, you are not using the option "Start external DC supply voltages at 0V" in your simulation configuration panel, and in your second simulation your are indirectly using it because of the non-ideal voltage supply starting from 0V. If you want to double check it, just enable this option in your first simulation and you should get at similar outcome.

What is happening in your first simulation

By not enabling the aforementioned option, upon solving the operating point, at t=0 the collector voltage is set to 9V, the base to approx. 1.5V and the output node to 0V. So basically, your op-amp's operating point is already set and it is ready to amplify. Everything looks nice, and the applied signal does not drive your opamp out of its operating point.

What is happening in your second simulation

By (indirectly) setting the supply voltage to 0V, you are experiencing something called capacitive coupling, which basically means that a capacitor will do everything to keep the voltage between its terminal to stay the same. As the collector voltage at start up ramps up together with your supply voltage, so does the node output. By the time the circuit has reached its operating point, the output voltage already has some offset, which is basically what you see in your simulation. 

How to solve it / avoid it

Depending on the application, if you are going to build the circuit later, you should consider enabling the aforementioned option because it is a closer representation of a real circuit (The voltage does just appear suddenly in all nodes of the circuit). In your case you could either find the biasing point with the option enabled, or remove the output capacitor and mathematically determine the AC amplified signal by subtracting the DC component from your collector's voltage.