how to simulate 4 bit ring counter using max+plus II
Read your error report carefully: it complains about an output, 4.Q, tied to another "output", A:5. The simulator complains because you are likely to drive your input A with some values, but flip-flop four is also quite likely to drive that same exact node with its output. What if A wants to drive a 1 while Q.4 wants to drive a 0? That's not acceptable for a simulator.

So what's the solution? Remove input A. As you see in your above schematich input A is not present. You can preload the counter with the appropriate starting status by driving the PRN/CLRN pins accordingly. You should tie all the CLRNs to something anyway.

Alternatively you can use a selector, or multiplexer: its inputs would be A and Q.4, while you should tie its output to D.1
Of course you will have another input, that is the multiplexer control input: this wire controls what your counter is doing:


normal operation, i.e. Q.4 tied to D.1, A hanging
preload, i.e. A tied to D.1, Q.4 hanging


Just remember: the compiler is your friend, get used to understand it.