What does this bus signal representation mean?
Since most logic and microprocessor IC's use edge clocked timing, it's when the transitions from 0-1 and 1-0 occur that are important to timing. The high and low parallel lines simply tell you that a line may be high or low but not some indeterminate level such as tri-state). In your case shown, greyed out means not valid data/address (multiple signals), not greyed out means they will be 0 or 1 but the data is valid.
The crossovers graphically show the setup and hold timing in relation to clocking. You would read accurate setup and hold times from a data sheet of course. 

For example in the image you show When the clock goes 0-1, the program memory address's are being setup after the greyed (invalid address on the lines) time period. Once the address is stable (non-greyed) the data lines represent (but can be 0 or 1) valid and stable data until the access time passes. Then the data bus will contain either 0 or 1 as appropriate for the memory address.