"Register is illegal in left-hand side of continuous assignment" in modelsim but not verilator
According to the Verilator documentation


  If no language is specied, either by this ag or +langext+ options,
  then the latest SystemVerilog language (IEEE 1800-2017) is used.


In SystemVerilog it is legal to have one (and only one) continuous assignment to a variable. 

According to the Questa/Modelsim Documentation


  If you use the -sv argument with the vlog command, then Questa SIM
  assumes that all input files are SystemVerilog, regardless of their
  respective filename extensions. If you do not use the -sv argument
  with the vlog command, then Questa SIM assumes that only files with
  the extension .sv, .svh, or .svp are SystemVerilog.