ads1232 SCLK pin timing
Since no maximum value for the clock pulse width is given, there's no reason to think the circuit won't work with arbitrarily long clock pulses. 

Making a circuit with a maximum clock pulse period would require extra effort (such as AC coupling the clock input, or implementing a time-out circuit). If the circuit designers had done such a thing, they would have included the relevant maximum clock pulse width in the datasheet.

In an ADC it's also possible that slow clocking could lead to a loss of accuracy as the hold capacitor loses charge during the conversion process. But in this case it appears the device has a separate conversion clock independent of the data interface clock, so that issue doesn't apply here.

Be sure to check the section "Data Retrieval" on page 19 of the datasheet --- where there is a limitation on the data interface rate. You don't want to have a data retrieval in progress when the ADC completes a new conversion. At the higher conversion rate (80 sps), you have 12.5 ms to complete a 24 clock period data retrieval, so clock pulses up to ~250 us could be made to work.