Why does the output of a register bank( designed by me in verilog) change after two clock cycles, even if input changes every clock cycle?
Looking at the waveform your instr is weird/wrong.

It is picked-up in tmp at the same clock edge that it changes. This is indicative that instr change at or before the clock edge. Not after.

Did you use this in your test-bench/code?

always @ (posedge clk)
   instr = some_test_value;


instead of?

always @ (posedge clk)
   instr &lt;= some_test_value;