Xilinx FPGA, error creating generated clock
You've constrained the clock for static timing analysis, but you never actually wrote the logic to divide a clock by two:

reg r_clk_div;
always @(posedge i_clk) begin

   r_clk_div  &lt;=  !r_clk_div;

end

assign o_clk2 = r_clk_div;


This should synthesize to a DFF clocked by input clock, Q tied to D through an inverter, and then the Q output is your new clock. Your constraint tells the tools that you've generated this clock from an existing clock / resource and to treat it accordingly.

Note that I don't have a reset for this divider since I didn't see one in your module, but it may not be a bad idea to avoid temporary meta stability.

Apologies for typos, I'm on mobile.