Where do all the PDN capacitors sit?
Think about where would they would be placed to minimize the inductance between them and your chip.   Smaller value ones being placed closer with the larger bulks a bit further away.  

Often times this is directly under your bga but depending on your reference plane design it could be right at the edge of the chip.   Parts with feet or qfns will want them close to the pins.

Again the goal as you said is minimize impedance wherever you can.  Every connection, via, trace and plane adds impedance between you and your PDN.  Think of it that way and you should be fine.

This is the reason for example you don't want to share vias with PDN caps as well as why via on side routing is prefered  now.

Btw you should take those into account when calculating your over all impedance the rcl models of just the caps is not sufficient.   You can make approximations if you are using spice or say an excel based PDN tool like Altera's.   More solid values can be determined through a post layout simulation tool like Sigrity.  If you are really working on something difficult you can measure the impedance on your boards later but the tools for that don't even rent cheaply :)