Oscillation in digital circuits?
Why is the topic of stability and oscillation primarily relegated to the domain of analog electronics? 


Short Answer: It may have been in a 401 elective you didn't take in non-linear circuits or you have yet to take in the "university of Life" in real design.

It may be taught this way for overlooked for undergrads, but those who have done serious design debugging have learned that all logic chips follow linear circuit behavior with gain and impedance when operating in the transition output voltage range. 

Logic families are designed with a specific current limiting source impedance (RdsOn) for lowest latency at defined pF loads.  They are not internally compensated like Op Amps. As a result buffered or 3 stage inverters are often explicitly avoided in ceramic and Xtal resonator designs to avoid parasitic oscillations at harmonics of the crystal fundamental. 

Although one could get away with buffered inverters in CD4xxx series follow-on generations had higher bandwidth and lower impedance increasing the opportunity for parasitic 
oscillations near unity gain or at resonator harmonics.