How to use USB to communicate PC with a USB device?
After cross-examining of posts from OP on other sites as suggested by Marcus Mueller, the original problem is now become apparent as X-Y problem. The OP is tasked for a college project to build a data acquisition system for some sort of spectrum analyzer for 40MHz-wide signal. They elected to sample the signal at 120 Msamples/s with 12 bit ADC, and send this raw data stream to a modern PC for processing. It is not clear whether the problem requires real-time processing, or block-processing can be fine. In any case the data acquisition system will produce a data stream of 200 Mbytes/s. This is a challenging problem for regular PC, to handle this king of data rate. It is obvious that this kind of bandwidth can't be managed by archaic interfaces as "COM port".

Other than barely manageable interfaces as direct PCIe extender or something like Thunderbolt or 10GB Ethernet, the standard USB 3.0 port should be capable to handle 200 MB/s stream. For example, Cypress EZ-USB FX3 peripheral controller was reported to achieve about 450 MB/s bulk transfer rate on USB 3.0 generic interface. The Cypress offers full development platform for the device side, and PC host driver with application examples. An alternative could be the FTDI FT600/601 bridge.

Therefore I would suggest the following hardware architecture for the project, based on Cypress as an example. A 12-bit ADC should be managed by a small FPGA, which provides the Cypress Master FIFO interface in addition to controlling ADC and store data into ping-pong buffer. The FPGA manages Cypress slave FIFO interface, and FX3 bridges the data stream into USB 3.0 interface.

The host side uses standard xHCI USB 3.0 controller with default OS software stack, and uses the Cypress driver to provide the link to application level.

The application should likely have a ping-pong receive buffer, and forward the data for processing, Fourier Transform, or whatever. It isn't clear if current PCs can perform Fourier processing in real time, so the processing might be resorted to one data block at a time, with post processing creating gaps in the stream of data.

In my professional opinion, at the target data rate, this project will need professional development of muli-layer PCB with ADC, FPGA, and FX3 chips in a chain, and a serious software effort to optimize/configure host software to achieve 200 Msps processing rate. I will restrain myself from commenting on amout of engineering time this project will take.