Is it possible for an FPGA to "partially" configure?
It's not really possible for the FPGA to exit the start up routine with a corrupted configuration as it confirms the CRC of the configuration after the complete configuration is loaded, but before it tries to start up.  If it does not match, then the DONE pin stays low and you can check on what happened by reading the status bits over JTAG.  

Since it seems like the configuration is always completing with the DONE pin released and your divided clock output is working, my guess is you may have a metastability issue or initialization issue in your design that you haven't caught yet.