Reverse engineering a high side MOSFET driver SMD circuit board
Drawing the schematic in a more conventional way usually helps at understanding it better: higher voltages should predominantly be on top and signals should flow from left to right.



simulate this circuit &ndash; Schematic created using CircuitLab
The level shifter
Q1 and R3 together form a constant current sink that draws 1.2 mA irrespective of the collector voltage when the PWM input is high:

When the PWM signal is at 5 V, Q1 turns on and begins to conduct.
As the emitter current rises, the voltage drop over R3 does too. At some point the base-emitter voltage becomes so low (&lt; 1 V) that significant current cannot flow anymore from the PWM input to the base of Q1. The reduced base current starts to limit the collector current.
The collector voltage and the base current eventually reach an equilibrium and Q1 conducts just enough current so that the voltage drop over R3 stays at 4V. Ohms law tells us that the resistor conducts approx. 1.2 mA.
When the PWM input is low, Q1 stays off and conducts no current.
R1 is for limiting the base current while R2 is a precaution against any slight interference that could otherwise turn Q2 on e.g. when the microcontroller is not driving the pin.

The MOSFET pull-up transistor
When the PWM input is high, Q2 drives the gate of the MOSFET high trough D1.

When the level shifter draws 1.2 mA, 300 μA of that current flows trough R3 while the remaining 900 μA comes from the base of Q2. Since Q2 is a PNP transistor, this negative base current switches it on, allowing current to flow trough D1 and charge the gate of Q4, turning it on as well.

The purpose of R3 is to make sure that Q2 turns off quickly and reliably when the level shifter is off. When the level shifter draws 300 μA or less, the voltage drop over R3 is too low (&lt; 1 V) to allow Q2 to turn on.


The MOSFET pull-down transistor
When the PWM input goes low, Q3 pulls the gate low as quickly as possible.

When Q2 is on and driving the gate high, the base voltage of Q3 is 0.7 V above the emitter voltage, keeping Q3 firmly switched off.

When Q2 switches off, R4 pulls current from the base of Q3 switching it on. Q3 then quickly discharges the gate capacitance of Q4.

D1 is there to allow Q3 to turn on. Without it, the gate voltage would always be the same as the emitter voltage, and Q3 would never conduct at all, since it can only turn on when the base voltage falls approx. 1 V below the emitter voltage. D1 blocks the gate capacitance from discharging trough R4, allowing R4 to quickly pull down the base of Q3 allowing it to rapidly discharge the gate capacitance of Q4.


The power section

D2 is a freewheeling diode, its purpose is to handle any inductive transients that occur when Q4 (the MOSFET) switches off.
D3 is presumably an indicator LED


Conclusion
The circuit is fine for the most part, although it does have a chance of exceeding the +/- 20 V gate to source rating of the MOSFET: When Q2 switches on, it momentarily opens a path for the full 22 V to the gate of Q4, as Q4 has a slight delay before turning on and thus the drain voltage doesn't immediately rise to 12 V. In theory the overvoltage is small (20.6 V) and only lasts a few nanoseconds, but in practice parasitic inductances and capacitances can add to the problem allowing the spike to punch trough the gate oxide layer destroying the MOSFET. I would add an unidirectional 15 V transient voltage suppressor diode from the gate to the source. In a pinch a 15 V or 12 V zener should help too.
Your conclusion about long switch-off times isn't justified, as you plotted  the load voltage (the yellow trace) instead of the MOSFET gate to source voltage. In any case, the accuracy of any simulation should be verified with a real world circuit.