SR Latch (Flip Flop) beginning Inputs?
They start out undefined, that is they could be set to either.  

When you switch power on, assuming a real latch with no input signals, both gates will want to output high. However due to no two gates being exactly the same (and other real world effects), one will "win" the race to bring it's output high first, and set the others output to low. The same gate may not win every time, so you can't predict the state at power on.   

This diagram (from the second link below) helps to visulalise things:



For further reading about this and metastability, see these links:

Wikibooks SR latch
Latches and FFs
Wiki Metastability
Metastability document