Tolerance of SPI comms bit ratres (transmitter and clock master too fast)
Clock difference is no problem with spi since the master generates the clock that eventually is used by the slave. You should check the maximum allowed clock of the slave of course. You are probably looking at configuring the tx clock settings of your spi pheripheral of the slave, but they are not used in slave mode. The settings might influence the maximum allowed clock if is some sort of a clock devider for the pheripheral as a whole. Set it to max speed in slave mode if power consumption is no problem.