Elegant way to check a STD_LOGIC_VECTOR to be all zero
You could use the unary operators, e.g.:

and
nand
or
nor

signal my_vector: std_logic_vector(7 downto 0);
...
if and my_vector then
    -- Do something for all 1...
elsif nand my_vector then
    -- Do something for at least one 0...
elsif or my_vector then
    -- Do something for at least one 1...
elsif nor my_vector then
    -- Do something for all 0...
end if;

Or you could use the functions defined in std_logic_1164, e.g.:
function &quot;and&quot;  (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function &quot;nand&quot; (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function &quot;or&quot;   (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function &quot;nor&quot;  (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;

use ieee.std_logic_1164.all;
...
signal my_vector: std_logic_vector(7 downto 0);
...
if and(my_vector) then
    -- Do something for all 1...
elsif nand(my_vector) then
    -- Do something for at least one 0...
elsif or(my_vector) then
    -- Do something for at least one 1...
elsif nor(my_vector) then
    -- Do something for all 0...
end if;