Max number of logic units / gates per logic-unit-output wire: FPGA
You can send a signal on to many many other destinations (the number of destinations is called the "fanout" of the signal).  The more destinations it goes to, the longer your critical timing path potentially becomes though, so the fmax of your design may suffer.

The tools will usually replicate the logic that drives those many nets if the timing becomes slower than you have requested in order to try and meet your timing target.

For Xilinx, this list of appnotes offers advice for reducing fanout when this is on your critical path (http://www.xilinx.com/support/answers/9410.html)