Does a 555 astable dissipate more power at higher frequencies?
Yes it does.

Reducing the oscillation frequency \$f_{osc}\$ will have an impact on your circuit power consumption, because you'll be charging and discharging the capacitor less frequently, thus reducing consumption.

If you also want to reduce the current drawn by the 555 itself, then the first thing you should look after is lowering the supply voltage \$V_{cc}\$. The efficient way to do this is with a switching regulator to bring down 9V to 5V. 

A lower \$V_{cc}\$ has the extra benefit of reducing the amount of charge required for the capacitor to achieve \$\frac{2}{3}V_{cc}\$, thus reducing the power consumption. You can have the best of both worlds and combine this with the reduction of \$f_{osc}\$.

EDIT:

As Jim Dearden has correctly pointed out in his comments:


Using the CMOS version of 555 will help in reducing the consumption of the IC. 
On top of that, the CMOS version can work with higher values of the timing resistor than the bipolar version, thus making possible to reduce the value of the timing capacitor while keeping the same time constant. A lower valued capacitor stores less charge, thus consuming less current while charging up.


Double win for the CMOS version, which adds these benefits on top of those already achieved by reducing \$V_{cc}\$ and \$f_{osc}\$.

Note: selecting the highest possible value for the timing resistor in order to lower the value of the timing capacitor will always yield a reduction in current consumption, regardless of the version of the 555. So it should be considered for any design in which consumption is a concern.