LDR, LDRD and STR instructions with immediate offset in ARM Cortex-M3
LDRD R8, R9, [R3, #0x20]

I believe that is a mistake in the document.  This instruction loads #0x20 (i.e. 32 bytes) above the address in R3 as you would expect.

LDRNE R2, [R5, #960]!

In this case the VALUE of R5 is incremented by the specified immediate value, 960.  If you consider that an address, then it's an address.  In most cases this will be an address.

STRH R3, [R4], #4

Again, as with the previous instruction, the VALUE in R4 is incremented, by 4 in this case.  If you, the programmer, are considering this to be an address, then it's an incremented address.
In the 2nd two cases only the register is modified.  Any memory address pointed to by these is unaffected.
BTW, a really handy thing to help your ARM Assembly learning is one of the many ARM emulators.  I like this one:
ARM Emulator