VHDL 2 segments coding style sensitivity list issue - std_logic_vector at X value
Your sensitivity lists are wrong, you should add every independent variable to the sensitivity list of the second process.

You could also switch to a single-process style, which doesn't have all these problems:

onlyprocess : process(clk, reset)
  type state_type is (state1, state2);
  variable r_state : state_type;
  constant N : integer := 4;
  variable r_counter : integer range 0 to N-1;
begin

  if reset = '1' then
    r_state   := state1;
    r_counter := 0;
  elsif rising_edge(clk) then
    if trigger = '1' then
      r_counter := r_counter +1;
      if r_counter = N-1 then
        case r_state is
          when state1 =&gt;
            r_state := state2;
          when state2 =&gt;
            r_state := state1
        end case;
        r_counter := 0;
      end if;
    end if;
  end if;

end process;