Multiple inputs to IP core in verilog
There are a lot of details that you will need to figure out, but the basic way to do this is to have a state machine with 5 states: idle, transmit 1st, transmit 2nd, transmit 3rd, and transmit 4th.  When a 32 bit word comes in, you transition from Idle through the transmit states, writing one byte per clock cycle, then returning to idle or maybe begin transmitting the first byte of the next word if it is available.

The additional things you will have to figure out are whether you need flow control on the 32 bit input bus, how the receiver will determine the message start and end, whether a 32 bit message is a complete packet, or if you need to transmit longer packets generated 32 bits at a time.

8b10 makes most of these options fairly easy as it automatically figures out the byte framing and provides control code words that can be used for message framing, but you have to make sure it works for your application.

The code would look something like this:

reg [31:0] data_in;
reg [7:0] data_out;

always @(*) begin
    case (state) 
      Idle: data_out = 8'b0;
      Send1: data_out = data_in[31:24];
      Send2: data_out = data_in[23:16];
      Send3: data_out = data_in[15:8];
      Send4: data_out = data_in[7:0];
    endcase
end


You then have to make sure the state machine iterates through states Send1..Send4 at the appropriate time.  You may also have to latch the data_in register so it doesn't change in the middle of sending, and implement a busy flag so to prevent the sender from trying to send a new message while the first one is in progress.