Mixing two square waves and isolating intermodulation component
You have one reference signal f1 in the range 50k to 100kHz. You have another signal f3 in the range 1k to 10kHz. You want to generate their sum, not their difference, let's call this f3, which will be in the range 51k to 110kHz.

The easiest way is to use a PLL to generate f3. Mix f3 with f1, call the difference f4. Phase lock f4 to f2.

This solves half the problem. The other half is to ensure that you lock to the upper sideband rather than the lower sideband, that f3 > f1. The easiest way to do that is to use a frequency discriminator, to provide a logical output for whether f3>f1 or f3f1, nothing more is done. If f3

There are two sorts of phase detector to use in the PLL, analogue and digital. Each have their own advantages and disadvantages, which bear on what sort of mixer can be used for producing f4.

An analogue phase detector, like a DBM (double balanced mixer) can accept dirty inputs, like using a simple XOR gate to mix f1 and f3, and all of the filtering is taken care of by the loop filter. The disadvantages are that most people these days are only educated in digital circuits, and the gain of the PSD (for loop gain calculations) varies with the input amplitude.

A digital PSD, as providing for example in the 4046 PLL IC, must have clean f2 and f4 inputs. Mixing f1 and f3 to produce f4 when f4 must go up to 10kHz and f1 may be as low as 50kHz requires some fairly steep filtering. It may need an elliptic design with a zero at 50kHz to get clean enough signals.

Given a simple PLL VCO like the 4046, setup the VCO Rs and Cs to cover the f3 range. Design the PLL filter components so the loop will be stable with PSD activity as low as 1kHz. A loop bandwidth of &lt;= 200Hz (&lt;20% of the lowest PSD frequency) is a necessary condition (but not sufficient, read the 4046 apps carefully for the sufficient conditions).

The simplest is the classic 3 state phase detector (yes, it is also used as a PSD), which also acts as a frequency detector. Although the PSDs in the 4046 have independent outputs, their inputs are common, so it's not possible to do both phase detection at f2 and frequency detection at f1,3 on the same part. 

Check out US patent US4851784 (now there's a link that should not vanish) figure 4 for an illustration of an all-digital frequency discriminator that can be made with one HC74 and one HC00 (central flipflop uses the other two of the 00 gates!). Ignore the current outputs and take the high/low output (after deglitching with a small RC) from either output of the middle flipflop.