How To extend bits in a VHDL code
I solved the problem by defining an array. my problem was not being able to use "I" iteration for mapping output, I defined an array and use iteration number to point to the proper row. here is the solution:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use WORK.constants.all;

package V_sig_p is
constant NBITS: integer :=8; 
type V_sig is array(0 to (NBITS/2)-1) of std_logic_vector (2 downto 0);
end package V_sig_p;



LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use WORK.constants.all;
use work.V_sig_p.all;


----------------
---- ENTITY ----
----------------
entity BOOTH_ENCODER_a is
    generic (NBITS :integer := 8
        );
    Port (    
        B:        In        std_logic_vector(NBITS-1 downto 0) ;
        S:        Out        V_sig);
end BOOTH_ENCODER_a;


----------------------
---- ARCHITECTURE ----
----------------------
architecture BOOTH_ENCODER_BEHAVIORAL2 of BOOTH_ENCODER_a is

signal B1: std_logic_vector(NBITS downto 0);          --Input with extra 0 at LSB

component BOOTH_ENCODER_comp is
    Port (    
        B:        In        std_logic_vector(2 downto 0);
        V:        Out        std_logic_vector(2 downto 0));
end component BOOTH_ENCODER_comp;

begin

B1 &lt;= B &amp; '0'; --Extension of bit for encoding

GEN_ENC : for I in 0 to (NBITS-2) generate
    GEN_ENC0: if (I mod 2 )=0 generate
        ENC : BOOTH_ENCODER_comp
        port map
           (B1(I+2 downto I), S(I/2));
    end generate  GEN_ENC0;
end generate  GEN_ENC;


end BOOTH_ENCODER_BEHAVIORAL2; 
```