Verilog design question: How to generate internal interrupts without delay?
This type of thing is normal within the synchronous system. It is like you have one DFF after another - the signal will propagate to second DFF only when first has changed its state on previous clock edge.

Think about changing clock edge your interrupt line is activated with - you can use negative edge of the clock, and then next time posedge happens, just raised interrupt signal will be sampled down the line.