FCS verification of ethernet frame
Here is a sample implementation of an Ethernet CRC in VHDL, suitable for a test bench: 

TYPE arr_byte IS ARRAY(natural RANGE &lt;&gt;) OF unsigned(7 DOWNTO 0);
CONSTANT CRC_POLY : unsigned(31 DOWNTO 0) := x"04C11DB7";

FUNCTION crc (data : arr_byte) RETURN arr_byte IS
  VARIABLE r  : arr_byte(0 TO 3) := (x"00",x"00",x"00",x"00");
  VARIABLE c  : unsigned(31 DOWNTO 0) :=x"FFFFFFFF";
  VARIABLE mm : unsigned(31 DOWNTO 0);
BEGIN
  FOR I IN data'range LOOP
    FOR J IN 0 TO 7 LOOP
      mm:=(OTHERS =&gt; data(I)(J) XOR c(31));
      c:=(c(30 DOWNTO 0) &amp; '0') XOR (mm AND CRC_POLY);
    END LOOP;
  END LOOP;
  FOR I IN 0 TO 31 LOOP
    mm(I):=NOT c(31-I);
  END LOOP;

  r(3):=mm(31 DOWNTO 24);
  r(2):=mm(23 DOWNTO 16);
  r(1):=mm(15 DOWNTO  8);
  r(0):=mm( 7 DOWNTO  0);
  RETURN r;
END FUNCTION crc;


The CRC for your frame is (as written in the previous answer): 9B F6 D0 FD.

If you have an MII interface (4 bits wide), the end of the frame should appear as:

2 4 2 4 2 4 2 4 2 4 2 4 | B 9 6 F 0 D D F ]
     end of the payload | CRC


The CRC is initalised with FFFFFFFF to correctly detect leading zeros in the frame. It is inverted and complemented at the end to generate a constant remainder to the Galois polynomial division: If you apply the CRC algorithm to the whole frame, including the 4 bytes FCS, you should always get the 'magic' constant 0xC704DD7B, for all valid frames.