Priority among prioritised interrupts
Refer to the fine User Manual.  The LPC1778 microcontroller contains an ARM Cortex-M3 core which includes the nested vectored interrupt controller (NVIC) peripheral.  The key word here is "nested", which means that the interrupt controller supports nested exceptions and interrupts, which means that an active interrupt can be preempted by a higher priority interrupt.  Search the User Manual for the terms "nest" and "preempt" to learn more.

You'll have to configure the interrupt controller and prioritize the interrupts appropriately for preemption to occur.  Perhaps you'll choose to use the SysTick exception for your timer so that it is higher priority than the CAN interrupt.  Or if you use an interrupt for the timer as well then you'll need to configure the group priority (see section 39.3.3.6) of the interrupts to ensure the timer ISR can preempt the CAN ISR.