Clock termination considerations, single clock driving multiple loads
The best way is to run one long trace and locate each of the loads as close to the trace as possible:







simulate this circuit &ndash; Schematic created using CircuitLab

Keep the stubs to the intermediate loads as short as possible.

HCMOS isn't really designed for resistive termination, so you could even possibly leave the termination off altogether. In that case it might be helpful to add a series resistance to the driver to limit the signal rise and fall times.

If you do need far end termination, then for HCMOS you'll prefer a split termination like I've shown. It would be even better to design the trace for higher characteristic impedance (85 or 100 ohms are common choices) and increase the termination resistance to match. 

You do not want to use matched source series termination for this case, because this method relies on the reflected wave to bring the voltage on the line to the full logic level. This means that the intermediate loads along the line will potentially see an initial edge transition about halfway up or down, then "the rest of the edge" appear a few nanoseconds later. This can cause some dramatic jitter when the first part of the edge gets to an indeterminate logic level.

10 ohms or so in series with the driver output, though, may be helpful for reducing edge rate, and thus reducing high harmonic content in the signal.