The output of a SAR ADC
The SAR uses a S&amp;H (Sample and Hold circuit) on the input and then successively compared with the voltage for that bit starting from most significant which equals full scale/2.

If the input is less than this reference ( i.e. comparator output =0) that bit must be a 0 and if positive that held values is next  offset by that bit analog voltage.

After offset is applied and the difference settles and is sampled and the same comparator output is sampled and if negative or "0" output then there is no change to the approximation and if positive then another offset for that bit voltage is applied . This repeats until all the bits have been compared whether it is a 8 bit SAR or a 12 bit SAR etc.

Hence the name Successive Approximation Register (SAR).



My attempt to explain how they work without specifying hardware type.


Sample and Hold input and buffer going into n bit SAR
Subtract Vref/2^n (DAC out switch voltage)  from Vin
wait small time to stabilize signal
Clock comparator output into shift register
If output=1 then keep that DAC bit high to offset Vref/2^n  (e.g 1/2,1/4,1/8...*Vref)
increment n and repeat from 2. until done.
result is stored in Shift Register. Output may be serial or parallel.
Clear Register when done waiting for next trigger to start ADC.