minimal delay between input and output possible to implement in FPGA
The simplest way to find out, is to pick an FPGA you like (e.g. based on cost and size), and compile a simple design in the FPGA vendors toolkit. 

You could take a piece of code as simple as:

module a (input b, output c);
    assign c = b;
endmodule


Pick to pins that would be in useful places for what you need. Then compile the design. You can then run timing analysis to find out exactly what delay the toolkit suggests the path with take under different temperature and silicon performance corners.

You can simplify the timing analysis by creating a design constraints (e.g. SDC for Intel FPGA) and specifying the delay target for the net. The fitter will then try its very best to meet the requirements, telling you if it fails.