Does a signal need to be in a clocked process to be registered (VHDL)?
In general (99% of the time) you will need a clock signal for each register.

But, verilog/VHDL you do not have to specify the exact register implementation.
You just tell it, this is a bitnode which is either level triggered or rising edge controlled by some signals.

For example if you are using a less common design style, like MS-CMOS, you may not need a clock for each register.  In this case, the register could be represented using an SR latch, which does not need a clock.  But even in this case it would be common to 'staticize' the SR latch's output using a regular type flip flop (which requires a clock).  There are other examples but they would vary a lot.

Each time you add a register into a serial path, you create a cycle boundary (a lock and dam type system controlled by the clock).  So in regards to your last question, it depends on the desired functionality.  But I think your case no, you do not need to register the outputs.  If the inputs are all coming from registers, the output will be 'in that cycle'.  If you add a register at the output it will push that output into the next cycle.