sample input signals and check their values VHDL
It must be = and not &lt;=

a &lt;='1' when id_vec ="10" else '0';
b &lt;='1' when id_vec ="00" else '0';
c &lt;='1' when id_vec ="01" else '0';
d &lt;='1' when id_vec ="11" else '0';

You want to compare if id is equal to 0 or 1 or 2 or 3. Not assign right?

After EDIT

&lt;= also means LESS_THAN_EQUAL comparison which you don't want it to be for your case.