NMOS - Bulk Voltage going from 0 to -Inf
This isn't correct. As \$V_{SB}\$ increases, the depletion region between the N+ implants and P body increases in width; this increases the threshold voltage as a stronger electric field is necessary to shrink the depletion region so that a channel can form.

Here's a Cadence simulation I performed against my PDK (TSMC 180nm 1.8V mixed-signal). Note that the green line (representing lowest Vth) corresponds to Vbs=0, while the red line (highest Vth) corresponds to maximum body effect.



Here's the schematic for my test. I performed a DC analysis sweeping Vgs to get each curve, and iterated this for seven evenly spaced (negative) Vbs values.