Query on Edge triggered D-flipflop using SR-latches
clk is inverted so what you're concerned about is clk changing from 1 to 0 while d is 0. That does make both r and rbar 1 to begin with. It's the way it's supposed to work. Then when clk becomes 0 and d becomes 1 at the same time r and rbar will be indeterminate, brief oscillations are possible before one of them ends up as 1 and the other 0. This is a well known phenomenon called metastability. So all the practical implementations of this type of flip-flop specify setup and hold times, which are the times before and after clk changes to the state that strobes in the value of d when d must not change state. See the data sheet for the SN7474. It's just like your diagram, except it also has a set input as well as a clear and doesn't invert clk.