Making flip-flops using logic gates in Proteus - I'm getting gray (unknown) signals
Can someone help me how can I get this flip-flop to work?


With J and K inputs set high (red squares) the output of a JK flip flop is not truly defined - it is in the toggle condition and, the current state of its outputs is defined by the earlier values of \$Q\$ and \$\bar{Q}\$ on the previous clock edge: -



Picture link.

So, maybe that is what the grey squares are telling you?

Maybe you need to add a preset input to define the initial state as in this SR flip-flop: -



Picture link.

Or as per this alternative version of the JK flip-flop: -



Link address.