Schematic for run of the mill SRAM?
I believe almost all basic SRAM designed and manufactured now use this 6T design. Smaller design exists but they are usually more expensive.

To analyse this cell circuit let's redraw it a bit:







simulate this circuit &ndash; Schematic created using CircuitLab

The bit is held in the two cross-coupled inverters formed by the four MOSFETs in the middle. Confusing looking, but this positive feedback loop latches, and this latching is what stores the bit.

The two MOSFETs on top are connected into constant current sources (or diodes, I cannot tell yet, but that does not really matter I believe.)

When the word line go high the two MOSFETs M1 and M2 turns on, allowing both detecting the voltage of the bit lines or forcing a voltage in changing the state of the latch.