Noise caused by improper decoupling of VDD pin
As pointed out in the comments:

If you have connected the digital and analogue grounds all over your PCB, the digital return current will happily mix with the analogue return current and couple into it, those spikes will then have a much bigger influence in your measurements. Of course if the analogue path is also (partly) inside the MCU, you might have to mix a little here and there, but you could still try to limit the AGND and DGND overlap.

The second thing is, the peaks reduce, because a 100nF capacitor will have a larger equivalent series resistance, it will take some more time to get the charge from it's more complex/longer plates out into your chip. The smaller value has a lower ESR, which will supply the power back to the MCU much quicker, making the peaks much smaller. If you put a 100nF and 10nF, or even 4.7nF next to each other on each VDD pin you will reduce the coupled noise in the case of fast internal switching and of more powerful but more slow external switching much better than with just either of them.

In some cases even 3 or 4 different values are used to cover all the frequency domains, though usually we are talking about single MHz, 100's of MHz and (near) GHz domains in a single chip, such as high end processors, WiFi or FPGAs when there's 4 different sized caps on the power pins.