What's the difference between 0 and high impedance (or floating)?
I don't know so much about other logic families, but let me tell you about TTL:

If you leave an input of a TTL gate un-connected, the gate will read that as a logic 1.  People say that to get a logic 0 you have to "drive the gate low."  But what that really means is, you have to pull current from the input pin to pull its voltage down below the logic 0 threshold.

A normal TTL output pin either drives the output line high (in which case, very little current flows), or else it drives the line low (in which case, the output pin pulls current from however many input pins it "fans out" to.

Note:  Those currents add up.  That is why there is a limit to how many inputs can be driven from one output.

A tri-state output can either drive the output line high, drive it low, or enter "hi-Z state" (a.k.a., "high impedance state", a.k.a., "disabled", a.k.a., "tri-stated").  In high-Z state, the output pin effectively is disconnected.

The purpose of tri-state outputs is to allow more than one chip to drive the same line, which usually is called a bus in this context.  Normally, if you connect two outputs together, when one goes high and the other goes low, you get smoke---maybe.  If not smoke, then you get a large current flowing from the output that's trying to drive the line high to the output that's trying to drive the line low, and you get a undefined voltage on the bus.

If, on the other hand, you have a number of tri-state outputs connected to the bus, then all you have to do is make sure that only one of those outputs is enabled (i.e., not in high-Z state) at any moment in time.

If none of the drivers on the bus is enabled, then the bus will "float" high, but probably not in a well-defined time frame.  To remedy that problem, a TTL bus with tri-state drivers typically is connected to V+ through a "pull up" resistor that helps it to achieve a well-defined logic 1 state in a timely fashion.