Why do we sometime use Pins instead of explicit Power Sources in Cadence?
Generally, you use global power pins and then have a single source tie them together, as you will see in the schematic here for an inverter.  

The places where pins have value over explicit sources are when you have multiple VDD systems, or isolated analog and digital sections.  This is very much driven by layout.  We never assume that the well of a device will be tied to the power because it helps to be sure that you do not have any errant connections, so we have a VDD, GND, NWELL, PWELL on all of our cells.  This is particularly useful for LVS and short isolations.  GND is a huge net, and if you have a PWELL pin, you can test to be sure that you only have explicit connections, not just implicit to the substrate.