Why do parallel memory chips in a DIP package have a disorganized pin arrangement?
First version of chip had address lines A0-A7 to the "left" and A8-A10 to the "right" (as you look into pinput in the datasheet). For compatibility reasons pins are being added from its "pin starting side" of the chip: if you ever programmed EEPROMs you know you always insert chips aligned with their "back", and then you only need to tell programmer the size of chip and it will automatically know where power pin is and how many addresses it has. That's why A0-A7 are contiguous, and then pin numbers start jumping at the "left" side of pinout.