Why do we use negative edge trigger Flip Flop instead of positive edge triggered?
This is an issue when you have one flip-flop output driving the input of the next.  If both flip-flops update on a rising edge, then the second one will be sampling its input at the same time the first is updating the output.  If the clock has more delay (due to trace length or capacitive loading) than the signal, then the second flip-flop can miss the value.  Note that this problem is independent of the clock frequency, slowing down the clock doesn't fix it, only fixing the relative delays will help.

On integrated circuits, FPGAs, and high speed interconnects, this is handled by careful clock routing and detailed knowledge of the setup and hold times of the flip flops, as well as their propagation delay.  However, for low speed buses routed on PCBs, there is another solution: update outputs on the negative clock edge, and latch inputs on the positive edge.  That way, there is an entire half clock cycle for the signal to stabilize before it will be read, and slowing down the clock gives more time for outputs to stabilize.  SPI is a good example of a communication protocol that operates this way.