Flip signal values in verilog simulation
There are no simulator commands that I'm aware of to invert a signal.  However, if you are doing the force from within the Verilog source, you should simply be able to do this:

force path.to.signal = ~path.to.signal;


If you are forcing it from the simulator, you can probably do the equivalent of the above statement in TCL. You would need to get the current value, invert it, and then apply a force with the inverted value.