VHDL - 10% Duty Cycle
You need to have different delays depending on whether the output is currently high or low.

So rather than having 50000 cycles high and 50000 cycles low you have 10000 cycles high and 90000 cycles low. This will require a bit of conditional logic and likely also a larger counter. 

P.S. I think your current code actually has 50001 cycles high and 50001 cycles low, so it will actually give you slightly less than 500Hz.

P.P.S, It's often better to count down to zero than to count up to a defined value. Especially when the number of cycles you need to count is variable.

P.P.P.S your indentation seems messed up.