Adapting an I2C FRAM chip to an SRAM-like parallel interface
This may be a case where a small microcontroller would do the job. The issue would be dealing with the I2C time overhead - your host will have to wait sometimes. You could mitigate that with a caching approach.

Does your host have GPIO? Then you could bit-bang the I2C. This may be acceptable if your I/O needs are low.