VHDL generate statement increment by 2
You can multiply the iterator :

adders: for N in 1 to bits/2-1 generate
        mapping: RBNS port map(
            a =&gt; a(N*2 downto N*2-1),
            b =&gt; b(N*2 downto N*2-1),   
            sum =&gt; result(N*2 downto N*2-1),
            cout =&gt; carry(N*2),
            cin =&gt; carry(N*2-1)
        );
        end generate;
carry(0) &lt;= '1'


... etc