Oscillations on High Side Sensing Current Source
Your simulation program looks like it's modeling ideal op-amps.


Real op-amps have phase shift around their loop-closure frequencies.  You cannot cascade them without compensation.
Real op-amps have finite output impedances in open-loop (600\$\Omega\$ is a nice round number, but it varies).  Real FETs have finite gate capacitances.  These gang up with each other to make even more phase shift when you have a FET in a current-source configuration like this.


You must have external compensation.  Something like what I've shown.  The amp-to-fet resistance should be around 200-1000 ohms.  The RC time constant of the other resistor and the added cap should be, roughly, 10 times RC time constant of the anticipated gate capacitance times the amp-to-fet resistance.

Some experimentation will be necessary, or simulation on an accurate simulator.