VHDL process sensitivity list
You are missing err_count_int in your sensitivity list. Basically, a sensitivity list says &quot;only perform calculations (in the simulation) when one of these signals changes&quot;.
Therefore, reset changes to 1 and you essentially simultaneously set err_count_int, err_count, and reset_out. But, the updated version of err_count_int isn't ready yet so I'm assuming you are getting undefined output for err_count. reset_out gets set correctly because the constant '1' is always available for assignment.
If you need further explanation, please also post the testbench and your simulation results.