How to reduce an ALU logic with the minimum logic possible? Its very challenging
You didn't take my hint form your previous question: "Gate count can be reduced further by share logic with the gates inside the fulladder." To get the minimum gate count you need to look the full combination logic.

One of the best methods to simplify the logic and reduce the gate count is by using a Karnaugh map (also referred to as a K-map). 

This is looks like a homework question, therefore I will not give the full solution. I may or may not have injected errors in the table/equation ;-)

The K-map should look like:

\ I[5:3]
 \  000 | 001 | 011 | 010 | 110 | 111 | 101 | 100
RS\_____|_____|_____|_____|_____|_____|_____|____
00|  0  |  0  |  0  |  0  |  0  |  1  |  0  |  0 
  |_____|_____|_____|_____|_____|_____|_____|____
01|  1  |  1  |  1  |  1  |  1  |  0  |  1  |  0 
  |_____|_____|_____|_____|_____|_____|_____|____
11|  0  |  0  |  1  |  0  |  0  |  1  |  0  |  1 
  |_____|_____|_____|_____|_____|_____|_____|____
10|  1  |  1  |  1  |  1  |  1  |  0  |  0  |  0 
  |_____|_____|_____|_____|_____|_____|_____|____


By pulling out the 1s expressions:
$$
ALU= \bar{R} S \bar{I_5} + R \bar{S} \bar{I_5} + I_5 I_4 (I_3 \oplus S) + I_5 \bar{I_4} \bar{S} (I_3 \oplus R) + ...
$$

If you want to reduce the transistor count, then apply De Morgan's Laws (aka Duality principle) and maximize the use of smaller gates (INV,NAND,NOR). For example every place you see an OR gate whose inputs are only AND gates then convert all to NAND.
$$
AB+CD \equiv \overline{(\overline{AB}) (\overline{CD})} \\
18 gates \rightarrow 12 gates
$$

XORs are a little tricky to spot, so I'll point out: 
$$
\bar{R} S \bar{I_5} + R \bar{S} \bar{I_5} \equiv \bar{I_5} (R \oplus S) \\
30 gates \rightarrow 16 gates
$$