How does strength work in Verilog?
Verilog strengths can be a bit of complicated process understand. To get the full breath of understanding read: IEEE Std 1800-2012 &sect; 10.3, 21.2.1.5, and 28.10 through 28.16.

To print the strength of a bit in a display message, use %v instead of %b. (&sect; 21.2.1.5)

Verilog mostly works in the digital logic space. Verilog strength only comes into play when two or more assignments continuously drive the same net as a from of conflict resolution. The strength value does not propagate through assignment statements. The strength value can be passed through the verilog switch primitives: nmos, pmos, tranif1, tranif0, cmos, tran, plus resistive switch primitives (which weakens the strengths on pass-through). For verilog primitives switches refer to IEEE Std 1800-2012 &sect; 28.7 through 28.9. 

assign (pull1,pull0)  bus = pullup_en ? 1'b1 : 1'bz;
assign                bus = output_en ? value : 1'bz;

assign                out = bus;
assign (weak1,weak0) outw = bus;
cmos inst_name (outs, bus, 1'b1, 1'b0);

// pullup_en output_en  |  out(%v)         outw(%v)        outs(%v)
// ---------------------+----------------------------------------------
//       0         0    |  1'bx(StX)       1'bx(WeX)       1'bz(HiZ)
//       0         1    |  value(St1,St0)  value(We1/We0)  value(St1/St0)
//       1         0    |  1'b1(St1)       1'b1(We1)       1'b1(Pu1)
//       1         1    |  value(St1,St0)  value(We1/We0)  value(St1/St0)


Pullup/pulldown logic from a standard cells libraries provide by your vendor  can be used for synthesis. Some synthesizers have pragmas to indicate a pullup/pulldown on a bus. Out side of that, verilog strength is typically not synthesizable. FPGAs have limited bidirectional bus support; if any. ASICs typically try to minimize the size and use of a bidirectional buses.