VHDL - converting types and integer substraction
First delete the non-standard  std_logic_arith and std_logic_unsigned libraries, leaving std_logic and numeric_std. 

As well as being non-standard, they cause problems through a VHDL rule that - if two definitions of a type (or procedure or operator or whatever) are visible - like unsigned or &lt;= - VHDL will try to discover which you intended (e.g. by the parameter types of the operator, because overloaded operators are legal).

But if two definitions are visible and indistinguishable - both are considered to be hidden. This makes you FIX the problem instead of allowing the compiler to pick one - probably wrong - at random.

So with only the standard libraries, things get a lot simpler.



Now another basic rule is that if you are fighting with lots of type conversions, something is declared the wrong type, which points to a design error.

I'm going to guess the mistake : min should be declared as unsigned but isn't. (Ditto d3 etc). It represents an unsigned number in bit (std_logic) form. So declare it as such. 

Fix that and see what happens. But first, find the source for the numeric_std package (the package spec, don't bother with the package body). You will see a lot of operators that allow unsigned and integer to interact directly.

Then I would expect your code snippet to work directly, without any type conversions. 

If you don't actually need the bits of min, go further and declare it as a subtype of natural with range 0 to 59. There is no reason not to do so, even for synthesis, and for ports on a component.

It is usually appropriate to use unsigned (or even std_logic_vector if you must) for ports at the very top level, where you need to connect each bit to an FPGA pin. But internally, convert to the types most appropriate to the design as soon as you can.