Is it safe to define a memory section over multiple physical memories?
There are several interpretations of 'safe'.

One is, can the processor access RAM blocks as contiguous blocks? 

That will be described in the datasheet for the part. I would expect Microcontrollers with separate but adjacent RAM might to have some restrictions. For example their may be no restrictions for the CPU, but the bus might prevent access to some blocks by DMA.

So, you might develop a program, then later discover it needs to use DMA. That would be a time when the behaviour might become 'unsafe'. Tracking down the bug might be hard if the memory needed in DMA transfers is crossing and uncrossing the memory boundary as the program evolves.

A second use of different segment names for the same memory is to 'reuse' memory at different stages in a programs lifecycle. For example some blocks of variables may be needed during an early phase of the program's lifetime, say for initialisation, but never later. So you could have the linker 'overlay' variables with disjoint lifetimes. This can be tricky to debug, and make maintenance significantly harder because your program is managing its variables lifetime.

What are you going to use the alternative memory segments (RAM0, RAM1, RAM0_M1PART1, and RAM1_PART2) for? 

Are you planning to ask the linker to place variables or code in all four memory segments within one program? As explained above, that is unlikely to be safe unless you mange when the alternative memory segments are 'alive', so that their lifetimes don't overlap.