Xilinx XPS : On what bases the AXI master changes AWSIZE/ARSIZE....?
The SIZE bits specify the axi bus width. To do a shorter write, use the STRB bits to specify which bytes are valid.

See the axi spec, page A3-49


  Write strobes
  
  The WSTRB[n:0] signals when HIGH, specify the byte lanes of the data
  bus that contain valid information. There  is one write strobe for
  each eight bits of the write data bus, therefore WSTRB[n] corresponds
  to  WDATA[(8n)+7: (8n)]. A master must ensure that the write strobes
  are HIGH only for byte lanes that contain valid data. When WVALID is
  LOW, the write strobes can take any value, although this specification
  recommends that they are  either driven LOW or held at their previous
  value.