How to latch a signal high at the first rising edge of a pulse train?
Look up something called a Set/Reset Flip-Flip.  In their pure form, these have two inputs.  When the SET input is asserted, the output goes high.  When the RESET input is asserted, the output goes low.  When neither is asserted, the output retains its state.

S/R flip-flops can be made with two NAND gates, but you can get them ready made in logic chips, like the 74xxx series.