building large shift registers
Usually, it's best to assume the worst case switching pattern, and in this case it will be the easiest. I will define worst case as the input to the shift register changing every clock cycle.

I'll break the power consumption down into several categories. This datasheet isn't exactly crystal clear, so I'm open to any corrections. These are also designed for very small capacitances, so if you have a very large load or long wires, you may be "swamping" these numbers.

Assumptions:


No current consuming load, like LEDs
\$V_{DD}\$ is not given, so it will be kept as a variable, and the maximum value will be calculated.
All traces are small enough to minimize capacitance


Leakage/Quiescent Power

Listed as 0.9uA at worst case, this power comes out to:

\$500\times0.9\mu A \times V_{DD}=450\mu A\times V_{DD}\$ (0.36mW to 1.49mW)

Internal (no load) Switching Power

You won't find a figure for this in the datasheet. Instead, they give you the value of something called \$C_{pd}\$, which is the equivalent of the load capacitance for a given switching event. Depending on your \$V_{DD}\$, you will have different values of effective \$C_{pd}\$. Texas Instruments describes \$C_{pd}\$ as:


  The equivalent capacitance used to
  determine the no-load dynamic power
  dissipation per logic function for
  CMOS devices.


I find this to be somewhat ambiguous for a flip-flop since it isn't clear whether the Data input transitions count. I will assume that they do not. The values would increase by 50% if the D input should be included.

\$500\times C_{pd}\times V_{DD}{}^2\times f=500\times 3.0pF \times V_{DD}{}^2\times 1.52MHz\$ (1.46mW to 24.83mW)

Output Load Switching Power

The next item is how much power is used to make all the output pins switch. At the bare minimum, each output will be driving one D input to the next flip-flop stage. Also, any board capacitance or additional loads will contribute to this power figure. Try to account for as much capacitance as possible.

\$C_{load}=\sum{Capacitance}=C_{Pin.D}+C_{wire}+?\$

\$C_{load}=1.5pF+3.5pF=5.0pF\$ (For the sake of calculation)

Then the output switching power is fairly easy to compute. If you have any appreciable capacitive load, your output switching power can skyrocket.

\$500\times C_{load}\times V_{DD}{}^2 \times f=500 \times 5.0pF \times V_{DD}{}^2 \times 760kHz\$ (1.22mW to 20.69mW)

Total Power

Again, this depends on your load and power supply voltage. For a worst-case switching pattern, we can simply add the three power losses listed, and get the result. The minimum value uses a \$V_{DD}\$ of 0.8V, and the maximum value uses a \$V_{DD}\$ of 3.3V.

\$\sum{power}=P_{leak}+P_{internal}+P_{load}\$

For \$V_{DD}=3.3V:\mbox{ }P_{total}=47.01mW\mbox{;    }I_{avg}=14.24mA\$

For \$V_{DD}=0.8V:\mbox{ }P_{total}=3.04mW\mbox{;    }I_{avg}=3.8mA\$

Clocking Considerations

It is difficult to determine the peak clock current without knowing more variables, including the board layout and clock tree structure and clock buffer behavior and the power supply voltage. However, delivering a clock pulse simultaneously to 500 clock sinks will be difficult. To make it even harder, the gate you have chosen is fast, so that reduces your margin. After you build your device, test it at the coldest operational temperature with the highest power supply voltage allowed and see if the data makes it through ok. 

The capacitance of all the clock pins is 750pF, but that doesn't account for any wiring load.