Determining Pipeline Cycle Time
Before pipelining, total delay = 26 + 40 + 26 = 92ns/instruction.

If an input is fed at 0ns, then 1st stage output will be obtained at 26ns, 2nd stage output at 70ns and final output at 100ns. So the maximum delay is 44ns (= 70-26, in the 2nd stage). So for pipelining, time period of clock must be at least 44ns. 

Since infinite number of instructions are executed, the initial latency can be neglected. Then after pipelining, time taken for executing one instruction will be one clock period. 

After pipelining, total delay =  44ns/instruction.