Propagation delay in shift register - in the context of a serial adder
The reason is probably that x and y are coming from other combinational logic with a little bit of delay, while c_i comes directly from a DFF close by.
It's not that important. In sequential logic like this you should always assume glitches during the start of a clock cycle (signals toggling up and down). As long as you are stable before the next clock edge, you are fine. Stable here means that all signals have had time to propagate to the the next DFF - your design reached timing.