What was the motivation for making behavioral descriptions such a big part of Verilog?
You have to remember that although hardware synthesis is important, the true reason for the existence of Verilog (and VHDL for that matter) is simulation.

These languages are designed to allow users to model and understand their hardware, often before it's even created. They allow entire systems to be analyzed and their designs tweaked to perfection. Then, the hardware model can be transformed into something synthesizeable. With the design model, the synthesis model, and the appropriate tests, the user is able to be sure that proposed hardware definition fully implements their design.

All the crazy (and not so crazy) features of Verilog that you aren't yet using, are there to make writing hardware models (relatively) easy.