Deign Finite State Machine - result doesn't look like what I want -vhdl
The problem is in s2. After reaching state s2, the "next state" is again assigned to s2 as per your flag logic. It is then assigned to "present state" in the next cycle by first process. The consequence is that your second process is never executed in the next clock cycle. Because nothing in its sensitivity list is changing. Flag, present state, start, all remain the same values before. Changing the design to one single process with only clock in the sensitivity list is the better choice.