When should we NOT simplify a digital signal in an expression?
You asked about digital design i.e. digital logic circuit design...

In a logic circuit, unnecessary logic stages might be added to get gate delays to skew the relationship of input or output signal paths. For example, an even number of inverters might be used to create a delay in a path while maintaining the original logic value at the output.

The need to do this depends on the logic device(s) used and the level of abstraction of your design entry. A design in schematic for 74xx ICs would have direct control over gate delays (and often of path delays). A design in VHDL/Verilog targeting FPGAs, CPLDs or ASICs will be optimised by the synthesis tools, which will remove such schemes during synthesis unless constraints stop it doing so. But constraints for min/max timing path delays are easy to add instead and will do the job better. And newer FPGAs often have dedicated delay path circuitry that removes the need for such tricks. So it's more often found in much older designs.