Asynchronous sequential circuit - state table reduction
reduce state table (?)

To reduce the state table you need to find two or more equivalent states
X and Y are equivalent if:

All the input combinations in X and Y will lead to transition to equal states
X and Y have the same output

Then remove any of X or Y if they are equivalent states. Removing equivalent states might lowers the number of bits required to represent all the states of your FSM in your case you need 4 bits to represent all the states of your FSM
I cant find equivalent states in the table you provided but maybe i`m wrong

reduce as Moore or Mealy machine (?)

Honestly i have no idea what does reduce as means, but this is a Moore machine since the circuit outputs does not depend on the inputs A and B instead it depends on the current state

what next? (?)

Just keep reminding yourself that this is just FSM, and all the FSMs looks the same

Your target is to build a combinational circuit that takes 4-bits[Current state] + 2-bits [Inputs a and b] total of 6-bits as input and the circuit output will be 4-bits [Next state] + 2-bits[X and Y] total of 6-bits as output.
A snapshot of the required truth-table might look like this


A,B represents the 2-bit inputs
C,DE,F represents the 4-bit current state inputs
G,H are 2-bit outputs [X and Y]
I,J,K,L represents the next state 4-bit outputs

This represents this part of the state table


get K-maps? (?)
draw circuits from boolean functions (?)

You will build K-map from the truth-table for every output in the circuit [Total of 6-Kmaps] then draw the required circuit. But keep in mind, the used registers will be SR flip flops this means you need some logic circuit between the next state output and the S-R f/f to make sure that the values are stored correctly