Which value will be used in an always block?
clk_at_time leads clk_from_time and there is a zero-time delay between the two of them. You cannot see the offset in a wave form or a $monitor statement, but it is there. To understand your simulation results, you need to understand the Verilog process scheduler.



The active region evaluates all assignments. In a procedural block, if blocking assignment (=) is used then the calculated value is applined to the variable immediately. If non-blocking assignment (&lt;=) is used then the calculated value is applied to the variable in the NBA region. Any reverences references to the variable with non-blocking assignments before the NBA region is executed will use the old value (not the updated).

This are the steps through the scheduler your simulator is likely taking for your code:


ACTIVE region


eval initial block and calculate but postpone update on r1, r2, clk_at_time

NBA region


update r1, r2, clk_at_time (values calculated in step 1)

ACTIVE region


eval always @ clk_at_time block (change 1'bx->1'b1) and calculate but postpone update on clk_from_time
eval always @(posedge clk_at_time) block (1'bx->1'b1 is posedge) and calculate but postpone update on r1, r2, r3

NBA region


update r1, r2, r3, clk_from_time (values calculated in step 3)

ACTIVE region


eval always @(posedge clk_from_time) block (1'bx->1'b1 is posedge) and calculate but postpone update on r4

NBA region


update r4 (value calculated in step 5)

#5 time progression
ACTIVE region


eval ~clk_at_time and postpone clk_at_time update

NBA region


update clk_at_time (values calculated in step 8)

ACTIVE region


eval always @ clk_at_time block (change 1'b1->1'b0) and calculate but postpone update on clk_from_time

NBA region


update clk_from_time (values calculated in step 10)

#5 time progression
ACTIVE region


eval always @ clk_at_time block (change 1'b0->1'b1) and calculate but postpone update on clk_from_time
eval always @(posedge clk_at_time) block (1'b0->1'b1 is posedge) and calculate but postpone update on r1, r2, r3

NBA region


update r1, r2, r3, clk_from_time (values calculated in step 13)

ACTIVE region


eval always @(posedge clk_from_time) block (1'bx->1'b1 is posedge) and calculate but postpone update on r4

NBA region


update r4 (value calculated in step 15)

Go back to step 7 until time progression is #200 then exit


How the propagation works should be easier for you to visualize of you change all &lt;= to &lt;= #1. 



FYI: By definition Verilog (intentionally) does not specify the evaluation order between two always blocks activated at the same time. This mean if you change clk_from_clk &lt;= clk_at_time; to clk_from_clk = clk_at_time; Then value that is assigned to r3 can be indeterminate because  always @ clk_at_time and always @(posedge clk_at_time) are triggered in the same ACTIVE region. In practices you are unlikely to see the indeterminate behavior in simulation