Adding trigger functionality in for FPGA in ADC capture board
I'm not familiar with your board/reference design, and you are free to implement what you see fit, so here are some general thoughts. 

It sounds like the ADC-FPGA connection is via SERDES. All serializing/deserializing steps have a latency cost. The data is being serialized in the ADC and deserialized in the GTX, so there's probably a hundred nanoseconds or so of latency there; this is much larger than the FPGA's pin-to-register delay. Thus when your trigger signal hits the FPGA, there's a kind of built-in data buffer that guarantees you'll have samples starting with the trigger edge. If you care about timing on the nanosecond level, you need to look up the numbers, do the analysis, and verify in hardware.

If you didn't have latency built into the system, you could make a pipeline buffer to create your own latency. But typically the way to ensure data availability is with a ring buffer. I believe the Virtex-5 BRAMs are dual-ported, so a ring buffer should be straightforward to implement; whether you need it is up to you.