Verilog mux using a clock
While not strictly recommended, the simplest way of achieving this is the following:

wire out;
reg outReg;
always @ (negedge clock) begin
    outReg &lt;= in;
end
assign out = outReg | clock;


This would ensure that when the clock goes high, the output will be a 1. Once the clock goes low, the data gets clocked into the register and appears on out (which is no longer being or'ed high). The trouble with this sort of method is that it results in the clock signal having to come off the global clock network to pass through the OR gate which can lead to timing issues due to excessive skew - if we are talking about slow clocks like 10-50MHz that will probably not be an issue though.

EDIT:

I remember now having come across the error this causes in the past. There is a work around to get this to compile (drop the error down to a warning), which is described in Xilinx AR#33025. Basically you need to add the constraint from the error message PIN "XLXI_3.O" CLOCK_DEDICATED_ROUTE = FALSE; to your UCF file and then also assign the global clock to one of the upper group of BUFG (clock buffers) to allow the signal to be able to get onto non-global-clock routing as well. The second part is done with another constraint in the UCF file: INST "name_of_bufg_instance" LOC = BUFGMUX_X*Y* where BUFGMUX_XY is one of the upper group BUFGs - details on how to find valid names can be found at the link above.



Another alternative would be to use a DCM block to generate a 2x clock signal. This clock would then be used to drive the register - in one cycle of the fast clock you would drive to 1, in the other you would drive to your input signal. Granted you would have to synchronise the two clocks to ensure that the 1 appears at the rising edge of the 1x clock, but that can be done.



My suggestion however would be to consider why your logic requires you to do this and see if there is alternate way to design the later logic. Talking from experience with making some pretty complex systems with FPGAs, I find that if you get to a situation where obscure signals have to be created with half clock periods things tend to get messy quickly and the design falls apart.