Rise/Fall time of GP Pins
This is usually called "drive strength" or "speed" and is configurable in some microcontrollers like STM32 and Altera FPGAs.

In general, the edge-rate is not controlled by clock speed.

Edge rate (or slew rate as Ben points out) is controlled by the source impedance of the driver, rather than the oscillation speed. Because edge rates can be so much faster than the clock rates, sometimes you want to limit it by changing the internal drive setting or by placing series resistance into the line to reduce RF emissions.

The edge rate has to be fast enough to get to full amplitude during a cycle for a fast clock speed, but otherwise there isn't any real limit on how fast or slow the edge rate is in comparison to the clock rate. Edge rate and clock rate are the result of different physical processes and circuitry.