Minimizing AND gates in ANF
There is an enormous amount of information about achieving minimal logic with only NAND or only NOR, both of which are functionally complete by themselves. The reason for this is that NAND and NOR can be made with a minimum number of transistors. I don't know if there is literature on minimum logic with AND and XOR. But you could use a minimum NAND solution to leverage this body of knowledge. A NAND gate for you would be an AND gate followed by an XOR based inverter. (XOR with one input wired high is an inverter). Initially I  was not planning to answer this question as it is not an area where I have deep knowledge, but nobody else provided a high quality answer, so I am giving it a shot.