DDR3 RAM, FPGA connection and termination
Normally the data groups (DQx, DQS, DM) have on die termination, the address and control pins however will need termination to VTT (Check the memory datasheet for details).
Note that for DDR3, address and control is normally routed flyby where the data groups are point to point.
Usually the FPGA can handle the source end of the termination if you pick the correct IO banks or let the MIG do it for you, so you just wind up needing a mess of resistors to VTT on the address and control lines.
Note that the VTT plane is the reference for the impedance calculations most of the time, if referencing to other planes (Gnd) you will want extensive capacitive stitching to VTT.