Why can't absolute delays be used in ASIC?
It is interesting that CS is used to ask CE questions. Anyway, it is a convention. It is impossible to obtain exact delays by combining transistors and conductors in the silicon. 

The delays you specify are used to model the expected delays, which is worth for simulation. In real HW you will have actual delays which will depend upon the propagation delay in your circuit. In Verilog you describe the structure of your circuit, which will be implemented in terms of gates, wires and transistors, which will be placed on the chip and connected by wire. Depending on the resulting structure and chip layout, your circuit will have its own delay, unrelated to what you have specified for simulation. In simulation you just make your best guess what that delay could be. Post synthesis and post-layout tools will upgrade your figures. You will resimualte your testbench with syntehsized netlist to see if it still behaves the same. 

I guess there are some synthesis attempts that may synthesize your timeings. But it is too difficult and unreliable because Verilog is intended to describe the logic of your circuit, implemented with transistors, whose speed depends even on the temperature. At the same time, current tools have difficulties even to synthesize large designs with timings disregarded. It would be an too much to ask them to synthesize your timeings. 

It is even unnecessary because all current designs are still synchronous. The only thing that is required of them is that propagation time between the registers is less than clock cycle. It makes no sense to ask to make some segment of the path of specific length, no more no less. In some cases, when you need to interface with external devices, the delays may still be important and, I believe, ASIC tools have custom means to keep these delays under control. FPGAs for instance have some phase managers in the IO pads.