What does "CL" stand for in this processor architecture block diagram?
In the PDF file the text under the diagram is "With the clock wired as shown, the A and B data bus are driven from data read from the register file when  CL is high, and the busses are driven from the ALU when CL is low". 

Although not explicitly stated, I think the author intended CL to mean "CLock".

When the CLock is high the register file values are presented to the ALU input latches, and when the CLock subsequently becomes low the output from the ALU is presented to the buss and written to the register file by asserting W (Write)...which I suspect should have been marked on the diagram as bar-W.