What will the output of filp-flop if its input is metastable?
In the paper it is explained that metastability is inevitable in a system with asynchronous signals:


  In a multi-clock design, metastability cannot be avoided, but the detrimental effects of metastability can be neutralized.


The picture you have uploaded shows the simplest solution, which is to use a flip-flop as a single "time delay" unit between the systems with different clock signals, to recreate a synchronized signal. As described here:


  metastability  may  not  always  result  in  unpredictable  output.  If provided  sufficient  time  with  proper  excitation,  the  f/f  can in fact settle to a stable state


What happens in your picture is that the arriving signal is initially metastable. This generally means the signal is oscillating around a voltage that neither can be interpreted as 0 or 1. If it were used directly in e.g. a combinational logic, results would be inconsistent between parallel systems that use the data.

The time delay caused by the buffered flip-flops give it enough time to resolve its state to a valid voltage level, as metastability is very sensitive to thermal noises and other interferences (just like the example of a ball that is about to roll down a hill). It is only a passing state, never a final one.