How many stall cycles resulted by incorrectly predicted branch in instruction pipelining
So, the reason why an incorrectly predicted branch can cause 3 stall cycles is because in this problem, it is stated: "Assume that branch outcomes are determined in the EX stage..." This means, that it takes us 3 clock cycles to determine whether or not a branch is taken. Going back to your scenario, you may be wondering how this applies to the TINS instructions, in other words, the target instructions. Looking at the very first TINS1, we can observe that it takes that instruction AT MOST 3 clock cycles before we branch off to INSNX. If you are wondering why, you must understand that our branch is predicted in the execution stage which is 3 CLOCK CYCLES. Therefore, if we branch to ISNX, we will have a penalty of 3 CLOCK CYCLES to flush out potentially 3 (TINS1, TINS2, TINS3) instructions. Please refer to page 308 figure 4.59 of Computer Organization by Patterson and Hennessy Risc-V edition to have a better visualization of what I mean. The problem is very similar. I hope this helps. 


BEQ       F   D   E  
TINS1         F   D   X        (Branch Taken prediction, target instruction prefetched,      
                                but prediction failed, thus instruction cancelled)
TINS2             F   X        (prediction failed, thus instruction cancelled)
INSNX                 F   D... (Instruction after BEQ executed)

             |&lt;---&gt;|           (Two instructions cancelled. 
                                Isnt this equals two stall cycles?)