Verilog circuit not synchronous
Two problems:


In a sequential always block (one on the clock) always always always use the "non blocking assignment" which looks like a less than/equal to sign (&lt;=).
Never ever assign to a signal from two always blocks. If you want q to be asynchronously reset, make the always block sensitive to negedge clock or posedge reset. Then have if reset first, followed by else for the other conditions. This probably isn't causing your problem now, but it will cause problems eventually.