Delayed ON level on pulse
This can be done with one quad NOR gate.  Two gates form an adjustable monostable, and two gates form a S-R flipflop with a power-on reset.

U1A and B form a true monostable that ignores all switch bounces after the first positive edge.  U1C and D form the output flipflop to hold the output state after the monostable times out and triggers it.  U1 pin 3 rests high after power-on, which would create a false signal at U1 pin 13.  The added C3-R3 differentiator has a time constant that is five times shorter than the power-on reset pulse from C4-R4, so C3 has time to charge up before the flipflop is enabled.  In this way, the flipflop ignores the monostable high output state on power up, but responds to the high state at the end of the delay period.

Once the flipflop is set after the first time-out period, all subsequent inputs are ignored.  Power should be off for 1 sec. minimum to reset C1.