Finding common mode level and max output swing in two stage op-amp
Indeed, the task data are incomplete or at least formulated tacitly -- depends on the context of your project. The design uses short channel MOSFETs (lenth &lt; 2u), but if you absolutely need to attempt this task, you can start and replace transistors with the simplest MOSFET model (longchannel and without channel length modulation) as a voltage controlled current source (similar to technique used in an answer to this question)



simulate this circuit &ndash; Schematic created using CircuitLab
I_DS = 0                                       V_GS &lt; V_Thresh
I_DS = beta·(V_GS – V_Thresh – V_DS/2)·V_DS    V_GS &gt; V_Thresh , V_DS &lt; V_DSAT
I_DS = (beta/2)·(V_GS – V_Thresh )^2           V_GS &gt; V_Thresh , V_DS &gt; VDSAT
                                               V_DSAT = V_GS – V_Thresh
For pMOS, change signs to accommodate device polarity.
beta = u0 (carrier mobility) * Cox (oxide capacitance) * W/L
You can find V_Thresh, u0, and Cox parameter values in reference documents, e.g. Star-HSpice Manual.
Typical V_Thresh are 0.45V for nMOS and 1V for pMOS; the default u0 are 2.0718e-5 (NMOS) and 8.632e-6 (PMOS), Cox about 0.00035 Farade/square meter.
If you succeed in this undoubtedly useful exercise, you can further attempt more advanced transistor models.
A regular approach to analysis of electronic designs is the use of simulators (SPICE/PSPICE/HSPICE, Cadence Spectre X simulator, Mentor AMS simulator, other high-end packages and numerous free tools).