STM32F10xxx ODR register atomic write
the statement GPIOB-&gt;ODR = 0x00000002 is a store(STR) instruction and accoring to this technical reference manual, is a single cycle execution, therefore atomic.
please note that GPIOB-&gt;ODR = myVariable is not.
for finding out which instruction is atomic and which on is not, you have to find out which instructions your C code generates, then use provided references to see if they are executed in single cycle or not.
when you are writing to a register, you are loading a system bus with 32bit data at CPU[DMA] side and unloading it at a peripheral register. all the 32 bits in the bus are either 0 or 1. so you can't keep the previous value for some bits in the peripheral register. the workaround is two things. the first you are familiar with :
GPIOB-&gt;ODR |= (1UL&lt;&lt;3);

which is a shorted form of a longer statement :
GPIOB-&gt;ODR = GPIOB-&gt;ODR | (1UL&lt;&lt;3);

as you can see, it means read GPIOB-&gt;ODR, OR it with (1&lt;&lt;3) and write the new value to the GPIOB-&gt;ODR. so you read it, modify it, and write it.
there is no way to do single bit operations with this structure [programatically]. so there was a problem when fast bit manupulations were needed.
here comes the bit banding:
in this method which is used for frequently used registers (e.g. IO) each bit is hardware-mapped to another memory location (which is 32bit wide, a whole register). so when you write in this register, a single bit would be changed accordingly. as it's obvious, it seems inefficient in case of hardware because you need a full register for just another single bit in a peripheral register :

so for GPIOB you need 16x32bit memory locations, for 16 pins! this part of memory is called bit band alias region. it's just an ARM Coretex M3,M4 specific feature.