What is the formula for calculating out the time delay for the sum output in a ripple-carry adder circuit?
For a 4-bit ripple carry adder, since the carry is rippled through, the final Cout and S3 is valid only after the propagation delays through each full adder. So the total delay would be:
$$t_D = 4 \times t_{FA}$$

Inside Full Adder:



The critical or most delayed path is for C_out. It is via XOR --> AND --> OR. Suppose all gates have equal delay = \$t_g\$, then \$t_{FA} = 3t_g\$. Therefore \$t_D = 12 t_g \$