Safe I/O voltage levels for Xilinx SP605
1) Yes, FPGA IOs are usually powered per bank, on your board BANK0 is powered by 2.5V, so will be fine with 2.5V in. However you will want to check the datasheet for the high/low voltage threshold. Don't forget to check what voltage each bank is working at before you connect things up though! Bank0 is 2.5 but there no reason why the other banks are not at 1.8 (or even 1.2) or up to 5V depending on the development board.

2) I wouldn't expect so on a dev board such as the one you have, however you may be able to bodge it on the PCB if you check out the schematics and know what you're doing.