Why is there a resistor in a cmos X-OR gate?
The resistor limits the current shorted from VDD to GND by the output stage when both output transistors are conducting.

Some logic gates, such as 60-70's CMOS gates or 74LS, have a linear region whereby their input voltage can be moved through levels that produce a linear change of output.

This was/is very pronounced in CMOS gates. If a the input of a CMOS non-inverting gate is moved gradually up from GND to VDD, its output is GND until the input reaches a starting point, then its output quickly but gradually increases to VDD. All that time its output is transitioning, both output transistors are on to some degree and you're drawing excess current from your rail. The resistor stops the transistors pulling too much current and wasting it or damaging the gate. 

What you want from an ideal logic gate input is for all voltages below a certain input threshold level to be seen as logic low and all those above to be seen as logic high. And an ideal push-pull logic gate would have an output which: drives high by turning its top FET(?) full on and its bottom FET completely off; drives low by turning its top FET completely off and its bottom FET full on. But this would use a lot more transistors than the current implementations of logic gates, so you'd get fewer on a chip.

If you look around, you'll see 74LS inverters used with crystals and capacitors to make oscillators by keeping them in their linear regions. You can't do that with their successor, 74HC(T), because they don't have a much smaller or non-existent linear region (would have to look which up).