always statement inside case in Verilog
No, but you can put a case stament inside an always block:

always @(posedge CLK) begin
  case(EncodingMode)
    0 : EncodingNumbers[EncodingIndex]=EncodingNumber ^ Masks[EncodingIndex];
    1 : EncodingResult=EncodingNumbers[EncodingIndex];
  endcase
end


always blocks are executed in parallel, control structure goes inside of it.

Think of Always blocks as sections of hardware, if, case and other control mechanisms are branches of logic within that block. If you are selectively creating always blocks you are creating and destroying hardware on the fly.

If it is for improved reusability of code where we control the hardware base on constant parameters then generate statements or pre-processing techniques can help.

In your case you seem to want to trigger the block differently, write on posedge and read on any edge. Therefore I would recommend using 2 separate blocks which check the set mode.

always @(posedge clk) begin
  if (EncodingMode == 0) begin
    EncodingNumbers[EncodingIndex]=EncodingNumber ^ Masks[EncodingIndex];
  end
end

always @(clk) begin
  if (EncodingMode == 1) begin
    EncodingResult=EncodingNumbers[EncodingIndex];
  end
end