12 to 6 look up table
The on-chip cache memory is designed as part of the memory interface circuits and is optimised for speed at the expense of other considerations such as power consumption and die area that may make it impractical for larger sizes. It's also not generally accessible to the user so its addressing circuits and data paths can be simplified. All of that in combination with the lack of parasitic inductances and capacitances and the buffering needed to support off-chip access makes it considerably faster.

Tell us more about your application, as there may be other options available.