Erratic behavior from 16-bit counter IC SN74LV8154
I see 3 concerns in your schematic:


First, and most needed: There's no decoupling for the 555 timer.

The bipolar (i.e. not CMOS) version of the 555 timer is notorious for high current spikes when its output changes state, which requires local power rail decoupling.

Not all 555 datasheets have the same decoupling recommendations, but the old National Semiconductor datasheet (and some others) say:


  Adequate power supply bypassing is necessary to protect associated circuitry. Minimum recommended is 0.1μF in parallel with 1μF electrolytic.


That recommendation was probably from the era before MLCC SMD ceramic capacitors, and a single 1uF MLCC might be enough IMHO.

The current TI datasheet says:


  A bypass capacitor is highly recommended from VCC to ground pin; ceramic 0.1 μF capacitor is sufficient.


Depending on which set of recommendations you follow, these one or two capacitors must be fitted within a few millimeters of the IC, for maximum effectiveness.
Second, there's no decoupling for the other ICs either. As flagged already as a duplicate, this previous question highlights that the 74LV8154 can be affected by power rail spikes, due to lack of decoupling:

Binary counter (SN74LV8154) jumps (internal bits seems to flip)

Again, decoupling capacitors are needed immediately next to those ICs.
Finally, you've added capacitors to the two clock signals. I don't see how that would be helpful and I would remove them.


So overall, it's very similar to the linked question above, but the 555 timer in your design is a specific problem, as that device is known for its high current spikes which will affect the power rail to the other devices in your design, due to the missing decoupling. Even if adding decoupling next to the 555 seems to solve your problem, add decoupling next to the other ICs too.