Impedance matching at the boundary between two PCB's
With clarifications added, here is my answer. The particular device of interest is a 16-bit DAC. It has a PARALLEL interface, and settling time is 5us. This means that the converter should not be used with data changes faster than 5us (200 kHz sampling). This means that all concerns about edge rate and impedance matching have little to no grounds. The parallel interface with separate strobe and data has enough room at 5us rate to avoid any ringing that might emerge due to trace impedance mismatches. That's why the TI evaluation board does not have any special precautions for data input connector, and uses the cheapest 0.100" IDC headers. The 0.100 connectors have typical impedance of 100-120 Ohms, and the 10mil trace over 14mil substrate comes up to 78 Ohms.

Now, to get nice edges out of this setup,  it is advisable to have the same kind of traces on the baseboard, and, since the drivers are thought of fast LVC245 nanosecond-grade buffers, a set of in-series resistors of about 47 Ohms would be in order, on driver side. They can be later adjusted for the best waveform. But again, you can do nothing, and the DAC interface will work just fine.