Noisy top peak of clock signal with CMOS inverter circuit
Switch the scope trigger to &quot;LINE&quot;. And drop the sweep to 2 milli Seconds per division. This may reveal the cause.
Otherwise, slow the sweep to 10 microSeconds/divison, and set the trigger to DC Internal, then adjust the trigger level to be near the waveform top.
This may reveal SwitchReg ripple.
As the comments suggest, have 0.1uF cap across VDD/GND within 1cm of the oscillator.
And have your scope probe Ground lead going to the bottom of that Scope Ground lead.
Other circuits sharing the VDD, such as MCU, thru long leads/wires to the power supply may cause this. But the smoothness of the waveform's top suggests there is no high_frequency energy here.