preventing Rx/Tx data clashing on a xmega USART
My question is then, if I am in the middle of transmitting a byte OUT of this data register, how do I prevent an interrupt triggered by a byte coming IN from causing me to lose data?


You don't. There are two separate registers, accessed using the same address but different modes. One holds the last byte pulled from the receive hardware, and the other holds the next byte to put into the transmit hardware.

If you read from DATA you access RXB, and if you write to DATA you access TXB.