Why do layout footprints for Crystals often define via keepouts?
The green &quot;shaded&quot; area is the vRestrict area, which restricts the
placement of vias in the designated area for design-rule checking
(DRC). Why is this an important consideration?

Because the metallic (and therefore conducting) crystal can is laid flat and could make contact to exposed PCB traces that are not covered with solder resist. Typically, vias are not covered with solder resist. However, it's not a good idea to put any copper traces (covered in solder resist or not) in the area directly under the metal can.
You can use an insulating pad of course then it's OK.