Dynamic Logic - Transistor Sizing
In normal static CMOS logic, you need to maintain equal rise &amp; fall times because there is both PDN &amp; PUN networks. But in this footed Dynamic logic, you have only PDN network. So during precharge period (\$\Phi=0\$), PDN network is idle and charging through PMOS can occur more slowly than static CMOS logic. Therefore, PMOS transistor can have small width. 

For example, consider this 2-input NAND: 



Here, PMOS transistor is chosen to have unit width (W) and thus it has twice the unit resitance (2R), assuming \$\mu_n=2\mu_p\$. But for NMOS transistors we need to have unit resistance  (R). Since there are three series NOMS transistors, each will have three times the width of unit transistors(3W). So the total resistance is equal to unit resistance (R). 

As you can see, PMOS has the twice the resistance than the total NMOS transistors' equivalent resistance. So the rising delay will be larger than the falling delay. But it wont  affect the performance, since during precharge, inputs are idle.

You can follow the same technique for other PDN networks. This example was taken form "CMOS VLSI Design - Weste &amp; Harris'