I need to derive a lower frequency clock from the main clock and sample it in verilog
Your problem is probably this line:

assign result = reg2[0];


Because earlier you declared

output reg [3:0] result;


Nets declared as reg type can only be assigned within procedural blocks (always and initial blocks).

If you want to use continuous assignment, you must declare the variable as a wire type. 

In the case of an output, that just means removing the reg keyword from the declaration:

output [3:0] result;