NAND equal rising and falling time in Spice
As a general guideline you will want to have the PMOS ~ 2.5X the width of the NMOS (assuming that the lengths are the same).  This is because of the mobility differences.

However, I see you are in a smaller process and a node in which some processes implement mobility enhancement in the PMOS, principally through stress.  So the guideline may or may not be useful.

Your best bet is to just keep the NMOS at a fixed width and vary the width of the PMOS only.  You can also look into the spice file for the process and get the mobility values directly from there.