AND gate between 2 std_logic_vector Isn't working correctly
in vhdl two distinct types of instruction could be used : sequential an concurrent. You can have a look at the difference between the two instructions have a look at the answer here . in your case you are using a concurrent statement generate which translates into the following :

   b1(i)(i)&lt;=mb(i);
-- b1(0)(0)&lt;=mb(0)
-- b1(1)(1)&lt;=mb(1)
-- b1(2)(2)&lt;=mb(2)
-- ..........
-- b1(23)(23)&lt;=mb(23)
bt(i)(msb2+i downto i)&lt;=b1(i) and ma; --line-A
-- bt(0)(23 downto 0)&lt;=b1(0) and ma;
-- bt(1)(24 downto 1)&lt;=b1(1) and ma;
-- bt(2)(25 downto 2)&lt;=b1(2) and ma;


analyzing that you can see that, since you initialized your signals here :

signal bt       : matrix:=(others=&gt;(others=&gt;'0'));  
signal b1       : minimatrix:=(others=&gt;(others=&gt;'0'));


they all start with zeros. In the expansion of your concurrent code b1(i)(i)&lt;=mb(i); as you can see from my comments above, you are constantly assigning the b1(i)(i) to one single bit of the mb and the rest is filled with zeros. 
you are then moving the whole vector of b1(i) padding it with zeros on the left and right depending on its position. This is explains what you are seeing in the simulation. 
In order to achieve what you are asking for 


  |0.....ma|
  |0...ma 0|
  |0..ma 00|


you can simply avoid the first copy and the AND so that line-A becomes bt(i)(msb2+i downto i)&lt;= ma; --line-A and as you can see b1 is not needed