Need help understanding an universal pin driver schematic
The drive signal has to rise approximately to Vpp to turn that transistor off. That is not possible with direct drive and Vpp greater than the supply of the 74HC chip. Something with an open collector or open drain fills the bill, and the ULN2003 is cheap and has 7 such outputs.
If the pin is switched to Vpp > Vcc the transistor would otherwise conduct, even with base drive = Vccx (off). There is a bit of variable voltage drop (depending on current) due to the diode so it's not ideal, but it's a cheaper solution than using a better switch design. 
The diode and series resistor clamps the voltage to Vcc plus a diode drop and the additional series resistor keeps the current into the FPGA input protection network relatively low. It's a cheap solution that is probably adequate in many situations. 
Probably just to deal with inputs on the target device that may be outputs from time to time, and should be held in some defined state when inputs. It would be better to have the pins individually programmed as high-Z, pull-up, or pull-down but this arrangement is cheaper/simpler and adequate for most situations.