How to reduce EM radiated emissions in a 2 layer board with 2 components?
To reduce the area further the best option would be to position the two ics as close as possible. Is this correct?


Yes.

Other things you can do:


If the signal is digital, design the source to have as slow a rising and falling edge speed as possible. This might involve a series resistor at the source's output pin.
Add a ground on the top layer, surrounding the signal trace, and connect this to the ground pins of the "source" and "sink" chips. If you're designing controlled impedance traces, you are now working with "coplanar waveguide with ground plane" (sometimes abbreviated "CPWG") rather than microstrip.