PCB layout for decoupling capacitors
As TomCarpenter says, in this scenario, a good solution would be to move the capacitor near the VCC pin (pin 8 of U1, I think), then connect its ground side to the thermal pad under the chip, and connect thermal pad directly to the ground pin (pin 4).


  Is it even necessary for the GND of the decoupling capacitor to be connected to the same via as the GND of the chip?


Ideally, the ground pin/pad of the capacitor should be connected by as short a trace as possible to the ground pin of the chip, and the VCC pin of the capacitor connected by as short a trace as possible to the VCC pin of the chip. 

The idea is to make as small a loop as possible from VCC, through the chip to GND, and through the capacitor back to VCC. This will generally minimize the equivalent inductance of the connection between the chip and the capacitor.

If your soldering process is capable of it, you might prefer to use smaller capacitors than 0805, because they have lower internal equivalent inductance. (on the other hand, using a larger package will allow getting a capacitor with higher voltage rating, and thus generally less reduction of capacitance due to applied voltage) 

Reducing the inductance (in the connection to the chip, and internal to the capacitor itself) increases the resonant frequency of the connection to the capacitor, so it increases the frequencies at which the capacitor continues to provide a low impedance for currents drawn by the chip.