Implementing a counter in VHLD with edge triggered clear
You can't drive a single flip-flop (such as you might use to implement a synchronous state machine) with two different clock signals. In general, when you need to react to edges on multiple signals in this way, you need to use an asynchronous state machine. Unfortunately, design techniques for ASMs don't seem to be widely taught any more.

In this specific case, you could use a simple R-S latch. This latch would be set by a low on the frame signal, and cleared by a high on the clk signal. Call the output of this latch first. In your counter, which is driven by the clk signal alone, if first is set, you clear the counter; otherwise, you increment the counter.

When you try to synthesize this code (especially for an FPGA), you will undoubtedly receive one or more warnings about this combinatorial feedback loop &mdash; you'll just have to ignore them. Or if your tools allow it, add a specific exception for this case.