Lucid (Verilog) intermittent generated clock signal
Your output only goes high for 1 cycle out of every 500. 

Your graphical display probably doesn't have the resolution to show this correctly. If you zoom in on one of the regions that seems to have no transitions, you will probably be able to see the missing high pulses.

If you want to create an output clock with 50% duty cycle, then you should be setting out &lt;= ~out when the terminal count is reached, and not changing out otherwise. You would need to halve the terminal count value to have the same period.