Poor man's clock MUX with an LVDS input
As I read the specs, even a controlled bipolar switched 3.5mA current source into a  100 Ω Differential load on clock will add 4ps (p-p) of INL jitter to subsequent clocks generated.

Now the LVDS expects 350mV diff. input from 100 Ω so use a 1.8V 25 Ω CMOS switch voltage source with +/-25% tolerance (est.) on RdsOn Pch/Nch may have skew but significantly more ringing without a load from Z mismatch depending if the prop. delay on the path is greater than 10% of the rise time from inherent load capacitance. This may reduce your false trigger voltage margin with a return loss near 0 dB.  Therefore without a balanced differential signal, signal integrity may be worse from crosstalk to nearby output signals due to the unbalanced drive.

But without knowing your crosstalk or mutual coupling or stripline layout, added jitter may be hard to estimate. But keep in mind the datasheet for a t_Stop2-1 is 94.4ns with the 6 sigma jitter of about 10ps. but I would not eliminate the differential load if you can Gate the driver input, but that may cause other latency issues.

Just a SWAG, but differential CML or current mode logic is best for any jitter sensitive logic and use CoG caps to avoid microphonic jitter.