Difference between >> and >>> in verilog?
It is not similar to ==/===, if the left hand operand is signed then &gt;&gt;&gt; performs sign extension.

reg signed [9:0] b = 10'sb11_0101_0101;
reg signed [9:0] a_signed;
reg        [9:0] a_unsigned; 

always_comb begin
  a_signed   = b &gt;&gt;&gt; 2;
  a_unsigned = b &gt;&gt;  2;
end


Result:

#a_signed   1111010101
#a_unsigned 0011010101


Example on EDA Playground.