Which of these is the correct circuit for JK flip-flop
The first one is correct. The second one will inhibit the outputs from ever changing.

The cross coupling arrangement of the second one is correct for a JK flipflop built from two and three input nand gates.

Incidentally the inputs are labelled incorrectly. The J &amp; K should be swapped over.
With this circuit when the inputs are at opposite binary states, it is the input which is set to 1 which sets the diagonally opposite output after the rising edge of the clock. So to set the Q output (top output), it is the the bottom input which should be set to 1 (top input reset to 0). Conventionally the J input is the set input (sets the Q output when set to 1) and therefore the lower input should be called J.

EDIT: If the clock signal is a square wave (or something close) it should be converted to very narrow clock pulses by one of the circuits below. Top circuit below creates a positive edge triggered JK flipflop, the bottom circuit creates a negative edge triggered JK flipflop when connected to your first circuit.







simulate this circuit &ndash; Schematic created using CircuitLab