Improving dV/dt turn-on immunity of a mosfet without increasing turn-off time
I simulated your circuit using a similar FET with a transient suppressor added, switching a 'short circuit' drawing 1000 amps from a 50 V battery with 10 nH of wiring inductance. It 'worked' in that it had no effect on the switch-off time or power dissipated during the transition. However in this scenario the transition is slowed down by Miller effect, so (assuming adequate transient suppression) you should not have to worry about Dv/Dt causing the MOSFET to turn on again. 

So when might Dv/Dt be a problem? One possibility could be if the battery is plugged in while the FET driver is not powered. In this case there could be a fast rising Drain voltage with only weak resistance pulling the Gate down. But would this cause the FET to turn on? Looking at the MOSFET's capacitance graph we see that Gate-Drain capacitance is ~800 pF at 50 V, while Gate-Source capacitance is ~12 nF. That corresponds to a division ratio of 16:1, so 50 V on the Drain could produce ~3.1V on the Gate. As the threshold voltage is between 2 and 4 V the FET might partially turn on for a few microseconds. 

By adding extra capacitance to the Gate your circuit increases the capacitive division ratio which makes the power-on transient Gate voltage lower, (hopefully) ensuring that the FET stays turned off when an external voltage is applied.