How to generate signal who have value less then one clk in vhdl?
The best you can do is to use the high period from the clock to 'gate' a compare signal. But you might still end up with some 'runt' pulses. This is what might get:
  

This is where the 'runt' pulses can come from:

At the beginning your individual dat1 bits will have tiny delays to get to the final value. Thus your compare might not straight go to 1 or 0 but take a while to settle. Your clock gate might filter some of those out, or not. Also they may be so short/fast that the following logic (especially of it is a slow output port) filters them out. But if the req is uses as some sort of gate/clock you should be aware that they might happen.

A bigger problem is at the end. Your dat1 will change after the clock edge so between it changing, it is very possible that the req signal comes out again. Here you have the issue that your individual dat1 bits will have tiny delays to get to the final value and thus again you can have runt pulses after your runt pulse.