How instructions get executed in a pipelined architecture?
Why the second instruction ADD R5, R4, R3 is in decode state two times? (in 3rd cycle and again in 10th cycle)


The decode stage includes the reading of the operands from the register file. In the second cycle, the decoder discovers that one of the operands for the second instruction is not yet available &mdash; the decode of the first instruction had marked R3 as "busy". Therefore, the decode of the second instruction needs to be repeated after the write from the first instruction makes R3 "not busy". The write occurs in cycle 9, which means that the read can happen in cycle 10.


  Why the third instruction ADD R6, R4, R1 did not do its DECODE state 4th cycle?


Because the decode of the second instruction had not been completed. Instructions must be decoded in sequence, because that's how the data dependencies are established.