Character '0' used but not declared for type std_logic_vector??? (Algorithm state machine)
VHDL is strongly typed language.


count is a 3-bit vector. You should assign it as "000", not '0'
adding should be like count &lt;= count + "001" 
counter_out has not been declared.
in your second process, count will never increment after "001". As it is always assigned "000" in the beginning of the process.
your if blocks dont have else block in the second process. Also, on reset initialise all signals to a known initial state. And make sure that all signals are assigned some value in all possible input combinations. It will  avoid inferring latches during synthesis.