System-verilog generate module instances and pass input/process output data
You cannot instantiate a module instance inside an always block. You choices are to move the synchronous logic inside MyUnit or flop the output MyUnit at the same level.

Typically, you want to flop your final outputs. You may put some combinational logic after the flop, but be aware this can can make flop-to-flop timing across different modules harder to calculate.

So assuming MINIMUM and MAXIMUM are the values you want flopped, I would recommend the following logic:

always_comb begin
  // Set defaults
  next_MINIMUM = '1; // fill with all 1s
  next_MAXIMUM = '0; // fill with all 0s

  // Alternative default with the previous MIN/MAX values
  //next_MINIMUM = MINIMUM;
  //next_MAXIMUM = MAXIMUM;

  // Update MIN/MAX based on MYOUT
  foreach(MYOUT[idx]) begin // IEEE Std 1800-2012 12.7.3 The foreach-loop
    if (MYOUT[idx] &lt; next_MINIMUM) next_MINIMUM=MYOUT[idx];
    if (MYOUT[idx] &gt; next_MAXIMUM) next_MAXIMUM=MYOUT[idx];
  end
end

always_ff @(posedge clk) begin
  MINIMUM &lt;= next_MINIMUM;
  MAXIMUM &lt;= next_MAXIMUM;
end


It is a best practice to always assign a flop with non-blocking. Blocking assignments are needed to properly calculate the next value. Therefore, the intermediate signals next_*. When using SystemVerilog, it is recommend to use always_comb and always_ff instead of always (See IEEE Std 1800-2012 &sect; 9.2.2.2.2 always_comb compared to always @*).