Verilog: negative value in brackets of vector signal definition
Example 1
  
  reg [3:0] addr;
  
  The 'addr' variable is a 4-bit vector register made up of addr[3] (the
  most significant bit), addr[2], addr[1], and addr[0] (the least
  significant bit).
  
  Example 2
  
  wire [-3:4] d;
  
  The d variable is 8-bit vector net made up of d[-3] (msb), d[-2],
  d[-1], d[0], d[1], d[2], d[3], d[4] (lsb).


Source: http://verilog.renerta.com/mobile/source/vrg00057.htm

So [7:-12] c_in; would create this array of wires/integers or whatever your creating an array of:

c_in[7]
c_in[6]
c_in[5]
c_in[4]
c_in[3]
c_in[2]
c_in[1]
c_in[0]
c_in[-1]
c_in[-2]
c_in[-3]
c_in[-4]
c_in[-5]
c_in[-6]
c_in[-7]
c_in[-8]
c_in[-9]
c_in[-10]
c_in[-11]
c_in[-12]