SMD board: Routing feedback trace for SOIC OP amp
Bypass caps layout is bad in both examples.

When your opamp output stage delivers enough current to enter the "B" part of its class AB, it will draw halfwave rectified currents from its power pins. You do not want to inject these currents into your GND plane.

Fix is to put both decoupling caps (for V+ and V-) next to each other, on the lower side of the opamp (according to your drawing) and have the caps' GND connected to GND plane at one spot with 2-4 vias.

Now, about feedback layout, at 100MHz 1nH won't add much phase shift if your feedback resistor is something like 150-330 ohms. Put the resistor on the bottom if you want a really short path, but this will only work on 4 layer. On double sided it will make a slit your GND plane on bottom layer, which I guess would be worse than routing feedback on top layer. 

EDIT:

It should work better with pics. I attempted to use online PCB editor easyeda.com...



And the PCB layout:



Now, since this is my first time using EasyEDA (sorry, too lazy at the moment to boot my main PC and load up Altium)... just imagine the tracks are the right size, etc.


  Your "fix" for the bypass issue makes no sense at all. For one thing, the current pulses you're talking about are not in-phase, so there's no cancellation possible.


V+ and v- opamp pins draw halfwave rectified current when it enters class B. These currents are a very distorted version of the original signal. Letting these currents flow into GND plane will create a distorted voltage across the plane. If you use GND as a 0V reference, this may increase distortion depending on where your 0V reference vias are taken (there is one on the + input here, since the opamp is inverting).

This is why I put the two decoupling caps together, and connect them to GND at the same point. This way, the current injected into GND is the sum of V+ and V- currents, which is simply the output current, and is therefore not distorted. Only linear current is injected into GND, which means the potential on the 0V reference via on the + input may still move around, but it will be linear with the signal. This will cause a tiny gain error, but no extra harmonics.

This other layout will decrease feedback resistor inductance, but it will increase power supply inductance: