What exactly do the well taps in MOSFETs do and how?
Well taps, if placed densely enough to quickly provide charges into the well and thus maintain the well at either Ground or VDD, allow a fast and clean switching of the FET's channel conductivity. This clean switching gives low gate/FF delays and low edge jitter.

I've seen place-and-route cell-libraries that DID NOT HAVE A WELL TAP in each cell; in fact, the library/rules allowed up to 30 (THIRTY) cells between Well Taps (also called Well Ties). Clearly the new-graduates and the SENIOR_LIBRARY_DEVELOPER had a learning experience just ahead.

I later heard that library caused lots of SHMOO problems, lots of delays in logic state changes (surprise), and the library had to be redone by adding Well Taps/Ties into each cell.

WARNING --- substrate ties/taps have the SAME function and behavior and responsibility.

WARNING#2 --- ignore well taps, and end up with massive interactions between the various logic activities, massive crosstalk on switching, massive ISI InterSymbolInterference, and horrid Deterministic Jitter.