How to make a register in VHDL remember?
One possibility is that your mentor is considering that signal declarations are needed to provide the &quot;storage&quot; for the register. Just as an example, they are declared in this document from Xilinx:

The flip-flops are not synthesized because of the signal declarations. It is the edge triggered part of the code you have shown that implies the flip-flops, regardless of the fact that they handle inputs and outputs directly.
As you can see, the synthesis of your code (using Vivado) correctly results in a series of d-flip-flops:

Additionally, take a look at this question and the 2 up-voted answers.