How does CLKOUT works on the LTC2323-12 ADC on "High-speed" speed mode?
The other way is described as a "high speed" that can "ease the
  timming requirements for the FPGA" (would you clarify this for me?) ,
  this last one method is trough the CLKOUT signal, which is seemingly a
  Clock that comes out of the ADC that is matching (or latching) the ADC
  results out of the SDO port. Is that correct? Did I get it correctly?


Yes, that is correct. Your data receiver can use CLKOUT to latch the data coming from the ADC. The CLKOUT signal and the data out can be delayed by PCB tracks feeding the FPGA (receiver) and if both are created at the ADC and generally routed along similar paths to the FPGA then they will remain in sync no matter whether it's millimetres or several centimetres between ADC and FPGA.

The SCK line comes from your FPGA and if it was used to latch in your digital data then there is a clock delay going to the ADC and a delay to the data coming back and this can mean (on longer PCB tracks) that you won't latch clean data.


  So do I have to design the FPGA module in order to output the CNV
  signal of startup, then keep it for TCNVH nanoseconds, then release
  it, then just wait until ADC AUTOMATICALY send the first CLKOUT, so I
  can register it and count 11 more of these CLKOUT, while passing the
  SDO data out to my own registers on each of these CLKOUT cycles?


Yes, to get optimum high speed performance on longer PCB tracks.


  Then after the last 14 CLKOUT clocks, I must design a counter that
  trigger a valid signal that will start another counter of TDSCKLCNVH
  nano seconds




Yes, according to the timing diagram above (which I've also added a few minimum timings to).