Clock line of SDIO bus has worse rise/fall time than rest of bus
As I suspected, I was able to resolve this by increasing the drive strength of the Pi GPIO to 16mA for all of the pins on the bus. I'm fairly certain that what I was seeing was the ATWILC3000 driving the data line while the Pi was driving the clock. With that change, I am now able to operate at 25MHz without issues.