Synchronising GPIO transitions to an external clock
The two flip-flops are used to avoid issues with metastability. The idea is that the first flip-flop has some small probability of going metastable, but if it does, it's much less likely that the metastable state will propagate to the second flip-flop.

A "hardened" flip-flop has higher internal gain than an "ordinary" flip-flop, which means that a metastable state should decay more quickly, reducing the chances of propagation. However, I've only ever seen "hardening" discussed in the context of custom IC design, and I'm not aware of hardened devices that are available as discrete devices.

Putting a delay between the flip-flops is actually counterproductive, as this would reduce the window of time for the metastable state to decay.

So, just use two flip-flops of whatever technology best fits in with the rest of your circuit.