Is it possible to design a SD 3.0 controller in UHS-ii/uhs-i mode using simplified specifications?
I read simplified spec and I think that it is sufficient to build the UHS-II host.
Maybe some things are explained in a simplified way, but it is possible to check them on the builded prototype and improve it if they did not work.

The bigger problem is probably implementing this in FPGA.
My favorite FPGA manufacturer, Lattice, not helping because requires a subscription license to use SERDES FPGAs (free license is only for non-SERDES FPGAs). I'll probably must switch to XILINX.

The commands look the same as in SD Legacy mode. Difference is mainly in the PHY, due to 8b10b and SERDES coding (and maybe in CRC to).

What FPGA do You plan to use for this?