How an electrolytic capacitor survives in negative half cycle?
If you do a small signal analysis the capacitor sees a small negative voltage, however that is actually on top of the bias  which is a relatively large positive voltage (5V or something like that). The voltage across C2 can never be negative for a passive load. 

Presumably you would add a collector load resistor in order to see some output, because there will be none at the collector and precious little at the emitter. 



Note: That's assuming "normal" conditions. If you feed a 10kV 1kHz sine wave into the circuit you will see negative voltage across the 100uF cap, but other bad things will likely be happening too