Understanding Phase frequency detector logic
2(C) shows the PFD with constant waveform time-delay, where the +IN always occurs some small time before the -IN edge. The Out waveform should be labeled "CP out", because that is the SUM of the two internal waveforms, the UP and the Down.

Let's back up a bit, and consider how this 2-FlipFlop PFD behaves (some PFDs have more internal logic, to achieve yet more useful behavior, but I'll let you research that). This simple PFD (and an EXOR gate is a PhaseDetector but not a Frequency Detector) pushes UP on the VCO if the Fref_input (re-label the +IN as Fref) rising edge occurs first.

And if the other input -In (re-label it as Fvar, from the voltage-controlled oscillator) rising edge occurs first, this PFD pushed DOWN on the VCO.

Here is a better drawing of the same logic diagram.







simulate this circuit &ndash; Schematic created using CircuitLab