VHDL: What is correct way to model open collector output for FPGA?
FPGAs have tri-state outputs :

sda &lt;= 'Z' when dout='1' else '0';


There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor.

VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs. 
You can write

sda &lt;='H';


in the test-bench to simulate a pull-up.

std_logic is a "resolved" type, a signal can have several drivers, and a resolution function is used to determine the final state : 'Z' + 'H' = 'H' , '0' + 'H' = '0'