Thermal protection effectiveness against short circuit
The thermal timeconstant of a cubic meter of silicon is 11,400 seconds,

The thermal timeconstant of 1 cubic millimeter of silicon is 1,000,000X faster, at 11,400 microseconds or 11.4 milliSeconds.

Typically the die are thinned (from 300 microns in raw form) to 100 microns.
The thermal timeconstant of 100 microns is 100X faster at 0.114 milliSeconds.

Unfortunately, unless the over-temp-detector is imbedded into the power-device (not off to the side), the power region can melt before the detector "detects" its_too_hot.

Even if the device is operating at 25  &deg; C, and a short occurs, the rate of heating between the top and bottom of the silicon will be far too fast to be detected by some "diode" off to the side.

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I performed some thermal modeling 15 years ago, that showed the "temp detector" needed to be no further than 10 microns from the periphery of the power device, and preferably placed within a niche , or even in the middle of the power device.

As you've seen, the magic-smoke gets to escape (or that horrid "click" sound gets emitted as the plasma ball expands and ruptures the epoxy lid).

There is a severe interference issue in "temperature detectors" on power devices. Unless the "diode" runs at high current (milliAmps), the dynamic resistance will be high and the diode voltage easily upset from charges injected INTO THE SUBSTRATE or from EFIELDS coupled metal-to-metal on surface of the die.

======================== May 11

Where  to read about such topics? I'm going to say "Its just simple physics", and visualizing cubes of material with uniformly_flowing columns of heat.

I recall ONE article in Journal of Solid State Circuits (the Red Rag) where the placement of the bias_generator transistor was computed, and the math for 100 micron grid size was agreeing with my math (within the use of physical constants for silicon at room temperature but from different text books).

About 25 years ago, I was simulating Substrate Currents for silicon, to develop very quiet working regions on very_trashy_integrated_circuits (you need nested Substrate Shields). 

And I soon realized, at the next job, I could model Heat Flows, important because my first new assignment was a data bus power driver with the need to survive 8:1 overvoltages. But the Thermal Protection did not work.

Developing the theory, I computed the Thermal TimeConstant of 10micron silicon spacing was 1.14 uS, of 100micron spacing was 100X slower, and of 1,000 micron spacing (about what we had onchip) was 100 * 100 slower at 11.4 milliSeconds. As result, the design team finally was persuaded to both (1) move the ItsHot sensor much closer, and (2) redesign the power output devices to ensure current uniformity even when hot.

Why are there not books, or chapters in books, on such thermal-survival design?
I think its because sometimes we engineers have to extend our personal understanding beyond what we've been taught. And if such understandings lead to more profitable products (perhaps they build a better reputation among the customer base), then we can say "This is a proprietary understanding. Do not publish about it."

This is why "world class design teams" will "lose the magic touch". There are many traps between concept of system-on-silicon and success. If the team, in early products, should get lucky and avoid a few of the traps, but in later versions stumble into such traps, chances are the revenues collapse and the team is dispersed, because crucial phenomena were not identified and methods developed to manage the RISKS.