Best way (logic) to model an XOR?
There is no "one best way", there are only requirements (explicit and inferred) and designs that do or do not meet those requirements.  

Among the many requirements are:


# of transistors in the cell
the fan-in (how much of a load does each cell present to the the source)
the fan-out (how much of load can each cell drive)
the propagation delay
symmetry of propagation delay (+'ve vs. -'ve edge) or assymmetry for that matter
power consumption
shoot through current when switching
metal layers used in fabrication
any more that I can't think of right now.


THe pass gate and TG versions mentioned have very low transistor counts and very poor driving (fan-out) to name some of their attributes.

To answer your question explicitly, the best way to model a XOR gate is to model what was actually built or how you intend to build it.