Transistor level netlist benchmarks
I would put this in the comments, but it's too long.

For research purposes, I always just make my own because I can publish over them.  I have commercial libraries as well, but there's a no publish clause that is in the contracts.  You might be able to get someone to supply you with something for the larger nodes.  http://www.vlsitechnology.org/ might get you started.  

On the side of practicality, a single library might be fine if you are just looking at graph routing because the details generally do not have to know anything about the cell but the ports.  The routers just locate the pins and then route the graphs.  You might do better to just make a "pin matrix" tool that then routes the wires, and then you can narrow down if/why/what is the best pin placement for the standard cells.  You can simulate these just by doing the layout wire extraction and the circuit netlist. 

If you are dead set on standard cells, and have access to the Cadence/Synopsys tool chain, I would suggest emailing Dr.Mooney at Georgia Tech and as him for "Phil's" document for creating and analyzing standard cells.  I cannot recall Phil's name, but we have extensive documentation for creating, testing, comparing standard cells that I used extensively in my time as a grad student.  Dr. Mooney's advisor started Synopsys, so standard cells and routing are sort of his speciality.