How can I avoid "Minimum Pulse Width" slack violations in Quartus FPGA synthesis?
I think pjc50 has the right idea; have you edited the .sdc file 
"create_clock" statement?  it has a "waveform" keyword that gives a rise and fall time for the clock waveforem, and the above can happen if these are too close together (e.g. "{ 0.000 1.000 }").  Not to belabor the obvious, but it should be more like "{ 0.000 18.519 }" for a 50% duty cycle and a 27 MHz clock.