Syntax and/or best practice for buffering a vector in Verilog or VHDL
A FIFO will work in most if not all scenarios, but it is not the only solution for multi-bit clock domain crossing. Since the source data rate is low in your scenario when compared to the destination clock rate, it would be well suited to a handshake based system. You would not even need the acknowledge signal.

This article has a decent explanation of the main types of sychroniser and when they are each appropriate. Of course you would need to calculate for the worst case to make sure that there was no chance of missing any data in your particular case.

If your primary goal is to just get it working as quickly as possible, then a FIFO is a great tool, but I wanted to point out that there are others if you are having to scrape around for the leanest possible solution, as I usually am.

I don't understand your system fully, but what I'm imagining is a signal from the serial clock domain that toggles every time it finishes receiving a serial word, with the serial data also being latched into a parallel register at this point (again, in the serial clock domain). The toggling signal would then go through a simple two-register CDC element, where it would then feed an edge detector in the destination clock domain. The output of this edge detector would be a single-clock pulse, which would act as an enable signal for a data register in the destination clock domain, latching data directly from the serial clock domain parallel data register. Assuming your serial words are 8-bits wide, this should I think work with a serial bit clock up to almost double the parallel clock, but you would need to verify this of course.