Differential Pair Length Matching
The answer is driven by the output timing diagram of your ADC, shown here:



The chip provides a clock signal synchronized to the data. The clock falling edge is in the middle of the data valid interval as they leave the chip.

At maximum data rate, the clock period is about 10 ns. 

This means you need to keep all your data signals aligned to the clock, with skew no more than 3 or 4 ns.

Since propagation velocity on the board is somewhere in the neighborhood of 40 cm / ns, this should be relatively easily achieved. To be tidy, I'd shoot for no more than 1 or 2 cm of trace length difference between any data signal and the clock.