Question about PCB layer stackup
Somehow you have gotten things mucked up. There definitely should be a dielectric layer between every two adjacent copper layers. 

However, if you can't figure out how to fix it, it's of little consequence. Altium doesn't manufacture your board, your fab shop does. And your fab shop doesn't need any design data to describe the dielectric layers. They just need to be told how thick the layers should be and what material to use for them.

You can easily draw the stack-up drawing manually into your fabrication drawing layer, and your fab shop should have no difficulty following it. In the past it was even common to give the stack up information in a separate text file rather than in a drawing layer in gerber format.

For example, the drawing can be as simple as this:

------------  Top Layer -- 0.5 oz copper
============  FR-4 0.6 mm
------------  Plane layer 1 -- 1 oz copper
============  FR-4 0.4 mm
------------  Plane layer 2 -- 1 oz copper
============  FR-4 0.6 mm
------------  Bottom Layer -- 0.5 oz copper


Of course, if you like you could specify which layers are cores and which pre-pregs, designate a specific laminate product instead of simply "FR-4", etc., depending on the needs of your design.