Multiplexing cell of matrix
If I assume, each switch is independent, or say, multiple switches can close at the same time, a structure with two levels of mux can be used. A 8 (N) to 1 mux is used for each cell, and another 8 (M) to 1 mux is used for all the cells. The processor needs to set the mux to 00, 01, ..., 0N, 10, 11, ..., 1N, ..., M0, M1, ..., MN, and read each value and decide whether each SW is on or off.