What is wrong with this voltage shifter?
If you look at the Xilinx data sheet, you can see that the input current per pin could be 10 - 15 uA.  So you would have to use a resistor divider network with much lower values, which would in turn mean that you would require more power.

As far as rise time goes, the same thing applies.  The input capacitance is 10 pF, plus whatever capacitance is associated with your board layout and other devices on the trace.  So your RC time constant for the output impedance of your network with the input plus stray capacitance is going to be in the microsecond range, making the rise time unacceptable for a 2 MHz write speed.