How to explain the decrease in the voltage spike due to the resistor in this RL circuit?
When you apply a fixed voltage to an inductor for a set period of time the current through the inductor rises from zero (if previously uncharged) to some positive value. That is what your circuit does; you apply a pulse to the base of the transistor and the collector current rises from zero to some positive value. I'm ignoring whether a 100 kohm or 100 ohm resistor is connected.

When the transistor is deactivated, the inductor still wants to conduct current and, in order to do so, it naturally generates a back-emf voltage that almost instantly rises to a level that can allow the current flow to continue. That current now has to find a path and the only path is via the 100 k resistor or the 100 ohm resistor.

Simple ohms law tells us that the current x resistance equals the voltage generated so, if the resistor value is much smaller, then the voltage generated is also much smaller.

Looking at the 2nd scenario (100 ohm load), the voltage rises to 18 volts the instant the transistor turns off and this makes complete sense. The natural voltage on the resistor will be 9 volts after some time of transistor inactivity but, at the instant the transistor disconnects (after briefly connecting) there is a back emf of 9 volts that takes the standing 9 volts up to a peak of 18 volts.

This comes from the inductor formula \$V = L\dfrac{di}{dt}\$: -

$$V\cdot dt\cdot\frac{1}{L} = di$$

Where V = 9, L = 1E-3 and dt = 10E-6. Plugging the numbers in means that di is 90 mA after 10 us hence, this extra current generates 9 volts over and above the standing 9 volts on the resistor.

There are other circuit nuances that causes the voltage generated when the 100 k resistor is fitted not to be 1000 times the voltage generated when the 100 ohm resistor is fitted. Particularly, the FZT849 is only rated for a maximum collector emitter voltage of 30 volts and in practice, this means your transistor will very likely fail in the 1st scenario. Your simulation may even try and model some breakdown feature of the transistor and that may somewhat limit the peak voltage. There is also collector emitter capacitance that can limit the rise in the 1st scenario.