How is the Q and Q' determined the first time in JK flip flop?
The JK flop can power up in either state. With perfectly matched gates, the odds would be 50-50 for each state. It is up to the rest of the system to initialize to a known, desired state, or to not care about it. Same goes for a D flop.
It’s the same as having an uninitialized variable in a program. Until the variable is set, any values that depend on it (including itself) are not known.
Hardware simulation of this flop would show up as an ‘X’ state until it has had a 0 or 1 clocked into it. Otherwise, it will stay ‘X’ if both J and K are 0 (hold) or 1 (toggle).
In actual hardware (like software), unknown things could happen depending on how the unknown-state output is used.
A variant of this flop has direct set and clear inputs to force an  initial state with separate signals (e.g., reset.) In that case a startup behavior can be defined.
MORE: the logic diagram shown for the JK is crap. This is actually a gated JK latch, and it has a hazard when both J and K inputs are ‘1’ and the clock is high: it becomes a ring oscillator due to the 'race around' issue.
Unfortunately, while the the linked article discusses this, it gives a mealy-mouthed answer about using a very narrow clock pulse to avoid the ‘race around’ issue. This is hugely misleading. Integrated circuit-based JK flops use a pair of latches wired as 2 stages (&quot;master-slave&quot; or &quot;edge-triggered&quot;) and don't have the race-around problem.
Another complaint. The logic diagram given for the 74xx73 type JK is not only incomplete (doesn't show set/reset), it's wrong (74xx73 uses the 2-latch &quot;master-slave&quot; design, not gated latch.) I left a note for the page author for them to fix it.
This answer discusses the JK gated-latch problem in detail. SR FlipFlop Question
And here: JK latch, possible Ben Eater error?