SystemVerilog: Race condition in memory
You do not show all your code but basically:

if (R) begin
    Data_buffer_out&lt;=Buffer[Address_R];
end
else Data_buffer_out&lt;= '0;
if (W) begin
    Buffer[Address_W]&lt;=Data_buffer_in;
end


That code by itself is a race condition if R and W are both active and Address_R equals Address_W.  

It is not bad code, because that is how all dual-ported memories in ASICs++ work. There are two solutions to the problem:


Make sure it never happens.
Catch/recognize the condition and deal with it. 


The former is the case if you e.g. have a FIFO. You normally do not read from a FIFO until after it has been written. In all the years I have worked with dual-ported memories this has been the case in 99% of the code. 

The latter requires you to compare the addresses and 'do something'. e.g. if you see a read and write-clash you could ignore the read result and return the write data. You get some code in along the lines of:

if (R &amp;&amp; W &amp;&amp; Address_R==Address_W)
begin
   &lt;do something special&gt;
else
   &lt;normal action&gt; 


In reality it is a bit more complex and the actual solution depends on if you want to have, read-after-write (Read returns the data being written) or write-after-read (The old data is returned, the new data is written)

++Many FPGA vendors allow you to specify the read-after-write or write-after-read behavior using a parameter when you instance their dual-ported memory block.