Variable Bit shift within 1 Clock Cycle (Verilog)
I don't know if there's a good solution beyond 64 63:1 multiplexers, each one of which is comprised of 21 4:1s or 63 2:1s, depending on the architecture.  If delay time or gate count is a priority for you, you might want to generate something that would clock the register n times based on a trigger event.