How to connect/terminate differential CML logic outputs to single ended ECL logic input?
In comments you said the signal is clock-like (by which I mean switching frequently with 50% duty cycle). In this case you can simply AC-couple one of your two CML signals to the input of your PECL gate.







simulate this circuit &ndash; Schematic created using CircuitLab

If your PECL gate doesn't have a VBB pin you'll have to generate a termination voltage near the switching threshold for the PECL logic.