Upper limits to chip size
It isn't actually all that difficult to design a clock distribution network that can deliver a clock with low skew across quite a large chip. (Look at pretty much any FPGA, for example.)

It also isn't difficult to deal with the latency of propagating data signals across a large chip, using pipeline registers where necessary.

So, the clock speed argument against large chips is mostly a red herring, based on overly-simplistic assumptions.

Using such techniques, systems as large as an entire wafer have been built. They are very costly, so the motivation needs to be high.

Of course, such systems have to deal with the inevitable defects that occur on any wafer, using redunancy and fault-tolerant mechanisms throughout the design.

But it's actually pretty rare to design such a system to operate completely synchronously on a single high-speed clock. Instead, individual subsystems may operate synchronously internally, but communicate asynchronously with other subsystems.