External bus interfacing
What I'm confused about is how the fully address decoded SRAM will differ from the partially addressed i/o ports.


"Partial decoding" simply means that even though each port only requires 1 byte,
it occupies 64 bytes worth of address space.

In other words, no matter which of the 64 possible addresses you use, you're accessing the same hardware port.

On the other hand, the SRAM occupies one block of addresses, and each address within that block accesses a unique location within the SRAM.


  And will the i/o ports have the same address range?


Yes.