Poor clock output from Spartan6 FPGA
Your measurement is not correct.

The duty cycle is measured at 50% (\$\frac{1}{2}V_{dd}\$). So measure again at 1.65 Volt, if \$V_{dd}\$ is 3.3V.

The 'real' high and low times:
- above 90% of \$V_{dd}\$ is high
- below 10 % of \$V_{dd}\$ is low
does not matter. If a circuit has special requirements for the clock or data signal, it defines rising and falling time.

Example: \$t_{LH} \le 5\,ns\$
Rise time from low to high (10% to 90%) should be less than 5 ns.

So the circuit can be sure that the signal is risen or fallen after a predefined time and the signal can be sampled by the input logic.