Carry-lookahead adder - what happens to carry bit?
The carry input for each adder subunit (marked "PFA") is located on the bottom of the subunit schematic. It gets injected via the ripple carry subunit, which is duplicated for each adder unit.

Now I see what the issue is.

The reason the CLC has G and P outputs is for cascading into another CLC so that higher-order carries can be looked ahead (lookaheaded?). However:


  If there are only four bits in the adder, then the
  logic circuit used for C1 can be used to generate C4 from these two outputs; we will
  later refer to the C1 logic block as OC (Output Carry) for generating the output
  carry from an adder, in this case, C4.


So, you need to duplicate the AND and OR gates at the LSb of the CLC in order to get C4 from G0-3 and P0-3.