What does a transistor look like in the Intel 4004 microchip?
I'm still looking for a good cross-section SEM image or similar representation. Until then let's see how close we can get.
UPDATE: Newest results at the end!
Worth watching in YouTube: Engineering History Interview with Ted Hoff
PDF DataSheet:  4004 Single Chip 4-bit P-channel Microprocessor
PDF DataSheet: MCS-4 Microcomputer Set
See Figure 6 (page 34): The_MOS_Silicon_Gate_Technology_and_the_First_Microprocessors
See Figure 6 (page 12): The Intel 4004 Microprocessor:
What Constituted Invention?
LAYOUT and Mask Layers: Complete Artwork, Schematics, and Simulator for Intel MCS-4 (4004 family) microprocessor chip-set: &quot;Together again after 38 years!&quot; and also The Intel 4004 after 44 years! 2015 Progress Report
One of the important elements that needs to be captured in the SEM images to fully answer the question is the use of self-aligned, poylsilicon gates, rather than the real metal (aluminum) gates used previously. The M in MOS (CMOS, PMOS, NMOS) stands for metal and it's important to remember it used to really be metal!

From The Intel 4004 Microprocessor and the Silicon Gate Technology:

The Silicon Gate Technology
The Silicon Gate Technology was the world’s first commercial MOS self-aligned-gate process technology. Before this technology, the control gate of the MOS transistor was made with aluminum instead of polycrystalline silicon. Aluminum-gate MOS transistors were three to four times slower, consumed twice as much silicon area, had higher leakage current and lower reliability compared with silicon-gate transistors. Faggin created the silicon gate technology in 1968 while working in the R&amp;D Laboratories of Fairchild Semiconductor in Palo Alto, CA. He also designed and built the world's first commercial integrated circuit using the silicon gate technology: the Fairchild 3708 - an 8-bit analog multiplexer with decoding logic. The first 3708 was fabricated in July 1968 and demonstrated a substantially improved performance over its metal-gate counterpart (called the 3705) and became commercially available in October 1968.

The article is quite long, here's another excerpt:

A number of innovations were necessary to make this process possible:

A novel process architecture (the sequence of masking steps and their topology.)

Replacing vacuum-evaporated amorphous silicon with poly-crystalline silicon obtained by vapor phase deposition, since evaporated, amorphous silicon did break at oxide steps. In the Bell Labs experiments, the amorphous silicon did not go over oxide steps; this is the reason why only discrete transistors could be fabricated and the process was unsuitable for integrated circuits.

A reliable method for etching the polysilicon material,

The use of phosphorous gettering to soak up the impurities, always present in the transistor, causing reliability problems.


The SGT was also adopted by Intel at its founding (1968), and within a few years became the core technology for the fabrication of MOS integrated circuits worldwide, lasting to this day.

From The Intel 4004 Microprocessor and the Silicon Gate Technology

Paywalled link to IEEE Transactions on Electron Devices ( Volume: 16 , Issue: 2 , Feb 1969): https://ieeexplore.ieee.org/abstract/document/1475473 Researchgate: https://www.researchgate.net/publication/3068458_Insulated_Gate_Field_Effect_Transistor_Integrated_Circuits_with_Silicon_Gates

Earliest papers on the Silicon Gate Technology (SGT) and the Fairchild 3708:
Faggin, F., Klein, T., and Vadasz, L.: &quot;Insulated Gate Field Effect Transistor Integrated Circuits With Silicon Gates&quot;.
The Silicon Gate Technology, developed in 1968 by Federico Faggin at Fairchild Semiconductor, was first presented by Faggin at the IEEE International Electron Device Meeting on October 23, 1968 in Washington DC.

Verified Schematic:  http://www.4004.com/assets/redrawn-4004-schematics-2006-11-12.pdf

From a 2011 post Understanding the Intel 4004 found in IC Reverse Engineering and Other Adventures
Top view optical microscope view, partial deconstruction, one pin interface:
 
Chip select output (?) for external 4002 RAM:
 


From The Intel 4004 Microprocessor and the Silicon Gate Technology
:

From Current 4004 Display at Intel Museum (2014) &amp; Introductory Note

Screenshot from the YouTube video The Designer Behind the First Microprocessor: Federico Faggin

From The Story of the Intel® 4004:

I Found Something!
From  I found some screenshots of similar PMOS device fabrication steps from

Earliest papers on the Fairchild 3708:  Federico Faggin and Thomas Klein.: &quot;A Faster Generation Of MOS Devices With Low Thresholds Is Riding The Crest Of The New Wave, Silicon-Gate IC’s&quot;. &quot;Electronics&quot; magazine, September 29, 1969.
The cover features the Fairchild 3708, the world's first commercial integrated circuit using Silicon Gate Technology, designed by Federico Faggin at Fairchild in 1968.


view cover and page 1
view pages 2 and 3
view pages 4 and 5
view pages 6 and 7




Check the following for Cross-section SEM images:

Paywalled: Silicon-gate technology L. L. Vadasz, A. S. Grove, T. A. Rowe, and G. E. Moore, IEEE Spectrum, p. 28 (1969)


Abstract
Silicon-gate technology provides an advantageous approach for implementing large-scale integrated arrays of field-effect transistors. Its advantages-principally resulting from the low threshold voltage and the self-aligned gate structure buried under an insulator-ease the problem of interfacing these circuits to bipolar integrated circuits and increase both their performance and functional density, making MOS integrated circuits easier and more economical to use. This article reviews recent progress with this technology and shows its application to the construction of complex digital functions as illustrated by a memory circuit.

Paywalled: Silicon gate technology F. Faggin and T. Klein, Solid-State Electronics, 13, 1125 (1970)

Abstract
This paper describes the technology and characteristics of insulated-gate field-effect transistor integrated circuits using deposited polycrystalline silicon as the gate electrode.
After a brief outline of the characteristics of the silicon gate technology, some of the basic properties of the silicon-silicon dioxide-silicon system, the processing steps for the fabrication of silicon-gate devices, and the electrical characteristics of the devices obtained will be reviewed. A comparison between silicon gate technology and standard technology will be carried out, using the 3705, an eight-channel multiplexer switch with decoding logic.
Design considerations for silicon gate technology and some design examples will be given.

Paywalled Metal-nitride-oxide-silicon field-effect transistors, with self-aligned gates J. C. Sarace, R. E. Kerwin, D. L. Klein, and R. Edwards, Solid-State Electronics, 11, 653 (1968)

Abstract
Silicon insulated-gate field-effect transistors (FETs) have been fabricated by processes involving relatively non-critical photoresist and self-limiting etching steps. Important features of the method include the formation of the gate insulator under extremely clean conditions, incorporation of an alkali ion barrier (silicon nitride) to achieve stable device characteristics and automatic alignment of the gate electrode with respect to source and drain. The gate insulator, comprising 600 Å of grown silicon dioxide covered with 400 Å of silicon nitride, is formed at the beginning of fabrication. Thus, the SiSiO2 interface is established at a point where the best state-of-the-art cleaning techniques can be applied to the starting material. A thick (8000 Å) layer of SiO2 is pyrolytically deposited over the nitride to minimize contact capacitances in the finished structure. This must be removed from the active device region, and advantage is taken of the difference in etch rate between SiO2 and silicon nitride to ensure a well-controlled gate insulator thickness. Thus the nitride layer serves the dual function of providing a barrier to mobile ions in the completed structure, and of acting as an etch-resistant layer during fabrication to achieve control over geometry.
A polycrystalline layer of silicon is used to form the gate electrode, which is shaped early in the process, and is used to define the limits of the source and drain windows. This aspect of the fabrication assures self-alignment of the gate electrode with respect to source and drain. During the diffusion of source and drain regions the polycrystalline silicon is rendered sufficiently conductive that no metallization of the gate electrode is required, except at one end for contacting purposes. This eliminates the need for a critical photoresist alignment.
Both n and p induced-channel (enhancement) devices have been made with this process. Turn-on voltages at 10 μA drain current of +1.35 V (n-channel) and −2.6 V (p-channel) with less than 12 per cent spread over a slice were obtained. Analysis of the device characteristics indicates field-effect mobilities of 335 and 233 cm2/V-sec for the n- and p-channel devices respectively. Aging behavior under bias at 300°C indicates the presence of residual mobile positive charge of the order of 1.5 × 1011 charges/cm2, resulting in turn-on voltage shifts of less than 1 V over several hundred hr with +10 V applied to the gate.