How to account for input noise on a zero crossing detector op amp?
Low signal to noise ratio may cause glitches if the device can support sufficient frequency transitions. Also additive noise causes phase noise on zero crossing limiters.  

Hysteresis is generally added when the noise cannot be controlled using positive feedback R ratio. This doesn't eliminate the phase noise but will move the crossing threshold in the opposite away from "zero" each time the output hits the peak.  Often 1% is considered reasonable for some analog signals 10% for others and 33% for noisy logic interfaces.

For single supply amps, the "zero" crossing is set to Vcc/2 by some method.

One can even use CMOS inverter logic as a limiter (aka slicer, aka zero crossing detector)  if the signal is  AC coupled and use a self-biasing high R value (1M) as negative feedback.

The other thing about Op Amps is since they have so much gain and high order delay effects they must put in a cap inside to make the Op Amp essentially a 1st order filter for open loop to make it stable with unity gain.

Comparators on the other hand do not have this compensation cap so they work much faster as zero crossing detectors and ECL comparators work over 1GHz as well as current mode logic but using differential current with zero crossing current and differential load resistors.