Signal Strength to ADC quantisation levels
You are missing that a correctly dithered quantiser is LINEAR, and that there is more then enough uncorrelated noise in the ADC input bandwidth to correctly dither the quantiser. 

You are not digitising just the signal you care about, you are digitising a whole bands worth of mostly uncorrelated stuff, and then reducing the bandwidth in the digital domain. The bandwidth reduction strips off noise outside the range of interest, but that noise includes quantisation noise. 

Every time you halve the bandwidth you gain 3dB on the signal to (total) noise ratio, so that every time you drop the bandwidth by a factor of 4 you gain an effective extra bit. 

If the ADC is running at say 125MHz and you are downconverting to an 8KHz sample rate for the baseband processing then that gains you an effective 8 bits of extra meaningful word length if you do it right, putting the noise floor at about 20 bits or so (The number you want for the ADC is the ENOB, not the output word length). 

If the thing basically follows the HPSDR architecture there is probably also a 1:2 (voltage ratio) transformer feeding the preamp, so another 3dB on the voltage there (But obviously no power gain).