Understanding Test Parameters on Datasheet (CL pF)
For the test conditions part of your question, CL is a specific test load applied to each output to measure parametric data, and a different load is used for different tests.

DUT is indeed the Device Under Test.

At the test circuit, there is a note:

CL = 50pF/150pF or equivalent (includes jig and probe capacitance).

Looking at the device parameters (page 7 in particular), under Test Conditions, you will see CL. Note that the propagation delay and the high impedance to output valid timings are tested with load capacitances of both 50pF and 150pF, with (expected) longer timings with a higher capacitance load.

All other tests are measured with a 50pF total load.

An interesting parameter that you ignore at your peril is in the recommended operating conditions:

Input Rise and Fall Time. There are maximum times listed. This is very well explained in a TI application note, and is a well known issue in CMOS devices.

[Updated for application use]

To use these together, I would operate the counter clocks synchronously (i.e. the counter clock for all the stages is the same clock) and use the application suggestion in the datasheet for gating using the RCO to CCKEN for each subsequent stage.

There will be some timing uncertainty in your measurement results due to the propagation delay from clock to output Q(n) changing state.

The maximum frequency you can run at in cascaded mode is determined by the propagation delay (max) from CCK to RCO (upstream output) and the input setup time (min) of CCKEN to CCK (downstream input)

Together, these have a worst case timing of 80 nanoseconds. That yields Fmax of 12.5MHz