Is it possible to have STD_LOGIC_VECTOR range constraint applied bottom-up?
The best thing is to use generics.  Here's an example entity declaration for a shift register:

entity shift_register is
  generic (n_bits :integer := 8);
  port (clk  :std_logic;
        din  :std_logic_vector (n_bits-1 downto 0);
        dout :std_logic);
end entity shift_register;


When you instantiate this shift register you'd do it like this:

signal data :std_logic_vector (15 downto 0);
...
U0:  shift_register 
  generic map (n_bits =&gt; data'length)
  port map (clk, din, out);


In the entity, I defined the default value of n_bits to 8.  When I instantiate it I could have left off the generic map stuff and then the default value of n_bits would be used.

EDIT:  To better answer your question.  Going in "reverse" doesn't really work that well, and I would avoid it if possible.  But if you must, then you can always declare some constants in your package and use them farther up.  It's not very clean, but it does work.