Is it a good practice to define TRUE/FALSE constants in SystemVerilog?
A good practice is creating a package with a set of global parameters used by your project that you can import. Putting them in a package avoids namespace collisions with other projects or external IP that you might have to integrate later.
`define macros are global and have the problem with namespace collisions and file compilation order dependancies.
const variables are not constants, they are still variables. See Verilog - Use integer constant to define signal width