What is the difference between Machine and Time Cycle in 8085 microprocessor?
A time cycle is one tick of the core CPU clock.  A machine cycle is what the internal state machine of the CPU is doing at the time.

This document explains it all in detail

Basically the machine cycles are:


Opcode Fetch (OF)
Memory Read
Memory Write
I/O Read (I/OR)
I/O Write (I/OW)
Acknowledge of INTR (INTA)
BUS Idle (BI) : DAD
ACK of RST, TRAP
HALT
HOLD


The first one, Opcode Fetch, is described as:


  Each read or writes operation
  constitutes a machine cycle. The instructions of 8085 require 1–5 machine cycles containing
  3–6 states (clocks). The 1st machine cycle of any instruction is always an Op. Code fetch cycle
  in which the processor decides the nature of instruction. It is of at least 4-states. It may go up
  to 6-states.


... continued later ...


  The process of opcode fetch operation requires minimum 4-clock cycles \$T_1\$, \$T_2\$, \$T_3\$ and \$T_4\$ and is the 1st machine cycle (M 1 ) of every instruction.


... and another good snippet that describes the relationship more ...


  It is well known that an instruction cycle consists of many machine cycles. Each machine
  cycle consists of many clock periods or cycles, called T-states. The 1st machine cycle (\$M_1\$) of
  every instruction cycle is the opcode fetch cycle. In the opcode fetch cycle, the processor comes
  to know the nature of the instruction to be executed. The processor during (\$M_1\$ cycle) puts the
  program counter contents on the address bus and reads the opcode of the instruction through read
  process. The \$T_1\$, \$T_2\$ , and \$T_3\$ clock cycles are used for the basic memory read operation and the
  \$T_4\$ clock and beyond are used for its interpretation of the opcode. Based on these interpretations,
  the μP comes to know the type of additional information/data needed for the execution of the
  instruction and accordingly proceeds further for 1 or 2-machine cycle of memory read and writes.


So that machine cycle takes 4 (minimum) time cycles.