Data Rate, Bandwidth and Data transfer Rate - PCIe
The total bandwidth for PCIe depends on a number of factors.

1 The payload size. The maximum payload size specified has implications as each payload is part of a transaction layer packet. The larger the payload size, the higher the bandwidth, but this can have delay implications where a lot of small payloads might be better.

2 The line coding. PCI express version 3 uses 128b / 130b encoding for a 3.125% coding overhead (which is not information). Earlier versions used the venerable 8b / 10b encoding.

3 The overhead traffic.

There are three types of overhead. Datalink layer packets (which are necessary for back pressure flow control and acknowledgement packets between link partners) and the packetisation of the transaction layer packets.

The final overhead is ordered sets, in particular the skip ordered set which prevent buffer overruns for link partners with independent clock sources.

So the bandwidth of a PCIe link is system dependent. The raw bandwidth ignoring overheads is just under 97% of the link rate for PCIe 3. A more typical bandwith is between 70% and 90% of the link transfer rate.

A multi-lane implementation will have identical bandwidth per lane, so it will be lane bandwidth * number of lanes as the data are striped (interleaved) across lanes.

If you know al the details of the particular system, you can calculate the bandwidth pretty closely.

See this application note from Xilinx.