Circuit with two clocks
Multi-phase non-overlapping clocks were (are?) often used in semiconductor logic design.  This is due to the possibility of very large worse case skews (max vs. min propagation) in the rise/fall edges of a single clock's distribution, especially in non-symmetric technologies, such as depletion-mode NMOS (no P transistors).  So two edges of the same polarity are distributed instead.  

Another variation is overlapping quadrature clock systems.