Why pulsed drain current is higher than continuous drain current in MOSFETs?
The main problem of current is that when it runs through a resistance it drops a voltage and hence generates heat, which causes a rise in temperature. A lot of things will break down at a certain temperature (think of light bulbs, fuses).

When the spot where the heat is generated is thermally-connected to something that can quickly absorb a lot of heat and pass it off to the surroundings at a slower rate, a small 'heat-pulse' will not generate much rise in temperature, hence it will not be a problem, provided that it is not repeated too often. In such a case a high current pulse can be tolerated, but is subject to certain limitations (pulse duration, repetition frequency). This type of limitation is typical for a semiconductor that is intimately coupled to a metal tab.

The bonding wire(s) of a chip or MOSFET have a very different characteristic: they are suspended in air (or some other stuff that does not conduct heat very well), hence they have a hard limit on the current, that is almost independent of the pulse duration.

In a datasheet you will often find a graph that expressed the maximum current under various circumstances. In the graph below the DC and 5ms ... 100uS lines show the average-heat limits of the Safe Operating Area. They depend on the VCE, because the heat is generated in the semiconductor area where this volateg drop occurs. The horizontal line at 5A is the DC limit. It is (for a large part) independent of the VCE, because it is about a bonding wire, which is Ohmic (voltage drop and hence heat is determined only by I * R).

There are other limits, like the maximum emitter-collector voltage, that are also expressed in this diagram.