Why don't my programs stay in the FPGA MAX 10 after a power cycle?
You'll need to set up Quartus to produce a POF file.  You can either generate a POF directly or convert a SOF to a POF.  This file can then be loaded into the flash memory.  See page 37 of this document: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/max-10/ug_m10_config.pdf .  Once you have generated the POF file, it can be written to the FPGA internal flash via the JTAG interface with a USB blaster cable.  

There is a similar process for Xilinx FPGAs as well, where an MCS file is generated instead of (or from) a bit file.  The reason this step is necessary is there's really only one way to program the FPGA directly, but there are several different ways of programming a flash chip.  Now, usually it's just the data from the bit file loaded starting at address 0...but there are other options if required.  For example, two different designs can be loaded into the flash chip at different offsets, enabling failed FPGA firmware upgrades to fall back onto a 'golden' boot image.  Or multiple designs on the same flash chip targeting different FPGAs.  Or multiple designs that can be swapped out on the fly (well, more or less).  Or perhaps some extra data is required after the bit file, perhaps a boot image for a soft core that gets loaded into external DRAM.