What is the purpose of fifo in serialize of HDMI?
At lower resolutions, your clock can be at a lower frequency which means that the timing requirements are relaxed when you place and route your design in the FPGA. The issue with higher resolutions is that they require a higher clock frequency, which in turn tightens these timing requirements.

Let's say you wanted more resolution. What do you need to do? You need to increase the rate at which you feed data to your serializers. This is done by increasing the frequency at which you shift data out. As you increase your frequency, the clock period decreases and the amount of logic you can perform in that cycle also decreases. You also need your logic to be placed physically closer together on the FPGA. Your timing requirements just got very tight. Your design tool might not even be able to find a solution that fits on the FPGA since everything would have to be so close together and implemented in very few LUTs. The solution is to have a slower clock domain that "feeds" your fast clock domain. You put your complex logic in the slow domain and minimize the fast domain logic as much as possible. You then communicate between the two domains using a short FIFO to send lots of bits all at once from the slow domain to the fast domain.

Another way commonly used to increase the datarate is by using hard IP blocks that implement the serializer for you (and "fifo" as well, though it's not necessarily exposed as a FIFO). These sort of things are very common these days on FPGAs (take a look at the GTP tranceivers on the Artix-7). You pass it tons of bits at a time (think 60, 80, etc) at some slow frequency and it shifts them out at a far higher frequency. Once you start requiring your data to be shifted out at frequencies exceeding 500MHz or 1GHz you absolutely must use FPGA with this kind of hard IP since FPGAs that can handle a &lt;2ns cycle time on actual logic are quite expensive.