SDRAM: Why CAS latency is configurable
Inside the SDRAM chip, the actual CAS latency requirement is a combinatorial time delay, independent of the external interface's clock period. It may help to think of it as an old-fashioned asynchronous DRAM chip "wrapped" in a synchronous interface.

Since the bus master (CPU) can choose the interface clock speed, it makes sense to also allow it to configure the number of clocks to use for CAS latency, in order to get the best performance without dropping below the amount of time the chip requires internally.