Write into external registers from FPGA
The external component is clocked based on the falling edge of SCLK. However, if you notice, the data is changing on the rising edge of SCLK. In your FPGA driving these signals, you should just update the data output on every rising edge of SCLK. There's no need for you to use the falling edge at all in your design.
The only reason you care about the falling edge is when calculating max frequency/duty cycle, ensuring you don't violate the setup/hold time specifications.