How do we initialise unpacked arrays in Verilog?
Remember, b[7:0] means an array of eight 1-bit numbers. In your example you are trying to initialise it with a single 8-bit number, which is not the same thing.

For Verilog, you have to initialise each element in the array one by one:
b[0] = 1'b0;
b[1] = 1'b0;
b[2] = ...

You could also use a for-loop and localparam to initialise it, by storing the packed initialisation value in the localparam, then using the for-loop to copy it in to your unpacked array. As a bonus, the loop can be parameterised allowing you to change the size of the variable if you desire.
integer i;
localparam b_init = 8'hA8;
initial begin
    for (i = 0; i &lt; 8; i = i + 1) begin
        b[i] = b_init[i];
    end
end

You could also try $readmemb or $readmemh if your synth tool supports it to load a binary or hex file of eight 1-bit numbers.

For SystemVerilog, you can do array initialisation:
reg b [7:0] = '{1'b1, 1'b0, 1'b1, ...};