Using generate to create module ports in systemverilog
This is something that cannot be done in SystemVerilog; actually several things.

You can't use a generate construct in the middle of a another construct, in your case, a module header declaring a port list. And even if you could, you cannot use generate to build an identifiers like logic ready_0, ready_1, etc. Nor could you use it to declare individual elements of an array, like logic ready_[0], ready_[1].

You have several alternatives, the easiest is declaring these ports as arrays.

`define PORTS 4
module mulitplexer
(
  input logic clock,
    output  a_t       multiplx_a_[`PORTS],
    input   a_fc_t    a_multiplx_[`PORTS],
    input   b_t       multiplx_b_[`PORTS],
    input   logic     ready_[`PORTS],
input logic reset
);


You can also create struct with these as fields, but you would need to separate the inputs form the outputs. 
Finally, you could find a macro pre-processor that allows you to write a `for loop as a macro. SystemVerilog does not have that built in.