State of CMOS Inverter
PFET has Vgs=Vdd(source=5V) - Vi   with Vt = -ve voltage
NFET Vgs=Vi (source=0V) with Vt = +ve voltage 

So they are only at the same driver intermediate output impedance to AC ground at roughly Vdd/2 transition output level.  This is by careful logic family design. 


This is at the intermediate voltage level where slew rate and signal integrity is important to avoid multiple transitions, so impedance control on the FETs is important.


Thus at Vdd = max and Vi= 0, or Vdd the RdsOn or Ron is the lowest value and when Vi= Vdd/2 both FETs are conducting and conducting  some current between 5V to 0V.... but typically at same or less current than the PCB + load typical reference load capacitance with Ic=CdV/dt rated for a 15 or 30pF load.  

This means each 74' CMOS logic family must have roughly the same carefully controlled Vt and RdsOn will reduce as supply voltage increases.   

Similarly when logic families are designed for lower voltage, they need lower RdsOn to have faster slew rates but then also limits their maximum supply voltage.  So they may be rated for example; 3.6V max or 5.5V max or 18V max.

This is critical to minimize this shootthru current characteristic. This is a good thing for analog pulses and tends to give the drivers a more constant impedance in the transition between PFET and NFET. but keep in mind the worst case tolerance is +/-50% for these levels which you may compute as  Vol/Iol=Zol.  and (Vdd-Voh)/Ioh=Zoh ( = output V="1" (high V)but low impedance)

However shootthru is  bad for digital half-bridges which must have a dead-band for RdsOn in between Vss and Vdd with high impedance to avoid thermal transition problems.

3.3V logic max was typically 25 Ohms.
5V logic was typically 50 Ohms.
74HC logic was around 1kOHm at 5V and 200~300 Ohms at Vdd max.=18V? 

However like hFE for  BJT's the tolerances of channel geometry affect RdsOn with a wide tolerance of +/-50% worst case.