Low Pass Filter requirements
I need to make some assumptions on ambiguous  "specs".   

Your amplitude jitter is 0.5/5V,  which maybe Vpp or Vp.


let's assume that was Vpp so you have 10% jitter and you indicate that's unacceptable.  But what is acceptable?  


and at what f?  Obviously the jitter in amplitude reduces with rising f.   



Goal: measure Vdc (avg) &lt;&lt;10% jitter pulse 5Hz to 60Hz approx 5Vpp input variable amplitude (0-Vpk) and duty cycle (d.c.)  nominal 50%, no extreme limit, yet. TBD

One method is to have a true integrator in one cycle create the result voltage and assume f does not change rapidly or &lt; 1% per cycle. This is called an Integrate and Dump method or IDC often used in DMM ADC's for high noise immunity.

We know a simple LPF regardless of the order 1st or 4 more LPF's added (9th order) will always add delay or latency to the Vdc avg and that's also undesireable and unspecified.

So let's go with the IDC approach that uses the duty cycle and Vpeak voltage, where the product is the Vavg, DC steady result, regardless of the frequency.

Design motus operandi:

Using signal polarity relative to the midpoint, and edges , control an Integrator with sample &amp; hold to integrate the positive pulse up and negative or 0V pulse down to achieve the integrated average voltage * period.  Since the frequency is required to equalize time and thus a flat constant equal voltage a pulse at 5 Hz requires 10 pulses at 50 Hz to yield the same scaled result.  

This result will be a perfect constant result at the slowest pulse rate of 5 Hz by design choice in 200ms with perhaps 0.1% ripple between the results of a dual S&amp;H between two consecutive samples. 

Gain control to prevent saturation and NPO ceramic or film caps only for the S&amp;H are essential to avoid hysteresis, tolerance and acoustic errors.

Good luck with your specs for latency and ripple tolerance errors.

Mine are: 200ms and 0.1%