When does a register need to get a load control-signal in order to be updated at the next clock?
A register is characterized by a setup time \$t_s\$ and a hold time \$t_h\$. These define a window around the clock event during which the input signals must be stable for the register to be guaranteed to work as expected.

If the clock event happens at time \$t_c\$, the input signal must be at the desired new value before \$t_c-t_s\$, and it must maintain that value until at least \$t_c+t_h\$. If this is done, then the new value of the output after the clock event will be as expected. If the input value changes during the window \$t_c-t_s &lt; t &lt; t_c+t_h\$, then it is uncertain what the new output value will be, and the register may even enter a metastable state where its output doesn't take a legal logic level.



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Any control signals such as LOAD and synchronous SET or RESET inputs must meet setup and hold time requirements in exactly the same way as the data input must.

As a side note, it's also common in FPGAs for \$t_h\$ to be negative, so the entire timing window occurs before the clock event (by at least a few picoseconds). This ensures that when one register feeds another, changing the output of the first register doesn't violate the hold time requirement of the next register.