What can go wrong when producing an ASIC from an FPGA-verified verilog design?
Lots ...

A FPGA verification is just a functional verification or something that you can use to emulate the final chip in system before you get the final Silicon.

There are companies that provide FPGA to Si conversions and they do it via different methods.  Either they have a structure that maps 1:1 to the FPGA structure (really just a metal and routing change)  Or they know how to get timing closure with std cells.

The linked to website is for Std cells, so unless you know what you're doing be prepared to get it wrong. The timing closure, the regressions and constraints used in FPGA synthesis is a subset of what you need to get a Std cell out the door.  So you may have RTL, which certainly will change.  The P&amp;R will be driven by very different constraints than what a FPGA uses.  You'll have to be more explicit and detailed in critical paths than you would in a FPGA.

The debuggablility is a factor of whether you have scan insertion, JTAG interfaces and built in debug support.  If you think you can rely on a probe-station and advanced tools to probe inside the chip you've already lost the game.  MOST signals are not available or are only available once the chip is greatly disabled. And some signals aren't even probable as the capacitance of the probe is too large.

You must design in test from the get go.  Full stop.  So the RTL now is no longer the same RTL you started out with.