Trouble Storing Information in D Flip Flop
Examine the internal logic diagram of 7474 D FlipFlop.
Ou will see 2 cascaded latches (NAND gates with feedback).
The data input affects the first (leftmost) FF.
WHen the clock transitions to be high, the logic state of the first crossed_NAND latch is transferred into the 2nd latch.
This rate of transfer has limitations, because of propagation delays of these various NAND gates.
Examine that logic diagram.