Reliability FPGA depending on its number of gates
As integrated circuits get smaller feature sizes they get less of a risk from failure from single event upsets (SEUs). This is because the single transistor area is less, reducing the chance for a hit by a energetic particle. This makes modern FPGAS less vurnerable to SEUs. 

FIT is usually specified as expected failures per billion hours of operating time. Of course different manufacturers have different testing scenarios, but the number they provide is the same. (yes?)

As an example, look at FPGA/CPLD Reliability from CERN. It is a nice source related to your question and how to make a more reliable system. 

A FPGA with more logical units can provide more reliability and double or triple redundancy. With fewer logical units, you cannot do that. The complexity comes more from the designed functions, and not the architecture itself in my opinion. 

I would say that a modern FPGA with more transistors can be more reliable than an older one. Because reliability is a design goal, and would not regress over time.