Verilog Code: When should I bother making a detailed code if I can make it shorter?
In general, you should not be focusing on optimizing the implementation via the source code — the toolchain is much better at that than you are anyway. And specifying individual gates in the source code is pointless on an FPGA anyway — A function like (s_t &gt; 9) becomes a single 4-input LUT in either case.
Instead, focus on clarity and readability for other programmers, even if that other programmer is you — weeks, months or years in the future. You'll thank yourself later!
When building larger systems, it is the module interfaces that are much more important than their internal implementations. To that end, here are a few rules that I follow, relative to your code:

Don't declare more than one thing per line (module ports, internal signals).
Don't use binary constants if it's the decimal value that is really relevant.
Don't create signals that are never used.
Don't create signals that are only used once unless they improve readability.
You can merge a wire declaration with its assignment in many cases.

With that in mind, I would use your second version, and I would write it like this:
module BCD_Adder_v2 (
  input   [3:0] a,
  input   [3:0] b,
  input         c0,
  output  [3:0] s,
  output        c4
);
  wire    [3:0] s_t = a + b + c0;

  assign c4 = (s_t &gt; (4'd9));
  assign s = s_t + {1'b0, c4, c4, 1'b0};    // Adjust sum by adding 0 or 6
endmodule

Note that I not only declare one thing per line, but I also line up the names vertically. This makes it easy to glance up to remind yourself what the declaration of any given item actually is.