Input and output oapacitor for PoE + DCDC controller
Possibly, the extra capacitance on the reference design is to overcome surge testing to EN 61000-4-5. Although a common-mode test, the applied surge (1 kV or upwards) may not be perfectly balanced by the impedances seen at Vin and Vss and this can easily lead to an excessive differential voltage between them that can blow the pants off the chip. Adding more capacitance between Vin and Vss is a pretty reliable way of limiting this potential over-voltage condition. 

That extra capacitance may also be used to prevent over-voltage/current damage to the piddling little TVS across those two inputs (SMAJ58A).

Given that the output may also route out along ethernet wires (via the magnetics), the same is possibly true for the output port and hence extra capacitance is chosen. You cannot rely on ethernet magnetics for offering much of a block to surge voltages by the way.

Of course, other reasons cannot be ruled out (as well as testing to different surge specifications).