how to compare each and every element with other element of two multi dimensional arrays in verilog?
Before answering the question, some major mistakes need to be pointed out:


Never use blocking delays in synthesizable code. Remove the #100. If you what to put delay between operations, then create an FSM.
A synthesizable for-loop must static unroll. This means the number of loops must be constant. The f is an input so for(i=1;i&lt;=f;i=i+1) should be 

for(i=1;i&lt;16;i=i+1) begin // &lt;-- static loop
  if (i &lt;= f) begin // dynamic condition
    // ... your code here
  end
end

Non-blocking assignments (&lt;=) will update the value in a later stage in the Verilog scheduler (this is used to protect agents hold-time violations). With the code b&lt;=i; memb[i]&lt;=b;, memb[i] will be assigned the old value of b not the value it was just assigned. Often in an edge sensitive always block all assignments use non-blocking, however this practice is only needed for signals that will be synthesized to flops (i.e. D-flip-flips and latches). There are three ways to resolve this:


b = i; memb[i]&lt;=b; Immediate assignments to b. This assumes b in only an intermediate signal. This is not common practice, but it is legal and synthesizable.
memb[i]&lt;=i; assign i to memb[i]
memb[i]&lt;=i[15:0]; Like above but no range warning Best





Now to the actual question: (how to compare)

The main key to doing any comparison (such as finding a max value) is to use is to use conbinational logic.

// Find max
always @* begin
  mem = 16'h0; // initial default value
  for(address=0; address&lt;16; address=address+1) begin
    if (mem[address] &lt;= memb[address]) mem[address] = memb[address];
    if (mem[address] &lt;= memc[address]) mem[address] = memc[address];
  end
end


If you want to flop the value (good idea if the result is an output), then I'd suggest renaming the above mem to next_mem or mem_next (or any other meaning full name), then add a sequential clocking assignment:

always @(posedge clk)
  mem &lt;= next_mem;