Passing input on one pin of FPGA straight out to another output pin for monitoring
Unconstrain the output (set a false path) and the timing violation will go away.
In Vivado you put these in the .xdc file for your design. More about that here: https://forums.xilinx.com/t5/Timing-Analysis/What-does-quot-set-false-path-through-quot-do/td-p/397531
set_false_path is part of the group of tcl commands called SDC, short for Synopsys Design Constraints. Xilinx, Altera and other FPGA vendors adopted SDC some time ago; I recommend this method over the older 'TIG' approach.
SDC is very powerful and a bit opaque, but once you learn it you will have much better control over your design, especially when it comes to constraining I/O timing.