Interfacing static ram to fpga
I assume you're looking at "Read Cycle No. 1". Yes, that's the correct interpretation of the datasheet.

Now you have to worry about the FPGA side, which has its own setup/hold times and delays. If you have enough frequency headroom on the FPGA you don't need to worry much about this beyond basic timing constraints; the tools will abstract things away to some extent. But eventually you will find something that needs to be micromanaged, so it helps to start thinking about these issues now. I suggest completing the HDL side of your project (read those timing reports) before finalizing your hardware design.

Operating an external 100 MHz interface on budget FPGA families is probably going to require some care. You can start low and slow, though, like a few tens of MHz, before really getting your feet wet.