UART Receiver in Xilinx Spartan 6 FPGA
That sure is a lot of code, with no indentation and almost no comments at all. It turns out that it can be simplified to the following form, which is exactly equivalent, and a lot more readable.

module UART_RX (
  input clk,
  input d_in,
  output reg [9:0] D_Out
);

  reg [9:0] Clock_Divider;
  wire Clk = (Clock_Divider == 54); //for 115200 baud

  always @(posedge clk) begin
    Clock_Divider &lt;= Clock_Divider + 1;
    if (Clk) Clock_Divider &lt;= 0;
  end

  reg [6:0] Counter;
  wire Rst = (Counter == 76);

  reg latch;
  always @(d_in or Rst) begin
    if (d_in == 0) latch &lt;= 1'b1;
    if (Rst) latch &lt;= 1'b0;
  end

  always @(posedge Clk) begin
    if (latch) Counter &lt;= Counter+1;
    if (Rst) Counter &lt;= 7'b0000000;
  end

  always @(Counter) case (Counter)
     4: D_Out[0] &lt;= d_in;
    12: D_Out[1] &lt;= d_in;
    20: D_Out[2] &lt;= d_in;
    28: D_Out[3] &lt;= d_in;
    36: D_Out[4] &lt;= d_in;
    44: D_Out[5] &lt;= d_in;
    52: D_Out[6] &lt;= d_in;
    60: D_Out[7] &lt;= d_in;
    68: D_Out[8] &lt;= d_in;
    76: D_Out[9] &lt;= d_in;
  endcase

endmodule


Can you spot the issue described here: UART Receiver glitches? (also here: FPGA starts working after irrelevant changes, why?)