Asynchronous FIFO for fast-write-slow-read
If the average input and output data rates are fixed and different, then you will overflow or underflow a FIFO eventually. There is no 'processing' you can use to avoid corrupting data. 

What a FIFO does is act as a flexible buffer to take up temporary variations in the data arrival and consumption rate. The FIFO has to be deep (long?) enough so that it can store all of the excess data, and a bit more for margin.

If your input and/or output rates are not externally fixed, then you can use the FIFO to control one or the other. A FIFO will have full and empty flags, and the Xilinx ones have programmable 'nearly full' and 'nearly empty' flags as well. These can be fed back to your data source and/or and sink to tell them to wait. The deeper the FIFO, the longer you can allow a difference in input/output rate to persist before having to throttle the faster connection.