Understanding timing constraints
Open the TimeQuest Timing Analyzer by choosing Tools > TimeQuest Timing Analyzer.
Choose File > New SDC file. The SDC editor opens.
Type the following code into the editor:

create_clock -period 20.000 -name osc_clk osc_clk
derive_pll_clocks
derive_clock_uncertainty

Save this file as my_first_fpga_top.sdc (see Figure 1–38).