Can you explain the operation of this RC network for a crystal oscillator?
10M provides the DC input self-centering bias so the CMOS can amplify the signal near Vdd/2 by virtue of negative feedback from the internal CMOS inverter.
The two C’s are designed to match the crystal load rating for centre frequency. (C1//C2)
The 33k reduces the current so that the internal crystal lattice only draws &lt;50uW due to the high density of power limitations on the crystal lattice inside. It does not affect the frequency and the voltage gain in the CMOS now working as an analog amplifier that limits to a square wave.