Digital Logic Design - Sequential Circuits
If you accept that a logic level can be only 0 and 1 it is clear that the circuit must be in one of the two states, because there are no other (stable) states for it to be in.

If you relax this assumption there can be, depending on the transfer characteristic of the inverters, more stable states, for instance all nodes at 1/2.

In practice, an inverter will likely amplify, and that 1/2 state will be amplified towards one of the two stable states. (In theory it could still be at 1/2 forever, this is called a meta-stable state, and it is a real problem in some circumstances.)

How did the circuit arrive at one of the two states? If the inverters amplify, all states above 1/2 will quickly be amplified to 1, and below 1/2 to 0.

In practice there will be more circuitry around your 'memory cell', which can force the cell to one of the states.