How to properly constrain generated clock and synchronizer in Altera Quartus?
Likely, it is because clk4_del2 is not used as a clock (e.g. connected to a clock input of a DFF), but as an intermediate signal... you may even find it gets optimized-out (in your reports?) as it is a continuous assignment.  Unless you use a primitive (clock buffer maybe) and tell the tool not to remove the buffer, and thus the buffer contributes to path delay (and it forces a "name change"), I don't think it will resolve as you intend.

Alternatives, you probably realize already and are only asking because want to keep the RTL as-is, but jic:

If you were to replace your clk_4_77MHz clocked process with clk4_del2 you should find that the constraint resolves properly....  but, then you have the dangling net of clk_4_77_MHz (assuming it isn't used anywhere else) and that is kind of ugly.

If you like your clk_4_77MHz (i.e. it is more descriptive), eliminate the clk4_del2 and replace the assignment: clk4_del2 &lt;= clk4_del1 with clk_4_77MHz &lt;= clk4_del1.

Either that, or just leave everything the way it is and remove the constraint for clk4_del2, and your intent, and the tool's interpretation of your intent, should remain the same.