How many IP can I fit into an FPGA?
The estimate given in the description of the IP core is just that: an estimate. Actual size and layout may vary during synthesis, depending on


other components
stuck signals
timing constraints
optimization level


and possibly a few others. The estimate given for a particular FPGA architecture is usually not that far off in absolute space used, but placement of an IP block will affect placement of other components as well, in a highly nonlinear way.

Thus, your best bet is to try whether your project still compiles to a valid output file, and whether timings can be met.

There is no hard boundary between "compiles" and "no longer compiles", but rather a fuzzy area where it works with a certain probability (and retrying a failed compilation may work), and the higher you go, that number drops towards zero.