Feedback loop in Verilog
I don't see any code that resets K0, K1, and K2, until the load state is used. 

This means that on start-up, these registers have X value.

Therefore the outputs of u_mult1, u_mult2, and u_mult3 have X value.

Therefore the outpus of u_adder1, u_adder2, and u_adder3 get X value.

Therefore on the next clock edge, sum_out_old gets X value. Probably at the same time, the K variables get loaded with their values from the module inputs. But it's too late. Since sum_out is calculated from sum_out_old, it then becomes X, and sum_out_old is trapped in the X state.

The easy way to solve this is to have K0, K1, and K2 reset to 0 when rst_n is asserted (low), but you should consider if this is correct for your situation.