Calculate thermal noise power of receiver
Excllent realworld design challenge.
[ see end of my answer for discussion of the ADC datasheet ]
The ADC has numerous internal random thermal Boltzmann noise generators. And one LARGE correlated variance generator --- the quantization error, which may dominate. And those circuits have finite Power Supply Rejection of trash, so you need to FILTER the VDD pins.
At least ONE noise generator is costly in area and INPUT SIGNAL POWER.
Other noise generators are costly in VDD POWER and in glitching of the internal VDD rails. Thus lowering the &quot;noise floor&quot; of an ADC is a balancing_act.
(A) The input sampling cap (probably 10pF or less), using

V_cap_noise = sqrt(K &amp; T  / C) is exactly 20 microVolts_RMS for 10pF.

Larger sample_hold caps require more signal noise. At 100MHz Fsample and 10pF and 1volt charging transient, the power is P = F * C * V^2
The power DEMANDED FROM SIGNAL SOURCE is 100MHz * 10pF * 1^2 = 1 milliWatts.
Charging that 10pF (may be smaller, for really fast ADCs) must be done with cleanly settling action. Some companies sell SiliconGermanium opamps for this.
Realize the (computed) value of 20uVrms is total integrated noise, spread over the Nyquist bandwidth of the ADC. Does that mean &quot;DC to Fsample/2&quot; ??? You  must decide that.
(B) The comparators that make the binary approximation decisions will have noise in their bipolar or FET transistors. For bipolars, the dominant factor is the rbb' where the input base signal enters the useful region between emitter and collector. For FETs, the standard model for noise is dominated by 1/gm of the FET channel at the operating point (which in transient/decision making will vary wildly); if the FETs have poor layout on silicon, there can be gate_charge movement noise generation, but that noise contribution has been known for decades and should be in the maths.
To predict the comparator noise, use 10GHz noise bandwidth (allows 16 picosecond * 2 for the positive_feedback decision loop, exiting metastability).
And assume high current (several milliAmps) to produce transconductance of 1/1K ohm, thus Rnoise is about 1Kohm, promising 4 nanoVOlts/rtHz noise density.
The total comparator noise is swqrt(10GHz) * 4 nanoColts.
Or sqrt(10^10) * 4 nanoVolts = 1e+5 * 4e-9 = 4e-4 = 400 microVolts RMS.
Thus the comparator noise should dominate.
But what is your Quantization Noise? I think its Vquanta/sqrt(12).
A 1 millivolt quant gives 0.001/3.5 or 0.28 milliVolts CORRELATED noise.
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The datasheet tries to be helpful in this system design.
The full power bandwidth is 575 MHz.
The transition noise is 0.25 Quanta RMS.
The SNR varies slightly with sampling frequency, but is 71dB +-1 dB.
Also read page 23, regarding PhaseNoise.
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The ADC will have a sample_hold input capacitor + FETswitch + optional lumpedResistor.
All of that is just a low Pass Filter  responding to VOLTAGE.