Input clock of a Direct Digital Synthesizer
1) They mean the clock input is low frequency. A 10MHz clock is 'low frequency' in the context of this part, and single ended CMOS should be fine.

2) CLKP and CLKN are 180 degrees out of phase, intended to comprise a differential signal. Generally we like differential signals for clocks because they a) isolate common mode signals and b) have twice the slew rate as a single ended. 

Whether you use a clock driver or not is up to you. The parts they suggest, AD9510 and the like, are clock distribution buffers. If you already have a clean LVDS 10MHz signal, then there's no need to use an additional buffer. If you have a single ended CMOS signal, use that. Use the appropriate coupling for either.

Note the absolute max and min voltages for the clock inputs, they should not go outside the digital supply rail and ground. Choose a rail voltage for your CMOS clock output no higher than that used for the 9102.

A 10MHz clock with a 150kHz output gives you plenty of leeway to design your output anti-alias (aka reconstruction) filter.