ISA efficiency code compaction and memory traffic
As a hint to get you started, here are some possible instruction sequences for the first HLL statement:

Accumulator-based

load A
add B
store A


Stack-based

load A
load B
add
store A


Memory-to-memory (2-address)

add B, A


Register-based

load A, r1
load B, r2
add r2, r1
store r1, A


Your job is to figure out how big each instruction is, and also what the memory access patterns are for both instruction and data operations as each sequence executes.