How to get a low clocking rate by ARTY 7?
Chris is right that clock enables are considered best practice, but if you want a slow clock anyway, you could use a manual clock divider like the following:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clkdiv is
    port (
        clki : in std_logic;
        divider : in unsigned(31 downto 0);
        clko : out std_logic := '0'
    );
end entity clkdiv;
architecture rtl of clkdiv is
    signal count : unsigned(31 downto 0) := (others =&gt; '0');
begin
    process (clki)
    begin
        if rising_edge(clki) then
            if (count = divider) then
                count &lt;= (others =&gt; '0');
                clko &lt;= not(clko);
            else
                count &lt;= count + 1;
            end if;
        end if;
    end process;
end rtl;