PMOS, NMOS length width concept for low power circuit
The width differences arise from the difference in mobility of the electrons and holes with holes being a factor of ~2.2 slower than electrons.

\$ \frac{W}{L} \mu_e = \frac{W}{L} \mu_h  \$

Having balanced \$ g_m\$ on teh PMOS and NMOS will give symmetrical rising and falling edges times. Which is not a necessary condition for low power as you state.  Low power design arises through other mechanisms.