Random Access Memory Modelling in Verilog
I believe you are aware that there are different types of modelling systems in HDLs: 
1) Behavioral modelling - describing the behaviour of the system like a computer program
2) Structural modelling - interconnecting primitive and complex components by signals
3) Mixed - combining (1) and (2)

If you are more into behavioral - use the array representation. It is a best abstraction for "program-like" paradigm. 
If you like more interconnecting existing components - you can model yourself, download or use a RAM from some standard library, that will be represented as a component with inputs and outputs for you.