Understanding CMOS performance and complexity for ASIC : 350nm to 45nm process
For basic info check out the link:  

http://www.msc.rl.ac.uk/europractice/vendors/date2010_imec_foundries.pdf.  

Europractice is similar organization to MOSIS with discount for European academic/research institutions. As a bonus from the link you will get a feeling what does it cost to make prototype.

For gate count per square mm rule of thumb is that each generation of process will double gate density with .18u having around 100k/mm^2 (so .13u should have around 200k/mm^2 and .25u around 50k/mm^2).

However I would never make such important decision as technology choice based on such rudimentary info. You will have to contact prototyping service (mosis/europractice) and get as detailed info as possible. As it is "digital" circuit what would be most important is as detailed info on standard cells as possible. To make things more complicated each technology will have several standard cells libraries available with different options/tradeoffs.

Also  100 picoseconds per pipeline stage sound like typo - this would translate to 10GHz clock frequency, which is out of reach even for most advanced techs. If you meant 100 nanoseconds (10MHz) I believe this is well within 350nm tech capabilities.

Side note:
I admire boldness of you endeavor and wish you success but you have to prepare for significant cost and getting some external expertise. The IC design is orders of magnitude more expensive than PCB design (both engineering and prototyping). Unless you are with academic/research facility and have prospect for sizable grant or VC backing (or VC grade  money for the project) most likely you will not be able to complete it.