SDC Constraint for reset synchronizer
My constraints now look like this:
set_max_delay -to [get_pins -nocase -hierarchical s_rst_sync_ff[*]|CLRN] 10.000
set_max_delay -from [get_cells -nocase -hierarchical s_rst_sync_ff[*]] -to [get_cells -nocase -hierarchical s_rst_sync_ff[*]] 2.500

Besides, I enabled synchronizer identification in the Quartus qsf file:
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION &quot;FORCED IF ASYNCHRONOUS&quot;

With these settings, the design meets timing and all synchronizer flops are placed close together.