Create a pulse that is active from ~0.3 to 0.4 times the clock period
The analog way

The straightforward way is the following:


Convert square wave to harmonic (sinusoidal)
Delay that with a filter
use a comparator with a fixed threshold to achieve your fixed duty cycle


Luckily, step 1 is usually nothing but a low-pass filter (i.e. an RC filter), so by adjusting that, you can implement step 2 just on the way.

The comparator can actually be a comparator IC / circuit, or just a single appropriately biased transistor. 

Advantages


cheap
works with much higher frequencies, too


Disadvantages


relies on analog component tolerances
might hence be intense to tune


The full PLL way


Get a VCO at a nominal frequency N·1 MHz, e.g. N=16
Get a PLL IC, or build a PLL circuit, with a clock factor of N
Discipline your PLL using your 1 MHz clock
use simple binary counters, reset by the input clock, on the VCO-generated clock to implement your delay and your duty cycle appropriately


Advantages


Street cred
much lower jitter and much higher accuracy than RC-filter-based approach
high flexibility


Disadvantages


needs PLL, VCO
design effort might be higher


The lazy digital way


Define an acceptable jitter for output vs 1 MHz input
Get a CPLD or FPGA with an integrated or external clock source >> 1 MHz; the amount by which that clock needs to be higher than 1 MHz depends on the acceptable jitter.
Implement a counter for high-speed clock cycles happening while your 1 MHz clock does one -> period estimate
implement your delay and duty cycle digitally


Advantages


Low component count
small CPLDs and FPGAs are cheap
Digital only: small dependence on environmental specs
high flexibility (you can adjust your 1 MHz as much as you like, as long as the CPLD/FPGA can divide the number of clock cycles just like you want it to, everything is frequency-adaptive)


Disadvantages


Design complexity
quantization of possible delays and duty cycles


The crazy way (a.k.a. Müller proposes a hack)

Your off-on-off sequence can also be implemented by some shift register producing some 0, then some 1, then some 0 again. Let's say you have another clock running at a fixed 10 MHz, and it's good enough.

Just use a shift register (chain) with parallel latchable preload inputs, and a datain/dataout serial interface. Hard-wire the parallel preload inputs to said sequence (which needs no external components, just solder bridges to GND and VCC); hard-wire the datain to ground. You use the rising edge of your 1 MHz signal to latch in the sequence, and use the free running 10 MHz clock to push out the bits to the receiver.

Instead of implementing this using shift register ICs, you can just as well use a microcontroller in SPI slave mode and use the external clock to assert the chip select line (might need further hacking). That would allow for adjustable sequences, and very low integration cost.

What you've then basically built is something like a ROM that contains the signal you want to generate, which you read out sequentially at a higher frequency than your input frequency. You use the input clock to reset the ROM "address" to the beginning of your sequence.

Advantages


I propose this hack
It's cool
Future engineers will be in awe
Did I mention it's cool?
Low component count and cost


Disadvantages


I propose this hack
It sounds cool
The clocks run asynchronously, so this depends on your higher clock being relatively stable in frequency, when compared to your input clock
Might not be trivial to explain