1Hz Sine wave oscillator - Multisim
Let's define the project in a way, I would expect from a Sr. Analog Design Eng with > 5yrs years experience, that I once considered hiring.  With more experience, good measurements in a log book such as AV, vs Rs  vs rise time. 


  1Hz the start time will be 10^3 times slower than 1kHz but use the same number of cycles.  A Xtal Oscillator with a Q of 10k might take > 1000~10k cycles to start up as it depends on the Q and the spectral density of the step voltage or noise in the BW of the BP resonator which is the starting condition for positive feedback oscillation.


All specs @ room temp only 


Vout: Bipolar Sine 1.00 Hz +/-1%    


Amplitude:   +/-2.8Vp min,  +/-3Vp max        
Distortion: &lt;1% THD   

Input:  +/-5V to +/-15Vdc,  1mA max      
start up time: &lt; 20 cycles. 


Eng. Notes:


use a phase shift oscillator that regenerates itself from positive feedback 
positive loop H(f) when Zseries=Zshunt (RC) = 50%  with 180 deg phase shift f=1Hz}     
positive loop gain = 1+|Av|
negative loop gain:    


if Av=-2.0 for huge Q it super long start up time   
if Av > |-10 | , Q is reduced and output saturates even with peak diode feedback giving an ugly pulse wave.
consider Av=-2.1 and then reduce gain to 1.9 when Vout reaches Vp=3V with soft current limiting 


this reduces peak compression and THD
consider using 5mm LEDs for Blue, white which are ~ 3V at 10mA but only ~2.8V at 50uA or so as back to back Zeners




Take 1.


Av=2.1, 1/(2piRC)= 1 Hz  C= 100nF, R= 1.57M  for Falstad Sim only, choose std 0.1% parts later.
Env Range: 20~30'C  Diode temp compensation -4mV/'C not needed.
Use White and Blue LED back to back in feedback, with current limited by R ratio 5 to 10x Rf used for linear negative feedback to get Av=2.1
choosing Rs for LEDs will affect Vout greatly as the VI curve is in the exponential region, well before ESR takes affect thus Vout peak can be tuned with this probably 50% with 50% variation of Rs using Av=2.1  I'll use 3x Rf 
Av is just 5% more than required for oscillation 0.1/2.0 so I expect 5% soft compression which on 10% of the whole signal will be &lt; 1% THD. 




Design Validation Test (DVT)

OK ... 1Hz error  1% max
OK ... +/-3V error 3.5V with Rs (LED)=50k and  2.96V  with 30 k , &lt; 1% error @ 25'C

Other approach I might have done in 1977 with 4yrs experience with CD4xxx logic ( 2yr in Univ + 2yr on the job in Aersopace) CMOS just came out using CD4060 clock binary  and R sine ladder  network using Q4~Q10 as a DAC outputs using 1024Hz relaxation Schmitt trigger clock.   

Here was my Shift Register version before filtering.  (circa 1976)

R&amp;D time 15 minutes.
Documentation 20 minutes.