Altera Cyclone IV PLL: What limits the available multiplication/division factor values
There are several limits on PLLs.  The main one is the VCO output frequency range.  You need to pick divider values that will result in an in-range output frequency.  Second is the PFD frequency range.  This is the frequency range supported by the phase and frequency detector that drives the VCO control voltage.  Usually it's the low frequency end of the PFD range that you have to worry about, you can't divide the reference below this frequency.  

In the case of the Cyclone IV, the input clock frequency range (supported by the input pin and internal routing) is 5 MHz to 265-472.5 MHz, depending on the speed grade, the PFD range is 5 MHz to 325 MHz, and the VCO range is 600 MHz to 1300 MHz (see device handbook vol 3 page 1-24, table 1-25).  So you need to pick divider values that work with these ranges.  

According to the PLL block diagram, there are four different dividers, n, M, K, and Cn, where n, M, and Cn range from 1 to 512 and K is either 1 or 2.  You need to pick these values such that Fout = (Fin / n * M) / K / Cn and Fin / n is in the PFD range and Fin / n * M is in the VCO range.  

Interestingly, it looks like 50*12/25 should work if n=1, M=12, K=1, and Cn=25 as this has a PFD frequency of 50 MHz and a VCO frequency of 600 MHz.  It will not work if n=25, M=12, K=1, and Cn=1, as this has a PFD frequency of 2 MHz and a VCO frequency of 24 MHz.