How to best synthesize a systolic circuit on FPGA?
If your circuit is made of simple logic, it will be difficult to really constraint the design to fit in the FPGA's matrix. You should probably let the FPGA vendor's tools do the work. It you had to make an ASIC, you could really design a cell then copy/paste it over the surface, with FPGAs, you have to deal with the fact that they are not as regular as they seem.

If you use fixed resources like memory blocks or multipliers, they can be more easily constrained (using "LOC" constraints), the remaining logic will be arranged around them...

See Xilinx "CGD" : Constraint Guide