Connected to Multiple Drivers Problem Verilog
Here, the signal BCD0 is being assigned values under 3 separate 'always' processes. Hence the synthesis is returning multiple driver error.
Try moving all assignments of BCD0 signal under a single 'always' process. That will solve the issue. You could use different conditions under the same always block itself to define the behaviour of the signal.

The BCD counter which you are trying to implement is sensitive to clock edges, clear, up as well as down signals. So the process should be sensitive to clock edges and all other signals can be sensed w.r.t clock edges. One way of rewriting the code is like:

always @(posedge Clock) begin  
  if (Clear) begin  
    BCD1 &lt;= 0;  
    BCD0 &lt;= 0;  
  else if (up == 1) begin  
    if (BCD0 == 4'b1001) begin  
        BCD0 &lt;= 0;  
        if (BCD1 == 4'b1001)  
          BCD1 &lt;= 0;  
        else  
          BCD1 &lt;= BCD1 + 1;  
        end  
    else  
        BCD0 &lt;= BCD0 + 1;  
    end  
  else if (down == 1) begin  
    if (BCD0 == 4'b0000) begin  
        BCD0 &lt;= 4'b1001;  
        if (BCD1 == 4'b1001)  
          BCD1 &lt;= 4'b1001;  
        else  
          BCD1 &lt;= BCD1 - 1;  
        end  
    else  
        BCD0 &lt;= BCD0 - 1;  
    end  
  end  
end  


Here, all sensitivity conditions of both BCD0 and BCD1 signal are captured under a single 'always' block which will synthesize it properly.