NAND2 tpHL delay worst case
Assuming that there is some finite rise time for your input signals, I think the worst case would be 00 to 11. You typically measure propagation delays from the 50% point of the inputs to the 50% point of the outputs, so the non-zero transition time of the inputs is important. You also have Miller effect coupling from the inputs to the outputs, which should not be ignored.

By the way, you have the body of Q3 tied to its source. In conventional, bulk CMOS technology the bodies of all NMOS transistors are usually tied to ground. Likewise, the bodies of all PMOS transistors would be tied to Vdd.