How do you design a bare-metal Zynq PS-PL system with an accelerator/coprocessor in the PL?
Can you be more specific about what you want to do with these arrays?  Are you outputting them to the terminal?  What is it that you are trying to accomplish with your design?   Is it something that could be done with a processor only or are you using the FPGA for a specific hardware algorithm?

Have you read the Xilinx documentation or seen the Vivado training videos?  Xilinx has a ton of great documentation and tutorials.  


  -For such a design, what would the programming sequence in the bare-metal application look like?


I would recommend you use the automated tools to configure the FPGA.  You can use the Vivado IP Integrator to configure the internal bus connections with block diagrams.  

This tool will create a design file which can then be exported to the SDK where you can write your C code. The communication between the FPGA and ARM should be done with a data type defined in the generated C header files.


  -What would the structure of the C code used to generate the IP be (for the IP to be able to accept and return arrays using AXIS ports)?


The IP is generated from the Vivedo IP Integrator.  Better use the automated tools if you are new to designing.

Remember the FPGA is a blank slate and must be configured before it is used unlike the processor which is hardwired to Fetch Decode Execute.

Note:  I have used Xilinx ISE and designed with VHDL and IP.  I am less familiar with the newer tools.