Static Hazard in Specific Value or Any changes?
Your teacher is correct, if there is a propagation delay for NOT gates going into the NAND gates. If there is no propagation delay for NOT gates going into the NAND gates, then there would be no Static-Hazard '1'.

Assuming there will be a propagation delay for NOT gates going into the NAND gate, there will only be a Static-Hazard '1' when 'A' goes from 1 to 0. There is not another Static-Hazard '1' when 'A' goes from 0 to 1.

To demonstrate this, I recreated the circuit using VHDL and simulated it.

At 10 ns time in the waveform, you can see 'A' transitions from 0 to 1. However, the output 'F' does not change. At 20 ns, 'A' transitions from 1 to 0. After 1 ns (a propagation delay I programmed all components to have), 'F' changes from 1 to 0 and stays at 0 for 1 ns. After that 1 ns, it changes back to 1. This is an example of Static-Hazard '1'.

VHDL Code: https://gist.github.com/pjbollinger/55e021b6f560fbedac10

Waveform Result: