Bus arbiter that can handle multiple concurrent requests vhdl
If you only have one 'sink,' then you have to arbitrate.  You'll have to apply backpressure to any source that has yet to receive a grant.  If you can't apply backpressure to whatever is generating the requests directly, then the only option is to put in a 'large enough' FIFO on each source and apply backpressure to those FIFOs.  The trick is figuring out how big those FIFOs need to be to eliminate drops - maybe some sources can accept backpressure, maybe some send more often and therefore require deeper FIFOs, etc.  You can usually make FIFOs of depth 16-128 or so using distributed RAM with 1 LUT per bit.  

AXI stream is super simple, it's just a ready and a valid signal that go along with the data.  Valid is high when the data is valid, ready indicates that the sink is ready to receive the data, and data is transferred when both valid and ready are high.  When you connect a FIFO with a 'traditional' FIFO interface, you can map input_ready, input_valid, output_ready, and output_valid onto read, write, full and empty like so:

read = output_ready &amp;&amp; output_valid
write = input_ready &amp;&amp; input_valid
input_ready = !full
output_valid = !empty