Warning while synthesing VHDL code
Whenever you have an asynchronous process that doesn't make an assignment to every output variable in every possible path through the code, you create an implicit asynchronous latch for each variable not assigned. This is what the warnings are about: Each of your PlowLatch_out variables is only assigned in one branch of your if-then-else structure, so a latch is created for each one.

It's possible that this is what you intended, but the problem is that this is a poor design approach for FPGAs. In general, the logic fabric of an FPGA is not fully characterized with regard to the performance of asynchronous state machines (including basic latches), and the design tools go to great lengths to encourage to to make your design synchronous (i.e., with a clock).

You should bring the same clock that drives the ring counter into this module, something like this:

entity PLowLatch is
  Port ( 
    clock         : in   STD_LOGIC;
    ppOut_MUX1    : in   STD_LOGIC;
    ring          : in   STD_LOGIC_VECTOR (3 downto 0);
    PlowLatch_out : out  STD_LOGIC_VECTOR (3 downto 0)
  );
end PLowLatch;

architecture Behavioral of PLowLatch is
begin

  process (clock) begin
    if rising_edge(clock) then
      if (ring(0) = '1') then
        PlowLatch_out(0) &lt;= ppOut_MUX1;
      elsif (ring(1) = '1') then
        PlowLatch_out(1) &lt;= ppOut_MUX1;
      elsif (ring(2) = '1') then
        PlowLatch_out(2) &lt;= ppOut_MUX1;
      elsif (ring(3) = '1') then
        PlowLatch_out(3) &lt;= ppOut_MUX1;
      else
        PlowLatch_out &lt;= "0000";
      end if;
    end if;
  end process;

end Behavioral;