Where reset happens with SR flip-flop
The reset, given the truth table you provided, happens just because the state 11 of the state machine is mapped in the state 00; in fact, if you look at the outputs, both states have the same next state, so if the inputs are 00 (buffer), from the state 11 it will go to 00.
An optimization of the machine would use the Mealy topology, where you map the state 11 in 00 just changing the output if coming from an activating sequence.
Update
You can udnerstand it better using the diagrams:
Moore:

Small error: the arrow that goes from (10) to (11) is for both the inputs 01 and 10 
Mealy: