ADC - LVDS/LVCMOS Interface
Per the datasheet, the pin functionality of the clock input does not change regardless of which mode you are using:

The clock signal is always a differential input. However it is possible to drive it from an LVCMOS signal by AC coupling and applying a DC offset as shown later in the datasheet. The LVDS/CMOS mode selection has no bearing on this ability.

In this configuration (single-ended input) you are actually making a pseudo-differential signal with a common mode offset that keeps changing, though the performance of this will be worse in terms of jitter performance and is not recommended for high speed sampling.