inout port in VHDL RS232 Module from Digilent
In VHDL, if a port is declared "out", it can be assigned to, but it can't be used elsewhere inside the module. Specifically, the assignment on line 155 would be flagged as an error:

OE &lt;= RDA;


Making the port "inout" makes this usage allowable.

However, inout ports are "messy" for a number of reasons, and I try to avoid them wherever possible. Another approach is to declare a second copy of the signal (e.g., RDA_int) that is used everywhere inside the module, and then to assign that signal to the output port just once.

RDA &lt;= RDA_int;