Why are transparent latches discouraged / encouraged in digital design?
To understand why an unclocked component of any kind is discouraged in sequential digital design you need to understand why a clock exists in the first place.
The clock keeps things in synch and makes it easier to design for. With no clock you have to rely on the delay between components matching up with each other so signals arrive at their next destinations neither too early nor too late (i.e. at exactly the right time). With thousands of branches and paths that are always changing, this is really difficult for very large circuits.
With a clock, everything just needs to arrive at its destination faster than the clock.
Since a transparent latch is not clocked, it is a bit of a renegade when using it amongst clocked components since it can allow signals to change when the clocked components are not expecting it. You can get away with it sometimes at the input or output of a system where things are more predictable, but in the middle of a system is often no good. It's about manageability of the timing. If part of the system is simple enough so you know what is going to happen, you can get away with it.
In FPGAs, specifically, transparent latches are discouraged because their timing is uncontrolled and FPGA architecture does not support them well so it produces unpredictable results.
Latches are a form of memory, be definition, and combinatorial circuits do not have memory by definition. But you can have simpler, unclocked, sequential circuits where the timing is more manageable. That's where transparent latches can be useful.
They are also useful to shield noise between circuits like ADCs, but that isn't digital logic design.