Confusion about open-drain for I2C
Your reasoning isn't quite right. The open drain configuration is used so that any line can be an output and an input, even both at the same time.  So, to read the state of SCLK you look at SCLK IN.  If you want to drive SCLK you drive SCLKN1 OUT.  Obviously, if you drive SCLK low, you will read back a low signal. But if you &quot;drive&quot; it high (actually  you release it), then by reading the input you can find out if it really is high, or if another device has driven it low.

It is difficult to tell from your comments where the misunderstanding lies.  So let's look at a few facts to see if we can find it.

The drawing doesn't say which device is master. Either one could act as master.  Or a master may be somewhere else but not shown.  From a protocol standpoint it doesn't really matter which it is.
Each device is going to have the necessary circuitry to read the IN's and set the OUT's.  This may be a micro controller (mcu), but doesn't have to be.  Let's assume they are, for simplicity.  Wherever the master is, it has an mcu there, connected to its INs and OUTs, and no one else's.  The only things tied together are the bus signals on the other side of the buffers and FETs.
The meaning of OUT is, &quot;I want to OUTPUT a LOW state on the bus&quot;.  Choosing the name of a signal presents many choices. Consider that the software executes an out instruction that sends out a signal on an I/O pin, which is then routed to the input of an FET, which responds by sending out a low signal on the bus, where the other devices look at the signal routed into the read buffers, which output the state of the signal to the mcu I/O pin that's configured as an input to read in the state.
The notion that the master is the only one driving (outputting to) the bus is incomplete. The slave device will drive SDA low to create the ACK.  It will also control SDA when data is being read from it.  In addition, devices have the option of pulling SCLK low if they need more time to get their data ready.  The master releases SCLK to high and if it doesn't read back as high, then &quot;clock stretching&quot; is in effect. This is slightly more advanced, but it is very real, especially if the slave device is operated by an mcu.

So, in the big picture, each device must be able to control both bus lines, and be able to read their state back at the same time.  And make sense of it all.