SDR over DDR memory in FPGA based design
This seems like an XY problem.
Nevertheless, I'll answer:

DDR DRAM part types are more available (SDR is becoming / has become obsolete)
SDR is not cheaper. Not on a per-bit or per-device basis. It's considered specialty now.
You still need to route carefully for timing reasons, be it SDR or DDR
DDR uses source-sync timing which is much easier to meet. SDR uses system-sync, which faces skew problems
Lower power (DDR is made on smaller device nodes than SDR)
Available reference designs (Zynq, etc.) use DDR.

As far as the I/O voltage, it's not such a big deal to place the DRAM pins on the appropriate banks (e.g., 1.8V for DDR2) and power them separately. Suitable DCDC regulator ICs for this are very cheap (1-2A, less than 10 cents in volume).
And differential routing should not be a stumbling block. This only affects DQS and CLK. That's two pairs. In return you get better timing.