Bounded time synchronizer
The synchronizer doesn't fix the problem. That's the point.
With an input that fails setup or hold, some percentage of the time the flip-flop will have an unknown state.  The 'unknown' state is sometimes called metastable, where the flop fails to properly resolve to a 1 or 0.
More about all that here: http://www.asic-world.com/tidbits/metastablity.html
How often a metastable event occurs depends on the data rate, the clock rate and, how 'crunchy' (metastable-hard) the flip flop is. Flops designed to be metastable-hard have low internal delays, that is, the window between setup and hold is small.
The failure rate for a flip-flop can be computed as follows:

MTBF = 1 / (Fin * Fclk * Td)

Where:

Fin = signal input frequency
Fclk = clock frequency
Td = flop propogation delay (Setup/hold window)

It is possible to use multiple synchronizers in series to mitigate the results of metastability in the first flop. But it will always be there.