Bias common source diode connected load
In order to keep M1 in saturation, 

Vg - Vth = Vd for M1 to just be at the edge of saturation is the upper limit.

So,

The drain voltage needs to be equal to or higher value than gate voltage which brings us to :

Vg - Vth &lt; Vdd -Vd

Thus,  Vg &lt; (Vdd + Vth) / 2. (at the GATE node)

So, the gate node needs to biased satisfying  the above condition probably using a resistor divide bias.

The small signal voltage is then coupled at the input so that dc bias does not get affected.

The input gets amplified by a factor which is independent of the transconductance of the MOSFETs.

Gain = - sqrt((W1/L1) /(W2/L2) ). ( independent of gm is a good thing)

Replace the diode NMOS with a PMOS, you can get even higher gain because of the mobility factor in the expression. 

DEMERITS:

However, the major problem with the above circuit is that the SWING is constrained by both the overdrive voltage and the threshold voltage because
if you replace W/L by the overdrive voltages in the expression.
Then,

GAIN = (|Vgs2 - Vth2|)/(Vgs1 -Vgs2).

So, if for transistor M1, say  overdrive =200mV then it would require 
|Vgs2| =2.7 Volts for a mere gain of 10 which clearly indicates the severe limitation on the output swing!