Why does it take 2 clock cycles to move to the RESET state in my state machine?
I think the problem lies in this part

always @(posedge CLK)
begin
    if (Reset_L==0) SCURRENT &lt;= A;
    else SCURRENT &lt;= SNEXT;

    case (SCURRENT)
        A: Y&lt;=9'b000000001;
        B: Y&lt;=9'b000000010;
        C: Y&lt;=9'b000000100;
        D: Y&lt;=9'b000001000;
        E: Y&lt;=9'b000010000;
        F: Y&lt;=9'b000100000;
        G: Y&lt;=9'b001000000;
        H: Y&lt;=9'b010000000;
        I: Y&lt;=9'b100000000;
        default: Y&lt;= 9'b111111111;
    endcase
end


From my understanding of Verilog and the testbench I created to test your code, I think that what is being executed in parallel is:

posedged(k) (if || case) ----&gt; posedged(k+1) (if || case)


where the first posedged sets 

SCURRENT(k+1) &lt;= A, and 
Y &lt;= X. (where X depends on the original value of SCURRENT(k))


and the second one does

SCURRENT(k+2) &lt;= A, and 
Y&lt;=9'b000000001. (since  SCURRENT(k+1) is A)


What you probably intended to do is

always @(posedge CLK)
begin
    if (Reset_L==0) SCURRENT = A;
    else SCURRENT = SNEXT;

    case (SCURRENT)
        A: Y&lt;=9'b000000001;
        B: Y&lt;=9'b000000010;
        C: Y&lt;=9'b000000100;
        D: Y&lt;=9'b000001000;
        E: Y&lt;=9'b000010000;
        F: Y&lt;=9'b000100000;
        G: Y&lt;=9'b001000000;
        H: Y&lt;=9'b010000000;
        I: Y&lt;=9'b100000000;
        default: Y&lt;= 9'b111111111;
    endcase
end


Where the case will be evaluated after the if being "executed", and since mixing blocking and non-blocking statements can lead to problems synthesizing, use this to sort it all out,

always @(posedge CLK)
begin
    if (Reset_L==0) SCURRENT = A;
    else SCURRENT = SNEXT;

    case (SCURRENT)
        A: Y=9'b000000001;
        B: Y=9'b000000010;
        C: Y=9'b000000100;
        D: Y=9'b000001000;
        E: Y=9'b000010000;
        F: Y=9'b000100000;
        G: Y=9'b001000000;
        H: Y=9'b010000000;
        I: Y=9'b100000000;
        default: Y= 9'b111111111;
    endcase
end