Help needed with SPARTAN-3AN FPGA frequency doubler
Basically what it is saying is that there is a fast path (a direct connection) from certain pins into the DCM but for some reason this fast path can't be used.  This could be for a number of reasons.  If I'm reading the datasheet right, P53 isn't a clock capable pin so there won't be a fast path.  You can also get problems if you've LOC'd the DCM to the wrong site in the UCF or you are using many DCMs such that the ideal site isn't available.  Looking at your project though, it looks like this is the only thing in the design?

Where did you get the PAD53 constraint for the input clock?