Difference between implementations of a 4 bit counter in verilog
The two codes produce identical output, so it's down to your synthesis tool whether they produce the same implementation.

With the first one, the synthesis tool may be more likely to co-optimize the logic to produce the 4 output bits.

With the second one, the synthesis tool may be more likely to use special-purpose hardware (like fast carry chains in FPGAs).

But in principle, either code could be implemented with any logic that produces the correct outputs.

If you really need to know which one produces better results (depending what you consider better), you need to try both on your synthesis tool and compare the results. I think it's quite likely that for an FPGA implementation on current FPGAs, you get the same result (one LUT and one flip-flop per output bit) with either code.