Is using floor plan tool during FPGA design ever actually useful or required?
Since nobody has answered, here are a few things you can do in the floorplanner (my experience is with Xilinx tools, but I expect the others are similar):

Verify &quot;visually&quot; that some particular resources have been used. For example carry chains, block RAMs, clock management tiles, etc.

Verify that highly interconnected logical functions have been placed where they can communicate using local rather than regional or global routing resources.

Verify that logic sharing the same clock has been efficiently placed with respect to clock routing resources.

Visually edit the connections to the debug logic


Many years ago, I manually placed certain logic very close to the associated I/O blocks to obtain the fastest possible I/O. I don't know if this would still be necessary or helpful.