What is the least expensive way to build a three-bit shift register?
Your description reads, in part, "when (shift) goes high ..." &mdash; this describes edge-triggered behavior, so yes, you need master-slave flip-flops to hold the internal bits.

You can also do something like this using dynamic logic, where each stage consists of a capacitor, a buffer and a transmission gate. This would be driven by a 2-phase (non-overlapping) clock. But it still requires two such stages for each "bit" of storage.

But if all you're looking for is a large FIFO buffer, then an actual shift register is not the preferred implementation. Instead, use a block of RAM (either SRAM or DRAM, with the understanding that DRAM will also require refreshing) along with a pair of counters to keep track of the current write ("head")  and read ("tail") addresses. Increment the counters to logically "shift" the data.