ICL 7673 circuit Hysteresis Resistor values
I solved the problem. Design the hysteresis network (assuming Vs+Hys>Vp).

I needed 0.5V Hysteresis. So, I designed the circuit for 0.5V drop across Rs. The catch in the design is I needed to design the Rf to sink enough current into the Sbar internal FET so the FET will operate in saturation always. 

The best part of this circuit is the hysteresis circuit is selectively connected or disconnected by the Sbar FET.