fpga multiplexor - select line controlled by a soft processor
This is demultiplexing, not multiplexing. You're routing fewer paths into more, not more paths into fewer.

You don't say if the pins without the input routed to them will (a) be tri-state or (b) be at a fixed level.

The circuit for (a) would connect inputs to both outputs, then use the mux control to enable the tri-state drivers on the two output sets. One set would be enabled while the other set was disabled.

The circuit for (b) would connect the each input to output set 1 through a logic gate, with the same done for output set 2. The mux control would switch the logic gates to a fixed level on one set while letting the other set flow through. OR gates would let the unused output set be driven high, AND gates let it be driven low, or you could produce some other pattern.