how to handle a data set with negative values in verilog?
Proper use of the new signed capability in Verilog 2001
can be summarized by a few basic rules.


Investigate fully all signed to unsigned conversion occurs. (VER-318)
synthesis warnings. These point to incorrect functionality
All signed operands will be signed extended to match the size of the
largest signed operand.
Type casting using $unsigned will make the operation unsigned. The
operand will be sign extended with 0’s if necessary.
Type casting using $signed make the operand signed. The operand will 
be sign extended with 1’s if necessary.
Pad the operand with a single 0 before the cast if this is not
desired. Expression type depends only on the operands or operation,
it does not depend of the LHS of the expression


Reference :
http://www.tumbush.com/published_papers/Tumbush%20DVCon%2005.pdf