Which pins belong in a "I/O region" on a MAX II CPLD?
The best interpretation I could think of is based on the words I/O between GNDIO pads: all the pins whose numbers are in between two consecutive GNDIO pins belong to the same I/O region. Look at the pinout files to find out the pin numbers for a device. E.g. for an EPM570 in TQFP100 package, the regions are:

pin 1 to 8 and 95 to 100
pin 12 to 30
pin 33 to 44
pin 47 to 58
pin 61 to 78
pin 81 to 92

Beware that regions 1 and 4 has pins controlled by different I/O banks. It's unclear which VCCIO/GNDIO pair belongs to each I/O region, so this interpretation may not be entirely correct.