Should I gate SCRs on when reverse-biased?
From an Infineon app note, page 19, 3.3.1.1.


  Thyristors shall only be pulse triggered during the forward off-state phase. 
  Positive trigger pulses during the reverse off-state phase will lead to significantly increased off-state losses due to the transistor effects caused. These losses adversely affect the functionality and may lead to destruction.
  Exception: For light triggered thyristors control pulses during the reverse off-state phase are permissible.


Infineon has told me that they can't really quantify the additional losses because it depends on reverse voltage, junction temperature, part number, and the exact unit you happen to have.

I also received this from SanRex today:


  When the SCR is reverse biased and a gate signal is present, reverse leakage current will go up typically by 10 times or more.  This increased reverse current will cause over temperature on certain areas of the die, which will deteriorate the die itself.