What is the precise use of a memory controller and RAM latency?
A dedicated memory controller is mandatory for several reasons (built into the CPU or not). Because it is dynamic memory each memory cell has to be 'refreshed' with a strobe every 16mS or so. With some Dram chips having gigabytes of storage, the CPU would spend all of its time refreshing the Dram. Using timed latency or handshake signals (still a known latency - or delay time to refresh the DRAM) the DRAM controller lets the CPU know when it can read or write to the DRAM. The memory controller also handles another complicated chore, and that is allowing other devices such as a LCD driver chip to have access to the DRAM if the CPU is not demanding access. This priority tree built into the DRAM controller allows several devices besides the CPU to 'have their turn' to access the DRAM. Synchronous simply means the CPU and DRAM controller share the same clock, or the CPU supplies the clock for read/write request.Synchronous can allow data to be moved in short burst, improving data transfer speed.Dram memory cells use just one transistor and one capacitor to 'hold' the state (1 or 0), so a fast refresh pulse to each cell is mandatory, or the cells will forget their state and cause a CPU crash.  About 30 years ago when DRAMs first came to market crashes and data loss were common.