VHDL UART core transmitter bits
The design is hard-coded to send 11 bits per byte. tx_ctr_bit runs from "0000" through "1010", inclusive. So it's obvious that the designer wanted two stop bits per byte.

It is, however, a bizarre choice to send the extra stop bit at the beginning of the byte rather that at the end (i.e., tx_data &lt;= "11"&amp;data_i&amp;"0";). All that does is to increase the latency of the transmitter &mdash; when the system wants to send a byte, the start bit comes out one bit time later than it otherwise could.



Another odd thing is the initialization value for tx_data:

  if reset='1' then
    tx_data &lt;= "10111111111";


Why is the 0 bit in there? It doesn't really matter, because this data is never used anyway (except for the LSB, which sets the idle state of the output), but why not just set it to all ones?