shift registers/d flip-flop memory states
It's not clear how you intend to "stop the input stream".  In a synchronous circuit like this, there is really no way to stop an input from existing at D.  All you can do is stop clocking the input through.

Some D-Flops have an enable pin that will disengage the clock and make it possible to allow the clock to run in the rest of the circuit without affecting the output.  If there isn't an internal enable, you can create one externally using an additional logic gate.  If you disable the clock, then the value at the D input will have no affect on the rest of the circuit.

If you clock the flop, and it is enabled, it will capture the input and shift it through, destroying the previous state.  If the input is 0, the output will be 0 after a clock.  If the input is 1, the output will be 1 after a clock.  If you disconnect the input and leave it high impedance (let it "float"), then the output will be unpredictable (and possibly metastable) after a clock.