Verilog output is hiZ in testbench
You declared the out signal as a wire in your testbench, and you connected it to the out output port of your mux module.  However, the out signal in mux is undriven (it is not connected to anything else).  In Verilog, wire signals default to the z value.

In mux you have an undeclared signal named outX.  Is this X a typo?  In other words, out and outX are two different signals.  If you rename outX as out everywhere, the out will be connected.

UPDATE:  You have confirmed the X was a typo, and updated the Question accordingly.  That problem is solved.

Since you added the inv/and/or module code to the Question, we can see that you try to connect 2-bit signals to 1-bit ports in your submodules. For example: w4[1:0] to i1 in inv2bit.  You need to change the port declarations to be 2-bit wide, such as:

input  [1:0] i1;
output [1:0] out;