Cache. MESI protocol for multilevel cache in Intel processors
I guess your question is about how a coherence protocol extends to multi-level caches. This book is a good reference. Here's my understanding:

Ill take the example of Core i7 (as I'm not very familiar with core 2 duo architecture). 

In Core i7 every core has a private L1 and L2 cache, and all cores share a single large on-chip L3 cache. One can in-turn join multiple such processors using point-to-point links to form a NUMA system. 
So there are 4 levels in the memory hierarchy: L1, L2, L3, Main memory.

There is one coherence protocol between multiple L2's on a chip and the L3.
There is a separate protocol between multiple L3's on separate chips. The two are independent of each other. One may use snooping, and other may use directory-based implementation. I think in Core i7, both are directory-based MESIF protocols (F is a new Forward state). 

All caches in Core i7 are inclusive. This simplifies the protocol somewhat.
As L2 is inclusive of L1, a block that is evicted from L2, has to be evicted from L1 too. Similarly, a block evicted from L3 has to be evicted from all L2s.
L3 maintains core_valid bits for each block. A core_valid bit is set if the L2 cache of that core has a copy of the block. This way when a block is evicted from L3, the invalidations need to be sent to only those L2s that have a copy of the block. I guess the core_valid bits also act like a kind of directory.
If you have inclusion, only the coherence messages for blocks existing in a lower level cache need to be forwarded to the higher level cache. So the lower level cache acts like a snoop filter.

I'm not sure I understand your question about the non-exclusive policy. Maybe this link will help.