Divide by integer in VHDL
This answer isn't what you're looking for, but the basic solution to this problem is this: Don't use division.

Many processor architectures and even DSP chips do not have a division instruction at all, and where they do have division, it is usually a multi-cycle operation, because division is fundamentally iterative. Division is expensive in terms of area, and slow, so it is usually avoided if possible.

I strongly suggest that yourself or anybody reading this question tries very hard to avoid implementing a hardware divide function of any sort, let alone a single-cycle one. As some comments have said, the standard approach would be to implement a multiplication by the reciprocal of the divisor. Even here, if you expect good performance in your FPGA, this would be implemented using a pipelined architecture, and so would not have single-cycle latency.

An even better solution would be to revise your design such that there is no need for any division or an equivalent. However, without knowing what your design is supposed to do, it's impossible to suggest alternatives.

As a footnote, and as a comment noted, division by a power of two is relatively simple, because it boils down to a shift operation.