What's the point of putting two NOT gates sequentially?
Answers: 


Yes
They want to emphasize that the input signal is active high or active low
There is probably that circuit inside (or certainly something very close to two CMOS inverters), to buffer the input, so the input does not have to drive all the flip-flops directly and has no more capacitance than any other input. Also it's frequently required to generate clock and /clock signals inside CMOS logic. Also, as Ignaciao mentions- to sharpen up the edges on the clock signals (not so important on the other inputs).