8051 ADXL SPI interfacing
The ADXL345 Datasheet Rev E page 15 states "the timing scheme follows clock polarity (CPOL) = 1 and clock phase (CPHA) = 1". Make absolutely sure none of the timing limitations are violated. This chip in particular must follow the minimum and maximum timings shown on page 17. A digital-storage oscilloscope (preferred) or logic analyzer may be very helpful for troubleshooting.