Logic network with NAND gates
First we should divide our problems to smaller parts. 

We should begin from a symbol which has a lot of lines over it, in this case it's \$\overline{X_1}\$, but in the schematic there is no \$\overline{X_1}\$ found so it's first error.

Then we draw(track)  \$\overline{\overline{X_1}X_3}\$, then we draw(track) \$\overline{X_2}\$ and so on to reach our function \$Y\$

Using these steps will make you analyze the problem and discover errors faster!.

I think schematic should be like that:



Here is the schematic after editing it.



But I think you'd better simplify the boolean equation algebraically then try to draw our schematic. If we simplify it we will get
$$
Y=X_1+\overline{X_2}\,\overline{X_3}
$$