"Power On Reset" on CD4026 IC
Your power on reset circuit doesn't make sense. The reset pin is always tied to ground via the resistor.

This is a conventional power on reset circuit for pulsing the reset pin high at power on to reset a 'reset pin high' chip. When power is first applied, both sides of the discharged capacitor rise to Vdd. Then the capacitor charges through the resistor and its lower plate drops to 0V releasing the chip. The diode prevents the reset pin going more than 0.7V below ground at power down thereby protecting the IC's input.

For a 'reset pin low' IC. The positions of the capacitor and resistor would be swapped and the diode omitted. 







simulate this circuit &ndash; Schematic created using CircuitLab

EDIT

Your first guide is incorrect because the RC reset circuit doesn't provide a power-on pulse to the reset pin. The second guide RC reset circuit does.

Your concern about the slowly transitioning reset pin in my original circuit is a valid one and this could cause problems in certain situations. As the capacitor charges, the reset pin falls slowly and this could take the chip in and out of reset multiple times during power up possibly causing glitches at the chip’s outputs if it is being clocked during power up. This may or may not be a problem to you. My circuits below get around this potential problem by including Schmitt triggers to cause a ‘snap’ transition of the reset pin.



The bottom reset circuit is for when there are both ‘reset low’ and ‘reset high’ chips in the circuit.

You can use the top circuit of the three and reset the chip, via one input of the 4093 schmitt nand, whenever you want to.