DSPs: Can I perform floating point division in a Xilinx DSP48?
I don't know which Xilinx device you're targeting, but here's an overview page of the Xilinx DSP blocks:


XtremeDSP 48 Slice


There's a small section about division in the Virtex 5 XtremeDSP user guide (p.74), for example:


Virtex-5 FPGA XtremeDSP Design Considerations


However, your best bet is to create a divider using 'coregen'. Launch 'coregen', create a new project and go to 'Math Functions -> Dividers' (the options appear depending on the target device). Then go through the wizard choosing your preferred setup.

Here's a bit more information on how to use 'coregen': 'coregen' will create a '.v' or'.vhd' instantiation file depending on the language you've chosen. It will run XST to generate a '.ncg' "blackbox" netlist so the implementation process can include it when you run 'ngdbuild'.

Now, coregen will also generate a '.xco' and '.cgp', which are the only files you actually need (in ISE version 12.x) in order to regenerate the core. In command line, do

coregen -p &lt;core&gt;.cgp -b &lt;core&gt;.xco


and you'll get the HDL instantiation and the netlist (and a bunch of other things in the process). Note that 'coregen' will generate its output where the input files are, not where it is invoked from, and there's no switch to indicate an output path!