SDC constraints for reusable component
You can specify SDC commands inside of your VHDL code with ALTERA attributes. The PoC Library is using this to apply relative timing constraints for synchronizers:

architecture rtl of sync_Bits_Altera is
  attribute ALTERA_ATTRIBUTE  : string;

  -- Apply a SDC constraint to meta stable flip flop
  attribute ALTERA_ATTRIBUTE of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers {*|sync_Bits_Altera:*|\gen:*:Data_meta}] """;
begin


Source: https://github.com/VLSI-EDA/PoC/blob/master/src/misc/sync/sync_Bits_Altera.vhdl?ts=2

I think you could do a similar approach for your generated clock.

Please note, that c0 does not fulfill all requirements to be a clock signal.