What is the use of pull-down networks in CMOS gates?
No, you wouldn't have ground voltage, you would have a floating or undefined voltage. This could cause havoc with the input to the next stage if it is a CMOS input. Its input impedance is so high that its input capacitance could hold it high when you switch off your arrangement. It would also be susceptible to stray electrical noise and switch randomly.







simulate this circuit &ndash; Schematic created using CircuitLab

Figure 1. (a) Shows one gate driving another.

Figure 1a shows your gate driving a second one. Figure 1b shows a representation of your gate replaced with simple switches and driving the next gate.

All CMOS gates have some input capacitance. It's in their nature due to their construction. A capacitor tends to hold voltage across it unless there is some discharge path for it. The input impedance of CMOS gates is so high (GΩ) that discharge is very slow. Figure 1c represents your proposed scheme with only the P-channel switch. When SW5 is closed the input to the next stage is pulled high and that will work just fine. The problem occurs when SW5 is opened: C1 is charged and with no discharge path the input to the second gate (M11 and M12) will remain high. 

This could be solved with the addition of R1 as shown in Figure 1d but now notice that when SW6 is closed that R1 is passing current all the time. This will waste power and CMOS is famous for its extremely low power consumption when not switching. (The power consumption rises with frequency as all the input capacitors have to be charged and discharged.)

For fast logic it is necessary to charge and discharge the next stage inputs as quickly as possible. The P-channel and N-channel arrangement of the standard gates achieve this very well.