How to chain I²C level shifters?
Yes, there is sometimes an alternative to using I2C level shifters.

Since I2C is an open-drain bus, it is (often) possible to connect multiple master and slave devices to the same bus, as long as these rules are followed:


The I2C bus is pulled up to the higher voltage, e.g. 3v3 in your example
For each master and slave device, verify datasheet Electrical Characteristics table for SCL and SDA, supports the higher voltage (SCL/SDA exceeding the chip's supply voltage.)
For each master and slave device, verify datasheet Electrical Characteristics table for SCL and SDA, uses compatible logic thresholds (minimum logic high voltage, and maximum logic low voltage)
Maximum I2C capacitive loading (400pF) is not exceeded and all other I2C specs are met


Proper I2C devices are designed with open-drain structures on their SCL and SDA pins, so there is no direct electrical connection to the chip's supply voltage. What limits the maximum voltage the chip's SCL/SDA can tolerate, is the foundry "process" used by the manufacturer. A chip that normally runs at 3.3V might be manufactured on a process whose Absolute Maximum (permanent damage) rating is 6V. As long as the Absolute Maximum rating is never violated, and there is no internal structure that becomes a random forward-biased PN diode junction when SCL>VDD, then that chip shouldn't need a level translator to interface to the higher voltage I2C bus. (Assuming logic level thresholds and timing are compatible.)

This doesn't apply if the chip has push-pull structures, such as a microcontroller bit-banging I2C on its GPIO pins. Those GPIO pins have internal pull-up transistors present in the output structure, even if not used, so there's a path for SCL>VDD to do harm. In that case the datasheet would restrict the GPIO (SCL) not to exceed chip VDD. I'm not sure whether this applies to your system's FPGA pins, you'll need to investigate. If the manufacturer designed them specifically for I2C, they should be open-drain, but otherwise you may be stuck using at least the one level translator for the FPGA.

Be sure to check the datasheet for the logic thresholds for each chip. Sometimes the logic-high and logic-low thresholds are specified as a % of the chip's supply voltage, and sometimes the thresholds are specified by voltage.

It may still be necessary to use I2C level shifters or digital isolators in cases where the master or slave cannot tolerate the higher bus voltage, or in cases where ground return isolation is needed.