Xilinx ISE warns that a signal is trimmed since it has a constant value of 0, but the signal is used within my code
Because this line:

last_clk_val &lt;= count_clk;


is outside of the clocked process, both signals will have the same value in hardware (and also in simulation after a delta-cycle1). Thus, this condition within your process

if (last_clk_val = '0' and count_clk = '1') then


will never be true and the process will be equivalent to:

process(clk, reset)
begin
    if (reset = '1') then
        temp_value &lt;= (others =&gt; '0');
    elsif (rising_edge(clk)) then
        null;
    end if;
end process;


Together with the signal initialization, this gives a constant value of all '0' for temp_value.

If you want to delay count_clk for one cycle to detect a rising-edge on this signal, you have to move the assignment of last_clk_val inside the process:

process(clk, reset)
begin
    if (reset = '1') then
        temp_value &lt;= (others =&gt; '0');
    elsif (rising_edge(clk)) then
        if (last_clk_val = '0' and count_clk = '1') then
            if (count_up = '1') then
                temp_value &lt;= temp_value + 1;
            elsif (count_down = '1') then
                temp_value &lt;= temp_value - 1;
            end if;

        last_clk_val &lt;= count_clk;  -- moved here
    end if;
end process;




In simulation, all signal assignment are delayed. If no delay is given, then the signal assignment is delayed by a delta-cycle. Thus, if count_clk changes then count_clk will differ from last_clk_val for one delta-cycle in the original code. In hardware both signals are represented by the same wire.