Clock Configuration of Zynq Processing System
That means exactly what you wrote: if you need to supply some external clock to the chip, you use input clock; the processor clock is used to run processor; the DDR clock is used to communicate with external DDR memory, and the PL clock can be used to supply the programmable logic on the chip. Check this UG585 user guide chapter 25.

EDIT: (a response to your comment)

It is not enough to describe the speed of your design in terms of the clock frequency. You know that your design already has three different clocks, and each unit indeed runs at its own frequency, however, it does not mean that the unit with the higher frequency is faster. For example, your processor will be running at the 667MHz, but let's say it executes a function that takes say 1000 processor clock cycles when run instruction by instruction. This will take about total time 1.5us to return. Now, if you implemented this same function on hardware (to perform parallel) and optimized it (latency) to return in 100 PL clock cycles @250MHZ, this would take about 0.4us. So, even with the slower clock you sill get >3x speed. So, the slower clock does not necessarily mean slower performance (if this is your concern). 

Your statement the maximum frequency of my design will be no more than 250 MHz is not entirely true (again the maximum clock frequency in the whole system is 667MHz), however, you can claim that your hardware block, or the entire PL runs at 250MHz clock. And this statement is not sufficient to know how fast is your design.