can we do one always inside another always for verilog?
No, you can not. 

what you can do is drop the 'always' and just wait for a negative clock edge:

 always @(posedge clk) 
 begin
    if (n==10) 
    begin      
       @(negedge clk) 
       begin
           n &lt;= 5;
       end
     end
 end


Please realise that the code can only be used in a test-bench. You can not synthesize this.




  Even for your code which removes always, it is still not synthesizable?


Nope! That is what I wrote. There is no single logic element that responds to both rising and falling clock edges. 

All double edge logic like DDR interfaces are comprised of two sets of FFs: falling and rising edge and the results are combined. Most often transferring the falling edge data to the risign edge so you end up with double width data. 

 I had to fix your if (n=10) and nededge I suggest you be more careful even when making examples.