Verilog module instantiation during synthesis?
At the top of your hierarchy you MUST have one module which contains all the logic. 


  but then I'll have single modules with a lot of ports which would clutter my code


There is no simple solution to 'unclutter' your code. The only way is to use sensible port and signal names.
It is not unusual for digital designs to have lots of signals at the top level. That is why you find FPGAs with 400+ I/O ports. Inside a design the port connections are an order of magnitude bigger. 


  I'd like to know your thoughts on the correct approach for reorganizing/reformulating my module instantiations into a code structure that I can synthesize and assign pins to.


That is not possible unless we know a lot more what your code does and all the ports you have. The phrase "Cleanliness is next to godliness" comes to mind here. The names in your example above are the quintessence of how not to name ports.