Is the GPIO speed involved in the baud rate of my USART?
Take a look at the architecture of your proccesor. For this purpose I use the LPC1769, but is very similar on other proccesors.

On this platform the proccesor is not directly connected to peripherals. The proccesor, as with DMA, Ethernet, USB, RAM and ROM run on it's own AHB matrix. This matrix contains connections to several high-speed peripherals on the proccesor. For example, the proccesor connects directly to the SRAM. The DMA does as well, so the CPU can handle instructions and the DMA can (on the background) move or read data from/to peripherals.

The general purpose peripherals like SPI, UART, ADC, PWM, etc. are on a seperate peripheral bus (APB). There is a bridge between the high-speed matrix and this bus. This will cause delays in data-transfer (because the bus may be busy).

In case of the LPC1769, there are 4 High Speed GPIO pins. If the state of these are changed, it wil; take immediate effect. This allows, theoretically, an update speed of over the CPU clock frequency.

You say that the max. update speed depends on the APB1 clock rate. The APB1 clock rate is the clock rate of all peripherals on group 1, which may be GPIO and UART. This clock is usually lower than the CPU, to save power.

The GPIO update speed and UART are not dependant on each other, but dependant on the clock rate of the peripherals and the AHB/APB structure.