Should I get rid of my bias towards active high?
Active low does have one significant advantage: the active level is always the same, even in systems where components run on different supply voltages or can be turned off completely (power gating). So for something like a reset line, it can make a lot of sense as you can hold components in reset while the power supplies settle and what not by simply pulling to to ground, which is usually the same voltage level for all components in a circuit. Presence detect pins also make sense to be active low - the device or connector only needs to short the pin to a ground pin, there are no dependencies on power supplies so there are no issues with sequencing or gating. Active low can also give an indication of a missing transmitter or bad connection, as in the case of most UARTs.

Anther consideration is the reset state of a pin. For example, it's rather common for FPGAs to have internal weak pull-ups active on all IO pins before they are configured. Therefore, it may make sense to make some external signals active low so they are not considered asserted before the FPGA is configured. Or maybe you want the signal asserted, in which case make it active high.

On the other hand, inside of a CMOS circuit, the logic level in most cases doesn't really make much difference. Long wires can be split by periodically inserting inverters, and you just need to make sure an even number are added or the inversion is taken into account by changing the destination logic. Additionally, it's common to build "inverted" versions of basic blocks such as full adders so you can chain adder with inverted outputs to adder with inverted inputs and reduce the number of transistors you need (this is because the core of a full adder is inverting, so a "normal" full adder includes at least one inverter). In many cases, the tools can do this automatically as an optimization step.