Driving capacitance with a high voltage level shifter
Since you're getting the output from the collector, the output impedance of the whole circuit will be the R3, 1k. It's quite high to drive a capacitive load, because if you connect one then it will form a low-pass filter with a cutoff frequency of \$f_c = 1/(2\pi \ 1000 \ C_L)\$. For a 100pF load, the cutoff frequency will be around 1.6MHz. That's why you cannot meet the rise-time requirement.

The output impedance should be low. Extremely low. You can try the following circuit:







simulate this circuit &ndash; Schematic created using CircuitLab

The first stage is a translator and the output is a push-pull output stage having extremely low output impedance.