Frequency of a MCU is higher than frequency of a quartz
This is very common for processors for a variety of reasons.  First, the clock tends to be the highest frequency signal in a system, so using a lower frequency oscillator will reduce radiated RF interference.  Second, generating the actual core clock frequency on-chip means that the clock speed can be configurable.  Lowering the clock speed in CMOS saves power, so by giving the CPU the ability to control its own clock rate, the software can scale the CPU speed as needed to reduce power consumption.  This is also done on your desktop or laptop computer - the core runs at 2 to 3 GHz, but nothing on the motherboard runs anywhere near that fast except for serial busses (SATA, PCIe, and USB 3).  

This clock generation is done with a device called a PLL (Phase Locked Loop).  Most PLLs contain a voltage controlled oscillator (VCO), one to three dividers, a phase comparator, and a filter.  The basic idea is to lock the output of the VCO onto an integer multiple of the reference clock frequency.  The main part of the PLL generates the drive voltage for the VCO.  This is done by dividing down the output of the VCO and performing a phase comparison with the reference clock.  If the phase is leading or lagging, a positive or negative error voltage is produced.  This voltage is then integrated in the loop filter and then passed to the input of the VCO.  If the phase is leading, the VCO control voltage will be lowered and the VCO frequency will decrease.  If the phase is lagging, the VCO control voltage will be raised and the VCO frequency will increase.  Eventually, the divided VCO output and the reference clock will match in phase and frequency, and the PLL will be locked.  

This method can only generate integer multiples of the clock frequency.  If the reference oscillator is 12 MHz, then a division by 2 in the PLL will result in a multiplication by 2 to  get a 24 MHz output frequency.  A division by 3 will produce 36 MHz.  Division by 4 will produce 48 MHz, etc.  

Adding another divider at the input or output allows for fractional clock rate generation.  Division by 2 and the multiplication by 3 in the PLL would produce 18 MHz.  Division by 2 and multiplication by 5 would produce 30 MHz.  Division by 2 and multiplication by 45 would produce 270 MHz.  

Another consideration is that the frequency range of the VCO is often limited.  This can prevent generation of frequencies that require large dividers because then the VCO frequency would be too low or too high.  Adding another divider so that both the reference input and PLL output can be divided mitigates this problem somewhat so the PLL can generate a wider range of frequencies.  So long as the division is not a prime number, it can be split up between the input and output dividers so the VCO is working in its operating frequency range.