Is it safe to self-reset a flip-flop based on its output state
I think it could cause problems, but you haven't provided enough information to know for certain one way or another. When the FF output is high and the clock goes high the reset input to the FF will start to rise. Since it is an asynchronous reset the FF output will start to fall. If the AND gate is fast then the reset input will start to fall before the FF output has fallen completely to a low level. Even worse, the output of the FF could go low long before the internal state of the FF has completely changed to a 0.

Seems to me you could end up in a metastable state or the whole thing could oscillate. You need to have precise control over the timing to make it work, and make sure that the delay through the AND function is much longer than it takes for the FF to completely reset.