Is making a D flip flop with asynchronous level triggered reset possible?
Here's Xilinx's example of a "Flip-Flop with Negative Edge Clock and Asynchronous Reset": 

always @(negedge C or posedge CLR)
    begin
        if (CLR)
            Q &lt;= 1’b0;
        else
            Q &lt;= D;
    end


(Source: Synthesis and Simulation Design Guide, UG626, Oct 19, 2011)

Notice that this is basically the same as your second example (except using the opposite clock edge). And in fact this is a level-sensitive clear, not an edge-sensitive clear, because if clear is held high, the output will continue to be held low, even if new clock edges arrive and/or the D input changes.