Combining components and timing in VHDL (And probably verilog) / FPGA
It sounds like you understand this correctly. To answer your questions individually:


This could be a real problem, but the FPGA registers and clock infrastructure work in a way that means you do not have to worry about this problem in a fully synchronous system such as the one you have described.
There a few factors that allow you to reliably register data on the same clock edge that is altering said data:


The hold times for internal registers are very small, well under 1 nanosecond in for example a Xilinx Spartan 6 FPGA, and less than 0.2 nanoseconds for the block memory in said FPGA.
The clock network typically uses a very low skew design, so that the clock edge in one part of the FPGA happens very close in time to the edge in other parts. Contrast this with the data path, where your changing data signal has to propagate along the wire from one register to the next.
Each clocked element has a propagation delay from it's D input to its Q output.


Combining these factors, when a clock edge occurs, the data seen by the second register (in your case a memory element) will not change until the register propagation delay plus the wire delay. As long as this total is more than the hold time for the receiving register, the design will work reliably. The clock skew does play a role here, but as before, this should (but see point 3.) be small compared to the other two factors.
Your FPGA design tool chain will perform very detailed timing analysis of the entire design, provided that you have given it the right information in the form of constraints. This analysis will include any internal clock skews, delays, temperature and process verations, etc. It is always important to create constraints for clock periods, and any I/O timing. With these in place, the tool chain will tell you if there were any timing problems in your design. Even though the particular scenario you describe would never actually have a timing problem, I think this is an important point.