Why this concept in VHDL doesn't work?
It appears that you are trying to create latches in the last section by using when in your assignment statements. This is not recommended design practice. Among other things, this allows the data to "flow through" as soon as the conditions are met, which is what the simulator is showing you.

If you want to create pipeline registers (edge-triggered, master-slave), you need to do those assignments within a clocked process.



EDIT: I'm really not following all of the complexity in your code. If I had to do what I think you're trying to do, I would code it more like this:

entity pe_element is
  port(
    --Output signals
    AD_o        : out std_logic_vector (7 downto 0);
    SHIFT_CB_o  : out std_logic_vector (7 downto 0);
    SHIFT_RB_o  : out std_logic_vector (7 downto 0);
    --Input signals
    cb_en_i     : in  std_logic;
    rb_en_i     : in  std_logic;
    diff_en_i   : in  std_logic;
    clk_i       : in  std_logic;
    rst_i       : in  std_logic;
    CB_i        : in  std_logic_vector (7 downto 0);
    RB_i        : in  std_logic_vector (7 downto 0) 
  );
end pe_element;

architecture pe_element of pe_element is

  --Signal definitions
  signal adder_tmp      : std_logic_vector (8 downto 0);

  -- That particular hack is a pretty annoying one. Idiots. 
  signal am             : integer;
  signal bm             : integer;

begin

  process (clk_i)
  begin
    if rising_edge(clk_i) then

      -- update CB pipeline
      if cb_en_i = '1' then
        SHIFT_CB_o &lt;= CB_i;
      end if;

      -- update RB pipeline
      if rb_en_i = '1' then
        SHIFT_RB_o &lt;= RB_i;
      end if;

      -- update output
      if diff_en_i = '1' then
        AD_o &lt;= adder_tmp (7 downto 0);
      end if;

    end if;
  end process;

  -- Output Logic
  am &lt;= to_integer(signed(CB_i));
  bm &lt;= to_integer(signed(RB_i));
  adder_tmp &lt;= std_logic_vector(to_signed(abs((am - bm)),9));

end pe_element;