JK flip-flop timing diagram positive edge triggering
Your output diagram seems correct to me, but I'm not sure whether it is clear to you what a J-K flip-flop is.


  If I am not wrong the input is only J and K = 0 right?


Well, not really: as you can see in https://en.wikipedia.org/wiki/Flip-flop_(electronics)#JK_flip-flop, by setting \$K=0\$ you just put your flip-flop in the "set state", which means that its output \$Q\$ will constantly be \$1\$ (starting from the subsequent clock edge, of course), no matter what your input is. So, yes, the output you plotted is correct but it isn't your assumption of what "input" is. 

I suppose that a more correct use of a J-K flip-flop would be to use one of the ports (let's say \$J\$) as a proper input carrying a signal from a circuit and using the other one (thus, \$K\$) as a control for what you want your output to be like (I assume you may want it to signal some conditions or events, or stuff like that).