Sensitivity list for clock edge and state change
I output the data on the rising edge of the FETCH signal (this is not a clock).


You change OUT_DATA and WordCounter on the rising edge of FETCH (but not merely to reset or preset them). Therefore FETCH is a clock (at least for this subcircuit).

If you don't want to use FETCH as a clock, but still watch its rising edges, you need to have another clock signal to use, and it must be guaranteed to have at least one rising edge for each pulse of FETCH. Then you can do

reg FETCH2;
always @(posedge CLK) begin
    FETCH2 &lt;= FETCH;
    if ( state == OUTP ) begin
        if (FETCH &amp; ~FETCH2) begin // rising edge of FETCH
            OUT_DATA &lt;= DATA[WordCounter];
            WordCounter &lt;= WordCounter + 1;
        end
    end
    else begin
        WordCounter &lt;= 0;
    end
end