Variable PMW generator using Verilog
The only thing I would say about your PWM implementation is that it is way too wordy, with unnecessary signals. Here's a much more compact representation of exactly the same thing:

`timescale 1ns / 1ps
module PWM_gen (
    input       clk,
    input [7:0] duty,
    output      sig
);
    reg [7:0] count = 8'b00000000;

    always @(posedge clk) begin
      count &lt;= count + 8'b00000001;
    end

    assign sig = (duty &gt;= count);
endmodule