Finite State Machine (FSM) bit sequence detector for a stream of several bits
Got to admit, for that I would be very tempted to ignore the FSM approach all together, in favour of something like a 5 bit shift register and some simple combinatoric stuff, easier to write, easier to READ (Arguably more important) and very, very obvious in just about any HDL.

5 flipflops and at most one or two LUTS, which is I suppose your second option.

Small FSMs have their place, and in a dense state coding it might actually be more dense then the shift reg approach (by one, maybe two flipflops), but there are reasons why one hot coding for state machines is generally favoured and that is not going to be any better then the shift reg thing, while being harder to understand.

TBH, doing that sort of thing as a FSM strikes me as undergrad excersize, not something that should be done in reality.