What is important in computer clocks' signal: signal edges or intervals when signal is stable? Will multiple value propagation occur?
I see nothing in the circuit that should stop multiple same-clock-cycle propagations if the circuit is fast enough?


This is referred to as a hold time violation, and they are terribly fatal to a circuit. It doesn't happen because ASIC creators run expensive timing analysis software to check every single path in the design to make sure that the path is not too fast that the input value could change before the hold time window ends.

Generally paths feed through enough combinatorial cells and the wires have enough RC that the inputs don't change until well after the hold time period expires.

You can read wikipedia about Setup and Hold times for more detailed explanation.