Efficiency of FIR filter in verilog language
Do it in following 

   assign add01   = xn0+xn1;
   assign add23   = xn2+xn3;
   assign add_all = add01+add23;
   assign Yout    = add_all;

   always @ (posedge Clk or negedge reset_n)
   begin
     if(~reset_n)
     begin
       xn0  &lt;= 'd0  
       xn1  &lt;= 'd0
      xn2  &lt;= 'd0
   xn3  &lt;= 'd0
   Yout &lt;= 'd0
 end
 else
 begin
 //unit delays using flip flops
   xn0    &lt;=Xin; //x[n]
   xn1    &lt;=xn0; //x[n-1]
   xn2    &lt;=xn1; //x[n-2]
   xn3    &lt;=xn2; //x[n-3]
 end
end //always