Simulation of blocking assignments in always @ blocks
I'm no Verilog guru, but as I understand it (from here http://www.sigasi.com/content/verilogs-major-flaw amongst other places), using blocking assignments to communicate between clocked processes is asking for non-determinism.

Regarding part 2 - As I understand it... if you only use non-blocking assignments when you communicate between processes, you'll get deterministic behaviour across all simulators.  The non-determinism of blocking assignments is not a "simulator thing" - it's inherent in the way Verilog works.  Changing the order of the processes in the source files (for example) may change the order of the updates and hence the behaviour of the code, even within the same simulator.