VHDL design: why my integer goes by the number of bits and not the value?
There's just nothing that would reset the counter_test back to 0.

VHDL's integer ranges aren't magic, they don't automagically wrap around. The range only seems to specify the values that are to be expected to fit.

Many tools don't do the range-checking by default, my guess is it does impair the performance a bit. It's often possible to enable this, however.

Synthesis tools usually don't rangecheck, there's really no way for them to know beforehand, and there's no way for the synthesized design to report any "runtime errors".