Mosfet array as FPGA power consumption model
Using "power MOSFETS" to model FPGA power consumption is not a correct idea, they have no common features with mechanisms of power dissipation in digital logic.  The question about "parallel" or "in-series" doesn't seem to be well thought, FPGA use low-voltage power rails and "sereis" connecton of dissipation elements obviously has no place here.

Power dissipation of FPGAs depends on (a) static dissipation (via leakage), and (b) dynamic dissipation, which depends on how many gates are switching and at which frequency. Here is an Altera/INTEL article that provides overview of the models. The model obviously must rely on a particular logic design (because only then you can know the number of switching gates and their frequency), which can be determined only by VHDL compiler and associated power estimator tool.

But if you mean "thermal model" for some crazy 150W FPGA package with thermal spreader, then yes, any array of properly-distributed elements (resistors or power MOSFETS) will do the job, regardless of parallel or series connection.