Why is current controlled feedback faster than voltage controlled feedback in PWM controllers?
All transistors have GBW limit whether they are BJT’s or FETS.  Yet common emitter or source configurations are unity gain thus maximum BW.  This is why ECL and CML and current mode comparators are fastest yet have lower input impedance.

But in this analog case the CM PWM does not have to integrate the voltage and simply compares the voltage error with the current * Rsense =Vs to match the scaled down voltage error in order to cut off the driver (reset).   The voltage error ripple  is reduced by detection on each pulse rather than the integration of many pulses from the filter time constant which must be many pulses in delay to reduce ripple voltage.

The Current Mode Feedback (CMF) reduces the inner loop to a much faster 1st order LPF for smaller Step load variations.

The Voltage Mode Feedback (VMF) with a 2nd order group delay response is twice as much even if the BW were the same, yet we know the  pulse feedback has much higher loop bandwidth than the switching frequency so the small step delays are much less.


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But given the Volt-second saturation limits of the inductor's  charge current, there are limits to the benefit of the CML feedback when the PW rises to 100% for large step load or large input step voltage changes.  These tradeoffs improve the small step response delay more than the large step response but in both cases improve stability and ringing.