How to reduce or remove noise when using an ADC to sample CAN bus
Your FPGA has input and output DFFs for each pin. Read up on I/O pin DFFs in Xilinx UG381, particularly on the pin input DFF (ILOGIC2) and the programmable input-pin-to-DFF delay path to that DFF (DDLY).

Use these input DFFs on your ADC input data bus pins to latch in the ADC conversion results. 

The timing relationships between a pin to its input DFF and its output DFF are fixed for the silicon, varying only with temperature and slightly from part to part. You can adjust their DDLYs to get a clock-to-setup time that accommodates ADC bus timings.

Then you don't need timing constraints and synthesis routing is eased and consistent over builds. This is much simpler.

Make sure your VHDL takes the ADC bus straight into DFFs, with no combinatorial logic between pins and DFFs. Otherwise, the input pin DFFs can't be used because the circuit can't be routed during synthesis.