What is the fastest I/O planning for FPGA?
The global clock doesn't have a 'path' per se.  You can go in any of the global clock pins on the chip and then route the signal from there onto one of the global clock nets.  These nets are dedicated so it doesn't matter how any of the other signal nets are routed as it won't affect the global clock nets.  Also, the connection to the global clock net from the pin does not involve the general routing fabric of the FPGA so long as the pin is capable of directly driving a global clock net.  

I would not be too worried about the influence of the clock input on traces that aren't immediately next to the pin.  If you're very worried about the clock input, then use a lower frequency oscillator on the board and get the frequency you need by using one of the DCMs in the FPGA to synthesize the higher frequency clock.  

In terms of IO pin locations, what I usually do is figure out what they're going to be connected to outside of the FPGA.  The software can route signals wherever they need to go inside the FPGA.  And if you follow some of the design rules of thumb, all of your inputs and outputs should pass throgh IOB flip flops.  This greatly helps the place and route stage by synchronizing the inputs and outputs and hiding much of the skew that occurs in the routing.  The expense is a clock cycle of delay on the input and a clock cycle of delay on the output, a reasonable price to pay for synchronization.  

Bottom line: most pins can go wherever it is convenient with no performance degredation.  The toolchain will take care of the details.  Use this to your advantage to simplify the board layout and trace routing outside of the FPGA.