Create array of std_logic_vector in VHDL with increasing bit-width based on generic parameter
Use the maximum bit width for A[n], but assign only the required bits in your loop:

A(1)(W downto 0) &lt;= resize(I(1), W+1) + I(2)
A(2)(W+1 downto 0) &lt;= resize(A(1)(W downto 0), W+2) + I(3)
...


The unassigned bits will be removed by synthesis.