How to have an edged triggered reset signal in a sequential verilog circuit?
The most straightforward way to do this would be to synchronize the reset signal into the counter's clock domain and then do the edge detection on it. Here's an actual snippet from a project I'm currently working on. I'm using a fixed local clock to measure the period of an incoming data signal.

  /* This logic is in the "fast local clock" domain.
   * The local clock is assumed to be faster than the RF signal itself, by
   * a factor of at least two. We resynchronize bit_pulse to the FLC domain
   * and count the number of cycles between the rising edges of those pulses.
   *
   * The bit_period is stable by the time the logic in the rf_in domain
   * looks at it based on a delayed version of the original bit_pulse.
   */
  always @(posedge clock) begin
    flc_pulse_a &lt;= bit_pulse;
    flc_pulse_b &lt;= flc_pulse_a;
    flc_pulse_c &lt;= flc_pulse_b;
    if (sim_reset || (flc_pulse_b &amp;&amp; !flc_pulse_c)) begin
      bit_period &lt;= bit_count;
      bit_count &lt;= 0;
    end else begin
      bit_count &lt;= bit_count + 1;
    end
  end


Note that it IS possible to do what you want with a complex asynchronous state machine, but FPGAs do not generally have the resources to implement such things efficiently, and the tools are not set up to support such designs.

Plus, you need to think about boundary cases: If the two events (posedge clock and negedge reset_l) are truly asynchronous, that means they can occur arbitrarily close together. What behavior do you expect when that happens?