Explanation of the filter timing analysis in FPGA
Your filter is a synchronous design with a clock. Assuming you have provided the timing constraints correctly, the minimum clock period or the maximum clock frequency is the maximum frequency (as reported by the Synthesiser) at which you can clock your design and guarantee reliable operation (ie., with no timing violations) on the FPGA you have chosen.
Beyond this clock frequency, the operation of your design is not guaranteed to be reliable, as it may cause timing violations.