Mismatch between RTL-level simulation and post-synthesis simulation using xilinx xst
Add (and use) a reset signal.  

Xilinx FPGAs have a global set/reset (GSR) signal that puts all registers in the their default state or as specified in the register declaration (this is documented in the XST User's Guide at the beginning of chapter 5).  AFAIK, the @initial block is ignored.

However, things are chaotic when the FPGA starts up, because:


The GSR is asynchronous.
PLLs are not locked
Not all PLLs lock at the same time
There are race conditions everywhere


So the initial Flip-Flop values after the GSR are not enough.  

Create a module that generates a reset signal for each clock domain.  You can create it by by AND'ing relevant asynchronous reset signals, such as an external reset pin, PLL/DCM locked signals, and using it with a synchronizer, as follows:



(Source: How do I reset my FPGA?)