When is the concurrent signal assignment executed?
When looking to understand what's happening in a HDL in general, it's a good idea to think about what's going on in the actual hardware. There isn't a concept of "execution" in an FPGA in the same way that there is in a CPU. I was taught that when you read a concurrent statement, you read it as Q is driven by not out1.

In hardware, the above concurrent statement (Q &lt;= not out1), is the equivalent of this:







simulate this circuit &ndash; Schematic created using CircuitLab

When does the output change? After the input changes + some delay that's a characteristic of the chip. Is this called execution? No. 

Processes are constructed using flip flops which are clocked. For example, this:

p1:process(clk)
begin
  if rising_edge(clk) then
    b &lt;= a
    c &lt;= b
  end if;
end process;


produces







simulate this circuit

Since the flip flop is clocked, the driven outputs only change on the clock edge, even though the input may have changed sometime before. Could this be called execution? No.

Writing HDL really needs a change of mindset away from the CPU to a place where you actually consider the hardware implications of what you're coding. You're describing the hardware.

As an exercise, take a look at the final block diagram for the code that you write once it's been built and see if you can identify where the concurrent statements are and where the processors are. it's quite interesting to see.

Disclaimer: I've simplified what's going on in the FPGA quite a bit. It doesn't use discrete gates and I don't think it uses D-type flip flops either, so there are some inaccuracies here, I picked those components for illustration purposes.