Please explain the following integer constant used in verilog
Even though the type indicator may be hexadecimal or decimal, the size indicator is always measured in bits.

8'h81 

Since 81 is an 8-bit number in binary (1000 0001), it requires 8 bits. This is why the size is 8, even though the number is expressed in hex. 

Also, size may be the bus size that the signal is driving (or part of it), even though the value itself may require fewer bits.

This is shown here:

16'd5

The decimal 5 only needs 3 bits (101), however, this value may be desgnated for a 16 bit bus:

wire [15:0] test;
assign test = 16'd5;


While verilog does pad smaller sizes, sometimes if you're concatenating, you want to specify each length:

wire [31:0] test;
assign test = {16'd5,16'd5};


In the last case:

32'h8f_32_ab_f7

32 bits are required to store the hexadecimal number, which is 1000 1111 0011 0010 1010 1011 1111 0111 in binary.

The hexadecimal is just the short way of writing the number, but the size is still 32 bits.