What is standard coding practice for a non-blocking assignment to a large register array with variable part select in Verilog?
r1 &lt;= r1 is not required in any synthesiser, as it is in the definition of RTL. Since the logic is written under @posedge clk, it is implicit that the previous value of a the register r1 should be held in that clock cycle if r1 is not driven any value at that clock edge ie., in this case, if the condition cond1 is violated.
This is true for the second example as well. The a_reg vector is formed by 1024 1-bit registers. Therefore the earlier conclusion we made on 1-bit register r1, is applicable to each register in a_reg vector as well.