Question about IDELAYE3 of Xilinx FPGA
That clock input is supposed to be synchronous with the LVDS data, so inserting a PLL like that does not make any sense.  Not to mention it's not possible as drawn as the IBUFDS_DIFF_OUT instance is an input buffer and as such may only be connected directly to the appropriate IO pins on the FPGA.  This is because those instances are physically located in the FPGA IO banks, it is not possible to configure them to be connected to anything else than the physical package pins.  

If clock frequency you're interested in is outside the capabilities of that app note, then you're going to have to make more extensive modifications.  That is, of course, assuming the example design actually does what you want it to do, which isn't clear.  TBH, this sounds like an X-Y problem.  What are you really trying to accomplish here?