Using MSP430G2452 Timer + ADC
The MSP430G2452 has three Timer A bugs in both revisions, any of which might be affecting you. They can be read in the Errata for the chip. I believe maybe Bug TA12:


  Interrupt is lost (slow ACLK):
  Timer_A counter is running with slow clock (external TACLK or ACLK)compared to MCLK. The compare mode is selected for the capture/compare channel and the CCRx register is incremented by one with the occurring compare interrupt (if TAR = CCRx). Due to the fast MCLK the CCRx register increment (CCRx = CCRx+1) happens before the Timer_A counter has incremented again. Therefore the next compare interrupt should happen at once with the next Timer_A counter increment (if TAR = CCRx + 1). This interrupt gets lost.
  
  Workaround: Switch capture/compare mode to capture mode before the CCRx register increment. Switch back to compare mode afterwards.


Even if this is not the case, you can easily fix this. You are using the default 1MHz Master clock. You can change this to 2 MHz or 4 MHz with a simple code change, at which point the same divider would produce a VLO of 24KHz or 48Khz. This would allow you to set a timer count a bit higher, again either 12 or 24, avoiding the lower count issue. Of course, testing is needed to be sure.

Your alternative plan also works. If you are not too concerned with low power, simple delays would work. Of course, as this is running on the Master clock of 1Mhz instead, you will need to calculate an apropos delay, and realize that there will be some slight drift.