Accessing all the data and to store in wire using BLOCK RAM GENERATOR in Vivado using verilog
Firstly, review your use of terms, it's quite important when using a HDL that you are aware of what you are describing. You can't store data in a wire - a wire is literally just a connection between two points. 

Secondly, you need to start thinking about how your code could be converted to hardware. Without understanding the underlying hardware you are trying to describe, it is very difficult to use a HDL.

You're main problem here is that the entire contents of a block RAM cannot be read in a single cycle, unless it has an address width of zero (i.e. it is configured as Nx1). This is because the address line selects which element in the RAM is being read, and this address can only take one value in any clock cycle. This is the same reason that when programming software, you can't access every element in an array simultaneously.

In your case, in order to read the entire contents, you would need to have a RAM that was 3232x1. However there are no FPGAs that I know of which have block RAM memories with a data port width of 3232 bits. You could instantiate a 3232x1 memory using discrete registers (e.g. reg [3231:0] mem;).

If you want to use a 2-D block RAM, you need to describe a circuit that reads from the block RAM one address at a time. Each clock cycle you read an address, and then have to do something with the data, such as storing it in another register, performing some calculation with it, etc.