When to use State Machines - FPGA
If you have to split an operation across multiple clock cycles, you have two options : pipelining, and sequencing

Let's consider a mythical operation consisting of four multiplications , for example - where each multiplication (except the first) requires the output of the previous multiplication as one of its inputs. However the basic ideas are much more general.

In pipelining, you have enough hardware to perform every operation simultaneously, interconnected by pipeline registers. This implies four multipliers, separated by pipeline registers.  It will take 4 clock cycles to get the first result (so we say the pipeline is 4 stages deep, and the latency is 4 cycles) but then you get a new result every clock cycle (so we say the throughput rate is 1 cycle). A little more info on pipeline design...

Downside : this is a large piece of hardware - 4 multipliers are relatively expensive (which is why some FPGA families offer many small multipliers as highly optimised blocks).

The alternative is to sequence each operation in the same multiplier, giving a much smaller design, but delivering a result every 4 cycles.

In this case you can use a single multiplier, storing its result in a single register, for a much smaller design. 

Every 4th cycle (or whenever something else signals a new input in ready) you connect the new input to one input port of the multiplier; in other cycles you feed that port from the output register (to use the previous multiply result). And in every cycle you feed the appropriate data (filter coefficients, matrix values, whatever) into the other multiplier port. Four cycles later, you present the final result as your output, and signal to your consumer that a new result is ready.

The obvious way to sequence these operations is a state machine (FSM).

Indeed the computations can be embedded in the actions associated with each state, for example:

if rising_edge(clk) then
   Done &lt;= '0';   -- and any other default actions
   case state is
   when Idle =&gt;
      if Start = '1' then
         Temp  := Input * C1;
         State := S1;
      end if;
   when s1 =&gt;
      Temp  := Temp * C2;
      State := S2;
   when s2 =&gt;
      Temp  := Temp * C3;
      State := S3;
   when s3 =&gt;
      Temp  := Temp * C4;
      State := S4;
   when s4 =&gt;
      Output &lt;= Temp;
      Done   &lt;= '1';
      State  := Idle;
      -- optional alternative for bombproof handshaking
      -- if Start = '0' then
      --    Done &lt;= '1';
      --    State &lt;= Idle;
      -- end if;
   end case;
end if;


If you are interacting with other units - SPI interfaces, UARTs etc, the FSM is again usually the best method.