Sleep vs low frequency
The majority of current draw in CMOS parts occurs when signal switch state. So, to conserve power you want to minimize signals switching states. Clock nets are large and therefore have a lot of capacitance, so you want to disable clocks to circuits that aren't being used. 

You might disable all clocks except the timers so a timer interrupt can wake-up the processor (from a low-power mode). Or, you could use an external signal to wake-up the processor.

Table 2.2 in this processor user's guide lists some of the power-down modes. http://www.ti.com/lit/ug/slau144j/slau144j.pdf