Range-limited integers or unsigned/signed in VHDL
Which bits are you expecting to be optimised away?

y depends on itself and x, both of which are full-width integers.  

The multipliers will get a few low-order bits optimised to zero, and the fact that the high 3 bits of y are 'lost' when you multiply by 12 reduces the size of the y register slightly.  

But it won't drop the bits > 16 if that's what you're expecting.



PS: The divide by 100 is probably going to be quite large in LUT terms - you'd be better off with 128 (or some other power of 2) as your base scaling.