FPGA/VHDL Design guidance: intermittent inputs
It seems like to you want to process when there are a fixed pipeline (32) of elements available, so a shift register should work fine, and that would be the simplest way if implemented in logic cells. But 32 words can be a lot of cells, so you may instead want to implement that storage in memory. In that case, whether you call that a FIFO or shift register just depends on the in and out pointers manipulation. So this would be part of the datapath scheme.

Moving on to the control scheme, you have some description of the wanted behavior at the tail end, but not much on the front end. So I am going to ignore the front end. You want to start processing and output a word when there are 32 words, so it is natural to have a counter to count the number of words stored in the datapath (FIFO or shift register). When the counter hits 32, output starts and the the counter is kept at 32. So for the tail end, it simply means letting the counter going back down to zero before stopping.

A quite obvious way to add up the elements is to add them as they come in one words a time. When the count hits 32 and is kept at 32, add the new one while subtract the old one spilling out at the other end (I am guessing this is how you want it to work).