How to compare in Verilog?
There's nothing wrong with the comparison per se. The real problem is how you are assigning values to the signals being compared.
The only assignment to TBPRD_reg that you've shown us is in an initial statement. If this is the only assignment in the design, then that's your problem.
An initial statement is primarily useful in simulation, where it is used to initialize signals before the simulation starts. As such, it cannot be used to copy values from an input port, because in general, those values haven't yet been set.
The initial statement should not be relied upon to do anything at all in the synthesized design, unless you know for sure that the FPGA technology you're using allows initial values for FFs to be stored in the configuration file. Again, even if this is true, it cannot be used to copy dynamic values from an input port.
In general, you should develop the habit of initializing FFs based on the reset signal and nothing else. That way, you can reset your design without power-cycling it to force a reconfiguration.