Low cost UART over fibre
You could add additional modulation, it would keep the receiver devices ALC features happy.

As you have at least 3 MBit/s data rate available you have quite a lot of headroom.

You could use basic FSK modulation with two tones of say 250kHz and 1000 kHz.

This would let you use a rather simple demodulator (pulse width comparator) and have less than 20% bit edge jitter.

Higher frequencies could be tried but require more careful design work.

EDIT:
For those not regularly worried about such things ASYNCH comms is designed to be able to tolerate a nominal half bit period edge jitter, this because the sampling of bits should occur in the middle of the bit cell and the start edge is assumed to be the reference point.  This means that you can have up to half a bit timing error on the last (of usually 10) bits and still decode correctly.  So 50% also corresponds to a cumulative 5% bit period error (or clock error) over 10 bits.  Edge jitter from a simple FSK modulation system is not cumulative but adds to the clock error budget.  

Clocks these days are pretty good so using a 5 x oversample will leave the signal looking noisy but well within spec.