Output Impedance of Instrumentation Amplifier
Here is Zout for Enabled and Disabled of a highspeed OpAmp; the dip in Zout(disabled) at 500MHz is likely the resonance of Package / bondwire / silicon / testPCB inductance and the output capacitance of: ESD structures, and depletion / isolation regions of output drivers. To resonate at 500MHz, with 10nH (5nH of output pin, 5nH of VDD or 5nH of GND pins), requires 10pF. And that's about right.

How to interpret these two plots? The descending "Disabled" plot drops 20dB/decade, thus is capacitive. The ascending "Enables" plot rises 20db/decade, thus is inductive. We are not shown the phase shifts, but deduce that from the 20dB changes.

Notice the low drive level; -30dBm (50  ohms?) is 1/31.6 of 0.632vpp, thus 20mvpp. That drive level is low enough to not upset the operating conditions of the output transistors, even out past UGBW.
UGBW is ~~ 200MHz for the ADA4896.



And now for a very low power (1uA Idd) opamp; notice the high frequency ( a relative term, for this slow opamp) Rout levels off at 80,000 ohms. Notice how the Zout for Av = 101 levels off near 80Kohm even for Frequency of 500Hz. 



Notice how the G*H controls the Zout --- for high gain, there is little surplus loop gain to retain control of the output impedance. UGBW for this opamp? 10KHz.

Why is Zout important? As others mentioned, ringing occurs because of inductive Zout. And ringing affects Settling Time. I'm presently writing "rules" to synthesize precision-settling circuits, so need to document and manage all the gotchas.

Finally, Signal Chain Explorer has "OutZ", that looks backward into all prior stages interacting; here the Cshunt of 10uF interacts with OpAmp Zout (Rout is 100 Ohm). For clarity, I selected (clicked on) the "GainFollower" to display the "Amp Output Resistance-Open Loop" in the screen-shot. Previously I selected the "Capacitive Shunt" stage, then clicked "OutZ" to generate that lower right plot (Z, R, X) of "output impedance".
Here is tutorial on measuring "output impedance".
http://www.robustcircuitdesign.com/signal-chain-explorer/visualizing-op-amp-impedances-using-sce/


Here is the ADI INA topology; the output circuit is a standard commonmode stripper, thus expect the standard Inductive Zout behavior.