Designing a state machine to detect if input was high exactly 2 times in last 4 clocks
To refine my comment further, you need to keep track of whether the previous three inputs, plus the current input, contain exactly two ones, in order to set or clear the output on the next clock edge.

Since order matters, a 3-bit shift register (8 states) is the easiest way to remember the last three input values. Then the rest of the logic works like this:


If the current input is zero, set the output if the shift register contains exactly two ones.
If the current input is one, set the output if the shift register contains exactly one one.
In all other cases, clear the output.


If that isn't the definition of a Mealy state machine, I don't know what is. It should be straightforward for you to fill in the details and complete your assignment.



For completeness (a different answer has been accepted), here's the full transition table:

Current          Next
 State   Input   State   Output
 -----   -----   -----   -----
 0 0 0     0     0 0 0     0
 0 0 0     1     0 0 1     0
 0 0 1     0     0 1 0     0
 0 0 1     1     0 1 1     1
 0 1 0     0     1 0 0     0
 0 1 0     1     1 0 1     1
 0 1 1     0     1 1 0     1
 0 1 1     1     1 1 1     0
 1 0 0     0     0 0 0     0
 1 0 0     1     0 0 1     1
 1 0 1     0     0 1 0     1
 1 0 1     1     0 1 1     0
 1 1 0     0     1 0 0     1
 1 1 0     1     1 0 1     0
 1 1 1     0     1 1 0     0
 1 1 1     1     1 1 1     0


It is straightforward to convert this into a logic implementation.