Avalanche ruggedness
This topic can go very deep! I'll try to say a bit about it, according to my understanding, to at least get you started.

Power FET manufacturers began advertising their transistors as "avalanche rugged" in the mid-80s. While there was - and still is - some confusion as to what this means, many modern power FETs have a degree of robustness in the face of avalanche conditions.

Physically, avalanche robustness is achieved by preventing the mechanisms that would otherwise degrade or destroy a FET under breakdown. The two that I am aware of are snap back and hot-carrier injection. When a FET experiences snap-back, it essentially turns itself on under breakdown and can't easily be turned back off, resulting in destruction. Hot-carrier injection is a phenomena which can degrade a FET or alter its characteristics over time, even if it doesn't go into "deep breakdown". The phenomena is, again, a fairly complex one, but basically high energy carriers are generated in the drain depletion region and - if they are close to the gate - can actually penetrate the gate and impregnate it with permanent charge.

Both of these phenomena can be avoided if the breakdown current is made to run through a safe path where it doesn't generate problematic hot carriers near the gate, and doesn't activate the parasitic snap-back BJT. An avalanche rugged FET don't snap back, so for VDS above their avalanche rating, it acts a bit like a TVS diode. This is achieved physically by altering the doping profile of the backgate or adding an auxiliary drain-body diffusion that is designed to run substantial current without thermal hot-spotting issues and without activating any parastic BJTs. As for the design trade-offs, I am not expert enough to say - my guess is that it adds die area and perhaps additional parasitic capacitance.

When a rugged FET avalanches, VDS will clamp near the breakdown voltage. Any current that runs through the FET at this time will result in significant power dissipation (ID*BVDSS). But often, power supply designers only need to break the FET down for a short time. This situation comes about, for example, when there is residual energy in the inductor of a switching mode power supply after a switching event. Designers can calculate the energy in the inductor that needs to be dissipated, and datasheet curves allow them to calculate the junction temperature rise that will result. As long as the transistor can tolerate the energy delivered to it in breakdown without thermal issues, then it can survive even periodic breakdown events.

In case it is not clear, this about surviving in the face of transient avalanche events, NOT DC avalanche conditions.

Materials from FET vendors will give you a better practical guide of how to interpret data-sheet curves and design for avalanche. I recommend the following two white papers: 

http://www.st.com/content/ccc/resource/technical/document/application_note/05/13/69/ee/aa/87/49/b6/CD00100956.pdf/files/CD00100956.pdf/jcr:content/translations/en.CD00100956.pdf

http://www.vishay.com/docs/90160/an1005.pdf