Load/Store architecture
What you mention is only one of many differences between CISC and RISC.

One way that RISC tries to minimize memory stalls is by having the compiler schedule the memory accesses. With CISC, the compiler has little opportunity to optimize memory accesses, but an advantage of RISC's simpler, single-cycle instructions is that it can rearrange those instructions at compile-time to optimize memory accesses. CISC instructions are too complex for the compiler to know when and where instructions can be rearranged. RISC's advantage partially depends on an optimizing compiler understanding how instruction flow can be manipulated.

There are other attributes of RISC that are meant to offer improvements. One is heavy pipe-lining, another is the potential for faster clock speeds, and a third is instruction and data caches. However, CISC architectures have adopted many of the techniques that were envisioned for RISC, and have tended to keep up with RISC in performance.