In what condition power MOSFET gate capacitances Cgs and Cgd can be paralleled?
When we think about transient behavior, we usually pin the VDD to a perfectly-fixed voltage. In reality, we have a huge capacitor from VDD to GND. 

Thus when the circuit is charging the gate, the C_GS has charge flowing directly to GND.

And the C_GD has charge flowing into VDD, which has that huge capacitor to let the change in charge be flowing into GND.

For circuits that do not keep VDD in a well-controlled state, we tend to call those circuits oscillators, or expect warrantee-problems down the road because of un-reliable behaviors.