How to analyze S-R latch circuits?
This is a S-R latch for the most part, but an extra latch is added up top with two feedback paths. This is to make sure that RESET always overrides SET if both commands occur at the same time.

Also a SET will not work unless the latch has been 
RESET (initialized). This extra logic is to block irrational duplicate commands from entering the computer.

NOTE: Only one RESET or one SET command can be entered at a time (state is maintained). If both commands are entered RESET will dominate. The double feedback posed a behaviour question, so I built this in LabView to see its true behaviour. This is what I observed:



Note that power-up without a RESET results in a unknown output state. Also only 5 (including un-initialized) rational states are possible with the schematic provided. Other possible states involving various open gate inputs should be posted as a separate question.

EDIT: To really understand multi-stage logic it is best to buy a breadboard plus the ICs and a 5 volt supply and build the circuits yourself. A single 74LS02 or 74HC02 can be wired at least 7 different ways.

Our software versions work fine for fixed patterns like the image you show, but showing a wide range of "what-if" scenarios would take many pages to answer.