VHDL case with different outputs
The case itself adheres to VHDL syntax, and in general synthesis tools handles case.

The warning is related to general coding style.  If a process is used to make combinatorial logic, then all the signals driven from a process must always be assigned in order to avoid latches, but my guess without seeing the rest of your code, is that it is not the case.  A good coding style (when feasible) is to assign all the signals in the beginning of the process, like:

process (IR, RTA, ...) is
begin
    R0 &lt;= ...;
    R1 &lt;= ...;
    ...
    case ...
end;


So to avoid the warning and the latches, ensure that all the signals driven from a combinatorial process are assigned.  

For example this code will intentionally make a latch, since q is held if en = '0', and only updated if en = '1':

process (en, d) is
begin
    if en = '1' then
        q &lt;= d;
    end if;
end process;


For sequential logic there is not the same problem, since flip-flops can just hold they state if they are not updated.