How can I make Verilog HDL ModelSim test bench for a simple ripple adder circuit output an addition table instead of a long list of every calculation?
You can use nested for loops for the body of your table, and another for loop for the header.  To show numbers within a line (and avoid the newline character), use $write instead of $display.  Use $display to end a line.  Refer to IEEE Std 1800-2017, section 21.2.1 The display and write tasks.
integer i, j;

initial begin
    $write(&quot;     &quot;);
    for (i=1; i &lt;= 15; i = i+1) begin
        $write(&quot;__ &quot;);
    end
    $display;

    for (i=1; i &lt;= 15; i = i+1) begin
        A = i;
        $write(&quot;%d | &quot;, A);
        for (j=1; j &lt;= 15; j = j+1) begin
            B = j;
            CIN = 0;
            #5;
            $write(&quot;%d &quot;, S);
            #5;
        end
        $display;
    end
end

Output:
     __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ 
 1 |  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 
 2 |  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 
 3 |  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 
 4 |  5  6  7  8  9 10 11 12 13 14 15 16 17 18 19 
 5 |  6  7  8  9 10 11 12 13 14 15 16 17 18 19 20 
 6 |  7  8  9 10 11 12 13 14 15 16 17 18 19 20 21 
 7 |  8  9 10 11 12 13 14 15 16 17 18 19 20 21 22 
 8 |  9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 
 9 | 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 
10 | 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 
11 | 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 
12 | 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 
13 | 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 
14 | 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 
15 | 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 


I'll let you have the fun of printing the header numbers and a table for the carry output :)