Tips for using a switching regulator on a board where EMI must be kept to a minimum
This is a complex question that entire books have been written about. Many application notes from TI, Maxim and LT talk about this problem as well. I'll try to distill down to a couple of tips / notes:


To chunk up your problem, you have two regulatory classes of EMI to worry about -- conducted and radiated. The former, as the name suggests, is noise that is conducted along the system, through the input or output sides of the converter. The latter is noise that is radiated away from the switching circuit.
There are 100%, unavoidable sources of noise in a traditional hard-switching SMPS circuit. You cannot remove this noise, only mitigate it. Your goal (probably) is to mitigate enough to pass CISPR/FCC testing, but perhaps you need to be even quieter for your application.


Thinking about the sources of noise (from this paper out of Missouri UST):


Conducted via the DC Input Side
Conducted via the DC Output Side
E-field coupling / emission from the phase node (switch node)
H-field coupling from the small switching loop 




For #1, you should search for "Input EMI Filter Design" (the app note linked above covers some of it). In my experience, this is something you can simulate, but you may also need to empirically determine final values of components in the lab. When using an input filter, effects on the stability of the converter should be considered as well.

For #2, this is unavoidable -- this is of course, a switching converter. A fundamental ripple at the switching frequency will always be there. You can tune your inductor value, and output cap values to minimize this ripple. Using LTSpice/PSPICE to simulate the effects of various output filters on your ripple will be useful.

For #3, this is the source of the high-frequency, broadband emissions from a SMPS in the 100s of MHZ range. This is due to design parasitics (image below taken from Maxim app note):



With some hand-waving and over-simplification (for the purposes of illustration):



RLC tanks are oscillatory as you may recall, and in this case, the frequency can be in the 100s of MHz. To "solve" #3 (mitigate it), I would recommend search for "RL or RC snubbers on phase node / switch node" -- there are app notes from vendors covering how to design these. These hurt efficiency slightly, but can severely attenuate the noise generated. A shield may also be necessary to attenuate these emissions.

Additionally, burying your SW node may help (for both #3 and #4) -- you'll trade a resistive loss, but make that copper as small as possible, and burying it inside your board in an inner layer will give you some shielding as well.

For #4, your goal is minimize the size of your switching loop. Search for app notes on the layout of the switching loop. Here's some diagrams from (10.1109/TEMC.2011.2145421) illustrating a few different loop sizes:



Often, the datasheets + app notes for SMPS controllers will go to great lengths to remind you to keep that loop as humanly small as possible. Using a FET device that combines the HS + LS in one package also helps in this regard. This minimizes CSI and parasitics of the SW node, at least between the two power switches, which helps considerably at higher switching frequencies. You may also have to consider your PCB stackup here -- a thin dielectric between L1/L2 will help shrink this size.

A last word of warning -- don't take any individual application note or paper in isolation. They're all zeroing in on a specific problem in a specific manner. It's on you to synthesize that data and tailor it to your specific application, keeping in mind your requirements and what you're trying to do.

I don't have the time to type up a super detailed answer on how to solve each of the areas, and to be honest, smarter folks than I have gone into detail on how to attack each portion, backed by theory. If there's interest, I can put together a bibliography of the papers + app notes + books I use to attack my problems.