Transistor sizing in CMOS circuit
I think the assumption is that all the PFETs are to be adjusted so the overall performance is similar to the NFETs, not just Mpa and Mpc.  In parallel, the speed will only be improved, so you have to look at the series combinations.  If 2um is the N-type reference and the P equivalent is 5um, we'll assume the Ns are 2um.

Mpc, Mpd and Mpe each have to have half the resistance of the 5um reference since Mpc is in series with either of the others.  Therefore they're sized at 10um.

Mpa and Mpb in series combination must match Mpc, so they have half the resistance, or twice the gate width, as Mpc...20um.

As an aside, I'd be asking the prof why I'm using a book that uses units of um instead of nm.  Technology marches on.