Give synthesis freedom to choose signal
No. As far as VHDL is concerned, they are either the same signal, or a different signal. Even if you know that they (for instance) start from the same signal and go through two different functionally identical gates, or that they are two equivalent pins from an I/O block of a general purpose chip, and you can choose what they do later in software.

You could do it mandronically, by having two different architectures, one using signal A, one using B, and see which gave you the better synthesis. That will work for one uncertain signal, but would rapidly become tedious if you needed to compare dozens, or permutations of dozens. That's when you need to fire up the 'generate' statement, to create those architectures for you.

If it's the case that you are assigning bus pins, then you just have to make an intelligent stab at what's likely to be best, and let the tools sort it out. Only start optimising the pins if you get a routing fail.