Use condition from one clock with registers from another, synchronized clock
Since both your clocks are generated by the same PLL, they are synchronous with well known phase relationship. Hence, there is no asynchronous clock domain crossing between the signals driven by base-clk and fast-clk. 

When sending data from slow clock to fast clock, as long as the fast clock has sufficiently smaller time period, there should be no risk of data loss. However, these inter-clock paths have to be properly multi-path constrained and ensure that timing is met.

Sending data from fast clock to slow clock is different story. You will get some good insight here