Can't get ADC chip to work
Justme gave the answer, you have to clock it.

continuous conversion without having to initialise and command the conversion?

That would mean the ADC would change the level of its output pins every time it does a new conversion. Counting uneven propagation delays, skew, etc, if the device that reads these pins reads them at the wrong time, it will get some bits from the previous value, some bits from the new value, and some bits in transition which will be garbage.
That's why synchronous logic uses clock to synchronize things and ensure signals are sampled when they are valid.
If an ADC does continuous conversion, it must have an output with an edge to indicate when the data is valid and can be sampled by the next device. You will need to apply proper clock domain crossing to that in your FPGA. It is simpler to just generate the timing signal from the FPGA, plus you will get a stable sample frequency instead of whatever RC internal oscillator the ADC uses.
Note for 300ksps you don't need a flash ADC, a SAR will do just fine, and it's cheaper.
EDIT:

Mainly because I have to use opto-couplers between the FPGA and the ADC bits, so I will have to also isolate the CS and RD signals from the FPGA too.

OK, so you want an isolated reading on a potentiometer. I really wonder why, but there are much simpler solutions for that.

SPI ADC. Pretty cheap, less opto couplers. It will be fast enough.

Isolated ADC (check mouser/digikey). Should be expensive.

Cheap micro as the ADC, output the data on a UART, isolate that, and instantiate a UART receiver in your FPGA.

Or turn the pot signal into PWM, or variable frequency, or pulse density modulation (many ways of doing this, 555, opamps, etc), isolate it with one opto, and read the duty cycle, period, etc with a timer/counter in your FPGA.