Level shifting a clock signal
The rising edges of your signal will be slowed down by the RC filter formed by the pullup and any parasitic capacitances in your circuit. Assuming those are 10 pF, you get a time constant of 100 ns, which is way too slow for an 8 MHz square wave.

You could try to build a level shifter that actively drives both low and high signals with multiple FETs, but it would be easier to just use a level-shifting logic chip.
There are level shifters with two supply voltages (e.g., 74LVC1T45), but 3.3 V signals are TTL compatible, so you can use any 5 V buffer with a TTL-compatible input, such as the (SN)74AHCT1G125/MC74VHC1GT125/TC7SET125.