PAR taking too long - Xilinx ISE
It is likely the double-subscript is causing synthesis to infer distributed memory rather than memory blocks. I would combine the selecting bits from N_int and sine_counter_d1 into a single signal addr and use this as the index within SINE_TABLE(addr). A synthesis report (not even P&amp;R) should show the improvement. 

I don't know VHDL, in verilog I'd do something like

wire [8:0] addr = { N_int[x:y], sine_counter_d1 };
...
   sine &lt;= SINE_TABLE[addr];


You will need to tweak the constant loading to follow the same pattern. Spending hours laying out sea-of-gates to do what could be pushed into a memory is a good way to waste P&amp;R time.