Phase register in phase accumulator
It is an N bit register that serves in combaination with the adder at the input to integrate the frequency tuning word (Phase being the integral of frequency after all).

If you look at the diagram you can clearly see that on each clock the register will be loaded with the modulus 2^N sum of its old output and the FTW.

In real parts N is quite often larger then the address range of the ROM (32 or even 48 bits is not uncommon), and various phase dithering and Taylor series approximations are used to improve the spurious performance.