Internal oscillator drift and its effect on UART
UART is very robust when it comes to clock accuracy requirements. This is a consequence of the fact that each byte is processed independently and any time difference associated to clock mismatch doesn't propagate for more than 10 bits (start bit + 8 data bits + stop bit) in time.

This analysis from Maxim concludes that 2% in clock frequency mismatch is still tolerable. In your particular case you have 150kHz/8MHz, what is equivalent to 1.88%. If the other side of the link has a much more accurate clock (let's say a crystal oscillator with 50ppm, or 0.005%), then the clock mismatch is below 2% and  you should be OK. If both sides of the link have a clock that is 1.88% inaccurate, then in the worst case scenario (one side has 8MHz+150kHz, the other has 8MHz-150kHz) you may have 3.8% of clock difference, in which case you run the risk of starting to see problems.