Verilog counter made of 32 bit adder (syntax error)
@ThePhoton gave the correct answer to your immediate problem, "You can't instantiate a module inside a procedural block."

But the whole approach is impractical for many other reasons. I understand why they make you build adders out of gates when you're learning the language, but continuing to use such techniques to build larger systems is just silly. You need to start using the power of the language to make your tasks easier. A counter in Verilog should be a 7-line block:

always @(posedge clock) begin
  if (reset) begin
    count &lt;= 0;
  end else begin
    count &lt;= count + 1;
  end
end


Which can be replaced by a single line if you want:

always @(posedge clock) count &lt;= reset ? 0 : count + 1;


Keeping your source code simple makes it both easier to debug and easier to understand and extend later. It also gives you more room for comments that capture the design requirements and implementation constraints that are not visible in the code itself. THAT's the real lesson here!