Is it possible to estimate the execution time of an FPGA design?
You will need to run a functional simulation to determine signal latency. A complex design can have many paths from inputs to outputs and there is no way for the timing analysis tools to know which particular path is of interest to you. Write a testbench, wiggle the inputs, and count the clock cycles until the outputs change.

Whether a LUT operation takes one clock cycle depends on the delay through the LUT and your chosen clock frequency. That sounds like a silly answer, but the question is poorly framed. An FPGA cannot do anything interesting if you run the clock so fast that a signal can't propagate through a single LUT, so every useful FPGA design has a clock period that is (much) longer than the delay through a single LUT.