Benefits of RAM vs FIFO in FPGA
Usually a FIFO is built around a simple dual port RAM.  So it either consumes exactly the same resources (if you use hard FIFO logic) or slightly more (if you use soft FIFO logic) compared with a RAM of the same capacity.  If you need data more than once, maybe a bare RAM makes more sense than a FIFO.  Or perhaps several FIFOs back-to-back.  Or just a register pipeline.  Really depends on exactly what it is you want to do.