Is there a right way of implementing a T flip flop in verilog wrt using reset signal?
The problem with a T FF is that its state always depends on its previous state. So if you have no way of initializing the state, the simulator will always propagate "unknown" on every clock edge.

Of course, in real life, the TFF will always definitely be in one state or the other, and you often don't care exactly which one it is at any given moment, which is why you see no initialization in typical applications.