Curious Behavior In Logisim while trying to mimic a halt instruction
Why is the original intended circuit as seen in Conditions A &amp; B not allowing the counter register to count to the desired value and resetting at [n-1]?


The resulting 1 from the comparator resets the counter asynchronously. That means, it does not need a rising edge.


  Thus the comparator part of the circuit never outputs 1 […]


This is not correct. You just don't see it on 1 because the 1 resets the counter immediately. The counter value of 0 leads to a 0 output of the comparator. So the 1 is there just for a very short moment.

You could use a spike catcher like this one:




  […] why does it appear to work when I tie that same line to a constant 0 as in Condition C?


Well, actually it does not work, it just seems so. If you tie the line to 0 the output of 1 leads to an error which is clearly indicated by the red colour and a value of E. This error propagates to the clock input of the counter blocking any further action.


  Is this a potential bug in Logisim?


No.


  My other question would be what would be the proper way to design a halt signal in Logisim to stop the master or system clock?


Why did you consider a 3-state-buffer? The output is undefined if disabled when not driven by another source. You could use an OR gate to, well, "gate" the clock. Look:



You use an OR because the clock has just risen and the "off" signal is 1. In other situations you would use an AND or anything else appropriate.