Current mirror design using PMOS
The output current will only be exactly the same as the input current when both transistors have exactly the same voltages across all terminals.
Their \$V_{GS}\$ are the same as the gates and sources are in parallel.
But what about the drain and \$V_{DS}\$?
Hint: learn about &quot;channel length modulation&quot;.
Short channel, L = 0.5 um: the channel length modulation will have a large influence
Long channel, L = 5 um: the channel length modulation will have a much smaller influence
To (almost) completely eliminate the influence of channel length modulation you will need a more complex circuit like a 3-transistor current mirror.