Some confusion about noise margins in digital abstraction!
To answer your question, you are misreading the initial slide.
It lists the noise margin as \$V_{OH} - V_{IH}\$ and \$V_{IL} - V_{OL}\$.  The noise margin must be greater than zero, and is a measure of how much noise can be tolerated between gates to still register proper logic levels. I don't know where you got your initial equations, which are incorrect.


\$V_{OH} - V_{IH} &gt; 0 \$ becomes \$V_{OH} &gt; V_{IH}\$
\$V_{IL} - V_{OL} &gt; 0 \$ becomes \$V_{IL} &gt; V_{OL}\$


All of this talk of receiver and sender is over complicating the problem since everyone discusses these concepts in terms of input and output levels.  

Keep in mind what these terms refer to:

\$V_{IL}\$ : Highest possible input voltage which will register as a low logic

\$V_{OL}\$ : Highest possible output voltage representing a high logic produced by the gate

\$V_{IH}\$ : Lowest possible input voltage which will register as a high logic

\$V_{OH}\$ : Lowest possible output voltage representing a low logic produced by the gate

Consider: \$V_{IL}\$ and \$V_{OL}\$, which describes the case of one gate producing a low output feeding into the same gate as an input.

If two gates are back to back and \$V_{IL} = 2V\$ and \$V_{OL} = 2.5V\$, or \$V_{IL} &lt; V_{OL}\$ , the gate clearly won't work: the highest 'low' output voltage produced would not be low enough to register as a 'low' voltage at the next gate.  

So the constraint is \$V_{IL} &gt; V_{OL}\$ for proper functioning.

Similarly, you have a gate producing an output voltage \$ V_{OH} = 4V\$ feeding into a gate with \$V_{IH} = 4.5V\$.  The 4V input will not be registered as a high input at the next gate, since it is less than \$V_{IH}\$. 

So the constraint is \$ V_{OH} &gt; V_{IH} \$

Typically for a robust system, you want the \$V_{IL} \$ and \$ V_{IH}\$ to be about half of the supply voltage.  And for \$V_{OH}\$ to be at the positive supply and \$V_{OL}\$ to be at the negative supply.  This gives you a solid  noise margin of half of the supply voltage for both logic levels.

EDIT

Based on your comments there is some confusion regarding inputs and outputs.  A circuit produces an output, based on its input states.  It does not produce an input; inputs are driven by other logic gates.  VIH and VIL are not produced by the circuit.  They are simply the 'most-off' input levels (from previous gates) which will still register properly.  An output will produce a logic level (VOL or VOH).  This may or may not be corrupted by noise as it travels to the next input.  If the noise is sufficient, it will cause the output voltage of the previous gate to change enough to register as the opposite logic value in subsequent gates.