The IDCODE read from the device does not match the IDCODE in the BSDL file
It could be any number of things.  Assuming you've checked (double checked, triple checked, etc) that your JTAG connections are correct, I'd try the following additively, one at a time, in this order:


Insert a small resistor (between 22R and 220R) in the TDI line, as close as possible to the CPLD.
Snubber circuit - 68R and 100pF in series to GND on the TCK line, as close as possible to the CPLD.
Another resistor, same size as the TDI one, but on the TMS line as close as possible to the CPLD.
Another resistor, same size as the TDI one, but on the TDO line as close as possible to the connector.


[edit] scratch the clock impedance matching, I was thinking of the FPGA CCLK signal, which is 50 ohm. [/edit]

1,3,4 damp reflections on the data in and out.  2 tries to damp ringing on the TCK line.

I suspect a combination of 1 &amp; 2 will solve your problem.