Understand MIPI-CS2 camera connector on ZYBO Z7
This is the recommended D-PHY termination for the Xilinx I/O pins for both high-speed and LP modes.

Xilinx uses separate pins for the LVDS differential signals and the LP single-ended signals. They fixed this with the Ultrascale parts, but the regular series 7 needs this setup. 

More here: https://forums.xilinx.com/t5/Video/MIPI-CSI2-D-PHY-to-FPGA-Zynq/td-p/903883