PCI-E throughput calculation
Simple calculation would just be number of lanes times the lane rate.  The lane rates are 2 Gbps for PCIe gen 1 (2.5 Gbps raw), 4 Gbps for PCIe gen 2 (5 Gbps raw), and 7.877 Gbps for PCIe gen 3 (8 Gbps raw).  The lane rates are lower than the raw serializer rates due to encoding overhead (8b/10b or 128b/130b).  The number of lanes is usually going to be 1, 2, 4, 8, or 16.  So, a gen 3 x16 card would give you 7.877*16 = 126 Gbps.  I think there may be some other lane counts possible, but they are not very common.  If you want to do a more thorough calculation, then you have to look at PCIe transaction layer packet (TLP) overhead for reasonable packet sizes, which could be system and application dependent.  

The 100 MHz is just a reference clock that's distributed to components in the system.  Each card will feed that reference clock through a PLL to generate the high frequency clocks required to operate at the desired link rate.