How to interpret this layout?
I believe this is a layout for a tri-state buffer. In this circuit, both the top two PMOS transistors are in series as well as the bottom two NMOS. The middle two MOSFETs are used to turn the tri-state &quot;ON&quot; or &quot;OFF&quot; and then the outer two MOSFETs act as a normal buffer/inverter. The &quot;z&quot; labels seem to suggest the inverted of the normal signal.

Image source: https://www-inst.eecs.berkeley.edu/~cs150/sp11/agenda/lec/lec08-cmos.pdf