Does fly-by order of bytes matter in DDR3+ design?
There is no specific order of DQ lanes vs. their fly-by position on the clock. The delays are discovered by the calibration process, and as you noted, used to set up the memory controller.
This paper gives a good overview: https://www.nxp.com/docs/en/application-note/AN4466.pdf
Summary of the calibrations done:

ZQ (drive strength and termination)
Write leveling (set outbound delay of DQ and DQS based on per-lane skew)
DQS gating (set read DQS 'validity window', that is, round-trip latency)
Read DQS delays (set inbound DQS DLL to align with read data midpoint)
Write DQS delays (set outbound DQS delay to align with write data midpoint)

The standard for doing this is laid out in JESD79-3E, available here: https://www.jedec.org/document_search?search_api_views_fulltext=JESD79-3