How are opcodes decoded at hardware level in any controller?
Original 8051 CPUs tend to use 12 clock cycles per instruction. Therefore it can use 12 clock cycles per instruction, to instruct internal logic gates in a 12-step sequence according to the opcode to select the immediate value from opcode operands onto internal data bus, and store it into some register, which is register A as instructed by the opcode.
The correct opcode to move immediate value of 8 into register A is:
0x74 0x08