STM32 external 5V pullup
If the datasheet says &quot;Vcc + 0.4V&quot; and Vcc=0V then +0.4V is your maximum safe voltage, until the rails come up. That is according to the datasheet. I would personally try to arrange things so that the situation where the 74xx IC is powered while the uC is not does not happen. As well as damage to the IO ports, weird things like latch up conditions and so on when you do not respect this type of constraint. Don't make your design risks worse thna they have to be. Eliminate unknowns.