How do the Dflipflops in the SAR Logic work?
The top group of Dffs generate a wavefront thusly

000000 &lt;- upon the initial  reset
100000 &lt;- upon first clk rising edge
110000 &lt;- upon second clk rising edge
111000 &lt;- upon third
111100
111110
111111

and the bottom group implement the testing/latching behavior of binary search.
The comparator logic-level determines whether the bit just set high, as the wave moves along to the right, will remain high after the wave moves one bit to the right. 

The feedback from bit 7 "Q" to bit 8 "CLK" [ the triangle input ] is the digital signal performing the sample-the-comparator-output, and make that binary-search activity for that bit (which is controlling a DAC).

Have you drawn a timing diagram? Start with "reset", and "clock". and some random "Comp" NRZ pattern. And the Q outputs of all the FFs.