Understanding data transmission rates over copper wire
Shannon's Theorem sets the ultimate limit of information bandwidth on a cable. Here's some more info about that: https://www.gaussianwaves.com/2008/04/channel-capacity/

tl; dr version: the Shannon-Hartley Equation:


\$ C = B \; log_2 \left( 1 + \frac{S}{N}\right)  \;\;\;\;\;\;\;\;\;\; \rightarrow (1)\$


Where \$B\$ is bandwidth in Hz, \$\frac{S}{N}\$ is the signal-to-noise ratio.

I2C obviously isn't anywhere near the Shannon limit for a cable. Instead, it is a lightweight protocol with intentionally-slow timing (100/400 kbit/s) using an open-collector bus to make it easy to implement for a network of small devices with modest I/O and control needs. The slow operation specified by I2C avoids most signal integrity issues.

There are faster variants of I2C that use 1 Mbit and 3.2 Mbit/s rates. These require more attention to layout and termination than normal I2C and of course have tighter, more demanding timing.

Moving up the food chain Shannon-wise, Gbit Ethernet uses multiple techniques to achieve its throughput:


Differential signalling
Multiple pairs (4)
Multi-level signalling, called PAM-5
Preemphasis / Deemphasis
Adaptive Equalization


These techniques take a lot of silicon, including a fast, large mixed-signal ADC/DAC block to talk to the cable and some fairly heavy signal processing to manage it. Add to this, the much more-complex software stack to drive it. This makes Ethernet as an on-chip block a bit much for a low-end microcontroller (some of which opt to use an external PHY instead). Its maturity however places it well within the reach of larger Systems-on-Chip.

How close are we getting to the Shannon limit, anyway? More here: https://pdfs.semanticscholar.org/482f/5afbf88a06d192f7cb052f543625c4b66290.pdf