Quartus 2 VHDL Clock Frequency Divider: can't determine definition of operator "+"
You are trying to perform addition on std_logic and std_logic_vector -- that makes no sense in VHDL, because these types do not hold numerical values.

If you want addition to work, you need to use either


a type that has well-defined overflow semantics, so it is clear what should happen if two '1' values meet in an addition, or
a type that is a pure numerical value and does not have a representation attached.


For a counter that is only compared against a fixed value, but never read, I'd go with the latter, change the type to natural and give it a range constraint, and leave it up to the compiler to select an internal representation.