AVR external interrupt triggering by the falling edge: for how long should I keep signal low to guarantee triggering?
From the datasheet, for the description of ISC11, ISC10:


  If edge or toggle interrupt is selected, pulses that last
  longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
  If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction
  to generate an interrupt.


Since a 1MHz clock means that the 800ns interrupt pulse will last less than 1 cycle, the interrupt will not be generated reliably. The longest AVR instruction requires 4 cycles, so using a minimum clock of 6MHz will ensure that you catch all interrupts while the chip is active.