Safe to tie erase pin on MCU to a GPIO pin?
You could use a sized ceramic capacitor to GND to debounce the spike period.  This will mean you have to set GPIO High and wait a bit for the line to come up.

Beyond that, depending on how close to 3V3 the flash chips needs to be (some are ok with 70% of VDD), you could use a weak pull-down resistor to keep it low.

Assuming a 50K internal pull-up resistor on your GPIO pin, a 150K external pull-down will allow you to pull up the line to 2.45V or 75% of the VDD and still keep the line from 'floating high' somehow when not being directed high for erase.

One thing for sure, don't route any other PCB traces parallel and near by as the cross talk can set your chip to erase mode at random.