Verilog, Is this statement interpreted as I expect?
The Verilog standard defines that a number without a base is always an integer. Taking this into account, your third comparison is checking if r is "ten" and not "two" as in the second example. To make Verilog simulators interpret values as binary you will always need to include its base 'b.

If your design is working in the same way in both examples, then I can only assume that r is never set to 2'b10. Otherwise, you would have different behaviors.