How PCIe can tranmit data at 2.5 GTps?
It is a Phase Lock Loop which takes an accurate 100Mhz reference clock distributed over the connection, and multiplies the frequency to modulate data at extremely high speeds, almost exactly the same as RF transmissions do for things like common Wifi Signals (2.4GHz), except via a high speed serial bus. 

There is some interesting info on page 3 of this app note AN562 by Silabs which describes the PCIe clock architecture. You think 2.5GB/second is cool, check out PCIe 3.0 x16 which is what graphics cards use in modern computer motherboards, getting 32GB/second!

Phase Lock Loops are really interesting to read about, and I encountered them when trying to design my own Time of Flight laser range finder, where the one thing you can do is take a 100-200Mhz reference clock and crank it up to 3GHz and run a counter at the same time as the laser is pulsed, and the return diode stops the counter, giving you time of flight. 

You can also make clock dividers which can do a similar thing but instead of multiply the reference clock frequency, they divide! Seems pretty straight forward, but pretty complicated circuitry and control theory.