Verilog parallel CRC with arbitrary polynomial
There are a few ways to do this.  In essence, what you need to do is 'unroll' the shifting part of computing the CRC so that it gets evaluated combinatorially within one clock cycle.  One way to do this is with a for loop inside of a combinatorial block.  If the polynomial is coming from a register (i.e. it can change at run time), then this is really the only way to do this.  However, if the polynomial is coming from a parameter (i.e. determined and fixed at synthesis time) then you can compute what amounts to a matrix transformation that converts the previous CRC state and input data to a new CRC state and shifted output data.  

Here is an example of some verilog code that implements the 2nd style, taking an arbitrary polynomial via a parameter: https://github.com/alexforencich/verilog-lfsr/blob/master/rtl/lfsr.v .  That code forms the combinatorial core of a CRC module: https://github.com/alexforencich/verilog-lfsr/blob/master/rtl/lfsr_crc.v .