Testing JK Flipflop using system verilog
Yes, there is something wrong with your testbench.  You are currently checking the output (q) every other clock cycle, but you should check it every clock cycle.

One way to check on every clock cycle (at the negedge as in your checker) is to add this code to the bottom of your testbench:

logic q2;
always @(posedge clk) begin : good
    case ({j,k})
        2'b00 :  q2 &lt;= q2;
        2'b01 :  q2 &lt;= 0;
        2'b10 :  q2 &lt;= 1;
        2'b11 :  q2 &lt;= ~q2;
    endcase
end

always @(negedge clk) begin
    if (q === q2) begin
        $display($time, " pass q=%b", q);
    end else begin
        $display($time, " fail q=%b q2=%b", q, q2);
    end
end


You should see a fail at time 60.

q2 is a model of your known-good jk_ff.