Bad synchronous description error in VHDL
why does it give me an error - 

There's a single driver for each signal in a process, you can't clock the same storage elements off both edges of a clock.  Synthesis won't treat a variable different from a signal.  It's not the VHDL language's responsibility to insure shared variables are operated correctly, though you can imagine PixelCounter and FastCounter may only be assigned in this process.

A possible solution

Because you tried and we see the word pixel I take it you are up against a performance limit and can't simply double the clock speed.

Try two processes, FastCounter/PixelCounter with different names, operating off the two clock phases.  You increment by two but one set has an LSB constant '0' and the other '1'. The incrementers are shorter by 1, the actual FastCounter, PixelCounter counters are one shorter in length. 

A 2:1 mux with MainClk as the select is faster than the increment on the PixelCounter. You'd gate the select with (Stop or SLEEP).

Somewhere you may need a half clock delay on some signals requiring pipeline registers on the opposite clock phase. 

(Stop or SLEEP) also resets both sets of counters.

And about now...

You realize you can instead simply multiplex the LSB constants and use a single set of counters in a single process - but the process of figuring out how to speed the counters up gave you the answer.  It works because the shortened counters increment at half the speed or a period of one MainClk.

The MainCounter &gt;= 35 expression tells you which phase of the MainClk is used in the LSB multiplexer select.

If you had provided declarations I would have edited it.  Are FastCounter and PixelCounter global variables?