AVR PWM output delay before start
Disabling the PWM mode of TIMER1 does not stop TCNT from counting - it only stops the PWM from being output.

So when you disable the output using CLR(TCCR1, PWM1A), TCNT1 keeps merrily counting along and does not reset to 0 when it hits OCR1C since it is not in PWM mode anymore. It runs right past OCR1C and will keep on counting up to 255 when it rolls over.

The delay you are seeing is the time it take TCNT1 to count from where ever it happens to be when you enable PWM mode back to OCR1C, at which time it will reset to 0 and start doing a normal PWM cycle. 

One way to control when the PWM cycle starts after you enable PWM mode is to preload the counter such that it will not have to do a wrap around before starting the normal PWM compare points in  OCR1A and then OCR1C. For example...

    while(1) {
        TCNT1=254;
        SET(TCCR1, PWM1A);
        SET(PORTB, PB2);
        _delay_us(BIT_DELAY);
        CLR(TCCR1, PWM1A);
        CLR(PORTB, PB2);
        _delay_us(BIT_DELAY);
    }


... generates this waveform...



Note that this approach seems like a hack to me and that there are probably better ways to gate the PWM signal that would more straightforward, but the best choice would depend on your application.