5V Tolerance of 3.3V OUTPUT pin
In the most abstract sense, what happens is this:







simulate this circuit &ndash; Schematic created using CircuitLab

You have a difference of 1.7V across 2.47 \$k\Omega\$, and so a current of about 0.69 mA flows from V2 to V1. 

The line is not diven to a clearly defined state. On the left of R1, the level is whatever V1 is putting out. On the right, the voltage that of V2.  Throughout the body of R1, there is a blend from V1 to V2.  Obviously, this is probably not useful behavior for digital circuits where we want a defined logic level on a given signal line: the same level on both sides of any resistor.

The worst case current of about 2 mA occurs when V1 is driven low, and V2 is at 5V. From V2's perspective, it's just driving a 2.47 \$k\Omega\$ resistor to ground, but V1 has to sink the current.  In the opposite case, V2 has to sink somewhat less current from V1.