PCB - matching length - relevant in that case?
The difference in propagation delay between 15mm and 50mm of PCB trace is less than 250ps (assuming 150mm/ns VoP), and the clock period here is just under 12ns. So no big deal. The only thing I might do is increase your clock length to match the longest data trace, then document the maximum skew (250ps) to the FPGA designer, who can probably play with the clock phase to deliver the best possible setup and hold margins at the destination.

If it were me, the FPGA clock output would be a DDR register toggling with the data, and I'd invert it to put the rising edge right in the middle of the data eye.

I am assuming the FPGA is the transmitter because I see no series termination resistors on the IC on your layout.