Difficulty of implementation of this Rayleigh variate generator on simpler FPGA
The abstract of the paper gives the resource utilization, which is very minimal; additional details are given in the body of the paper. There clearly would be no problem fitting this into any FPGA that has block RAM and hardware multipliers.

The Cyclone IV may  or may not be able to achieve the same raw speed as the Vertex-5 &mdash; how important is that to you?