How to load std_logic_vector array from text file at start of simulation
Here is a simple example function that reads a *.hex file from disk and initializes a RAM.

A hex file stores one RAM word per line in hexadecimal encoding (ASCII chars: 0-9, A-F, a-f)

At first a memory needs to be defined by word_t and ram_t. The generics or constants DATA_BITS and DEPTH define the memory layout:

subtype word_t  is std_logic_vector(DATA_BITS - 1 downto 0);
type    ram_t   is array(0 to DEPTH - 1) of word_t;


Secondly, a function is defined to read a file and return a initialization vector:

-- Read a *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
  file FileHandle       : TEXT open READ_MODE is FileName;
  variable CurrentLine  : LINE;
  variable TempWord     : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
  variable Result       : ram_t    := (others =&gt; (others =&gt; '0'));

begin
  for i in 0 to DEPTH - 1 loop
    exit when endfile(FileHandle);

    readline(FileHandle, CurrentLine);
    hread(CurrentLine, TempWord);
    Result(i)    := resize(TempWord, word_t'length);
  end loop;

  return Result;
end function;


A signal for the RAM is defined and initialized:

signal ram    : ram_t    := ocram_ReadMemFile(FILENAME);


This example should work in all simulators and in Xilinx ISE in synthesis, too. If you need a synthesizable example for Altera altsyncram, have a look at the complete files in our PoC-Library.

For example PoC.mem.ocram.tdp (true dual port memory).