How to constrain delay in the circuit without a clock?
SOLUTION which works for my test case. I was able to reduce the delay_C from approx. 1200 ps (unconstrained) down to 420 ps (constrained). 

create_clock -name virtual_clk -period 2.5  -domain virtual
set_input_delay  -clock virtual_clk 2.0   [find / -pin AM_fsm/SR_latch/Q]
set_output_delay -clock virtual_clk 0.100 [find / -port m1]