What are the typical tasks of a Design Verification Engineer?
Your first guesses seem right.  You would create and run testcases to verify functionality of the RTL.

For the other items, I have listed how I would classify them.

It will definitely vary between companies.  But in general I would say:


Debug the RTL (RTL Design Engineer; Circuit Design Engineer if you want to try different implementation than how it was originally coded)
Linting (RTL Design Engineer, sometimes they pass off bad RTL, then it becomes Design Engineer's job)
LEC (Library Design Engineer on individual cells; RTL vs. Schematic is Circuit Design Engineer, RTL vs. RTL may be RTL Design Engineer)  There are other equivalence tools as well such as symbolic which could be used.
Synthesis (Circuit Design Engineer on critical blocks; Physical Design Engineer at top level glue logic)
STA (Circuit Design Engineer on critical blocks; Physical Design Engineer at top level)
Debug timing (Library Design Engineer on individual cells; Circuit Design Engineer on critical blocks; Physical Design Engineer at top level)
Generate SDF (Library Design Engineer on individual cells; Circuit Design Engineer on critical blocks; Physical Design Engineer at top level)


Depending on how wild-west your company is you could do all of these!