How to control rise time of output of LTSpice's Voltage Controlled Switch?
What you are experiencing is not the rise time of the "real circuit", but the limitations of the simulation engine.

The rise time of the swout output is theoretically zero, since the switch is ideal and there is no reactive element on the output line that can introduce a delay. What you measure depends on the time resolution (the time step) of the simulation algorithm. If you put a maximum limit to the time step that is much smaller than 1ns, e.g. 100ps, you'll see a shorter rise time.

Change, for example, the simulation directive to:

.tran 0 150u 0 100p startup uic


to see what I mean.

In other words, trying to measure the rise time in that circuit is pointless and nonsensical because the modeled circuit is "too ideal" to show a non-zero rise time at its output.

If you want meaningful results in that respect, you should model the real circuit more accurately. For example, add a non-zero series resistance for the switch (around 10 milliohm for a real mechanical switch) and add at least a capacitor in parallel to R2 to model the parasitic capacitance that the switch is going to drive in the real world. Then you'll see a "real" rise time.