Question about trace length matching patterns for high speed signals
I don't work with DDR memory, so I'll assume there's no on-chip deskewing available, and length matching is in fact required. If the chips themselves are able to do the de-skewing, of course you should use that feature rather than extend the traces to do length matching.

But given that length matching is required, it looks like everything you're doing is done as well as it can be. Mainly because, 1, you're actually doing the length matching, and 2, you're using arcs rather than 90 or 45 degree bends.

In your comment, you mention your concern that the serpentine shape puts the trace in parallel with itself. That's a reasonable concern, but there's not much you can do about it. Certainly I wouldn't suggest moving the two chips farther apart to enable separating the traces further apart --- and anyway you probably have a board space limitation to prevent it. Given the spacing between traces looks like 4x or more the trace width, I wouldn't expect this to cause a serious problem. 

Of course a simulation with HyperLynx or other good SI tool is a better way to get a definitive answer. You should be able to simulate this particular issue without having models for your actual chips. 

One thing you haven't shown is your board stack-up. Without a good simulation and good knowledge of your materials, its not obvious that the propagation velocity on the inner layers is equal to the velocity on the outer layers (it probably isn't), and that strictly length matching between the layers is the right thing to do. Even if you have accounted for that, you can expect some variation in materials to cause mismatch between trace delays on different layers.