USB2512 - Too low input voltage in datasheet
Actually, there is a glitch in the datasheet. But not in the area of min-max VIN on XTALIN pin. Here is the problem.
The USB2512 chip has XTAL driver designed to accommodate small-formfactor crystals in tiny 2 x 2.5 mm (and smaller) packages, which are getting increasingly popular in portable electronics, and cheap. These tiny crystals have very low power dissipation limit, 10 uW - 100 uW. To be not overdriven, these tiny crystals require low driving voltage. In USB2512 this requirement is met by having a fairly weak XTAL driver inverter running from 1.2 V rail. This is a simple CMOS inverter, and it will switch around 1/2 of its voltage rail, or at about 0.6V.  So the specification essentially says that it needs 0.6V +- 0.3V to operate. The value of 0.3 V is taken from thin air by technical marketing with a very good fudge factor. In fact, anything that oscillates around 0.6 V (+-0.15V) will reliably toggle the internal buffers.
The problem is that any input signal that exceeds the LVCMOS12 levels (0V-1.2V) will stress the input I/O pad cell buffer leading to accelerated aging. So it is strongly recommended to feed the XTALIN with no more than 1.2 -1.5V  signals.
This requirement is very easy to meet by using a simple resistor divider at the pin input, something like 150 Ohms/100 Ohms. More accurate resistor network can be selected by playing with your driver model in any SPICE simulator, even if you have long trace and have to account for transmission line effects.
NOTE: the effect of input waveform can be easily tested on XTALOUT pin, and the resistor network values can be corrected to get a square wave output with 50% duty cycle (although it isn't really necessary).
The glitch in this datasheet is that the absolute max value is listed as 4 V. This is too much, and the IC will likely die in a couple of month of operation due to pad fatigue.
ADDITION: There are several available datasheets, from different periods of product development. I found this note in one of datasheets,

7.2  External Clock
50%  duty  cycle  ±10%, 24 MHz ±350  ppm, jitter &lt;100 ps  rms. The  external  clock  is  recommended  to  conform  to
the  signaling  level  designated  in  the  JESD76-2 Specification[5]
on 1.2 V CMOS Logic. XTALOUT should be treated as a weak (&lt;1mA) buffer
output