normalized parasitic delay
From my understanding, the rough way to calculate the parasitic delay is the ratio between the output capacitance of a complex gate and the capacitance of the input of the inverter. 

The output capacitance could be calculated by adding the size of the transistors that directly connect to the output. 

The capacitance of the input is like what you said, 3, because in a inverter, in order to make the output charge and discharge at the same time, the size of the PMOS must double because of the electron mobility.