In VHDL, does having large bus input to component take extra resources?
When you have a large array in HDL design (whether VHDL or Verilog) the synthesizer will often recognise it as a "ram" and implement it using block ram rather than a huge pile of registers.

However it can only do this in a limited subset of cases, if it can't map it to a ram you will end up with a huge pile of registers. In particular most rams only have two "ports", so reading or writing your array from more than two places (whether in the same module or not) is almost certain to land you up with a pile of registers. 

I do not know if the inferring of block ram happens before or after the design is flattened, you would have to experiment to find that out.

Finally be very careful when testing partial designs. It's all too easy to end up with large parts of your design synthesized away completely because you didn't connect its output to anything or because you fed it's input with a constant.