Verilog conditional assignments without using procedural blocks like VHDL with/select
You can simplify the procedural block by using an implicit sensitivity list, always @* in Verilog and preferably always_comb in SystemVerilog. And you should not be using non-blocking assignments in combinational logic.
always_comb case (sel)
  2'b00 : out = a;
  2'b01 : out = b;
  2'b10 : out = c;
  2'b11 : out = d;
endcase

Almost the same amount of typing as the VHDL with/select.