Finding Absolute Value In Verilog Data Designated by System C/Xilinx X
(Disclaimer: I'm not a Verilogger - its signed arithmetic foibles being one of the reasons why not :)

Prior to Verilog-2001 all vector arithmetic in Verilog was unsigned.  

In Verilog-2001 you can explicitly call for signed arithmetic, so I think you'll need to cast your in:

if ($signed(in) &lt; 0)
 out = -$signed(in);
else
 out = in;


Reading matter which may be of interest:

Signed arithmetic in Verilog-2001 - Opportunities and Hazards