Instantiating Parameterized Modules in SystemVerilog
change const to parameter

parameter int primeArray [11] = '{3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37};
...
genvar n;
for (n = 0; n &lt; 11; n++) begin : gen_loop
        PrimeCounter #(primeArray[n]) counter ( .match(match[n]), .* );
end


working example here

I added initial $display("%m id:%0d",id); into my PrimeCounter, output is as follows:

# dut.gen_loop[0].counter id:3
# dut.gen_loop[1].counter id:5
# dut.gen_loop[2].counter id:7
# dut.gen_loop[3].counter id:11
# dut.gen_loop[4].counter id:13
# dut.gen_loop[5].counter id:17
# dut.gen_loop[6].counter id:19
# dut.gen_loop[7].counter id:23
# dut.gen_loop[8].counter id:29
# dut.gen_loop[9].counter id:31
# dut.gen_loop[10].counter id:37