Shifting a result in 16-bit register
What you try to do doesn't work in VHDL

tst &lt;= unsigned(q sll 2);

tst is an out port of type STD_LOGIC_VECTOR (15 downto 0) and q is actually the same. As correctly stated in the comment, you cannot perform any action on an out-port that requires reading it, so q sll 2 doesn't work.

So define an internal temporary signal e.g. signal q_int : std_logic_vector(15 downto 0). Use this in the result register port map and to perform the left shift.

REG0: reg16 port map (Bit8_multi_result, clk, rst,load, q_int);
q &lt;= q_int; --to still have the same result at q
tst &lt;= q_int sll 2;


Note that the unsigned casting in the line with the sll is wrong as both types are std_logic_vectors.

Edit
As I've learned from the comments, reading from an output port is allowed since the VHDL2008 standard. So it should be sufficient to just correct the unsigned cast.