T-flip flop in Verilog
Your title and question ask about a T flip flop, but then you post code for a JKFF.

While a TFF can be built from a JKFF (by tying the inputs together), you can accomplish a TFF in much simpler code:

module tff_sync_reset (
    data, clk, reset, q
);
 input data, clk, reset; 
 output q;
 reg q;

 always @ ( posedge clk)
 if (~reset) begin
     q &lt;= 1'b0;
 end else if (data) begin
     q &lt;= !q;
 end

 endmodule