FPGA double buffer strategy
One possible strategy could be to use stale bits. Dunno if that's standard terminology, but it's similar to a dirty bit. Writing a new entry will clear the corresponding stale bit in the unlocked buffer and set the bit in the locked buffer. After switching buffers, have an internal copy routine transfer every entry marked stale in the unlocked buffer from the locked buffer to the unlocked buffer. In this way, new data written while the copy is in progress will not be overwritten, and all the old updates should be retained. The only thing you need to do is ensure that there is enough time for the copy operation to complete between buffer switches, or you need some sort of optimization to keep track of which entries are stale so you don't have to iterate over all of them, making the copy operation faster.

Another possible strategy could be to store the updated entries while a single buffer is locked, then apply only those updates when it is unlocked. If only a handful of entries are updated, then this might be more efficient. The updates could be stored as a linked list or similar data structure so that the list can be traversed efficiently while multiple updates to the same location can be coalesced.