Multi-processor memory controller chips
I think what you have in mind might be a "DMA controller". DMA = "Direct Memory Access". The microprocessors will need to be DMA-compatible.

An alternative would be to use bidirectional buffers for this particular memory bank, one set per microprocessor, and some sort of "shared memory bank active" semaphore or handshake between microprocessors such that no two are trying to access the same memory at the same time (a condition that could have all sorts of bizarre side effects); shared memory access isn't super-simple to implement, and timing for controlling that semaphore would be critical.

The low-tech way of accomplishing it would be to equip each microprocessor with a slot for SD cards (of whichever footprint). Then you could "sneakernet" the shared memory.