VHDL: Is there a tool that automatically generates the signals (for use in testbench) and a component instantiation if an entity is given?
Emacs with VHDL mode can do that: 
set the cursor inside a entity, choose 

VHDL-&gt; Port -&gt; Copy


then 

VHDL-&gt; Port -&gt; Paste as Testbench 


generates a testbench architecture with entity, architecture, signals, instance, clock generator and stimuli process. The testbench look and feel can be defined in the vhdl mode options: 

| [-]-\ Group Vhdl Testbench
|     |--- Option Vhdl Testbench Entity Name
|     |--- Option Vhdl Testbench Architecture Name
|     |--- Option Vhdl Testbench Configuration Name
|     |--- Option Vhdl Testbench Dut Name
|     |--- Option Vhdl Testbench Include Header
|     |--- Option Vhdl Testbench Declarations
|     |--- Option Vhdl Testbench Statements
|     |--- Option Vhdl Testbench Initialize Signals
|     |--- Option Vhdl Testbench Include Library
|     |--- Option Vhdl Testbench Include Configuration
|     |--- Option Vhdl Testbench Create Files
|     |--- Option Vhdl Testbench Entity File Name
|     `--- Option Vhdl Testbench Architecture File Name