Unexpected indeterminate outputs from verilog conditional operator
I found the answer, and it was from a surprising source -- the testbench code had an incorrectly defined connection for the ififo_di output:

wire ififo_di = 0;


The 1s produced were being merged with the zeros hardwired as the output and generating an indeterminate result; I would naturally have expected this to be an error condition, but it seems it isn't.