Writing to a Register happens one or two clock cycles after asserting write enable?
The problem is with your testbench's use of #(tclk*N) followed by the use of blocking assignments to your design's inputs—it's a race condition. Your testbench should be using non-blocking assignments to any signals synchronized to the rising edge of tclk. Or you can adjust your testbench initial block so that the signal changes do not coincide with the rising edge.