single-cycle design using and shared memory for both data and instruction
Your question is making some assumptions it shouldn't.  However, you have answered this yourself in large part.

In general a memory can do one access at a time.  Since fetching the instruction and fetching the operand are two separate accesses at two separate addresses, they must be done sequentially with traditional memories.  Even if not, the instruction has to be fetched first before you know that the operation requires a data fetch and then at what address.  The logical sequence is inherently sequential.

That said, there are various speedup techniques beyond the conceptually simple scheme of a traditional processor.  It would be too long to get into them here, but three that immediately come to mind are caching, pipelining, and separate instruction and data memories.  All these are used to various extents in current mainstream products.  Real modern processors are no longer as simple as what you are assuming in your question.

For example, most small microcontrollers use a harvard architecture, which means separate instruction and data memories.  They can to simultaneous accesses since they are separate memories.  However, there is still the issue of having to fetch and decode the instruction before knowing what, if anything, needs to be read from or written to data memory.  This is usually dealt with to various extents with pipelining, pre-fetching, and other techniques.

I can't reproduce a whole college level course on computer architecture here, but hopefully I've given you enough keywords so that you can find lots more information on your own.