External clock with Arty Z7 FPGA development board
If the frequency is low (which is usually the case for audio applications), generally what is done on FPGAs is to use clock enables.  The idea is to detect the edges of the input signal with a fast core clock and generate single-cycle pulses.  Then use those pulses to sample/latch in the input data and control internal operations.  With that setup, there is no need to use a specialized global clock capable input pin to supply the clock.  This also means you don't need to deal with clock domain crossing because all of the logic is in the same clock domain.  The internal clock can also be much faster, enabling pipelined processing and even time-interleaving processing of multiple channels using the same logic.