Shift Registers for generating codes
Simple Words.
It is a binary  sum of &quot;certain&quot; bits in a shift register of length N to give some undefined cycle bit pattern.  There is an optimal configuration of feedback which has certain math  properties of a  flat freqeuncy response or even  spectral density of frequencies (with constaints).  (not obvious with only 4 bits) This is used for bit pattern generators and cyphers.
These called Max-length pseudo-random sequence generators.  Your example is not one of them.
You are showing a non-inverted XOR symbols so we know that a forbidden starting  point is all 0's and would never change.
So one starts with PRESET or all 1's or adds an inverter to the feedback, to allow a starting with a master RESET or all 0's.
This requirement for choosing the polarity of feedback (+/-) is necessary to determine the forbidden state.
N bits determines the maximum number of clock cycles for the repeating &quot;Pseudo-Random&quot; (PR) pattern&quot;.  Since it repeats, it is not truly random.

There  is a range of different cycle patterns for any random connection of feedback . There may be short or long cycles.  Your schematic is not ideal.
, for which I have taken the liberty to simulate.

Details
Monic Polynomials which can be used to express the stages for  feedback terms for a maximal length random sequence.  Consider the + 1 as an odd parity term with negative feedback or an inverted XOR sum.
$$ PRBS.4 =   x^{{4}}+x^{{3}}+1 $$
.
$$   PRBS.7 =  x^{{7}}+x^{{6}}+1 $$
$$    PRBS.9 =   x^{9}+x^{5}+1 $$
$$  PRBS.11 = x^{11}+x^{9}+1$$
$$    PRBS.15 =  x^{{15}}+x^{{14}}+1$$
$$    PRBS.20 =  x^{20}+x^{3}+1$$
$$    PRBS23 = x^{{23}}+x^{{18}}+1$$
$$    PRBS31 =  x^{{31}}+x^{{28}}+1$$   etc

Your schematic is wrong for maximal length and has taps on 1,3,4 instead of 3,4  shown above in 1st equation in reverse order.

My simulation has a (mouse) switch ( ignore floating input for simplicity) to go between your schematic and the maximal length sequence for N=4 bits. Note that this becomes a divide by 15 counter on the AND gate pulse output thus 100Hz /15= 6.66 Hz a the Fourier spectrum of one of the outputs is shown in Red. With all the harmonics as expected.  This would be a smoother flat spectrum with more bits e.g. N=15 or N=31

But are special conditions to produce a maximal length pseudo-random sequence generated (ML-PRSG).  This determines the n stage that need to be added for feedback.  This pattern length is \$2^N -1\$ clock cycles.
If you are guessing you could end up with a shorter length sequence , which is not very useful. ;)
Here is a list of taps to the polynomials represented by each stage of delay using a shift register of D FF's.  , some of which are above.
REFS:
https://en.wikipedia.org/wiki/Pseudorandom_binary_sequence#Practical_implementation
https://en.wikipedia.org/wiki/Linear-feedback_shift_register
https://en.wikipedia.org/wiki/Pseudorandom_number_generator