Negative slack while designing a feedback controller using Xilinx System Generator
It doesn't look like the delay you added after the Constant block will have any effect (there's nothing to delay - it's (apparently) just a constant signal). Is there more work happening in there that's not obvious?

The bigger question is what's the propagation time through those AddSub blocks? If the total delay from {In1,In2} to {Out1} through those two blocks is longer than a clock cycle, then a transition on those inputs isn't guaranteed to be reflected at the output within one clock. That's the negative slack, basically.

There can be designs that are intended to take multiple clock cycles (imagine your AddSub latched the inputs, processed them over a few cycles, then latched the results), but the constraints would need to be specified properly for that (it's not clear that's what's happening here).

Xilinx's Timing Closure User Guide can be helpful in debugging such issues.