Gated clocks and clock enables in FPGA and ASICS
To answer your question, the same guidelines do not apply to ASICs and gated clocks are used very often to reduce power consumption.

In FPGAs, clock signals have dedicated routing resources that ensure low skew delivery of the clocks to fairly large areas of circuitry. If you try to gate the clock then the output of the gate will probably be forced to use normal logic signal routing resources, which can introduce significant delays and cause large clock skews. FPGAs are designed with some assumptions about how logic design should be done, and one of those assumptions is that you use clock enable signals rather than gated clocks. For common FPGAs the power consumption is enormous anyway so there is little motivation to gate the clocks.

ASICs are a much different beast. When you design an ASIC you have complete control over the gates and wires. You can safely create a gated clock and make sure that the gated clock signal is distributed properly. This is a very common technique for minimizing power consumption. For example, look at a modern microcontroller and you will see that you can, in software, turn the clock signal on and off for large chunks of circuitry such as a UART. The downside is that ASIC designers must use very expensive and sophisticated timing analysis tools to get this right.