Read-only for some masters but read-write for other?
If you have a look at the latest AXI document you will find that there are several descriptive 'signals' which tell what type of transaction is on the bus. It also holds an ID which tells where the transaction is coming from. 

You can then have a memory (or any other slave device) which would accept only certain type(s) of transactions. Or only transactions from certain masters or any combination of the two. 

You can, and I have, design a system where the acceptance of transaction can be programmed for each slave. (Of course there the transaction permission registers can only be written using supervisor access mode and only if the source is the main processor).

If you are not familiar with AXI: it is a bus protocol designed by ARM and used by many systems which have ARM cores.