ADC problem with ATMEGA32 using external clock more than 8MHz
You might need to slow down the ADC. The analog to digital converter runs at half the system clock frequency by default so at 6MHz the ADC's input clock is at 3MHz. Setting ADCSRA |= 2 (for the ATmega328, datasheet section 23.9.2, page 265) divides the clock by 4 instead of by 2. 12MHz / 4 = 6MHz / 2 = 3MHz.