Output from latch clock
Here is a diagram of a TTL Nand gate straight out of Wikipedia. The input buffer for the clock line is going to be the same as this except it will only have one of the two inputs (A or B). You can see that this will tend to pull up the input the exact voltage that you get will depend on a number of factors e.g. voltmeter impedance, characteristics of the input transistor and the values of the other components built into the buffer.

The point is that this should not be left floating it should be tied to ground or through a pullup to VCC the chip itself will not define the level of an input for you. For any case you need to define all of the logic inputs even for a minimal example.