SPI frame on a dsPIC
dsPIC SPI manual Figure 35-3: SPI1 Master Mode Timing:-


  Note 1: If there are no pending transmissions, SPI1TXB is transferred
  to SPI1SR as soon as the user application writes to SPI1BUF.


It takes some time for the transmitter to start transmitting. If the shift register MSB was previously 0 and the MSB of your data is a 1 then you will see SDO go high at the start of this period, but if they are both 0 then SDO will stay low. 

However if your data is 'queued up' in the TX buffer then the transmitter must wait until the previous Byte has been transmitted before reloading the shift register, so you won't see this 'early' transition.  

In the timing diagram this period is shown in grey, which means the level is undefined. In any case you shouldn't have to worry about it. The only thing that matters is that SDO must be stable when SCK goes from low to high.