not sure how to draw the nandgate schematics for my segment display
You were not that far from the answer.  First thing is to isolate each output (BCD segment, that will be named a,b,c,d,e,f,g) from the inputs (BCD bits, that i will name ABCD)

so : A = 2⁰; B = 2¹; C=2²; D=2³
and lower cap abcdefg will be lines on your 7-segment display.

I do not have a scanner at hand, but here would the first Karnaugh map go :

FOR 'a' segment :
(This is from your BCD representation table)


The a segment is on for ABCD = '0000' => 1
The a segment is off for ABCD = '0001' => 0
The a segment is on for ABCD = '0010' => 1
The a segment is on for ABCD = '0011' => 1


(So on, you got that part almost right, except for the 7 and 9 BCD digits)

   \AB| 00 | 01 | 11 | 10
 CD  \---------------------
 00   |  1 |  0 |  X |  1
 01   |  0 |  1 |  X |  1
 11   |  1 |  1 |  X |  X
 10   |  1 |  1 |  X |  X
 ------------------------


Repeat this table for each segment of the 7-segment display, which should yield 7 different Karnaugh map.

Now, you need the equation of the map.  For the a-segment.  Personnally, i initially prefer the SOP (Sum-Of-Product) equation (consider !x = not(x) and !xy = not(x)+y):


You can make a 2x4 group from the two bottom lines (A=X; B=X; C=1; D=X => C)
You can make a group with upper right corner (A=1; B=X; C=0; D=X =>A!C)
You could put a XOR gate for the remaining, but since you need NANDgates, prefer only AND/OR constructs, even if XOR gate can be emulated with NAND : !A!B!C!D ; !AB!CD


a = C+A!C+!A!B!C!D+!AB!CD

You build such equations for each table.  When done, you can use boolean algebra to perform some rearrangement in order to optimize redundant block (common sets between each map)

Finally, to draw the circuit, you need to convert each term of the equation using equivalent NAND gates circuit.  You may use this simple NAND gates logic reference from Wikipedia.

For 'a' circuit, it would yield :







simulate this circuit &ndash; Schematic created using CircuitLab

Well you could do that kind of schematic for all 7 segments and merge redundant parts of circuit to get the final optimized circuit.  As you can see, some gates could also be stripped of (not gates, namely), but I haven't for two reasons : 


Educationnal purpose
To be able to mention that in a digital circuit that conveys time-critical data, you would try to ensure that all signal path would convey the signal will an almost equal time delay (inserting buffers and unrequired NOTs) to match that specification, so that edge trigerring FPGA inputs (for example) would not trigger "randomly" while your signal propagates throughout your circuit.