How can I add a signed vector with an unsigned one in VHDL?
The easiest way might be to to convert both signals to an integers, add them, and then convert back to signed. There are to_integer functions for both signed and unsigned. You can also try simply typecasting the unsigned signal into a signed signal, however that might turn 15 ("unsigned 1111") into -1 ("signed 1111"), and might mess up your addition.