Can I use the same file for a diferent FPGA speed grade?
If the new speed grade is slower than the old one, you should resynthesize to make sure that the timing requirements are met.  The FPGA will be routed differently to meet the slower timing characteristics, and it is possible that you will have to make adjustments to the HDL source code to get timing closure.  This is not necessary if you are moving to a faster FPGA.