4024 cmos counter not resetting
74HC4024 clocks use negative edge and positive Reset (not shown on your schematic)
74HC164 clocks use positive edge with negative Reset
This should count 1/2 after the shift register is clocked and reset after the - 16th bit when you only have 15 bits. Is that what where you went wrong??


How many clock pulses did you send?

Also 74HC4024 counters should be labeled Q0 to Q6 ( 7 bit counter ) although you have the Q1 as the correct pin for Q0, the first binary output.