what is a transceiver reconfiguration controller on FPGA
There are some cases, when the transceiver is used for application, that can work in various modes or speeds. E.g. SDI (http://en.wikipedia.org/wiki/Serial_digital_interface). If You use SD quality video signal, the data rate is 270Mbps, if You connect HD video HD-SDI to the same interface, then the data rate is 1485Mbps. Same for other SDI standards. Now the deserializer does deserialization of the data... From SD-SDI it extracts 27Mhz clock and 10 bits of data. From HD-SDI it extracts 74MHz clock and 20 bits of data. Because of internal PLL clock difference and data bus difference, You need to reconfigure transceiver for proper clock recover, because the clock has to be recovered from the same wire as data.