Ramp compensation for UC1843 and UCC38C44
There should not be a difference between the two circuits beside the rad-hard qual for one of them provided that the external slope is added to the CS pin. Slope compensation consists of reducing the current loop gain by adding an external positive slope to the CS pin. It helps taming the double sub-harmonic poles located at \$F_{sw}/2\$. If you now decide to subtract the ramp from the CMP pin instead, then yes, the divide-by-three gain enters the picture as it reduces the internal slope effectively applied at the CS comparator.

Rather than taking a portion of the oscillator ramp, it is more rugged to actually build a lower-impedance ramp generator from the DRV pin. It has been implemented by R. Ridley in the 90' I think and has proven to be an excellent solution versus the solution from Unitrode.

The ramp is generated using a simple \$RC\$ network and a switching diode. See the below slide excerpted from this APEC 2018 seminar:



The divide-by-3 circuit affects the loop gain and enlarges the dynamics of the feedback signal: 0 to 3 V to produce a 0-to-1-V setpoint versus no divider which would produce a 1:1 CMP to CS setpoint, constraining the op-amp dynamics. The two series diodes provide a true 0% duty ratio setpoint when the CMP pin falls below \$\approx 1.2\;V\$.