Meaning of two NOT gates in parallel
They are directly in parallel, just drawn weirdly, usually this is to increase the amount of current that can be driven over just a single not gate, they would normally have some series resistance on the outputs, but in some cases can get away without it (the mosfet capacitance takes longer to discharge than the maximum difference in gate delays)

for the application they are in, a mosfet gate drive, the faster you can charge / discharge the gate, the sharper the transition, and possibly less heat generated during the transition, equally the NOR gates are in parallel for the same reason, to increase how quickly it can switch the mosfets.

For some fast pulse sources e.g. for time domain reflectometery you may also find similar, with 6,8,10 or more in parallel to give a very fast transition on a capacitive load.