Producing a VHDL design unit from a State Diagram
What you have there is the state diagram of a Mealy Statemachine (en.wikipedia.org/wiki/Mealy_machine)

It's a very simple one that has only 1 input and 1 output, that's what the notation on the transition arrows represents (input/output). 
I'm wondering where you found this diagram, because it doesn't make much sense.
So what this diagram technically illustrates is the following


Let's assume the entry point is SA (State-A)
If your input is '1', the transition guard to SB is true, so you change to SB and set the output to '0'. At SB (State-B) you have the same transition guard to SC (State-C) and again the output is '0' - so for now this is your final state.


What's rather strange are the two transition guards between SA and SC, both have a guard of input '0', this means from any of the 3 states you'll end up toggling between these two states as long as your input is '0' - as correctly mentioned in the comment, the output would toggle as well.