VHDL: Instantation question
You must use some signals, you can't map straight from one pin to another (I'm also using direct instantiation to avoid creating component declarations - see also my answer here):

signal aout : std_logic_vector(5 downto 0);

A: entity work.componentA port map(
    output_pin =&gt; aout
); 
B: entity work.componentB port map(
    input_pin =&gt; aout(5 downto 3)
); 
C: entity work.componentC port map(
    input_pin =&gt; aout(2 downto 0)
); 




Aside

You seem to be confused in your instantiation syntax.  You wrote:

componentA:componentB port map (...


implying that componentA connects to component B.

What is actually being said is

individual_name_of_component: name_of_entity


So you pick an entity which you are instantiating on the right of the : and give it a name on the left.