Should every FPGA design include a reset signal?
Pretty much every design that has a register or a latch should have a reset. Now whether or not that reset is anything more than the power-on-reset of the FPGA is another question.

The following is a not-complete list of places which should always have a specific reset (either power on or design specific such as push button), and places where it probably doesn't matter so much.

Reset a must:


Control Signals - any signal which controls the flow of data through a system should have a reset signal to ensure that they are in a known state. For example, if you have a register which when high ends the world, you probably want to know that it won't be high when you turn it on.
Data Valid Signals - any signal which indicates that data on a bus is valid. If you reset the circuit, you want to know that no data bus is marked valid unexpectedly (e.g. data loading into FIFO).
Counters - things that count should probably have a reset so that you know what value it started counting at. For example if you have a counter for a clock divider, you probably want it to always start at the same point after reset to ensure deterministic behaviour.
State Machines - most have an IDLE state which is entered after power on or reset to wait for some event to occur. These should therefore have a reset


Reset is optional:


Some Data Buses - I say some. Any which are qualified by a valid signal (see above) don't really need reset signals, and not adding them can save routing pressures and timing issues with reset signals, expecially on large data buses. The reason they aren't required is because the valid signal should have a reset. Whenever the valid signal indicates the bus is invalid, any downstream logic should be designed to not rely on the value of the data - the data is effectively don't care. It is assumed that you will change the value of the register anyway before you assert valid.
Pure Combinational Circuits - Any stateless combinational circuit. There is no point having a reset because the output of the circuit depends only on the inputs - there is no way of having an invalid/unknown value after power on.
Non-Critical Registers - For lack of a better term. Basically anything where you have verified in your design that it works fine regardless of what value in on the register - i.e. you don't care what the value is. For example if you want to test an adder circuit as in your case and are simply buffering and output input signals, then a reset is not really necessary.


There are probably more for each list, but that is a good starting point. If there are any key places I've missed, let me know in the comments.