AND/NAND LED Flasher circuit help?
Initial conditions:


C1 discharged so NAND pin 4 is high.
This feeds back to AND pin 1 and since 2 is permanently high AND pin 4 goes high charging up C via the parallel paths of (R1 and diode) and R3.
When C1 voltage is high enough NAND pin 4 goes low.
AND pin 1 now goes low and C discharges through R3 only.
Repeat.


The diode makes the waveform asymmetric. C charges through R1 and R3 but can only discharge through R3.


  How do I tune R1, R2, R3, and C1 to adjust frequency and duty cycle?



C1 charge-up time, \$ \tau_1 \$, will be given approximately by the time constant \$(R1 || R3) \times C\$. (where "||" is the parallel resistor value.) 
The discharge time, \$ \tau_2 \$, by \$R3 \times C\$. 
The total period of each cycle will be \$ {\tau_1 + \tau_2} \$.
The frequency will be \$ \frac {1}{\tau_1 + \tau_2} \$.
The duty cycle will be \$ \frac {\tau_1}{\tau_1 + \tau_2} \$.
The diode introduces a further slight complication in that there is a voltage drop across it. The effect seems to have been minimised by using a Schottky diode which has a lower voltage drop than a regular silicon diode.





  The \$V_{IH} \$ level is 3.5 V, and the \$V_{OL} \$ level is 1.6 V. How does that change the equation?


It doesn't. I assumed the thresholds would be about those proportions.

Going from low to high C will initially be at 1.6 V and the charging voltage close to 5 V. Switching will take place at 3.5 V which is \$ \frac {3.5 - 1.6}{5 - 1.6} = 56\% \$ of the way to fully charged. You can see from Figure 1 that this is quite close to the 63% value of one RC time constant, \$ \tau \$.

Going from high to low C will initially be at 3.5 V and the discharging voltage close to 0 V. Switching will take place at 1.6 V which is \$ \frac {3.5 - 1.6}{3.5} = 55\% \$ of the way to fully discharged. This time you can see from Figure 1 that this is not close to one time constant, \$ \tau \$ but probably good enough. 

Don't forgot that you will have variation from chip to chip.



Figure 1. RC charge / discharge curve.


  Furthermore, what role does R2 play? I was presuming there was some discharge through it, at one point at least....


On power-off the NAND gate will have no supply. C will discharge through the input protection diodes and will try to power up everything on the PCB that's connected to that power rail. R2 limits that current to a value that the protection diodes can handle. In normal operation it has no effect on the timing because the NAND inputs have such high impedence - typically GΩ.