What device controls whether a signal is high or low
Your question is very broad so here's just a simple example.
We have an electronic counter using various latches shown here as SR (set-reset) latches (for want of something better in the component library). On power-up we need to reset the counter to zero to avoid it starting at a random number.



simulate this circuit &ndash; Schematic created using CircuitLab
Figure 1. A power supply, on-off switch and power-up reset circuit to reset all the latches.
How it works:

When SW1 is open (as shown) C1 will discharge through R1 and the rest of the circuitry. The voltage across it will be 0 V.
When SW1 is closed to power up the circuit NOT1 and LTCH1 to LTCH3 will power up. The latches could power up with their Q outputs high or low but we don't want that.
Since C1 is initially at 0 V, the input to NOT1 will be at 0 V (low) and, since it is an inverter, the output will be HIGH. This is fed to the R (reset) input of each of the latches and this will force their Q outputs LOW.
R1 - C1 forms a time delay with a time constant τ = RC = 10k × 1μ = 10 ms. The voltage will rise exponentially and after about 10 ms will reach the HIGH threshold of NOT1 causing it to read the input as logic '1'. The output will switch to logic '0' removing the reset from the latches and enabling them to count when their 'S' inputs are triggered.

The above should give you an idea of how we can have the input of one device controlled by an external event (SW1 closing) and that controlling other devices by switching internal signals.