Negative level shifter
I'd rather go with a simple common base level shifter







simulate this circuit &ndash; Schematic created using CircuitLab

R1 is choosen not to saturate Q1 looking for "high speed" turn-off. In this conditions fall time is mostly ruled by R2 and output stray capacitance.  

Output clock  more probably swings from 0V to around 13V w.r.t the -15V line. This should be more than adeguate to 4047 input.