Verilog if else if construct
You have to look at the BNF to understand how code is parsed. Indenting makes code easier to read, but is meaningless for the compiler

conditional_statement ::= // from A.6.6
          [ unique_priority ] if ( cond_predicate ) statement_or_null
          { else if ( cond_predicate ) statement_or_null }
          [ else statement_or_null ]


And a begin/end is considered a statement, as well as another nested conditional_statement. So your code is illegal because there is no statement_or_null after if(condition4) Adding a null ; would make the last else go with the last if.

Once you have a completely legal always block, a synthesis tool looks at the flow of variable references across all possible branches. If there's a possibility that a variable could be read without first being written, then is gets implemented as a latch. It's a bit more complicated than that; do read your synthesis tool manual.