Design a full adder of two 1-bit numbers using multiplexers 4/1
Yes, it's correct. 

This is the sort of optimization that used to happen manually in the old days of FPGAs and before that with PALs. You had to rejigger your result based on selection and minimal logic gates.

I've not run across this solution, but then I've never been stuck with just multiplexors. 

Oh incidentally,... one more multiplexor would do that inversion (generating the invert in the previous stage), so you could easily create a large adder with a three-pole switch for each binary digit. No logic needed. Nice.