VHDL - Send string using a function or similar
There's a lot of digital design concepts you'll need to know to do this. I guess an outline would be:


Design a finite state machine that shifts out a single 10-bit serial frame (assuming 8-N-1 so one start bit, 8 data bits, 1 stop bit). The module accepts a clock (your baud rate) and some 8-bit data, as well as a "go" (start shifting data) input and "done" (all bits shifted) output indicator.
Design a baud rate generator module that produces your clock of say 9600 baud. This will probably be some kind of counter that you'll compare to a value to know when to toggle the baud clock output and reset the counter. Its input will be whatever clock sources are available on your FPGA board, probably something in the MHz range.
Design a FIFO module for storing data to be transmitted serially. The FIFO has data in, data out, a clock and reset, and status flags for full and empty.
Design another state machine that unloads data from the FIFO and transfers that single byte to the shifting-out module you previously developed. This way when the FIFO is full, it will send out new characters until empty. It will need to examine the FIFO empty flag to know when to start and stop.
Make a top-level module that loads some data into the FIFO. Maybe your development board has buttons or switches to accomplish this, you can load in a binary word at a time to the FIFO and then press a button to make the FSM start outputting data byte by byte.


At every step you need to write a test bench module and validate all aspects of the module you are testing. It's a critical part of development even though some people put it off until the end.

I'd read up on state machine design to get more information. You need to know about Mealy and Moore type state machines, how the control unit (FSM) controls a data path which operates on data, etc.