Trying to measure a pulse width and then send pulse of same width using Verilog
You don't need to measure the output pulse, you just have to set it high for the same number of clock cycles.
One way to do this would be to have two separate counters, an input counter and an output counter. The input counter could count up from 0 as you are already doing. Whenever you are done measuring the input count, you could then use that to set the initial value of the output counter. Then every clock cycle, have the output counter count down, stopping at 0. Set the output signal high whenever the output counter value is nonzero.
You could also possibly use the same counter for both input and output (count up while measuring input, then count down for output), but it will probably be a little trickier to handle all the corner cases properly.
By the way, when you say &quot;I can then take the last number from this counter and multiply it by the clock time period to get the time,&quot; I just want to make sure you mean just for a debug output. You don't need to do this multiplication within the design itself.