Verilog : Using previous generate iteration's wire in current iteration
Declare the intermediate wires between the stages inside the generate loops

wire Ain[0:15];
genvar Cv,Bv,Av;

wire Din[0:1];
mux2 Dm( Y,D ,Din[0], Din[1]);
for (Cv=0;Cv&lt;2;Cv=Cv+1) begin : Clevel
   wire Cin[0:1];
   mux2 Cm( Din[Cv], C, Cin[0], Cin[1]);
   for (Bv=0;Bv&lt;2;Bv=Bv+1) begin : Blevel
      wire Bin[0:1];
      mux2 Bm( Cin[Bv], B, Bin[0], Bin[1]);
      for (Av=0;Av&lt;2;Av=Av+1) begin : Alevel
          mux2 Am(Bin[Bv], B, Bin[8*Cv+4*Bv+2*Av], Bin[8*Cv+4*Bv+2*Av+1]);
      end
   end
end


This might not be exactly hooked up the way your picture shows, but it should be enough to get you started.