Increase EEPROM capacity and data lines
You are confusing address space with data space.

You do indeed need to multiply your address space by 8, but you only need to multiply your data width by four.

As such you need a matrix of memory devices that is 8 rows by 4 columns. That is, 32 devices.

You are correct, you need to decode the upper three bits of the 1M address bus to select the appropriate row. Then feed each device across that row into the appropriate byte of the 32 bit data bus.

If the memory is byte addressable you will need to offset the address on the devices to ignore the bottom two bits. That is, feed address bus bit 2 to device A0... etc.

Also, make sure whatever is driving the address control and data lines has enough fan-out to drive all those devices in parallel. If not, you will need additional buffers in there with consequent timing delays.