error defining multiple parameters
You can only initialize an unpacked array parameter in SystemVerilog. 

parameter signed [15:0] b [0:18] = {26,270, ... ,26};


In Verilog, you would have to pack the array and the select a slice of the parameter. But each slice would be unsigned. 

   parameter [0:(16*19)-1] b = {16'd26, 16'd270, ... , 16'd26};


Then each slice b[I] unpacked would be b[I*16+:16] packed.