Numeric literal constant in VHDL treatment
In VHDL, the constant declaration requires that the type is specified. The length is usually baked in to the type. For example

constant my_constant : unsigned(63 downto 0):= X"0000000000000001";


Whenever a signal is driven by a numeric constant, it's necessary to match the constant length with the signal length. 

For example:

signal my_signal : unsigned(63 downto 0);
....
my_signal &lt;= X"0000000000000001";


Since VHDL is strongly typed, if the literal length does not match the signal declaration, it will produce an error. 

As jeff mentioned, it's also possible to use to_unsigned, as follows:

my_signal &lt;= x + y + to_unsigned(1,my_signal'length);