DG flip-flop behavior?
The first one is a negative-edge-triggered D flip-flop with clock enable. When EN is high, the input at D is latched on to the flip-flop at the falling edge of the clock. When EN is low, the previous data remains latched, and the input has no effect.
The second one looks like a level-triggered D latch. When G is high, the latch becomes transparent ie., the input at D appears at the output of the latch. When G becomes low, the previous data remains latched, and the input has no effect.