Should a D Flip Flop store its input on clock rise?
Firstly there are D flipflops available that trigger on (Depending on the part) the rising or falling edge. 

Secondly D changing too close to the triggering clock edge (which ever one it may be) tends to cause the mess known as metastability where the output can hang in an undefined state for an undefined length of time and can even (depending on what the following device thinks logic thresholds are) switch states a few times. The datasheet has values for setup and hold times, violate them at your peril, because 1 or 0 are NOT the only possible outcomes!

This is a major pain when crossing clock domains in things like FPGAs as the fixes are basically to cascade a few flipflops on the output clock domain and do statistics on how often it still bites you. 

So the answer to your question, is either, both, neither depending on how unlucky you get, don't do that!