verilog assign different width input
If you want to leave the pin in the top level of the design, but want Quartus to not route it to a physical pin, you can make a "Virtual Pin" assignment in the assignments editor.

Simply open the assignment editor in Quartus, then add a new assignment at the bottom by clicking in the empty row. Select "Virtual Pin" as the type, and the name of the pin in your top level design as the target (e.g. JTAG_TDI[3]). Set the value of the assignment to "On".

Alternatively, simply remove the pin from your design. For example:

output [2:0] JTAG_TDI;
wire [3:0] JTGA_TDI_pad;
assign JTAG_TDI = JTAG_TDI_pad[2:0];

...
     .TDI_out(JTAG_TDI_pad)


Having said that, based on the comments and description, the JTAG_TDI signal is supposed to be an input, in which case you should declare it as such and can simply do:

input [2:0] JTAG_TDI;
...
    .TDI_out({1'b0,JTAG_TDI})