set and reset of D flip-flops : always physically present?
I believe FPGAs always have an asynchronous reset for the whole device, as part of the programming process. I don't know whether you can always wire individual async resets to individual cells.

In ASIC technology, the cell libraries have the option of flops with and without asynchronous reset. Which one gets used depends on what you asked for in Verilog. If you didn't design in a reset, you don't get one.

You could have a synchronous reset instead: Reset: synchronous vs asynchronous

By "discrete", do you mean 74-series style individual devices?