Inrush control circuit
1:  When CHG_OK is high the R10 is open-circuit and both series pass FETs conduct with a slow turn-on time. When this signal goes low R10 shunts Vgs quickly as the 0.1uF is discharged in 1us then FETs are shut off.

2: low ESR caps of 10uF have an inherent \$\tau=\$ESR*C&lt;=10us constant in any given family at some Vdc rating and size.    


High ESR or General Purpose has a  τ>200us thus high ESR
you can reduce the ESR by using parallel Caps of the same size but not by increase C value unless the sub-miniature SMD size is also substantially increased. However, experience dictates that shunting smaller low ESR Caps improves results immensely as the length of the cap also increases inductance 0.5nH/mm which then reduces the Series Resonant Frequency (SRF) which increase rise-time of current.


Expect a typical Panasonic 10uF low ESR to be &lt; 1 Ohm and 10 in parallel = 0.1 Ohm ESR which thus reduces voltage rise from dV=I*(ESR+dt/C)