How to borrow time in STA?
In the example you have shown, there are two clocks, the normal clock driving L1, L3, and a late clock driving L2 and L4. The late clock must be 3ns after the main clock. This gives 8ns required for the first path.
From L4 to L1, the launch is late, the path adds 2ns, and capture is on the clock edge.

Of course, the diagram is a simplification because it does not anticipate any window between setup-hold boundaries - but actually adding skew in the clock tree can compensate for hold problems which might otherwise be introduced where there exist very short paths. Hold can always be fixed by adding redundant logic (up to the point where different operating points overlap with setup and hold conflicting).

In ASIC flows, this optimisation is a natural part of the flow (performed after the first couple of passes). In FPGA, I expect it is less likely to be useful (since the structure makes very short paths less likely), and would require dedicating of a clock net.