Verilog - Wiring multiple hardware instances together
With access to System Verilog I would use a 3-dimensional array:

wire [31:0] a [0:N-1][0:N-1];


Now you can wire the ports using a[x][y].
For the module at position [i][j] you can use e.g. a[i][j] at the output. To connect that to the input of the next module you can there use a[i-1][j] or a[i][j-1] or if you need to connect diagonally even a[i-1][j-1]

If ever you must use Verilog (As I had to do before System Verilog came along) you use the same method as compilers use to map an N-dimentional array on a linear memory:

wire [31:0] a [0:N*N-1];


Now the index is a combination of j and i: a[j*N+i] (If I remember correctly)