How to design a control bit to turn unsigned binary into two's complement?
You're correct in your intuition that there's a better solution than a multiplexor selecting between two entirely independent circuits.

Recall the meaning of a positional number system, for an unsigned input \$a_3 a_2 a_1 a_0\$ the value is $$8 a_3 + 4 a_2 + 2 a_1 + a_0$$

For two's complement, the only change is that the sign bit takes on a negative place value: $$-8 a_3 + 4 a_2 + 2 a_1 + a_0$$

Now, the condition for comparison of two signed two's complement numbers is

$$-8 a_3 + 4 a_2 + 2 a_1 + a_0 &lt; -8 b_3 + 4 b_2 + 2 b_1 + b_0$$

Add the sign-bit terms to both sides, to get

$$8 b_3 + 4 a_2 + 2 a_1 + a_0 &lt; 8 a_3 + 4 b_2 + 2 b_1 + b_0$$

which is the unsigned comparison between \$b_3 a_2 a_1 a_0\$ and \$a_3 b_2 b_1 b_0\$

That is, you can use your control input to swap the sign bit, then feed the normal comparison logic.



If a multiplexer isn't one of your fundamental gates, then this "swap" adds non-trivially to the complexity.  So let's look at that inequality again:

$$-8 a_3 + 4 a_2 + 2 a_1 + a_0 &lt; -8 b_3 + 4 b_2 + 2 b_1 + b_0$$

Add \$8\$ to both sides and group:

$$8 (1 - a_3) + 4 a_2 + 2 a_1 + a_0 &lt; 8 (1 - b_3) + 4 b_2 + 2 b_1 + b_0$$

Note that \$1-x\$ is just the NOT operator.

$$8 \overline{a_3} + 4 a_2 + 2 a_1 + a_0 &lt; 8 \overline{b_3} + 4 b_2 + 2 b_1 + b_0$$

and this is again the unsigned comparison logic applied to the two inputs \$\overline{a_3} a_2 a_1 a_0\$ and \$\overline{b_3} b_2 b_1 b_0\$

Now your control input only needs to select between \$a_3\$ and \$\overline{a_3}\$ (and likewise for \$b_3\$), and this is just the XOR function.

Finally, your dual-mode comparator is made by simply taking your working unsigned comparison circuit, and feeding its inputs with

$$(a_3 \oplus S) a_2 a_1 a_0$$
$$(b_3 \oplus S) b_2 b_1 b_0$$