Unable to figure out VGA [Verilog]
Problems I see in your code:


640x480@60 uses a pixel clock of 25.175 MHz, not 25 MHz. The difference may be enough to keep some monitors from synchronizing. Consider using a PLL to generate the appropriate clock (50 MHz x72÷143 gives 25.1748 MHz, which is within 9 ppm), or targeting 800x600@72 instead, which uses a pixel clock of exactly 50 MHz.
The polarity of your sync pulses is wrong. 640x480@60 uses negative sync pulses -- HS and VS need to be low during sync, not high.
There's a typo in the definition of VS_END. You probably want to use the constant 480, not 6480.


Possible problems outside your code:


Do you have an appropriate constraints file? Are the signals being mapped to the right pins to reach the DAC?
Make sure your levels are correct. R/G/B are 0 to 0.7V; sync voltages aren't critical but should probably be 3.3V.