Correct way to define propagation delays in VHDL
Delays such as "wait for" and "after" are not synthesizable. That said, they way you separate the input and output datapath seems wierd. I would do something like this:

--
    -- 74153 implementation
    -- Dual 4-Line to 1-Line
    --

library ieee;
use ieee.std_logic_1164.all;


entity TTL_74153 is
  port(
  c0, c1, c2, c3: in std_logic_vector(1 downto 0);
  sel: in std_logic_vector(1 downto 0);
  g: in std_logic_vector(1 downto 0);
  y: out std_logic_vector(1 downto 0));
end TTL_74153;

architecture behav of TTL_74153 is


  signal mux_out: std_logic_vector(1 downto 0);
begin
  -- logic
  -- the vector indices aren't necessary, but i prefer them
  mux_out(1 downto 0) &lt;= c0(1 downto 0) when sel = "00" else
                         c1(1 downto 0) when sel = "01" else
                         c2(1 downto 0) when sel = "10" else
                         c3(1 downto 0) when sel = "11" else
                         "00";
 y= "00" when g(0) = '1' else mux_out;


end behav;