Is there an intuitive explanation of the classic edge-triggered flip flop circuit?
I think there is always an intuitive way to understand a circuit... you just have to be willing to do it... Let's try it...

The situation is difficult but intriguing - there is an unknown circuit in front of us and we begin looking for something familiar in it. As OP have figured out, there are three \$R\neg\$\$S\neg\$ latches in total (for simplicity, I will name them "RS latches"). But how are they connected to each other?

1. Figuring out the structure. As we can see, there is one MAIN LATCH (on the right) assembled by NAND 5 and NAND 6. The other two latches are connected to its inputs. The S LATCH (NAND 1 and NAND 2) is inserted before the S input and the R LATCH (NAND 3 and NAND 4) - before the R input of the MAIN LATCH.



So, our first conclusion is that we see an RS latch wich inputs are latched by the same RS latches... shortly, а "latched latch". Why is this done?

Then we see something else interesting and quite odd - the Q output of the R LATCH is connected to the R input of the S LATCH, and then the Q output of the S LATCH is connected to the R input of the R LATCH. In other words, both input latches are connected in a "global" positive feedback loop... as they say, they are "cross-coupled" like the single RS LATCH where two NANDs are cross-coupled. The Data signal is inserted in the global loop so it acts as a sole input to the big latch. What does all that mean? What is the sense of this additional positive feedback as they have such?

2. Investigating the operation.  It's time to look at the Clock. Initially it is low. Also, for completeness, assume some value of the Data input, e.g., "0".

Clock = 0. As the Clock is low, there are logical "0s" at the R input of the S LATCH (NAND 2) and at the S input of the R LATCH (NAND 3). They cause these outputs to be high... and this is the neutral input combination for the MAIN LATCH allowing it to hold undisturbed the previous Data. So the two input latches are blocked... and also, the BIG LATCH consisting of them is blocked (there are no positive feedbacks). 

Clock = 1. When the clock signal goes high (logical "1"), NAND 2 and NAND 3 are enabled and the input latches are unblocked. The positive feedbacks - two local and one global, begin acting... and the BIG LATCH is set to the state corresponding to the input signal Data (S LATCH - "1",  R LATCH - "0"). The data from its outputs is stored in the MAIN LATCH... that is forced to stay in this state (Q = "1") until the Clock is high.

And here is the key point of this circuit solution - from now on, the input latches can no longer be controlled by the input D... they are locked. So, if Data goes high until Clock is high, this will not change the latch states.

Clock = 0. When the Clock is low again, the NAND 2 and NAND 3 outputs are forced to be high... and the input latches are blocked again. There are two "1s" at the inputs of the MAIN LATCH; so it is released and begins holding its contents.

3. Final conclusion (answer). The trick of this clever circuit solution (7474 positive-edge triggered D latch) is to latch the inputs of an RS latch by RS latches. So this combination can be thought of as a gated D latch with latched input gates. While the Clock is low, the input latches are blocked; when the Clock is high, they are set by the Data input signal and can no longer be changed by it... the circuit is locked. Thus the circuit accepts the Data signal only during the rising edge.

So the circuit exploits the well-known property of the RS latch that the input signal (e.g., at the S input) can toggle it only once; that is why it has another input (R).

(I apologize for the rough drawing and the explanation currently made... but I had no clear idea of the answer at the beginning... and started developing it right now in front of you.)

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(I have replaced the picture with more qualitative... but I am not sure if this is better for the understanding...)