How do I produce WE in this diagram?
After taking a closer look at your diagram, my initial answer was not completely correct.

You need to use another OR gate to logically AND together (all of these signals are active-low) the WR- signal and the IO/M signal from the CPU. The output of this gate goes to all of the RAM WE- inputs. It pulses low only during memory write cycles, and not during I/O write cycles.

The issue here is timing. Your CE- signal is a simple decode from the address bus, so you need to use the WR- signal from the CPU to generate the correct timing for a WE- controlled write cycle to the RAM chips, in order to meet the required address and data setup and hold times. Since you don't want those writes to occur during I/O cycles that happen to have address values that match your RAM addresses, you need the additional gate.

If you can guarantee that no I/O write cycles will have addresses that match RAM addresses (in your firmware1), then you can dispense with the gate and tie WR- from the CPU directly to WE- on the RAM chips.



1 In other words, make sure that the upper address bits are zero. This may be inherently true on the 8085 anyway; off the top of my head, I don't remember what appears on the upper address bits during the data transfer cycle of an OUT instruction. (On the Z80, the contents of the A or B register appear there, which can create issues if you're not aware of it.)



Followup: I found a datasheet that states that the 8-bit I/O address appears on BOTH halves of the address bus during I/O cycles, so you would have to avoid using I/O addresses that match the patterns  xx101xxx, xx110xxx or xx111xxx.