best and worst-case delay of an adder
What you have drawn here is what we could call a logical schematic.  It is a schematic representing concepts, not an actual physical component.  You cannot estimate propagation delays with this.

Let's take an example.  If you have an FPGA, you usually describe a concept using a language such as VHDL or verilog.  Then you can write test benches to test the logical behavior or that concept circuit.  But this is just a conceptual simulation for ideal components.  You can feed a 1THz signal through your gates and it pass pass just fine.  There is no rise-time, no propagation delay, etc.  Now once you are confident about your circuit, you run perform a synthesis step.  The tool will map your logical concept to actual hardware.  FPGA are usually implemented with LUTs (multiplexer, more or less) that have say 4 inputs.  Any combinatorial 4 input circuit with a single output can be described using a 4 input LUT.  The FPGA will map your design to physical hardware available in the FPGA.  Finally, you can run an RTL simulation, which implies running your test bench on a selected chip, with selected speed specification.  At that point, you simulation won't work with your 1THz signal, because your FPGA is very unlikely to be able handle to handle that...

Beyond using unrealistic signals, your process or hardware will have limited resources.  Again, on an FPGA, your tool will usually try to map adders to physical hardwired adders on your FPGA. If you try to implement more adders that those available, the tool should implement remaining adders using digital fabric (LUTs or whatever ressources it sees fit to use).  Those remaining adders will probably be less efficient/fast than the hardwired ones.  So the performance and maximum delay, clock skew, etc are bound to actual hardware you implement on.

You say that you use Cadence.  Fine, but your simulator must use a model to simulate your gates.  It will be either a logical (ideal) model or a physical one.  If it is a logic one, there are probably no propagation delays or a default one which might no fit the physical implementation you would get in real life.  If it uses a physical model, then your simulation will reflect result you would get on that physical part, nothing else.

Consider standard discrete logic gates chips such as QUAD 2 input NANDs or chips of the like.  You have multiple possible families (RTC, DTL, TTL, ECL, PECL, etc.).  Each of those logic families have difference performance.  It could be the same conceptual circuit, but maximum speed, propagation delay, power consumption, etc. will be very different.

In summary, a physical propagation delay/speed simulation will be at most meaningless if you do not have models of the actual hardware you plan to implement your circuit on, whether it is discrete logic, FPGA, ASIC or whatever.  If your are only toying, then such an analysis is bound to whatever model you want to use.

Just in case you are wondering why I'm not directly answering your question from a theoretical point of view, it is because some hardware won't implement actual discrete logic gates, such as an FPGA (which might use logic gates or an hardwired adder), so a theoretical analysis won't give you the whole picture.