How a multiplier will be implemented with LUT?
A multiplier is basically a series of shifters, AND gates and adders.

Start with an accumulator of 0.


If bit 0 of the second operand is set, add the first operand, shifted left by 0.
If bit 1 of the second operand is set, add the first operand, shifted left by 1.
...


If you want a non-clocked design, you need to create lookup tables for all different shift counts, which is obviously fairly resource-intensive, even after optimizing the design by combining operations and flattening the hierarchy, so many FPGA fabrics contain fixed multiplier blocks.