In VHDL 2008, can a type from a package with generics be used for a port signal?
Credit for the answer goes to user8352 who provided the solution and some background. The vp_4 package is found in the work library and the following will work:

package vp_4 is new work.vector_package generic map (size =&gt; 4);

entity bar is
    port (
        signal vector : out work.vp_4.vector_t);
end entity;