pseudo nmos inverter
Let's call the threshold voltage of the NMOS VTN and the threshold voltage of the PMOS VTP.


Input voltage &lt; VTN. The NMOS is off.  The PMOS is in linear reagion, no current, Vds of the PMOS is zero. Vds of the NMOS is Vdd.
Small input voltage, slightly larger than VTN.  The NMOS is in saturation and the PMOS is in the linear region. The PMOS acts as a resistor. The voltage drop across the PMOS is the  drain current set by the NMOS times the  Ron of the PMOS. Basically you see the upside down version of the square law behavior of the NMOS in the diagram.
Larger input voltage. The PMOS saturates as soon as the output voltage is smaller than |VTP|. The NMOS will leave saturation when Vout &lt; Vin - VTN. It depends on the geometry and the parameters which case occurs first, but at some point the NMOS will leave saturation and the curve will flatten out.