Odd PCB Layout for Voltage Regulator
I would have done the same design, in order to reduce dynamic and static load regulation error.

The details for the reasons are evident in the datasheet.


look at dynamic load regulation error and input step regulation error.
I can only guess what error budget the designer had in mind, but it common for every LDO to have the above responses , although this FET LDO is exceptional low power and dropout voltage.


5mV error {input step=0.6V} with 1mA step load, 200mV error with 150mA step load*
the static load regulation error is only rated above 1mA as 0.007%/mA . This implies it is worse below 1 mA and improves with a dummy load of 7.6mA to the designers satisfaction.  It also improves dynamic step load regulation error above.*



This 1mA ensures the rise fall time of Gate drive to speed up response. 7.6mA is even better with diminishing returns above this.


static load regulation error is only due to RdsOn of the PFET used in the LDO divided by its internal Loop gain. This true for any voltage regulator whether it is FET or BJT. But infinite loop gain can increase stability errors or more ringing, under certain load , (ESR, C ) conditions so it is finite.


Fishy? No way