Prerequisites for Power Integrity Analysis
What you need to get is the s-parameter measurements of the capacitors. Some manufacturers are better than others. Murata, for example, have a really detailed online tool. It's a good idea to think about this before choosing components. 

The current draw is a big problem. Manufacturers very rarely, read almost never, provide the shape of the drawn current pulses. This is because it all depends on the application. However, you can have some assumptions. The worst case scenario is a Dirac pulse, which has a flat frequency domain representation. You can relax that to say a 10th of the clock period.

After you have that there are generally two steps to PI analysis. You simulate the impedance of the power network at each IC. This will show you whether you need to place more decoupling capacitors to lower the impedance at specific frequencies. You can also check the resonant frequencies of the planes. After that, you need to put your current draw model on the ICs, and do a frequency sweep. Now, you will be able to see what the noise is etc. 

In the majority of cases I have worked on, the impedance analysis, which requires only the capacitor data, is all you need. You can do the more detailed analysis, if you want to minimize the capacitance or are worried about current loops crossing each other. Generally, you can assume that current is drawn in Dirac pulses, and design the impedance budget for that. It works surprisingly well even for Gbps applications.