Transistors in a logic gate
A gate uses as many transistors as needed or as can be used with the accompanying voltage level. A 1000 input AND or OR gate would be untenable in most modern CMOS processes of the last... ever. A great way of understanding the number of mosfets (and thus inputs) is to understand how much voltage it takes to turn on and off a MOSFET and how many are "vertically" in between the power rails and the output. 

Picture example:







simulate this circuit &ndash; Schematic created using CircuitLab
This is a 4 input NOR gate. Short, sweet, and technically correct in all ways other than the M numbering system. See how there are 5 transistors between VDD and ground? Your VDD must be high enough to place those 4 pmos into saturation. That's your limit. Oh, you also get to combine that with the gate-source break-down voltage limit. Which means for any given process there is, in fact, a maximum number of inputs to a logic gate (not to be confused with inputs to mosfet gates, which is generally one).

Now if you wanted to calculate all this, you'd need to know a lot of device physics. My example with NOR doesn't suffer from back-gate effects like the other logic gates do. Then there's current limitations and it just gets messy enough to be hard for people. Computers are your friend in this case.