Cause of systematic offset in operational amplifiers
I think you should make a distinction between what I would call "balance" and "offset".

In my view your circuit actually doesn't have any Offset! All transistors are all perfectly matched and identical, or exactly 10 times wider if W is 10 times larger for example.

Offset is a statistical effect that is the result of small variations between transistors (and other components). You usually simulate this using a Monte Carlo simulation and for that also statistical models are required.

Balance is the result of the circuit, for example making sure that the input differential pair transistors (M1 and M2) are identical in size and have a identical operating points meaning the same \$I_D\$ but also the voltage must be the same. If that is the case (and it looks like it is in your circuit, at least in the input stage), your circuit is balanced.

The 2nd and 3rd stages in your opamp both add a very large amount of gain (I would never do that, chances are this opamp will be unstable when feedback is added) because these stages are all "current into a high impedance point" amplifiers. So even the smallest imbalance is amplified a lot. Even small numerical rounding off of the simulator could show up this way. My guess is that the 116 uV you see is caused by this.

I would just ignore that 116 uV and consider it to be zero. Also I would suggest to limit the number of "current into a high impedance point" amplifier stages you have now as these WILL get you into trouble. That's my 25 years of design experience tip :-)