Xilinx IP for delaying data
Just write one. It's only a few lines of VHDL. Depth can be a generic natural, and it can take its width from the ports. Synth it independently and check that ISE/Vivado use the expected shift register mode in LUTs. 

If you can't easily wrap it as a block, that calls the usefulness of the whole block diagram approach into question. Most of these things go right back to Mentor Graphics "Renoir" tool, in which wrapping VHDL as a block was easy.