Tricky problem regarding CMOS
The important part of the question is the wording that you have "A [single] gate" with "a [single] pullup network...of PMOS" and "a [single] pulldown network...of NMOS". That greatly restricts the kinds of gates that you need to consider. For example, you can't make an XOR gate fit this definition.

So, think about what kinds of individual gates can be built in this style what the output would be for \$f(1,1,1)\$.