JESD78D - pin clamping voltage and current
CMOS circuit latchup (for example) is explained here. The purpose of the JEDEC document specified is to test a particular device to see if it is vulnerable to latchup. It does this by (in simple words) testing at 1.5 x the supply voltage on inputs and outputs. This is the pin clamping voltage.

Voltage latch-up testing forces a voltage onto pins to see if CMOS latchup takes place. This can also be tested by injecting a current so "current clamp" is an alternative test using a current injection limited to the value in the document.

Hope this makes sense.