Designing a RAM, using 4x2 chips, with a 8 address capacity
You need two banks of four chips. The four chips in each bank simply have their A0, A1, CS, R/W signals connected and their D0/D1 connected to D0/D1, D2/D3, D4/D5, D6/D7.

The CS signal of each bank has to be calculated by a logic using the external CS and the external A2 signal. Two AND gates and one inverter.

These are all pointers you need.