Loop for two binary values in VHDL
Here is the working version. I'm using 100kHz clock.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;


entity moove is 
port (clk : in std_logic;
        rst : in std_logic;
        count : out unsigned (7 downto 0));
end entity;

architecture moving of moove is
    signal Cnt: std_logic_vector(11 downto 0);
begin
forwrd: process (clk)
    begin
    if Rst = '1' then 
        Cnt &lt;= (others =&gt; '0');
            elsif (rising_edge(Clk))then
            Cnt &lt;= Cnt +1;  
            if (Cnt = "011111010000") then--20ms(2000 clock cycles)
            count &lt;= "10010110";--1.5ms
            elsif (Cnt = "111110100001") then
            Cnt &lt;= "000000000000";
            count &lt;= "01100100";--1ms

end if;
end if;
end process;
end architecture;