Design an AND gate using 2:1 multiplexor
Let's start with the truth table for a 2x1 mux:

sel in0 in1 out
0   0   0   0
0   0   1   0
0   1   0   1
0   1   1   1
1   0   0   0
1   0   1   1
1   1   0   0
1   1   1   1


In the circuit shown, in0 is hardwired to 0, so we don't care about any rows in the truth table where it's 1. Let's delete them:

sel in0 in1 out
0   0   0   0
0   0   1   0
1   0   0   0
1   0   1   1


Now we don't need the in0 column so it can be deleted. Also, rename sel and in1 to the inputs we've wired to them:

B   A   out
0   0   0
0   1   0
1   0   0
1   1   1


...which is just the truth table for an AND gate.