Stm32f discovery internal clock
OK I figured it out. There is a mistake in the STM32F4xx_spi.c Peripheral Driver file
that doesn't allow the use of the HSI(internal clock) value needed for calculating the appropriate divider and odd values for the I2SPR register. (see the last line)
I changed it to:

  i2sclk = (uint32_t)(((HSI_VALUE / pllm) * plln) / pllr);


and now it works. Hours wasted as usual!!
The clock configuration tool is also wrong as it creates a message in the system_stm32F4xx.c file that states 

*        To achieve the following I2S config:   |
*         - Master clock output (MCKO): ON      |
*         - Frame wide                : 16bit   |
*         - Audio sampling freq (KHz) : 48      |
*         - Error %                   : 0.0186  |
*         - Prescaler Odd factor (ODD): 0       |
*         - Linear prescaler (DIV)    : 2       |


which conflicts with the programmers reference that ODD=1 and DIV=3 for 48kHz sample rate, which is correct.

/* Get the PLLI2SN value */
plln = (uint32_t)(((RCC-&gt;PLLI2SCFGR &amp; RCC_PLLI2SCFGR_PLLI2SN) &gt;&gt; 6) &amp; \
                  (RCC_PLLI2SCFGR_PLLI2SN &gt;&gt; 6));

/* Get the PLLI2SR value */
pllr = (uint32_t)(((RCC-&gt;PLLI2SCFGR &amp; RCC_PLLI2SCFGR_PLLI2SR) &gt;&gt; 28) &amp; \
                  (RCC_PLLI2SCFGR_PLLI2SR &gt;&gt; 28));

/* Get the PLLM value */
pllm = (uint32_t)(RCC-&gt;PLLCFGR &amp; RCC_PLLCFGR_PLLM);      

/* Get the I2S source clock value */
i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);