Are FPGA's as powerful as the number of gates they have?
You're basically asking two questions:

-- "Are FPGAs as powerful as the number of gates they have?"

I'd actually say that the answer is "no". The size tells you how "big" they are, but not how "powerful" they are, because:


"powerful" is very subjective to your end application.
"powerful" is typically more associated with the technology node than the die's size (a small device from current generation can be the same size as one from an older generation -- are they equally "powerful"?)


-- Paraphrasing: "Can I divide the number of required "gates" by the number of total "gates" and get the number of cores I could fit in the device?"

The answer to this is also "no". This is because FPGAs are routing limited, which means that:


Even though there may be enough logic resources on the chip, the software won't be able to route that many cores, particularly if there's connectivity overhead.
The design, overall, is likely not to meet the timing performance of the individual core.


Another problem is how to handle off-chip I/O -- will there be enough bandwidth and number of I/O to supply/read data from that amount of cores?

(BTW, we're trying to start an SE site dedicated to FPGAs... consider supporting it... http://area51.stackexchange.com/proposals/20632/programmable-logic-and-fpga-design?referrer=YmxhQ2OJUo-FAaI1gMp5oQ2)