Range of MIPS j instruction
Addressing in most CPU cores I know works on a per-byte basis. You don't address individual bits.

The MIPS requires it's instructions to be 4-byte (word) aligned - i.e. the two LSBs are always zero. That way, they're not encoded in the instructions.

@sherrelbc's answer explains it quite thoroughly, although I like the semantics of "word-aligned" more, than "word-addressed".

The link @valcroft gave also has the answer mid-page:


  Pseudo-Direct Addressing
  
  Direct addressing means specifying a complete 32 bit address in the instruction itself. However, since MIPS instructions are 32 bits, we can't do that. In theory, you only need 30 bits to specify the address of an instruction in memory. However, MIPS uses 6 bits for the opcode, so there's still not enough bits to do true direct addressing.
  Instead, we can do pseudo-direct addressing. This occurs in j instructions.


| Opcode  |              Target              |
|---------|----------------------------------|
|  B31-26 |               B25-0              |
| oooo oo | tt tttt tttt tttt tttt tttt tttt |



  26 bits are used for the target. This is how the address for pseudo-direct addressing is computed.


PC &lt;- PC31-28::IR25-0::00


  Take the top 4 bits of the PC, concatenate that with the 26 bits that make up the target, and concatenate that with 00. This produces a 32 bit address. This is the new address of the PC.


So, 26 bits left shifted by two gives a relative address boundary of \$2^{28}.\$

\$2^{28} bytes\$ is \$256 MiB\$, or \$256*1024^2\$.