How would I design a clocked D latch from first principals
In the world of sequential circuits, there are asynchronous state machines and synchronous state machines. A D flip-flop is an example of the former, and it is used to construct the latter.

The design of asynchronous state machines (combinatorial logic with feedback) is much more challenging than synchronous state machines. You need to account for all possible "race conditions" in order to make sure that you always end up in the correct state.

I'm not going to teach you how to design ASMs in general. That topic could fill a whole book, and there are many references available online.