How can the FPGA design induce a system wide reset?
For Xilinx devices at least, the answers to your questions are all in Xilinx UG470 and UG953.
https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug953-vivado-7series-libraries.pdf

FPGAs have a reset signal that is spread across through the global
routing.

That's correct.

If the user logic needs to carry out a system reset for whatever
reason, how should this be done?

It depends on what FPGA architecture you are using.  For Xilinx parts pulsing the PROGRAM_B signal causes the part to reconfigure.

You could physically put an AND gate on the board and tie one input to an external reset, and tie the other input to a GPIO pin.  The GPIO pin needs a pullup resistor on it.

You can use the IPROG command on the ICAPE2 primitive as documented in  UG470 Table 5-19.



Can the user logic actually drive the reset signal from itself which
is ANDed with the reset coming from outside the FPGA?

Yes, using the IPROG command.  Or alternatively if you just want to reset the flip-flops without reloading the bitstream you can use the GSR pin on the STARTUPE2 primitive.

If so, what will happen with the routing resource usage?

Nothing.  There is a dedicated global reset line in the FPGA, so additional routes are not needed.

Is there another way e.g induce the FPGA to reconfigure itself somehow
like it does just after power-up?

Pulsing PROGRAM_B (by whatever method) causes a complete reconfiguration of the device.