Logic level MOSFET gate trace length
If you expect noise interfering with the gate signal, next to @RohatKılıç comment to configure the pin as push/pull, make sure the gate resistor is closest to the mosfet.

Compare circuit A and B below(1).
On both cicuits noise is acting as represented by red arrows.
In circuit A, (assuming push/pull configuration) noise can hardly alter the gate signal because the uP pin is low impedant. Moreover, the noise will be attenuated by R1 and the gate capacitance.
In circuit B, R1 is cancelling the benefit of the low impedant pin of the uP.







simulate this circuit &ndash; Schematic created using CircuitLab



(1) Although from a schematic view exactly identical, an attempt is made to show the physical location of the gate resistor.