Clock Domain Crossing
A chain of flip-flops does not 'cure' metastability. However, by delaying the final decision, it gives more time for the metastability to resolve itself, so reduces its likelihood. As the likelihood of it persisting falls exponentially as time passes, you do not have to add many stages for a circuit to improve enough to be usable. 

To put some numbers on it. Let's say a flip flop has a metstability resolution time constant of 1nS, is operating at a 100MHz clock, and fails once per hour, needing a system reboot to recover from the resulting crash. If we add a second stage, then it improves things by 10 time constants, e^10, that is 22000, so now fails once in 2.5 years, a huge improvement, maybe good enough for some products. Add another stage and it fails once in 55000 years, probably good enough for one system to be called perfect. However, if you had deployed 10M systems to customers, then there would still still be 2 failures in the field per year. You do the sums for what improvement adding another stage would result in.

If a flip-flop goes metastable, it means it doesn't matter whether the output is 0 or 1, there is no 'correct' result, as long as two other circuits using the output data agree what it is. For instance, let's synchronise an external interrupt line to the program counter logic. Did an interrupt occur this clock cycle? If yes, provide the next program address from the interrupt vector. If no, provide it from the program counter. If the IV thinks there was no interrupt, and the PC thinks there was, then the system could crash. 

See other answers 1 2 3 so I don't have to type too much more .