VHDL signal assignement
In the first case you are simply declaring a type. You would have to then instantiate a signal of that type like so:

type word is STD_logic_vector(15 downto 0);
signal word_signal : word;


My preference is to append _type to type names, so your type would be WORD_type, and your signal declaration could then be:

signal word : WORD_type;


Your second case is a plain std_logic_vector. Using your own type instead of a predefined one might make your code more readable and/or provide more compile time checks on signal assignments, etc. It also means that if the length of your 'word' changes, you might only have to change the original type definition, instead of having to go round everywhere changing 15 downto 0 into 31 downto 0, or whatever the new size might be.

You can allow automatic conversion between your type, and the base type, by making your type a subtype:

subtype WORD_type is std_logic_vector(15 downto 0);


This allows you to do the following:

signal word : WORD_type;
signal another_signal : std_logic_vector (15 downto 0);


...

another_signal &lt;= word;