In digital logic, when given a requirement of a 64 byte FIFO, is it possible to calculate the width and depth?
I think your confusion comes from the fact that the code you posted is referring to an "address", while normally when you utilize a FIFO, there is no concept of an "address". As a normal user, you just "push" data onto the FIFO and "pop" data off of the FIFO. This makes the application of a FIFO easy to comprehend. You still need to understand and consider the concept of the FIFO's data width, and the FIFO's depth.

If you are designing a FIFO, then you need to realize that a FIFO is just a RAM block with some logic that controls the read/write address automatically (and internally). Since RAM blocks do have address lines, we at least need to consider them. This is easy: The depth will be 2^(numAddrBits). Or alternatively, the number of Address bits must be, at minimum, ceil(log2(depth)).

This picture may help you visualize:



The fundamental task of designing a FIFO is to determine how many bits you really need to store. In your example, this was 64 bytes, or 512 bits. The next thing you should do is decide how you want these bits organized. For example, You could choose for your FIFO to have 8-bit word length, and a 64 word depth, meaning your RAM would need ceil(log2(64)) = 6 address bits.

For your example, the determination was already made: Word length = 4 bytes.