SPI terminology confusion for project
Your question is about a board with a TI Sitara processor.

These often let you assigned the D0 and D1 to MISO vs MOSI roles under software control for example in device tree bindings.

Here's a post over on stackoverflow about doing so on a beaglebone:
https://stackoverflow.com/questions/25393225/beaglebone-black-spi0-swap-d0-and-d1

The information there would seem to suggest that the default for master mode is probably D1 MOSI and D0 MISO.  But that could be wrong...

Realistically your best is to write a software test that attempts to do a write operation on the SPI, send something with a lot of toggles like 0x5a, and then look with a scope to see which pin is actually toggling.  Do this before you commit to the result, fortunately it looks like you're probably making a connector-base connection to an existing board, not designing a board, or at least not the one with the processor on it.  So you have the opportunity to prove things first.