What kind of VHDL process is this?
Incomplete answer.
First note this is a block, not a process. A block wraps some declarations and concurrent statements (which can include processes) together, without exposing those details to the wider design.
But the problem here is not the block; it's that these Asserts are written in PSL, Property Specification Language, which is used to extend VHDL's formal verification capabilities. I'll let the linked Wiki article describe PSL in more details. I have rarely come across it myself...
See also &quot;Property (PSL)&quot; in the VHDL-2008 LRM index or or search for PSL in the entire LRM.
Most VHDL simulators allow PSL embedded in VHDL code, as here; (including the open source ghdl, as far as I understand).
And the Aldec website hints at PSL support in Active-HDL (though without opening an account there, I can't look any more closely than that. This is the incomplete aspect!).
So my guess is that your best way forward is to read the Aldec docs and find out why PSL support isn't enabled (sim version? missing compile option?) and enable it. And add to the question (or answer it yourself) with your findings.
If PSL assertions were trivial to re-write in VHDL, PSL support wouldn't be available, so rewriting these as VHDL is probably not optimal...
If you can't enable PSL, or move to a simulator that understands it, you need some way forward...
In that case I'd suggest adding a boolean constant (or generic) use_psl, and surround this block with label: if use_psl generate ... end generate. That'll let you move forward, and the design will work equally well, but obviously you lose the verification provided by this block.
Finally it's probably worth reporting this to the Vunit team via their github site : their support is excellent and they may well have answers I have overlooked.