Gate array propagation delay times
Propogation delay in a CMOS system is \$\approx g_m/C\$


\$g_m\$ is the transconductance and has units of \$1/\Omega\$
So \$g_m/C \approx 1/R_{eq}\cdot C \$    which has units of seconds


And actively biased transistor will have a \$g_m = u C_{ox} V_{eff} \frac{W}{L} \$


\$u\$ = mobility in units of \$m^2/V\cdot S\$
\$C_{ox}\$ is the oxide gate capacitance in units of \$F/m^2\$
\$W\$ and \$L\$ are dimensions of the transistor
\$V_{eff}\$ is the overdrive voltage - (\$V_{gs}-V_{th}\$)


As power supply lowers:


\$V_{gs}\$ lowers
\$g_m\$ lowers
propagation delay lengthens


Once \$V_{gs}\$ gets close to the \$V_{th}\$ then the the transistor starts to operate in the triode region and slows down even more (lower \$I_d\$ -> even lower \$g_m\$).