VHDL Finite State Machine Pattern Checker
There are several issues with your code.  My rewritten version is below.

The main problem is that your code was that the assignment of Z was incorrect.  The next problem was that the state machine itself was incorrect.  As it was written, Z should have gone high after a pattern of "11", and not "110".  It also would have gotten stuck in state S2 and not recovered.

I should also mention that there were several "stylistic" issues with your code too.  Having two processes instead of one was a major one.  I cleaned up that as well.  This allowed for having only a single state signal, which makes the whole thing more readable as well.

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

 entity checker is
   Port ( clk : in  STD_LOGIC;
            x : in  STD_LOGIC;
            z : out STD_LOGIC);
 end checker;    

 architecture Behavioral of checker is    
   type state_type is (S0, S1, S2);
   signal state: state_type := S0;
 begin

     process(clk)
     begin
       if rising_edge(clk) then
         case state is 
             when S0 =&gt; 
                z &lt;= '0';
                if x='1' then 
                  state &lt;= S1;
                else 
                  state &lt;= S0;
                end if;

             when S1 =&gt; 
                z &lt;= '0';
                if x = '1' then 
                  state &lt;= S2;
                else 
                  state &lt;= S1;  -- S1, not S0 because we also want to detect a "111...1110" 
                end if;

             when S2 =&gt; 
                if x = '0' then
                  state &lt;= S0;
                  z &lt;= '1';  -- Z='1' only when a match is made
                else
                  state &lt;= S0;  -- Goes back to S0 to detect the next pattern
                  z &lt;= '0';
                end if;

             when others =&gt; 
                z &lt;= '0';
                state &lt;= S0;  -- In case the state machine is in an invalid state 
         end case;
       end if;    
     end process;

   end Behavioral;


Update:  Here's a rewritten testbench:

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture arch_testbench of testbench is
  component checker
    port (clk   :in  std_logic;
          x     :in  std_logic;
          z     :out std_logic);
  end component;

  signal clk    :std_logic := '1';
  signal x      :std_logic := '0';
  signal z      :std_logic := '0';

  signal sr     :std_logic_vector (15 downto 0) := "0001100011111110";
begin

  process (clk)
  begin
    if clk='1' then
      clk &lt;= '0' after 5.0 ns, '1' after 10 ns;
    end if;
  end process;


  process (clk)
  begin
    if rising_edge(clk) then
      sr &lt;= sr(sr'high-1 downto 0) &amp; "0";
    end if;
  end process;

  x &lt;= sr(sr'high);

  UUT:  checker
      port map (clk, x, z);

end arch_testbench;