Output frequency of asynchronous and synchronous counter
If you have a binary counter, modulo M = 2^N, where N is the number of flip-flops, then the frequency of the most significant bit (I assume this is what you're referring to with "output frequency") will be f/M = f/(2^N), where f is the input frequency. This regardless if the counter is synchronous or asynchronous. (Yes, in a synchronous counter, the clock is fed to all the flip-flops, but there is some combinational logic which, taken the outputs of the current state, will determine the inputs of the next state, to actually have the counter to ... count).
The duty cycle will be 50%.

If your counter is modulo M, with M &lt; 2^N (think of a decade counter such as 74LS90), then the frequency of the MSB will be f/M, but:


The frequency of the MSB is no more f/(2^N), despite there are N flip flops.
The duty cycle may not be 50%.