ASIC Verfication Do I need to verify all possible combinations?
OK, black box is not a problem, as long as you know the functionality. You'll need something like 64 logical functions in (maximum) 2400 variables.  

Worst case you have an untestable product. That's for instance if each of the 64 outputs indeed depends on all input states. I imagine values of different ports are compared for equality, or greater than, and those results are used in a logical combination. In that case you could test for values around the comparison value, which can dramatically decrease the number of combinations.  

Say output Y should be high if port A > port B. You could apply the value 0x25 to port B, and check what the output is for values 0x24, 0x25 and 0x26 of port A. Repeat for 0x211 and 0xE5A (I'm just making up numbers). Then you have reduced 2\$^{24}\$ = 16 777 216 combinations to 9.  

You may have a problem here. Even if that's indeed the comparison you need to make, the result may be internal, and only come out after some logic function with similar internal results. That's how you make an untestable product.  

I would have split up the design into several ASICs, where intermediate results go from one ASIC to the next. This way you might only have to test \$O(\sqrt{N})\$ combinations, instead of \$O(N)\$. 1000 billion tests may be impossible, but 1 million is not that large a number. It may also decrease I/O number if there are mutually independent functions.  

A solution for the single chip might be to have test pads for intermediate results on the die, so that they can be tested on the wafer with flying probe testing.