How do I implement a tri-state buffer for a vector in VHDL?
If you need enable control for each bit, then the easiest way is to use a generate statement:

tristate : for i in 0 to N generate
begin
    Y(i) &lt;= A(i) when EN(i) = '1' else 'Z';
end generate tristate;


Generate statements with for constraints create multiple circuits which operate in parallel, unlike a for loop in programming where the same code is executed multiple times in series.