Finding the broken cicuit in an Xor Gate
Let's label some nodes in the circuit to make more sense of things:







simulate this circuit &ndash; Schematic created using CircuitLab

How It's Supposed to Work

\$A\$ and \$B\$ are the logic inputs, and should be logic HIGH when the switch is closed and LOW otherwise. \$C\$ will go high when either \$A\$ or \$B\$ are high, i.e. a basic OR gate:

$$C=A+B$$

\$D\$ will go LOW when both \$A\$ and \$B\$ are high, i.e. a basic NAND gate:

$$D=\overline{AB}$$

And \$OUT\$ will only go HIGH when both \$C\$ and \$D\$ are high:

$$OUT=CD$$

$$OUT=(A+B)\cdot \overline{AB} = A \oplus B$$

Here is a CircuitJS model that allows you play around with this circuit.

There are a few spots in this circuit that make it unsuitable for real-world use. It's probably okay for a hobbyist / learning project, but there are a few things that could confuse people and cause unpredictable behavior.

Gripes / Concerns with This Circuit

Gripe #1 - The Inputs Are Not Reliably Driven to Logic Levels

In the schematic we can see that when SW1 is open then node "A" is essentially left floating, along with the base inputs of Q1 and Q3. The voltage at this noce will be set by whatever leakages are present in the circuit. Similarly, when SW2 is open then node "B" is essentially left floating, along with the base inputs of Q2 and Q4. This can result in some unpredictable behavior that can vary from one transistor to the next and is probably highly sensitive to circuit parasitic effects. (Particularly true on a solderless breadboard.) For robust repeatable operation the transistor inputs should always have a reliable connection to logic HIGH or logic LOW.

One way to test this is to just touch this node with your fingers. If the circuit "responds" to your touch (your fingers ought to be a pretty poor conductor of electricity) then the circuit is way too sensitive to outside influences.

The easiest remedy is to add two resistors to the circuit, one from node A to ground and one from node B to ground. A resistor value of 10kΩ ought to work just fine for this purpose. This way node A and node B are never "floating", they are always connected to a reasonably low resistance. This ought to remedy any issues you were seeing in your circuit before.

Gripe #2 - Output Doesn't Drive to a Proper Logic Low

When node C is at a logic LOW then transistor Q5 is OFF and node Q6C is essentially left floating. The concept is that Q6 can never turn "on" because it's not getting any supply to its collector. But in practice, if node D is at a logic HIGH then there is still current flowing through the base-emitter junction of Q6. You can see this in the CircuitJS example above. The only reason the LED doesn't turn on is only because there is "not too much current" flowing out of Q6. (Or perhaps a better way to look at it is that the voltage at OUT is the voltage from VCC after an 11kΩ/1kΩ resistor divider.)

This second gripe is probably more forgivable, but in a "real" digital logic circuit it is better practice to have your HIGH voltages be driven all-the-way high and your low voltages being driven all-the-way low. In this circuit, when both SW1 and SW2 are open, the node OUT is at 0.37V which is being considered "close enough" to a logic LOW.