How to determine timing delay of SR-Latches?
Let's follow what happens when the SET input (1) is taken high:


SET input (2) goes high.
1.4 ns later Q' (3) goes high.
This turns off the input to the lower NOR gate at (4).
1.4 ns later Q (5) turns on.


For the SET operation Q' reacts with one gate delay. Q reacts with a further gate delay.

For the RESET operation Q reacts with one gate delay. Q' reacts with a further gate delay.

If you understand this you should be able to figure out the rest.