Issues on using VHDL module in verilog
If integer does not match integer this looks like a tool issue with ISE rather than a problem with your design. 

First I would eliminate the latter by verifying it in simulation : either ISIM (with some restrictions) or Modelsim should handle mixed designs.  

Having confirmed the design, you need a workaround for the tools issue. 

If you change the chosen FPGA to something like Spartan-3, ISE defaults to an older VHDL parser which handles some VHDL constructs better, with an "advanced" option touse the new parser instead. Try both... Of course if you need a newer FPGA this won't solve your problem but it may point closer to the problem ... see below.

Alternatively, Xilinx now offers a third VHDL parser in the form of Vivado - maybe this will solve the problem.

(If the problem actually lies on the Verilog side I'm afraid I can't help, if it was my job I'd re-write that little Verilog module in VHDL and be done with it).

If none of the above helps, then you will have to go against my usual advice and actually use std_logic_vector for the port, and whatever the Verilog equivalent is, and the appropriate type conversions to/from integer via (signed or unsigned) on either side.