Digital downcounter not resetting
The problem is a glitch on the outputs when the counter tries to go from 8 to 7. There is an intermediate glitch state of 1111 when the 3 left flipflops' Q outputs have all changed state to 1 but the right hand flipflop's Q output has not quite changed state, it is still at 1. The And gate decodes this all 1's glitch (all zeros on the ~Q outputs) and resets the flipflops to 9.
Solution
Add an extra stage to the counter as shown below. Then when the lower 4 bits transition from 8 to 7, the extra most significant bit will be zero and the And gate will not generate a glitch pulse. Of course you'll generate the same problem if you try to reset the counter to a value greater than 15 because the And gate will produce a glitch output when the counter tries to step from 16 to 15.