Which input of NAND is preferred and why?
I would place input A closer to the output. If input B switches first then the bottom NMOS transistor has time to bring the source capacitance of the top NMOS transistor fully to ground before input A goes high.

If input A goes high but the source terminal of its NMOS transistor is not at ground then the effective \$V_{GS}\$ for that transistor is reduced by the existing voltage at the source, thus reducing \$I_{DS}\$.