Inner layer routing of LVDS traces in between ground vias
You may be trashing the ADC's VDD lines or REF lines, or trashing the sampling clock (causes jitter, ruining the noise floor). 

Assuming 1mm by 100micron coupling area (parallel-plate model) with 100micron spacing, and ER=5, the capacitance is C = E0*Er*Area/Distance. The 100micron / 100micron cancels, thus C is 1e-11F/meter * 5 * 1mm = 50 femtoFarads.
With 1nanosecond edge to the LVDS, and 0.2v swing, or 0.2v/nS, the induced current is (I = C*dV/dT) = 50e-15F * 0.2v/1e-9s = 50 * 0.2 * e-15 e+9
or current is 10*e-15+9 = 10e-6 =10uA with rise time of ?? 100 picoseconds?
Into bypass caps with 1nH inductance, the upset voltage is V=L*dI/dT or
V_cap_upset = 1nH * (10 * 1e-6)/100pS == 1e-9 * 1e-5/1e-10 = 1e-14 * 1e+10
V_cap_upset = 100 microVolts.
Can you live with that, occurring on EVERY BITTIME of the LVDS?