My counter for my cpu stack alternates between counting up and down
Are you violating setup or hold timing constraints on the Up/Down input?

If U/D is changing at the same time as clk, you can't be sure if the old or the new value of U/D is seen - it is even possible that part of the counter sees Up and the rest sees Down. As you can imagine, the counter won't work reliably if that happens.

You need to setup U/D some finite time BEFORE the clock edge and hold it at that same level for some finite time AFTER, to guarantee seeing the right level when the clock actually happens.. Failing to do these is called "setup and hold violations".

What the correct setup and hold times are, I can't tell you. For old fashioned TTL logic there was a fat book with a bright orange cover called "The TTL Databook", with about a thousand pages of setup and hold timings and other data for every logic IC that Texas made. 

You'll need to find out what the equivalent timing parameters are for this system, and keep U/D stable throughout this time window. You can change it at any other time.

In FPGAs, the timing analysis tools do a very good job of warning if you have accidentally violated one of these timings, but you still have to fix it yourself. There are a basic set of "synchronous design rules" that help avoid almost all of these problems : they all basically come down to "don't do that" (clock and other signals at the same time). 

In your system I have no idea how that all works; hopefully now you know you're looking for such a thing, it'll be easy to find.