Assistance with CMOS simulation
Unfortunately the MCH models given out by ON are not directly usable with LTspice (and I lack the patience/time to make them work tonight), so here's a substitute simulation with discrete, long-channel FETs, which still have pretty low thresholds:



The curve looks just as shitty/slow as yours. Also note the gigantic shoot-through current (hundreds of amps) that will blow the FETs off in real life.

Now look at a real CMOS gate done with short-channel FETs, which are only found in ICs (as far as I know):



The transition looks much sharper and the current while having the same shape is in micropampere range. The latter files are from http://ecee.colorado.edu/~ecen4827/spice.html The library included there is for some BSIM3.3 model.

So yeah, you got the schematic right, but not the process/FET details that make a workable CMOS gate. Also note in that 0.35um sim that the two FETs are not mere twins. They have different geometries in a CMOS inverter to get the midpoint right. To actually set the midpoint see p. 150  here. If you change the pmos there to W=3u (to "match" the nmos), the curve moves to the left and starts to look a bit like the discrete version (but the transition remains sharp).



Also textbook material:


  Transistor current drive in the saturated state for submicron technologies is not quadratic but linear. It is dominated by carrier velocity saturation
  (vmax),
  
  I = WCox(VDD – Vt)vmax


And given your not very clearly expressed expectations, you want to review how a CMOS inverter actually works:




  Region I. nMOS off, pMOS ohmic.
  
  Region II. nMOS saturated, pMOS ohmic.
  
  Region III. nMOS saturated, pMOS saturated.
  
  Region IV. nMOS ohmic, pMOS saturated.
  
  Region V. nMOS ohmic, pMOS off.


These quotes and figure are from Segura and Hawkins CMOS textbook.

Also, it's possible to make CMOS gates with long-channel FETs, but textbooks tend not to cover this much anymore... I think you'd still need different geometries for the two transistors.



For amusement purposes only: Here is (totally ridiculous) way to get something more symmetrical with discretes (since we can do nothing about the geometry): use two p-channel mosfets in parallel on the high side (this is basically a way to double the width)!



Of course this does nothing to fix the lazy curve. To actually fix that you nee to pick a an appropriate Vdd for these MOSFETs, which depends on their thresholds. Here's an experiment varying Vdd:



You can see that at much lower Vdd voltage (given their low thresholds) these MOSFETs start to look more promising. In a real CMOS design, this of course done backwards: the transistors are designed with a Vdd (range) in mind. 

And here we go, we'd made a 3v MOSFET gate (who needs Intel anymore?? :p). I would still not try this in practice, except with very disposable MOSFETs. We are exceeding the static current rating on those (which is 5A), but we're within the pulse current rating (30A). If the drive pulse is not fast enough though... bam.



Actually you can get something just as good with just one PMOS at this low voltage (the 6407 part is 5A while the 6408-part is 7A). Probably if you find some complementary pair that is closer it will look even better in terms of symmetry. I've just cut one of the pmos legs in the schematic below; that's on purpose.



If you limit Vdd to 2.5V, it would even look sensible even with respect to their static current limit (for these parts). I'm not gonna paste another graph here though. What I am going to add is a graph of a CD4000-series inverter, just so you see how much less power that uses (tens of milliamps at most). Goes to show that using power/trench mosfets to make a CMOS gate is still a very silly idea.



Alas TI doesn't give a FET model for those chips, but someone reverse-engineered (traced) them: http://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf