What does Computer-in-the-loop or CIL mean related to embedded systems
These are terms I have never used before because I was never in the 'merican military which use 3 and 4 letter abbreviations like crazy.  But basically you start with precise parameters and values for every source of error on every interface and then validate the design on those parameters.  

e.g. 


  Monte Carlo runsets using known CIL/HWIL interface errors, such as scale factor, bias and noise, are used to create minimum-maximum boundary value plots.


Although I have worked for and with many American Corporations, the common terms we used are: Design Specs; DVT plan, PVT plan, HALT, HASS and Tolerance Stackup.


DVT = Design Verification ( or Validation) Test plan (&amp; results) that verfies EVERY spec and in my case, test to failure or margin to failure. Uses every Design Spec.
PVT= Production or Process Verification Test  Uses DVT results to fine tune for production tolerance verification and ALL design Specs.
HALT= Highly Accelerated Life Testing ( like shock and vibe with Temp stress while running voltage margins on supply with crystal tolerance errors , then increase until failure occurs)
HASS = Highly Accelerated Stress Screening ( like above but not to stressed to failure mode) and used for quality screening and burnin. 
For complex process with many e.g. 10 variables such as pre-flux and wave-soldering, Taguchi Method is used.
For embedded code work, this means doing worst case input and output test vectors to ensure all faults are detected, reported or corrected. and every Function is validated.  Design Specs are a MUST for HIPO design specs. Heirarchical Input Process Output. ( an IBM acronym)  For complex IO processes, TAguchi Method can be used to reduce number of experiments to determine process sensitivity of each variable.