Sram circuit design recommendations
It means you route everything (all of the fast signals like address and data lines) on the top layer and for the signals you want running at 100MHz you run them as short as possible. If your trying to connect an SRAM off board, your probably not going to be able to do that without impedance control of the lines, and connectors. 

The pic below shows an FPGA with an SRAM with most of the traces routed on the top layer. If you don't do this, then when it doesn't work you have to go through each signal and measure the delay and make sure its within bounds of the datasheet. That doesn't sound like much fun, so I follow the guidelines and overdesign.