Little change in Verilog module results in high change in power consumption (Synopsys Design Compiler)
I have seen that some synthesizers are intelligent enough to optimize logic expressions.

If the source code for example contains:

(A or B) and (A or C)


... they will actually produce the following logic on the FPGA:

A or (B and C)


If your synthesizer did so it may happen that not only the /8 divider will "see" the 400 MHz signal.



A hypothetical example:

B might be a 400 MHz input signal and C might be another signal which behaves in a way that the expression B and C might result in a 50 MHz signal. The duty cycle of B and C would not be 50% in this case but the duty cycle is not that important for the power consumption of CMOS circuits.

If you have the following code (here pseudo-code, not Verilog):

Z = B and C
Y1 = X1 or Z
Y2 = X2 or Z
...
Y100 = X100 or Z


... you might think that only one logic cell receives a 400 MHz signal: The one that generates the signal Z.

However the optimizer might optimize the logic the following way:

Y1 = X1 or (B and C)
Y2 = X2 or (B and C)
...
Y100 = X100 or (B and C)


... which means that all logic cells are driven with 400 MHz.

For many FPGA types the power consumption of a cell mainly depends on the fastest input signal of that cell while the other input signals have less impact on the power consumption.

Please also note that some FPGAs have "global clock lines" which are inputs to all logic cells used (maybe even if the signal is unused). Feeding a high-frequency signal into such a line would be a bad idea.