*how* are things triggered on clock rise, fall, high or low,
Take a look at a diagram of the simplest type of edge-triggered flip-flop, the D Flip-Flop. It's basically an SR Latch with an extra inverter so that S and R are always complementary states, as well as a clock signal input.

What makes it edge-triggered is that when the clock signal is low, the state of the output will not change. It is only when the clock signal is high that the change in state propagates to the output. You can consider the clock input to be an "enable" input, since it functions like an SR-latch (albeit a kind with only one input) when the clock is high. 

If there is data waiting on the input while the clock signal is low, the state will only change once clock is brought high, and so we say that the change occurs at the transition from low to high, or the rising edge.