Why the start bit and the stop bit(s) are necessary?
The scenario that you seem to be talking about (with start and stop bits), is likely UART (of which RS232 is a type of). UART stands for Universal Asynchronous Receive Transmit, the key part of which is Asynchronous. There is no clock line, only data.

In this sort of system you have two devices (TX and RX) which don't necessarily share a common clock. Both systems might for example agree on 9600 Baud, but without a common clock, one might produce 9601 Baud while the other gets 9599 Baud. Clocks are not perfectly accurate, which means over time the two will drift out of alignment.

Additionally because the communication is asynchronous, it can start whenever the transmitter feels like it (ignoring flow control). The transmitter and receiver might will turn on at different times, and the receiver has no way of knowing when it starts to transmit.

The key requirement then is known as synchronisation. The protocol must include some way of the transmitter to signal to the receiver that it has just started transmitting. Additionally there must be some way to synchronise the clocks at both ends.

In the case of UART, this synchronisation is done in the form of a high to low transition on the data line. The line will idle high, then drop low when transmit starts. This transition acts to synchronise the timing between both devices. The receiver then knows to clock in enough cycles of data based on its baud clock. There are however two problems with this scheme:


The single high to low transition is not enough to synchronise timing over a long period of time. Remember the two devices will have slightly different internal clock rates. As long as those two clocks are within a certain % of each other, the transition will provide enough information to synchronise the devices for at most a few clock cycles. That means you need periodic resynchronisation.
If your line is idling high, and the first bit of data you want to send is also represented by a high level, then you don't have a transition. If your line is idling low and the first bit you want to send is low, you have the same problem. That means you need some way to distinguish the first bit.


Both of these problems are solved in the case of UART by using start and stop bits. The data that is being sent is split into packets of a few bits (e.g. 8 bit). Each packet is preceded by a start bit of "low" and followed by a stop bit of "high". That means that between every few bits there is a known high to low transition - the stop bit of the last packet and the start bit of the current packet. You can now resynchronise every packet.



This is by no means the only way of solving the problem. There are many other schemes - Manchester coding is one example. In that scheme a low to high transition signifies a logic 1 while a high to low transition signals a logic 0. That means that every bit you send encodes clock information within it meaning you can resynchronise every bit you send.

You could have other signalling methods such as using ternary - three voltage levels. For example you might use +5V for a 2, 0V for a 1, and -5V for a 0. You could send binary via this system using one of those states to signify idle. However in that example you have simply replaced a start and stop bit with a period of time at a third voltage. You won't change the need for periodic resynchronisation, so it doesn't really save you anything, and it just adds complication to the circuitry.