Verilog assign breaks the synthesis using Icestorm
In Verilog, assign can only be used with wire type variables. If you had declared it as output [7:0] detect or output wire [7:0] detect it would work fine (wire is implicitly inferred in the first declaration). This question is also relevant.
Also bear in mind that initialisation like you have done here is not guaranteed to be synthesisable in an FPGA, and certainly not in an ASIC. You should have a reset input, and use that to reset your detect_sig variable to 8'h00. Note also that you should give defined widths to your assignments, rather than bare 0 or 1; the tool may complain about truncated widths otherwise, and your intent is clearer.