H-bridge logic driver in Verilog
Without wanting to sound rude, there is a lot syntactically wrong with the code you have presented, and that is before getting down to the logic of what you are trying to do.

Basically I'd suggest finding a tutorial on Verilog and following that before you try your own designs. For example this is a good starting point to get the very basics.

HDLs are not something you can just jump in at the deep end with, as you basically need to forget anything you know about regular programming.