Input resistance of biased amplifiers
1.) First circuit: Assuming that the gate voltage divider is connected to a voltage source (zero internal source resistance) both resistors can be regarded to be ground referenced (signal ground). Hence, as seen from the gate node, both resistors are in parallel and connected to ground. Therefore, rin=RG1||RG2.

2.) Second circuit: The feedback resistor RG is connected between the input node (gate) and a node that is NOT connected to signal ground. Rather it is connected to the drain node. During normal operation, this node has a signal voltage that is phase shifted by 180 deg (in comparison to the input signal at the gate).
Thus, the voltage DIFFERENCE across this resistor is larger than the input signal voltage. As a conseqence, there is a larger signal current through RG. Thus, this resistor - as seen from the input - seems to be SMALLER than its value indicates.
The corresponding calculation involves the input signal voltage AND the amplified voltage at the gate (corrected: at the drain). Thus, signal gain comes into play.
The result is 
rin=RG/(1-G).
Note that G is the gain at the drain node (negative value due to phase inversion).

All calculation above are based on the assumption that the FET input resistance at the gate can be neglected. otherwise, it is in parallel to the given rin expressions.