design data storage using a simple MUX instead of a complicated SR latch
Assuming that your circuit works, and I'm not going to bother to find out, it isn't a fundamentally different circuit from an SR latch. You've removed the !Q output, so one of the feedback paths in the latch now looks like a feed-forward path. This seems intuitively true because you have shifted the OR gate to the right, so the path from the bottom AND gate to the OR gate doesn't look like a feedback path anymore.

In any event, the important characteristic is not the number of feedback paths but the number of gates. You replaced a nice 2-gate latch with four gates, so most people would say you've taken a step backwards. Worse, the natural gate style in CMOS is NOR and NAND rather than OR and AND so your solution might actually require additional inverters for a practical implementation.