Trying to understand the difference between a regular clocked flip flop and a falling edge triggered one
You can only make latches this way and bad ones too that oscillate with negative feedback.  Notice the blur of oscillations. when both JK =1.



True Flip Flops MUST HAVE  2 latches to make the output edge triggered so that the 2nd stage input conditions cannot change on the clock edge.

They are actually implemented in CMOS  Transmission gates as well.