Verilog Iterative Circuit
It's not iterating, it's just calculating the bits of gtb in parallel. The calculation of some bits of gtb depend on other bits of gtb.

We could rewrite the questioned line (making the substitution k=8 for simplicity) as

gtb[8] = ( eqi[7] &amp; gtb[7] ) | gti[7];
gtb[7] = ( eqi[6] &amp; gtb[6] ) | gti[6];
// ...
gtb[1] = ( eqi[0] &amp; gtb[0] ) | gti[0];
gtb[0] = 1'b0;


Notice that this structure does mean that a change in the low bits of a or b could affect all the higher significance bits of gtb. And that these changes will have to go through several gates to ripple up to the high-order bits of gtb. As such this structure will produce longer and longer path delays as the width (k) is increased.

You can see similar behavior in a ripple-carry adder