Discrepancy between RTL schematic and Behavioral simulation in Vivado
No tool errors as I see. Synthesis has generated exactly what you expect but simulation is dealing with the 2 flip flops differently in the 2 cases.
In the signal version the simulator recognises (and treats) the clocks as being the same event. 
In the variable version the simulator sees clock edges as being different events. Because your latch for FF0 appears first in your code, the simulator operates on FF0 first and updates the FF0 Q in response to that clock edge.
Now the simulator moves on to look at FF1, but the FF0 Q output (FF1 input) has already changed so the same clock edge now changes FF1 Q output in exactly the same simulation delta period. The AND gate output doesn't change because the 2 inputs are never different. 
You have created a situation where the simulation (legitimately) behaves differently to the design - not good. 
I never design with variables in RTL and in many places I have worked, are not allowed under company coding rules. They can always easily be avoided.