create sr_latch from gates in verilog
A signal should not exists on the left and right side of an assign statement. A latch should be assigned in it own always @* block (with SystemVerilog use always_latch) and use non-blocking assignments (&lt;=). 

When all possible inputs combinations are described in an always @* then the block describes combinational logic. If it is not fully described then a latch is inferred. Unintentionally latches are troublesome for all RTL designers. 

Non-blocking assignments (&lt;=) should be used for the same reason it should be used for edge-sensitive flip-flops (hint simulation race conditions). In addition it helps identify intentional latches; but most synthesizers don’t care. 

Note most FPGAs do not support level-sensitive latches or have limited support. 

Your sr_latch should look something like this (not tested or syntax checked). 

module sr_latch(input set, reset, enable, preset, clear, output reg out);
  always @* begin
    if (clear) out &lt;= 1'b0;
    else if (preset) out &lt;= 1'b1;
    else if (enable &amp;&amp; reset) out &lt;= 1'b0;
    else if (enable &amp;&amp; set) out &lt;= 1'b1;
    // inferred latch since not all possible conditions are defined
  end
endmodule