RC High Pass Filter output drift problem
When the first pulse arrives (after a period of inactivity), the capacitor does what it must do and it transfers that rising edge from one terminal to the other terminal. This is what you initially see in your 2nd diagram.

During the "on" period of that first pulse, the capacitor witnesses a short period of DC on one terminal and this causes the small decay on the output terminal. Then the falling edge of the first pulse happens and that change in voltage transfers across the capacitor. But now, the waveform has sunk below 0V and will progressively continue to sink below 0V on repeating falling edges.

So, it's all down to what happens once the rising edge has transferred and the input pulse top is flat - this is where things are happening that ultimately cause the output pulse train to have an average DC value of zero. 

If the capacitance value was infinite the output pulse train would look exactly like the input pulse train. Hopefully this diagram will help: -



The diagram's input square wave is centred around 0V so that the output is symmetrical (unlike your pulse train) but it's the decaying output when the pulse is constantly high or low that is important to consider.

As for recommendations I stand by my proposal in the question you raised here.