Understand the Primary/Secondary/Subordinate Bus number in PCI/PCIe Bridge
Sounds like you've pretty much got it figured out.


That's pretty much right.  The secondary bus number is the one that is directly downstream of the port, secondary bus number plus one through the subordinate bus number are then buses that exist below that port somewhere.  PCIe TLP routing logic would send any packets with bus numbers that fall into that range out of the port.  
That's a good way of thinking about it.  This only applies for TLPs that are routed by ID, TLPs that are routed by address use base and limit registers to accomplish the same thing.  The fields allow PCIe TLP routing logic to determine which port to send a received TLP out of.  
That's essentially correct, except software can only send configuration read and write TLPs by ID, so most communication after configuration completes will probably be done via memory-mapped IO (MMIO) in the form of memory or I/O read and write request TLPs, which are routed based on separate base and limit registers.