Modeling a Time to Digital Converter in Verilog-AMS
Quite embarrassingly, I left an [i] for the output within the generate block, which should be:

generate i (50 - 1, 0) begin
  V(TDC_therm_o[i]) &lt;+ transition(delay_reg[i],0 , 2p, 2p);
end


With that, the model works well.