Multi-layer layout and return currents of high-speed signals
What edge rates are we looking at here? 

Return currents will flow in both 2 &amp; 5, split in direct relation to how close the signal layer is, so you will want to bridge gaps with caps, but remember that a via typically has a 1nH inductance, before you consider the added loop area, this is very much inferior to a solid plane.

I would note that asymmetric stripline is something that layout tools sometimes have trouble computing impedances for, you may have to do this manually.  

I normally work on the basis that anything with fast edge rates runs close to a plane on at least one side, and if I must have a signal layer without an adjacent plane (or with one that is chopped up) it is only used for low speed stuff. 

Further it is worth defining the stackup such that internal high speed signals are very much closer to the reference plane then they are to any plane that is cut up, custom stackups are a very standard sort of thing by the time you are looking at a 10 layer board.