Time-series Statistical Analysis with FPGA
In theory, you could do it in constant time, but only until you run out of resources. Let's just consider hardware multiplies for now, since they will likely constrain the design. For example, the largest Xilinx Spartan-6 (the value line) contains 180 multipliers; the largest Virtex-6 contains 2128 multipliers (and will probably cost tens of thousands). These are 18-bit multipliers, but for the sake of argument treat them as abstractions. The number of multipliers then gives you the number of multiplications you can do at one time. If I understand the problem right, the square root of that number gives you the dataset that can run in one clock cycle.

In practice there are add/subtractions to worry about, the required precision will lower the amount of multiplies you can do, and the connections you'll need to make across the FPGA fabric will be very dense. All of these factors lower the maximum speed you can clock the FPGA at. Plus you have to get the data in and out of the FPGA. Thus my gut feeling is that this is not a 'killer app' for FPGAs. Conventional processors and GPUs are probably a better bet. (See R+GPU.)