Verilog Concatenation Problem
Is there anything in particular that's wrong with my mapping ideas? 


That fact that the 'mismatch' signal goes high says there is.

What is wrong is that you are mixing up LS and MS bits when you split up your values. W needs the whole of A and the MS bits of B. You are assigning the LS bits!

There is a simple solution splitting a nasty vector like that without having to worry where all the boundaries are:

assign {W,X,Y,Z} = {a,b,c,d,e,f,2'b11};