Getting starting designing CMOS ASIC - What is the must have software?
Big names in EDA software are Synopsys, Cadence, Mentor, and Magma.

Here is some of the software typically involved in a standard-cell ASIC flow:

HDL simulators read an RTL description of the design (typically written in Verilog or VHDL) and mimic the behavior of the hardware described by the RTL. Wikipedia has a list of Verilog simulators; the list notes which ones also support VHDL.

Synthesis tools read the RTL description and map it onto the cells available in your target library. The cell library is usually described in .db format, and may be provided either by your foundry or by a third-party library provider. The output of the synthesis tool may also be Verilog, but it won't have any high-level constructs, only cell instantiations and wires. This is called a netlist. Wikipedia has a list of tools.

Place and route (P&amp;R) tools take the netlist and search for a physical implementation of that netlist. This involves placing all of the cells in two dimensions and figuring out how to route the connections between the cells. Examples are IC Compiler, Encounter, and Blast Fusion.

As a design goes through P&amp;R there will be additional quality checks including static timing analysis (using e.g. PrimeTime), layout vs. schematic, and DRC.