PSpice - simulation worst case - delay on AND gate?
You have combinational feedback, from the outputs of the 393 through the AND gate and OR gate back to the CLR input of the 393. This is an inherently dangerous design style. Adding delay at the AND gate is not a good fix.

I'm not sure what it is you are trying to make this circuit do, but you might need to replace the OR gate with another AND gate so the the counter is only reset when clr_1 is also high. Then make sure that the delay between the falling clock edge and the assertion of clr_1 is long enough to allow the counter outputs and the first AND gate to reach their final values.