Brute-force convolution reverb in FPGA
A brute-force implementation of a 500,000-tap FIR filter @ 44.1 ksps requires about 22 G operations per second. Large FPGAs have hundreds of DSP units capable of doing a multiply-add in one clock, so the resulting clock frequency of a few hundred MHz is quite reasonable.

A slightly more interesting problem is managing the data. Let's be conservative and assume that a sample or a coefficient requires a 32-bit word for storage. That would require 32 Mbits of on-chip storage, which is rather a lot, except for the very largest (and most expensive) FPGAs.1

So, if we assume that you'll be using external memory, you'll need to read/write three words (96 bits) of data per DSP clock cycle in order to keep the DSPs busy. This is well within the capability of a DDR memory interface running at a reasonable speed. The larger Spartan 6 or Spartan 7 devices could easily handle this, and they have prices in the range of $100 - $150.



1 Just doing a quick check of the Xilinx Virtex Ultrascale line, the XCVU190 has enough on-chip resources to brute-force a 2 million tap FIR (1800 DSP slices, 132.9 Mb of on-chip memory). Unfortunately, this is a $32,000 chip!