Converting Pulse Sequence Inputs Into Separate Outputs
The input pulse train can be used to advance a two-bit counter made from a dual flip flop. Three gates in a quad three-input NAND IC can be used to generate the three decoded outputs without any other glue logic as long as the FFs have Q and Q bar outputs. Three monostable pulse generators in series, the first triggered by the first pulse in the pulse train, can respectively produce a first delay to cover the max. length of the pulse train, a pulse fed to the third input of the three AND gates to make the output pulse via the third input of the NAND gates, and the third pulse to clear the FFs. If you need it to work right after initial power up, there is also a need to clear the FFs unless they are spec'd to come up in a known state. 

An alternate design could use a three-bit shift register. That approach would not need decoding logic as long as the input was appropriately changed from a 1 to a 0. Some shift registers have an integral output enable so no extra logic would be needed outside the shift register IC. If the leading edge of the pulse train triggered the shift, the trailing edge of the input pulse could drop the input to the shift register to a 0. Similar to the reset needed in the case of using a counter, some action after the max length of the three pulse would need to raise the input to the shift register to a 1 to be ready for the next set of pulses. One way to do this would be a three-input NOR gate with the inputs respectively connected to the three outputs and the output connected to the input of the shift register.