Splitting a bit array in Verilog
The easiest way, if you don't need to parameterize stuff, would be to use binding, i.e. { }.

For your example using an 8-bit input_sig, you could do this in the following way:

reg [1:0] part0, part1, part2, part3;
always @(input_sig)
   {part3, part2, part1, part0} = input_sig;


That last line essentailly makes one big wire out of each part and assigns input_sig to the new wire bitwise (just like if the new wire was any other 8-bit wire). So if input_sig was 10111011: part3 = 10, part2 = 11, part1 = 10, and part0 = 11.

You can then you can manipulate the parts as you wish. If you do care about parameters, you could use a for loop, but the logic might get a tad complex (at least for my tastes). This solution won't be too cumbersome even for splitting a signal into 16 parts.