Reading a parameter value of module instance in verilog
You can access any variable within a hierarchy, including parameters, in Verilog testbenches pretty much exactly as you have shown.

instanceName.variableName


Say you instantiated your module and called the instance alu, then you could access the value of the parameter ADD in that instance by simply accessing:

alu.ADD




You can even do multi-level. Say your alu instance instantiated something called adder, which had a signal called cout. You could access that with:

alu.adder.cout