Can't get simulation of single phase parallel inverter working in LTSpice
First, you have a few design errors: you are driving the gates of the SCRs directly referenced to ground, as opposed to their G-K. The solution is to remove the grounds for the driving sources and connect them to the cathode of each. Then you are using zero values rise/fall times for the sources. You should know that this is not only a physical impossibility, but LTspice defaults to 10% of (Ton+Toff)/2, so what you really have are 100ns rise/fall times.

Then you are trying to use some thyristors at a 500kHz switching frequency. These SCRs are not MOSFETs, they're only good for low switching frequencies. If you reduce it to, say 1kHz, it will work. How well? That is up to you, the designer. But you should know that, if you only wanted to verify the concept of that schematic, you could have discarded the SCRs and used the builtin VCSW (switches, sw). But maybe you want to see SRCs in action, that's also up to you to know.

With these, here's a reworked version:



There is some forced dead-time for the driving pulses (Ton=0.98ms), the "transformer" has increased values and added some series resistance (when coupling is on, there is no more a default series resistance, I never understood why was it decided like this), and I've chosen a different SCR (reminisce of the trials before, didn't bother to change it back). The load is also increased, along with added rise/fall times for the driving sources, lower peak pulse values, and greater series resistance. Please note that I haven't bothered, in the least, to calculate usable values for components, I simply used the never-aging ogling.