Designing a three stage BJT transistor amplifier
For starters, to proceed with low distortion in mind, bias that first transistor to have the Vout at VDD/2.
Then bias the 2nd transistor to have Vout at 3/4 * VDD.
What does this allow?
What gains are achievable?
Then, if necessary, adjust your bias points.
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The maximum gain you can achieve with ONE bipolar transistor (so we are focusing on just that first transistor, for now) is VDD/0.026 volts.
In this case, with 15 volts, the maximum gain is 15/0.026 = 15 * 39 ~~ 600.
This formula assumes NO EMITTER RESISTOR. There is a 1Kohm in the emitter.
Working with that, let us get the gain of 50 in that first transistor.
Ignoring (initially) the 'reac' of that transistor (the 1/gm), for a gain of 50 we need 50 = Rcollector / 1Kohm, which is ignoring the loading effect of the 2nd stage.
This suggests the Rcollector be 50Kohm.
Now adjust the biasing network (on base of first transistor) to place Vce at about 7.5 volts.
Now compute the actual gain achieved, given a finite 1/gm of the first transistor.
What will the collector current be? 7.5 volts / 50,000 ohms
And 50,000 ohms is also 20 uAmp/volt, so Ic = 20 * 7.5 = 150 microAmps.
Across that 1Kohm in the emitter, Vemitter = 0.150 volts.
Now design the base_biasing network, including the base current demand.
And compute the achieved gain: 50,000 ohms / (1K + 1/gm_Q1)
Now you need to consider what to do with Q2.
By the way, notice the gain of that first stage will be lower than 50x. Why?

the small_signal resistance of the transistor's diode (BE junction) gets added to the 1Kohm Remitter

the loading effect of Rin of the 2nd transistor, which will be beta * that Re, thus 150 * 1Kohm = 150,000 ohm