What causes the difference in tPLH and tPHL?
Because the pullup and pulldown path at the output is not completely symmetric.  Just looking at the schematic in the datasheet, the pullup path is 130Ohm resistor, a NPN BJT, and a diode.  The pulldown path is just a NPN BJT.  

So it makes perfect sense to me that the high to low transition would be faster (there is less resistance in series with the power supply).  

Of course the designers could size the pullup BJT and diode to be larger than the pulldown path.  But then the stage back would need to be perfectly balanced as well, and you can see from the datasheet they are not symmetrically driven.

Even in CMOS logic this occurs because it is very rare that the PMOS and NMOS will be equally strong.  In the case of multiple input gates, the situation becomes even more complex since now the pullup/pulldown speed depends on how many inputs are switching in parallel or how many transistors are stacked in series!