How can I improve my 3 decade counter design so that it counts sequentially in Verilog
Since your code is for a learning exercise I will not give a full answer.

Synch_BCD_Counter should have 1 more input for enable. This input will replace PWR. It also needs to be added to various parts of your combinational logic, which I will leave to you to figure out.

The y output will become the enable for other Synch_BCD_Counter instances.

All instances should be using the same clock. In general, it is a bad practice to use output logic as a clock of other blocks (there are timing issues and other limitations).