How to identify areas of a FPGA design that use the most resources and area?
I cross posted this question on the Xilinx Forum here:
http://forums.xilinx.com/t5/Implementation/How-to-determine-what-part-of-the-design-consumes-the-most/td-p/393247

This answer is largely based on the comments there. Thanks to Deepika, Sikta and Gabor.

First, enable 'Generate Detailed MAP Report' in the map process properties (-detail).

Then, open the Design Summary, and navigate to Module Level Utilization. Here is the complete hierarchy, showing exclusive and inclusive design utilization.

Each line will show a number pair like 0/5392. This means that that module contains zero of that specific element, but that module and all of its sub-modules contain a total of 5392 elements.

Here is my output (partially expanded)



When working on reducing the size, Gabor recommends switching to a larger FPGA in the synth tools so that it can completely map even when it's too large to fit in your current FPGA, and it will make the tools run faster.