Bad design of shift register
You're right &mdash; you can't read from an out port in VHDL.

You need to create an internal variable that you use for the logic, and then assign its value to the output port:

architecture arch of ShiftRegister is
    signal y_int : std_logic_vector(n - 1 downto 0);
begin
    process (clk)
    begin
        if rising_edge(clk) then
            if w = '1' then
                y_int &lt;= x;
            else if shift = '1' then
                y_int(n - 2 downto 0) &lt;= y_int(n - 1 downto 1);
                y_int(n - 1) &lt;= '0';
            end if;
        end if;
    end process;

    y &lt;= y_int;
end architecture arch;