calculating FSM's maximum clock frequency
Timing is fully dependant on the implementation. You will need to fully specify all the state equations, transition equations and output equations. Then you go through a minimization process to reduce the equations to a minimal set. After that you can map your standard gate and flip-flop selections to the sets of logic equations. Once you compute the worst case timing condition that will lead directly to the maximum clock frequency. Sounds like you know where to start. There is some work to do before you can start throwing around timing numbers.