Can someone explain a couple of lines of Verilog to me?
What is the purpose of key0_dly? Why does the if statement check the 2 bits of it?
  


It wants to complement LEDG[0] only if the trigger has occurred during the previous loop but not 2 loops ago. Looks like simple debouncing/edge detection to me.


  
  Why is key0_dly assigned the values {key0_dly[1:0], KEY[0]}? What does that line do?
  


It left-shifts key0_dly one bit, shifting the value of KEY[0] in.


  
  Is this line key0_dly &lt;= {key0_dly[1:0], KEY[0]}; in the if statement? Am I correct in saying that if there is no begin and end then like in C only the one line of code that follows in the if block?
  


Sounds right. But you need the shift to happen each loop otherwise there will be no way to trigger the condition.