SRAM memory cell - what kind of flip-flop
A typical SRAM uses a trick I call "resistor priority logic", even though it actually uses variable-sized transistors rather than resistors.  A "normal" latch design would use transistors to control whether the input to one of the inverters should be driven by the holding latch or by the signal to be latched.  This would allow a new value to be latched without generating any bus conflicts, but would require more transistors per memory cell.  It's cheaper and easier to make sure that when writing a memory cell, the bus is driven hard enough that--even with the memory cell transistors trying to drive the bus to the opposite state--the bus transistors will overpower the transistors in the memory cell, but when reading, the memory transistors are large enough to drive the bus when nothing else is doing so.  This type of trick requires some care in manufacture, to achieve the optimal balance between having the memory-cell transistors large enough to drive the bus at reasonable speed, but small enough that the bus drive transistors can overpower them without wasting too much energy.  The amount of tweaking necessary to make this type of logic work efficiently is such that it isn't used much.  On the other hand, RAM is sufficiently common that it's worthwhile for chip manufacturers to refine their process especially for it.