iCE40 LVDS clock input
Signal Critical Length

How long a PCB Trace can be before we MUST pay attention to Impedance Control.  

Function of Frequency (1/16th Wavelength)

\$ l_{critical} = \frac {c}{f} * \frac{1}{ 16*  \sqrt{ε_{eff}}} \$

example


At 1 GHz = approx .425” = 10.8mm (Microstrip- FR4)  
At 1 GHz = approx .375” = 9.5 mm (Stripline - FR4)


- since rise time BW (-3dB)= 3 /Tr for 10~90%


and your 200MHz clock has rise time 0.2ns , BW = 15GHz


However your impedance is not controlled so one can only guess how many cycles of ringing will occur if the tracks were several hundred ohms reactance The Q can be determined and then amount of overshoot/undershoot.

If the undershoot crosses  gate threshold then that gate will experience jitter of about 10~20% on the edge of that gate. If undershoot ringing did not reach Vss/2 then no possible edge jitter would occur. 

Your design needs more care in Zo design as it is marginally ok, but I would need a 3D model of the clock path with more details.

So all I can say is it is marginal.