Why do I get a failure in Quartus while trying to programming my FPGA?
As Socrates says, this is a JTAG problem. Check signal integrity on the JTAG lines. Check the voltage level and especially the clock. If there is ringing during the rise of the clock, it will try to clock in 2 bits instead of one. This will cause JTAG to fail.

Regarding the warnings:


  Warning (20028): Parallel compilation is not licensed and has been
  disabled


means it Quratus II using one core. It will not take long for such a simple design


  Warning (169174): The Reserve All Unused Pins setting has not been
  specified, and will default to 'As output driving ground'
  This means don't connect other chips to other pins.
  
  Warning (292013): Feature LogicLock is only available with a valid
  subscription license. You can purchase a software subscription to gain
  full access to this feature.


This isn't necessary for a small design. It is useful for large designs and partial recompilation.


  Warning (306006): Found 1 output pins without output pin load
  capacitance assignment
      Info (306007): Pin "pin_name2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing
  analysis


This means the reported timing will be faster than it really is.


  Warning (332068): No clocks defined in design.


That makes sense; you don't have any clocked registers.