Offset of Output voltage of an op amp circuit with capacitor
You're feeding the OpAmp's non-inverting input via a fairly high-value resistor (1&nbsp;M&Omega;). It seems like the simulation considers the TL081's input offset current with a value of 50&nbsp;pA, because your (unity gain amp = buffer) produces an output offset voltage of 50&nbsp;µV&nbsp;=&nbsp;1&nbsp;M&Omega;&nbsp;*&nbsp;50&nbsp;pA, ignoring the sign (simulation says -&nbsp;50&nbsp;µV).

To be sure, plot the current into the "+" pin of your TL081 and check if it's 50&nbsp;pA.

The output offset current in your picture is actually anything that will "leak" into the "-" input (theoretically zero, practically equal to the input offset current of this very pin). Proof: Kirchhoff's current law - there is nothing else connected to the output, so anything coming from the output must be going the only possibly way which is the inverting input.

Fun fact: The value I expect you will see as the input offset current into the non-inverting input matches what you already see as the input offset current into your inverting input ;-)

As others have already mentioned, the TL081 has an input offset voltage some orders of magnitude higher than the error you see caused by the input offset current. As you are using your OpAmp as a buffer (gain = 1), your input offset error translates directly to your output offset error. In a practical circuit, this would be your main concern, and the lesson to be learned here is this: Simulations help you understand stuff, but they are always to be taken with a grain of salt. You are not done designing a circuit unless a simulation tells you exactly the same story as a breadboard on the bench, tested with instruments you trust. Any difference between the simulated and the real picture may be tolerated only if you have a good explanation. If the picture on the scope and the simulator's waveforms don't match, improve the simulation until they do and double, triple, ... check your practical circuit. But as you are asking this question, I guess you know already ;-)

Also, the effect that caught your attention is one of the reasons why circuit designers try to stay away from high-value resistors (say: above 100&nbsp;k&Omega;) in signal-processing circuits if they can, because practical parasitic effects like leakage, offset etc. start to become annoying once you get into this range. If your circumstances permit, try to decrease the resistor's value and increase the capacitance just by the same factor; the RC time constant will remain the same and you gain the freedom to neglect parasitics. Also, low-value capacitors are tricky: Any parasitic capacitance (OpAmp input capacitance, layout traces, ...) are in parallel with C1 and increase the effective value to, say, 205...220&nbsp;pF, which is a considerable error.

Edit (in response to comment):

The start-up behaviour (change of offset at the beginning of the plot) is just the DC offset current charging the 200&nbsp;pF capacitor. For a DC analysis, we can consider your AC source to be a short and we end up with this scenario - a 50 pA current source connected to a parallel capacitor and resistor:



The current source charges the capacitor, and because of the resistor, the voltage reaches a steady state after a while. Note that the RC time constant is 200&nbsp;µs - as can be observed in both simulations, yours just has the additional AC component of your source V2.