How does Altium Designer's "impedance constraint" feature work?
You must have at least one power/ground plane defined in your layer stack-up for impedance controlled routing to work. From the docs linked by @danny:


  Defining the Layer Stackup
  
  A fundamental requirement for controlling the impedance is to include
  power planes.


Basically, the calculations for microstrip or stripline traces require knowledge of the distance between the signal plane and the ground plane. Since you cannot have a plane as an external layer (this is a Altium restriction), you therefore must have a minimum stackup of three layers.

If you want to do two-layer impedance controlled layout, the best workaround right now is to add a third layer as a ground plane, specify the thickness between the signal plane and ground plane the same as your full 2-layer core thickness, and just either fill the bottom plane with a manual ground polygon and don't export the ground plane when generating gerbers, or export the power plane as a positive layer and ignore the bottom layer when you're generating gerbers.