What would happen if write strobe signal is asserted in asynchronous SRAM as data & address are toggled
Yes, that is correct. If you change the address value while both CE and WE are asserted, you may corrupt any number of other locations in the memory as the change propagates through the internal row and column decoders at various speeds.

However, it is not necessary to toggle both WE and CE on every write cycle, since the actual write operation is controlled by the logical AND of both signals. You could leave one of them asserted continuously and only toggle the other when the address and data setup times have been met.

For example:

      _________________               ______________               _________
CE-                    \_____________/              \_____________/

WE-   ___________________________________________________________________
      ____      ________________________      ________________________
addr  ____XXXXXX________________________XXXXXX________________________XXXXXX
      ____                 _____________                 _____________
data  ____XXXXXXXXXXXXXXXXX_____________XXXXXXXXXXXXXXXXX_____________XXXXXX


Note that in  the datasheet, the address setup time tSA is relative to the leading (falling) edge of CE- (or WE-, whichever occurs last), while the data setup time is relative to the trailing (rising) edge. The address setup time is zero, but it still means that the address cannot change while CE is asserted. Both the address and data hold times are relative to the trailing edge.