Why should we not change inputs to a sequential circuit (Moore machine) at the clock edge?
Investigation
Using Mentor Questa 2020.1 and Cadence Xcelium 20.09 we don't get any glitches.
Using Synopsys VCS 2020.03 and Icarus Verilog 14 we get glitches.
I used EDA Playground to simulate, if interested please visit this link.
Why do you get a glitch?
The reason you are getting glitches is race conditions / race hazards due to the non-deterministic ordering of concurrent Verilog blocking statements in simulation.
How do you fix it?
Here are 2 techniques to avoid glitches in sequential logic simulation:

Apply stimulus a little bit after the active edge of the clock, using a delay, as you have done in your question.

Using nonblocking assignments you can drive the inputs on the active edge of the clock without getting glitches.


This testbench uses nonblocking assignments and simulates without glitches on these simulators: Mentor Questa 2020.1, Cadence Xcelium 20.09, Icarus Verilog 14 and Synopsys VCS 2020.03.
module tb();
initial begin
  $dumpfile(&quot;dump.vcd&quot;);
  $dumpvars(0,tb);
end

reg clk;
reg in;
reg rst;
wire out;

initial begin
    clk = 1'b1;
    forever #5 clk = ~clk;
end

seqDetector s0(in,clk,rst,out);

initial begin
    fork
    #0 rst &lt;= 1'b1;
    #10 rst &lt;=  1'b0;
    #20 rst &lt;= 1'b1;
    #10  in &lt;= 1'b0;
    #20  in &lt;= 1'b1;
    #30  in &lt;= 1'b0;
    #40  in &lt;= 1'b1;
    #50  in &lt;= 1'b1;
    #60  in &lt;= 1'b0;
    #70  in &lt;= 1'b0;
    #80  in &lt;= 1'b1;
    #90  in &lt;= 1'b1;
    #100 in &lt;= 1'b1;
    #110 in &lt;= 1'bx;
    #120 $finish;
    join
end
endmodule

How to avoid glitches in State Machine Designs?
Register the outputs. To learn more, you can read this answer.