VHDL: Output is always U
Your testbench component/UUT is named incorrectly.  

You're module is named "first", but your testbench is declaring a component "test1".  So your testbench is trying to run tests on a component that doesn't exist.  Rename all instances of "test1" in your testbench to "first" and it should work.

COMPONENT first
 PORT( 
 F : IN STD_LOGIC;
 R : IN STD_LOGIC;
 W : IN STD_LOGIC;
 CF : OUT STD_LOGIC;
 WI : OUT STD_LOGIC
 );
 END COMPONENT;


and

 UUT: first 
 PORT MAP(
    F =&gt; F,
    R =&gt; R,
    W =&gt; W,
    CF =&gt; CF,
    WI =&gt; WI
 );


As an aside, all of your naming conventions are painfully obfuscated.  Name things in a manner that you can understand what they are without context.  Avoid names like "first", and "test1", also avoid single character or hyper-abreviated port/signal names like 'F' and 'WI', unless it's solely a D flip-flop where D, Q, and CLK, are standard nomenclature.

ALSO ALSO, in your module you're assigning CF &lt;= F and F;  this is identical to just doing CF &lt;= F;.  ANDing a value to itself will always just output itself.

\begin{array}{|c|c||c|} F &amp; F &amp; CF \\
\hline
0&amp;0&amp;0&amp;F = 0\\
0&amp;1&amp;0&amp;will\ never\ happen\\
1&amp;0&amp;0&amp;will\ never\ happen\\
1&amp;1&amp;1&amp;F = 1\\
\end{array}