IO clock pin far from design, reduce propagation delay
Two key concepts:

FPGAs in general (and Xilinx FPGAs in particular) have clock distribution networks that are designed to deliver clocks with low skew across the entire chip.
A PLL (or DCM) can be used as a zero-delay clock buffer.

Combining these concepts gets your clock across the chip with essentially zero delay.



simulate this circuit &ndash; Schematic created using CircuitLab
The PLL adds enough delay so that the total delay through it and the clock distribution network is exactly one clock period. Since that means there is essentially zero delay between the PLL inputs, and there is zero delay among the loads of the clock tree, the transceiver gets a clock that has essentially zero delay from the input pad on the other side of the chip.