Time (Propagation delay) taken for adding 3 n-bit binary numbers using Carry Propagate Adders (Ripple carry adders)
Here's a diagram for 3 bits to show what many commenters are describing for the parallel execution of the addition of the 3rd input.
It's drawn such that the lsbs are on the left, and the calculation delay propagates left-to-right.
For n=3 bits, you can get the total sum of S[4:0] = A[2:0] + B[2:0] + C[2:0]
after a delay of only 5.  That's U1-&gt;U4-&gt;U5-&gt;U6-&gt;U7.
Perhaps the (2n+1) is for half-adders?  Or some more structure, perhaps where the adders are reused, sequentially in time?



simulate this circuit &ndash; Schematic created using CircuitLab