"Increase" of a register in VHDL and hardware synthesis
The carry-out is ignored in such expressions. If you care about it, you need to account for it explicitly. For example, you could write something like this:

-- perform the addition, making room for the carry-out
signal sum : std_logic_vector (4 downto 0);
sum &lt;= ("0" &amp; reg) + "00001";

-- update the register and capture the carry-out at the same time
process ...
    reg &lt;= sum (3 downto 0);
    carry &lt;= sum (4);
end