Overshoot and undershoot on clock signal
Total Signal path loop Inductance with circuit and probe capacitance will cause overshoot due to the tiny reactive load on a very high impedance probe. For this reason all signal and ground leads must be very short. Your square wave has only 20% symmetry so you may want to check your bias.
CMOS is an almost perfect voltage switch with a bipolar switch resistance RdsOn, that is low 50 ohms +-50% depending on the family 3.3V lower , vs 5V higher.
With short(1m)  10:1 probes most likely you are seeing false signal from the probe ground inductance being too long which tends to resonate with the coax capacitance when L/C &gt;&gt;1.

Any signal inductance in series with a 30pF probe will cause overshoot with typ. 0.5~1nH/mm trace (signal + ground ) and probe ground wire inductance.
I assume you have a decoupling cap near the IC &gt;10nF as this will also add inductive trace length.

These are all reactive circuit impedance that affect the high slew rate voltage V(L) =LdI/dt with current not from 10 meg but the probe pF Ic=CdV/dt .
So it is normal, what you see, but if you want textbook waveforms then learning how as a Test Engineer does, is well documented in thus forum using the calibrated probe with clip and gnd wire removed using only wire tip and coaxial barrel to IC gnd with a convenient resistor wire test point .  Matched load impedance attenuates 50% or 0.1pF buffered FET differential probes also work better for maximally flat frequency response to the probe limits.