AD7928 timing diagram question
You are correct that T4 is the critical parameter. This defines the timing window that defines valid data, and reading after this time will not guarantee that.

T7 appears informative, in the sense that the next data bit will appear at this time plus any internal setup, transition and settling time. What it does tell me is that you may make no assumptions about what data is on the output in this window between the end of T4 and the end of T7. The output may have valid driven data, but it is unknown as to what that data will be.

T7 is interesting - if you look at the maximum clock frequency (20MHz), that yields a minimum cycle time of 50ns. If you add the time (max) that the data may be held for (T7) and the guaranteed minimum hold time (considering data held on bit n and hold  on bit n+1), they add up to that minimum cycle time.

It is highly likely that the internal registers have a 10nsec setup time (certainly the Din timing requires it, see T9), so we have, from Sclk transition at bit n (out):

40nsec max to bit n+1 appearing internally.

10nsec internal setup time (data bit appears at clock transition).

10nsec hold (guaranteed).

So from a clock transition at bit n to guaranteed hold for bit n+1 = 60nsec (max).