Cascaded flip-flops and shift register timing
Edge triggered FFs have set-up and hold time requirements. Only data that was present before the clock triggered, will have satisfied the set-up time, and thus be &quot;registered&quot;. Since (if well designed) the FFs have their clocks triggered at the same time, or nearly the same time, data that is &quot;registered&quot; at the input of one FF will appear at that FF's output too late to be registered by the next FF. That is why changes that happen in one FF don't just ripple down the entire shift register in one clock cycle.
Addendum:
The design of an edge triggered D-Flip-Flop used in another answer (by Paul Ghobril), and shown here, may work in an integrated circuit, but relies upon careful control of propagation delays. That is, it is susceptible to race conditions. (Sadly it is found all over the internet).

A edge triggered D-Flip-Flop that does not depend upon careful control of propagation delays is this:

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