Should the clock from a PS/2 keyboard be used in a Verilog always block?
It's not always advisable to block on a relatively slow clock in a relatively fast logic chip. Depending on how the synthesis tool worked, it may use one of a few dedicated clocking trees in the chip or just a regular IO line. A dedicated clock tree may not support a low frequency and the regular IO may skew improperly. I suspect one of the following:

Timing issue across domains

If you are connecting with faster logic you'll need some FIFO to cross the clock domains or you may lose data in the transfer. Typically this happens when going from faster to slower (eg. FIFO overflow) but in real silicone crossing a clock domain is tricky

setup and hold times 

if your LUT or slice is running on a slow clock it's possible the button pressing that causes the miss sync is due to propagation delay. Unlikely but it may be worth putting the frequency of the PS/2 clock in your timing closure tool to see.

my solution

I'd block on the clock used in the rest of your system. Use a 2 bit register and bit shift in the  PS/2 clock to make an edge detector. Then you control your state machine on the falling edge (2'b10). Using the fast clock even if you have a 1 cycle delay before reading the data bit you still have hundreds of cycles to take a sample.