Why delays cannot be synthesized in Verilog?
Synthesizing means somehow converting what you have described (in Verilog here) into real hardware.

Now in your Verilog you say that you have a 50ns delay. Ok, but now, in term of hardware, how would you convert this into actual hardware?

If you are using an FPGA, how would you actually build your 50ns delay using the available FPGA resources (LUT, Registers, Ram element, ...)? By adding additional routing delays? imagine that you specify 1s delay! Impossible without using ALL the routing capability of your chip (maybe not enough). Your design can't be fitted.
Same for an ASIC. You would use 80% of the silicon surface to add a delay to ONE line.

The way is it supposed to work is that you use synchronous design and you implement the delay by yourself using counters or other techniques. But delays have to be multiples of the clock of that element.

Usually you find things such as "after 10 ns" theses are propagation delays. When doing an ideal simulation on a Verilog simulator, outputs happen exactly when the inputs change. This is not realistic and does not describe the way real hardware work. To account for that you can specify after how much time your output will be changed: using the delay declaration.