Timings constrains for isochronous clocks
You can use -phase with create_generated_clock. For example, below are two 125.0 MHz clocks, but the second one is shifted 90 degree:

create_generated_clock                                                  \
    -source {pll0|altpll_component|auto_generated|pll1|inclk[0]}        \
    -divide_by 4 -multiply_by 5 -duty_cycle 50.00                       \
    -name clk_125                                                       \
    {pll0|altpll_component|auto_generated|pll1|clk[0]}

create_generated_clock                                                  \
    -source {pll0|altpll_component|auto_generated|pll1|inclk[0]}        \
    -divide_by 4 -multiply_by 5 -phase 90.00 -duty_cycle 50.00          \
    -name clk_125_90                                                    \
    {pll0|altpll_component|auto_generated|pll1|clk[2]}