constraint error and illegal load problem in Virtex-2
That Verilog module is top-level, right?  Make sure, because the toolchain will try to map the UCF onto the top level module.  If you're using a third-party toolchain that "sits above" the Xilinx toolchain, you will want to investigate what top-level file the third-party toolchain is creating.

I looked in my UCF files and I don't see INST at all.  I use NET everywhere (with the exception of one TIMESPEC on the main clock)



Another thing I noticed...

always @(posedge clk_ddr or posedge rst) begin
    if(rst)
        cnt &lt;= 1'b0;


You are using posedge on two different signals.  Pin C on FDC probably means the "clear" pin of a D Flip Flop (hence, FDC).  You probably actually want an FDCE (D Flip Flop with async Clear and clock-Enable), or an FDE (D Flip Flop with clock-Enable).  The synther is probably confused because flip flops only have one edge-sensitive input and you're asking it for a flip flop with two edge sensitive inputs.

Did you want an async clear, or a sync clear?  If async, get rid of the "posedge" in front of rst.  If sync, get rid of the entire "posedge rst".  Async clear (FDCE) is trouble unless you know what you're doing; go for the sync clear (FDE).