How can I draw layout for 2 NMOS having different body potential?
In a bulk CMOS process there's only one P-substrate area so then you cannot make this circuit. All NMOS body contacts connect to the P-substrate and that is the only option.

If you have a triple well option available then it is possible to make a separate P-well (which which sits inside an N-well which sits inside the global P-substrate) then this is possible but realize that there will be (reverse biased) diodes between that &quot;local Pwell&quot; and the P-substrate.

If you have an SOI (Silicon On Insulator) process available (lucky you!) then you can make an isolated P-well for every NMOS.


So &quot;how do I draw this&quot; depends on the process you're using. It might not even be possible!