No CS pin available on components (external ADCs) with SPI interface to choose one
What is being proposed is to gate the SPI clock with GPIO pins.

Looks like ATMega328 SPI controller stops the clock between transfers, so it’s practical to use clock gating. GPIO can be used to direct the clock to the appropriate device, with software changing the GPIO between transfers.

This ADC uses clock-idle low (CPOL=0), so the gating logic needs to ensure the clock is low on the deselected devices. Take care on this detail if you choose a mux: some set the deselected pin high instead of low. This may seem weird, but an analog SPDT switch like the On Semi NLAS1053 can work for this, and has the benefit of less inserted skew. Add a pull-down to the device-side clock to ensure it is at a '0' state.

Or, use two 'and' gates and two GPIOs, one for each device.

One more thing: CONVSTn needs to be toggled at least once to set the device in an initial state and to start the conversion. So one more GPIO for that. ADI has some suggestions in the datasheet for handling CONVSTn.

Finally, the DOUT pins of the ADCs can be tied together and connected to MISO. This is okay because the DOUT of an inactive (not-clocked) device goes high-Z, so it won’t interfere with the chip being read.

So you have 2 GPIOs (1 for mux, one for CONVSTn) or 3 GPIOs (2 for clock gates, one for CONVSTn.) The choice is up to you.

Software stuff. Before each SPI transfer, software sets the GPIO to select the device and toggles CONVSTn. It then waits the specified time (6us) for the conversion to complete, then initiates the SPI read.