Verilog RAM module with Register File & Testbench
May be I misunderstand something, but where is inputs for your ALU module? So I think, the first problem in your structure is, in the case you haven't inputs for ALU you write into the memory unknown values (U or Z, what you have on ALU output) when write_en is active;  The second problem is in the module lab3_reg you have incorrect assignment in line assign data = DataOut;, it should be assign DataOut = data; because data is output of internal module you have "X" on the port (multiple drivers); And last problem is in the tesbench testbench_lab3_reg module, there you also have bad assignment assign DataOut = (read_en) ? memory[Read_address] : memory[Write_address]; in this line. DataOut is output of your top module, but in the line you assign another value, in the case you also will get "X" on the wire.  Try to fix the mistakes in the assignments logic to correct and then I think your module will work well.   P.S. By the way, what do you want to get by the follow assignment assign DataOut = (read_en) ? memory[Read_address] : memory[Write_address]; when DataOut is output? If you want to use bidirectional bus you should declare it like inout in modules.