Different Adder Implementations
What you don't want to do is implement the adder yourself out of gates.  Use the features that VHDL/Verilog give you for adding numbers.  Any adder you create is going to be larger and slower than anything the VHDL/Verilog compiler can do.

The reason for this is simple:  FPGA's have dedicated logic in them for doing adders with a minimum amount of logic and as fast as possible.  This includes special carry chain logic and routing.  If you let the compiler utilize these then you'll benefit from the stuff that's already in the FPGA.  In other words, just do Sum=X+Y+cin, where X and Y are multi-bit numbers.