LVDS_25 voltage range
LVDS_XX only gives you the voltage of the power rail for that IO bank. LVDS_25 is only allowed on a 2.5V bank, LVDS_18 is only allowed on a 1.8V bank, etc. The actual voltage levels are just "LVDS level."

The information in this Answer specifically targets Xilinx, because that's what the question refers to and that's what I'm experienced with. To apply this to other FPGAs or devices, just check the input and output specs on the datasheet.

LVDS common mode voltage is around 1.25V. See the blue circles in the below tables.
LVDS differential voltage is around 350mV. See the red circles in the below tables.  

To know if a driver is compatible with a given receiver, check the levels. If the output min is above the input min, and the output max is below the input max, you're fine. Check the whole datasheet for other constraints, such as max IO-to-Vsupply difference (the Xilinx datasheet takes this into account).


source


source
NOTE: "LVDS" here is referred to as "LVDS_18" in other contexts.

Information and tables taken from the following sources:  


TI: Interfacing Between LVPECL, VML, CML, and LVDS Levels 
Xilinx: Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics