Two phase latch max delay constraint
This example uses transparent latches instead of edge-triggered flip-flops, and notice that the data inputs (D1, D2, D3) are changing while the latch enable signals (\$\phi1\$ and \$\phi2\$) are high (asserted). Therefore, the important delay parameter is from when the input changes until the output is valid, \$t_{pdq}\$.

If the circuit used edge-triggered flip-flops then \$t_{cpq}\$ would be relevant. If the data inputs to the latches changed only while the latch enable was deasserted then the delay from the enable to Q would be relevant.