FPGA with a logic gate simulator
Usually the functionality of what goes on an FPGA is so complicated that a schematic representation is extremely cumbersome. And usually when working with FPGAs, one works much higher than at the level of logic gates. The synthesis software then takes over the job of converting a relatively easy to read and maintain behavioral description into FPGA specific components. Note that I don't say 'gates' here because FPGAs are generally built from reconfigurable logic elements which can stand in for rather complex logic functions which would otherwise a number of gates to implement.

Another problem is that there are no standard methods for saving graphical schematics for FPGA use. Vendors sometimes have proprietary tools for this. And the tools, when they exist, are usually quite cumbersome. Not much development time is spent on them because most people who do serious FPGA work use only HDL.