Intel FPGA: applying timing constraints
In your set_output_delay -min statement, just enter the hold time as a negative value, like this:

set_output_delay -clock &lt;clock&gt; -min -&lt;hold time&gt; &lt;port&gt;


Have a look here: http://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/

Here too: https://forums.xilinx.com/t5/Timing-Analysis/How-to-set-input-delay-and-output-delay-when-source-Synchronous/td-p/549028