Clock distribution gone wrong
It sounds like your oscillator is designed to drive a CMOS load. With the load you gave it, it has to produce 66 or 100 mA to reach a high voltage (66 mA for 3.3 V, 100 mA for 5 V), and it's probably not designed to do that.

One option is to terminate with the equivalent of 100 ohms to Vcc/2:







simulate this circuit &ndash; Schematic created using CircuitLab

This reduces the output current required from the source by half.

Even better, if you're able to do it, is route the signal past the two loads in sequence and terminate only once. Since you're able to produce 100 ohm tracks, use that geometry for the whole path:







simulate this circuit

This reduces the current demanded from the source by half again. 

Of course it's also possible to add a buffer amplifier that can drive the relatively low impedance of your load, but that adds components you might not have budget or space for.