How to calculate open-loop input impedance of an opamp if it is not explicitly given in the datasheet?
Generally, input resistance for commercial CMOS opamps are high enough (in the 100M to G Ohms range at DC) that optimizing the circuit for it are futile, considering the optimal resistors will have mismatch themselves. This is caused by the differential input stage for the opamp being a (or two in the case for rail to rail opamps) MOS differential pair generally. As for the input capacitance for frequency domain behavior, you can see the value listed to be 2pF single ended and 4pF differential. Usually, this capacitance will not have any observable effect since the gain bandwidth of the amplifier is much lower.

For CMOS opamps, to calculate the input impedance, you can simply consider the input capacitance parallel to a very, very high resistance value, which is almost equivalent to just considering the capacitance.