Efficient single cycle huffman decoding technique with wider input data?
If there's one thing that FPGAs are good at, it's lookup tables — both the little LUTs used for logic and the larger block RAMs that can be used as ROMs. In order to avoid falling behind, in the worst case, you  need to be able to decode up to 14 input bits (two 7-bit symbols) at a time. A 16k-word (but rather wide) ROM can easily do it in a single clock cycle. You just pre-compute all of the possible decodings for 14-bit combinations and load them into the ROM. The outputs of the ROM will be:

The number of complete symbols found in the current set of 16 input bits (1-8, 3-bits)1
The decoded symbols (8 × 7 bits)
The number of bits left over for the next cycle (2-8, 3 bits)

for a total of 62 bits of width. This is just under a megabit of block RAM, which would well within the capability of many modern FPGAs. You just need to add a 16-bit register to hold the input data and a barrel shifter2 to move it around as each new byte comes in.

1 Note that it doesn't matter if there are more than 8 symbols in the current set of input bits. If that happens, the rest of them get decoded on the next clock cycle.
2 And remember, if your FPGA has dedicated hardware multiplier modules, they make great barrel shifters!