Trouble with converting PWM to analog
TI has a better Filter App for this then you can choose Elliptical, Cauer, Butterworth , exact values or 0.5%' 1% etc. 

You must learn to define specs first, pass band gain , cutoff f, passband ripple, band reject f and attenuation before starting any design. 

So define your gain and PWM attenuation then it will compute order of filter needed. Then menu> edit > design and start again until happy.

added

What you need to learn is how rise speeds up with more BW using higher order filters not simple ones. It's not hard with TI filter design app.

All digital telephony needs a brick wall 4kHz LPF to sample at 8kHz and fit at least 3.5kHz using single IC filter chips that are 7th order.

You have many choics; but not a simple RC solution, yet not that hard! Again only YOU can define the specs. 

Decide what latency you can live with at 490Hz (slow) PWM ?1ms, 2,4,8,16,32,64,128 ms ? and not 1second then how much accuracy 10%,2% etc.

This determines the optimum solution. 

Common to all solutions is convert 8mVpp pulse to logic levels thus gain &lt;1000, while all inverting CMOS logic gates (except non-buffered) have a DC gain of 1000+ so to get logic levels it is as simple as C coupled to INV input and R feedback using ~RC >10/f to get good square wave or narrow pulse, as long as PWM traces don't have noise glitches. you will get full swing from 0 to Vdd.

1) the fastest PWM to DC converter takes one (1) cycle of latency . this is done with an integrate that dumps the charge cap using a precision Vdd/2 Vref on Vin(+) and a CMOS analog switch with a small NPO cap.

2) the next approach is a steep high order LPF at 250Hz with ripple at 490Hz TBD?? this has latency of ~&lt;0.5/250Hz

3) the worst design is 50xT simple RC filter