3-state buffer mechanism
A typical output stage uses a totem-pole or push-pull configuration. For a logic 0 the lower transistor is on for a logic 1 the upper one.

Now it is possible to turn off both transistors which neither drives the output high or low. The circuit is basically disconnected (high impedance, high-Z).

A circuit that accomplishes that is shown below.



When enabled the signal QP12 and QN12 are on the inverter formed by QP11 and QN11 can drive the output.

In the disabled state QP12 and QN12 disconnect the inverter from the supply and the output is in a high impedance state regardless of the input signal.