Implementing a Mealy Machine in Verilog
I assume this is a shortcut for: 

A[0]===1'bx || A[0]===1'bz


If A[0] is 1'bx ~A[0] will still be 1'bx.
If A[0] is 1'bz ~A[0] will make it 1'bx.

I have to assume this is in a test bench because that code can not be synthesized.