Reading From a Large Array of Photoresistors
You say 18 x 24 grid implying =432 inputs BUT do not let the optical or geometric constraints force you into treating them logically as an array of a given shape or number of dimensions.

The "obvious" way is to address an X=-Y array.
 If you use 18 rows and 24 columns you need 18+24 = 42 pins.
 But sqrt(432) = 20.78.
 As we can't find 0.78 of a pin a square array = 21 x 21 = 42 pins still. No gain. But that will access 21 x 21 = 441 locations so you have 441-432 = 9 more "free" locations if desired.

BUT the cube root of 432 =~ 7.56.
 If we implement an 8 x 8 x 8 array we can access 512 locations with only 24 pins.
 = 42 - 24 = 18 less pins and 512-432 = 80 extra locations.  

BUT can we scan a cubical array?
That's a definite maybe. 
 Much depends on other parameters such as access speed loading etc, but one way may be to eg make each photocell position into a DTL (diode-transistor logic)  AND gate or a DTL NOR gate. In one case the optical transistor can be active only when all 3 address lines are high - if any one is low the transistor is disabled. In the other case all inputs must be low - if any is high the transistor is disabled. This MAY require 3 diodes and a resistor per node, and may not. The opto transistors may all be able to be paralled when off - or th e loading may be too high.
 The transistors may be able to be broken up into moddules with simple addressing of this sort.

Consider the possibility of using an open collector multiple output digital driver IC that normally has outputs open circuit but grounds one at a time as required. Or N at a time. The IC may have been conceived as a digital device but can still be used for analog enabling.

eg look at the MM5450 / MM5451 34 output LED display driver  and get excited.
 This IC MAY be able to do what you want. MAY. Just possible 432/34 = 13 of these may be able to drive your array with little else. Or not. But if not something similar may.



Be aware of what the CD4051 / 52 / 53 analog multiplexers  can do for you. Very olde. Very useful. Better and newer available - usually for more $. These are about 25 cents in 100+ quantity.
 DO note th ability to switch higher V AC with lower V DC or to switch bipolar signals with +ve control voltages.

DTL

Note that if implementing a 3D multiplex address scheme, careful design will probably allow most or even all of the resistors to be eliminated. 

Wikipedia


Schematic of basic two-input DTL NAND gate. R3, R4 and V- shift the positive output voltage of the input DL stage below the ground (to cut off the transistor at low input voltage).





The DTL circuit shown in the picture consists of three stages: an input diode logic stage (D1, D2 and R1), an intermediate level shifting stage (R3, R4 and V-) and an output common-emitter switching-transistor stage (Q1 and R2). The two resistors R3 and R4 form a resistive summing circuit with weighted inputs that adds the negative bias voltage V- to the positive diode logic output voltage. As a result, the unipolar (positive) diode output voltage (about V+ for logical one and 1.0 V for logical zero) is converted into a bipolar voltage (a few volts above and below ground) to drive the output transistor.
The IBM 1401 (announced in 19591) used DTL circuits similar to the simplified circuit, but avoided the level shifting stage (R3, R4, and V-) by alternating NPN and PNP based gates operating on different power supply voltages. The 1401 used germanium transistors and diodes in its basic gates[2].  - The 1401 also added an inductor in series with R2[2][3].
In an integrated circuit version of the DTL gate, two series connected level shifting diodes replace R3. Also the bottom of R4 is connected to ground to provide bias current for the diodes and a discharge path for the transistor base. The resulting integrated circuit runs off a single power supply voltage.[4][5][6]