How are the bitflip and row hammering effects taken care of by micro controllers in critical systems?
Most MCU manufacturers have a line of &quot;safety MCUs&quot; nowadays, with built-in hardware ECC (&quot;error correction code&quot;). Not so much used for actual error correction, but to stop in a safe manner when RAM corruption happens.
The most prominent feature of &quot;safety MCUs&quot; is otherwise that they execute the code on two cores in &quot;lock-step&quot;. There's various levels of more or less intricate error checking of hardware peripherals too.
One example is MPC56/SPC56 from NXP/ST. Similar safety MCUs should be available from Renesas, Infineon and others. Pretty much all modern cars use some flavour of safety MCU.