How can you design a frequency divider circuit?
Assuming a maximum frequency of ~4GHz you could cascade three of these x4 ECL divider chips (SY10100EP33V), by a total 4x4x4=64 division ratio. They are not programmable, so they are simple to use, just like flip-flops. Enough to bring the frequency to a more manageable ~63MHz. 

Further division can then be achieved using a plain binary counter of a common logic family, like the 74HC4060 which can work safely up to ~80MHz if powered at 5V. It has an internal 14-stage counter, so it can divide by a maximum factor of 2^14=~16,000, enough to perform the division to any lower frequency you would want.

Of course you might have to design a proper interfacing circuit between those ECL chips and the HC counter: the logic levels might not be compatible by direct connection, study the datasheets carefully. Anyway the "4060" counter is a fairly common part also in other CMOS families (AC,LV, etc.), so you can search analogous parts (e.g.: 74LVC4060, 74AC4060, etc.) and see if their logic levels are better suited for direct connection with ECL outputs.