What is the exact order of execution to access SRAM using a multplexers?
You are definitely "in over your head" with this project. An answer that is detailed enough to get you going would be far too long for the Q&amp;A format we use here.

Using a pair of SRAMs as a double-frame video buffer is a decent idea, but you'd have to run them "flat out" to produce a 1280&times;720 (1 Mpixel) display. In terms of capacity, you'll only have 4 bits per pixel &mdash; 16 colors, like the RGBI scheme used in the original CGA. And in terms of the bandwidth required to read out the data, you'll have to run them at their full speed of 18 MHz (55 ns per cycle). 36 Mpix/sec is just barely enough to produce a 720i (interlaced) image at 30 fps.

A shift register to generate the addresses is definitely a non-starter. The serial data rate required would be insane. You'll need 5 packages of quad 2:1 multiplexers for the address bus, and four packages of octal bidirectional data buffers to steer the data to the right places. In addition, you'll need logic (counters, etc.) to generate the display timing.

It's definitely doable &mdash; any computer geek as old as I am has probably built a display controller pretty much like this. But you need to get a lot more experience with digital logic in general before you can tackle it.