Parameterized net width in Verilog
You want to match the right hand side width with the declaration width to avoid tool warnings? 

First use a 1-bit wide zero constant, this will be expanded using the Verilog expansion rules, which will give you an appropriate width zero:

wire [width-1:0] a_net = 1'b0;


If that generates a simulator/synthesiser warning your tools are outside of the Verilog spec. A common way to get around this is with the replication operator, which can take a constant width:

wire [width-1:0] a_net = {width{1'b0}};