How can I generate a circuit image from VHDL?
What you're asking for is a two-step process:


Convert HDL to a netlist (a logical description of connectivity)
Convert a netlist into a diagram.


HDL (whether that's Verilog or VHDL) to netlist can only be done by a synthesis tool. While there are a few "free" synthesis tools, mostly for specialized applications, most are tied to specific technology vendors.

While converting a schematic to a netlist is fairly straightforward (most any schematic-capture software can produce netlists in a number of formats), converting a netlist into a usable diagram is a hard problem, and I have yet to see a tool, free or otherwise, that does a decent job.

And in the end, such automatically-generated diagrams are rarely useful for any real work anyway.