Serializing 4 channels to 1
The number of bits per second has to be the same both in and out of the MUX; the difference is that there are more simultaneous bits, and therefore a slower sample rate, on one side. So your MUX takes in 4 bits per 0.4 ns and outputs 1 bit per 0.1 ns. Your question may involve something else but is unclear. &quot;How to drive&quot; seems obvious: drive 4 bits and hold them constant every 0.4 ns. Make sure everything is in phase; use matched trace lengths and serpentining if needed.

Yes, this is serialization. You are converting 4-bit parallel data to serial data.

Most likely. Your transmitter is using its FIR filter to bandwidth limit the signal, i.e. it's not trying to drive out 0.01 ns or so edge times, which would require a lot more bandwidth than the wiring will give you. So the receiver needs some way to detect and equalize the signal, recover the clock, and sample it. That requires at least a PLL, probably more.

That's a tough question, because it depends on the bandwidth your signal is actually using. You only need about 2 samples per bit to receive the signal if using digital equalization, and 1 sample per bit if equalization is done before detection, but this isn't nearly enough to get a good eye diagram. The rule I've heard from scope vendors (note: not the most disinterested of sources) is that you need enough bandwidth to see the 5th harmonic of your transmitted signal (25 GHz in your case) and the sample rate needs to be at least twice that per Nyqiust, though more samples won't hurt. so 5 samples per bit or 10 samples per cycle.


Details

I was thinking how to feed a signal, which comes out through a single channel of an NRZ signal generator, into each of the 4 channels of the MUX so that 10Gbps is divided by 4 channels equally?

So you have a 10 Gbps signal coming out of an NRZ generator? Then it's 1 bit per 0.1 ns already and you don't need a MUX at all. If you have to have use that MUX, then you need to demultiplex (DEMUX). This is simply a 4-bit shift register feeding a 4-bit D-register plus a 2-bit counter.
Your NRZI out goes to the shift register data in, and the NRZI clock goes to the shift register, D register, and counter clocks. The 4-bit parallel output of the shift register goes to the D flip-flop inputs, and the counter value is compared to a constant (usually 0 or 3) and this comparison goes to the D flip-flop clock enable. The D flip flop outputs are your DEMUX out and can go to your MUX.

The reverse would also occur in the receiver end which has a 1:4 MUX.

Normally, it doesn't. Why deserialize only to reserialize?

I wanted to know how to do this kind of mechanism so that something can be done for rest of the MUX which are say 2:1 etc.

Number of bits in the shift register is the number of MUXed bits.

Yes, the transmitter has a FIR filter. If you could kindly illustrate how to connect a PLL.

Not sure why you'd want to. The PLL would be on the receiver. For how to do this, consult a communications text. It's more than I can really cover here.