VHDL: A function to determine array length
SOLUTION: I found the solution to my problem in this another question: https://stackoverflow.com/questions/20072851/how-to-use-a-constant-calculated-from-generic-parameter-in-a-port-declaration-in

So, applying the solution to my code, the "minimal.vhd" become :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use work.arrayout_type.all;

entity minimal is
  Port (
        a : in std_logic;
        b : out std_logic
         );
end minimal;

architecture Behavioral of minimal is
type array_intern is array (calc_adder_length(M)-1 downto 0) of std_logic_vector(M+N-1 downto 0);

begin


end Behavioral;


That is syntetizable.

Hope it can be usefull for someone, and thanks to the author of the solution in the linked question