Hard reset for SD Card interfaced with FPGA?
You will have to simulate your Verilog code or use analyzer to see things going on in live system.

In my opinion, there're only two circumstances when SD-card appears "hung":


bad specification implementation, when card does not understand what is going on, or is unable to understand that previous command must be cancelled. However card must anyway tell you something other than all 1 during execution of these commands - for example during multiple block read there's CRC transmitted, which will contain zeroes, during multiple block write host must transmit CRC otherwise card responses with error, which will also contain 0s. Your task here is to check set of SD-card commands your controller uses, and adjust initialization sequence (number of spare clock cycle before you proceed to CMD0) accordingly;
your FPGA state machine fails after you press reset. For example, clock stops working at the SD-card clock input pin, MOSI gets stuck etc. This is most suspect for hung cards, because SD-card will output nothing if clock does not toggle, or there's no activation of CS and no useful information on MOSI line.