Inverting REFCLOCK of Ethernet PHY
The answer is on page 29 of the LAN8720A datasheet: The REF_CLK Out Mode is not part of the RMII Specification. Timing in this mode is not compliant with the RMII specification. To ensure proper system operation, a timing analysis of the MAC and LAN8720 must be performed.

I would bet that NXP did that analysis and needed to invert the clock to achieve good timing margins. The propagation delay of the LVC inverter, and maybe even the RMII trace lengths, will have been part of that process.

The STM32F427 timing requirements and characteristics should be very similar to the LPC1769; RMII is RMII... But I would do a fresh analysis if I were you!