Two VHDL process statements reading the same signal and one modifying it
There are a number of nuances that come into play here.  


VHDL simulation is divided into a signal update phase and a run phase.  The signal update phase always finishes before the run phase starts.
Signal assignments get evaluated during a run phase, but never update until the next signal update phase.  If there is no delay placed on the signal, the signal will be scheduled to update on the next delta cycle (zero in wall clock time, but is there for ordering).  If there is an after with a time value greater than 0 ns, then the signal will be scheduled to update on the first execution of the simulation time = current time + after time value.


Hence, your reset signal will update one delta cycle after clock.  The "do work" portion of your process will see reset exactly one clock cycle after the clock cycle on which it was set.  The VHDL simulation model is rock solid stable, so there will not be any uncertainty about how this particular process runs (like suggested by @MaximGi).

In a hardware design, you have put a flip-flop on reset and then fed that signal to other pieces of your design.

From a synthesis portability perspective, I caution you against putting any other logic in the same if condition as the clock.  I would instead recommend re-writing your process as the following.  Note your process is correct for simulation, it is just that some of the synthesis tools are fussy.  

-- First process
process (clk)
begin
    if rising_edge(clk) then
      if reset= '1' then
        -- do work
      end if ; 
    end if;
end process;


Also there is no need for reset on this sensitivity list since rising_edge(Clk) will only be true on the exact delta cycle in which clock changes.  You only need reset on a sensitivity list when you use asynchronous reset.