How to remove error in below verilog statement while running for ise simulator?
Right, so what is happening is you have declared your module as this:

module s_three(m1,m2,m3,a,b,c,en,clka);                                              
input [7:0] a,b,c;                       
input en,clka;                            
output [7:0] m1,m2,m3;               
wire [7:0] m11,m12;


Now you might expect the ports to be connected in the order they appear in the brackets, but this is actually not so, they need to be connected in the order they are declared by the input ..., output ... lines, i.e. the implicit connection order for your module will actually be:

s_three call(a,b,c,en,clk,m1,m2,m3)


As a result you are connecting up your ports in a way you aren't expecting which can lead to funny errors. In this case outputs are connected to inputs, the register c is connected to an output (bad!), etc.



Implicit connection of ports is a debugging headache and while it saves a little bit of typing you really should avoid it for your own sanity when it comes to testing things. Also if you happened to want to add a new port, or change them around later on, anything that is implicitly connected would break.

To solve the problem, you should use explicit connections. For example the following explicitly connects the pins:

s_three call(.m1(m1),.m2(m2),.m3(m3),.a(a),.b(b),.c(c),.en(en),.clka(clk));   


The connections are described as: .portInModule(signalToConnect). By doing it this way it doesn't matter what order they appear. This would work just as well:

s_three call(.clka(clk),.en(en),.a(a),.b(b),.c(c),.m1(m1),.m2(m2),.m3(m3));