Are FPGA Mezzanine Card (FMC) interfaces supposed to be compatible across different FPGA boards?
TL;DR If your FPGA board, and your mezzanine card both conform to VITA 57.1, and both use the same connector pin count (HPC or LPC) then yes, it should work.



An FMC connector is just an off the shelf Samtec SEARAY™ (SEAF/SEAM) connector. Just seeing the connector gives no guarantee of any form of intercompatibility. While it would be very unhelpful if different manufacturers used different pinouts, if history tells us anything, one or more will find a way to end up with incompatibilities.

This is where standardisation enters in. VITA 57.1 is one of a few different standardised pinout and mechanical specifications around for multi-signal high speed interconnects. 

The VITA 57.1 standard makes use of the FMC connector style and defines both the mechanical aspects (options for stack height, hole positions, card sizes) and the electrical aspects (pinout, supply pins, IO voltage levels, clock pins, data lines) for an interconnect between a base board and a mezzanine card. It actually defines two different pinouts, the LPC (low-pin-count) and HPC (high-pin-count) variants, one which provides more data lines than the other.

If both your mezzanine card, and your FPGA base board are specified to conform to VITA 57.1, both are the same pin count (both LPC or both HPC), and the base board allows for the correct stack height for the mezzanine card, then they should be interoperable.

There are however some cases where the baseboard, say not having enough FPGA IO pins, may not completely conform - it could for example have the odd few IO pins running at a different voltage, or it may be missing some data lines if unavailable. In this case the intention would be that the differences cause no damage to either board (e.g. power pins are correct), but things may not work as designed.

It is always a good idea to check that the pinout for card you intend to buy, and the baseboard you intend to use are suitably compatible. You would need to do this check anyway for an FPGA to be able to work out pin assignments for your design.