jtag boundary scan pin testing
You're correct, and this is LSB first.
TL;DR

You shift IR Sample/Preload, then shift DR to N bits of boundary scan register. This initializes the future pin state.
As soon as you set IR to Extest (go through Update-IR, actually), pins will be controlled by boundary scan register values (output value, tri-states), values you've set at previous step.
As long as IR stays Extest, you can go through Capture-DR, Shift-DR and Update-DR as many times as needed (without touching IR at all). Each time you go through Capture-DR, boundary cell state will be copied to boundary scan register, ready to be shifted out, each time you go through Update-DR, boundary scan register will be committed to boundary cells (i.e. pins). All you have to do is issue a N-bit DR shift between Capture-DR and Update-DR to simultaneously extract current pin state, and inject future pin state.
When you're done with Extest, set IR back to Bypass (for instance), and pin control will be back as normal.

Actually, Sample/Preload and Extest have the exact same effect on the the boundary scan and boundary cell behavior. The only difference between the two is when IR is Extest, pin control is from boundary cells, not from internal logic.
In JTAG, all registers are shifted in (and out) LSB first.