Unsigned addition overflow and synthesis
Synthesis will give you a truncated but otherwise accurate result, assuming all regs/wires mentioned are unsigned (i.e. not declared with reg signed). The map tooling will probably warn about a 'carry' line having 'no load', if you can find it in the logs. You might be able to suppress the warning with an explicit bit select on the result or a mask:

a &lt;= (b + c) &amp; 0x7;