How to read/write from a CPU using a usbWiggler?
The Cortex M3 will almost always be implemented with a CoreSight DAP providing the eternal debug port. Simplistically, you use the JTAG to set control registers in the DAP, and the DAP performs memory mapped accesses into the SoC to implement your requests.

The IR values are documented in the CoreSight Component TRM. This is effectively the first level of addressing. DP accesses allow you to set the AP select register. AP accesses allow you to set the transfer address register, and perform reads and writes.

Bear in mind that for a read, you need to request the read, then issue another transaction to retrieve the result - the on-chip accesses are asynchronous to the JTAG transaction. You would then see APACC-address, APACC-read, APACC-result for a single 32 bit memory transaction.

At the API level, you might want to add a level of abstraction. Switching between the CoreSight APACC and DPACC requires shifting a 6 bit string into the instruction register, but once the DP registers are initialised, most transactions only need to use the APACC instruction register state with a 35 bit payload.

Your stream of APACC transactions will use data bits [1:0] as an address to the AP registers, bit2 as read/write, and [35:3] as the payload.

One of the DPACC transactions (selected by the first 2 DR bit values as an address) is a static ID register, you should make sure this doing what you expect before trying to do anything more complex.

This overview white paper has a slightly more verbose description of the debug connections (from page 8).

DP    //Debug port (JTAG or Serial wire, external interface)   
AP    //Access Port (APB in this case, on-chip bus master)   
DPACC //JTAG state, transactions are handled by the DP (r/w with 2 bit address)   
APACC //JTAG state, transactions are handled by the AP (r/w with 2 bit address)