Subtracter with VHDL
You have &quot;used&quot; two incompatible definitions of &quot;signed&quot;. That means,
neither of them is visible. Get rid of std_logic_arith and the
&quot;conv_signed&quot; function calls from it. Declare your ports and signals
signed not std_logic_vector as far as the assignment permits, to
eliminate useless type conversions.

-Brian Drummond