Does cache access time scale down with frequency in modern CPUs?
It was in old days (mid-90') when every CPU block did scale with frequency. With modern processors it is not true anymore. The CPU core and caches have different design topologies, and memories usually do not scale much. The timing alignment between CPU core clock and caches is usually done by re-configuring the pipeline access to cache, so it is very likely that the cacheline access time doesn't scale with core frequency at all. I recall running into similar issues while working on K6 processors, when for every clock multiplier the cache access must be re-configured.

With modern CPUs and adaptive core frequency the things are much-much more complicated. CPUs are designed by thousands of design engineers and architected by hundreds of architects, so to get into details you need top clearance access to top secret documentation, and even then it will be difficult to find the exact answer.