What are Soft, Firm and Hard IP Cores?
At least from an FPGA standpoint, hard IP refers to features built into the silicon of the FPGA itself. These can range from mixed signal components such as clock management components, PLLs, and high speed serializers and deserializers to fully digital components such as CPU cores, memory controllers, Ethernet MACs, and PCI express cores. Hard cores have the advantage of ASIC level performance at the expense of reconfigurability. Soft IP is distributed as encrypted or unencrypted HDL or as a netlist and ends up being implemented in normal FPGA logic. 

Firm IP is not a term that I am familiar with, unfortunately. It's possible that this refers to IP cores distributed as placed and routed geometry for implementation on an ASIC.