Xilinx bit file different between builds
There is an option to randomize the build process, which IIRC is enabled by default.

As FPGA layout is an optimization problem with high complexity, it is not possible to find the globally optimal layout in a sensible time frame. The compiler instead starts with a random but correct layout, and performs local optimizations on it, until no further optimizations are possible, then checks if the layout satisfies timing requirements.

If the FPGA is close to getting full, this randomization is often the difference between passing and failing timing, so restarting compilation after a failure may give you a working result. Without the randomization, failing timings would reproducibly fail in the next iteration as well.

For production, I'd do ten to twenty different builds, pick three with the best timing margins and actually test them on real hardware at different temperatures (typically, 0° and 55°).