How do some SAR ADCs allow the input range to be 0 to 2xVref?
For 2's complement or unsigned SAR conversions always use the "remainder voltage" /2 to decimate then next bit. 
So I believe using Vref/2 as the comparator level for SAR conversion is normal and the input full-scale is 0 to Vref.  i.e.


MSBit conversion 0 means &lt; Vref/2 and 1 means >= Vref/2 


In this chip Vref = 2.5V and the logic supports 3V and 5V supplies however if the the user sets 1 bit in a register to indicate 2xVref is going to be used i.e. 0~5V analog in, then the logic supply MUST BE 5V.  This feature prevents the comparator from having to do level shifting down and prevents over-voltage to the logic side where the analog comparator drives the logic in successive approximation register ( SAR )steps. So the analog input range comparator input must not exceed the logic supply.