how to pass parameter variable to module in verilog
Parameters are defined at synthesis time, you can't change them at run time based on signals.  With that in mind, there are basically two options: either convert that parameter to a signal, or instantiate multiple copies of the module with different (constant) parameters, and then appropriately select which one to use.  

Here is an example of doing that: https://github.com/alexforencich/verilog-ethernet/blob/14d8819cd31f569e18bd8574c9a8417d130472ca/rtl/eth_mac_10g_tx.v#L128, with the appropriate output selected here: https://github.com/alexforencich/verilog-ethernet/blob/14d8819cd31f569e18bd8574c9a8417d130472ca/rtl/eth_mac_10g_tx.v#L296.  

There are advantages and disadvantages to each technique - converting a parameter to a signal may not be possible depending on how it is used, or it may result in generating a lot of additional logic.  Multiple module instances can also result in a lot of logic, but perhaps less than converting a parameter to a signal, not to mention the toolchain can usually optimize redundant logic across multiple instances that have the same inputs.  Or, you could write a more specialized module that is more specific to what you're trying to do.