VHDL: is there a way to create an entity into which constants can be passed?
Add a generic clause to your entity. It allows you to pass in e.g. constants:

entity counterTst is
  generic (
    constant COUNTER_LEN : integer -- := 4
  );
  port (
    enable: in  STD_LOGIC;
    clk:    in  STD_LOGIC;
    rst:    in  STD_LOGIC;
    output: out STD_LOGIC_VECTOR(COUNTER_LEN - 1 downto 0)
  );
end counterTst;


architecture rtl of counterTst is

  -- constant COUNTER_LEN:   integer := 4;


Moreover generic values can be used in you port clause to size ports. A generic can have a default value, thus the user doesn't need to apply it in a generic map. In you case, you shouldn't apply a default value to force the user to think about his choice :).

And here is the usage:

cnt : entity work.counterTst
  generic map (
    COUNTER_LEN =&gt; 4
  )
  port map (
    -- ...
  );


Like in a port map, you map generics in a generic map.