How to solve routing issues in Artix7?
It's recommened to use clock capable pins (CC Pins) for clock inputs. These can be routed to BUFGs.

But the error it in another part of your code. As you wrote you are using

if rising_edge(input) then


You cannot use rising_edge on none clock nets, this promotes them to a clock net, which input isn't.

The correct way is to synchronize the input with 2 D-FF and add an edge detection after that (3rd D-FF, not-gate, and-gate). All FF are driven by your system clock.

input_meta &lt;= input      when rising_edge(Clock);  -- 1st synchronizer D-FF
input_sync &lt;= input_meta when rising_edge(Clock);  -- 2nd synchronizer D-FF
input_d    &lt;= input_sync when rising_edge(Clock);  -- edge detection D-FF (d = delayed)
input_re   &lt;= not input_d and input_sync;          -- edge detection equation (re = rising edge)

process(Clock)
begin
  if rising_edge(Clock) then
    if (input_re = '1') then
      -- do something
    end if;
  end if;
end process;