MSP430 UCS - FLL/DCO Source
Setting UCS_DCOCLK_SELECT as "clock source for FLL" is possible only because the API is constructed this way (poorly one may say, but I've seen worse). This is not valid, and not possible in hardware. For some reason (space, simplicity?) TI wanted to make one function to set sources for all 3 clock signals (i.e. ACLK, MCLK and SMCLK) AND for FLL which is somewhat different from those three. 

On UCS diagram in user's guide you would find that FLL and DCO are in fact one big module (surrounded by a box labeled "FLL"). You can source input signal to FLL only from XT1CLK, XT2CLK or REFOCLK and as an output you get DCOCLK and DCOCLKDIV which can be passed further as a source to the ACLK and/or MCLK and/or SMCLK.

Refer to the diagram I mentioned and maybe try to color the wires (I did this and it helped :).