Shift Register Vs Multiplexer
Here are some thoughts on hardware coasts:

8 bit shift register on virtex-5, spartan-6
A slices contains 4 LUTs and 4 registers. You'll need 2 slices to store 8 bits.

8 bit shift register on virtex-6, 7-series
A slice contains 4 LUTS and 8 registers. You can store the complete byte in one slice.

3 bit counter
Small counters are implemented using LUTs and registers. This counter fits into one slice

8to1 multiplexer
A 6-input LUT architecture can map 4to1 muxes into one LUT. A 8to1 mux requires two 4to1 muxes and one 2to1 mux (mux-tree). Xilinx FPGA slice cells contain additional F7MUX and F8MUX primitives which can be used to build wider muxes. In case of 8 bits: 2 LUTs and one F7MUX. All in all: A half of a slice.

Note 1:

If you are using a shift-register, you also need to know when to stop shifting, if it's not a pipeline.