What's the difference between switching speed and gate delay for a transistor?
Clock speeds for logic have to satisfy the full logic margin of the design.  The logic output load will be a small-integer number of other logic gates' inputs.  Switching times for transistors are commonly measured by making a ring oscillator, and measuring the oscillation frequency.   

Ring-oscillator oscillation frequency is not the
worst-case over temperature and power variations, does not necessarily mean that the transistors have made a full logic-level excursion, and implies the power gain of the transistor is almost exactly '1', which is inadequate for a gate
that has to drive multiple other gates (instead of one subsequent transistor
in the ring oscillator).

The speed difference you see in the literature relates to the difference in
test methods.