How are interrupt handlers implemented in CMSIS of Cortex M0?
The following information is in addition to Igor's excellent answer.

From a C programming perspective, the interrupt handlers are defined in the cr_startup_xxx.c file (eg cr_startup_lpc13.c file for LPC1343).  All possible interrupt handlers are defined there as a WEAK alias.  If you do not define your own XXX_Handler() for an interrupt source, then the default interrupt handler function defined in this file will be used.  The linker will sort out which function to include in the final binary along with the interrupt vector table from cr_startup_xxx.c

Example of GPIO interrupts from ports are shown in the demo files in gpio.c.  There is one interrupt input to the NVIC per GPIO port.  Each individual bit in the port can be enabled/disabled to generate an interrupt on that port.  If you require interrupts on ports PIO1_4, and PIO1_5 for example, then you would enable the individual PIO1_4 and PIO1_5 interrupt bits in GPIO0IE.  When your PIOINT0_Handler() interrupt handler function fires, it's up to you to determine which of PIO1_4 or PIO1_5 (or both) interrupts are pending by reading the GPIO0RIS register and handling the interrupt appropriately.