Why is data delayed by 1 clk cycle in AHB write transfer?
What will happen if the HWDATA is put on the bus at the same time as
  the address and control signals and kept there?


I've added four labels to your diagram.


  Is it true that the address, control signals, and the HWDATA must be
  kept on bus for only 1 clk cycle and then be reset to zeros?


They are "Don't care" labels: -




  The HWDATA comes 1 clk cycle after the control signals and the
  address. Why is this so?


Possibly because the address needs to be set up one HCLK cycle earlier and clocked in on the falling edge of HCLK with the next falling edge being reserved for data. It's just the way it is without trying to examine the actual circuit.