What is the difference between DCM and PLL in e.g. Xilinx FPGA?
Xilinx use the term DCM for their enhancement to what they used to call a DLL, or Delay Locked Loop.

This (DLL) was a tapped delay line fed from the original clock signal, by selecting different taps, you could get different delays on the output clock signal. As the delays are unpredictable, logic compared the outputs from different taps until it found which tap number gave a full clock cycle delay - it was "unlocked" until it found the right tap. Then it updated that tap number as the delays drifted (e.g. as the input frequency changed or the chip warmed up) then other delays (e.g. 90 degrees, 180 degrees, were computed from that.

So it provided vaguely PLL-like behaviour without any analog circuitry, which was difficult to achieve in their processes at the time. Downside was that the jitter spectrum was different from a PLL as the delay was always an integral number of taps. 

If you cascaded DLLs or DCMs, the second one will probably work, but a third one may have dificulty locking up due to the jitter imposed by the others.

The DCM is based on the same idea but provides other functionality such as clock frequency multiplication.

Newer FPGAs offer both DCM (DLL) and PLL but I expect the DCM is still easier to produce.