VHDL code works well in ModelSim and strange behavior in Altera FPGA
There are several problems in your code:

1)
PRESENT_STATE is not in the sensitivity list of process listen. It should be, otherwise the simulation gives you other results as in hardware.

2)
SGN_IN is not an input of your FSM. There is no transition that depends on this signal. Listing signals in the sensitivity list does not promote them to inputs. This list is just for simulators and ignored by synthesis tools.

3)
Because you are using SGN_IN in the sensitivity list it seams to work correctly in simulation, but this is just the luck of 2 errors resulting in the correct simulation result :). Your FSM would also transition if SGN_IN is changed to X or L, because the signal changed, but I assume you want to check for 1-0/0-1 transitions, am I right?

listen: process(PRESENT_STATE, SGN_IN) is
begin
  NEXT_STATE &lt;= PRESENT_STATE;
  Y          &lt;= '0';

  case PRESENT_STATE is
    when ST0 =&gt;
      if (SGN_IN = '1') then
        NEXT_STATE &lt;= ST1;
      end if;
    when ST1 =&gt;
      Y &lt;= '1'; 
      if (SGN_IN = '0') then
        NEXT_STATE &lt;= ST0;
      end if;
  end case;
end process listen;