When does the reset on a 74HC164 Shift Register occur?
Synchronous timings are associated with a clock and in general asynchronous timings are not. (This can get confusing in terms of asynchronous events that are then aligned to a clock but that is not the case here).

Looking at the timing diagram:



You can see that the firstclear event ensures the outputs are all low aligned with the falling edge of \$ \overline {CLR}\$.

Had this been a synchronous clear, then at the second event the outputs would have been taken low aligned with the clock (the blue line), but they are taken low (as before) when aligned with the falling edge of \$ \overline {CLR}\$

So the outputs will go low in response to the falling edge of clear and the clock has no effect on this.