What are some things that can be done in VHDL but not in verilog and vice versa?
VHDL borrows from Ada, and its strongly typed compared to Verilog.  Simple things are easier to do in Verilog, but complex things are easier to do in VHDL.  Both can get the job done.  Verilog does let you use the C preprocessor which is nice sometimes compared to generics.  

Nothing is impossible in either.