Possible test patterns produced by ATPG Software like Tetramax
ATPG generation is a very complex subject. We had a dedicated Design-For-Test* engineer full time handling the testing (and Tetramax). Wat I know about testing is mainly from glimpses over his shoulder.

What I saw was that ATPG patterns are often not externally made but internally using PRBS logic. You can bypass the PRBS and run your own vectors for detailed failure analysis.
Possible the patterns you have are used to control the test logic including the PRBS blocks. 

Also in test mode the registers are converted into scan chains where the order is based on vicinity of other registers. Without knowledge about every logic gate in the design you are unlikely to understand what the test pattern files do. 

Lastly:Generating the actual test pattern is the least problem. Most of the work is to find the best test coverage with the shortest pattern. You need to do a full circuit analysis with the test-vectors, for which you need to know about every gate in the design. To make a generic test pattern generator you are more likely going to need C or C++, access to the design library and a few hundred man years. 

If there is a DFT engineer he may be able to answer your question about 'standards' for test vector formats. 

*Never call a Design-For-Test engineer a "test engineer". For some reason they find that very insulting.