Velilog HDL(Logic cricuit)
I'm not sure where you're going with all of that Verilog code, but your diagram basically boils down to the following statements:

wire [7:0] mask = 8'b01110001;
reg [7:0] LFSR_Reg;

always @(posedge Clock)
  LFSR_Reg &lt;= Reset ? 8'b10000000 : {^(LFSR_Reg &amp; mask), LFSR_Reg[7:1]};


Use the power of the language to avoid unnecessary work!