How to control AXI DMA and/or BRAM cores in a ZYNQ
Your whole set-up does not make sense to me.

In cases like this follow KISS: Keep It Simple and Stupid.

Make a dual ported block ram memory which has an AXI interface on one port. This lets the CPU write (en possible read) your memory.

Tie the other block ram's port read signal active (always read) and put a counter on the second address bus.
Connect the DOUT of the memory to your DAC data input.
You now have the core of a function generator.

Ideally you should make the counter run at different (programmable) speeds to get different frequencies. You should also set a start and end value so it loops between specified addresses. But all that can be postponed until after you got the core running.