4-bit Finite State Machine with 6 states and synchronous reset using D Flip-Flops
Based on your state diagram and explanation, you have everything you need there.

For every register (you have 4), you need to create a Karnaugh Map which determines what value will be clocked onto that register in each clock cycle.

The next value for each state register will depend on the current state as a whole (i.e. all state registers), and any other inputs (in your case only reset). So build your Karnaugh Map using those inputs.

Each of your states has a 4-bit value (e.g. your starting state is 1101). So you will need 4 registers to hold the value indicating current state. So for example lets call your state registers \$\left(S_3, S_2, S_1, S_0\right)\$, where the starting state would be say \$S_3=1\$, \$S_2=1\$,  \$S_1=0\$, and \$S_0=1\$. Also lets call the reset signal \$R\$. 

You will have maps which look something like:

$$
\begin{array}{c c c| cc}
S_0 &amp;     &amp; R   &amp; 0 &amp; 0 &amp; 0 &amp; 0 &amp; 1 &amp; 1 &amp; 1 &amp; 1\\
    &amp;     &amp; S_3 &amp; 0 &amp; 0 &amp; 1 &amp; 1 &amp; 1 &amp; 1 &amp; 0 &amp; 0\\
    &amp;     &amp; S_2 &amp; 0 &amp; 1 &amp; 1 &amp; 0 &amp; 0 &amp; 1 &amp; 1 &amp; 0\\
S_0 &amp; S_1 &amp;  \\
\hline
0   &amp;   0 &amp;     &amp;   &amp;   &amp;   &amp;   &amp; 1 &amp; 1 &amp; 1 &amp; 1\\
0   &amp;   1 &amp;     &amp; 1 &amp;   &amp;   &amp;   &amp; 1 &amp; 1 &amp; 1 &amp; 1 \\
1   &amp;   1 &amp;     &amp; 0 &amp; 1 &amp;   &amp; 1 &amp; 1 &amp; 1 &amp; 1 &amp; 1 \\
1   &amp;   0 &amp;     &amp;   &amp; 1 &amp; 1 &amp;   &amp; 1 &amp; 1 &amp; 1 &amp; 1 \\
\end{array}
$$

I've been exceedingly nice and filled in the map for \$S_0\$ for you based on your next state table. I'll let you make and fill in the other three maps.

Once you have your four maps you know the logic for each of the state registers.