What mathematical function do I2C falling edges follow, and why?
At the falling edge of an I2C line the trace capacitance is discharged through the low side FET. The FET has a constant gate-source voltage.
This results in the current first beeing almost constant and leveling down to a constant resistance discharge, when the line voltage (which is \$V_{DS}\$) drops below \$V_{GS}-V_{th} \$.
So in the constant current discharge segment the voltage falls linearily and then levels off to the typical RC discharge curve.
But in reality you will have difficulties seeing such a voltage waveform, because the discharge happens almost instantly. Assume a trace capacitance \$C_t\$ of 5 pF. With an \$R_{DS}\$ of \$1~\Omega\$ the RC constant is in the order of 5ps. With lower \$R_{DS}\$ it obviously is even faster.
If you want to be even more precise you might want to add the effect of the pullup resistor, which will still be present. This will result in a minor DC offset.