Are there ways/technologies to use High negative voltages in flash memories?
The basic answer is yes. This is an intrinsic problem of IC design, your substrate has to be biased in a way that reverse-biases all parasitic PN junctions in the circuit. For most processes you have a P-substrate which means that the substrate has to be at the lowest potential in the circuit (generally -Vss). For a flash memory, where you also want a high density of elements, this limitation remains. 

However:


In modern processes, where oxide thickness is just a few atoms, you can get tunneling going with less than 6V across a gate.
There are processes (e.g., trench-isolated) in which you can have isolated islands of substrate that can tolerate voltages in some cases in excess of ±300V.
High-voltage options on some processes can tolerate N-wells and P-wells at voltages in excess of 30V above the substrate.


With those considerations, you could segment your flash memory into trench-isolated sections, and drive those sections to a high enough voltage to tolerate positive and negative excursions.

But in most cases you might be better off by using injection processes (high-energy electron scattering at a junction edge) to place the electrons in the floating gate, not just a potential difference to drive them through tunneling.