VHDL: Kan sequence of if/else be optimized?
No need. 

Write sequential code - and synth will unroll it all to execute in parallel anyway (but preserving the same semantics as your sequential version). 

Some more detail here: https://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant/13956532#13956532

What you are defining with your sequential code is the semantics not the implementation. 

That is : focus on the semantics of the problem - the highest level abstraction that accurately encapsulates your meaning. That's difficult enough to get right as the question demonstrates!
In that context, functions and procedures are good practice, raising the level of abstraction.

Now consider what happens to something even more sequential like a FOR loop in a process. Synthesis will unroll it so that each loop iteration runs in parallel anyway. Same happens here. 

For completeness, in VHDL-2008, conditional and case expressions (when/else and with/select) are available within processes, so a shorter expression of your example is possible:

return (2 when val &lt; 0 else 1 when val &gt; 0 else 0); -- vhdl-2008 syntax 


but the implementation will likely be identical.

As would a CASE statement based implementation of the identical algorithm (at least, where the expressions are mutually exclusive as here. An IF statement prioritises when expressions overlap : that would be a compile error in a CASE).

Both the implementation and the speed are likely to be identical. It's a different expression of exactly the same algorithm, and synth tools are brutal at reorganising and optimising; brutally honest in preserving semantics accurately, and brutally ruthless in exploiting mistakes to optimise away redundant hardware ( cough return 2;) 

Which boils down to : TEST it first in simulation; THEN synthesise.

Given big enough, complex enough examples, unrolling a whole sequential algorithm and attempting to execute it in a single clock cycle is undesirable and consumes too much FPGA. But that's a story for another day; learn about pipelining and state machines before tackling that.