How do you select pin functions on an EPM7128 CPLD?
The functionality of the pins is inferred from your code, rather than set directly.
The pin names are telling you what that pin could be connected to internally within the FPGA.

 

The above diagram shows what INPUT/OE2/GLCK could be connected to. Note that while it looks like it's connected to everything at once, that is not the case.

To connect to the GCLK2 network you need to infer a clock by using the signal from that pin to drive the clock input of a register. Don't forget your timing constraints for this.
To connect to the OE2 network use the signal to control the output enable on an IO block by either instantiating an IOB megafunction or writing the right code pattern to infer an IOB.
To connect to the general purpose interconnect just feed to a logic block as normal.

For fun you could connect to all three and watch the synthesis tools have a fit as they try to decide what it is you want to do.