Draw the maginitude as function of frequency
This is where I am confused


You are not the only one. First off you haven't defined U1, Uc1 and Uc2. I presume they are the input signal voltage. signal voltage at T1 Collector, and signal voltage at T2 Collector.

Your formula assumes that both stages have the same input impedance and same current gain, even though the bias currents are different. This could be true if the transistors had just the right different characteristics, but for the general case when they don't the formula would be clearer if the two stage gains were grouped separately, like this:-

$$ \frac {Uc2}{U1} = \frac{\beta1 * Rc1}{Rbe1} * \frac{\beta2 * Rc2}{Rbe2}$$   

However this formula is not complete, because it ignores the loading effect that the  second stage has on the output of the first stage. Assuming that C2's impedance is negligible, Rbe2 is effectively in parallel with Rc1, so the actual gain of the first stage (when driving the second stage) is:-

$$ \frac {Uc1}{U1} = \frac{\beta1 * (Rc1 || Rbe2)}{Rbe1}$$ where || is the parallel operator.

(Even this isn't quite correct, but Rb2 is high enough compared to Rbe2 that it can be ignored)


  This is the result but I just don't know how it came to be like that


Your graph looks like a crude attempt to plot the frequency response of each stage. I'm guessing your question is why does the amplitude drop at low and high frequencies? 

At the low frequency end the signal amplitude reduces because capacitive reactance \$ Xc = \frac{1}{2\pi fc}\$, so as frequency reduces more signal voltage is dropped across C1 and C2, creating high pass RC filters. This starts to have significant effect at the 'cutoff' or 'corner' frequency \$\frac{1}{2\pi RC}\$, below which the level drops off at a rate of -20 dB per decade. 

For the first stage this frequency is easily calculated using the values of C1 and Rbe1. 1 / (2&pi; * 80 nF * 2k) = ~995 Hz. For the second stage we must also take into account Rc1. Again the effective resistance here is Rc1 || Rbe2. 4k &ohm; || 2k &ohm; = ~1.33k &ohm;. 1 / (2&pi; * 3.3 uF * 1.33k &ohm;) = ~36 Hz.   

Since the first stage's 'pole' has a much higher frequency than the second stage, this will dominate the loss at low frequencies and Uc2 will roll off at ~20 dB per decade. 

At the high frequency end the internal parasitic capacitances of the transistors, in combination with the resistances, form low pass RC filters. Each stage produces one pole, but the second stage has no load capacitance so its cutoff frequency will be higher and the first stage will dominate, making the level drop off at ~20 dB per decade at high frequencies too. 

Since we don't have values for the parasitic capacitances we cannot calculate the upper corner frequency. To get some idea of what to expect I simulated your circuit in LTspice using 2N3904 transistors. Here is the result:-