SPI slave unreliable on PIC18LF2550
As Sphero Pefhany notes, the list of silicon errata for the PIC18F2455/2550/4455/4550 family is extensive. In particular, erratum 37 (applicable to three revisions, including my revision B5 chips) reads


  If configured in SPI Slave mode, the MSSP may not successfully
  recognize data packets generated by an external master processor. This
  applies to all SPI Slave modes (CKE/CKP = 1 or 0), whether or not
  slave select is enabled (SSPM&lt;3:0> = 010x). 
  
  Work around: Insert a
  series resistor between the SPI master Serial Data Out (SDO) and the
  corresponding SPI slave Serial Data In (SDI) input line of the
  microcontroller. The required value for the resistor varies with the
  application system’s characteristics and the process variations
  between the microcontrollers. Experimentation and thorough testing are
  encouraged.


I assume the purpose of this resistor is to slow down the data transition, to make sampling at the end of the clock period (more) reliable.

This bug has been fixed in the latest (B7) revision.