Connecting CMOS digital ICs that are powered from different power sources
A 100 mV difference in Vdd levels will not normally cause any problems. No current limiting resistor would be required. 

However, if it's possible for the upstream device to be powered up while the downstream device is not powered (for example during start-up or shut-down) and for the upstream device to produce a "1" output during this time, then you can get upredictable behavior. 

If you need to allow for this scenario, the best solution is to re-design to avoid it entirely (for example, use a tri-state buffer with the enable pin controlled by the power state of the downstream circuit). If that isn't an option, in many cases a 5 kohm or higher series resistance can minimize problems, but even then certain circuits could still misbehave.