How does JFET cascode amplifier reduce input capacitance?
Let's say I disregarded the upper JFET and applied a fixed DC bias of 10 volts to the lower JFET's drain as per this diagram: -



Although it isn't a voltage amplifier any more, can you see that that the miller capacitance (shown as a red capacitor above) no longer has much of an effect? It still acts as a regular capacitor but instead of being connected to a (drain) node that is swinging about with the amplified input signal, it connects to a DC node?

Can you also see that the circuit still functions as a pretty phenomenal amplifier of current in that the input signal voltage still causes a significant AC signal current to be taken from the 10 volt source? Now consider the upper transistor circuit: -



I've disregarded the lower transistor and replaced its circuit with a red resistor called \$\color{red}{\text{LOAD}}\$. Can you see that if \$\color{red}{\text{LOAD}}\$ varies, despite this variation, the voltage at the source of the JFET will remain fairly constant at + 10 volts. I've estimated 10 volts based on what I know about JFETs i.e. the gate will be 2 or 3 volts below the source for a typical bias arrangement.

This means that when the two circuits are joined, the drain of the lower JFET is biased with a fixed (and steady) DC voltage. The upshot is that the lower JFET's drain produces very little AC signal voltage. This means that miller capacitance effects are very small and just like the top diagram.

However, now the upper JFET turns the AC signal current produced by the lower JFET back into an AC voltage at its drain hence, we get regular voltage amplification. And, it should be noted that the upper JFET doesn't suffer from its own miller capacitance effects because, its gate has a capacitor to ground that ensures that AC signal variations are decoupled to ground.