How do I eliminate latches in FSM Verilog implementation?
What I see is the coding style where you have a registered and a combinatorial section. It is a good coding style but it also only works if you are 100% consistent in your code:
Everything you clock (state, counter, shift) must be in the clock section. and you must only use non-blocking "&lt;=" assignments.
All combinatorial code must be fully! encoded and you must only use blocking "=" assignments.Start by adding a next_shift and next_cnt and in the clocking section use

always @ (posedge clk)
   if (rst) 
   begin
      state &lt;= `RST_STATE;
      shift &lt;= `RST_SHIFT;
      cnt   &lt;= `RST_CNT;
   end
   else
   begin
      state &lt;= next_state;
      shift &lt;= next_shift;
      cnt   &lt;= next_cnt;
   end
 end


I am not going to re-code your whole combinatorial section (sorry) but there you use:

always @ ( * ) // easiest!
begin
    case (state)
        `RST_STATE: begin
            next_shift = x;
            next_ctr   = 0;
            next_state = `DONE;
        end
        `LSH1: begin
             if (shift[3]) begin
               next_shift = shift; // no change
               next_ctr   = cntr;  // no change
               next_state = `DONE; // 
             end
             else begin 
               next_shift = {shift[2:0], 1'b0};
               next_ctr   = cntr+1;  
               next_state = `LSH2;
             end
  etc...

end


As I said it is a good coding style because it can handle some nasty cases better but the other coding style (I just saw another answer appear) is much easier. 

Disclaimer: code not compiled there may be typos in there