What problems arise when a clock signal is connected to a nondedicated clock input pin on an FPGA?
The clock input pins have optimised routes to the clock distribution logic.
At worst this means lower delays compared to general purpose pins.
At best this means accurately constrained delays, that allow the clock PLLs to drive the clock nets with near zero skew from the clock input pins.
The tools generally don't forbid a design that uses GP pins as clock inputs, you may be forced for some reason to do that. However, your design will not be able to take advantage of all the optimisations that the dedicated pins can provide, so will probably be slower.