System verilog on Quartus synthesis issue
When you type

y=x|c;
x=a&amp;b;


it means that you want to calculate y = x|c, then you want to set x to a&amp;b.  Since this must be implemented with gates, the old value of x must be stored until the end of the clock cycle, hence the extra flip-flop.  If you rewrote this with nonblocking assignments, you would do:

y&lt;=x|c;
x&lt;=a&amp;b;


However, when you write

x=a&amp;b;
y=x|c;


it means calculate x, then calculate y with the new value of x.  If you wanted to implement this with nonblocking assignments, you would do:

x&lt;=a&amp;b;
y&lt;=(a&amp;b)|c;


You could also use an assign statement to set x earlier, or mix a blocking and a nonblocking assignment.  In this case, if the registered x value is never used, the flip flop will be deleted automatically by the optimizer.