A problem with counter
As mentioned in the comments, I'm not sure that input clamping current has much to do with this problem.

When setting the frequency by changing the RC timing capacitance with an analog switch without any kind of synchronization to the generated clock, you are probably generating some garbage on the clock during the transition from one frequency to another.

The 10K resistor along with the input capacitance on the CMOS gate is probably acting as a low pass filter and removing the glitchy clocks before they can mess up the counter.

Switching the resistance values instead of the capacitance values might be less glitchy, since when changing frequencies only the rate of change of the charge is modified,  not the actual capacitance and charge state.