Does it always make sense to constrain an I/O port?
Well, it does make sense to apply meaningful constraints if you actually care about timing and it does matter. How to constrain it heavily depends on your design. Thankfully, Altera has tons of examples for different cases.

But if you don't care at all then the best way to go is to mark that path as a false path so that Time Quest is happy and synthesizer does not hang for hours trying to route your design in order to meet timing requirements that you don't really have. That you can do with set_false_path command. For example:

set_false_path -from * -to [get_ports { output_port }]


(where output_port is a module's top level port assigned to a pin)

If Time Quest gives you a diagnostics that not every output port has a delay, you may want to add some dummy delay as well, like this:

set_output_delay -clock [get_clocks src_clk] 2 [get_ports { output_port }]


For a more practical example, you can check out this SDC file for this top-level module, the path to led_n is market as false path there since I pretty much don't care about timing from my logic to the LEDs.

Hope it helps.