Do case statements inside a for loop work in verilog?
If "five 12-bit partial products as outputs" desired, then reg [4:0] b11 [0:11]; should be reg [11:0] b11 [0:4];. 

Your b11 calculation is likely incorrect. There are missing elses before many of the if statements. Therefore, all except the final if condition with fall into the final else condition. You need to nest the else-ifs. Alternatively ,you can use another case statement. Also you need to control the ou1 range otherwise the upper assigned bits will be out of range for b11 and masked out. 

Suggestion: (i-2'd3)/2'd2 and format variations of the same equations is used many places. Assign it to a variable, such as reg [2:0] c2, and call the variable (c2) instead of the equation. c2 should be assigned just like your c1. This will help readability of the code and lower chances of a typo.