Do unintended latches only happen for signals in the process sensitivity list?
NO.

Latches are generated for the "assigned to" signals. 
You could define these, as Dave Tweed said, as output signals.

Latches appear if you have combinatorial logic where a variable does not get assigned a value in every possible path. 
You find latches by checking every if, else, case, when etc. to see if at that point in the code a value has been assigned to every variable. 

This is not required for clocked sections. There a variable holds its previous value if no assignment has been made.