Intra-assignment delay in verilog
If you've a blocking assignment statement it'll be executed in the order that's  specified in a sequential block. For example,

initial begin
x=#5 a;
y=#5 b;
end


The a is assigned to x at simulation time 5, while b is assigned to y at simulation time 10. Now consider nonblocking assignment statements with intra-assignment delays that follow in a sequential block:

initial begin
x&lt;=#5 a;
y&lt;=#5 b;
end


In the above case both a and b are  concurrently assigned to x and y at simulation time 5. In other words, non-blocking assignment statements don't block execution of other statements that follow in a sequential block. Or it can be said that the ordering of non-blocking assignment statements in a sequential block doesn't matter at all.