Verilog Code for this (simple) Logic Gate?
It really doesn't make any sense to me how the wires going from o0/a2 into o3 aren't labeled.


They are labelled -- they're g and h.

Here's a redrawn version of that part of the schematic which might make it clearer what is intended:







simulate this circuit &ndash; Schematic created using CircuitLab

Fix the instantiations of o0, a2, and o3 such that there are two inputs and one output for each one. Besides that, what you've got looks correct.