Increasing cache line size when cache and RAM don't work asynchrounsly
It is not clear to be whether you are thinking about going from an N x 1 word direct-mapped cache to a (for instance) N/2 x 2 word DM or to a N x 2 word DM cache. The first might improve sequential access a little, because the second word in a line acts as a prefetch-buffer. The second alternative will improve the hit rate significantly, but mainly because the cache size has been doubled.