2 E-Mosfets connected in series calculations
The question APPEARS straightforward, if unrealistic.
The upper FET has gate connected to drain. 
Nothing is going to change how it is biased :-).
It's resistance is given.  

It's gate source voltage is SAID to be 10V (full supply).
If this is true in both input cases then the output MUST always be zero.
ie you or they have not got the question quite correct.
I take it to mean that you have a fixed resistance FET channel come what may.
If that is NOT what they mean then you may have to ask them.

But, assuming a 10V supply and a 2K resistor where the top FET goes.

The bottom FET resistance is 150 Ohms or infinite.
Go from there ... .