How are such low op-amp input currents possible?
The input impedance can't be compared directly with the leakage current. 

Input impedance is the change in input current with voltage. An input could have a 1uA bias current and 1G\$\Omega\$ input resistance if the 1uA was very stable with input voltage.

They're MOSFETs and almost zero gate leakage is completely normal. Remember that you can store charge for 100 years in nonvolatile memory just with a bit of charge on a tiny gate capacitance. The more impressive achievement is providing any kind of gate protection within that leakage requirement. I suspect they may have some clever bootstrap circuit to minimize leakage. You can search for patents to see if they've disclosed anything relevant (it would be a National Semiconductor patent). 

There are options to using FR4 PCBs, which are not perfect even when perfectly clean (and are easily contaminated by some fluxes to have relatively massive leakage). Here is a document which discusses some of the issues. I think Bob Pease also had some good tips and tricks for achieving low leakage. You can avoid a PCB entirely for the low leakage pin and use a PTFE (teflon) standoff, for example.