How to make valid harness port when generate sub-sheet from vhdl
It sounds like you have no connectivity between your VHDL design and your manually created sheet symbol. 

The issue here sounds like that VHDL doesn't have 'signal harness' 'pins' (ports).  While you can have a port that's a composite (record) type, all it's elements are required to have the same mode (in, out, inout).  Array type have the same name and mode.

Altium appears not to have a mechanism to associate the underlying VHDL design represented by a sheet symbol you create with a signal harness pin - it doesn't match your VHDL entity declaration. 

You could overcome this by using Altium's generated symbol in a sub sheet represented by your new symbol with any nets connected from the VHDL generated symbol to signal harnesses, also allowing a name change from the connected nets.

This represents a 'mapping' from the underlying VHDL model represented by Altium's generated symbol to a new symbol with signal harness pins.

Back in the day when schematic editors had textual representations for their schematics and symbols (or could at least import them) we'd write tools to generate portions of schematics and symbols representing this sort of thing, to save the manual work.

addendum

The file formats Altium uses are Microsoft Compound Document File Format, and appear to be readily reverse engineering eligible with access to Altium's tools to make simple files used to correlate size and length accuracy (units). It should be possible to programmatically generate information that's so onerous to enter by hand.  It wouldn't be a small task, but appears manageable.

There are lots of potential pitfalls, if I recall correctly The geometry used for schematics and schematic symbols  (inherited from Protel) is fixed precision, that infers a maximum symbol size, not to mention sheet drawing outline. You'd likely have to break really large FPGA symbols into sub elements.

I recall in ViewDraw breaking the rules and generating a table format, with pin boxes, short wires with signal names, essentially making really big symbols equivalents of component centric net list views.  I doubt if Altium's formats are so forgiving.  

You could also look for formats that Altium can import.  Cadence's Allegro tools have easy symbol and net list formats, although I'd suspect Altium wold want to import .brd files themselves.

It turns out Altuim imports a myriad of foreign design file formats including the Allegro ASCII brd file format (See Importing and Exporting Design Files ).  Somewhere I have the Allegro Training Manuals describing file formats, it used to be common as I said to manipulate design files with other tools.