Deriving two independently stoppable clocks from one clock
In an FPGA design, you don't typically want to actually stop a clock signal.

If you do so, it's called a "gated clock", and having one in your design will make it harder for your synthesis tool to optimize the design and to achieve timing closure. 

Instead, you simply de-assert the EN (enable) input on all the flip-flops that you don't want to respond to the clock at some particular time. 

In this case, it could mean de-asserting the EN inputs on all the flip-flops in the upstream blocks when the downstream blocks are not ready for new data.

I don't know enough VHDL to write it off the top of my head, but in Verilog, you can infer a flip-flop with an EN signal with something like

always @(posedge clk or posedge reset) begin
    if reset
         out &lt;= 0;
    else if enable begin
         out &lt;= ...
    end
end