Understanding Verilog Netlist
Your netlist has created tie cells, effectively a good electrical 0 or 1.

The have been created using GND cells and they drive your wires similar to synth_net.

{a,b} is a concatenation operator if a &amp; b are 1 bit each you will have a 2-bit value which looks like ab.

Therefore  {synth_net, in1} is effectively in1 with a 0 (GND) added to the MSB.

The Article you linked to only seemed to show ordered port list connections, I prefer to use named connection as you have in your netlist.

ADD2 synth_ADD(
  .in1( {synth_net, in1}  ), 
  .in2( {synth_net_0, in2}),
  .cin( synth_net_1       ),
  .out( {synth_net_3, synth_net_4})
);


The above is an instance of ADD2 this instance is called synth_ADD. synth_ADD has ports in1, in2, cin and out. Looking at the instantiation we can see that in1 is being driven by  {synth_net, in1}.