How is pipelined DES different from sequential DES?
a series implementation puts all the data through each stage and you have towait for the output to settle before you can use it. 







simulate this circuit &ndash; Schematic created using CircuitLab

with a pipelined implementation there's a register between each stage so that after the first stage has processed the block it's output can be stored in the register and the second block can enter the pipeline. in this way at the expens of some latency throughput can be increased manyfold. 

The reason why the lower pipelined implementation is faster is because the first stage can only be clocked as fast as the inverse of the propagation delay of F1-F4 cascaded. If F1-F4 takes super long to compute, then you can't pump a lot of data through it.

The pipedlined datapath can be clocked as fast as the worst of the propagation delays of the stages allow it to. That means, assuming F1-F4 have the same propagation delay, you can pump 4x more data through.