Do bubbles affect the delay?
Not really.

The "bubble" is a logical inversion. It doesn't necessarily correspond to a physical inverter.

Delay is a property of the physical implementation of a circuit. There isn't really a "standard gate delay" which you can use for all gates at all times. Different logical implementations will have different delay, and it's affected by all sorts of factors including the size of the gates and also the wiring between them.

For the specific case of a CMOS gate, as found in computers, if you were to compare a NAND gate with a bubble against an AND gate without a bubble, and the gates are of comparable size and load capacitance, you would find the AND gate was probably slightly slower. That is because CMOS gates are "naturally" inverting, and tend to be built from NAND/NOR structures as fundamental building blocks.