Verilog to spice using v2s- specificing the port order in the command v2s
Since this question has been unanswered for a couple a of days now I am now posting the following slightly off-topic answer in the hope that it helps.

I don't know about v2s (I don't have access to hsim), but Yosys can also be used to convert Verilog to spice.

I don't suggest that you use Yosys (although I would find that awesome since I am the author of Yosys), I suggest that the v2s authors maybe had a similar approach to the problem as I had when I wrote my code.

Yosys defaults to alphabetical ordering of ports if no blackbox module for the cell is provided, but uses the ordering from the blackbox module if one is found.

So given the following input (as test.v)

module test(VDD, VSS, cnfg, nor1_o);
  input VDD, VSS;
  input [1:0] cnfg;
  output nor1_o;
  F10L16B_NOR2X4 nor1 ( .o ( nor1_o ) , .i0 ( cnfg[0] ) , .i1 ( cnfg[1] ) ,
                        .VDD ( VDD ) , .VSS ( VSS ) );  
endmodule

(* blackbox *)
module F10L16B_NOR2X4(input VDD, VSS, i0, i1, output o);
endmodule


the command yosys -p 'write_spice test.sp' test.v will create the following output (as test.sp).

* SPICE netlist generated by Yosys 0.3.0+ (git sha1 3b52121)

.SUBCKT test VDD VSS cnfg[0] cnfg[1] nor1_o
X0 VDD VSS cnfg[0] cnfg[1] nor1_o F10L16B_NOR2X4
.ENDS test

************************
* end of SPICE netlist *
************************


(The blackbox attribute is a specialty of Yosys. For most tools every empty module is a blackbox module.)

For me this seems to be the most natural way to do that. Maybe you are lucky and the authors of v2s felt the same way..