Designing a deterministic-startup precise oscillator
While crystal frequency stability is nice, only high overclocking
will achieve low 'jitter', because powering down the crystal
takes many cycles (like, thousands); the high Q of a crystal makes
it unsuitable for start/stop operation.  High enough crystal frequency
(low period time), means the one-cycle response uncertainty to
an asynchroous trigger might be acceptable.

Monostables are generally not adjustable over the microseconds-to-milliseconds range.    Counters, though, are.

Consider a startable oscillator that comprises an inverting gate feeding
a delay line (a foot of CAT-5 wire, four pairs in series, has circa  five nanoseconds
of delay), would make a low-jitter startable clock, and some programmable
counters can generate the events.   







simulate this circuit &ndash; Schematic created using CircuitLab

Turning the clock off, and
waiting for the next trigger, would be the last 'event', and requires
only a few cycle times to clear the delay line (damp the 
reflections in the delay line with its termination resistor).

The hypothetical 5-ns delay line would generate a 100 MHz
clock, but that can be divided down to something slower, without
compromising phase and timing repeatability.