how to trigger another clk in mainclk (verilog)
Well i beat this one. I just needed to built rising and falling edge detector

all i neeg is that few lines

reg    main_reg;
wire    pos_sclk, neg_sclk; 
assign  pos_sclk = sclk_adc &amp; ~main_reg;
assign  neg_sclk = ~sclk_adc &amp; main_reg;


and in main clk block

main_reg &lt;= sclk_adc;