PoE Circuit Resistor Question
At first glance, this looks like a circuit that will do bridge rectification of a POE input signal, provides (body) diode rectification to bootstrap the system, and then allows for automatic MOSFET biasing to decrease the losses in the system. 

When ADPT is pulled low, current can flow through Q6. This allows the bias voltage generators for the positive and negative side to function. Suppose PR12 is a positive voltage and PR78 is a negative voltage. There will be a current path from 


PR12
D9 - D13 - Q2 (Base-Emitter)
Q6 - R14
Q10 (Base-Emitter) - D22 - D26
PR78


In this example, Q2 and Q10 are on. Q2 will pull down the gate voltage of PFET Q1C to about (V(PR12) - 9V), and Q10 will pull up the gate voltage of NFET Q11A to (V(PR78) + 9V). Here, C6 stabilizes the gate voltage of Q1C, reducing susceptibility to noise. 

R5 is present to discharge the gate-source voltage of PMOS Q1C if the gate should no longer be pulled down. This could happen either due to driving ADPT high, or the POE power being turned off / disconnected.

C10 and R9 perform a similar function for the NPN Q2. On the bottom side, the topology is mirrored with C19 and R18 stabilizing the base voltage of the PNP Q10. R22 and C23 stabilize the gate-source voltage of NMOS Q11A

This scheme will provide significantly lower loss compared to a diode only solution, and shouldn't be speed critical as I believe PoE should be DC.