Understanding "Verilog default:’1"
The inner single quote before the 1 is a numeric literal fill. The '0, '1, 'z, and 'x literals will be extended to fill the width of whatever context they are used in.
The outer single quote before the { means that this is an assignment pattern to an array or struct. Assignment patterns require a value for every element of the array or struct, which can be positionally ordered or matched by name/index. When matched by name/index, the default: serves as a match to any unspecified element.
This is all explained in section 10.9 Assignment patterns in the IEEE 1800-2017 SystemVerilog LRM