branch address computation single-cycle vs multi-cycle vs pipeline risc-v
In single-cycle processors, everything is calculated during one cycle and there is no dividing into the stages. For example on the following image is the single-cycle MIPS processor from This book.




The branch address is the signal PCBranch.


In pipelined processors, however, every instruction executing is divided into five stages:
Instruction Fetch
Instruction Decode
Execute (ALU)
Memory
Write Back  


The complete pipelined MIPS is on the following image



The address is calculated in the Execute stage but taken in Memory stage. 


I did not work with multi-cycle processors, but according to the book and the following image, the address is calculated in the Execute stage. The signals flowing during beq instruction is shown with dotted-line.