Master SW (bit-bang) I2C with Interrupts?
Turns out that JustMe (thanks) pointed out that during an interrupt the I/O lines are held in their interrupted state. Since slave devices have no minimum clock time, the i2c interface essentially becomes frozen in time during the interrupt. Therefore interrupts should present no problems for bit-bang I2C code (assuming of course that the interrupt code does not interfere with the I2C port lines). 

Also, in writing bit-bang, I2C code SSPCON1 should use the SSPM3:SSPM0 setting of 1011b (Firmware controlled Master mode) rather than the 1000b setting (Master mode clock). Setting SSPM3:SSPM0 to 1011b releases hardware control over the timing allowing the BB code to handle the clock timing. Turns out that I was using the wrong setting here. :(