DDR3 Address Bus Quations
Generically speaking, DRAM &mdash; whether asynchronous or synchronous, SDR or DDR &mdash; receives the row addresses and column addresses multiplexed on a single set of pins.

With older asynchronous DRAM, this is controlled explicitly by the RAS (row address strobe) and CAS (column address strobe) control pins.

With synchronous DRAM of any type, the RAS, CAS and WE pins have been combined into a more generic command bus, but the basic concept is still the same: row addresses and column addresses are transferred on two separate clock cycles.