Declaring vector variable in the Verilog not starting with the MSB(e.g,. reg var[0][20])
In Verilog, the numeric index ordering of a memory is only a matter of preference except when loading the memory from a text file. The first line in the file represents the left index, and like most other languages, starts at 0, so [0:15] is the more common way to declare a memory range. Otherwise there is no advantage one way or the other in how you declare a memory range since you canny only reference one memory element at a time. 

The same can be said about a vector if you never plan to access individual bits of the vector. But once you do, how you address each bit becomes significant in position of an integral value. 

In SystemVerilog, the ordering of both the vector width and memory dimensions becomes significant because you can stream memories as a whole and well as selects parts just like you do a vector.