My NMOS inverter is showing negative spikes in the LTspice simulation
I am getting a negative spike when the input is on falling edge. Why
is this?

In a MOSFET there is capacitance between gate and drain so, when the gate voltage falls to zero rapidly, the effect it has is to capacitively couple energy through to the drain and start to forward bias the bulk diode in most MOSFETs hence, it gets limited to about -0.7 volts (or thereabouts).
In short: capacitive coupling from gate to drain.