AXI Stream Master - M_AXIS_TVALID not always be '1' during a transaction and M_AXIS_TLAST
I get the answer from here and would like to write a short summary.
1.) The signal M_AXIS_TVALID can be discontinuous, so this testbench is valid (I have tested it on the hardware by setting some interrupt signal to influence the M_AXIS_TVALID):



2.) M_AXIS_TLAST is to tell the AXI S2MM DMA that a transaction is done. So, the XAxiDma_SimpleTransfer can be run properly and XAxiDma_Busy(&amp;AxiDma,XAXIDMA_DEVICE_TO_DMA) is not always busy which is set to zero.
3.) (2) has resolved this problem. Moreover, I made a mistake of transferring false MAX_PKT_LEN at the line259 of XAxiDma_SimpleTransfer. This is also a factor that will make the program stuck at this line272-XAxiDma_Busy.