Help with design of current DAC
Here is a sanity check on the DAC goals.

1) update rate is 150Mhz (6 nanoseconds)

2) want settling to 1%

3) need to operate with 25 nanoAnps

4) summing node has 0.1pF total drain capacitance

5) assume the summing node must change the voltage by 0.1 volts, as switch form 1 LSB to 255 LSB.

Given C = 0.1pF and dV/dT = 0.1v/6nS, we use I = C * dV/dT 
and find

I = 1e-13 * 0.1 /6nS = 1e-13 * 1e+9 * 0.1/6 = 1e-4 * 0.016 = 1.6uA

Thus 25nanoA are 64x too slow.