FPGA automatic pipelining?
I am not aware of any tool having that option. The closest is the 'register balancing' support in e.g. Synopsys synthesis. There YOU put X register stages at the output and the tool pushes them into the design to get timing closure. I don't know in how far this is supported by synthesis tools from other vendors.
What you are doing is absolutely incorrect!!! You can't just set a multi cycle path and "find" that your problem has gone away. The timing error is still there, your circuit will still fail but the tool will be silent about it. So instead of an error you now have an error which is ignored by the tool.


  This fixed timing checks


Not it does not! What you are doing is absolutely incorrect!!! You can't just set a multi cycle path and "find" that your problem has gone away. The timing error is still there, your circuit will still fail but the tool will be silent about it. So instead of an error you now have an error which is ignored by the tool. There are numerous pitfall with multi cycle paths. This may sound pedantic but: From what I read I think you should not touch multi-cycle path settings until you have some more experience and know what you are doing. 
 The closest to 'automatic' solving your probem is:


Check if your tool has register balancing. 
If so take your negative slack and divide it by the clock period.
Round the number up to the nearest integer.
Add that number of register stages at the output.
Synthesis with register balancing on.


Otherwise you are back to having to figure out yourself the best place to put a register stage in.