How do FPGAs reconfigure themselves based on the users wishes?
It's a bit complicated and involves a lot of software.  

Initially, you write code in a hardware description language such as Verilog or VHDL.  This, along with timing and location constraints, make up the input of the FPGA toolchain software.  The toolchain is a series of software programs that transform the HDL description of the design into a binary format that's specific to the FPGA that you are using.  The same basic sequence is used for designing ASICs, though it is much more complex and there many more adjustments that can be made along the way as there is significantly more flexibility in what you can do on an ASIC.  

The first step in the toolchain is called 'synthesis'.  The software 'synthesizer' elaborates the HDL and converts it to a generic netlist.  This process is somewhat similar to what goes on in a compiler such as gcc.  Preprocessor and synthesis directives in the code are carried out during elaboration as well as some basic optimization (computation of constant values, constant propagation within modules, removal of disconnected/unused components, etc.).  The output netlist is a representation of a schematic, and it contains logic primitives (gates, multiplexers, RAMs, etc.) connected together with 'nets'.  These primitives may also get timing and placement constraints attached as metadata.  

After synthesis, the design is optimized and mapped.  Optimization involves reorganizing and simplifying the logic for smaller area and shorter paths.  Mapping involves replacing generic primitives with primitives that are supported by the specific FPGA that you are using (block RAM instances, flip flops, LUTs, etc).  The mapping step also determines how the logic gates will be divided up into the look-up tables that the FPGA uses to implement the logic.  The output of the mapper is also a netlist, but with device-specific primitives instead of generic ones.  

Mapping is followed by placing.  The FPGA contains uncommitted logic resources that can be used by your design - look up tables, flip flops, RAMs, etc.  The placer decides which specific instances on the physical FPGA will be used for each instance in the mapped netlist.  This information is generally included in the netlist as metadata.  The placer tries to position connected components close to each other so they can be connected with the shortest possible routes so that the timing constraints can be met.  

Placing is followed by routing.  The routing software takes the placed netlist and figures out what wires in the routing network to use for each net in the netlist.  This can take a long time for a complicated design with hundreds of thousands of wires.  The placer also takes timing constraints into account to try to make sure that the connections that it makes will allow the chip to run at the clock speed specified in the timing constraints.  

Placing is generally followed by a static timing analysis.  The timing analysis looks at all of the paths through the logic and it computes how long it takes signals to propagate down those paths as they have been placed and routed.  Detailed timing information including required setup and hold times of internal flip-flops, block RAMs, and other components as well as delays through all LUTs and routing network segments are measured by the manufacturer and included with the toolchain.  This information is used to make sure that the design will operate correctly on the FPGA.  

After the timing analysis passes, the final steps are design rule checking and bitstream generation.  Design rule checking makes sure that the various components are configured correctly.  It's a much more involved process in ASIC designs than in FPGAs.  Bitstream generation is the final step, and it takes the placed and routed design and converts it into a set of configuration commands for the FPGA.  The FPGA bitstream tells the FPGA how to configure its internal routing components, PLLs, flip-flops, IO banks, block RAMs, etc. to implement the design.  

Now, as for the FPGA itself...there is a lot of good information in various tutorials online and in the device manuals.  I would recommend downloading the PDF manuals for an FPGA and take a look at the figures.  One decent example would be Xilinx UG384, the manual for the configurable logic on the Xilinx Spartan-6 FPGA.  On pages 9, 10, and 11, the manual has rather detailed diagrams of a few different logic slice types.  The gist of it is that basically every logic component (LUT/RAM, flip-flops) can be configured both in operation mode and initial value.  The LUT in the SLICEM, for example, can be configured as a LUT, a single or dual port RAM or ROM, or a shift register, all with initial contents loaded from the configuration bitstream.  The output flip-flops can be configured as flip-flops or latches, also with initial value configurable from the bitstream.  All of the multiplexers that aren't driven from a drawn-in signal are set by the configuration bitstream (A/B/C/DMUX outputs, flip flop D input, LUT DI1 input, etc.).  There are some details on the interconnect resources on page 36 as well.