AD7147-1 CDC Conversion Complete Interrupt
I'm not seeing anything that looks wrong in your question; are you having any problem with the ADC readback, or just asking why bits 0 and 1 might also be set when bit 2 is set in STAGE_COMPLETE_INT_STATUS? 

I'm not familiar with this part, but it looks like bit 2 of STAGE_COMPLETE_INT_STATUS tells you that stage 2 of the conversion is completed. If you set SEQUENCE_STAGE_NUM to 2, that should mean the entire conversion is completed. Bits 0 and 1 are sometimes set if the next conversion is starting to be processed; it shouldn't strictly be a problem, though you probably need to handle the interrupt within a certain time limit to avoid losing the sample if that's important to you. 

Are you setting the SEQUENCE_STAGE_NUM register to 2 to tell the part you only have 3 inputs connected? (At least I think that might be how it works...)