When a processor has a given frequency, what is the order of magnitude of the typical transition frequency of the internal transistors that make it?
Not a complete answer: 

Of the order of 10x (on the high side) I think, for a high performance CPU; more for a less optimised one. 

It's more often expressed as the number of primitive (NAND/NOR) gate delays in a clock cycle, which is computable from the logic design, and I recall reading in the Dec Alpha/Pentium Pro era that the target for some CPU design was 14 gate delays in a clock period : that is, every logic path between registers had to be &lt;= 14 gates (considered as 2 input NAND gates). 

This was unusually tight, aiming at a fast clocked CPU for its day. May have been the Pentium-4 which had an unusually long pipeline (introducing extra pipeline registers to reduce the length of logic chains in each pipeline stage).

Found a paper from 2002 discussing this tradeoff; it describes pipeline stages reducing from 84 gate delays to 12 at one point, and discusses the DEC Alpha 21264 in some depth.

The delay in a gate is naturally related to the Ft of its transistors; I don't know the relationship offhand.

Put these two factors together and you will have your answer.