Verilog: Break an always block
Yes, you should name your begin-end block and then use disable statement like this:

always @(posedge clk_i or posedge rst_i) begin : block_to_disable
  if(rst_i) begin
    // Do stuff
    disable block_to_disable;
  end

  // Do stuff
end


Though, this is probably non-synthesizable, so you can do such tricks only in simulation (testbenches, etc.).