can quartus synthesize a tri-state bus?
FPGA internals do not really do tristate, that is a feature of the IO drivers.

Ignoring issues of verilog syntax (I don't know the language) it might build, but is a bad idea, as I would expect it to be represented in reality by a stonking great mux, being the closest thing the internal fabric can get to a tristate bus, it is also possible that it may not build, as I say I don't know verilog. 

You might want to take a careful look at the size of your parts LUTs before doing a binary tree, some of the more modern parts have 6 input LUTS that might make something else optimal. 

I would also suggest that you are maybe thinking a little too close to the hardware, writing a mux something like (in VHDL) outb &lt;= inb(selector); is likely to synthesise to something reasonably optimal and will not have possible 'X' or 'Z' states in its output.
My selector signal really wants to be a priority encoder over your enb lines unless you can do something more reasonable there, individual enables like this are a pain?

Regards, Dan.