Implementing timeouts/timers in VHDL
Here's a flexible pattern I've used a lot for this and similar purposes.

I prefer to use the actual clock period and delay values to generate the count values, rather than calculating magic numbers.

It will generate a counter - but a 16 bit counter is invisibly small in any FPGA you're likely to find today. Beyond about 24 bits it may start to impact speed, then you can break it into two smaller counters, using the first as a prescaler, generating a clock enable for the second.

And the pattern shown re-uses the same counter, to matter how many different delay values you need - unless you need more than one delay simultaneously.