Can someone give me some ideas concerning the logic of a serial-parallel converter?
Once I can get the FPGA's clocks to be locked together


Rather than do this, consider using the typical solution for transferring high speed serial data along a single lane: use an encoding from which the clock can be recovered. 8b/10b is perhaps the most common encoding for this, used in HDMI/DVI/DisplayPort/Firewire/SATA/SAS and so on. 8b/10b will ensure your signal is DC-balanced and has enough edges to reliably recover a clock.

I am not very familiar with Lattice FPGAs, but most FPGAs (with the exception of very low cost devices have built in SERDES blocks. Transceiver IP can greatly the configuration of these transceivers. Given that you are using a Kintex-7, you should have GTX transceivers at your disposal, which can operate plenty quick (12.5 Gbps). Additionally, you will likely want to implement some rudimentary protocol (to perhaps carry more refined timing information) on top of the 8b/10b encoding, but for your use case it can probably be quite simple.

You didn't provide any details of your fiber transceiver(s), but I'm assuming it's designed to be driven by some flavour of high-speed serial transceiver, and should be easy to connect to the transceivers at both ends. What is the interval between gate signals (i.e. what clock rate is the far end operating at)? If it's long enough, you can send an entire symbol to indicate each gate state change. Linking a timing diagram of your gate drives would be helpful.