Frequency divider works only for some divisors (Verilog on Lattice iCEstick FPGA)
If you use long counters (32 bits) with pretty fast clocks (12 MHz) there might be a problem when using counters without a carry look ahead logic. The ripple carry needs so much time from LSB to MSB that the next clock pulse will be at the input before the ripple carry signal have reached the highest bits of the counter. If the ripple carry have to path a very long way from clock input to MSB, there is no time left when all counter bits are stable at the same moment of time. The comparison of the counter state to the maximum value is not possible anymore. A better aproach is to use a down counter loaded the divison factor each time when counting down to zero. It is much easier to detect the zero state when all counter bits are 0, you invert all bits and feed them to a 32 inputs and gate. Instead of using a very long counter, it is better to use a prescaler dividing by 16 and a counter with only 28 instead of 32 bits. By the way, for a maximum counter value of 6E6, you need only 23 bits, not 32. You might use a prescaler dividing by 8 and a 20 bit counter only.