Verilog test bench incorrectly reading test vector
The clue is in the warning messages at the beginning of the simulation:


  WARNING: testbench3.v:17: $readmemb: Standard inconsistency, following 1364-200 .
  WARNING: testbench3.v:17: $readmemb(xor_4.tv): Not enough words in the file for the requested range [0:10000].


Each entry of testvector is 4 bits wide, however xor_4.tv is 5 bits and {a,b,c,d,yexpected} is also 5 bits.  

Change reg [3:0] testvector [10000:0]; to reg [4:0] testvector [0:10000];