Bypass SuperSpeed USB3.1 lines around USB2.0 Hub
This design uses one USB 2.0 channel for the high-speed data channel of USB 3.0 and another for FT2232 for jtag/uart/spi for programming and debugging.

Traditionally FT2232 is usually connected a independent USB 2.0 port, but this design multiplexes it into the main USB port using a USB 2.0 Hub IC.

Super-speed channel is not split because FT2232 is a full-speed chip and can not make use of the super speed channel.


  But in the proposed FPGA host interface scheme,
  instead of connecting the USB 2.0 signals (D+/D-) directly to the
  upstream connector, a USB hub (USB2422 – A 2-  Port USB 2.0 Hi-Speed
  Hub Controller from Microchip Technologies) is inserted in between.
  This allows the USB2.0 bus available on USB C connector to be shared
  between FT601 and the FT2232H USB 2.0 FIFO bridge acting as the
  sideband processor (See figure 3   below).    In this scheme, the SPI
  signals available on FT2232H Bus A are connected to the SPI bus used
  for FPGA configuration. A General Purpose IO on this bus is also
  connected to PROG_B of the FPGA to allow the host to reset the FPGA.
  Optionally,  additionally available General Purpose IOs on FT2232H can
  be used to monitor the FPGA configuration progress by observing the
  DONE signal.


This solution works because the high/full/low-speed channel and super-speed channel work independently and not simultaneously on one endpoint, so the FT601 chip either sees itself directly connected to the super-speed channel, or to the high/full/low-speed channel via a hub. One more hoop in the high/full/low-speed channel than the super-speed channel is not an issue.