Is this a flip-flop?
It's a cute way of drawing the schematic. A less-cute drawing would look like:







simulate this circuit &ndash; Schematic created using CircuitLab

Now, it is pretty easy to see that the RTS line needs to pull down (be LO) in order to have an impact on RESET and that the DTR line needs to pull down (be LO) in order to have an impact on GPIO0. Both the RESET and GPIO0 lines are also now very clearly also simply "open-collector outputs," so they will need some kind of passive pull-up (at least) in order to have a definite output voltage in all cases.

With only a very slight moment's consideration, it's also clear that if both DTR and RTS are pulled LO then neither GPIO0 or RESET are actively pulled down. The same is also true if both DTR and RTS are pulled HI. So the only way either of GPIO0 or RESET can be actively held LO is if RTS and DTR are different from each other, with the one held LO actively controlling its associated output by pulling it LO, too.

So if DTR=HI and RTS=LO then RESET is actively pulled low and if RTS=HI and DTR=LO then GPIO0 is actively pulled low. Otherwise, neither GPIO0 or RESET is actively pulled LO.



The above assumes that DTR and RTS are logic-level signalling. However, those lines may be RS-232 signals since those pin names are also often found with RS-232 devices. You don't say. But if they are, then everything I mentioned above is put into jeopardy. With RS-232, a MARK is from -3 to -15 volts and a SPACE is from +3 to +15 volts. And it's rather likely that the whole scheme winds up damaging the two BJTs as well as whatever is connected to GPIO0 and RESET.