Disorder pin arrangment
Pin mappings are often done in a "what's easy for both the manufacturer and customers" manner. 

For example, in DIP/SOP package, you'll often find the power supply pins at the corners, or smack in the middle. That doesn't have any specific advantage aside from maybe making it easier to route signals on a PCB so that the data lines do not have to cross power lines.

Pin ordering on "old" families like the Atmegas often "grew" over size. That way, you can just show people reference designs with the socket for the "longest" variant in your portfolio. The "crucial pins" (VCC, GND, xtal, reset) would be in "fixed" positions, and the GPIO pins that the larger variants have over the smaller ones are just added to either side of that (that's my guess why a lot of Atmegas have power straight in the middle of the case).

For very low-integration devices (read: early ICs, high-current ICs), the cost of routing a metal plane lane around on the die might be high enough to dictate an manufacturer-perspective "easy" pin mapping that doesn't look overly sensible from a user's perspective. On MCUs, that's typically not the case. More often, the DIP/SOP packages are "lower volume/lower speed" customer-targeted, so that the primary design target was some square package, and the sheer geometry makes it hard to keep a sensible pin mapping when using the same silicon die in another package.

I've downloaded the Datasheet to your Atmega8A, and I must agree, the DIP pin ordering is a bit arbitrary. In fact, it's relatively much arbitrary compared to other MCU architectures in packages of that pin count. But maybe that's due to (in my impression) the fact that Atmega's niché is not "easy to integrate" MCUs, but MCUs that are capable of sourcing high currents, and thus, the aforementioned flexible IO routing might get a bit more complicated, and also, not that often necessary.