FPGA power management capabilitites
First let me say that power is not an FPGA strong point.  However, there are some things that can be done to tame that power hog (some overlap what you have listed for asics, some are vendor/model specific):


Clock domain separation (same as in asics).  Use slower clocks whenever you can.
Clock gating.  This the traditional way of 'disabling' blocks of circuitry.
Separation into Banks.  FPGAs usually have multiple banks, and what you can safely power down varies with vendor and model, but they can have separate power supplies for IO, high speed transceivers, differential clock inputs, among others.
Programmable output slew rate and drive strengths.
Power-down option for certain built-in hardware blocks (such as memory blocks, hardcopy blocks, certain PLLs, specialty transceivers, etc.).
Partial Reconfiguration, which is being able to reconfigure part of the FPGA (with other parts of it being operational).  When certain features/modules are not needed, you could "erase" them for minimal power, and reconfigure them later on, or even reconfigure the FPGA with a lower-power design/profile.


There is some additional information on Altera's Reducing Power Consumption and
Increasing Bandwidth on 28-nm FPGAs