Input CLK Keeps Showing As Hi-Z on ModelSim
At the top-level of your simulation you have two modules:


FPGA_testing
FPGA_testing_tb


Thus somehow you managed to include your bare, unconnected "FPGA_Testing" module at the top level (alongside your test bench).

In the hierarchy I can see your module because under "FPGA_testing_tb" there is a [+] with the name 'test'. That is where you DUT (Device Under Test) is.

To see your module working look at the signals inside that. You should,hopefully, see your counter working in there.