feedback loop component dc converter
With a ratio of 5 or about 2 octaves with only a 2nd order filter you get -11 to -13 dB of ripple rejection at Fs and only half this at the Nyquist rate of Fs/2 so it will be noisy.

If your ADC is say 10bit with -60dB quantization level and you want to reject PWM noise, then a higher order active Bessel or Chebychev filter with the group delay and rejection is required or a sigma delta type ADC.

Search this site for better ADC designs and filters, and learn to make a list of test criteria or specs.!!!


define your specs for input SNR , BW and level range then desired output SNR + quantization noise. From this choose your filter and oversample Fs, with decimation is the best way done by Sigma Delta types or others, just as it is done in DSO’s with Gb/s sampling rates and xxx MHz signal BW.


Unless you also sense input /output current for forward PWM loop error correction with Vout , you will probably experience horrid startup currents and step load overshoot or fancier lead/lag compromises with ripple to improve stability. 

You must use minimal lag (group delays) filters and latency for best 1st order stability. 2nd and 3rd order OA effects or 4th order ADC averaging effects all reduce stability.