Why I can not copy a content of register to another one in “always” block in Verilog?
I think your real problem is that you are trying to load the delay flip-flops on two different edges, signal and clk_1khz. Such a flip-flop is (generally) not synthesizable, so the tools will throw an error if you try to do it. You will need to figure out a way to accomplish your goal without assigning to the same reg in two different always blocks.