Optimization of Vivado synthesis
They are pretty close for the exact thing you describe, but often writing something very slightly different but with the same essential behaviour will get you a smaller or faster design. 

For example on a 7 series device, there are multiple registers per slice but they share a clock and IIRC also reset and set, so there can be opportunities to improve the packing is what you have is pathological, then there are neat tricks like the availability of the SRL16s (16 bit shift register implemented as an alternative use for a LUT, but it has some constraints, very efficient when the tool can use it, but that depends on how you write the code). 

You need to respect the details of whatever architecture you are targeting if you want to write efficient hardware because (for example) not paying attention to the need for (at least) a sum of products register in a DSP48 will cause it to run very slowly, the details of the chip architecture really matter. 

The general FPGA tradeoffs are area for speed, and clock speed for latency, you can do a lot but you have to think like a hardware designer not a programmer, it is the classic newbie mistake for people coming from the software side. In software you tell a pre defined CPU what to DO (in, usually, a mostly sequential manner), when designing hardware you are telling a sea of gates what to BE, it is a fundamentally different outlook. 

UG901 is a good starting point, also UG474 or the equivalent for whatever family you are using.