Clock Multiplier / Clock Boosting
C2 is charged to 3.3V when the clock is high.

When the clock goes low the lower end of C2 (attached to the inverter) goes to 3.3V. This causes the source of M1 to rise (potentially to 6.6V but parasitic capacitances will cause it to be lower). This will pass through M1 to the output node.

When the clock is low the transistor to the left and right of M1 will both be off.

Be careful about terminology - a clock multiplier is usually interpreted meaning the frequency of the clock is multiplied, not its voltage.