What were gate length of early SSI circuits?
1960s ICs generally did not have gates, as they were bipolar. NMOS, PMOS and CMOS came into their own in the 70s. So we have to talk about feature size. Early TTL (1960s) was around 12um. There's an interesting (and freely available) IEEE publication reviewing predictions. Here is a relevant chart: 



So around 1960/62 we have about 25um and a few um in the early 1970s. 

The feature size did not decrease as dramatically as the number of devices increased. More of the improvement was from increased chip size and better use of the available space, all of which together accounted for Moore's Law. 

Keep in mind also that most of the applications in the 1960s were driven by military/aerospace programs and were not necessarily subject to the usual rules of economics (Moore's law refers to the most economical number of devices/chip).