Non-trivial logic function to CMOS schematic
From your drawing, I derive this:







simulate this circuit &ndash; Schematic created using CircuitLab

Your 10T implementation is correct.

There are alternative 6T implementations as an OAI complex gate:







simulate this circuit

The OAI could be as drawn or the nFETs can be rearranged.

(Note that the bulk nodes of the stacked FETs are drawn inappropriately.  I didn't intend to imply these are discrete ICs with the source and bulk nodes shorted... this is just what I pulled from the library.)