Digital input pin voltage treshold (voltage to register 1 or 0)
The titles of the graphs are actually saying what happens: the hysteresis.

In other words:


if the input level is high (greater than 2.6V), it will be considered high through the hysteresis area (until it goes below 2.2V)
if the input level is low (below 2.2V), it will be considered low through the hysteresis area (until it goes above 2.6V)


According to the description you gave, this should work for your case.
In case it doesn't, you have to condition it until the values you want to consider 0 and 1 are respectively below 2.2V and above 2.6V, with a safety margin, for good measure (say 30%).

The hysteresis is meant to prevent noise from causing unwanted spurious transitions: without safety margin, it should be greater than 0.4V.

You can dimension the safety margin to meet your needs.

But, for the sake of completeness, I'll say that it might be preferable to have a timer to trigger periodic sampling with the ADC.

If you know the maximum frequency at which every input can vary, you can sample it at twice that frequency and be sure that you will not miss anything. Again, this is theory, I would probably make it 4 times, to allow for unforeseen variations.

This works as long as the conversion time of the ADC is shorter than the maximum combined frequency at which you need to read the values.

The GPIOs, of course, are faster, but might require additional circuitry for the conditioning I mentioned earlier.