Interfacing with SPI
The AD7390 data sheet timing diagrams show that /LD is in effect a slave select, but an active high one.

Specifically, it says that while /LD is high, each rising clock edge causes "Shift-Register-Data Advanced One-Bit", while when it is low, the shift register data is transferred to the DAC.

So basically you would need to use SPI in a mode where the slave select is controlled by software and asserted with the opposite of the usual polarity, but the actual shifting of the data can be accomplished with the hardware SPI engine.

It does not seem that you are always required to use the /CLR input - if you don't want to use it, wire it high.  Otherwise, you can connect it to a GPIO, take it low, and then raise it so that the rising edge causes an asynchronous clear.