parallel communication simulation problem
You problem is that you are only using one phase of your &quot;ES&quot; clock, when in fact you should be using two.
In the first phase, where ES is high, is where you set the IO pins to represent your transmitted byte. Only once that is done can you then progress to the second phase, where ES is low, to indicate to the receiver that &quot;I have set up my outputs, it's now time for you to read them&quot;.
So your transmitted code would flow like:

Set ES HIGH
Set output pins to represent the byte
Set ES LOW
Delay
Set ES HIGH

If you look at any timing diagrams for any protocol there will be places where the data is being written to the bus, and places where the data is considered stable and able to be read by the receiver. It's the job of the clock signal to indicate where these points in the protocol - to synchronise the receiver.
For example, here is the Centronics (parallel port) protocol:

The data changes while nStrobe is HIGH, and only when that data is &quot;settled&quot; is nStrobe brought LOW to tell the receiver it can read the data. Once nStrobe is taken HIGH again the data is changed to the next byte to transmit.