Sync issue with signals
I did not tried it out. But something like this might help to synchronize the inverted signals to the rising edge of the high frequent signal.
I removed the FDCSoffset delay, because it is negative according to the variables at the top.
// initialize CIState with 00 
int CIState=B00000000;

// lines not shown .....

for( totalCnt=0; totalCnt&lt;8000; totalCnt++ )
{
  CIState=CIState^B01000000;
  if(totalCnt%4==0)
  {
    CIState=CIState^B00100000;
  }
  // both signals are set at the same time
  PORTD=CIState;
  delayMicroseconds(PWus);
}