3-way multiplexer built on 2-way multiplexers in Verilog
I don't see any problems with the code functionally, and the layout follows good practices for the most part.  That style guide seems mostly reasonable, and it is a good idea to use a set of guidelines.
In my many years of Verilog coding, I have most frequently seen parameters use all capital letters (this departs from the guide you posted):
Use WIDTH instead of Width.
The guide recommends 2-space indents in some places and 4 in others; I recommend 4-space indent everywhere because I think it is much easier to read.
I don't think  your for loop follows the guide.  I would lay it out like this:
for (int i = 0; i &lt; 3; i++) begin
    control = i;
    #1
    $display(&quot;When Control = %d, Y = %c&quot;, control, y);
end

I would also add a space between reg and [:
  reg [1:0] control;
  reg [7:0] a;
  reg [7:0] b;
  reg [7:0] c;
  reg [7:0] y;

I usually find it helpful for debugging to also display the time (copied from my Answer to your previous Verilog Question):
$display($time, &quot; When Control = %d, Y = %c&quot;, control, y);

The for loop exercises 3 of the 4 possible values of Control.  It is a good practice to simulate all possibilities (Control = 3).  Perhaps make it an extra-credit question to explain what happens and why.

I assume one of the goals of this assignment is to demonstrate module hierarchy using an extremely simple design.  Otherwise, your design modules normally would be replaced with a single assign statement.