Pulse-width modulation module
The layout of your code is consistent and easy to read.  I don't see any functional problems.
One consideration for all digital logic is whether you can tolerate glitches on your outputs.  If your PWM output is directly driving a load such as a power inverter, you likely want to avoid glitches.  To avoid glitches, change your combinational output to a registered output:
always_ff @ (posedge clk_i) begin
    if (1'h0 == s_rst_n_i) begin
        channel_o &lt;= 1'h0;
    end
    else begin
        channel_o &lt;= (req_value_i != counter);
    end
end

I also simplified the expression by removing the ternary code ? 1'h1 : 1'h0.  But, this is just a matter of coding style preference.
Another consideration is whether to use a synchronous reset (as you have) or an asynchronous reset.  The advantage of asynchronous is that you don't need to have the clock toggling in order to reset your logic.  For asynchronous, you would use:
always_ff @ (posedge clk_i or negedge s_rst_n_i) begin