Full Adder in Verilog
In the design module, use ANSI-style port declarations to reduce redundant port lists (refer to IEEE-Std 1800-2017, section 23.2.1 Module header definition):
module ADDER (
  input     a,
  input     b,
  input     c_in,
  output    sum,
  output    c_out
);

In the testbench, use connections-by-name instead of connections-by-order:
ADDER adder (
    .a     (a),
    .b     (b),
    .c_in  (c_in),
    .sum   (sum),
    .c_out (c_out)
);

This involves more typing, but it avoids common connection errors, and it makes the code easier to understand (more self-documenting).  Refer to Std section
23.3.2.2 Connecting module instance ports by name.
I usually find it helpful for debugging to also display the time:
$display($time, &quot; %b + %b + %b = %b%b&quot;, a, b, c_in, c_out, sum);