16-bit Parity Generator
As mentioned in the comments the or part of your "xor_gate" prevents it from actually working as an xor gate to calculate bit parity. 

Instead your paro signal will be '0' when a=b  and '1' when a/=b (the 16 bit vectors, not the bits within xor_gate). If that was your intended functionality, then paro &lt;= '0' when a=b else '1'; would be simpler.

Finally, it would be much clearer and cleaner to not have a whole component for such a simple operation. The following does an xor of all the bits (a typical parity calculation) and is shorter and easier to read. If I was only going to use this calculation in one or two places, I'd absorb this whole block into those as well, as it is only 6 additional lines.

library ieee;
use ieee.std_logic_1164.all;
entity parity_2 is
  port(a: in std_logic_vector (0 to 15);
       b: in std_logic_vector (0 to 15);
       paro: out std_logic
      );
end parity_2;

architecture behavior of parity_2 is
  signal parry: std_logic_vector (0 to 15);
begin

parry(0) &lt;= a(0) xor b(0);
c: for i in 1 to 15 generate
  parry(i) &lt;= parry(i-1) xor a(i) xor b(i); 
end generate;

paro &lt;= parry(15);

end behavior;