Hardware Clock Divider
Yes, there are some issues. 

With process (clk, divfactor) you're making it difficult for the synthesis software to generate a nice clocked process. So you should separate the clocked process from the clock multiplexer.

A bigger problem is the clock multiplexer. divfactor is — even if it is synchronous — a 16-bit value, for which all bits have to be checked for 0. This introduces quite some logic, which will always be glitchy... and you're putting it directly into your clock output. danger! danger! A glitchy clock results in undefined behavior... it can even lock your FSMs to an unresolvable state.

Instead check the condition in a clocked process and set a single synchronous output based on its value.

This is how I would write something like this:

library ieee;
use ieee.std_logic_1164.all;

entity config_clk_div is
    port (
        clk : in std_logic;
        divfactor : in std_logic_vector (15 downto 0); -- Note this is actually not a factor!
        clkout : out std_logic);
end entity;

architecture rtl of config_clk_div is
    use ieee.numeric_std.all;
    signal clk_counter : unsigned(15 downto 0) := (others =&gt; '0');
    signal div_clk : std_logic := '1';

    signal divider_disabled : std_logic := '0';
begin
    process (clk)
    begin
        if rising_edge(clk) then
            if divfactor = x"0000" then
                divider_disabled &lt;= '1';
            else
                divider_disabled &lt;= '0';
                if clk_counter = 0 then
                    clk_counter &lt;= unsigned(divfactor) - 1;
                    div_clk &lt;= not div_clk;
                else
                    clk_counter &lt;= clk_counter - 1;
                end if;
            end if;
        end if;
    end process;

    clkout &lt;= clk when divider_disabled = '1' else div_clk;
end architecture;


Note: counting down on a counter makes the compare (to 0) a bit easier. Although this makes more of a difference when designing ASICs.