A byte endian swapper
The code makes good use of parameters.  However, I see a potential problem.
    if (0 == (DATA_WIDTH % 4)) begin

That code seems to imply that any multiple of 4 is supported.  But, if I try DATA_WIDTH = 20, then I see z values in the output.  Perhaps you should restrict values to be a multiple of 8 instead:
    if (0 == (DATA_WIDTH % 8)) begin

Conventionally, the word &quot;check&quot; means that you will compare an actual value to an expected value and report an error if the two do not match.  The check_swap task simply displays the values.  If that is all you are looking to do, then I suggest renaming the task as display_swap or monitor_swap.
However, you could add code to the testbench to do a comparison.  If your tool suite supports SystemVerilog features, then the following additions/modifications would provide automatic checking:
wire [DATA_WIDTH - 1 : 0] data_o;
generate
    if (0 == (DATA_WIDTH % 8)) begin
        assign data_o = {&lt;&lt; 8{counter_dir_value}};
    end else begin
        assign data_o = '0;
    end
endgenerate

task check_swap;
    repeat(ITERATION_NUMBER) begin
        @(posedge clk);
        $display(&quot;A direction value:  %h -&gt; the swap value: %h&quot;, counter_dir_value, counter_swap_value, $time);
        if (data_o !== counter_swap_value) begin
            $display(&quot;ERROR: data miscompare&quot;, $time);
        end
    end
endtask

To create the expected data (data_o), I copied the generate code from the design and made some simplifications.  The {&lt;&lt; 8{counter_dir_value}} syntax is another way to perform the byte swap.  Refer to IEEE Std 1800-2017, section 11.4.14 Streaming operators (pack/unpack).  The '0 syntax is a simplified way of assigning all bits to 0, equivalent to what you have already.  If you plan to synthesize the design, and your tool chain supports this syntax, you could even use this code in your design module.
A minor note: with that type of task body, the begin/end keywords are now optional.