Divide a clock signal by 8
I would recommend a using modern Verilog header:

module prescaleMainCLK(
    input      CLK,
    output reg prescaledCLK
);


adding bit size to your constants is best practice. 'b0 for all zeros with auto sizing. 0 is an integer likely only 32 bits long which can get you in trouble if you start applying to regs bigger than than 32 bits.

The use of initial is only valid in FPGA synthesis, for ASIC you should use a active low async reset.

reg [3:0] counter;

initial begin
    // Initialise both variables
    counter      &lt;= 'b0;
end

always @ (posedge CLK) begin
  counter &lt;= counter + 1'd1;
end


Versus for ASIC:

always @ (posedge CLK or negedge rst_n) begin
  if(~rst_n) begin
    counter &lt;= 'd0;
  end
  else begin
    counter &lt;= counter + 1'd1;
  end
end


You can reuse the counter bits (as mentioned in another answer) for your slower clocks

wire clk_div2  = counter[0];
wire clk_div4  = counter[1];
wire clk_div8  = counter[2];
wire clk_div16 = counter[3];


At faster frequencies this often becomes tricky to balance clocks correctly. A standard industry practice would be to use enables (derived from this counter) for a clock gate. The clock gate allows a pulse from the faster clock through, you loose the 50 50 duty cycle of the clock but balancing the clock tress becomes much easier.