Trying to improve and better understand Intel SSE intrinsics
One improvement would be to restrict the number of (random) memory accesses. First notice is that for each sourceY[fixed] there's also a memory read from sourceY[fixed+1];

I believe these should be at least combined to single 64-bit memory accesses.

A more crucial improvement would be at higher level: is the interpolation really random, or could the xvalues be say localized to say 8-15 successive indices? Then I'd pursuit for a technique that reads them to 2 or 4 xmm registers and tries to shuffle the values in place an in parallel.