d an overview of Agere PayloadPlus. (Source: Agere) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. AGERE PAYLOAD PLUSTM FAMILY OF NETWORK PROCESSORS 107 overhead, fewer clock cycles, and more data processing per clock cycle than enhanced RISC-based processors. As shown in Figure 7.1, the FPP takes packets or frames from the PHY chip over an industry- standard interface that can be either a POS PHY Level 3 (POS-PL3) or a UTOPIA 2 or 3 interface. Then it performs protocol recognition and classification as well as reassembly. The FPP can classify traffic based on information contained at layers 2 through 7. Once this is done, the FPP sends the pack- ets and its classification results via a POS-PL3 interface over to the RSP. The RSP is responsible for handling queuing, packet modification, traffic shaping, the application of QoS tagging, and segmen- tation. The FPP and RSP chips interface with the ASI chip. The ASI chip handles exceptions, maintains state information, and is responsible for the interface with a host central processing unit (CPU) over a PCI bus. The FPP and the RSP are configured and updated via the ASI chip over the Configuration Bus Interface (CBI). A special 8-bit asynchronous bus called the Management-Path Interface (MPI) enables the FPP to receive management frames from the local host CPU through the ASI. A third sys- tem bus called the Functional Bus Interface (FBI) connects the FPP to an ASI and/or other applica- tion-specific custom logic that is used to externally process function calls. All memory interfaces are 64 bits wide either to standard PC-133 synchronous dynamic random access memory (SDRAM) or 133 MHz pipelined zero bus turnaround (ZBT) synchronous static ran- dom access memory (SSRAM). This is a significant advantage as the FPP stores all pattern-matching data in standard memory rather than in expensive and po