ming. Rambus enables the use of many memory banks, but it is difficult to design a system around it because of high-speed signals. It is neither trivial nor within everyone's reach. Its shortcoming of the bank-access randomness can be overcome if adequate time is spent developing and testing highly spe- cialized system software to randomly store information in different banks every time. This would min- imize the impact of the access randomness by spreading it on all Rambus I/O operations. The problem with that approach is that a designer may be able to pick banks to write to cleverly, but he or she has no control over which bank information must be read from. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SYSTEMS ENGINEERING ISSUES 338 NETWORK PROCESSORS An interesting technology originally introduced by Toshiba and Fujitsu is fast cycle DRAM (FCDRAM) (sometimes also called FCRAM). Samsung calls this technology network DRAM (NDRAM). This technology is targeted for high-performance designs. Agere is using it heavily. It is characterized by a 25-nanosecond random cycle time (depending on the generation of the chip) back to back accessing the same bank. This means that FCDRAM is quite faster than DDR SDRAM and offers lower random access times than RDRAM. FCDRAM can be electrically compatible with DDR SDRAM provided the corresponding mem- ory controller is embedded in the NPU. The two solutions have different bandwidths and prices, but this can possibly lower the cost. Bay Microsystems and IBM are already doing it. Another contender in the network-processing field is reduced latency DRAM (RLDRAM) from Infineon and Micron. This technology is competing with FCDRAM in pin bandwidth and latency. SRAM Flavors The basic cost/performance context of SRAM was expressed in the beginning of this section. High- speed contexts require SRAM, but designers d