thing Figure 6.12 Pulse stuffing synchronization. (From Ref. 5, Figure 29-2.) DIGITAL NETWORKS 274.176 Mb/s 44.736 Mb/s 6.132 Mb/s 3.152 Mb/s 1.544Mb/s Figure 6.13 The North American Digital Hierarchy. VF Channel VF Channel 1.544 Mb/s chan. bank chan. bank 6.312 Multiplex Multiplex 1.544 Mb/s Figure 6.14 The formation of the DS2 signal from four DS1 signals in an M12 multiplexer. F bit. The F bits are a 0101 sequence used to identify the location of the control bit sequence and the start of each block of information bits. 6.8.4 European E1 Digital Hierarchy The E1 hierarchy is identified in a similar manner as the DS1 hierarchy. E1 (30 voice channels) is the primary multiplex; E2 is the second level and is derived from four E1s. 6.8 HIGHER-ORDER PCM MULTIPLEX SYSTEMS FO.01.07.03.04 C120102,03,04 C1301,02,03,04 F1:01:02:03:04 M1 subframe Time slots available for M2:01,02,03:04 EITII FORTILL CHIII CIIII] FOR stuff pulses M2 subframe FO[III] ] EITH FILI M3 subframe ] FO[III EIIII FITTO M4 subframe M frame control bit sequence Figure 6.15 Makeup of a DS2 frame. Thus E2 contains 120 equivalent digital voice channels. E3 is the third level and it is derived from four E2 inputs and contains 480 equivalent voice channels. E4 derives from four E3 formations and contains the equivalent of 1920 voice channels. International digital hierarchies are compared in Table 6.2. Table 6.3 provides the basic parameters for the formation of the E2 level in the European digital hierarchy. CCITT Rec. G.745 (Ref. 6) recommends cyclic bit interleaving in the tributary (i.e., E1 inputs) numbering order and positive/zero/negative justification with two-command control. 10 The justification control signal is distributed and the Cjin bits (n = 1, 2, 3; see Table 6.3) are used for justification control bits. Positive justification is indicated by the signal 111, transmitted in each of two con- secutive frames. Negative justification is indicated by the signal 000, also transmitted in each of two consecutive frames. No-justification is indicate