 include companies such as Bay Microsystems, which uses the Xtensa core in the exception/control plane of the MontegoTN Internetworking Processor (InP), and others such as Transwitch for its T3BwP (bandwidth processor), Onex for its Omni Service Processor, Trebia for its Storage Network Processor, Marvell for its NetGx coproces- sor, and NEC3 for its Wideband Code Division Multiple Access (W-CDMA) network infrastructure chip. Depending on the exact function of the development tools, they not only produce executable code for and work directly with the new customized instruction set, but they also reflect the underlying design configuration resources, integration, and use that the user has stipulated. Tensilica's patented design database is an integrated repository for all pertinent information. It facilitates the parallel devel- opment of hardware and software. At the same time, the company has developed patented technology that allows the compression of code instructions in less than 32-bit words (decompressing them on- the-fly during operations), thereby optimizing the memory footprint of embedded implementations. Up to now, we have described what happens in the software development process. For the hard- ware development process and depending on the actual hardware choices and performance constraints that are imposed (regarding power, speed, and size) on the design during the interactive processor gen- erator session, the company's generator tool will also automatically generate the appropriate hard- ware tree of the newly configured core in synthesizable hardware description language (RTL). It also provides Electronic Design Automation (EDA) scripts for the subsequent synthesis step, the neces- sary verification suite, and a bus-functional model (BFM) to interface with the instruction set simu- lator (ISS) and other standard ASIC design tools for synthesis, functional, and timing verification. The processor generator GUI also provides an impressive set of dynamically changing colored bars that show in real tim