very difficult to achieve but in recent years two codes have been designed with near Shannon limit performances. The Shannon limits for common FEC coding rates are shown in Table 6.1. Note that as coding rate increases, the number of extra bits used to generate a mathematical relation between information bits, and thereby the ability to correct errors, decreases. This leads to a higher required power (E,IN) to achieve (virtually) error free communications. Convolutional Coding Convolutional codes are the other class of FEC codes and similar to block code were first introduced in the 1950s. Decoding of convolutional codes is complex but these codes became popular with the invention of the trellis decoder in the mid-1960s. Convolutional codes use memory elements, or shift registers, and modulo-2 adders to generate parity bits as a function of a number of previously input bits as shown in Figure 6.13. The shift registers keep their input for one clock period (one time delay, D) before passing it on to the next memory element at the next clock cycle and as a result, each parity output bit is a function of several input bits (here three input data bits - which is technically referred to as a code with constraint length 3). For most systems of interest to this book, the shift registers are set to 0 at the beginning of the encoding process. The memory elements create a mathematical relationship between the parity bits and the data bits which can then be used at the receiver to correct errors which may occur during the transmission process. The convolutional code shown in Figure 6.13 is a rate 1/2 code, and by convention is denoted by its number of output bits, number of input bits and the constraint length as (2,1,3). Convolutional codes may be designed with a wide range of coding rates and constraint lengths. For example 3G standards use convolutional codes with coding rates of 1/2 and 1/3 with constraint lengths of 9. Example 6.5 For the (2,1,3) convolutional encoder of Figure 6.14, and for input bit sequence of '1100