er therefore expects the 750TM on the 10 GbE cards on the ingress and egress paths. The same principle is also expected with the 550 on the 4X1 GbE and OC-48c cards. The line cards will be computationally split into three planes of computing realms: the data plane, the control plane, and the management plane. Data plane tasks will be the responsibility of the net- work processor. Signaling protocols and some parts of routing protocols such as Open Shortest Path First (OSPF) and Border Gateway Protocol (BGP), or the signaling part of Private Network-to- Network Interface (PNNI) (central routing will be reserved for the system host CPU card) will be offloaded onto the line cards. They will all run on the control plane host CPU of each line card. The management plane work will combine configuration management of the various chips on each line card and exception processing. For our design, the control and management plane may be combined on the same host CPU running on each line card. The designer goes back and forth in this iterative process, mentally scanning issues locally (per card) and globally (per system). Forward movement only occurs when consistency is ensured at both Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SYSTEMS ENGINEERING ISSUES 352 NETWORK PROCESSORS levels of granularity in his or her thought process. An issue that has now popped up in his or her mind is the granularity of the partitioning of each protocol among the host CPUs that are on the individual line cards and the central system host CPU. A few years ago a pioneering approach taken by some vendors involved distributing ATM protocols by putting the ATM signaling on the line cards.6 was a result of the poor performance during ATM call setup time. The same principle now can be in routing protocol partitioning. The designer starts allocating protocols from an inventory