 DS interface Hardware Classifier Egress DS interface (Read) (Read) Dispatcher FIGURE 4.4 The internal structure of the NP4GS3 chip's EPC. (Source: IBM) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. IBM POWERNPTM 68 NETWORK PROCESSORS Frame Access Data Store Search Engine RED Flow Control Policer Counter Assistance Counter Shared Memory Frame Enqueuing Checksum Checksum Chip Control Memory Access String Copy data handlers e.g. GxH Resources Semaphore FIGURE 4.5 Nine Hardware-Assist coprocessors per DPPU. (Source: IBM) SPECIAL COPROCESSOR AND ASSIST HARDWARE Figure 4.5 shows the block structure of a DPPU where the picocode is executed. The figure also includes the nine Hardware-Assist coprocessors. These coprocessors are associated with each DPPU and function in parallel with the data movement by accessing and maintaining internal registers per thread. The suite of the nine Hardware-Assist coprocessors comprises the following units: Data Store Coprocessor This handles all data transfers (read/write) between ingress and egress data stores and the shared memory data pool. It is structured to handle 128 bits per transfer. CAB Interface Coprocessor This provides all DPPUs with access to internal registers, counters, and memory for debug or statistics gathering. Enqueue Coprocessor This interfaces with the Completion Unit (discussed later in this section) from the special hardware units to enqueue frames to the switch and to the target port queues. Checksum Coprocessor This deals with half-word data in order to generate half-word header checksums based on RFC 1071 for the computation of Internet checksums. It works based on two instructions: generate checksum and verify checksum. All checksum calculation results are stored in a special accumulation scalar register. String Copy Coprocessor This moves multibyte data within the shared memory pool. 