ension FIGURE 10.11 The example illustrated here is for a new instruction called here ACS, which adds some operands, com- pares some other entity with the obtained sum, and based on the comparison result selects the content of one among sev- eral registers. (Source: ARC Cores) Resolve a major resource-sharing problem that will be experienced by the cores, especially when it comes down to embedded and off-chip memory access, with scalable, real-time, and fair arbi- tration. Implement a convincing and (above all) functional scheme to address context-switching issues (mul- tithreading with zero switch overhead) in an area where RISC has been traditionally incapable of addressing the problem efficiently. Last but not least (in order to compete with network processors), come up with a flexible and mod- ular programming model that allows the efficient use of such a massive computational artillery in a transparent way, offering a single-image perception to software engineers, who do not need to worry about allocating software work to individual engines. The model should also eventually allow "hot" swaps or code upgrades in the field without requiring the chip to be redesigned every time just to accommodate new functionality. Therefore, the assessment is that this type of technology can be used either in low-speed forwarding-plane designs for packet processing (customer premises equipment [CPE] or enterprise network equipment) or in multiprocessor designs where multiple embedded core processors are inte- grated into the same SOC. That inevitably brings along a whole series of systems architecture issues. However, in the network processing field, this type of configurable processor technology usually seems ideally suited for supervisory and control plane applications, where neither wire-speed Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIV