rain of Dirac impulses. where WVCO(T) is the instantaneous oscillation frequency of the VCO. This frequency is assumed to be proportional to the control voltage that steers the VCO. As long as the models in Fig. 4.3 are valid, PLL design amounts to the design of a CT-LTI feedback loop. This problem is handled using techniques for traditional time- invariant feedback theory [Fran94]. However, as will soon be demonstrated, this CT- LTI PLL model only works fine as long as the unity-gain frequency of the open-loop gain G(s) is well below the frequency of the input signal. If this condition does not hold, the CT-LTI model runs into trouble as the time-varying aspects of the building block behavior become important. Especially for PLLs with a fast feedback loop and a sampling PFD, the impact of the time-varying behavior on the system performance can become quite dramatic. A second problem involving the CT-LTI PLL model lies in a lack of clear theoretical foundations. Contrary to true LTI systems, like filters, the CT-LTI PLL model can- not be derived formally as a small-signal approximation in the neighborhood of a DC operating point. As noted above, the operating point of a PLL is a periodically time- varying one. This rises questions as to how to determine when we can safely assume the CT-LTI model to be correct. 4.2.2.2 Discrete-time, linear time-invariant model It is already known for some time that PLLs implemented using sampling-PFDs, e.g. based on digital logic and a charge pump, exhibit discrete-time behavior [Gard80, Hein88]. The instantaneous phase error is sampled once (or twice) per period of the ref- erence signal. Sampling is triggered by the zero-crossings of the input signal. Fig. 4.4 illustrates the functional model that serves as a starting point for analysis. Sampling is modeled as a multiplication of the phase error with a train of Dirac impulses. 4.2 PHASE-LOCKED LOOP ANALYSIS A number of authors [Gard80, Hein88] have suggested to treat these PLL implementa- tions as discrete-time systems. To do s