essages carrying QL information are not considered for QL- disabled mode. ITU-T G.781 Annex A captures the detailed description of this process. It is important to note that QL-enabled and QL-disabled modes suggested in G.781 are applicable only to SDH/SONET deployments-no similar approach exists for SyncE-a clock generating a SyncE signal but without an ESMC stream is not be considered as a reference source. ITU-T G.8264 describes only synchronous and non synchronous modes of operation for SyncE. Synchronous mode is always accompanied with ESMC messages, and the receiver can recover the frequency for synchronization purposes, whereas in non synchronous mode, the Ethernet port is not considered as a candidate reference for the clock selection process, and the frequency is not used for clock synchronization (but it can be used to drive the frequency of that single link). The clock selection process gets triggered by occurrence of one or more of the following events: Change in received QL (as signaled by SSM or ESMC) Signal failure detected on the currently selected source Configuration changes by operator; for example, addition or deletion of assigned frequency source(s) In general terms, once a physical port is available as a frequency source, the selection process con- siders the following data to select the best clock: Quality of a clock: The clock with the highest QL value is always a winner, as the clock is traceable to the highest-quality source. Note that a change in QL can occur anytime during nor- mal operations. The slave clock acts on a QL change event only if a better QL than the current selection is discovered. Availability of a clock signal: A frequency source must be always available for it to stay as the selected source. In case of physical link failures, the frequency source is marked as signal fail (SF), and the QL for this source is marked as QL-FAILED. If the frequency source moves to QL-FAILED state, the clock starts the process of selecting the next best source. Synchronization source priorit