 Each microengine supports multithreading by maintaining four copies of the program counter. Zero overhead occurs when switching contexts between threads. Each thread uses 32 general-purpose registers as well as 32 transfer registers. The 128 transfer registers are used for the temporary retention of data that happens to be in transition to or from memory. An internal direct memory access (DMA) engine, which automatically steps in after software has loaded the registers, accomplishes the actual data transfer. D-cache 32 bit Mini D-cache Write Buffer 64 bit 4 timers SDRAM Read Buffer 32 bit Microengine Microengine Microengine 64 bit IX bus interface Microengine Microengine Microengine FIGURE 5.1 Internal block structure of the Intel IXP1200 network processor. (Source: Intel) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. INTEL IXATM NETWORK PROCESSORS 80 NETWORK PROCESSORS RDRAM RDRAM RDRAM ME #1 ME #2 ME #3 ME #4 128 bit ME #8 ME #7 ME #6 ME #5 128 bit Intel 64-bit XScaleTM 66 MHz ME #9 ME #10 ME #11 ME #12 48/64/ Scratch Timers Boot ROM ME #16 ME #15 ME #14 ME #13 E/D Q Enqueue/ dequeue 18 18 buffers FIGURE 5.2 Internal architecture of the Intel IXP2800 network processor. (Source: Intel) Whereas the StrongA ARM processor core and the microengines are clocked at 166 MHz, 200 MHz, or 232 MHz (depending on exactly which member of the 12x0 network processor family is used), the IX bus and the PCI bus have their own clock domains. PCI runs at 33 or 66 MHz point to point. The IX bus on the IXP1200 has a typical operating frequency of 33 to 85 MHz. In many designs, if the Intel IXF440 Ethernet MAC chip is used, the clock speed will usually be 66 MHz. The memory interfaces run at half the speed of the core, thus 100 MHz SDRAM and 100 MHz SRAM are required on a system based on the 200 MHz core. SRAM is typically used for lookup tables, whereas SDRAM