ould be to simulate with other feed configurations, and other Simulator settings such as reasonable environment off, or two signals maximum in each input queue instead of one. 7.4.9 Exhaustive simulation with stop conditions More details on stop conditions are provided in Chapter 5. We want to detect that a DLC is established: it means, in our V.76 SDL model, that: instance 1 of process DLC in block DLCa is in state connected, and instance 1 of process DLC in block DLCb is in state connected. 7.4.9.1 Run the exhaustive simulation A. Start the Simulator as indicated previously (be sure not to compile any MSC with the SDL model). Check that the feeds are correct and that the step number is 4. B. Select Edit > Stop Conditions and enter: (DLCa!DLC (1) !state= connected) and (DLCb!DLC (1) !state= connected) C. Select Execute > Verify: in Stop Limit, enter 2 and check the halt box; the simulation will stop after finding two scenarios leading to a global state where the stop condition is satisfied. To stop after one scenario instead of two, you should type the textual command stop limit 1, halt. D. Press Verify and confirm the verification startup. The exhaustive simulation stops after finding two stop condition scenarios: mode breadth deadlock limit 2 exception limit 2 stop limit 2 , halt define stop_cut true define states limit 0 define depth_limit 0 Exhaustive Simulation 251 define verify_stats true verify stopped by a stop condition Number of states : 1554 Number of transitions : 3550 Maximum depth reached : 11 Maximum breadth reached : 325 duration : 0 mn 0 S Number of exceptions : 1 Number of deadlocks : 0 Number of stop conditions : 2 An exception has been found because we have not set Reasonable environment to on. 7.4.9.2 Replay the exception scenario The Simulator has generated two files containing the stop condition scenarios: v76.b1.scn and v76.b2.scn. The letter b means break, being used for means success. A. In the Simulator, select File > Scenario > Load, and open v76.b1.scn. B. Press on Start MSC. C. Pres