t frequency /(4.5 X TLB), where TLB is the LB duration. 11.1.3 Spatial Signal Separation Using a MIMO-MMSE Equalizer The spatial separation of the data signals transmitted from two transmit antennas is performed inside the FPGA in the frequency domain after FFT per subcarrier, based on MIMO processing; the minimum mean square error (MMSE) [3] or MRC © 2009 by Taylor & Francis Group, LLC Early Real-Time Experiments and Field Trial Measurements Received Buffer signals 0.85 ms equalizer Weight CE/Int. matrix calc. Figure 11.4 Partitioning of signal processing. Processing is implemented in a Virtex 2Pro/100 FPGA except for interpolation and MMSE weight matrix computation. filter weights per subcarrier are calculated in the DSP every 500 us. Furthermore, the SNR [2] per chunk is estimated and made available to the Viterbi decoder for soft decoding. Due to the stringent timing requirements of calculating 1,200 2 X 2 MIMO matrices every 500 us, we decided on a DSP star architecture (as seen in Figure 11.4) using four floating point DSPs TI 6713, each processing 300 SCs. 11.1.3.1 Latency Issues In order to separate the two spatially multiplexed data streams in the downlink or to separate the two user signals in the uplink in a simple and robust manner, we have implemented the linear MMSE filter [13]. In a preceding 1-Gb/s trial [2] with a 3 X 5 antenna configuration and 64 subcarriers, one TI 6713 DSP was used to obtain all weight matrices in 2 ms. For LTE, the number of subcarriers is increased by a factor of 32. In turn, the number of antennas is approximately halved. The complexity of weight calculation scales linearly with the number of carriers but cubically with the number of antennas at one side of the link. The complexity per coherence interval is roughly multiplied by a factor of four compared to Jungnickel et al. [2]. Due to hardware constraints, signal processing has been divided among four TI 6713 DSPs (Figure 11.4) synchronously triggered by the 0.5-ms TTI clock period. Each DSP is connected over an individu