 ADONNEESATRANSMETMivreSimul\models0GW76\v76 P geodedit FSM: default: dicaldle (1) File Edit View Execute Icols Help File Edit View Navigate Tools Window Help About selection: input 320 from dicade(1) to dicaddl(1) FSM default: dica!dic (1) Stop it Filter DECISION N320cnt < N320, Watch Print OUTPUT DLCstopped (me) ss DLC (0, maxDLC 1) FPAR me DLCident, originator Boolean output destopped from dicaldi(1) via des to dcaldispatch waitUA Traces: + STOP Defaults stop dicade(1) originator V76frame (V76pora) Unexpected signal disstopped in dicaldispatch line 296 of F: Restore step 25 True ) False V76para present N320cnt N320 SDL tracking 320cnt V76frame ( UA ) (UA: me ( True ) Start MSC Firable Transitions RESET (T320) DLCstopped N320cnt:= DLCstopped Watch iclcaldicil Irom_waltua_input_t320 connected N320cnt dicbidispatch from_ready_prionity_input__releasereg with _relea EstabConf V76frame MSO -driven: BME (me retry Activate connected ET (T320) TIMER , Temporary variables: * ledo: waitUa T320 12.0; uData Integer, 25/26 Now: 48 Verify MSC: ogsm4 inst_1_dica.dispatch inst_1_dica.dic inst_1_atob v76frame( sabme (.00 K Watch Watch creation process diobido not created or stopped Queues Procedure dicaldic(1 Jorook not active 1320(12.0) States dcaldispatch state waitua Active timers dcbidispatch I state ready I! state waitua State coverage process diobido not created or stopped v76frame( sabme Transition coverage atob|1 state ready New window btoal1 state ready 1320(12.0) Close 17 objet(s) émarrer 10:32 Figure 4.46 Searching for the unexpected signal bug In the Editor, select Navigate > Up: the block type V76_DLC is now displayed, as in Figure 3.12; you see that signal DLCstopped goes to process dispatch, through the signal route DLCs. D. In the Editor, select process dispatch and do Navigate > Down and Navigate > Next Partition: you see that under state waitUA, the input of signal DLCstopped is missing. 4.3.3.3 Correct the bug You will add the missing input of signal DLCstopped under state waitUA in process dispatch. A. When 