 website. NETWORK PROCESSORS: JUSTIFICATION 36 NETWORK PROCESSORS serious memory bottleneck as well as from a suboptimal instruction set. The following bullets explain these factors: First, current off-the-shelf processors are clocked at rates of a few gigahertz. Due to their typically pipelined architecture, they are able to perform billions of instructions per second, thereby almost achieving the rate of executing one instruction per clock cycle. However, data must be fetched con- tinuously from memory SO that the processor can work at any moment on the instruction at hand. It also produces data from operations. This data needs to be stored back in memory before new instruc- tions are tackled. However, memory read and write operations are unable to sustain activity at these gigahertz rates. Therefore, elaborate memory subsystem designs must be devised using a multilevel hierarchy of different memory technologies, interleaving multiple memory banks, and synchroniz- ing memory pages and bus access-techniques that usually lead to a prohibitive cost and levels of power consumption. The lack of performance that results from this structural deficiency is an architectural paradox. On one hand, the typical processor pipeline stages end up being in high-speed networking applications often empty (a phenomenon called pipeline bubble) and consequently underutilized. On the other hand, the system remains squarely incapable of dealing with the expected workload. Network traffic obeying completely different statistics models than local traffic on a computer bus does not have the same spatial and temporal locality properties as regular desktop or client-server IT application workloads. The result is that the typical processor's cache systems are not effective in a network-processing environment. Without the benefits of their caches, conventional CPUs sim- ply slow down to a proverbial crawl. The instructions that are needed to handle and modify live packets in a network-processing envi- ronment require specific bit-level opera