the iSNAP hardware architecture. Incoming data are first placed in the SDRAM. The classification engine performs integrity checking. Based on its results, it generates an event in the appropriate queue. All TCP/IP and ULP events are dispatched by the Queue Manager to the processor nodes, which act directly on a packet's header data without having to move the packet around which other architectures would do. When the bit content is properly built and structured, the Event / Queue Manager Flash General Processing Header DMA memory Timer Processor Context DMA Control DMA Memory SDRAM Controller Control Hub Controller Encapsulation Classification Engine Engine PCI-X SPI-3 FIGURE 11.7 The hardware architecture of the iSNAP processor. (Source: Silverback Systems) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. STORAGE NETWORK PROCESSORS (SNPS) STORAGE NETWORK PROCESSORS (SNPs) 213 packet is transferred by DMA to the host. If the direction of the packet is outbound, the header infor- mation and the data will be forwarded separately to the encapsulation engine. The splitting of data from the header and the queuing of all TCP/IP and ULP events are key tasks in the elimination of access conflicts and bottlenecks, which ultimately maximizes the iSNAP chip's performance. In a method that is reminiscent of Fibre Channel HBA designs characterized by optimal host CPU offloading and low latency, the iSNAP host interface is built SO that PDU awareness allows the direct data placement (DDP) of host-bound incoming data into specific application buffers. This minimizes the number of interrupts issued to the host and improves the overall performance. Hardware performs the cyclic redundancy check (CRC) and checksum of all iSCSI PDU data. External memory is pro- tected by error correction coding (ECC), whereas all internal memory is parity checked. Full-duplex Gig