ion of its NISC instruction set in a multitasking environment and its inherent zero-cost task switching, the nPcore engines achieve 4 to 12 times the network-processing capacity of typical RISC central processing units (CPUs). 1. Data sheets, application notes, and white papers on AMCC products and technologies can be found at the company's web site at www.amcc.com. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. AMCC nPTM FAMILY OF NETWORK PROCESSORS 94 NETWORK PROCESSORS AMCC deduced the instruction set after studying the most typical routing and switching algo- rithms and understanding the kind of operations involved. The result of the analysis was a highly spe- cialized instruction set that optimizes the parsing, search, and modification of packets. An example based on RFC 1812 routing shows it can be implemented in just 50 NISC instructions, where each instruction takes 1 clock cycle. AMCC estimates that a typical RISC-based NPU implementation uses 200 to 800 instructions to accomplish the same task. If layer 2 and layer 4 classification were added to the RFC 1812 routing, the nPcore engine implementation would only need 5 more instructions for a total of 55 instructions. At the same time, a RISC-based NPU would need between 350 and 1,200 instructions (and clock cycles). By implementing this NISC model in the nPcores without imple- menting unusable instructions (such as arithmetic operations), AMCC eliminated the waste of silicon. The company further improved the efficiency of the design by adding features that allowed for future expansion, performance scalability, and the attachment of specialized coprocessors either internally or externally. As shown in Figure 6.1, the architecture of the nP is straightforward. The NPU is positioned between the switch fabric on one side and an array of multiple physical (PHY) interfaces on the other s