ormance. The example design is of a simple router that is implemented as a full-duplex ATM-to- Fast-Ethernet conversion engine handling IP packets and working over a dual OC-3 (155 Mbps) link. The router design example in real life obviously requires software to properly handle the following tasks: SAR of ATM cells and IP packets IP over ATM encapsulation based on Subnetwork Access Protocol (SNAP)/Logical Link Control (LLC) ATM Adaptation Layer (AAL-5) as unspecified bit rate (UBR) traffic CRC-32 for reliable transmission As a reference design, the complete software can be licensed from Intel. It can be modified by Intel clients who are eager to shorten their time to market and who want to create their own version of a similar design but cannot afford to start from scratch. Figure 5.10 shows macroscopically and conceptually the protocol conversion that needs to happen in both directions-namely, from Ethernet to ATM and vice versa. In this generic approach, Ethernet Institute of Electrical and Electronics Engineers (IEEE) 802.3 packets go through LLC/SNAP encap- sulation and are then followed by segmentation into AAL-5 cells. The opposite process is applied onto ATM cells, which are stripped from their ATM headers and finally reassembled into Ethernet packets. Figure 5.9 gives an overview of the control flow and an idea of how to apportion the packet pro- cessing needed over the available (in the case of an IXP1200 network processor) six microengines. In this case, three of the available six microengines are tasked to handle the ATM-to-Ethernet data flow, whereas the other three are assigned to the reverse direction from Ethernet to ATM. Multiple queues are used by the microengines to send data from one stage to the next. Details as to how this Microengine 0 Microengine 1 Microengine 2 Ethernet Ethernet Check Tx Queue Ports Ethernet Queue 0 AAL-5 Tx Queue Ethernet Tx Queue Check Check Ethernet Queue 1 Tx Queue ports Ethernet Queue 0 Queue 0 Ports AAL-5 Generator Queue 1 Queue 1 ports Microengine 5 Microengine 4 Mi