twork equipment merely through software. Microengine technology capabilities span a wide range of speed and functionality requirements from layer 2 through layer 7. They can deliver deep packet inspection (as required by the latest intelligent applications) at wire speeds up to OC-192 and beyond. XScale is a new Intel microarchitecture that provides a high-performance, ultra-low power envi- ronment that is compliant with the ARMTM Version 5TE ISA instruction set (excluding the floating- point instruction set). The microarchitecture surrounds the ARM-compliant execution core with instruction and data memory management units, and instruction, data and mini-data caches. It also has other features such as write, fill, pend, and branch target buffers; power management, perform- ance monitoring, debug, and Joint Test Action Group (JTAG) units; a coprocessor interface; a Media Access Control (MAC) coprocessor; and a core memory bus. Although it is obviously targeted to con- trol plane applications, this microarchitecture can take care of communicating with a backplane, man- aging and updating data structures that are shared with microengines (such as routing tables), and setting up and controlling media and switch fabrics. It can also handle exception packets that require complex additional processing. At OC-192 speeds, if carriers and network service providers are to provide new services and bill their customers accordingly, Intel estimates that deep packet inspection must occur within a short time window of around 35 nanoseconds. Within this interval, the network processor must execute all the pertinent and relevant layer 3 through layer 7 applications on these packets and then transmit them in the correct sequence (not to mention at the correct speed rate) and without bit losses to their destina- tion. Intel uses a store-and-forward architecture that lends itself well to this model. The speed of the second-generation NPUs is more than enough to handle the 10 Gbps wire speed. The highly parallel processing afforded by