marred by a number of adverse properties, This process continues, passing through as many cycles as there SO more complex designs are sometimes used (Wallace et al., 1991). are bits in the storage register, with each pass determining whether the input voltage lies in the upper or lower half of the range selected 19.4.2 The coder in the previous cycle. The storage register then contains the ADC conversion value. The analogue sampler performs the transformation from continuous The successive approximation ADC must perform several oper- time to discrete time representation. The coder or analogue to digital ations in sequence to encode each sample. For high sampling rates converter (ADC) performs the complementary operation of trans- (e.g. above 1MHz), in order to reduce the conversion time, it is formation from continuous amplitude to discrete amplitude. There necessary to use a circuit which requires fewer operations to be are a variety of techniques which may be used in an ADC, such as performed. Signal input Signal output Sample input Figure 19.15 Simple sample-and-hold circuit 19/14 Digital modulation Binary decision X 1 if x>y Analogue input Sample Comparator Regenerator output Clock Digit store source Figure 19.16 Successive approximation ADC The flash converter, shown in Figure 19.17, consists of a chain of 1 V reference. The comparators thus compare the input voltage with fast comparators, with one input of each comparator driven by the 1/16V, 1/8V, 3/16V and so on. voltage to be converted. The other input of each successive com- The comparator outputs are then passed to a priority encoder, parator is connected to the corresponding point of a resistor chain, which determines the position of the last comparator in the chain to containing as many resistors of equal value, as there are compara- indicate that its reference voltage is lower than the flash encoder tors. The number of comparators, and hence resistors, in the divider input voltage. This indicates directly which segment of the conver- chain, is equal