leted silicon on insulator (RF-SOI/FD-SOI) is a semiconductor technology which realizes fully/partially depleted CMOS devices on SOI and combines the flat structure of 2D CMOS transistors with the fully depleted mode of SOI. The SOI has a good power-performance-area-cost (PPAC) value. It uses a unique type of substrate material whose thickness is controlled to atomic scale and could provide excellent transistor perfor- mance. The FD-SOI technology can operate in mmWave frequencies, thus it is gaining more attention in practical 5G mmWave applications. Packaging processes which are available and in production for RF analog components are Quad Flat No-leads (QFN) Package, embedded Wafer-Level-Ball (eWLB) Grid Array Package, Flip Chip. However, the existing mmWave RF components are mostly bare die or modules. The eWLB examples with System in Package (SiP) demonstrate that assembly and packaging using the eWLB technology offer outstanding system integration capabilities. This includes the integration of different chips and the design of integrated pas- sive components such as resistors, inductors, and transformers either in the redistribution layer (RDL)24 using through encapsulate (TEV). Antennas integrated into the package. Other technologies where silicon wafer level technology and back-end merge are through silicon via (TSV)20 and die embedding in laminate technologies. TSV technologies are typically combined with RDLs, for example, for silicon interposer. However, a major obstacle against their broad adoption is cost [23]. The evolution of RF analog components integration for mmWave applications depends on several factors including the following: Permissible output power and EIRP of the system including the antennas Phase noise required for standard modulation schemes (BPSK, QPSK, 16QAM, 256QAM, etc.) Noise figure Power consumption Form factor and cost eWLB grid array is a packaging technology for integrated circuits. The package interconnects are applied on an artificial wafer made of silicon chips and a castin