am of packets is then processed by multiple high-performance, fixed-cycle pipes. Each pipe is com- posed of multiple engines (which are non-RISC-based in this case) that execute simultaneously, Data n Data n-1 Data 1 Execution Execution Execution engine engine lengine Execution Execution Execution engine engine engine Execution Execution Execution engine engine engine Execution Execution Execution engine engine engine Execution Execution Execution \engine engine I engine Processed data that traversed the series of pipes Incoming data Gets "de-verticalized" and gets "verticalized" proceeds to the output horizontally FIGURE 9.2 Vertical Instruction Processing (VIP) inside the Montego NPU. (Source: Bay Microsystems) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES 144 NETWORK PROCESSORS thereby eliminating the nondeterministic characteristics of sequentially programmed RISC core engines such as the ones found in other network processors. Each pipe executes a series of operations on the data stream. It then passes the data stream onto the next pipe in line. Each engine within a pipe is responsible for executing a particular network feature. By enabling (turning on) or disabling (turn- ing off) the engine that is associated with a specific feature, that specific feature is applied on the processed packet or it is simply skipped. In Figure 9.2, inside the first stage of pipes (shown as an oval) where the classification and policy instructions are executed, the data is subjected to engines that will parse and search, filter, and per- form statistics. When the data is moved to the next stage of pipes, a traffic management set of instruc- tions will take place. The data is then subjected to shaping and marking, and executing algorithms such as WRED and weighted fair queuing (WFQ). Farther down the horizontal path, the data is t