ses simulation times over multiple-device techniques and greatly increases the complexity of the external circuitry that can be modeled. Mixed-level capability has been incorporated into many of the commercially- available 3D device codes [245,281-283]. These codes were first used to study SEU in CMOS SRAMs in 1991 [294], and since then have received a great deal of continued use for this purpose [51]. II-52 Circuit Particle Simulation Strike Device Simulation Figure 5.4. Mixed-level simulations solve the device and circuit equations simultaneously, taking advantage of the localization of the ion strike. Only the struck device is modeled in the multidimensional device domain, reducing the computational burden. 5.2.2 Recent Enhancements A drawback of the mixed-level method is that coupling effects between adjacent transistors have been shown to exist at the device level using 2D simulations [258]. These effects cannot be taken into account when only the struck device is modeled at the device level. To address this difficulty, a recent paper has described simulation of the entire SRAM cell in the 3D device domain [295]. An illustration of the technique is shown in Figure 5.5 (interconnects between device regions are defined in the usual manner for an SRAM cell, but are not shown in the illustration for clarity). The authors compared the results to standard mixed-level simulations and found that in cases where no coupling effects between transistors existed, mixed-level simulations were adequate to reproduce the full SRAM cell results. For some strike locations, however, coupling effects between adjacent transistors were observed [295]. Mixed-level simulations are incapable of predicting such effects. As inter-device spacing decreases with increasing integration levels, coupling effects can be expected to become more important, and simulating entire the SRAM cell in the device domain may become routinely necessary [295]. Techniques like mixed-level simulation are useful for in-depth studies of SEU in specific small-