the row and column strobe signals. After waiting a certain amount of time called the access time, the DRAM either would pres- ent the corresponding data at its output for the processor to read or would write new data provided from the processor into that location, depending on the operation performed (read or write). However, as processors became faster, memory caused a bottleneck and the processor was forced to wait for DRAM memory to deliver results. It was subjected to artificially inserted, idle, or wait states. Meanwhile, the processor could do other useful things if it was free. By making DRAM synchronous (and therefore activated by an external clock), latches were inserted at the DRAM inputs and outputs SO the information presented by a processor could be effec- tively latched on until the DRAM core was able to handle it. In the meantime, the processor was free to do something else. As soon as a read operation was finished, the results were latched on at the DRAM output for the processor to return and read it at its convenience. Of course, other architectural breakthroughs slowly appeared, such as the pipelining of addresses, the prefetching of data, and even the use of multiple modes (such as page mode, burst mode, and SO on). The judicious combination of these breakthroughs has led to further improvements of DRAM performance in conjunction with ever-increasing performance of processors. Ample information on this evolution is provided in the references at the end of this chapter. Most network processors use DRAM in order to store packets. As packets must be written to and then read from memory, the memory system bandwidth must be twice as fast as the intended wire- speed performance. As a gauge of the cost and complexity involved, we will mention the obvious fact that if a system must be able to buffer (for safety) the equivalent of one second of full-capacity wire- Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All