lt, aggregate bandwidth performance can reach a rate of terabits per second. BMU The BMU is 139 bits wide based on 128 bits of data, 9 bits for error correction coding (ECC), and 2 control bits. The size of buffer memory under its supervision can be up to 128MB. XP The XP handles supervisory tasks and is also a 32-bit RISC CPU core. It is equally program- mable in C/C + + with the same instruction set as the RISC cores that are inside the 16 CPs. Externally, it provides support for a 32-bit3 33/66 MHz Peripheral Computer Interconnect (PCI) bus and a serial programmable read-only memory (PROM) interface, along with a two-wire serial bus interface that supports 400 Kbps links. As shown in the architectural structure of Figure 8.1, several internal communications buses can be found in the C-5e network-processor chip: The payload bus is 128 bits wide, transfers 64 bytes at a time, and can handle a throughput of up to 34.1 Gbps. The ring bus is 64 bits wide, transfers anything from 8 bytes to 32 bytes, and can handle a through- put of up to 21.1 Gbps. The global bus is a 32-bit bus that can transfer 4 bytes at a time with a maximum bandwidth of 4.2 Gbps. The M-5 Channel Adapter supports a 5 Gbps aggregate and can be configured in 1 to 48 ingress channels. It essentially maps external links onto C-5e channels, and vice versa. For instance, an OC- 1 link maps as three M-5 ingress channels to one C-5e CP channel, whereas an OC-3c maps as one M-5 ingress channel to one C-5e CP channel, an OC-12c link maps as one M-5 ingress channel to one C-5e CP cluster (four CP channels), and an OC-48c link maps as one M-5 ingress channel to four C- 5e CP clusters (16 CP channels). An OC-48c can also map as one M-5 ingress channel to one C-5e FP channel, if it is connected onto the FP instead. The M-5 handles packet data units (PDUs) that are 52 bytes long for ATM cells. For POS, the packet length can vary from 28 bytes to 9,216 bytes. Figure 8.2 shows a typical configuration of a router system based on the Motorola C-5e network process