the previously integrated DASL ports of the NP4GS3 are now replaced by a CSIX-L1 for the interface with a switch fabric, whereas a couple of look-aside interfaces imple- mented according to the NPF LA-1 specification allow the support of either external coprocessors or quad data rate (QDR) SRAM memory. Cleverly, the memory controllers of the multiple DRAM chan- nels of the NP4GX have been designed to also support fast cycle RAM (FCRAM), in addition to the native DDR SDRAM. The NP4GX network processor's package will be a HyperBGA replacing the ceramic package of the NP4GS3. It is estimated that it will consume around 10 watts. IBM released the first samples of this network processor in early 2003. TRADE-OFFS WHEN DESIGNING WITH NP4GS3 Designing high-speed network equipment with the IBM NP4GS3 network processor brings some clearly discernible advantages to the designer, but he or she must face some trade-offs as well. On the positive side, the performance afforded by the NPU architecture is flexible, fast, and scal- able. The behavior choices implemented in picocode are endless. Customers can easily implement differentiating features into their products by simply developing the appropriate picocode in the NPU(s) they use. Beyond that, however, IBM's fine-tuning of the robust internal systems design 3. http://www.tollygroup.com. 4. http://www.npforum.org. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. IBM POWERNP™ 74 NETWORK PROCESSORS makes the need for the customers to design their own optimized networking ASICs a problem of past. The NP4GS3 is SO integrated with ancillary functionality, such as traffic management, MAC lay- ers, and switch fabric interfaces, that a whole Gigabit Ethernet line card can be produced simply by adding PHY chips and memory. IBM's software is not only tested, but it is also fully validated. This means that customer