ombine both approaches in a hybrid clocking architecture, whereby fre- quency is carried with SyncE and phase synchronization with PTP packets. "Chapter 7. Precision Time Protocol", delves into this a little more. A physical link failure (or fault) will break the frequency distribution via SyncE or interrupt the PTP packet path between slave and master. During such events, the slave clock will start slowly "drifting" away from the reference or master clock. This frequency and phase drift, besides depend- ing on many external factors, also depends on components used for the local clock and the charac- teristics of the PLL circuitry. Obviously, it is desirable for the drift from the reference clock during holdover to be small, although "small" is not a helpful measure and SO it is defined in more quantitative terms. The measurement of holdover performance is done when either one, both, or all clock sources (frequency and phase) are removed, and the output of the slave clock is measured against a reference signal from the master clock. The ITU-T recommendations specify MTIE and TDEV masks to compare the accepted holdover performance for each clock type (the masks are not as strict as the masks used when the clocks are locked to an external reference clock). Two major factors determine holdover performance. These are primarily the internal components of a clock or PLL and secondly the external factors that could impact the clock output signals. Among the components, the oscillator (chiefly its stability) plays the most important role in providing better holdover performance from a clock. For example, a clock based on a rubidium (stratum 2) oscillator or an OCXO (stratum 3E) oscillator will provide better holdover characteristics than a stratum 4 oscillator. Similarly, smaller variability in environmental conditions (especially temperature) during the hold- over period will result in better holdover characteristics. For example, rubidium oscillators are very stable, but they are susceptible to being less SO when expos