sly improving processors speed t, the bus becomes the bottleneck of the router, as evident from Equation 7.43. Considering the architecture of Figure 7.54 from a different point of view, it is clear that the bus appears to be a time domain switch fabric with input queues and distributed processing. If the switch fabric becomes the bottleneck it is needed to substitute it with a faster switch fabric. This can be done by passing from time domain switching to space domain switching; since historically this architecture allowed to introduce routers with multigigabit capacity we will call this type of machines multigigabit routers (MGR). The block scheme of an MGR is reported in Figure 7.55. The line cards are connected via a space division strictly nonblocking switch fabric with a set of forwarding engines real- izing a distributed processing space switch architecture. Also a bus connects all the units of the router, but it is used for commands and configu- ration and for exchanging information like the routing table update. Datagrams never are transmitted through the bus. Every forwarding engine can process a different packet since each has a completely updated replica of the routing and the forwarding tables. The packets are assigned from the line cards to the forwarding engine by transferring to the engine the corresponding header for the forwarding calculation in a round-robin fashion. Since in some applications QoS requires that packet order is maintained, the output con- trol circuitry also goes round-robin, guaranteeing that packets will then be sent out in the same order as they were received. The forwarding engine returns a new header (or multiple headers, if the packet is to be fragmented), along with routing information (i.e., the immediate destination of the packet). Then the input line card integrates the new header with the rest of the packet and sends the entire packet to the output line card for transmission. Switching Systems: Architecture and Performances Also the central processor is connected to t