etection, and correction techniques discussed above for spatial redundancy. This technique is highly effective in tolerance to transient fault conditions, such as the errors introduced by single event upsets and electrically induced corruption; it is of little value in mitigating permanent fault conditions (obviously, due to the use of the same faulty hardware or software to perform both operations). The technique also is dependent upon the requirement for known error-free conditions on the input signals or variables used in the operations. Either independent detection and correction must be provided to inputs, or the use of alternating logic techniques or complementing functions must be utilized to provide tolerance to input signal or variable errors. Alternating logic utilizes a class of boolean functions which are self dual, i.e. they satisfy the property f(x1_ X2. Xn. = X2, Recomputing with shifted operands (RESO) is applicable to certain problems in which the shifting of inputs forms a complementing function which produces known relationship in outputs which may be utilized in detection and correction. 6.4.2.3 Combined Redundancy Implementation [Mavis98] The use of static spatial redundancy as a fault tolerance technique for single event upsets in memory elements (latches, flip-flops, and RAM), along with temporal redundancy as a mitigation provision against single event transients in combinatorial logic has been proposed for advanced technology devices. The increased bandwidth provided by advanced technologies provides opportunity for propagation of transient pulses which result from energetic particle strikes on combinatorial logic nodes. The increased bandwidth of these technologies also enables the use of high clock rates; 200 MHz to 400 MHz in present day commercial production technology. In older technologies, the 100 ps to 200 ps transient pulses would not propagate along a path of combinatorial logic gates; the bandwidth of advanced technologies supports propagation of such pulses, and the high clock