Figure 6-10) are as follows: The node clocks are interconnected via N network elements, each being a clock compliant to ITU-T G.813. The maximum value of n is determined by the quality of timing required by the last network element in the chain. This also means that the quality of timing synchronization deteriorates for each hop as the number of synchronization links increase. The longest chain should not exceed k SSU/BITS type clocks, those compliant to ITU-T G.812. As shown in Figure 6-10, there could be n number of G.812 clock nodes between (K-1)-th and K-th SSU/BITS clock nodes. Note that only one type of clock is shown because the differ- ence in holdover performance between SSU-T and SSU-L (the two clock types defined under ITU-T G.812) is no longer relevant in SDH network synchronization. The worst-case synchronization reference chain values allowed are k = 10 and N = 20. And the total number of SDH network element clocks in one synchronization network chain is limited to a maximum of 60 elements. 6.8 Clock Selection Process A good timing distribution network is designed such that more than one frequency source (or mas- ter clock) is available to the slave clock, providing one or more backup timing signals during clock outages, which can occur for a variety of reasons. When more than one frequency source is avail- able, the slave clock needs to make a decision to pick the best clock from those available to it. This decision is a result of a well-defined process, referred as the clock selection process. Two different modes of selection process are possible: QL-enabled mode and QL-disabled mode. As the names suggest, QL-enabled mode is relevant in deployments where SSM messages are ex- changed and interpreted by the NEs. It means that there is QL information available to assist in making a clock selection decision. With QL-disabled mode, either QL information is not available or the engineer chooses not to use it. The process itself does not change much between these two modes, except for the fact that SSM m