responsible for MBU in DRAMs was lateral diffusion of the ion-induced charge to multiple junctions. Funneling can increase charge collected at the struck node, reducing the charge available for diffusive transport to adjacent nodes [115]. Zoutendyk et al. found that for the small capacitances typically associated with individual storage elements, funnel-assisted drift collection for direct hits on a storage node is very limited. For direct bit-line hits with larger nodal capacitance, however, substantially reduced charge collection at adjacent nodes was observed [110]. Ion tracks that do not hit a junction therefore allow the greatest amount of lateral charge transport and constitute the worst-case strike location for MBU [110]. The issue of MBUs in SRAMs has also been studied using simulations [60,117]. In [60], two adjacent SRAM cells were simulated, and the strike location was varied to determine the region of sensitivity to multiple-bit upset from normally-incident heavy ion strikes. A simulated error map was produced showing the region of vulnerability to MBU, as shown in Figure 3.14. Only strikes incident between the two cells were capable of producing MBU for the ion strikes simulated in this work. Strikes directly incident on the drain of one cell resulted in upset of the struck cell, but insufficient charge was collected at the adjacent cell to cause upset. The mechanism for multiple-bit upset in the simulated SRAMs thus was found to be diffusion from between-cell strikes, similar to the DRAM results [60]. For grazing angles of incidence and very closely-spaced cells, however, drift collection and funneling can be expected to play greater roles. Figure 3.13. Physical map of a cluster of errors due to single-event multiple-bit upset in a 256K DRAM [110]. Error locations are shown as solid black capacitor regions, while outlined capacitor regions indicate bits without errors. II-24 Drain Drain Source Source Strike here upsets both cells Strike here upsets a single cell Figure 3.14. Simulated multiple-bit u