d of compute intensive compo- nents of the processing stack. Networking-centric offloads often include: Acceleration of ciphering algorithms. This includes both IPSec acceleration as well as ZUC/SNOW/AES 3GPP f8/f9 encryption and authentication. Ciphering can be supported through optimized ISA support where modern Arm and x86 architectures both support dedicated AES instructions (but no ZUC/SNOW) or through a look-aside accelerator that performs these operations autonomously once its drivers have been integrated into the application. Some processors offload not only the cipher algorithms but in fact the complete (IPSec, networking) protocol stack through an embedded Network Processor that is customized per vendor and application. This offload provides best possible performance per Watt but comes at the cost of integration efforts and is unique to each vendor. This vendor lock-in may be undesirable. Acceleration of Networking Quality of Service. Software implementations of (wireline) Quality of Service algorithms such as Ethernet policing and shaping are notoriously CPU intensive and limited in their capabilities. Most Network Interface Cards or on-chip integrated Ethernet controllers include hardware capabilities for some QoS offload. Not all are easily mapped to 3GPP or application use-case requirements. Artificial Intelligence (AI), Machine Learning (ML) and other math-centric offload. The 5G application space is not only about implementing a wireless connection but about intelligent use of user data. Consider location-based services, low-latency edge compute and similar applications that fashionably use AI/ML. If the edge application is integrated with the networking processor (stack host), it requires efficient support for these applications, which implies access to (or integration of) AI/ML capabilities. PCle performance Given that PCIe is a key interface used in O-RAN and SO many other embedded applications, we will discuss this standard and related performance topics here. Different versions of the PCIe st