DRAM & CONTROL STORE SWITCH Ports SWITCH Ports Ingress En / Egress En / Dequeue Dequeue I-SCI E-SCI Scheduler Scheduler E-SDM Switch Interface INTERNAL S-RAM INTERNAL EMBEDDED External CONTROL PROCESSOR INSTRUCTION STORE COMPLEX STORE Shaper Control Store ETHERNET PHY or POS FRAMER FIGURE 4.3 The internal block structure of the IBM NP4GS3 network processor. (Source: IBM) The I-EDS stores frames from the DMUs into the data store. It performs some filtering decisions and frame alterations, such as VLAN tags. It then dequeues the frames from the data store and sched- ules them to be forwarded or discarded. This happens when the target NPU or the switch fabric indi- cates to this NPU that they are running low on resources. The SWI provides a data cell-based interface between NPUs either via switching fabric (for three or more NPUs) or direct wire connections (for one or two NPUs). The SDM and the SCI for both the ingress and the egress path convert the output of the EDS logically into a cell flow, and vice versa. They also provide/receive cells to/from the PHY. The DASL is IBM's fast method for implementing the physical interface between the NPU and the switch fabric, between the ingress and egress sides of one NPU, or between the ingress and egress sides of two NPUs. The E-EDS receives frames through the switch interface. It reassembles them because they arrive in a cell flow. It then enqueues the resulting frames into its data store where extensive frame processing is provided. It finally dequeues the frames from the data store and schedules them to be forwarded. The Traffic Shaper manages bandwidth on a per-frame basis for all egress DMU ports. It is an optional NPU component and can be configured by software. It implements weighted fair queuing (WFQ) regulation for up to 2K queues, which sustains a good performance in a Differentiated Services (DiffServ) environment. The Shaper discards traffic depending on its configuration and based on sev- eral algorithms such as RED and WRED. Downloaded from Digital Engineeri