H IP CORES ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES (increasing the size of the underlying hardware core), but allowing the design to stay more predictably close to the one-cycle execution rate objective of native instructions. These two latter examples are not in the same MIPS league as ClearSpeed's MTAP, which outperforms both of them by orders of magnitude. However, we are referring to customizing instruction sets in order to optimize application performance. We consider architecture/performance trade-offs involved in designing a system with various approaches. We conclude our discussion on ClearSpeed's technology by saying that with all the computational power of its technology, it is not a coincidence that the company has pushed the emphasis of original applications on core networks that require 40 Gbps performance, but do not necessarily need intricate deep packet processing. As the technology can be scaled down rather easily, users will most likely come forward with designs that implement in-house-designed network-processing chips performing more elaborate tasks outside the core and at the edge level. Indeed, much of ClearSpeed's initial customer interest has been at lower line rates, from 2.5 Gbps to 10 Gbps, but with high levels of func- tionality-what the company affectionately calls the high touch. Other computationally heavy appli- cations (from the network-processing arena) besides wire-speed classification/routing and quality of service (QoS)-based traffic management will also most likely emerge soon. We will examine some of these applications later in this book. TENSILICA The other side of the IP licensing spectrum, as applied to the network-processing realm, has a couple of promising IP companies. Tensilica (www.tensilica.com) apparently has the most significant tech- nology proposition. Because the company has created a new paradigm of the design flow, we will dis- cuss the actual look and feel of designing a configurable processor CPU with this technolo