ned to be either synchronous or asynchronous and the distribution of a global synchronizing clock signal from the control proces- sor board can become a very serious issue for the system designer. The links typically perform at 2.5 Gbps, although manufacturers sometimes quote the speed at 3.125 Gbps. A trend to design 5 Gbps links in the next-generation backplanes also seems to be appearing. Current backplane high-speed serial links are implemented with fast switching bus drivers designed around various high-speed, low-impedance, circuit technologies such as low-voltage differential signaling (LVDS),2 current mode logic (CML), and differential-mode positive emitter coupled logic (DM-PECL). We will not expand on these circuit techniques here. See the references provided at the end of this chapter for more information. 2. For instance, Agilent Inc. provides a nice series of white papers with a solid introduction to the theory and advantages of LVDS in signal integrity contexts (serdes). Seewww.measurement.tm.agilent.com/insight/2000_v5_i2/insight_v5i2_article01.shtmland www.measurement.tm.agilent.com/insight/2000_v5_i3/insight_v5i3_article05.shtml.Vitesse also offers several helpful white papers and application notes explaining this technology in detail. See www.vitesse.com. 3. Any good advanced microelectronics textbook provides ample description of CML technologies. Some examples are provided in Chapter 3, "Packet Processing." An interesting presentation can be found at www.bol.ucla.edu/~ive/ee215b.htm. 4. Good textbook sources of analog integrated circuit design also cover this subject in detail. However, an application note from Philips explains the basics of both PECL and LVDS. See www.philipslogic.com/support/appnotes/an253.pdf. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SWITCH FABRICS SWITCH FABRICS 277 We mentioned the presence of