the Xtensa architecture for some networking applications. (Source: Tensilica) More specifically, we compare EEMBC NetMarks/MHz of out-of-box scores for Xtensa and sev- eral other architectures, where the IDT 32334 (MIPS32) at 100 MHz has a performance reference of 1.0. Out-of-box means as shipped by the vendor and without any customer-performed architecture optimization. The results shown in Figure 10.6 indicate that Xtensa, even without any networking- specific extensions, consistently has twice the performance of some major alternative 64-bit RISC and Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES 180 NETWORK PROCESSORS Optimized NetMark Performance Xtensa 300 Xtensa 350 ARM 1020- MIPS 64 M32 (NEC optimized out-of-the-box EJ-S 266 VR4122) 180 VR5000) 250 FIGURE 10.9 The performance increase that is obtained from properly configuring the Xtensa to suit the needs of the networking application at hand. (Source: Tensilica) three times the performance of 32-bit RISC architectures. 4 Out-of-the-box testing is good because it gives a first good feeling about a basic architecture as well as the quality of the compiler. This per- formance difference is further magnified by the clock frequency advantages of the Xtensa pipeline, as shown in the absolute NetMark performance, which is shown in Figure 10.7. Figure 10.8 shows the performance of the same networking applications, but this time it includes Xtensa optimized for packet processing. Looking at results per MHz provides a better idea of the architectural efficiency. These optimizations are small but highly effective, adding less than 14,000 additional gates (less than 0.2 mm² in area) to the processor. The extended Xtensa processor achieves about 7 times the cycle efficiency of a good 64-bit RISC processor core a