92 Queue Manager with its CSIX interface on one side toward the NPU. Figure 14.14 shows the inner structure of the C192. This C192 will convert the traffic to and from an HSS link that supports the Switch Core Interface Chip (SCIC) chip (discussed in the following paragraph) and which in turn interfaces with the switch fabric. Figure 14.15 shows these configurations. It is worthwhile to note that the standard CSIX-L1 interface of the C192 ensures that non-IBM network processors can be used with the IBM switch fabric chips. The potential of this interoperability is already apparent with EZchip's NP-1 network processor. IBM also provides as we said, a new chip called Switch Core Interface Chip (SCIC). This chip allows the portability of line cards that were designed for the previous PRS product (the 64G), SO that they can now be upgraded to take advantage of IBM's new 2.5 Gbps serdes used with the Q64G. As shown in Figure 14.16, the SCIC interfaces via a DASL link on one side with the older 64G switch fabric and on the other side with the C192 Queue Manager via an HSS link (in fact, a group of eight 2.5 Gbps links). The diagram in Figure 14.16 is straightforward. Data coming in on the ingress flow 8 HSS (ex Unilinks) Ingress flow serial output 2.5 Gbps each resync PowerPRSTM Q-64G PowerPRSTM resync IBM PowerPRS TM C192 8 HSS (ex Unilinks) serial output Egress flow 2.5 Gbps each FIGURE 14.14 The inner structure of the IBM PowerPRS C192 Queue Manager. (Source: IBM) 27. Ibid. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SWITCH FABRICS NETWORK PROCESSORS Backplane PowerNPTM Physical NP4GS3 PowerPRS Optical layer Network 64G's device Processor Utopia-3 IBM Packet OC-48 Protocol Routing Switch optical Framer Engine Serial Interface Converter Layer2, Layer 3, or Layer 4 Switching Engine OC-192 Physical Protocol PowerPRS PowerPRS Optical layer Engi