n Figure 5.9. It means that the signal sequence present in the loaded MSC has been simulated. You can see that the trace MSC is identical to the loaded MSC. Note that if the simulated parameter values did not match the MSC expected values, the MSC property would not have been satisfied. 3 The MSCs can also be verified using the Simulator rather than the Validator. Automatic Observation of Simulations 119 Navigator Up 1: Transition START Pld : <<Block DLCa>> dispatch:1 State : ready Input DLCstopped Sender Stopped Pld Parameter(s) : 0 No down node MSC Test1 verified Figure 5.9 The MSC test1 is verified 5.2.3 Simulate with an MSC containing inline operators The basic MSC testl used in the previous section represents only a single execution sequence. To represent several expected behaviors consistent with the V.76 textual specification without creating too many basic MSCs, we will add inline operators to the MSC testl. 5.2.3.1 Create the MSC With the MSC Editor, you will rework a copy of the basic MSC testl.msc generated by the Simulator in Chapter 4, to obtain the MSC testlinline.msc, shown in Figure 5.10: A. In Windows (or Unix), make a copy of the file testl.msc into testlinline.msc B. In the Organizer, select Tools > Editors > MSC Editor C. In the MSC Editor, select File > Open and choose testlinline.msc D. Enter the MSC name testlinline, and remove the XID part (eight signals from L_SetparmReq to L_SetparmConf). E. Using copy-paste, duplicate the data transfer part, arrange the pasted signals to reverse the originating side of the second data transfer, and replace 86 by 39, as shown in Figure 5.11. F. Using opy-paste. duplicate the DLC release part and arrange the pasted signals to reverse the originating side of the second release: release originated by B. G. Using the Symbol Menu, insert one loop and two alt inline operators, depicted in Figure 5.10. Resize them and add two expression separators, to obtain the layout shown in Figure 5.11. 120 Validation of Communications Systems with SDL loop <0, inf> loop op