with hardware and instruction sets optimized for DSP operations. 2. Special-purpose DSP processors: These include both hardware designed for efficient execution of specific DSP algorithms like FFT or feed-forward equalizer (FFE)- decision feedback equalizer (DFE) filtering and hardware designed for specific applications like forward error correction (FEC) coding-decoding. Technology for Telecommunications: Integrated Optics and Microelectronics 5.7.4.1 DSP Hardware Architecture In most of the applications requiring the use of a DSP, digital algorithms like digital fil- tering and FFT involve repetitive arithmetic operations such as multiplication, additions, memory access, and heavy data flow through the CPU. The Von Newman architecture of standard microprocessors is not suited to this type of activity due to the fact that heavy mathematics without any access to the memory or to the input/output interfaces of the system practically nullify the ability of the processor to share the computation power among different processes exploiting the time each process takes to access the memory or the peripheral devices of the system. DSPs overcome this difficulty by a hardware architecture that exploits a sufficient degree of parallelism SO as to avoid the intense mathematics that will destroy the proces- sor performance. An example of basic DSP architecture is shown in Figure 5.49; this is a particular imple- mentation of the so-called Harvard architecture [64] and exploits different levels of paral- lelism to speed the real-time processor operations: Program memory is separated by the data memory, thus massive data transfer does not collapse the transfer of program instructions to the arithmetic-logical unit (ALU). Moreover, in a standard microprocessor, where the program codes and the data are held in one memory space, the fetching of the next instruction while the current one is executing is not allowed, because the fetch and execution phases each require memory access. On the other hand, since the execution of an instr