mination process. If you read the first 10 chapters of this book, you will see the appli- cability of several network-processor architectures in this field. From a systems architect's point of view, plenty of room is available for subjective choices. We will now look at some implementations. We will first provide an example from Adaptec, a leading provider of TOE technology. According to their estimates, an ASIC implementation of TOE provides sustained transmission rates of 900 Mbps to 1,000 Mbps with host CPU utilization of less than 20 percent, as opposed to board-based products delivering TOE functionality. Although the host CPU utilization remains at the same level (< 20 per- cent), these products can only sustain about 650 Mbps of traffic. In April 2002, Adaptec also announced that one of its products (ANA-7711 TCP/IP Offload Adapter) sustains 226 MBps throughput of variable-packet-size traffic, including packets that are as small as 512 bits. This prod- uct, whose block structure is shown in Figure 11.5, is a board that contains the company's storage EEPROM 125 MHz SDRAM oscillator 32 MBytes Storage Protocol Opto- Gigabit Electronic SDRAM Ethernet Accelerator Transmitter 32 MBytes serdes Receiver (SPA) 64-bit/66-MHz PCI bus FIGURE 11.5 The block structure of Adaptec's ANA-771 TCP/IP Offload Adapter. (Source: Adaptec) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. STORAGE NETWORK PROCESSORS (SNPS) STORAGE NETWORK PROCESSORS (SNPs) 209 protocol accelerator (SPA), a highly optimized TOE, and a 1 Gigabit Ethernet MAC. This level performance means that full-duplex (and almost saturated) Gigabit Ethernet traffic can be sustained in storage network processing using this level of TOE technology. Adaptec has used several of these techniques in its ANA-7711 TCP/IP Offload Adapter to provide a cutting-edge solution. As shown in Figure 11.5, the 