ssembly. A good compromise for high-end applications (e.g., E-band high power, 256QAM) is to use compound semiconductors for the front-ends (LNA of the receiver input and PA of the transmitter output) and silicon semiconductors for the lower frequency mixed signal functions and control/digital elements. The III- V compound devices can realize systems to expand the use of the electromagnetic spectrum above 90 GHz. However, improve- ments in the high-frequency capability of CMOS/BiCMOS technology have made it possible to consider it as a low-cost, lower performance alternative to III-V compound devices. 5.6.2 Analog Front-End Design Considerations The baseband modems utilize digital signal processing to perform channel coding and complex-valued modulation and demodulation in order to transmit extremely high data rate streams over RF carriers in mmWave bands. For backhaul applications with data rates ranging from 1 to 10 Gbps, the systems typically utilize channel bandwidths of 250 and 500 MHz which have recently increased to 1 and 2 GHz to support integrated access and backhaul applications. The baseband modulation schemes, generating complex-valued symbols, range from BPSK, QPSK, 16QAM and up to 256QAM (or higher) for high-performance systems. Therefore, it is necessary to perform real-time I/Q ADC (receive) and I/Q DAC (transmit) at the interface between the analog and digital domains. Moreover, such data conversions require low jitter baseband clocks in order to minimize inter-symbol interference. The combination of I/Q ADC, I/Q DAC, and baseband phase-locked loop (PLL)2 is known as AFE as shown in Fig. 5.25. The performance of the AFE has a significant impact on the overall performance of the modem in terms of the receiver dynamic range, transmitter spurious emissions, and end- to-end bit error rate/packet error rate (BER/PER). A PLL is a closed-loop frequency-control system based on the phase difference between the input clock signal and the feedback clock signal of a controlled oscillator. The main blocks of 