fied gets bigger). They are useful where table sizes are small (storing large lookup tables in CAMs is prohibitively expensive in terms of cost and power). They are helpful where lookup latency is critical (although latency can often be hidden with a suit- able use of pipelining and threads with memory-based approaches). Search Engines When wire speed becomes SO high that an external SRAM is not the best approach (OC-48 and above), an integrated search engine must be considered. This is either a TCAM implementation or part of a dedicated classification processor with the appropriate system speed design. The newer switching/routing systems are based on network processors; therefore, the interface between NPUs and search engines poses a real challenge. Some current designs are implemented around cumber- some field-programmable gate arrays (FPGAs) that are meant to replace a sea of glue logic. Several standardization efforts are currently under way to address this problem, as we will see later in Appendix III in the discussion about standardization. Some search engine vendors interface their engines to the NPU through a memory interface SO that the NPU is essentially fooled to believe that it communicates with an ordinary memory bank. The leading providers of search engines include IDT, NetLogic Microsystems, SiberCore, and Kawasaki LSI (KLSI). Typical search engines offer the possibility of about 100 millions of searches per second (Msps), but this number is rapidly increasing. If a certain piece of switching/routing gear requires bandwidth that is higher than 100 Msps, multiple search engines may be used. They can either be centrally located in the switch/router (a demanding proposition for high-speed links), or the designers can include a search engine on each line card, reducing the performance constraints on the search engine, which is most often the case. The key size is nowadays usually 72 bits; however, with the appropri- ate soft configuration at half the clock speed, search engines will usually also work w