erican digital hierarchy is illustrated in Figure 6.13. The higher-level mul- tiplexers are type-coded in such a way that we know the DS levels (e.g., DS1, DS1C, DS2, DS3, DS4) that are being combined. For instance, the M34 multiplexer takes four DS3 bit streams at its input to form the DS4 bit stream at its output. We describe the operation of the M12 multiplexer because it typifies the series. The formation of the second-level North American multiplex, DS2, from four DS1 inputs is shown in Figure 6.14. There are four inputs to the M12 multiplexer, each oper- ating at the nominal 1.544-Mbps rate. The output bit rate is 6.312 Mbps. Now multiply 1.544 Mbps by 4 and get 6.176 Mbps. In other words, the output of the M12 multiplexer is operating 136 kbps faster than the aggregate of the four inputs. Some of these extra bits are overhead bits and the remainder are stuff bits. Figure 6.15 shows the makeup of the DS2 frame. The M12 multiplex frame consists of 1176 bits. The frame is divided into four 294-bit subframes, as illustrated in Figure 6.15. There is a control bit word that is distributed throughout the frame and that begins with an M bit. Thus each subframe begins with an M bit. There are four M bits forming the series 011X, where the fourth bit (X), which may be a 1 or a 0, may be used as an alarm indicator bit. When transmitted as a 1, no alarm condition exists. When it is transmitted as a 0, an alarm is present. The 011 sequence for the first three M bits is used in the receiving circuits to identify the frame. It is noted in Figure 6.15 that each subframe is made up of six 49-bit blocks. Each block starts with a control bit, which is followed by a 48-bit block of information. Of these 48 bits, 12 bits are taken from each of the four input DS1 signals. These are interleaved sequentially in the 48-bit block. The first bit in the third and sixth block is designated an Original signal Stuffed signal Represents stuffed pulses Stuffed signal received to be multiplexed and demultiplexed Destuffed signal after smoo