uction requires fetching and decoding before the effective execution phase, it would contribute to speed up operations if the fetching phase would be carried out contemporary to the execution of a previous instruction. This is possible if data memory and program memory are separated and exploit separate busses. Thus, in a DSP with the architecture of Figure 5.49 two instructions are contempo- rary under processing in the ALU, one is executed, the other fetched. Multiplier accumulator A data B data Program memory memory memory Shifter Program bus A-data bus B-data bus Input/output interfaces FIGURE 5.49 Architecture of a basic DSP. Telecommunication Networks In many DSPs the pipeline process, which is the process constituted by putting in parallel different operations with a different state of completion, is even more developed. In these cases, three instructions are active at the same time: one is in the fetching state, the second in the decoding state, and the third in the execution state. The data memory is separated into two independent memory units, each of which has its own bus; in this way parallel data transfer is possible, easing operation on real-time data coming from the environment, for example, on data arriving from a transmission line. The ALU is supported by the parallel operation of a multiplier with an accumu- lator. The basic numerical operations in DSP are multiplication and addition. Multiplication in software is time-consuming, and additions are even worse if floating-point arithmetic is used. To make real-time DSPs possible, a fast dedicated hardware Multiplicator and Accumulator Circuit (MAC), using either fixed-point or floating-point arithmetic, is mandatory. This device also generally uses a pipeline process, since the operations can be represented in three steps: data read, execution and accumulation. Thus generally also the MAC has three active, contemporary operations, each of which is in a dif- ferent state of its life cycle in the MAC. The ALU is also supported by a shifter that allo