r (TIE) after a reference input signal is removed. For the eEEC, there is a mask for holdover in G.8262.1 and in G.8262 for both option 1 and 2 of the EEC clock. Of course, holdover tests should be initiated only following a period that allows the clock to settle down after setup. For frequency tests, that should be at least 15 minutes. Of all these tests, the most popular performance value to test is the wander noise generation. Addi- tionally, some operators like to confirm what the response is of the SyncE signal during an event like a switchover in the control plane processors. But performing every test in this list is not a trivial amount of effort, especially when considering the long run times and the number of possible plat- forms and different interfaces involved. The only functional area that operators like to check is the behavior of ESMC to confirm that the QL transmission mechanism is behaving correctly. Especially popular is confirming that a router transmits the correct QL levels during a switchover between redundant processors. With the in- creasing adoption of the enhanced ESMC TLVs to support eSyncE, there might arise a few new scenarios of interest, particularly to confirm the correct interworking in both EEC and eEEC clocks. Like the other test categories, the tester supports the ability to automatically set up the test paramet- ers and methods and measure the results. It also comes with statistical software to calculate device metrics such as phase gain, MTIE, and TDEV and perform any necessary filtering. It also has all pass/fail masks built-in to quickly determine the result. What it will not do is stop the unwary engin- eer from using the wrong mask to confirm pass/fail for the test set results. So, now that you are happy with the frequency performance of your EEC/eEEC clock, it is time to determine how it performs as a time/phase clock using PTP. 12.3.1 Testing Standalone PTP Clocks The frequency performance of the SyncE/eSyncE clocks is treated separately in the previous sec- tion, but t