signers who use embedded processors and who want to accomplish more work in a given amount of time. A new 64-bit long instruction format provides parallel access to multiple execution modules, which could be store-and-load units, ALUs, MACs, barrel shifters, and SO on. By keeping the lowest 4 bits of all instruction words as the indication of the instruction length, FLIX allows the seamless mixing of 16-, or 24-, or 64-bit long instructions without a problem and with the possibility of aligning them at byte boundaries. It also guarantees the compatibility of preexistent Xtensa code with the new architecture. A designer can do the following tasks with such a flexible approach: Simplify the decoding of instructions based on a more rational instruction field allocation. Optimize the memory footprint especially if multiple streams of instruction sequences (threads) must be executed in parallel cycle by cycle in need of data from different areas of the addressable memory space. Save silicon space on a custom design by using a consolidated instruction sequencer. Take advantage of the possible and deterministic coordination between various on-chip modules. Adjust localized power management by software executing in real time. The most significant advantage for a network-processing designer, however, is that this new archi- tecture can simultaneously handle several instruction sequences (also known as threads) in parallel. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES NETWORK PROCESSORS This has been one of the weakest spots as far as network processing is concerned in the original con- figurable architecture approach with which Tensilica started. The company is now addressing this issue. A note of caution: It will be interesting to follow the arrival of the actual 