 is the time slot interchanger (TSI) [26]. The scope of the TSI is to interchange two given time slots in the TDM frame without doing other changes. The working of a single TSI is shown in Figure 7.16. A TSI can be realized with a simple high-speed memory that is written sequentially and read selectively SO as to reproduce at the output the wanted order of the time slots [27]. The equivalent of an NxN crossbar matrix can be realized with a TDM multiplexer, a TDM demultiplexer, and N TSIs as shown in Figure 7.17. This is a simple consequence of a more general equivalence between switch matrixes realized using different types of multiplexing as detailed in [28]. Since both the TSI and the TDM multiplexer and demultiplexer can be realized with memories, the required memory is a measure of the scaling pace of the time domain switch with the number of ports. Assuming to switch channels at the same bit rate, the number B of memory bytes is (7.10) Switching Systems: Architecture and Performances Input frame Control: (2,5) Output frame FIGURE 7.16 Scheme of the working principle of a TSI. In the figure, ch1, ch2, are the payload and h1 h2 the headers of the individual tributaries while hh is the header of the TDM frame. 5x5 Time domain cross-bar Ch-il Ch-i2 TSI-1 TSI-2 TSI-3 TSI-5 Ch-i3 Ch-i4 Ch-i5 FIGURE 7.17 Time division switch equivalent to an N X N crossbar matrix realized with a TDM multiplexer, a TDM demul- tiplexer, and N TSIs. where BM indicates the memory used in the multiplexer BD is the memory used in the demultiplexer BT is the memory used in the TSIs Equation 7.10 shows that the complexity of the time domain crossbar is linear with the number of ports, contrary to the complexity of the space division crossbar whose number of crosspoints grows with the square of N. This advantage of the time domain crossbar is paid with the need of a much faster elec- tronics. If the passband of the space division crossbar elements has to be at least equal to the bit rate of the signal, in the case of the time division switc