 and that to a lesser cost for the electrical functions. The new generations of components need to allow smaller characteristic dimensions, higher integration levels and reduced defect densities. As commercial integrated circuit technologies continue to advance, sensitivities to radiation tend to evolve, unpredictably. For example, LOCOS is being replaced by more compact isolation as trenches. polysilicon Planar Trench Recessed Trench 13 nm gate oxide N-well trench trench p-api Electric Field Magnitude (MV/cm) Figure 88. Two leakage paths in a trench Figure 89. Electric field distribution in an isolation technology [Shan-98]. example of trench lateral isolation [Shan-98]. III-93 In the modeling work of [Shan-98], two parasitic transistors are identified (fig. 88), resembling the LOCOS case. As in LOCOS technologies, the most active is the edge transistor. At the difference of LOCOS, the maximum of trapping occurs where the oxide thickness is at its smallest, i.e. at the corner of the trench. It is also the place where the electric field is at its maximum due to the field line fringing (fig. 89). 9.2. PLANAR ISOLATION OXIDES (P-FOX) Planar Field Oxides (P-FOX) are topologically and perhaps physically different from lateral oxides. They are fundamentally thick insulators with a constant thickness, and their role is to separate lines of interconnections (poly, metal) of the surface of silicon. Hereafter is shown an example for the case of the CMOS technology. MOS TRANSISTORS EXAMPLE 122M2 Caping Glass Inter Level Metal1/Metal2 Inter Level Metol1/Poly T4 TO T1 T2 T3 CMOS/BULK 4 Transistors TO : Regular Transistor T1, T2, T3, T4 : PARASITIC MOS TRANSISTORS LEAKAGE PATHS - BETWEEN TRANSISTORS AV # tox 1 to 2 - BETWEEN SUPPLY RAILS - BETWEEN LOGIC OR ANALOGIC BUSES - AT INPUT E.S.D. BLOCKS Figure 90. Illustration of different parasitic "Planar Field Oxide transistors" in a 2-metal layer technology. The vulnerability of a planar technology to the field oxide leakage comes from the possibility of surface inversion of the 