earch engines for 10 Gbps/OC-192 and 1 Gigabit Ethernet applications. The NP-1 chip provides fully programmable packet classification, modification, forwarding, queuing, and policing at wire speed. By using exter- nal DRAM only, the NP-1 requires no classification coprocessors, TCAMs, or even SRAMs. It pro- vides full-fledged packet processing between layers 2 and 7 and classification. The company has also integrated all search engines and eliminated the need for such external com- ponents. A series of proprietary and patented search algorithms ensure that the NP-1 can perform lookups in very large tables with over 1M entries at 10 Gbps throughput. The user does not have to worry about data or entry caching. Flexible, user-definable lookup table formats are inherently sup- ported. Tables with variable-length keys and results can be included or wildcards can even be used. It is particularly important to notice that the NP-1 processor seems able to reduce to about one fifth, the chip count, power dissipation, and cost of implementation of several networking solutions. This is feasible through the network processor's combination of embedded search engines and embed- ded DRAM, full-duplex 10 Gbps throughput, and integrated 10 Gigabit Ethernet and 1 Gigabit Ethernet MAC controllers. This all culminates to a situation that can have very serious ramifications not only for the company, but also for the evolution of this industry. The company has based the design of its NP-2 processor on its TOPcore architecture, thereby scal- ing the original 10 Gbps NP-1 design to achieve 40 Gbps throughput. In fact, the NP-2 chip is imple- mented around the same task optimized processing (TOP) cores that EZchip used in the NP-1 design. As a result, software that has been developed for the NP-1 is portable and can be easily reused in higher-speed designs that are centered on the NP-2 network processor, thereby offering the customer a smooth migration path from 10 to 40 Gbps systems. Based on market input, EZchip is currently focusing on