m itself, thereby preventing a local timing loop. Figure 6-13 shows the same network topology as shown previously in Figure 6-11, along with the SSM values that are carried in each direction (clockwise and counterclockwise). This example uses the SSM/QL values for an Option I network. SSU/BITS Switch A Switch B Single link (EEC node) (EEC node) Switch D Switch C (EEC node) (EEC node) Figure 6-13 Timing Distribution in Ring Topology with SSM Figure 6-14 shows the clock rearrangement in the case of a physical link failure, and the way the affected nodes go through the clock rearrangement process to select a new clock source. As the fig- ure illustrates, the clock rearrangement settles on a topology in accordance with the QL values be- ing received. The clock selection algorithm uses the QL values to select the correct reference clock. In addition to timing loop prevention, with this clock selection algorithm the best possible re- arrangement is achieved, considering the timing information flow in the network. SSU/BITS Switch A Switch B Single link (EEC node) (EEC node) Switch D Switch C (EEC node) (EEC node) Figure 6-14 Timing Distribution with Link Failure in a Ring Topology with SSM Figure 6-13 also shows another case whereby a timing loop can arise. Under normal conditions, Switch A receives the PRC from the SSU/BITS, but Switch A is also receiving the PRC from Switch D, which is just a copy of its own clock signal that has gone around the ring. There is no mechanism stopping Switch A from preferring that link to Switch D over the link to the SSU/BITS device (there may be a tie-breaker mechanism that will decide which one). The operator must set a local priority on the correct link SO that Switch A will select the SSU/BITS source of frequency above all others, even if they are all signaling PRC/PRS. If not, it is possible that a timing loop can develop. In addition, when designing a frequency distribution network, the network engineer must also ensure that timing signals can never flow upward in the clock distri