red in increasing order in a time-first manner, starting with 0 for the first OFDM symbol and the lowest numbered resource block in the CORESET. A UE can be configured with multiple CORESETs. Each CORESET is associ- ated with only one CCE-to-REG mapping (see Fig. 4.14). There is a direct correspondence between the number of CCEs and the AL, for example, for ALs 1, 2, 4, 8, and 16, there will be 1, 2, 4, 8, and 16 CCEs, respectively [6]. The time-frequency structure of REG, CCE, REG bundle, and CORESET as well as example mappings of CCE to REG bundles are illustrated Fig. 4.14. The PDCCH processing steps are illustrated in Fig. 4.15. At a high level, the PDCCH pro- cessing in NR is similar to that of LTE ePDCCH than LTE PDCCH in the sense that each PDCCH is processed independently. As shown in the figure, the entire DCI bits are used to calculate the CRC parity bits. Let us assume that ao, a1 ANDCI-1 denote the DCI input bits, and Po, PL-1 represent the parity bits, where NDCI and L 24 are the payload size and the number of parity bits, respectively. Let us assume that a'o, a' anda- Chapter 4 Scheduling information (DCI data) Information element Modulation multiplexing TS 38.211 Section 7.3.2.4 TS 38.212 Section 7.3.1 PDCCH PDCCH CRC attachment Resource element mapping TS 38.212 Section 7.3.2 TS 38.211 Section 7.3.2.5 Channel coding TS 38.212 Section 7.3.3 Rate matching TS 38.212 Section 7.3.4 Scrambling TS 38.211 Section 7.3.2.3 Figure 4.15 Physical layer processing of NR PDCCH [6,7]. sequence such that a' = 1 Vi = 0, 1, L - 1 and a- = L + NDCI - 1. The parity bits are computed with input bit sequence a'o,a ,ANDa+L-1 using the genera- tor polynomial gCRC24C(D) = D24 - D23 + D21 + D20 + D17 +D15+D13 + D12 ++D4+ D2 + D + 1. The output bit sequence is given as bo,b1,..., ,bb-1 where bk=akVk= = 0, 1, NDCI - 1 and bk = Pk-NDCI Ak :=NDcI,NDCI+1,...,NDCI+L-1.Following = the attach- ment of the CRC bits, the sequence is scrambled with the corresponding 16-bit RNTI XRNTI (0), XRNTI(1), XRNTI(15), where XRNTI(0) correspond