that the user had a new level of control over the silicon. It subsequently manifested into software packet processors running on CPUs with maximum flexibility and openness such as Open vSwitch (Open vSwitch) and Vector Packet Processor (The Fast Data Project). And in the near future, suppli- ers will be developing highly programmable ASICs for high throughput packet processing. In the idealized future, packet processors should be open, abstracted, and highly programmable with only a few differentiating variables such as throughput (ASIC > Server throughput), buffers for class of service (Server > ASIC buffers), and logical table sizes (Server > ASIC tables) to allow for simplified selection, application, and control. These packet processors should be accompanied by robust open source distributed control plane stacks that include multiservice unifying constructs such as EVPN. 12.6.2 OPEN CONFIGURATION AND PROGRAMING OF PACKET PROCESSORS The most active area of research and development is in the area of configuring and programming packet processor data planes. Configuring a vertically integrated switch or router is a painstaking exercise involving writing many lines of commands in a unique language that varies across suppliers as well as across platforms from the same supplier. This is loosely equivalent to programming a CPU in assembly language, requiring lots of fine tuning in multisupplier networks to tune each platform to meet a common Network Edge carrier specification for services such as layer 2/Ethernet VPNs or layer 3/IP VPNs. Out of necessity, the academic community began to propose high-level abstractions for configuring packet pipelines. A major step forward in overcoming the painstaking process of configuring packet platforms arrived with OpenFlow, which provides a standard open interface to directly access and manipulate the forwarding plane of network processors in switches and routers (McKeown et al. 2008). The next major leap occurred with the arrival of the top-down approach of P4 (programming pro