tions by overwriting bit fields inside packets by inserting or adding bits, swapping bits, and/or rotating bit fields. These four types of engines are cascaded in a four-stage parallel-pipelined fashion. As soon as one stage is done with its computing tasks, it passes the processed data onto the following stage down- stream in the pipeline. The term parallel pipeline means that at each stage of the parse-resolve-search- modify pipeline, multiple TOPs engines perform identical functions. As a result, multiple packets are processed simultaneously at each stage. The multiple TOP processors at each stage execute the same code in principle, but they all have their own instruction memory. Therefore, they are able to preserve their independence and high efficiency while executing a series of tasks. A hardware scheduler trans- Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES OTHER NPU ARCHITECTURES parently allocates incoming packets to available hardware resources at each stage of the pipeline while preserving synchronized frame pointers across the pipeline and ensuring that messages are passed on between the engines to coordinate processing. As a result, the programmer does not have to worry about addressing individual TOPs processors. It should be clear, however, that writing code for the NP-1 entails actually writing code for the four types of engines. In terms of facilitating the development of software for its network processors, EZchip is offering several tools. To start with, EZdesignTM is a comprehensive suite of design and testing software tools for developers, which enables the rapid delivery to production of new designs based on the company's NP-1 network processor. EZdesign enables designers to create, verify, and implement NP-1 applica- tions that must meet specific functionality and performance targets. EZdesign