to dielectric breakdown as a function of LET [197]. Note that because SEGR is a destructive event, obtaining such data requires that many devices be destroyed during the experiment. Semi-empirical expressions that relate the voltage threshold for SEGR as a function of bias conditions, oxide thickness, and incident particle LET have been developed for specific devices and fit measured SEGR data very well [197,198]. As implied above, the sensitive region for SEGR in vertical power MOSFETs is the neck region under the gate contact, since this is where high fields exist in an oxide. Much of this gate area is not necessary to device operation, and recent studies have proposed eliminating parts of the gate polysilicon (e.g., the cross-hatched region in Fig. 4.3) to decrease the area sensitive to SEGR [199]. Two interesting recent papers have studied the effects of ion energy on SEGR in vertical power MOSFETs [196,200]. The first of these showed that the substrate response had a clear dependence on ion energy [200]. As ion energy increased, the maximum gate voltage that could be applied without producing SEGR decreased until the ion range was sufficient to penetrate the entire epitaxial layer. At this point the device was most sensitive to SEGR. The results were explained by the fact that this condition resulted in the maximum amount of charge being deposited into the epitaxial layer [200]. The authors noted that at zero drain bias (i.e., no substrate response component), there appeared to be no energy dependence of the SEGR gate bias threshold. This observation spurred further research to explicitly measure the capacitor response as a function of ion energy [196]. In this study, no apparent difference was found in the SEGR gate bias threshold as a function of ion, corroborating the earlier data. Data from this study are shown in Figure 4.4. Note the surprising result that the gate bias at the onset of SEGR does not track with the LET value, appearing to be a constant value regardless of the ion energy. Although the res