of the forwarding table. The connection between input and output ports is realized via a modular space diversity switch fabric, while a service bus connects all the units with the central board having a computer like architecture with a processor, a ROM and RAM memory and generally a flash (FLS) memory. and the buffer space needed for packet processing tasks related to all the packets flowing through it. They perform the processing of all protocol functions (in addition to QoS processing functions) that lie in the critical path of data flow. In order to provide QoS guarantees, a port may need to classify packets into predefined service classes. Depending on router implementation, a port may also need to run data- link level protocols or network-level protocols. The exact features of the processing com- ponents depend on the functional partitioning and implementation details. Concurrent operation among these components can be provided. The network interfaces are interconnected via a high-performance switch that enables them to exchange data and control messages. The central CPU is used only to perform some really centralized tasks. As a result, the overall processing and buffering capacity is distributed over the available interfaces and the CPU. 7.8.3 Routing Tables Lookup For a long time the main performance limitation of both core and edge routers has been the time required for the lookup of the routing tables. The problem can be defined as that of searching through a database (routing table) of destination prefixes, the longest prefix that matches the destination address of a given packet. Longest prefix matching was introduced as a consequence of the requirement for increas- ing the number of networks addressed through classless inter-domain routing (CIDR). Switching Systems: Architecture and Performances The CIDR technique is used to summarize a block of addresses into a single routing table entry. This consolidation results in a reduction in the number of separate routing table entries. This advantage is co