/1.371, page 3, ITU-T Rec. 1.371 (Ref. 13).] 20.12 TRANSPORTING ATM CELLS 20.12.1 In the DS3 Frame One of the most popular high-speed digital transmission systems in North America is DS3 operating at a nominal transmission rate of 45 Mbps. It is also being widely implemented for transport of SMDS. The system used to map ATM cells into the DS3 format is the same that is used for SMDS. To map ATM cells into a DS3 bit stream, the physical layer convergence protocol (PLCP) is employed. A DS3 PLCP frame is shown in Figure 20.16. I PLCP Framing I POH I PLCP Payload First ATM Cell ATM Cell Path Overhead Indicator ATM Cell Path Overhead ATM Cell BIP-8 Bit Interleaved Parity 8 ATM Cell Unassigned Receiver ATM Cell required to ignore A1, A2 ATM Cell Frame Alignment ATM Cell ATM Cell ATM Cell ATM Cell Twelfth ATM Cell Trailer 1 Octet 1 Octet Octet Octet 53 Octets 13 14 Object of BIP-8 Calculation Nibbles Figure 20.16 Format of DS3 PLCP frame. (From Ref 1, courtesy of Hewlett-Packard.) ASYNCHRONOUS TRANSFER MODE There are 12 cells in a PLCP frame. Each cell is preceded by a 2-octet framing pattern (A1, A2) to enable the receiver to synchronize to cells. After the framing pattern there is an indicator consisting of one of 12 fixed bit patterns used to identify the cell location within the frame (POI). This is followed by an octet of overhead information used for path management. The entire frame is then padded with either 13 or 14 nibbles (1 nibble = 4 bits) of trailer to bring the transmission rate up to the exact DS3 bit rate. The DS3 frame, as we are aware, has a 125-usec duration. DS3 has to contend with network slips (added/dropped frames to accommodate syn- chronization alignment). Thus PLCP is padded with a variable number of stuff (justifi- cation) bits to accommodate possible timing slips. The C1 overhead octet indicates the length of padding. The BIP (bit-interleaved parity) checks the payload and overhead func- tions for errors and performance degradation. This performance information is transmitted in the overhead