vailabil- ity of an in-house foundry is therefore not enough. The foundry must be already almost fully exploited from a capacity usage standpoint in order for this to be a real economic advantage. TRADE-OFFS WHEN DESIGNING WITH STANDARD OFF-THE-SHELF CPUS Packet processing would usually be implemented in software that runs on a standard off-the-shelf CPU because of the ease and flexibility with which such a CPU can be programmed. To obtain new functionality, a new software version with the appropriate additions or modifications is needed. Software can be easily downloaded into a system with the corresponding memory architecture (read- only memory [ROM], erasable programmable read-only memory [EPROM], flash, and SO on). Bugs can also be easily fixed. When an entirely new functionality is required, implementing it is straight- forward. The time needed to accomplish this kind of change is usually short, and this flexibility trans- lates into a significant business advantage for the device vendor. This is also advantageous for the user, as the user does not need to invest in new hardware to obtain some enhanced or corrected functional- ity. From the user's perspective, an existing network device can be upgraded easily (many times directly on site) by updating its software, which costs much less than new hardware. The downside to this approach is a decrease in performance, as off-the-shelf CPUs are designed for a general computing environment. Generally speaking, they will spend many clock cycles on tasks that are not directly related to packet processing; therefore, the percentage of their processing capac- ity that is used directly for packet processing is only going to be a small fraction of the network's requirements. For instance, the fastest off-the-shelf CPUs can currently only handle a throughput of around a couple of hundred megabits per second. This is far less than today's backbone networks, whose minimum requirement is easily tens of gigabits per second. Figure 2.2 compares the growth of bandwidth requirem