aded at con- figuration time, but they can be selected for queues dynamically. For the definition of queues, the queue must first be added to a data structure called the stream tor destination ID table. This table includes a pointer to the Stream Editor Compute Engine's modi- fication instructions for the queue. The compute engine program parameters must then be defined. These are used to set thresholds for the discard policies or to define bytes to add or replace when mod- ifying a PDU. Finally, the queue must be assigned to a scheduler. By doing that, the actual program- ming of the Traffic Management Compute Engine and Traffic Shaper Compute Engine are chosen, as well as both the physical and logical ports that will need to be used for the queue. Again, all these steps can occur at configuration time or dynamically during operation. In terms of memory interfacing, the RSP comes equipped with a 64-bit interface that can be clocked up to 133 MHz for queuing PDUs in SDRAM and with four 32-bit-wide interfaces that offer point-to-point memory access up to 133 MHz. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. 112 NETWORK PROCESSORS As mentioned earlier, the ASI chip's role is to seamlessly interface the FPP and RSP to a supervising host processor. More specifically, it makes it possible for the systems designer to do the following: Create a method for the centralized initialization and configuration of the network-processing sys- tem and all its physical interfaces. Send routing and Virtual Path Identifier/Virtual Connection Identifier (VPI/VCI) table updates to the RSP. Implement various routing and management protocols. Handle any occurring exceptions. The ASI also enables other high-speed, flow-oriented state maintenance tasks for the FPP, which include the following: Gathering Remote Network Monitoring (RMON) statistics needed for remote