necessary, and the solution can become more complex and costlier than desired. Nonetheless, with bandwidth-limited systems (our example of 100 MHz bandwidth) and lower antenna counts JESD works well. At the same time, once we scale up to mmWave capacities and 5G evolves to 6G, it is clear that the digital interface becomes less and less desirable. This limited interface capacity also imposes challenges when integrating Digital Front End (DFE) functionality. Digital predistortion requires the data converter subsystem to oper- ate at a higher sample rate than the (native) baseband rate, multiplying the required IO and associated SerDes count to become unsustainable, specifically when power consumption is prime. The answer begins to carve out some of the DFE functionality and migrates this to the RFIC, as pioneered by ADI in 2018 10 but also supported by other RFIC vendors. The computational requirements associated with DPD are high, driving for an aggressive process node roadmap and hence a potentially costly solution. The advantage of this solution is the high level of functional integration: the customer doesn't need to be concerned with DPD algorithmic development, ADC/DAC specs and other items considered complex due to their analog nature. Analog The alternative to integration of DPD into the RFIC is to integrate the RFIC functionality into the baseband chip, moving the integration complexity from the digital to the analog domain (Fig. 4-23). In this partitioning option, data converters are integrated into the baseband device, either as a baseband I/Q interface or as an IF or RF data converter, both of which Baseband/Modem Antenna Connector 122.88 RF Clock (<7GHz) VCTCXO 0° 90° PLL+VCO PLL Freq Synthesizer (eg LMX2592) FIGURE 4-22 Digital baseband (JESD) interface between modem and RFIC. Chapter 4 Hardware architecture choices IQ Modulator Baseband/Modem Antenna Connector 122.88 RF Clock (<7GHz) VCTCXO PLL+VCO PLL Freq Synthesizer (eg LMX2592) IQ Demodulator FIGURE 4-23 Analog baseband interface between modem a