block dlcb is in state waitparmresp. Watch dica!dispatch ! state = ready dicbidispatch ! state = waitparmresp dlcbidlc(1) ! state = connected atob(1) ! state = ready btoa(1) ! state = ready Figure 6.6 The watch window B. In the Editor, open the partition part1 of process dispatch: you see that in state waitparm- resp, the only input is L_SetParmResp; therefore, when a v76frame is first in the process queue, it is discarded. If required, the MSC trace corresponding to the bug can be generated by pressing the buttons Start MSC, undo K and then redo We will not correct this bug, because we will learn how to find it with exhaustive simulation. 174 Validation of Communications Systems with SDL 6.3.2 Multiple random simulations The random simulation algorithm used in the Simulator is based on a pseudorandom number called seed. The initial default seed value (619430284 in the version used) can be changed using Edit > Configuration. At each random simulation step, the Simulator: executes a transition selected among the firable transitions according to the current seed value, (for example, if there are two firable transitions, depending on the seed value, the first or the second transition is executed), computes the new seed value function of the current seed value. It means that the seed changes at every simulation step. Also, if you go back (undo or init commands) to previous simulation steps, seed does not return to its previous value: this is to simulate different branches easily. Otherwise, using the same seed from the same model's state would simulate the same scenario. To illustrate this: A. Quit the Simulator, start the Simulator as indicated in Section 6.3.1.1 and enter the stop condition rstep = 500. B. Press on to start the random simulation: at Step 261 (you may get another number), the simulation stops (unexpected signal). C. Press on init K four times on redo N and then on this time, the simulation stops at Step 264 (you may get another number). D. Repeat the same sequence: this time, the simulation stops at