S 170 NETWORK PROCESSORS RISC's power. To give an idea of the PE capabilities, the company clarifies that a combination of PEs clocked at 400 MHz offers the equivalent of 102,400 MIPS, 4MB of embedded memory, and 400 GBps of memory bandwidth. For those who like to think in terms of DSP MAC operations, they vide the capabilities of 100 billions of MACs/per second. Figure 10.2 shows an image of a four-PE subpanel in a low-dielectric k constant, 0.13u tech- nology library from UMC with eight layers of copper metalization. The various logic blocks in the design use the lowest four metal layers, whereas the higher four blocks are used for overrouting-that is, for interblock stitching between the individual cores at the chip level. It is part of a good SOC design methodology. Its size is about 3 mm high by 0.5 mm wide. The outermost regular blocks are the PE memories, which are 4KB each in this example. The company uses them in their EV1 evalu- ation chip. The next section down is the programmed I/O (PIO) logic. The PIO is a fairly complex, high- bandwidth direct memory access (DMA) engine per PE-hence the significant size. Below that sec- tion is another regular block. This represents the memory associated with the stream I/O (SIO), which is 128 bytes per PE for the EV1 chip. A smaller slice of logic appears before reaching the register files -one per PE, making up 64 1-byte registers. Each register file has five ports, SO they end up being quite big. Finally, the main block of logic appears below the register file. This includes the ALU, the 8X8 to 16+48 MAC, and the rest of the configuration. It is extremely important to note that native hardware support exists for multithreading by the con- trol unit, which is in charge of instruction fetching and decoding. The actual thread switching, which remains accessible under software control, can be triggered upon the occurrence of specific events, such as when an I/O operation has completed. I/O can be handled by two methods called SIO and PIO. The former is used for very-