 frequencies provide ample opportunity for clocking of errant results into memory elements. The combined scheme uses temporal triple mode redundancy by sampling the output of combinatorial logic at three different times, storing the individual result in three different latch or flip-flop elements, and majority voting the latched result. By ensuring that the separation between clock edges is greater than the duration of a transient pulse emerging from the combinatorial logic, the transient can corrupt only one of the three values. The majority voting of static triple mode spatial redundancy ensures that upset of individual latches or flip-flops will also be corrected through action of the majority vote logic. The impact of utilizing the combined technique is an approximate 50% reduction in the usable clock frequency from that which would otherwise be achievable. An increase in power due to added clocks and registers (approximate 1.8 times the otherwise achievable power), and an increase in design complexity, due again to the complex clocking and added registers/latches, are also impacts resulting from this implementation. System Error Detection and Recovery [Sosnowski] Whereas the fault detection capabilities of hardware based schemes such as modular redundancy are good, fault detection is the most difficult aspect of fault tolerance to achieve in applications oriented fault tolerance using algorithms, or software based fault detection, due to the elusive nature of the signature of most faults. A fault which results in a fail-stop consequence enables obvious opportunity for detection; most conditions of compromised system state produce signatures which are difficult to discern. Once detection is accomplished, recovery may be as complete and efficient as necessary to restore normal system operation. 6.5.1 Application-Oriented Fault Tolerance [McMillin97] Application-oriented fault tolerance is a software solution to the problem of error detection and recovery. Additional processor hardware is used in some of the te