 FIGURE 7.52 Schematic representation of the process a router carries out for each IP datagram. Continuous lines indicate the datagram flow, dotted lines the control and address flow. AD represents the adaptation function between layer 2 and layer 3, LC up represents the line card microprocessor and the packet is stored in a memory (queue) located in the line card while the routing process is carried out. Switching Systems: Architecture and Performances The routing processor starts a process of access to the routing and forwarding tables. From the access to the routing and forwarding tables, the routing processor deter- mines where is the output card and the corresponding output queue where the packet has to be transferred. If no correspondence is found it means that the packet is affected by an uncor- rected error SO that its destination cannot be reconstructed; in this condition the packet is deleted. The processor looks at the destination output queue to determine if there is a free queue slot. If a free queue slot is present, the packet is transferred to the destination output queue. In the absence of a free output queue slot, the processor repeats the lookup peri- odically, up to the moment in which the slot is freed. The processor transfers the packet from the input to the output queue; three dif- ferent types of transfers exist, depending on the IP address of the packet: A local delivery (i.e., the destination address is one of the router's local addresses and the packet is locally delivered) A unicast delivery to a single output port A multicast delivery to a set of output ports After forwarding the processor performs two other operations: Packet lifetime control: It adjusts the time-to-live (TTL) field in the packet used to prevent packets from circulating endlessly throughout the network. Checksum calculation: The IP header checksum must be recalculated due to the change in the TTL field. The output line card confirms the correct transfer to the processor. The processor also regenerates the layer 2 enve