ndwidth, which is well above the 1.422 Gbps ingress requirement mentioned previously. The total ingress and egress IX bus bandwidth in this example is 4.2 Gbps. Ready bus The ready bus is an 8-bit bus that runs parallel to the IX bus and provides sideband messaging between IX bus devices. The IXP1200, as the IX bus master, manages the collection of ready flags from IX bus peripherals/slaves through this ready bus. The ready bus can also perform other functions, including flow control. Memory-mapped I/O interface Sharing the SRAM interface, this bus offers the possibility of independently programmable timing. It can also serve as the third connection between the IXP1200 network processor and another peripheral processor sitting on the IX bus. This bus behaves like a slow port. As a result, it can be used for configuring Ethernet MAC controllers, managing an attached device, and even collecting statistics in the context of Remote Network Monitoring (RMON) and/or SNMP. POS-PL3 This is a first in/first out (FIFO) interface that is 32 bits wide. It works at a rate of 104 MHz for each transmit and receive path. This amounts to a consolidated bandwidth of 3.3 Gbps paths on this interface. MII bus This is a standard MII, and it forms the link between the Ethernet MAC ports in the Intel IXF440 MAC and the Intel LXT9763 PHYs. PCI bus In Figure 5.4, the 32-bit 33 MHz PCI bus provides a point-to-point connection from the IXP1200 network processor to the 82559ER Fast Ethernet management port. In yet another case in a much higher-performance environment, Figure 5.5 shows a typical block structure for an OC-48 line card that is built around the IXP2400 NPU. A strikingly similar approach is taken with IXP2800 in a core network application, as shown in the LAN/WAN example of Fig- ure 5.7. The scalability of the Intel architecture at this point should be quite obvious. On the ingress path of this example, the first IXP2800 is responsible for issues like SAR, classification, metering, pricing, and initial congestion management. On 