 a single instruction that is executed in a 1 clock cycle instruction Field-programmable gate arrays loop. First, there is a loop control mechanism. This loop FPGAs are programmable devices that are different in control has a counter that has to be initialized and then nature from GPPs and DSPs. An FPGA comprises some incremented in each operation, providing a set of N+1 discrete set of units, sometimes referred to as logical operations. Within the loop, there is also an evaluation elements (LE), logic modules (LM), slices, or some of the loop control state; this evaluation is performed N other reference to a self-contained Boolean logical op- times. Within the loop, a series of memory fetch oper- eration. Each of these logical devices has at least one ations have to be performed. In this case, there are N+1 logic unit; this logic unit could be one or more multi- accesses to get the coefficient and store the result. pliers and one or more accumulators, or a combination There are additional N+1 circular accesses of the of such units in some FPGA chip selections. Logical sample data plus the fetch operation of the new data devices are also likely to contain some memory, usually point, yielding a total of 2N+2 memory accesses. a few bits. The developer then has some freedom to Finally, there are the arithmetic operations: the coefficient configure each of these logical devices, where the level multiplied by the signal sample, and the accumulation of reconfigurability is arbitrarily determined by the operation (including the initial zero operation) resulting FPGA manufacturer. The logical devices are set in in 2N+1 operations. Therefore, the DSP typically per- a logic fabric, a reconfigurable connection matrix that forms on the order of 6N operations per instruction allows the developer to describe connections between clock cycle. different logical devices. The logic fabric usually also has Assuming that a GPP performs a memory fetch, access to some additional memory that logical devices memory store, index update, c