ried MSR platform. The APP550TM offers the possibility of embedded segmentation and reassembly (SAR)ing and traffic management. The APP540 does not offer the pos- sibility of extensive ATM reassembly functionality. Consequently, when the intended solution is purely IP-packet driven, APP540 may be the right choice. Another related component, the APP530, offers the possibility of cutting the performance speed in half, which may be the right choice for some Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SYSTEMS ENGINEERING ISSUES SYSTEMS ENGINEERING ISSUES Policing/Statistics DDR-II Schedul./Parameters DDR-II chassis midplane Packet FCRAM Queue DDR-II 48VDC clock Reassembly Parameter FCRAM FCRAM power Program 266MHz Stream editor signals FCRAM Context DDR-II line card generation Control APP550 Link-list interface DDR-II FCRAM 64-bit PCI bus at 66MHz Arbiter Primary datapath 2 X 32-bit 133MHz buses Ethernet interface CBI 8-bit bus coprocessor at 33MHz datapath e.g. 82559 2 X 32-bit buses at 133MHz coprocessor connector fabric Configuration interface coprocessor local bus system reset, bridge Local 32-bit bus clock control, at 33MHz FPGA pump EEPROM signals, etc. FIGURE 16.5 Typical 2.5 Gbps line card based on the APP550. The 10 GbE card of our case study would be struc- tured along similar guidelines, but with the APP750 network processor and traffic manager chipset instead. (Source: Agere Systems) traffic environments. Yet another member of this network-processing family, the APP520, supports only two as opposed to four Gigabit Ethernet interfaces. Traffic management will be handled by the native Agere traffic managers for each wire-speed regime. Some applications only require traffic management at the egress path. We will assume our system is complicated enough to require traffic management at both the ingress and the egress paths. Our design