Switch (CPU) Timing PCle (CPU) Block BCM88470 Switch 2x XRI(10G) 2x XFI (10G) 2x XFI (10G) (neal) 2x xR (100) 2x (FI (106) BCM68620 BCM68620 BCM68620 BCM68620 BCM68620 BCM68620 BCM68620 BCM68620 4x QSFP28 FIGURE 11.9 Main system block diagram of 16-port OCP design. Network Access Host Module XLP208 Timing Block PCle (CPU) BCM88270 Switch 2x XFI (10G) 2x XFI (10G) PCle (CPU) PCle (CPU) BCM68620 BCM68620 FIGURE 11.10 Main system block diagram of 4-port OCP design. 4 Port Hardened OLT-The Open XGS-PON 4-port remote vOLT is a cost-optimized access design focused on NFV infrastructure deployments, which support symmetric 10 Gbps PON access connectivity and provide 40 Gbps uplinks to the ToR or Spine layer of the network. Figure 11.10 shows the main system block diagram 4-port OCP design consisting of two BCM68628 devices connected to the BCM88270 QUX switch that supports up to 120 Gbps of traffic. AT&T plans to deploy vOLT hardware into the access network by using designs approved by OCP as new merchant silicon becomes available. These designs represent AT&T's first open speci- fications for virtual access node hardware, and can pave the way for open specifications for other virtual access technologies. 11.4.7 WIRELINE ACCESS SOFTWARE The overall SDN, NFV, and ONAP architectures will extend to include support of wireline access nodes such as the vOLTs described in the preceding section. Some software functions are more Building the Network of the Future Control Manager Access Controller Network Abstraction Layer North Bound Interfaces (eg OpenFlow, NETCONF) Extensions (eg PON Manager, vOMCI) Hardware Drivers (Vendor Hardware Drivers) OLT Pizzabox, R-OLT and MicroOLT FIGURE 11.11 Software architecture of next-generation PON. specific to wireline access components. These can include functions that come from the disaggrega- tion of current software in conventional access nodes, as well as specific software components that enable services to be written once and applied across a variety of types of access nodes. Figure 11.