rity carrier lifetimes reduce the diffusion current at the struck node. The cell feedback time is simply the time required for the disturbed node voltage to feed back through the cross-coupled inverters and latch the struck device in its disturbed state. This time is related to the cell write time and in its simplest form can be thought of as the RC delay in the inverter pair. This RC time constant is thus a critical parameter for determining SEU sensitivity in SRAMs - the smaller the RC delay, the faster the cell can respond to voltage transients (including write pulses) and the more susceptible the SRAM is to SEU. Obviously this has implications for the sensitivity of future, higher speed technologies, as discussed in Section 6. Single-Event Upset in Other Circuit Types Although we have concentrated on SEU in memory circuits, the reader should be aware that SEUs can occur in almost any integrated circuit. For example, SEU is not constrained to digital circuits, but occurs in analog circuits as well. We have already mentioned the problem of SET in optocouplers, which can lead to errors in data transmission [23,28]. Errors are observed in many analog circuit types, including operational amplifiers [91-93], comparators [93,94], and analog- to-digital converters (ADCs) [95-97]. Upsets in ADCs are interesting in that analog errors are observed as corruptions in digital output codes [98]. Figure 3.12 shows an example of analog SEU in a 12-bit ADC, where the SEUs appear as a distribution of erroneous codes around the expected output (4 codes centered at 1428 that were removed in this plot for clarity [95]). An excellent summary of SEU in analog ICs is found in [98]. II-22 DIGITAL OUTPUT CODE Figure 3.12. SEU in a 12-bit analog-to-digital converter [95]. Errors are indicated by deviations from the expected digital output codes (4 codes centered at 1428 that were removed in this plot for clarity). SEUs also occur in digital circuits other than memories, prime examples being microprocessors [99-103] and digital signal pr