 networks are backed up by the local PSTN. 6.12.2 Technical Requirements of the Digital Network 6.12.2.1 Network Synchronization Rationale and Essentials. When a PCM bit stream is transmitted over a telecommunication link, there must be synchronization at three different levels: (1) bit, (2) time slot, and (3) frame. Bit synchronization refers to the need for the transmitter (coder) and receiver (decoder) to operate at the same bit rate. It also refers to the requirement that the receiver decision point be exactly at the mid- position of the incoming bit. Bit synchronization assures that the bits will not be misread by the receiver. DIGITAL NETWORKS Obviously a digital receiver must also know where a time slot begins and ends. If we can synchronize a frame, time-slot synchronization can be assured. Frame synchronization assumes that bit synchronization has been achieved. We know where a frame begins (and ends) by some kind of marking device. With DS1 it is the framing bit. In some frames it appears as a 1 and in others it appears as a 0. If the 12-frame super-frame is adopted, it has 12 framing bits, one in each of the 12 frames. This provides the 000111 framing pattern (Ref. 3). In the case of the 24-frame extended superframe, the repeating pattern is 001011, and the framing bit occurs only once in four frames. E1, as we remember from Section 6.2, has a separate framing and synchronization channel, namely, channel 0. In this case the receiver looks in channel 0 for the framing sequence in bits 2 through 8 (bit 1 is reserved) of every other frame. The framing sequence is 0011011. Once the framing sequence is acquired, the receiver knows exactly where frame boundaries are. It is also time-slot aligned. All digital switches have a master clock. Outgoing bit streams from a switch are slaved to the switch's master clock. Incoming bit streams to a switch derive timing from bit tran- sitions of that incoming bit stream. It is mandatory that each and every switch in a digital network generate outgoing bit streams whose 