adiation (VDs=+4V) using the self-consistent code A. III-102 90 krad 0 krad +1e+10 +1e+12 +1e+14 +1e+16 +1e+18 +1e+10 +1e+12 +1e+14 +1e+16 +1e+18 300 krad 210 krad +1e+10 +1e+12 +1e+14 +1e+16 +1e+18 +1e+10 +1e+12 +1e+14 +1e+16 +1e+18 VDs=+4V Figure 98. Trapped charge in the oxides of a NMOS/SOI transistor in worst case during irradiation using the self-consistent code A. alina 20 inci 90 lmcé Here Hall - Years Stituat 300 kmcd 25 ind Illine issue VDS=0 VDs=+1V VDs=+2V Figure 99. Charts of the charge build-up for other drain voltages of OV, 1V and 2V using the self-consistent code A. III-103 11. CONCLUSIONS: TRENDS, MODELING, AND NEW ISSUES As radiation dose increases for new generation of satellites, it becomes more stringent to correctly use devices closer to their limits. For that, we have to look further on modeling and characterization. In this course, we have focuses on the oxide trapped charge as it is of first concern in discrete parts (Power MOS), most post-irradiation effects (rebound) and circuit leakage currents (build-up and recovery), and explored links with process and various situations as case studies. As gate oxide thickness decreases with the progress device integration, the total dose hardness of MOS transistors is mostly limited by parasitic MOS structures. The gate oxide to field oxide bird's beak forms a non-planar transistor responsible for leakage current at low dose. 1D, 2D and 3D-simulation codes are available or are being developed to calculate charge transport and trapping in non-planar MOS structures. Some codes are introducing detrapping phenomena. The dose induced leakage current is due to the threshold voltage shift of the lateral parasitic transistor mainly in the edge, which is directly related to the slope of the surface of parasitic transistors. The isolation geometry is determinant for the behavior of a technology. The isolation shape, the silicon doping level, the supply voltage and the trap parameters in the insulators are the key parameter tools to optimize a rad-tolerant t