ity is selected. In the case of a tie in priority, the currently selected source is retained. 6.9 Timing Loops All NEs in a synchronous network must be synchronized to the same clock frequency to prevent data loss. However, as noted in previous sections, there could be failures of the physical links that are carrying the timing signal. During such events, the nodes that are impacted directly by the phys- ical link failure run a clock selection algorithm to choose the next best available clock. This process is known as a clock rearrangement. During the clock rearrangement process, it is possible for the node to lose synchronization to the master reference clock (such as PRC/PRS) and to become part of a timing loop. In this state, syn- chronization is looped back through the network SO that all nodes affected by the timing loop synchronized to the delayed version of their own clock. This causes the network clock frequency inside the timing loop to drift outside of the frequency range acceptable to the synchronous net- work. This is a major failure condition that can have adverse effects on the data traffic throughput and stability of the network. Figure 6-11 shows a typical configuration of four NE nodes synchronized within a ring topology. Note that unlike what is shown in Figure 6-11, most real network topologies can have many more NE nodes, spanning across wide geographical areas. The figure only illustrates a simple example whereby all NE nodes are EEC nodes, whereas real networks can have many different types of nodes and physical links carrying the timing signal. SSU/BITS Switch A Switch B Single link (EEC node) (EEC node) Switch D Switch C (EEC node) (EEC node) Figure 6-11 Timing Distribution in a Ring Topology Switch A is synchronized to an onsite SSU/BITS, which itself is synchronized to a PRC traceable clock. Switch A then makes the traceable frequency signal available on both of its output interfaces. The other switches in the ring recover the timing from their adjacent node, SO that the timing signal pr