eces fit together. Frequency and phase synchronization each require their own separate engineering when it comes to designing equipment to support them. The sections that follow discuss the main hardware and soft- ware components as well as the reference architectures for each. 12.1.1 Synchronous Equipment Timing Source Before discussing the hardware and software architecture of synchronous equipment, it is important to understand the core hardware component of the clock, an element called the synchronous equip- ment timing source (SETS) device. This device provides the necessary controls to manage timing references, clock recovery, and clock signal generation for synchronous equipment. The performance requirements of SETS devices are defined in ITU-T G.8262 for SyncE Ethernet equipment clocks (EEC), G.8262.1 for enhanced Ethernet equipment clocks (eEEC), and ITU-T G.813 for SDH or synchronous equipment clocks (SEC). Figure 12-1 illustrates the main compon- ents and interconnection of these components of a SETS device. Synchronous Equipment Local oscillator Frequency System frequency recovery PLL (TO path) (TO PLL) Input Clock Phase frequency & phase Phase multipliers recovery PLL references T4 path (PTP PLL) dividers Timing interfaces SSU/BITS T4 path Input monitoring Clock cleanup T4 path T4 path (T4 PLL) Figure 12-1 SETS Block Diagram The list that follows explains the functionality of each component: Use of the terms "master" and "slave" is ONLY in association with the official terminology used in industry specifications and standards, and in no way diminishes Pearson's commitment to promoting diversity, equity, and inclusion, and challenging, countering and/or combating bias and stereotyping in the global population of the learners we serve. System phase-locked loops (PLL): Instead of equipment having only a single system PLL, more recent and better equipment designs have multiple system PLLs. A good and versatile SETS device in synchronous equipment is usually equipped with three PLLs, as shown in Fig- ure 