ne device Switch Core (N X N) Switch Fabric FIGURE 14.15 The connectivity options of network processors with 64G switch fabrics. (Source: IBM) Eight 2.5Gbps 32 DASL links HSS serial Ingress flow each of 0.5 Gbps input links serial output PowerPRS 10b/8b receivers Decoder deskew drivers packet formatting PowerPRS PowerPRS C192 loopback loopback Shared memory grants PowerPRS 8b/10b transmitters Encoder packet deskew receivers formatting Programming interface Switch Core Interface Chip Eight 2.5Gbps 32 DASL links HSS serial Clock output links Egress flow Microprocessor each of 0.5 Gbps source serial input FIGURE 14.16 The architecture of the IBM PowerPRS SCIC. (Source: IBM) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SWITCH FABRICS SWITCH FABRICS from the C192 Queue Manager chip through the HSS links (each one of them being of 2.5 Gbps) is received by the SCIC. It is decoded, and then the logical units (LUs) (an IBM term used for the fragments of 16 to 20 bytes at a time from an initial packet, which was created for compatibility with the 64G), are realigned to avoid the potential skew that may occur with packets of differing delays while they traverse the backplane. After the appropriate formatting of the packets, the data are ejected onto the DASL, which will now take the data bits into the switch fabric. On the egress flow, the exact opposite occurs; data exiting the switch fabric through the DASL links are received by the SCIC, deskewed, and prepared for the appropriate formatting. Then they are 8b/10b encoded (because both the C192 and the SCIC use Fibre Channel Standard 8b/10b codes) and transmitted on one of the HSS links toward the C192 Queue Manager for onward transmission. The SCIC upgrades the older 64G switch fabric system backplane from 500 Mbps DASL to the 2.5 Gbps HSS high-speed serdes (previously known as Unilink). This IBM-