r file controller controller Shift / Logical / MAC unit MAC unit Register file Emulation unit Sequencer Program control FIGURE 5.50 Architecture of a more advanced DSP. (After Ceva, The Architecture of Ceva DSPs-Product Note, 2010, www.ceva- dsp.com [accessed: October 18,2010].) As a matter of fact, depending on the DSP-specific architecture, several recurring opera- tions in digital processing are carried out by hardware parts of the ALU or by parallel elaboration circuitry, like MACs. For example, key parts of an FFT algorithm can be encoded into a single machine lan- guage instruction in a DSP optimized for this kind of application. Moreover, a DSP-embedded instruction set is almost always a reduced instruction set computer (RISC) set, where no micro-language is present to elaborate complex instructions. The characteristics of a RISC set are as follows: The instructions are short and the execution time does not vary SO much from instruction to instruction. The instructions have a fixed length. Every instruction is executed in a clock cycle. Memory is addressed with a small number of simple instructions. In order to face the reduced number of instructions and the absence of micro- language, registries are used much more than in a traditional CPU. Pipelining is easier. 5.7.4.3 DSP Performances As in the case of FPGAs, it makes little sense to talk in detail about DSP performances, as they vary depending on the application and on the inner DSP architecture. Telecommunication Networks In the following part of this chapter we will see a lot of applications requiring DSPs or FPGAs in order to have an idea of what can be achieved with these electronic circuits in the telecommunication environment. 5.8 Electronics for Transmission and Routing After a general review of the developments of microelectronics and of the architecture of a few general-purpose circuits that have a relevant impact on telecommunication systems, we discuss in this section a set of specific applications of microelectronics to telecommu- nication 