 sure that OPS calculated in industry. Processors are moving away from single-core step 4 of the waveform-specific solutions to multicore solutions, in which a chip is analysis are reduced by cycle-saving composed of more than one processing core. Several capabilities outlined in step 2b of advantages are evident from such solutions. First, even the platform-specific analysis. though the chip area is increasing, it is now populated by (2) The result of the algorithm map is an multiple processors that can run at lower clock speeds. In MIPS count for each device. order to understand the ramifications of such change, it is first important to recall the power consumption of an (ii) For FPGA: active circuit as (1) Mapping of the algorithm is a question of the number of occupied logical devices. P = a.C.f.V2 (2.4a.1) (2) Make sure that clock domains needed for algorithms can be supported by the As shown in Eq. (2.4a.1), the power dissipated, P, by FPGA. an active circuit is the product of the switching activity, (b) If a solution set of MIPS and/or LE exists for the a, the capacitance of the circuit, C, the clock speed, f, combination of devices in the set, then save the and the operating voltage, V, squared. It is then clear resulting solution set for this device set; if a so- from the above equation that the reduced clock speed lution does not exist, discard the device set. results in a proportional reduction in power consump- tion. Furthermore, since a lower operating frequency 7. Apply appropriate optimization algorithm over means that a lower voltage is needed to operate the resulting solution set/device set from step 6. Addi- device, the reduction in the operating voltage produces tional optimization algorithms include power bud- a reduction in power consumption that follows a gets and performance metrics. quadratic curve. The process described yields a coarse solution set for One of the principal bottlenecks in processor design is the hardware necessary to support a particular set of the input/output interface f