outputs, while the remaining input is invari- ably routed to the remaining output. It should be clear that the complexity of the decision-making process will ultimately determine the complexity of the decision-making circuits. This is the key component of the B-element design. In some cases, the activity bit of an ATM cell will determine the crossconnect element's state. In other cases, the decision process on the destination of the cells is based on an elaborate inspection by a finite-state machine (FSM) of virtual circuit numbers inside the cell headers. This may or may not involve a lookup of appropriate tables, an action that further complicates the design of the B-element. However, the design remains SO simple and straightforward that it can be easily integrated in large numbers in very regularly repetitive circuit structures inside a very large scale integration (VLSI) chip. In the case of packets, the delay stages are simply buffers. The header of an incoming packet is inspected and, according to some routing rule, the packet is directed to one or both outputs. For example, if a specific 1-bit header is 0, then the routing rule states that the packet will need to be forwarded to the upper output, whereas the packet will need to be routed to the lower output of the switching element when the same 1-bit header of the packet is 1. If packets that arrive from both inputs must compete for the same output, only one will be forwarded to the output whereas the others will need to be temporarily latched (if storage space is still available). If this is not done, packet loss may occur. An interesting variance of the basic design shown in Figure 14.4 is that provisions of buffering traffic may appear at the input, at the output, or at both of the switching element. In addition to buffer- ing inside the switching cores, this more generic approach of buffering at the input or at the output of a switch offers flexibility and various possibilities of configuration to the designer who strives to achieve an overall design 