ccurs as illustrated in the preceding section (see Figure 2.18(a)). However, a contribution will also be made to the clock edge jitter by the incoming data signal. The decision-making process at the regenerator requires that the extracted clock follow any phase variations in the incoming data. The most important is the relative timing of a particular decision instant, as far as the instantaneous SNR and the decision error prob- ability are concerned-that is, the difference in the time position at the clock edge with respect to the most favorable decision time for the particular incoming data symbol. However, jitter will still accumulate from one regenerator to another even when jitter tracking is supporting the decision-making process at a particular regenerator. At the end of a link it might be necessary to use a stricter network clock to alleviate the jitter situa- tion. Large data buffers might be also required to decrease data slips (loss or gain of bits). Nevertheless, the most important cause of trouble is the data pattern-dependent effect due to the reinforcement of each at subsequent repeaters. PLLs carefully designed are preferred in long chains of regenerators with extreme accumulation of jitter, rather than bandpass filters in the clock selection circuits. Data scramblers can also be used at inter- mediate regenerators to break up the data patterns. Jitter Specifications Standardization is needed to specify the maximum jitter allowed in a system. These speci- fications can be in terms of Unit Intervals (UI) versus frequency for different bitrates. UI is defined as one cycle of the clock frequency. The jitter measurement will then be the fraction of the variation with respect to the ideal period of the clock. This kind of metric allows comparison of different bitrates because it scales with the clock frequency. Other metrics include absolute units such as picoseconds, degrees, or radians. For example, if a clock rate of 622.08 MHz is considered, 1 UI will be equal to the period of the signal, which will