he output of the component. This architecture is shown in Figure 7.33. The serial signals at the output of the deserializer are completely different from the real tributaries of the high-speed signal, since they are obtained artificially dividing the signal, without any reference to the structure of the signal itself (the deserializer is not an elec- tronic demultiplexer for this reason). Thus, no grooming or sub-wavelength switching can be done; the signal is simply rear- ranged differently to ease the switch fabric work. Once the signal is SO rearranged, the switch fabric can work on lower speed signals, but increases its dimensions correspondingly. On the contrary, if no deserializer is used, the signal is directly sent to the switch fabric without any parallelization. The first solution is convenient either when other kind of processing has to be done on the signal or when the transmission is at 40 Gbit/s or beyond, to reduce the required switch bandwidth. One of the most used, architecture of the switch fabric itself is the Clos architecture that is strictly nonblocking and exploits at best the bigger crossbar chips that can be realized. An example is reported in Figure 7.34, where it is imagined to build up a nonblocking switch fabric with a crossbar chip 200 x 200 obtaining a 10,000 X 10,000 switch. This exam- ple well represents what happens for OXCs with input channels at 40 Gbit/s. As a matter of Switching Systems: Architecture and Performances Synchronization Deserializer Switch Serializer Tests and clock generation fabric realignment High-speed signal after regeneration Clock period Original and scaled clock scaling distribution FIGURE 7.33 Architecture of an OXC based on a low internal bit rate electrical switch fabric. 50x 100 200 X 200 100 x 50 20,000 interconnects FIGURE 7.34 Scheme and interconnects number of a Clos 10,000 X 10,000 nonblocking switch fabric. fact, designing the fabric to work at 2 Gbit/s and if four input WDM systems are foreseen with 128 wavelengths each, a switch of 10,240 x 10