 inventory of the 2400 NPU capabilities. Rather, we show what can be expected from its specifications. This flexibility provides industry-standard cell and packet interfaces to media and fabric devices that deliver a performance rate of 4 Gbps. Therefore, the 2400 can support OC-48 plus fabric encapsulation overhead or even four channels of 1 GbE. The standard interface also simplifies the design and interface to custom ASIC devices that a customer may decide to connect. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. INTEL IXATM NETWORK PROCESSORS 82 NETWORK PROCESSORS On the other hand, the 2800 offers SPI-4 Phase 2 operation based on a transfer clock of 311 to 500 MHz using 16-bit Low-Voltage Differential Signaling (LVDS) dual-edge signaling. Figure 5.2 shows the internal architecture of the Intel IXP2800 network processor. The switch fabric can also be inter- faced using a CSIX interface with the same clock rating and LVDS dual-edge signaling. In terms of memory banks, the 4 channels of quad data rate (QDR) SRAM offer the IXP2800 a peak bandwidth of 1.6 GBytes/sec per channel using 200 MHz SRAMs (800 MBytes/sec read and 800 MBytes/sec write). The 3 channels of RDRAM offer a peak bandwidth of 1.6 GBps (12.8 Gbps) per channel, sup- porting 800 to 1066 MHz RDRAM. Notice that bandwidth on memory interfaces is quoted in megabytes per second (MBps) or in gigabytes per second (GBps) (corresponding to stored capacity measurement units, file sizes, and SO on), whereas transfer rates on serial links are rated in megabits per second (Mbps) or gigabits per second (Gbps). The QDR SRAM interface is used for lookup tables, access lists, content-addressable memory (CAM) or ternary CAM (TCAM) associative mem- ories, the connection of Internet Protocol Security (IPsec) coprocessors, and other coprocessors stan- dardized by the Network Processing Forum (NP