is higher priority to internal events than to signals from ENV). 7.3.8 Bit-state simulation with a user-defined rule We want to detect that in our V.76 SDL model: instance 1 of process AtoB is in state ready, and instance 1 of process BtoA is in state ready. 218 Validation of Communications Systems with SDL More details on user-defined rules are provided in Chapter 5. A. In the Organizer, select the SDL system V76test and press the Validate button. B. In the Validator command line, enter: Define-Rule state (AtoB:1) =ready and state (BtoA:1) =ready C. Select Options1 > Report : Abort, and choose UserSpecified. After one report, the simula- tion will stop. D. Press on Bit State, the Validator displays: Search depth : 100 Hash table size : 1000000 bytes Bit state exploration statistics No of reports: 1. Generated states: 3. Truncated paths: 0. Unique system states: 2. Size of hash table: 8000000 (1000000 bytes) The simulation is terminated because the Validator has encountered a global state where the rule is true. The Report Viewer appears, as in Figure 7.40, showing that the rule is satisfied. To view the corresponding MSC trace, double-click on the lower box in the Report Viewer. Report Viewer 1 report 1 UserRule User-defined rule satisfied Depth: 2 Figure 7.40 The Report Viewer showing that the rule is satisfied 7.3.9 Verifying an MSC with bit-state simulation You will simulate the V.76 SDL model, observed by the basic MSC testl.msc. The Validator also accepts MSCs containing in-line operators and High-Level MSCs (HMSC). Check that in testl.msc there is either a single environment instance named env_0 or two environment instances named DLCaSU and DLCbSU (the names of the two external channels in the SDL model), otherwise the simulation would not match the loaded MSC. Exhaustive Simulation 219 More details on verifying an MSC are provided in Chapter 5. A. In the Organizer, select the SDL system V76test and press the Validate button. B. In the Validator, press on Verify MSC, and select the MSC testl.msc. The Valid