can be implemented next to a full-fledged TOE inside the same piece of silicon. Although the answer is not a flat-out no, the objective remains largely elusive if today's state-of-the-art very large scale integration (VLSI) design tools and semiconductor technologies are considered. This is because in addition to the massive cryptographic prowess that such a chip must have, it must also be able to correctly terminate several thousands of TCP/IP-based iSCSI and FCIP connections with low latency and at line speed. Each connection carries multigiga- bit-per-second traffic. It must also be superbly intelligent and flexible SO that it can manage all of these sessions seamlessly and properly, ensuring compatibility with multiple systems and different software systems. This seems quite a few years away from today's reality. Therefore, IPsec processing for IP stor- age networks in the short to medium term will most likely have to be implemented as a small daugh- ter-board carrying a couple of complementary-function chips. This daughter-board would work as an adjunct coprocessor to the main SNP. With the evolution of semiconductor technology, the problem may be addressed in a more integrated way, especially if cryptographic advances allow the more effi- cient performance of several of the necessary operations in less time and using less silicon real estate. The security industry is already taking some interesting initiatives to address these issues in a com- prehensive manner. For instance, Hifn (a leading IPsec accelerator chip design house-see www.hifn.com) has formally teamed up with Trebia to formulate a next-generation security frame- work that addresses these concerns. NetOctave (another major IPsec-accelerator semiconductor com- pany [see www.netoctave.com]) is pushing its flow-through architecture forward to efficiently tackle IPsec processing at endpoints in need of storage network processing at line speeds, as opposed to the traditional look-aside approach to IPsec computations. Tehuti Networks (www.tehutinetwor