DRAM for the performance of billing operations. This usually implies the use of a read/modify/write sequence involving transfers of 42 and sometimes even 128 inefficient bits (if the memory interface is 64 bits wide) to update a 21-bit counter. The iAC handles this type of operation internally with a single command. Its horsepower allows the equivalent of roughly 20 counter operations per packet at a traffic throughput of 30 Mpps. The iAC comes in a 520-pin ball grid array (BGA) package and typ- ically consumes 5 watts. In a typical line-card application, such as the one shown in Figure 9.1, the packets arriving from the line interface are handed over to the iPP to initiate the required processing. The iPP extracts the Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES OTHER NPU ARCHITECTURES 141 desired search keys from the packet header (and in some cases, from the packet payload too). engages the CAM of the iCL to look up the keys. Based on that, a route lookup is then executed on the iAP chip, which can yield per-hop or per-entry data in a single pass. The classification results are then handed over by the iPP to the iAC, which polices the packet and brings billing data structures up-to-date with the compilation of needed statistics. Following the classification and policing work, the iPP sometimes modifies specific fields on the packet according to the application, such as creating encapsulations or updating bit fields in the header. An internal bit tag (flow identification number) is generated and attached in front of the packet for internal tracing by the traffic manager. The packet is then turned over to the iTM, which handles queuing and other typical traffic management functions. In terms of development tools, the company provides a C-language compiler and a source-level debugger. Although the programming model