on the hopped carrier patterns. It is on this leader sequence that the two-level synchronization scheme must acquire and, hence, the length of the leader represents the maximum time (in hops) that the receiver has for FH acquisition. The way in which the acquisi- tion is accomplished is as follows. Each of the hop patterns begins with a specific short segment (say m hops long) referred to as a sync prefix. A passive correlator (m-stage matched filter) is used to detect this short m-hop sync prefix and generate a code start signal for those intervals in which its detection threshold is exceeded (see Figure 3.12). The code start signals as they occur each engage any (one) active correlator from the total bank of correlators provided and cause it to cycle through the remaining (say k m) hops in the pattern. Non-coherent detection and post-detection integration over these k hop intervals produces an output which is compared against a second threshold. If this threshold is exceeded the test terminates and sync acquisition is declared. Otherwise, the active correlator is again made available to the common bank. If all active correlators are engaged (none are idle) when a code start signal occurs, then this signal is ignored. Since typically the size (say C) of the bank of active correlators shared among arriving code start signals can be chosen much less than k, then a sig- nificant reduction in hardware is potentially possible compared to a full (m + k) parallel correlator structure. Clearly depending on the relative choices of m, k, and bank size C, and the number (say n) of repetitions of the hopped carrier pattern in the leader, a variety of performance tradeoffs are possi- ble between the two extremes of the traditional single-level active and single- level passive correlation schemes. The notion of estimating from the received signal the state of the linear feedback shift register (LFSR) that generates the local PN code in DS/SS systems (see the discussion of rapid acquisition by sequential estimation in Chapter 