the gate up to the interface, as illustrated in fig. 25. Thickness Applied electric fied Figure 25. Schematic representation of the field dependence of the measured voltage shift, for a uniform bulk charge trapping (left). The corresponding trap distribution (NT=cst) and charge distribution (x) in each case (E>0 and E<0) are also shown (right). The centroid of the trapped charge is in this case close to the SiO2/Si interface, and the image charge induced in the silicon substrate is therefore sizeable. Charge trapping also increases with increasing applied field, because the fraction of holes escaping initial recombination increases, and more holes are available to be trapped. For a similar irradiation, but under a negative bias and uniform trap density, the trapping process is symmetrical. Holes flow toward the gate, but can however get trapped in the oxide bulk. The centroid of the trapped charge is then displaced toward the gate, and the image charge induced in the silicon substrate is less important than under a positive bias. A similar dose of irradiation, but deposited under zero applied bias, leads to a very small voltage shift, smaller than that obtained under negative and positive bias. Indeed, under zero applied bias, the fraction of separated pairs is far smaller and recombination is enhanced, and thus, the number of carriers likely to get trapped is greatly reduced. The V ot (E) curve, obtained in the case of a uniform trap distribution, displays an almost symmetrical behavior with regards to the sign of the applied field. The shift obtained under negative field remains however smaller than that obtained under positive field. By integrating the trapped charge profiles shown schematically in fig. 25, we can evaluate the associated voltage shifts. In this case of uniform trap distribution, and if the trap density is not too high, it has been shown that analytical calculation as developed above leads to a Vot/D ratio of 1/2. III-40 MOS Capacitors NMOS Transistors Applied gate voltage (V) Figure 26. The vo