he second component of the back-end module is a K-qubit measurement gate, which restitutes the P1Q2 OK bits. The full PE circuit including front and back ends, is represented schematically in Fig. 20.2, assuming that the phase Q is exactly defined by K bits, or 2K Q is an integer. Consider next the more general case where 2K Q is not an integer. Let us calculate the state of the output register after the circuit shown in Fig. 20.2. Starting from the input 10) |u), and based on the result in Eq. (20.1) followed by the inverse Fourier transform, we have the following state evolution: (20.9) The probability of measuring n from the output register (or the probability of the N-qubit register being in state |n)) is given by the square modulus of the corresponding amplitude, namely, from Eq. (20.9): (20.10) Shor's factorization algorithm Q1... QK Figure 20.2 Full quantum circuit for phase estimation, with (a) front-end and (b) back-end modules. The measurement of n, with associated probability p(n), corresponds to the phase estimation = n/N. The probability is maximal when 8=4-0 is minimal. The probability defined in Eq. (20.10) rapidly vanishes as the error 8 departs from this minimum. The conclusion is that the measurement has the highest probability of yielding the closest approximation of the phase Q. Based on the results in Eqs. (20.9) and (20.10), it is also established that the circuit output is of the form 1) /u), where 1) is a state superposition which, when measured, yields a fair approximation of the phase Q. It is an academic issue, which I shall not address here, to determine the size of K required for obtaining a phase accuracy of 2-1 (or l bits) with an arbitrary high probability of success. Suffice it to provide the result of the analysis: for this probability to be at least 1 - E, the rule is that the control register size must be K=1+ [log2[2 + 1/(2s)]]. It is readily checked that the probability's lower bound increases from 50% (E = 0.5) to 99% (E = 0.01) and 99.9% = 0.001) withK=1+2,K=1+6, and K resp