y Steve Leibson called "Jazz Joins VLIW Juggernaut," which appeared in the Microprocessor Report publication on March 27, 2000. It is available by subscription at www. imdronline.com/mpr/h/2000/0327/141303.html Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES The Jazz platform enables the easy integration of multiple VLIW processors inside an SOC. Each one capable of executing between 8 to 12 operations per instruction. Each processor communicates with other processors through a proprietary on-chip fast Q-bus where control messages are exchanged. Data is passed on between processors by using shared banks of embedded memory. The advantage of this approach is that in a multiprocessor SOC, contention will never appear among processors for access to memory or a shared bus. The technology can be easily scaled to extraordinary computational capabilities. In addition to the hardware platform and architecture, the Improv approach deserves some serious attention for its advanced development tools and overall design flow approach. Designers first describe the architecture that they have chosen into the company's interactive tool suite, either based on one of the company's several standard configurations or by embedding one or more designer-defined computational units (DDCUs) next to one or more Jazz VLIW CPU cores. The DDCUs can be essentially any piece of hardware logic that may be required to properly execute an application. The designers then use ordinary Java language along with a few extensions in some handy class libraries that the company has created as a notation tool to correctly describe behavior. The rea- son for this choice is that Java competency is much easier to find as a 