new CPUs would run much faster if the novel RISC architectural schemes that the designers had developed were used. A typical example would be loop and branching look-ahead in iterative code. Unfortunately, tak- ing full advantage of the capabilities of a RISC CPU involved a deeper architectural understanding on behalf of the programmer, which he or she rarely had. Writing code in assembly was no longer an option (except for some minor optimization parts of an application) as the underlying CPU was designed to decode extremely simple operations. The programmer would prefer the opposite-that is, to compact as many different logical operations within the boundaries of one single instruction (a phi- losophy created in the minds of most computer science graduates largely by the CISC industry legacy). Therefore, the burden had to be shifted onto the compiler tool developers, who had to create new types of sophisticated development tools for these new processors, if these CPUs were to ever stand any chance of commercial success against the established market presence of CISC CPUs. 37. P.A. Perrier, "Position, Functions, Features and Enabling Technologies of Optical Cross-Connects in the Photonic Layer," Technical Paper, Alcatel, Nevada, September 1999. 38. David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface (San Francisco: Morgan Kaufmann Publishers, 1997). 39. John Hennessy, David Goldberg, and David A. Patterson, Computer Architecture: A Quantitative Approach (San Francisco: Morgan Kaufmann Publishers, 1996). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. THE EVOLUTION OF NETWORK TECHNOLOGY: DISTRIBUTED COMPUTING AND THE CONVERGENCE OF NETWORKS THE EVOLUTION OF NETWORK TECHNOLOGY 21 Around the early to mid 1980s, the speed of electronics enabled the faster digitization of analog signals (voi