ponents in the integrated small cell. Chapter 4 Hardware architecture choices Networking processor/host The NPU is considered the central point of the architecture, providing Wide Area Network level connectivity to the CU or Core Network (e.g., 3GPP S1 interface) as well as hosting upper layer (control plane) stacks, 5G L2 U-Plane, modem drivers and application Virtual Machines. Typically defined as a custom networking centric SoC, this chip supports loads for networking functions such as IPSec/GTP tunneling functionality, Ethernet switching/routing, and QoS. Depending on performance and cost tradeoffs, this is typi- cally an SoC in the 5-25 W DC power range. It interfaces to the 5G modem (and/or other modems) through a PCIe interface (physically) and FAPI (logically, Application Protocol Interface or API). If the ISC is not 5G-only but supports additional wireless air interfaces such as Wi-Fi (both 2.4 and 5/6 GHz), these are also connected over PCIe. Separation of the NPU from the 5G modem is new to the 5G era; in the 4G days, the host and modem were supported on a single device that would implement both the and Physical Layer stacks and provide embed- ded Ethernet connectivity as mentioned above. In a multimode 4G/5G scenario, the legacy 4G modem is connected over Ethernet (RGMII). Given Ethernet connectivity, routing of S1 frames to the 4G modem can be handled by the networking functions in the Networking Processor. System timing is supported by Networking Processor integrated hardware timing logic that supports IEEE1588/PTP, GPS and Network Timing Protocol (NTP) based frame timing. This logic can also be used to control an external (30.72/122.88 MHz) VCTCXO that drives the 3GPP modems. Hardware support for Ethernet MAC layer or PHY timestamping is expected to be supported. Timing logic can optionally be handed in a separate FPGA or CPLD implementation, external to the Networking Processor. Physical layer/5G modem Given power and cost targets in the ISC, the Physical Layer is implemented as an ASIC/ASSP devic