ve a mechanism to determine the distance, or hop count, between a clock node and the PRC/PRS (looking at Table 6-5 shows that this changes with the eESMC mechanism). In case of synchronization failures, such as that caused by physical link failure, the impacted nodes go through the clock rearrangement process to select a new clock source. If such a clock rearrange- ment is automatic, this process could pick up clock references in such a fashion that it creates tim- ing loops. One such possibility is shown in Figure 6-12, where the physical link between Switch A and Switch B suffers a fault, and although Switch B picks up another clock reference, it happens to be coming from Switch C. However, because Switch C was itself locked to Switch B, this situation creates a timing loop. SSU/BITS Switch A Switch B Single link (EEC node) (EEC node) Switch D Switch C (EEC node) (EEC node) Figure 6-12 Timing Distribution in Ring Topology with Link Failure One of the ways to prevent timing loops is to enable the SSM or ESMC mechanism on the links. As outlined earlier in this chapter, the SSM and ESMC both carry QL information, which denotes clock quality using values such as PRC/PRS, stratum level, SSU, and SO on. This can be used by the nodes during a clock rearrangement to determine the best possible input frequency source. One special value specified by the SSM or ESMC is do not use (DNU) for Option I, or do not use for synchronization (DUS) for Option II. This SSM value is sent upstream when a node selects an input frequency as a timing reference signal. It indicates that the downstream receiving node is locked onto that transmitted signal. In the example shown in Figure 6-13, Switch B sees that its link to Switch A is traceable to a PRC, SO it selects it as an input frequency reference. When it does this, Switch B sends DNU back to Switch A to indicate that Switch A should not use this signal as a candidate for clock input. This mechanism warns the transmitting node not to use the clocking information, as it originated fro