E APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES NETWORK PROCESSORS performance nor complexity management of multiprocessor integration is required. Several interest- ing articles9 and application notes about the engagement of configurable processor technology from Tensilica and ARC in the network-processing field are available. Some of them can be found either directly from the web sites of the individual companies involved or from the trade journals mentioned in the list of references. IMPROV SYSTEMS A completely different architectural approach to the IP core-based SOC design problem has been taken by Improv Systems (www.improvsys.com) and its JazzTM VLIW CPU technology. 10 The com- pany originally pursued the network-processing market, but recently it seems to have steered more heavily into applications that require extremely powerful scalable embedded DSP processing. This does not preclude the use of its approach in fast communications processors, which is why we discuss it here. Figure 10.12 illustrates parallel and scalable architecture based on the Jazz VLIW platform. I/O Pins I/O Pins I/O Pins I/O Pins I/O Pins I/O Module Private Shared Private Shared Private Shared Private Shared Private Memory Memory Memory Memory Memory Memory Memory Memory Memory Engine Engine Engine Engine Engine Instruction Instruction Instruction Instruction Instruction Memory Memory Memory Memory Memory FIGURE 10.12 Parallel and scalable architecture based on Improv's powerful Jazz VLIW core platform. (Source: Improv Systems) 9. See, for instance, Loring Wirbel, "Onex Communications Corp.'s Omni Switching and Processor Architecture," which is avail- able online at www.eetimes.com/story/OEG20020721S0005, and "Bay Microsystems Uses Xtensa Processor Architecture To Reach New Heights in 10G Integration and Packet Processing Performance," which is available online at www.baymicrosystems.com/ news/press_release_tensilica_07_29_02.html 10. A nice introduction to the Jazz architecture can be found in an article b