ating system and faced with traffic that is flying in and out of the chip at multiple-gigabits-per-second wire speeds. Classical RISC tech- nology in that case, will be obliged to yield to more scalable and flexible architectures (off-the-shelf network processors) that can usually be procured and programmed more easily, more efficiently, and less expensively than custom ASICs. SUGGESTED REFERENCES Many good books are available on computer architecture. Interested readers can find valuable infor- mation in the following sources: Gerrit L. Blaauw and Frederick P. Brooks, Jr., Computer Architecture: Concepts and Evolution, 2 volumes (Reading, Massachusetts: Addison-Wesley, 1997). John L. Hennessy, David A. Patterson, and David Goldberg, Computer Architecture: A Quantitative Approach (San Francisco: Morgan Kaufmann Publishers, 2002). Richard Y. Kain, Advanced Computer Architecture: A Systems Design Approach (Upper Saddle River, New Jersey: Prentice-Hall, 1995). The following source is another book that provides a good discussion of the MIPS architecture and a complete software-based instruction simulator of the MIPS core along with many other relevant architecture-related references: David A. Patterson and John L. Hennessy, Computer Organization & Design: The Hardware/Software Interface, 2nd edition (San Francisco: Morgan Kaufmann Publishers, 1998). In terms of the reuse of IP cores in SOC designs and associated design and verification issues, the following sources are some good starting points for readers who may want to go deeper into the subject: Peter J. Ashenden, Jean P. Mermet, and Ralf Seepold, eds., System-on-Chip Methodologies & Design Languages (Boston: Kluwer Academic Publishers, 2001). Janick Bergeron, Writing Testbenches-Functional Verification of HDL Models (Boston: Kluwer Academic Publishers, 2000). Henry Chang et al., Surviving the SOC Revolution-A Guide to Platform-Based Design (Boston: Kluwer Academic Publishers, 1999). Alfred L. Crouch, Design for Test for Digital IC's and Embedded Core Systems (Up