ut number to the DDR memories is not achieved in practice. Both aspects can be made visible by benchmarking the DDR performance as described elsewhere. We show an example below that shows DDR benchmarking for random memory accesses with small (single cache line) access width as shown in Fig. 3-10: As the benchmark shows, when DDR loading exceeds approximately 50%, latency starts increasing exponentially, negatively impacting system performance. This "50%" number is used as a rule-of-thumb and can be relaxed in specific use-cases, for example, with large sequential accesses. Innovative new external memory techniques (Low Power DDR (LPDDR), High Bandwidth Memory (HBM), etc.) can have very different performance characteristics that need to be assessed independently. Note how external memory accesses are done in discrete quanti- ties of cache lines sizes, typically 64b (8byte). Besides establishing the peak or maximum practical loading of the memory interface, we need to find the application required throughput. Given the nondeterministic nature of cache-based systems, this is done by estimation. We track what is referred to as "life of a packet" (PDCP/RLC/MAC) or "life of a sample" (Physical Layer) processing through the applicable SoCs and memory subsystems to determine the memory transactions associated with the processing steps. Let's look at an example for a CU/DU combined flow associated with PDCP/RLC/MAC U-Plane processing below in Fig. 3-11. The description is done for the downlink direction. The uplink direction is assumed reverse from downlink or can be left as an exercise for the reader. Key components are described below: 120 Open Radio Access Network (O-RAN) Systems Architecture and Design Average DDR latency =f(DDR loading) DDR loading FIGURE 3-10 DDR latency as function of bus loading. Ethernet Rx-Pre-IPSec The packet Rx function receives an Ethernet frame from the Ethernet interface, either on-chip from an embedded controller or off-chip through an Intelligent NIC. The Ethernet interface writes some f