 5-20 kilorad in CMOS technologies, despite the considerable evolution these last 20 years. 9.1.3. CONCEPTUAL MODELING OF EDGE TRANSISTORS AND EXPERIMENTS More specifically, parasitic transistor can be viewed as a series of transistors in parallel. It can be shown [Flam-98], that the response of these elementary transistors can be deconvolved by considering the Vt shift of each level of current: Id (log) Fixed Drain Currents 1.00E-11 Before Irradiation 1.00E-10 1.00E-09 After Irradiation Thin Transistor 1.00E-08 Thin Transistor 1.00E-07 1.00E-06 y=-02854x+44 R =09901 Dose (krad) 19 20 Thick Transistor Thick Transistor y=0646x+60741 R2=09918 Vot e OX Figure 78. Method for obtaining the elementary transistors of an edge structure [Flam-98]. It is important to notice that leakage current generally evolves in time, as typified in this sequence of experiments (fig. 78). III-88 Room Temperature Evolution After Irradiation Irradiation After half decades in time (t from 103 to 3.106) Before Irradiation Before Irradiation From 10 to 20 krad by 1krad steps 3.103s 3.105s 3.104s 10-10 10-11 20 krad 18 krad Gate Voltage Vg (V) 10-10 Before 1 krad Irradiation Progressive Elevation of Temperature 10-11 Gate Voltage Vg (V) After 1x & 2x5' at T (T from RT to 300°C by 25°C steps) Before Irradiation 125°C 125°C 10-10 100°C 150°C 10-11 Gate Voltage Vg (V) Figure 79. As for gate transistors, leakage lateral is capable of time-dependence or thermally-activated recovery [Chab-97a]. As for gate transistors, this recovery can be modeled by considering the equations and parameters of the thermal detrapping for each of the elementary lateral transistors. By relating the current level and the lateral position, the energy spectrum of traps can be extracted from isochronal anneals [Chab-97a]. The reader is invited to look further in this reference. 9.1.4. NUMERICAL MODELING OF EDGE LEAKAGE TRANSISTORS We follow here the method exposed in [Briss-96], applied to LOCOS (however, this method can be generalized to any edge structure). elementary t