le, at junction points. As a result, conflicting packets can be judiciously delayed where and when it makes sense. In the called shared memory switch fabric approach, which is favored by IBM, packet memory appears inside the switch fabric where incoming packets are written and from where outgoing packets are read. backplane Control Host CPU Ingress line SWITCH Egress line FABRIC Ingress line Egress line Ingress line Egress line FIGURE 14.5 The conceptual architecture of a typical switch-fabric-based MSR/ multiservice switch. Ingress and egress functions reside physically on every single line card. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SWITCH FABRICS 274 NETWORK PROCESSORS For some applications or, more specifically, in cases where congestion appears, this embedded mem- ory may not turn out to be sufficient. The systems designer must then introduce buffering on the ingress card as well. Whether this is feasible or desirable will largely be dictated by the answer to a separate question - namely, whether in this case network processors that are used on the line card have enough embedded static random access memory (SRAM) for such buffering. IBM fabrics contain a 4K-packets buffer (as shared memory) for congestion. In addition, IBM pro- vides a 2K virtual output queue (VOQ) per line card in the card interface chip of the fabric chipset. Therefore, a 32-port system would have 4K 1 2K332 68K packets to handle congestion, since with- out congestion, this memory is free. Fabric vendors such as IBM then expect some VOQ capabilities from the network processing unit (NPU) on the line cards, handling things at the flow level (as the fabric is completely unaware of flows). Their success in design wins and factory orders indicates that they are doing the right thing as far as the market is concerned. This is an unrelated issue for the specific t