structive Failures The concerns for TID failure and soft errors treated in the last two sections are serious issues for designers, but the possibility of an unrecoverable catastrophic failure from a single particle event ranks among the highest concerns. Where cosmic ray heavy ions are present, proton-induced hard failures may not be the dominant threat from the natural environment; however, these failure modes should not be overlooked. In the three sections below on Single Event Latch-up (SEL), Single Event Burnout (SEB), and stuck bits, we examine the various ways in which proton-induced single events can render a circuit unusable. 4.3.1 Latch-Up (and COTS): We first consider SEL with the recognition that it is not solely a COTS issue, but it is a major concern when using COTS CMOS parts in space. Latch-up in CMOS devices is well understood in terms of a particle-induced triggering of an SCR action in a parasitic p-n-p-n path. Details of the mechanism, modeling tools, hardening approaches, and references to related topics are in covered in the NSREC Short Course Notes from 1996 [John-96]. It should be noted that not all latch-up modes lead to destructive failure, and in some cases power cycling may be used to restore nominal operating conditions. For many years, SEL was considered to be a CMOS phenomenon only in cosmic ray environments, but at the 1992 NSREC two papers reported first the laboratory confirmation of proton-induced latch-up [Nich-92] and the observation of a proton-induced latch-up event in space [Adam-92]. In these studies, the affected CMOS devices were either on a bulk or a thick epitaxial substrate, and the corresponding heavy ion latch-up threshold was fairly low (below 10 MeVcm2/mg). Even so, the proton energy threshold below 50 MeV for both cases suggests that proton-induced latch-up may be a higher risk than cosmic ray induced latch-up in mid-latitude LEO applications. Since 1992 there have been many examples of proton-induced latch-up, both in the laboratory and in-flight. Table 2 has bee