y, he or she securely submits to Tensilica through the company's web site the configuration files that the processor gener- ator produces. Within an hour or so, the company's tools will generate a completed set of customized development tools that the user can download. With the arrival of the company's fifth-generation technology in the fall of 2002, several impor- tant enhancements were made: With the intention to maximize the usable I/O bandwidth and to improve the communications between multiple embedded processors in an SOC, Tensilica enhanced the core processor's Xtensa Local Memory Interface (XLMI), which now allows multicycle devices to be attached with variable latency. A convenient incoming request feature for the Xtensa Processor Interface (PIF) now enables an Xtensa CPU to simultaneously execute instructions and handle read/writes to the processor's local data memory. This can be useful for some external functional modules in an SOC (such as DMA engines) that need to get in touch with a specific processor or, most importantly, for other tightly coupled processors. With configurable interface widths up to 128 bits, the Xtensa processor can deliver a peak I/O bandwidth of 45 Gbps. The addition of a processor ID register to the instruction set architecture (ISA) can identify each unique processor integrated on an SOC. This eases system software development when an overlay application must be broken down to pieces that need to be allocated to specific processors. It can 2. According to the company, this greater than 400 MIPS number is derived from a Dhrystone V2.1 benchmark. For the Dhrystone benchmark, with no in-line code or file-merging activities, Xtensa V achieves 1.2 MIPS/MHz. With optimizations (in-lining and file merging), Xtensa V has been reported to achieve an impressive 2 MIPS/MHz or over 700 MIPS if the core is clocked at 350 MHz. It should also be kept in mind that MIPS is not a good metric for a configurable processor for obvious reasons. For exam- ple, one single Tensilica Instruction Exte