. This time, the exhaustive simulation has discovered 77 exceptions instead of 568, as indicated in the results: (8192 states 19777 trans. 0 seconds, depth=13, breadth=1925) (16384 states 40292 trans. 1 seconds, depth=15, breadth= 3944) verify stopped by states limit Number of states : 20000 Number of transitions : 49140 226 Validation of Communications Systems with SDL Maximum depth reached : 16 Maximum breadth reached : 6115 duration : 0 mn 1 S Number of exceptions : 77 Number of deadlocks : 0 Number of stop conditions : It proves that the model has been improved by the previous correction. 7.4.2.2 Replay the exception scenario Again, the Simulator has generated two scenario files: v76.x1.scn and v76.x2.scn. A. In the Simulator, select File > Scenario > Load, and open v76.x1.scn. B. Press the button Redo: All. The Simulator replays the scenario, reaches the exception, and displays: Unexpected signal l_releasereq in dlcb!dlc(1) , line 907 of v76.pr 14 transitions executed end of scenario execution The Editor displays the MSC trace of the exception scenario, shown in Figure 7.47. bug_exh2 inst_1_dlca.dispatch inst_1_atob inst_1_dlcb.dispatch PROCESS/ PROCESS/ PROCESS/ v76test/dlca/ v76test/ v76test/dlcb/ dispatch(1) inst_1_dlca.dlc datalink/atob(1nst_1_btoa dispatch(1) l_estabreq( 0) PROCESS/ PROCESS/ v76test/ v76test/ dlca/dlc(1) datalink/btoa(1) v76frame( sabme : (.0.) v76frame( sabme : (.0.) ) t320(12.0) I_estabind(0) inst_1_dlcb.dlc PROCESS/ I_estabresp v76test/ dlcb/dlc(1) releasereq( 0 |_releasereq( 0 I releasereq( 0 ) I_releasereq( 0) v76frame( ua: (.0.) v76frame( disc (.0.) Figure 7.47 MSC trace of the exception scenario C. Enter the command print state; the Simulator answers: > print state btoa (1) ! state = ready Exhaustive Simulation 227 atob (1) ! state = ready dlcb!dlc (1) ! state = waituadisc dlca!dlo (1) ! state = waitua dlcb!dispatch ! state = ready dlca!dispatch ! state = waitua We see that process DLC in block DLCb is in state waitUAdisc. If we look at the SDL model, under this state no input or