There are two Central Processing Units (CPU) based on 32-bit microprocessors operating in parallel, simultaneously executing the same instructions with the same data. They are linked by a Mate 32.14 DMS-Core Exchange Bus (MEB) for fault detection and maintenance purposes. Each has its own integrated Program and Data store, data changes DMS SuperNode employs a distributed processing architecture. in the active CPU data store being copied to the inactive one across Real time functions associated with a particular facility or periphe- the MEB. Message links DMS-Bus DMS-Core Program Program CPU 0 CPU 1 SLM 0 SLM 1 Figure 32.15 DMS central control DMS-Bus 32/23 Directly associated with each CPU is a System Load Module Oriented Type Enforcing Language), a high level language de- (SLM) incorporating a Winchester disk for software loads and a veloped at BNR. PROTEL is a block structured, type enforcing magnetic tape cartridge drive for archiving. This allows more rapid language that enables extensive type checking on the source code at loading and saving of software than via the Input/Output Controller. compile time. Crossover buses are provided to allow either CPU to be loaded by In both generations of the DMS, multitasking in real time is based either SLM. Periodic back-ups of the contents of Program and Data on processes that use messages to communicate with one another. Stores (Office Image) are taken on the disks and are constantly made These messages can be exchanged by processes within the control available to the system for use in the event of a major system failure. component; they can also be exchanged by control component Reloading and full recovery after a total system failure (e.g. after processes and processes in the Switching Network or in the Periph- power supply failure) is fully automatic. eral Modules. The first generation systems are generally similar but use 16-bit The software is structured in functional layers so that each layer microprocessors, separate stores for Data and Program and are not prov