 solution. However, for the moment, our designer does not need to make up his or her mind fully. Control Plane CPUs on Line Cards The load of the 10 GbE cards will definitely justify something like a 7410 PowerPC as host CPU, whereas a PowerQUICC 3 class CPU or maybe a PowerPC 750 would usually be expected for the other lower-speed line cards (4X1 GbE and OC-48c). Incidentally, our designer realizes that such a PowerQUICC 2 or 3 CPU should also be placed ideally (but not nec- essarily) on the switch fabric cards to make a more complete design with diagnostics and handle front- panel light-emitting diodes (LEDs). Resources Budget The designer then starts adding up the available resources needed. Using the Agere simulator from the Festino development environment, the main data plane applications will be written, tested, simu- lated, and evaluated at typical and worst-case scenarios of traffic based on the available modeling. Downloaded from Digital Engineering Library McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SYSTEMS ENGINEERING ISSUES 354 NETWORK PROCESSORS Then the number of instructions that must be executed per second, as well as instruction memory and data memory requirements, will be tabulated for each line card's computational needs on the ingress and egress paths, depending on whether one or two NPUs are used on each card. The findings should corroborate his or her initial choices for CPU at each instance, or the choice will have to be revised. The process will continue on the control plane CPU as well as on the system CPU based on the development tools that are available by the operating system of choice, such as Linux or VxWorks. A similar budget for control plane CPUs will be compiled and the appropriate choices of CPU and mem- ory locally on each card will be settled upon. This has been a very brief overview of how to tackle the issues of designing real-life equipment. F