 force the CAM vendors to optimize their interface mechanisms to accommodate at least the most widely used NPUs from established leading companies, such as AMCC, IBM, Intel, and Motorola. Of course, the NP industry is still very young. Many players are still alive and active (although a couple have gone out of business as of this writing because of the financial rigors of the market). Until some inevitable industry consolidation occurs, vendors are entitled to their view of the world. Because some NPU vendors still claim that CAMs are not needed because they already provide embedded SRAM in their NPUs to store the associated date, the NPU-CAM interface problem is not even being discussed. However, the majority of established vendors do think differently. This is why announce- ments are constantly being made between CAM and NPU vendors about how they propose to tackle the problem. One of the interesting efforts is the work that is being done at the Network Processor Forum (NPF) and, more specifically, at the Look Aside Task Group (organized under the Hardware Working Group). This organization strives to provide standardized mechanisms for interfacing between all types of coprocessors and network processors. This effort can have very important ramifications of the ability to natively connect CAMs (search engine coprocessors) on NPUs. CAMs are accused of being expensive. In absolute terms, this is true, especially since some of the latest CAMs are almost more expensive than an NPU or a regular DRAM chip. The truth of the mat- ter, however, is that CAMs are very sophisticated devices that are absolutely indispensable in most designs and cannot be considered as a commodity product. Their complexity and manufacturing entail yield issues precisely because they push the silicon technology process envelope to its quality limits. In our view, only time and consistently larger quantities (such as those experienced by other success- ful semiconductor products) will improve the situation. Hopefully, we will see an improvement