al studies of SEU mechanisms in SRAM," IEEE Trans. Nucl. Sci., vol. 34, no. 6, pp. 1281-1286, 1987. [155] R. L. Johnson, Jr., and S. E. Diehl, "An improved single event resistive-hardening technique for CMOS static RAMs," IEEE Trans. Nucl. Sci., vol. 33, no. 6, pp. 1730-1733, 1986. [156] A. Ochoa, Jr., C. L. Axness, H. T. Weaver, and J. S. Fu, "A proposed new structure for SEU immunity in SRAM employing drain resistance," IEEE Electron Dev. Lett., vol. 8, no. 11, pp. 537-539, 1987. [157] S. Verghese, J. J. Wortman, and S. E. Kerns, "A novel CMOS SRAM feedback element for SEU environments," IEEE Trans. Nucl. Sci., vol. 34, no. 6, pp. 1641-1646, 1987. [158] F. Ootsuka, M. Nakamura, T. Miyake, S. Iwahashi, Y. Ohira, T. Tamaru, K. Kikushima, and K. Yamaguchi, "A novel 0.20 um full CMOS SRAM cell using stacked cross couple with enhanced soft error immunity," IEDM Tech. Digest, pp. 205-208, 1998. [159] D. Alexander, "Design Issues for Radiation Tolerant Microcircuits for Space," 1996 IEEE NSREC Short Course, Indian Wells, CA. [160] L. R. Rockett, Jr., "An SEU hardened CMOS data latch design," IEEE Trans. Nucl. Sci., vol. 35, no. 6, pp. 1682-1687, 1988. [161] H.T. Weaver, W. T. Corbett, and J. M. Pimbley, "Soft error protection using asymmetric response latches," IEEE Trans. Electron Dev., vol. 38, no. 6, pp. 1555-1557, 1991. [162] M. N. Liu and S. Whitaker, "Low power SEU immune CMOS memory circuits," IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1679-1684, 1992. [163] D. Wiseman, J. Canaris, S. Whitaker, J. Venbrux, K. Cameron, K. Arave, L. Arave, M. N. Liu, and K. Liu, "Design and testing of SEU/SEL immune memory and logic circuits in a commercial CMOS process," IEEE NSREC Data Workshop Record, pp. 51-55, 1993. [164] R. Velazco, D. Bessot, S. Duzellier, R. Ecoffet, and R. Koga, "Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits," IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2229-2234, 1994. [165] T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technolog