ry (see section 3.5.3 in the previous chapter) to analyze the impact of the VCO's phase noise on the PLL's spectral purity. Frequency divider: Frequency dividers are often implemented by means of digital logic, e.g. flipflops and NAND gates. If the VCO oscillation frequency hits the RF range, then we need, as part of the frequency divider, a prescaler that can handle these high frequencies [Demu02]. Due to their digital nature, frequency divider operations are typically triggered by the zero-crossings of the incoming VCO signal. A detailed time-varying model would therefore involve an interconnection of sampling and filter- ing operations. A similar argument can be made for prescaler architectures, e.g. the phase-switching architecture in [Cran98]. Introducing the noise before the integrator is needed to account for the cumulative nature of oscillator phase noise. 4.2.5 PLL closed-loop input-output HTM However, as was the case for modeling the VCO behavior, such a detailed frequency di- vider model would be overly complex, introducing a multitude of irrelevant behavioral details11. In practice, the frequency-divider model depicted in the right-hand block of Fig. 4.11 captures most relevant behavior. Here, the frequency-divider divides the in- coming VCO frequency by N. This result is delayed by a time Tfd before it is passed to the PFD. Typically, if present at all, the delay time Tfd is proportional to the period of the VCO signal. Hence, for a given input frequency, it can be considered constant. The resulting frequency divider model can be described as a time-invariant filter e-sTfd (4.44) The corresponding HTM HFD(s) is a diagonal matrix similar to the one in (4.37). 4.2.5 PLL closed-loop input-output HTM Having constructed the building block models, we can now tie them together in order to obtain the HTM that describes the PLL's overall behavior. In what follows, we focus on the HTM that characterizes the tranfer from the input phase Oin(t) to the output VCO phase O(t). Computing HTMs associated with other i