on to the problem. The ClearSpeed TLE is an optional part of that solution. It can be used in application areas where more than 100 million searches are needed per second. Figure 12.6 shows the arrangement of the ClearSpeed TLE. It is based on a proprietary implementation of the level compressed (LC) trie algorithm with some improvements including the number of memory accesses needed per lookup. Typically, each branch of the tree held in memory requires a memory access. Level compression causes branches to vary in depth; therefore, the algorithm causes lookups with a varying number of memory accesses. The table data is distributed over a series of memory banks, some of which may be SRAM, DRAM, embedded, and external. ClearSpeed provides the software tool that will reformat typical routing tables in a format that optimizes the use of the TLE. This software can run on the ClearSpeed NPU or on a typical control plane CPU. It has many interesting and powerful search fea- tures, such as programmable tree depth for table size versus performance trade-offs, LPM with and without false hits, multiple tables, and configurable search key size and results index. The company's software also allocates the table entries to the various memory banks, SO the most necessary ones will be accessible from embedded RAM. The memory banks are also accessible to any device that has access to the on-chip ClearConnectT bus and can therefore be managed if nec- essary from another processor such as the control plane CPU. One of the advantages of this solution is that the table can be searched and managed simultaneously, minimizing the downtime for mainte- nance. The company also claims it has developed a strategy that allows the incremental replacement of a table by only requiring that 10 percent of the table be kept in memory as opposed to storing an extra copy of the entire table. The lookup elements (LEs) are highly optimized state machines that can completely traverse the tree accessing any of the memory banks required for the search. Unl