ng frequency Timekeeper (In out) (In out) Figure 12-3 SETS Architecture for Phase and Time Synchronization in Synchronous Equipment Because there can be multiple ToD and 1PPS inputs (from different front panel ports of the NE), hardware-based multiplexer (usually implemented in an FPGA) is used to select the input from among the configured ports. The 1PPS multiplexer design has its own complexity because the ex- pectation is that the multiplexer itself should not delay the 1PPS signal while passing it to the phase PLL in the SETS device (any delay results in phase error). The PLL residing inside the SETS device recovers the phase from the 1PPS input. As illustrated in Figure 12-3, the SETS device uses the recovered phase to generate a 1PPS signal for internal use, and the same 1PPS signal can also be routed to the external 1PPS port for output. This allows a quick method for an engineer to check the phase offset of a device by use of external phase measur- ing equipment (see the section "Field Testing" toward the end of this chapter). The output 1PPS signal from the SETS device is also carried to other hardware components on the system. The main components that need this 1PPS signal are the timekeeper and the timestamping unit (TSU), which uses the 1PPS signal to maintain an accurate time of day for the system. Main- taining and distributing this accurate time of day around the NE requires careful hardware design. In the absence of PTP, the time of day is periodically received from external sources (such as once every second) by a combination of the external 1PPS and ToD signals. However, during this period between updates, the time of day needs to roll forward with the correct frequency for it to maintain good accuracy. To achieve this, the time of day is maintained in a piece of hardware (usually imple- mented in the FPGA, although some SETS devices also have the capability to maintain current time) that needs to be fed with the synchronized frequency for it to increment time accurately. Fig- ure 12-3 represent