bu- tion hierarchy. But what happens when the input from the higher SSU/BITS layer is lost? As Switch A starts the clock selection algorithm, it will see that Switch D is sending it a PRC/PRS signal, SO it will select that as the best clock available. But the signal from Switch D is only traceable back to itself, and there is no PRC/PRS involved in this frequency signal. Now, once again, a timing loop has developed. If this scenario should ever occur, the clocks will all indicate that they have a frequency input that is traceable to a PRC/PRS source, but in fact, they do not because the timing signal is going around in circles, SO the frequency will start to wander. An operator might not be able to determine this state exists until they notice strange things happening in their network. To avoid this, an operator must configure Switch A to tell it that an input from Switch D is not to be selected. In this case, another source must be found, or the clocks must go into holdover. This is an analogous situation to other data protocols that need to have a break in the ring to avoid situations with loops. Figure 6-15 shows the case where the input to Switch A from the SSU/BITS layer is lost, and Switch A was configured not to allow the input from Switch D. Because no better source is avail- able to it, Switch A goes into holdover, which means SEC or EEC quality, and it sends that out as an SSM value. SSU/BITS Holdover Holdover Switch A Switch B Single link (EEC node) (EEC node) Holdover Holdover Switch D Switch C (EEC node) (EEC node) Figure 6-15 Timing Distribution with Link Failure from Timing Reference Node It is also interesting to note in Figure 6-15 that because all the clocks are of SEC quality, all the re- maining clocks also go into holdover, SO none of the clocks are aligned with each other; they are all relying on the holdover performance of their own oscillator (using saved data). 6.10 Standardization This chapter has referenced numerous recommendations from several standards development organ- izations, suc