ter all. To estimate marging, we assume the transmitter DAC cannot degrade EVM by more than 0.25% (0.6 dB impact). Assuming the following equation for system SNR < System SNR = -20log (10-sNRa/10 + 10-sb/10 +...0.10-SNRR/10/1/2 this requires adding 8.86 dB SNR margin, or rounded to 9dB. 0dB FS PAPR: 12dB Gain + AGC margin: 6dB Fade Margin: 10dB Blocker Margin: 10dB SNR Required: 25dB Processing Gain: 3dB FIGURE 3-21 ADC Dynamic Range Analysis. Chapter 3 Hardware system dimensioning 135 12 dB required PAPR to be supported. Gain errors (4 dB) consist of Gain and offset errors as caused by inaccuracies in internal reference and amplifier offset voltages reduce the usable dynamic range. Assuming gain error and offset errors to be 10% of full scale, then each contributes a 1 dB reduction in dynamic range. The DAC must be backed off 1 dB to prevent output clipping and another 1 dB to account for limited dynamic range. Add 2 dB dynamic range margin. In aggregate: 30 + 9 + 12 + 4 = 55 dB. Note, this does not include any additional safety margin. Again, a graphical representa- tion below in Fig. 3-22. PLL performance is defined by the SNR degradation for the ADC/DAC caused by clock jit- ter from the PLL. This degradation is defined by: Phase noise and clock jitter are closely related-phase noise is the instability of a fre- quency expressed in the frequency domain and clock jitter is fluctuation of the signal wave- form in the time domain. Hence, the clock jitter in time domain can be calculated by integrating the phase noise of the clock signal over a specific section of the frequency domain, where most phase noise definitions are stated as the ratio between carrier power and noise power as a function of the offset frequency from the carrier as shown in Fig. 3-23. The integration can be estimated by adding the individual section areas (A1, A6 in the plot above), from typically a few KHz in the low side up to (rule of thumb) 2x Fsample in the high side (say, 245.76 MHz for the 122.88 MHz VCXO taken in the example above): 