al routers, a First In First Out queue is not enough. In a practical case, it is probably needed to control the correctness of the data in the packet payloads by means of an EDC, and in any case, QoS rules sometimes force a packet that is not in the first cell to be extracted from the memory. In order to implement this type of operation, memories of the second type have to be realized. For this task, a different elementary cell has to be used, that is shown in Figure 10.41. This is quite similar to the queue elementary cell, but for the fact that input and output 2 X 2 switches are substituted by 3 X 3 switches. This allows the elementary cell to have more states, in par- ticular to have two write states, one for each possible input port, and two read states, one for each output port, as is shown in Figure 10.41b. When the elementary cells are arranged in series, connecting the first and the sec- ond port of the Input/output switches, but not the third, they form a queue with the possibility of inserting a packet in an intermediate position (if it is free naturally) and extracting a packet from an intermediate position. This type of queue is shown in Figure 10.42. This queue has all the required functionalities to be used in a packet switch line card. What we have presented is a general discussion around a possible implementation of optical memories suited for use in all-optical packet switches. Several other types of mem- ories have been proposed [55], which are also compatible with large-scale integration like Delay T Write from first Read from first Read from first FIGURE 10.41 Five states elementary optical memory cell: (a) architecture; (b) three cell states out of the five possible. Next Generation Networking: Enabling Technologies, Architectures, and Performances Direct read Direct write Direct read Direct write cell 1 cell 1 cell 2 cell 3 FIGURE 10.42 Scheme of an FIFO optical queue with the possibility of inserting and extracting the packets to/from intermedi- ate positions. those based on photonics crys