ful 10-GbE-based enterprise servers, a wire speed of 10 Gbps must be attainable. The systems architect must also be given the choice of using the clas- sification processor in a look-aside or flow-through configuration depending on his or her system objectives. The classification system must be protocol aware, able to handle an entire header, and look at the payload of a packet in real time. Of course, it must be able to scale in numbers of rules that can be supported and the concurrency of rules needed at wire speed. In terms of programmability, it should be easy for software engineers to master. Combining these requirements into their design specification, Raqia has come up with its impres- sive 10 Gbps deep packet classifier RQDPC10G (the name at first sounds a little kludgy and impos- sible to memorize, but there is logic behind it). Figure 13.10 illustrates the processor. The figure shows the internal structure of the chip and how it fits into an overall NPU-based system design. The Raqia deep packet classification processor can sustain flow-through-mode classification at 10 Gbps. In the look-aside mode, it offers 4 Gbps performance. It is cascadable up to eight chips deep Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. CLASSIFICATION PROCESSORS 258 NETWORK PROCESSORS for the extension of the rule database at wire speeds, and it embeds Packet over SONET (POS)/ Ethernet framing for higher integration capabilities in a systems configuration. In fact, its MAC/framer can be configured as 1XOC-192, XOC-48, 16XOC-12, or 64XOC-3 interfaces. It can also be con- figured as 1X10 GbE, 10X1 GbE, or 96X10/100 Mbps Ethernets. In some applications, it can be used as a shared classification coprocessor where multiple subsystems turn for their classification needs. It can also operate as a standalone classification processor next to a high-speed network