ngine, DMA engine) Chapter 5 System software 193 Defined by the maximum L2 packet size, typically L2 packet buffers are typically larger then 4KB and as such cannot be allocated as a physically contiguous buffer using standard Linux mechanisms. Hardware acceleration model In the discussion above ("challenge 2"), we discussed DPDK frameworks for IO and accelera- tion. We want to explore these concepts a bit more in detail. There can be two model for HW acceleration usages-look-aside and inline. Look-aside Acceleration Model (Fig. 5-5) In this look-aside acceleration model where the host CPU invokes an accelerator for data processing and receives the result after processing is complete. A look-aside architecture allows the application to offload work to a hardware accelerator and continue to perform other work in parallel-this could be to continue to execute other software tasks in parallel as shown in Fig. 5-6 or to sleep and wait for the accelerator hard- ware to complete. This model requires the API to support two operations, one for initiating the offload and another for retrieving the operation once complete. This model requires careful software design to ensure that the accelerator overhead is appropriately parallelized. VNF/CNF Interface Lookaside Accelerator HW Accelerator FIGURE 5-5 Look aside accelerator physical implementation. Software Task Latency Software Software Flow Accelerator Response Response Provided Needed Hardware Accelerator Accelerator Accelerator Latency FIGURE 5-6 Parallelizing accelerator calls. 194 Open Radio Access Network (O-RAN) Systems Architecture and Design VNF/CNF Interface Function Function HW Accelerator FIGURE 5-7 Inline accelerator. IPC Instance 0 Channel ID = 0 Channel ID = 1 Channel ID = N Endpoint 1 Endpoint 2 IPC Instance 1 Channel ID = 0 Channel ID = 1 Channel ID = M FIGURE 5-8 Inter processor communication model. Inline Acceleration Model (Fig. 5-7) In the inline acceleration model where acceleration by function and I/O-based accelera- tion are performed on the physical