fford to at this point. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. Source: NETWORK PROCESSORS CHAPTER 10 ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES We have seen that network processing is a computational area that requires several resources to ensure good performance at wire speed while preserving flexibility of the network protocols and applications supported. In previous chapters, we saw how some of the most promising network-processor archi- tectures address this problem. In order to complete our overview of the network-processing architec- tural landscape, we will turn our attention to a couple of different approaches toward achieving the same goal. More specifically, we will look at a special breed of microchips called net application-spe- cific integrated circuits (Net ASICs). We will also look at specialized integrated solutions that some companies build around IP cores. NET ASICS Net ASIC is a generic name that has been adopted by the industry to denote a special type of network- processing integrated circuit that contains specialized assist hardware (sometimes referred to as embedded coprocessors) for most functions required in packet processing; however, there is one big difference-unlike networking processing units (NPUs), a Net ASIC is not programmable. It could be argued that this lack of programmability is a mark of inflexibility, as users cannot change the behavior of the Net ASIC chip, depending on the application at hand. This is the price you pay for having the privilege of combining fast and deterministic performance (like the performa