e the impact and cross-influence between a user's architectural decisions and the underlying clock frequency (in MHz), the logic-gate count (number of gates), the silicon area (in mm²), and the estimated core-power dissipation (in mW). If the architect knows what the power or space budget is for the corresponding system design resources, he or she can easily readapt his or her thoughts and ideas in a series of iterations that ultimately lead through balanced compromises and trade-offs to the satisfaction of the design requirements at hand. The toolset is completed with a real-time operating system overlay that works with a hardware- abstraction layer on the custom-configured core processor data path. This layer also natively supports ATI's Nucleus PLUSTM or TornadoTM for VxWorks from WindRiver Systems. The company also offers a prototyping development system based on a board that uses either Altera custom-program- mable logic device (CPLD) technology or Virtex II platform field-programmable gate array (FPGA) technology, which can be used for processor emulation and early software development for some types of applications. Customers configure the processor and download from Tensilica's servers generated tools for the emulated testing of the design on the CPLD. Last but not least, it is worth mentioning that Tensilica and CoWare (www.coware.com) have been working very closely on a multiyear commitment, whereby the Xtensa V processors in configurations using multiple cores and peripherals along with multiple memory blocks are integrated into CoWare's 3. NEC engineers not only configured the Xtensa core, but they also designed 20 new powerful bit-handling instructions for ATM timer control and data queue manipulation in this ATM-centric communications chip by using the TIE language. ATM the communications among base station nodes, radio network controllers, mobile services switching centers, and gateways to the Public Switched Telephone Network (PSTN). Downloaded from Digital Engineering Library @ McGraw-Hill (www.d