. 20.12.2 DS1 Mapping One approach to mapping ATM cells into a DS1 frame is to use a similar procedure as used with the DS3 PLCP. In this case only 10 cells are bundled into a frame, and two of the Z overhead octets are removed. The padding of the frame is set at 6 octets. The entire frame takes 3 ms to transmit and spans many DS1 ESF (extended superframe) frames. This mapping is illustrated in Figure 20.17. The L2_PDU is terminology used with SMDS. It is the upper-level frame from which ATM cells derive through its segmentation. One must also consider the arithmetic of the situation. Each DS1 timeslot is 8 bits long or 1 octet in length. By definition, there are 24 octets in a DS1 frame. This, of course, leads to a second method of transporting ATM cells in DS1, by directly mapping ATM cells in DS1, octet-for-octet (timeslot). This is done by groups of 53 octets (1 cell) and would, by necessity, cross DS1 frame boundaries to transport a complete cell. 20.12.3 E1 Mapping E1 PCM has a 2.048-Mbps transmission rate. An E1 frame has 256 bits representing 32 channels or time slots, 30 of which carry traffic. Time slots (TS) 0 and 16 are reserved. 53 Octets L2_PDU L2_PDU L2_PDU OH Byte Function A1, A2 Framing Bytes L2_PDU P9-PO Path Overhead Identifier Bytes PLCP Path Overhead Bytes L2_PDU Z4-Z1 Growth Bytes PLCP Path User Channel L2_PDU BIP-8 PLCP Status L2_PDU M2-M1 SMDS Control Information Cycle/Stuff Counter Byte L2_PDU L2_PDU Trailer = 6 Octets L2_PDU 3 msec Figure 20.17 DS1 mapping with PLCP. (Courtesy of Hewlett-Packard.) 20.12 TRANSPORTING ATM CELLS Bits 129 - 136 Reserved for signalling Bit numbers Bit numbers Figure 20.18 Mapping ATM cells directly into E1. (From Ref. 1, courtesy of Hewlett-Packard.) Transmission direction 9 octets 261 octets STM-1 AU-4 PTR VC-4 POH ATM cell STM-1 SOH structure 53 octets Z2 Z2 Z2 Figure 20.19 Mapping ATM cells into STM-1 (155.520 Mbps rate), at the SDH-based UNI. [From Figure 8/1.432, page 13, ITU-T Rec. 1.432 (Ref. 4).] ASYNCHRONOUS TRANSFER MODE TSO is used for synchronizat