of auxiliary data that can be appended to each analog sample to help characterize the downstream processing. In this man- ner, trigger time-stamping and over-range conditions can be tagged per sample SO that a back- end FPGA can have further intelligence about data alignment and its validity. The adaptive gain algorithms are important in terms of adjusting the amplitude of an analog input signal, since a saturated ADC input essentially makes the system blind in its ability to decipher signals. Ideally, the gain adaptation feedback loop should be as fast as possible. Whether the high-speed ADC output is LVDS-based or uses JESD204B/C, the added latency of this digital output often can be too long to wait to receive the saturated data, detect the issue, and react to the condition. One solution to this issue is to use a variable- level comparison within the ADC core itself and directly send an immediate output flag upon occurrence of an over-range condition. This technique bypasses the latency of the lon- ger back-end output stage, which shortens the feedback time to the amplifier, allowing for a faster adaptive gain cycle. In addition to this fast, over-range detection output the over- range samples can be appended with alert bits, using the JESD204B interface, to let down- stream system processing make appropriate decisions about the data. A wideband ADC not only offers the benefits of broadband sampling, but also may provide more data than needed in some applications. For high-sample-rate systems that do not need to observe a large frequency spectrum, digital down-conversion (DDC) allows a subsampling and filtering strategy for decimating the amount of data output from the GSPS ADC. Downstream processing then observes a smaller portion of the frequency spectrum. The DDCs are often implemented after the ADC in the signal chain. This not only consumes more resources in an FPGA but also requires the full bandwidth to be transmitted between the ADC and FPGA. Instead of transmitting and processing the sampled data in a