each design implementation. However, this architecture does have some unique benefits. For example, without a clock there are no clock timing or latency issues. This lack of clock- ing results in a potential increase in data-transfer speeds. In an asynchronous system, only the frequency and length of the data transmission limit data-transfer speeds. Clocked systems have a constantly running clock, regardless of whether data is being transferred or processed. An asynchronous design can yield a potential reduction in power usage due to the lack of a constantly running clock. Asynchronous architecture can be complex to implement and verify, since traditional timing verification methods do not work. In addition, data streams coming from a backplane of this type still need to be retimed for Transmission Systems Architectures and Performances system processing. Despite these potential issues, asynchronous architecture has found favor with some designs. 6.5.3 Backplane Bus Protocols Backplane bus protocols determine-electrically and mechanically-how signals are dropped off or picked up at every device attached to the line. Protocols determine how cards pass information, the speed of data transfer, the maximum number and type of peripheral devices allowed, and the physical size and layout of the system. In general, the choice of the correct protocol for a backplane design is a complex decision that involves many design compromises. No one solution will give the best performance in each design category. A few systems simply adopt ethernet, allowing asynchronous transmission along the backplane to be performed with a consolidated protocol. Frequently 1 Mbit/s or 10 Mbits ethernet is enough, otherwise there is 100 Mbit/s ethernet that for sure satisfy all the com- munication and configuration exigencies. At present, chips performing ethernet switching and data multiplexing and demulti- plexing in the ethernet format are cheap and diffused. The issue in using ethernet is that the protocol implements several functionalities t