arry out protocols in switching machines. Technology for Telecommunications: Integrated Optics and Microelectronics Inputs C1 C2 C3 C4 Selector State Outputs Lookup table Lookup table State Lookup table Clock FIGURE 5.47 Example of reconfigurable logical block of a high-performance FPGA. (After Actel, Technical Reference for Actel Antifuse FPGAs, 2010, www.Actel.com [accessed: October 18, 2010].) We will select a particular application that is quite studied in literature and that is a key for several equalization algorithms: basic linear algebra subroutines (BLAS). We will essentially follow [63] in comparing the performances of a typical high-perfor- mance FPGA with C programs to execute linear algebra operations with both a standard high-speed central processing unit (CPU), and with a massively parallel graphic process- ing unit (GPU) running a standard mathematic kernel for high-performance and high- precision applications. The time elapsed to perform a standard operation on an NxM matrix (like the multipli- cation for a 1 X M vector) is shown in Figure 5.48. The disadvantage of the FPGA versus a fast CPU with an advanced mathematical kernel is not SO significant, and even the parallel GPU with the mathematical kernel gains only about a factor of 3 in speed, at the cost of an expensive and complex parallel processor. Moreover, a correctly programmed FPGA is superior to a standard C programming of about a factor of 1.8, qualifying as a real-time processor. On the other hand, the FPGA advantages are clear in terms of dissipated power, which is one of the main parameters to judge the electronic circuitry for signal processing. In all the considered examples the FPGA is able to go over the 3000 iteration per Joule of burned energy, while the GPU can carry out an average number of 800 iterations for burned Joule and the CPU less than 600. This is an important advantage that qualifies FPGA as a competitive alternative for many telecommunication applications, where the consumed power is a key issue. Another useful co