ment. However, the difference is that IBM's network processing unit (NPU) can access seven different external memories and one internal memory for table storage. IBM's approach excels in cases where many table accesses are required despite its apparent memory-related shortcomings. In order to use DDR SDRAM and take advantage of the low cost of these memory components in 10 Gbps designs, the memory subsystem must be designed with a width of 128 bits for simplex 10 Gbps (OC-192) network processors and a width of 256 bits for full-duplex OC-192 network-pro- cessing systems. This means that the pin count required on the network-processing chips (especially if they are custom designed using cores, as shown in Chapter 10, "Alternative Approaches to Network Processing: Net ASICs and Designing with IP Cores") must be SO high that the cost savings from mov- ing to a commodity memory technology are completely wiped out by the spectacular increase in NPU packaging costs. In other words, we must always keep things in perspective. The alternative is RambusTM-conceived RDRAM. This technology provides a lot of work per pin due to its significantly higher bandwidth. However, it requires its own signaling and coding and is expensive (four to five times more than SDRAM). RDRAM was designed for a cache line of prod- ucts. Therefore, when it comes down to network processing, it unfortunately suffers from poor ran- dom cycle times, even when accessing the same bank of memory. As the future of Rambus technology remains largely uncertain (since many companies are unhappy about the level of licensing rates), this randomness of bank access creates a real concern for network- processing designers. Some original equipment manufacturers (OEMs) are using it in their 5Gbps solutions (such as Vitesse with IQ2000 and 2200), but others have not been as convinced. Intel has also seemingly adopted it in their 10Gbps platform, although they have not yet adopted it in their 2.5Gbps solutions. This can be seen as a serious systems engineering shortco