ntegrated circuit in InP containing two couplers and two SOAs optimized to work as fast gates. The signal is distributed among the SOAs and is here coupled with a pump depressing the gain in correspondence to the bit to cancel. At the output, the signal is cleaned by a filter. As far as the all-optical switch is concerned, what is needed is a 1 X 2 switch whose configuration is fixed by an optical control signal. This component also can be realized with a MZI having SOAs on the two branches, as presented in Figure 10.53. The system is Next Generation Networking: Enabling Technologies, Architectures, and Performances InP monolithic chip Output 1 Control signal Output 0 FIGURE 10.53 SOA based 1 X 2 fast all-optical switch cell. completely identical to a WC; this is the reason why, at the output, it is possible to select the data on the desired port simply by correctly commanding the SOAs through the optical control signal without any need of tuning the output filters. Thus, we have described how all the elements of a switch fabric with a complete optical control can be realized using SOAs. It is at this point interesting to understand the number of SOAs and some basic perfor- mances of the resulting all-optical packet switch. Let us imagine having four input DWDM systems bringing 45 channels with an optical bandwidth of 40 GHz (unilateral as always) and a data bit rate of 100 Gbit/s achieved using a suitable multilevel modulation format. Let us also imagine that slotted packet transmission is adopted, SO that only a random jitter thwarts the synchronism of different signals. Naturally, this condition can be real- ized only if a suitable synchronization network is superimposed on the data network as happens in SDH, for example. For the moment, we will neglect jitter, even if it can become a real problem at high trans- mission rates. In order to apply the architecture we have described, we will assume that our switch is realized by an input queued Banyan network and conflicts are simply managed by dis- carding confli