rammable Gate Array FPGA chips are the most powerful and versatile programmable logic devices. They com- bine the idea of programmability and the architecture of uncommitted gate array which is one of the ways to develop ASICs [59]. The main elements of an FPGA chip are a matrix of programmable logic blocks (these blocks are named differently, depending upon a vendor) and a programmable routing matrix. The interconnections consist of electrically programmable switches which is why FPGA differs from Custom ICs (see Section 5.7.2), as these are programmed using integrated circuit fabrication technology to form metal interconnections between logic blocks (see Section 5.7.2). An abstract FPGA block scheme is shown in Figure 5.45, where these fundamental building blocks are shown in a common FPGA architecture, in which the logic blocks are arranged as a square matrix. However, different vendors use different internal architec- tures, functional to their particular logic block and routing technology and to the perfor- mances [60]. FPGA configuration memory is usually based on volatile SRAM (static random access memory), SO these FPGAs must be connected to a dedicated Flash chip if stable memory has to be implemented. However, there are also both SRAM-based FPGAs with integrated flash module and pure Flash-based FPGAs that don't use SRAM at all. 5.7.3.1 Programmable Connection Network In order to build the programmable connection network, present-day FPGAs adopt essen- tially two different technologies: SRAM-controlled switches and antifuse. An example of the use of an SRAM-controlled switch is shown in Figure 5.46 where the connection between two logic blocks through two switches constituted by one pass transis- tor and then a multiplexer is depicted. The whole subsystem is controlled by SRAM cells [61]. Logic block Input/output dev. Connections Programmable switches FIGURE 5.45 Functional block scheme of an FPGA. Telecommunication Networks Logic block Logic block FIGURE 5.46 Example of interconnection between two logi