time step. When an input packet reaches the correct output port, it joins the end of the local output queue, and a new input coming from this same card/port takes the slot, which was just vacated by the exiting packet on the inner ring of the hub. The helix switch is very fast because it uses very short interconnects between all I/O ports and because an open slot (such as the slot vacated by the packet of our example) is immediately used again to move the packets. A COUPLE OF COMMERCIAL EXAMPLES We will now turn our attention to some world-class switch fabric platforms from a couple of solid vendors to show the concrete form that the concepts we discussed take in a commercial product setting. IBM PowerPRS Switch Fabrics So why do we include a section on IBM's switch fabrics? The truth is that each one of the major ven- dors on whose architectures we elaborate has taken a different approach to tackle the overall systems issue. In the NPU design trade-offs, IBM's architecture has a very unusual approach as compared to vendors who propose their own traffic manager chip. Likewise, in the case of switch fabrics, IBM has its own separate philosophy based on the use of a powerful, shared memory switch fabric architec- ture. As IBM's offerings deeply influence some choices for an NPU user, the IBM switch fabric realm definitely requires some coverage at this point. At the end of 2001, IBM started delivering its fourth-generation switch fabric chips called PRS- Q64G (PRS stands for packet routing switch). The original form of the technology called PowerPRS was used for internal work at IBM in the early 1990s. The second-generation switch fabric chip tech- nology materialized into a commercial product that was dubbed the PRS-28.4 chipset. This continues to be a very important revenue generator for IBM today as it supports up to 16 OC-48 ports. The third- generation chipset was named PowerPRS-64G. It scaled the connectivity and performance to 32 OC-48 ports. The PRS-Q64G switch fabric provides support for 32 OC-192 or 128 O