~ = 161 dB + 10log10(245 X 106-10 X 106) = -77 dBc 0dB FS PAPR: 12dB SNR margin: 9dB Gain and Offset Margin: 4dB SNR Required: 30dB FIGURE 3-22 DAC dynamic range analysis. 136 Open Radio Access Network (O-RAN) Systems Architecture and Design 100Hz 10KHz 100KHz 10MHz FIGURE 3-23 Phase noise plot for typical Voltae Controlled Crystal Oscillator (VCXO) (example: Microchip/Vectron MX-805). 160 dB + 10 log10(10 X 106-1 x 106) = -90 dBc 140 dB + 10 = -100 dBc Assuming the broadband noise (A7) is dominating the performance, we calculate the Phase Jitter in radians [root mean square (RMS)] as: (A = dBc) ~2 X 10 4 for our example, which translates to an RMS jitter time value in seconds using: or (f = 245 X 106) ~ 130fs. Note that when multiple clock components (say, oscillator and a clock generator/PLL) are combined, we can calculate combined Tjitter as: Online tools such as can help in deriving the clock jitter from the phase noise plots. Chapter 3 Hardware system dimensioning References 1. World Broadband Statistics, http://point-topic.com/wp-content/uploads/2013/02/Point-Topic-Global- Broadband-Statistics-Q1-2013.pdf,2 2013. 2. Wikipedia, M/D/1 queue, https://en.wikipedia.org/wiki/M/D/l_queue. 3. Verizon, Verizon IP Latency Statistics, http://www.verizonbusiness.com/about/network/latency/. 4. Mahmoud, H.; Arslan, H. Error vector magnitude to SNR conversion for nondata-aided receivers. IEEE Transactions on Wireless Communications 2009, 8 (5), 2694-2704 May. 5. Silicon Labs, Phase Noise to Jitter Calculator, https://www.silabs.com/jittercalculator/phase-noise-jitter- calculator.aspx. Further reading FCC Form 477. Federal Communications Commission. https://www.fcc.gov/economics-analytics/industry- analysis-division/form-477-resources. Silicon Labs AN739, Estimating Clock Tree Jitter, November 2012. This page intentionally left blank Hardware architecture choices This chapter covers the different hardware architectural choices for implementing O-RAN systems, from the very high-end (data center scale-out) to the low-end (In