essing cycle budget analysis", 310 158-159 Processor binding, 196 data converter and PLL, 133-136 Profiling, 206-208 digital beamforming and fast Fourier transform, Program Counter (PC), 184 77-78 Proportional fair (PF), 250 digital predistortion, 131-132 Protocol, 277, 333 digital up conversion, channelization, and digital down conversion, 78 digital-to-analog conversion and analog-to- QoS Class Identifier (QCI), 55 digital conversion, 159-162 QoS Flow Identifier (QFI), 52-53, 215 digital < > analog conversion and analog Quadrature amplitude modulation (QAM), 74, components, 83 159, 241, 315, 335 eCPRI termination, 157-158 Quadrature Phase Shift Keying (QPSK), 241, 335 generalized block diagram, 76-77 Quality of Service (QoS), 44, 242 IBW, 128 flows in 5GC and NG-RAN, 52f key components in integrated radio unit, 157f and related concepts, 52-55 latency and delay, 130-131 scheduler, 245-246 low physical layer and digital front end, 158 376 Index Radio Unit (RU) (Continued) Roadside unit (RSU), 358-360, 359f disaggregated approach, 159f system architecture, 359-360 software defined approach, 158f Robust Header Compression (RoHC), 49, mmWave radio frequency module, 168-171 219-220, 219f OBW, 128 ROHC vl, 219 peak-to-average power ratio reduction and Roll your own (RYO), 186 performance improvement techniques, Round Trip Time (RTT), 100 78-83 Round-Robin algorithm (RR algorithm), 245 PRACH, 85-86 Rx DC offset, 336 radio frequency subsystem, 162-165 Rx/Tx antennas, reduced number of, 361 receiver chain analysis, 128-129 Rx/Tx IQ mismatch, 336 sub 6 GHz front end module, 165-167 time and frequency synchronization, 84 Ramdisk, 184 "Safe For Network" testing, 338 RAN Intelligent Controller (RIC), 2 Scalability aspect, 139-141 Random Access Channel (RACH), 23, 71 Scalable Vector Extension (SVE), 176 Random Early Discard (RED), 98, 100 Scale-out scenarios, 140 Random-access procedure, 89-91 SCHED-FIFO (Scheduler policy), 196 Random-access response (RAR), 90 SCHED-OTHER (Scheduler policy), 196 Read Only Memory (ROM), 184 S