quired functionalities: for that, we must use observers, as we will do in Sections 7.4.9 to 7.4.11. 7.4.3.2 Replay the exception scenario The Simulator has generated one scenario file: v76.x1.scn. A. In the Simulator, select File > Scenario > Load, and open v76.x1.scn. B. In the Simulator, press on Start MSC. C. Press the button Redo: All. The Simulator replays the scenario, reaches the exception, and displays: Unexpected signal l_datareq in dlca!dlc (1), line 907 of v76.pr 18 transitions executed end of scenario execution The Editor displays the MSC trace of the exception scenario, depicted in Figure 7.49. D. Enter the command print state; the Simulator answers: > print state btoa (1) ! state = ready atob (1) ! state = ready dlcb!dlc (1) ! state = connected dlca!dlc (1) ! state = waituadisc Exhaustive Simulation 229 bug_exh3 inst_1_dlca.dispatch inst_1_atob inst_1_dlcb.dispatch PROCESS/ PROCESS/ PROCESS/ v76test/dlca/ v76test/ v76test/dlcb/ dispatch(1) inst_1_dlca.dlc datalink/atobf16t_1_btoa dispatch(1) _estabreq(1) PROCESS/ PROCESS/ v76test/ v76test/ dlca/dlc(1) datalink/btoa(1) v76frame( sabme (. .1.) ) v76frame( sabme : (.1.) ) I_estabind(1 t320(12.0) inst_1_dlcb.dlc I_estabresp PROCESS/ v76test/ dlcb/dlc(1) v76frame( ua (. ) ) v76frame( ua : (.1.) ) v76frame( ua: (. 1 ) |_releasereq( 1) I_releasereq( 1 |_datareq( 1,39 I_datareq (1,39) _estabconf(1) v76frame( disc : (. 1.) ) Figure 7.49 MSC trace of the exception scenario (bug_exh3) dlcb!dispatch ! state = ready dlca!dispatch ! state = ready We see that process DLC in block DLCa is in state waitUAdisc. If we look at the SDL model, under this state no input or save of signal L_DataReq are specified. Thus, this signal has been discarded. The discarded L_DataReq signal is shown in Figure 7.49. 7.4.3.3 Correct the exception After examining the error, we decide that as the connection is being released, it is better to lose L_DataReq than to save it. Therefore, you will add a dummy input of signal L_DataReq in state waitUAdisc of process DLC. A. Exit from the Simu