pplication. As a rule of thumb, an IPC of below 0.7 is an indication of limited use of capabilities of the processor and room for optimization efforts that improve cache utilization. The counters are typically associated with the core vendors (e.g., Arm, Intel, or AMD x86) and not with the SoC manufacturer. Bus utilization Most SoCs have a vendor specific infrastructure to measure bus utilization. Alternatively, a static (paper) analysis can provide insight into bus utilization limits. Hitting internal bus limitations present a "hard stop" on system performance optimization that dictates a move to a new dataflow through the system. Double data rate (DDR) memory utilization Most SoCs have a vendor specific infrastructure to measure bus utilization. As we explained before, a DDR utilization above 50% implies increased memory latency and associated suboptimum performance. Such metrics are taken from SoC HW counters on a running system. These counters are implemented in each IP block in the device, with the specific purpose of being able to track system-level performance. They can include timestamping and "packets or operations/sec- ond" type metrics. SoC-level performance counters are mainly useful to verify that system-level parameters have enough headroom (e.g., bus/DDR loading). They also help identify SW architectural issues such as low cache hit rates due to code/data locality, etc. 320 Open Radio Access Network (O-RAN) Systems Architecture and Design Life-of-a-packet double data rate utilization analysis DDR utilization is difficult to estimate up-front and is often forgotten in a performance analy- sis scenario. As we indicate earlier, DDR bound systems show up as performance bound implementations where "the system simply cannot do better, whatever we throw at it." To help with DDR bandwidth dimensioning before using SoC or other counters for field mea- surements, consider using a life-of-a-packet analysis to trace the use of DDR memory band- width as the packet goes through the system. Say, the example of an