next synchronization level. ITU-T G.811 specifies the performance requirements for these reference clocks. Each of these SSU/BITS clocks supplies timing to a subnetwork in the second synchronization level. The role of the SSU/BITS for the subnetwork is like the role of the PRC/PRS for the whole network. If the SSU/BITS clocks lose reference signals coming from the PRC/PRS, the SSU/BITS takes over as the reference source for the subnetwork. Hence this role requires high- quality clocks with good holdover performance (their characteristics are specified in ITU-T G.812). The EECs/SECs or NEs become the leaf level of the synchronization network chain, receiving clocking information from SSU/BITS. Note that the SECs can be further chained together in a network to pass timing information from one node to another, achieving network-wide fre- quency synchronization. ITU-T G.813 (and G.8261) specifies the performance requirements for these clocks. Just as networks are planned and designed to optimize various networking data protocols, the net- works also need to be designed (and engineered) specifically for synchronization purposes. And like the deployment of data networks, the engineering of the synchronization aspects of a network should be done prior to the equipment being commissioned. The result of this engineering process is often described in a synchronization plan or timing plan. The timing plan should specify a synchronization network design that reliably distributes timing us- ing a combination of clock types and failover mechanisms. And the plan should contain the physical and logical topology of the equipment, carefully considering the different quality levels of the clock equipment connected to each other. There are several very important principles that this plan should include: The synchronization network forms a pyramid hierarchy with the master clock at the top of the tree and supplying timing information to other nodes using a master-slave methodology. Note that this hierarchy is a logical topology, whic