 above the NPe405, IBM introduced the NP2G in 2002. This network processor is based on the same powerful architecture, but has fewer resources than the NP4GS3. More specifically, it offers 12 picoprocessors. Interested readers can find more information once again from the IBM Microelectronics web site. The NP4GS3 is one of the most powerful NPUs currently in the market. It contains 16 so-called picoprocessors that handle packet manipulation operation. It also contains a powerful PowerPC 405 central processing unit (CPU) core that handles control functions. Each picoprocessor is a full-fledged 32-bit reduced instruction set computer (RISC) CPU running at 133 MHz with a 1-cycle arithmetic logic unit (ALU) and with arithmetic, logical, compare, shift/rotate, and bit test/set/clear instructions. It also contains a scalar read-only register bank that provides interrupt vector management, a time- stamp, pseudorandom number generation (PRNG), processor status, and work queue status, namely whether the information at hand refers to an ingress or egress queue. Each picoprocessor supports 2 threads in hardware (for a total of 32 threads per NPU) and includes 9 hardwired function units for common tasks such as copying string, checking bandwidth policy, and generating and verifying checksums. Besides a switching engine, each NP4GS3 also contains tree-search engines (TSEs), one of which is shared with each pair of coprocessors. A TSE is based on 3 different algorithms. There are also frame processors, Ethernet Media Access Control (MAC) controllers, four 1 Gbps media access ports Guided frames NP4GS3 Ethernet or POS data frames Guided frames NP4GS3 NP4GS3 Ethernet or POS data frames FIGURE 4.1 Scalability of configuration with IBM's NP4GS3 network processors. (Source: IBM.) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. IBM POWERNP TM IBN POWERNPTM (giv