on, standard 10 Gbps and QoS-enabled interfaces. The max- imum allowed payload on the ViX bus is 64 bytes plus a 16-byte header that is full of special bit fields used for specifying the destination port, parity, priority, credit, flow control, and SO on. The 5700 traf- fic manager chipset and the 5800 switch fabric communicate via serialization and deserialization (serdes) devices over the ViX bus by sending special ViX-bus-formatted cells over multiple 16-bit sub-buses. These sub-buses operate at 125 MHz. An aggregation of eight sub-buses can handle an OC-192 link, leaving plenty of overspeed for other system functionality. Internally, the nPX5800 is based on a shared-memory architecture with a centralized scheduler. The chip is built with 16 input ports and 16 output ports, which are interconnected through 256 inter- nal queues. Incoming traffic cells destined for one of the output ports are stored in the appropriate log- ical output queue. They will be authorized to exit by the centralized scheduling logic based on the highest priority among cells with the same output destination. When a conflict arises for access to the same output port by cells that are rated at the same priority level, the scheduler simply cycles through the same priority queues. Multicast cells are assigned to one of four traffic classes. They are queued at the input port before they can be sent to the output for which they have been earmarked. Multiple multicast requests are scheduled based on an RR fashion and multicast cells receive priority over uni- cast cells of the same priority level. In order to operate with performance in systems that require a higher throughput than 20 Gbps, multiple nPX5800 chips must be connected in a master-slave configuration. In this configuration, an incoming cell gets sliced into several pieces (slices), which are then switched in a distributed fashion by the group of interconnected nPX5800 chips. This is done according to the master chip's schedul- ing decision instructions. It takes place over multiple