more comprehensive discussion of destructive SEE, the reader is directed to the recent NSREC Short Course segment by Johnson and Galloway [172]. Single-Ever Latchup It is well-documented that in semiconductors with a p/n/p/n structure, a high-current destructive failure mode known as latchup can occur [173]. Unfortunately, just such a structure occurs in all CMOS technologies when an n-channel transistor is located next to a p-channel transistor, such as in a CMOS inverter used in an SRAM. The p/n/p/n structure can be thought of as a connection of two parasitic bipolar junction transistors (BJTs), as illustrated in Figure 4.1 [174]. For the CMOS structure shown in this figure, a parasitic lateral npn transistor is formed by the n-channel source (emitter), p-substrate (base), and n-well (collector). Similarly, a parasitic vertical pnp transistor is formed by the p-channel source (emitter), n-well (base), and p-substrate (collector). Note that the collector of each parasitic BJT is the base region of its counterpart. This leads to a positive feedback loop between the two transistors, although in normal operation both transistors are in an "off" condition. Depending on interdevice spacing, junction depths, doping densities, etc., the parasitic BJTs can be turned "on" and the positive feedback loop can be activated by a device overvoltage, improper sequencing of power supplies, or the presence of a large substrate or n-well current [173]. Once triggered, the device goes into a sustained high- current mode that can destroy the device due to thermal runaway or failure of metallization [174]. Substrate Contact Contact n-well p-substrate Figure 4.1. Illustration of the parasitic latchup structure inherent to bulk CMOS technologies [174]. II-34 Usually it is necessary to reduce or remove power from a device in a latched state to return it to normal operation before destructive failure. 4.1.1 Single-Event Latchup Mechanism The astute reader will note that one of the triggering mechanisms for latchup listed above was well o