ound. As there is no free lunch in technology, from a hardware design standpoint, two extreme choices are available. One choice is to have a small efficient DES module that implements the com- putations of one round and keeps the internal state in buffers, SO the triple DES data flow actually implies 48 passes through this same module (a solution that is inexpensive and slow). The other choice is to have a huge pipeline of 48 replicas of a DES encryption round module that allows wire-speed performance, but with a huge expense in silicon and power consumption. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SECURITY COPROCESSORS 378 NETWORK PROCESSORS Plaintext Encryption Decryption Encryption Ciphertext Plaintext Encryption Decryption Encryption Ciphertext FIGURE 17.5 Triple DES encryption using the EDE configuration: (a) using more often two keys and (b) rarely three keys As fears about DES security grew over the last few years, the U.S. government moved through a public bid and scrutiny process to establish the new Advanced Encryption Standard (AES), which ended up being the Belgian algorithm Rijndael. Several good descriptions of the Rijndael algorithm can be found in the references at the end of the chapter. A good source to start with is located at J. Savard's web site athttp://fn2.freenet.edmonton.ab.ca/~jsavard/crypto/comp04.htm.The NIST web site (www.itl.nist.gov/fipspubs/index.htm) has extensive high-quality documentation of the entire process that led to the scrutiny and the acceptance of the new standard. Numerous papers analyze the algorithm and discuss its implementation in software and in hardware in either field-programmable gate array (FPGA) or in application-specific integrated circuit (ASIC) form. The inventors of the algorithm, Dr. Joan Daemen and Dr. Vincent Rijmen, also have lots of interesting information on their web s