ion sequence: VC11 Payload left to right back to front VC12 Payload top to bottom VC2 Payload VC3 Payload 21 x TUG2s Figure 42.15 Partially filled VC4 with TU structured payload 42/14 The Synchronous Digital Hierarchy (SDH) STM-1 STM-1 SITE B SITE C SITE C STM-4 SECTION CROSS STM-1 CONNECT SECTION STM-1 SECTION STM-1 VC4 PATH SECTION VC4 PATH SITE A SITE D STM-1 STM-1 VC4 PTP VC4 PTP VC12 PATH Figure 42.16 VC12 path between sites A and D, showing the VC4 and STM sections involved nels, Engineer Orderwire channels, data channels reserved for the immediately introduces the possibility of a slight asynchronism PTO and synchronisation signalling channels. Even when these between STM and VC4, and, as with the VC12, this problem is also have been accommodated, there is substantial unallocated capacity solved by a slip mechanism plus pointer. The pointer bytes occupy which is being kept in reserve, to service future network control defined positions within the SOH and indicate the offset, in bytes, requirements that have not yet been identified. between themselves and the first byte of the VC4 POH. The main difference between this and the VC12 pointer is that when a VC4 42.4.5 Further use of Pointers slips its phase relative to the STM SOH, it does SO by three bytes at a time, rather than the single byte phase change experienced by the The use of STMs and their associated SOHs entails a few additional VC12. complications beyond those discussed above. An STM may well be A second difference between this case, and that of a VC12, is that generated by a network element which did not have the privilege of the combination of a VC4 plus its pointer is known as an Adminis- also generating the particular VC4 that it is attempting to load. This trative Unit 4 (AU4), rather than a TU4, when the pointer is located STM-4 MSOH Created and destroyed at these two points STM-1 STM-1 REGEN REGEN STM-4 STM-4 STM-4 STM-4 RSOH Created and destroyed at each of these pairs of points Figure 42.17 Line transmission system showing the multiplexe