dress Output queue manager Release address scheduler FIGURE 14.12 (a) The block structure of IBM PRS Q64G fabric switch and (b) the internal architecture of each 16X6 switch element. (Source: IBM) In order to ensure that the shared memory never overflows and that the core of the switch fabric is lossless, rigorous flow control has been implemented. The fabric core itself does not handle flow control, which is instead implemented with the help of the IBM C192 Common Switch Interface (CSI) chip. This companion chip handles a pair of I/O ports known as the CSI. The C192 CSI chip is instru- mental in avoiding HOL blocking at any of the input ports. We discussed the HOL-blocking problem elsewhere in this chapter. The situation can be summa- rized as follows. In order to prevent an overloaded output queue from overflowing when the shared memory is already quite full, the switch fabric core decides that all input ports must be notified that no packet (destined for that specific output queue) be allowed into the core memory anymore until new instructions to the opposite effect are issued. The input card normally buffers incoming packets. The first packet in this input queue that happens to be destined for that clogged output queue is now blocked at the input and cannot enter the core memory. However, behind it on the same input port, other inoffensive packets may be present that are destined for other potentially idle output queues. Due to the HOL-blocking effect, these packets are not allowed into the switch and are thus unduly penalized. The following section discusses how IBM has addressed the problem with the C192 in the context of the PowerPRS architecture. The CSI implements an input-queuing scheme based on VOQ. All incoming packets are sorted per destination port at each input port (that is, at each CSI ingress point). This means that if an output line card is experiencing excessive traffic load and potential congestion, input traffic destined for another Downloaded from Digital Engineering Library @ McGraw-Hill (