ed to temperature changes. Figure 5-22 provides a very rough comparison of holdover performance of clocks with different classes of oscil- lator. Note that Figure 5-22 is a graphical representation to show the magnitude of deviation with respect to time; either positive or negative deviations are possible for different oscillators. Deviation Reference removed Figure 5-22 Relative Holdover Performance for Different Classes of Oscillator Hardware designers are constantly innovating to improve holdover performance. One such innova- tion is to observe and record the variations in the local oscillator while the reference signal is avail- able, sometimes also referred to as history. When the reference signal is lost, this historical inform- ation is used to improve the preservation of the accuracy of the output signal. When using such techniques, the quality of this holdover data plays an important role in the holdover performance. There are cases where multiple paths of synchronization are available, and not all are lost simultan- eously. For the hybrid synchronization case, where frequency synchronization is achieved via phys- ical network (SyncE) and phase synchronization is achieved via PTP packets, it may be that only one of the synchronization transport paths breaks (such as, only the PTP packet path or just the fre- quency synchronization path). For such cases, one of the synchronization modes could move into holdover. For example, it could be that the PTP path to the master is lost (for example, due to logical path fail- ure to the PTP master) but frequency synchronization (SyncE) is still available. In this case, the fre- quency stays locked to the reference and just the phase/time moves into holdover. Why is holdover performance important, and how long should good holdover performance be required? As an example, let us examine the case of a 4G LTE-Advanced cell site, which may have a phase alignment requirement to be always within +1.5 us of its master. This cell site is equipped with a GPS receiver and exter