the idea of designing customized network-processing chips using IP cores obtained by multiple third-party sources. We discussed the cutting-edge performance offered by a leading supplier of network-processing-optimized IP technology as well as other mainstream config- urable IP CPU cores-namely, those that are based on either RISC or VLIW approaches. Many of these approaches offer flexibility, but they may also decrease wire-speed performance. In other words, this flexibility comes at a serious price. In addition to having to design the entire network-processing ASIC by themselves, which implies that an organization has the necessary design skills and money for in-house work based on this approach, IP-based network-processing design seems a viable approach for fast packet-processing ASICs if the design is based on the scalable and powerful ClearSpeed IP approach or on VLIW processors that are easily configurable. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES NETWORK PROCESSORS If however, the configurable RISC or VLIW approach proposed by Tensilica and others who have tried to emulate its model is used, then this technology should be considered in lower-speed applica- tions when dealing with the data forwarding plane, or as is more often the case control plane compu- tational tasks or tasks where the daunting challenge of integrating multiple processors inside the same piece of silicon can be handled from the affordable silicon-die real estate and an architecture and sys- tems engineering standpoint. However, the latter case has a different result when dealing with programming and coordinating multiple embedded processors, scheduling and arbitrating their access to internal, scarce, and some- times conflicting resources, while working under a real-time oper