ables, etc. FIGURE 8.2 A typical line-card architecture based on Motorola's C-5e network processor and Q-5 TMC in a high- function edge router. The backplane is implied on the right side of the drawing running vertically across all the cards. (Source: Motorola) Due to the flexibility of the Q-5 TMC interfaces, the company targets it to different markets of net- work equipment, such as Internet access routers, optical edge multiservice platforms, virtual private network (VPN) access devices, packet/ATM internetworking devices, IP/ATM access/aggregation devices, and even devices for wireless network infrastructure, base stations, and SO on. The Q-5 TMC offers the following interface possibilities with a network processor (or special application-specific integrated circuit [ASIC]), a host processor, or memory: A PCI host interface that is 32 bits wide, is clocked at 66 MHz, and can be used for system config- uration and statistics gathering. An external traffic management interface (TMI) that is 58 bits wide and works at 100 MHz between the Q-5 TMC and a network processor or ASIC. The TMI is used to pass descriptors and control information. The definition and role of the descriptors are described later in this section with a real- life example of a high-performance edge router. For the moment, think of this as simply a data struc- ture associated with the internal description of traffic payloads. In the Motorola C-5e network processor, the TMI replaces the QMU's external SRAM. A double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface for descriptor storage. This interface is 72 bits wide, is clocked at 133 MHz, and can address a maxi- mum of 64MB of storage. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. MOTOROLA'S C-PORT™ FAMILY OF NETWORK PROCESSORS MOTOROLA'S C-PORTTM FAMILY OF NETWORK PROCESSORS Q-5 TMC Buffer PCI