band signal proces- sing on a single chip. However, each of these architectures has some structural issues that must be resolved. In the zero-IF receiver, the desired signal is degraded by time variant DC offset caused by local oscillator leakage and self-mixing. In the low-IF receiver, nonideal hardware results in amplitude and phase mismatches between the I and Q signal paths, which results in degradation of the desired signal with leakage from the interference signal. In the generic low-IF receiver architecture, the incoming RF signal in the antenna is filtered by the band selection filter and amplified by a low-noise amplifier. The quadrature demodu- lator down-converts the RF signal to the complex low-IF signal, which is represented by in- phase and quadrature components. The IF signals pass through low-pass filters and then sampled by the analog to digital converters (ADCs). After the ADC sampling and conver- sion, the digitized IF signal is down-converted to the baseband, yielding digital complex signals. Using a moderately low-IF frequency, this architecture can avoid DC offset and 1/f noise issues that frequently arise from zero-IF receivers. However, it also reintroduces image issues. Image cancellation can be achieved after the low-noise amplifier, but requires narrowband filtering, thus significantly increasing the complexity and cost of the device. The latter issue can be addressed by complex mixing and subsequently and filtering techni- ques in the low-IF receiver. 784 Chapter 6 In order to meet the stringent link budget requirements of NB-IoT, low-cost low-complexity single-chip devices have been developed by various vendors [20]. The integration of the power amplifier (PA) and antenna switch simplifies routing by reducing the number of RF components in the frontend. The PA design with a low PAPR is possible with the use of the single-tone transmission technique. This enables the implementation of an RF chip that includes an efficient on-chip PA that may be operated near its saturation point for ma