ent is substituted by the content of the cell placed before, but for the first cell that is enabled to receive packets from the input lines. The scheme of the queue realized with optical elements is reported in Figure 10.40. In order to forecast possible performances of such a memory, we have to decide the technology that is used to implement them. We will consider both silicon-based 2D MEMs and InP-based SOAs, targeting optical technologies that are compatible with monolithic integration and, thus, volume production. To evaluate the power consumption of such a queue, it is necessary to start from the elementary cell. Let us take 2D MEMs technology, SO that it can be assumed that a single cross-point has a power consumption of 5 mW (see Table 5.8) and the overall power con- sumption of the cell is 60 mW. However, it must be taken into account that 2D MEMs are "slow" switches that are not always suitable for such applications. Very fast switches can be built using SOAs [52], with a much higher power consumption on the order of 4W for a 2 X 2 switch, SO that all the memory blocks will consume 12W. It clearly appears that there is somehow a trade-off between power consumption and speed that is common to all these kinds of applications. It is interesting to compare such figures with the power consumption of a possible very- high-speed electronics queue. If we assume that we have a queue of four elements, and that the line rate is NRZ 100 Gbit/s, it can be built with a RAM placed after a deserial- izer that reduces the 100 Gbit/s incoming flux in 40 fluxes at 2.5 Gbit/s. A very-high-speed RAM with a memory of 256 Mbyte working at 2.5 Gbit/s can consume less than 500 mW [53]. The deserializer cannot be built all in CMOS, due to the very high input bit rate. The common architecture of these devices is constituted by an SiGe front end and a CMOS core. In total, a deserializer, like the one needed here, will consume up to 1.05W in total assuming it is composed of one deserializer from 100 to 4 X 25 Gbit/s [54] and four de