ll (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES NETWORK PROCESSORS RSF switch fabric interface RSF Connector "Back-side Ports Pointer Packet Buffers Instruction Dictionary Registers, Scratch Memory Memory Cache Source Source Source Source Route Route Route Route Execution Execution Execution Execution FIGURE 9.4 The architecture of each RCU inside the Cognigine network processor. (Source: Cognigine) cycle. While other typical network processors will have a hard time even approaching that level of raw-speed performance, the Cognigine network processor provides a single-chip solution. It consol- idates all classification for layers 2 through 7 as well as traffic management functions within one chip and can handle wire-speed fast-path packet processing at 10 Gbps. It has an internal overspeed of 40x, finally yielding a useful packet-processing performance of about 25 Mpps. The implementation of a full-duplex 10 Gbps data path requires only two Cognigine processors. As each RCU is four-way multithreaded, it should not be surprising that each RCU has four 64- bit reconfigurable data paths and four 20-bit address paths. In addition to the fact that the hardware of each RCU provides support for operations such as timestamping and CRC, it also has the conven- ience of a 4K packet buffer and 2K of scratchpad memory inside each RCU. The RSF handles all com- munications from RCU to RCU or from RCU to peripheral units. Two programmable Optical Internetworking Forum (OIF) SPI-4.2 network interfaces provide external connectivity toward lines and/or external switch fabric serialization and deserialization (serdes), whereas the interface with a supervisory host CPU is handled over an industry standard PCI 2.2 bus. The heart of each RCU contains an interesting concept called a dictionary, which decodes a VISC instruction (as soon as it is pulled out of an instruction cache) and decides wh