varying pattern density. Conformance to the code rules is 622.08Mbit/s (STS-12, STM-3) < 4.6ppm usually checked automatically with a digital transmission tester. It is also useful to inject code errors on a test pattern to check that the equipment under test recognises this condition. 61.2.2.5 Framing 61.2.2.4 Clock frequency As with interface codes, conformance to the specified frame format The clock frequency at a hierarchical interface must lie within the is usually checked automatically by a framed digital transmission specified tolerances shown in Table 61.3, otherwise justification tester. Likewise, injecting frame errors in a test pattern checks that and clock recovery will not operate correctly in terminal equipment. equipment under test recognises the condition. 1U.I. Ideal transmitted signal Jittered signal viewed at instants Tn over a period of time Jitter function Figure 61.4 Displacement of timing instance of a digital signal due to jitter modulation 61/6 Telecommunication system measurements Both code errors and frame errors can be used as a simple means jitter present at the input is amplified or attenuated by the equipment of in service error monitoring. Testing may also include a check on (Figure 61.6). The input jitter tolerance is checked by increasing the the accuracy of these indications. level of jitter on a test pattern at a given modulation frequency and The standards specify the conditions for loss of frame synchroni- determining the level at which the equipment under test starts to sation and for regain of synchronisation. These criteria can be tested generate errors. by injecting a known sequence of frame errors in a test pattern (refer to G.704 and G.706). Input jitter Network Output 61.2.2.6 Jitter and wander tolerance equipment jitter Timing jitter is defined as the short term variations of the significant instants of a digital signal from their ideal positions in time. The significant instant might be the rising or falling edge of a pulse. The effect of jitter is shown in Figures 61