nput sources, e.g. with the VCO noise source in Fig. 4.11, is accomplished in a similar manner. Using the relations (4.6)-(4.7), the input-output HTM for the PLL feedback topology in Fig. 4.2 is found to equal s)((s))( (4.45) Here, we used the expression (4.26) to describe the PFD behavior. Furthermore, (4.46) is the PLL's open-loop gain HTM. The input-output relation (4.45) is valid for all types of PLLs, at least as far as their small-signal behavior is concerned. Note that this equation is the HTM generalization of the CT-LTI model (4.10). Evaluating and/or approximating (4.45) is achieved by means of the techniques out- lined in the previous chapter. For example, for PLLs with a mixing PFD, the power series method in section 3.4.3.2 tends to yield good results. The use of rank-reduced approximations (see section 3.4.3.3) for the open-loop gain HTM G(s), however, al- lows us to obtain results that are valid for any PFD implementation. Even more, for PLLs based on sampling PFDs, this method yields an exact closed-form expression for the PLL's closed-loop input-output HTM. In what follows, we first consider approxi- mate expressions for (4.45) based on the rank reduction of G(s). These approximations hold for all types of PLL implementations. They establish the link with traditional CT- LTI models that are commonly used for PLL analysis and design. For PLLs with a sampling PFD, section 4.2.5.3 presents an exact input-output relation. It establishes the link with the discrete-time PLL models presented in [Gard80, Hein88]. 11 It is only interesting to construct a detailed model for circuit-level verification. In this case, one can use general-purpose numerical algorithms, build on the results in section 3.4.4 of the previous chapter, to extract the exact HTM corresponding with a particular frequency divider circuit-level implementation. 4.2 PHASE-LOCKED LOOP ANALYSIS 4.2.5.1 A general rank-reduced approximation: By combining the different building block models, it is readily shown that the elements of G(s) are str