atic asymmetry is to either model or measure it, because any- thing that is known and fixed can be compensated for. The engineer can configure the PTP slave port with an estimate for the asymmetry, SO that the servo corrects by that known value when solv- ing the timing equations. Similar mechanisms apply to building a PTP clock because electronic components will introduce delays to the signals inside the device. Signals within the node sometimes take alternate paths of different lengths, which can also impact the asymmetry. But if these values are not varying, the hardware designer can calibrate the signals to deal with the delay, latency, or resulting asymmetry. For more details on building an accurate PTP clock, refer to Chapter 12. IEEE 1588-2008 has a very detailed Annex C, "Examples of residence and asymmetry corrections," that explains, with copious examples, the mechanisms for dealing with residence (transparent clock) and asymmetry corrections. Figure C.2 of 1588-2008 is a good figure to consult for the simple case of a one-step master, a one-step transparent clock, and a one-step slave port on a boundary clock. This example uses the end-to-end delay-response mechanism, which would be a common scenario for many readers. But at first glance it is a little intimidating, SO it might be somewhat difficult to understand and absorb the important lessons. For that reason, this section explains the main mech- anism using the same time values as in the C.2 example. Figure 9-20 illustrates this example with a single PTP message exchange determining the four timestamps necessary to calculate the mean path delay and offset from master. For a primer on that process, see the section "The (Simple) Mathematics" in Chapter 7. What is being added to that simple example is the compensation for asymmetry and residence time. Both mechanisms rely on the use of the correctionField (CF) to carry a "running total" of the accumulated asymmetry. Master T1 time = 144:7.3 T4 time = 144:864.85 Receive TS = 144:7 Origin TS = 144:7 = 1