r then will naturally choose the more appropriate instructions when generating code. To further clarify the overall systems engineering context, we must point out that the generated code is microcoded. Understanding why this is so, is straightforward. PEs are CPUs that are 8 bits wide, but it may be that a new custom instruction revolves around a 16- or 32-bit operation. By microcoding everything in terms of available 8-bit operations, ClearSpeed allows the implementation of essentially anything. If you want to add two 32-bit numbers, depending on the exact addition algo- rithm's use of carry, you will need four 8-bit operations. As each native 8-bit operation is executed in one clock cycle, the number of cycles required to execute a custom microcoded instruction will depend on the actual operations involved. Our 32-bit addition example will take four cycles. When an instruction is issued for execution, it is looked up in a special table that shows the steps of how to implement it in 8-bit PE operations. In this context, the lookup table is the actual microc- ode. For all practical purposes, one application may require different microcode than another. Therefore, microcode is loaded at run time from external memory (ideally at boot time) along with the actual application code to be run. In fact, the microcode space can be booted partially or com- pletely, thereby affording an extra degree of flexibility around systems engineering. We should briefly pause and compare ClearSpeed's approach of customizing the MTAP instruc- tion set to the ones taken by Tensilica's configurable XtensaTM CPU or even by ARC. The definition of a new instruction usually entails the (automatic) creation of a significant number of extra logic gates Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WIT