packets are forwarded through the split IX bus to the IXP1200 network processor for subsequent processing. Deep packet-processing applications are partitioned among the NPU's microengines. All supervisory systems control functions that will be exercised onto the NPU are dispatched by a host CPU externally through the PCI bus. A field-programmable gate array (FPGA) is required to handle the application-specific glue logic translating the IX bus cycles into VX Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. INTEL IXAT NETWORK PROCESSORS INTEL IXATM NETWORK PROCESSORS bus cycles. This is required because on the time slot interchange (TSI) side the data are coming in and going out serially in real time, whereas on the IX side the NPU prefers to handle data in burst mode. The shown IXS1000 chip is the Intel media processor responsible for translating the VX bus traf- fic to and from TSI slots for the TDM-multiplexed H.110 backplane used to interface with the teleph- ony world. The IXS1000 media processor is a good choice for many reasons. It can handle 240 voice channels split over 512 full-duplex TDM channels; mix and match call configurations with all clas- sical vocoding schemes such as G.711, G.726, and SO on; take care of G.168-compliant echo cancel- lation; adopt fax modem or fax relay behavior based on V.17, V.29, and SO on; and handle typical A-law and/or u-law pulse code modulation (PCM) interfaces. In short, it can implement all the essary signaling context of a typical PSTN network interface with functions such as Dual Tone Multiple Frequency (DTMF) detection and generation. This hardware design along with the appropriate software can manage the TSI slots. It can easily process all signaling messages for the call setup and teardown. It can also manage the combination of Real-Time Protocol (RTP)/User Datagram Protocol (UDP)/IP for the h