tor as in SOI technology to achieve maximum hardening [Plat-88, Flam-95]. CONSEQUENCES OF LEAKAGE CURRENTS FOR CMOS CIRCUITS AND PERSPECTIVES LINKED TO PROGRESS OF THE INTEGRATION These parasitic channels can be extremely numerous in complex circuits because there exist a great number of topological situations where NMOS transistors are facing in such a way that they can be connected and also are possibly N wells or well plugs. The voltage of the interconnection lines can play a great role because, in the worse-case, it can influence the parasitic structure by polarizing it positively. This line voltage can be distributed in an unpredictable or variable manner during the irradiation, because it results from the status of variable logic levels. Parasitic leakage paths can affect complex circuits above a certain level of dose consequently and become unpredictable. sees therefore the fundamental role that the parasitic leakage currents play in modern integrated technologies, while the effects related to gate oxides tend to be relatively less important. This is due to the fact that progress of the integration leads to a strong diminution of the thickness of the gate oxide, and consequently, for a given dose, threshold voltages of the main transistor decrease strongly because of the decrease in radiation-induced charge trapping with the "square" of the thickness (in first approximation, cf. supra) [SIA-98], [John-98]. On the contrary, lateral transistor leakage does not decrease with the same factor, as the lateral oxide does not scale with the same roadmap and those due to parasitic "field" transistors not more, since the thickness of the field insulator of tend to decrease only in well lesser proportions (e.g., [Shaw-95] reports 340 nm for 16 Mb DRAM of three manufacturers and 240 nm for 64 Mb DRAM). And, LOCOS is now being abandoned, even in its modified "encapsulated" more abrupt version when evolving from 0.25 um to below [John-98]. With the use of Shallow Trenches Isolation (STI), new problems arise, notably rel