 data context. Even more than that, they do not consume power while they are in that nullified state. This means for instance in the example just mentioned that the central instruction fetch/decode unit issues code pertaining to both Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES 167 FIGURE 10.2 The very large scale integration (VLSI) layout of the basic building block for the PE array within the MTAP processor. (Source: ClearSpeed) Reprinted with permission. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES 168 NETWORK PROCESSORS Classification Layer-7 Metering Framing Policing Forwarding Packet Marking Analysis Traffic Ingress datapath Conditioning Control Policy Accounting proprietary Egress datapath Traffic Handling Queue Framing Shaping Scheduling Management FIGURE 10.3 Architecture of a line card and based on ClearSpeed IP Technology. (Source: ClearSpeed) IPv4 and MPLS and broadcasts this code to all PEs. However, if a specific PE is only dealing with, say, an MPLS packet, it will consistently nullify all instructions that it is handed that pertain to IPv4. This approach seems extremely deterministic and efficient based on numerous simulations that the company has performed. For example, ClearSpeed has simulated a chip with four such MTAP processors performing simultaneous IPv4, IPv6, and MPLS protocol processing. It found that less than 30 percent of its available cycles was used for the actual packet processing. Thi