An LDPC decoder can be implemented using serial, parallel, or par- tially parallel architectures. The performance of the LDPC decoder depends on various fac- tors such as decoder algorithm and architecture, quantization of LLRs and the maximum number of decoding iterations. The maximum number of decoding iterations used for the decoding process determines the data rate and latency of the LDPC decoder. After perform- ing maximum number of decoding iterations, the codeword is then estimated. In order to save decoder power consumption and to decrease the latency, a decoder design that verifies the codeword after each iteration and stops the decoding process when the estimated code- word is correct, is needed. If parity check is satisfied then the codeword is estimated at the beginning of the next iteration and the decoding process is stopped. 532 Chapter 4 4.1.7.4 NR Low Density Parity Check Coding 3GPP NR has taken a different approach to LDPC coding for the downlink and uplink traf- fic channels. In order to ensure support of a wide range of code rates with sufficient granu- larity and HARQ-IR, two base graphs with the structures that are explained later in this section have been adopted. Code extension of a PC matrix (lower triangular extension, which includes diagonal-extension as a special case) is used to support HARQ-IR and rate- matching. The 3GPP NR LDPC base graphs consist of five submatrices A,B,C,D,E as shown in Fig. 4.50. As depicted in the figure, matrix A corresponds to the systematic bits; B is a square matrix and corresponds to the parity bits. The first or last column of matrix B has a weight equal to one. The last row of B has a non-zero value and a weight equal to one. If there is a column with weight of one then the remaining columns contain a square matrix such that the first column has weight three. The columns after the weight three col- umn have a dual diagonal structure (i.e., main diagonal and off diagonal elements). If there is no column with weight one, B consists of only a square matrix