into account fluxes, field and traps in the surrounding oxides. Such codes, necessarily in 2 or 3D for SOI, exist only since recently. For example self-consistent modeling with code B has been presented for a lateral cross-section of the SOI structure [Mila- 98], realistically computing the back-channel induced MOS as a function of dose and of the body-tied-to-source (BTS) dimensions. In the following, as another application of numerical modeling, we present a study using the code A, on a typical thin-film partially-depleted SOI technology, with gate length of 0.5 um and III-99 LDD feature. This study can be viewed as "orthogonal" to the [Mila-98], as it operates in another cross-section, orthogonal to the previous one. We aim at describing here the other cause of leakage in NMOS/SOI, i.e. the back-channel leakage current, whereas [Mila-98] described the edge-channel leakage current. In SOI, the "mechanical substrate", i.e. the bulk silicon underlying the buried oxide, is connected to the chip case, and usually tied to ground. In other terms, back-gate is usually at zero Volt with respect to the source. This is typically a case where electric field is low (determined, for instance, by built-in potential between the two silicon facing each other, e.g. P-type for the N-channel MOS and P type for the bulk silicon substrate). If drain is itself at zero voltage during irradiation, in effect, trapping is at minimum and usually no back-channel parasitic transistor appears. However, it has been recognized since the early times that the worst-case of irradiation occurs when the NMOS drain bias is at supply voltage (e.g. +5 V). In this situation, the back-MOS threshold voltage shifts significantly and the back-MOS transistor can be revealed and cause a major drain-source leakage current. The following set of figures verifies this hypothesis, by computing the electric field, the induced MOS current in the back-side of the silicon film, the trapped charge in the buried with the self- consistent code A. These set of experimen