end devices can exclude the L3 cache altogether. Note that L3 cache memory is (optionally) accessible by accelerators and/or IO interfaces-consider the use-case where the content of an (DDR) Memory System-on-Chip CPU Cluster CPU Cluster CPU Core CPU Core CPU Core CPU Core Memory L2 Cluster Shared Cache L2 Cluster Shared Cache Controller Platform Cache and Interconnect Accelerator IO Interface FIGURE 3-9 Generic (modern) system-on-chip (SoC) architecture showing cache hierarchy. Chapter 3 Hardware system dimensioning 119 Ethernet frame coming in on an IO interface is read by a CPU immediately on reception and thus the path to and from DDR is not needed. Each of the (SoC internal) interfaces has an associated bandwidth and latency, but these interfaces are assumed dimensioned for enough performance by the SoC manufacturer for most, if not all, use-cases. The typical bottleneck in the system as such becomes external (DDR) memory bandwidth. DDR interfaces are defined by their interface speed (counted in (giga) transactions/second or GTPS) and the transaction width which is typically 64 (or with Error Correcting Codes (ECC) enabled, 72) bits. Combined, these two values give a raw throughput of the external memory, calculated from the multiplication of those two values. Consider a modern multicore CPU with dual 72-DDR4 interfaces running at 2.4 GHz which gives a raw throughput of 2 X 64bit (ECC bits are not used by the application) X 2.4 GTPS = 307.2 Gbps (note, unlike peripheral component interconnect express (PCIe) and Ethernet, this bandwidth is shared across Read and Write operations). Latency to DDR memory is above 100 (if not 100 seconds) CPU clock cycles. For various well-documented reasons, this raw performance is not achieved in real-world applications that access memory in a near-random fashion. We identify two challenges: Latency to DDR memory tends to increase as the loading to the memory increases. This behavior is different from on-chip memories, latency to which tends to bounded. The theoretical throughp