ers and regenerators in the transmission system. In fact, the amplitude of the jitter is directly proportional to the number of these repeaters and regenerators. There are different ways to compensate for the impact of jitter. The most common is to use a Phase Lock Loop (PLL) for clock recovery. In its simplest form, a PLL consists of a phase comparator, a lowpass filter and a Voltage Controlled Oscillator (VCO) in a closed feedback loop. By employing a PLL when a gap occurs between the reference timing signals, the extracted clock signal can be used to stimulate the phase comparator. The performance of a PLL is evaluated based on two main metrics: phase noise and lock time. For a carrier frequency at a given power level, the phase noise of a PLL is defined as the ratio of the carrier power to the power found in a 1-Hz bandwidth at a defined frequency offset. The lock time of a PLL is also defined as the time it takes to move from one specified frequency to another specified frequency within a given frequency tolerance. After all, dejitterizers can be employed to reduce the effect of jitter in digital signals. Dejitterizers consist of an elastic buffer in which the signal is temporarily stored and then retransmitted at a rate based on the average rate of the incoming signal. Resources Carlson, B., Rutledge, J. C., and Crilly, P. B. (2001) Communication Systems: An Introduction to Signals and Noise in Electrical Communication, Fourth Edition, McGraw-Hill. Gibson, J. D. (2005) Speech Coding Methods, Standards, and Applications, IEEE Circuits Syst. Mag. 5(4):3049. Glover, I., and Grant, P. (2003) Digital Communications, Second Edition, Prentice Hall. Kondoz, A. M. (2005) Digital Speech: Coding for Low Bit Rate Communication Systems, John Wiley & Sons. Owen, F. F. E. (1982) PCM and Digital Transmission Systems, McGraw-Hill. Painter, T., and Spanias, T. A. (1997) A Review of Algorithms for Perceptual Coding of Digital Audio Signals, Proceedings 13th Int. Conf. Digital Signal Process. This page intentionally left blank