 micro- engine to improve performance, built-in resources for tasks such as Asynchronous Transfer Mode (ATM) segmentation and reassembly (SAR), pseudorandom number generation (PRNG) for table lookups, timestamps for supporting flow metering, and a multiply function for performing complex algorithm calculations such as those encountered in quality of service (QoS) environments. These lat- est network processors also automatically align code and data bytes for better code streamlining, thus enhancing the productivity of software engineering. The following are other interesting and innovative features of this architecture: Next-neighbor registers, which enable the rapid transfer of data and state information from one microengine to an adjacent one. Reflector mode pathways, which ensure that data and global event signals can be shared by multi- ple microengines using 32-bit-wide unidirectional buses (called the D and S bus) that connect the IXP2800 network processor's internal processing and memory resources. Ring buffers, which establish producer-consumer relationships between microengines, thereby pro- viding a very efficient mechanism for the flexible cascading of linked tasks among multiple soft- ware pipelines. This combination of flexible software pipelining and fast interprocess communication accounts for a large part of the suitability of the IXA architecture NPUs in core, edge, and access applications. 32 bit 33 MHZ PCI bus SDRAM Flash Intel 64 bit 32 bit 82599ER 100 MHz 100 MHz Memory-mapped I/O device interface 10/100 Mbps TPE management Intel Generic XP1200 16-bit 8x 10/100 Mbps Network Twisted-pair Ethernet Processor (TPE) LAN ports Fiber Intel 32 bit 66 MHz LXT9763HC Rx IX bus Intel Intel Intel OC-12 IXF440 IXB8055 IXF6012 Intel 32 bit 66 MHz 32 bit 8-bit TTL LXT9763HC Tx IX bus 104 MHz 77.76 MHz POS-Utopia FIGURE 5.4 A systems design based on the IXP1200 network processor for an enterprise IP router connecting fast Ethernet with SONET over OC-12. (Source: Intel) Downloaded from Digital Engineering Libr