he switch fabric since, besides caring of man- agement and configuration of the equipment, it is the central processor that updates the routing table and distributes it to the different forwarding engine that from it derives the forwarding table. Since the packet is never completely passed to the routing processor, the IP datagram elaboration made by a router with the architecture of Figure 7.55 has to charge the local line card processor of the checksum calculation at the packet input and other similar oper- ations, while the forwarding engine only verifies the header to control that it really comes from an IP packet. From this point of view, in the MGR there is a substantial step toward a really distrib- uted architecture. Possible limitations of the architecture of Figure 7.55 are the processing power and the amount of memory usage. Both these limitations can be alleviated by pushing further the distribution of the router tasks among a set of processors. These are the processors on the line card, a set of special- ized forwarding engines for packet forwarding evaluation [71,72], and a central equipment processor. The principle diagram of a completely distributed processing router is presented in Figure 7.56 [73,74]. In this scheme each network interface provides the processing power Switch fabric Memory Service LC up LC up FIGURE 7.55 Distributed router architecture based on the presence of routing caches in the distributor forwarding engines (FEs). Connection between input and output ports is realized by a single, space division, switch fabric. Telecommunication Networks Forwarding Intelligent line cards Modular switch fabric processors Service bus Switch Central main board FIGURE 7.56 Complete distributor router architecture. The line cards (LC) have the architecture of a computer, with ded- icated hardware for packet processing. Packet forwarding is calculated by a battery of parallel forwarding engines (FEs), realized with a completely dedicated hardware, each of which store a complete and updated replica 