 such, two-way OFDM radio systems are much harder to implement than receive-only systems (DAB/DVB broadcasting and DRM). As bit rates increase over time it will be necessary to implement higher-order FFTs. This will place a premium on the techniques needed to reduce the complexity/calculation overheads implicit in these schemes. We will need faster more efficient transforms. Note that these schemes all depend on either the com- pressibility of the transform itself or the compressibility of the data that in turn depends on the symmetry and essentially repetitive nature of sinusoids and their associated input number series. Note also how compression techniques become more important as FFT complexity creases. A 32-point FFT is typically ten times faster than a standard FT. A 4096-point FFT (used for example in a DVB H receiver) is typically one thousand times faster. 2.13.7 The Impact of Transforms on DSP and Microcontroller Architectures - Maths in the Microcontroller We said earlier that the efficient implementation of fast Fourier transforms (and transforms in general) imply a trade off between multiplication, division, addition, subtraction, memory space, bus width, bit width and clock cycle bandwidth. These trade offs are in turn dependent on the architecture of the host device. Devices using parallel processing (super scalar devices capable of operating multiple parallel instructions) have become increasingly useful for all sorts of tasks including the FFT, DCT and related filtering, convolution, correlation, decimation and interpolation routines. Physical Layer Connectivity Hardware optimisation includes the integration of hardware repeat loops for filtering and FFT routines and the task-specific optimisation of fixed-point, floating-point and saturation arithmetic - the maths of the microcontroller. Although FFT algorithms are a commodity item in most DSP libraries there are still plenty of future performance optimisation opportunities particularly as increasingly complex higher-order FFTs are introduced int