commonly available skill among software engineers than traditional hardware description languages, which are not SO well mastered by the software community. Improv strongly believes that it is becoming more important than ever to control the complete SOC design cycle by software, as opposed to struggling with the integration of multiple and often incompatible or unverifiable IP cores. The role that software engineers play becomes more critical to the overall flow of work. Solo, Improv's development environment compiler, reads the Java notation along with the descrip- tion of the underlying architecture and generates the application image. It then maps this image code onto the configured multiprocessor hardware. As a result, a very complex application, which was developed with a single programming engine in mind, is automatically and seamlessly partitioned onto multiple processors, each working from its own private instruction memory. The SOC designer can simulate the complete solution using a cycle-accurate simulator and identify bottlenecks or decide on the necessary modifications in order to better balance loads or tasks or to change the architecture by adding more standard or optional customized hardware resources, when necessary. The final executable can also be emulated using standard FPGA-based boards. The results are both impressive and fast. Improv has designed several multicore SOCs for and with its licensees. However, for our dis- cussion, we will only mention one case where five embedded Jazz VLIW cores with their memory obtained sustained aggregate I/O throughputs close to 8 GBps on top of heavy-duty processing of packet-processing applications. This was achieved without pushing semiconductor die fabrication to boundaries of feasibility (meaning that more Jazz cores could be easily packed onto the same die if necessary). This makes the technology a more than viable candidate in the network-processing field for cus- tom-designed SOCs based on third-party IP cores. SUMMARY In this chapter, we looked at 