ular regener- ator, jitter will still accumulate from one regenerator to another. Problems can arise at the end of a link where the data signal may have to relate to a more rigid network clock. At this point, the incoming data signal may contain timing jitter which amounts to (1.5) several clock periods. If data slips (loss or gain of bits) are to be avoided quite large data buffers may be required. The way in which jitter builds up has been extensively studied in the literature (Byrne (0.2) et al., 1963). Suffice it to say here that it is the data pattern dependent effects which cause most trouble as they tend to reinforce each other Jitter frequency Intermediate at subsequent repeaters. In long chains of regenerators it is usually preferable to prevent the build up of excessive jitter in the first place by using carefully designed phase locked loops rather than band- pass filters in the clock selection circuits. Alternatively, data scram- Figure 28.17 Typical jitter limits for a digital transmission system blers may be installed at intervals to break up the data patterns and 28/16 Digital transmission and G824, although reference to these will show that the higher Frame Frame multiplex levels in the transmission hierarchy attract somewhat Data bits Data bits tighter specifications. The figure serves to highlight the low fre- Frame alignment words quency timing jitter (or wander) which can amount to many clock intervals. Figure 28.18 Frame structure 28.4.7 Further reading 28.19 shows the principal tasks which have to be performed, with Apart from the references given in the text, useful chapters on clock the desirable state shown shaded. extraction are to be found in (Bylanski and Ingram, 1986) and also In practice, the aligner's task is made yet more challenging when in (Lee and Messerschmitt, 1988), the latter includes details of one notes that: waveform sampling methods which are applicable to fully digital realisations. For detailed analytical treatment the early work on Alignment found timing and jitter pub