g 1,536 PEs, 3MB of embedded DRAM, structures that provide 600 GBps of on-chip bandwidth, and computational power that amounts to 1.5 Teraops of integer performance and 3 Gigaflops (floating-point performance). All this was coupled with four RambusTM channels that offered a bandwidth of 6.4 GBps in communications with off-chip devices. ClearSpeed manufactured this proof-of-concept chip using a standard but now quite obsolete 0.25 m CMOS process from UMC and packaged the chip with roughly 1,000 pins. This is an impres- sive set of numbers, and it deserves the appropriate level of attention from the industry. ClearSpeed is offering an elaborate Software Development Kit (SDK) for the development of com- plete applications. The SDK, which runs on standard platforms like Linux, Solaris, and Windows 2000, is comprised of the following: An ANSI-compatible optimizing C compiler along with a few extensions that allow the program- ming of the parallel features available in the MTAP architecture. An assembler. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES 172 NETWORK PROCESSORS A linker along with a set of source- and object-code libraries, including standard functions and application programming interfaces (APIs). A debugger. A profiler. A microcode compiler. A full-fledged simulator and associated simulation tools for rapid prototyping, including models of the associated hardware IP cores. An Applications Development Kit (ADK), which contains a traffic generator, optimized libraries of key functions, reference implementations, and test code, thereby accelerating overall development time. A Hardware Development Kit (HDK), including tools that allow silicon configuration and design verification as well as operating system and drivers. Helping promote the parallel deve