pecific integrated circuit (ASIC) or other standard product device used to implement the detection and correction code logic. Conventionally, error detection and correction is performed in real time for processor accesses to memory, with the correct result forwarded to the processor, and the corrected value Check Bit Length for Information Bit Lengths (k) Class k=128 SEC DED BCH Based 12 to 16 14 to 18 16 to 23 Majority-Logic-Decodable 16 to 24 22 to 32 31 to 48 SEC DED SbED SbEC DbED Table 6-3. Check-Bit Lengths for Various Codes also written back into memory if correction was necessary. In the case of scrubbing access to memory locations, corrected values are again written back into memory if correction was necessary. The time necessary for detection and correction becomes additive to the memory subsystem access time and often generates the need for additional wait states in processor accesses to memory. One potential approach for reducing the performance penalty imposed by the added wait states is to allow the processor direct access to the memory without performing error correction. In this manner the memory contents are forwarded directly to the processor without requiring the delay associated with detection and correction logic. The use of Markov reward modeling techniques may be utilized to establish the frequency of operation necessary for the scrubber, and to analyze the potential for erroneous values to be forwarded to the processor when considering such a provision. The error detection and correction strategies for mass memory subsystems are again optimized to address the error characteristics of the specific application. In addition to the randomly occurring single bit errors induced by environmental factors, the effects of the media involved in these systems introduces burst error characteristics. Reed-Solomon codes, which are sometimes interleaved with other coding techniques and erasure techniques, provide solutions for these applications. Compact disc ROM (CD-ROM) uses cross interleaved Reed-Solom