ITS sys- tems because they are part of the timing network and not part of the transport network. Figure 6-4 shows an example network with connections for external timing and line timing. The solid arrows between the elements represent the transfer of timing information, and in external tim- ing mode, only timing signals pass. In the line timing mode, both timing and data pass over the in- terface. The data transfer between SECs is represented as dashed lines. External timing External timing SSU/BITS SSU/BITS Line timing mode Figure 6-4 Partial Network with External Timing and Line Timing Figure 6-4 also shows that the clock signal starts degrading while being carried over a network of SEC nodes. Each SEC node on the path recovers and regenerates the clock using its own oscillator and phase-locked loop (PLL). During this process, the clock starts accumulating jitter and wander at a rate based on the quality of oscillators being used in SEC clocks. Refer to "Chapter 5. Clocks, Time Error, and Noise", for more information on jitter and wander of clocks. On other hand, the SSU/BITS equipment either sources its clock from a stratum 1-traceable refer- ence or contains a better oscillator, such as a stratum 2 rubidium. By using higher quality timing sources and/or better oscillators, SSU/BITS nodes can filter out the impairments or noise introduced into the timing signal. Figure 6-4 shows such a case where an SSU/BITS node in the middle of a SEC chain is cleaning up the jitter that has accumulated in the clock distribution network across the stratum 3 nodes. This process is sometimes referred as clock cleanup in the timing industry. Use of the terms "master" and "slave" is ONLY in association with the official terminology used in industry specifications and standards, and in no way diminishes Pearson's commitment to promoting diversity, equity, and inclusion, and challenging, countering, and/or combating bias and stereotyping in the global population of the learners we serve. The SEC clock, like any clock slaved to anot