, Ethernet PHY (RMII), Gigabit Ethernet PHY (GMII or TBI), OC-3/STM-1 PHY, and OC-12/STM-4 PHY through the M-5 Channel Adapter, and a Universal Test and Operations PHY Interface for ATM Level 3 (UTOPIA 3)/Packet over SONET/physical (POS-PHY) interface, which can support OC-48/OC-48c/STM-16 MPHY capabil- ities. Also note that OC-3/STM-1, OC-12/STM-4, and OC-12c/STM-4 f are built into the archi- tecture of the SDPs. Moving up one level to layer 2, the SDPs can be independently configured to support Ethernet, High-level Data Link Control (HDLC) streams, POS, frame relay, ATM, and Fibre Channel, as well as almost any other required format, including Multiprotocol Label Switching (MPLS) and other encapsulations. The SDPs are highly programmable; therefore, they support a whole array of diverse MAC interfaces and data-parsing requirements to the extent that each port can be made to implement a different protocol. Programming the SDP must be done in microcode. Motorola provides the microc- ode for a vast spectrum of applications (such as all flavors of Ethernet, IP and ATM over SONET, T/E carrier serial data streams, and SO on). Interestingly, no coding is required on behalf of the user for the support of the diverse MAC interfaces. The RISC core of each CP is clocked at the same frequency as the core clock rate of the C-5e. It possesses its own instruction and data memory of 32KB and 48KB per cluster (that is, a group of four CPs). The RISC core engine's instruction set is a subset of the widely known and used MIPS instruc- tion set, SO Motorola judiciously capitalizes on using a de facto industry standard. The RISC core is programmable in C or C+ This feature lends the computing power of the RISC core of each of the CPs to tasks that can be best implemented in a high-level language. These tasks include the decision making for forwarding, scheduling, statistics gathering, and SO on. The natural result is that bit-level operations can be offloaded to the specialized SDPs; therefore, RISC core capacity is preserved for a