 network proces- sor is housed in a 1,088-pin ceramic column grid array (CCGA) and consumes 22 watts. For com- parison, we will mention that the SCIC is housed in a 399-ball BGA package consuming 5.2 watts and the C192 Queue Manager is housed in an 840-ball BGA with a consumption of 13 watts. In September 2002, IBM introduced a new chipset comprising the PowerPRS 64Gu and the C48 CSI. The PowerPRS 64Gu has the same function as the PRS-64G, but IBM has now replaced the DASL (low-speed serial link of 500 Mbps) with the IBM HSS link (2.5 Gbps). This change simpli- fies the layout and wiring of boards significantly. The 64Gu offers up to 80 Gbps of switching capability and port speeds of up to 10 Gbps/OC-192c. It supports both frame-based (through seg- mentation and reassembly [SAR]) and cell-based traffic. In a protocol-agnostic nonblocking capac- ity, it offers an aggregate throughput of 64 Gbps and 128 Gbps when configured in a 40 Gbps or 80 Gbps switching system, respectively. The afforded overspeed as compared to aggregate user band- width is obvious. A few comments regarding SARing are needed here. IBM considers the SAR function traffic manager related, not switch fabric related. Consequently, any SARing must be handled by the traffic manager regardless of whether this function is embedded inside the network-processor chip itself or whether a separate standalone traffic manager chip is available. The 64Gu is a fixed packet length fabric, whose packet length can be adjusted. This is why IBM calls its switch fabric protocol agnostic. The 64Gu can be configured as 16 input and 16 output ports with 40 Gbps of aggregate user band- width if engaged as a single chip. It can also be organized in a set of two chips, thereby offering 80 Gbps of aggregate user bandwidth along with 32 input and 32 output ports. Each port can have up to four GbE or one OC-48c, or each group of four ports can have one 10 GbE or one OC-192c. The functionality of the C48 is similar to the C192, but used for a single OC48/2.5 Gbps CSIX- L1 conn