uced by adding feedback resistors. These resistors are typically implemented in the cell layout as lightly-doped polysilicon regions. Because the resistivity of polysilicon is very sensitive to the doping concentration and numerous other factors, it is very difficult to control the resistor value [151]. Rockett reports that SEU feedback resistor variance may be as much as half the mean value [152]. To add to this problem, polysilicon resistivity has a negative temperature dependence. This leads to temperature dependence of both the write speed and the SEU response. As low temperature, the feedback resistance increases, providing good SEU performance, but slowing the maximum operating frequency. At higher temperature, the part operates faster, but the SEU threshold drops. These characteristics make it challenging to optimize a resistively-hardened technology SO that it will operate within specifications across a wide temperature range. A variation on the resistive hardening method is the use of gated resistors (essentially thin- film polysilicon transistors) as a feedback element [152]. The advantage of this approach is that during a write pulse the feedback resistance can be lowered to reduce the impact of the feedback element on operating speed. A diagram of the gated resistor-hardened SRAM cell is shown in Figure 3.21. During a write operation, the resistor gates are clocked into a low-resistance condition by the wordline pulse, greatly improving the write speed over a standard resistively- hardened SRAM. At all other times the resistors are in their "off" (high-resistance) state and protect against SEU in the usual manner. The gated-resistor SRAM is therefore faster than a standard resistively-hardened SRAM, has reduced temperature dependence, and may require no additional area to implement [152]. It does, however, require two levels of polysilicon, which although fairly common, are not present in all technologies. II-31 Legend: R(?) -> Gated Resistors Wordline P(?) -> PFETs in N-well at VDD Bitline N(?) -> NF