nd can be managed to achieve a 20-fold increase in peak downlink throughput while ensuring the rich system flexibility for 5G NR. 13.2.1 Channel Coding Aspects Versus UE Complexity To achieve a 20-fold increase in data rate, the error correcting decoder is the critical modem component. For capacity-achieving performance, turbo code and advanced iter- ative decoding algorithms are utilized in 3G and 4G systems. However, not only is the corresponding arithmetic complexity very high, the dedicated accelerator is also typi- cally one of the largest hardware modules in the modem. With the same coding scheme, 13 5G Modem Design Challenges 16 nm Speed (normalized) Figure 13.2 Processing speed characteristics. a 20-fold increase in data rate will fundamentally imply a prohibitive 20-fold increase of the decoder die area. An advanced foundry process node¹ is necessary but not sufficient. Considering a common LTE category supporting two component carriers, the baseline process node is 16 nm. While 7 nm technology is two generation more advanced than 16 nm, it can only provide ~0.5x area reduction and up to ~1.4x faster speed than the 16 nm process node; see Figure 13.2. In other words, advancing the process node by two generations can only improve the throughput by a factor of ~2.8x. A fundamental change in data channel coding is therefore necessary to close the remaining ~7.2x throughput gap. Low Density Parity Check (LDPC) code is considered for NR due to its superior area efficiency compared to turbo code used in LTE, particularly at higher code rates. In [2], the area efficiencies, in terms of Gbps/mm, of an LTE turbo decoder and an LDPC decoder (extended from the 802.11ac decoder design) are compared. As can be observed in Table 13.2, the LDPC decoder can provide up to ~7.5x better area efficiency at high code rates compared to the turbo decoder. It should be noted that the turbo decoding process always operates at a mother code rate of 1/3 - that is, there is no complexity reduction when the code rate is higher and t