idea is to connect a 1 Gigabit Ethernet SAN (or NAS) to the host Peripheral Computer Interconnect (PCI) bus. From an architectural stand- point, the transmit and receive paths are mapped onto different processors. The processing core of the adapter is a pipeline of network processors. Different processors work in parallel to handle different functions of the TCP/IP protocol stack. As a result, the technology scales easily to 10 Gbps. The company provides drivers and application programming interfaces (APIs) and supports Linux and Windows environments SO software can be upgraded to future platforms. Synchronous dynamic random access memory (SDRAM) is used for data and header storage, whereas the electrically eras- able programmable read-only memory (EEPROM) bank is used to store systems code such as the serial bus interface and, more importantly, programmable MAC addresses. The Ethernet interface, which supports both copper and fiber, offers configurable TBI/GMII interfaces with full IEEE 802.3x flow control, IEEE 802.3z compliance, and Remote Monitoring (RMON)/management information base (MIB) support SO traditional data-processing network management can also be expanded encompass storage networks. The TCP/IP engine in the Adaptec ANA-7711 can handle TCP segmentation and reassembly in the hardware; provides slow start, congestion, and sliding window; supports 1,000 TCP sessions; offers the capability of selective acknowledgements; and allows the choice of a configurable window size and Maximum Transmission Unit (MTU) size. It can handle all TCP encapsulation and segmentation requirements as well as TCP decapsulation and reassembly. At the other side of the capability spectrum, a lower-speed approach is taken by Adescom (www.adescom.com), which offers a TOE on its IPAC E100 core that integrates TCP offloading with an Ethernet 10/100 Mbps MAC and supports up to 64K connections. This might seem like overkill as 64,000 TCP connections will rarely need to be supported on a Fast Ethernet link, but it is important to tr