tures. This section describes two types of small cell platform architectures, their pros and cons, and their suitability for different types of disaggregation architectures. The traditional, and most common, hardware architecture for small cells is a system on a chip (SoC), where a SoC consists of several subsystem components specifically designed for the small cell. The other hardware architecture considered is a virtualized architecture, which is an extension of the 5G trend for virtualization to the gNB. These two architectures are shown in Figure 4.6.2. The SoC architecture typically consists of a mix of different compute resources, hardware accelerators, internal memory, and I/O, where these components are sized for a specific set of small cell use cases. This means that a small cell designed for a residential deployment will consist of a different configuration than an outdoor small cell. It also means that the small cell is optimized for a specific disaggregation architecture, and probably won't support all split options. While the dimensioning of the small cell components will vary between SoCs, there is much commonality in what these components are. Typically, there will be two different types of compute architecture: the first is general purpose compute (GPP) where the L3 14 Note that this option was discussed in 3GPP during the 5G study, but has not been standardized in 3GPP. 4.6 Small Cells (1) System on Chip (2) Virtualized Accelerators Compute L3/L2 Software Hypervisor Memory Hardware Figure 4.6.2 Small cell platform architectures. (RRC) and L2 (PDCP, RLC, and MAC) functionality resides; and the second is digital signal processor (DSP) where the L1 (PHY) functions are performed. The GPP and DSP within small cell SoCs are chosen to be low-power options with just enough processing power for the task. There are also tasks within a small cell that are typically implemented with hardware accelerators as they are too compute intensive for either the GPP or DSP. This group of tasks is decreasing over time,