pressive list. Traditional PowerPC CPUs, which are used on the control plane to complete a systems design, should also not be forgotten. Architecture The NP4GS3 architecture combines an array of eight so-called dyadic processor units (DPPUs) next to the embedded PowerPC 405 CPU core. These offer a combined total of 16 active threads and 16 inactive threads. This means that a single NPU can process up to 32 frames at the same time with context-switching overhead when switching between threads. In other words, absolutely no cycles lost when switching from one thread to another. All incoming packet data reside in system memory on the NPU and do not need to be copied to and from some working, register, or user area for pro- cessing, which is usually the case in a computing environment. The data are processed right where they are stored, which definitely improves the performance of the architecture. Support for large lookup tables for layers 2, 3, 4, and other higher-layer functions are performed by hardware-assisted programmable picocode processors using specialized coprocessors for tree searching and updating. The packet-processing prowess of the NPU is distributed among its picoprocessors, coprocessors, and hardware-assisted units. The NPU system design minimizes contention for access to the coproces- sor engines. Forwarding and filtering is done without retaining any data copy by hardware-imple- mented mechanisms, which ensures the wire-speed performance of the chip. Common layer 2, 3, 4, and higher functions can be implemented in extremely fast schemes. For example, support is avail- able for the on-the-fly alteration of frames on well-known protocol elements, such as the Time to Live (TTL) field in the IP header. Tag deletion for virtual LANs (VLANs) and MPLS label manipulation (such as delete or swap) can be implemented efficiently and quickly in IBM's picocode. As mentioned earlier, in order to ensure scalability with high performance, the NP4GS3 enables different connectivity schemes that distribute the neces