er-flow statistics, and modifies packets when necessary. On the other side, the QX-1 handles all queuing, manages congestion, manages per-flow queuing, and is responsible for hierarchical scheduling. When used in the egress path, QX-1 is the last device prior to transmitting the traffic to the phys- ical (PHY) interfaces and enables the precision shaping of traffic directly to the network link(s). The QX-1 offers several types of interfaces that enable it to interconnect to the system switch fabric or line links. QX-1 offers a CSIX or SPI-4.2-based streaming interface when connecting to the switch fab- ric. It supports a 1X10 GbE, 1XOC-192, 4XOC-48, 16XOC-12, or 16X1 GbE channels when con- necting to an external framer or Ethernet multiplexer through the integrated SPI-4.2 interface. Instead of using the approach taken by some other network processors that integrate generic RISC processors, EZchip's TOPcore architecture consists of engines called task optimized processors (TOPs), which are typically 10 times faster than alternative RISC cores and are customized to per- form a specific networking function at an optimal speed. Multiple instances of these fast and efficient processors are integrated inside the same die configured in a super-scalar architecture, which has been designed to optimize packet-processing tasks. The following describes the four types of TOP engines: The OPparse processors handle packet parsing. These processors can parse any type or format of frame or packet, regardless of whether it is encapsulated, and extract entire headers, tags, addresses, port numbers, protocols, bit patterns, keywords, and SO on. The TOPsearch processors handle lookup and search operations by using the parsing results as keys for lookups in the tables maintained by the system for routing, policy, and classification. The TOPresolve processors take care of all forwarding and QoS decisions as well as updating state- related information and the tables themselves. The TOPmodify engines perform all required packet modifica