 AVX2 in the mid-2010s and AVX512 in the late 2010s, first supported by the Knights Landing processor by Intel. ARM A-series (just like Power architecture devices) provides high-performance and high- efficiency hardware support for Floating-Point (FP) and SIMD operations. The ARM A72 core is the "de facto" baseline benchmark core, from which scaling up and down to higher and lower core and frequency classes is done. It supports 128-bit SIMD using what is called the ASIMD (or often, NEON) unit, shown in the execution pipeline below Fig. 4-29: Native Floating-Point (FP) and NEON/ASIMD instructions are executed in the same exe- cution units running at core speed of about 2 GHz in the 16 nm or more advanced technol- ogy nodes. Catching up to Intel efforts, Arm is extending the vector processing capabilities with implementation options for vector lengths that scale from 128 to 2048 bits in the Scalable Vector Extension (SVE) and SVE2 definitions. Rather than specifying a specific vector length, the SVE architecture scales the vector width between 128 and 2048 bits per register, with a Vector-Length Agnostic (VLA) programming model that allows a single piece of software to execute over the range of supported vector widths. The idea is that code no longer needs to be re-written as the processor implementation changes and this obviously reduces deploy- ment cost and time-to-market. Chapter 4 Hardware architecture choices Branch Integer 0 Integer 1 Decode, Integer Multi Cycle Fetch Rename, Issue Dispatch FP/ASIMD 0 FP/ASIMD 1 Store In-Order Out-of-Order FIGURE 4-29 Arm A72 processing pipeline. In order to enable the O-RAN ecosystem, Arm has released a set of reference libraries for Physical layer processing that are optimized to ASIMD/NEON. Performance benchmarking Choosing among processors involves benchmarking to define which device provides the minimum processing power estimated to be used for the application, with some safety mar- gin added. Performance benchmarking can be done using synthetic benchmarks to compare de