ed. Flexibility indicates the possibility to use the CAM to perform different types of operations. Commercial CAMs frequently can be configured either as real CAM or as TCAM depending on the activation of a mask flag. Another configurable feature is the priority policy, whose parameters can be set via a CAM control. Sometimes the prior- ity mechanism can also be disabled SO that all the found matches are reported at the output. A CAM/TCAM realized with dedicated hardware and CMOS 65nm technology can reach 100 Mbit capacity with a width comprising between 40 and 640 bits. With a suit- able clock speed (around 360MHz) the search speed can arrive at 360 Msearch/s, all in a processor-like package Perhaps the most critical performance of large CAM/TCAM is the power consumption and much industrial effort is directed to reduce it. A TCAM having the performances summarized in the earlier paragraph can consume about 15 W. Taking into account that in order to design a core router packet-forwarding engine eight TCAMs could be needed, a power consumption up to 120W can result. A possible way to reduce power consumption is to cascade different pipelines in CAM/TCAM architecture, as shown in [107]. In this case, maintaining a low latency, which means limiting the number of cascaded pipelines, an energy consumption as low as 7W seems attainable. Another possible approach is to use FPGAs to program the CAM/TCAM functionality. In principle, FPGAs are general-purpose chips, being thus less optimized with respect to a specific dedicated hardware. In practice, the huge volumes and the large application domain of FPGAs have pushed a rapid improvement of performances via SO good a design optimization that sometimes they are competitive with dedicated chips. From a density and power consumption point of view, the last three generations of FPGAs have seen the density scale from 10k gates to 300k gates and the power consump- tion from 30 to 12W (see Section 5.7.3) [110]. Therefore it is possible in some conditions to spare a few watts us