achieved by the deposition of 8.3 X 1011 MeV/g(GaAs) of non-ionizing energy, delivered by proton fluence of 1.8 X 10 14 p/cm². The radiation hardened characteristics of GaAs technology enabled tolerance to the 5 x 107 rad d(GaAs) total ionizing dose which was imparted at these fluence levels. A similar technique for achieving reduced carrier lifetime in the substrate through formation of recombination sites using low temperature grown buffer layers (LT GaAs) has shown the ability to provide immunity to single event upsets. The low temperature layer formation results in about 1% excess arsenic being introduced into the crystal which coalesces into precipitate sites which form very fast recombination centers. The material thus efficiently eliminates the charge enhancement mechanisms described above; test results exhibited SEU immunity up to maximum LET of 90 MeV_cm2/mg at particle fluence of 1 X 107 particles/cm2 Identical devices fabricated without the LT layer exhibited threshold LET approximately 1 MeV_cm2/mg and an appreciable cross section. 6.3.4 Mitigation of Circuit Response [Vinson92][Rockett88] [Calin96] [Liu92] Techniques to mitigate circuit response include provisions to increase critical charge, to suppress response by limiting circuit bandwidth such that no response is provided to the short collected pulse, and to provide circuit design provisions which block the propagation of pulses in memory cell feedback paths. Commercial SRAM manufacturers have utilized stacked capacitor structures to increase cell capacitance, decreasing the voltage transient due to collected charge, and also reducing the bandwidth of the cell to respond to short transient pulses. The use of high valued polysilicon resistors (typically exceeding100K ohms) in the feedback path of RAM cells is indicated in Figure 6-6. The resistance works with the cell Yord Line capacitance to reduce the bandwidth of the feedback path, preventing the cell from responding to the short duration of charge collection. Limiting the cell bandwidth in thi