deal of material to reach the sensitive region [129]. Devices with vertical structures (e.g., power MOSFETs) may be sensitive to charge collection deep within the substrate and may exhibit interesting energy effects [130]. A recent study using carefully controlled experiments demonstrated that for four CMOS SRAM technologies, no significant differences were observed between low- and high-energy II-26 heavy ion SEU data [118]. For example, Figures 3.16 and 3.17 show low- and high-energy data for two of the tested technologies, a 256Kb SRAM and a 1Mb SRAM. Within experimental uncertainty, the cross-section data measured with low-energy ions (open symbols) and high- energy ions (solid symbols) appear the same. In the few inconclusive cases where there may have been small differences, the low-energy ion data were always conservative compared to the high- energy data. This suggests that standard low-energy ion testing is sufficiently (but not overly) conservative for CMOS SRAM technologies down to 0.5 um (the smallest technology tested). The results were explained by the fact that the track structures of low- and high-energy ions are not greatly different except in the outer regions where they have low charge density. Due to the large radial extent of the track, high-energy ions might be expected to cause more MBUs than equivalent low-energy ions. The authors of [118] therefore examined their high- energy SEU data for evidence of MBUs. None of the almost 4000 error maps taken at low- and high-energy facilities showed physically adjacent upset locations. Unfortunately, only about 400 of the error maps were from high-energy facilities, but none of these maps gave evidence of an increase in normal-incidence MBUs due to high-energy ions. Of course, at grazing angles of incidence we would expect a big difference between low- and high-energy MBU results due to range effects. In the future it is possible that there will be devices sensitive to the low induced charge densities in the outer regions of high-energy ion tracks, b