 engineers, responsible for the overall frontend design, communicate their desires by means of specification models for the behavior of the frontend building blocks. Creating these models involves synthesis, specification translation and system exploration. Circuit engineers create a transistor netlist. This netlist acts both as a specification model for layout and as an implementation model for building block verification at the architectural level. Here, in a verification step, one checks whether the implementation model can be mapped on the specification model that was initially passed down. A nonideality is said to be non-dominant if there is no frequency band of interest in which the nonideality contributes the major part of the unwanted signal energy. 2 For a more complete introduction to hierarchical design methods, see [Donn98]. 2.1 MODELS, MODELING AND ANALYSIS system-level frontend model RF in Synthesis & Spec Translation Exploration Verification building block models wo. go W1,q1 Wn. In Synthesis & Spec Translation Exploration Verification circuit-level model to o- Exploration Figure 2.3: Minimizing design time requires the introduction of hierarchy in the design process. Frontend design is done in terms of LNAs, filters, mixers, A/D converters, etc. These building blocks (e.g. a A/D converter) are in turn implemented using integrators, operational amplifiers, etc. In a next step, transistor-level details are filled out. To support this hierarchical design process, good models are of utmost importance. They serve as interfaces used to communicate design decisions between the different levels in the design tree. 2.1.4 Modeling languages All models used in a top-down design flow need to be "good models": they must ac- curately represent real-life system behavior. For example, a system-level mixer model should capture all of the relevant behavior that characterizes a mixer's transistor-level implementation. Otherwise, wrong design decisions will be taken at the architectural level, them being based on ana