for the test setup. Regarding the equipment limits, the same source of reference information is available, specifically the clock limits in G.8273.4 (in clause 8) and the network limits in clause 7.3.2 in G.8271.2. The following represents a synopsis of the performance tests of T-BC-P/T-TSC-P clocks from G.8273.4: Frequency accuracy: Confirm that when running free, the clock's oscillator is accurate to within 4.6 ppm of the nominal frequency. Noise generation: The tester applies an ideal signal and measures the phase error on the signal returning from the DUT. For this case, the tester generates a PTP signal, passes it to the meas- urement port via the DUT, and measures the amount of TE introduced. The output of the T-BC-P is measured at both the 1PPS output and the PTP master port; the out- put of the T-TSC-P is measured at the 1PPS output (if available). As in the assisted case, the value for the limits of max|TE| is currently for further study. The tester calculates the cTE (averaged over 10,000 s) and the MTIE and TDEV for the (filtered) For cTE, the limit applicable for Class A is +50 ns, and for Class B it is +20 ns (the same as the T-BC-A/T-TSC-A case). The dTEL (after 0.1-Hz filtering) should be less than 200 ns peak-to- peak (again, tested over 10,000 s), while the dTEH limit is for further study. See section 8.2 of G.8273.4 for more information on the noise generation limits and perform- ance of T-BC-P/T-TSC-P clocks. Tolerance to phase/time and frequency noise from the input (PTP and SyncE) signals: The tester applies a noise pattern to the timing input signal while the engineer monitors the clock be- havior. A pass result is that the DUT should maintain its lock to the reference signal without switchover or moving into holdover. The PTP noise is the max|pktSelected2wayTE network limit (1100 ns from clause 7.3.2.1 of G.8271.2) applied as an input (it is only defined for option 1 networks), which is the maximum allowed TE at the end of a chain of clocks. The tolerance to frequency wander must be the sam