ng Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. IBM POWERNP IBN POWERNPTM The heart and brains of the NP4GS3 are formed with the combination of the EPC and the ePPC. Figure 4.4 shows the EPC in more detail. It contains eight DPPUs and nine Hardware-Assist coprocessors. It determines what must be done with the frames received in the data store on either ingress or the egress side of the NPU. It provides the overall steady state control and programmabil- ity of the NPU-i other words, the code that makes the NPU equivalent to a programmable ASIC. The ePPC is a specialized PowerPC CPU core with 16KB of instruction cache and 16KB of data cache, which can be used to provide CP functionality- other words, the nonsteady state process- ing for packets. As mentioned earlier, each NP4GS3 has 8 DPPUs (16 programmable protocol processors) and each DPPU has 9 Hardware-Assist coprocessors. These packet processors share 128K of the local control store memory; for more space, external memory is needed. Incoming packets/frames are allo- cated and assigned to specific threads. When processing is completed, they are de-allocated and passed over to the corresponding scheduler. NEVs can modify the code that runs in the NPU or develop their own software that runs on the CP processor. IBM provides both high-level (C application programming interfaces [APIs]) and low- level APIs to facilitate the interface with the network-processor system for software developers. On-Chip Memories Off-Chip Memories TSM Arbiter Ingress Egress Enqueue Counter Policy Enqueue PowerPC Completion Unit Manager Manager Interrupt Debug LU Def Table EPC CAB Interrupts Interrupts & Comp Table & FreeQ's Control FreezeEPC Single Step Control Internal EPC Exception Egress DS Egress Ingress interface (Read/Write) interface interface Ingress interface (Read/Write) CAB Arbiter Instruction CAB Watch interface Memory CABWatch Ingress