onfiguration of an instruction and/or data cache, a memory interface, interrupt control mechanisms, timers, and the size and count of registers. Most importantly, it allows the potential insertion of custom units that the company calls generically designer-defined execution units. These execution units can be blocks such as a floating-point unit or even a full-fledged, very pow- erful, customized-width DSP engine that can even have multiple MACs for extremely fast DSP pro- cessing. In the case of instruction extensions, the configuration of the data path must be reiterated using the company's processor generator tool. Instruction set extensions (a feature that network- processing system designers using this platform seriously need to engage) are easily coded in what Tensilica calls Tensilica Instruction Extension (TIE) language. This is a Verilog-like language that Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES 177 describes the desired instruction mnemonics, operands, encoding, and semantics into what the com- pany calls TIE files. TIE files serve as inputs to the processor generator tool. This takes a matter of minutes if the user knows architecturally what he or she wants to achieve and not more than a few hours if the user must think through the architecture and experiment first. Once this done, the user uploads the newly produced configuration tools to Tensilica, who will gen- erate a new set of development tools for the user. The flexibility afforded toward configuring a CPU data path is revolutionizing the industry. It no wonder that Xtensa cores have been chosen by several network-processing chip designers to be part of larger in-house created designs. These designers