- anced read/write workloads. Because of its common I/O, DDR is more pin efficient for workloads where read operations dominate write operations. Some competition to DDR SRAM appeared from a newcomer technology called Sigma SRAM in early 2002. This technology was positioned mainly for the 5Gbps realm, but it does not seem to have attracted significant market acceptance yet. CAM is a peculiar, but very interesting, memory technology. We discussed CAM and its role exten- sively in Chapter 12, "Search Engines," and Chapter 13, "Classification Processors." For more detailed information on CAMs, refer to those two chapters. We will summarize some systems-related issues and characteristics of this technology. The brute-force hardware lookups that CAMs provide require incurring both a significant cost and performing a worst-case power consumption analysis. Many CAM vendors do not happily provide their worst-case power needs. In a recent Communications Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SYSTEMS ENGINEERING ISSUES SYSTEMS ENGINEERING ISSUES 339 Systems Design conference in 2002, one of the major CAM vendors privately disclosed that their 9Mb CAM has a worst-case power consumption of 12 watts! Therefore, it is imperative that the correct numbers are unearthed from CAM vendors. For the systems designer, CAMs are attractive in the following situations: When large bit patterns must be recognized using classification based on multiple bit fields because of the use of many pins. As we say in the industry, CAMs "do a lot of work per trip across the I/O pins." Approaches using conventional memory usually need to make many trips as the bit pattern that will be classified gets bigger. When table sizes are small, as storing large lookup tables in CAMs is often prohibitive, as meas- ured both in direct chip cost and power consumption needs. When loo