of the square of the gate length. Unfortunately, the parasitic capacity and resistance cannot be neglected in a high-per- formance CMOS after the 90 nm node, SO that the behavior given by Equation 5.35 is no more even approximated. Technology for Telecommunications: Integrated Optics and Microelectronics Capacitance (F/um) Intrinsic Parasitic MOS gate length (nm) FIGURE 5.40 Intrinsic and parasitic CMOS gate capacitance versus the different component generations. (After Parthasarathy, S.E. and Thompson, S., Mater. Today, 9(8), 20, 2006.) Resistance (12/um) Intrinsic Parasitic FIGURE 5.41 Intrinsic and parasitic CMOS gate resistance versus the CMOS generations. (After Parthasarathy, S.E. and MOS gate length (nm) Thompson, S., Mater. Today, 9(8), 20, 2006.) The decrease of the intrinsic capacitance of the CMOS and the behavior of the parasitic one is demonstrated in Figure 5.40 and a similar plot is shown in Figure 5.41 for the intrin- sic resistance and for the parasitic resistance [47]. Several phenomena imply a growth of the parasitic parameters. As MOSFET geometries shrink, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold volt- age of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available. The final MOS design is a compromise between strong current in the "on" case and low current in the "off" case. Sub-threshold leakage which was ignored in the past can now consume upward of half of the total power consumption of modern high-performance very large-scale integration (VLSI) chips [49,50]. The gate oxide, which serves as insulator between the gate and the channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. Telecommunication Networks However, with current gate oxides with a thi