following represents a synopsis of the performance tests of T-BC-A/T-TSC-A clocks from G.8273.4: Frequency accuracy: Confirm that when running free, the clock's oscillator is accurate to within 4.6 ppm of the nominal frequency (of the Ethernet signal). There is no mandatory need for a frequency reference, and this is the same requirement on frequency accuracy as the stan- dalone EEC clock. For further details, refer to the preceding section "Testing EEC and eEEC SyncE Clocks" for testing frequency accuracy. Noise generation: The tester applies an ideal signal and measures the phase error on the signal returning from the DUT. So, like the T-BC/T-TSC case, the tester generates a time signal, sends it out one port, receives the return signal on another port, and measures the amount of TE intro- duced by the time signal passing through the DUT. G.8273.4 currently defines noise generation limits only where 1PPS is the input signal to the DUT, not when it is delivered by PTP. The output of the T-BC-A is measured at both the 1PPS output and the PTP master port; the output of the T-TSC-A is measured at the 1PPS output (if available). Unlike the G.8273.2 case, the value for the limits of max|TE| is currently for further study. The tester calculates the cTE (averaged over 10,000 s) and the MTIE and TDEV for the (filtered) dTE. For cTE, the limit applicable for Class A is +50 ns, and for Class B, it is +20 ns (the same as the T-BC/T-TSC case). The dTEL (after 0.1-Hz filtering) should be less than 50 ns peak-to- peak (again, tested over 10,000 s), while the dTEA limit is for further study. See section 7.2 of G.8273.4 for more information on the noise generation limits and perform- ance of T-BC-A/T-TSC-A clocks. Tolerance to phase/time noise from the input (PTP or 1PPS) signal: The tester applies a noise pattern to the timing input signal while the engineer monitors the clock behavior. A pass result is that the DUT should maintain its lock to the reference signal without switchover or moving into holdover. The PTP noise is th