 processor offloading the heavy-duty classification chores, enabling the NPU to benefit from plenty of saved capacity cycles that it can use for other types of work. A 2MB on-chip rule memory can be accessed in a single- or dual-plane approach (for online and standby setups). In order to further extend the rule database, the RQDPC10G can easily interface to up to 128MB of external SSRAM (either zero bus turnaround [ZBT] or sync burst) through a 64-bit-wide bus. Such an approach, however, would degrade the performance by 50 percent to 5 Gbps maximum classification throughput, but only when all the rules are stored in external memory. The interfaces to the MAC/framer, network processor, and the one used for cascading multiple RQDPC10G chips are standard System Packet Interface 4.2 (SPI-4.2). The results bus is 32 bits wide and SSRAM compatible, which is handy if subsequent indexing is required or more often for the NPU interface itself. It had been announced that the company's first-generation product was being designed in a 0.18 um process technology. Therefore, ample room would be available for relatively straightforward future improvement if the market requests it. It would be offered in a 550-pin ball grid array (BGA) that should consume approximately 5 watts. In fact, the ReGXP2G regular expression coprocessor, which is designed with a look-aside interface to the NPU, supports an aggregate data rate of 2.5 Gbps. It was taped out to manufacturing toward the end of 2002 and is available in a 648-FBGA package. It supports packets of up to 9KB and can handle up to 4 memory banks of 8MB of ZBT SSRAM, using up to 8,000 regular expressions per bank and up to 8 rule sets per bank. The Regular Expression Coprocessor supports rule matching across multiple packets. The user can be sure about its deter- ministic performance at wire speed regardless of the packet size, the protocol used, the complexity of the rules, or the actual number of rules. Classification results are presented on the 32-bit-wide results bus. They can