EU performance [71,141- 146]. Even in body-tied SOI designs, manufacturers have found it necessary to incorporate other hardening methods for applications where very high upset thresholds are desired [147,148]. Fully-depleted SOI transistors exhibit reduced floating-body effects, and have shown excellent SEU performance [149]. Given an understanding of the upset mechanism in SRAMs, we can immediately understand another typical technology-level technique used to harden SRAMs against SEU. We have discussed (Section 3.4) how the SEU process in an SRAM is essentially a race condition between the feedback and recovery processes. To harden an SRAM, we need to either slow the feedback process or decrease the recovery time. The feedback process can be slowed by adding either resistance or capacitance to the feedback loop [150]. Cross-coupled feedback resistors (see Fig. 3.9) are the classical method of increasing the cell feedback time by increasing the RC delay in the feedback loop. Unfortunately, because the SEU process in SRAMs looks just like the write process, this same RC delay directly impacts the write pulse width of the SRAM. The resistive decoupling technique is very effective, as illustrated in Figure 3.20. This figure shows the measured SEU cross-section (area of the chip sensitive to SEU) as a function of LET for a microprocessor before and after hardening by resistive decoupling [101]. The predicted upset rate in a geosynchronous orbit for the unhardened microprocessor is about once a day, while in the resistively-hardened part it is about once per century. Unfortunately, the effectiveness of resistive hardening does not come without a price. We have already mentioned the speed penalty incurred by adding feedback resistors. Probably even II-30 Commercial Part Rn=50 kn 160 kn LET (MeV-cm2/mg) Figure 3.20. Measured SEU cross-section of a 16-bit commercial microprocessor showing the effectiveness of resistive hardening for mitigating SEU [101]. worse than this penalty is the increased process complexity introd