CTURES 139 (primary and redundant) Switch Fabric Interface CSIX-L1 CSIX-L1 SPI 4.2 SPI 4.2 Control Traffic Traffic Manager Manager SPI 4.2 SPI 4.2 ZBT SRAM interface SPI 4.2 SPI 4.2 Two 1x10 GbE or Two 10x1 GbE MAC interfaces FIGURE 9.1 An example of an OC-192 line card based on the Silicon Access iFlow NPU architecture. (Source: Silicon Access.) in the context of CAM in Chapters 12 and 13). Therefore, it actually saves the external SRAM that is normally required when such an external CAM is used. The iCL can handle classification tasks layers 4 through 7 with 36K entries up to 144 bits each providing both per-entry and per-hop associ- ated data in a single access. Multiple iCL and iAP chip pairs can be combined to support larger tables. It is important to note that both iCL and iAP provide error correction coding (ECC) on all their embedded memory. This feature makes them especially useful in network gear destined for carriers that provision edge and core networks where reliability is critical. Powered from a 1.2V supply, the iCL is offered in a 560- pin EBGA package and consumes typically less than 2.5 watts. The iAP is primarily used for address searching and, more specifically, for Ethernet MAC, n-tuple flows, and virtual private networks (VPNs) with tag lookup, or traditional Internet Protocol version 4/6 (IPv4/v6) address lookups. It contains embedded memory, which can be filled with up to 256K table entries (producing the equivalent content of a 9Mb CAM) for IPv4 or 82K table entries for IPv6 addresses. The iAP is rated at 65 million lookups per second with deterministic result latency. penalty is associated with the key size. It can perform more than two lookups per minimum-length packet at OC-192 speeds, and associated data fields can be modified on-the-fly by the on-chip arith- metic logic unit (ALU) simultaneously with any lookup operation. In addition to the chip's double cycle deselect (DCD) synchronous SRAM (SSRAM) interface, its available zero bus turnaround (ZBT) SRAM interface enables it to conne