esting of memories involves loading a pattern and setting up desired test conditions, exposing the Device Under Test (DUT) to some predetermined fluence, and interrogating the device to determine level of functionality and changes from the initial test conditions. The exposures may take place either in air or vacuum for high energy (>10 MeV) protons, and it is almost always required, for health safety reasons, that test personnel be remote to the exposure area during irradiations. Usually, the test setup involves test equipment (e.g., memory tester, computer with controller card, transient digitizer, etc.) local to the test and the ability to control that equipment remotely from either an extended monitor and keyboard or across a communication link or network connection. IV-23 For devices other than memories, the test instrumentation can become quite complicated. For example, processor tests may require comparison with either a second (ghost) processor or with expected results emulated in software. Such a test usually involves real time monitoring of the DUT during exposure. Often, testing of a given component must be done in situ with supporting flight hardware and software to fully assess the impact of SEEs and their likelihood of propagating through the system. This is especially true for circuit implementations incorporating error detection and correction circuitry. Throughout this section, the examples for discussion and case studies have been selected to illustrate not only some of the effects that protons may have, but also the choices and tradeoffs confronting the test engineer in gathering meaningful data without overcomplicating the test effort. 4.1.1 High Speed Technologies: While there still exists some controversy regarding the ability to accurately correlate proton and heavy ion SEE sensitivities, it is generally agreed that protons are more likely to affect technologies which exhibit lower thresholds for heavy ion SEE effects (e.g., LET below ~10 MeVcm2/mg). By virtue of their lower nodal capacitan