ents that can function as PTP-aware devices (meaning some form of PTP clock). Of course, the most common of these is the boundary clock and the trans- parent clock. For the telecom profiles, these are known as the T-BC and the T-TC, respectively. The transparent clock is a straightforward device in concept; it uses an accurate oscillator (ideally with a frequency reference such as SyncE) to measure the residence (transit) time of the PTP mes- sage as it passes through the node. This residence time is then added to the correctionField SO that the slave can compensate for any delays that the message suffered in its path from master to slave. An example of how the correctionField is used is included in the section "Correction and Calibra- tion" later in the chapter. The boundary clock is quite a bit more involved. As illustrated in Figure 9-12, the concept is straightforward, although the hardware design is quite complex. There is a whole section in Chapter 12 on clock hardware design, SO you are referred to that for a more detailed description on how a PTP-aware T-BC is designed and implemented. Egress Time carried Time carried Ingress in H/W in H/W Time- Time- stamper stamper Frequency Time carried Time carried Frequency via SyncE in packets in packets via SyncE Timing subsystem Master port Controlled time error Slave port G.8273.2 Class A, B, C, D Figure 9-12 Functionality of a PTP Telecom Boundary Clock Look first at the frequency subsystem, as SyncE on the (right-hand) ingress port is being used as the frequency source for the system. The SyncE is recovered and routed over a hardware signal to the PLL dealing with frequency. The output frequency of the PLL is then eventually routed out to all the egress ports (including the one on the left). For phase/time, the ingress port is configured as a slave port and incoming PTP messages are timestamped on arrival. The source of clock for the timestamping comes over a hardware path from the timing subsystem. Following timestamping, the incoming messages and timestamps a