ption scenario (bug_exh5) D. Enter the command print state; the Simulator answers: > print state btoa (1) ! state = ready atob (1) ! state = ready = dlca!dlc (2) ! state = waitua dlcb!dispatch ! state = ready dlca!dispatch ! state = ready Exhaustive Simulation 243 We see that instance 2 of process DLC in block DLCa is in state waitUA. If we look at the SDL model, under this state no input or save of signal L_DataReq are specified. Thus, this signal has been discarded. 7.4.6.3 Correct the exception We decide to save signal L_DataReq in state waitUA, because once the connection is set up, the signal can be processed. A. Exit from the Simulator (answering No to the question). Do not exit from the Editor. B. In Windows (or Unix), make a copy of the file v76.pr into v76_v7.pr. C. In process DLC, partition part1, add below state waitUA a save symbol containing signal L_DataReq, as shown in Figure 7.58. D. Save the SDL model. waitUA V76frame (V76para) L_DataReq V76para ! present N320cnt < N320 Figure 7.58 Process DLC after adding save L_DataReq 7.4.7 Eleven minutes to detect missing input L_ReleaseReq and answer DM 7.4.7.1 Run again the exhaustive simulation A. In the SDL Editor, unload all files except v76.pr. B. If the ObjectGeode Launcher is not running, in the Editor select Tools > SDL & MSC Sim- ulator. C. In the ObjectGeode Launcher, remove any file other than v76.pr, press the Build button, then, if there are no errors, press the Execute button. D. In the Simulator, select Edit > Configuration and set Reasonable environment to on (box checked) and Loose time progression to off (box not checked). E. Select Edit > Filter Conditions and check that the filters are the same as in Section 7.4.5.2 (especially the signal loss is no longer filtered). F. Select Execute > Verify, press Verify and confirm the verification startup. The exhaustive simulation starts: mode breadth deadlock limit 2 exception limit 2 , halt stop limit 2 define stop_cut true define states limit 0 define depth_limit 0 244 Validation of Communication