n the left FPGA on board 2. The right FPGA on board 2 hosts the transmit processing for the uplink (see top of Figure 11.6) as well as the interfaces to the radio frame (RF) unit. The left FPGA on board 1 contains the MIMO-OFDM MMSE equalizer for the downlink. Coarse and fine synchronizations in downlink are implemented in the right FPGA on board 1. In total, four DSPs are mounted in a sandwich-like fashion on board 1 as well. There are external interfaces to the RF via low-voltage differential signaling (LVDS), to 1 Gb/s Ethernet for real-time data applications, and to the local moni- toring terminal (LMT) where received constellations, channel estimates, and other information are displayed. Terminal RF units operate in full-duplex frequency division duplex (FDD) mode at 2.53 and 2.68 GHz. The spectrum on the air is shown in Figure 11.8. Note that the second transmitter, which is available in our experimental terminals, has been fed with the same signal, and cyclic delay diver- sity (CDD) has been applied. At the base station, commercial RF units and duplex filters matched to the new 3G spectrum have been used. Terminal and base station © 2009 by Taylor & Francis Group, LLC user 1 user 1 FD MIMO Pilots exp(-j2xf UL,est1t) CFO DEMUX EQUALIZER Terminal 1 user 2 UL.err2 exp(-j2xf Channel and phase UL.err1 exp(-j2xf Receiver error estimation user 2 -UL,est2 Pilots exp(-j2xf Individual phase tracking Terminal 2 at the base station Frequency advance at each terminal Figure 11.6 Uplink transmitters and receiver for virtual MIMO. © 2009 by Taylor & Francis Group, LLC Long Term Evolution: 3GPP LTE Radio and Cellular Technology Hardware Structure of 3G LTE Experimental System LMT application USB 2.0 (Notebook) Backplane Backplane interconnections FFP basic VP100 Board 1 FFP Basic VP100 Board 2 64 Bit FPGA 1 FPGA 2 FPGA 1 FPGA 2 interconnection LMT control MIMO-OFDM FEC Decoding TX SC-FDMA 2x2 SDEMUX Processing Framing, DeMux Processing (1 or 2 Antennas) (linear MIMSE Equalizer) FEC Encoding Synchronization RF Interface, F