sion to replace common internal bus or ring that was becoming the bottleneck with a switch fabric. The switch fab- ric can be conceptually visualized as an intelligent network that provides multiple parallel connec- tivity paths from any ingress port to any egress port. Figure 14.5 shows the concept of the evolved multiservice switch. To increase efficiency and maximize the available switching capacity or bandwidth, incoming packets would be fractured into meaningful smaller pieces of information called frames or cells. shared control CPU in the switch fabric would tag these frames or cells performing the work of the original port-mapping function with the correct destination port number. The frames/cells would then be injected into the switch fabric. The switch fabric would be responsible for their automatic routing to the appropriate egress port through a sequence of actions from the various switching elements inside the fabric. At the egress port, the fabric would strip those frames/cells from their internally cre- ated tags and headers/trailers needed to traverse the core. They would then be automatically reassem- bled into their original parent form by combining their multiple segmented offspring frames/cells. Different types of switch fabrics are available. Some can only handle fixed-size packets (such as cells), whereas others can handle variable-size packets. In order to fine-tune and optimize the performance of the evolving switch fabric architectures, a major issue was deciding where buffering would need to be introduced. Three obvious options buffers introduced at the input, the output, or both. Because controlling or avoiding the potential blocking conditions altogether remains one of the primary objectives of switch fabric designers, many techniques and combinations of methods have been used to address this problem and this is discussed in-depth in a good fundamental switching texbook like S. Keshav's book (see footnote 12). A major technique is to use buffers inside the switch fabric core, for examp