chitecture based on a single central- ized memory and a time division bus-based switch fabric. Line interfaces are indicated with LI. Switching Systems: Architecture and Performances Routing calculation: Since routing calculation by access to the routing and forward- ing tables is carried out contemporary to the new transfer of the packet to the RAM memory we have that the time needed for this phase is Max(t ro TRAM), where tro is the time for the routing calculation that is dominated in this context by the RAM access time, since also the routing and forwarding tables are hosted into the RAM Transfer of the packet to the output line card: The needed time is T+ TRAM If we call T the time needed to access to the RAM and write a bit, and t the time needed to elaborate the operation corresponding to a clock cycle in the CPU, we can say that RAM proportional to T and tel is proportional to t. Regarding the term Max(tron T + TRAM), faster the processor, more the term T TRAM is dominant. At the end, the time TIP needed for the processing of a packet can be written as (7.42) where a and b are constant depending on the process implementation. Equation 7.42 means that increasing the speed of the processor more and more beyond the value (3 + 3aT)/b is useless, since the packet processing time is dominated by the bus speed and by the access time to the memory. Not only the speed of the processors increases much faster with passing from a CMOS technology node to the other with respect to the memory writing time, but the bus access and propagation time can be improved only by increasing the bus speed, again much slower compared with the processors' speed evolution. Thus, in order to fully exploit the CMOS continuous evolution to burst routers speed, a most efficient architecture has to be devised. An important step ahead is done using the architecture depicted in Figure 7.54. Distributing fast processors and route caches, in addition to receive and transmit buffers, over the interface cards reduces the load on the system bus a