the ASI chip. It can be compiled by Agere's VLIW compiler into VLIW engine code. In order to ensure that freshly written code executes within the available number of clock cycles, the program- mer also has access to the VLIW instruction simulator. The effort customers put forth to write their own code from scratch to implement various common functions or protocols is further minimized by Agere's library of code blocks that provide reference implementations of protocols. These include protocols such as IP over AAL5, IP over SONET, and POS/Point-to-Point Protocol (PPP) as well as raw switch functionality such as the implementation of the WRED algorithm, aspects of ATM polic- ing, or traffic shaping. The array of available tools inside Agere's FestinoTM Software Development Environment (SDE) in its latest version 3.0 includes a full-fledged performance and functional simulator of individual chips from the product family and of systems with multiple-chip topologies and configurations. This enables the offline analysis and simulation of switch designs that even include external custom logic. The latter is depicted in the SDE environment by using an extended model based on eXtensible Markup Language (XML). A source-level debugger for FPL completes the toolset along with a traf- fic-generation module, a throughput-accurate software simulator, and one common environment that offers support for both the OC-48c and the OC-192 realms. In addition to a convenient graphical user interface (GUI) approach, the environment has the following: A tracer tool, which keeps track of an individual packet during its lifetime inside a system and logs all functions and subsequent actions taking place on it. A profiler, which can help by throwing the proverbial spotlight on performance bottlenecks through the identification of the number of clock cycles spent on a particular context or on a specific "tree" (in Agere's meaning of the word, as we have seen). An available Software Development Kit (SDK) enables the designer to write C- or Java