iple of operation of virtual concatenation for a high-order VC-n-Xv. Chapter 11 Next Generation Synchronous Digital Hierarchy Frames Multiframe 1 Multiframe 2 HO VCAT Reserved (= "0000") Reserved (= "0000") 512 ms Fig. 11.10 H4 coding for a high-order VCAT OH. LO VCAT Payload Containers VC-m-Xv C-m-Xc VC-2-Xv VC-12-Xv VC-12 500 us q + 1 VC-11-Xv VC-11 q + 1 VC-m-Xv 500 us Fig. 11.11 Principle of operation of virtual concatenation for a VC-m-Xv. container consists of 9 rows by p + 1 columns, where p is either 260 or 84 for VC4 and VC3 payloads, respectively. Each VC-n has its own administration and management path over- head, while the remaining columns contain the payload. The H4 byte of each OA&M path overhead contains VCAT path overhead. The signal label in the OA&M path overhead (C2 byte) indicates that the H4 byte is to be used for this purpose. As previously discussed, the standards require a maximum differential delay tolerance between VCAT members of 256 ms. This has been implemented through the use of a two- stage VCAT multiframe, as illustrated in Figure 11.10. Because each frame is 125 us, 4096 multiframes provide the necessary 512 ms (+256 ms). The four most significant bits of H4 (MFI1) are used for the first stage, creating 16 frames per multiframe, and the four least significant bits (MFI2) of the first two frames of a multiframe identify each of the 256 multiframes. To reassemble the members at the receiving interface, the sequence indicator byte is implemented as four bits in frames 15 and 16 of each multiframe. Low-Order VCAT Low-order virtual concatenation employs a similar mechanism to route low-order virtual containers over the SDH infrastructure and reassemble the low-order paths at the far end. The frame structure of a VC-m-Xv consists of 4 rows and (q +1) columns and is repeated every 500 us. The first 4 columns contain the four POH bytes. The value of q is dependant on the type of container, as shown in the Figure 11.11 inset. Link Capacity Adjustment Scheme Signal Label "101" - Extended S