 APP750TM (EX-TM10) CHIPSET Agere had originally targeted the PayloadPlus family to the OC-48c (2.5 Gbps) market. It has recently introduced a new chipset (originally called PP10G) that scales the architecture up for the OC-192 (10 Gbps) realm and offers carrier-class performance in edge and core networks. The NP10 network proces- sor and the TM10 traffic manager chips (recently renamed APP750NP and APP750TM, respectively) comprise the new chipset, which can handle complex multifield packet classification, policing, queu- ing, statistics, scheduling, shaping, buffer management, and, of course, cell or packet modification. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. AGERE PAYLOAD PLUSTM FAMILY OF NETWORK PROCESSORS Switch fabric Ten 2.5 Gbps serdes memory 750TM 750TM memory memory 750NP Host CPU Ingress OC-192 Framer memory PCI 2.2 32-/64-bit bus 33MHz or 66MHz Egress FIGURE 7.7 A block diagram of a typical OC-192 line card based on the APP750NP/ APP750TM chipset. (Source: Agere) Figure 7.7 shows the block structure of a typical 10 Gbps system based on these new chips. The three-chip configuration can easily handle full-duplex 10 Gbps, supporting wire-speed processing based on access control lists (ACLs) with thousands of ACL rules; however, an additional APP750NP network processing unit (NPU) may have to be used if the intended system design requires egress classification. One of the major advantages of the new chipset is that it works with inexpensive external DRAM. It requires very little SRAM to provide high-performance functionality. As the classification rule data- base is stored in fast cycle RAM (FCRAM), which is also referred to as network DRAM, no external CAM is needed. For instance, 1 million Internet Protocol version 4 (IPv4) routes can be kept in DRAM with separate information for each virtual private network (VPN) supported.