d coprocessors that handle other functions are located next to these. These include a buffer management unit (BMU), a table lookup unit (TLU), a queue manage- ment unit (QMU), a fabric processor (FP), and a supervising CPU that Motorola affectionately calls executive processor (XP). In addition to this heavy artillery inside the NPU die, intrinsic provisions are available to interface externally with an optional traffic management coprocessor (TMC). This role is ideally fulfilled by the company's powerful Q-5 chip. The CPU combination of what is available inside the C-5e leaves more than 4,500 millions of instructions per second (MIPS) of computing power for a switching/rout- ing systems designer who may be confronted with the task of adding services throughout the prover- bial protocol stack. Sixteen channel processors (CPs) are at the heart of the C-5e design. These are extremely flexible computing engines that can be individually programmed. Their flexibility means that each engine can be programmed to play different roles depending on the application at hand. Therefore, they can be made to easily support Asynchronous Transfer Mode (ATM), Internet Protocol (IP) over Ethernet IP over Point-to-Point Protocol (PPP), SONET/SDH, frame relay, and even proprietary protocols. Each CP consists of a dedicated RISC core and dual SDPs: one for ingress and one for egress com- puting in each CP. The CPs can be assigned to physical interfaces that the network processor is called to support. They can be combined into aggregates that support input/output (I/O) bitstreams of higher bandwidth, or they can be assigned to other computational tasks internally as dedicated coprocessors. The SDPs handle all data encoding/decoding, framing, formatting, parsing, cyclic redundancy check (CRC)-based error checking, and data movement. As the SDPs can also control an external pro- grammable pin logic block, they enable systems designers to implement almost any layer 1 interface. This flexibility includes connecting with T/E carrier framers