ol, SRAM is fast and very expensive. DRAM is slower, but more difficult to design due to the periodic need to refresh the retained data. It is also much less expensive to buy. Engineers have traditionally thought about arranging these two families into a hierarchy of memories to maximize performance while optimizing the cost budget. One result of such ingenuous approaches was the caching structure of traditional computers. A small pool of very expensive and very fast SRAM memory operates next to the central pro- cessing unit (CPU) (often it is embedded right inside the CPU chip). This is where it retains a collec- tion of the most recent and most frequently used blocks of data. Chances are the CPU will need one of these memory blocks for its next operation. Therefore, it is convenient to have it in the cache as opposed to initiating a memory input/output (I/O) cycle to go off-chip to the memory bank (usually made with DRAM) to fetch it, which would stall the processor's frantic pace of execution. This is caused by the fact processors are much faster than memories. This principle has also been carried over to multiple sophisticated levels of caching with the intention to maximize the performance while min- imizing the cost. We will not expand on these techniques here because traditional IT-computing environment mem- ory hierarchies based on a cache approach do not work with network processors. Network processors need to search unpredictable and deep trees because both the spatial and the temporal locality of net- work traffic content data are radically different from traditional computer data. Therefore, designers are forced to use other means to solve storage and buffering problems. Memory measures of merit for the network-processing arena include the work done per pin, the random cycle time, the capacity, the cost, the power, and the space. DRAM Flavors SDRAM stands for synchronous DRAM. Originally, DRAMs had been controlled asynchronously. A processor would present an address to the DRAM, and it would activate 