products and tools enabling the wide-scale acceptance of the configurable VLIW (FLIX approach). It will be especially interesting to see how code compatibility can be preserved between customer-extended Tensilica legacy instruction sets and the new parallelized technology. ARC CORES ARC (www.arccores.com) is a British IP core technology company that offers a configurable, extendable, and synthesizable 32-bit RISC architecture based on a CPU platform. called ARCtangent TM. The heart of the ARCtangent technology is the A-5 32-bit RISC processor, which is based on a four-stage pipeline and implements the company's ARCompactTM orthogonal instruction set (meaning that all addressing modes and therefore all registers are accessible to all instructions). ARCompact combines a mixture of 16- and 32-bit instructions and intends to minimize instruction in the memory footprint. A core register file of thirty-two 32-bit registers can be doubled or extended with extra registers if desired. The company's core technology is a little less configurable than Tensilica's, and its development tools do not exhibit the same possibility of customized generation based on the user-implemented extensions.8 Nevertheless, the technology has been commercially accepted because of its simple and clear-cut approach and what appears to be extremely reasonable licensing terms. In order to take advantage of its technological configurability, ARC offers a GUI-based configu- ration tool that enables a user to decide all the features and characteristics of the CPU. The user could decide to do things such as creating and adding extra instructions for specialized repetitive operations, customizing the cache configuration, or reconfiguring the interrupt-handling priorities and vectoring mechanisms. The user could also decide to use a Harvard-bus configuration (separate and parallel- running instruction and data buses accessing different memory banks for program code and data respectively) as opposed to a von Neumann structure that has one common shared b