s has announced two members of the APP550 family: a 266 MHz version supporting 2 to 4 Gigabit Ethernet (GbE) or full-duplex 2.5 Gbps Packet over SONET (POS)/ATM processing capacity and a 133 MHz version supporting 1 to 2 GbE or full-duplex 622 Mbps POS/ATM processing capacity. The entire network-processing solution rotates around the capabilities of the FPP, which can be called to action by programming the FPP chip through a high-level language that Agere has devel- oped called Functional Programming Language (FPL). Through FPL code, the FPP can analyze classify patterns based on the bit content of every byte of the payload or the headers of packets and/or frames. Agere's patented search and pattern-matching technology enables the buildup of very large lists. The search time is also deterministically limited. You can search for any length of data pattern, and the search time is only limited by the pattern length, not by the number of entries in the search table. On top of these three fundamental chips, Agere has also introduced another member of the PayloadPlus family known as the Voice Packet Processor (VPP). This coprocessor chip is capable of ATM Adaptation Layer 2 (AAL2) segmentation and reassembly (SAR) and switching functions sup- porting up to 32,767 conversations. Figure 7.1 shows the block structure of the PayloadPlus architecture. It is based on a patented search technology called Pattern-Matching Optimization. According to Agere, this architecture enables the company's network processor to achieve a performance more than five times greater than network processors based on advanced reduced instruction set computer (RISC) cores. This per- formance attains the level of fixed-function application-specific integrated circuits (ASICs) while pro- viding the flexibility and programmability of RISC. The architecture achieves this by using less POS-PHY Fabric Physical Switch Interface Interface UTOPIA Fabric Controller 8-bit POS-PHY Configuration 8-bit POS-PHY PCI to Host CPU FIGURE 7.1 The block architecture an