 requirement is also dependent on the power margin neces- sary to cope with both gain variations in the mmWave transmitter chain as well as the digi- tal power control. The DAC dynamic range requirement can be calculated as = - Sp - LIF + CF + PH (dB), where Sp is the spurious emissions requirement, LIF is the IF filter attenuation, CF is the crest factor of the wanted signal, and PH is the required DAC power headroom. This equation applies to all modulation and coding schemes, thus if the power headroom is fixed, the dynamic range becomes dependent on only the crest factor. A baseband PLL is required to generate the local I/Q sampling clocks required for the I/Q ADC and DAC. Depending on the channel bandwidth, the sample clock frequency can range from 500 MHz to 3 GHz or higher. The phase noise of this baseband clock may have an impact on the overall system performance. To evaluate this effect, consider the single- sideband phase noise characteristics of an example commercial ADC clock PLL with a 40 MHz crystal reference, which achieves an rms phase noise of 1.57 degrees in the band- width ranging from 100 Hz to 4.5 GHz. This phase noise can be translated into an equivalent SNR value of 31.24 dB in the Nyquist band between + fs/2 using the following equation SNRAdB = 10log10 (180/) where fs is the sampling frequency. The required phase noise per- formance of the ADC clock PLL can be further estimated from an analysis of the receiver SNR at reference sensitivity for all modulation schemes and later defining the acceptable additional reduction in SNR that could be tolerated as a result of the additional phase noise contribution of the sampling clock. If the additional reduction of SNR is set to 0.1 dB, it can be shown that the corresponding rms phase noise of the PLL would be 2.08 degrees and the rms time jitter for a sample clock of 2.64 GHz would be 2.2 ps. Therefore, a reasonable jitter requirement for the baseband PLL should be less than 2 ps [23]. In order to evaluate the performance impact of high-frequency 