ere, a drop of 7 to more than 10 dB depending on whether DPD algorithms are applied. Second, the complexity of the DPD algorithm defines the level of improvement of the ACLR, with incrementally worse value. At some point, the PA simply cannot be corrected beyond its inherent capabili- ties. The question is whether (from a system point of view) it is worthwhile investing in com- plex DPD algorithms with maximum performance or live with a "good enough is good enough" system. As we discussed before, for all but indoor applications, the value of invest- ing in compute resources for advanced DPD algorithms is worth it with regards to DC power consumption metrics but the engineering effort or financial cost may be considered too high. Note the trade-off on spending DFE (compute) resources spending can become a tradeoff between CFR and DPD. CFR limits the PAPR of the transmitted signal and hence allows the Power Amplifier back-off to be reduced (order of magnitude 3-5 dB) at the cost of compute clock cycles spent on CFR implementation. DPD doesn't change the PAPR of the system but allows the Power Amplifier to continue to operate linearly at higher output powers, also at the cost of com- pute clock cycles. Typically, CFR gains are more modest (as can be seen in the chart above) but also lower effort in terms of compute resource requirements as compared to DPD gains. The required DPD feedback bandwidth is much wider than the OBW of the signal. There is no single mathematical equation that defines this bandwidth and it becomes part of the trade- off between performance, cost and implementation complexity. Typically, 3-5x OBW or enough bandwidth to cover one RF carrier above and below the target band (cover the Adjacent Carrier Leakage Ratio) are used. DPD feedback bandwidth is limited by the quality of components, like the antialiasing filter and ADC circuits, which degrade the linearization per- formance of the DPD system. The DPD ADC performance needs to be sufficient to support a system with 45 dB ACLR and hence needs 