performance. Figures 5.40 and 5.41 individuate a threshold technology node with a dimension of the gate on the order of 22 nm, where the parasitic resistance and capacitance will become almost equal to the intrinsic one. Before that point, the strategy to decrease the dimensions is effective in increasing the CMOS switching speed; beyond that point, it seems to become less and less effective up to a point at which the component will become slower while shrinking. This evolution is individuated also in Figure 5.42, where the inverse of the response time is plotted versus the technology node. Relative switching speed No parastic With parasitic MOS gate length (nm) FIGURE 5.42 Impact of parasitic capacitance and resistance on CMOS commutation speed. (After Parthasarathy, S.E. and Thompson, S., Mater. Today, 9(8), 20, 2006.) Technology for Telecommunications: Integrated Optics and Microelectronics TABLE 5.9 Characteristic Speed and Power Consumption of 65nm Gate CMOS Elements Optimized for Different Applications Total Power Consumption TPD (ns) at Maximum Speed (uW) Standard gate High speed Advanced Low voltage To manage the increase in parasitic Rp and Cp a number of solutions are under consid- eration, among them using novel silicides different from Si3N4 and reduced polysilicon height [10] that will bring to a vertical the scaling of the structure. Another option is that along critical paths of a circuit, the devices are not placed as close as possible to the nearby devices in the wafer. In this case there is some area pen- alty, but there may be a path for reducing the device degradation caused by the nominal device pitch. Concluding the section on CMOS switching speed, Table 5.9 provides figures for last-generation CMOS gates in terms of characteristic propagation time [52,53]. This is expressed through the propagation delay, which is the time for an input instantaneous switch to manifest at the gate output. Considering the digital circuits speed, last generation CMOS are currently used to design processors and 