gresses is absolutely astounding. It shows that the functional requirements of evolving networking devices will simply not be able to be serviced by the expected evolution of CPU processors, where the progress of semiconductor capabilities has been more or less accurately predicted and charted for the last 20 years. Another unrelated factor that contributes dramatically to the exhaustion of the computational capa- bilities of off-the-shelf standard CPUs in a networking environment is that we are witnessing a rapid move of the processing function upwards in the protocol stacks. Barely six to seven years ago, net- working still used layer 2 processing. With the evolution of Internet Protocol (IP) and Multiprotocol Label Switching (MPLS), network computing started to involve layer 3 calculations. The recent trend has now climbed even higher by seeking, capturing, and exploiting information from the transport to the application layers (layers 4 through 7). In order to accomplish such a feat, network devices must be able to look deep inside packets to scan, parse, recognize, and extract features that reveal infor- mation from each packet about specific levels of QoS, service levels the user contractually has bought, or load balancing based on uniform resource locators (URLs). This type of intensive and intelligent packet processing implies that more bits per packet need to be examined and handled than before. It is estimated that a single standard CPU processor chip is incapable of performing deep-packet pro- cessing all the way to the application layer in real time faster than a couple of hundred megabits per second. Beyond the shortcoming of off-the-shelf CPUs when it comes to network processing, one should also not underestimate the fact that processors that perform packet processing usually suffer from a Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the