e of its technology platform, the company has created an impressive list of licensees and varied applica- tions ranging from workstations to network routers and from digital cameras to laser printers. It has also helped create an entire industry of third-party software development tools, such as assemblers, compilers, debuggers, and simulators, that facilitate programming and enable applications to be smoothly ported from one system to another. MIPS offers embedded, scalable 32- and 64-bit CPU platforms that are presented in the market as a base architecture or as a CPU core. Historically, MIPS CPUs have always been designed to handle general-purpose computing. As a result, they were never intended to become part of the unusual com- putational environment that ultrafast packet processing has become. This pushed the adoption of MIPS IP cores predominantly in control plane applications or in applications that were meant to be part of a supervisory computer system. These are applications where the classical development tools, methodologies, and programming models ensured that the MIPS approach would yield results. It is not surprising that MIPS IP cores were deficient when it came down to manipulating gigantic quan- tities of packets that needed sophisticated processing in real time and at wire speeds of several tens of gigabits per second. In addition to the lack of powerful input/output (I/O) bus and speed capabilities, the following are the two most important reasons for this deficiency: The original MIPS CPU core instruction set did not offer provisions for such packet-processing functionality such as one-cycle bit-field extraction, swapping, insertion, modification, rotation, and SO on. As a result, implementing them on a MIPS core meant that entire programs would have to be written. This is a painful experience in RISC assembly when referring to having to fine-tune the CPU's multistage pipeline-something that C compilers cannot do that well. These programs would have to be recalled numerous times from the main