K PROCESSORS: JUSTIFICATION NETWORK PROCESSORS: JUSTIFICATION 33 The PHY interface chip is the component at the edge of the networking device closest to the phys- ical medium and the bidirectional handling of traffic. PHY chips are designed for different transmis- sion media. For example, 100Base-T networks, Gigabit Ethernet, and Asymmetric Digital Subscriber Line (ADSL) are some types of media that use PHY chips. Companies that offer PHY chips include Agere, Alcatel, AMCC, Broadcom, Conexant, Fujitsu, and IBM. Switch Fabric The networking device is physically structured in several ways. The most straightforward and mod- ular way is to use either a bus or a backplane into which adapter modules or line cards are inserted. The switch fabric is a functional module that reads packets at an input (also known as the ingress point) and routes them to an appropriate output (also known as the egress point). The current switch fabric function is usually offered in a highly integrated standard off-the-shelf chip set, as proposed several vendors, such as Agere, IBM, Vitesse, and Zetacom. Its speed is the most critical factor for defining the switching capacity of a network device. As an alternative, the designer/manufacturer the network device sometimes proposes an in-house custom-designed very large scale integration (VLSI) chip that implements a tailor-made switch fabric implementation. Packet Processing The overall packet-processing set of operations is positioned between the PHY interface and the switch fabric. The industry usually categorizes these operations into two operation groups or two pro- cessing paths: a fast packet-processing path and a slow packet-processing path. A fast path refers to a data path that handles all operations that are executed in real time directly on a packet. These include, but are not limited to, the five fundamental operations of framing/parsing, classification, modifica- tion, compression/encryption, and queuing. A slow path refers to the required operations that are exe- cuted independen