.82) Furthermore, b = (N + 1)/N and K2 evaluates to K2=29PB (2.83) Finally, then substituting (2.82) and (2.83) in (2.79) gives the desired result for the mean time to loss-of-lock (normalized by the loop bandwidth) of the DLL, namely, exp{pL[D(y)-D(x)]}dydx (2.84) Comparing (2.15) with (2.42), it is easily seen that (2.84) also applies to a first-order TDL if PL is replaced by (2.85) Figure 2.19 illustrates 10 log10(BLT) as computed from (2.84) versus OL = 1/VPL for N = 2, 4, and 8. Clearly, the mean time to lose lock decreases with increasing N in agreement with our previous observation con- cerning the width of the linear tracking region. The Double Dither Loop Figure 2.19. Mean time to loss-of-lock performance of delay-locked loop. 2.5 THE DOUBLE DITHER LOOP The double dither loop (DDL) [8] is a PN code tracking loop that combines the desirable features of the DLL and TDL, i.e., the effects of detector imbalance are eliminated at no significant cost in noise performance. To understand better how this is accomplished, it is convenient to first redraw Figure 2.9 in its conceptually equivalent form illustrated in Figure 2.20. Here a single pair of time-synchronous dither switches is used to accomplish the alternation between early and late codes at the input phase detector and the post-detection multiplication by the square wave q(t). The salient feature of the DDL is that it employs two sets of time synchronous dither switches that n;(f) BAND-PASS DETECTOR S (1) SQUARE-LAW ENVELOPE DETECTOR EARLY PN CODE VOLTAGE- - GENERATOR CONTROLLED FILTER CLOCK F (s) DITHER GENERATOR Figure 2.20. A conceptually equivalent version of Figure 2.9. The Product of Sum and Difference DLL time share two square-law envelope detectors alternately between the two correlators (see Figure 2.21). From an implementation point of view, the two switched post-multipliers and summer can be replaced by a single switched differencer as in Figure 2.22. An equivalent loop model for Figure 2.21, which is valid for analysis pur- poses, is (analogo