ults are still not fully understood, the authors presented a new model for the critical gate field to cause SEGR in terms of the atomic number of the incident ion rather than its LET. Further study is necessary in this field to develop physical explanations for this result. 4.2.3 Single-Event Gate Rupture in Thin Gate Oxides SEGR effects have been studied for some time in power devices, but a topic that has recently received a considerable amount interest is SEGR in logic and memory ICs. As gate oxide thicknesses decrease, SEGR could become a problem in ICs because they will likely be operated at somewhat higher electric fields. Hard errors have occasionally been observed during heavy ion tests of SRAMs, and have been attributed to local total ionizing dose deposition ("microdose") [201-203]. In 1994, Swift et al. noted the occurrence of a new kind of hard error in 4 Mbit DRAMs that was clearly inconsistent with the microdose phenomenon [204]. For example, these errors did not disappear with high-temperature annealing and showed different retention-time characteristics than microdose hard errors. Other characteristics of the mechanism seemed II-38 Niobium lon VGS @ SEGR Failure LET Value lon Energy @ Gate Oxide [MeV] Figure 4.4. Energy dependence of SEGR failure threshold in vertical power MOSFETs for niobium ions [196]. The failure threshold is roughly constant even though the ion LET varies considerably over the energy range. consistent with SEGR failures, but the mechanism was not conclusively identified. Of particular concern was the fact that 4 Mbit DRAMs from the same manufacturer that had undergone a die shrink (0.8 um to 0.6 um) were even more sensitive to SEGR, showing hard errors at lower LET and with a much greater cross-section. The electric fields at which ruptures were observed were less than 3 MV/cm. These results led Johnston et al. to conclude that SEGR could become a major failure mechanism for scaled microelectronics in space [205]. Below a feature size of about 0.25 um, it was predicted that t