wer-hungry content-addressable memory (CAM) devices. If the arrows of the data flow shown in Figure 7.1 are inverted, the egress path can be determined; therefore, it explains how the same chipset can operate in a full-duplex line card as in OC-48c. If pack- ets on the egress side require further classification, a new FPP needs to be inserted into the egress path. If packets need queuing at the egress path, another RSP chip will be needed. Finally, if separate sta- tistics gathering is required at the egress path, a separate ASI chip is needed. In the worst case, the configuration of Figure 7.1 should also be replicated on the egress path, as well. For systems that are based on the use of the VPP, the VPP is inserted in the structure shown in Figure 7.1 between the FPP and the RSP. It connects both upstream and downstream with 32-bit POS- PL3 interfaces. It can be configured by the ASI over the CBI bus, and it supports a 64-bit SSRAM interface for maintaining state and statistics. The VPP chip cannot handle speeds of above OC-40, (broken down as a maximum of OC-12 of AAL cells and a maximum of OC-12 of CPS packets). As a result, we do not intend to cover it in more detail here. Interested readers can refer to technical doc- umentation from the Agere web site for more details on the VPP. In terms of physical presence and power consumption, both the FPP and RSP are available in ball grid array (BGA) packages that have 655 pins each. The ASI comes in a 448-pin BGA. The maxi- mum total consumption of the set of three chips is 9 watts when it operates at 13 MHz. The FPP is a pipelined, multithreaded processor that can simultaneously analyze and classify up to 64 protocol data units (PDUs). Each incoming PDU is assigned its own processing thread, which is called a context. The context is essentially a processing path that keeps track of all the blocks of a PDU, the number of the input port through which the PDU arrived, the data offset for the PDU, the last-block information, any potential program variables that are as