eometrically on the silicon die and financially) that enables the designers to embed more (and previously unthinkable) functionality and therefore improve the integration and value of the new product. However, the mere knowledge that the underlying architecture can be easily expanded is a tremen- dous advantage in the designer's mind. The designer is now confronted with a certain peace of mind that is rare in this industry. This is why Cognigine and industry analysts are SO excited about the prospects of this technology in the OC-768 environment and beyond. The optimization of the memory bandwidth in terms of balancing the memory read/write load and the cost and performance of memory access by intelligently managing that bandwidth in a hierarchi- cal and distributed fashion is a very important task. Cognigine engineers have clearly done their home- work in this regard. To start with, the NPU chip provides a first memory level of shared 2Mb of internal SRAM. Most importantly, however, several memory controllers are integrated inside the chip. More specif- ically, four 64-bit DDR SDRAM controllers operate at 200 MHz for packet buffering. This means that the capability of 512MB of space for packet buffers is supported. A configurable SSRAM controller (2X64 bit and 4X16/2X32/1X64 bit) running under a 200 MHz clock provides access to classifica- tion memory and coprocessor interfacing. The NPU chip's memory-controller landscape includes a Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES 148 NETWORK PROCESSORS RCU: Reconfigurable Communications Unit RSF: RCU Switch Fabric Crosspoint Switch Fully Pipelined Framer Interface Fabric Interface External Memory Expansion Bus RSF Connector Distributed Arbitration Transaction Scheduling Scalability dimension of the Hardware Architecture FIGURE 9.6 The scalability of the Cognigine NPU