s discovery seems to justify the company's approach to solving the network-processing problem despite the fact that it obviously runs against the intuitive impression that this brute-force approach of throwing vast amounts of MIPS on the computational task at hand causes a waste of computational bandwidth. ClearSpeed claims that their deterministic software approach has particular benefits for network- processing software. If the worst-case performance guarantees are to be met, each path through "branchy" code must be proven to take no more cycles than the number available. Also, systemwide instruction fetch bandwidth must be guaranteed under all circumstances; otherwise, unnecessary packet drops may occur. In systems that have many units that can fetch instructions and that have branchy software following different paths on different cores, systemwide performance proof is next to impossible. A program on ClearSpeed's MTAP cores is essentially straightline, running the worst-case code on each core. Since every PE will now run that same code, instruction fetch band- width and instruction store are both massively reduced by more than an order of magnitude. This results in significant savings in power and area. Also, straightline code has predictable, determinis- tic performance, which provides obvious benefits to the user. Finally, ClearSpeed also claims that software can easily be written in a manner that minimizes the cost of running multiple code paths through every PE. For example, if code to process IPv4 and IPv6 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES 169 packets is written separately, each code path takes about the same number of cycles to execute. Running them bo