ne (TLE), which was designed for situations where lookup capabilities are needed for more than 300 million lookups per second. In a reference design, by embedding 24 lookup engines in the TLE and multiple banks of compiled SRAMs from third parties, ClearSpeed managed to attain an impressive performance of 350 million lookups per second while clocking at 400 MHz. The TLE (which is further discussed in Chapter 12, "Search Engines") can be configured to work with internal SRAM or DRAM depending on the capabilities of the targeted semiconductor process. At the same time, support for external DDR SRAM or DRAM enables the creation of systems that match performance, table size, and key length requirements with actual budgeted design costs. As the Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES design has been largely optimized for tree walking, multiple parallel level compressed (LC) trie search engines operating simultaneously provide results out of order because this increases the overall effi- ciency of the TLE. ClearSpeed clarifies that its MTAP architecture will restore the order of operations automatically without any special buffering. The TLE can support tables with over 2 million entries at application wire speeds requiring 350 million lookups per second, and can use variable size keys from 32 to over 128 bits. It also has significant advantages as opposed to the traditional use of external CAM. A global semaphore unit, which is usually unique in one SOC design, coordinates synchroniza- tion and communication between the multiple cores. Any major core has its own collection of private semaphores to which only it has access. The MTAPs have these semaphores to coordinate chore