harge transfer rate for the traps to efficiently trap signal charge. Further details of radiation induced CTE IV-80 degradation are beyond the scope of this course, but are described in detail in many papers, including [Mohs74, Bang91, Dale93, Jane95, Hopk96]. Direction of charge transfer oxide p-epi layer p-substrate buried channel n-channel stops Figure 14a Illustration of parallel charge transfer down a row of MOS capacitors. A 3 phase CCD is pictured, in which each pixel is composed of 3 electrodes for charge transfer. The signal charge travels in the buried channel and is restricted to a single row by implanted channel stops. Channel stops Parallel Transfers in the Imaging Region Output Serial Readout Register V1V2V3 Figure 14b Schematic of a top view of a CCD array showing both the parallel and serial readouts. CCD evaluations include measurements of both the parallel and serial CTE. IV-81 Unfortunately, efforts to harden CCDs to displacement damage have not been nearly as successful as TID hardening. However, displacement damage effects can be ameliorated using several techniques. CTE loss can be somewhat reduced by substantial cooling (often to about -80 °C), to mitigate the trapping effects of the E-center (and also minimize dark current). As illustrated in figure 15, background charge can dramatically impact the CTE loss by filling the traps SO that they do not interact with the signal charge packet. The magnitude of the improvement depends on the signal size, and usually (though not always [Robb92]) comes at the price of additional noise. Another CTE hardening technique employs an additional phosphorus implant to confine the signal charge to a smaller volume (referred to as a notch or minichannel) SO that fewer traps are encountered as the signal charge is read out. Notches may be useful for low signal level applications and some CCD operating conditions, but the efficacy of a notch may vary considerably between manufacturers (or even lots from a single source). Further information concerning mitigatio