unctionality in a tightly integrated environment, which minimizes chip count. As a result, printed circuit board (PCB) real estate, power consumption, and cost are also minimized while offering 32 Gbps of switching capacity and a packet-processing speed that is rated at 31.25 Mpps. Its programming model provides direct access to the computational resources of the chip by enabling an application to be mapped onto the underlying engines that compose the architecture. More specifically, the model contains a multiphase dynamic classifier, a flexible transformation editor, a wire-speed capable segmentation and reassembly (SAR) unit (cells/packets), a robust queue manager, and, last but not least, a sophisticated traffic manager. The chip provides native support for ATM, IPv4, Packet over SONET (POS), PPP, Ethernet, frame relay, MPLS, DiffServ, and IPv6. It can therefore easily be envisioned inside MPLS label edge router (LER) and label-switched router (LSR) switch or router systems. In fact, its AnyMappingTM pro- grammable function allows the flexible internetworking mapping of any protocol to any protocol. The line-speed forwarding and bridging design arguably bridges the packet-processing gap between the legacy circuit-switched paradigm and connectionless world of IP. For example, the company's com- prehensive MPLS support can simultaneously map multiple IPv4/6 microflows and ATM virtual chan- nels (VCs) onto MPLS traffic streams at guaranteed data rates of 10 Gbps. On top of all this, a whole series of programmable modification and editing functions is available, which can be engaged by the user to handle both standard and proprietary protocols. For instance, the Montego can seamlessly handle mapping, stripping, encapsulation, cyclic redundancy check (CRC), Time to Live (TTL), and even checksum operations. We mentioned Montego's robust multiphase dynamic classifier. By directly interfacing to state- of-the-art TCAM lookup memories and in-band deep packet preclassifiers, this classification engine, which supports fl