-MeV alpha particle. Indeed, there is historical evidence supporting this view as data from more than 10 years of microprocessor evolution show a constant upset threshold just above the threshold for alpha particle upset. However, it is also known that many manufacturers have specific soft-error driven design rules for placement of devices relative to on-chip solder bumps and/or use hardened circuit designs for I/O circuitry that must be in the vicinity of such on-chip alpha sources [299,320]. This clearly implies that many devices being manufactured are in fact already below the alpha-particle threshold for upset. Many of the techniques traditionally used in the radiation effects community to SEU-harden devices are of such a nature that they would never be adopted by commercial manufacturers. They tend to consume more power, reduce manufacturability, and severely impact IC performance. Commercial DRAMs have generally exhibited a fairly constant SEU performance because DRAM manufacturers have intentionally maintained the unit cell capacitance through the use of clever modifications to the storage cell [321]. The nodal capacitance for SRAMs, however, has been steadily shrinking [316]. To counteract increased terrestrial soft error rates, manufacturers may find it necessary to explicitly add capacitance to high-density SRAMs [158,316]. Lage has predicted that this will be necessary for the 4 Mbit generation of SRAMs and beyond [316]. Design-hardened circuits may be useful for critical paths or circuitry, but because of area penalties will not be adopted on a large scale [320]. The use of error-correcting memory architectures is already becoming more common again and this trend will likely continue. Mitigating soft errors in high-speed digital logic circuits will be especially challenging. Fault- Device Types 1 NMOS 2 CMOS bulk 3 CMOS/SOS 4 GaAs 5- CMOS/SOI 6 ECL Corrected for alpha upset 0.023L hardening 0.001 Feature Size (L, um) Figure 6.9. Technology trend for critical charge to upset as a function of feature si