opment tools in conjunction with evaluation and hardware development platforms from compilers all the way to models based on Hardware Description Language (HDL) for the FOCUS interconnect in order to facilitate and accelerate the overall system development. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES 154 NETWORK PROCESSORS WINTEGRA Although we have not focused on the lower part of the performance spectrum where devices need access to 622 Mbps links or where at the worst case they must provide connectivity to 1 Gbps links, we will slightly deviate and mention a company that is setting some serious precedents in that arena. No one should be surprised if we start seeing the same trend in network processors that address the higher-speed links. Wintegra (www.wintegra.com) is an interesting startup in this field. It is certainly not a coincidence that several major players in the industry such as Motorola and Marvell have participated in its fund- ing. The company has introduced WinPathTM, a family of single-chip solutions in the access network arena, based on a technology that is equally at ease with packetized traffic as well as with frames and voice pulse code modulation (PCM)/TDM channels. Wintegra has already announced important agreements and project breakthroughs in areas such as DSL, wireless base stations, or voice over net- work with major partners such as Texas Instruments in the digital signal processing (DSP) arena with whom they have created a full-fledged reference design. Rightfully so, it takes pride in multiple com- munication protocols that are implemented on board its chips. The respinning of silicon is not required by these protocols as they are implemented in RAM memory. The evolving list includes ATM AAL0, AAL2, and AAL5 SARing; ATM cell switching and AAL2 CPS switching; ATM Circuit Emulation Serv