ocessors [103,104]. These digital logic circuits are very difficult to test for SEU due to their complexity, especially for advanced high-speed technologies [105]. Errors in logic circuits are also very sensitive to critical timing windows and logic paths, and may never propagate to the output pins [106-109]. As circuit operating speeds continue to increase, the probability of a momentary glitch in a line voltage from a single-event transient (SET) propagating through a logic path to become an observable error rises. Given the ever-growing demand for higher functionality, faster speeds, and greater integration in tomorrow's space systems, SEU testing increasingly complex logic ICs will be one of the biggest challenges for the future. Single-Event Multiple-Bit Upset Single-event multiple-bit upsets (MBUs) occur when a single particle strike causes more than one error in an IC. For example, diffusion of charge to closely-spaced junctions can upset more than one bit in both SRAM and DRAM cells [60,110]. For a particle striking an IC at a grazing angle of incidence, the charge track may intersect several sensitive regions and cause multiple upsets [111]. The effects of MBU are typically alleviated by a combination of error-correcting codes that work on a word-by-word basis (see Section 3.8.2) and layout rules that prevent physically-adjacent bits from belonging to the same word of memory. Still, single-word multiple- bit upsets (SMUs) can occur and pose a substantial threat to system integrity [112]. MBUs have been observed in on-orbit spacecraft data [113,114]. II-23 Multiple-bit upset in DRAMs has been studied fairly extensively using experiments and 2D cylindrically-symmetric simulations [110,115,116]. Figure 3.13 shows an example error map obtained from heavy-ion exposure of a 256Kb DRAM. MBU error locations are shown as solid capacitor areas, surrounded by the outlines of adjacent capacitors where no errors were observed [110]. Simulations showed that for normal-incidence strikes the charge-collection mechanism 