 Read for slot context Write and Read Assuming an FR1/ <6 GHz small cell targeting 64 Active Users and 2.5 Gbps throughput with 500B frame size (2.5 Gbps/500B = 625 K packets/second) and 2000 slots/second, this equates to 625 K X 6 X 8 cache lines frame payload 625 K X 6 X 1 cache line frame descriptor 2 K X 64 X 2 cache lines UE context 2 K 2 X 10 cache lines slot context The aggregate is approximately 34 M cache lines or 17.5 Gbps of required DDR through- put, which is equivalent to approximately 35 Gbps raw throughput assuming 50% maximum Chapter 3 Hardware system dimensioning DDR utilization. A 2.4GTPS, 72-bit DDR controller provides 153.6 Gbps, leaving (more than) enough headroom for this application. Above analysis is highly theoretical and optimistic in that it assumes very few overheads or software inefficiencies. For that reason, typical implementations add significant safety margin (2x) on top of this number. At the same time, above example doesn't consider L3 cache offload of DDR bandwidth which typically reduces the DDR load by up to half, when present and not implemented as write-through cache. HARQ memory and bandwidth dimensioning One of the largest bandwidth consumers in the DU is the Physical Layer HARQ operation and its associated context store/re-store operation. Transport blocks, code blocks, and HARQ 3GPP defines a MAC PDU as the unit that is transferred between MAC and Physical Layers, or transmitted/received by the MAC layer. In the Physical Layer, the MAC PDU is trans- formed to a TB by: Segmenting the TB into a set of Code Blocks (CB) that are smaller (and bounded) in size Adding a cyclic redundancy check (CRC) to each CB Adding a CRC across all CBs to have a TB level CRC as shown below in Fig. 3-12. HARQ operation between base station (gNB) and client (UE) includes HARQ Ack/Nack operation which is acknowledgment of (in)correct reception of the TB by the other side. In addition, CB level CRC pass/fail information is transmitted, at groups of multiple CBs (Code Block Groups). This is a dif