 a working product that meets the customer requirements within budget and on time carried a massive penalty when judged against the ever- present need to excel in terms of time to market. Established and startup companies started coming up with off-the-shelf switch fabric chips and chipsets that would offer high performance and elimi- nate the risk of failure. As a result, a trend appeared and network equipment companies started mov- ing from expensive, risky, and cumbersome do-it-yourself switch fabric ASIC designs to off-the-shelf commercial chipsets. With the arrival of these high-performance commercial off-the-shelf switch fabrics, the predomi- nant remaining problems include deciding where buffers must be placed in the architecture, how to schedule access to these buffers, and how to manage the switching bandwidth more efficiently. Unlike the fabric architects, users of these fabrics may not have to worry about them as they can pretty much choose the corresponding switch fabric architecture that matches their system requirements. BACKPLANE DESCRIPTION Figure 14.5 shows the typically modular structure of a modern MSR. Line cards for the various sup- ported network types are connected to a switch fabric card (or cards) through a set of high-speed serial (HSS) links. A supervising/monitoring control processor is also provided. This processor sometimes appears on the switch fabric card or as a separate control processor card from where clock signals are distributed, ensuring the synchronization of operations, multiple clock domains, and SO on. The typical line card can be conceived in three cascaded stages. First, regardless of what the medium or physical (PHY) layer is (such as Ethernet, Gigabit Ethernet, SONET, and SO on), the net- work side contains the corresponding PHY chip(s) implementing the PHY interface layer, the Medium Access Control (MAC) chip(s), and the framing functions. The network processor is right behind this layer of logic and takes care of the packet/frame processing functions that we descri