ypes of advanced routers. By replacing the multiple switch fabrics with one common underlying switching architec- ture, these companies purport to offer native support for multiservice networks regardless of whether the traffic is TDM voice, frame relay, IP packets, or ATM cells. THE EVOLUTION OF THE MULTISERVICE ROUTER/SWITCH The packet switch/router originally started as a simple bus-based computer with multiple input/out- put (I/O) adapters (also known as line cards) providing the correct physical and data link interface to the various networks that the packet switch connected. The main CPU either polled the input line cards periodically for any input activity update or it was interrupted by a line card upon the arrival packet, in which case the line card would buffer-deposit the incoming packet into the switch's main memory for subsequent processing by the main CPU of the switch. The switch/router CPU would read the packet's destination and would consult the routing table in order to determine to which output buffer this packet should be forwarded. This was the same CPU that arbitrated any access to output lines at all times. Most low-end packet routers and even simple Ethernet bridges were implemented according to this model. The shortcomings of this approach were the lung capacity of the main CPU, the extent and performance of the main memory, and the performance of the I/O bus or the line cards themselves. Different implementation technologies always suffer from bottlenecks that may be caused by differ- ent architectural components. In other words, the designer can use a fast CPU to solve the perform- ance problem, but if the I/O bus is not fast, a problem still arises. Subsequent I/O bus designs brought faster transfer speeds than were previously available. This allowed the faster CPU processors to be utilized more efficiently, but given the ever-increasing demand for traffic, a designer then had to struggle with the performance limits of the line cards themselves, SO some sort of decentralized intelligen