y the start of a new, nested level of predication. A PE's state will only be changed by the instructions in that basic block if all the conditions up to and including the most recent are true. Hence, by the time the endif is left, each PE has either written src1 or src2 to max, but not both. So this is just a straightline piece of code. It will always take eight cycles regardless of the conditions. This technique is, of course, not new. It is quite common in several CPUs these days. Since branches are one of the biggest performance bottlenecks in modern microprocessors, many include predicated execution just like this for turning small branches into straightline code, which can then executed in their wide, fast, multi-issue pipelines much more efficiently. ARM has had this for some time. It is also available in STMicro/Hitachi's SH5. The small difference here is that they have a stack of such enable bits and have multiple PEs using their different enable states to produce the effect of control flow but without the branches. Incidentally, this could easily be microcoded into just one instruction-for example, max, which saves code space (4 bytes instead of 20). Also, some details of the architecture enable the other- wise to be performed at the same time as the first mov and the endif to be performed at the same time as the second mov. However, this can only occur when it is written in microcode. This means the microcode max will only take six cycles instead of eight. However, not everyone can or wants to code in microcode. Compared to a small RISC core, a PE occupies on silicon about one-tenth of the area, offers about one-third of the computational horsepower of a RISC CPU, and consumes less than one-tenth of the Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORE