roducts SO far. The first is called the WIN777. Since it embeds a 200 MHz 64-bit MIPS core CPU along with the rest of its packet-processing hardware, it can handle both control and data path functionality. The second product is called the WIN707. By mere fact that it does not contain an embedded CPU core that could function as a control processor, it is meant to operate only in the fast data path, leaving all control path processing work to an exter- nal processor such as a PowerPC 750, which offers full bus compatibility. One of the interesting abilities of the WinPath is the device's ability to balance dynamically mul- tiple 200 MHz embedded processors with 200 MHz memory subsystems, thereby creating a very pre- dictable performance environment that could otherwise be matched only by custom ASIC designs. This means that if an application requires more entries in the routing table than another, or if it needs access to more virtual channels than another, no degradation of performance will occur. Downloaded from Digital Engineering Library McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES OTHER NPU ARCHITECTURES Last but not least, Wintegra takes pride in the fact that not one line of assembly code has been writ- ten for its chip. It touts its C compiler and integrated SDE as a key factor in accelerating the customer's time to market. XELERATED PACKET DEVICES While most vendors were struggling to stabilize their network-processing platform at OC-48 levels, to verify whether it is feasible to scale what they have at higher speeds, or to prove the actual scala- bility of their architectures to full duplex OC-192, some vendors were entertaining ambitions higher-speed products. Others have presumably moved forward with the development of actual and concrete product plans. One of the major surprises in this industry was the sudden announcement in the summer of 2002 from