 is readily appreciated that, instead of directly computing s(t), we can equally well compute O(t) and use the signal model (4.13) to retrieve s(t) afterwards. This is one of the key ideas underlying the construction of PLL small-signal models. Phase-modulated signals occur at three positions in the PLL architecture depicted in Fig. 4.2. There is the input signal Xin(t), the oscillation Xvcol (t) at the output of the VCO and the oscillation X1/N(t) at the output of the frequency divider. Typically, the input signal is deliberatly generated to fit the phase-modulated signal model (4.13). In order for the other two signals to fit (4.13), we need to assume that the PLL as a whole settles much, i.e. an order of magnitude, slower than the free-running (frequency- divided) VCO. This condition is mostly satisfied. If not, the poles induced by the settling behavior of the (frequency-divided) VCO tend to jeopardize the PLL's stability. To describe the phase-modulated signals mentioned above, we first need to determine the reference signals with respect to which their phases will be defined. For the input signal, we set Xin(t)=Sin(1+0in(t)) (4.14) Here, Sin(t) is the periodic reference with respect to which the input phase Oin(t) is defined. Typically, it is a sinusoid or a square wave. Selecting the references Svco(t) and S1/N(t) that are used to measure the phase changes of the VCO's output and of the output of the frequency divider is a little bit more complicated. One possible choice are the PLL's steady-state waveforms that occur when the (unmodulated) signal Sin(t) is applied to the input. The advantage of such a choice lies in some nice structural properties characterizing the PLL's input-output HTM. The disadvantage lies in the fact that it complicates modeling the VCO behavior. A more common choice for Svco(t) (S1/N(t)) involves the steady-state output of the VCO (frequency divider) with the VCO input being driven by a control voltage with constant value. This value is hereby chosen to equal the DC component of th