dose exposure to 10 Mrad [Babc-95]. For this type of device, the cause of the improvement resides in the oxide/nitride spacer and a strong doping level under the surface of the base region. 9. LEAKAGE CURRENTS: VISIBLE AND HIDDEN TRANSISTORS Parasitic transistors exist in all technology processes (Bipolar or CMOS). Trapped charges can turn-on these parasitic devices, causing leakage paths and inversion or accumulation channels. These channels act as MOS transistors and connect active transistors with each other or with supply lines, causing leakage currents. These leakage currents can cause the device to malfunction or simply degrade, with consequences on the system performance. In fig. 70, let us first describe the simple case of a CMOS with LOCOS. III-83 PECVO Nitride Final Passivation AL- 1.5% Si METAL2 AL - 1.5% Si METAL 1 Field Oxide P-well N<100> -10 a -cm N<100> 0.008-0.025 52-cm TL/F/11651-1 FIGURE 1. Cross Section of FACT JAN Product Figure 70. Cross section of an actual CMOS technology (FACT1 TM JAN of NSC [Mahe-94]. The figure 71 depicts very classical location of leakage currents in this kind of planar process. VISIBLE and HIDDEN MOS TRANSISTORS PRINCIPAL PRINCIPAL MOS TRANSISTORS PRINCIPAL PARASITICS BIPOLAR PARASITICS DIODE DEPOSITED INSULATOR CMOS TECHNOLOGY BIPOLAR TECHNOLOGY Figure 71. Some MOS parasitic transistors in bulk silicon structures Basically a 2D view (fig. 72) helps to differentiate between Edge-Field Oxides (E-FOX) and the two main types of Planar-Field Oxides (P-FOX). This essential topological difference helps to define a modeling strategy. Edge transistors share their gate with the main transistor, wgereas planar Field-Oxide transistors occur when a supply or bit line is deposited over a P-type region comprising two N-type zones (drain, N-well contact, guard-band, etc). In any case, an electron leakage channel occurs when the voltage applied on this parasitic gate approaches or passes over the threshold voltage of this parasitic transistor. III-84 Planar FOX Planar FOX Planar FOX 