ycles/second or roughly 1 X 2 GHz core/100 MHz carrier. Topic 3 is implemented like any other DSP algorithm, using Single Instruction Multiple Data (SIMD) or similar operations. We estimate the overall CPU loading as done typically in DSP algorithms by the number of operations-as we are doing next for Physical Layer com- plexity analysis. Each sample (say, 9 bit decompression) requires: an overhead of about 20 clocks/RE to extract the exponent value or ~ 1.7 clocks/sample with 12 samples in 1 RE load operations to load the compressed vector into a register assuming a 128-bit SIMD engine, assume ~ 7 I + Q samples/operation or 0.14 clocks/ IQ sample and an additional ~ I + Q samples/operation or 0.14 clocks/IQ sample to load an offset value of the compressed as we need for combining two shift operations per I or Q value to align the 2 components of the 9-bit element assuming a 128-bit SIMD engine and operation on 8-bit values (16 operations/clock), 0.25 clocks/IQ sample an OR/XOR operation per I or Q value to combine the two components assuming a 128-bit SIMD engine and operation on 16-bit values (8 operations/clock), 0.25 clocks/IQ sample an expansion operator per I or Q value to place the combined 9-bit value into a 16-bit register assuming a 128-bit SIMD engine and operation on 16-bit values (8 operations/clock), 0.25 clocks/IQ sample a multiply (or shift) operation per I or Q value to apply the exponential assuming a 128-bit SIMD engine and operation on 16-bit values (8 operations/clock), 0.25 clocks/IQ sample a store operation to store the resulting 16-bit sample in memory assuming a 128-bit SIMD engine and operation on 16-bit values (8 operations/clock), 0.25 clocks/IQ sample Aggregate performance is added as ~ 3 clocks/sample in theory of (assuming 50% utiliza- tion of the vector unit for intrinsics based code) ~6 clocks/sample in practice. Given 3276 X 14 symbols (peak) X 1 (IQ sample) X 2000 slot/second = 92MSPS, we count for 550 MHz/layer or (roughly) 1 core/4 layers. From the aggregate of topics 1/2 and 