 serial links simultaneously and in perfect syn- chronization among slices. The attached switch fabric devices exchange control messages over a 4-bit ring bus that helps them remain coordinated. The master chip manages an in-band back-pressure mechanism using Xon/Xoff signals or credits. The credit system works in AMCC's nP family in the following way: Every time a cell in the fabric leaves its queue for an output port, the nPX5800 sends a credit, which the traffic man- ager nPX5700 uses as a grant to send a new cell to the fabric. The traffic manager stops sending new cells when the credit balance available becomes zero. Another interesting AMCC switch fabric that we must mention is the nPX8005, which is a terabit- class fabric that is based on a three-dimensional crossbar architecture with a large number of virtual output queues and distributed scheduling. As this fabric is using fixed-cell switching, it can handle time-division multiplexing (TDM) traffic on top of Internet Protocol (IP) and ATM flows. This is very significant as the tight requirements that traditional TDM traffic places on delay jitter and latency can be extremely hard to handle (if at all possible) for an average switch fabric chip that was designed only for IP and ATM traffic switching. The nPX8005, which is positioned by AMCC for metro access network, metro core network, and storage area network (SAN) switching applications, is actually a chipset comprised of a memory sub- system (S8905), a scheduling device (S8805 or S8505), and a crossbar with an integrated arbiter Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. AMCC nPTM FAMILY OF NETWORK PROCESSORS AMCC FAMILY OF NETWORK PROCESSORS 101 (S8605). It is designed to work seamlessly with AMCC's 7510 and 7250 network processors as well as with the company's nPX5700 traffic manager chipset. It features an integrated 2.5 G