is the asymmetry that causes problems with accuracy in the recovery of phase/time. See the section "The (Simple) Mathematics" in Chapter 7 and the section "Correction and Calibration" later in this chapter. As a definition, asymmetry is any behavior or characteristic of the network that causes PTP mes- sages travelling in the forward direction (from master to slave) to take a longer or shorter time than the trip in the reverse direction (slave to master). There is a lot more information on it in the upcom- ing section "Asymmetry," but before that, it is time to revisit some of the timing metrics first dis- cussed in Chapter 5. 9.3 Parameters for Timing Performance Besides the end-to-end network limits that define the performance of phase/time transfer with pack- ets, there is a range of timing metrics that apply to the individual clocks themselves. Standards de- velopment organizations (mainly the ITU-T) have developed numerous recommendations to ensure that clocks can be assembled into a timing network without encountering issues. To do that, the SDOs have defined metrics for equipment limits that define the performance of individual network clocks. Even the most basic problem could make a timing network unusable, such as where clock N + 1 in the chain of clocks cannot tolerate (as input) what the preceding clock N is generating as output. When building the timing network, the engineer needs to procure network elements that meet defined equipment limits and criteria to ensure they can work with each other. For phase/time distribution using a packet-based method, this covers factors such as Noise generation: The amount of time error produced at the output of a clock when it is sup- plied with an ideal input reference packet signal Noise tolerance: The minimum amount of time error that can be tolerated at the input of a clock without causing it to reject the input and generate errors Noise transfer: A clock property describing how time error from the input PTP interface can be detected in the PTP and 1PPS output i