ve network-processing solution used in the OC-48c realm. It has been recently expanded to the OC-192 realm through the NP10/TM10 chipset (the two were recently renamed APP750NP and APP750TM, respectively). Until recently, this was basically a three-chip solution that handled all of the classification, policing, traffic management, quality of service (QoS)/class of service (CoS), traffic shaping, and packet modification functions required a carrier-class network platform. This network-processor family includes the Fast Pattern Processor (FPP), the Routing Switch Processor (RSP), and the Agere System Interface (ASI). The FPP and RSP process the wire-speed data stream. The ASI provides an industry-standard Peripheral Component Interconnect (PCI) inter- face between a host processor and other high-speed processors from Agere that are responsible for control and management functions, including routing table and virtual circuit updates, hardware con- figuration, and exception handling. The ASI also helps the FPP police Asynchronous Transfer Mode (ATM) and frame-relay traffic at rates up to OC-48c while maintaining state information on data flows and even capturing statistics. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. 106 NETWORK PROCESSORS In midsummer 2002, Agere announced a new integrated version of its 2.5 Gbps network-proces- sor solution in the form of a new superchip called the APP550 (previously known as the INP5). The APP550 integrates the FPP, RSP, and ASI; doubles the performance; and reduces the power, cost, and space required for supporting external memory. The goal is to drastically cut down the chip count an integrated solution, improving the customer's time to market and system cost, performance, and density. In fact, a single APP550 can replace a six-chip configuration of the first-generation PayloadPlus chipset. Agere System