0 Synchronous Optical Networks and Synchronous Digital Hierarchy 2 Mbit/s MUX 1 Site A VC-12-1 Site D 2 Mbit/s VC-12-2 MUX 2 MUX 4 VC-4 containing Site B VC-12-1, -2, 3 2 Mbit/s Fig. 10.8 Synchronous 2 Mbit/s VC-12-3 multiplexing of VC-12s into a MUX 3 VC-4 when VC-12s are created in various places. Site C Bytes Allocated Block of 63 Bytes Allocated to VC-12-38 Pointers to VC-12-1 (35 bytes/125 us) VC-12 Payload 9 Bytes (these actually are distributed throughout VC-4) VC-4 = 2349 bytes/125 us Tall end of previous First few bytes of VC-12-38 group of 35 Bytes (remainder of the 35 bytes are in VC-12-38 delivered in the following VC-4) Fig. 10.9 Fixed location of VC-12 pointers within a VC-4. VC-12) to cope with a VC-12 that is running too fast. On the other hand, when a VC-12 is running slow, occasionally a VC-12 byte can be repeated. Second, this (hopefully) infrequent change of phase of a VC-12 relative to its VC-4 is recorded by means of a pointer. A VC-4 maintains one pointer for each of the VC-12s within its payload, and each pointer registers the offset in bytes between the first byte of the VC-4 and the POH byte of a particular VC-12. Each pointer is located in a predefined position within the VC-4 SO that, when the VC-4 POH has been located, it is a simple matter of counting bytes to locate each of the 63 pointers to the VC-12s (see Figure 10.9). The trigger for a rephasing of a VC-12 relative to its VC-4 is when the fill of the VC-12 input buffer (into which the incoming VC-12 is written prior to loading into the VC-4) exceeds a predetermined threshold. At this point, a fairly conventional justification opera- tion occurs, with either an extra VC-12 byte being loaded into the VC-4 (into the overflow position mentioned earlier) or, conversely, one byte being repeated (see Figure 10.10). Either way, the resulting change of phase of VC-12 relative to VC-4 is tracked by a corresponding change in pointer value. SDH Standards Block of Bytes Allocated VC-12-38 Input Buffer Fill 63 Pointers to VC-12-38 Nearly full