hould also mention EZdriverTM which is essentially a control processor API layer. This is a toolset designed to facilitate the development of software that is meant to be executed on computational resources of the control path CPU of NP-1-based systems. EZdriver contains a set of routines that execute on the control path CPU and provide an API for appli- cations that run on the same control path CPU and need to interface with the NP-1. With EZdriver, soft- ware engineers working on control path development tasks can easily handle tasks such as configuring the NP-1 chip, loading the microcode, creating and maintaining NP-1 lookup structures, sending and receiving frames to and from the NP-1, and configuring and accessing the NP-1 statistics block. EZdriver, in conjunction with the company's EZdesign tool, provides an extensive set of debug- ging capabilities by offering software-driven debugging features (such as breakpoints, single step, reg- ister, and memory access), which the code developer can activate on both the NP-1 simulator and the actual NP-1 chip. To help expedite the development of a complete system based on its NP-1 and QX-1 chips, EZchip offers evaluation boards with a choice of 1 Gigabit Ethernet, 10 Gigabit Ethernet, or OC-192 POS interfaces. Their design enables two boards to interconnect in order to obtain a complete ingress and Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES 152 NETWORK PROCESSORS egress line-card path. In addition to this, multiple boards may be connected over an external switch fabric and backplane. In 2002, the company demonstrated interoperability with IBM's latest PowerPRSTM 64G switch fabric. All evaluation boards can be accessed through a standard PCI-bus connector that plugs into a standard single board computer on which control plane software can be developed. As a result, 