 a small Swedish startup called Xelerated Packet Devices (www.xelerated .com). It announced that it has not only designed, but is actually sampling an integrated network- processing chipset, which is the first one to be able to function at full wire speed in 40 Gbps1 (OC- 768) networks. The chipset is based on an architecture that the company calls PISCTM, which stands for Packet Instruction Set Computing. It is composed of two chips-the XeleratorTM NPU and the XeleratorTM traffic manager. They can be used either as a combination or as standalone units. One of the development tools that the company provides is a cycle-accurate simulator, which is fed with files containing the executable code the programmer creates for forwarding plane applica- tion. The Xelerator chipset offers a single-threaded programming model to the programmer, who writes code as if he or she were faced with a single-image traditional sequential machine without the slightest need to know how parallelism will be involved in the actual code execution. The executable code is the result of the linking process, which occurs on the output of the assembler that generates compiled code by processing the PISC instructions (source code) that the programmer has to write. These PISC instructions perform the actual packet-processing operations (parsing, editing, encapsu- lating, modifying, and SO on) and call on hardware resources such as engines, meters, counters, TCAM, and SO on. The simulator is part of the GUI-based integrated development environment, which also contains a debugger and an integration support library along with ready developed code exam- ples for several real-life applications such as IPv4, IPv6, MPLS, layer 4 packet filtering, and traffic conditioning. The Xelerator network-processor units are available in three models, as shown in Table 9.1. Their packet-processing performance is always at wire speed and the deterministic processing delay of the chips offers very good jitter characteristics. Conceptually, the internal structure of th