stacks TCP/IP Low-level API drivers Device drivers and messaging layer Cycle/pipeline Cycle-accurate Montego accurate layer performance & simulator functional Traffic analysis verifier Traffic verifier Analysis Ethernet Compare? Development CASE development (computer-aided SW engineering) FIGURE 9.3 The parallel development of hardware and software using the IDS environment leads quicker to a converged design. (Source: Bay Microsystems) COGNIGINE A pioneering effort in the quest for architectural preeminence in the field of network processing is the Intelligent Network ProcessorTM by Cognigine (www.cognigine.com). The company calls its technol- ogy Variable Instruction Set Communications ArchitectureTM and VISC ArchitectureTM for short. It constitutes a scalable platform that is poised to handle traffic processing up to OC-768 levels of wire speed and beyond. It has intrinsic support for multiprotocol services such as Ethernet, PPP, IP, ATM, MPLS, TDM, and others; traffic management possibilities for up to 512K queues; and classification lookup capabilities for up to 1 million table entries in its product. The company is naturally targeting its products to metro, edge, core, and point of presence (POP) switches and routers, TCP termination systems, multiservice aggregation nodes, load-balancing server switches, and even storage area net- works (SANs). Figure 9.4 depicts this powerful multiprocessor platform. It is based on the integrated combina- tion of five-stage pipelined 16 four-way multithreaded processors called reconfigurable communica- tions units (RCUs) and a highly intelligent embedded switch fabric called an RCU switch fabric (RSF), which interconnects the RCUs. Figure 9.5 shows the five-stage pipeline that is located at the heart of the VISC Architecture. The result of these combinations inside Cognigine technology's current implementation is a com- putational powerhouse of 38 billion operations per second, which can be executed in a single clock Downloaded from Digital Engineering Library @ McGraw-Hi