 switch and the need to support bands at higher frequencies. Table 5.6 shows the performance of a nine throw switch implemented using a silicon sapphire process. This provides good isolation and the use of CMOS means that the off-chip logic can be integrated which is generally harder to achieve in GaAs switches. The switch also integrates the low pass filters. CMOS scaling combined with finer metal pitch technology and improved transistor per- formance should, however, realise future benefits both in terms of size and insertion loss, a 0.18-um process would halve the insertion loss and core area and double the bandwidth. The insertion loss and size benefits are shown below. Note that on the basis of these measurements the insertion loss of silicon on sapphire has now achieved parity with GaAs. Similar flexibility options and cost and performance advantage can be achieved using their proprietary thin-film ceramic material, a doped version of barium strontium titanate (BST). The dielectric constant of the material varies with the application of a DC voltage. The device is claimed to have a Q of 100 at 1 GHz and better than 80 at 2 GHz, and is claimed to be highly linear and provide good harmonic performance with low power consumption, high capacitance density, an IP3 of greater than 70 dBm, fast switching speed and low current leakage. 24 http://www.psemi.com Wireless User Hardware Table 5.6 Silicon on sapphire process versus GaAs insertion loss comparison. Reproduced with permission of Peregrine Semiconductor 0.36 um 0.35+ 0.35++ 0.18 um Production Launch Symmetric Throws TRX Paths TX Palhs RX Paths XtorRon Coff (fs) 587.5 TX/TRX IL @ 2 GHz (dB) RX IL @ 2 GHz (dB) Min Iso 1 GHz (dB) IMD (Band 1) (dBm) < 120 Normalised Solution Area 0.72X 0.59X Antenna Innovations 5.6.1 Impact of Antenna Constraints on LTE in Sub-1-GHz Bands The design of the antenna system for LTE mobile devices involves several challenges; in particular if the US 700 MHz (Bands 12, 13, 14, 17) bands have to be supported alongside the legacy cellu