ion results in a transient current in the struck transistor. As this current flows through the struck transistor, the restoring transistor ("on" p-channel transistor in Fig. 3.9) sources current in an attempt to balance the particle-induced current. Unfortunately, the restoring transistor has a finite amount of current drive, and equally importantly, a finite channel conductance. Current flow therefore induces a voltage drop at the drain of the restoring transistor. This voltage transient in response to the single-event current transient is actually the mechanism that can cause upset in SRAM cells. The voltage transient is essentially similar to a write pulse, and can cause the wrong memory state to be locked into the memory cell. In SRAM cells, there are four possible sensitive strike locations, namely the four transistor drains interior to the SRAM circuit. An important consideration for charge collection is whether the junction is located inside a well or in the substrate [70,87]. A diagram of mechanisms for each drain strike location in an n-substrate technology is shown in Figure 3.10. Generally speaking, in each case the transient resulting from an ion strike has a quick initial response followed by a slower, sustained current mechanism [70]. For example, in the familiar outside- the-well "off" strike (Figure 3.10a), there is an initial drift photocurrent (ip) followed by diffusion II-19 "on" p-channel (restoring transistor) Feedback lon Strike "off" in-channel (struck transistor) Figure 3.9. Competition between the feedback process and the recovery process governs the SEU response of SRAM cells. current (id). Both currents are directed such that they tend to raise the struck node voltage and cause SEU. This is the most sensitive strike location for most technologies [87]. In the outside- the-well "on" strike (Figure 3.10b), the initial drift current again raises the node voltage, but this reinforces the stored logic state. As the node rises, the struck junction becomes slightly forward- biased, and a condu