22 Open Radio Access Network (O-RAN) Systems Architecture and Design Prefetching. Both instruction and data prefetching can be useful. The base station application uses multiple processes/threads on multiple cores. Given the large footprint of the codebase and the user contexts, this means that the achieved performance in terms of Instructions Per Cycle/Clock (IPC) is often relatively low. Performance improvement thus comes from prefetching both code and data. Cache locking. Like prefetching, cache locking can provide for an improved IPC. System software should provide appropriate APIs. Large memory pages limit the software load associated with Memory Management Unit (MMU) misses by allocating packet buffers from a single large MMU entry rather than from standard Linux 4-KB pages. Interrupt coalescing/NAPI ("New API"). The overhead associated with interrupts and (associated) task switches is significant. As such, most networking stacks provide the option to tune the tradeoff between response time (latency) and throughput. Optimized hardware configuration. The default device configuration as provided by the Board Support Package typically is not optimized for final hardware. For example, DDR timing settings may be less strict than supported by the actual hardware. Review of such settings between hardware and software teams can provide an overall performance gain. Limit context switching. Remove unnecessary context switches. Examples include regular message queue checking using a separate process (could be triggered on message send), or excessive process-count where tasks could better be managed from within a SW process. Removal of system calls from the real-time path and replace necessary functionality with optimized, user-space functions. Use of timers from the user space is a great example of code that can efficiently be replaced with single-instruction timebase-read functionality. Software optimization techniques is never possible to provide an exhaustive list of software optimization techniques. Based on our e