 rate as the access frequency increases [83,84]. Bit-line errors can be caused by strikes to the access transistor drains along the floating bit-line or strikes to the sense amplifier circuitry itself [75,85]. Because of their inverse dependency on cycle time, bit-line errors become a significant reliability concern as memory speeds increase. 3.3.3 Combined Cell and Bit-Line Errors A new failure mode for DRAMs was demonstrated ten years ago when it was found that charge collection at both the storage cell and bit line that was insufficient to individually cause an upset could cause an error in combination [86]. This new failure mode, dubbed the combined cell-bit line (CCB) error, was shown to dominate the storage cell and bit-line error rates for very short cycle times. The three components of soft errors in a 512K DRAM are shown in Figure 3.8 as a function of the cycle time. Note the independence of storage-cell errors on cycle time, and the domination of CCB errors for short cycle times [86]. lon Path Bit Line Word Line Field Plate Poly Stored Information Charge Figure 3.7. Illustration of storage cell SEU in a field-plate DRAM after Massengill [75]. Collection of electrons at the reverse-biased field plate reinforces a stored "0," but can lead to an upset of a stored "1." II-18 Source: AM241 CCB Component Bit Line Component Cell Component Cycle Time (ns) Figure 3.8. Components of soft-error rate in a DRAM [86]. The storage cell component is not dependent on the cycle time, while soft errors involving the bit lines increase dramatically as the cycle time decreases. Single-Event Upset Mechanisms in SRAMs The upset process in SRAMs is quite different from DRAMs, due to the active feedback in the cross-coupled inverter pair that forms a typical SRAM memory cell. When an energetic particle strikes a sensitive location in a SRAM (typically the reverse-biased drain junction of a transistor biased in the "off" state [70,87], for example the "off" n-channel transistor shown in Figure 3.9), charge collected by the junct