s from a radiation-hardened technology are not available II-32 [159]. Several design-hardened SRAM and latch circuits have been proposed and fabricated [160-165]. These memory cells typically rely on redundant circuit elements (usually 12-16 transistors per memory cell as opposed to 6 in a standard unhardened cell) to protect against SEU. Because of the large number of transistors per cell, these designs consume considerably more area (and frequently more power) than 6 transistor cells. While these cells can be appropriate for protecting a limited number of critical data paths, they are not usually suitable for very highly-integrated circuits. A design-hardened SEU tolerant DRAM cell that is comparable in size to conventional single transistor DRAMs has also been proposed [166]. System-level hardening approaches include the use of error detection and correction (EDAC) circuitry to monitor and correct errors as they occur [167-169]. This approach requires that extra bits of information be stored with the data to reconstruct the original data in the event of an upset. System overhead can be non-negligible, but this is sometimes the only method available if relatively susceptible parts must be used. Cruder methods such as watchdog timers, redundancy, lockstep operation, majority voting, etc., are commonly used to detect control system errors [170]. While simple in concept, overhead can again be significant, but in many cases this is the only option available to the spacecraft engineer. Last year's NSREC Short Course segment by Kinnison and this year's segment by Heidergott contain additional information on system-level hardening methodology [170,171]. II-33 BASIC MECHANISMS FOR DESTRUCTIVE SINGLE-EVENT EFFECTS In this section we will briefly discuss mechanisms for destructive SEE, namely single-event latchup (SEL), single-event gate rupture (SEGR), and single-event burnout (SEB). This is not intended to be a complete list of destructive SEE failure modes, but are some of the more commonly encountered effects. For a 