clock speed and version, and its high-performance cousin, (b) Establish mapping between different FPGA the TMS320C64x, is rated at 250-1650 mW, depending families. This mapping can be done on the basis on clock speed and version. of logical devices, available multiplies per ele- ment, or another appropriate metric. 2.4a.2.3 Baseband processing deployment (c) Find logical device count for each target algo- rithm. FPGA manufacturers usually maintain One of the problems that the CR developer will encounter thorough libraries with benchmarks. when designing a system is attempting to determine what (d) Use mapping between devices to find approxi- hardware should be included in the design and what mate target load on devices when a benchmark is baseband processing algorithm to deploy into which pro- not available. cessors. The initial selection of hardware will impose Once the platform-specific analysis is complete, the limits on maximum waveform capabilities, while the developer now has the tools necessary to map specific processing deployment algorithm will present significant algorithms onto a set of devices. Note that at this stage, run-time challenges if left entirely as an optimization there is no information as to the suitability of each of process for the cognitive algorithm. If the processing de- these algorithms to different platforms, since a base ployment algorithm is not designed correctly, it may lead clock rate (or data rate) is required to glean that type of to a sub-optimal solution that, while capable of supporting information. the user's required quality of service (QoS), may not be Given the platform-specific information assembled power efficient, quickly draining the system batteries or above, it is now possible to create performance estimates creating a heat dissipation problem. for the different waveforms that the platform is intended The key problem in establishing a deployment meth- to support: odology is one of scope. Once a set of devices and algo- rithm performance for each of these devices 