ect this issue. However, the major problem with this distributed approach is that in very-high-speed heavy-traffic- load contexts, the performance of an application cannot be gauged before the application has actually been developed. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. INTEL IXA TM NETWORK PROCESSORS INTEL IXA TM NETWORK PROCESSORS 89 Switch Fabric Control Tables Tables Plane Queues Switch Fabric Queues Interface Chip (CSIX) QDR SRAM QDR SRAM PCI 64-bit 15 Gbps 66MHz QDR SRAM QDR SRAM 15 Gbps QDR SRAM Intel IXP2800 Intel IXP2800 QDR SRAM QDR SRAM Ingress Egress QDR SRAM Processor Processor 10 Gbps SPI Interface 1x OC-192 4x OC-48 16 OC-12 1x 10 GbE Packet 10x 1 GbE Packet Memory Memory FIGURE 5.7 Configuration of a typical LAN/WAN interface using the IXP2800 network processor. (Source: Intel) H.110 TDM backplane 4 signal processing modules based on Intel's TSI Cross Connect PCI control IXS1000 Media Processor backplane bridge VX bus IX bus Control Packet processing processing IXP1200 IXF440 IXF440 Network Processor SDRAM LXT971 LXT971 LXT1000 LXT1000 10/100 Base-T 1000 Base-T Ethernet Gigabit Ethernet FIGURE 5.8 Design example of a Voice-over-IP gateway linking Fast and Gigabit Ethernet LANs with the TDM-multiplexed PSTN telephony network. (Source: Intel) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. INTEL IXATM NETWORK PROCESSORS 90 NETWORK PROCESSORS In order to better understand the principle of allocating parts of the packet processing to different microengines, we must also look at a real-life application and, more specifically, at how Intel recom- mends the application be logically partitioned over the available microengines in order to optimize perf