 form a complete L1 chain. In aggregate, we come to 21 X 4 = 84 GOPS/second required processing. Assuming a lower end 128 SIMD-capable CPU core at 2.2 GHz operation, each core can do 128/32 = 4 multiply-accumulate or 8 (multiply and accumulate are 2 separate operations) operations or roughly 18 GOPS/second. Similarly, when operating in 16-bit (fixed point), the number of GOPS/second doubles to 36. As a first pass, we conclude that Physical Layer processing per carrier takes roughly (84/36 to 84/16 3 to 5 CPU cores. Phase 2: performance proof points A very high-level analysis has shown above. In the next stage, we need to prove that the assumed cycle counts for each individual software kernel is achievable in real life. This requires actual software development-building proof points of the actual application or acquiring performance relevant software components from the device or other vendors. This stage allows us to eliminate guesswork around topic 1 abovementioned (low-level kernel inefficiencies). We still have overheads associated with integration inefficiency (topic 2) but we start eliminating risk in the development cycle. As an example, let's assume we need to validate performance for QAM demodulation (LLR generation) in software. 3GPP 38.212 defines QAM mapping for 16QAM as follows: quadruplets of bits, b(4i), b(4i + 1), b(4i + 2), b(4i + 3), are mapped to complex-valued modulation symbols d(i) according to: or, shown graphically in Fig. 9-2. Chapter 9 Software performance -3V10 1-v10 -3V10 FIGURE 9-2 QAM demodulation. QAM, quadrature amplitude modulation. Assuming an signal-noise-ratio Y and a complex (R(eal) + I(imaginary)) data subcarrier output (from channel estimator) d(n) for each symbol, LLR calculations are shown in the following: L0=-~R(d) L2= - I (d) Assume the input data format to be an I/Q sequence of 16-bit values. The LLR outputs have to be quantized to 8 bit to be passed on to the descrambler and decoder units. Vectorized QAM modulation is implemented in a two-step process: 1. LLR generatio