SafeXcel-2141 coprocessor, which has been designed together with Analog Devices (and also contains a powerful embedded and user-programmable digital signal processor [DSP] core), as shown in Figures 17.9 and 17.10, which are used in computational envi- ronments of workstations or small gateways with aggregate throughputs less than 1 Gbps. Figure 17.9 shows how the coprocessor fits into a system, and Figure 17.10 shows the internal structure of the chip. The cryptographic modules are shown in gray for clarity. However, the trend in the network-processing arena, where wire speeds of several gigabits per sec- ond is the norm and where every packet flowing by belongs to a completely different session and must be treated in a different way involving different ciphers and keys, places a tremendous stress on tra- ditional encryption chips. These classical encryption chips contain special hardware units that will calculate all modular exponentiations with hardware assistance. On top of that are usually embedded modules that will calculate DES (and/or AES in the latest designs) in the appropriate mode, as well as hashes such as MD5 and SHA-1. The main systems processor therefore hands out the data to be secured along with the parameters required to the security coprocessor, which will calculate all is required and pass the results of the cryptographic calculations back to the main CPU. The main CPU during that time can use its power on other tasks. In our case, we emphasize two types of security coprocessors: IPsec accelerators and SSL accel- erators. The products appear in chip and board format. SafeXcel Local SRAM Ethernet Ethernet SA storage EMI bus PCI bus boot and control Dual-port Packets and descriptor PCI bus System System & PCI bus controller FIGURE 17.9 The systems configuration of a SafeNet-2141 security coprocessor based on the Peripheral Computer Interconnect (PCI) bus (Source: SafeNet) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hi