queuing), layer 3 warding and filtering (flow control and frame alteration), and layer 4 flow classification based on priority and multicast handling. They also maintain network management counters. The CP in Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. IBM POWERNP™ IBN POWERNPTM Figure 4.2 handles layer 2 support (spanning tree), layer 3 support (OSPF, the Routing Information Protocol [RIP], and the Border Gateway Protocol [BGP]), networking management (the Remote Network Monitoring [RMON] agent), configuration, diagnostics, and other box-related functions. Up to 64 NPUs can be connected with a switch fabric in one system. This scheme supports up to 1,024 Fast Ethernet ports or multiple POS configuration possibilities. The NP4GS3 is built using a 0.18u copper-interconnect process. It is housed in a 1,088-pin pack- age (with 815 signal input/output [I/O] lines) using a 24-pin debug bus. Its core is powered by a 1.8 voltage supply, whereas the DDR and ZBT RAMs are powered by 2.5V and the so-called data mover units (DMUs) as well as the PCI interfaces are supplied by a 3.3V supply. Power dissipation is estimated at 14 watts. MAJOR FUNCTIONAL BLOCKS IN THE NP4GS3 Figure 4.3 shows an architectural view of the NP4GS3 system. This illustration shows its major func- tional components with the abbreviations that IBM uses to describe them in its technical literature. These blocks are as follows: Physical MAC Multiplexer (PMM). Ingress Enqueue/Dequeue Scheduler (I-EDS). Switch Interface (SWI). Switch Data Mover (SDM). Switch Cell Interface (SCI). Data-Aligned Serial Links (DASLs). Egress Enqueue/Dequeue Scheduler (E-EDS). Traffic Shaper. Embedded Processor Complex (EPC). Embedded PowerPC Complex (ePPC). Various storage areas are also deployed throughout the system. Imagine that the data flow on the ingress side proceeds from the bottom of the drawi