Prestera-MX two-chip offering: full-duplex 10 Gbps 98MX20 for 1X10 Gigabit Ethernet 98MX30 for 10X1 Gigabit Ethernet Traffic manager Yes, through the company's Congestion management (Weighted chip companion ZEN-QM two-chip Random Early Detect [WRED]) (QMD-QMC) Traffic shaping and traffic scheduling only at egress Integrated Ethernet Yes (easy connection with the company's Media Access Control physical [PHY] chips) (MAC) Packet over SONET Not easily; glue logic is needed for OC-192 (POS) and ATM suitability framers. Classification Yes, at ingress only Policing Both on cells and packets Yes, only on packets and only at ingress Packet modifications Yes, with support for ATM, IP, Yes, with support for IP and MPLS and only and Multiprotocol Label at ingress Switching (MPLS) Host interface Generic bus that is 16 bits wide Standard Peripheral Computer Interconnect and works at 66 MHz (PCI) Search engine External content-addressable No need for external engine memory (CAM) up to 1 million Types of memory needed Packets in double data rate DDR-SDRAM is absolutely needed, (DDR) synchronous dynamic offering a cost advantage to the memory random access memory subsystem. (SDRAM). Other types of memory are optional. SRAM needed for the traffic manager External CAM is needed for search engine implementation. Interface toward the System Packet Interface, 4.2 RGMII for Gigabit Ethernet and XGMII for line side (SPI-4.2) 10 Gigabit Ethernet Interface toward the CSIX-L1 bits at 250 MHz Proprietary 15 Gbps and HSTL uplink fabric side CSIX-L1 fabric adapter chip that also does ingress scheduling Package 1,036-pin HPBGA 901-pin ball grid array (BGA) Power consumption + 10 watts Not disclosed (max) The idea of using IP cores for the design of sophisticated integrated circuits is not a new phe- nomenon. In fact, it has become a widely practiced principle over the 1990s. The fundamental idea is as follows: Instead of designing a specific and usually very complex part of an integrated circuit, a designer licenses the use of a core circuitr