t equipment (dense wavelength division multiplexing [DWDM] and SONET). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES OTHER NPU ARCHITECTURES In order to achieve very high levels of performance while maintaining the maximum flexibility, Bay Microsystems has created a new technology that is optimized for the specific requirements of high-performance packet processing. The company calls this technology Vertical Instruction ProcessingTM (VIP) and Vertical Data ProcessingTM (VDP). The term vertical processing is used here to denote its principles. The basic idea is that sets of deterministic, programmable, and pipelined processor engines, which are optimized for specific packet-processing operations, are arranged in a data flow-through structure. As one can infer from Chapter 14, "Switch Fabrics", this flow-through structure is quite reminiscent of a shared-buffer switch complete with an ingress processor, shared output buffer memory, and an egress processor. In addition to improving performance, the utilization of VIP and VDP technologies is in line with the school of thought that has consistently advocated structured very large scale integration (VLSI) design. Therefore, it allows for the undisputedly improved and structured integration of massive cir- cuitry as opposed to other more traditional processor designs. Unlike alternative architectures, the most distinguishing characteristic of the Montego architecture is the deterministic performance that it affords. The vertical-processing environment accomplishes this. Figure 9.2 shows how this principle is implemented. Imagine that data comes in from the lower-left side of the picture. By deploying the data on a dimension that is perpendicular to the actual data flow input/output (I/O), the Montego chip is applying a multiple instructions single data (MISD) model. A stre