ch embraces configurable VLIW principles. For obvious reasons, we will examine the importance of this trend from a network-processing standpoint. 5. Anthony Cataldo, "Reconfigurable Processors Make Move into Big Time," EE Times (May 24, 2001). This is accessible www.eetimes.com/story/OEG20010324S0001. The same story is also mentioned in another article by the same author called "Comms Warm a Bit to Reconfigurable Processor," EE Times (March 23, 2001). This is accessible at www.eetimes.com/story/OEG20010323S0071. 6. Seewww.tensilica.com/press/Tensilica_press_20011017_mprvision.html 7. The introduction was made on October 16, 2002 at the Microprocessor Forum conference. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES Complex network-processing tasks, especially since they must be executed at wire speed, amount to extremely heavy computational loads that ordinary architectures cannot handle. With more data and applications to deal with per unit time, more work needs to be accomplished in the same short amount of time. The following are two fundamental ways of going about doing this: Increase the frequency clock when possible and force the hardware to complete more operations per second. Deploy a sense of parallelism into a design. With dramatically shrinking lithography line widths and with IP core reuse methodologies prolif- erating by the need to meet shorter times to market, integrated systems become more complex by the massive piling up of multiple subsystems on one and the same SOC. This context makes the choice of increasing the frequency of the fundamental clock unacceptable as it drastically increases the chip's power consumption, which creates package choice (and therefo