 themselves locally possessing some network-processing intelligence, which could enable each line card to decide a packet's destination and output port without the intervention of the main switch/router CPU. In order for this to happen at wire speed, designers created fast application-specific integrated circuits (ASICs), which would operate directly on arriving packets. Splitting the work into the slow path and fast path processing (in other words, a slow path CPU had to be placed on the line cards) enabled designers to minimize the routing dependency from a centralized CPU. These tasks were soon to be expedited through the local caching of routing tables in fast memory that designers made available on each line card. This meant that the macroscopic port-mapping func- tion of the generic switch architecture was now effectively distributed among the line cards. Switching and routing were no longer central CPU functions. The main CPU of a switch/router would now act more as an overseeing controller to which exceptional tasks are handed over. For instance, when no route could be found locally on a line card, the main CPU would handle a request for routing such an exceptional packet and would also install a new route entry in the lookup table that line cards would use where the problem originated. In the case of ATM switching, the line-card network-processing intelligence made sure that it would find a match between the cell's VCI and an entry in the locally cached routing table. This match was necessary because at call setup time, the supervising controller created that specific entry. In the case of non-ATM packet switching, the route entry may or may not exist inside the cache. If it was found, then the line card logic would switch it accordingly by sending the packet to the appropriate line card that was associated with the intended output. If it was not found, then the task would be handed over to the supervising CPU of the switch/router. The line cards in such a switch architecture would share access to (and c