C-48 ports with a scalable aggregate throughput up to 512 Gbps. This effectively quadruples the performance of the third-generation product. 23. B. Patel et al., "The Helix Switch: A Single Chip Cell Switch Design," Computer Networks and ISDN Systems 28 (1996): 1791-1807. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SWITCH FABRICS NETWORK PROCESSORS IBM switch fabrics of the PowerPRS architecture implement several of the concepts we have already studied such as VOQ and shared memory, flow control, priority levels, credit tables and sched- uling, multicast, and redundancy. Refer to "PowerPRSTM" by René Glaise24 and "A Combined Input and Output-Queued Packet-Switched System Based on PRIZMA Switch-on-a-Chip Technology" by Cyriel Minkenberg and Ton Engbersen ²5 for more information on the switch fabric internals. These features offer multiterabit growth capability within a common architecture while supporting redun- dant switch fabrics and enabling manufacturers to design scalable, compact, and nonblocking switches ranging from 8 OC-48c/2.5 Gbps ports to 64 OC-192c/10 Gbps ports. The 64G and Q64G switch fab- rics are available either as single, highly integrated silicon components or as board-level products. The Q64G has been designed with a speed-up factor (overspeed) of 60 percent, sustaining throughput of 16 Gbps per port (on 10 Gbps connection links). The extra headroom is required in order to take care of the overhead needed to disassemble, label, strip, and reassemble the cells that are internally created following the fragmentation of incoming packets. 26 The Q64G combination output queuing with a shared memory. The advantages of both these techniques were discussed ear- lier in this chapter when we discussed switching internals. With output queuing, no internal blocking occurs and the delay is minimal. With shared memory, the best ove