more noise, and can be more operates by performing a binary search through the ADC dynamic difficult to trim than the corresponding LC filter. Switched capacitor range to find the input voltage. filters (Sedra and Smith, 1982) can be highly integrated, requiring Upon receiving the Convert command, the storage register is only off chip capacitors, and hence lead to a cheap package which cleared. The output from the storage register is passed to the digital does not require large amounts of PCB area. They do, however, add to analogue converter (DAC), but with the most significant bit set. considerably more noise than the passive and active filters. This causes the DAC to output its half range voltage. This voltage The analogue sampler, commonly known as the 'sample-and- is then compared with the input sample by the comparator. The hold', performs the task of sampling the input analogue voltage and comparator output is then stored in the most significant bit (MSB) maintaining that voltage until the next sampling instant. A simple of the storage register. The converter has thus decided whether the sample-and-hold is illustrated in Figure 19.15. When the Sample input voltage is in the lower or upper half of the ADC's dynamic command is given, the buffer is connected via the FET switch to the range. storage capacitor, the voltage on which tracks the input voltage On the next clock cycle, the storage register output is passed to the thereafter. The capacitor is at all times buffered by a voltage fol- DAC with its 2nd most significant bit set. The comparator output lower. When the Sample command is removed, the capacitor is then indicates whether the input signal lies in the upper or lower half isolated from the input buffer. The voltage across the capacitor, and of that portion of the dynamic range selected in the previous deci- hence the voltage follower, will then remain steady until the next sion. The comparator output is stored in the 2nd most significant bit Sample command. of the register. Such a simple design is 