f the hardware is characterized by a few critical parameters, the scheme of Figure 10.37 has the advantage of being able to store an optical packet also for a very long time, up to the moment in which the packet intensity cannot be any more amplified effectively for its very low SN. Stored packet FIGURE 10.37 Input Switch Output Example of the first type optical memory: A linear ampli- packet packet fied ring. Telecommunication Networks Stored packet Delay T Delay 2T Delay 4T Input Output packet packet Delay 8T FIGURE 10.38 Switch Combiner Delay line-based optical memory. A completely different behavior is shown by the scheme of optical memory reported in Figure 10.38. Here, the optical packet enters into the memory through a 1xN switch that sends the packet to one out of N different memories. The memories are simply delay lines with different length SO that the packet storage time is decided by the switch position. This type of optical memory is much simpler to design, since no possibility of oscilla- tions exists, but cannot store the packet for a time longer that the maximum delay imple- mented by the delay lines. Combining the two principles, that is the recirculating memory and the delay line mem- ory, any memory of the first type can be built. In particular, in order to build an FIFO queue (First In First Out), first an elementary memory cell has to be built, as is shown in Figure 10.39a. The elementary cell has three states, as common to all memories: "write," "store," and "read." The schemes of the three states are shown in Figure 10.39b. Delay T Input Storing Output packet packet Write (e.g., from input one) Read (e.g., output one) FIGURE 10.39 Three states elementary optical memory cell: (a) architecture; (b) the three cell states. Next Generation Networking: Enabling Technologies, Architectures, and Performances FIGURE 10.40 Scheme of an FIFO optical queue. Cascading a certain number of elementary cells a queue is realized where, when a cell is free since the content is moved to the next cell, its cont