 Step 48 (you may get another number). The fact that the random simulation starting from the same SDL model state stops at Step 261, 264 or 48 means that different scenarios have been simulated, because the seed was always different (computed at every step, then never reinitialized during init). To automatically perform the previous random simulations, we are going to write a script. E. With a text editor, type the following lines and save the file as rand.wri: return to step 0 source start. scn execute the 4 start untrace all - - remove textual traces define trace_stmt 'false' - - remove PR traces Protection against double declaration of sim_ok: if $vars_declared' = define vars_declared 'Yes' dcl sim ok Boolean let sim ok = true while sim ok Random Simulation 175 print seed go until step = 500 random simulation if step / = 500 let sim_ok = false print step redo 4 - - play again the 4 starts endwhile F. In the Simulator, select Edit > Configuration and uncheck the box Trap unexpected signals; otherwise our script would stop during the first iteration. G. In the Simulator, type the command: source rand. wri The Simulator performs four times the while loop (you may get different results), as shown in Figure 6.7: three times without discovering any error before Step 500, then one more iteration where an error is encountered at Step 60. The error encountered is: No receiver for output l __releasereq from dlcb!dispatch via dlcs to dlcb!dlc(1). It means that instance 1 of process DLC in block DLCb was stopped before the signal L_ReleaseReq was transmitted to it by process dispatch. As performed previously, you could press the Traces: Defaults button to turn the trace on (it was removed by the script to speed up the simulation), and use the undo command to get the MSC trace to understand the error and fix it. If you launch again the script rand.wri without exiting from the Simulator, the seed values will be different, and the number of while loops performed will change. If the simulation never terminates (no error is en