achieved at the circuit design level by a number of possible Spurious signals coupled into a logic signal circuit will have no effect until they reach the logic threshold. At the same time, the strategies: amplitude of signals coupled into the circuit from a given field will depend on the impedance of the circuit, which is defined by the 1. Minimising the signal bandwidth, SO that interfering signals driver output impedance. 4000B series CMOS has around 10 times outside the wanted frequency range are rejected. higher output impedance than LSTTL, depending on supply volt- 2. Operating the interface at the highest possible power or voltage level consistent with other requirements, such as dynamic age, SO although it has a higher input noise margin it is more susceptible to capacitively coupled interference. 74HC series has a range, SO that relatively more interference power is required to roughly equivalent output impedance and a higher input noise upset it. margin, SO it is to be preferred over ordinary 74LS series TTL. 3. Operating the interface where possible with the signal bal- anced, SO that interference is injected in common mode and is The lowest possible clock frequency will minimize the amplitudes therefore attenuated by the common mode rejection of the input of the higher harmonics, and allow the smallest 'window' for dis- circuit. ruptive transients in synchronous circuits. It may be possible to use 4. In severe cases, galvanically isolating the input with an opto low frequency multi-phase clocks rather than a single high fre- isolator or transformer coupling, SO that the only route for the quency one. In some circumstances changing the spot frequency of interference is via the stray coupling capacitance of the isola- the clock slightly may move its harmonics sufficiently far away tion components. from a particularly susceptible frequency, though this is more a case of EMC within a system than of meeting emission regulations. Not SO obvious is the overload performance of the circuit. If the interference