2.11 The digital subscriber switching stage central processor (CP). The APT central software units are stored and executed in the central processor. The two processor sides work in a synchronous parallel mode. Permanent or temporary (intermittent) hardware faults can affect only one side at a time, data mutilation occurs in that side only. The by buffer memories and space switching by electronic crosspoint intact side automatically continues traffic handling with correct data matrices. The switching part of the group switch is duplicated in two while the faulty side is taken out of traffic. This process is suffi- planes and all calls are established in both planes. The active plane ciently fast to make corrective software actions unnecessary. Thus, is determined on a per call basis. in the majority of cases hardware recovery will not affect switch The timing in the digital group switch is performed by a triplicated operation. The synchronous duplication model in fact guarantees clock module. Synchronisation is implemented by means of a soft- that central processor hardware faults will not cause software ware algorithm that can accommodate alternative network syn- failures. In addition, comparison between the two processor sides is chronisation methods. an effective diagnostic tool for locating a faulty hardware sub-unit. The Trunk and Signalling Subsystem, TSS, supervises the state of The ability to separate the system without affecting its operation is trunks to and from other exchanges. For analogue and analogue to also a valuable aid during major extensions or substantial software digital conversion trunks, the signalling is extracted and inserted in modifications. the trunk before entering the switch. Multi frequency signalling is Error correcting techniques in the memories mean that most handled via the group switch using code senders and code receivers. memory faults are corrected without affecting the application soft- The Common Channel Signalling Subsystem, CCS, implements ware. the Message Transfer Part