forms, which have become the bulwark of mainstream com- puting, are simply not capable of handling the multiple facets of complex network-processing applications running on live packetized networks at wire speed. At the same time, however, do not discard the fact the industry has been struggling conscientiously to address this need. Tests like the EEMBC benchmarks are a good first effort to solve the problem. They can also be found useful for evaluating and comparing the control plane. However, more work is needed to develop representative, universally accepted, and useful test suites. The EEMBC Networking benchmark suite is based on applications that are drawn from the net- working reality and that have significantly different characteristics than consumer or IT applications. They usually involve less arithmetic computation, generally show less low-level data parallelism, and frequently require rapid control flow decisions. The EEMBC Networking benchmark suite contains representative code for routing and analyzing packets. Figures 10.6 to 10.9 show some interesting results obtained by executing this code on multiple processors. NetMarks/MHz 0.035 0.025 0.015 0.005 Xtensa ARM 1020- MIPS 64 M32 (NEC VR4122) VR5000) FIGURE 10.6 A comparison of EEMBC NetMarks/MHz of out-of-box scores for Xtensa 350 and several other architectures. (Source: Tensilica) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES NetMark Performance Xtensa 350 ARM 1020- MIPS 64 (NEC M32 (NEC VR5000) VR4122) FIGURE 10.7 The comparative results of Figure 10-6 are only further exacerbated if the impact of the higher clock frequency now used in the Xtensa V pipeline is considered. The results shown here are in absol