Q scheme, both user data and complementary parity bits are included in every re-transmission. The type III HARQ schemes are less efficient than incremental redundancy schemes due to repeated user data bits. Also in this case, after every re- transmission, a richer set of parity bits is available at the receiver, improving the probability of reliable decoding. Moreover, by adopting combining techniques, reliability may be further improved. In a type III incremental scheme, information can be recovered from every transmission. In a self-decodable HARQ re-transmission scheme, the user data may be recovered from every single transmission. 7.2.2 IEEE 802.16m HARQ Mechanism The HARQ mechanism is used for all unicast data traffic in both downlink and uplink. The IEEE 802.16m HARQ scheme is based on an N-process stop-and-wait protocol. In single channel stop- and-wait, the transmitter waits after each transmission until an acknowledgement from the receiver is obtained. In the case of positive acknowledgement, a new packet is transmitted; otherwise, the same packet is re-transmitted. The N-process stop-and-wait mechanism makes use of the waiting time and transmits other sub-packets. Both BS and MS are required to maintain multiple simultaneous HARQ channels. The DL HARQ channels are identified by a HARQ Channel Identifier (ACID), whereas the UL HARQ channels are identified by both ACID and the index of the UL subframe in which the UL HARQ data burst is transmitted. Multiple UL HARQ channels in the same UL subframe are identified by different ACIDs and UL HARQ channels in different UL subframes are identified by the index of the UL subframe when they are addressed with the same ACID [3]. Generation of the HARQ sub-packets follows the channel coding procedures. The received sub- packets are combined by the FEC decoder as part of the decoding process. The use of incremental redundancy HARQ is mandatory in IEEE 802.16m compliant entities with chase combining as a special case. Each sub-packet contains part of a codeword ident