high-speed packet entry and acceptance directly into memory for subsequent processing. The latter is used when access is required to other coprocessors or memory. The number and type of these I/O channels can be configured by the user of the company's IP core architecture. To facilitate the design of complicated SOCs based on the IP core architecture, ClearSpeed has developed an on-chip, high-speed, modular interconnect bus called ClearConnectTM. It is a point-to- point link based on distributed arbitration. It is structured in segments that connect different SOC com- ponents to the bus. Each segment behaves like a local bus between the corresponding nodes. These links can be scalably structured with up to four lanes of bidirectional traffic where each lane provides up to 6.25 GBps of bandwidth for an aggregate bandwidth per link of 50 GBps between any attached nodes. The segmentation of the ClearConnect bus means that multiple transfers can take place simul- taneously between unrelated nodes on the bus. In addition, ClearConnect uses standard Virtual Component Interfaces (VCIs) (as specified by the VSI Alliance) for the easy integration of third-party cores and other coprocessor or components on the same SOC design. ClearConnect is delivered in synthesizable RTL. It fits perfectly into any standard ASIC design flow and interfaces easily with place and route tools. In addition to the embedded MTAP processors that share access on the ClearConnect embedded bus, the standard architecture that ClearSpeed proposes also provides for the potential presence of a series of parallel coprocessors (also known as accelerators) that can be either among those designed by the company or user or that can be licensed from a third party. ClearSpeed offers a series of IP cores that may be interesting to customers for the integration of a complete design. It offers among others accelerators for tree-search functions as well as for queue and state management. However, the most prominent of these designs is a powerful Table Lookup Engi