nce that these chips usually deliver) with most of the necessary packet-processing functions, which are already integrated into the same Net ASIC die. This combination, along with the associated trade-off, is somewhat appealing to many companies that are confronted with the dilemma of choosing between a more traditional network processor and designing a specialized ASIC for their project. In order to understand the rationale behind the Net ASIC phenomenon, we must examine this dilemma. Looking at a contemplated ASIC, many companies that decide to use a Net ASIC lack the necessary design and engineering skills, lack the financial resources, or cannot afford the longer time to market that is associated with designing a complex fast-networking ASIC from scratch. This ven- ture usually takes between 12 and 18 months. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES 160 NETWORK PROCESSORS On the other hand, companies that favor a Net ASIC seem to shun the idea of using a program- mable network processor because of the amount of time it takes to develop software for packet cessing over a vendor's proprietary development system. This task often must be implemented based on unusual instruction sets, unfamiliar languages, and the tools themselves. Application developers actually have to learn the underlying NPU architecture and how to activate its various parts. All is deemed by such companies as time consuming. They would rather opt for a Net ASIC. The word deterministic was used to describe the packet-processing performance of Net ASICs. This is not a coincidence. As a Net ASIC is completely hardwired, as long as the available integrated functions are exactly what a customer wants, the user has little to worry about regarding issues such as jitter or packet-processin