10' what are the output bit sequences? Answer Data bits (top branch): '00010011' Parity bits (bottom branch): '01111001' Error Control Coding Output bit 1 Input bit Delay Delay Output bit 2 Figure 6.13 A constraint length 3 convolutional encoder Output bits (upper): 00010011 Input bits: 00010011 Output bits (lower): 01111001 Figure 6.14 Example of coding with the constraint length 3 convolutional encoder In contrast to block codes which take at input a fixed number of data bits, the input size of convolutional codes is indefinite and generally depends on applications and standard. However, when the data block does end, the shift registers must be reset to 0. This is carried out by several O's to the end of the data sequence. These are referred to as tail bits, and are necessary for the proper operation of the decoder at the receiver side. For example placing two zeros at the end of the input bit sequence of '110010', to make it '11001000' ensures that both shift registers return to the 0 state. The outputs of the convolution encoder there- fore become: Data bits (top branch): '00010011' Parity bits (bottom branch): '01111001' The two parallel output sequences are converted to a serial sequence and transmitted as: 0001011101001011. Viterbi Decoder Convolutionally encoded codewords can be decoded using a trellis decoder or Viterbi decoder (named after Andrew Viterbi) [7]. A trellis decoder traces the received codes and calculates its Hamming distance from all possible sequences that an encoder may produce. For the encoder of Figure 6.14 the trellis diagram is shown in Figure 6.15. The circles indicate the state of the shift registers and branch out to another state based on the input data bit. For example at the start the shift register state is '00'. This state may remain '00' if a 0 is input or may change into state '10' if a 1 is input. Similarly the trellis may move from state '10' to '11' or '01' depending on the input data. The output of the decoder after each state transition is indicated on the link connect