he software servo into an actual physical clock ticking at the rate of the PTP master. Various implementations are possible, but the net result is the same-a clock that can be tuned up or down with a very fine resolution (often better than parts per billion) to align the local clock rate to real time, as received from the PTP master. Time-of-day counter-The final hardware component is the time-of-day counter, which is responsible for storing the actual time-of-day information, typically in the form of the number of seconds and nanoseconds since the epoch. In many cases, phase is more 30000 20000 10000 -10000 -1000 -20000 -1500 -30000 16000 24000 16000 24000 Simple PI Controller Servo Proprietary Optimized Servo (note vertical scale change) FIGURE 8-31 Servo performance comparison. 302 Open Radio Access Network (O-RAN) Systems Architecture and Design PTP Stack Extracted Timestamps Messages Time Recovery Timestamping, Servo ToD H/W SysClk Control + 1PPS Physical Layer PLL & DCO FIGURE 8-32 PTP + SyncE solution flow. PTP, Precision time protocol. relevant than absolute time, in which case a so-called 1PPS signal can be generated from the time-of-day counter. This is a signal that pulses once per second and is aligned to the time-of-day counter, typically with its rising edge corresponding to the start of each second. This 1PPS signal can be used to phase align the air interface, for example, without having to worry about the details of actual time in terms of date, hours, minutes, and seconds. The interaction of these hardware and software components is shown in Fig. 8-32. Designing a PTP + SyncE solution It should be clear from the preceding section that quite a lot of design thought and effort is needed in designing a PTP + SyncE sync subsystem, especially when compared, for example, to the frequency-only equivalent. This is largely due to the involvement of software elements as well as hardware, and the cross-over between the sync and data planes. It is possible to take a traditional building block approach to th