er Rx or Tx), SO they can work in simplex and duplex envi- ronments. Like the NPU, the structure of the traffic managers is based on Rx ports (one or two depending on the model) feeding the PISC programmable pipeline that takes care of classification and statistics counting. It now feeds an SAR module that outputs its work into a queue manager before the results go to the one or two Tx ports. The queue manager uses WRED and performs individual queue scheduling and shaping up to three levels. An embedded memory manager controls the inter- face to external quad data rate (QDR) SRAM and DRAM. A look-aside engine enables it to interface with an external coprocessor, SRAM, or TCAM again with the possibility of multiple accesses per processed packet. The queues are structured based on packets and different applications, and may require that the queues be combined upon specific structures. Such applications could be guaranteed- bandwidth VPNs or switch fabrics based on virtual output queuing. In a full-duplex OC-768 environment on the ingress side of a line card, the OC-768 framer through the SPI-4.2 interface connects to the NPUs (Rx port), which connects to the traffic manager (through the Tx ports). The traffic manager then connects onto the switch fabric interface. The egress side is the exact opposite. The fabric interface is connected on a traffic management chip, which is cascaded with the egress path NPU, which connects via SPI-4.2 with the OC-768 framer. The originally imple- mented SPI-4.2 interface (which the company has promised to replace with SPI-5 when it becomes available) enables the convenient structuring of the I/O bandwidth as several OC-192. This allows a better utilization of the chipset's computational power. OTHER APPROACHES To describe the approach taken by large network equipment vendors (NEVs), we will use Cisco as an example of a company that has been very active developing its own internal designs of network processors. The Cisco PXF chip (better known in the industry as Toaster) has been re