n. In this step, input samples are converter to LLRs. This step is implemented by executing the math as outlined above for L0, L1, L2, L3 in parallel on a set of 4x {I + Q} samples. The LLR generation process is not implemented by means of table lookups, but by directly implementing the required math. 2. LLR storage to memory. In the previous step, each output vector that is generated holds 8 X either {L0, L1, L2, L3}. These vectors are required to be stored in an interleaved manner, and with a limited LLR size (assume here 8 bit). Interleaving can be implemented using mask/shift/operations to truncate and combine the individual LLRs, or by using the <usri_n>instruction that does a vector shift/merge operation combining these instructions. 318 Open Radio Access Network (O-RAN) Systems Architecture and Design We do an inner-loop implementation that does not concern with the precision analysis and quantization boundaries but focusses on depicting an efficient implementation of basic math functions in the algorithm: void11r16(const int16_t*input, int bytes, uint8_t* output) { //uint16_t* out = (uint16_t*)output uint8_t* out = output; int i, j; // Gamma const int 16x8_t gamma = vdupq_n_s16 (32000) // Two over square root ten multiplied by gamma const int16x8_ttwo_square_ten_gamma=vdupq_n_s16(0xefff); = int16x8_t in; int16x8_t LzeroLtwo, LoneLthree; for (i=0; < bytes; i + = 16*1) { //load 1 X 16B at a time in=v1d1q_s16(input + i); //multiplywith gamma LzeroLtwo vqdmulhq_s16(in, gamma); LoneLthree = vsubq_s16(two_square_ten_gamma, vabsq_s16(LzeroLtwo)); // build 8 bit LLRs ann combine them, store to memory vst1q_u8 (out, vreinterpretq_u8_s16(vsriq_n_s16(LoneLthree,Lzeroltwo, 8)) ; ; // next set of input values out + = 16; This inner loop is quickly developed and can be used as an input for productized kernel development later by the software team. It is also an excellent benchmarking tool that can be used to compare device vendor performance. In this example, benchmarking shows 16 LLRs are generated in ~6 CPU clocks on