 network management Timestamping packets. Checking packet sequence. Policing ATM and frame relay at up to OC-48c rates. An 8-bit POS-PHY interface over which the ASI sends packets to the FPP and receives packets from the RSP. The ASI is connected to the host CPU by a PCI interface, which is a 64-bit, 66 MHz bus designed in a full master-slave implementation with full interrupt and direct memory access (DMA) support. Its support for SSRAM is based on two industry-standard, 32-bit-wide memory interfaces. The ASI's 8-bit CBI bus enables the initialization and configuration not only of the FPP and RSP, but also of six additional devices. It is interesting to note that it has been designed deliberately to be compatible with both Intel and Motorola bus formats, SO it enables the configuration of third- party devices such as framers or PHY interfaces. The CBI also loads the FPP and RSP chips with their corresponding programs and the dynamic updates to the FPP tables and RSP queues, respectively. The FBI is a 32-bit bus that extends the capabilities of the FPP by enabling the FPP to make func- tion calls that are executed by the ASI itself. These function calls can involve requiring the use of an ALU for a calculation and looking for access to data that is stored in SRAM, or it can be as all encom- passing as taking control of the FBI bus itself. Through several configurations of the leaky bucket (LB) algorithm, the ASI performs high-speed policing of ATM and frame-relay traffic. Its default configuration, for instance, uses the generic cell rate algorithm (GCRA) as defined by the ATM Traffic Management Specification, version 4.0. This works as follows: We saw earlier that the FPP is programmed in FPL. It is important that the FPL code can invoke functions that are sometimes executed on external hardware, thereby extending the capa- bilities of the FPP. At the same time, the ASI contains an ALU and an SSRAM interface state buffer, which are used to implement functions invoked by the FPL code. This means that when the FPL