parts ever tested is an AMD K-5 microprocessor (latchup threshold = 0.4 MeV-cm2/mg) fabricated on a very thin (2.5 um) epitaxial substrate [186]. This unexpected result indicates that SEL could become a serious concern for advanced devices that may be designed with very little margin to the latchup point. Other technology changes which decrease latchup susceptibility include the use of retrograde wells and trench isolation [188,189]. The effectiveness of trench isolation for decreasing latchup sensitivity depends heavily on the trench depth, with deeper trenches preventing latchup better than shallow trenches. In technologies such as CMOS/SOI or CMOS/SOS, the latchup path can be completely eliminated due to total dielectric isolation between adjacent devices [190]. Guard bands have been used to lower latchup sensitivity [180,191,192], as have neutron-irradiated substrates to kill parasitic BJT gain [193]. (Feature size shown in parentheses) (1.5 um) (1.8 um) (1.6 um) (2 um) (1.2 um) (1.6 um) (1.25 um) AMD K-5 (0.35 mm) Threshold LET for latchup (MeV-cm2/mg) Figure 4.2. Latchup threshold as a function of epitaxial layer thickness for several technologies [174]. The AMD K-5 is one of the most single-event latchup-sensitive parts that has been tested, even though it is fabricated on a thin epitaxial substrate. II-36 Single-Event Gate Rupture Dielectric breakdown can occur when the electric field across an insulating material exceeds some threshold value. When initiated by an energetic particle strike to the gate region of an MOS device, this phenomenon is referred to as a single-event gate rupture (SEGR). In this section we will present the basic mechanism for SEGR, and discuss recent results obtained in power MOSFETs and devices with thin gate oxides. 4.2.1 Single-Event Gate Rupture Mechanism Single-event gate rupture has been studied most extensively for power devices such as double-diffused power MOSFETs (DMOS), SO we will use this device for describing the SEGR mechanism. As shown in Figure 4.3, current flow in 