 8 (bit in 256QAM) X 8 (bit/LLR) = 11.7 Gbps. Note that this bandwidth is higher than the bandwidth between the DU and the RU. This LLR bandwidth is input to the HARQ combining and Forward Error Correction decoding stages. We will discuss HARQ in more detail later to explain how the peak bandwidth input to the Forward Error Correction decoder can be up to 3x the LLR bandwidth of 35 Gbps. Chapter 3 Hardware system dimensioning 117 Output from the LLR decoder can be calculated like the LLR rate but taking into account the Code Rate as 2 (layers) X 3276 (subcarrier/FFT) X 14 (symbol/slot) X 2000 (slots/ second) X 8 (bit in 256QAM) X 0.9 (Peak Code Rate approximation) = 1.3 Gbps. Above rate is assuming 14 occupied symbols/slot ignores Physical Downlink and Uplink Control Channels (PDCCH/PUCCH), reference symbols and other overheads. Assume approximately 20% reduction to define the MAC/PHY throughput at approximately 1 Gbps. Memory dimensioning Memory dimensioning needs to be done for both memory size, enough to accommodate the Operating System (OS), packet buffers, user contexts etc., as well as memory bandwidth to ensure that the system can sustain the Read and Write bandwidth demands of the applica- tion at peak throughput. Memory sizing DDR sizing is relevant for defining memory components to be used in the system. As an example of a low-end DU, we work through a numerical: os image-an embedded Linux image can most often be accommodated in approximately 0.5GB. We assume a similar memory requirement for the application images, approximately 0.5GB. Bulk U-Plane packet buffers can be implemented in the CU (dual/multiconnectivity) or DU component, depending on how the system is deployed. Buffer memory estimation can be done from the average (or peak) user data rate to be supported together with an indication of required buffer memory. As an example, assume the 500Mbps DU site throughput we estimated before with approximately 1 second of buffer memory of this throughput. This equates to approximately 500Mbit of buffer 