ts produce double bit error conditions, erasure correction can be utilized to remove the fixed errors leaving the single SEU induced bit error for the code to correct. In the case of memory systems in which large word size is constructed using several devices, each providing byte (8-bit) or nibble (4-bit) width segments, the potential exists for multiple bit error patterns in which the errors are all contained within the byte or nibble segment produced by one memory device. The single-byte-error-correcting (SbEC) code is capable of correcting all single byte error conditions; however, this code has poor performance in detecting any error pattern which spans more than one byte. Because SbEC codes do not detect most randomly occurring double-bit error patterns, most applications use the single-byte-error- correcting double-byte-error-detecting (SbEC-DbED) codes. Reed-Solomon codes are the general class of byte oriented codes; however, the code length constraints of RS codes prevent codes having 64 and 128 bit information lengths in usable byte definitions. Kaneda and Fujiwara have developed a class of SbEC-DbED codes having arbitrary code and byte length. A further extension of this technique is to provide a class of codes which possess the property of single-bit- error-correction, double-bit-error-detection, and single-byte-error-detection (SEC_DED_SbED). Table 6-3 indicates the properties of several of these codes. Utilization of EDAC techniques in high-speed processor memory systems typically employs either a hardware or software provision which enables all locations within the currently used address space to be subjected to periodic verification. This provision requires periodic read access of all memory locations and examination by the EDAC protection to prevent the accumulation of single errors from exceeding the capability of the code to perform error correction. This procedure is usually termed "washing" or "scrubbing" the memory subsystem, and is usually performed under hardware control by an application s