traditional software-based protocol implementation versus integrated hardware- assisted acceleration in a chip. When coupled with a few ancillary and specialized chips, this can help provide cutting-edge performance at line rates. The following are a few other important systems issues to consider when implementing an inte- grated TOE solution: Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. STORAGE NETWORK PROCESSORS (SNPS) NETWORK PROCESSORS In a board implementation, when the TOE implementation has to go off-chip to retrieve that session data, a severe time penalty occurs. This immediately translates into lower performance (latency and throughput) from the SNP device. An ASIC approach of the TOE solution, on the other hand, can combine embedded memory. This has a tremendously positive impact on the latency and through- put performance, along with the other parameters from the previous list. More importantly, to avoid making multiple visits to the memory bank to retrieve session-specific data, state-of-the-art TOE implementations utilize embedded content-addressable memory (CAM). The use of CAM enables a single memory lookup to retrieve all pertinent data that has been properly indexed. It is a key tech- nology for the acceleration of TCP termination. A certain degree of parallelism is more than warranted in this application. Instead of having one single CPU sequentially deal with different parts of TCP processing for different sessions (no mat- ter how powerful it is), it is much more efficient for multiple parallel CPUs to tackle TCP process- ing for different sessions. One CPU can handle checksum processing for one session, while another CPU can reorder data for yet another session. A third CPU can handle TCP flow control or be involved in the startup process for a new TCP session. This is an easy way to enhance performance in the TCP ter