memory 62Mbyte. Assuming static buffer sizing (say, 2KB buffer storing a 500 byte packet), this equates to approximately 0.25GB. HARQ buffer memory is dimensioned as (more detail later) as 8 (maximum HARQ processes) X 64 (active users) X 2MB (TB HARQ buffer) or approximately 1GB. Aggregate memory requirements are approximately 1GB for the OS, approximately 0.25GB for packet buffering and 1GB for HARQ buffering. Rounding up to power-of-two numbers, 4GB of DDR memory is chosen. Life-of-a-packet memory bandwidth analysis An often-overlooked aspect of performance is DDR bandwidth consumed by the system. All practical Linux based systems as used in CU and DU applications use an external DDR 118 Open Radio Access Network (O-RAN) Systems Architecture and Design memory for storing both instruction and data. Most modern processors have a cache-based memory hierarchy where both CPU access to external memory and often also accelerator and IO traffic access to external memory is shielded by on-chip cache memory that reduces the bandwidth to external memory and provides a lower (average) latency to instruction and data access, thus improving performance. A generic System-on-Chip (SoC) architecture shown in Fig. 3-9 below. We identify three levels of cache: Ll cache, separate for Instruction and Data storage. This cache memory is local to the CPU only and characterized by very low access latency (single digit clock cycles from the CPU). Typically dimensioned to small values such as 32 or 64KB. L2 cache, which is typically shared by a group of CPUs (cluster) with slightly higher latency of 10 seconds of clock cycles for CPUs within the cluster (or more for access by a CPU from a different cluster). Typically dimensioned to few 100 KB or up to several MB across multiple CPU clusters. L3 or platform cache which is either integrated into the SoC interconnect or implemented as part of the memory controller to offload DDR traffic explicitly. This cache has higher latency and is dimensioned to multiple MBs in higher-end chips. Lower-