ed into the correspon- ding intended output ports. The control module can often be easily reloaded to reflect new executable code that manages different QoS requirements. The size of the shared memory can be shown to directly influence the possibility and rate of cell loss, SO this is a rather convenient situation for the designer. 15 Also the memory technology the implementation of the actual shared memory is one of the fundamental constraints of the formance of such a switch fabric by the mere fact that all operations of the fabric will invariably revolve around writing to and reading from the shared memory. Consequently, memory access times are important. This can be a problem if the chosen memory technology does not allow data to be writ- ten into the shared memory N times faster than the rate at which data arrive at the N inputs. In terms of scalability, as the Figure 14.10 shows, multiple switch fabric cards can be used, which combined with the striping (IBM calls it byte slicing) of frames/cells (similar to the striping concept discussed in the context of data storage in Chapter 11, "Storage Network Processors," where reviewed storage network processors) across multiple fabric cards allows an easy performance scaling. The advantages of this technology include the in-service scalability, cost efficiency (as no external memory is required), and relatively easy implementation without a complex centralized scheduler like those needed in the input- or output-buffered approaches. Some vendors claim this approach has a serious drawback. This has caused many designers to worry each time they are asked by a vendor to stripe data. If striping is implemented across multiple serdes lanes, then a designer needs to worry about what happens when even one serdes in the set fails. In some design implementations, this problem will prevent the other serdes lanes in the set from car- rying any traffic. This will force the entire system to switch over to the backup fabric plane. This lat- ter combination of possibilities is ex