y Transmit Physical Logical Scheduler Block from And Block SDRAM Block Block Update (b) Scheduling, Modifying & QoS and Transmitting a PDU Block CoS for the flow FIGURE 7.4 Queuing PDUs and block scheduling. (Source: Agere) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. AGERE PAYLOAD PLUSTM FAMILY OF NETWORK PROCESSORS 111 PDU Data & Classification SDRAM SSRAM POS-PHY/ Conclusions UTOPIA Data Output Stream Input Output Editor Interface Assembler Interface Compute Mgmt. Output Buffer POS-PHY Transmit Conclusions Management Request Transmit Queue Traffic Traffic Queue Logic Manager Shaper Manager Compute Logic Compute Engine Engine Scheduler / External Scheduling Queue Entry Link List Parameter SSRAM Interface SSRAM SSRAM FIGURE 7.5 The internal block structure of the RSP chip. (Source: Agere) of the three VLIW compute engines that we just mentioned. By selecting a queue definition that performs the desired processing, the RSP can execute multiple protocols. The external host CPU can be used to dynamically add queue definitions, as needed, to set up ATM virtual circuits, for example. To execute code, the compute engines must be properly configured. This means that a program, along with the necessary parameters, must be loaded at configuration time or dynamically during operation. The number of compute engines configured depends on the operation of the system, size of the engine code, and the available internal RAM. Channels and physical ports are configured first. Then logical ports are configured and assigned to the physical ones. After these steps are completed, the desired compute engine program is loaded. The next step is the creation of schedulers for each logical port. The definition of each logical port includes the program selection that will handle traffic management, policy, and shaping, as desired. The compute engine programs are lo