h can span different physical topologies (such as rings). No parts of the synchronization network should operate isolated from the master clock. During cases of clock reference failures (due to any faults in the transport or the network), the clock nodes should be able to rearrange themselves such that there exists a new master clock on the top of the newly formed tree. This new master clock may receive a reference clock signal from an alternate source or supply a good quality holdover (such as an SSU/BITS clock with stratum 2 performance). A clock should never lock to a reference of lower quality. If a case arises where only a clock of lower quality is available, even during physical link failures, this clock should revert to a hold- over mode of operation. Loops in the timing signal must not be present nor be allowed to form following failures. More on this in the upcoming section "Timing Loops". The lengths of the branches of the synchronization tree are kept as short as possible. This branch length refers to the synchronization links between SSU/BITS and EEC/SEC nodes con- nected to each other in the network chain. The longer the path through a specific synchroniza- tion chain becomes, the more susceptible it will be to impairments and wander accumulation. While some of these points are very specific, the last point provides a general guideline. Each clock node adds its own noise (different types of errors) while recovering the reference clock signal and before passing that signal to the next clock. So, any errors that arise accumulate over the chain-the longer the chain, the more error. Refer to Chapter 5 for descriptions of parameters defining clock performance and error. Besides the general guideline of keeping the network chain as short as possible, ITU-T G.803 also defines the maximum number of nodes that can exist in such network chain. These limits on the number of nodes in the chain are also shown in Figure 6-10 for each clock type. The main points of the synchronization reference network chain (from 