ADE-OFFS WHEN DESIGNING WITH INTEL NPUS Intel IXA network processors work together with several other Intel families of chipsets in various complementary technologies to produce working systems that are straightforward to design because they all essentially share common interfaces: Embedded Intel architecture control processors improve the scalability of the design while provid- ing broad software support in communications environments. Intel media signal processors can be used in conjunction with NPUs for applications such as voice over IP (VoIP), as shown in Figure 5.8 and discussed in this section. Intel I/O processors are extensively used for networked storage applications. Intel provides a very broad line of framers, media access controllers, and even physical (PHY) layer devices. These features significantly facilitate the overall systems design process. Designing systems with Intel's network processors implies that in high-speed links, one NPU is required for the ingress (receive) path and another is required for the egress (transmit) path. This is a characteristic of the whole family and not just of one of the network processor chips that Intel pro- poses. In certain applications, however, a single Intel network processor may be adequate for the avail- able traffic load. For example, a single network processor is adequate for a VoIP gateway that works up to an OC-3 (155 Mbps) capacity, as shown in Figure 5.8. This gateway system is connected on one side on multiple Gigabit Ethernet (1000Base-T) and Fast Ethernet (10/100 Base-T) media and on the other side on the Public Switched Telephone Network (PSTN) through a time division multiplexing (TDM) backplane that transfers voice channels. In this example, based on an Intel reference design, voice is carried over IP packets coming in from Ethernet and Gigabit Ethernet links. After the respective PHY and MAC stages of their reception (which is handled by other convenient Intel chips, as shown in the Figure 5.8, and require no other glue logic around them), the 