ted to subsequent regenerators where it follows that any jitter suppressors or data buffers will need to be may combine with any locally generated timing variations to cause designed to deal especially with low frequency jitter, thus they may an overall accumulation of jitter. When assessing the effect of this need to store large numbers of consecutive data bits SO that slow jitter accumulation in a self-timed system, two inter-related factors timing variations can be smoothed out. have to be taken into account. These are eye jitter and clock edge jitter and are depicted in Figure 28.14(h). Eye jitter is a direct 28.4.6 Jitter specifications consequence of any timing variations already present on the incom- ing data signal. Clock edge jitter arises as described in the previous Specifications for jitter accumulation in digital systems have to take section (which refers to Figure 28.14(a)) except that now a contribu- account of the low frequency build-up implied in Figure 28.16. A tion will also be made to it by the incoming data signal. typical specification for jitter limits for a digital transmission system The decision making process at the regenerator may not be as comprising many regenerators is given in Figure 28.17 where peak- difficult as implied by Figure 28.14(h). The extracted clock will to-peak jitter, expressed in clock periods, is plotted against jitter tend to follow any phase variations in the incoming data. What frequency. (It should be noted that r.m.s. values will be typically a matters as far as the instantaneous signal-to-noise ratio and so factor of ten less than these figures.) This representative example is decision error probability is concerned, is the relative timing of a loosely based on figures given in CCITT Recommendations G823 particular decision instant. That is, the difference between the time position at the clock edge with respect to the optimum decision time for the particular incoming data symbol. Although this jitter track- ing may help the decision making process at a partic