per Saddle River, New Jersey: Prentice-Hall, 1999). Michael Keating and Pierre Bricaud, Reuse Methodology for System-On-A-Chip Designs (Boston: Kluwer Academic Publishers, 1998). Thomas Kropf, Introduction to Formal Hardware Verification (New York: Springer-Verlag, 2000). Rochit Rajsuman, System-on-a-Chip: Design and Test (Boston: Artech House, 2000). Prakash Rashinkar, Peter Paterson, and Leena Singh, System-on-a-Chip Verification-Methodology and Techniques (Boston: Kluwer Academic Publishers, 2000). Wayne Wolf, Modern VLSI Design: System-on-Chip Design, 3rd ed., (Upper Saddle River, New Jersey: Prentice- Hall, 2002). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES 189 Exploring some old concepts (and once considered heretic approaches) that now seem to come back to life with cutting-edge advantages that they offer, asynchronous interconnects inside an SOC allow the integration of multiple IP cores in unusual new designs using methods that are the complete opposite of today's best-design practices that have been taught at electrical engineering departments worldwide during the last 25 years and that have been systematically practiced in the industry SO far. The following sources provides good coverage of this new school of thought: John Bainbridge, Asynchronous System-On-Chip Interconnect, CPHC/BCS Distinguished Dissertations (New York: Springer-Verlag, 2002). More information for this type of technology can be found from research done at Sun Microsystems at the web site http://research.sun.com/features/tenyears/F3Async1JB.html The following is a nice book that is focused on the issues surrounding integration of ARM RISC cores into larger designs, but it also discusses the ge