integrated into the APP550, along with Ethernet Media Access Control (MAC) controllers and 3MB of on-chip DRAM. The APP550 inter- faces to the line and to the fabric side through standard GMII/SMII or POS-PHY/UTOPIA interfaces. At the same time, it can be interfaced with a supervising host CPU through a PCI bus and with exter- nal optional coprocessors through a standard POS-PHY interface. Figure 7.8 also shows the data path through the APP550 and the internal architecture of this highly integrated network processor. For fast table lookup, the APP550 uses FCRAM, which is a fast-cycle DRAM and which offers SRAM-like performance at DRAM prices. This means that for memory clock rates of 200 to 400 MHz, the network DRAM can achieve data rates equivalent to 400 to 800 MHz. Agere already has several large memory suppliers (such as Samsung, Fujitsu, and Toshiba) signed up and committed to the FCRAM used by its APP550 and APP750NP/APP750TM chips. The use of DRAM for the table lookup function saves significant cost and power and greatly increases the capacity compared to the Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. AGERE PAYLOADPLUS FAMILY OF NETWORK PROCESSORS AGERE PAYLOAD PLUSTM FAMILY OF NETWORK PROCESSORS POS-PHY/ Utopia GMII/SMII Buffer 32-bit POS-PHY/ Input I/F to PHY Utopia Buffer Scheduler/ Stream GMII/SMII Coprocessor 32-bit Manager Interface Shaper Editor to fabric POS-PHY Packet Processing Output I/F 32-bit Engine (PPE) Coprocessor Interface 32-bit POS-PHY Statistics Policing PCI-bus to supervising host FIGURE 7.8 The internal architecture and data path of the APP550 network processor. (Source: Agere) use of CAM or SRAM. FCRAM is used to provide a system with storage capabilities for high-den- sity interfaces, such as tree memory, packet buffering, and data modification parameters. It is charac- terized by less power consumption th