ks.com) is yet another promising startup. It combines the offloading of TCP termination with IPsec in the same silicon die, allowing gigabit-per-second-level performance and processing at wire speed. Chapter 17 discusses such approaches in more detail. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. STORAGE NETWORK PROCESSORS (SNPS) 216 NETWORK PROCESSORS SUMMARY In this chapter, we discussed the need for SNPs, which are used to ensure fast and adequate process- ing of data traffic transmitted on a whole new generation of SANs using IP technologies. We discussed the evolution of storage technology, which in its more recent forms, serves as the catalyst for the appearance of several of these chips and board-level products. We reviewed the requirements they called to satisfy as well as the capabilities that they exhibit. We briefly reviewed a few cutting-edge technological approaches by leading companies at various levels of integration. To set up the discus- sion in Chapter 17, we provided an overview of communications and information security concerns that these SNP chips are required to handle on top of their expected network-processing operations. SUGGESTED REFERENCES Refer to the companies' web sites provided throughout the text to find more information about com- panies that design specialized board products and/or network-processing chips. Aristos Logic (www. aristoslogic.com) and Astute Networks (www.astutenetsworks.com) are two additional companies not mentioned in the text. Hifn (www.hifn.com) and NetOctave (www.netoctave.com) are two security coprocessor design companies involved in SNP projects and plans. References for more similar design houses, whose business emphasis might also eventually include the secure SNP arena, are listed at the end of Chapter 17. Several white papers have been written covering all aspects of IP storage 