l Hierarchy (SONET/SDH) framers (155/622 Mbps). Integrated coprocessors handle classification and traffic management, but an externally connected Q-3 chip from Motorola can handle traffic management, offering multilevel hierarchy scheduling and support for up to 64K queues. Motorola is positioning the next-step-up product-C-5-for a wide range of network applications around the OC-12 level. The latest product-C-5e-is geared for the OC-48 realm. The potential applications include multiservice access platforms (MSAPs), edge routers, digital subscriber loop access multiplexers (DSLAMs), wireless base stations, cable head ends, load balancers, web switches, and SO on. The company's publicized product roadmap indicates that the C-10 and Q-10 chipsets will be introduced in 2003 to handle 10 Gbps of sustained throughput. Motorola is not present in the 40 Gbps realm yet. The family contains two additional chips: the Q-5 (a traffic manager) and the M-5 (an interface- adapter chip that enables full-duplex and channelized OC-48 applications for the C-5e). The Q-5 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. MOTOROLA'S C-PORT™ FAMILY OF NETWORK PROCESSORS 124 NETWORK PROCESSORS provides fine-grained traffic management by handling relevant issues such as traffic policing, shap- ing, and scheduling. The C-5 has a throughput of 5 Gbps and is available in the following clock frequencies: 166, 200, and 233 MHz. The more recent C-5e is clocked at 266 MHz. The C-5 is offered in an 840-pin high thermal coefficient of expansion ceramic ball grid array (HiTCE CBGA) package. Typically, it sumes 15, 17.5, and 20 watts respectively with its three available clock frequencies. The HiTCE mate- rial out of which the package is built has the unique characteristic of expanding thermally at the same rate as a typical printed circuit board (PCB). This accounts for the exc