is a current (low impedance) phenomenon, 23.12 Circuit design and layout and it increases with increasing current in the source circuit. Electric induction, or capacitive coupling, is a voltage phenomenon and The most fundamental point to consider in designing for EMC is the occurs when changing electric fields from the source interact with circuit's grounding regime: the majority of post design interference the victim circuit. The induced voltage due to a sinusoidal voltage problems can be traced to poor grounding. Printed circuit layout V of frequency f on the source conductor coupled through a mutual also has a significant impact. The common underlying problem is capacitance C farads is given by Equation 23.4 where Z is the that all conductors have a finite impedance which is predominantly impedance to ground of the victim circuit. inductive above a few kHz, and SO increases with frequency. Since EMC phenomena are critical at higher frequencies, two physically volts (23.4) separate ground points cannot be regarded as being at the same potential unless no current flows between them. Ground tracks must be treated as low impedance routes by which return current is Mutual capacitance between conductors depends on their distance encouraged to flow (Ott, 1979), rather than as equipotential circuit apart, respective areas, and any dielectric material or electric reference points. The principles to follow in this regard are to: screening between them. In some cases, component or cable manu- facturers provide figures for mutual capacitance. It is generally in 1. Identify the circuits of high di/dt (for emissions) e.g. clocks, bus the range 1pF to 100pF for typical circuit configurations. buffers and drivers, high-power oscillators. 2. Identify sensitive circuits (for susceptibility) e.g. low level analogue and fast digital data circuits. 23.11.2.1 Electromagnetic induction 3. Minimize their ground inductance by minimizing the length and enclosed area of their circuit traces or wires, and/or using When the source and vi