s able to contain an array of up to 2,048 processing elements (PEs). Each PE can execute several simple tasks in parallel and can therefore be roughly seen as the equivalent of a small VLIW engine. If the maximum number of PEs inside an MTAP sounds impressively large, it is. However, some basic characteristics of the PE structure enable the deep levels of integration that the company's IP can achieve when it is synthesized against various foundry technology libraries. More specifically, the data path of the PEs is 8 bits wide (as opposed to the typical case of 32- or 64-bit RISC cores). They only contain a small and efficient arithmetic logic unit (ALU), a register file, and local memory. If necessary, some of them can also offer special extension capabilities such as a hard- ware-based multiplier-and-accumulator (MAC) module used in DSP algorithm implementations. (This brings to mind the applicability of the technology in TDM-based voice applications such as voice coding and echo cancellation.) Another significant characteristic of the PE structure facilitating large-scale integration is that PEs do not contain their own instruction fetch and decode units. Instead, the MTAP has a centralized Downloaded from Digital Engineering Library McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES 166 NETWORK PROCESSORS ClearConnectT bus Parallel Parallel External Coprocessor Coprocessor Processor Interface e.g. TLE, etc. FIGURE 10.1 The architecture of the ClearSpeed IP technology. (Source: ClearSpeed) control logic that according to the fundamental principle of SIMD architecture, fetches, decodes, and then issues one instruction, which is broadcast to all the PEs to execute on their own set of data. The MTAP processor assigns packets to the individual PEs. All the PEs inside the MTAP have to execute the same common i