iques Like almost any single-event effect, techniques have been developed to mitigate the occurrence of SEL. One difference with SEL is that since latchup can also be initiated by electrical signals in normal terrestrial ICs, it is not unique to the space environment. This means that high-volume commercial IC manufacturers also have to deal with latchup on their own accord. Unfortunately, it does not follow that just because an IC is latchup immune in normal environments it will also be latchup free in space [174]. However, the same general techniques that improve latchup characteristics on the ground can usually be expected to improve the SEL response in space environments. The keys to decreasing latchup susceptibility are to decrease the ability of the parasitic BJTs to become forward biased, and to decrease the current gain of the BJTs should they become forward biased. Factors which make it harder to forward bias the BJTs include increasing the substrate and well doping levels (heavier doping decreases series resistance and hence limits II-35 voltage drops) and increasing the well thickness (thicker decreases resistance and again limits voltage drops). Using an epitaxial substrate can decrease latchup sensitivity both by limiting the charge-collection volume, and by decreasing the substrate series resistance. Increasing the spacing between devices lowers the current gain of the lateral BJT (basically by increasing the base thickness), and increasing the well thickness can do the same for the vertical BJT. While at first it seemed that fabrication on epitaxial substrates was enough to eliminate latchup, this can no longer be considered to be the case. Figure 4.2 shows a compilation of data where the latchup threshold LET for several devices and technologies is plotted against the epitaxial layer thickness. The data were compiled from [186,187] after the method of [174]. Because latchup depends on a diverse set of process and layout parameters, there is no clear trend, and in fact one of the most SEL-sensitive 