en the fact that the aggregate bandwidth of the NP4GS3 is 4 Gbps), 2 full-duplex switch fabric interfaces, and separate interfaces to 10 external memory banks. These interfaces can support up to eight double data rate (DDR) synchronous dynamic random access memory (SDRAM) ports and two zero bus turnaround (ZBT) static random access memory (SRAM) ports. The NP4GS3 offers sophis- ticated capabilities in terms of hardware-based scheduling, policing, and flow control, including the Shock-Absorber Random Early Detection (S-RED) algorithm. IBM claims that S-RED is more ele- gant, dynamic, and efficient in its ability to self-adjust to different traffic rates as well as handle peak traffic flows than the traditional weighted random early detection (WRED) algorithm. Therefore, IBM has been pushing for the industry-wide acceptance of this algorithm through the Institute of Electrical and Electronics Engineers (IEEE) standardization process. The NP4GS3 can easily cope with a single OC-48 channel or up to 40 Fast Ethernet 100 Mbps ports. Alternatively, it can be configured to handle a fat pipe in an OC-48c configuration. In each NP4GS3 NPU, the 16 parallel coprocessors (picocode processors) and the 9 available hardware- assisted coprocessors (one for each of the 16 parallel picocode processors) provide in total a stagger- ing 2,128 millions of instructions per second (MIPS) of processing power with 32K words of internal instruction memory. Its flexibility is driven by picocode and application software rather than any application-specific integrated circuit (ASIC) components. Scalability was one of the highest priorities for the IBM designers. As a result, the NP4GS3 proces- sor can be connected in series with another NP4GS3 chip as shown in Figure 4.1 using the switch fab- ric interfaces under the control of the PowerPC 405 core in one of the two NPUs. This scheme effectively doubles the bandwidth of the system. This brings the NP4GS3 extremely close to 10 Gbps, which is the next expected equipment performance milestone. IB