 traffic that just arrived from the crossbar switch- ing stage over multiple 2.5 Gbps links, keeping in mind that link groups provide a dynamic bandwidth allocation. Traffic is then buffered and queued. As in the ingress mode, not only is traffic isolation and fairness present, but a QoS-capable scheduler serves all the queues. The PI40X's embedded memory provides room and capabilities for unicast and multicast cells similar to those found at the ingress mode. The PI40 family offers a modular, scalable switch fabric design because it can be configured eas- ily as a single-chip 40 Gbps switch or as a multistage system in a larger switch configuration up to 1,024 fabric ports. One of the nice characteristics of the family is that the ultimate chip count needed for a multistage solution increases linearly with the desired capacity growth. Switching is protocol independent and can be programmed to switch cell payloads of variable size (64, 72, or 80 octets). All switching cell headers contain information that is exclusively used by the switch fabric. A user's protocol-related data are encapsulated deep inside the payload of the fabric cells. TABLE 14.1 Configuration Examples of Switch Babrics based on Agere's PI40 Family Number of Ports Number of Chips Capacity OC-768c OC-192c OC-48c OC-12c PI40X PI40C Total 40 Gbps 80 Gbps 160 Gbps 320 Gbps 640 Gbps 1,024 1.25 Tbps 2.5 Tbps * Requires the single chips PI40SAX Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SWITCH FABRICS 300 NETWORK PROCESSORS In the PI40 switch fabric family of chips, which implements an arbitrated crossbar design, a sophis- ticated queuing structure ensures that no HOL blocking occurs and that native support is available multicast traffic. The availability of four different buffer management classes and two different sched- ulers, in conjunction with end-to-end flow control a