 Typically higher data rates Devices are more expensive Lower output swing requirements Board space Generally lower electromagnetic emissions Difficult to implement Synchronous clock is the standard architecture used in many low and medium data rate systems. The design is implemented utilizing a single clock source that provides timing for all components requiring a clock. This means that all devices throughout the system receive the clock at the same time. This implies laying out clock lines of equal length to each device. Careful layout, system timing analysis, and minimization of clock skew are critical to this design. Source-synchronous clock architecture uses a clock generated at every driver to toggle the receiving device. This is implemented by laying out a clock line between every trans- ceiver and driver receiver pair that passes data. To ensure correct timing, the clock lines must be the same length and have the same loading as the data lines. A system master clock is normally used to retime received data coming out of backplane boards. Since timing is now "relative" from each driver to each receiver, much of the system latency is removed as compared to a synchronous system. Data can be passed between system devices without regard to clocking times of other components in the system. The benefits of this design are a significant increase in throughput and a potential for larger backplanes, because of the elimination of latency and speed issues associated with synchronous designs. The draw- back is a significant increase in clock lines-one set for each pair of data-linked devices. Asynchronous system architecture does not use a clock. Instead of clock-synchronized data, a local "handshake" protocol between the driver and receiver is implemented. There are many different design approaches for this protocol. One example is a request signal from the driver to send data, followed by an acknowledged signal from the receiver when the data is processed. Asynchronous design can be complex and is often unique for 