 architecture that is composed of structured combinations of RCU- RSF clusters. (Source: Cognigine) programmable flash-memory controller for system boot operations. It is interesting to note that the SRAM peak bandwidth is 76 Gbps, whereas the peak DDR SDRAM bandwidth is 100 Gbps. The Cognigine network processor is available in a 1,517-pin HFC-BGA package. The picture is completed with a GUI-based integrated development environment that offers a sin- gle-processor programmer's model; therefore, the software engineer does not have to worry about allocating tasks to specific engines. The development environment contains an application configu- ration tool as plenty of software components function on-chip, such as framing, parsing, traffic man- agement, accounting modules, and SO on. There is also naturally a C/C+ + compiler, assembler, and debugger for code development; a clock-accurate software simulator; and a services library that facil- itates the tackling of issues such as fabric access, parsing, traffic management, and SO on. EZchip TOPcore TM EZchip (www.EZchip.com) is an Israeli company that has very strong ties to IBM (EZchip's silicon foundry and strategic investor). It is poised to have a very significant impact on the evolution of the Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES OTHER NPU ARCHITECTURES 149 network-processing industry as it has developed extremely integrated products that eliminate multi- ple chips for the realization of complete switching cards. The company's current products include the NP-1 (a 10 Gbps seven-layer network processor), the NP-1c (a second-generation 10 Gbps network processor), and the QX-1 (a 10 Gbps traffic manager). It also provides the necessary software devel- opment infrastructure around these chips. The company's NP-1 is a single-chip, full-duplex NPU with embedded s