the DMOS structure is vertical rather than lateral as in a standard MOSFET [194,195]. Application of a positive bias to the gate in this channel DMOSFET inverts the p-body region to form a channel between the in-source at the top of the structure and the drain (substrate) contact at the bottom of the structure. To handle large currents, the full structure usually contains hundreds or thousands of these cells connected in parallel. The thick lightly-doped epitaxial region allows the power MOSFET to sustain high voltages without breakdown. When an ion strikes the neck region through the gate oxide, SEGR can occur as charge is transported near the Si/SiO2 interface. As charge from the ion strike accumulates underneath the gate region (and depending on the gate bias), the electric field in the gate insulator can temporarily increase to above the critical field to breakdown, causing a localized dielectric failure (i.e., an SEGR). The SEGR response in vertical power MOSFETs has two components [196]. The "capacitor response" describes the interaction of the ion directly with the gate dielectric, inducing an oxide breakdown at a lower field than would occur in the absence of the ion strike. If a drain bias is applied when the ion strike occurs, part of the drain voltage lon Path Source holes electrons n epilayer n+ substrate Drain Figure 4.3. Structure of a vertical power MOSFET and current flow paths following a heavy ion strike [195]. II-37 may be transferred through the epitaxial layer to the gate interface [194]. This part of the response is referred to as the "substrate response." Increasing the gate voltage increases susceptibility to SEGR through the capacitor response by increasing the pre-existing electric field in the oxide. Increasing the drain voltage also increases the susceptibility to SEGR because part of this voltage can be coupled to the interface through the substrate response. 4.2.2 Single-Event Gate Rupture in Power MOSFETs Typical SEGR data taken for vertical power MOSFETs include the critical field 