ebsite. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES library, and even power consumption factors are judged fairly. If they are not, a very erroneous set of conclusions can be reached. In other words, if core A implemented in 0.13 um CMOS library matches the performance of core B when it is implemented in an 0.18um library, you cannot just brush the underlying silicon technology issue aside and state shamelessly that the two cores perform identically. In a similar example with different parameters, if you compare a 1 GHz off-the-shelf processor X with a 200 MHz IP core Y and state that the former wins by a factor 5 in throughput, it may not be a File Edit View Program Commands Status Source Data Performance Lookup break Watch Print Display BEGIN("main") int i,ComponentIndex; int Oracle=0; /" Oracle means that we use the lexer interactively */ MakeImage(); /* Construct the image structures / MakeFrame() MakeScan() Dump of assembler code from 0xa912 to Oxaa12: 0xa912 <ChenDct+6> s321 a3, al, 0x88 Interrupt 0xa915 <ChenDct+9>: movi.n a15, 0 0xa917 <ChenDct+11>: addi.n a14, al, 4 Step Stepi 0xa919 <ChenDct+13>: al, 0x90 Nexti 0xa91c <ChenDct+16>: a14, al, 0x84 0xa91f <ChenDct+19>: a4, a15, 1 Until Finish 0xa922 <ChenDct+22>: add.n a8, a14, a4 0xa924 <ChenDct+24>: 132i.n a6, a8, 0 0xa926 <ChenDct+26>: a5, a8, 0x70 With cache attribute 1503461 18.37 12.56 ) Stores 592465 4.95 ) With cache attribute 592465 4.95 ) Dcache Load misses 0.00 ) 0.00% of loads Dcache Store misses 0.00 ) 0.00% of stores Dcache Load allocations 0.00 ) 0.00% of loads Cycles: total = 11973410 Summed Summed % Cycle % Cycle Instruction fatchor 7775072 Taken branch Performance Profiling Source intel Flat profile: Icache allo cumulative total Dcache load time Kcycles Kcycles calls K/call K/call 14.49 1734.66 1734.66 73754 divsi3 12.66 3249.18 1514.52 Quantize Time for Simu 4415.94 1166.75 ReadXBuffer 5403.87 987.93 0.96 BoundDctMa