 are caused by charge deposition by direct ionization from heavy ions, and indirect ionization from protons and neutrons. The deposited charge can be collected by drift and diffusion in semiconductor devices, causing current transients that can result in circuit malfunction. Funneling can increase the charge collected due to drift processes, and is especially important for DRAMs and devices not fabricated on epitaxial substrates. In SRAMs, voltage transients can cause upsets by mimicking the write process. In complex and high-speed circuits such as microprocessors, even a momentary glitch can propagate through an IC to cause upsets. SEUs are not unique to digital circuits, and have been observed in analog devices. Multiple-bit upsets occur when more than one bit in a digital circuit is upset by a single particle strike. Mitigation techniques for SEU include system-level methods such as error detection and correction, lockstep execution, and redundant systems using voting. Circuit-level methods are also effective, and several SEU-hardened latch designs have been proposed. These techniques have the advantage of allowing the use of commercial fabrication technologies, but usually lead to greatly increased transistor counts. Traditional radiation-hardened circuits use process techniques such as lightly-doped polysilicon feedback resistors to provide SEU immunity. While very effective, passive feedback elements reduce circuit performance and degrade IC manufacturability. SEE can also cause permanent failures in ICs, such as single-event gate rupture (SEGR), burnout (SEB), or latchup (SEL). Latchup is a concern for any standard CMOS technology, and can be triggered by particle strikes in ICs that are otherwise immune to electrically-induced latchup. Thin epitaxial substrates are usually effective at limiting SEL, but recent data indicate that this may not always be the case. Lower supply voltages in the future may reduce the SEL susceptibility of low-power ICs. SEGR, long a concern for power devices, is a possible conc