r year FIGURE 5.39 Shrink of the characteristic dimensions of CMOS in time and indication of the main technology nodes of the last 10 years. (After Parthasarathy, S. E. and Thompson, S., Mater. Today, 9(8), 20, 2006.) Telecommunication Networks The gate length reduction is expected to decrease the time constant associated to the gate of each MOS increasing the circuit speed. The electronic charge associated to the gate is smaller, thus a switch operation is expected to burn less power. More circuits fit on the same wafer area, thus a circuit cost is expected to decrease. 5.7.1.1 CMOS Speed Evolution up and beyond the 32 nm Node As far as the intrinsic RC circuit represented by the transistor gate is dominant over all the spurious RC contributions, the decrease of the gate length is directly related both to the switching speed of the transistor and to the power consumption. Just to carry out an order of magnitude evaluation, both the capacitance and the equivalent resistance of the CMOS depend on the linear dimensions of the components. Assuming that the material does not change and that all the dimensions but the gate depth scale proportionally (both are in reality not true) in a very first approximation we can write (5.33) R=Rp+p (5.34) where Cp and Rp are the parasitic capacitance and resistance E0 is the dielectric constant of vacuum K is the permittivity of the material filling the gate P is the resistivity of the doped silicon electrode W, L, d are the spatial gate dimensions, d being the depth, l the electrode equivalent length, W the electrode width, and A its equivalent section If all dimensions scale with the same constant the second term of both Equations 5.33 and 5.34 scale with L, while it is expected that the parasitic term increases, decreasing the characteristic dimensions of the CMOS. Thus, as far as the parasitic elements can be neglected, it is (5.35) Since the depth of the gate does not scale and A is also proportional to d, the second term of Equation 5.35 would increase almost as the inverse 