ves (that is, have zero disparity) are to be preferred Many line codes, designed to meet the requirements of a variety of in that a single input-to-output mapping is sufficient. However, transmission systems are known. Useful surveys, together with there will only be a limited number of these and so the table has to references to further details, are to be found in for example (Duc and be completed by using non-zero disparity pairs where members of Smith, 1977; International J. of Electronics, 1988; Bylanski and each pair have a disparity of opposite sign. The selection of output Ingram, 1987). A rather different approach suitable for high bit rate words is then made on the basis of minimising the cumulative systems which currently require simple encoding and decoding disparity. It follows that some possible output words will not be procedures is to be found in (Fair et. al., 1991). 28/12 Digital transmission delay T/2 Figure 28.12 Duobinary, a partial response code: (a) step input to channel; (b) channel equaliser response; (c) binary input; (d) pre-transmit coding; (e) waveform for pre-transmit coding; (f) received signal; (g) decoded output Clock extraction passed on via the regenerated data stream to the next repeater. Thus the locally generated phase jitter will combine with the incoming 28.4.1 Self-timed systems signal jitter, a situation which will lead to a progressive build-up of jitter at subsequent regenerators. Careful design is required to en- sure that this potential timing problem remains within acceptable Clock extraction, (known also as timing recovery or bit synchroni- bounds. sation), is the process by which a digital regenerator obtains a synchronising signal which enables it to optimise the timing of its decision making process. (Decision making and its relationship to 28.4.2 Timing content of a digital signal the eye of the received signal has been discussed elsewhere.) Most digital transmission systems are self-timed in that they All pulse sequences have symmetries in the amplitude and phas