UTOPIA3 fiber transceiver OC-48 serializer Fiber In/Out Rx 32-bit UTOPIA3 OC-12 fiber transceiver Local bus OC-12 fiber transceiver OC-12 Control fiber transceiver OC-12 SONET UTOPIA fiber clock clock transceiver generator generator FIGURE 16.4 The principle of multiple-source use of the TADM chip in the PHY interfacing with POS, ATM, or frame relay, and OC-48 or slower links (Source: Agere Systems) The LXT1000 uses a single common network interface to support 1000BASE-T, 100BASE-TX, and 10BASE-T. This physical interface consists of four signal pairs that are used for 1,000 Mbps transmission. Each signal pair consists of two bidirectional signals that transmit and receive at the same time. The LXT1000 also provides a Management Data Input/Output (MDIO) interface and an HCI. The MDIO enables upper-layer devices to monitor and control the state of the LXT1000. The HCI will be used to set configuration options and operational settings of the device. Both of these interfaces will connect to the local bus FPGA interface through the VHDM backplane connector for local control. The I/O card should provide a programmable logic device that will be used to interface the LXT1000's HCI interface to the Peripheral Computer Interconnect (PCI) local bus through the VHDM connector. The programmable logic should contain registers that can be accessed for read- ing or writing from over the PCI local bus. These registers will be used to control the signals asso- ciated with the HCI. The appropriate devices must be foreseen in the final design to provide support for the required clock frequencies, and the appropriate filtering and decoupling components must be used as required. This seems like a reasonable list of requirements regarding this specific board for the engineering team, which must ultimately do the same thing for all components in the design and then put together full-fledged specifications on their intended design before starting the design of the board. We don't exhaustively design a system here. We just want to give a 