the cables for continuity and signal integrity and the connectors for compatibility. Step 3. Follow the chain of timing through the network downstream from the T-GM. At each clock, start by ensuring that the node is receiving a good frequency signal and then check phase/PTP. Remember that using a physical frequency source is mandatory for G.8275.1 and optional for G.8275.2. For frequency: a. Check that the proper frequency source is selected and that the device receives ESMC packets with QL-PRC/QL-PRS (if the QL value looks weird or is unexpected, check that the SSM/ESMC is configured with the correct option). If the clock indicates that the fre- quency source is internal (meaning internal oscillator), then something is wrong (there is no valid reference). b. Frequency selection follows the ESMC, SO check that first. If no ESMC packets are being received, then you might need to ensure that untagged traffic is allowed on the source in- terface. Make sure that the ESMC packets reflect the capability of the link on the link they arrive on (such as the ESMC packets have not been "tunneled" and that there is no copper SFP in the path). C. Check that the device is properly frequency aligned and stable (no "flapping"). Step 4. Now that the node is in the state FREQUENCY-LOCKED, perform the following steps to discover why the clock is not PHASE-ALIGNED: a. Confirm the intended interface is configured with the correct profile, domain number, and transport. For G.8275.1, ensure that untagged traffic is allowed, and for G.8275.2, con- firm that the IP path to the master is via the interface expected (for timestamping sup- port). Your implementation of G.8275.2 might support PTP only on a physical or layer 3 (L3) interface versus some logical device (such as a loopback device). b. Obtain a list of the foreign masters discovered by the Announce message and check what values the potential masters are advertising. Specifically, check the clock quality fields, domain number, and priority fields. Also ensure that the GM is settin