 be collected at the drain, where they add to the original particle-induced current and can cause an increased SEU sensitivity. Because the electrons are injected over the source/well barrier, this is referred to as a bipolar transistor effect, where the source acts as the emitter, the channel as the base region, and the drain as the collector. Reducing the channel length effectively decreases the base width, and the effect becomes more pronounced [69]. Essentially the same effect occurs in floating body silicon-on-insulator (SOI) devices, where excess carriers in the body turn on the parasitic bipolar transistor [69,71,72]. This bipolar effect severely impacts the intrinsic SEU hardness of floating- body SOI transistors. II-16 Source Drain P-Well N-Substrate Figure 3.6. Electron concentration contours inside an n-channel MOS transistor following a heavy ion strike [70]. The bipolar effect is evidenced by the contours emanating from the source, showing that the source is injecting electrons into the p-well, where they may be collected at the substrate or at the drain. Single-Event Upset Mechanisms in DRAMs We've seen how an ion strike releases charge along its path through a semiconductor and how this charge can be collected by p/n junctions, but what really matters is determining whether the event actually causes an error in circuit operation. In the following subsections we'll study how charge collection interacts with the circuit type and design to create a single-event upset. The focus will primarily be on memory circuits, but we'll briefly address SEU in other circuit types at the end of the section. SEUs in terrestrial electronics were first observed in DRAMs [73,74]. DRAMs have historically been quite susceptible to soft errors because they rely on passive storage of charge to represent information. Their charge state is readily modified by funnel-assisted drift or diffusion following an energetic particle strike. DRAMs have therefore received less use in space systems as engineers have preferred SRAM tech