sociated with the PDU, and, of course, the classification information that is related to the PDU. The FPP does not suffer from the speculative execution of instructions that cannot be followed up by the rest of the executable code- a situation that all too often stalls pipelines in RISC processing environments. It also does not suffer 1. Technical documentation with white papers, application notes, and data sheets is available at the Agere web site at www.agere.com and directly from the company. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. NETWORK PROCESSORS 32-bit UTOPIA / POS-PHY Buffer from PHY Data Buffer Input Output Controller 8-bit POS-PHY Framer Interface 32-bit Management POS-PHY Path Interface to RSP from ASI Block Buffers & Context Memory Pattern Program Checksum/ Processing Memory CRC Engine Engine Control Queue Memory 32-bit Memory FBI bus to ASI 8-bit Configuration Functional Bus Interface Bus Interface FIGURE 7.2 The internal block structure of the FPP chip. (Source: Agere) from the undesirable switching-context overhead that is typical in most architectures that process data sequentially. Figure 7.2 shows the internal structure of the FPP. Some blocks have an identifiable function such as the arithmetic logic unit (ALU) or the checksum/cyclic redundancy check (CRC) engine. The purpose of the other major blocks is as follows: The input framer frames the incoming stream into 64-byte blocks. Then it writes these blocks into the data buffer and into the block buffers and context memory. The latter temporarily stores blocks that are being processed as well as other associated con- text data for the execution of the FPP operations on the incoming data. The output interface strips the payload away from PDUs, such as packets or frames, according to block offsets, and forwards them along with their classification conclusions to the