tch is in the cross state (see Figure 5.43). Realizing the circuit with simple gates and counting the number of elementary CMOS it is possible to evaluate the power consumption per bit of the switch. Assuming a clock at 3 Gbit/s and a total power consumption of 750 UW, we obtained a value of p JJ/bit for the energy consumption per bit. As underlined in the caption of Table 5.9, data we are using are relative to the 65 nm tech- nology node since this component generation is widely diffused in high-volume products and reliable average data are available. It is possible to imagine that passing to 35 and 22 nm the power consumption will fur- ther decrease and it will be possible to get near the value of 1 pJ/bit, which is considered the target for the consumption of electronic switches. 5.7.1.3 CMOS Circuit Cost Trends A powerful driver both for the shrink of CMOS dimensions and for the increase of wafer radius is the continuous push to decrease prices of CMOS circuits even if functionalities grow. The price to pay for this evolution is the use of more and more expensive planar pro- cesses, whose cost is partially due to the requirement to fabricate smaller and smaller structures and partly to the need of maintaining the process uniformity over greater and greater wafers. This evolution is represented in Figure 5.44, where the time evolution of the cost in dol- lars of a single CMOS (estimated starting from the average cost of an integrated circuit) is compared with the time evolution of the cost of a lithography machine [47]. The cost of the CMOS is decreased as much as seven orders of magnitude, even if the lithography tooling has become continuously more expensive. At the end of the story, this is really the propulsive strength of microelectronics: it is able to conjugate better performances and lower prices. Before illustrating specific telecommunication applications of electronics, we will briefly illustrate the structure and the performances of three base electronics-integrated cir- cuits: the application-speci