processing is required to correct the error. The general form r multipliers and latches (where before). The latches are of a cyclic error correcting decoder of the Meggitt or error trapping initially cleared. During the first cycles of operation control line c variety is shown in Figure 14.3. During the first n cycles control line is ON and the k digits of the data word are fed through the 2-to-1 multiplexer M to the output; also AND gate G is open, so the adder output A is fed back to the coefficient multipliers. These multiply A by the values For the last r cycles of operation, control Input line c is OFF, so gate G is closed and the multiplier inputs and Feedback connections outputs are all zero. The r values stored in the shift register are therefore sequentially output through the 2-to-1 multiplexer. The function of this circuit is equivalent to the polynomial divi- sion x'd(x)/g(x); the digits produced at A are the quotient of the division, and the contents of the shift register after the cycle are Syndrome register the remainder (x° term at the left, xr-1 term at the right). For binary coders, all the coefficients are 0 or 1; multiplication by 0 is equivalent to removal of the corresponding path and adder, and Error pattern detector multiplication by -1 is equivalent to multiplication by 1 (in modulo- (combinatorial logic circuit) 2 arithmetic), which in turn is equivalent to a direct connection to the adder input. Each adder is a modulo-2 adder, or XOR gate. Hence the systematic binary coder for the (7,4) code with generator Buffer register Input Output polynomial given by Equation 14.23 (which would be represented in tables as 1011 in binary, or 13 in octal) is as shown in Figure 14.2. (14.23) Figure 14.3 General form of a Meggitt or error trapping cyclic error correcting decoder The decoder calculates the syndrome of the received (possibly corrupt) codeword. This is done using a linear feedback shift regis- C is ON and the syndrome is calculated as already described; while ter circuit exactly as in the 