s still in use for low- capacity machine, is very simple and it is reported in Figure 7.53. This architecture is not SO different from that of a general purpose computer. The incoming packets are stored in the central RAM memory after transiting from the input line card. When the CPU is ready for it, the packet is sent to a registry inside the CPU to allow all the verifications on the packets to be done (e.g., checksum calculation) and from it to a location in the RAM memory again. While the packet is in the RAM, the CPU calculates the routing and then the packet is transmitted from the RAM to the correct exit line interface. Node management software, routing protocol operation, routing table maintenance, routing table lookups, and other control and management protocols such as SNMP are also implemented in the CPU. The architecture depicted in Figure 7.53 is very simple and it is still used for home rout- ers, for example, but is limited to small capacity machines. The reasons for which this architecture cannot achieve high performances, even if high- performance components are used, can be summarized essentially as follows. The CPU is in charge of all the processes needed inside the router, comprising the elabora- tion of all the transiting packets. This makes the CPU a potential bottleneck of the system. Even more important is the fact that packets transit two times through the bus to be written on the memory. If we analyze the times needed to carry out the different phases of the packet processing we have Packet input storage: Neglecting the time needed to enter the input line card we have that the time elapsed for this operation is T + TRAM where T is the bus latency due both to the waiting time and to the real propagation time, and TRAM is the RAM writing time Packet verification: With the earlier definition we have T+ + tel where is the writing time of the packet in the CPU register and tel is the time needed for the packet verification Routing processor Memory Memory (CPU) (RAM) (ROM) FIGURE 7.53 Router ar