kup latency is critical. However, latency can often be easily hidden with the use of archi- tectural features such as pipelining and threads, especially when threads are combined with mem- ory-based approaches. An important point must be made regarding the first one of these three premises. When search- lookup-classification has to occur based on an algorithmic process such as a trie approach, then by necessity fewer pins are going to be used for I/O. In addition, the number of cycles involved in the execution of the algorithm significantly change the cost-performance comparison of a CAM versus other memory technology approaches. Other network processors such as EZchip's, which enable the use of other memory technologies instead of CAM, also offer an important cost incentive to the intended user. NPU ARCHITECTURE ISSUES Throughout this book, we have examined the different approaches taken by multiple vendors. We have seen the scalar architectures offered by complex instruction set computer (CISC) and reduced instruc- tion set computer (RISC) engines and where they fit. We discussed configurable computing, where new instructions can be easily generated that are specific to the application. This can be a successful means of dramatically enhancing the performance of such processors in the network-processing field. Most network processors offer multiple engines that can process packets simultaneously. Four different computing philosophies exist in this realm: One approach is the so-called run-to-completion processors. They essentially hand a packet over to an engine among the multiple engines available in the chip. This engine will work on this specific packet until its tasks are completed. The packet will then be forwarded to the next step in its intended computation realm. Pipeline network processors with one or more packet engines per stage is another approach. Here different engines work on different packets and run different code at the same time. The efficiency of the pipeline is difficult to determine as bubbl