R 4 IBM POWERNP TM We will now take a closer look at some of the most advanced network processing unit (NPU) archi- tectures that have been proposed by several vendors. Some of these vendors are solidly established and some are promising startups. Our coverage will not be exhaustive in detail for two reasons. First, this book does not take a cookbook approach. Second, the subject is massive and only SO much can be packed in one single book. Detailed information can be found in each vendor's product datasheets and chipset documentation. We relied on these items as the main sources for compiling these overview chapters. Our approach is to explain the fundamentals of each architecture by not only showing the break- throughs, but also by highlighting the techniques, modules, analogies, and paradigms that we may have already reviewed in earlier chapters. We will look at how a complete network gear solution can be implemented for tackling design problems through the various NPU architectures and will pinpoint the strong and weak points of each approach. In this chapter, we look at IBM's PowerNPTM family of network processors. More specifically, we look at the architectural structure of the NP4GS3 network processor, the capabilities, and the com- plementary peripheral chips (queue managers, switch fabrics, interface converters, and SO on) that are required to produce a working system based on the IBM platform. This requires an overview of the systems model that IBM NPUs favor. Finally, we will examine the tools that enable and support devel- opment of this IBM NPU and will discuss the design trade-offs that these network processors impose on the designer of switching/routing equipment. IBM POWERNP: THE BIG PICTURE IBM is one of the uncontested leading vendors in the global information industry. It combines advanced networking expertise with unparalleled microelectronics technology, deep submicron design, and semiconductor manufacturing process capabilities. Through its IBM Microelectronics unit, a very large engineering