orm of frame/buffer descriptor to(wards) DDR memory that contains at a minimum a pointer and length field with some "valid" bit. The Ethernet controller also writes bulk payload (Ethernet frame) to the DDR memory and signals the GPP core through an interrupt that (a) frame(s) are available for processing. The GPP core reads the frame/buffer descriptor from memory and parses it to conclude this is a U-Plane IPSec frame that needs to be de-ciphered IPSec de-ciphering IPSec de-ciphering can be implemented as a software function on a GPP core or in an accelerator, for the purpose of memory dimensioning there is little difference. For both cases, there is a memory read operation, followed by a de-cipher stage within the SoC and a memory-write operation. IPSec postprocessing and PDCP preprocessing The de-ciphered (now plaintext) frame is parsed to process the GTP-U header and classified to identify the bearer or PDCP context as required for the PDCP cipher operation. PDCP ciphering The main memory-intensive operation in PDCP is ciphering which (like for IPSec) involves a read operation followed by a cipher stage and a write operation. Chapter 3 Hardware system dimensioning 121 Ciphering Network General-Purpose IO to Physical External (DDR) (GPP or Interface Processor (GPP) Layer DSP Memory Accelerator) CU Processing per IP frame Frame Arrival From UPF Frame Payload Buffer Descriptor Hardware Packet Parsing/Processing Interrupt GPP Buffer Descriptor Trigger IPSec De-Cipher IPSec Pre-Processing Frame Payload (Ciphered) Frame Payload (Plaintext) Trigger Post De-Cipher IPSec Post-Processing Trigger PDCP Cipher PDCP Pre-Processing Frame Payload (Plaintext) Frame Payload (Ciphered) Trigger Post De-Cipher PDCP Post-Processing Buffer Descriptor RLC SDU Enqueue DU Processing per Slot Active UE Context Trigger Scheduler Slot Context DU Processing per MAC TB DU Processing per RLC PDU Buffer Descriptor TB Descriptor Element Slot Context Slot Context Physical Layer Processing TB Descriptor DU Processing per RLC PDU RLC PDU FIGURE 3