 rights reserved. Any use is subject to the Terms of Use as given at the website. SYSTEMS ENGINEERING ISSUES SYSTEMS ENGINEERING ISSUES 337 speed traffic, we can determine the amount of memory that should be available for a 2.5 Gbps link (312.5MB), for a 10 Gbps link (1.25GB), and for a 40 Gbps link (5GB) system. Using single data rate (SDR) SDRAM to transfer data at one edge of the clock signal is inexpen- sive, but very few companies still use this approach. The industry has moved over to double data rate (DDR) SDRAM memories. By transferring data on both edges of a clock signal (and therefore effec- tively at twice the clock rate) and in a manner that is synchronous to a data source, DDR SDRAM memories are more efficient for many applications. For example, a DDR266 device with a clock frequency of 133 MHz has a peak data transfer rate of 266 Mbps or 2.1 GBps for a subsystem that is configured as a times-64 dual inline memory module (DIMM). This feat is accomplished by utilizing a two-times-prefetch architecture where the internal data bus is twice the width of the external data bus and data capture occurs twice per clock cycle. To provide high-speed signal integrity, the DDR SDRAM utilizes a bidirectional data strobe and interface with differential inputs and clocks. DDR SDRAM has become the uncontested cost-per-bit capacity leader due to the vast PC market that commands unprecedented volumes for these same components. DDR SDRAM is also better in direct pin-count cost for the same I/O load than SDR SDRAM. Therefore, many companies use these memories on their network-processing platform for packet storage. Although in some applications, such as the OC-48 realm, SDRAM bandwidth is sufficient for basic packet queuing at wire speed, some processors are characterized by small, embedded memory banks and therefore architectural features are needed to give them an upper hand. An example of such a processor is the IBM NP4GS3, which has less memory than AMCC, Agere, or even Motorola net- work processors for the same seg