igured by connection rate type, such as constant bit rate (CBR), variable bit rate (VBR), or unspecified bit rate (UBR). A set of schedulers is defined for each logical port. Each scheduler supports a single type of traffic (such as CBR, VBR, or UBR). Figure 7.4 shows the extremely efficient data flow inside the RSP. As we mentioned earlier, the systems designer has the extra flexibility to connect an external scheduler. This opens up the possi- bility of custom-written algorithms beyond the ones that the RSP offers. This feature is useful when processing priorities need to be changed based on live traffic conditions. In some cases, it is even imperative. This may be the case in situations where a switch fabric is used that makes global deci- sions about the overall scheduling of traffic. Figure 7.5 shows the RSP chip's internal block structure. Three powerful compute engines based on very long instruction word (VLIW) architecture are cascaded in a pipelined fashion that allows heavy-duty computing performance while maintaining wire speed compatibility. These three engines are a Traffic Management Compute Engine, which enforces packet-discard policies and keeps queue statistics; a Traffic Shaper Compute Engine, which ensures QoS and CoS for each queue; and a Stream Editor Compute Engine, which performs all potentially necessary PDU modifications. In each queue definition, the RSP includes a destination, scheduling information, and pointers to programs for each Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. NETWORK PROCESSORS Scheduling Queues decisions Queues Schedulers Logical Ports Physical Ports FIGURE 7.3 Scheduling hierarchy for each PDU. (Source: Agere) (a) Queuing a PDU Traffic Preparation Management input Perform Determine Queue or Assemble Traffic Discard the PDU Queue ID Traffic Shaping Modification Pick the Pick the Get the Modif