 the multiple microengines allows the segmentation and partitioning of a single-stream packet analysis, such as routing into a set of multiple, sequential tasks including packet receive, route table lookup, and packet classification. The microengine design of Intel's second-generation network processors constitutes the first implementation of Intel's Hyper Task Chaining, as shown in Figure 5.3. This approach provides hard- ware support for managing data-dependent operations among multiple parallel processing stages with low latency. Downloaded from Digital Engineering Library McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. INTEL IXA TM NETWORK PROCESSORS IXA TM NETWORK PROCESSORS Intel has also introduced a series of patented techniques of register technologies that enable data and event signals to be shared among threads and microengines with virtually zero latency while maintaining coherency. We discuss several of them in the following section. ARCHITECTURE Figure 5.1 shows the internal block diagram of the Intel IXP1200 network processor. The architec- ture combines an embedded Intel StrongARMTM processor, which is targeted for control plane appli- cations and is supported by a 8KB data cache and a 16KB instruction cache with a set of 6 microengines that are used for packet processing. Other important features in the IXP1200 architecture include the IX bus unit (which we discuss later in this section) along with the hash unit that expedites address table lookup by performing poly- nomial hash on several values simultaneously. It also contains scratch pad memory (used to exchange data back and forth between microengines), a Peripheral Computer Interface (PCI) unit (used to inter- face with an external host central processing unit [CPU] or other PCI-compatible peripherals), and separate static random access memory (SRAM) and synchronous dynamic random access memory (SDRAM) controllers.