ice channels, in order to guarantee stable demodulation. Another point to note is that no sampling and minimal latency. In much the same way, video is shown in Figure 2.4a-1 It is mathematically possible has both low error rate and fixed latency channel re- to place the sampling process anywhere between the quirements, and thus networking protocols have been LNA and the FEC, giving the designer significant flexi- established to manage the quality requirements of video bility. An example of such design choice selection is over wireless networks. Many wireless video applications shown in Figure 2.4a-1( where the sampling process is are designed to accept the bit errors but maintain the shown as a discrete step. fixed latency. The differences seen between Figures 2.4a.1(a) and In contrast, for data applications, the requirement is 2.4a. are not at a functional level; they are imple- that the data must arrive with very few or absolutely mentation decisions that are likely to lead to a dramati- no bit errors; however, latency is tolerated in the cally different hardware structure for equivalent systems. application. The following discussion on hardware concentrates on Voice coding applications are typically implemented processing hardware selections because a discussion of on a DSP. The common voice coding algorithms require RF and IF design considerations is beyond the scope between 20 and 60 MIPS and about 32 Kbytes of RAM. of this book. Voice coding can also be successfully implemented Several key concepts must be taken into consideration on GPPs, and will typically require more than six for the front-end of the system, and it is worthwhile to times the instructions per second (100-600 MIPS) in briefly mention them here. From a design standpoint, order to perform both the multiply-accumulate signal signals other than the signal of interest can inject more processing arithmetic and the address operand fetch noise in the system than was originally planned, and the calculations. effective noise floor may be significan