tion set. Regardless The algorithm in Figure 2.4a-2 has several charac- of whether the machine is CISC or RISC, they both teristics. Assuming that the filter is of length N (N- share a generic nature to their instructions. These include order polynomials), then the total computation cost for instructions that perform multiplication, addition, or this algorithm can be computed. To optimize radio storage, but these instruction sets are not tailored to modem performance, filters are frequently designed to The software defined radio as a platform for cognitive radio CHAPTER 2.4a A DSP, in contrast, has the ability to reduce some of the cycles necessary to perform the given operations. For example, some DSPs have single-cycle MAC (multiple and accumulate). The Motorola 56001 is an example DSP that performs single instruction multiply and ac- cumulate with zero overhead looping. These reductions result in a computational total of 3N+3. Given these reductions, the computation load for the DSP is now (3 X 32 + 3) 100 X 103 = 9.9 MIPS. Given its customized instruction set, a DSP can im- plement specialized signal processing functionality with a significantly fewer clock cycles than the more generic GPP processors. However, GPPs are attempting to erode this difference using multiple parallel execution arith- metic logic units SO that they can perform effective ad- Figure 2.4a-2 Structure and data flow for Direct Form Il IIR filter dress calculations in parallel with arithmetic operations. as a basis for an estimate on computational load. These are called superscalar architectural extensions. They are also attempting to raise the performance of GPP multipliers through use of many pipeline stages, SO that the multiplication steps can be clocked at higher be FIR filters with only the b (all zeros) polynomial. In speed. This technique is called a highly pipelined order to implement extremely efficient DSP architec- architecture. tures, most DSP chips support performing many oper- ations in parallel to make an FIR filter nearly