effect, called "back parasitic transistor" as represented in fig. 93. A leakage current is usually observed in N-type MOS transistors, due to an electron conduction channel, which shows that the trapped charge is overall positive. III-98 Polysilicon gate N+ diffusion Gate oxide LOCOS Back conduction Buried oxide Silicon substrate Figure 94. Illustration of a radiation-induced back transistor in a SOI structure (after [Ferl-96, Flam-95c]). Charge trapping not only generates a back-gate FET effect but also a lateral FET effect and often also a parasitic bipolar transistor effect. The improvement brought about by the SOI technology over bulk CMOS technology is that these parasitic structures are located in the silicon island instead of being distributed in the bulk or at the surface of the silicon chip. On the other hand, as noted above, a new parasitic FET transistor appears due to the buried oxide, the underlying substrate acting as a back gate. MOS/SOI Lateral Cross Section Equivalent Circuit Lateral MOS Principal MOS gate oxide LATERAL MOS active silicon Buried MOS buried oxide Substrate Figure 95. Illustration of parasitic elements in a MOS/SOI or MOS/SOS transistor a) The five regions of transistor b) The corresponding parasitic elements [Lera-88b] 10.4. MODELING THE TRAPPED CHARGE IN SOI DEVICES In the following, is presented the application of the modeling equations of chapter 3 to the realistic situation of a NMOS transistor on SOI, with the use of codes computing self- consistently the charges, currents and the electric field. Two kinds of modeling have been presented up to know. A first kind uses the standard codes, by supposing a trapped charge distribution at the silicon surface. This allows useful insights, because the functioning of the silicon part of the device can be evaluated [Ferl-98]. But the modeling is not complete and is based on charge amount and profile that must be supposed. Major improvement is allowed by the use of self-consistent codes, in which the trapped charge is computed by taking 