p file (here v76.startup), if necessary. Here are some more stop conditions that you can enter in the Simulator as indicated previously. To detect when one of the variables n320cnt is > 2: stop if n320cnt > 2 To detect when the variable n320cnt declared in the first instance of process DLC in block DLCa is > 2 (replay the scenario retryl.scn to get such a value): stop if DLCa!DLC(1) n320cnt > 2 9 Naturally, stop conditions also work when simulating without replaying a stored scenario. 10 If after executing the four start transitions the Simulator is blocked, it means probably that the feeds are missing. They should be loaded by the model startup file, v76.startup. See previous chapters. 138 Validation of Communications Systems with SDL To detect if the transitions coverage rate of the SDL model is > 95%: stop if trans_cover_rate (system) > 95 To detect any output of signal EstabInd: stop if output L_EstabInd To detect the output of any signal to the environment: stop if output TO ENV To detect the input of signal v76frame by instance 1 of process AtoB, coming from instance 1 of process DLC in block DLCa: stop if input v76frame from dlca!dlc (1) to atob (1) To detect when the input queue of instance 1 of process DLC in block DLCa contains more than two signals (the part is : active is not necessary for a process instance that always exists, such as dispatch(1)): stop if is active (DLCa!DLC(1)) and length (DLCa!DLC(1) !queue) > 2 To detect that the first signal in the queue of process dispatch in block DLCb is named V76frame and that process dispatch in block DLCa is in state waitUA: stop if (length (DLCb!dispatch! queue) > 0) and (DLCb!dispatch ! queue (1) !name=v76frame) and (DLCa!dispatch!state = waitUA) To detect the progression of time: stop if trans time To detect if the SDL time is > 100: stop if now > 100 To detect if timer T320 in instance 1 of process DLC in block DLCa is set (i.e. is armed): stop if dlca!dlc (1) t320 ! active To detect the creation of any process instance: stop if create To detect the cr