andard define the baud rate and code rate of the SerDes interface that is used as follows: (Table 4-1) Table 4-1 PCle per-lane performance. Generation Baud rate (GTPS)/lane Code rate Net rate 1.0a, 1.1 2.0, 2.1 3.0, 3.1 128/130 128/130 15.75 128/130 31.51 180 Open Radio Access Network (O-RAN) Systems Architecture and Design All above numbers are for a single lane. By deploying multiple lanes ("PCIe gen 3 X 4" would indicate four-lane operation), rates can be scaled by an integer amount. As is shown in the table, the code rate reduces the actual number of bits transferred over the wire by about 20% (PCI gen 1 & 2) or approximately 2% (PCI gen 3, 4, & 5). Additional overhead is lost to packetization and protocol overhead. Transaction layer packetization Originator-to-target bits aren't just transferred over the SerDes link but wrapped into a proto- col layer that allows the PCIe interface that provides the functionality required present itself as a reliable memory mapped entity to the user (SoC). Transaction Layer Packets (TLPs) are used for this encapsulation, for example shown for a PCIe gen 3 interface (Fig. 4-30): The TLP header indicates the transaction type (e.g., Memory Write Request), payload length, target address, etc. Payload is optional-for example, not needed if the TLP header indicates a Memory Read Request. In the case of the Memory Read Request, the first TLP indicates from Requester to Completer what the requested address and size (length) are. The Completer responds back with a Completion TLP that contains the desired payload (memory content). Note that this is a significant difference between write and read operations, write opera- tions are "posted" or fire-and-forget; once the packet is formed, it can be ignored. A read operation needs the requestor to wait for completion. This is also called a nonposted operation. TLP overhead is in the order of 20-30 bytes, depending on PCIe generation, optional Cyclic Redundancy Check (CRC), and so on. See the PCIe standards documents for more details. The M