rst device is substantially filtered out by the second device. So, the peak-to-peak limit is the same as for a single device. The max|TE| is a maximum of the absolute value of all the above TE values, accumulating the cTE, dTEL, and dTEH values for both devices. But there is a complication in that the sym- metry of the dTEH must be considered in its contribution to the calculation of max|TE|. Ap- pendix V of G.8273.2 proposes two assumptions/methods for this asymmetry to calculate max|TE| and averages the results of both cases to arrive at a value. For Classes A, B, and C, the max TE values are 160 ns, 100 ns, and 45 ns, respectively. See Appendix V for details. Noise tolerance: The noise tolerance is the same as a single clock; just because there is a differ- ent form of media downstream does not mean that this clock should be less tolerant to noise. Noise transfer: Noise transfer for PTP to PTP or PTP to 1PPS at the output of the pair of clocks should have a maximum phase gain of 0.2 dB at a bandwidth of 0.1 Hz. Transient response: This is for further study, and no requirement has been specified. Holdover requirement: This should not change, although the performance depends on whether there is still a frequency signal available during a failure of the media converter interface. If it is not available, then the case is the same as the oscillator holdover. Note that for noise generation, a similar method can be used to calculate the combined error from a chain of single-node T-BC clocks across a timing network. Values derived from MTIE and TDEV (such as dTEL) accumulate as the square root of the sum of the squared values and the cTE values simply add up. 12.3.1 Overwhelmed! What Is Important? At this point, it would be quite reasonable to expect most readers to be exhausted with all the details about the myriad of possible test cases against the performance limits in the clock specifications. For vendors, and for engineers concerned with all factors of timing performance, many of these tests are very important an