pelling case to be made for enhanced RF performance to be captured as a design goal and for the benefits of performance gain over conformance compliance to be more explicitly stated, in effect a standard for an advanced front end. Note there is no reason why this should not be complementary to present and future baseband algorithmic innovation including for example interference cancellation. Conformance standards are set to be achievable with acceptable manufacturing yield at the time when user products first become available. In practice, it should be possible to realise year-on-year user equipment performance gains from year one of a technology being introduced for at least five years, though these gains may be, and often are, traded against cost- saving opportunities. Operators and standard bodies working together have the opportunity to influence these trade off decisions. 5.7.4 Software-Defined Radio and Baseband Algorithmic Innovation The baseband processing of Release 99 3G technologies meant that the standard DSP archi- tectures that had begun to dominate GSM and EDGE could no longer be used. A Release 99 handset needed about 1.5 million gates of dedicated hardware logic and associated memory to perform rake receiver, combining and channel decoding. The introduction of HSPA and new equaliser designs added another million gates. LTE introduces further complexity. The layer 1 multiple high throughput FFT/iFFTF36 operations, and FIRF³7 and MIMO detection needed to decorrelate the OFDMA subchannels requires a hardware implementation of the LTE physical layer of the order of 3 to 4 million gates coupled to a megabyte of fast memory of a 50 Mbps class device. This has to be coupled with L2/L3 CPU requirements of the order of 150 to 200 MHz to support 100 Mbps operation. To be viable in terms of cost and power consumption, LTE and LTE-A devices will therefore need to use 32-nm silicon geometries. A 65-nm implementation costs over 40 million dollars, may not work first time and will be obsolete within less than e