. According to the com- pany, if off-chip SRAM is used, then 24 LEs are enough to sustain 350 Mlps. In an example implementation of a 40 Gbps 100 Mpps solution in need of search capabilities to support classification, the company has reported using a 260,000 entry table that has between 1.3MB and 4.8MB of memory for search key sizes between 32 and 128 bits. A 400 MHz implementation of the TLE shown in Figure 12.6 was used and there were 32 LEs. 2MB of embedded memory is enough to hold 330,000 trie entries. For the reported example, this was divided to two banks, which each had an access rate of 400 million accesses per second. External memory was structured in two banks that were accessible 200 million times per second. The size of the overall memory depends on the size of the search key. In a typical layer 3 classification application based on a source address, destination address, and TOS that requires a 72-bit search key, this ClearSpeed TLE performed 251 Mlps. A five- tuple lookup based on a 104-bit search key at layer 4 yielded a performance of 208 Mlps. These numbers clearly command attention. The only downside to the approach is that it is only available as intellectual property (IP core) and not as a ready off-the-shelf component. Therefore, it can only be used by customers who intend to build their own integrated solution and who are conse- quently advised to take a close look at this approach as well. SUMMARY In this chapter, we examined search engines and predominantly those that are based on CAM for the support of critical classification and forwarding processors that we discuss in the next chapter. We reviewed how CAMs operate as well as how they are organized. We discussed several important sys- tems engineering issues that need to be handled when trying to use CAM in larger designs of ever- increasing speed and functionality. We also looked at the trade-offs involved in using CAM technology and reviewed some of the rather serious image problems from which they seem to suffer-some jus- tified and so