lements that have been used before. In any case, the ASIC design is a complex task and several studies have been carried out on the process for ASIC design and on the ways to decrease the risk. As far as the performances are concerned, a good design allows an ASIC to have a better possible performance for the specified task, due to its specialization. Still at 90 nm, ASICs with a clock rate on the order of 20 GHz were produced for a variety of applications [55] and this limit decreases continuously, up to the ASICs with a clock rate exceeding 50 GHz that were produced using 45 nm technology [56]. It is to be expected that 32 and 22nm ASICs will be still faster, and it is not unbeliev- able that 22 nm ICs will reach 80 GHz clock, which is a threshold for some telecommunica- tion functionalities, like nonlinear equalization for 100 Gbit/s multilevel transmission (see Chapter 9). As far as the throughput is concerned, experimental ASICs for security applications have been constructed with a single line serial throughput as high as 61 Gbit/s for an aggregate throughput on two parallel ports in excess of 121 GHz [57]. Another key feature of ASICs is the maximum area available. As a matter of fact, this is directly related to the number of transistors that can be integrated and thus with how functional each of the ASICs can be. Measuring the ASIC area in a number of equivalent gates, ASICs with an area of more than 105 equivalent gates have been already built and this number will continuously increase while 32 nm technology will become more consolidated and the gates and func- tional libraries will enlarge, allowing easier ASICs design. It is to be taken into account that high-performance 45nm ASICs are in production with an equivalent area of more than 7 X 105 gates [58]; thus it is expected that 32 and 22nm technology will do better due both to smaller CMOS and to the continuous effort to increase the process planar uniformity. Technology for Telecommunications: Integrated Optics and Microelectronics 5.7.3 Field Prog