re cost) and system cooling issues that may be difficult to confront given chassis-based power-consumption budgets and constraints. In order to cope with the increasing computational load, the network-processing architect has to match the need for parallel architectures. This has been corroborated by the creative approaches taken by the designers of many commercial off-the-shelf NPU chips. Now parallelism in computer architecture does not just stand for one approach. For instance, a designer can deploy multiple cores inside an SOC and divide the work (when appropriate and feasi- ble) to these resources. However, he or she will have to contend with managing access and resolving conflicts by some sense of arbitration that instead of resolving complexity, he or she simply shifts the design challenges from one hard issue to another equally difficult one. Alternatively, a designer could consider engaging a wider data path on a CISC/RISC architecture platform and expect to accomplish more work per time unit. A 64-bit processor is expected (at least by some people) to perform more useful work than a 32-bit processor. However, this is not always true. Not all applications can benefit from longer word arithmetic or data transfers. A designer can also deploy superscalar architectures to tackle this design problem. However, if such an architecture is based on an extensible and configurable architecture like the Xtensa processor's, it will end up being a nightmare for the designer to manage all possible interdependency issues that can arise between cus- tom instruction set extensions and the basic architecture itself. Tensilica architects have decided to follow a different path-the VLIW approach. Other companies such as Improv Systems whose approach has been marked by a history of distinctly less aggressive marketing toward configurability by customers are discussed in a later section in this chapter. Tensilica's FLIX approach offers straightforward and easy configurability to the wide instruction community of custom ASIC de