an conventional DRAM. It is also optimized for small bursts of activity and random access, such as that needed in graphics and network applications (web content). In terms of memory inputloutput (I/O) paths, the APP550 supports multiple types of memory usage: In double data rate (DDR) SRAM, it maintains a 32-bit-wide interface with linked-list memory, a 32-bit-wide optional stream editor (SED) context memory, an optional 32-bit-wide interface with memory that contains policing and statistics-related information, an optional 32-bit-wide inter- face with queue memory, and another optional 32-bit-wide memory bank that stores scheduler parameters. In FCRAM, APP550 maintains a 32-bit-wide interface with packet-buffer memory, an optional 32-bit-wide interface with memory that stores reassembly-related information, a 16-bit-wide inter- face with SED parameter memory, a 1 or 2 16-bit-wide interface with FPP program memory, and an optional 16-bit-wide interface with FPP control memory. By its ability to perform 128K simultaneous reassembles, the APP550 can support a large number of virtual circuits, while the chip's integrated capacity of 256K queues enables the per-flow queuing Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. AGERE PAYLOADPLUS FAMILY OF NETWORK PROCESSORS 118 NETWORK PROCESSORS for a large number of queues. Programmable data segmentation and modification allow the support for tunneled protocols and the use of different switch fabrics, whereas sophisticated buffer manage- ment and traffic shaping over 1,024 shapeable ports enable a more efficient use of bandwidth high-density system design. The APP550 has been announced at two clock frequencies-133 MHz and 266 MHz. It is offered in a 1,413-pin FCBGA package and is manufactured in a 0.13u complementary metal oxide semi- conductor (CMOS) process by TSMC. The 266 MHz version has a throug