 keeps the individual packet engines away from the eyes of the software engineer as if a single engine was being programmed, the debugger provides the visu- alization of the status and progress of individual threads that are allocated over the multiple packet engines. Therefore, the programmer can inspect the interaction between threads. Silicon Access also offers under a nice graphical user interface (GUI) a cycle-accurate simulator that covers all the chips of the set, including the IZB code, a packet generator, and a performance ana- lyzer that monitors the packet engines and coprocessors that are embedded inside the iPP. During code execution, these are controlled by the packet engines. A time-accurate, but not cycle-accurate, model allows the emulation of the whole ingress and egress paths. This is obviously required to verify the performance of the entire chipset. Customers who use ASICs along with the company's chipset (as the case with traffic management functionality) can add their own ASIC models to the suite and ana- lyze/simulate the entire board design. The development environment has a powerful command-line capability that allows for scripting and the extension of the toolset. The company also offers several evaluation boards for many of these chips. Last but not least, Silicon Access, like other NPU vendors, provides their customers with optimized-quality reference code for several networking applications and protocols. These include routing IPv4 and IPv6 traffic, Multiprotocol Label Switching (MPLS), DiffServ, bridging (layer 2 switching), IP tunneling, virtual local area network (VLAN) tagging per IEEE P802.3ac, and Point- to-Point Protocol (PPP) over Synchronous Optical NetworklSynchronous Digital Hierarchy (SONET/SDH) per RFC 2615. BAY MICROSYSTEMS' MONTEGO™ AND THE InPTM FAMILY One of the most interesting architectural approaches in network processing is the Internetworking Processing (InP) family from Bay Microsystems (www.baymicrosystems.com). The first product this family is the Montego net