plementation options include: Software implementations on a GPP FPGA based designs Optimized ASIC IP, either implemented in a separate device or as part of a custom Wireless physical layer acceleration FPGA based designs Optimized ASIC IP, either implemented in a separate device or as part of a custom SoC. This ASIC IP is mostly a combination of embedded (programmable) Digital Signal Processing (DSP) cores and hardware accelerators that support the most compute intensive functions. Layer 2 stacks are typically implemented as a software function running on embedded processor cores. Acceleration for commonly used functions including PDCP ciphering, wireless scheduling can be integrated. Chapter 4 Hardware architecture choices Backhaul Layer 2 Physical Fronthaul Stack Layer 1588 / SyncE Time/ Frequency FIGURE 4-12 Functional components of the optimized cell site integrated CU/DU hardware solution. Most embedded implementations are Arm or x86 based, with potential for RISC-V implementations. Mid/backhaul IO potentially including a dedicated NPU or similar hardware to offload tunneling and Ethernet/IP switch/routing functions. This functionality is often colocated with the layer-2 stack processor cores Time/frequency synchronization Given the I/O requirements and sector configuration that we previously established, we can calculate all the required I/O bandwidths between the functional components allowing us to define the mix of components that serves the functional purpose whilst hitting cost/ performance/development time targets. Note that multiple functional components are likely physically integrated onto a single chip: FPGAs have embedded DSP and Arm cores, inte- grated ASIC/ASSP solutions can include all functionality into a single device. The question is whether the provided levels of integration make sense for the target application. We give a few example options for implementation here, in order from deeply integrated/ embedded to the disaggregated and software defined. Integrated Architectures such as 3 for 