 design a full-duplex OC-192 line card (or 2X10 Gigabit Ethernet card). The company specifies that the iFlow chipset is capable of handling layer 3 processing and forwarding at a rate of 50 million packets per second (MPPS). The figure shows the two search engines on the ingress path; however, depending on the application, classification capa- bilities may or may not be required on the egress path. The pair of iPPs and iTMs on the egress path in Figure 9.1 can be completely skipped for lower-speed applications, thereby saving two chips from the overall chip count. Although the number of chips needed to develop an integrated solution may seem daunting, the network-processing solution from Silicon Access Networks has an interesting advantage. The exten- sive embedded memory eliminates the need for external static random access memory (SRAM) or even content-addressable memory (CAM). It even reduces the need for external dynamic random access memory (DRAM). The iCL is used essentially for applications such as access control lists (ACLs), Differentiated Services (DiffServ) flow classifications, and controlled flow management based on quality of service (QoS) and class of service (CoS). It contains a 5Mb CAM that is rated for 100 millions of searches per second (Msps) plus 4.5Mb of 128-bit-wide associated data memory. The iCL can handle multi- ple 216-bit searches per minimum length packet at 10 Gbps wire speeds. It also supports large mul- tiple-field classification tables with additional features such as range matching, per-entry masking, and/or per-lookup masking. Interestingly enough, in addition to the traditionally required discrete ternary CAM (TCAM) that it displaces, the iCL also contains the associated data memory (we describe the use of this memory Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES OTHER NPU ARCHITE