rication technology used to manufacture ICs. Because they flow directly from the basic mechanisms of SEU, we will concentrate on technology hardening methods and give only a brief description of circuit- and system-level hardening. A review of several hardening techniques is also found in [131]. 3.8.1 Technology Hardening The most fundamental method for hardening against SEU is to reduce charge collection at sensitive nodes. This can be accomplished in DRAMs and SRAMs by introducing extra doping layers to limit substrate charge collection [132]. In advanced SRAMs, triple-well [133] and even II-28 quadruple-well [134] structures have been proposed to decrease SEU sensitivity. Retrograde wells and buried layers can also be used to provide an internal electric field that opposes substrate charge collection [135,136]. Even the simple use of an epitaxial substrate instead of a bulk substrate affords some level of reduced charge collection [60,83]. In GaAs-based heterojunction insulated gate FETs (HIGFETs), the use of GaAs buffer layers grown at low temperatures (LT GaAs) has proven a very effective means of limiting charge collection [44,137,138]. The LT GaAs buffer layer prevents charge-enhancement mechanisms and substantially reduces charge collection (by as much as a factor of 100 [44]) because of its sub- picosecond minority carrier lifetimes [139]. Figure 3.18 shows measured drain charge-collection transients for 3-MeV -particle strikes, illustrating the dramatic reduction in charge collection for the LT GaAs HIGFET [44]. An effective technique for reducing charge collection in silicon devices is the use of SOI substrates [140]. In this case the collection volume is reduced by the fact that the active device is fabricated in a thin silicon layer that is dielectrically isolated from the substrate. A diagram of a thin-film partially-depleted SOI transistor is shown in Figure 3.19. In a typical thin-film SOI device, the source and drain penetrate all the way to the buried isolation oxide (BOX). This substantially re