o or four 8-bit sequences DATA COMMUNICATIONS and we call it the FCS (frame check sequence), or sometimes the CRC (cyclic redundancy check). At the distant-end receiver, the same addition is carried out and if the sum agrees with the value received, the block is accepted as error-free. If not, it then contains at least one bit error, and a request is sent to the transmit end to retransmit the block (or frame). Even with the addition of LRC, errors can slip through. In fact, no error-detection system is completely foolproof. There is another method, though, that has superior error detection properties. This is the CRC. It comes in a number of varieties. 10.5.3.1 Cyclic Redundancy Check (CRC). In very simple terms the CRC error detection technique works as follows: A data block or frame is placed in memory. We can call the frame a k-bit sequence and it can be represented by a polynomial which is called G(x). Various modulo-2 arithmetic operations are carried out on G(x) and the result is divided by a known generator polynomial called P(x). 3 This results in a quotient Q(x) and a remainder R(x). The remainder is appended to the frame as an FCS, and the total frame with FCS is transmitted to the distant-end receiver where the frame is stored, then divided by the same generating polynomial P(x). The calculated remainder is compared to the received remainder (i.e., the FCS). If the values are the same, the frame is error-free. If they are not, there is at least one bit in error in the frame. For many WAN applications the FCS is 16 bits long; on LANs it is often 32 bits long. Generally speaking, the greater the number of bits, the more powerful the CRC is for catching errors. The following are two common generating polynomials: 1. ANSI CRC-16: X 16 + 15 + X2 + 2. CRC-CCITT: X16 + + X5 + 1 producing a 16-bit FCS. CRC-16 provides error detection of error bursts up to 16 bits in length. Additionally, 99.955% of error bursts greater than 16 bits can be detected (Ref.4). 10.5.3.2 Forward-Acting Error Correction (FEC). Forwar