C exist, such as System-C, that allow the developer to use nets, or any of a large set of algorithms. Instead, the issue C-like constructs to develop FPGA code, but the resulting is in determining the sample set over which to perform program still describes a logic circuit running on the FPGA. the optimization. The most appealing aspect of FPGAs is their compu- There is no openly available methodology for estab- tational power. For example, the Virtex II Pro FPGA by lishing the set of possible combinations over which opti- Xilinx has a total of 6460 slices, where each slice is mization can occur. However, at least one approach has composed of two look-up tables, two flip-flops, some been suggested by Neel al. [1] that may lead to significant math logic, and some memory. To be able to implement improvements in deployment optimization. The proposed 802.11a, a communications standard that is beyond the methodology is partitioned into platform-specific and abilities of any traditional DSP in 2005, would require waveform-specific analyses. The platform-specific analysis approximately 3000 slices, or less than 50 percent of the is further partitioned into two types, DSP/GPP and FPGA's capabilities, showing the importance of a high FPGA. The platform-specific analysis is as follows: degree of parallelism in the use of many multiply accu- 1. Create an operations audit of the target algorithms mulators to implement many of the complex-waveform (number and type of operations). signal processes in parallel. From a performance standpoint, the most significant 2. For DSP: drawback of an FPGA is that it consumes a significant (a) Create a set of target devices. amount of power, making it impractical for battery (b) Establish cycle-saving capabilities of each target powered handheld subscriber solutions. For example, the device. Virtex II Pro FPGA mentioned above is rated at 2648 mW of power expenditure, whereas a low-power DSP such as 3. For FPGA: the TMS320C55x is rated at 65-160 mW, depending on (a) Create a set of devices. 