the mechanisms responsible for these effects are quite different. SEGR is caused by heavy ion traverse through the gate-to-drain overlap region of the device (neck region) producing sufficient accumulation of charge at the silicon to silicon-dioxide interface to exceed the breakdown voltage of the oxide, resulting in localized dielectric breakdown. Subsequent gate-to-drain conduction further damages the structure resulting in catastrophic failure of the device in the form of a gate-to-drain short. 4.2.3 Single Event Hard Error and Single Event Dielectric Rupture [Katz97] Single Hard Error (SHE) is the condition in which a single permanent fault is created through damage produced by the passage of a single energetic particle through sensitive device structures. One mechanism observed to be responsible for SHE is termed micro-dose, this involves the introduction of sufficient ionization within the gate oxide of a transistor to create a localized region of total ionizing dose effects. The term single hard error is most often used in reference to the occurrence of micro-dose in which annealing often results in recovery of device operation. A second mechanism observed to produce SHE, Single Event Dielectric Rupture (SEDR), is similar to single event gate rupture in power MOSFETS. In this mechanism, oxide-nitride- oxide antifuses used in field-programmable gate arrays have been shown to be susceptible to heavy ion induced failure. Single Event Upset and Transients 4.3.1 Single Event Transient and Upsets in Digital Devices Single Event Transient (SET) is a voltage waveform impressed upon a signal within a device due to the collection of charge generated by the passage of an ionizing particle through the device structure. Single Event Upset (SEU) is a change of state in digital logic devices produced by a circuit level response to a single event transient. Single event upset is typically referred to as a bit level phenomenon, expressed in units of upsets/bit-time. The term single event upset is used in reference to space