ernal use of a content-addressable memory (CAM). Beyond the coprocessors, the NP4GS3 contains special hardware units that are also shown inside the EPC block, as depicted in Figure 4.4. These units offer the following functionality: A Dispatcher tracks the use of threads. It is engaged right at the beginning of processing as it is the unit that fetches the initial frame data before thread assignment occurs. A Completion Unit is responsible for maintaining the order of frames, which are enqueued, SO that both ingress/egress flow control and the overall scheduler can function properly. A Policy Manager performs policy management based on four management algorithms as specified in Internet Engineering Task Force (IETF) RFCs 2697 and 2698. They are the single-rate three- color marker (srTCM) (in color-blind or color-aware modes) and the two-rate three-color marker (trTCM) (also in color-blind or color-aware modes) algorithms. A Hardware Classifier is engaged in the classification of frames from various realms, such as Ethernet (802.3 and DIX), layer 3 (IP), VLAN header detection, and guided traffic. A Counter Manager is used by the EPC to control several counts used by the picocode for various purposes, such as statistics, policy management, and flow control. IBM considers the last two of these units particularly critical for the robustness of network equip- ment designs built around the NP4GS3 and for the predictable delivery of desired functionality. The NP4GS3 supports different types of memory that are connected to the chip in different loca- tions and used for different purposes. Memory for the NP4GS3 can be internal (on-chip) and SRAM, or it can be external (off-chip). In the latter case, it is either ZBT SRAM or DDR SDRAM. Internally, the NP4GS3 contains 384KB of memory that is used for internal NPU control information or for stor- ing frame data. The large amount of supported memory enables a large size of forwarding tables to be used in the local NPU. The NP4GS3 can easily sustain 500,000 table updates per s