ero. For example [10010101] is a valid codeword. We place this codeword on V1 to V8 nodes, that is vj=1, v2=0, and SO on. The modulo-2 sum at C1 is 0+1+0+1=0; at C2, 1+0+0+1=0; at C3, 0+1+0+1=0; and at C4, 1+1+0+0=0. The bipartite diagram confirms that [10010101] is indeed a valid codeword. Now let us assume that one bit has arrived in error: [10011101]. The constant node summation at C1 is now 0+1+0+1=1; at C2, 1+0+0+1=0; at C3, 0+1+0+1=0; and at C4, 1+1+0+0=1. The error must therefore come from a variable node connected to both C1 and C4 and which yields the error position of V5. In practice the LDPC decoder iteratively goes through the bipartite diagram and attaches probabilities to the variable node data on whether it is a 0 or a 1 to satisfy the modulo-2 sum rule. Similar to iterative turbo-decoding each iteration increases confidence on 0 or 1. This process continues until a certain degree of confidence in accuracy is reached. LDPC codes have been shown to virtually perform to within 0.2 dB of Shannon's theorem for LDPC codes of 10 000-100 000 codeword lengths. The BER for an LDPC code (4599,4227) is shown in Figure 6.22. Note that because of very low coding rate of 0.92, the Shannon limit is quite high and equal to 3.5 dB. Of greater interest is the BLER shown here. BLER is approximately 50 times the BER value. This is a 30 times BLER performance improvement over the BLER 2 4599 X BER value that a random error process would yield. The error correction process delivers most packets error-free: leaving erroneous packets with large numbers of errors. Rate Matching (Repetition and Puncturing) Both block and convolutional encoders generate a finite number of output bits as a function of the number of input bits and coding rate. In addition most convolutional codes require a number of tail bits to reset the shift register to the initial all 0 state. For example if 20 data bits are input to the 3G convolutional encoder (3,1,9) of Figure 6.18 which uses 8 shift registers, the output will be (20+8)x3=84 bits. Many 