to have a ADC performance of 45 dB or better. Chapter 3 Hardware system dimensioning Data converter and phase locked loop (PLL) ADC performance requirements are dominated by the dynamic range which is defined as the difference between the maximum allowed input signal level and the noise plus interference floor level. Thus we need to consider the maximum modulation and coding scheme which requires the maximum possible SNR in order to decode the signal with the desired rate. These are depending on the (algorithmic) modem implementation but we gave some values before (-5.5 dB for QPSK, 5-15 dB for 16QAM, 15-20 dB for 64QAM and 25 dB or better for 256QAM). Let's look at an example ADC analysis for a simple FR1/ < GHz baseband I/Q use- case, ignoring DPD feedback path support which requires to capture a wide RF bandwidth: Sample rate Fsample is defined from the signal bandwidth which is 100 MHz in the RF domain or 50 MHz for I and Q each. Given 3GPP sample rates in multiples of 30.72MSPS, we assume 122.88MSPS as a minimum sample rate above Nyquist criterium or 245MSPS with 2x oversampling to simplify aliasing filter implementation. SNR requirements are defined as Assume 25 dB required SNR for 256QAM decoding. 12 dB required PAPR to be supported, assuming the transmitting side did not reduce PAPR with CFR. Gain errors (4 dB) consist of gain and offset errors as caused by inaccuracies in internal reference and amplifier offset voltages reduce the usable dynamic range. Assuming gain error and offset errors to be 10% of full scale, then each contributes a 1 dB reduction in dynamic range. The ADC must be backed off 1 dB to prevent input clipping and another 1 dB to account for limited dynamic range. Add 2 dB dynamic range margin. Analog Gain Control (AGC) error. Assume 10% (i.e., 20%) error. Add 2 dB dynamic range margin. 10 dB rule-of-thumb fade margin which is the assumed channel fading over (short term) time and frequency in the target spectrum. If not taken as a rule-of-thumb, this number can be derived from channel me