parator. Again when the circuit is in lock both signals entering the phase comparator are exactly the same in frequency. For this to be true the voltage controlled oscillator must be running at a frequency equal to the phase comparison frequency times the division ratio as shown in the diagram. Take the example of when the divider is set to two, and the reference frequency is 1 MHz. When the loop is in lock the frequency entering both ports of the phase comparator will be 1 MHz. If the frequency divider is set to two this means that the frequency entering the divider must be 2 MHz, and the voltage controlled oscillator must be operating at this frequency. If the divider is changed to divide by three, then this means that the voltage controlled oscillator will need to run at 3 MHz, and SO forth. From this it can be seen that the loop will increment by a frequency step equal to the comparison frequency when the division ratio is increased by one. In other words the step frequency is equal to the comparison frequency. As the output frequency from the loop is locked to the reference signal, its stability is also governed by this. Accordingly most reference oscillators use quartz crystals to determine their frequency. In this way any drift is minimized, and the optimum accuracy is obtained. Receivers 139 Programming information Reference Phase Voltage Output Fixed Programmable divider controlled oscillator detector divider oscillator filter Figure 5.23 Comparison frequency reduced by adding a fixed divider after the reference oscillator Most synthesizers need to be able to step in much smaller increments if they are to be of any use. This means that the comparison frequency must be reduced. This is usually accomplished by running the reference oscillator at a frequency of a megahertz or so, and then dividing this signal down to the required frequency using a fixed divider. In this way a low comparison frequency can be achieved. This gives the block diagram of a basic synthesizer shown in Figure 5.23. Employing a digit