ated to doping loss, electric field enhancement due to fringing and control of the shape at corner [Shan-98]. More, progresses of the integration increase strongly the number of transistors, and consequently the global leakage current at the circuit level tends to increase. On the other hand, supply voltage of core logic circuits will go on decreasing, from 3.3 V (1995) to 1.8 V (1999) and below 1 V (circa 2005). At this level, the applied voltages, the space charge voltage due to the trapped charges and the built-in potentials (eg. ms) will become on the same order of magnitude in the lateral thick oxides. This is the reason why the analysis of radiation effects will require self-consistent models, able to take field-collapse and field-enhancement into account, and numerical modeling will probably become mandatory. This is the reason why we III-95 stress all these points in this Course. 10. SOI TECHNOLOGIES Silicon On insulator (SOI) technology is an efficient method that aims to prevent or reduce parasitic couplings between transistors and between data or supply lines. It consists in separating transistors by using insulating layers underneath and almost always around transistors. It is envisioned by SIA as a credible technology for low-power, low-voltage CMOS technology [SIA-98], and is likely to be introduced in mass production. As will be seen, SOI present some advantages for total dose hardness, as leakage between transistors is avoided, but at the same time can be inherently prone to radiation vulnerability due to leakage within the transistor surfaces itself. First recall that all the SOI variants have in common to use a specific substrate, which can be sapphire with epitaxied silicon film (Silicon-On-Sapphire) or a thin silicon dioxide film, topped with a silicon layer (specifically refered to by the community as "SOI SOI technologies have now a long and complex history, dating of the early times of microelectronics (for reviews on SOI, see [Cris-95, Coli-97]. In the latter case, the silicon dioxide is c