h which the Q-5 TMC and its enqueue processor, buffer manager, and scheduler can implement advanced QoS. In order to provide robust scheduling and ensure that service level agreement (SLA) stipulations are met for priority, fairness, and data rate, the Q-5 TMC offers a three-level scheduling hierarchy depending on the level of aggregation required. The schedulers at any of these three levels, as shown in Figure 8.5, can be configured with an assortment of algorithms to perform integrated shaping/ scheduling on different traffic types depending on the exact traffic requirements. The base element in the scheduling hierarchy of the Q-5 is the traffic queue, which represents an individual connection, a Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. MOTOROLA'S C-PORT™ FAMILY OF NETWORK PROCESSORS 130 NETWORK PROCESSORS collection of connections, or a flow. Traffic queues can aggregate through up to three scheduling levels. This scheduling hierarchy provides support for priority and multiprotocol (ATM, IP, frame relay, MPLS, or a mixture) fair scheduling and shaping algorithms. The schedulers at level 3 aggregate up to 128K traffic queues into a class or multiple classes. Level 2 schedulers can consoli- date up to 32 level 3 schedulers. Level 1 schedulers can cluster up to 32 level 2 schedulers. Offering a wide selection of algorithms, Motorola's Q-5 TMC enables customized implementa- tions of QoS by allowing various combinations used by the schedulers. The following are among the supported algorithms: Strict priority (SP) In this case, each input to a scheduler is statistically assigned one of 32 prior- ity levels without any minimum guarantees. All of the nonempty inputs within each level of prior- ity are served on a first-in first-out (FIFO) basis. Guaranteed bandwidth weighted fair queuing (GBWFQ) This is a non-work-conserving WFQ- type of a