stics of the struck device, and compare the collected charge to some critical charge to upset. However, the usefulness of this approach is extremely limited for SRAMs, since the charge-collection characteristics are greatly influenced by external loading and the feedback mechanism in latches [67,284]. Additionally, the critical charge itself may be ill-defined, once again being dependent on external loading and specific circuit designs [63,88,285]. Nevertheless, unloaded device simulation has been useful for studying the basic physical properties of charge collection, and for studying DRAMs, where loading effects are not as prevalent and critical charge is well-defined by noise margins [75]. For studying the upset process itself in SRAMs, circuit simulation has been a more usable tool. The single-event induced transient current is modeled as a current source at the struck node, and the effects on the SRAM are calculated with a circuit simulator such as SPICE [285-288]. One strength of this approach is the large scale of the circuit in question that can be modeled; another is its computational efficiency. A drawback is the accuracy of the transient current used as the input stimulus. For example, if the current is based on device simulations of a struck, unloaded device [117], then the circuit simulation inherits the inaccuracy of the improperly- loaded device simulation. If the charge collection input is approximated using one-dimensional, analytical models [288], even greater inaccuracy may result, particularly for heavily-ionizing particles. Still, circuit simulations have provided considerable insight into SEU in SRAMs and have resulted in improvements to hardening techniques for a variety of circuits [131,150,152, 155,166,286,289,290]. In the best of all possible worlds, one would desire a simulation methodology for SRAMs that allows either modeling the entire memory cell in the device domain, or allows concurrent solution of device and circuit equations. The former method has been used quite successfully wit