 bus Manager Enqueue Scheduler Processor SDRAM TMI interface Forwarding path implemented in a network processor or in an ASIC FIGURE 8.3 The logical flow of operations with the Q-5 TMC. (Source: Motorola) Two ZBT SRAM interfaces-namely, one for parameter storage, which is 72 bits wide, is clocked at 133 MHz, and can address a maximum of 8MB of storage, and one for queue-link storage, which is 18 bits wide, is clocked at 133 MHz, and can address a maximum of 10MB of memory space. Typical QoS configurations such as policy-based active queue management (AQM) with fair buffer sharing, statistics collection parameters, and traffic-monitoring policing and shaping. Even policy- based priority and fair bandwidth allocation to flows, along with the scheduling of flows, can be eas- ily implemented by software engineers working on switching/routing systems through the use of QoS application programming interfaces (APIs). These same APIs also enable the rapid modification of the QoS configurations SO the user can provide real-time service provisioning and reprovisioning. With its 5 Gbps throughput, the Q-5 provides multiprotocol support for virtually any type of link, enabling the implementation of QoS management up to OC-48c wire speeds in protocol environments, which can be anything among IP, ATM, frame relay, Ethernet, and POS. With the Q-5 TMC, the user can implement high-density per-flow and/or per-VCI queuing and very fine-grained traffic shaping for a broad range of packet- and cell-based applications. A three-level scheduling hierarchy, which provides support for up to 4,000 virtual channels (VCs), enables the implementation of a vast array of services including deep channelization and even integrated multicasting. The Q-5 TMC is designed as a look-aside traffic manager, which enables it to provide both ingress and egress traffic management. Ideally, it should be combined with Motorola's C-5e network proces- sor, but it can function equally well in a system as a stand-alone TMC. Figure 8.3 shows the flexibil- ity wit