 next processing stage downstream, which is usually the RSP chip. The Pattern Processing Engine (PPE) of the FPP performs pattern matching to determine how the incoming PDUs are classified. This will decide how they must eventually be processed. The Queue Engine manages FPP replay contexts, provides addresses for block buffers, and maintains informa- tion on blocks, PDUs, and connection queues. The FPP processes bit-stream data in two passes: first it processes the PDUs as separate 64-byte blocks and more specifically, the data offsets of the various blocks are stored and printer links are established between the blocks out of which the PDU is composed. In the replay phase (second pass) the PDU is processed as a whole entity. Pattern matching is exe- cuted at the same time as integral transmission is handled of the PDU toward the output interface. The latter will reassemble the PDU and if needed it will strip a certain amount of data away from the blocks of the PDU, of course according to the data offsets, which were defined during the first pass. Agere's architecture distinguishes the allocation of computational resources into a fast processing path and slow processing path. These paths were discussed in Chapter 2, "Network Processors: Justification." This logical partitioning is strongly reminiscent of the data versus control plane pro- Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. AGERE PAYLOAD PLUSTM FAMILY OF NETWORK PROCESSORS 109 cessing debate. With the PayloadPlus approach, the FPP, the RSP, the FBI bus, and part of the ASI are considered the fast processing path elements because they have to perform their tasks at wire speed directly on the traffic bitstream. The rest of the ASI, the MPI bus, and the PCI-based host, along with the host CPU itself, are the elements of the slow processing path, which is computationally responsi- bl