fferent aspects of designing a good PTP-aware NE. Hardware-Assisted Timestamping The precision time protocol uses the timestamps carried in PTP event messages to recover phase (and optionally frequency if frequency distribution is not via the physical layer). To achieve the highest precision, timestamping of the PTP messages must be applied just before the packet's depar- ture or immediately upon the packet's arrival. Performing the timestamping as close to the wire as possible is to make sure that the transit time between master and slave clock nodes is minimized. PTP-Aware Equipment Front panel Front panel ports Local ports oscillator Ethernet Clock interfaces recovery Frequency Ethernet (In out) from line recovery interfaces (TO PLL) (In out) Timing Frequency interfaces Clock Synchronized (BITS/ cleanup PLL frequency Timing 10 MHz) (T4 PLL) interfaces Phase (BITS/ (In or out) recovery 10 MHZ) (PTP PLL) (In or out) PPS/Phase (NCO) receiver (In or out) Timestamping Servo / PEC (In out) protocol slave stack (In or out) PTP packet Timekeeper (In or out) processing Figure 12-4 SETS Architecture for Full Timing-Aware Synchronous Equipment Design Hardware-based timestamping is the key mechanism needed to achieve nanosecond levels of accur- acy. The best implementations of PTP can be achieved only when utilizing a hardware element to assist in timestamping the PTP event packets. Furthermore, those timestamps must be both accurate and use a high-resolution clock with a fine granularity. Hardware timestamping engines are required to achieve the best accuracy (in the range of nano- seconds or better) and they are not impacted by software-induced latencies. On the other hand, soft- ware-based timestamping is susceptible to unpredictable interrupts and variable operating system latencies, and the final accuracy of such implementations will be very low (typically in the milli- second range). As shown in Figure 12-4, this hardware element is referred to as the TSU and is placed between the Ethernet media access control (MAC)