ETs in P-substrate at GND Bitline Complement Figure 3.21. Diagram of a gated-resistor hardened SRAM [152]. Clocking the gated resistor with the wordline reduces the feedback resistance during write pulses, thereby minimizing the timing penalties usually associated with feedback resistors. A similar, but distinct, approach has been used to harden high-density SRAMs in SOI [153]. In this approach an extra transistor is fabricated in the silicon device layer in parallel with a standard cross-coupled polysilicon feedback resistor. Under normal operation, this transistor is off, and the feedback signal must pass through the resistor in the usual manner. During a write pulse, the transistor is turned on, effectively shorting out the feedback resistor and maintaining the write performance of the memory cell. Other decoupling techniques have been proposed that place resistors or diodes in different locations [154-157], usually for the purpose of reducing the impact of the resistors on timing parameters or increasing manufacturability. For the most part these techniques have not been widely used (if at all) and have their own associated tradeoffs. Capacitors have been successfully used as a feedback element in SOI SRAMs [140,147,148], and very recently as a means to improve the soft-error performance of deep-submicron CMOS SRAMs for terrestrial applications [158]. While adding capacitance still degrades timing parameters, one advantage is reduced temperature-dependence compared to resistive hardening. 3.8.2 Circuit- and System-Level Hardening Because of the invasive nature of device-level hardening (i.e., the requirement for fundamental changes in the manufacturing process), easier to implement methods have been a frequent topic of research. The goal of circuit-level hardening techniques is to design circuits that are inherently SEU-hardened and can therefore be manufactured using any commercial fabrication process. Also sometimes referred to as design-level hardening, this can be an important technique in cases when part