 GNSS receiver with a connector for an external antenna. Synchronous Equipment Front panel Front panel ports Local ports oscillator Ethemet Clock Frequency interfaces recovery recovery PLL Ethernet (In out) from line (TO PLL) Clock interfaces multipliers (In out) Timing Frequency dividers interfaces (BITS/ Clock cleanup Timing interfaces 10 MHz) (In out) (T4 PLL) (BITS/ 1PPS/Phase Input 10 MHz) monitoring (In out) receiver Synchronization selection process Figure 12-2 SETS Architecture for Frequency Synchronization in Synchronous Equipment Note that as shown in the figure, some of these interfaces, such as SSU/BITS and 10 MHz, configured as input (receive frequency input) or output (output the system frequency) interfaces. Of course, the interfaces from the GNSS receiver can only act as inputs to the NE. Note also that Figure 12-2 shows different front panel ports on the left and right sides, but they are the same set of ports and are shown separately for better clarity. The ability for any one port to perform input or output should be flexible and controlled by configuration. Because this section talks about frequency synchronization only, the phase recovery PLL has been omitted in the figure for convenience and simplicity. When looking at Figure 12-2, the following points list the prominent features of the hardware and software architecture needed for frequency synchronization: Although the frequency recovery PLL (sitting inside the SETS device) accepts a single fre- quency source to lock to, the equipment can accept numerous frequency sources. These sources are usually multiplexed in a hardware device-such as a field-programmable gate array (FPGA) -to feed only a few of these sources to SETS. This module is shown as the Clock MUX (multiplexer) in Figure 12-2. Consider an NE having tens of Ethernet interfaces (all SyncE capable), while the SETS device supports only a few (in the range of five to seven) input references. In such cases, the FPGA- based clock multiplexer acts as an initial frequency source selecto