mething like the power consumption per square foot that must be addressed for the line cards. Instead, the problem will be physically managing the access to and from the switch fabric for SO many I/O lines. More specifically, in terms of requirements of the 4X1.25 GbE cards, The 4X1.25 Gbps PHY I/O card must be able to interface to the APP550-equipped line card through connectors that attach to the midplane of the system platform. The I/O card probably should have a 6U form factor (233.35 mmX160m A rough block diagram for the contemplated 4X1.25 Gbps PHY I/O card is provided in Figure 16.3. Each block is roughly described as follows: It must be able to provide four physical medium dependent (PMD) interface connectors (RJ-45) for connecting category 5 (CAT5) twisted-pair connections to a Gigabit Ethernet transceiver through the appropriate magnetics. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SYSTEMS ENGINEERING ISSUES 348 NETWORK PROCESSORS RJ-45 magnetics connectors LXT1000 Local bus 1st device XC95288XL connector local LXT1000 RJ-45 magnetics 2nd device connectors 4 x 2 = 8 simultaneous send/receive signals LXT 1000 RJ-45 magnetics 3rd device connectors magnetics LXT1000 RJ-45 connectors 4th device FIGURE 16.3 The PHY structure of a possible 4X1.25 GbE card based on the Intel LXT1000 (Source: Agere Systems) It must provide four Gigabit Ethernet PHY layer devices with a GMII/GPCS, which corresponds to layer 1 of the Open System Interface (OSI) model. The PHYs connect the media (CAT5 twisted- pair) to the MAC layer, which corresponds to OSI layer 2. It must allow for the appropriate connection of the GMII/GPCS and management/mode select interface signals to the backplane connector. It must provide programmable logic based on field-programmable gate array (FPGA) or custom- programmable logic device (CPLD) for the interfacing of the PHY H