gure 4.2: Typical PLL architecture consisting of a phase-frequency detec- tor (PFD), a loop filter and a voltage-controlled oscillator (VCO) - frequency divider combination. In the architecture above, the PFD is implemented dig- itally, driving a charge pump. 4.2.1 PLL architectures and PLL building blocks Fig. 4.2 illustrates a typical PLL architecture. It consists of a phase-frequency detec- tor (PFD), a loop filter HLF (s) and a voltage-controlled oscillator (VCO) - frequency divider combination. The PFD measures the phase difference between the input sig- nal that drives the PLL and the frequency-divided VCO signal. Its output is passed through the loop filter. This filtered error signal is then used to steer the VCO's oscil- lation frequency. Due to the correcting actions of the PLL feedback loop, the phase (and therefore also the frequency) of the frequency-divided VCO signal tracks that of the input2. This can be used for frequency synthesis, VCO phase noise suppression or frequency/phase modulation. If the input signal is periodic and if the PLL is stable, then there exists a periodic large- signal operating point. As outlined in section 3.1.3 of the previous chapter, linearizing the PLL's behavior in the neighborhood of this operating point results in an LPTV small-signal model. So, in analyzing PLL small-signal behavior, we are essentially dealing with a time-varying system. Especially for PLLs with a fast feedback loop, this time-varying behavior has a severe impact on, for instance, loop stability and cannot be neglected. The building block that contributes the most to a PLL's time-varying nature is the PFD. because of their superior acquisition of phase-lock, one nowadays most commonly uses digital PFDs that steer a charge-pump [Lee98]. These PFDs measure the phase error as the distance between the zero-crossings of the reference signal and the (frequency- divided) VCO signal. Hence, they only compute the phase error once per period of the reference signal, i.e. they sample the phase error. For this 