se no performance degradation will be observed. If not, then some delays may occur on some links and some traffic loss may occur, but the switch continues to function and connectivity is not lost. Depending on the arrangement the systems architect has created, such an approach has N+N, N+1, or N-1 redundancy. ROUTING/SWITCHING SYSTEMS CONSIDERATIONS Switch fabrics as systems modules are structured into two large conceptual subparts that need con- tinuous access to the high-speed serial backplane: the queuing manager, or scheduling control unit, and the crossconnect switching unit. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SWITCH FABRICS 280 NETWORK PROCESSORS PHY/MAC TM & NPU TM & NPU PHY/MAC Potential output buffers PHY/MAC TM & NPU TM & NPU PHY/MAC PHY/MAC TM & NPU TM & NPU PHY/MAC FIGURE 14.8 Redundancy based on load sharing between two sets of parallel active switch fabrics. In most current vendor architectures, this partitioning reflects a physical distinction between two actual chips-one on the line card (the queuing manager) and the other on the switch fabric card (the switch fabric chip). Serdes controllers for input and output can exist in both of these chips. They also sometimes appear in the implementation as separate serdes chips inserted in the bidirectional data path between the queuing manager and the switch fabric chips. In some rare cases, the queuing manager chip is physically located on the central switch fabric card in which case high-speed transceivers on the line cards will ensure communication with the serdes controllers on the switch fabric card. The queuing manager implemented on each one of the line cards, as the front end of connection to a network, disassembles and reassembles the incoming packets to and from cells, frames, or pack- ets. However, this is done with the tacit understanding that these cells are