complete database content within a single clock cycle. No other type of memory can accomplish this. They are configurable in multiple formats of width and depth of search that allows searches to be conducted in parallel. They enable multiple CAMs to be cascaded to dramatically increase the size of the lookup tables that they must store. They are able to learn what they don't know yet by updating specific entries into their table. They seem to have no competition at wire speeds above 2.5 Gbps. On the other hand, CAMs are reproached for having the following disadvantages: They cost several hundreds of dollars per CAM even in large quantities. They occupy a relatively large footprint on a card. They consume excessive power. They suffer from several more generic systems engineering problems when dealing with issues such as painless interfacing with a network processor and updating table entries simultaneously while looking up requests. We discuss these issues and whether these four reproaches against CAMs have any objective merit later in the chapter. CAM STRUCTURE Detailed information for a specific CAM can be obviously found in a vendor's product literature (data sheets and application notes). In this section, we limit our discussion to the fundamental notions as applied to the network-processing realm. The majority of CAMs are implemented in a two-port structure, as shown in Figure 12.1. The com- parand bus is parallel (usually 72 bits wide) and bidirectional, because it is used for writing the search keys and for table updates (read/write). The results bus is obviously only an output. A command bus enables instructions to be loaded to the CAM SO that it can configure the search operations according to the desired procedure. CAMs are usually configurable in banks of various sizes, as shown in Figure 12.1. Some of these logical partitions can be set up to be ternary, whereas others can be binary. Parallel searches can be performed this way simultaneously at different parts of the table, thereby increasing the effic