een a slave clock's input signal and the nominal (natural) fre- quency of its VCO, within which the slave clock stays in the locked mode and outside of which the slave clock cannot maintain locked mode, irrespective of the rate of the frequency change." This can be seen as the range of the frequency step, which if applied to a steady-state PLL, the PLL still remains in the steady (or locked) state. The PLL declares itself not locked if the input frequency step is outside of this range. Taking an example from ITU-T G.812, both the pull-in and hold-in ranges for Type III clock type is defined as 4.6 X 10-6, which is the same as +4.6 ppm. Table 3-3 in Chapter 3 provides a quick ref- erence of these frequency ranges for different types of clock nodes. When the PLL is tracking an input reference, it is the loop filter that is enforcing the limits of these frequency ranges. The loop filter is usually a low-pass filter, and as the name suggests, it allows only low-frequency (slow) variations to pass through. That means it removes high-frequency vari- ation and noise in the reference signal. Conversely, a high-pass filter allows high-frequency vari- ations to pass and removes the low-frequency changes. While these filters are discussed in the next section in detail, it is important to note that "low-fre- quency variations" does not refer to the frequency of the clock signal, but the rate with which the frequency or phase of the clock signal varies. Low rate (less frequent) changes are a gradual wander in the signal, whereas high rate changes are a very short-term jitter in the signal. You will read more about jitter and wander later in this chapter. Because PLLs synchronize local clock signals to an external or reference clock signal, these devices have become one of the most commonly used electronic circuits on any communication device. Out of several types of PLL devices, one of the main types of PLL used today is the digital PLL (DPLL), which is used to synchronize digital signals. It is worthwhile noting that, just l