software routine that generates eCPRI headers in the transmit direction and/or parses them in the receive direction. In this regard, eCPRI is no different from any other fast path packet processing implementation that is implemented in networking stacks and all optimization techniques apply. DSP-like functions are explicitly outside of the scope of this function: this is strictly about un)packing IQ samples in Ethernet frames. 3. The IQ extraction and (optional) decompression: this is the building/consumption of the IQ buffer that the DSP algorithms use in the receive direction and generate in the transmit direction. These functions involve a memory copy operation (read and write of IQ samples) as well as lightweight signal processing to perform the (de)compression activity. Topics 1 and 2 are benchmarked like other software benchmark analysis operations and broken down into a clock cycles/function as we did for other packet processing components. The cycle count/packet is then converted into CPU loading by multiplication with the eCPRI packet rate. We take the example from earlier with the following modem configuration: 5G/NR eMBB DL/UL OFDMA modem Time Division Duplex (TDD) downlink slot: 2 symbols PDCCH, 1 symbol Demodulation Reference Signal (DMRS), and 11 symbols Transmit uplink slot: 2 symbols PDCCH, 1 symbol DMRS, 10 symbols Receive, and 1 symbol Rx/Tx switch up to 100 MHz single-carrier RF bandwidth 30-KHz subcarrier spacing, 0.5-ms TTI. 1 X DMRS/slot 8 antennas, 4 layers 16 UE/TTI 312 Open Radio Access Network (O-RAN) Systems Architecture and Design downlink/uplink throughputs of ~ 2.5 Gbps at Medium Access Control (MAC)/PHY level We calculate theoretical IQ sample rate as: 3276 X 14 symbols (peak) X 32b (IQ) X 2000 slot/ second = 2.93 Gbps. Assuming 10% packetization overhead and (roughly) 1-KB eCPRI frames, this is ~ 400 K frames/second. Assuming ~1000 CPU clocks/packet (benchmark to be sourced from benchmarking), this equates to 400 M clock cycles/second/100 carrier/layer. At 4 layers, this is 1.6 G c