is and for an O-RAN equipment designer to develop the solution themselves. For example, they could use a stan- dard PLL with a DCO capability for the SyncE filtering and DCO portions, implement the time-of-day counter in an FPGA or as part of an Ethernet PHY in some cases, use an existing timestamping PHY and network driver, and either attempt to write the PTP stack and servo from scratch or use an open-source solution, such as the Linux ptp4l package. However, such an approach can easily result in unforeseen challenges and delays, espe- cially if the developer's area of expertise is not rooted in synchronization. Therefore many designers opt for a reference design approach from a vendor that can provide both some of the hardware components and the software functions. For example, such as solution might include a hardware PLL/DCO along with PTP stack and servo software and the necessary time-of-day counter IP to implement the complete solution on a defined platform, for exam- ple, one of the FPGA-based SoC solutions that are popular in O-RU designs. Not only does such an approach reduce design effort and time to market, but it also helps ensure perfor- mance since the vendor will typically be able to provide test reports measured on the refer- ence design, as opposed to the developer needing to set up a test environment and conduct their own testing to gain confidence in the performance. Chapter 8 Synchronization in open radio access networks The effects of timestamping location and resolution Oscillator selection and holdover One consideration that is often significant in the design is the sync subsystem is the selection of the local oscillator, since this can easily become the single most expensive sync-related component. There are two factors to consider when deciding on the oscillator requirements: the stability needed for normal operation and the stability needed when the network clock source is lost. For normal operation, we have already mentioned the need for a stable oscillator for the physical layer, Syn