orks in conjunction with a host or control plane processor, which is connected with the traffic manager in the majority of the cases over a Peripheral Computer Interconnect (PCI) bus. For the case of multicast traffic, the embedded SAR module, which works with its own multicast tables, which are stored in its own memory subsystem. As we have learned in previous chapters, the memory technologies for the various subsystems do vary between chip vendors. Different memory technologies address different needs. We summarize the choices of memory technologies and the rationale behind their respective use in Chapter 16, "Systems Engineering Issues." We will therefore not expand on this issue here. Incoming packets arriving from a line interface (physical [PHY] or framer) are classified either by embedded functionality offered by the network processor or by an external classification coproces- sor. A special descriptor (or tag) is generated, which is attached to the packet which is then forwarded for subsequent buffering or processing. In the case of look-aside architecture, the traffic manager will receive the traffic descriptors and only then will packets be fetched from the buffering memory. In the flow-through approach, the packets flow through the traffic manager. Deep packet analysis or further classification may be required. Another specialized coprocessor usually accomplishes this. Security coprocessors may also be used in some contexts. Packets may have to be buffered by the traffic man- ager either at ingress or at egress (with respect to the switch fabric) and sometimes at both. Not all traffic managers support all of these capabilities. Traffic managers may contain the inter- face with the switch fabrics. Standards interfaces are usually chosen, such as System Packet Interface 4 (SPI-4) and Network Processing Forum (NPF) CSIX, to connect the traffic manager to the switch fabric chipset component that lies on the line cards. This will then handle the interface with the cross- bar component on the switch fabric c