 Hoyt; system integrator Bob Dixon; and Bill Judge, Bragi Freymodsson, and Bob Gold. Although retaining the spirit of the DS-SS system developed at Sylvania, technologically the design evolved through several more phases at Magnavox. Nowhere was this more obvious than in the design of the SS code generators, the heart of the system. The earliest Magnavox code generators were built using a pair of lumped constant delay lines, run in syncopated fash- ion to achieve a rate of 5 Mchips/s. This technology was expensive with a code generator costing about $5000, and was not technically satisfactory. The first improvement in this design came when the delay lines were transistorized, and a viable solution was finally achieved when 100 of the first batch of high- B, gold-doped, fast rise-time 2N753 transistors made by Texas Instruments were received and used to build a single-register code generator operating at 5 Mchips/s. Originally to facilitate SS code synchronization, the system employed a synchronization preamble of 1023 chips followed by an m-sequence pro- duced by a 31 stage shift register. Register length 31 was chosen because the period of the resultant m-sequence, namely 2,147,483,653, is prime, and it seemed unlikely that there would exist some periodic substructure useful to a jammer. Lacking knowledge of the proper connections for the shift regis- ter, a special machine was built which carried out a continuing search for long m-sequences. Problems were encountered involving false locks on correla- tion sidelobe peaks in the sync preamble (sometimes it seemed that a cer- tain level of noise was necessary to make the system work properly), and concerning interference between different ARC-50 links as a result of poor cross-correlation properties between SS codes. The ARC-50 was configured as a fully coherent system in which the SS code was first acquired, and the sinusoidal carrier was then synchronized using PLL techniques. Because of apprehension that jamming techniques might take advantage of coupling betwe