pplications that require it. In order to maximize the impact of any combination among the main parameters of processing power, throughput, and bandwidth, the systems designer can easily combine the CPs of the C-5 network processor. For instance, to scale the bandwidth, multiple CPs can be clustered in parallel log- ical aggregates for wider data streams while maintaining the same simple and straightforward soft- ware model. Likewise, to increase the processing power for a particular application, the CPs can be cascaded in a pipelined fashion to enable higher-performance processing on the same bitstream. This is an interesting way of applying processing power to a set of tasks independently of the actual data Downloaded from Digital Engineering Library McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. MOTOROLA'S C-PORT™ FAMILY OF NETWORK PROCESSORS 126 NETWORK PROCESSORS rate. Sophisticated hardware mechanisms allow one or both of these techniques to be engaged with- out placing a further burden on the overall software complexity. The C-5e can be used as a stand-alone device with the possibility of supporting up to OC-48 line rates or four OC-12 streams in full duplex. However, for higher-speed applications that may require OC-48c full-duplex capabilities and channelized applications, the Motorola's M-5 Channel Adapter will be used. The M-5 Channel Adapter can seamlessly connect the external world onto the physical interfaces or the fabric interface of the C-5e in various user-defined configurations. The M-5 Channel Adapter accepts both Packet over SONET PHY Level 3 (POS-PL3) and UTOPIA 3 framer interfaces into the C-5e network processor's 16 clustered CPs, as well as its FP interface at up to OC-48c/STM- 16 wire speeds. Both SPHY and MPHY framers are supported on the C-5e CPs, and the FP also sup- ports SPHY framers. Up to 48 logical interfaces can connect through the MPHY, thereby enabli