nologies [75]. As the need for very large amounts of on- board memory is increasing, the use of DRAM technologies in space systems is becoming more common [76-81]. DRAMs are prone to SEU due to three primary mechanisms: storage cell errors, bit-line errors, and a combination of the two. The reader is directed to the review article by Massengill [75] for an excellent in-depth summary of SEU effects in DRAMs. 3.3.1 Storage Cell Errors Figure 3.7 illustrates the mechanism for storage cell errors in a field plate capacitor DRAM [75]. In this kind of DRAM a stored "0" is represented by electrons occupying a potential well under the field plate, while a stored "1" corresponds to electrons being depleted under the plate. Following a particle strike, electrons can be collected at the reverse-biased field plate. In the case of a stored "0", this just reinforces the original state, but a stored "1" can look like a stored "0" after electron collection. DRAM storage cell errors therefore can characteristically show a very II-17 large pattern dependence. Note also that data patterns may be inverted internally depending on the memory, SO that "0" to "1" errors are observed externally [73,74]. Two other effects can lead to storage cell errors in DRAMs. The ALPEN effect described in Section 3.2.2 can lead to channel conduction that shunts charge onto the storage cell, disturbing the cell information [64]. In DRAMs with closely spaced trench storage cells, charge can be transferred between two storage nodes by a particle track shunt effect [82]. In this case, the particle track intersects neighboring storage nodes in opposite memory states, and the resulting charge transfer between nodes can upset one or both storage nodes. 3.3.2 Bit-Line Errors Bit-line errors can result if sufficient charge is collected during a read cycle to create a charge imbalance on the precharged bit lines [75]. Because they can only occur during a read cycle, bit- line errors have a direct dependency on the read access frequency, with an increasing error