Status CRC Unit Multiply 32-bit & LRU Execution Logic Find first bit CRC-remain (6 bit) Add, Shift, Status Entry Local CSR's Logical Timers To next neighbor 128 D 128 S Xfer Out Xfer Out Timestamp D-pull bus S-pull bus FIGURE 5.3 The internal architecture of Intel's 2nd generation microengines. (Source: Intel) in a microengine has its own program counter, signal events registers, wake-up events register, and segmented storage among the 256 transfer and general-purpose registers within the microengine. The microengines are programmable using a symbolic microcode instruction set optimized for bit stream manipulation. It offers bit, byte, word, and double-word instructions, as well as a variety of optimization tokens. A key feature of the IXP1200 is its ability to swap contexts from one thread to another without affecting performance. The key benefit of multithreading is that each microengine can do useful work even while other threads are waiting for memory transactions to complete. This feature makes the IXP1200 rare, if not outright unique. Software engineers working on the embed- ded code will have a vested interest in taking advantage of this ability to tune code for maximum allelism and performance. The architecture of the IXP is clearly based on symmetric multiprocessing (SMP). As a result, it is very flexible. However, this flexibility comes at a price. The IX bus is a 64-bit-wide bus with a bandwidth of 4.2 Gbps at 66 MHz, 5.1 Gbps at 80 MHz, and 6.26 Gbps at 104 MHz. It works in a demultiplexed fashion (unlike PCI), SO it allows easy exter- nal device interfacing. In its split mode of operation, it can be configured as two separate 32-bit buses. From the newer Intel NPUs, the 2400 offers 2 unidirectional 32-bit media interfaces (receive sig- nal [Rx] and transmit signal [Tx]) programmable to be System Packet Interface version 3 (SPI-3), Utopia 1/2/3, or CSIX-L1. Each path is configurable for 4X8-bit, X16-bit, 1x32-bit, or combina- tions of 8- and 16-bit data paths. We do not intend to present an exhaustive