ability becomes the major component of dTE generated within a PTP node. Note that the PTP messages themselves can carry sub-pico- second values for timestamps, but that does not help if the value of the timestamp is much less precise. One of the most effective ways to minimize dTE because of this issue is to employ timing-aware nodes with a higher timestamping resolution. The details on the timestamping engine and its accur- acy in the design of a PTP clock are further covered in Chapter 12. For now, it is enough to know that this variability in timestamping is an important reason for dTE in a PTP clock. It is also important to appreciate how time error accumulates and propagates in timing networks us- ing hybrid mode, which uses SyncE for frequency combined with PTP for phase and time. To un- derstand this, one should understand the relationship between the SyncE frequency domain and its impact on packet-based time synchronization process. Figure 9-18 illustrates a model for T-BC and T-TSC that captures the relationship between the two timing domains very well (this is covered in Appendix III of G.8273.2). The figure shows a PTP clock with two separate clocks internally, a frequency clock locked to the physical frequency input and a time clock locked to the PTP input. There is a relationship between them, which is that the time clock uses the frequency clock to tick over the time. This also means that the TE from the fre- quency clock (after applying filters) is inherited by the time clock. T-BC/T-TSC 1PPS phase output PTP time input PTP time output clock (T-BC only) Physical layer Frequency Physical layer frequency input clock frequency output Figure 9-18 Model of T-BC/T-TSC Showing Signal Flows-Based on Figure III.2 of ITU-T G.8273.2 Recall that each timing node passes the physical layer frequency input through an LPF to filter out any jitter. When operating in hybrid mode, although the jitter is filtered out, the frequency clock in- jects the wander accumulated in the SyncE network into the time clock. This b