s this function as the timekeeper block. Like 1PPS, the value of the time of day also needs to be distributed to other components of the NE. A good example is loading a representation of the time of day value from the timekeeper into the TSU, which is then used for timestamping of PTP packets (normally this mechanism uses the TAI timescale). 12.1.1 Designing a PTP-Aware Clock So far in this chapter, the sections separately introduced a hardware and software architecture for frequency, phase, and time synchronization. Now, it is time to combine these separate elements to complete an architecture for an NE with full timing support. Full timing support is usually implemented as an NE that supports PTP hybrid mode along with front panel ports to receive ToD and 1PPS from external sources. Because it requires both physical methods and PTP packets, the NE is expected to incorporate all the possible methods of clock syn- chronization in its design. Figure 12-4 shows the hardware and software architecture for an NE with full timing support. No- tice how the different components discussed separately in earlier sections come together for design of an NE with full timing support. This section focuses on the design required to support the complete clock functionality, with particular focus on the PTP components. PTP is designed to provide time transfer on a standard Ethernet network with a synchronization ac- curacy in the range of 10s of nanoseconds. This is possible only by leveraging special hardware components to assist PTP operations and accompanying them with well-built software algorithms. Remember that to achieve the most accurate synchronization, system designers need not only to choose the hardware components correctly but also carefully design such equipment to minimize any systematic loss of accuracy. It is the same when designing networks for synchronization ser- vices-the equipment participating in such networks needs to be carefully engineered to carry tim- ing services. The sections that follow discuss the di