ferent adaptation algorithms and with and without ATC. From the figures it is evident that the insertion of an equalizer brings a performance degradation in the absence of dispersion, but increasing the dispersion increases the per- formance of the equalized receiver. From an implementation point of view, the FFE-DFE is generally realized in digital CMOS technology. In order to digitalize the band-limited photocurrent, a fast ADC is required. After the ADC, depending on the complexity of the tracking algorithm and on the number of taps, both a high-performance DSP and an FPGA can be used. It is difficult that the volumes related to long-haul and ultra-long-haul systems justify the use of a spe- cific ASIC, but FFE-DFE has been proposed also for interconnection on multimode fibers SN (dB) Uncompensated w/o ATC w/ATC FIGURE 5.57 Performance of an FFE-DFE dispersion compensator on a w/ATC dispersive fiber line. An equalizer with nine taps in the FFE and four in the DFE is considered, with two different adapta- tion algorithms and with and without ATC. (After Koc, U.-V., DL (ps/nm) J. Appl. Signal Process., 10, 1584, 2005.) ASN (dB Uncompensated w/o ATC w/ATC FIGURE 5.58 w/ATC Performance of an FFE-DFE dispersion compensator on fiber line with PMD. An equalizer with nine taps in the FFE and four in the DFE is considered, with two different adapta- tion algorithms and with and without ATC. (After Koc, U.-V., PMD (ps) J. Appl. Signal Process., 10, 1584, 2005.) Telecommunication Networks and class C G-PON. In these cases, if the use of equalizers becomes diffused, the develop- ment of dedicated ASICs is more than probable. From an implementation point of view, the ADC is the bottleneck of the FFE-DFE design, since the ADC is a power-consuming component at high speeds and cannot exploit the parallelization of the digital signal in the following components. Today, ADCs that realize a sampling at 5-10 GHz are available on the shelf, but arriving at 80 GHz requires special- ized and power-consuming circuits, while 200 GHz i