igitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES 178 NETWORK PROCESSORS N2CTM (the abbreviation of napkin-to-chipTM) platform. CoWare enables C-based design, simulation, and analysis. Therefore, it facilitates parallel hardware and software design and coverification instead of the traditional hardware and software partitioning of the problem. Interested readers can obtain more information from each company. Tensilica states in its product literature that in IP forwarding/routing, the addition of a few well- thought-out instruction extensions on its base instruction set and about 6,000 gates of extra logic on the fundamental core, which is usually a little more than about 100,000 gates, enables the achieve- ment of around 12 times the performance of a typical 32-bit RISC equivalent. This is important, and it argues in favor of the company's technology as opposed the technology proposed by its few direct competitors. However, it does not allow the multigigabit handling of real-time traffic, which requires deep packet inspection, classification and modification in conjunction with traffic management, flow control, scheduling, and SO on. It only allows this if a large number of multiple similar RISC engines are integrated. We will discuss benchmarking network-processing applications later in the book. At this point, we will only mention some rudimentary benchmarking efforts coming from the Embedded Multi- processor Benchmarking Consortium (EEMBC) forum. This forum was originally created to objec- tively measure and rate standard CPUs. However, standard computing applications such as word processing, database querying, spreadsheet calculations, and graphics rendering have a completely different temporal statistics and spatial structure where caching works miracles. As a result, the tra- ditional computing architectures and plat