e Xelerator NPUs can be imagined as a large program- mable pipeline fed from one side by one to four (depending on the model) Rx ports implementing the SPI-4.2 interface and fed from the other side based on the NPU model between one to four Tx ports implementing SPI-4.2. Four look-aside engines allow interfacing with external coprocessors, SRAM, TABLE 9.1 Xelerator Network Processor Models Chip Model Number of 10 Gbps Ports Packet-Processing Performance 25 Mpps 50 Mpps 100 Mpps 1. An interesting discussion on the advantages of using data flow architecture to process 40 Gbps traffic can be found in Gary Lidington's "Data Flow Architecture Must Match the Network to the Application," published by EE Times (May 9, 2003). The article can be found online at www.commsdesign.com/story/OEG20030509S0035. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES 156 NETWORK PROCESSORS and TCAM with the possibility of multiple accesses to each one of these resources per processed packet. The programmable pipeline has internal access to other hardware resources such as hash engines, classification hardware, counters, meters, and even an internal TCAM engine that manages the search process. The programmable pipeline is the implementation of the company's PISC architecture. It is essen- tially a packet-editing chain that performs operations on packets as they traverse the pipeline from the Rx side to the Tx side. All memory access channels are equipped with integrated ECC for carrier-class reliability. In order to be able to consult memory at full-duplex wire speed, the company's traffic man- ager needs reduced latency DRAM (RLDRAM) that behaves like Rambus-based DRAM but with sig- nificantly lower latency. The Xelerator traffic manager is available in two configurations-T10s and T10d. These are avail- able with one or two 10 Gbps ports (eith