ws recurring operations to be car- ried out efficiently. Beyond the basic architecture of Figure 5.49, a much higher degree of parallelization can be realized in high-performance DSPs, as shown in Figure 5.50. This architecture is inspired by what is presented in [65]; however, it is not intended to be the real product architecture, as it is simplified and schematized for explanation purposes and to present a more general example. Here, up to four MACs can be put in parallel to support the ALU in executing recurrent operations. The MACs are not connected to the ALU via the program bus, but via dedicated connections that allow a much more effective pipelining. Moreover, different DSPs can be built, where one or two MACs can be substituted by other kinds of support units that operate in parallel, like shifter or more complex logical units that can perform also complex operations using hardware-coded instructions. The pipeline operation and the division of the computation load among the ALU and the other parallel processing units are cared for by a specific part of the chip, a program control unit. This is supported by a sequencer that constructs the sequence of instructions for each parallel element. The program control unit has also as support an emulation unit that allows more com- plex operations that have to be emulated via the inner language of the machine to be solved without charging the ALU. As a matter of fact, emulation is a complex operation that would slow the pipeline operation if it would be in charge of the ALU. Finally different input/output units exist for data and program that are not shown in the figure. 5.7.4.2 DSP-Embedded Instruction Set Besides architecture that facilitates intense real-time mathematics, the DSPs are equipped with an internal set of machine language instructions that are very different from those of general-purpose CPUs. Technology for Telecommunications: Integrated Optics and Microelectronics Program memory memory Load/ Load/ Scalar store store Program memory memory/ Registe