. singular value decomposition and recursive least squares minimization, use QR factorization as a building block. Although the term "algorithm based" potentially implies a software implementation, these techniques are directly applicable to hardware based implementation of the algorithms. The checksum encoding scheme indicated for matrix multiplication is directly applicable to a hardware implementation which utilizes mesh-connected (orthogonal) array processors. The overhead time for algorithm execution to perform the additional checksum and array product operations in a software implementation of the algorithm become additional hardware overhead in the form of additional processing elements. The processing element overhead for the checksum encoding implementation for multiplying the n X n matrix by an m X m matrix is n 1. For small matrices, this overhead is as high as 125%, and for very large matrices the overhead will be on the order of 3% to 6%. There is an additional time penalty which is incurred due to the need for the processing elements to perform the checksum computations on input matrices and to verify the resultant matrix. An enhancement to the checksum encoding scheme, described as a resultant memory map provision, performs these computations in additional processing elements, eliminating the time penalty and providing the capability to utilize row and column checksum differences to accomplish single error correction. The weighted checksum scheme was indicated above as a means of achieving multiple error tolerance. The ability to tolerate r errors results in the requirements of 2r weighted vectors. This results in significantly higher overhead, approximately five times the overhead to achieve triple error tolerance. The use of error detection and time redundancy are indicated as possible means to achieve multiple error tolerance at a more acceptable level of overhead. An implementation which utilizes algorithm based structure for error detection and time redundancy through the use of processor roll