e that is highly optimized to the application. Most implementations follow a "Baseband on a Chip" architecture where the bulk of the Physical Layer processing is implemented using a combination of DSP cores and hardware accelerators-also known as a heteroge- neous multicore integration. The hardware is proprietary and so is often the software; tradi- tional implementations of ISC products assume the device (silicon) vendor to provide some form of a reference Physical Layer stack that is not required to be opened to the system inte- grator for product hardening or differentiation. In the 4G product generation with its (never materialized) hype around Pico- and Femtocells, roughly a dozen small cell chipsets were developed by vendors such as Broadcom, Freescale (now NXP), Mindspeed (now Intel), Octasic, Qualcomm, and others. The 5G market has fewer vendors including NXP (LA1200), Octasic (OCT3032W), and Qualcomm (FSM100xx). 174 Open Radio Access Network (O-RAN) Systems Architecture and Design Radio frequency subsystem The RF subsystem from the ISC is designed along the same criteria-if not re-using the exact same design-as that of the RU. Because of this, we refer the reader to the RU discussion for more information. Multicore central processing unit selection criteria All CU, DU, and RU systems we described here include a multicore processor, in one func- tion or the other. The choice of multicore processor architecture is an important one, as it defines the software development environment that the implementation teams work with during the duration of the project, as well as any roadmap/follow-on projects that come after. Consider Software re-use. Software development constitutes the bulk of the development effort. Consider selecting an Instruction Set Architecture and/or processor family that is supported by 3rd party stack vendors and does not come with the penalties (cost, time) associated with porting efforts. Tooling support and developer familiarity with tools and libraries is key to quickly ramp up develop