glibrary.com Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. NETWORK PROCESSORS: JUSTIFICATION 34 NETWORK PROCESSORS A CLOSER LOOK AT PACKET PROCESSING Until network processors appeared, system architects had to choose between two ways of tackling the overall design of the packet-processing module in order to implement network devices. One approach would entail using a standard off-the-shelf CPU, which would usually be a RISC processor. This choice is similar to choosing the CPU for the host-processing part of the design par- tition that we just discussed. However, in some cases, especially in network devices intended for low- end devices such as a small wide area network (WAN) router for the small office/home office (SOHO) market, it could also be a CISC processor. In fact, in some of these low-end cases, the packet-pro- cessing function and the host-processing function end up using the computational power of the same CPU chip on a time-sharing basis with the help of a real-time operating system kernel. The other approach would be to design a specialized high-performance ASIC that would handle packet processing. Because most network device design houses are fabless companies, the designer would have to hand off the custom design of the ASIC to a semiconductor house (fab) to have it built. Of course, some major semiconductor powerhouses such as IBM and Intel happen to be both design- ers of networking chips and manufacturers of integrated circuits. Therefore, these vendors obviously enjoy a vertical integration that offers them a more robust market advantage. However, this advantage is economically significant and sustainable only when the vertically inte- grated vendor has already been enjoying high levels of semiconductor manufacturing business that would allow the corresponding complementary metal oxide semiconductor (CMOS) processes at hand to achieve parity or overtake the economics of large silicon foundries such as TSMC. The a