s fashion also results in increased write time for the device. A negative temperature characteristic with significant change in resistance versus temperature results in Figure 6-6. RAM Cell with Polysilicon Resistors [Vinson92] considerable change in SEU and write cycle time characteristics of devices which utilize this technique. Figures 6-7 through 6-10 indicate several techniques for hardening based upon storage latch duplication and the use of state-restoring feedback circuits. Figure 6-7. Upset-Tolerant Memory Cell [Rockett88] Figure 6-8. Principle and Schematic of the Dual Interlocked Storage Cell (DICE) [Calin96] Figure 6-9. Transmission Gate and Clocked Inverter Latch DICE Implementations [Calin96] Figure 6-10. SEU Immune Whitaker Cell [Liu92] Fault Masking and Redundancy One of the techniques employed in fault masking, detection, correction and recovery is that of redundancy. The three basic techniques in the application of redundancy are informational (redundant data structures), spatial (redundant hardware), and temporal (redundant sequential operations). The fault detection and correction capabilities of redundant structures are good; recovery may be either simple or highly complex depending upon the nature of the function performed by each of the structures. The price of redundancy schemes includes increased system hardware content and decreased performance or throughput. Informational and spatial modular redundancy increases hardware content, increasing size, weight, power, cost, and failure rate. Although the increase in hardware content in informational redundancy is typically less than spatial modular redundancy, similar forms of impact are associated with the error detection and correction schemes. Temporal redundancy requires additional time to sample signal conditions in logic implementation and to perform consecutive computation operations in the case of processor implementation. 6.4.1 Error Detection and Correction Coding [Lin83] [Fujiwara90] [Nelson90] [Saxena95] Spatial and temporal redund