nd self-routing capabilities that decouple the arbi- tration complexity from the system capacity issue, are considered among this fabric's strong points. In addition, advanced traffic management and traffic isolation capabilities enable the provisioning of bandwidth through SLAs and the preservation of QoS in realms such as VoIP and virtual private net- works (VPNs). The PI40 family chips contain embedded high-speed serdes and clock-data recovery (CDR) cir- cuits. This combination enables the tight integration of a systems design with high capacity and high performance. In systems where line cards support different wire speeds, the PI40X can be configured as an ingress or egress switch in the fabric, with the PI40C providing the crossbar and arbitration functions. Figure 14.18 shows a 160 Gbps system built from two PI40C devices and eight PI40X chips. The first stage of PI40Xs aggregates the incoming user traffic and connects the traffic to all the second-stage devices. The second stage is essentially the crossconnector, which handles the actual switching function. For example, the PI40SAX can be connected directly to line cards, as shown in Figure 14.19, in a 32X2.5 Gbps I/O system that can be configured as a 32X32 switch operating at 2.5 Gbps. This enables the creation of a shared memory, nonblocking switch for up to 32 user ports. It can support 4 OC-192c ports, 16 OC-48c ports, 32 OC-12c/GbE ports, and other combinations. The afforded over- speed (speed-up factor) is 2:1. This means that for user traffic with a throughput of 40 Gbps, the fab- ric has an actual throughput capability of 80 Gbps. This leaves plenty of headroom for internal segmentation and reassembly as applied to variable-length packet size even under the worst traffic conditions. PI-40X PI-40X 1x OC-768c or 4x OC-192c or 16x OC-48c or 32x OC-12c PI-40X PI-40X Ingress Egress 2x PI-40C ports ports PI-40X PI-40X PI-40X PI-40X Central switch or Ingress or 1st Egress or 3rd 2nd stage stage stage FIGURE 14.18 The structure of a 160 Gbps switch based