t SSB Figure 5.18 Example illustration of SFTD measurement without measurement gap [ 29]. SFTD, SFN and frame timing difference. 706 Chapter 5 Therefore, the only way to sample higher dynamic range analog input signals above 1 GHz was to interleave multiple high-speed ADC cores with a sampling clock that had a staggered phase to each core with the required accuracy, or duty cycle. The analog input needed to be split and multiplexed to each ADC, which provided an opportunity for noise to enter the signal chain and reduce the input power. While this method may provide ade- quate results for some applications, the design was complex and yielded unwanted inter- leaving artifacts in the output frequency domain that needed digital filtering. The interleaving spurs can be seen in the frequency response of an FFT block, where the input offset, gain, bandwidth, and sample timing are not exactly matched across each of the internal interleaved ADC cores. This creates additional planning complexity for the sys- tem engineer to predetermine where interleaving artifacts will be seen in frequency and either avoid or remove them in digital postprocessing. Because each ADC core is discrete, the potential is high for manufacturing mismatch variance among these performance para- meters during the life of a system in production. These mismatches cause imbalances in the periodicity of the incoming signal, and spurious frequencies are seen at the output of interleaved ADCs. The new ADC technologies can take advantage of advanced architectures and algo- rithms that prevent the issues seen in dual and quad interleaved ADCs. Instead of using two interleaved ADCs at half speed, with added artifacts, the performance can be achieved in a single ADC at full speed without the interleaving spurs. Factory-trimmed algorithms and on-chip calibration ensure that each ADC operates to the expected high- performance standards, as opposed to being exposed to the mismatch variances seen from multiple discrete interleaved cores. When spurious frequencie