nd of the CPU. Packets are therefore transmitted only once over the shared bus. In this architecture, a router keeps a central master routing table and the satellite proces- sors in the network interfaces each keep only a modest cache of recently used routes. If a Routing processor Memory Memory (CPU) (RAM) (ROM) FIGURE 7.54 Router architecture based on an input queue realized using line card (LC) RAMs and a time division bus-based switch fabric. The LC processor is indicated as LCuP, SO that the line card is functionally composed by a line interface (LI), a memory and a processor. Telecommunication Networks route is not in a network interface processor's cache, it would request the relevant route from the central table. The route cache entries are traffic driven in that the first packet to a new destination is routed by the main CPU (the central route processor) via the central routing table informa- tion and as part of that forwarding operation, a route cache entry for that destination is then added in the network interface. This allows subsequent packet flows to the same destination network to be switched based on an efficient route cache match. These entries are periodically aged out to keep the route cache current and can be immediately invalidated if the network topology changes. With the new architecture it is easy do demonstrate that, neglecting the time needed to store a packet in the memory resident in the input line card upon the packet reception, the average time needed to process a packet is given by =p(3T+3aT+bt)+(1-p)(t+dt) =(1+2p)t+3apT+(3bp+d-dp)t=t+3apT+dt (7.43) where p<<1 indicates the probability that a packet needs to be routed by the CPU and a, b, d are constants depending on the implementation. From Equation 7.43 it is now clear how the importance of the memory access time is quite small and the improvement of the CPUs elaboration time is key to improve the router performances. However, this condition is realized only when p<<1, that is a condition that is not always realized. By continuou