tions that must be carried out at wire speed and they are not available as standard instructions in off-the-shelf processors. As ordinary off-the-shelf CPUs will need more than one of their standard instructions assembled into a microprogram that performs the intended functionality, these microprograms are executed over multiple clock cycles, stalling the pipeline and taking up time. This further negates the off-the-shelf CPU's capability to cope with the computational load associated with very high-speed traffic arriving and leaving in real time. This example illustrates the inadequacy of the instruction set associated with off-the-shelf CPUs. We will discuss this problem and its ramifications as well as ways to address it from a system designer's point of view in much depth in this book. Some vendors have looked to allocate the necessary work to more than just one such CPU proces- sor. However, in addition to the astronomical and direct increased cost of hardware with such an approach, the sheer complexity and cost (in time and money) of developing the intercommunicating multiprocessor real-time software that is needed to manage such a system efficiently, should not be underestimated. It becomes clear that the use of off-the-shelf CPUs is not the solution to the problem and that some- thing radically different is needed. TRADE-OFFS WHEN DESIGNING WITH ASICS Designers opt for the ASIC approach when the application requires the maximum performance. Typically, an ASIC in this environment delivers better performance than a typical off-the-shelf CPU with the same capacity properly programmed to handle the same packet-processing application. This performance edge has been instrumental in the wide-scale adoption of the ASIC approach in the high- speed network equipment design community. ASICs implementing efficient architectures can also designed to operate extremely fast. As a result, they can certainly provide one path of evolution toward the ongoing satisfaction of the ever-evolving needs in the networking industry