 the correct distribution of the electrical equivalent noise, the performances of the FEC gets better, less for BCH codes, while some- times a more significant difference occurs in turbo codes [100]. This observation allows us to set the target for an advanced FEC to use in ultra-high- speed DWDM systems, to 11 dB of code gain. 5.8.6 Content Addressable Memories As equalization and error correction is instrumental for high-capacity transmission, fast packet routing is fundamental to build the IP convergent network. As detailed in Chapter 7, IP routers and carrier-class Ethernet switches have to compare the address of each incoming packet with the entries of a routing table, whose content indicates the output port where the packet has to be sent. In the IP case, the operation is worsened by the fact that the so-called forwarding table does not contain whole addresses, but only prefixes, and routing is performed by search- ing the longest prefix matching the incoming IP address (see Chapter 3). Since this operation has to be performed several million times a second, it is natural that in large packet switches it is carried out by specialized hardware whose core is generally a content-addressable memory (CAM) [105]. CAM is a derivation of the random access memory (RAM). In addition to the conven- tional READ and WRITE operations typical of RAMs, CAMs also support the SEARCH operations. A CAM stores a number of data words and compares a search key with all the stored entries in parallel. If a match is found, the corresponding memory location is retrieved. In the presence of multiple matches, either several addresses are returned or a priority encoder determines the highest priority match on the grounds of a matching pri- ority policy (Figure 5.75). CAM-based table look-up is very fast due to the parallel nature of the SEARCH opera- tion. A schematic illustration of the CAM working is shown in Figure 5.76. CAMs can be divided into two categories: binary CAMs and ternary content-address- able memories (TCAMs). A binary