n have to implement it by themselves in an FPGA. The 104 MHz clock rate of the bridge opera- tion in this Intel reference design example can only be realized with a specialized ASIC, as FPGA implementations will have to function at a smaller clock rate. The LXT9763HX (Hex PHY) provides six standard media independent interface (MII) ports for various Ethernet media. Only four of them are used in this example to match the number of MAC units. The IXF440 is an octal MAC. It pro- vides eight standard MII 10/100 Mbps Ethernet ports without requiring glue logic to connect with the IXP1200 network processor. The 82599ER is an Ethernet controller that handles the interface with a 10/100 Mbps twisted-pair Fast Ethernet port, which is used here for network management and the overall configuration. In this design example, if it was implemented in real life, layer 3 routing across the optical net- work would also require other more complex protocols implemented in software and running on the IXP1200 itself. In addition, in such an environment, the IXP1200 can also run other gateway-type software. As a result, this system can ultimately serve as the front-end network interface in a CPE environment connecting to the WAN and LAN with substantial local traffic. The combined ingress traffic in this example of 1.422 Gbps is within the measured performance for the IXP1200. These network processors can drive 16 Fast Ethernet ports at wire speed while at the same time perform layer 3 routing (with 1.6 Gbps unidirectional traffic as its theoretical maximum). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. INTEL IXA TM NETWORK PROCESSORS 88 NETWORK PROCESSORS The system buses used in the design shown in Figure 5.4 are summarized as follows: IX bus This consists of two separate 32-bit paths for transmit and receive flows operating at MHz each. It offers 2.1 Gbps ba