nd Elephant Flow handling are mini- mized (see discussion elsewhere). Traffic distribution between transport and GTP/PDCP modules can be done, for example, based on the GRPS Tunneling Protocol Tunnel Endoint Identification (GTP TEID) field. The hardware implementation options for the accelerator are typically either FPGA-based or multicore networking processors (historically PowerPC or MIPS ISA but more recently 146 Open Radio Access Network (O-RAN) Systems Architecture and Design Server CU-CP PDCP-CP CU-UP CU-UP IPSec PDCP-UP Ethernet Ethernet FIGURE 4-5 Scale-out by multiple iNICs. Arm based). Both options come with integrated Ethernet and dedicated logic for ciphering protocols. These features ensure that power efficiency is a step function improved over software-only implementations as found in traditional (x86-based) servers. This type of off- load is not unique to the CU implementation but can be found throughout data center appli- cations where FPGAs and Network Processor Units (NPUs) are often used to offload IO from server cores. DU blades implement Layer 2/Physical layer stacks, either as a software-only function (for legacy 3GPP networks such as 2G and 3G) or with dedicated hardware acceleration (5G and in limited fashion for 4G). An example implementation is shown below in Fig. 4-7: Cell site integrated (CU/DU) solutions These solutions are more similar to the traditional (macro) base station as they provide inte- grated baseband functionality (the DU, optionally including CU functions) into a form factor that is reminiscent to macro base stations: typically, a 19-inch rack with 2U-4U height. We discuss two implementation options: server-based where the DU is built around an off-the- shelf server with acceleration card to turn it into a DU and optimized hardware that is tuned towards the use-case. Chapter 4 Hardware architecture choices 147 Server Blade Server Blade CU-CP CU-CP PDCP-CP PDCP-CP 100GbE Ethernet TOR Switch 2x100GbE 2x100GbE 100GbE Ethernet Backplane 100GbE Ethernet Backplane 100G Etherne