 Circuit switching is implemented using space-time switches that move the timeslots from one frame to another. Timeslots access is 40.4.2 Synchronous Digital Hierarchy (SDH) through multiplexers which operate in 'drop and insert' mode. This works by taking a timeslot that terminates on one channel, and therefore becomes free, and allowing another channel to use that In an attempt to reconcile the different high order multiplexers a timeslot for sending data back out. It can be seen that no method to new set of G. standards have been proposed which can support the dynamically allocate bandwidth is available. US and European variants. CCITT have initially proposed G.708, Figure 40.9 shows how circuit switching is implemented using G.708, and G.709 to offer a ultra high speed Synchronous TDM space-time switches that route the timeslots in high-speed T1/E1 system based on the US SONET. (See Chapter 42.) frames around a network. Time switching (switching timeslots) Timeslots 2345678 2345678 2345678 Trunk 1 Trunk 1 Trunk 1 2345678 2345678 2345678 Space/ Trunk 2 Space/ Trunk 2 Trunk 2 switch 8765432 switch 2345678 2345678 2345678 Trunk 3 Trunk 3 Trunk 3 2345678 Trunk 12 Space switching (switching trunks) Multiplexer (Drop and insert) 0000000 64kbit/s Figure 40.9 Circuit switching used to route frames 40/10 Multiplexers Packet switching, on the other hand, does not require permanent physical link connection problems by utilising an HDLC format bandwidth to be allocated. Data is sent through the network in LAPB and an X.21bis physical interface. discrete packets, each packet only demanding bandwidth on any In order to use X.25 in a packet switch network two components specific link for the time it is being transmitted. In this it is similar are required: a Packet Switch Exchange (PSE) and a Packet Assem- to statistical multiplexing. There are, however, two ways in which bler/Disassembler (PAD). The former takes in X.25 formatted packet switch connections can be tracked through a network for the packets and, after reading 