lls are reasonably consistent in mobile to mobile calls is due to the fact that error concealment is carefully specified across the range of full rate, enhanced full rate and adaptive multirate codecs. M-PEG4, however, permits substantial vendor differentiation in the way that error concealment is realised. This introduced a number of additional quality management challenges. Six years on, the story has moved on but the narrative stays the same. Headline clock cycle counts do not translate directly across into task speed and/or task consistency and stability. Take as an example Samsung's applications processor originally called Humming Bird but now called Exynos, a name apparently derived from the Greek words smart (expynos) and green (prasinos). This is an ARM-based device and competes directly with the Qualcomm Snapdragon device (also ARM based) and TI OMAP and Intel and AMD processors. Intel has a power optimised product codenamed Moorestown that at the time of writing is yet to be launched. All these devices build on the reduced instruction set architecture used in the original Acorn Computer. It is reassuring to know that rather like acorns and oak trees big ideas can still originate from small beginnings. Both the Snapdragon device and the Samsung device (used in Samsung's Galaxy tablet) are optimised for high speed and low power. but achieve that in different ways. Snapdragon chips are optimised to achieve more instructions per cycle and integrate additional functionality including an FM and GPS receiver, HSPA Plus and EVDO modem and Bluetooth and WiFi baseband. The Samsung device has a logic design that can do binary calculations. Both devices can be underclocked or overclocked and the 1-GHz version of the chip sets used in present products can process about 2000 instructions per second. However, the number of instructions needed to perform a task can be very different. This can be due to either how well the software has been compiled or hardware constraints dictated, for example, by memory and interface 