-56 charge in the cell. Simulations of this situation are shown in Figure 6.2a. However, reductions in power supply voltage are usually accompanied by reduced gate oxide thickness. Thinner gate oxides result in higher gate capacitance and higher current drives, SO SEU thresholds increase with decreasing gate oxide thickness if all other parameters are constant (Figure 6.2b). However, if all parameters are taken into account, the overall trend is still a general increase in SEU susceptibility with each technology generation. This trend is shown in Figure 6.3, which is a plot of the simulated and experimentally-measured SEU threshold for SRAMs without feedback resistors in the three most recent Sandia CMOS technologies [70]. A factor that is at least as important as the fundamental changes to the physics is simply the reduction in total capacitance as technologies shrink. Remember that the feedback time for the SRAM cell is to first order related to the RC delay in the inverter pair. As device areas shrink, the gate and drain capacitance shrinks, making the device faster but consequently much more susceptible to SEU. SEU can therefore be expected to continue as a growing concern for scaled technologies. Another area that is likely to become increasingly important is the propagation of single- event transients (SETs) in digital logic circuits. The problem here is that as circuit speeds rise, the probability that a momentary glitch will be clocked as valid data and propagated down the line increases. For example, in Figure 3.11 we saw that even a particle well below the upset threshold can cause a momentary flip in the state of an SRAM cell. Consider the case where this memory cell is actually a digital latch circuit in a microprocessor. In the example of Figure 3.11, if this latch value is read 10 picoseconds after an ion strike and the value is clocked down the line, it matters little that the struck latch eventually returns to its original state, because the corrupt value has already been passed on to the next sta