 the MSC rather than the Validator default test values. C. Press on Random Walk to start the random simulation: after a few seconds, the Report Viewer appears. The Validator has discovered 1 deadlock, 2 MSC violations and 1 MSC verification scenarios. If you do not get any MSC Verification, you can press again on Random Walk. Double-click on 2 MSCViolation and on 1 MSCVerification to expand the reports, as shown in Figure 6.4. Report Viewer 4 reports 1 Deadlock 2 ISCViolation 1 MSCVerification MSC Test1 violated MSC Test1 violated MSC Test1 verified Event: * OUTPUT Event: *** Depth: 47 of V76frame. Transition START Receiver: AtoB: 1 Pld : Parameter(s) AtoB:1 SABME (.0) State : Depth: 11 ready Input V76frame Sender: <<Block DLCa>> DLC:1 Parameter(s) DISC (.0) Depth: 36 Figure 6.4 The reports after the random walk D. Double-click on the left MSC violation in the Report Viewer to generate the corresponding MSC trace: timer T320 has timed-out, therefore signal V76frame has been retransmitted; this scenario does not match the MSC testl. E. Double-click on the MSC verification in the Report Viewer to generate the corresponding MSC trace: the MSC Editor displays a scenario identical to testl. Remark: the button Verify MSC loads an MSC and starts a bit-state exploration (or a tree- search) rather than a random walk. Verify MSC is explained in Chapter 7. 172 Validation of Communications Systems with SDL 6.3 CASE STUDY WITH OBJECTGEODE 6.3.1 Random simulation without observers You will run the random simulation on the V.76 SDL model to discover errors automatically. 6.3.1.1 Run the random simulation A. In the SDL Editor, unload all files except v76.pr, and select Tools > SDL & MSC Simulator. B. In the ObjectGeode Launcher, remove any file other than v76.pr, press the Build button, then if you do not get any SDL errors, press the Execute button. The Simulator starts. C. If the Simulator has not executed automatically the four start transitions (step should be equal to 4), the file v76.startup is missing (see Chapter 4). D. 