ice (CES); Inverse Multiplexing for ATM (IMA); traffic management for ATM; IP and Ethernet High-level Data Link Control (HDLC); IP over ATM; IP over Ethernet; IP over PPP; IPv4 longest pre- fix matching (LPM) routing; IP classification; VLAN tagging and detagging; ATM to Ethernet inter- working; and others. Every port can be immediately set up as an ATM, IP, or TDM port without any overhead or any hardware change. WinPath provides a direct interface with any one of these PHY level standards: T1/E1, T3/E3, xDSL, OC-3 ATM, OC-12 POS, and 10/100 Ethernet. Gigabit Ethernet is supported through an exter- nal and proprietary POS. The Universal Test and Operations PHY Interface for ATM Level 2 (UTOPIA 2) or POS interface is also meant to handle any external need of switch fabric interface. Multiple devices (in a one-master-many-slaves configuration) can be connected on the other UTOPIA interface, connecting up to 63 external DSPs for voice over IP (VoIP) applications (vocoding, com- pression, echo cancellation, and SO on) or up to 6 octal DSL PHYs for DSL applications. Any WinPath's various interfaces can be programmed by applications SO they interwork with any other interface. For instance, one can have ML-PPP over the T1/E1 serial channels, interworking with POS running over the POS OC-12 interface, IP over 10/100 Ethernet, and IP over ATMAAL5 over a multi- PHY OC-3 configuration on the UTOPIA interface. External memory is flash and synchronous dynamic random access memory (SDRAM). Both are 32/64 bits wide and three interfaces are available: one for host CPU interfacing needs and the other two for packet processing. Larger applications may need two chips: one for the ingress path and one for the egress path processing. As an added advantage, lower-end applications, where one WinPath chip can handle both, have only one SDRAM memory bank needed where both processing parame- ters and packet information can be stored, thereby further reducing the chip count and the cost of a solution. The company has announced two major p