ches have a distinct implementation advantage over STS switches when a large amount of traffic must be handled. Bellamy (Ref. 3) states that for small switches STS is favored due to reduced implementation complexities. The choice of a particular switch architecture may be more dependent on such factors as modularity, testability, and expandability. One consideration that generally favors an STS implementation is the relatively simpler control requirements. However, for large switches with heavy traffic loads, the implemen- tation advantage of the TST switch and its derivatives is dominant. A typical large switch is the ATT No. 4 ESS, which has a TSSSST architecture and has the capability of termi- nating 107,520 trunks with a blocking probability of 0.5% and channel occupancy of 0.7. 6.11.3 Review of Some Digital Switching Concepts 6.11.3.1 Early Notions and New Ideas. In Section 6.11.2 the reader was probably led to believe that the elemental time-switching stage, the TSI, would have 24 or 30 time-slot capacity to match the North American DS1 rate of the "European" E1 rate, respectively. That means that a manufacturer would have to develop and produce two distinct switches, one to satisfy the North American market and one for the European market. Most switch manufacturers made just one switch with a common internal switching network, the time and space arrays we just discussed. For one thing, they could map five DS1 groups into four E1 groups, the common denominator being 120 DS0/E0 (64-kbps channels). Periph- eral modules cleaned up any differences remaining, such as signaling. The "120" is a num- ber used in AT&T's 4ESS. It maps 120 eight-bit time slots into 128 time slots. The eight time slots of the remainder are used for diagnostic and maintenance purposes (Ref. 8). Another early concept was a common internal bit rate, to be carried on those "high- ways" we spoke about or on junctors. At the points of interface that a switch has with the outside world, it must have 8-bit time slots in DS1 (or high-level mul