thm both in terms of number of states and in terms of number of transitions, SO as to be able to manage it with a DSP or programming an FPGA [80,81]. One of the most used techniques is that leveraging the circuit scheme of Figure 5.58. Once a new sample is received the probability density function that a "1" is transmitted conditioned to the value of the received sample is estimated starting from the previous N samples. This is the transition metric for the transition to the two possible new states: a "1" is received or a "0" is received. Two operations help in limiting the complexity of the MLSE [82]: 1. Limiting the number of bits per sample and the number of samples per received intervals; as a matter of fact, if n samples are taken each bit interval and each sam- ple has N bits and the number of MLSE states to be considered in every received bit interval is n2N, a number that easily becomes too large to be managed by a DSP. 2. Simplifying the probability estimation (i.e., the channel characterization) contrib- utes to speed the algorithm. These two elements have been drastically simplified in order to realize equalizers that work at 10 and even at 40 Gbit/s, and the surprising thing is that the Viterbi algorithm works well also with a very simplified state machine. As an example let us consider the architecture presented in Figure 5.59, where a trace- back of three bits is realized via a parallel processor working at 622 Mchips/s. The number of bits per sample is eight, but only one sample is extracted per bit period. Demux Analog Data out receiver finder selector Channel estimator Clock FIGURE 5.59 Block scheme of an electronic equalizer implementing MLSE equalization with the Viterbi algorithm. Telecommunication Networks ASN (dB) Uncompensated FFE9/DFE2 10 Gbit/s FIGURE 5.60 Performance of an electronic equalizer implementing MLSE equalization with the Viterbi algorithm at 10 and 20 Gbit/s on a fiber line with chromatic dispersion. The per- 20 Gbit/s formances of an FFE-DFE with nine FFE taps and two DFE 10