ct without any glue logic to typical NPU chips. However, surprisingly, it cannot connect to the company's iPP. Therefore, Silicon Access provides field-programmable gate array (FPGA) code, which the company calls IZB. This allows the bridging between the iAP's ZBT bus and the iPP's high-speed coprocessor channel (HCC) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES 140 NETWORK PROCESSORS interface. The latter is discussed in the next section. With the IZB code on an FPGA chip, a single HCC can be shared by up to four iAP chips, thereby allowing table sizes of up to 1M entries. The iPP is clocked at 300 MHz, can process 30 Mpps, and can offer up to 115 Gbps bandwidth for connections with other look-aside or in-band coprocessors. The chip contains 4 clusters (called iAtomTM cores) of 8 packet engines, making a total of 32 programmable 8-way multithreaded engines that handle all the required packet modification as well as custom-written code. Therefore, these 32 packet engines provide a total of 256 concurrent threads of execution with a context switch of zero latency and an overall computing power of 9.6 billion operations per second. Of course, classical bit manipulation operations add flexibility to the tasks of adding, replacing, inserting, modifying, and deleting fields anywhere in a packet. Silicon Access has created several hardware-assisted coprocessors that can parse and insert bit fields into packet headers or that can hash bit sequences, etc. A most interesting piece of assistance hardware inside the iPP chip is called the Massively Parallel Branch Accelerator (MPBX). This block of custom hardware increases the execution performance over traditional reduced instruction set com- puter (RISC) execution more than 100 times when code for complex conditional statements is run. The compiler simply detects the presen