o everything possible to minimize the use and the cost of it. However, the expected wire-speed performance of specific platforms may dictate the use of SRAM. For example, the Agere NPU 5 Gbps platform implies that the systems designer can get without using external SRAM. This is because of the embedded 2.5MB of on-chip SRAM. If the same company's technology is used for a 10Gbps system, external SRAM is definitely required. As a mem- ory technology, SRAM is indispensable, especially in situations where a large number of queues or a large number of linked lists must be traversed because of the multiple accesses needed to assemble working lists. SRAM is also used to monitor performance. A common player on the high-speed network-processing stage is the zero bus turnaround (ZBT) synchronous SRAM (SSRAM). This high-speed SSRAM flavor is ideal for several current network- ing applications. This is because ZBT SSRAM offers superb bus utilization as buses can be used with- out any bus dead cycles, even when transitioning from read to write. In other words, ZBT SSRAMs can read or write every clock cycle for 100 percent bus efficiency. Clocked up to 166 MHz, ZBT SSRAM is available in chips of 2Mb to 18Mb. Micron, for example, seems to have a product roadmap for up to 72Mb. DDR SRAM and quadruple data rate (QDR) SRAM are also available. The DDR SRAM ap- proach accommodates transfers through different ports, SO if an application is balanced in read/write operations, it turns out to be a superb choice. QDR SRAM was developed by Micron, Cypress, and IDT, and is useful in 10Gbps designs. The data inputs and outputs are separate and operate simulta- neously in QDR SRAM. Because each data bus operates on two words of data per clock cycle, each bus effectively doubles its data rate. Since both of these buses operate in parallel, the QDR SRAM component operates on four bus widths of data per clock cycle. Therefore, the minimum set on which data can be operated on is two words-two times the component's bus width. QDR is ideal for bal