h the simulation code SIFCOD [291], which permits numerical modeling of multiple devices at once. Modeling an SRAM cell consists of four simultaneous device simulations, tied together through contact boundary conditions, as illustrated in Figure 5.3 [67]. These simulations were the first reported that were capable of studying the actual upset process at the device level, and were thus key to forming an understanding of fundamental mechanisms leading to upset [67,89,90]. Because four numerical device simulations must be performed at once, this technique is fairly computer intensive. More importantly, however, the SIFCOD program performed only 2D computations and hence suffered from the geometric limitations that have been discussed above. II-51 ION PATH Figure 5.3. Illustration of the use of multiple simultaneous device simulation to compute the SEU characteristics of a CMOS SRAM [67]. Each device's characteristics are simulated in the multidimensional device domain. Commercial 3D simulators such as Davinci have a similar capability to simultaneously simulate multiple devices [245], but are not generally used in this mode. Recently, the simultaneous solution of device and circuit equations has been increasingly used. This technique, known as mixed-mode or mixed-level simulation, was developed by Rollins at USC/Aerospace in the late 1980s [292]. The term "mixed-level" is probably less confusing and more descriptive than "mixed-mode." In a mixed-level simulation of SEU, the struck device is modeled in the "device domain" (i.e., using multi-dimensional device simulation), while the rest of the memory cell is represented by SPICE-like compact circuit models, as illustrated in Figure 5.4. The two regimes are tied together by the boundary conditions at contacts, and the solution to both sets of equations is rolled into one matrix solution [292,293]. The advantage is that only the struck device is modeled in multiple dimensions, while the rest of the circuit consists of computationally-efficient SPICE models. This decrea