us for instructions and data. Once a processor is designed with customized extensions or options, the tool will generate the appropriate RTL code files. The company also provides a series of ready extensions such as customized MAC instructions as well as an array of peripheral IP cores to help facilitate an SOC design. It also offers a complete series of development tools, high-level language compilers, simulators, and debuggers that facilitate and accelerate a systems design based on the company's technology. The technology is very flexible, but for fast network-processing applications it suffers from the same generic weaknesses that simple RISC architectures exhibit across the board. In other words, a designer must do the following: Deploy a large number of multiple cores to share the load. Decide how to schedule work on each core. Sort out how to coordinate the cores on tasks that make part of a larger piece of work the chip must perform. Decide how to allow the multiple embedded cores to communicate among themselves and with a supervising host CPU. 8. See several pertinent articles published in the Microprocessor Report. A good example is Tom R. Halfhill, "Tensilica Xtensa V Hits 350 MHz" (September 16, 2002). This is available online to paid subscribers at www.mdronline.com/mpr/h/2002/0916/ 163701.html. This article discusses comparative results between Tensilica and ARC processor cores based on ECL-certified results of the EEMBC benchmark suites. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES ALTERNATIVE APPROACHES TO NETWORK PROCESSING NET ASICS AND DESIGNING WITH IP CORES Instruction 32 X 32-bit Fetch Register Interface Instruction Decode OR, etc. Example Extension of the Instruction Compare implementation Decode of an e.g. ACS instruction Select ext