he redundancy is less. Furthermore, the sequential processing for the trellis-based algorithm and the interleaving/de-interleaving also cause long processing latency. In contrast, the LDPC decoding complexity is code rate dependent. Therefore, the complexity decreases as the code rate increases (or as the redundancy decreases); the decoding operates over the parity check matrix, and as there are fewer check equations with higher code rates (and 1 Manufacturing process for semiconductors - an Xnm terminology does not bear any direct relation with the actual size of a transistor but refers instead to a particular generation of such a process. The same X does not imply the same transistor size between foundries. However, the relative size reduction from one generation to the next is typically similar between foundries. The smaller the X, the more advanced the process, the smaller, faster, and more power efficient the transistor. 13.2 High Data Rate, System Flexibility, and Computational Complexity Table 13.2 Area efficiency comparison. Turbo decoder LDPC decoder LDPC decoder (mother code rate = 1/3) (Code rate = 2/3) (Code rate = 0.88) 12.48 27.72 efficiency (Gbps/mm2) Table 13.3 LDPC decoding complexity. Code rate Edge count Relative complexity 1.0 (reference) fewer redundancy bits), the decoding is as a result simpler. This allows for a significant data rate boost at reasonable costs for the adopted foundry process, and hence makes the targeted peak data rate of 20 Gbps for NR feasible from that standpoint. 5G NR LDPC is a rate-compatible design in order to support HARQ. Retransmissions can add redundancy bits for error correction; however, the decoding complexity per codeword is increased. Table 13.3 shows the complexity increment with respect to a high code rate of 8/9. When the code rate is reduced to 1/3, the decoding complexity is increased by a factor of 4. To confine the worst-case complexity, the HARQ buffer size is limited to accommodate code rates down to 2/3 according to the maximal available data volum