s such as signaling when a memory transfer has finished. The scalability of the technology stems from the fact that the architect-designer of a network- processing superchip using ClearSpeed IP can configure his or her design by judiciously playing with the following parameters in a five-dimensional space: The number of embedded MTAP processors in the chip. The number of PEs per MTAP. The amount of cache memory and instruction memory per MTAP. The number of lookup engines per TLE. The amount of table memory available per TLE. In the implementation of a reference design of a classification engine, ClearSpeed has used 4 MTAP processors, which each have 64 packet processing engineers, a TLE embedding 24 lookup engines, and 1MB of embedded memory for the TLE. Such a device is capable of classification and forwarding in protocol environments such as IPv4/v6 and MPLS (label-switched router [LSR] and label edge router [LER]) sustaining a performance of more than 100 Mpps. If the reader consults a typical traffic-correspondence table such as the one shown in Appendix II, this translates to a simplex OC-768 link with 40-byte packets. The idea is that by replicating this device, a unit can be created that can condition the traffic by performing policing and metering, among other tasks. Traffic management is a very important systems design issue, especially in realms of 40 Gbps and beyond. ClearSpeed presented a preliminary design of a programmable chip for multiple traffic man- agement tasks and algorithms at the Network Processor Conference in October 2001. This traffic man- ager can work at either the ingress or the egress path. It can handle congestion avoidance and scheduling as well as run statistics in the background. All these algorithms run in software on the MTAP cores SO simply altering the software may enable proprietary versions of the algorithms to be run. The company has already proven the concept of its architecture by building an actual piece of sil- icon on which it integrated: a single MTAP core containin