ike other solutions that require deterministic latency, the ClearSpeed TLE will produce results of searches as soon as they are avail- able. They can therefore arrive out of order without affecting the order of packet processing, which is designed to be in order for the engine to attain for maximum performance. Multiple tables are han- dled simultaneously, and atomic table updates can be done on-the-fly. The table structure is dictated by software and search keys can be larger than 32 bits. Both CIDR and structured wildcard searches are supported. A series of LEs has access to embedded on-chip RAM (either SRAM or DRAM, depending on which one is available for the semiconductor process) where more critical entries should be stored and potentially off-chip memory, in cases where lookup tables are large. Current implementation of the architecture allows up to 64 LEs inside the TLE. The beauty of this approach is that each LE can provide the answer to the searches it launches whenever it obtains a result, which means that searches are fulfilled potentially out of order. This does not affect the macroscopic packet-processing order. Typically, more LEs will be needed to perform more searches per second or depending on how long each lookup takes. This means that the systems architect will always need to make a trade-off at the system level depending on whether off-chip memory is used and whether this memory is expen- Downloaded from Digital Engineering Library McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SEARCH ENGINES SEARCH ENGINES sive, small-capacity, and power-hungry SRAM or cheaper, high-capacity, and lower-power consum- ing DRAM. The main disadvantage in the external DRAM case is the latency involved, as searches will take more time to be performed by a specific LE. This situation can be resolved by increasing the number of LEs SO the memory subsystem remains saturated and always busy