 from a single ampli- tude/angle output from the baseband SoC. 172 Open Radio Access Network (O-RAN) Systems Architecture and Design Integrated small cell The Integrated Small Cell (ISC, Fig. 4-27) is typically defined as a 2-4 antenna, <6 GHz, <24 dBm/output port or relatively low output power mmWave (<35 dBm EIRP) indoor small cell. We assume the system to deploy an Option 2 or "Option 0" (i.e., full stack in Integrated Small Cell) where Physical Layer and Stack are executing in the ISC context. Optionally, other functional splits (Option 6) are possible. Key components in the ISC include: 1. Layer 2 Stack a. This entails termination of the Ethernet/IPSec based fronthaul interface to the Core Network/Central Unit as well as support for the Layer 2 (MAC/RLC, PDCP/SDAP, RRC) stack b. Includes termination of network-based timing (IEEE1588/Synchronous Ethernet) C. Includes Operation and Maintenance (OAM) and related "slow path" functions. 2. Physical Layer a. Implements the Digital Signal Processing that converts the MAC/Transport Block information into time-domain analog I/Q that can be transmitted by the RF subsystem b. Typically includes Digital Front End (DFE) functions. 3. RF Subsystem a. Implements the analog conversion from baseband IQ to (IF and) RF and the antenna Receive (Rx) and Transmit (Tx) functions. Notes: Even though Fig. 4-27 does not dictate a physical implementation, it closely resembles actual implementations, with key components being a Networking Processor host (hosting the L2 stack), a 5G modem (hosting the Physical Layer), and an RF subsystem. We will discuss these in the upcoming subsections. Some implementations combine the Networking Processor and Modem functions into a single chip. This integrated architecture was popular in 4G/LTE ISCs and some 5G options such as Octasic's"-specifically towards the lower end of the performance spectrum. Integrated Small Cell 10GbE Layer 2 Physical RF Sub- Antenna Stack Cascade Layer System Array (optional) Timing NPU+Modem NPU+Timing FIGURE 4-27 Key com