ng (the net- work) upward, toward the left-hand side of the drawing (where the I-EDS block is), and then upward toward the top center to the output (switch fabric). In an egress flow, data enters the chip from the top of the drawing and proceeds toward the right-hand side of the drawing (where the E-EDS block is) and then downward toward the network interface. The center of the drawing contains the processor complex that acts on the frames while on ingress or egress flows. The various types of storage are also shown macroscopically. We will now look at each of these blocks. The PMM provides interfaces from POS framers and Ethernet physical layer (PHY) chips to the NPU's four flexible external ports. It contains two banks of five DMUs each for the ingress and the egress ports. One pair of DMUs is reserved for internal wraparound communications from egress to ingress inside the NPU. The rest can be configured to support either 10 Fast Ethernet 10/100 Mbps ports per DMU, a 1 Gigabit Ethernet per DMU, 4 OC-3 POS per DMU, 1 OC-12 POS per DMU, or 1 OC-48 per 4 DMUs. Each port contains an Ethernet MAC, which can support 1 full-duplex Gigabit Ethernet link or, with time division multiplexing (TDM), 10 full-duplex Fast Ethernet connections. All RMON groups are supported by special hardware counters in each MAC for remote monitoring in network management. The MAC controllers support 802.3ad link aggregation, 802.1q VLAN detec- tion, flow control, and even jumbo frames. The NP4GS3 through its standard Gigabit Media- Independent Interface (GMII) interface supports Gigabit Ethernet PHY chips that are directly attached. Alternatively, the available SMII interface can be used to support any mix of 10 Fast Ethernet ports running in combinations of 10 and 100 Mbps. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. IBM POWERNP TM 66 NETWORK PROCESSORS External 