ich local computing resources need to be dispatched to execute the instruction based on its "meaning." This is a flexible way of reconfiguring complex tasks such as 8 operations of 32 bits each or 32 operations of 8 bits each, effectively using the maximum of locally available resources while minimizing the access to slower off-chip memory. Figure 9.6 shows the beauty of the scalability that is obtained with the structured and extremely modular architecture that Cognigine has developed. Figure 9.6(a) shows the RSF-in other words, the crosspoint switch module that interconnects four RCUs. In Figure 9.6(b), multiple RSF modules Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES OTHER NPU ARCHITECTURES Instruction Fetch Address Calculate Operand Fetch Execute Write Back Dictionary Fetch Dictionary Decode Instruction Cache Dictionary Instruction Dictionary Instruction Memory, Address Execution Buffers, Calculate Registers Execution Instruction Execution Memory, Definition Execution Buffers, Units Registers Operand Sizes Operand Routing Base Operators Predicates FIGURE 9.5 VISC Architecture pipeline in the Cognigine network processor. (Source: Cognigine) combine with a series of RCUs to show how a much more powerful engine can be created to handle higher loads of traffic. Designers of next-generation products usually have access to a series of options upon which they can capitalize, such as moving the previous silicon design deeper into submicron realms and conse- quently into smaller geometries, thereby taking advantage of the latest spectacular lithography progress. The silicon die savings in such a move can be extraordinary. A company can decide whether it wants to save costs and pass them to its customers with a smaller, faster, and less expensive prod- uct, or whether it prefers to use this advantage as a cushion (both g