eptional reliability levels attained by the Motorola C-5 and C-5e processor packages over a wide temperature range. The C-5e, on which Motorola is pinning lots of hope, is offered in a slightly different 840-pin HiTCE CBGA package, but it consumes only 9 watts as it operates from a 1.2V supply. The Q-5 and M-5 chips are presented in a 600-pin EBGA and a 352-pin TBGA package. They typically consume 4.5 and 2 watts, respectively. NPU ARCHITECTURE Figure 8.1 shows the basic architecture of the C-5e. The network processor combines 17 program- mable reduced instruction set computer (RISC) cores for packet and cell forwarding, along with 32 very long instruction word (VLIW) engines called serial data processors (SDPs) for processing data Q-5 Traffic Queue Storage Management Coprocessor (optional) Physical Line Interfaces: Ring Bus Queue Management Unit 16x10/100 Ethernet 2-4 X Gigabit Ethernet CP Cluster 16 X OC-3c/ STM-1 Buffer Channel Processor 0 SDRAM 4 X OC-12 (c)/ STM-4 Management Frame/Cell 2-4 X FibreChannel Channel Processor 1 Storage N X serial interfaces Channel Processor 2 N X custom interfaces Channel Processor 3 Table Tables Lookup Stats CP Cluster CPs 4-7 Fabric Interfaces: CP Cluster Channel CPs 8-11 Adapter Utopia 2 & 3 (optional) CPs 12-15 Fabric CP RISC and glueless Processor Power X or Merge Space Extract Space IBM PowerPRSTM (All with integrated SONET SAR, link and per- RxSync RxByte RxBIT Interface flow congestion RxSDP (Rx Serial Data Processor) control plus QoS scheduling) TxBIT SONET TxByte External Host TxSDP (TX Serial Data Processor) Executive Processor FIGURE 8.1 The internal architecture of Motorola's C-5e network processor. (Source: Motorola) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. MOTOROLA'S C-PORT™ FAMILY OF NETWORK PROCESSORS MOTOROLA'S C-PORTTM FAMILY OF NETWORK PROCESSORS streams. Several powerful embedde