ide. Several nPcores are used depending on the link speeds that the device is expected to sustain. For instance, the nP7250 designed for the OC-48c realm uses two nPcores inside the die, whereas the nP7510 designed for OC-192c links uses just six nPcores and does not require any major architec- tural changes. Figure 6.2 illustrates the block structure of the OC-192c-capable nP7510. They both provide significant extra headroom for other features or additional computational loads beyond what typical application such as layer 3 switching or routing on multiple gigabit streams provides. In Switch fabric interface Packet Transform Engine Statistics nPcore #n Packet nPcore #2 buffers nPcore #1 Statistics externally Packet coupled Transform Policy specialized Engine Engine coprocessors Multiple PHY interfaces FIGURE 6.1 The block architecture of the AMCC nP family of network processors. (Source: AMCC) Downloaded from Digital Engineering Library @ McGraw-Hil (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. AMCC nPTM FAMILY OF NETWORK PROCESSORS AMCC NPTM FAMILY OF NETWORK PROCESSORS 95 External Search External Memory Host CPU Coprocessor Interface Interface interface Special Metering Policy Engine Engine Memory Access Unit Memory nPcores Packet Transform Engine inP7510-to-nP7510 General Control Debug Port Inter-module JTAG & Test Interface Interface interface interface FIGURE 6.2 The block structure of the OC-192c-capable nP7510 network processor. (Source: AMCC) Figure 6.1, X denotes any generic coprocessors. These coprocessors could be internally integrated on the same die as the network processor or externally coupled. AMCC's network processors include an innovative embedded on-chip engine called the policy engine. This engine is an example of an on-chip coprocessor that supports a single-clock-cycle simul- taneous lookup of layer 2, 3, and 4 packet header components. A software-configurable database sup-