ce and lower switching energies, as well as the absence of a complementary structure, this tends to include several high speed technologies. Protons are known to cause SEEs in Si bipolar devices (ECL), GaAs MESFET and HIGFET devices, GaAs HBT based devices, and other high speed technologies [McMo-96, and references therein]. In general, if the technology has been developed with high speed in mind, then it is likely to be sensitive to proton SEEs, unless SEE hardening has been explicitly incorporated. For a given component, the effect on the circuit and subsystem can be extremely dependent on how the part functions in the circuit, and how follow-on circuit parameters affect error propagation. Investigations have shown that SEE cross sections in high speed technologies can be very dependent on device clock speeds [Mars-95, Reed-96], and even circuit hardening attempts may exhibit a clock speed dependence [Schn-92]. This is understood in terms of reduced noise margins during switching SO that the circuit is more vulnerable to SEEs and that vulnerability occurs more often as the clock speed increases [Reed-96, and references therein]. The combination of inherent SEE softness in high speed logic with the increased sensitivity at high data rates argues for in situ proton testing of high speed circuitry where accurate flight error rate predictions are desired. Such testing is conceptually straight forward, but often challenging to carry out. Complications include the need to provide the DUT with high data rate signals and detect errors "on the fly" without being sensitive to the electrically noisy accelerator environment. The requirement to do this remotely argues for test automation with custom software and hardware. Supporting test hardware must itself be capable of the speeds of the DUT, and should in fact have broadband characteristics with ample bandwidth margin. This often requires the design of test circuits that must be fabricated to operate in the GHz regime. Figure 11 illustrates the test hardware and software