reated to the forwarding and multicast-related instruc- tions. Engines that handle pushing and popping, TTL, and checksums operate on the data, which is deverticalized at the end of the process and sent out to the next stop downstream in the switching sys- tem. We must note that the instruction memory is consulted on a per-flow basis for the next code steps to be executed. The Montego processor also preserves state-related information on a per-flow basis. An interesting by-product of this architecture is that it can scale in both the horizontal and verti- cal dimensions. This translates into an ability to add more engines into a pipe in order to increase a pipe's capabilities and to increase the number of pipes in order to obtain an overall higher perform- ance. With this vertical-processing architecture, because all the associated network features are execut- ing simultaneously and in parallel, it is completely irrelevant (from a performance measurement stand- point) whether an underlying packet requires and obtains the operations that correspond to features X or Y. This means that the performance remains deterministic, and the architecture is one of the pil- lars that help sustain this performance at the wire-speed levels. The other important pillar is the bal- ance of performance from the memory subsystem design. The Montego's core clock runs at 166 MHz. The chip, which is designed in a 0.18u complemen- tary metal oxide semiconductor (CMOS) process, is presented in a 1,600-pin BGA epoxy flip package. To facilitate the parallel development of hardware and software inside a customer's network equip- ment, Bay Microsystems has created an integrated development environment called Internetworking Development System (IDS). IDS provides a cycle/pipeline-accurate C simulation and emulation design environment as well as a complete original equipment manufacturer (OEM) application devel- opment platform that the development engineer can replicate, modify, and/or scale to fit his or her network gear application. IDS is m