ntage of NP-1/NP-1c-based routers is that no extra hardware is required to support such tables, whereas routers based on alternative network-processor technologies will probably need a significant number of extra chips. To make the case more tangible financially, EZchip clarifies that a 10 Gigabit per second interface of an IPv6 router will need a single NP-1c processor and four DRAM chips, which is identical to what happens in an IPv4 router. The bit density of typical DRAM chips is approximately 30 times higher than similar capacity CAMs, whereas the power dissipation of the DRAM chip is roughly 280 times less than that of power-hungry CAMs. Even the cost per bit of a DRAM chip is almost 1,000 times less than the corresponding cost per bit of a CAM. The total cost of the NP-1c solution for this example is estimated at $820 with 17 watt power dis- sipation. With other network processors, however, the same interface would have to be implemented based on the use of two network-processor chips and somewhere between 20 (especially for small routers) and 80 additional CAM and SRAM chips. These combinations total up to cost somewhere between $3,000 and $12,000, with 75 to 300 watts power dissipation. The NP-1c was scheduled to be sampled during the first quarter of 2003. VITESSE IQ TM FAMILY OF NETWORK PROCESSORS Vitesse (www.vitesse.com) has been a major player in the network-processing arena. It has gained even more presence since it acquired a startup called Sitera for its line of high-performance networking chips. The IQ2000 chip was its first important processor. The company now offers multiple NPUs and traffic managers, and it is also uniquely positioned to offer one-stop shopping for its customers. It pro- Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. OTHER NPU ARCHITECTURES OTHER NPU ARCHITECTURES vides essentially all the necessary com