ls. For this setup, the open-loop gain of the associated 4.2 PHASE-LOCKED LOOP ANALYSIS loop filter 2Kvco sin(t) cos(t+) Svco(t+Oop(t)) Figure 4.7: PLL architecture with mixing-type PFD and sinusoidal input and output oscillations. Note that the oscillation frequency is normalized to 2nfo = wo = 1. CT-LTI model equals (4.17) with HLF(s) the loop-filter characteristic. The closed-loop PLL transfer then equals (4.18) As far as the reference waveforms are concerned, it is clear that for a constant (and zero) VCO control voltage Svco(t)=cos(t) (4.19) The VCO's steady-state signal will, however, slightly deviate from this perfect cosine. This is because of small operating-point phase variations. These phase variations are due to the fact that the mixer's (large-signal) steady-state output approximately equals (4.20) Hence, the VCO's control voltage, and therefore the VCO's steady-state output phase, contains higher-order harmonics. It can be shown that, up to first order, (4.21) According to (4.15), the modulated VCO signal can then be described as (4.22) Again, for certain types of PLL architectures, the operating-point phase variation Oop(t) cannot be neglected during further computations. Having dicussed PLL signal modeling in depth, we are ready to construct HTM-based models that capture the time-varying behavior of each of the PLL building blocks. 4.2.4 HTM-based PLL building block models 4.2.4 HTM-based PLL building block models In computing a PLL's overall input-output HTM, we first need to determine the HTMs corresponding to the PLL building blocks shown in Fig. 4.2. The next couple of sec- tions respectively describe PFD, loop filter, VCO and frequency divider small-signal models together with the HTMs that accompany them. Note that in all the examples that follow, the PLL equations are assumed to be normalized such that the input oscil- lation frequency = wo = 14. 4.2.4.1 Phase-frequency detector (PFD) In a first step, we discuss modeling the PFD small-signal behavior. As a reminder, the PFD measures the pha