aximum Payload Size (MPS) according to the standard is 4096 bytes as shown above. For (size/cost) efficiency reasons, SoCs rarely support this MPS. 256B would be a typi- cal implementation choice. Assuming a 30B TLP overhead and a 256B payload, efficiency is reduced to 256/(256 + 30) = 90% of Net Rate in an ideal case. Larger transactions than the MPS are broken down into multiple smaller (MPS or less) sized ones. To provide system level efficiency when multiple devices are connected to a bus, Memory Read Requests can be configured to have a Maximum Read Request size. Note that systems that have a pay- load/packet transfer size smaller than the MPS will see degraded performance given that the various TLP, ACK/NAK, and overheads exist per transaction and hence need to be accounted for independent of the size of the transaction. For every TLP that is sent, an acknowledgment (ACK, or negative acknowledgment, NAK) Data Link Layer Packet is expected back from the receiver. The TLP is kept in transmitter Start Sequence Header Payload 4 Bytes 2 Bytes 12 or 16 Bytes 0-4096 Bytes 4 Bytes 4 Bytes FIGURE 4-30 PCle gen3 transaction layer packets (TLP). Chapter 4 Hardware architecture choices 181 memory until retransmitted and successfully acknowledged. This provides for the reliability of PCIe. Reduction of traffic amount on the link is done by collapsing acknowledgments- send a single acknowledgment for multiple TLPs. To provide for better alignment to natural (for example, 64 bytes) boundaries, the Read Completion Boundary concept allows the data TLPs that return to a read request to divide the payload into chunks that are below the MPS. Example calculation The various overheads and packetization options in PCIe impact the achievable perfor- mance. For example, take a PCIe Gen3.0 X 1 (single lane) system. The transfer rate for Gen3.0 was set to be 8 Gb/s to double the effective bandwidth from Gen2.0 rate of 5 Gb/s. Also, 128B/130B encoding was used (for Gen3) over the 8B/10B (Genl, Gen2) to reduce the loss characteristic f