her end of the emulated circuit. Figure 9-6 shows an illustration of a CEM service with timing based on ACR. It is quite common that this functionality is implemented using a field-pro- grammable gate array (FPGA). Customer CEM packets Customer premises premises Service Service clock clock TDM attachment Ethernet/IP TDM attachment circuit circuit TDM clock recovered Customer Dejitter frequency buffer source Figure 9-6 TDM Circuit Emulation, Timed with Adaptive Clock Recovery The CEM router at the other end of the service starts to receive the packets from the source but does not immediately start to process and forward those packets. The receiver always lags a little behind the transmitter SO that there is always a packet available to process. With a synchronous protocol, there needs to be data available when the TDM frame is ready to be filled, or blank space must be inserted. To guard against this blank space, the receiver builds up a small buffer of packets in case some packets arrive too late. This buffer is called the dejitter buffer. For emulation of E1/T1 circuits, this is normally a few milliseconds of data, and is configurable SO that it can be tuned to the amount of PDV/jitter experienced in the transport network. So, after the dejitter buffer fills up about 50%, the circuitry on the CEM router starts to drain the dejitter buffer (first-in, first-out, obviously). This gives it a few milliseconds of buffer in case of the late arrival of a packet. It reads the first packet in the queue and pushes it into the TDM framer on the AC for transmission to the customer site. Note that there is an equivalent process going on in the opposite direction, as each of these circuits is bidirectional. But the timing can only flow in one dir- ection (left to right in Figure 9-6). Note in Figure 9-6 that the timing flow has subtly changed from Figure 9-5. On the left-hand side, the CEM node is no longer providing clock to the TDM node in the customer premises; rather, it is receiving it. The attachment circuit interface on