lter will be an increasing or decreasing voltage depending on which signal has higher frequency. This voltage adjustment causes the VCO to continuously change its frequency, reducing the differ- ence between VCO and input frequency. Eventually the size of changes in the output voltage of the loop filter are also reduced, resulting in ever smaller changes to the VCO frequency-at some point achieving a "locked" state. Any further change in input or VCO frequency is also tracked by a change in loop filter output, keeping the two frequencies very closely aligned. This process continues as long as an input signal is detected. The filtering process is covered in detail in the following section in this chapter. Recall that the input signal, even one generated from a very stable source (such as an atomic clock), would have accumulated noise (errors) on its journey over the clocking chain. The main purpose of a PLL is to align frequency (and phase) to the long-term average of the input signal and ignore (fil- ter out) short-term changes. Now a couple of questions arise: Will the loop filter react and vary the voltage fed to the VCO for every phase variation seen on the input signal? When should the PLL declare itself in locked state or, conversely, if already in locked state, un- der what conditions could the PLL declare that it has lost its lock with the input reference? The first question raised is answered in the next section, but the second question needs a discussion on PLL states and the regions of operation of a PLL. The PLL is said to be in the transient state when the output is not locked to the input reference and it is in the process of locking to the input signal. Alternatively, the steady state is when the PLL is locked with the input reference. As ex- plained earlier, even during steady-state operations, the VCO will keep adjusting the frequency to match the input frequency based on the differential voltage being fed from the loop filter. These states are governed by three different frequency regions, known 