209/164901.html Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES 174 NETWORK PROCESSORS The basic Xtensa V (already in its fifth generation as of this writing) core is a fully configurable 32-bit RISC core that delivers above 420 MIPS, typically clocked at 350 MHz.² In the worst-case scenario, it is implemented in a 0.13um line-width CMOS technology. It occupies only a small area (~0.3mm²) in silicon real-estate-something extremely important when it is contemplated as part of a larger design. It can be ideally suited for low-power designs (<0.1 mW/MHz) when synthesized on typical 0.13um CMOS technology libraries. The Xtensa processor core is an implementation of a five-stage (or more) pipeline, as shown in Figure 10.5, which shows the involvement of different pieces of CPU hardware at each stage. More specifically, it shows the following: First, an instruction is fetched from the instruction cache. The instruction is then decoded and contents of needed registers are read. The ALU executes operations such as effective address generation and other operations as specified by the instruction opcode. Memory is then accessed for reference or a branch is taken. Results are written back into the register file. The company's processor generator is an intuitive browser-like graphical user interface (GUI) tool that enables the user to enter the configuration details of the processor that he or she designs. We should clarify what we mean by "the generation of customized development tools" and show what an impressive feat this is. When the user has defined custom instructions or extensions (such as special multipliers, cyclic redundancy checks [CRCs], checksums, packet header checks, or DSP-needed blocks such as single or dual MACs) to add on to the licensed core technolog