nsity re- decision threshold. Each time the signal crosses this point, a PLL quirement (also refer to Section 21.4.3). To obtain compliance with can lock its output to it. To perform this task effectively there have the ones density requirement, communications carriers use the to be sufficient crossings over a period of time. If the number of B7ZS technique. crossings is reduced, the PLL can drift from the frequency of the As an example of B7 zero code suppression, consider the DSO incoming signal. This will cause the incoming signal to be sampled time slot illustrated in Figure 21.9. If all 8 the bits are zeros, B7 zero incorrectly and result in data errors. With a ternary code, the logic code suppression will substitute a 1-bit in position 7. The adapted levels encoded into alternate high and low output signals provide time slot is also depicted in Figure 3.9. the clocking information. For example, in AMI coding, each time a Figure 3.10 shows the worst case scenario, where channel 24 is logic 1 is transmitted the receiver can lock the PLL onto the followed by a 0 frame bit, and all bits in channel 1 are zeros, incoming signal. Unfortunately, long series of zeros, which are resulting in a total of 16 consecutive zeros. The illustration shows that in this case B7 zero code suppression reduces the number of impossible to prevent, may deprive the PLL of all synchronisation consecutive zeros to 14. information. To avoid this, a group of several consecutive zeros is replaced by a group containing a factitious 1, signalled as such to As already mentioned in Section 21.4.3, this coding technique followed from the assumption that, in order to guarantee synchroni- the receiver by a polarity in violation of the law of alternation of the sation, at least one eighth, i.e. 12.5%, of the incoming bits were 1s. AMI mode. This principle is systematically applied to all primary However, if a data channel contains all Os, the data will be corrupted and second order digital transmission systems. due to B7 zero code suppression. As