exible packet parsing and key generation, has the impressive performance of 83 Msps. This can be expanded to 300 Msps. On one hand, in terms of its channelization capability, the Montego chip provides support for the seamless mixed multimode operation of 64K virtual channels and up to 4,096 media ports operating across 16 physical channels. On the other hand, in terms of its traffic engineering, it allows hierar- chical scheduling for QoS and CoS. This means that intrinsic support for class- and flow-based queu- ing, VPN-aware traffic isolation with guarantees, a variety of dequeuing algorithms, and even voice grade shaping are available. Policing with DiffServ occurs through the services of a dual leaky bucket (DLB) algorithm implementation, and congestion avoidance is implemented based on Weighted Random Early Detect (WRED), Partial Packet Discard (PPD), and Early Packet Discard (EPD). Both in-band and out-of-band versions of flow control are available. The programmable SAR facilities include ATM Adaptation Layer Level 5 (AAL5) for ATM. Multicast is natively supported for fabric, logical, or spatial modes. In terms of interfacing with a fabric and the rest of the word, Montego supports industry standard CSIX- and SPI-4-compliant inter- faces. A 32-bit RISC central processing unit (CPU) running at 166 MHz assumes the executive super- visory role inside the Montego system and is capable of handling statistics up to 1 million counts per second. With its native support for packets, cells, and frames and its seamless internetworking capabili- ties, the InP family is ideally suited to scale from requirements imposed on equipment designed for access networks all the way to carrier-class network gear designed and destined for deployment in long-haul carrier networks. As a result, the company targets its products toward designers of network equipment such as access concentrators for voice circuits, wireless base stations, xDSL gateways, multiservice switches and routers, cable head ends, and intelligent optical transpor