ber of traces that can be integrated into a board is intrinsically limited by the reliability and the cost of the board creation process. For all these reasons it is not practical to implement a backplane that has to transmit sev- eral signals at 10 Gbit/s using a huge number of parallel low-speed lines. In order to implement a high-speed serial bus there are two possible technologies: elec- trical high-speed busses and optical busses. Telecommunication Networks 7.5.1.1 High-Speed Electrical Backplanes The target of a high-speed serial electrical backplane is to provide electrical busses on the backplane that are able to transmit at least at 10 Gbit/s [34]. This has to be done in a transmission line that can be represented as in Figure 7.26: the transmitter is located on one card, the receiver on another card, and the line is divided between the two connected cards and the backplane, with connectors to join the pieces. Also, a more complex backplane architecture has been proposed, where the switch fabric is embedded at least in part into the backplane, SO that the overall system architecture is simplified [35]. We will not describe this option here, but with the evolution of nanoscale integrated optics on C-MOS platform it could become a quite interesting alternative. Returning to a backplane allowing pure connectivity among cards, the first choice to be made is the selection of the transmission format. Due to a plethora of reasons, unifor- mity with other transmitter/receivers applications, simplicity and SO on, nonreturn to zero (NRZ) is generally chosen as the preferred modulation format. Once the modulation format is chosen, all the components that are reported in the scheme of Figure 7.26 have to be chosen SO to satisfy both the required performance crite- ria and the rigid cost requirements that a backplane has to fulfill. 7.5.1.1.1 Transmitter The transmitter has to be capable to compensate jitter and dispersion introduced by the channel at such a high speed by introducing preemphasis in the transmitted pu