data at high speeds on fewer data lines without the matched timing board complexities of many high-speed LVDS lanes. Since the data sent over JESD204B/C is framed, based on an embedded clock and con- trol characters, the routing of the lower count serial lanes is much more tolerant of timing skew than LVDS. This eliminates the need to adjust output timing on every I/O of the system Low-voltage differential signaling (LVDS) is a high-speed digital interface that has become the solution for many applications that demand low-power consumption and high noise immunity for high data rates. Since its standardization under ANSI/TIA/EIA-644, LVDS has been implemented in a diverse set of applications and industries. The LVDS standard provides guidelines that define the electrical characteristics for the driver output and receiver input of an LVDS interface but does not define a specific communication protocol, required process technology, media, or voltage supply. The general, non-application-specific nature of the standard has been conducive to the adoption of LVDS across a wide variety of commercial and military applications. A standardized serial interface between data converters (ADCs and DACs) and logic devices (FPGAs or ASICs). JESD204B supports serial data rates up to 12.5 Gbps, a mechanism to achieve deterministic latency across the serial link, and uses 8B/10B encoding for SerDes synchronization, clock recovery, and DC bal- ance. In Revision A, the main goal was to support both single and multiple lanes per convertor device. In Revision B, the added features were programmable deterministic latency, usage of device clock as main clock source, and data rate up to 12.5 Gbps. In the latest Revision C, the data rate is increased up to 32 Gbps, and three link layers have been introduced as 64B/66B, 64B/80B, and 8B/10B where 8B/10B link layer is same as JESD204B link layer. JESD204C defines layer-wise relationship with the IEEE Ethernet model. 708 Chapter 5 board. Additionally, JESD204B offers informational control-bits 