rall buffering usage can be achieved, and as it is shared between inputs and outputs, it is cost effective. Scheduling in the PowerPRS family is completely distributed and it is one of the keys for attaining high performance with IBM switch fabrics. Traditional crossbar, memoryless switches implement a centralized sophis- ticated scheduler that supervises the input and output queues by applying an overloaded and usually complicated algorithm. This type of scheduler needs to collect a lot of information from all input adapters to reconfigure the crossbar during every single packet cycle. In addition, in multicast cases, traditional crossbars will create multiple copies of the packet to forward to output queues. With PowerPRS, the switch fabric output port queues keep pointers to the one and only copy of a packet in memory (in fact as many pointers as needed especially in the case of multicast). Based on their load, output queues decide on their own whether and when a packet residing in memory will be sent out from their port. Obviously, a packet is not erased from memory until all the pertinent queues have been served. Conversely, all input queues can decide on their own without any higher-logic intervention whether an incoming packet can be allowed to be read into the fabric's memory, unless backpressure signals from the switch fabric core have signaled to all input line cards that they must refrain from doing SO. The Q64G has room to internally store up to 4,000 packets entering the switch fabric through thirty- two 16 Gbps input ports. That is a rate of 1 packet every 32 nanoseconds potentially on each port. As packet fetching may be happening simultaneously at any (maybe all) of the 32 output ports, up to one memory operation (read or write) must be able to be performed within half a nanosecond if a full traf- fic load is to be sustained on every input and output port. This has led to the implementation of a four-port spatial/time shared memory implementation, as shown in Figure 14.12. Two independent read and