ort spent and performance gained. Lucky enough, through manufacturer efforts, there are software libraries available not only for generic SIMD tasks but specifically for O-RAN and 4G/5G pro- cessing, as provided by Arm, Intel, and others. It is important to keep in mind that when it comes to SIMD processing, "bigger is not always better." In these applications, the processor is not busy with "number crunching" all 176 Open Radio Access Network (O-RAN) Systems Architecture and Design of the time-the amount of CPU clock cycles spent doing Signal Processing work is limited due to memory artifacts (the CPU waiting for data to make it into its local L1 cache) and "control" code that simply isn't vectorizable. This explains the diminishing returns associated with very wide vector width CPU implementations: I can theoretically double the execution speed of my DSP algorithm, but if the CPU is only spending twenty percent of its time doing DSP processing, the overall gains are only ten percent. Increased vector widths come at a cost of CPU frequency: Intel CPUs reduce the turbo boost frequency of their cores when the instruction pipeline is heavy in wide-vector SIMD processing. Looking at O-RAN ecosystems, we find that x86-or more specifically, Intel-is an obvious candidate, given the implied (but as we noted, not explicit) software-defined, COTS nature of O-RAN products. An x86 based reference design named FlexRAN13 13 includes a reference implementation of a 4G/5G Physical layer, which is an obvious starting point for system design. SIMD support is present in all x86 processors since the introduction of MMX (64b)/SSE (128b) by Intel, and 3DNow! by AMD in the late 90s. SSE evolved into SSE-2, SSE-3 and SSE- 4 in the 2000s, increasing the supported instruction count and introducing more data types (e.g., double precision Floating Point). Intel Sandy Bridge and AMD Bulldozer family of processors supported 256b Advanced Vector Extensions (AVX) providing additional vector with an even richer instruction set. AVX evolved into