ern for other ICs as the gate oxide is thinned. Recent data show that thinner oxides have higher critical fields to rupture, but on the other hand, devices are being run at higher fields these days. In the end the susceptibility of commercial ICs to SEGR in space environments will depend on what scaling rules the manufacturers choose for terrestrial operation. SEB remains a concern primarily for power devices, and must be considered for proper system design. II-66 Simulations of SEE have been crucial to developing an understanding of the mechanisms behind SEE and for suggesting methods for hardening devices. As devices continue to evolve to smaller dimensions, device-level modeling will encounter new challenges such as the ion strike affecting more than a single transistor at a time. A greater level of usefulness can be reached when simulation tools prove to be validated and predictive. At this level, simulations become essential during the design process for reducing the number of "fab-and-test" cycles that must be completed to develop radiation-hardened technologies. Technology trends are unfortunately such that SEE are likely to become even more of a concern for the future. Decreasing feature sizes, lower operating voltage, and higher speeds all conspire to increase susceptibility to SEU. Upset in avionics is an established concern. Upset at the ground level will continue to be an increasing concern for manufacturers of microelectronics for terrestrial applications. The use of flip-chip packaging and multiple levels of metals will only serve to further exacerbate the problem. Typical methods of mitigation that either increase the transistor count or reduce IC performance will likely not be acceptable to commercial manufacturers, and new methods will need to be developed. Silicon-on-insulator (SOI) technology may help in this regard, but is not a magic bullet to end all SEE concerns. Hopefully, the fact that commercial manufacturers must deal with SEE concerns will provide a collateral benefit to the radiation 