r-intensive functions from the processing chain and implementing them in an FPGA or dedicated ASIC/accelerator. Forward Error Correction (FEC) Low Density Parallel Codes (LDPC) decoding is an obvious candidate in 5G/NR. Although the concept of offloading is counter-intuitive for a so-called software-centric solution, performance requirements dictate some form of offload for all but the lowest-end solutions. Some of the limitations of the standard White Box server architecture are being addressed by evolving standards. Consider the Open Telecom IT Infrastructure (OTII) white-box server project from the Chinese Open Datacenter group. 2 This white box design is driven by China Mobile, China Telecom, China Unicom, China Academy of Information and Communications Technology (CAICT), and Intel. The OTII server is optimized for 5G and Edge Computing both in form factor (physical and environmental) and IO (PCIe connectivity designed for fronthaul IO and Physical layer accelerator). Early versions of the standard call out the need for time/frequency synchronization without specifics on whether this is imple- mented as a feature on the main board or through a PCIe plugin board. Some of the offload functions obviously can be combined into one, with an accelerator board like shown here in Fig. 4-9: Note that this type of accelerator model requires multiple transfers of payload between server and offload engine. The associated bandwidth can become a bottleneck as we will see later. An alternative accelerator split is shown in Fig. 4-10: The advantage of this architecture is that the PCIe bandwidth is constrained (there is only a single path to/from the accelerator). In this example, the fronthaul I/O (eCPRI and framing) can reside either in the host processor or in the accelerator card. The latter option is of course most performance optimized and likely to be implemented. 150 Open Radio Access Network (O-RAN) Systems Architecture and Design Software/Server DL From MAC UL To MAC CRC Attachment Code Block Concatenation De-Scram