proprietary link is a serdes serial link that IBM introduced for the latest and future announcements in the PowerPRS family. The 64G switch fabric can be directly connected to the NP4GS3 network processor through the latter's DASL interfaces over an IBM proprietary DASL backplane. The SCIC also allows an NEV to use a queue manager from IBM. The C192 is the first chip that IBM has introduced in this function. The aggregate full-duplex throughput of the Q64G, which supports direct HSS interfaces (ex-Unilink), is 64 Gbps. For higher bandwidth needs, multiple devices can be cascaded in master- slave configurations. A cell is then sliced and distributed across multiple HSS interfaces to the different switch fabric chips. Each subfabric switch operates on a slice of the original cell. The mas- ter is responsible for all scheduling, synchronization and sequencing of operations, and control of entire process. The slave switches just provide the rest of the necessary data path. Figure 14.17 pro- vides a sample configuration for 256 Gbps aggregate throughput. Slave Device Memory Control Addresses Port 0 0 Slave Device Port 0 Memory (16 Gbps) (16 Gbps) Control Addresses 16 inputs (256-Gbps Slave Device 16 inputs aggregate (256-Gbps Memory throughput) aggregate Control throughput) Port 15 Addresses (16 Gbps) 0 Master Device Port 15 (16 Gbps) Memory Control FIGURE 14.17 An aggregate 256 Gbps throughput configuration using multiple PowerPRS-Q64G switch fabric chips arranged in a master-slave scheme. (Source: IBM) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SWITCH FABRICS NETWORK PROCESSORS The Q64G is housed in a 624-ball IBM ball grid array (HyperBGATM) package. Its maximum power consumption is 19 watts (when configured as master in a multiple-chip configuration). The slaves consume about 20 percent less. An older 64G fabric chip just like the NP4GS3