Many of today's intelligent carrier, service provider, and customer premises equipment (CPE) plat- forms require a feature-rich 10 Gbps traffic management context for the provision of subscriber band- width, the flexible scheduling of capabilities, and the exercise of rigorous admission control. The nPX5700 per-flow queuing mechanism offers very high levels of granularity and supports tens of thousands of subscribers and hundreds of thousands of queues. More specifically, the nPX5710 con- trol logic chip can easily support up to OC-192 bandwidth scheduling in fine-grain 256 subports, 64,000 virtual pipes (aggregates), and 256,000 input flows. Similarly, the nPX5720 memory man- agement device, which can support up to four OC-48 channels or one OC-192 channel, has its own embedded dynamic random access memory (DRAM). Therefore, it can provide local storage for up to 8 million cells of payload storage. NEVs who are designing network equipment can use the chipset to implement a variety of sophis- ticated admission control techniques. These techniques include dynamic marking and discard thresh- old levels, Random Early Detection (RED), Weighted RED (WRED), Early Packet Discard (EPD), and Partial Packet Timeout to manage and control potential congestion and enforce programmed serv- ice levels. Maximum flexibility is also preserved in the sense that the systems designer is free to imple- ment policy-based QoS features that support strict priority, WFQ, round robin (RR), WRR, constant bit rate (CBR), variable bit rate (VBR), and minimum and maximum bandwidth control among sev- eral intrinsically supported and available possibilities. SWITCH FABRIC The switch fabric function further augments the model based on which the designer must physically separate the network-processor chip from the traffic managers and then both of these functions from the switch fabric chipset. The switch fabric does this by maintaining local logical queues that are built upon the concept of classes and are further sorted per output port. Figure 6