ge of the circuit. These types of errors are likely to become a pervasive problem as clock speeds continue to increase, and will be difficult to protect against, especially in commercial microprocessors where speed is paramount. It has been suggested that for circuits built in technologies below 0.35 um, propagated SETs will be a VDD (V) Oxide Thickness (Angstroms) Figure 6.2. Simulated scaling trends for SEU threshold LET as a function of a) power supply voltage, and b) gate oxide thickness. II-57 Experimental Range Feature Size (um) Figure 6.3. Overall SEU threshold LET technology trend for the last three generations of Sandia CMOS SRAMs without feedback resistors [70]. The points are the results of 3D mixed-level simulations, and the shaded regions are the measured range. primary single-event failure mode [306]. The interested reader is directed to the final segment of this short course for more information on SETs in digital logic circuits and mitigation strategies [171]. For SEL, the trends from technology evolution are more difficult to predict. Technology trends working to increase SEL susceptibility are decreased well thicknesses and interdevice spacing. On the other hand, the decreased power supply voltages demanded in newer low-power technologies may alleviate latchup concerns, while technologies such as trench isolation also tend to improve latchup resistance. If CMOS/SOI technology proves to be manufacturable and becomes a mainstream technology solution, traditional latchup concerns may vanish. Hardening Strategies A considerable concern for SRAMs requiring SEU hardness in the future is whether traditional resistive hardening techniques will remain a viable option. The resistive decoupling technique is fundamentally incompatible with high speed because it relies on slowing the cell down SO that it cannot respond quickly to SEU voltage transients. This tends to mean that the write performance of hardened SRAM cells has to be kept at a nearly constant level to maintain a constant level of SEU hardness. 