its direct link to noise. A measurement fication. From a mathematical point of view the number that is better still is that of NSD for the converter. of bits the converter contains limits performance physi- cally. An ideal converter will exhibit an SNR that is de- NSD provides the amount of noise energy in a 1 Hz bandwidth for a converter. This number is not termined by this equation: usually specified in the data sheet because it is de- pendent on the actual sample rate used and the input SNR = 6.02N + 1.8 (2.3.6) termination condition. To determine the NSD of In reality, there are many other issues that determine a data converter, the performance of the converter, including clock jitter and thermal noise. Equation (2.3.6) provides the noise due to ideal quantization and does not take into account NSD = PADC_Fullscale - SNRADC_Fullscale any of the other sources of noise in a converter. A mod- - 10 log ( Sample_Rate (2.3.8) ification of this equation provides a more insightful measure of converter performance. Equation (2.3.7) for modified converter SNR takes into account clock Once the NSD has been determined, it can be used jitter, thermal noise, and the effects of non-ideal quan- either to confirm if the converter meets the noise tization, which are the major limitations in converter floor requirements or to determine the minimum gain performance. required from the front end of the transceiver design. As an example, an ADC is selected with an SNR of 70 dB at the selected input frequency. With the SNR = -20 Fanalogtims) + required input termination, a fullscale of +4dBm is achieved. The configuration requires a sample rate of 61.44 MSPS. Using Equation (2.3.8), the NSD is (2.3.7) -140.9 dBm/Hz. As outlined above, if it is desirable that the converter Although this equation is a little more complicated, it noise not limit the performance of the transceiver, then does take into account many of the important factors in the front-end noise needs to be approximately 10 dB converter performance. In Equation (2.3.7), 