silicon, allowing charge induced conducting paths between sources or drain of transistors (adjacent transistor most of the time) or wells of appropriate type of doping [Adam-76]. Also The inversion is caused by charges trapped in the thick field oxide. As trapped charges are mostly positive when it concerns thermal silicon oxide, the surface of the silicon enriches always in electrons, SO that leakage is established between NMOS transistors or NPN bipolar. The parasitic structure can be considered as a field effect transistor with a "virtual gate" and a threshold voltage can be defined by analogy with real transistors. Leakage currents in trenches belong also to this category, connecting surfaces via the bottom of the trench [Raym- 92], regardless of CMOS or bipolar technologies, regardless the trench is filled by polysilicon of an insulator. The situation is worsened when a interconnect line exists above this leakage path, because it acts a real gate possibly biased at positive voltage and then can increase the leakage current. These effects are measurable by designing "Field-Oxide" transistors with a dedicated control gate or FOXFET [Dawe-77], [Oldh-87]. III-94 THE CASE OF LEAKAGE IN BIPOLAR TECHNOLOGIES Furthermore, in bipolar integrated technologies, parasitic "Field Oxide" transistors can exist, and create leakage between adjacent collectors of NPN transistor as for source or drains or wells of MOS technologies. For example, TTL input protection arrays support a recessed Field Oxide which is a source of leakage in the range of 10 kilorad(SiO2) These problems have been analyzed in detail ([Peas-85] and more recent works of the same team, and [Pers-92]). Solutions reside there again in the "channel stops" or "hardened field oxides". Another radical solution resides in the lateral dielectric insulation, the modern version of which uses trenches [Enlo-89, Raym-92]. However, this author shows it can again exist a parasitic transistor located in the bottom of the trench, that can be avoided by using a bottom isola