nsion (TIE) instruction (using Tensilica's architectural extension definition language) can perform the equivalent of several instructions. One concludes that a single Xtensa TIE instruction produces work at a higher per- formance level than a single instruction in a standard 32-bit fixed RISC processor. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES ALTERNATIVE APPROACHES TO NETWORK PROCESSING: NET ASICS AND DESIGNING WITH IP CORES 175 Processor Configuration inputs Designer-defined instructions Processor generator Xtensa processor generator outputs Processor optimization Hardware System Modeling/Design SW tools Application Methodology Support Source Code GNU SW toolkit XTMP: scripts Instruction (compiler, System assembler, Simulation simulator linker, debugger, Compile profiler) Bus Functional Xtensa C/C++ Synthesis Model Compiler Executable (XCC) Block XT2000 Place & Emulation kit C-software Profile Route libraries Using ISS Verification verification OS-kit Operating Develop new tools System Extensions or overlay Choose new integration configuration Software development FIGURE 10.4 Parallel rapid development of hardware and software using the Tensilica approach of configurable processor cores. (Source: Tensilica) also impact the possibilities of large-scale SOC integration for natively parallel applications that are based on multiple copies of the same configuration of the Xtensa processor, as each processor can be now uniquely identified while it communicates with other fellow processors. The company has also implemented designer-defined conditional load and store instructions. This has significant value in deep packet classification tasks, which are SO often executed in network pro- cessing. When carefully used, it can result in programming that contain