 NPU or a fast specialized network ASIC. Data plane processor could also even refer to a reduced instruction set computer (RISC) or a complex instruction set computer (CISC) CPU, but this is less common. It is worth mentioning that some vendors logically split the control plane into two adjacent and complementary computational slices, which they dub the control and management plane, respectively. This is more of a cosmetic implementation-dependent characterization, which simply delineates the host CPU (usually a processor based on the PCI bus) that oversees the macroscopic management of the line card or system from another control plane processor, which may be handling much narrower day-to-day control responsibilities. We will not make this hypergranular distinction in this book and will continue using the predom- inant model of thinking in terms of two planes. It is also worth mentioning that NPUs may integrate in Ethernet MACs, but they rarely integrate in Ethernet PHYs. In addition to the complications of the mixed signal design (containing analog and digital inside the same silicon die) and the additional power dissipation, the pins used for SMII and GMII interfaces are electrically compatible with SPI-3/Universal Test and Operations PHY Interface for ATM Level 3 (UTOPIA 3). Therefore, no additional package pins are required when only MACs are integrated in. I/O pins are often a scarce resource for massively packaged NPU chips. PACKET-PROCESSING OPERATIONS So far we have used several generic terms to describe handling operations applied by the high-speed router/switch onto packets. We will now take a closer look at these operations: Packet Framing In the Ethernet environment, the MAC and PHY layers implemented in the transceiver are sometimes implemented in different chips. In high-speed links, however, such as SONET where either ATM or Packet over SONET (POS) is being transmitted, a separate framing unit is used to map the ATM cells or Point-to-Point Protocol (PPP) packets into the SONET frames for transmiss