e header payload divider is presented in Figure 10.51. The core of the subsystem is constituted by a monolithic InP chip with two SOAs on the branches of a four input MZI. At the output, two tunable filters are used to insulate the payload and the header on the two interferometers output ports. The packet is injected into the second MZI input while into the first input is injected a control signal as long as the packet header and as strong as needed to switch off the inter- ferometer at its end. The control signal on the last input is a pulse quite strong that is useful to force a carrier change into the SOA SO to arrive at a switching time smaller than the single SOA. Naturally, the MZI structure also works as a frequency converter; thus, the header and the payload can be recovered separately with tunable filters at the output. The block scheme of the all-optical deserializer that has to divide the header (in our case two bits) in parallel streams is shown in Figure 10.52. In line with the principle, it could be possible to replicate, at a different time scale, the circuit that divides the header from the payload. In this case, however, there are two bits to be deserialized and it would be difficult to introduce the pulse that in this case should elapse earlier than the bit time. The adopted scheme is based on XGM in SOAs, exploiting the fact that SOAs that have to work as a single gate can be fabricated with a set of characteristics suitable to shorten the response time. Telecommunication Networks Control 1 InP monolithic chip Payload Packet Header Control 2 Optical power Packet Header Payload Control 1 Control 2 FIGURE 10.51 Block scheme of a possible header payload divider. Control 1 InP monolithic chip First header bit Header (2 bits) First header bit Control 2 Optical power Header Control 1 Control 2 FIGURE 10.52 The block scheme of a possible all-optical deserializer that has to divide the header (in our case two bits) into parallel streams. Thus, the scheme of the deserializer is again constituted by an i