y leakage currents in the system. Figure 5.38 shows a schematic cross section of a typical advanced CMOS device with low-doped drain contacts implanted through Si3N4 spacers on either side of the gate to reduce the electric field between source and drain. All gates and ohmic contacts are treated with TiSi, CoSi, or NiSi to reduce the resis- tances of gates and contacts. The value chain of microelectronics is one of the most complex from wafer vendors to fabrication machine suppliers to foundries and chip producers. Such a great number of players have to be coordinated to hit common goals and allow an ordinate development of the technology. This is the role of the International Technology Technology for Telecommunications: Integrated Optics and Microelectronics n+ poly Si3N4 p+ poly Substrate FIGURE 5.38 Section of an advanced CMOS system. Roadmap for Semiconductors (ITRS), an industry road mapping group coordinating the efforts of the players in the microelectronics industry. In order to fix clear targets for the major technology advancement, the ITRS has defined the concept of technology node, the moment at which the entire cycle that is needed to intro- duce a significant technology improvement through research, experimentation, devel- opment, and start of production starts to have an impact on products presented on the market. Over the last 15 years, there has been a new CMOS technology node approximately every 2 years. The key feature of every node has been a doubling of the density of chips on the wafer and an increase of ~35% in switching speed and power consumption. This improvement history is summarized in Figure 5.39 where the sequence of the dif- ferent technology nodes is shown representing the decrease of the CMOS transistor gate length with time [47,48]. Different reasons have pushed the decrease of the dimensions of the CMOS, all oriented toward the improvement of CMOS circuit performances. IC typical feature size 10 um Technology nodes 130 nm 90 nm 65 nm 100 um 45 nm 32 nm Gate length 10 um Calenda