ffic queues. This is why the scheme is called active queue management. To further complete the AQM picture of the traffic management capabilities within the Q-5 TMC, it is worthwhile to note that Random Early Detection (RED) and Weighted RED (WRED) AQM schemes are supported and are mapped onto the chip's shared hierarchical buffer model. All packet/cell-discard models are parameterized and configurable, and all PDUs are either tagged or discarded based on the corresponding congestion schemes, which the user may have chosen to con- figure in the Q-5 TMC. For the sake of illustration, we will discuss an example of how the implementation of a typical QoS solution flows through a system that is based on the Q-5 TMC. The example is illustrated in Figure 8.2, which shows the implementation of a real-life high-performance routing system. In this design example, as soon as packets/cells enter the system, which is composed of the C-5e network processor and the Q-5 TMC, the ingress processor sends the actual data over the internal pay- 2. Srinivasan Keshav, An Engineering Approach to Computer Networking: ATM Networks and the Telephone Network (Reading, Massachusetts: Addison-Wesley, 1997). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. MOTOROLA'S C-PORT™ FAMILY OF NETWORK PROCESSORS MOTOROLA'S C-PORTTM FAMILY OF NETWORK PROCESSORS load bus to the BMU for temporary storage and it does SO after parsing and classifying the incoming bitstream. The ingress processor can be one or more of the 16 CPs (depending on the application and the point in time when the system functionality is looked at), the XP, or even the FP. Simultaneously, the internal processors of the C-5e network processor (one of the CPs, the XP, or even the FP) create an application-specific control packet called a descriptor, which is then enqueued into the Q-5 TMC through the auspices of 