o, they restrict the points in time for which they computate the PLL signal values to the sampling instances. These DT-LTI methods es- sentially amount to a lifting technique [Bam92]. They reveal constraints on the design of a PLL's open-loop characteristic that cannot be derived using a CT-LTI approxima- tion. However, discrete-time (z-domain) models [Gard80, Hein88] do not fully recognize the mixed continuous-time/discrete-time nature of a PLL. Moreover, these methods are not very well suited as a framework for symbolic computations, at least not for arbitrary loop characteristics. This limits their help in gaining understanding and in making decisions on design parameters. Finally, this discrete-time approach does not allow a unified treatment of PLL behavior that, amongst others, easily encompasses all possible PFD implementations. 4.2.2.3 Numerical simulation of PLLs When the previous (CT-LTI and DT-LTI) approximations fail, it is of course always possible to analyze a PLL's behavior by means of numerical simulation. This can either be done using a general-purpose simulation algorithm (SPICE or a VHDL-AMS simulator) or using dedicated methods [Perr02]. Note that use of dedicated algorithms can help us to reduce simulation times from hours to minutes. The advantage of numerical simulations lies in the inherent accuracy of the results. By construction, simulations capture time-varying behavior and even nonlinear effects3. The disadvantage is that numerical simulations require (sensible) numerical values for all design parameters. Somehow, a designer must come up with these values in ad- vance. Hence, numerical simulation algorithms are mainly useful in a verification stage or when finetuning a design. However, for the initial stages of a design process, one (also) desires methods that allow us to express input-output relations in a symbolic manner. 4.2.2.4 Contributions of this work This work presents a method for constructing s-domain small-signal PLL models that capture the time-varying aspects of a PLL's be