ing an Network Processing Forum (NPF)-like streaming interface based on System Packet Interface 4.2 (SPI-4.2). Agere also provides a system reference design with full software support that can be extremely useful for network equipment vendors (NEVs) trying to minimize their time to market. A connection with the framer is also made via an industry standard SPI-4 Phase 2 frame interface. Port-based rate shaping is programmable for up to 256 media ports and various configurations are supported, such as one OC-192c, four OC-48c, mixtures of 1 Gbps or one Gigabit Ethernet, 192 DS-3 links, and SO on. The chipset is accessible by a supervising host CPU over a PCI-2.2-compliant, 66 MHz, 32- or 64-bit bus. THE APP550 (EX-INP5) NETWORK PROCESSOR As mentioned in the beginning of this chapter, at the end of July 2002, Agere announced the APP550 (originally introduced in the market as INP5). APP550 is an integrated network processor that further optimizes the position of the product family for the OC-48 realm. It has also been designed to mini- mize the chip count (an issue that was perceived as the Achilles heel of the architecture previously offered by the company) and offer significantly decreased power consumption and a reduced overall systems cost. A comparison of a typical OC-48 solution based on the company's previous three chips and the APP550 single-chip solution, along with associated memory as well as PHY and fabric interface chips in both cases, shows some impressive results. More specifically, the APP550-based system costs less than half the cost of the three-chip solution. It takes only about 60 percent of the printed-board space needed for the three-chip solution and consumes 19 watts (including all of the associated memories) as opposed to 43 watts for the three-chip implementation. The company introduced the first APP550 chip samples by the end of 2002. Figure 7.8 shows how the APP550 fits between the PHY/framer and the switch fabric. A full-func- tion classifier, a policing engine, and a traffic manager are 