s are observed in an otherwise spectrally pure FFT, this reduces the available spurious free dynamic range (SFDR) of the carrier signal relative to other noise. To improve the SFDR of GSPS ADCs, new architectures and algorithms are now emerging beyond the use of inter- leaved cores. This removes the burden for system engineers to have dedicated ADC postprocessing routines that must identify and remove unwanted interleaving spurs (see Fig. 5.19). The SFDR is defined as the ratio of the rms value of the signal to the rms value of the worst spurious signal regardless of where it falls in the frequency spectrum. The worst spur may or may not be a harmonic of the original signal. SFDR is an important specification in com- munications systems because it represents the smallest value of signal that can be distin- guished from a large interfering signal (blocker). The SFDR can be specified with respect to full-scale (dBFS) or with respect to the actual signal amplitude (dBc). The definition of SFDR is shown graphically in Fig. 5.19. In other words, SFDR is the ratio of the rms value of the signal to the rms value of the peak spurious spectral component for the analog input that produces the worst result. New Radio Access RF and Transceiver Design Considerations Full-scale signal (FS) Input signal level (carrier) SFDR (dBFS) SFDR (dBc) Maximum spurious signal level f / 2 Frequency Figure 5.19 Illustration of SFDR concept. Multi-GSPS converters with 10, 12, or 14-bit resolution generate multiple output data lanes. The use of low-voltage differential signaling (LVDS)¹ 10 data could require 30 parallel lanes of 1-Gbps data for a 2.5 GSPS, 12-bit ADC, in which managing 30 differential LVDS pairs per ADC can be very challenging in terms of routing and maintaining matched lengths on a sys- tem layout. Equivalent data can be sent with only six or eight differential lanes using JESD204B/C, a high-speed serializer/de-serializer (SERDES) standard designed specifically for converter interfaces. JESD204B/C provides a means to output 