ets in a pipeline fashion. The synchronous static random access mem- ory (SSRAM) interface is 64 bits wide and runs up to 104 MHz. It can be configured to support exter- nally connected coprocessors such as classification chips from other vendors. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. AMCC nPTM FAMILY OF NETWORK PROCESSORS NETWORK PROCESSORS Switch Fabric nPX5800 nPX5800 Redundant Switch Fabric S2512 S2512 ViXTM v.3 bus serdes S2512 S2512 serdes nXP5710 nXP5720 nP7250 nXP5720 nXP5710 Network Ingress Path Processor Traffic Management Egress Path Traffic Management PHY & framer OC-48, OC-192, 10 GbE Line card FIGURE 6.6 A typical systems configuration with the nPX5800 switch fabric and the nPX5700 traffic management chipset. (Source: AMCC) AMCC documentation says that the nPX8005 family must be used to operate a switch fabric at a combined throughput above 160 to 320 Gbps. If we look at an example in a 16X10 Gbps switch fab- ric, then 5 chips need to be used for the switch fabric function, one in master, 4 chips need to be used in slave mode, and 48 chips need to be used for the queue management function. In addition, 16 serdes must be used for the switch interface and 16 FPGAs must be used for the line interface. Without count- ing memory, such a system requires a minimum of 85 chips if it is implemented with current AMCC technology. It will consume above 300 watts. FIFTH-GENERATION TECHNOLOGY We will conclude this chapter by adding a few comments on the company's fifth-generation technol- ogy, which AMCC introduced in late 2002 under the name nP5TM_ In addition to pursuing highly integrated products that efficiently offer headroom and flexibility customers who need to come up with economic complete design solutions, AMCC is now offering the possibility of designing products that can handle multiple protocols and services at a lower