,240 is needed. A key parameter of the switch matrix of an OXC is the power consumption, while the switching speed is not SO important since the optical layer would operate in a circuit switching mode also under the ASON/GMPLS control plane. This means that optical con- nections are established for a long time and fast switching is not a requirement. This natu- rally assumes that protection is implemented with separate switches. At the 22 nm technology node is reasonable to assume that the single chip consumes about 1 pJ/bit/s per switch crosspoint. Telecommunication Networks Considering an architecture with deserializers and 10 DWDM at the input, each of which carry 100 channels, we have 1000 channels at 10 Gbit/s; that is, we need a 10,000 x 10,000 Clos switch fabric with lines at 1 Gbit/s. This is exactly the example of Figure 7.34, where there are 1.4 million crosspoints and 40,000 connections between different chips, taking into account that the fan in and the fan out of a chip also are constituted by transistors and consume power. If we refer to an energy per transit bit of 1 pJ/bit/s, we have a global power consump- tion of 140 kW for the crosspoints and 40W for the chip connections. Adding the possible power consumption of the processor implementing the manager and the arbiter, we have an overall power consumption of about 1.8kW. It is very interesting to verify if power consumption due to parasitic currents can be neglected. The amount of parasitic power consumption depends on the structure of the crosspoint that can be a simple transistor with its driver polarization circuit or a more complex subsystem. As an example, we will assume that the crosspoint is realized using two flip-flops, each of which drives a single transistor used as physical switch. The microscopic analysis of this structure arrives at a conclusion that for 22 um it can be assumed a leakage power of 45 uW. Assuming a simple connection structure built with three transistors, each connection has a leakage power of 20 uW. This means that 