sev- modulation, the FPGA will provide timing and control as eral finite impulse response (FIR) filters, designed to well as any special-purpose hardware accelerators that introduce no phase distortion over the exact signal are particularly unique to the waveform. It appears that bandwidth. If necessary, the signal is despread, and then SDR architectures will continue to evolve as component refiltered to the information bandwidth, typically with manufacturers bring forward new components that shift an FIR filter. the boundaries of lowest cost, highest performance, and least power dissipation. Analog-to-digital converters The rate of technology improvement versus time has not Forward error correction been as profound for ADCs as for digital logic. The digital In some instances, the demodulated bits are passed on to receiver industry is always looking for wider bandwidth a forward error correction (FEC) stage for a reduction in and greater dynamic range. Successive approximation the number of bit errors received. One of the interesting ADCs were replaced by flash converters in the early aspects of FEC is that it can be integrated into the de- 1990s, and now are generally replaced with sigma-delta modulation process, such as in trellis-coded modulation; ADCs. Today's ADC can provide up to 105 Msps at or it can be closely linked to demodulation, as in soft 14-bit resolution. Special-purpose ADCs have been decoding for convolutional codes; or it can be an integral reported to provide sample rates over 5 giga samples per part of the next stage, medium access control (MAC) second (Gsps) at 8-bit resolution. processing. State-of-the-art research continues to push the bound- aries of analog-to-digital (A/D) performance with a wide Medium access control variety of clever techniques that shift the boundaries between DSP and ADC. MAC processing generally includes framing information, with its associated frame synchronization structures, MAC Modem addressing, error detection, link management structures, and payload encapsulat