 Some SETS devices host yet another PLL, referred to as the T4 PLL. The primary function of this PLL is to pass the input timing reference to a dedicated output timing port to be monitored externally or to facilitate the clock cleanup by external synchronization supply unit/building integrated timing supply (SSU/BITS) equipment (refer to the section "BITS and SSU", in "Chapter 6. Physical Frequency Synchronization", for more details on clock cleanup). This PLL usually locks to an external frequency source separate from the TO PLL and out- puts the T4 frequency on a single, specific port. This is sometimes also referred as the T4 path, as shown in Figure 12-1. Note that for the clock cleanup case, the T4 path enables the selected input frequency reference to pass to external SSU/BITS equipment. And the SSU/BITS equipment can then feed the cleaned-up clock back to the equipment via the same SSU/BITS port. The synchronous equipment can use this cleaned-up clock as input reference for the TO path, which is then used as input to the system frequency. Be careful not to generate a timing loop while using this mode. Input selector: Because the equipment can have multiple frequency sources (explained fur- ther in subsequent sections), the SETS device usually contains an input selector that selects one from the many possible frequency sources and switches that signal to the frequency re- covery PLL. The SETS device also provides the capability to monitor all the available refer- ence sources to assist the frequency selection process to select the best input frequency source. Clock multipliers and dividers: Clock multipliers and dividers are used to change a clock signal by a multiple of its frequency. With these multipliers and dividers, a SETS device can generate variations of the locked reference clock as outputs, which can be fed to different components of the equipment (requiring different frequencies to operate). For example, a 1 gigabit Ethernet interface requires 125 MHz and, at the same time, the 10-MHz front panel