te the values of various message fields that are carried to the PTP peer. Track the status of PTP peers to manage the communications with them. On a slave node, this would include the implementation of the correct best master clock algorithm (BMCA) and sim- ilar functions. A system designer could choose to design an implementation based on a separate dedicated pro- cessor for PTP functions. This would avoid problems occurring if the host processor is heavily loaded on a PTP master node-for example, it might become unable to communicate with all its slave nodes at the configured PTP message rate. On a slave node, CPU overload could cause non- deterministic response time, which becomes a problem when PTP packets are not received and pro- cessed in a timely manner. If this happens, the PLL will not be adjusted often enough, and that will decrease the accuracy of the recovered network clock. The second element required by a PTP-aware NE is the PTP packet processing engine. As the name suggests, the primary aim of this engine is to generate and receive PTP packets either at the configured or negotiated packet rates. The third key element of a PTP-aware NE is the PTP servo algorithm, commonly referred to simply as the servo. The goal of the servo algorithm is to synchronize the phase and frequency of the slave clock with that of the master clock. Thus, a high-quality servo is an essential component for high-accuracy synchronization. Recall from "Chapter 5. Clocks, Time Error, and Noise", that a PLL is an electronic device that generates an output clock signal that is synchronized to an input clock signal. For frequency syn- chronization, a PLL uses a phase comparator, which compares the phase of the input signal versus the phase of the output signal and generates a voltage-based phase difference. This voltage is fed to a voltage-controlled oscillator (VCO) to adjust the output signal. Using this process, the PLL im- plements a continuous loop of adjusting the output frequency based on the input signal. The servo perfor