 code, for example, invokes the policing function for a PDU, the ASI checks whether the PDU is compliant and returns an appropriate flag. The FPL program then determines what exactly must happen. For example, it can choose to just flag all noncompliant PDUs or it can discard them altogether, depend- ing on the application. Figure 7.6 shows the internal structure of the ASI chip. We have already discussed the role of most of its blocks. It is interesting, however, to note a couple of points. Two ALUs are available for pro- cessing FPP external function requests. One is for policing and the other is for maintaining state- related information and calculating statistics. Likewise, the two SSRAM interfaces, which were Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. AGERE PAYLOAD PLUSTM FAMILY OF NETWORK PROCESSORS Policing SSRAM Policing Compute Double Control Engine Logic SSRAM Interface State SSRAM Configuration SSRAM Interface PDU Data PDU Data To FPP Receive Transmit Interface Interface Interface POS-PHY POS-PHY PCI to Host Processor FIGURE 7.6 The internal block structure of the ASI chip. (Source: Agere) intended to handle memory access without contention, are used to simultaneously access two banks of SSRAM memory: one with policing information and one with state information. Transfer of management frames and statistics to a host CPU application is supported over the ASI's PCI bus. More specifically, through its direct memory access (DMA) master capabilities, the ASI wards this information to host memory. Likewise, if the host wants to generate specific PDUs, it will do SO and download them to the ASI over their PCI connection, and the ASI will then send them through its 8-bit POS-PL3 interface. In terms of management information, the ASI maintains a very large database where it stores the state-related information and statistics it gathers