ut this does not appear to be the case yet. If such effects do appear, they may manifest themselves as an increase in the cross-section for high-energy ions as devices become more sensitive to indirect strikes that do not hit the junction [118]. These results validate the continued use of standard low-energy heavy ion test facilities such as the BNL Tandem Van de Graaff and the Berkeley 88" Cyclotron for part testing Matra 65656 256Kb SRAM All SNs VDD = 4.5 V Brookhaven GANIL Effective LET (MeV-cm2/mg) Figure 3.16. High- VS. low-energy SEU cross-sections for 256Kb SRAMs manufactured in a 0.8-um radiation-tolerant technology [118]. II-27 Matra 65608E 1Mb SRAM VDD = 4.5 V Brookhaven GANIL Effective LET (MeV-cm2/mg) Figure 3.17. High- VS. low-energy SEU cross-sections for 1Mb SRAMs manufactured in a 0.5-um radiation-tolerant technology [118]. and qualification. This is important because the low-energy facilities are in general much better developed as user facilities, more accessible, and considerably cheaper to use. There are cases (e.g., grazing angle of incidence studies) where the use of high-energy ions is essential because of their increased range, and it is possible that in the future energy effects will become more significant. It is also possible that other device types or materials will prove to be more sensitive to energy effects than the Si CMOS SRAMs tested here. Based on the similarity in low-energy and high-energy ion track structures this seems unlikely, but cannot be positively ruled out. For the present, it appears that in most cases standard low-energy heavy-ion test methods are adequate to qualify similar technologies for current spacecraft use. Mitigation Techniques SEU mitigation techniques can be roughly classified into three distinct categories. System- level techniques deal with SEU at the system architecture level. Circuit-level techniques rely on changes in the circuit design to reduce SEU sensitivity. Technology- or device-level hardening requires fundamental changes to the underlying fab