croengine 3 FIGURE 5.9 Apportioning of a packet processing application running on the IXP1200 network processor over the 6 available microengines. (Source: Intel) Downloaded from Digital Engineering Library @ McGraw-Hil (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. INTEL IXA TM NETWORK PROCESSORS INTEL IXATM NETWORK PROCESSORS Ethernet data 14 bytes IP packet IP header IP data 20 bytes IP packet payload LLC/SNAP encapsulation 3 bytes 3bytes 2 bytes IP packet Padding Length CS-SDU Information field 0-47 bytes 1 byte 1 byte 2 bytes 4 bytes Payload 48 bytes Payload 48 bytes Payload 48 bytes ATM cell 4 bits 8 bits 16 bits 3 bits 1 bit 8 bits ATM Header 5 bytes long FIGURE 5.10 Apportioning a packet-processing application running on the IXP1200 network processor over the six available microengines. (Source: Intel) can be done are beyond the scope of this book. The corresponding code structure, interprocess sig- naling, data structures, initialization and startup, and SO on can be found in a detailed application note that Intel provides called "IXP1200 network processor ATM OC-3/Ethernet IP Router Example Design." It is available from Intel's web site at www.intel.com/design/network/ixa.htm Right before this chapter went to press, Intel announced a 1.4 GHz follow-on device to the 2800 -the IXP2850 network processor. This is a simplex 10 Gbps processor and is scheduled to be sam- pled by mid-2003. The interesting feature of this NPU is that it embeds encryption capabilities. More specifically, it contains two crypto engines as modules. Each crypto engine contains special hardware (some of them in multiple instances) for the implementation of the Advanced Encryption Standard (AES)/Rijndael, Triple DES, and SHA-1 cryptographic algorithms, which we discuss in length in Chapter 17. The 2850 is also capable of calculating TCP checksums. Interested readers can learn more details about this TCP termination-eng