 two independent write ports are used SO that two writes and two reads can always occur simultaneously. The rest of the sharing is done on a time-shar- ing basis by 16 over a packet cycle (which is 32 nanoseconds, with typical switch packets consisting of 64 bytes, although the PRS can be configured to handle up to 80-byte packets equally as well). 24. Rene J. Glaise, "PowerPRSTM: A Single-Stage, Reconfiguration-less, Packet Routing Terabit Class Switch Fabric with Distributed Scheduling," IBM Networking Technology Development, Microelectronics Division, 06610 La Gaude, France, 2002. This is also available online at www.ibm.com/chips/techlib/techlib.nsf/techdocs/AEE3588F9F253EE587256B680060F11B/$fil /PowerPRS_Tech_Overview.pdf. 25. Cyriel Minkenberg and Ton Engbersen (IBM Research, Zurich Research Laboratory), "A Combined Input and Output-Queued Packet-Switched System Based on PRIZMA Switch-on-a-Chip Technology," IEEE Communications Magazine (December 2000): 70-76. 26. Rene J. Glaise, "PowerPRSTM: A Single-Stage, Reconfiguration-less, Packet Routing Terabit Class Switch Fabric with Distributed Scheduling," IBM Networking Technology Development, Microelectronics Division, 06610 La Gaude, France, 2002. This is also available online at www.ibm.com/chips/techlib/techlib.nsf/techdocs/AEE3588F9F253EE587256B680060F11B/$file/ PowerPRS_Tech_Overview.pdf. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. Any use is subject to the Terms of Use as given at the website. SWITCH FABRICS SWITCH FABRICS 293 Unilink 0 to 15 Unilink 0 to 15 Output controller Input controller 16 x16 Output queue Input Switch scheduler controller Element D Unilink 16 to 31 Unilink 16 to 31 Output Ingress flow sequencer controller Egress flow Store addresses & data Shared memory 1024 10-Byte Rows Data output Retrieve addresses ports 0 to 15 Addresses & priority Output queues Output queue (one per port & per priority) Access manager addresses Ad