am is mapped sequentially (first-in-first-mapped) directly to the physical channel(s). The The UTRA Physical Layer Design mapping of BCH and FACH/PCH is equally straightforward, where the data stream after coding and interleaving is mapped sequentially to the primary and secondary CCPCH, respectively. Also for the RACH, the coded and interleaved bits are sequen- tially mapped to the physical channel, in this case the message part of the PRACH. Table 4.30 Mapping Transport Channels to Physical Channels Transport channels Physical channels Dedicated Channel (DCH) Dedicated Physical Data Channel (DPDCH) Dedicated Physical Control Channel (DPCCH) Random Access Channel (RACH) Physical Random Access Channel (PRACH) Common Packet Channel (CPCH) Physical Common Packet Channel (PCPCH) Common Pilot Channel (CPICH) Broadcast Channel (BCH) Primary Common Control Physical Channel (P-CCPCH) Forward Access Channel (FACH) Secondary Common Control Paging Channel (PCH) Physical Channel (S-CCPCH) Synchronization Channel (SCH) Downlink Shared Channel Physical Downlink Shared (DSCH) Channel (PDSCH) Acquisition Indicator Channel (AICH) Access Preamble Acquisition Indicator Channel (AP-AICH) Paging Indicator Channel (PICH) CPCH Status Indicator Chan- nel (CSICH) Collision-Detection/Channel- Assignment Indicator Channel (CD/CA-ICH) 4.3.11 Timing Relationship Between Physical Channels The P-CCPCH, which carries a cell's SFN, serves as timing reference for all the physi- cal channels, directly for downlink and indirectly for uplink. Figure 4.30 describes the frame timing of the downlink physical channels, for the AICH it includes the access slot timing. Uplink physical channels get their transmission timing from the received timing of the downlink physical channels. In general the following applies from [1]: SCH (primary and secondary), CPICH (primary and secondary), P-CCPCH, and PDSCH have identical frame timings. The S-CCPCH timing may vary for different S-CCPCHs, but the offset from the P- CCPCH frame timing is a multiple of 256 chips,