Due to the growing gap between CPU operating frequencies and DRAM access times , none of the techniques that enhance instruction-level parallelism ( ILP ) within one program could overcome the long stalls ( delays ) that occurred when data had to be fetched from main memory . Computer architects have become stymied by the growing mismatch in CPU operating frequencies and DRAM access times . None of the techniques that exploited instruction-level parallelism within one program could make up for the long stalls that occurred when data had to be fetched from main memory .